1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS
,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result
;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant
;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax
= FALSE
;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set
*legacy_cpu
= NULL
;
158 static const arm_feature_set
*legacy_fpu
= NULL
;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
162 static arm_feature_set
*mcpu_ext_opt
= NULL
;
163 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set
*march_cpu_opt
= NULL
;
167 static arm_feature_set
*march_ext_opt
= NULL
;
168 static const arm_feature_set
*march_fpu_opt
= NULL
;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set
*mfpu_opt
= NULL
;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
176 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
179 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
180 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
182 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
184 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
187 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
190 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
191 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
192 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
193 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
194 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
195 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
196 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
197 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
198 static const arm_feature_set arm_ext_v4t_5
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
200 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
201 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
202 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
203 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
204 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
205 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
206 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
207 /* Only for compatability of hint instructions. */
208 static const arm_feature_set arm_ext_v6k_v6t2
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
210 static const arm_feature_set arm_ext_v6_notm
=
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
212 static const arm_feature_set arm_ext_v6_dsp
=
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
214 static const arm_feature_set arm_ext_barrier
=
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
216 static const arm_feature_set arm_ext_msr
=
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
218 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
219 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
220 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
221 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
223 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
225 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
226 static const arm_feature_set arm_ext_m
=
227 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
228 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
229 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
230 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
231 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
232 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
233 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
234 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
235 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
236 static const arm_feature_set arm_ext_v8m_main
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
238 static const arm_feature_set arm_ext_v8_1m_main
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
240 /* Instructions in ARMv8-M only found in M profile architectures. */
241 static const arm_feature_set arm_ext_v8m_m_only
=
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
243 static const arm_feature_set arm_ext_v6t2_v8m
=
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
245 /* Instructions shared between ARMv8-A and ARMv8-M. */
246 static const arm_feature_set arm_ext_atomics
=
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
249 /* DSP instructions Tag_DSP_extension refers to. */
250 static const arm_feature_set arm_ext_dsp
=
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
253 static const arm_feature_set arm_ext_ras
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
255 /* FP16 instructions. */
256 static const arm_feature_set arm_ext_fp16
=
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
258 static const arm_feature_set arm_ext_fp16_fml
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
260 static const arm_feature_set arm_ext_v8_2
=
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
262 static const arm_feature_set arm_ext_v8_3
=
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
264 static const arm_feature_set arm_ext_sb
=
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
266 static const arm_feature_set arm_ext_predres
=
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
269 static const arm_feature_set arm_arch_any
= ARM_ANY
;
271 static const arm_feature_set fpu_any
= FPU_ANY
;
273 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
274 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
275 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
277 static const arm_feature_set arm_cext_iwmmxt2
=
278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
279 static const arm_feature_set arm_cext_iwmmxt
=
280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
281 static const arm_feature_set arm_cext_xscale
=
282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
283 static const arm_feature_set arm_cext_maverick
=
284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
285 static const arm_feature_set fpu_fpa_ext_v1
=
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
287 static const arm_feature_set fpu_fpa_ext_v2
=
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
289 static const arm_feature_set fpu_vfp_ext_v1xd
=
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
291 static const arm_feature_set fpu_vfp_ext_v1
=
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
293 static const arm_feature_set fpu_vfp_ext_v2
=
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
295 static const arm_feature_set fpu_vfp_ext_v3xd
=
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
297 static const arm_feature_set fpu_vfp_ext_v3
=
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
299 static const arm_feature_set fpu_vfp_ext_d32
=
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
301 static const arm_feature_set fpu_neon_ext_v1
=
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
303 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
305 static const arm_feature_set mve_ext
=
306 ARM_FEATURE_COPROC (FPU_MVE
);
307 static const arm_feature_set mve_fp_ext
=
308 ARM_FEATURE_COPROC (FPU_MVE_FP
);
310 static const arm_feature_set fpu_vfp_fp16
=
311 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
312 static const arm_feature_set fpu_neon_ext_fma
=
313 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
315 static const arm_feature_set fpu_vfp_ext_fma
=
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
317 static const arm_feature_set fpu_vfp_ext_armv8
=
318 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
319 static const arm_feature_set fpu_vfp_ext_armv8xd
=
320 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
321 static const arm_feature_set fpu_neon_ext_armv8
=
322 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
323 static const arm_feature_set fpu_crypto_ext_armv8
=
324 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
325 static const arm_feature_set crc_ext_armv8
=
326 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
327 static const arm_feature_set fpu_neon_ext_v8_1
=
328 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
329 static const arm_feature_set fpu_neon_ext_dotprod
=
330 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
332 static int mfloat_abi_opt
= -1;
333 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
335 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
336 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
338 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
339 /* Feature bits selected by the last -mcpu/-march or by the combination of the
340 last .cpu/.arch directive .arch_extension directives since that
342 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
343 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
344 static arm_feature_set selected_fpu
= FPU_NONE
;
345 /* Feature bits selected by the last .object_arch directive. */
346 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
347 /* Must be long enough to hold any of the names in arm_cpus. */
348 static char selected_cpu_name
[20];
350 extern FLONUM_TYPE generic_floating_point_number
;
352 /* Return if no cpu was selected on command-line. */
354 no_cpu_selected (void)
356 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
361 static int meabi_flags
= EABI_DEFAULT
;
363 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
366 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
371 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
376 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
377 symbolS
* GOT_symbol
;
380 /* 0: assemble for ARM,
381 1: assemble for Thumb,
382 2: assemble for Thumb even though target CPU does not support thumb
384 static int thumb_mode
= 0;
385 /* A value distinct from the possible values for thumb_mode that we
386 can use to record whether thumb_mode has been copied into the
387 tc_frag_data field of a frag. */
388 #define MODE_RECORDED (1 << 4)
390 /* Specifies the intrinsic IT insn behavior mode. */
391 enum implicit_it_mode
393 IMPLICIT_IT_MODE_NEVER
= 0x00,
394 IMPLICIT_IT_MODE_ARM
= 0x01,
395 IMPLICIT_IT_MODE_THUMB
= 0x02,
396 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
398 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
400 /* If unified_syntax is true, we are processing the new unified
401 ARM/Thumb syntax. Important differences from the old ARM mode:
403 - Immediate operands do not require a # prefix.
404 - Conditional affixes always appear at the end of the
405 instruction. (For backward compatibility, those instructions
406 that formerly had them in the middle, continue to accept them
408 - The IT instruction may appear, and if it does is validated
409 against subsequent conditional affixes. It does not generate
412 Important differences from the old Thumb mode:
414 - Immediate operands do not require a # prefix.
415 - Most of the V6T2 instructions are only available in unified mode.
416 - The .N and .W suffixes are recognized and honored (it is an error
417 if they cannot be honored).
418 - All instructions set the flags if and only if they have an 's' affix.
419 - Conditional affixes may be used. They are validated against
420 preceding IT instructions. Unlike ARM mode, you cannot use a
421 conditional affix except in the scope of an IT instruction. */
423 static bfd_boolean unified_syntax
= FALSE
;
425 /* An immediate operand can start with #, and ld*, st*, pld operands
426 can contain [ and ]. We need to tell APP not to elide whitespace
427 before a [, which can appear as the first operand for pld.
428 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
429 const char arm_symbol_chars
[] = "#[]{}";
444 enum neon_el_type type
;
448 #define NEON_MAX_TYPE_ELS 4
452 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
456 enum pred_instruction_type
462 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
463 if inside, should be the last one. */
464 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
465 i.e. BKPT and NOP. */
466 IT_INSN
, /* The IT insn has been parsed. */
467 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
468 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
469 a predication code. */
470 MVE_UNPREDICABLE_INSN
/* MVE instruction that is non-predicable. */
473 /* The maximum number of operands we need. */
474 #define ARM_IT_MAX_OPERANDS 6
475 #define ARM_IT_MAX_RELOCS 3
480 unsigned long instruction
;
484 /* "uncond_value" is set to the value in place of the conditional field in
485 unconditional versions of the instruction, or -1 if nothing is
488 struct neon_type vectype
;
489 /* This does not indicate an actual NEON instruction, only that
490 the mnemonic accepts neon-style type suffixes. */
492 /* Set to the opcode if the instruction needs relaxation.
493 Zero if the instruction is not relaxed. */
497 bfd_reloc_code_real_type type
;
500 } relocs
[ARM_IT_MAX_RELOCS
];
502 enum pred_instruction_type pred_insn_type
;
508 struct neon_type_el vectype
;
509 unsigned present
: 1; /* Operand present. */
510 unsigned isreg
: 1; /* Operand was a register. */
511 unsigned immisreg
: 2; /* .imm field is a second register.
512 0: imm, 1: gpr, 2: MVE Q-register. */
513 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
517 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
518 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
519 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
520 instructions. This allows us to disambiguate ARM <-> vector insns. */
521 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
522 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
523 unsigned isquad
: 1; /* Operand is SIMD quad register. */
524 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
525 unsigned iszr
: 1; /* Operand is ZR register. */
526 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
527 unsigned writeback
: 1; /* Operand has trailing ! */
528 unsigned preind
: 1; /* Preindexed address. */
529 unsigned postind
: 1; /* Postindexed address. */
530 unsigned negative
: 1; /* Index register was negated. */
531 unsigned shifted
: 1; /* Shift applied to operation. */
532 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
533 } operands
[ARM_IT_MAX_OPERANDS
];
536 static struct arm_it inst
;
538 #define NUM_FLOAT_VALS 8
540 const char * fp_const
[] =
542 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
545 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
555 #define CP_T_X 0x00008000
556 #define CP_T_Y 0x00400000
558 #define CONDS_BIT 0x00100000
559 #define LOAD_BIT 0x00100000
561 #define DOUBLE_LOAD_FLAG 0x00000001
565 const char * template_name
;
569 #define COND_ALWAYS 0xE
573 const char * template_name
;
577 struct asm_barrier_opt
579 const char * template_name
;
581 const arm_feature_set arch
;
584 /* The bit that distinguishes CPSR and SPSR. */
585 #define SPSR_BIT (1 << 22)
587 /* The individual PSR flag bits. */
588 #define PSR_c (1 << 16)
589 #define PSR_x (1 << 17)
590 #define PSR_s (1 << 18)
591 #define PSR_f (1 << 19)
596 bfd_reloc_code_real_type reloc
;
601 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
602 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
607 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
610 /* Bits for DEFINED field in neon_typed_alias. */
611 #define NTA_HASTYPE 1
612 #define NTA_HASINDEX 2
614 struct neon_typed_alias
616 unsigned char defined
;
618 struct neon_type_el eltype
;
621 /* ARM register categories. This includes coprocessor numbers and various
622 architecture extensions' registers. Each entry should have an error message
623 in reg_expected_msgs below. */
653 /* Structure for a hash table entry for a register.
654 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
655 information which states whether a vector type or index is specified (for a
656 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
662 unsigned char builtin
;
663 struct neon_typed_alias
* neon
;
666 /* Diagnostics used when we don't get a register of the expected type. */
667 const char * const reg_expected_msgs
[] =
669 [REG_TYPE_RN
] = N_("ARM register expected"),
670 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
671 [REG_TYPE_CN
] = N_("co-processor register expected"),
672 [REG_TYPE_FN
] = N_("FPA register expected"),
673 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
674 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
675 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
676 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
677 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
678 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
679 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
681 [REG_TYPE_VFC
] = N_("VFP system register expected"),
682 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
683 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
684 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
685 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
686 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
687 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
688 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
689 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
690 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
691 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
692 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
693 [REG_TYPE_RNB
] = N_("")
696 /* Some well known registers that we refer to directly elsewhere. */
702 /* ARM instructions take 4bytes in the object file, Thumb instructions
708 /* Basic string to match. */
709 const char * template_name
;
711 /* Parameters to instruction. */
712 unsigned int operands
[8];
714 /* Conditional tag - see opcode_lookup. */
715 unsigned int tag
: 4;
717 /* Basic instruction code. */
720 /* Thumb-format instruction code. */
723 /* Which architecture variant provides this instruction. */
724 const arm_feature_set
* avariant
;
725 const arm_feature_set
* tvariant
;
727 /* Function to call to encode instruction in ARM format. */
728 void (* aencode
) (void);
730 /* Function to call to encode instruction in Thumb format. */
731 void (* tencode
) (void);
733 /* Indicates whether this instruction may be vector predicated. */
734 unsigned int mayBeVecPred
: 1;
737 /* Defines for various bits that we will want to toggle. */
738 #define INST_IMMEDIATE 0x02000000
739 #define OFFSET_REG 0x02000000
740 #define HWOFFSET_IMM 0x00400000
741 #define SHIFT_BY_REG 0x00000010
742 #define PRE_INDEX 0x01000000
743 #define INDEX_UP 0x00800000
744 #define WRITE_BACK 0x00200000
745 #define LDM_TYPE_2_OR_3 0x00400000
746 #define CPSI_MMOD 0x00020000
748 #define LITERAL_MASK 0xf000f000
749 #define OPCODE_MASK 0xfe1fffff
750 #define V4_STR_BIT 0x00000020
751 #define VLDR_VMOV_SAME 0x0040f000
753 #define T2_SUBS_PC_LR 0xf3de8f00
755 #define DATA_OP_SHIFT 21
756 #define SBIT_SHIFT 20
758 #define T2_OPCODE_MASK 0xfe1fffff
759 #define T2_DATA_OP_SHIFT 21
760 #define T2_SBIT_SHIFT 20
762 #define A_COND_MASK 0xf0000000
763 #define A_PUSH_POP_OP_MASK 0x0fff0000
765 /* Opcodes for pushing/poping registers to/from the stack. */
766 #define A1_OPCODE_PUSH 0x092d0000
767 #define A2_OPCODE_PUSH 0x052d0004
768 #define A2_OPCODE_POP 0x049d0004
770 /* Codes to distinguish the arithmetic instructions. */
781 #define OPCODE_CMP 10
782 #define OPCODE_CMN 11
783 #define OPCODE_ORR 12
784 #define OPCODE_MOV 13
785 #define OPCODE_BIC 14
786 #define OPCODE_MVN 15
788 #define T2_OPCODE_AND 0
789 #define T2_OPCODE_BIC 1
790 #define T2_OPCODE_ORR 2
791 #define T2_OPCODE_ORN 3
792 #define T2_OPCODE_EOR 4
793 #define T2_OPCODE_ADD 8
794 #define T2_OPCODE_ADC 10
795 #define T2_OPCODE_SBC 11
796 #define T2_OPCODE_SUB 13
797 #define T2_OPCODE_RSB 14
799 #define T_OPCODE_MUL 0x4340
800 #define T_OPCODE_TST 0x4200
801 #define T_OPCODE_CMN 0x42c0
802 #define T_OPCODE_NEG 0x4240
803 #define T_OPCODE_MVN 0x43c0
805 #define T_OPCODE_ADD_R3 0x1800
806 #define T_OPCODE_SUB_R3 0x1a00
807 #define T_OPCODE_ADD_HI 0x4400
808 #define T_OPCODE_ADD_ST 0xb000
809 #define T_OPCODE_SUB_ST 0xb080
810 #define T_OPCODE_ADD_SP 0xa800
811 #define T_OPCODE_ADD_PC 0xa000
812 #define T_OPCODE_ADD_I8 0x3000
813 #define T_OPCODE_SUB_I8 0x3800
814 #define T_OPCODE_ADD_I3 0x1c00
815 #define T_OPCODE_SUB_I3 0x1e00
817 #define T_OPCODE_ASR_R 0x4100
818 #define T_OPCODE_LSL_R 0x4080
819 #define T_OPCODE_LSR_R 0x40c0
820 #define T_OPCODE_ROR_R 0x41c0
821 #define T_OPCODE_ASR_I 0x1000
822 #define T_OPCODE_LSL_I 0x0000
823 #define T_OPCODE_LSR_I 0x0800
825 #define T_OPCODE_MOV_I8 0x2000
826 #define T_OPCODE_CMP_I8 0x2800
827 #define T_OPCODE_CMP_LR 0x4280
828 #define T_OPCODE_MOV_HR 0x4600
829 #define T_OPCODE_CMP_HR 0x4500
831 #define T_OPCODE_LDR_PC 0x4800
832 #define T_OPCODE_LDR_SP 0x9800
833 #define T_OPCODE_STR_SP 0x9000
834 #define T_OPCODE_LDR_IW 0x6800
835 #define T_OPCODE_STR_IW 0x6000
836 #define T_OPCODE_LDR_IH 0x8800
837 #define T_OPCODE_STR_IH 0x8000
838 #define T_OPCODE_LDR_IB 0x7800
839 #define T_OPCODE_STR_IB 0x7000
840 #define T_OPCODE_LDR_RW 0x5800
841 #define T_OPCODE_STR_RW 0x5000
842 #define T_OPCODE_LDR_RH 0x5a00
843 #define T_OPCODE_STR_RH 0x5200
844 #define T_OPCODE_LDR_RB 0x5c00
845 #define T_OPCODE_STR_RB 0x5400
847 #define T_OPCODE_PUSH 0xb400
848 #define T_OPCODE_POP 0xbc00
850 #define T_OPCODE_BRANCH 0xe000
852 #define THUMB_SIZE 2 /* Size of thumb instruction. */
853 #define THUMB_PP_PC_LR 0x0100
854 #define THUMB_LOAD_BIT 0x0800
855 #define THUMB2_LOAD_BIT 0x00100000
857 #define BAD_SYNTAX _("syntax error")
858 #define BAD_ARGS _("bad arguments to instruction")
859 #define BAD_SP _("r13 not allowed here")
860 #define BAD_PC _("r15 not allowed here")
861 #define BAD_ODD _("Odd register not allowed here")
862 #define BAD_EVEN _("Even register not allowed here")
863 #define BAD_COND _("instruction cannot be conditional")
864 #define BAD_OVERLAP _("registers may not be the same")
865 #define BAD_HIREG _("lo register required")
866 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
867 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
868 #define BAD_BRANCH _("branch must be last instruction in IT block")
869 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
870 #define BAD_NOT_IT _("instruction not allowed in IT block")
871 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
872 #define BAD_FPU _("selected FPU does not support instruction")
873 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
874 #define BAD_OUT_VPT \
875 _("vector predicated instruction should be in VPT/VPST block")
876 #define BAD_IT_COND _("incorrect condition in IT block")
877 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
878 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
879 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
880 #define BAD_PC_ADDRESSING \
881 _("cannot use register index with PC-relative addressing")
882 #define BAD_PC_WRITEBACK \
883 _("cannot use writeback with PC-relative addressing")
884 #define BAD_RANGE _("branch out of range")
885 #define BAD_FP16 _("selected processor does not support fp16 instruction")
886 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
887 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
888 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
890 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
892 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
894 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
896 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
897 #define BAD_MVE_AUTO \
898 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
899 " use a valid -march or -mcpu option.")
900 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
901 "and source operands makes instruction UNPREDICTABLE")
902 #define BAD_EL_TYPE _("bad element type for instruction")
903 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
905 static struct hash_control
* arm_ops_hsh
;
906 static struct hash_control
* arm_cond_hsh
;
907 static struct hash_control
* arm_vcond_hsh
;
908 static struct hash_control
* arm_shift_hsh
;
909 static struct hash_control
* arm_psr_hsh
;
910 static struct hash_control
* arm_v7m_psr_hsh
;
911 static struct hash_control
* arm_reg_hsh
;
912 static struct hash_control
* arm_reloc_hsh
;
913 static struct hash_control
* arm_barrier_opt_hsh
;
915 /* Stuff needed to resolve the label ambiguity
924 symbolS
* last_label_seen
;
925 static int label_is_thumb_function_name
= FALSE
;
927 /* Literal pool structure. Held on a per-section
928 and per-sub-section basis. */
930 #define MAX_LITERAL_POOL_SIZE 1024
931 typedef struct literal_pool
933 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
934 unsigned int next_free_entry
;
940 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
942 struct literal_pool
* next
;
943 unsigned int alignment
;
946 /* Pointer to a linked list of literal pools. */
947 literal_pool
* list_of_pools
= NULL
;
949 typedef enum asmfunc_states
952 WAITING_ASMFUNC_NAME
,
956 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
959 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
961 static struct current_pred now_pred
;
965 now_pred_compatible (int cond
)
967 return (cond
& ~1) == (now_pred
.cc
& ~1);
971 conditional_insn (void)
973 return inst
.cond
!= COND_ALWAYS
;
976 static int in_pred_block (void);
978 static int handle_pred_state (void);
980 static void force_automatic_it_block_close (void);
982 static void it_fsm_post_encode (void);
984 #define set_pred_insn_type(type) \
987 inst.pred_insn_type = type; \
988 if (handle_pred_state () == FAIL) \
993 #define set_pred_insn_type_nonvoid(type, failret) \
996 inst.pred_insn_type = type; \
997 if (handle_pred_state () == FAIL) \
1002 #define set_pred_insn_type_last() \
1005 if (inst.cond == COND_ALWAYS) \
1006 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1008 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1014 /* This array holds the chars that always start a comment. If the
1015 pre-processor is disabled, these aren't very useful. */
1016 char arm_comment_chars
[] = "@";
1018 /* This array holds the chars that only start a comment at the beginning of
1019 a line. If the line seems to have the form '# 123 filename'
1020 .line and .file directives will appear in the pre-processed output. */
1021 /* Note that input_file.c hand checks for '#' at the beginning of the
1022 first line of the input file. This is because the compiler outputs
1023 #NO_APP at the beginning of its output. */
1024 /* Also note that comments like this one will always work. */
1025 const char line_comment_chars
[] = "#";
1027 char arm_line_separator_chars
[] = ";";
1029 /* Chars that can be used to separate mant
1030 from exp in floating point numbers. */
1031 const char EXP_CHARS
[] = "eE";
1033 /* Chars that mean this number is a floating point constant. */
1034 /* As in 0f12.456 */
1035 /* or 0d1.2345e12 */
1037 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
1039 /* Prefix characters that indicate the start of an immediate
1041 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1043 /* Separator character handling. */
1045 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1048 skip_past_char (char ** str
, char c
)
1050 /* PR gas/14987: Allow for whitespace before the expected character. */
1051 skip_whitespace (*str
);
1062 #define skip_past_comma(str) skip_past_char (str, ',')
1064 /* Arithmetic expressions (possibly involving symbols). */
1066 /* Return TRUE if anything in the expression is a bignum. */
1069 walk_no_bignums (symbolS
* sp
)
1071 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1074 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1076 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1077 || (symbol_get_value_expression (sp
)->X_op_symbol
1078 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1084 static bfd_boolean in_my_get_expression
= FALSE
;
1086 /* Third argument to my_get_expression. */
1087 #define GE_NO_PREFIX 0
1088 #define GE_IMM_PREFIX 1
1089 #define GE_OPT_PREFIX 2
1090 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1091 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1092 #define GE_OPT_PREFIX_BIG 3
1095 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1099 /* In unified syntax, all prefixes are optional. */
1101 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1104 switch (prefix_mode
)
1106 case GE_NO_PREFIX
: break;
1108 if (!is_immediate_prefix (**str
))
1110 inst
.error
= _("immediate expression requires a # prefix");
1116 case GE_OPT_PREFIX_BIG
:
1117 if (is_immediate_prefix (**str
))
1124 memset (ep
, 0, sizeof (expressionS
));
1126 save_in
= input_line_pointer
;
1127 input_line_pointer
= *str
;
1128 in_my_get_expression
= TRUE
;
1130 in_my_get_expression
= FALSE
;
1132 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1134 /* We found a bad or missing expression in md_operand(). */
1135 *str
= input_line_pointer
;
1136 input_line_pointer
= save_in
;
1137 if (inst
.error
== NULL
)
1138 inst
.error
= (ep
->X_op
== O_absent
1139 ? _("missing expression") :_("bad expression"));
1143 /* Get rid of any bignums now, so that we don't generate an error for which
1144 we can't establish a line number later on. Big numbers are never valid
1145 in instructions, which is where this routine is always called. */
1146 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1147 && (ep
->X_op
== O_big
1148 || (ep
->X_add_symbol
1149 && (walk_no_bignums (ep
->X_add_symbol
)
1151 && walk_no_bignums (ep
->X_op_symbol
))))))
1153 inst
.error
= _("invalid constant");
1154 *str
= input_line_pointer
;
1155 input_line_pointer
= save_in
;
1159 *str
= input_line_pointer
;
1160 input_line_pointer
= save_in
;
1164 /* Turn a string in input_line_pointer into a floating point constant
1165 of type TYPE, and store the appropriate bytes in *LITP. The number
1166 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1167 returned, or NULL on OK.
1169 Note that fp constants aren't represent in the normal way on the ARM.
1170 In big endian mode, things are as expected. However, in little endian
1171 mode fp constants are big-endian word-wise, and little-endian byte-wise
1172 within the words. For example, (double) 1.1 in big endian mode is
1173 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1174 the byte sequence 99 99 f1 3f 9a 99 99 99.
1176 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1179 md_atof (int type
, char * litP
, int * sizeP
)
1182 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1214 return _("Unrecognized or unsupported floating point constant");
1217 t
= atof_ieee (input_line_pointer
, type
, words
);
1219 input_line_pointer
= t
;
1220 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1222 if (target_big_endian
)
1224 for (i
= 0; i
< prec
; i
++)
1226 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1227 litP
+= sizeof (LITTLENUM_TYPE
);
1232 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1233 for (i
= prec
- 1; i
>= 0; i
--)
1235 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1236 litP
+= sizeof (LITTLENUM_TYPE
);
1239 /* For a 4 byte float the order of elements in `words' is 1 0.
1240 For an 8 byte float the order is 1 0 3 2. */
1241 for (i
= 0; i
< prec
; i
+= 2)
1243 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1244 sizeof (LITTLENUM_TYPE
));
1245 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1246 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1247 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1254 /* We handle all bad expressions here, so that we can report the faulty
1255 instruction in the error message. */
1258 md_operand (expressionS
* exp
)
1260 if (in_my_get_expression
)
1261 exp
->X_op
= O_illegal
;
1264 /* Immediate values. */
1267 /* Generic immediate-value read function for use in directives.
1268 Accepts anything that 'expression' can fold to a constant.
1269 *val receives the number. */
1272 immediate_for_directive (int *val
)
1275 exp
.X_op
= O_illegal
;
1277 if (is_immediate_prefix (*input_line_pointer
))
1279 input_line_pointer
++;
1283 if (exp
.X_op
!= O_constant
)
1285 as_bad (_("expected #constant"));
1286 ignore_rest_of_line ();
1289 *val
= exp
.X_add_number
;
1294 /* Register parsing. */
1296 /* Generic register parser. CCP points to what should be the
1297 beginning of a register name. If it is indeed a valid register
1298 name, advance CCP over it and return the reg_entry structure;
1299 otherwise return NULL. Does not issue diagnostics. */
1301 static struct reg_entry
*
1302 arm_reg_parse_multi (char **ccp
)
1306 struct reg_entry
*reg
;
1308 skip_whitespace (start
);
1310 #ifdef REGISTER_PREFIX
1311 if (*start
!= REGISTER_PREFIX
)
1315 #ifdef OPTIONAL_REGISTER_PREFIX
1316 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1321 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1326 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1328 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1338 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1339 enum arm_reg_type type
)
1341 /* Alternative syntaxes are accepted for a few register classes. */
1348 /* Generic coprocessor register names are allowed for these. */
1349 if (reg
&& reg
->type
== REG_TYPE_CN
)
1354 /* For backward compatibility, a bare number is valid here. */
1356 unsigned long processor
= strtoul (start
, ccp
, 10);
1357 if (*ccp
!= start
&& processor
<= 15)
1362 case REG_TYPE_MMXWC
:
1363 /* WC includes WCG. ??? I'm not sure this is true for all
1364 instructions that take WC registers. */
1365 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1376 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1377 return value is the register number or FAIL. */
1380 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1383 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1386 /* Do not allow a scalar (reg+index) to parse as a register. */
1387 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1390 if (reg
&& reg
->type
== type
)
1393 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1400 /* Parse a Neon type specifier. *STR should point at the leading '.'
1401 character. Does no verification at this stage that the type fits the opcode
1408 Can all be legally parsed by this function.
1410 Fills in neon_type struct pointer with parsed information, and updates STR
1411 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1412 type, FAIL if not. */
1415 parse_neon_type (struct neon_type
*type
, char **str
)
1422 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1424 enum neon_el_type thistype
= NT_untyped
;
1425 unsigned thissize
= -1u;
1432 /* Just a size without an explicit type. */
1436 switch (TOLOWER (*ptr
))
1438 case 'i': thistype
= NT_integer
; break;
1439 case 'f': thistype
= NT_float
; break;
1440 case 'p': thistype
= NT_poly
; break;
1441 case 's': thistype
= NT_signed
; break;
1442 case 'u': thistype
= NT_unsigned
; break;
1444 thistype
= NT_float
;
1449 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1455 /* .f is an abbreviation for .f32. */
1456 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1461 thissize
= strtoul (ptr
, &ptr
, 10);
1463 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1466 as_bad (_("bad size %d in type specifier"), thissize
);
1474 type
->el
[type
->elems
].type
= thistype
;
1475 type
->el
[type
->elems
].size
= thissize
;
1480 /* Empty/missing type is not a successful parse. */
1481 if (type
->elems
== 0)
1489 /* Errors may be set multiple times during parsing or bit encoding
1490 (particularly in the Neon bits), but usually the earliest error which is set
1491 will be the most meaningful. Avoid overwriting it with later (cascading)
1492 errors by calling this function. */
1495 first_error (const char *err
)
1501 /* Parse a single type, e.g. ".s32", leading period included. */
1503 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1506 struct neon_type optype
;
1510 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1512 if (optype
.elems
== 1)
1513 *vectype
= optype
.el
[0];
1516 first_error (_("only one type should be specified for operand"));
1522 first_error (_("vector type expected"));
1534 /* Special meanings for indices (which have a range of 0-7), which will fit into
1537 #define NEON_ALL_LANES 15
1538 #define NEON_INTERLEAVE_LANES 14
1540 /* Record a use of the given feature. */
1542 record_feature_use (const arm_feature_set
*feature
)
1545 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1547 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1550 /* If the given feature available in the selected CPU, mark it as used.
1551 Returns TRUE iff feature is available. */
1553 mark_feature_used (const arm_feature_set
*feature
)
1556 /* Do not support the use of MVE only instructions when in auto-detection or
1558 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1559 && ARM_CPU_IS_ANY (cpu_variant
))
1561 first_error (BAD_MVE_AUTO
);
1564 /* Ensure the option is valid on the current architecture. */
1565 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1568 /* Add the appropriate architecture feature for the barrier option used.
1570 record_feature_use (feature
);
1575 /* Parse either a register or a scalar, with an optional type. Return the
1576 register number, and optionally fill in the actual type of the register
1577 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1578 type/index information in *TYPEINFO. */
1581 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1582 enum arm_reg_type
*rtype
,
1583 struct neon_typed_alias
*typeinfo
)
1586 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1587 struct neon_typed_alias atype
;
1588 struct neon_type_el parsetype
;
1592 atype
.eltype
.type
= NT_invtype
;
1593 atype
.eltype
.size
= -1;
1595 /* Try alternate syntax for some types of register. Note these are mutually
1596 exclusive with the Neon syntax extensions. */
1599 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1607 /* Undo polymorphism when a set of register types may be accepted. */
1608 if ((type
== REG_TYPE_NDQ
1609 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1610 || (type
== REG_TYPE_VFSD
1611 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1612 || (type
== REG_TYPE_NSDQ
1613 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1614 || reg
->type
== REG_TYPE_NQ
))
1615 || (type
== REG_TYPE_NSD
1616 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1617 || (type
== REG_TYPE_MMXWC
1618 && (reg
->type
== REG_TYPE_MMXWCG
)))
1619 type
= (enum arm_reg_type
) reg
->type
;
1621 if (type
== REG_TYPE_MQ
)
1623 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1626 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1629 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1631 first_error (_("expected MVE register [q0..q7]"));
1636 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1637 && (type
== REG_TYPE_NQ
))
1641 if (type
!= reg
->type
)
1647 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1649 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1651 first_error (_("can't redefine type for operand"));
1654 atype
.defined
|= NTA_HASTYPE
;
1655 atype
.eltype
= parsetype
;
1658 if (skip_past_char (&str
, '[') == SUCCESS
)
1660 if (type
!= REG_TYPE_VFD
1661 && !(type
== REG_TYPE_VFS
1662 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1663 && !(type
== REG_TYPE_NQ
1664 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1666 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1667 first_error (_("only D and Q registers may be indexed"));
1669 first_error (_("only D registers may be indexed"));
1673 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1675 first_error (_("can't change index for operand"));
1679 atype
.defined
|= NTA_HASINDEX
;
1681 if (skip_past_char (&str
, ']') == SUCCESS
)
1682 atype
.index
= NEON_ALL_LANES
;
1687 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1689 if (exp
.X_op
!= O_constant
)
1691 first_error (_("constant expression required"));
1695 if (skip_past_char (&str
, ']') == FAIL
)
1698 atype
.index
= exp
.X_add_number
;
1713 /* Like arm_reg_parse, but also allow the following extra features:
1714 - If RTYPE is non-zero, return the (possibly restricted) type of the
1715 register (e.g. Neon double or quad reg when either has been requested).
1716 - If this is a Neon vector type with additional type information, fill
1717 in the struct pointed to by VECTYPE (if non-NULL).
1718 This function will fault on encountering a scalar. */
1721 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1722 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1724 struct neon_typed_alias atype
;
1726 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1731 /* Do not allow regname(... to parse as a register. */
1735 /* Do not allow a scalar (reg+index) to parse as a register. */
1736 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1738 first_error (_("register operand expected, but got scalar"));
1743 *vectype
= atype
.eltype
;
1750 #define NEON_SCALAR_REG(X) ((X) >> 4)
1751 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1753 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1754 have enough information to be able to do a good job bounds-checking. So, we
1755 just do easy checks here, and do further checks later. */
1758 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1759 arm_reg_type reg_type
)
1763 struct neon_typed_alias atype
;
1766 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1784 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1787 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1789 first_error (_("scalar must have an index"));
1792 else if (atype
.index
>= reg_size
/ elsize
)
1794 first_error (_("scalar index out of range"));
1799 *type
= atype
.eltype
;
1803 return reg
* 16 + atype
.index
;
1806 /* Types of registers in a list. */
1819 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1822 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1828 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1830 /* We come back here if we get ranges concatenated by '+' or '|'. */
1833 skip_whitespace (str
);
1846 const char apsr_str
[] = "apsr";
1847 int apsr_str_len
= strlen (apsr_str
);
1849 reg
= arm_reg_parse (&str
, REGLIST_RN
);
1850 if (etype
== REGLIST_CLRM
)
1852 if (reg
== REG_SP
|| reg
== REG_PC
)
1854 else if (reg
== FAIL
1855 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1856 && !ISALPHA (*(str
+ apsr_str_len
)))
1859 str
+= apsr_str_len
;
1864 first_error (_("r0-r12, lr or APSR expected"));
1868 else /* etype == REGLIST_RN. */
1872 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
1883 first_error (_("bad range in register list"));
1887 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1889 if (range
& (1 << i
))
1891 (_("Warning: duplicated register (r%d) in register list"),
1899 if (range
& (1 << reg
))
1900 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1902 else if (reg
<= cur_reg
)
1903 as_tsktsk (_("Warning: register range not in ascending order"));
1908 while (skip_past_comma (&str
) != FAIL
1909 || (in_range
= 1, *str
++ == '-'));
1912 if (skip_past_char (&str
, '}') == FAIL
)
1914 first_error (_("missing `}'"));
1918 else if (etype
== REGLIST_RN
)
1922 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1925 if (exp
.X_op
== O_constant
)
1927 if (exp
.X_add_number
1928 != (exp
.X_add_number
& 0x0000ffff))
1930 inst
.error
= _("invalid register mask");
1934 if ((range
& exp
.X_add_number
) != 0)
1936 int regno
= range
& exp
.X_add_number
;
1939 regno
= (1 << regno
) - 1;
1941 (_("Warning: duplicated register (r%d) in register list"),
1945 range
|= exp
.X_add_number
;
1949 if (inst
.relocs
[0].type
!= 0)
1951 inst
.error
= _("expression too complex");
1955 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
1956 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
1957 inst
.relocs
[0].pc_rel
= 0;
1961 if (*str
== '|' || *str
== '+')
1967 while (another_range
);
1973 /* Parse a VFP register list. If the string is invalid return FAIL.
1974 Otherwise return the number of registers, and set PBASE to the first
1975 register. Parses registers of type ETYPE.
1976 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1977 - Q registers can be used to specify pairs of D registers
1978 - { } can be omitted from around a singleton register list
1979 FIXME: This is not implemented, as it would require backtracking in
1982 This could be done (the meaning isn't really ambiguous), but doesn't
1983 fit in well with the current parsing framework.
1984 - 32 D registers may be used (also true for VFPv3).
1985 FIXME: Types are ignored in these register lists, which is probably a
1989 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
1990 bfd_boolean
*partial_match
)
1995 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1999 unsigned long mask
= 0;
2001 bfd_boolean vpr_seen
= FALSE
;
2002 bfd_boolean expect_vpr
=
2003 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2005 if (skip_past_char (&str
, '{') == FAIL
)
2007 inst
.error
= _("expecting {");
2014 case REGLIST_VFP_S_VPR
:
2015 regtype
= REG_TYPE_VFS
;
2020 case REGLIST_VFP_D_VPR
:
2021 regtype
= REG_TYPE_VFD
;
2024 case REGLIST_NEON_D
:
2025 regtype
= REG_TYPE_NDQ
;
2032 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2034 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2035 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2039 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2042 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2049 base_reg
= max_regs
;
2050 *partial_match
= FALSE
;
2054 int setmask
= 1, addregs
= 1;
2055 const char vpr_str
[] = "vpr";
2056 int vpr_str_len
= strlen (vpr_str
);
2058 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2062 if (new_base
== FAIL
2063 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2064 && !ISALPHA (*(str
+ vpr_str_len
))
2070 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2074 first_error (_("VPR expected last"));
2077 else if (new_base
== FAIL
)
2079 if (regtype
== REG_TYPE_VFS
)
2080 first_error (_("VFP single precision register or VPR "
2082 else /* regtype == REG_TYPE_VFD. */
2083 first_error (_("VFP/Neon double precision register or VPR "
2088 else if (new_base
== FAIL
)
2090 first_error (_(reg_expected_msgs
[regtype
]));
2094 *partial_match
= TRUE
;
2098 if (new_base
>= max_regs
)
2100 first_error (_("register out of range in list"));
2104 /* Note: a value of 2 * n is returned for the register Q<n>. */
2105 if (regtype
== REG_TYPE_NQ
)
2111 if (new_base
< base_reg
)
2112 base_reg
= new_base
;
2114 if (mask
& (setmask
<< new_base
))
2116 first_error (_("invalid register list"));
2120 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2122 as_tsktsk (_("register list not in ascending order"));
2126 mask
|= setmask
<< new_base
;
2129 if (*str
== '-') /* We have the start of a range expression */
2135 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2138 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2142 if (high_range
>= max_regs
)
2144 first_error (_("register out of range in list"));
2148 if (regtype
== REG_TYPE_NQ
)
2149 high_range
= high_range
+ 1;
2151 if (high_range
<= new_base
)
2153 inst
.error
= _("register range not in ascending order");
2157 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2159 if (mask
& (setmask
<< new_base
))
2161 inst
.error
= _("invalid register list");
2165 mask
|= setmask
<< new_base
;
2170 while (skip_past_comma (&str
) != FAIL
);
2174 /* Sanity check -- should have raised a parse error above. */
2175 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2180 if (expect_vpr
&& !vpr_seen
)
2182 first_error (_("VPR expected last"));
2186 /* Final test -- the registers must be consecutive. */
2188 for (i
= 0; i
< count
; i
++)
2190 if ((mask
& (1u << i
)) == 0)
2192 inst
.error
= _("non-contiguous register range");
2202 /* True if two alias types are the same. */
2205 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2213 if (a
->defined
!= b
->defined
)
2216 if ((a
->defined
& NTA_HASTYPE
) != 0
2217 && (a
->eltype
.type
!= b
->eltype
.type
2218 || a
->eltype
.size
!= b
->eltype
.size
))
2221 if ((a
->defined
& NTA_HASINDEX
) != 0
2222 && (a
->index
!= b
->index
))
2228 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2229 The base register is put in *PBASE.
2230 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2232 The register stride (minus one) is put in bit 4 of the return value.
2233 Bits [6:5] encode the list length (minus one).
2234 The type of the list elements is put in *ELTYPE, if non-NULL. */
2236 #define NEON_LANE(X) ((X) & 0xf)
2237 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2238 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2241 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2243 struct neon_type_el
*eltype
)
2250 int leading_brace
= 0;
2251 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2252 const char *const incr_error
= mve
? _("register stride must be 1") :
2253 _("register stride must be 1 or 2");
2254 const char *const type_error
= _("mismatched element/structure types in list");
2255 struct neon_typed_alias firsttype
;
2256 firsttype
.defined
= 0;
2257 firsttype
.eltype
.type
= NT_invtype
;
2258 firsttype
.eltype
.size
= -1;
2259 firsttype
.index
= -1;
2261 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2266 struct neon_typed_alias atype
;
2268 rtype
= REG_TYPE_MQ
;
2269 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2273 first_error (_(reg_expected_msgs
[rtype
]));
2280 if (rtype
== REG_TYPE_NQ
)
2286 else if (reg_incr
== -1)
2288 reg_incr
= getreg
- base_reg
;
2289 if (reg_incr
< 1 || reg_incr
> 2)
2291 first_error (_(incr_error
));
2295 else if (getreg
!= base_reg
+ reg_incr
* count
)
2297 first_error (_(incr_error
));
2301 if (! neon_alias_types_same (&atype
, &firsttype
))
2303 first_error (_(type_error
));
2307 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2311 struct neon_typed_alias htype
;
2312 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2314 lane
= NEON_INTERLEAVE_LANES
;
2315 else if (lane
!= NEON_INTERLEAVE_LANES
)
2317 first_error (_(type_error
));
2322 else if (reg_incr
!= 1)
2324 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2328 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2331 first_error (_(reg_expected_msgs
[rtype
]));
2334 if (! neon_alias_types_same (&htype
, &firsttype
))
2336 first_error (_(type_error
));
2339 count
+= hireg
+ dregs
- getreg
;
2343 /* If we're using Q registers, we can't use [] or [n] syntax. */
2344 if (rtype
== REG_TYPE_NQ
)
2350 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2354 else if (lane
!= atype
.index
)
2356 first_error (_(type_error
));
2360 else if (lane
== -1)
2361 lane
= NEON_INTERLEAVE_LANES
;
2362 else if (lane
!= NEON_INTERLEAVE_LANES
)
2364 first_error (_(type_error
));
2369 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2371 /* No lane set by [x]. We must be interleaving structures. */
2373 lane
= NEON_INTERLEAVE_LANES
;
2376 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2377 || (count
> 1 && reg_incr
== -1))
2379 first_error (_("error parsing element/structure list"));
2383 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2385 first_error (_("expected }"));
2393 *eltype
= firsttype
.eltype
;
2398 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2401 /* Parse an explicit relocation suffix on an expression. This is
2402 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2403 arm_reloc_hsh contains no entries, so this function can only
2404 succeed if there is no () after the word. Returns -1 on error,
2405 BFD_RELOC_UNUSED if there wasn't any suffix. */
2408 parse_reloc (char **str
)
2410 struct reloc_entry
*r
;
2414 return BFD_RELOC_UNUSED
;
2419 while (*q
&& *q
!= ')' && *q
!= ',')
2424 if ((r
= (struct reloc_entry
*)
2425 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2432 /* Directives: register aliases. */
2434 static struct reg_entry
*
2435 insert_reg_alias (char *str
, unsigned number
, int type
)
2437 struct reg_entry
*new_reg
;
2440 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2442 if (new_reg
->builtin
)
2443 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2445 /* Only warn about a redefinition if it's not defined as the
2447 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2448 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2453 name
= xstrdup (str
);
2454 new_reg
= XNEW (struct reg_entry
);
2456 new_reg
->name
= name
;
2457 new_reg
->number
= number
;
2458 new_reg
->type
= type
;
2459 new_reg
->builtin
= FALSE
;
2460 new_reg
->neon
= NULL
;
2462 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2469 insert_neon_reg_alias (char *str
, int number
, int type
,
2470 struct neon_typed_alias
*atype
)
2472 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2476 first_error (_("attempt to redefine typed alias"));
2482 reg
->neon
= XNEW (struct neon_typed_alias
);
2483 *reg
->neon
= *atype
;
2487 /* Look for the .req directive. This is of the form:
2489 new_register_name .req existing_register_name
2491 If we find one, or if it looks sufficiently like one that we want to
2492 handle any error here, return TRUE. Otherwise return FALSE. */
2495 create_register_alias (char * newname
, char *p
)
2497 struct reg_entry
*old
;
2498 char *oldname
, *nbuf
;
2501 /* The input scrubber ensures that whitespace after the mnemonic is
2502 collapsed to single spaces. */
2504 if (strncmp (oldname
, " .req ", 6) != 0)
2508 if (*oldname
== '\0')
2511 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2514 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2518 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2519 the desired alias name, and p points to its end. If not, then
2520 the desired alias name is in the global original_case_string. */
2521 #ifdef TC_CASE_SENSITIVE
2524 newname
= original_case_string
;
2525 nlen
= strlen (newname
);
2528 nbuf
= xmemdup0 (newname
, nlen
);
2530 /* Create aliases under the new name as stated; an all-lowercase
2531 version of the new name; and an all-uppercase version of the new
2533 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2535 for (p
= nbuf
; *p
; p
++)
2538 if (strncmp (nbuf
, newname
, nlen
))
2540 /* If this attempt to create an additional alias fails, do not bother
2541 trying to create the all-lower case alias. We will fail and issue
2542 a second, duplicate error message. This situation arises when the
2543 programmer does something like:
2546 The second .req creates the "Foo" alias but then fails to create
2547 the artificial FOO alias because it has already been created by the
2549 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2556 for (p
= nbuf
; *p
; p
++)
2559 if (strncmp (nbuf
, newname
, nlen
))
2560 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2567 /* Create a Neon typed/indexed register alias using directives, e.g.:
2572 These typed registers can be used instead of the types specified after the
2573 Neon mnemonic, so long as all operands given have types. Types can also be
2574 specified directly, e.g.:
2575 vadd d0.s32, d1.s32, d2.s32 */
2578 create_neon_reg_alias (char *newname
, char *p
)
2580 enum arm_reg_type basetype
;
2581 struct reg_entry
*basereg
;
2582 struct reg_entry mybasereg
;
2583 struct neon_type ntype
;
2584 struct neon_typed_alias typeinfo
;
2585 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2588 typeinfo
.defined
= 0;
2589 typeinfo
.eltype
.type
= NT_invtype
;
2590 typeinfo
.eltype
.size
= -1;
2591 typeinfo
.index
= -1;
2595 if (strncmp (p
, " .dn ", 5) == 0)
2596 basetype
= REG_TYPE_VFD
;
2597 else if (strncmp (p
, " .qn ", 5) == 0)
2598 basetype
= REG_TYPE_NQ
;
2607 basereg
= arm_reg_parse_multi (&p
);
2609 if (basereg
&& basereg
->type
!= basetype
)
2611 as_bad (_("bad type for register"));
2615 if (basereg
== NULL
)
2618 /* Try parsing as an integer. */
2619 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2620 if (exp
.X_op
!= O_constant
)
2622 as_bad (_("expression must be constant"));
2625 basereg
= &mybasereg
;
2626 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2632 typeinfo
= *basereg
->neon
;
2634 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2636 /* We got a type. */
2637 if (typeinfo
.defined
& NTA_HASTYPE
)
2639 as_bad (_("can't redefine the type of a register alias"));
2643 typeinfo
.defined
|= NTA_HASTYPE
;
2644 if (ntype
.elems
!= 1)
2646 as_bad (_("you must specify a single type only"));
2649 typeinfo
.eltype
= ntype
.el
[0];
2652 if (skip_past_char (&p
, '[') == SUCCESS
)
2655 /* We got a scalar index. */
2657 if (typeinfo
.defined
& NTA_HASINDEX
)
2659 as_bad (_("can't redefine the index of a scalar alias"));
2663 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2665 if (exp
.X_op
!= O_constant
)
2667 as_bad (_("scalar index must be constant"));
2671 typeinfo
.defined
|= NTA_HASINDEX
;
2672 typeinfo
.index
= exp
.X_add_number
;
2674 if (skip_past_char (&p
, ']') == FAIL
)
2676 as_bad (_("expecting ]"));
2681 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2682 the desired alias name, and p points to its end. If not, then
2683 the desired alias name is in the global original_case_string. */
2684 #ifdef TC_CASE_SENSITIVE
2685 namelen
= nameend
- newname
;
2687 newname
= original_case_string
;
2688 namelen
= strlen (newname
);
2691 namebuf
= xmemdup0 (newname
, namelen
);
2693 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2694 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2696 /* Insert name in all uppercase. */
2697 for (p
= namebuf
; *p
; p
++)
2700 if (strncmp (namebuf
, newname
, namelen
))
2701 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2702 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2704 /* Insert name in all lowercase. */
2705 for (p
= namebuf
; *p
; p
++)
2708 if (strncmp (namebuf
, newname
, namelen
))
2709 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2710 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2716 /* Should never be called, as .req goes between the alias and the
2717 register name, not at the beginning of the line. */
2720 s_req (int a ATTRIBUTE_UNUSED
)
2722 as_bad (_("invalid syntax for .req directive"));
2726 s_dn (int a ATTRIBUTE_UNUSED
)
2728 as_bad (_("invalid syntax for .dn directive"));
2732 s_qn (int a ATTRIBUTE_UNUSED
)
2734 as_bad (_("invalid syntax for .qn directive"));
2737 /* The .unreq directive deletes an alias which was previously defined
2738 by .req. For example:
2744 s_unreq (int a ATTRIBUTE_UNUSED
)
2749 name
= input_line_pointer
;
2751 while (*input_line_pointer
!= 0
2752 && *input_line_pointer
!= ' '
2753 && *input_line_pointer
!= '\n')
2754 ++input_line_pointer
;
2756 saved_char
= *input_line_pointer
;
2757 *input_line_pointer
= 0;
2760 as_bad (_("invalid syntax for .unreq directive"));
2763 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2767 as_bad (_("unknown register alias '%s'"), name
);
2768 else if (reg
->builtin
)
2769 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2776 hash_delete (arm_reg_hsh
, name
, FALSE
);
2777 free ((char *) reg
->name
);
2782 /* Also locate the all upper case and all lower case versions.
2783 Do not complain if we cannot find one or the other as it
2784 was probably deleted above. */
2786 nbuf
= strdup (name
);
2787 for (p
= nbuf
; *p
; p
++)
2789 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2792 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2793 free ((char *) reg
->name
);
2799 for (p
= nbuf
; *p
; p
++)
2801 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2804 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2805 free ((char *) reg
->name
);
2815 *input_line_pointer
= saved_char
;
2816 demand_empty_rest_of_line ();
2819 /* Directives: Instruction set selection. */
2822 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2823 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2824 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2825 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2827 /* Create a new mapping symbol for the transition to STATE. */
2830 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2833 const char * symname
;
2840 type
= BSF_NO_FLAGS
;
2844 type
= BSF_NO_FLAGS
;
2848 type
= BSF_NO_FLAGS
;
2854 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2855 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2860 THUMB_SET_FUNC (symbolP
, 0);
2861 ARM_SET_THUMB (symbolP
, 0);
2862 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2866 THUMB_SET_FUNC (symbolP
, 1);
2867 ARM_SET_THUMB (symbolP
, 1);
2868 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2876 /* Save the mapping symbols for future reference. Also check that
2877 we do not place two mapping symbols at the same offset within a
2878 frag. We'll handle overlap between frags in
2879 check_mapping_symbols.
2881 If .fill or other data filling directive generates zero sized data,
2882 the mapping symbol for the following code will have the same value
2883 as the one generated for the data filling directive. In this case,
2884 we replace the old symbol with the new one at the same address. */
2887 if (frag
->tc_frag_data
.first_map
!= NULL
)
2889 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2890 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2892 frag
->tc_frag_data
.first_map
= symbolP
;
2894 if (frag
->tc_frag_data
.last_map
!= NULL
)
2896 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2897 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2898 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2900 frag
->tc_frag_data
.last_map
= symbolP
;
2903 /* We must sometimes convert a region marked as code to data during
2904 code alignment, if an odd number of bytes have to be padded. The
2905 code mapping symbol is pushed to an aligned address. */
2908 insert_data_mapping_symbol (enum mstate state
,
2909 valueT value
, fragS
*frag
, offsetT bytes
)
2911 /* If there was already a mapping symbol, remove it. */
2912 if (frag
->tc_frag_data
.last_map
!= NULL
2913 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2915 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2919 know (frag
->tc_frag_data
.first_map
== symp
);
2920 frag
->tc_frag_data
.first_map
= NULL
;
2922 frag
->tc_frag_data
.last_map
= NULL
;
2923 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2926 make_mapping_symbol (MAP_DATA
, value
, frag
);
2927 make_mapping_symbol (state
, value
+ bytes
, frag
);
2930 static void mapping_state_2 (enum mstate state
, int max_chars
);
2932 /* Set the mapping state to STATE. Only call this when about to
2933 emit some STATE bytes to the file. */
2935 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2937 mapping_state (enum mstate state
)
2939 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2941 if (mapstate
== state
)
2942 /* The mapping symbol has already been emitted.
2943 There is nothing else to do. */
2946 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2948 All ARM instructions require 4-byte alignment.
2949 (Almost) all Thumb instructions require 2-byte alignment.
2951 When emitting instructions into any section, mark the section
2954 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2955 but themselves require 2-byte alignment; this applies to some
2956 PC- relative forms. However, these cases will involve implicit
2957 literal pool generation or an explicit .align >=2, both of
2958 which will cause the section to me marked with sufficient
2959 alignment. Thus, we don't handle those cases here. */
2960 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2962 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2963 /* This case will be evaluated later. */
2966 mapping_state_2 (state
, 0);
2969 /* Same as mapping_state, but MAX_CHARS bytes have already been
2970 allocated. Put the mapping symbol that far back. */
2973 mapping_state_2 (enum mstate state
, int max_chars
)
2975 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2977 if (!SEG_NORMAL (now_seg
))
2980 if (mapstate
== state
)
2981 /* The mapping symbol has already been emitted.
2982 There is nothing else to do. */
2985 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2986 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2988 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2989 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2992 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2995 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2996 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
3000 #define mapping_state(x) ((void)0)
3001 #define mapping_state_2(x, y) ((void)0)
3004 /* Find the real, Thumb encoded start of a Thumb function. */
3008 find_real_start (symbolS
* symbolP
)
3011 const char * name
= S_GET_NAME (symbolP
);
3012 symbolS
* new_target
;
3014 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3015 #define STUB_NAME ".real_start_of"
3020 /* The compiler may generate BL instructions to local labels because
3021 it needs to perform a branch to a far away location. These labels
3022 do not have a corresponding ".real_start_of" label. We check
3023 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3024 the ".real_start_of" convention for nonlocal branches. */
3025 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3028 real_start
= concat (STUB_NAME
, name
, NULL
);
3029 new_target
= symbol_find (real_start
);
3032 if (new_target
== NULL
)
3034 as_warn (_("Failed to find real start of function: %s\n"), name
);
3035 new_target
= symbolP
;
3043 opcode_select (int width
)
3050 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3051 as_bad (_("selected processor does not support THUMB opcodes"));
3054 /* No need to force the alignment, since we will have been
3055 coming from ARM mode, which is word-aligned. */
3056 record_alignment (now_seg
, 1);
3063 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3064 as_bad (_("selected processor does not support ARM opcodes"));
3069 frag_align (2, 0, 0);
3071 record_alignment (now_seg
, 1);
3076 as_bad (_("invalid instruction size selected (%d)"), width
);
3081 s_arm (int ignore ATTRIBUTE_UNUSED
)
3084 demand_empty_rest_of_line ();
3088 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3091 demand_empty_rest_of_line ();
3095 s_code (int unused ATTRIBUTE_UNUSED
)
3099 temp
= get_absolute_expression ();
3104 opcode_select (temp
);
3108 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3113 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3115 /* If we are not already in thumb mode go into it, EVEN if
3116 the target processor does not support thumb instructions.
3117 This is used by gcc/config/arm/lib1funcs.asm for example
3118 to compile interworking support functions even if the
3119 target processor should not support interworking. */
3123 record_alignment (now_seg
, 1);
3126 demand_empty_rest_of_line ();
3130 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3134 /* The following label is the name/address of the start of a Thumb function.
3135 We need to know this for the interworking support. */
3136 label_is_thumb_function_name
= TRUE
;
3139 /* Perform a .set directive, but also mark the alias as
3140 being a thumb function. */
3143 s_thumb_set (int equiv
)
3145 /* XXX the following is a duplicate of the code for s_set() in read.c
3146 We cannot just call that code as we need to get at the symbol that
3153 /* Especial apologies for the random logic:
3154 This just grew, and could be parsed much more simply!
3156 delim
= get_symbol_name (& name
);
3157 end_name
= input_line_pointer
;
3158 (void) restore_line_pointer (delim
);
3160 if (*input_line_pointer
!= ',')
3163 as_bad (_("expected comma after name \"%s\""), name
);
3165 ignore_rest_of_line ();
3169 input_line_pointer
++;
3172 if (name
[0] == '.' && name
[1] == '\0')
3174 /* XXX - this should not happen to .thumb_set. */
3178 if ((symbolP
= symbol_find (name
)) == NULL
3179 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3182 /* When doing symbol listings, play games with dummy fragments living
3183 outside the normal fragment chain to record the file and line info
3185 if (listing
& LISTING_SYMBOLS
)
3187 extern struct list_info_struct
* listing_tail
;
3188 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3190 memset (dummy_frag
, 0, sizeof (fragS
));
3191 dummy_frag
->fr_type
= rs_fill
;
3192 dummy_frag
->line
= listing_tail
;
3193 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
3194 dummy_frag
->fr_symbol
= symbolP
;
3198 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3201 /* "set" symbols are local unless otherwise specified. */
3202 SF_SET_LOCAL (symbolP
);
3203 #endif /* OBJ_COFF */
3204 } /* Make a new symbol. */
3206 symbol_table_insert (symbolP
);
3211 && S_IS_DEFINED (symbolP
)
3212 && S_GET_SEGMENT (symbolP
) != reg_section
)
3213 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3215 pseudo_set (symbolP
);
3217 demand_empty_rest_of_line ();
3219 /* XXX Now we come to the Thumb specific bit of code. */
3221 THUMB_SET_FUNC (symbolP
, 1);
3222 ARM_SET_THUMB (symbolP
, 1);
3223 #if defined OBJ_ELF || defined OBJ_COFF
3224 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3228 /* Directives: Mode selection. */
3230 /* .syntax [unified|divided] - choose the new unified syntax
3231 (same for Arm and Thumb encoding, modulo slight differences in what
3232 can be represented) or the old divergent syntax for each mode. */
3234 s_syntax (int unused ATTRIBUTE_UNUSED
)
3238 delim
= get_symbol_name (& name
);
3240 if (!strcasecmp (name
, "unified"))
3241 unified_syntax
= TRUE
;
3242 else if (!strcasecmp (name
, "divided"))
3243 unified_syntax
= FALSE
;
3246 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3249 (void) restore_line_pointer (delim
);
3250 demand_empty_rest_of_line ();
3253 /* Directives: sectioning and alignment. */
3256 s_bss (int ignore ATTRIBUTE_UNUSED
)
3258 /* We don't support putting frags in the BSS segment, we fake it by
3259 marking in_bss, then looking at s_skip for clues. */
3260 subseg_set (bss_section
, 0);
3261 demand_empty_rest_of_line ();
3263 #ifdef md_elf_section_change_hook
3264 md_elf_section_change_hook ();
3269 s_even (int ignore ATTRIBUTE_UNUSED
)
3271 /* Never make frag if expect extra pass. */
3273 frag_align (1, 0, 0);
3275 record_alignment (now_seg
, 1);
3277 demand_empty_rest_of_line ();
3280 /* Directives: CodeComposer Studio. */
3282 /* .ref (for CodeComposer Studio syntax only). */
3284 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3286 if (codecomposer_syntax
)
3287 ignore_rest_of_line ();
3289 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3292 /* If name is not NULL, then it is used for marking the beginning of a
3293 function, whereas if it is NULL then it means the function end. */
3295 asmfunc_debug (const char * name
)
3297 static const char * last_name
= NULL
;
3301 gas_assert (last_name
== NULL
);
3304 if (debug_type
== DEBUG_STABS
)
3305 stabs_generate_asm_func (name
, name
);
3309 gas_assert (last_name
!= NULL
);
3311 if (debug_type
== DEBUG_STABS
)
3312 stabs_generate_asm_endfunc (last_name
, last_name
);
3319 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3321 if (codecomposer_syntax
)
3323 switch (asmfunc_state
)
3325 case OUTSIDE_ASMFUNC
:
3326 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3329 case WAITING_ASMFUNC_NAME
:
3330 as_bad (_(".asmfunc repeated."));
3333 case WAITING_ENDASMFUNC
:
3334 as_bad (_(".asmfunc without function."));
3337 demand_empty_rest_of_line ();
3340 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3344 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3346 if (codecomposer_syntax
)
3348 switch (asmfunc_state
)
3350 case OUTSIDE_ASMFUNC
:
3351 as_bad (_(".endasmfunc without a .asmfunc."));
3354 case WAITING_ASMFUNC_NAME
:
3355 as_bad (_(".endasmfunc without function."));
3358 case WAITING_ENDASMFUNC
:
3359 asmfunc_state
= OUTSIDE_ASMFUNC
;
3360 asmfunc_debug (NULL
);
3363 demand_empty_rest_of_line ();
3366 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3370 s_ccs_def (int name
)
3372 if (codecomposer_syntax
)
3375 as_bad (_(".def pseudo-op only available with -mccs flag."));
3378 /* Directives: Literal pools. */
3380 static literal_pool
*
3381 find_literal_pool (void)
3383 literal_pool
* pool
;
3385 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3387 if (pool
->section
== now_seg
3388 && pool
->sub_section
== now_subseg
)
3395 static literal_pool
*
3396 find_or_make_literal_pool (void)
3398 /* Next literal pool ID number. */
3399 static unsigned int latest_pool_num
= 1;
3400 literal_pool
* pool
;
3402 pool
= find_literal_pool ();
3406 /* Create a new pool. */
3407 pool
= XNEW (literal_pool
);
3411 pool
->next_free_entry
= 0;
3412 pool
->section
= now_seg
;
3413 pool
->sub_section
= now_subseg
;
3414 pool
->next
= list_of_pools
;
3415 pool
->symbol
= NULL
;
3416 pool
->alignment
= 2;
3418 /* Add it to the list. */
3419 list_of_pools
= pool
;
3422 /* New pools, and emptied pools, will have a NULL symbol. */
3423 if (pool
->symbol
== NULL
)
3425 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3426 (valueT
) 0, &zero_address_frag
);
3427 pool
->id
= latest_pool_num
++;
3434 /* Add the literal in the global 'inst'
3435 structure to the relevant literal pool. */
3438 add_to_lit_pool (unsigned int nbytes
)
3440 #define PADDING_SLOT 0x1
3441 #define LIT_ENTRY_SIZE_MASK 0xFF
3442 literal_pool
* pool
;
3443 unsigned int entry
, pool_size
= 0;
3444 bfd_boolean padding_slot_p
= FALSE
;
3450 imm1
= inst
.operands
[1].imm
;
3451 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3452 : inst
.relocs
[0].exp
.X_unsigned
? 0
3453 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3454 if (target_big_endian
)
3457 imm2
= inst
.operands
[1].imm
;
3461 pool
= find_or_make_literal_pool ();
3463 /* Check if this literal value is already in the pool. */
3464 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3468 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3469 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3470 && (pool
->literals
[entry
].X_add_number
3471 == inst
.relocs
[0].exp
.X_add_number
)
3472 && (pool
->literals
[entry
].X_md
== nbytes
)
3473 && (pool
->literals
[entry
].X_unsigned
3474 == inst
.relocs
[0].exp
.X_unsigned
))
3477 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3478 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3479 && (pool
->literals
[entry
].X_add_number
3480 == inst
.relocs
[0].exp
.X_add_number
)
3481 && (pool
->literals
[entry
].X_add_symbol
3482 == inst
.relocs
[0].exp
.X_add_symbol
)
3483 && (pool
->literals
[entry
].X_op_symbol
3484 == inst
.relocs
[0].exp
.X_op_symbol
)
3485 && (pool
->literals
[entry
].X_md
== nbytes
))
3488 else if ((nbytes
== 8)
3489 && !(pool_size
& 0x7)
3490 && ((entry
+ 1) != pool
->next_free_entry
)
3491 && (pool
->literals
[entry
].X_op
== O_constant
)
3492 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3493 && (pool
->literals
[entry
].X_unsigned
3494 == inst
.relocs
[0].exp
.X_unsigned
)
3495 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3496 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3497 && (pool
->literals
[entry
+ 1].X_unsigned
3498 == inst
.relocs
[0].exp
.X_unsigned
))
3501 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3502 if (padding_slot_p
&& (nbytes
== 4))
3508 /* Do we need to create a new entry? */
3509 if (entry
== pool
->next_free_entry
)
3511 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3513 inst
.error
= _("literal pool overflow");
3519 /* For 8-byte entries, we align to an 8-byte boundary,
3520 and split it into two 4-byte entries, because on 32-bit
3521 host, 8-byte constants are treated as big num, thus
3522 saved in "generic_bignum" which will be overwritten
3523 by later assignments.
3525 We also need to make sure there is enough space for
3528 We also check to make sure the literal operand is a
3530 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3531 || inst
.relocs
[0].exp
.X_op
== O_big
))
3533 inst
.error
= _("invalid type for literal pool");
3536 else if (pool_size
& 0x7)
3538 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3540 inst
.error
= _("literal pool overflow");
3544 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3545 pool
->literals
[entry
].X_op
= O_constant
;
3546 pool
->literals
[entry
].X_add_number
= 0;
3547 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3548 pool
->next_free_entry
+= 1;
3551 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3553 inst
.error
= _("literal pool overflow");
3557 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3558 pool
->literals
[entry
].X_op
= O_constant
;
3559 pool
->literals
[entry
].X_add_number
= imm1
;
3560 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3561 pool
->literals
[entry
++].X_md
= 4;
3562 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3563 pool
->literals
[entry
].X_op
= O_constant
;
3564 pool
->literals
[entry
].X_add_number
= imm2
;
3565 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3566 pool
->literals
[entry
].X_md
= 4;
3567 pool
->alignment
= 3;
3568 pool
->next_free_entry
+= 1;
3572 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3573 pool
->literals
[entry
].X_md
= 4;
3577 /* PR ld/12974: Record the location of the first source line to reference
3578 this entry in the literal pool. If it turns out during linking that the
3579 symbol does not exist we will be able to give an accurate line number for
3580 the (first use of the) missing reference. */
3581 if (debug_type
== DEBUG_DWARF2
)
3582 dwarf2_where (pool
->locs
+ entry
);
3584 pool
->next_free_entry
+= 1;
3586 else if (padding_slot_p
)
3588 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3589 pool
->literals
[entry
].X_md
= nbytes
;
3592 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3593 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3594 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3600 tc_start_label_without_colon (void)
3602 bfd_boolean ret
= TRUE
;
3604 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3606 const char *label
= input_line_pointer
;
3608 while (!is_end_of_line
[(int) label
[-1]])
3613 as_bad (_("Invalid label '%s'"), label
);
3617 asmfunc_debug (label
);
3619 asmfunc_state
= WAITING_ENDASMFUNC
;
3625 /* Can't use symbol_new here, so have to create a symbol and then at
3626 a later date assign it a value. That's what these functions do. */
3629 symbol_locate (symbolS
* symbolP
,
3630 const char * name
, /* It is copied, the caller can modify. */
3631 segT segment
, /* Segment identifier (SEG_<something>). */
3632 valueT valu
, /* Symbol value. */
3633 fragS
* frag
) /* Associated fragment. */
3636 char * preserved_copy_of_name
;
3638 name_length
= strlen (name
) + 1; /* +1 for \0. */
3639 obstack_grow (¬es
, name
, name_length
);
3640 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3642 #ifdef tc_canonicalize_symbol_name
3643 preserved_copy_of_name
=
3644 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3647 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3649 S_SET_SEGMENT (symbolP
, segment
);
3650 S_SET_VALUE (symbolP
, valu
);
3651 symbol_clear_list_pointers (symbolP
);
3653 symbol_set_frag (symbolP
, frag
);
3655 /* Link to end of symbol chain. */
3657 extern int symbol_table_frozen
;
3659 if (symbol_table_frozen
)
3663 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3665 obj_symbol_new_hook (symbolP
);
3667 #ifdef tc_symbol_new_hook
3668 tc_symbol_new_hook (symbolP
);
3672 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3673 #endif /* DEBUG_SYMS */
3677 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3680 literal_pool
* pool
;
3683 pool
= find_literal_pool ();
3685 || pool
->symbol
== NULL
3686 || pool
->next_free_entry
== 0)
3689 /* Align pool as you have word accesses.
3690 Only make a frag if we have to. */
3692 frag_align (pool
->alignment
, 0, 0);
3694 record_alignment (now_seg
, 2);
3697 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3698 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3700 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3702 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3703 (valueT
) frag_now_fix (), frag_now
);
3704 symbol_table_insert (pool
->symbol
);
3706 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3708 #if defined OBJ_COFF || defined OBJ_ELF
3709 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3712 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3715 if (debug_type
== DEBUG_DWARF2
)
3716 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3718 /* First output the expression in the instruction to the pool. */
3719 emit_expr (&(pool
->literals
[entry
]),
3720 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3723 /* Mark the pool as empty. */
3724 pool
->next_free_entry
= 0;
3725 pool
->symbol
= NULL
;
3729 /* Forward declarations for functions below, in the MD interface
3731 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3732 static valueT
create_unwind_entry (int);
3733 static void start_unwind_section (const segT
, int);
3734 static void add_unwind_opcode (valueT
, int);
3735 static void flush_pending_unwind (void);
3737 /* Directives: Data. */
3740 s_arm_elf_cons (int nbytes
)
3744 #ifdef md_flush_pending_output
3745 md_flush_pending_output ();
3748 if (is_it_end_of_statement ())
3750 demand_empty_rest_of_line ();
3754 #ifdef md_cons_align
3755 md_cons_align (nbytes
);
3758 mapping_state (MAP_DATA
);
3762 char *base
= input_line_pointer
;
3766 if (exp
.X_op
!= O_symbol
)
3767 emit_expr (&exp
, (unsigned int) nbytes
);
3770 char *before_reloc
= input_line_pointer
;
3771 reloc
= parse_reloc (&input_line_pointer
);
3774 as_bad (_("unrecognized relocation suffix"));
3775 ignore_rest_of_line ();
3778 else if (reloc
== BFD_RELOC_UNUSED
)
3779 emit_expr (&exp
, (unsigned int) nbytes
);
3782 reloc_howto_type
*howto
= (reloc_howto_type
*)
3783 bfd_reloc_type_lookup (stdoutput
,
3784 (bfd_reloc_code_real_type
) reloc
);
3785 int size
= bfd_get_reloc_size (howto
);
3787 if (reloc
== BFD_RELOC_ARM_PLT32
)
3789 as_bad (_("(plt) is only valid on branch targets"));
3790 reloc
= BFD_RELOC_UNUSED
;
3795 as_bad (ngettext ("%s relocations do not fit in %d byte",
3796 "%s relocations do not fit in %d bytes",
3798 howto
->name
, nbytes
);
3801 /* We've parsed an expression stopping at O_symbol.
3802 But there may be more expression left now that we
3803 have parsed the relocation marker. Parse it again.
3804 XXX Surely there is a cleaner way to do this. */
3805 char *p
= input_line_pointer
;
3807 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3809 memcpy (save_buf
, base
, input_line_pointer
- base
);
3810 memmove (base
+ (input_line_pointer
- before_reloc
),
3811 base
, before_reloc
- base
);
3813 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3815 memcpy (base
, save_buf
, p
- base
);
3817 offset
= nbytes
- size
;
3818 p
= frag_more (nbytes
);
3819 memset (p
, 0, nbytes
);
3820 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3821 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3827 while (*input_line_pointer
++ == ',');
3829 /* Put terminator back into stream. */
3830 input_line_pointer
--;
3831 demand_empty_rest_of_line ();
3834 /* Emit an expression containing a 32-bit thumb instruction.
3835 Implementation based on put_thumb32_insn. */
3838 emit_thumb32_expr (expressionS
* exp
)
3840 expressionS exp_high
= *exp
;
3842 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3843 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3844 exp
->X_add_number
&= 0xffff;
3845 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3848 /* Guess the instruction size based on the opcode. */
3851 thumb_insn_size (int opcode
)
3853 if ((unsigned int) opcode
< 0xe800u
)
3855 else if ((unsigned int) opcode
>= 0xe8000000u
)
3862 emit_insn (expressionS
*exp
, int nbytes
)
3866 if (exp
->X_op
== O_constant
)
3871 size
= thumb_insn_size (exp
->X_add_number
);
3875 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3877 as_bad (_(".inst.n operand too big. "\
3878 "Use .inst.w instead"));
3883 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
3884 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
3886 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3888 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3889 emit_thumb32_expr (exp
);
3891 emit_expr (exp
, (unsigned int) size
);
3893 it_fsm_post_encode ();
3897 as_bad (_("cannot determine Thumb instruction size. " \
3898 "Use .inst.n/.inst.w instead"));
3901 as_bad (_("constant expression required"));
3906 /* Like s_arm_elf_cons but do not use md_cons_align and
3907 set the mapping state to MAP_ARM/MAP_THUMB. */
3910 s_arm_elf_inst (int nbytes
)
3912 if (is_it_end_of_statement ())
3914 demand_empty_rest_of_line ();
3918 /* Calling mapping_state () here will not change ARM/THUMB,
3919 but will ensure not to be in DATA state. */
3922 mapping_state (MAP_THUMB
);
3927 as_bad (_("width suffixes are invalid in ARM mode"));
3928 ignore_rest_of_line ();
3934 mapping_state (MAP_ARM
);
3943 if (! emit_insn (& exp
, nbytes
))
3945 ignore_rest_of_line ();
3949 while (*input_line_pointer
++ == ',');
3951 /* Put terminator back into stream. */
3952 input_line_pointer
--;
3953 demand_empty_rest_of_line ();
3956 /* Parse a .rel31 directive. */
3959 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3966 if (*input_line_pointer
== '1')
3967 highbit
= 0x80000000;
3968 else if (*input_line_pointer
!= '0')
3969 as_bad (_("expected 0 or 1"));
3971 input_line_pointer
++;
3972 if (*input_line_pointer
!= ',')
3973 as_bad (_("missing comma"));
3974 input_line_pointer
++;
3976 #ifdef md_flush_pending_output
3977 md_flush_pending_output ();
3980 #ifdef md_cons_align
3984 mapping_state (MAP_DATA
);
3989 md_number_to_chars (p
, highbit
, 4);
3990 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3991 BFD_RELOC_ARM_PREL31
);
3993 demand_empty_rest_of_line ();
3996 /* Directives: AEABI stack-unwind tables. */
3998 /* Parse an unwind_fnstart directive. Simply records the current location. */
4001 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4003 demand_empty_rest_of_line ();
4004 if (unwind
.proc_start
)
4006 as_bad (_("duplicate .fnstart directive"));
4010 /* Mark the start of the function. */
4011 unwind
.proc_start
= expr_build_dot ();
4013 /* Reset the rest of the unwind info. */
4014 unwind
.opcode_count
= 0;
4015 unwind
.table_entry
= NULL
;
4016 unwind
.personality_routine
= NULL
;
4017 unwind
.personality_index
= -1;
4018 unwind
.frame_size
= 0;
4019 unwind
.fp_offset
= 0;
4020 unwind
.fp_reg
= REG_SP
;
4022 unwind
.sp_restored
= 0;
4026 /* Parse a handlerdata directive. Creates the exception handling table entry
4027 for the function. */
4030 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4032 demand_empty_rest_of_line ();
4033 if (!unwind
.proc_start
)
4034 as_bad (MISSING_FNSTART
);
4036 if (unwind
.table_entry
)
4037 as_bad (_("duplicate .handlerdata directive"));
4039 create_unwind_entry (1);
4042 /* Parse an unwind_fnend directive. Generates the index table entry. */
4045 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4050 unsigned int marked_pr_dependency
;
4052 demand_empty_rest_of_line ();
4054 if (!unwind
.proc_start
)
4056 as_bad (_(".fnend directive without .fnstart"));
4060 /* Add eh table entry. */
4061 if (unwind
.table_entry
== NULL
)
4062 val
= create_unwind_entry (0);
4066 /* Add index table entry. This is two words. */
4067 start_unwind_section (unwind
.saved_seg
, 1);
4068 frag_align (2, 0, 0);
4069 record_alignment (now_seg
, 2);
4071 ptr
= frag_more (8);
4073 where
= frag_now_fix () - 8;
4075 /* Self relative offset of the function start. */
4076 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4077 BFD_RELOC_ARM_PREL31
);
4079 /* Indicate dependency on EHABI-defined personality routines to the
4080 linker, if it hasn't been done already. */
4081 marked_pr_dependency
4082 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4083 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4084 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4086 static const char *const name
[] =
4088 "__aeabi_unwind_cpp_pr0",
4089 "__aeabi_unwind_cpp_pr1",
4090 "__aeabi_unwind_cpp_pr2"
4092 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4093 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4094 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4095 |= 1 << unwind
.personality_index
;
4099 /* Inline exception table entry. */
4100 md_number_to_chars (ptr
+ 4, val
, 4);
4102 /* Self relative offset of the table entry. */
4103 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4104 BFD_RELOC_ARM_PREL31
);
4106 /* Restore the original section. */
4107 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4109 unwind
.proc_start
= NULL
;
4113 /* Parse an unwind_cantunwind directive. */
4116 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4118 demand_empty_rest_of_line ();
4119 if (!unwind
.proc_start
)
4120 as_bad (MISSING_FNSTART
);
4122 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4123 as_bad (_("personality routine specified for cantunwind frame"));
4125 unwind
.personality_index
= -2;
4129 /* Parse a personalityindex directive. */
4132 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4136 if (!unwind
.proc_start
)
4137 as_bad (MISSING_FNSTART
);
4139 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4140 as_bad (_("duplicate .personalityindex directive"));
4144 if (exp
.X_op
!= O_constant
4145 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4147 as_bad (_("bad personality routine number"));
4148 ignore_rest_of_line ();
4152 unwind
.personality_index
= exp
.X_add_number
;
4154 demand_empty_rest_of_line ();
4158 /* Parse a personality directive. */
4161 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4165 if (!unwind
.proc_start
)
4166 as_bad (MISSING_FNSTART
);
4168 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4169 as_bad (_("duplicate .personality directive"));
4171 c
= get_symbol_name (& name
);
4172 p
= input_line_pointer
;
4174 ++ input_line_pointer
;
4175 unwind
.personality_routine
= symbol_find_or_make (name
);
4177 demand_empty_rest_of_line ();
4181 /* Parse a directive saving core registers. */
4184 s_arm_unwind_save_core (void)
4190 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4193 as_bad (_("expected register list"));
4194 ignore_rest_of_line ();
4198 demand_empty_rest_of_line ();
4200 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4201 into .unwind_save {..., sp...}. We aren't bothered about the value of
4202 ip because it is clobbered by calls. */
4203 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4204 && (range
& 0x3000) == 0x1000)
4206 unwind
.opcode_count
--;
4207 unwind
.sp_restored
= 0;
4208 range
= (range
| 0x2000) & ~0x1000;
4209 unwind
.pending_offset
= 0;
4215 /* See if we can use the short opcodes. These pop a block of up to 8
4216 registers starting with r4, plus maybe r14. */
4217 for (n
= 0; n
< 8; n
++)
4219 /* Break at the first non-saved register. */
4220 if ((range
& (1 << (n
+ 4))) == 0)
4223 /* See if there are any other bits set. */
4224 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4226 /* Use the long form. */
4227 op
= 0x8000 | ((range
>> 4) & 0xfff);
4228 add_unwind_opcode (op
, 2);
4232 /* Use the short form. */
4234 op
= 0xa8; /* Pop r14. */
4236 op
= 0xa0; /* Do not pop r14. */
4238 add_unwind_opcode (op
, 1);
4245 op
= 0xb100 | (range
& 0xf);
4246 add_unwind_opcode (op
, 2);
4249 /* Record the number of bytes pushed. */
4250 for (n
= 0; n
< 16; n
++)
4252 if (range
& (1 << n
))
4253 unwind
.frame_size
+= 4;
4258 /* Parse a directive saving FPA registers. */
4261 s_arm_unwind_save_fpa (int reg
)
4267 /* Get Number of registers to transfer. */
4268 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4271 exp
.X_op
= O_illegal
;
4273 if (exp
.X_op
!= O_constant
)
4275 as_bad (_("expected , <constant>"));
4276 ignore_rest_of_line ();
4280 num_regs
= exp
.X_add_number
;
4282 if (num_regs
< 1 || num_regs
> 4)
4284 as_bad (_("number of registers must be in the range [1:4]"));
4285 ignore_rest_of_line ();
4289 demand_empty_rest_of_line ();
4294 op
= 0xb4 | (num_regs
- 1);
4295 add_unwind_opcode (op
, 1);
4300 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4301 add_unwind_opcode (op
, 2);
4303 unwind
.frame_size
+= num_regs
* 12;
4307 /* Parse a directive saving VFP registers for ARMv6 and above. */
4310 s_arm_unwind_save_vfp_armv6 (void)
4315 int num_vfpv3_regs
= 0;
4316 int num_regs_below_16
;
4317 bfd_boolean partial_match
;
4319 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4323 as_bad (_("expected register list"));
4324 ignore_rest_of_line ();
4328 demand_empty_rest_of_line ();
4330 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4331 than FSTMX/FLDMX-style ones). */
4333 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4335 num_vfpv3_regs
= count
;
4336 else if (start
+ count
> 16)
4337 num_vfpv3_regs
= start
+ count
- 16;
4339 if (num_vfpv3_regs
> 0)
4341 int start_offset
= start
> 16 ? start
- 16 : 0;
4342 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4343 add_unwind_opcode (op
, 2);
4346 /* Generate opcode for registers numbered in the range 0 .. 15. */
4347 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4348 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4349 if (num_regs_below_16
> 0)
4351 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4352 add_unwind_opcode (op
, 2);
4355 unwind
.frame_size
+= count
* 8;
4359 /* Parse a directive saving VFP registers for pre-ARMv6. */
4362 s_arm_unwind_save_vfp (void)
4367 bfd_boolean partial_match
;
4369 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4373 as_bad (_("expected register list"));
4374 ignore_rest_of_line ();
4378 demand_empty_rest_of_line ();
4383 op
= 0xb8 | (count
- 1);
4384 add_unwind_opcode (op
, 1);
4389 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4390 add_unwind_opcode (op
, 2);
4392 unwind
.frame_size
+= count
* 8 + 4;
4396 /* Parse a directive saving iWMMXt data registers. */
4399 s_arm_unwind_save_mmxwr (void)
4407 if (*input_line_pointer
== '{')
4408 input_line_pointer
++;
4412 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4416 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4421 as_tsktsk (_("register list not in ascending order"));
4424 if (*input_line_pointer
== '-')
4426 input_line_pointer
++;
4427 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4430 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4433 else if (reg
>= hi_reg
)
4435 as_bad (_("bad register range"));
4438 for (; reg
< hi_reg
; reg
++)
4442 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4444 skip_past_char (&input_line_pointer
, '}');
4446 demand_empty_rest_of_line ();
4448 /* Generate any deferred opcodes because we're going to be looking at
4450 flush_pending_unwind ();
4452 for (i
= 0; i
< 16; i
++)
4454 if (mask
& (1 << i
))
4455 unwind
.frame_size
+= 8;
4458 /* Attempt to combine with a previous opcode. We do this because gcc
4459 likes to output separate unwind directives for a single block of
4461 if (unwind
.opcode_count
> 0)
4463 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4464 if ((i
& 0xf8) == 0xc0)
4467 /* Only merge if the blocks are contiguous. */
4470 if ((mask
& 0xfe00) == (1 << 9))
4472 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4473 unwind
.opcode_count
--;
4476 else if (i
== 6 && unwind
.opcode_count
>= 2)
4478 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4482 op
= 0xffff << (reg
- 1);
4484 && ((mask
& op
) == (1u << (reg
- 1))))
4486 op
= (1 << (reg
+ i
+ 1)) - 1;
4487 op
&= ~((1 << reg
) - 1);
4489 unwind
.opcode_count
-= 2;
4496 /* We want to generate opcodes in the order the registers have been
4497 saved, ie. descending order. */
4498 for (reg
= 15; reg
>= -1; reg
--)
4500 /* Save registers in blocks. */
4502 || !(mask
& (1 << reg
)))
4504 /* We found an unsaved reg. Generate opcodes to save the
4511 op
= 0xc0 | (hi_reg
- 10);
4512 add_unwind_opcode (op
, 1);
4517 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4518 add_unwind_opcode (op
, 2);
4527 ignore_rest_of_line ();
4531 s_arm_unwind_save_mmxwcg (void)
4538 if (*input_line_pointer
== '{')
4539 input_line_pointer
++;
4541 skip_whitespace (input_line_pointer
);
4545 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4549 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4555 as_tsktsk (_("register list not in ascending order"));
4558 if (*input_line_pointer
== '-')
4560 input_line_pointer
++;
4561 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4564 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4567 else if (reg
>= hi_reg
)
4569 as_bad (_("bad register range"));
4572 for (; reg
< hi_reg
; reg
++)
4576 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4578 skip_past_char (&input_line_pointer
, '}');
4580 demand_empty_rest_of_line ();
4582 /* Generate any deferred opcodes because we're going to be looking at
4584 flush_pending_unwind ();
4586 for (reg
= 0; reg
< 16; reg
++)
4588 if (mask
& (1 << reg
))
4589 unwind
.frame_size
+= 4;
4592 add_unwind_opcode (op
, 2);
4595 ignore_rest_of_line ();
4599 /* Parse an unwind_save directive.
4600 If the argument is non-zero, this is a .vsave directive. */
4603 s_arm_unwind_save (int arch_v6
)
4606 struct reg_entry
*reg
;
4607 bfd_boolean had_brace
= FALSE
;
4609 if (!unwind
.proc_start
)
4610 as_bad (MISSING_FNSTART
);
4612 /* Figure out what sort of save we have. */
4613 peek
= input_line_pointer
;
4621 reg
= arm_reg_parse_multi (&peek
);
4625 as_bad (_("register expected"));
4626 ignore_rest_of_line ();
4635 as_bad (_("FPA .unwind_save does not take a register list"));
4636 ignore_rest_of_line ();
4639 input_line_pointer
= peek
;
4640 s_arm_unwind_save_fpa (reg
->number
);
4644 s_arm_unwind_save_core ();
4649 s_arm_unwind_save_vfp_armv6 ();
4651 s_arm_unwind_save_vfp ();
4654 case REG_TYPE_MMXWR
:
4655 s_arm_unwind_save_mmxwr ();
4658 case REG_TYPE_MMXWCG
:
4659 s_arm_unwind_save_mmxwcg ();
4663 as_bad (_(".unwind_save does not support this kind of register"));
4664 ignore_rest_of_line ();
4669 /* Parse an unwind_movsp directive. */
4672 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4678 if (!unwind
.proc_start
)
4679 as_bad (MISSING_FNSTART
);
4681 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4684 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4685 ignore_rest_of_line ();
4689 /* Optional constant. */
4690 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4692 if (immediate_for_directive (&offset
) == FAIL
)
4698 demand_empty_rest_of_line ();
4700 if (reg
== REG_SP
|| reg
== REG_PC
)
4702 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4706 if (unwind
.fp_reg
!= REG_SP
)
4707 as_bad (_("unexpected .unwind_movsp directive"));
4709 /* Generate opcode to restore the value. */
4711 add_unwind_opcode (op
, 1);
4713 /* Record the information for later. */
4714 unwind
.fp_reg
= reg
;
4715 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4716 unwind
.sp_restored
= 1;
4719 /* Parse an unwind_pad directive. */
4722 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4726 if (!unwind
.proc_start
)
4727 as_bad (MISSING_FNSTART
);
4729 if (immediate_for_directive (&offset
) == FAIL
)
4734 as_bad (_("stack increment must be multiple of 4"));
4735 ignore_rest_of_line ();
4739 /* Don't generate any opcodes, just record the details for later. */
4740 unwind
.frame_size
+= offset
;
4741 unwind
.pending_offset
+= offset
;
4743 demand_empty_rest_of_line ();
4746 /* Parse an unwind_setfp directive. */
4749 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4755 if (!unwind
.proc_start
)
4756 as_bad (MISSING_FNSTART
);
4758 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4759 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4762 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4764 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4766 as_bad (_("expected <reg>, <reg>"));
4767 ignore_rest_of_line ();
4771 /* Optional constant. */
4772 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4774 if (immediate_for_directive (&offset
) == FAIL
)
4780 demand_empty_rest_of_line ();
4782 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4784 as_bad (_("register must be either sp or set by a previous"
4785 "unwind_movsp directive"));
4789 /* Don't generate any opcodes, just record the information for later. */
4790 unwind
.fp_reg
= fp_reg
;
4792 if (sp_reg
== REG_SP
)
4793 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4795 unwind
.fp_offset
-= offset
;
4798 /* Parse an unwind_raw directive. */
4801 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4804 /* This is an arbitrary limit. */
4805 unsigned char op
[16];
4808 if (!unwind
.proc_start
)
4809 as_bad (MISSING_FNSTART
);
4812 if (exp
.X_op
== O_constant
4813 && skip_past_comma (&input_line_pointer
) != FAIL
)
4815 unwind
.frame_size
+= exp
.X_add_number
;
4819 exp
.X_op
= O_illegal
;
4821 if (exp
.X_op
!= O_constant
)
4823 as_bad (_("expected <offset>, <opcode>"));
4824 ignore_rest_of_line ();
4830 /* Parse the opcode. */
4835 as_bad (_("unwind opcode too long"));
4836 ignore_rest_of_line ();
4838 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4840 as_bad (_("invalid unwind opcode"));
4841 ignore_rest_of_line ();
4844 op
[count
++] = exp
.X_add_number
;
4846 /* Parse the next byte. */
4847 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4853 /* Add the opcode bytes in reverse order. */
4855 add_unwind_opcode (op
[count
], 1);
4857 demand_empty_rest_of_line ();
4861 /* Parse a .eabi_attribute directive. */
4864 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4866 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4868 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4869 attributes_set_explicitly
[tag
] = 1;
4872 /* Emit a tls fix for the symbol. */
4875 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4879 #ifdef md_flush_pending_output
4880 md_flush_pending_output ();
4883 #ifdef md_cons_align
4887 /* Since we're just labelling the code, there's no need to define a
4890 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4891 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4892 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4893 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4895 #endif /* OBJ_ELF */
4897 static void s_arm_arch (int);
4898 static void s_arm_object_arch (int);
4899 static void s_arm_cpu (int);
4900 static void s_arm_fpu (int);
4901 static void s_arm_arch_extension (int);
4906 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4913 if (exp
.X_op
== O_symbol
)
4914 exp
.X_op
= O_secrel
;
4916 emit_expr (&exp
, 4);
4918 while (*input_line_pointer
++ == ',');
4920 input_line_pointer
--;
4921 demand_empty_rest_of_line ();
4925 /* This table describes all the machine specific pseudo-ops the assembler
4926 has to support. The fields are:
4927 pseudo-op name without dot
4928 function to call to execute this pseudo-op
4929 Integer arg to pass to the function. */
4931 const pseudo_typeS md_pseudo_table
[] =
4933 /* Never called because '.req' does not start a line. */
4934 { "req", s_req
, 0 },
4935 /* Following two are likewise never called. */
4938 { "unreq", s_unreq
, 0 },
4939 { "bss", s_bss
, 0 },
4940 { "align", s_align_ptwo
, 2 },
4941 { "arm", s_arm
, 0 },
4942 { "thumb", s_thumb
, 0 },
4943 { "code", s_code
, 0 },
4944 { "force_thumb", s_force_thumb
, 0 },
4945 { "thumb_func", s_thumb_func
, 0 },
4946 { "thumb_set", s_thumb_set
, 0 },
4947 { "even", s_even
, 0 },
4948 { "ltorg", s_ltorg
, 0 },
4949 { "pool", s_ltorg
, 0 },
4950 { "syntax", s_syntax
, 0 },
4951 { "cpu", s_arm_cpu
, 0 },
4952 { "arch", s_arm_arch
, 0 },
4953 { "object_arch", s_arm_object_arch
, 0 },
4954 { "fpu", s_arm_fpu
, 0 },
4955 { "arch_extension", s_arm_arch_extension
, 0 },
4957 { "word", s_arm_elf_cons
, 4 },
4958 { "long", s_arm_elf_cons
, 4 },
4959 { "inst.n", s_arm_elf_inst
, 2 },
4960 { "inst.w", s_arm_elf_inst
, 4 },
4961 { "inst", s_arm_elf_inst
, 0 },
4962 { "rel31", s_arm_rel31
, 0 },
4963 { "fnstart", s_arm_unwind_fnstart
, 0 },
4964 { "fnend", s_arm_unwind_fnend
, 0 },
4965 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4966 { "personality", s_arm_unwind_personality
, 0 },
4967 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4968 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4969 { "save", s_arm_unwind_save
, 0 },
4970 { "vsave", s_arm_unwind_save
, 1 },
4971 { "movsp", s_arm_unwind_movsp
, 0 },
4972 { "pad", s_arm_unwind_pad
, 0 },
4973 { "setfp", s_arm_unwind_setfp
, 0 },
4974 { "unwind_raw", s_arm_unwind_raw
, 0 },
4975 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4976 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4980 /* These are used for dwarf. */
4984 /* These are used for dwarf2. */
4985 { "file", dwarf2_directive_file
, 0 },
4986 { "loc", dwarf2_directive_loc
, 0 },
4987 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4989 { "extend", float_cons
, 'x' },
4990 { "ldouble", float_cons
, 'x' },
4991 { "packed", float_cons
, 'p' },
4993 {"secrel32", pe_directive_secrel
, 0},
4996 /* These are for compatibility with CodeComposer Studio. */
4997 {"ref", s_ccs_ref
, 0},
4998 {"def", s_ccs_def
, 0},
4999 {"asmfunc", s_ccs_asmfunc
, 0},
5000 {"endasmfunc", s_ccs_endasmfunc
, 0},
5005 /* Parser functions used exclusively in instruction operands. */
5007 /* Generic immediate-value read function for use in insn parsing.
5008 STR points to the beginning of the immediate (the leading #);
5009 VAL receives the value; if the value is outside [MIN, MAX]
5010 issue an error. PREFIX_OPT is true if the immediate prefix is
5014 parse_immediate (char **str
, int *val
, int min
, int max
,
5015 bfd_boolean prefix_opt
)
5019 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5020 if (exp
.X_op
!= O_constant
)
5022 inst
.error
= _("constant expression required");
5026 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5028 inst
.error
= _("immediate value out of range");
5032 *val
= exp
.X_add_number
;
5036 /* Less-generic immediate-value read function with the possibility of loading a
5037 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5038 instructions. Puts the result directly in inst.operands[i]. */
5041 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5042 bfd_boolean allow_symbol_p
)
5045 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5048 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5050 if (exp_p
->X_op
== O_constant
)
5052 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5053 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5054 O_constant. We have to be careful not to break compilation for
5055 32-bit X_add_number, though. */
5056 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5058 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5059 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5061 inst
.operands
[i
].regisimm
= 1;
5064 else if (exp_p
->X_op
== O_big
5065 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5067 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5069 /* Bignums have their least significant bits in
5070 generic_bignum[0]. Make sure we put 32 bits in imm and
5071 32 bits in reg, in a (hopefully) portable way. */
5072 gas_assert (parts
!= 0);
5074 /* Make sure that the number is not too big.
5075 PR 11972: Bignums can now be sign-extended to the
5076 size of a .octa so check that the out of range bits
5077 are all zero or all one. */
5078 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5080 LITTLENUM_TYPE m
= -1;
5082 if (generic_bignum
[parts
* 2] != 0
5083 && generic_bignum
[parts
* 2] != m
)
5086 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5087 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5091 inst
.operands
[i
].imm
= 0;
5092 for (j
= 0; j
< parts
; j
++, idx
++)
5093 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
5094 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5095 inst
.operands
[i
].reg
= 0;
5096 for (j
= 0; j
< parts
; j
++, idx
++)
5097 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
5098 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5099 inst
.operands
[i
].regisimm
= 1;
5101 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5109 /* Returns the pseudo-register number of an FPA immediate constant,
5110 or FAIL if there isn't a valid constant here. */
5113 parse_fpa_immediate (char ** str
)
5115 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5121 /* First try and match exact strings, this is to guarantee
5122 that some formats will work even for cross assembly. */
5124 for (i
= 0; fp_const
[i
]; i
++)
5126 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5130 *str
+= strlen (fp_const
[i
]);
5131 if (is_end_of_line
[(unsigned char) **str
])
5137 /* Just because we didn't get a match doesn't mean that the constant
5138 isn't valid, just that it is in a format that we don't
5139 automatically recognize. Try parsing it with the standard
5140 expression routines. */
5142 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5144 /* Look for a raw floating point number. */
5145 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5146 && is_end_of_line
[(unsigned char) *save_in
])
5148 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5150 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5152 if (words
[j
] != fp_values
[i
][j
])
5156 if (j
== MAX_LITTLENUMS
)
5164 /* Try and parse a more complex expression, this will probably fail
5165 unless the code uses a floating point prefix (eg "0f"). */
5166 save_in
= input_line_pointer
;
5167 input_line_pointer
= *str
;
5168 if (expression (&exp
) == absolute_section
5169 && exp
.X_op
== O_big
5170 && exp
.X_add_number
< 0)
5172 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5174 #define X_PRECISION 5
5175 #define E_PRECISION 15L
5176 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5178 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5180 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5182 if (words
[j
] != fp_values
[i
][j
])
5186 if (j
== MAX_LITTLENUMS
)
5188 *str
= input_line_pointer
;
5189 input_line_pointer
= save_in
;
5196 *str
= input_line_pointer
;
5197 input_line_pointer
= save_in
;
5198 inst
.error
= _("invalid FPA immediate expression");
5202 /* Returns 1 if a number has "quarter-precision" float format
5203 0baBbbbbbc defgh000 00000000 00000000. */
5206 is_quarter_float (unsigned imm
)
5208 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5209 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5213 /* Detect the presence of a floating point or integer zero constant,
5217 parse_ifimm_zero (char **in
)
5221 if (!is_immediate_prefix (**in
))
5223 /* In unified syntax, all prefixes are optional. */
5224 if (!unified_syntax
)
5230 /* Accept #0x0 as a synonym for #0. */
5231 if (strncmp (*in
, "0x", 2) == 0)
5234 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5239 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5240 &generic_floating_point_number
);
5243 && generic_floating_point_number
.sign
== '+'
5244 && (generic_floating_point_number
.low
5245 > generic_floating_point_number
.leader
))
5251 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5252 0baBbbbbbc defgh000 00000000 00000000.
5253 The zero and minus-zero cases need special handling, since they can't be
5254 encoded in the "quarter-precision" float format, but can nonetheless be
5255 loaded as integer constants. */
5258 parse_qfloat_immediate (char **ccp
, int *immed
)
5262 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5263 int found_fpchar
= 0;
5265 skip_past_char (&str
, '#');
5267 /* We must not accidentally parse an integer as a floating-point number. Make
5268 sure that the value we parse is not an integer by checking for special
5269 characters '.' or 'e'.
5270 FIXME: This is a horrible hack, but doing better is tricky because type
5271 information isn't in a very usable state at parse time. */
5273 skip_whitespace (fpnum
);
5275 if (strncmp (fpnum
, "0x", 2) == 0)
5279 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5280 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5290 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5292 unsigned fpword
= 0;
5295 /* Our FP word must be 32 bits (single-precision FP). */
5296 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5298 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5302 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5315 /* Shift operands. */
5318 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5321 struct asm_shift_name
5324 enum shift_kind kind
;
5327 /* Third argument to parse_shift. */
5328 enum parse_shift_mode
5330 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5331 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5332 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5333 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5334 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5335 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5338 /* Parse a <shift> specifier on an ARM data processing instruction.
5339 This has three forms:
5341 (LSL|LSR|ASL|ASR|ROR) Rs
5342 (LSL|LSR|ASL|ASR|ROR) #imm
5345 Note that ASL is assimilated to LSL in the instruction encoding, and
5346 RRX to ROR #0 (which cannot be written as such). */
5349 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5351 const struct asm_shift_name
*shift_name
;
5352 enum shift_kind shift
;
5357 for (p
= *str
; ISALPHA (*p
); p
++)
5362 inst
.error
= _("shift expression expected");
5366 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5369 if (shift_name
== NULL
)
5371 inst
.error
= _("shift expression expected");
5375 shift
= shift_name
->kind
;
5379 case NO_SHIFT_RESTRICT
:
5380 case SHIFT_IMMEDIATE
:
5381 if (shift
== SHIFT_UXTW
)
5383 inst
.error
= _("'UXTW' not allowed here");
5388 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5389 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5391 inst
.error
= _("'LSL' or 'ASR' required");
5396 case SHIFT_LSL_IMMEDIATE
:
5397 if (shift
!= SHIFT_LSL
)
5399 inst
.error
= _("'LSL' required");
5404 case SHIFT_ASR_IMMEDIATE
:
5405 if (shift
!= SHIFT_ASR
)
5407 inst
.error
= _("'ASR' required");
5411 case SHIFT_UXTW_IMMEDIATE
:
5412 if (shift
!= SHIFT_UXTW
)
5414 inst
.error
= _("'UXTW' required");
5422 if (shift
!= SHIFT_RRX
)
5424 /* Whitespace can appear here if the next thing is a bare digit. */
5425 skip_whitespace (p
);
5427 if (mode
== NO_SHIFT_RESTRICT
5428 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5430 inst
.operands
[i
].imm
= reg
;
5431 inst
.operands
[i
].immisreg
= 1;
5433 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5436 inst
.operands
[i
].shift_kind
= shift
;
5437 inst
.operands
[i
].shifted
= 1;
5442 /* Parse a <shifter_operand> for an ARM data processing instruction:
5445 #<immediate>, <rotate>
5449 where <shift> is defined by parse_shift above, and <rotate> is a
5450 multiple of 2 between 0 and 30. Validation of immediate operands
5451 is deferred to md_apply_fix. */
5454 parse_shifter_operand (char **str
, int i
)
5459 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5461 inst
.operands
[i
].reg
= value
;
5462 inst
.operands
[i
].isreg
= 1;
5464 /* parse_shift will override this if appropriate */
5465 inst
.relocs
[0].exp
.X_op
= O_constant
;
5466 inst
.relocs
[0].exp
.X_add_number
= 0;
5468 if (skip_past_comma (str
) == FAIL
)
5471 /* Shift operation on register. */
5472 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5475 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5478 if (skip_past_comma (str
) == SUCCESS
)
5480 /* #x, y -- ie explicit rotation by Y. */
5481 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5484 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5486 inst
.error
= _("constant expression expected");
5490 value
= exp
.X_add_number
;
5491 if (value
< 0 || value
> 30 || value
% 2 != 0)
5493 inst
.error
= _("invalid rotation");
5496 if (inst
.relocs
[0].exp
.X_add_number
< 0
5497 || inst
.relocs
[0].exp
.X_add_number
> 255)
5499 inst
.error
= _("invalid constant");
5503 /* Encode as specified. */
5504 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5508 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5509 inst
.relocs
[0].pc_rel
= 0;
5513 /* Group relocation information. Each entry in the table contains the
5514 textual name of the relocation as may appear in assembler source
5515 and must end with a colon.
5516 Along with this textual name are the relocation codes to be used if
5517 the corresponding instruction is an ALU instruction (ADD or SUB only),
5518 an LDR, an LDRS, or an LDC. */
5520 struct group_reloc_table_entry
5531 /* Varieties of non-ALU group relocation. */
5539 static struct group_reloc_table_entry group_reloc_table
[] =
5540 { /* Program counter relative: */
5542 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5547 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5548 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5549 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5550 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5552 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5557 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5558 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5559 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5560 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5562 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5563 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5564 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5565 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5566 /* Section base relative */
5568 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5573 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5574 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5575 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5576 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5578 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5583 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5584 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5585 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5586 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5588 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5589 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5590 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5591 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5592 /* Absolute thumb alu relocations. */
5594 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5599 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5604 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5609 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5614 /* Given the address of a pointer pointing to the textual name of a group
5615 relocation as may appear in assembler source, attempt to find its details
5616 in group_reloc_table. The pointer will be updated to the character after
5617 the trailing colon. On failure, FAIL will be returned; SUCCESS
5618 otherwise. On success, *entry will be updated to point at the relevant
5619 group_reloc_table entry. */
5622 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5625 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5627 int length
= strlen (group_reloc_table
[i
].name
);
5629 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5630 && (*str
)[length
] == ':')
5632 *out
= &group_reloc_table
[i
];
5633 *str
+= (length
+ 1);
5641 /* Parse a <shifter_operand> for an ARM data processing instruction
5642 (as for parse_shifter_operand) where group relocations are allowed:
5645 #<immediate>, <rotate>
5646 #:<group_reloc>:<expression>
5650 where <group_reloc> is one of the strings defined in group_reloc_table.
5651 The hashes are optional.
5653 Everything else is as for parse_shifter_operand. */
5655 static parse_operand_result
5656 parse_shifter_operand_group_reloc (char **str
, int i
)
5658 /* Determine if we have the sequence of characters #: or just :
5659 coming next. If we do, then we check for a group relocation.
5660 If we don't, punt the whole lot to parse_shifter_operand. */
5662 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5663 || (*str
)[0] == ':')
5665 struct group_reloc_table_entry
*entry
;
5667 if ((*str
)[0] == '#')
5672 /* Try to parse a group relocation. Anything else is an error. */
5673 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5675 inst
.error
= _("unknown group relocation");
5676 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5679 /* We now have the group relocation table entry corresponding to
5680 the name in the assembler source. Next, we parse the expression. */
5681 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5682 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5684 /* Record the relocation type (always the ALU variant here). */
5685 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5686 gas_assert (inst
.relocs
[0].type
!= 0);
5688 return PARSE_OPERAND_SUCCESS
;
5691 return parse_shifter_operand (str
, i
) == SUCCESS
5692 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5694 /* Never reached. */
5697 /* Parse a Neon alignment expression. Information is written to
5698 inst.operands[i]. We assume the initial ':' has been skipped.
5700 align .imm = align << 8, .immisalign=1, .preind=0 */
5701 static parse_operand_result
5702 parse_neon_alignment (char **str
, int i
)
5707 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5709 if (exp
.X_op
!= O_constant
)
5711 inst
.error
= _("alignment must be constant");
5712 return PARSE_OPERAND_FAIL
;
5715 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5716 inst
.operands
[i
].immisalign
= 1;
5717 /* Alignments are not pre-indexes. */
5718 inst
.operands
[i
].preind
= 0;
5721 return PARSE_OPERAND_SUCCESS
;
5724 /* Parse all forms of an ARM address expression. Information is written
5725 to inst.operands[i] and/or inst.relocs[0].
5727 Preindexed addressing (.preind=1):
5729 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5730 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5731 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5732 .shift_kind=shift .relocs[0].exp=shift_imm
5734 These three may have a trailing ! which causes .writeback to be set also.
5736 Postindexed addressing (.postind=1, .writeback=1):
5738 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5739 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5740 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5741 .shift_kind=shift .relocs[0].exp=shift_imm
5743 Unindexed addressing (.preind=0, .postind=0):
5745 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5749 [Rn]{!} shorthand for [Rn,#0]{!}
5750 =immediate .isreg=0 .relocs[0].exp=immediate
5751 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5753 It is the caller's responsibility to check for addressing modes not
5754 supported by the instruction, and to set inst.relocs[0].type. */
5756 static parse_operand_result
5757 parse_address_main (char **str
, int i
, int group_relocations
,
5758 group_reloc_type group_type
)
5763 if (skip_past_char (&p
, '[') == FAIL
)
5765 if (skip_past_char (&p
, '=') == FAIL
)
5767 /* Bare address - translate to PC-relative offset. */
5768 inst
.relocs
[0].pc_rel
= 1;
5769 inst
.operands
[i
].reg
= REG_PC
;
5770 inst
.operands
[i
].isreg
= 1;
5771 inst
.operands
[i
].preind
= 1;
5773 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5774 return PARSE_OPERAND_FAIL
;
5776 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5777 /*allow_symbol_p=*/TRUE
))
5778 return PARSE_OPERAND_FAIL
;
5781 return PARSE_OPERAND_SUCCESS
;
5784 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5785 skip_whitespace (p
);
5787 if (group_type
== GROUP_MVE
)
5789 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5790 struct neon_type_el et
;
5791 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5793 inst
.operands
[i
].isquad
= 1;
5795 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5797 inst
.error
= BAD_ADDR_MODE
;
5798 return PARSE_OPERAND_FAIL
;
5801 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5803 if (group_type
== GROUP_MVE
)
5804 inst
.error
= BAD_ADDR_MODE
;
5806 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5807 return PARSE_OPERAND_FAIL
;
5809 inst
.operands
[i
].reg
= reg
;
5810 inst
.operands
[i
].isreg
= 1;
5812 if (skip_past_comma (&p
) == SUCCESS
)
5814 inst
.operands
[i
].preind
= 1;
5817 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5819 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5820 struct neon_type_el et
;
5821 if (group_type
== GROUP_MVE
5822 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5824 inst
.operands
[i
].immisreg
= 2;
5825 inst
.operands
[i
].imm
= reg
;
5827 if (skip_past_comma (&p
) == SUCCESS
)
5829 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
5831 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
5832 inst
.relocs
[0].exp
.X_add_number
= 0;
5835 return PARSE_OPERAND_FAIL
;
5838 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5840 inst
.operands
[i
].imm
= reg
;
5841 inst
.operands
[i
].immisreg
= 1;
5843 if (skip_past_comma (&p
) == SUCCESS
)
5844 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5845 return PARSE_OPERAND_FAIL
;
5847 else if (skip_past_char (&p
, ':') == SUCCESS
)
5849 /* FIXME: '@' should be used here, but it's filtered out by generic
5850 code before we get to see it here. This may be subject to
5852 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5854 if (result
!= PARSE_OPERAND_SUCCESS
)
5859 if (inst
.operands
[i
].negative
)
5861 inst
.operands
[i
].negative
= 0;
5865 if (group_relocations
5866 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5868 struct group_reloc_table_entry
*entry
;
5870 /* Skip over the #: or : sequence. */
5876 /* Try to parse a group relocation. Anything else is an
5878 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5880 inst
.error
= _("unknown group relocation");
5881 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5884 /* We now have the group relocation table entry corresponding to
5885 the name in the assembler source. Next, we parse the
5887 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5888 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5890 /* Record the relocation type. */
5895 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
5900 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5905 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
5912 if (inst
.relocs
[0].type
== 0)
5914 inst
.error
= _("this group relocation is not allowed on this instruction");
5915 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5922 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5923 return PARSE_OPERAND_FAIL
;
5924 /* If the offset is 0, find out if it's a +0 or -0. */
5925 if (inst
.relocs
[0].exp
.X_op
== O_constant
5926 && inst
.relocs
[0].exp
.X_add_number
== 0)
5928 skip_whitespace (q
);
5932 skip_whitespace (q
);
5935 inst
.operands
[i
].negative
= 1;
5940 else if (skip_past_char (&p
, ':') == SUCCESS
)
5942 /* FIXME: '@' should be used here, but it's filtered out by generic code
5943 before we get to see it here. This may be subject to change. */
5944 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5946 if (result
!= PARSE_OPERAND_SUCCESS
)
5950 if (skip_past_char (&p
, ']') == FAIL
)
5952 inst
.error
= _("']' expected");
5953 return PARSE_OPERAND_FAIL
;
5956 if (skip_past_char (&p
, '!') == SUCCESS
)
5957 inst
.operands
[i
].writeback
= 1;
5959 else if (skip_past_comma (&p
) == SUCCESS
)
5961 if (skip_past_char (&p
, '{') == SUCCESS
)
5963 /* [Rn], {expr} - unindexed, with option */
5964 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5965 0, 255, TRUE
) == FAIL
)
5966 return PARSE_OPERAND_FAIL
;
5968 if (skip_past_char (&p
, '}') == FAIL
)
5970 inst
.error
= _("'}' expected at end of 'option' field");
5971 return PARSE_OPERAND_FAIL
;
5973 if (inst
.operands
[i
].preind
)
5975 inst
.error
= _("cannot combine index with option");
5976 return PARSE_OPERAND_FAIL
;
5979 return PARSE_OPERAND_SUCCESS
;
5983 inst
.operands
[i
].postind
= 1;
5984 inst
.operands
[i
].writeback
= 1;
5986 if (inst
.operands
[i
].preind
)
5988 inst
.error
= _("cannot combine pre- and post-indexing");
5989 return PARSE_OPERAND_FAIL
;
5993 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5995 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5996 struct neon_type_el et
;
5997 if (group_type
== GROUP_MVE
5998 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6000 inst
.operands
[i
].immisreg
= 2;
6001 inst
.operands
[i
].imm
= reg
;
6003 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6005 /* We might be using the immediate for alignment already. If we
6006 are, OR the register number into the low-order bits. */
6007 if (inst
.operands
[i
].immisalign
)
6008 inst
.operands
[i
].imm
|= reg
;
6010 inst
.operands
[i
].imm
= reg
;
6011 inst
.operands
[i
].immisreg
= 1;
6013 if (skip_past_comma (&p
) == SUCCESS
)
6014 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6015 return PARSE_OPERAND_FAIL
;
6021 if (inst
.operands
[i
].negative
)
6023 inst
.operands
[i
].negative
= 0;
6026 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6027 return PARSE_OPERAND_FAIL
;
6028 /* If the offset is 0, find out if it's a +0 or -0. */
6029 if (inst
.relocs
[0].exp
.X_op
== O_constant
6030 && inst
.relocs
[0].exp
.X_add_number
== 0)
6032 skip_whitespace (q
);
6036 skip_whitespace (q
);
6039 inst
.operands
[i
].negative
= 1;
6045 /* If at this point neither .preind nor .postind is set, we have a
6046 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6047 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6049 inst
.operands
[i
].preind
= 1;
6050 inst
.relocs
[0].exp
.X_op
= O_constant
;
6051 inst
.relocs
[0].exp
.X_add_number
= 0;
6054 return PARSE_OPERAND_SUCCESS
;
6058 parse_address (char **str
, int i
)
6060 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6064 static parse_operand_result
6065 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6067 return parse_address_main (str
, i
, 1, type
);
6070 /* Parse an operand for a MOVW or MOVT instruction. */
6072 parse_half (char **str
)
6077 skip_past_char (&p
, '#');
6078 if (strncasecmp (p
, ":lower16:", 9) == 0)
6079 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6080 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6081 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6083 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6086 skip_whitespace (p
);
6089 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6092 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6094 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6096 inst
.error
= _("constant expression expected");
6099 if (inst
.relocs
[0].exp
.X_add_number
< 0
6100 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6102 inst
.error
= _("immediate value out of range");
6110 /* Miscellaneous. */
6112 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6113 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6115 parse_psr (char **str
, bfd_boolean lhs
)
6118 unsigned long psr_field
;
6119 const struct asm_psr
*psr
;
6121 bfd_boolean is_apsr
= FALSE
;
6122 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6124 /* PR gas/12698: If the user has specified -march=all then m_profile will
6125 be TRUE, but we want to ignore it in this case as we are building for any
6126 CPU type, including non-m variants. */
6127 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6130 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6131 feature for ease of use and backwards compatibility. */
6133 if (strncasecmp (p
, "SPSR", 4) == 0)
6136 goto unsupported_psr
;
6138 psr_field
= SPSR_BIT
;
6140 else if (strncasecmp (p
, "CPSR", 4) == 0)
6143 goto unsupported_psr
;
6147 else if (strncasecmp (p
, "APSR", 4) == 0)
6149 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6150 and ARMv7-R architecture CPUs. */
6159 while (ISALNUM (*p
) || *p
== '_');
6161 if (strncasecmp (start
, "iapsr", 5) == 0
6162 || strncasecmp (start
, "eapsr", 5) == 0
6163 || strncasecmp (start
, "xpsr", 4) == 0
6164 || strncasecmp (start
, "psr", 3) == 0)
6165 p
= start
+ strcspn (start
, "rR") + 1;
6167 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
6173 /* If APSR is being written, a bitfield may be specified. Note that
6174 APSR itself is handled above. */
6175 if (psr
->field
<= 3)
6177 psr_field
= psr
->field
;
6183 /* M-profile MSR instructions have the mask field set to "10", except
6184 *PSR variants which modify APSR, which may use a different mask (and
6185 have been handled already). Do that by setting the PSR_f field
6187 return psr
->field
| (lhs
? PSR_f
: 0);
6190 goto unsupported_psr
;
6196 /* A suffix follows. */
6202 while (ISALNUM (*p
) || *p
== '_');
6206 /* APSR uses a notation for bits, rather than fields. */
6207 unsigned int nzcvq_bits
= 0;
6208 unsigned int g_bit
= 0;
6211 for (bit
= start
; bit
!= p
; bit
++)
6213 switch (TOLOWER (*bit
))
6216 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6220 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6224 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6228 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6232 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6236 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6240 inst
.error
= _("unexpected bit specified after APSR");
6245 if (nzcvq_bits
== 0x1f)
6250 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6252 inst
.error
= _("selected processor does not "
6253 "support DSP extension");
6260 if ((nzcvq_bits
& 0x20) != 0
6261 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6262 || (g_bit
& 0x2) != 0)
6264 inst
.error
= _("bad bitmask specified after APSR");
6270 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6275 psr_field
|= psr
->field
;
6281 goto error
; /* Garbage after "[CS]PSR". */
6283 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6284 is deprecated, but allow it anyway. */
6288 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6291 else if (!m_profile
)
6292 /* These bits are never right for M-profile devices: don't set them
6293 (only code paths which read/write APSR reach here). */
6294 psr_field
|= (PSR_c
| PSR_f
);
6300 inst
.error
= _("selected processor does not support requested special "
6301 "purpose register");
6305 inst
.error
= _("flag for {c}psr instruction expected");
6310 parse_sys_vldr_vstr (char **str
)
6319 {"FPSCR", 0x1, 0x0},
6320 {"FPSCR_nzcvqc", 0x2, 0x0},
6323 {"FPCXTNS", 0x6, 0x1},
6324 {"FPCXTS", 0x7, 0x1}
6326 char *op_end
= strchr (*str
, ',');
6327 size_t op_strlen
= op_end
- *str
;
6329 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6331 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6333 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6342 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6343 value suitable for splatting into the AIF field of the instruction. */
6346 parse_cps_flags (char **str
)
6355 case '\0': case ',':
6358 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6359 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6360 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6363 inst
.error
= _("unrecognized CPS flag");
6368 if (saw_a_flag
== 0)
6370 inst
.error
= _("missing CPS flags");
6378 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6379 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6382 parse_endian_specifier (char **str
)
6387 if (strncasecmp (s
, "BE", 2))
6389 else if (strncasecmp (s
, "LE", 2))
6393 inst
.error
= _("valid endian specifiers are be or le");
6397 if (ISALNUM (s
[2]) || s
[2] == '_')
6399 inst
.error
= _("valid endian specifiers are be or le");
6404 return little_endian
;
6407 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6408 value suitable for poking into the rotate field of an sxt or sxta
6409 instruction, or FAIL on error. */
6412 parse_ror (char **str
)
6417 if (strncasecmp (s
, "ROR", 3) == 0)
6421 inst
.error
= _("missing rotation field after comma");
6425 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6430 case 0: *str
= s
; return 0x0;
6431 case 8: *str
= s
; return 0x1;
6432 case 16: *str
= s
; return 0x2;
6433 case 24: *str
= s
; return 0x3;
6436 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6441 /* Parse a conditional code (from conds[] below). The value returned is in the
6442 range 0 .. 14, or FAIL. */
6444 parse_cond (char **str
)
6447 const struct asm_cond
*c
;
6449 /* Condition codes are always 2 characters, so matching up to
6450 3 characters is sufficient. */
6455 while (ISALPHA (*q
) && n
< 3)
6457 cond
[n
] = TOLOWER (*q
);
6462 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6465 inst
.error
= _("condition required");
6473 /* Parse an option for a barrier instruction. Returns the encoding for the
6476 parse_barrier (char **str
)
6479 const struct asm_barrier_opt
*o
;
6482 while (ISALPHA (*q
))
6485 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6490 if (!mark_feature_used (&o
->arch
))
6497 /* Parse the operands of a table branch instruction. Similar to a memory
6500 parse_tb (char **str
)
6505 if (skip_past_char (&p
, '[') == FAIL
)
6507 inst
.error
= _("'[' expected");
6511 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6513 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6516 inst
.operands
[0].reg
= reg
;
6518 if (skip_past_comma (&p
) == FAIL
)
6520 inst
.error
= _("',' expected");
6524 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6526 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6529 inst
.operands
[0].imm
= reg
;
6531 if (skip_past_comma (&p
) == SUCCESS
)
6533 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6535 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6537 inst
.error
= _("invalid shift");
6540 inst
.operands
[0].shifted
= 1;
6543 if (skip_past_char (&p
, ']') == FAIL
)
6545 inst
.error
= _("']' expected");
6552 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6553 information on the types the operands can take and how they are encoded.
6554 Up to four operands may be read; this function handles setting the
6555 ".present" field for each read operand itself.
6556 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6557 else returns FAIL. */
6560 parse_neon_mov (char **str
, int *which_operand
)
6562 int i
= *which_operand
, val
;
6563 enum arm_reg_type rtype
;
6565 struct neon_type_el optype
;
6567 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6569 /* Cases 17 or 19. */
6570 inst
.operands
[i
].reg
= val
;
6571 inst
.operands
[i
].isvec
= 1;
6572 inst
.operands
[i
].isscalar
= 2;
6573 inst
.operands
[i
].vectype
= optype
;
6574 inst
.operands
[i
++].present
= 1;
6576 if (skip_past_comma (&ptr
) == FAIL
)
6579 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6581 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6582 inst
.operands
[i
].reg
= val
;
6583 inst
.operands
[i
].isreg
= 1;
6584 inst
.operands
[i
].present
= 1;
6586 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6588 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6589 inst
.operands
[i
].reg
= val
;
6590 inst
.operands
[i
].isvec
= 1;
6591 inst
.operands
[i
].isscalar
= 2;
6592 inst
.operands
[i
].vectype
= optype
;
6593 inst
.operands
[i
++].present
= 1;
6595 if (skip_past_comma (&ptr
) == FAIL
)
6598 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6601 inst
.operands
[i
].reg
= val
;
6602 inst
.operands
[i
].isreg
= 1;
6603 inst
.operands
[i
++].present
= 1;
6605 if (skip_past_comma (&ptr
) == FAIL
)
6608 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6611 inst
.operands
[i
].reg
= val
;
6612 inst
.operands
[i
].isreg
= 1;
6613 inst
.operands
[i
].present
= 1;
6617 first_error (_("expected ARM or MVE vector register"));
6621 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6623 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6624 inst
.operands
[i
].reg
= val
;
6625 inst
.operands
[i
].isscalar
= 1;
6626 inst
.operands
[i
].vectype
= optype
;
6627 inst
.operands
[i
++].present
= 1;
6629 if (skip_past_comma (&ptr
) == FAIL
)
6632 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6635 inst
.operands
[i
].reg
= val
;
6636 inst
.operands
[i
].isreg
= 1;
6637 inst
.operands
[i
].present
= 1;
6639 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6641 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6644 /* Cases 0, 1, 2, 3, 5 (D only). */
6645 if (skip_past_comma (&ptr
) == FAIL
)
6648 inst
.operands
[i
].reg
= val
;
6649 inst
.operands
[i
].isreg
= 1;
6650 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6651 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6652 inst
.operands
[i
].isvec
= 1;
6653 inst
.operands
[i
].vectype
= optype
;
6654 inst
.operands
[i
++].present
= 1;
6656 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6658 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6659 Case 13: VMOV <Sd>, <Rm> */
6660 inst
.operands
[i
].reg
= val
;
6661 inst
.operands
[i
].isreg
= 1;
6662 inst
.operands
[i
].present
= 1;
6664 if (rtype
== REG_TYPE_NQ
)
6666 first_error (_("can't use Neon quad register here"));
6669 else if (rtype
!= REG_TYPE_VFS
)
6672 if (skip_past_comma (&ptr
) == FAIL
)
6674 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6676 inst
.operands
[i
].reg
= val
;
6677 inst
.operands
[i
].isreg
= 1;
6678 inst
.operands
[i
].present
= 1;
6681 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6684 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6685 Case 1: VMOV<c><q> <Dd>, <Dm>
6686 Case 8: VMOV.F32 <Sd>, <Sm>
6687 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6689 inst
.operands
[i
].reg
= val
;
6690 inst
.operands
[i
].isreg
= 1;
6691 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6692 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6693 inst
.operands
[i
].isvec
= 1;
6694 inst
.operands
[i
].vectype
= optype
;
6695 inst
.operands
[i
].present
= 1;
6697 if (skip_past_comma (&ptr
) == SUCCESS
)
6702 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6705 inst
.operands
[i
].reg
= val
;
6706 inst
.operands
[i
].isreg
= 1;
6707 inst
.operands
[i
++].present
= 1;
6709 if (skip_past_comma (&ptr
) == FAIL
)
6712 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6715 inst
.operands
[i
].reg
= val
;
6716 inst
.operands
[i
].isreg
= 1;
6717 inst
.operands
[i
].present
= 1;
6720 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6721 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6722 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6723 Case 10: VMOV.F32 <Sd>, #<imm>
6724 Case 11: VMOV.F64 <Dd>, #<imm> */
6725 inst
.operands
[i
].immisfloat
= 1;
6726 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6728 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6729 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6733 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6737 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6739 /* Cases 6, 7, 16, 18. */
6740 inst
.operands
[i
].reg
= val
;
6741 inst
.operands
[i
].isreg
= 1;
6742 inst
.operands
[i
++].present
= 1;
6744 if (skip_past_comma (&ptr
) == FAIL
)
6747 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6749 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6750 inst
.operands
[i
].reg
= val
;
6751 inst
.operands
[i
].isscalar
= 2;
6752 inst
.operands
[i
].present
= 1;
6753 inst
.operands
[i
].vectype
= optype
;
6755 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6757 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6758 inst
.operands
[i
].reg
= val
;
6759 inst
.operands
[i
].isscalar
= 1;
6760 inst
.operands
[i
].present
= 1;
6761 inst
.operands
[i
].vectype
= optype
;
6763 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6765 inst
.operands
[i
].reg
= val
;
6766 inst
.operands
[i
].isreg
= 1;
6767 inst
.operands
[i
++].present
= 1;
6769 if (skip_past_comma (&ptr
) == FAIL
)
6772 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6775 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6777 inst
.operands
[i
].reg
= val
;
6778 inst
.operands
[i
].isreg
= 1;
6779 inst
.operands
[i
].isvec
= 1;
6780 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6781 inst
.operands
[i
].vectype
= optype
;
6782 inst
.operands
[i
].present
= 1;
6784 if (rtype
== REG_TYPE_VFS
)
6788 if (skip_past_comma (&ptr
) == FAIL
)
6790 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6793 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6796 inst
.operands
[i
].reg
= val
;
6797 inst
.operands
[i
].isreg
= 1;
6798 inst
.operands
[i
].isvec
= 1;
6799 inst
.operands
[i
].issingle
= 1;
6800 inst
.operands
[i
].vectype
= optype
;
6801 inst
.operands
[i
].present
= 1;
6806 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6809 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6810 inst
.operands
[i
].reg
= val
;
6811 inst
.operands
[i
].isvec
= 1;
6812 inst
.operands
[i
].isscalar
= 2;
6813 inst
.operands
[i
].vectype
= optype
;
6814 inst
.operands
[i
++].present
= 1;
6816 if (skip_past_comma (&ptr
) == FAIL
)
6819 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6822 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
6825 inst
.operands
[i
].reg
= val
;
6826 inst
.operands
[i
].isvec
= 1;
6827 inst
.operands
[i
].isscalar
= 2;
6828 inst
.operands
[i
].vectype
= optype
;
6829 inst
.operands
[i
].present
= 1;
6833 first_error (_("VFP single, double or MVE vector register"
6839 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6843 inst
.operands
[i
].reg
= val
;
6844 inst
.operands
[i
].isreg
= 1;
6845 inst
.operands
[i
].isvec
= 1;
6846 inst
.operands
[i
].issingle
= 1;
6847 inst
.operands
[i
].vectype
= optype
;
6848 inst
.operands
[i
].present
= 1;
6853 first_error (_("parse error"));
6857 /* Successfully parsed the operands. Update args. */
6863 first_error (_("expected comma"));
6867 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6871 /* Use this macro when the operand constraints are different
6872 for ARM and THUMB (e.g. ldrd). */
6873 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6874 ((arm_operand) | ((thumb_operand) << 16))
6876 /* Matcher codes for parse_operands. */
6877 enum operand_parse_code
6879 OP_stop
, /* end of line */
6881 OP_RR
, /* ARM register */
6882 OP_RRnpc
, /* ARM register, not r15 */
6883 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6884 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6885 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6886 optional trailing ! */
6887 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6888 OP_RCP
, /* Coprocessor number */
6889 OP_RCN
, /* Coprocessor register */
6890 OP_RF
, /* FPA register */
6891 OP_RVS
, /* VFP single precision register */
6892 OP_RVD
, /* VFP double precision register (0..15) */
6893 OP_RND
, /* Neon double precision register (0..31) */
6894 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
6895 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
6897 OP_RNQ
, /* Neon quad precision register */
6898 OP_RNQMQ
, /* Neon quad or MVE vector register. */
6899 OP_RVSD
, /* VFP single or double precision register */
6900 OP_RVSD_COND
, /* VFP single, double precision register or condition code. */
6901 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
6902 OP_RNSD
, /* Neon single or double precision register */
6903 OP_RNDQ
, /* Neon double or quad precision register */
6904 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
6905 OP_RNDQMQR
, /* Neon double, quad, MVE vector or ARM register. */
6906 OP_RNSDQ
, /* Neon single, double or quad precision register */
6907 OP_RNSC
, /* Neon scalar D[X] */
6908 OP_RVC
, /* VFP control register */
6909 OP_RMF
, /* Maverick F register */
6910 OP_RMD
, /* Maverick D register */
6911 OP_RMFX
, /* Maverick FX register */
6912 OP_RMDX
, /* Maverick DX register */
6913 OP_RMAX
, /* Maverick AX register */
6914 OP_RMDS
, /* Maverick DSPSC register */
6915 OP_RIWR
, /* iWMMXt wR register */
6916 OP_RIWC
, /* iWMMXt wC register */
6917 OP_RIWG
, /* iWMMXt wCG register */
6918 OP_RXA
, /* XScale accumulator register */
6920 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
6922 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
6924 OP_RMQ
, /* MVE vector register. */
6925 OP_RMQRZ
, /* MVE vector or ARM register including ZR. */
6927 /* New operands for Armv8.1-M Mainline. */
6928 OP_LR
, /* ARM LR register */
6929 OP_RRe
, /* ARM register, only even numbered. */
6930 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
6931 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
6933 OP_REGLST
, /* ARM register list */
6934 OP_CLRMLST
, /* CLRM register list */
6935 OP_VRSLST
, /* VFP single-precision register list */
6936 OP_VRDLST
, /* VFP double-precision register list */
6937 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6938 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6939 OP_NSTRLST
, /* Neon element/structure list */
6940 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
6941 OP_MSTRLST2
, /* MVE vector list with two elements. */
6942 OP_MSTRLST4
, /* MVE vector list with four elements. */
6944 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6945 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6946 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6947 OP_RSVDMQ_FI0
, /* VFP S, D, MVE vector register or floating point immediate
6949 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6950 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
6951 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6952 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
6954 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6955 OP_RNDQMQ_RNSC
, /* Neon D, Q or MVE vector reg, or Neon scalar. */
6956 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6957 OP_VMOV
, /* Neon VMOV operands. */
6958 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6959 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
6961 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6962 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6963 OP_VLDR
, /* VLDR operand. */
6965 OP_I0
, /* immediate zero */
6966 OP_I7
, /* immediate value 0 .. 7 */
6967 OP_I15
, /* 0 .. 15 */
6968 OP_I16
, /* 1 .. 16 */
6969 OP_I16z
, /* 0 .. 16 */
6970 OP_I31
, /* 0 .. 31 */
6971 OP_I31w
, /* 0 .. 31, optional trailing ! */
6972 OP_I32
, /* 1 .. 32 */
6973 OP_I32z
, /* 0 .. 32 */
6974 OP_I63
, /* 0 .. 63 */
6975 OP_I63s
, /* -64 .. 63 */
6976 OP_I64
, /* 1 .. 64 */
6977 OP_I64z
, /* 0 .. 64 */
6978 OP_I255
, /* 0 .. 255 */
6980 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6981 OP_I7b
, /* 0 .. 7 */
6982 OP_I15b
, /* 0 .. 15 */
6983 OP_I31b
, /* 0 .. 31 */
6985 OP_SH
, /* shifter operand */
6986 OP_SHG
, /* shifter operand with possible group relocation */
6987 OP_ADDR
, /* Memory address expression (any mode) */
6988 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
6989 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6990 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6991 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6992 OP_EXP
, /* arbitrary expression */
6993 OP_EXPi
, /* same, with optional immediate prefix */
6994 OP_EXPr
, /* same, with optional relocation suffix */
6995 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
6996 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6997 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
6998 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7000 OP_CPSF
, /* CPS flags */
7001 OP_ENDI
, /* Endianness specifier */
7002 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
7003 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
7004 OP_COND
, /* conditional code */
7005 OP_TB
, /* Table branch. */
7007 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
7009 OP_RRnpc_I0
, /* ARM register or literal 0 */
7010 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7011 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7012 OP_RF_IF
, /* FPA register or immediate */
7013 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7014 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7016 /* Optional operands. */
7017 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7018 OP_oI31b
, /* 0 .. 31 */
7019 OP_oI32b
, /* 1 .. 32 */
7020 OP_oI32z
, /* 0 .. 32 */
7021 OP_oIffffb
, /* 0 .. 65535 */
7022 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7024 OP_oRR
, /* ARM register */
7025 OP_oLR
, /* ARM LR register */
7026 OP_oRRnpc
, /* ARM register, not the PC */
7027 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7028 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7029 OP_oRND
, /* Optional Neon double precision register */
7030 OP_oRNQ
, /* Optional Neon quad precision register */
7031 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7032 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7033 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7034 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7036 OP_oSHll
, /* LSL immediate */
7037 OP_oSHar
, /* ASR immediate */
7038 OP_oSHllar
, /* LSL or ASR immediate */
7039 OP_oROR
, /* ROR 0/8/16/24 */
7040 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7042 OP_oRMQRZ
, /* optional MVE vector or ARM register including ZR. */
7044 /* Some pre-defined mixed (ARM/THUMB) operands. */
7045 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7046 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7047 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7049 OP_FIRST_OPTIONAL
= OP_oI7b
7052 /* Generic instruction operand parser. This does no encoding and no
7053 semantic validation; it merely squirrels values away in the inst
7054 structure. Returns SUCCESS or FAIL depending on whether the
7055 specified grammar matched. */
7057 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
7059 unsigned const int *upat
= pattern
;
7060 char *backtrack_pos
= 0;
7061 const char *backtrack_error
= 0;
7062 int i
, val
= 0, backtrack_index
= 0;
7063 enum arm_reg_type rtype
;
7064 parse_operand_result result
;
7065 unsigned int op_parse_code
;
7066 bfd_boolean partial_match
;
7068 #define po_char_or_fail(chr) \
7071 if (skip_past_char (&str, chr) == FAIL) \
7076 #define po_reg_or_fail(regtype) \
7079 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7080 & inst.operands[i].vectype); \
7083 first_error (_(reg_expected_msgs[regtype])); \
7086 inst.operands[i].reg = val; \
7087 inst.operands[i].isreg = 1; \
7088 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7089 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7090 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7091 || rtype == REG_TYPE_VFD \
7092 || rtype == REG_TYPE_NQ); \
7093 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7097 #define po_reg_or_goto(regtype, label) \
7100 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7101 & inst.operands[i].vectype); \
7105 inst.operands[i].reg = val; \
7106 inst.operands[i].isreg = 1; \
7107 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7108 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7109 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7110 || rtype == REG_TYPE_VFD \
7111 || rtype == REG_TYPE_NQ); \
7112 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7116 #define po_imm_or_fail(min, max, popt) \
7119 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7121 inst.operands[i].imm = val; \
7125 #define po_scalar_or_goto(elsz, label, reg_type) \
7128 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7132 inst.operands[i].reg = val; \
7133 inst.operands[i].isscalar = 1; \
7137 #define po_misc_or_fail(expr) \
7145 #define po_misc_or_fail_no_backtrack(expr) \
7149 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7150 backtrack_pos = 0; \
7151 if (result != PARSE_OPERAND_SUCCESS) \
7156 #define po_barrier_or_imm(str) \
7159 val = parse_barrier (&str); \
7160 if (val == FAIL && ! ISALPHA (*str)) \
7163 /* ISB can only take SY as an option. */ \
7164 || ((inst.instruction & 0xf0) == 0x60 \
7167 inst.error = _("invalid barrier type"); \
7168 backtrack_pos = 0; \
7174 skip_whitespace (str
);
7176 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7178 op_parse_code
= upat
[i
];
7179 if (op_parse_code
>= 1<<16)
7180 op_parse_code
= thumb
? (op_parse_code
>> 16)
7181 : (op_parse_code
& ((1<<16)-1));
7183 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7185 /* Remember where we are in case we need to backtrack. */
7186 backtrack_pos
= str
;
7187 backtrack_error
= inst
.error
;
7188 backtrack_index
= i
;
7191 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7192 po_char_or_fail (',');
7194 switch (op_parse_code
)
7206 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7207 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7208 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7209 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7210 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7211 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7214 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7218 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7221 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7223 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7225 /* Also accept generic coprocessor regs for unknown registers. */
7227 po_reg_or_fail (REG_TYPE_CN
);
7229 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7230 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7231 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7232 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7233 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7234 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7235 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7236 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7237 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7238 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7241 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7244 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7245 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7247 po_reg_or_goto (REG_TYPE_RN
, try_rndqmq
);
7252 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7256 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7258 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7261 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7263 po_reg_or_goto (REG_TYPE_VFSD
, try_cond
);
7266 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7268 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7273 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7276 po_reg_or_fail (REG_TYPE_NSDQ
);
7280 po_reg_or_fail (REG_TYPE_MQ
);
7282 /* Neon scalar. Using an element size of 8 means that some invalid
7283 scalars are accepted here, so deal with those in later code. */
7284 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7288 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7291 po_imm_or_fail (0, 0, TRUE
);
7296 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7300 po_reg_or_goto (REG_TYPE_MQ
, try_rsvd_fi0
);
7305 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7308 if (parse_ifimm_zero (&str
))
7309 inst
.operands
[i
].imm
= 0;
7313 = _("only floating point zero is allowed as immediate value");
7321 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7324 po_reg_or_fail (REG_TYPE_RN
);
7328 case OP_RNSDQ_RNSC_MQ
:
7329 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7334 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7338 po_reg_or_fail (REG_TYPE_NSDQ
);
7345 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7348 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7351 po_reg_or_fail (REG_TYPE_NSD
);
7355 case OP_RNDQMQ_RNSC
:
7356 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc
);
7361 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7364 po_reg_or_fail (REG_TYPE_NDQ
);
7370 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7373 po_reg_or_fail (REG_TYPE_VFD
);
7378 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7379 not careful then bad things might happen. */
7380 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7383 case OP_RNDQMQ_Ibig
:
7384 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_ibig
);
7389 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7392 /* There's a possibility of getting a 64-bit immediate here, so
7393 we need special handling. */
7394 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7397 inst
.error
= _("immediate value is out of range");
7405 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7408 po_imm_or_fail (0, 63, TRUE
);
7413 po_char_or_fail ('[');
7414 po_reg_or_fail (REG_TYPE_RN
);
7415 po_char_or_fail (']');
7421 po_reg_or_fail (REG_TYPE_RN
);
7422 if (skip_past_char (&str
, '!') == SUCCESS
)
7423 inst
.operands
[i
].writeback
= 1;
7427 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7428 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7429 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7430 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7431 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7432 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7433 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7434 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7435 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7436 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7437 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7438 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7440 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7442 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7443 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7445 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7446 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7447 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7448 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7450 /* Immediate variants */
7452 po_char_or_fail ('{');
7453 po_imm_or_fail (0, 255, TRUE
);
7454 po_char_or_fail ('}');
7458 /* The expression parser chokes on a trailing !, so we have
7459 to find it first and zap it. */
7462 while (*s
&& *s
!= ',')
7467 inst
.operands
[i
].writeback
= 1;
7469 po_imm_or_fail (0, 31, TRUE
);
7477 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7482 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7487 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7489 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7491 val
= parse_reloc (&str
);
7494 inst
.error
= _("unrecognized relocation suffix");
7497 else if (val
!= BFD_RELOC_UNUSED
)
7499 inst
.operands
[i
].imm
= val
;
7500 inst
.operands
[i
].hasreloc
= 1;
7506 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7508 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7510 inst
.operands
[i
].hasreloc
= 1;
7512 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7514 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7515 inst
.operands
[i
].hasreloc
= 0;
7519 /* Operand for MOVW or MOVT. */
7521 po_misc_or_fail (parse_half (&str
));
7524 /* Register or expression. */
7525 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7526 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7528 /* Register or immediate. */
7529 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7530 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7532 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7534 if (!is_immediate_prefix (*str
))
7537 val
= parse_fpa_immediate (&str
);
7540 /* FPA immediates are encoded as registers 8-15.
7541 parse_fpa_immediate has already applied the offset. */
7542 inst
.operands
[i
].reg
= val
;
7543 inst
.operands
[i
].isreg
= 1;
7546 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7547 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7549 /* Two kinds of register. */
7552 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7554 || (rege
->type
!= REG_TYPE_MMXWR
7555 && rege
->type
!= REG_TYPE_MMXWC
7556 && rege
->type
!= REG_TYPE_MMXWCG
))
7558 inst
.error
= _("iWMMXt data or control register expected");
7561 inst
.operands
[i
].reg
= rege
->number
;
7562 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7568 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7570 || (rege
->type
!= REG_TYPE_MMXWC
7571 && rege
->type
!= REG_TYPE_MMXWCG
))
7573 inst
.error
= _("iWMMXt control register expected");
7576 inst
.operands
[i
].reg
= rege
->number
;
7577 inst
.operands
[i
].isreg
= 1;
7582 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7583 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7584 case OP_oROR
: val
= parse_ror (&str
); break;
7586 case OP_COND
: val
= parse_cond (&str
); break;
7587 case OP_oBARRIER_I15
:
7588 po_barrier_or_imm (str
); break;
7590 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7596 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7597 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7599 inst
.error
= _("Banked registers are not available with this "
7605 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7609 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7612 val
= parse_sys_vldr_vstr (&str
);
7616 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7619 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7621 if (strncasecmp (str
, "APSR_", 5) == 0)
7628 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7629 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7630 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7631 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7632 default: found
= 16;
7636 inst
.operands
[i
].isvec
= 1;
7637 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7638 inst
.operands
[i
].reg
= REG_PC
;
7645 po_misc_or_fail (parse_tb (&str
));
7648 /* Register lists. */
7650 val
= parse_reg_list (&str
, REGLIST_RN
);
7653 inst
.operands
[i
].writeback
= 1;
7659 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7663 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7668 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7673 /* Allow Q registers too. */
7674 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7675 REGLIST_NEON_D
, &partial_match
);
7679 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7680 REGLIST_VFP_S
, &partial_match
);
7681 inst
.operands
[i
].issingle
= 1;
7686 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7687 REGLIST_VFP_D_VPR
, &partial_match
);
7688 if (val
== FAIL
&& !partial_match
)
7691 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7692 REGLIST_VFP_S_VPR
, &partial_match
);
7693 inst
.operands
[i
].issingle
= 1;
7698 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7699 REGLIST_NEON_D
, &partial_match
);
7704 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7705 1, &inst
.operands
[i
].vectype
);
7706 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7710 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7711 0, &inst
.operands
[i
].vectype
);
7714 /* Addressing modes */
7716 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7720 po_misc_or_fail (parse_address (&str
, i
));
7724 po_misc_or_fail_no_backtrack (
7725 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7729 po_misc_or_fail_no_backtrack (
7730 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7734 po_misc_or_fail_no_backtrack (
7735 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7739 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7743 po_misc_or_fail_no_backtrack (
7744 parse_shifter_operand_group_reloc (&str
, i
));
7748 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7752 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7756 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7761 po_reg_or_goto (REG_TYPE_MQ
, try_rr_zr
);
7764 po_reg_or_goto (REG_TYPE_RN
, ZR
);
7767 po_reg_or_fail (REG_TYPE_ZR
);
7771 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7774 /* Various value-based sanity checks and shared operations. We
7775 do not signal immediate failures for the register constraints;
7776 this allows a syntax error to take precedence. */
7777 switch (op_parse_code
)
7785 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7786 inst
.error
= BAD_PC
;
7791 if (inst
.operands
[i
].isreg
)
7793 if (inst
.operands
[i
].reg
== REG_PC
)
7794 inst
.error
= BAD_PC
;
7795 else if (inst
.operands
[i
].reg
== REG_SP
7796 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7797 relaxed since ARMv8-A. */
7798 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7801 inst
.error
= BAD_SP
;
7807 if (inst
.operands
[i
].isreg
7808 && inst
.operands
[i
].reg
== REG_PC
7809 && (inst
.operands
[i
].writeback
|| thumb
))
7810 inst
.error
= BAD_PC
;
7815 if (inst
.operands
[i
].isreg
)
7825 case OP_oBARRIER_I15
:
7838 inst
.operands
[i
].imm
= val
;
7843 if (inst
.operands
[i
].reg
!= REG_LR
)
7844 inst
.error
= _("operand must be LR register");
7849 if (!inst
.operands
[i
].iszr
&& inst
.operands
[i
].reg
== REG_PC
)
7850 inst
.error
= BAD_PC
;
7854 if (inst
.operands
[i
].isreg
7855 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
7856 inst
.error
= BAD_ODD
;
7860 if (inst
.operands
[i
].isreg
)
7862 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
7863 inst
.error
= BAD_EVEN
;
7864 else if (inst
.operands
[i
].reg
== REG_SP
)
7865 as_tsktsk (MVE_BAD_SP
);
7866 else if (inst
.operands
[i
].reg
== REG_PC
)
7867 inst
.error
= BAD_PC
;
7875 /* If we get here, this operand was successfully parsed. */
7876 inst
.operands
[i
].present
= 1;
7880 inst
.error
= BAD_ARGS
;
7885 /* The parse routine should already have set inst.error, but set a
7886 default here just in case. */
7888 inst
.error
= BAD_SYNTAX
;
7892 /* Do not backtrack over a trailing optional argument that
7893 absorbed some text. We will only fail again, with the
7894 'garbage following instruction' error message, which is
7895 probably less helpful than the current one. */
7896 if (backtrack_index
== i
&& backtrack_pos
!= str
7897 && upat
[i
+1] == OP_stop
)
7900 inst
.error
= BAD_SYNTAX
;
7904 /* Try again, skipping the optional argument at backtrack_pos. */
7905 str
= backtrack_pos
;
7906 inst
.error
= backtrack_error
;
7907 inst
.operands
[backtrack_index
].present
= 0;
7908 i
= backtrack_index
;
7912 /* Check that we have parsed all the arguments. */
7913 if (*str
!= '\0' && !inst
.error
)
7914 inst
.error
= _("garbage following instruction");
7916 return inst
.error
? FAIL
: SUCCESS
;
7919 #undef po_char_or_fail
7920 #undef po_reg_or_fail
7921 #undef po_reg_or_goto
7922 #undef po_imm_or_fail
7923 #undef po_scalar_or_fail
7924 #undef po_barrier_or_imm
7926 /* Shorthand macro for instruction encoding functions issuing errors. */
7927 #define constraint(expr, err) \
7938 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7939 instructions are unpredictable if these registers are used. This
7940 is the BadReg predicate in ARM's Thumb-2 documentation.
7942 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7943 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7944 #define reject_bad_reg(reg) \
7946 if (reg == REG_PC) \
7948 inst.error = BAD_PC; \
7951 else if (reg == REG_SP \
7952 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7954 inst.error = BAD_SP; \
7959 /* If REG is R13 (the stack pointer), warn that its use is
7961 #define warn_deprecated_sp(reg) \
7963 if (warn_on_deprecated && reg == REG_SP) \
7964 as_tsktsk (_("use of r13 is deprecated")); \
7967 /* Functions for operand encoding. ARM, then Thumb. */
7969 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7971 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7973 The only binary encoding difference is the Coprocessor number. Coprocessor
7974 9 is used for half-precision calculations or conversions. The format of the
7975 instruction is the same as the equivalent Coprocessor 10 instruction that
7976 exists for Single-Precision operation. */
7979 do_scalar_fp16_v82_encode (void)
7981 if (inst
.cond
< COND_ALWAYS
)
7982 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7983 " the behaviour is UNPREDICTABLE"));
7984 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7987 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7988 mark_feature_used (&arm_ext_fp16
);
7991 /* If VAL can be encoded in the immediate field of an ARM instruction,
7992 return the encoded form. Otherwise, return FAIL. */
7995 encode_arm_immediate (unsigned int val
)
8002 for (i
= 2; i
< 32; i
+= 2)
8003 if ((a
= rotate_left (val
, i
)) <= 0xff)
8004 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
8009 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8010 return the encoded form. Otherwise, return FAIL. */
8012 encode_thumb32_immediate (unsigned int val
)
8019 for (i
= 1; i
<= 24; i
++)
8022 if ((val
& ~(0xff << i
)) == 0)
8023 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
8027 if (val
== ((a
<< 16) | a
))
8029 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
8033 if (val
== ((a
<< 16) | a
))
8034 return 0x200 | (a
>> 8);
8038 /* Encode a VFP SP or DP register number into inst.instruction. */
8041 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
8043 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
8046 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
8049 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8052 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8057 first_error (_("D register out of range for selected VFP version"));
8065 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8069 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8073 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8077 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8081 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8085 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8093 /* Encode a <shift> in an ARM-format instruction. The immediate,
8094 if any, is handled by md_apply_fix. */
8096 encode_arm_shift (int i
)
8098 /* register-shifted register. */
8099 if (inst
.operands
[i
].immisreg
)
8102 for (op_index
= 0; op_index
<= i
; ++op_index
)
8104 /* Check the operand only when it's presented. In pre-UAL syntax,
8105 if the destination register is the same as the first operand, two
8106 register form of the instruction can be used. */
8107 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8108 && inst
.operands
[op_index
].reg
== REG_PC
)
8109 as_warn (UNPRED_REG ("r15"));
8112 if (inst
.operands
[i
].imm
== REG_PC
)
8113 as_warn (UNPRED_REG ("r15"));
8116 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8117 inst
.instruction
|= SHIFT_ROR
<< 5;
8120 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8121 if (inst
.operands
[i
].immisreg
)
8123 inst
.instruction
|= SHIFT_BY_REG
;
8124 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8127 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8132 encode_arm_shifter_operand (int i
)
8134 if (inst
.operands
[i
].isreg
)
8136 inst
.instruction
|= inst
.operands
[i
].reg
;
8137 encode_arm_shift (i
);
8141 inst
.instruction
|= INST_IMMEDIATE
;
8142 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8143 inst
.instruction
|= inst
.operands
[i
].imm
;
8147 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8149 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
8152 Generate an error if the operand is not a register. */
8153 constraint (!inst
.operands
[i
].isreg
,
8154 _("Instruction does not support =N addresses"));
8156 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8158 if (inst
.operands
[i
].preind
)
8162 inst
.error
= _("instruction does not accept preindexed addressing");
8165 inst
.instruction
|= PRE_INDEX
;
8166 if (inst
.operands
[i
].writeback
)
8167 inst
.instruction
|= WRITE_BACK
;
8170 else if (inst
.operands
[i
].postind
)
8172 gas_assert (inst
.operands
[i
].writeback
);
8174 inst
.instruction
|= WRITE_BACK
;
8176 else /* unindexed - only for coprocessor */
8178 inst
.error
= _("instruction does not accept unindexed addressing");
8182 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8183 && (((inst
.instruction
& 0x000f0000) >> 16)
8184 == ((inst
.instruction
& 0x0000f000) >> 12)))
8185 as_warn ((inst
.instruction
& LOAD_BIT
)
8186 ? _("destination register same as write-back base")
8187 : _("source register same as write-back base"));
8190 /* inst.operands[i] was set up by parse_address. Encode it into an
8191 ARM-format mode 2 load or store instruction. If is_t is true,
8192 reject forms that cannot be used with a T instruction (i.e. not
8195 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
8197 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8199 encode_arm_addr_mode_common (i
, is_t
);
8201 if (inst
.operands
[i
].immisreg
)
8203 constraint ((inst
.operands
[i
].imm
== REG_PC
8204 || (is_pc
&& inst
.operands
[i
].writeback
)),
8206 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8207 inst
.instruction
|= inst
.operands
[i
].imm
;
8208 if (!inst
.operands
[i
].negative
)
8209 inst
.instruction
|= INDEX_UP
;
8210 if (inst
.operands
[i
].shifted
)
8212 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8213 inst
.instruction
|= SHIFT_ROR
<< 5;
8216 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8217 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8221 else /* immediate offset in inst.relocs[0] */
8223 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8225 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8227 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8228 cannot use PC in addressing.
8229 PC cannot be used in writeback addressing, either. */
8230 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8233 /* Use of PC in str is deprecated for ARMv7. */
8234 if (warn_on_deprecated
8236 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8237 as_tsktsk (_("use of PC in this instruction is deprecated"));
8240 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8242 /* Prefer + for zero encoded value. */
8243 if (!inst
.operands
[i
].negative
)
8244 inst
.instruction
|= INDEX_UP
;
8245 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8250 /* inst.operands[i] was set up by parse_address. Encode it into an
8251 ARM-format mode 3 load or store instruction. Reject forms that
8252 cannot be used with such instructions. If is_t is true, reject
8253 forms that cannot be used with a T instruction (i.e. not
8256 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
8258 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8260 inst
.error
= _("instruction does not accept scaled register index");
8264 encode_arm_addr_mode_common (i
, is_t
);
8266 if (inst
.operands
[i
].immisreg
)
8268 constraint ((inst
.operands
[i
].imm
== REG_PC
8269 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8271 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8273 inst
.instruction
|= inst
.operands
[i
].imm
;
8274 if (!inst
.operands
[i
].negative
)
8275 inst
.instruction
|= INDEX_UP
;
8277 else /* immediate offset in inst.relocs[0] */
8279 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8280 && inst
.operands
[i
].writeback
),
8282 inst
.instruction
|= HWOFFSET_IMM
;
8283 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8285 /* Prefer + for zero encoded value. */
8286 if (!inst
.operands
[i
].negative
)
8287 inst
.instruction
|= INDEX_UP
;
8289 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8294 /* Write immediate bits [7:0] to the following locations:
8296 |28/24|23 19|18 16|15 4|3 0|
8297 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8299 This function is used by VMOV/VMVN/VORR/VBIC. */
8302 neon_write_immbits (unsigned immbits
)
8304 inst
.instruction
|= immbits
& 0xf;
8305 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8306 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8309 /* Invert low-order SIZE bits of XHI:XLO. */
8312 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8314 unsigned immlo
= xlo
? *xlo
: 0;
8315 unsigned immhi
= xhi
? *xhi
: 0;
8320 immlo
= (~immlo
) & 0xff;
8324 immlo
= (~immlo
) & 0xffff;
8328 immhi
= (~immhi
) & 0xffffffff;
8332 immlo
= (~immlo
) & 0xffffffff;
8346 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8350 neon_bits_same_in_bytes (unsigned imm
)
8352 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8353 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8354 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8355 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8358 /* For immediate of above form, return 0bABCD. */
8361 neon_squash_bits (unsigned imm
)
8363 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8364 | ((imm
& 0x01000000) >> 21);
8367 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8370 neon_qfloat_bits (unsigned imm
)
8372 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8375 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8376 the instruction. *OP is passed as the initial value of the op field, and
8377 may be set to a different value depending on the constant (i.e.
8378 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8379 MVN). If the immediate looks like a repeated pattern then also
8380 try smaller element sizes. */
8383 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8384 unsigned *immbits
, int *op
, int size
,
8385 enum neon_el_type type
)
8387 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8389 if (type
== NT_float
&& !float_p
)
8392 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8394 if (size
!= 32 || *op
== 1)
8396 *immbits
= neon_qfloat_bits (immlo
);
8402 if (neon_bits_same_in_bytes (immhi
)
8403 && neon_bits_same_in_bytes (immlo
))
8407 *immbits
= (neon_squash_bits (immhi
) << 4)
8408 | neon_squash_bits (immlo
);
8419 if (immlo
== (immlo
& 0x000000ff))
8424 else if (immlo
== (immlo
& 0x0000ff00))
8426 *immbits
= immlo
>> 8;
8429 else if (immlo
== (immlo
& 0x00ff0000))
8431 *immbits
= immlo
>> 16;
8434 else if (immlo
== (immlo
& 0xff000000))
8436 *immbits
= immlo
>> 24;
8439 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8441 *immbits
= (immlo
>> 8) & 0xff;
8444 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8446 *immbits
= (immlo
>> 16) & 0xff;
8450 if ((immlo
& 0xffff) != (immlo
>> 16))
8457 if (immlo
== (immlo
& 0x000000ff))
8462 else if (immlo
== (immlo
& 0x0000ff00))
8464 *immbits
= immlo
>> 8;
8468 if ((immlo
& 0xff) != (immlo
>> 8))
8473 if (immlo
== (immlo
& 0x000000ff))
8475 /* Don't allow MVN with 8-bit immediate. */
8485 #if defined BFD_HOST_64_BIT
8486 /* Returns TRUE if double precision value V may be cast
8487 to single precision without loss of accuracy. */
8490 is_double_a_single (bfd_int64_t v
)
8492 int exp
= (int)((v
>> 52) & 0x7FF);
8493 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8495 return (exp
== 0 || exp
== 0x7FF
8496 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8497 && (mantissa
& 0x1FFFFFFFl
) == 0;
8500 /* Returns a double precision value casted to single precision
8501 (ignoring the least significant bits in exponent and mantissa). */
8504 double_to_single (bfd_int64_t v
)
8506 int sign
= (int) ((v
>> 63) & 1l);
8507 int exp
= (int) ((v
>> 52) & 0x7FF);
8508 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8514 exp
= exp
- 1023 + 127;
8523 /* No denormalized numbers. */
8529 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8531 #endif /* BFD_HOST_64_BIT */
8540 static void do_vfp_nsyn_opcode (const char *);
8542 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8543 Determine whether it can be performed with a move instruction; if
8544 it can, convert inst.instruction to that move instruction and
8545 return TRUE; if it can't, convert inst.instruction to a literal-pool
8546 load and return FALSE. If this is not a valid thing to do in the
8547 current context, set inst.error and return TRUE.
8549 inst.operands[i] describes the destination register. */
8552 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8555 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8556 bfd_boolean arm_p
= (t
== CONST_ARM
);
8559 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8563 if ((inst
.instruction
& tbit
) == 0)
8565 inst
.error
= _("invalid pseudo operation");
8569 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8570 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8571 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8573 inst
.error
= _("constant expression expected");
8577 if (inst
.relocs
[0].exp
.X_op
== O_constant
8578 || inst
.relocs
[0].exp
.X_op
== O_big
)
8580 #if defined BFD_HOST_64_BIT
8585 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8587 LITTLENUM_TYPE w
[X_PRECISION
];
8590 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8592 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8594 /* FIXME: Should we check words w[2..5] ? */
8599 #if defined BFD_HOST_64_BIT
8601 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8602 << LITTLENUM_NUMBER_OF_BITS
)
8603 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8604 << LITTLENUM_NUMBER_OF_BITS
)
8605 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8606 << LITTLENUM_NUMBER_OF_BITS
)
8607 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8609 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8610 | (l
[0] & LITTLENUM_MASK
);
8614 v
= inst
.relocs
[0].exp
.X_add_number
;
8616 if (!inst
.operands
[i
].issingle
)
8620 /* LDR should not use lead in a flag-setting instruction being
8621 chosen so we do not check whether movs can be used. */
8623 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8624 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8625 && inst
.operands
[i
].reg
!= 13
8626 && inst
.operands
[i
].reg
!= 15)
8628 /* Check if on thumb2 it can be done with a mov.w, mvn or
8629 movw instruction. */
8630 unsigned int newimm
;
8631 bfd_boolean isNegated
;
8633 newimm
= encode_thumb32_immediate (v
);
8634 if (newimm
!= (unsigned int) FAIL
)
8638 newimm
= encode_thumb32_immediate (~v
);
8639 if (newimm
!= (unsigned int) FAIL
)
8643 /* The number can be loaded with a mov.w or mvn
8645 if (newimm
!= (unsigned int) FAIL
8646 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8648 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8649 | (inst
.operands
[i
].reg
<< 8));
8650 /* Change to MOVN. */
8651 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8652 inst
.instruction
|= (newimm
& 0x800) << 15;
8653 inst
.instruction
|= (newimm
& 0x700) << 4;
8654 inst
.instruction
|= (newimm
& 0x0ff);
8657 /* The number can be loaded with a movw instruction. */
8658 else if ((v
& ~0xFFFF) == 0
8659 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8661 int imm
= v
& 0xFFFF;
8663 inst
.instruction
= 0xf2400000; /* MOVW. */
8664 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8665 inst
.instruction
|= (imm
& 0xf000) << 4;
8666 inst
.instruction
|= (imm
& 0x0800) << 15;
8667 inst
.instruction
|= (imm
& 0x0700) << 4;
8668 inst
.instruction
|= (imm
& 0x00ff);
8675 int value
= encode_arm_immediate (v
);
8679 /* This can be done with a mov instruction. */
8680 inst
.instruction
&= LITERAL_MASK
;
8681 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8682 inst
.instruction
|= value
& 0xfff;
8686 value
= encode_arm_immediate (~ v
);
8689 /* This can be done with a mvn instruction. */
8690 inst
.instruction
&= LITERAL_MASK
;
8691 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8692 inst
.instruction
|= value
& 0xfff;
8696 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8699 unsigned immbits
= 0;
8700 unsigned immlo
= inst
.operands
[1].imm
;
8701 unsigned immhi
= inst
.operands
[1].regisimm
8702 ? inst
.operands
[1].reg
8703 : inst
.relocs
[0].exp
.X_unsigned
8705 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8706 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8707 &op
, 64, NT_invtype
);
8711 neon_invert_size (&immlo
, &immhi
, 64);
8713 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8714 &op
, 64, NT_invtype
);
8719 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8725 /* Fill other bits in vmov encoding for both thumb and arm. */
8727 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8729 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8730 neon_write_immbits (immbits
);
8738 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8739 if (inst
.operands
[i
].issingle
8740 && is_quarter_float (inst
.operands
[1].imm
)
8741 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8743 inst
.operands
[1].imm
=
8744 neon_qfloat_bits (v
);
8745 do_vfp_nsyn_opcode ("fconsts");
8749 /* If our host does not support a 64-bit type then we cannot perform
8750 the following optimization. This mean that there will be a
8751 discrepancy between the output produced by an assembler built for
8752 a 32-bit-only host and the output produced from a 64-bit host, but
8753 this cannot be helped. */
8754 #if defined BFD_HOST_64_BIT
8755 else if (!inst
.operands
[1].issingle
8756 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8758 if (is_double_a_single (v
)
8759 && is_quarter_float (double_to_single (v
)))
8761 inst
.operands
[1].imm
=
8762 neon_qfloat_bits (double_to_single (v
));
8763 do_vfp_nsyn_opcode ("fconstd");
8771 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8772 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8775 inst
.operands
[1].reg
= REG_PC
;
8776 inst
.operands
[1].isreg
= 1;
8777 inst
.operands
[1].preind
= 1;
8778 inst
.relocs
[0].pc_rel
= 1;
8779 inst
.relocs
[0].type
= (thumb_p
8780 ? BFD_RELOC_ARM_THUMB_OFFSET
8782 ? BFD_RELOC_ARM_HWLITERAL
8783 : BFD_RELOC_ARM_LITERAL
));
8787 /* inst.operands[i] was set up by parse_address. Encode it into an
8788 ARM-format instruction. Reject all forms which cannot be encoded
8789 into a coprocessor load/store instruction. If wb_ok is false,
8790 reject use of writeback; if unind_ok is false, reject use of
8791 unindexed addressing. If reloc_override is not 0, use it instead
8792 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8793 (in which case it is preserved). */
8796 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8798 if (!inst
.operands
[i
].isreg
)
8801 if (! inst
.operands
[0].isvec
)
8803 inst
.error
= _("invalid co-processor operand");
8806 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8810 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8812 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8814 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8816 gas_assert (!inst
.operands
[i
].writeback
);
8819 inst
.error
= _("instruction does not support unindexed addressing");
8822 inst
.instruction
|= inst
.operands
[i
].imm
;
8823 inst
.instruction
|= INDEX_UP
;
8827 if (inst
.operands
[i
].preind
)
8828 inst
.instruction
|= PRE_INDEX
;
8830 if (inst
.operands
[i
].writeback
)
8832 if (inst
.operands
[i
].reg
== REG_PC
)
8834 inst
.error
= _("pc may not be used with write-back");
8839 inst
.error
= _("instruction does not support writeback");
8842 inst
.instruction
|= WRITE_BACK
;
8846 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
8847 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8848 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
8849 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8852 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8854 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8857 /* Prefer + for zero encoded value. */
8858 if (!inst
.operands
[i
].negative
)
8859 inst
.instruction
|= INDEX_UP
;
8864 /* Functions for instruction encoding, sorted by sub-architecture.
8865 First some generics; their names are taken from the conventional
8866 bit positions for register arguments in ARM format instructions. */
8876 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8882 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8888 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8889 inst
.instruction
|= inst
.operands
[1].reg
;
8895 inst
.instruction
|= inst
.operands
[0].reg
;
8896 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8902 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8903 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8909 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8910 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8916 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8917 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8921 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8923 if (ARM_CPU_IS_ANY (cpu_variant
))
8925 as_tsktsk ("%s", msg
);
8928 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8940 unsigned Rn
= inst
.operands
[2].reg
;
8941 /* Enforce restrictions on SWP instruction. */
8942 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8944 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8945 _("Rn must not overlap other operands"));
8947 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8949 if (!check_obsolete (&arm_ext_v8
,
8950 _("swp{b} use is obsoleted for ARMv8 and later"))
8951 && warn_on_deprecated
8952 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8953 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8956 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8957 inst
.instruction
|= inst
.operands
[1].reg
;
8958 inst
.instruction
|= Rn
<< 16;
8964 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8965 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8966 inst
.instruction
|= inst
.operands
[2].reg
;
8972 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8973 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
8974 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
8975 || inst
.relocs
[0].exp
.X_add_number
!= 0),
8977 inst
.instruction
|= inst
.operands
[0].reg
;
8978 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8979 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8985 inst
.instruction
|= inst
.operands
[0].imm
;
8991 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8992 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8995 /* ARM instructions, in alphabetical order by function name (except
8996 that wrapper functions appear immediately after the function they
8999 /* This is a pseudo-op of the form "adr rd, label" to be converted
9000 into a relative address of the form "add rd, pc, #label-.-8". */
9005 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9007 /* Frag hacking will turn this into a sub instruction if the offset turns
9008 out to be negative. */
9009 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9010 inst
.relocs
[0].pc_rel
= 1;
9011 inst
.relocs
[0].exp
.X_add_number
-= 8;
9013 if (support_interwork
9014 && inst
.relocs
[0].exp
.X_op
== O_symbol
9015 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9016 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9017 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9018 inst
.relocs
[0].exp
.X_add_number
|= 1;
9021 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9022 into a relative address of the form:
9023 add rd, pc, #low(label-.-8)"
9024 add rd, rd, #high(label-.-8)" */
9029 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9031 /* Frag hacking will turn this into a sub instruction if the offset turns
9032 out to be negative. */
9033 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
9034 inst
.relocs
[0].pc_rel
= 1;
9035 inst
.size
= INSN_SIZE
* 2;
9036 inst
.relocs
[0].exp
.X_add_number
-= 8;
9038 if (support_interwork
9039 && inst
.relocs
[0].exp
.X_op
== O_symbol
9040 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9041 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9042 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9043 inst
.relocs
[0].exp
.X_add_number
|= 1;
9049 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9050 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9052 if (!inst
.operands
[1].present
)
9053 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9054 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9055 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9056 encode_arm_shifter_operand (2);
9062 if (inst
.operands
[0].present
)
9063 inst
.instruction
|= inst
.operands
[0].imm
;
9065 inst
.instruction
|= 0xf;
9071 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9072 constraint (msb
> 32, _("bit-field extends past end of register"));
9073 /* The instruction encoding stores the LSB and MSB,
9074 not the LSB and width. */
9075 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9076 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9077 inst
.instruction
|= (msb
- 1) << 16;
9085 /* #0 in second position is alternative syntax for bfc, which is
9086 the same instruction but with REG_PC in the Rm field. */
9087 if (!inst
.operands
[1].isreg
)
9088 inst
.operands
[1].reg
= REG_PC
;
9090 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9091 constraint (msb
> 32, _("bit-field extends past end of register"));
9092 /* The instruction encoding stores the LSB and MSB,
9093 not the LSB and width. */
9094 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9095 inst
.instruction
|= inst
.operands
[1].reg
;
9096 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9097 inst
.instruction
|= (msb
- 1) << 16;
9103 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9104 _("bit-field extends past end of register"));
9105 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9106 inst
.instruction
|= inst
.operands
[1].reg
;
9107 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9108 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9111 /* ARM V5 breakpoint instruction (argument parse)
9112 BKPT <16 bit unsigned immediate>
9113 Instruction is not conditional.
9114 The bit pattern given in insns[] has the COND_ALWAYS condition,
9115 and it is an error if the caller tried to override that. */
9120 /* Top 12 of 16 bits to bits 19:8. */
9121 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9123 /* Bottom 4 of 16 bits to bits 3:0. */
9124 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9128 encode_branch (int default_reloc
)
9130 if (inst
.operands
[0].hasreloc
)
9132 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9133 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9134 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9135 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9136 ? BFD_RELOC_ARM_PLT32
9137 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9140 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9141 inst
.relocs
[0].pc_rel
= 1;
9148 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9149 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9152 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9159 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9161 if (inst
.cond
== COND_ALWAYS
)
9162 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9164 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9168 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9171 /* ARM V5 branch-link-exchange instruction (argument parse)
9172 BLX <target_addr> ie BLX(1)
9173 BLX{<condition>} <Rm> ie BLX(2)
9174 Unfortunately, there are two different opcodes for this mnemonic.
9175 So, the insns[].value is not used, and the code here zaps values
9176 into inst.instruction.
9177 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9182 if (inst
.operands
[0].isreg
)
9184 /* Arg is a register; the opcode provided by insns[] is correct.
9185 It is not illegal to do "blx pc", just useless. */
9186 if (inst
.operands
[0].reg
== REG_PC
)
9187 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9189 inst
.instruction
|= inst
.operands
[0].reg
;
9193 /* Arg is an address; this instruction cannot be executed
9194 conditionally, and the opcode must be adjusted.
9195 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9196 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9197 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9198 inst
.instruction
= 0xfa000000;
9199 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9206 bfd_boolean want_reloc
;
9208 if (inst
.operands
[0].reg
== REG_PC
)
9209 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9211 inst
.instruction
|= inst
.operands
[0].reg
;
9212 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9213 it is for ARMv4t or earlier. */
9214 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9215 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9216 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9220 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9225 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9229 /* ARM v5TEJ. Jump to Jazelle code. */
9234 if (inst
.operands
[0].reg
== REG_PC
)
9235 as_tsktsk (_("use of r15 in bxj is not really useful"));
9237 inst
.instruction
|= inst
.operands
[0].reg
;
9240 /* Co-processor data operation:
9241 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9242 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9246 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9247 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9248 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9249 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9250 inst
.instruction
|= inst
.operands
[4].reg
;
9251 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9257 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9258 encode_arm_shifter_operand (1);
9261 /* Transfer between coprocessor and ARM registers.
9262 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9267 No special properties. */
9269 struct deprecated_coproc_regs_s
9276 arm_feature_set deprecated
;
9277 arm_feature_set obsoleted
;
9278 const char *dep_msg
;
9279 const char *obs_msg
;
9282 #define DEPR_ACCESS_V8 \
9283 N_("This coprocessor register access is deprecated in ARMv8")
9285 /* Table of all deprecated coprocessor registers. */
9286 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9288 {15, 0, 7, 10, 5, /* CP15DMB. */
9289 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9290 DEPR_ACCESS_V8
, NULL
},
9291 {15, 0, 7, 10, 4, /* CP15DSB. */
9292 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9293 DEPR_ACCESS_V8
, NULL
},
9294 {15, 0, 7, 5, 4, /* CP15ISB. */
9295 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9296 DEPR_ACCESS_V8
, NULL
},
9297 {14, 6, 1, 0, 0, /* TEEHBR. */
9298 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9299 DEPR_ACCESS_V8
, NULL
},
9300 {14, 6, 0, 0, 0, /* TEECR. */
9301 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9302 DEPR_ACCESS_V8
, NULL
},
9305 #undef DEPR_ACCESS_V8
9307 static const size_t deprecated_coproc_reg_count
=
9308 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9316 Rd
= inst
.operands
[2].reg
;
9319 if (inst
.instruction
== 0xee000010
9320 || inst
.instruction
== 0xfe000010)
9322 reject_bad_reg (Rd
);
9323 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9325 constraint (Rd
== REG_SP
, BAD_SP
);
9330 if (inst
.instruction
== 0xe000010)
9331 constraint (Rd
== REG_PC
, BAD_PC
);
9334 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9336 const struct deprecated_coproc_regs_s
*r
=
9337 deprecated_coproc_regs
+ i
;
9339 if (inst
.operands
[0].reg
== r
->cp
9340 && inst
.operands
[1].imm
== r
->opc1
9341 && inst
.operands
[3].reg
== r
->crn
9342 && inst
.operands
[4].reg
== r
->crm
9343 && inst
.operands
[5].imm
== r
->opc2
)
9345 if (! ARM_CPU_IS_ANY (cpu_variant
)
9346 && warn_on_deprecated
9347 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9348 as_tsktsk ("%s", r
->dep_msg
);
9352 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9353 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9354 inst
.instruction
|= Rd
<< 12;
9355 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9356 inst
.instruction
|= inst
.operands
[4].reg
;
9357 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9360 /* Transfer between coprocessor register and pair of ARM registers.
9361 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9366 Two XScale instructions are special cases of these:
9368 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9369 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9371 Result unpredictable if Rd or Rn is R15. */
9378 Rd
= inst
.operands
[2].reg
;
9379 Rn
= inst
.operands
[3].reg
;
9383 reject_bad_reg (Rd
);
9384 reject_bad_reg (Rn
);
9388 constraint (Rd
== REG_PC
, BAD_PC
);
9389 constraint (Rn
== REG_PC
, BAD_PC
);
9392 /* Only check the MRRC{2} variants. */
9393 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9395 /* If Rd == Rn, error that the operation is
9396 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9397 constraint (Rd
== Rn
, BAD_OVERLAP
);
9400 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9401 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9402 inst
.instruction
|= Rd
<< 12;
9403 inst
.instruction
|= Rn
<< 16;
9404 inst
.instruction
|= inst
.operands
[4].reg
;
9410 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9411 if (inst
.operands
[1].present
)
9413 inst
.instruction
|= CPSI_MMOD
;
9414 inst
.instruction
|= inst
.operands
[1].imm
;
9421 inst
.instruction
|= inst
.operands
[0].imm
;
9427 unsigned Rd
, Rn
, Rm
;
9429 Rd
= inst
.operands
[0].reg
;
9430 Rn
= (inst
.operands
[1].present
9431 ? inst
.operands
[1].reg
: Rd
);
9432 Rm
= inst
.operands
[2].reg
;
9434 constraint ((Rd
== REG_PC
), BAD_PC
);
9435 constraint ((Rn
== REG_PC
), BAD_PC
);
9436 constraint ((Rm
== REG_PC
), BAD_PC
);
9438 inst
.instruction
|= Rd
<< 16;
9439 inst
.instruction
|= Rn
<< 0;
9440 inst
.instruction
|= Rm
<< 8;
9446 /* There is no IT instruction in ARM mode. We
9447 process it to do the validation as if in
9448 thumb mode, just in case the code gets
9449 assembled for thumb using the unified syntax. */
9454 set_pred_insn_type (IT_INSN
);
9455 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9456 now_pred
.cc
= inst
.operands
[0].imm
;
9460 /* If there is only one register in the register list,
9461 then return its register number. Otherwise return -1. */
9463 only_one_reg_in_list (int range
)
9465 int i
= ffs (range
) - 1;
9466 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9470 encode_ldmstm(int from_push_pop_mnem
)
9472 int base_reg
= inst
.operands
[0].reg
;
9473 int range
= inst
.operands
[1].imm
;
9476 inst
.instruction
|= base_reg
<< 16;
9477 inst
.instruction
|= range
;
9479 if (inst
.operands
[1].writeback
)
9480 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9482 if (inst
.operands
[0].writeback
)
9484 inst
.instruction
|= WRITE_BACK
;
9485 /* Check for unpredictable uses of writeback. */
9486 if (inst
.instruction
& LOAD_BIT
)
9488 /* Not allowed in LDM type 2. */
9489 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9490 && ((range
& (1 << REG_PC
)) == 0))
9491 as_warn (_("writeback of base register is UNPREDICTABLE"));
9492 /* Only allowed if base reg not in list for other types. */
9493 else if (range
& (1 << base_reg
))
9494 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9498 /* Not allowed for type 2. */
9499 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9500 as_warn (_("writeback of base register is UNPREDICTABLE"));
9501 /* Only allowed if base reg not in list, or first in list. */
9502 else if ((range
& (1 << base_reg
))
9503 && (range
& ((1 << base_reg
) - 1)))
9504 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9508 /* If PUSH/POP has only one register, then use the A2 encoding. */
9509 one_reg
= only_one_reg_in_list (range
);
9510 if (from_push_pop_mnem
&& one_reg
>= 0)
9512 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9514 if (is_push
&& one_reg
== 13 /* SP */)
9515 /* PR 22483: The A2 encoding cannot be used when
9516 pushing the stack pointer as this is UNPREDICTABLE. */
9519 inst
.instruction
&= A_COND_MASK
;
9520 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9521 inst
.instruction
|= one_reg
<< 12;
9528 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9531 /* ARMv5TE load-consecutive (argument parse)
9540 constraint (inst
.operands
[0].reg
% 2 != 0,
9541 _("first transfer register must be even"));
9542 constraint (inst
.operands
[1].present
9543 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9544 _("can only transfer two consecutive registers"));
9545 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9546 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9548 if (!inst
.operands
[1].present
)
9549 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9551 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9552 register and the first register written; we have to diagnose
9553 overlap between the base and the second register written here. */
9555 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9556 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9557 as_warn (_("base register written back, and overlaps "
9558 "second transfer register"));
9560 if (!(inst
.instruction
& V4_STR_BIT
))
9562 /* For an index-register load, the index register must not overlap the
9563 destination (even if not write-back). */
9564 if (inst
.operands
[2].immisreg
9565 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9566 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9567 as_warn (_("index register overlaps transfer register"));
9569 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9570 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9576 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9577 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9578 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9579 || inst
.operands
[1].negative
9580 /* This can arise if the programmer has written
9582 or if they have mistakenly used a register name as the last
9585 It is very difficult to distinguish between these two cases
9586 because "rX" might actually be a label. ie the register
9587 name has been occluded by a symbol of the same name. So we
9588 just generate a general 'bad addressing mode' type error
9589 message and leave it up to the programmer to discover the
9590 true cause and fix their mistake. */
9591 || (inst
.operands
[1].reg
== REG_PC
),
9594 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9595 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9596 _("offset must be zero in ARM encoding"));
9598 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9600 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9601 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9602 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9608 constraint (inst
.operands
[0].reg
% 2 != 0,
9609 _("even register required"));
9610 constraint (inst
.operands
[1].present
9611 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9612 _("can only load two consecutive registers"));
9613 /* If op 1 were present and equal to PC, this function wouldn't
9614 have been called in the first place. */
9615 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9617 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9618 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9621 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9622 which is not a multiple of four is UNPREDICTABLE. */
9624 check_ldr_r15_aligned (void)
9626 constraint (!(inst
.operands
[1].immisreg
)
9627 && (inst
.operands
[0].reg
== REG_PC
9628 && inst
.operands
[1].reg
== REG_PC
9629 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9630 _("ldr to register 15 must be 4-byte aligned"));
9636 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9637 if (!inst
.operands
[1].isreg
)
9638 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9640 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9641 check_ldr_r15_aligned ();
9647 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9649 if (inst
.operands
[1].preind
)
9651 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9652 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9653 _("this instruction requires a post-indexed address"));
9655 inst
.operands
[1].preind
= 0;
9656 inst
.operands
[1].postind
= 1;
9657 inst
.operands
[1].writeback
= 1;
9659 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9660 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9663 /* Halfword and signed-byte load/store operations. */
9668 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9669 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9670 if (!inst
.operands
[1].isreg
)
9671 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9673 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9679 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9681 if (inst
.operands
[1].preind
)
9683 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9684 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9685 _("this instruction requires a post-indexed address"));
9687 inst
.operands
[1].preind
= 0;
9688 inst
.operands
[1].postind
= 1;
9689 inst
.operands
[1].writeback
= 1;
9691 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9692 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9695 /* Co-processor register load/store.
9696 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9700 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9701 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9702 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9708 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9709 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9710 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9711 && !(inst
.instruction
& 0x00400000))
9712 as_tsktsk (_("Rd and Rm should be different in mla"));
9714 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9715 inst
.instruction
|= inst
.operands
[1].reg
;
9716 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9717 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9723 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9724 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9726 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9727 encode_arm_shifter_operand (1);
9730 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9737 top
= (inst
.instruction
& 0x00400000) != 0;
9738 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
9739 _(":lower16: not allowed in this instruction"));
9740 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
9741 _(":upper16: not allowed in this instruction"));
9742 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9743 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
9745 imm
= inst
.relocs
[0].exp
.X_add_number
;
9746 /* The value is in two pieces: 0:11, 16:19. */
9747 inst
.instruction
|= (imm
& 0x00000fff);
9748 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9753 do_vfp_nsyn_mrs (void)
9755 if (inst
.operands
[0].isvec
)
9757 if (inst
.operands
[1].reg
!= 1)
9758 first_error (_("operand 1 must be FPSCR"));
9759 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9760 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9761 do_vfp_nsyn_opcode ("fmstat");
9763 else if (inst
.operands
[1].isvec
)
9764 do_vfp_nsyn_opcode ("fmrx");
9772 do_vfp_nsyn_msr (void)
9774 if (inst
.operands
[0].isvec
)
9775 do_vfp_nsyn_opcode ("fmxr");
9785 unsigned Rt
= inst
.operands
[0].reg
;
9787 if (thumb_mode
&& Rt
== REG_SP
)
9789 inst
.error
= BAD_SP
;
9793 /* MVFR2 is only valid at ARMv8-A. */
9794 if (inst
.operands
[1].reg
== 5)
9795 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9798 /* APSR_ sets isvec. All other refs to PC are illegal. */
9799 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9801 inst
.error
= BAD_PC
;
9805 /* If we get through parsing the register name, we just insert the number
9806 generated into the instruction without further validation. */
9807 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9808 inst
.instruction
|= (Rt
<< 12);
9814 unsigned Rt
= inst
.operands
[1].reg
;
9817 reject_bad_reg (Rt
);
9818 else if (Rt
== REG_PC
)
9820 inst
.error
= BAD_PC
;
9824 /* MVFR2 is only valid for ARMv8-A. */
9825 if (inst
.operands
[0].reg
== 5)
9826 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9829 /* If we get through parsing the register name, we just insert the number
9830 generated into the instruction without further validation. */
9831 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9832 inst
.instruction
|= (Rt
<< 12);
9840 if (do_vfp_nsyn_mrs () == SUCCESS
)
9843 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9844 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9846 if (inst
.operands
[1].isreg
)
9848 br
= inst
.operands
[1].reg
;
9849 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
9850 as_bad (_("bad register for mrs"));
9854 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9855 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9857 _("'APSR', 'CPSR' or 'SPSR' expected"));
9858 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9861 inst
.instruction
|= br
;
9864 /* Two possible forms:
9865 "{C|S}PSR_<field>, Rm",
9866 "{C|S}PSR_f, #expression". */
9871 if (do_vfp_nsyn_msr () == SUCCESS
)
9874 inst
.instruction
|= inst
.operands
[0].imm
;
9875 if (inst
.operands
[1].isreg
)
9876 inst
.instruction
|= inst
.operands
[1].reg
;
9879 inst
.instruction
|= INST_IMMEDIATE
;
9880 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9881 inst
.relocs
[0].pc_rel
= 0;
9888 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9890 if (!inst
.operands
[2].present
)
9891 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9892 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9893 inst
.instruction
|= inst
.operands
[1].reg
;
9894 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9896 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9897 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9898 as_tsktsk (_("Rd and Rm should be different in mul"));
9901 /* Long Multiply Parser
9902 UMULL RdLo, RdHi, Rm, Rs
9903 SMULL RdLo, RdHi, Rm, Rs
9904 UMLAL RdLo, RdHi, Rm, Rs
9905 SMLAL RdLo, RdHi, Rm, Rs. */
9910 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9911 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9912 inst
.instruction
|= inst
.operands
[2].reg
;
9913 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9915 /* rdhi and rdlo must be different. */
9916 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9917 as_tsktsk (_("rdhi and rdlo must be different"));
9919 /* rdhi, rdlo and rm must all be different before armv6. */
9920 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9921 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9922 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9923 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9929 if (inst
.operands
[0].present
9930 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9932 /* Architectural NOP hints are CPSR sets with no bits selected. */
9933 inst
.instruction
&= 0xf0000000;
9934 inst
.instruction
|= 0x0320f000;
9935 if (inst
.operands
[0].present
)
9936 inst
.instruction
|= inst
.operands
[0].imm
;
9940 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9941 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9942 Condition defaults to COND_ALWAYS.
9943 Error if Rd, Rn or Rm are R15. */
9948 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9949 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9950 inst
.instruction
|= inst
.operands
[2].reg
;
9951 if (inst
.operands
[3].present
)
9952 encode_arm_shift (3);
9955 /* ARM V6 PKHTB (Argument Parse). */
9960 if (!inst
.operands
[3].present
)
9962 /* If the shift specifier is omitted, turn the instruction
9963 into pkhbt rd, rm, rn. */
9964 inst
.instruction
&= 0xfff00010;
9965 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9966 inst
.instruction
|= inst
.operands
[1].reg
;
9967 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9971 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9972 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9973 inst
.instruction
|= inst
.operands
[2].reg
;
9974 encode_arm_shift (3);
9978 /* ARMv5TE: Preload-Cache
9979 MP Extensions: Preload for write
9983 Syntactically, like LDR with B=1, W=0, L=1. */
9988 constraint (!inst
.operands
[0].isreg
,
9989 _("'[' expected after PLD mnemonic"));
9990 constraint (inst
.operands
[0].postind
,
9991 _("post-indexed expression used in preload instruction"));
9992 constraint (inst
.operands
[0].writeback
,
9993 _("writeback used in preload instruction"));
9994 constraint (!inst
.operands
[0].preind
,
9995 _("unindexed addressing used in preload instruction"));
9996 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9999 /* ARMv7: PLI <addr_mode> */
10003 constraint (!inst
.operands
[0].isreg
,
10004 _("'[' expected after PLI mnemonic"));
10005 constraint (inst
.operands
[0].postind
,
10006 _("post-indexed expression used in preload instruction"));
10007 constraint (inst
.operands
[0].writeback
,
10008 _("writeback used in preload instruction"));
10009 constraint (!inst
.operands
[0].preind
,
10010 _("unindexed addressing used in preload instruction"));
10011 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10012 inst
.instruction
&= ~PRE_INDEX
;
10018 constraint (inst
.operands
[0].writeback
,
10019 _("push/pop do not support {reglist}^"));
10020 inst
.operands
[1] = inst
.operands
[0];
10021 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
10022 inst
.operands
[0].isreg
= 1;
10023 inst
.operands
[0].writeback
= 1;
10024 inst
.operands
[0].reg
= REG_SP
;
10025 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
10028 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10029 word at the specified address and the following word
10031 Unconditionally executed.
10032 Error if Rn is R15. */
10037 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10038 if (inst
.operands
[0].writeback
)
10039 inst
.instruction
|= WRITE_BACK
;
10042 /* ARM V6 ssat (argument parse). */
10047 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10048 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
10049 inst
.instruction
|= inst
.operands
[2].reg
;
10051 if (inst
.operands
[3].present
)
10052 encode_arm_shift (3);
10055 /* ARM V6 usat (argument parse). */
10060 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10061 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10062 inst
.instruction
|= inst
.operands
[2].reg
;
10064 if (inst
.operands
[3].present
)
10065 encode_arm_shift (3);
10068 /* ARM V6 ssat16 (argument parse). */
10073 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10074 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10075 inst
.instruction
|= inst
.operands
[2].reg
;
10081 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10082 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10083 inst
.instruction
|= inst
.operands
[2].reg
;
10086 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10087 preserving the other bits.
10089 setend <endian_specifier>, where <endian_specifier> is either
10095 if (warn_on_deprecated
10096 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10097 as_tsktsk (_("setend use is deprecated for ARMv8"));
10099 if (inst
.operands
[0].imm
)
10100 inst
.instruction
|= 0x200;
10106 unsigned int Rm
= (inst
.operands
[1].present
10107 ? inst
.operands
[1].reg
10108 : inst
.operands
[0].reg
);
10110 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10111 inst
.instruction
|= Rm
;
10112 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10114 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10115 inst
.instruction
|= SHIFT_BY_REG
;
10116 /* PR 12854: Error on extraneous shifts. */
10117 constraint (inst
.operands
[2].shifted
,
10118 _("extraneous shift as part of operand to shift insn"));
10121 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10127 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10128 inst
.relocs
[0].pc_rel
= 0;
10134 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10135 inst
.relocs
[0].pc_rel
= 0;
10141 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10142 inst
.relocs
[0].pc_rel
= 0;
10148 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10149 _("selected processor does not support SETPAN instruction"));
10151 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10157 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10158 _("selected processor does not support SETPAN instruction"));
10160 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10163 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10164 SMLAxy{cond} Rd,Rm,Rs,Rn
10165 SMLAWy{cond} Rd,Rm,Rs,Rn
10166 Error if any register is R15. */
10171 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10172 inst
.instruction
|= inst
.operands
[1].reg
;
10173 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10174 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10177 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10178 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10179 Error if any register is R15.
10180 Warning if Rdlo == Rdhi. */
10185 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10186 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10187 inst
.instruction
|= inst
.operands
[2].reg
;
10188 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10190 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10191 as_tsktsk (_("rdhi and rdlo must be different"));
10194 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10195 SMULxy{cond} Rd,Rm,Rs
10196 Error if any register is R15. */
10201 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10202 inst
.instruction
|= inst
.operands
[1].reg
;
10203 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10206 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10207 the same for both ARM and Thumb-2. */
10214 if (inst
.operands
[0].present
)
10216 reg
= inst
.operands
[0].reg
;
10217 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10222 inst
.instruction
|= reg
<< 16;
10223 inst
.instruction
|= inst
.operands
[1].imm
;
10224 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10225 inst
.instruction
|= WRITE_BACK
;
10228 /* ARM V6 strex (argument parse). */
10233 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10234 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10235 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10236 || inst
.operands
[2].negative
10237 /* See comment in do_ldrex(). */
10238 || (inst
.operands
[2].reg
== REG_PC
),
10241 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10242 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10244 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10245 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10246 _("offset must be zero in ARM encoding"));
10248 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10249 inst
.instruction
|= inst
.operands
[1].reg
;
10250 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10251 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10255 do_t_strexbh (void)
10257 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10258 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10259 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10260 || inst
.operands
[2].negative
,
10263 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10264 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10272 constraint (inst
.operands
[1].reg
% 2 != 0,
10273 _("even register required"));
10274 constraint (inst
.operands
[2].present
10275 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10276 _("can only store two consecutive registers"));
10277 /* If op 2 were present and equal to PC, this function wouldn't
10278 have been called in the first place. */
10279 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10281 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10282 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10283 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10286 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10287 inst
.instruction
|= inst
.operands
[1].reg
;
10288 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10295 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10296 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10304 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10305 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10310 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10311 extends it to 32-bits, and adds the result to a value in another
10312 register. You can specify a rotation by 0, 8, 16, or 24 bits
10313 before extracting the 16-bit value.
10314 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10315 Condition defaults to COND_ALWAYS.
10316 Error if any register uses R15. */
10321 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10322 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10323 inst
.instruction
|= inst
.operands
[2].reg
;
10324 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10329 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10330 Condition defaults to COND_ALWAYS.
10331 Error if any register uses R15. */
10336 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10337 inst
.instruction
|= inst
.operands
[1].reg
;
10338 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10341 /* VFP instructions. In a logical order: SP variant first, monad
10342 before dyad, arithmetic then move then load/store. */
10345 do_vfp_sp_monadic (void)
10347 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10348 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10351 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10352 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10356 do_vfp_sp_dyadic (void)
10358 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10359 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10360 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10364 do_vfp_sp_compare_z (void)
10366 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10370 do_vfp_dp_sp_cvt (void)
10372 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10373 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10377 do_vfp_sp_dp_cvt (void)
10379 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10380 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10384 do_vfp_reg_from_sp (void)
10386 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10387 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10390 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10391 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10395 do_vfp_reg2_from_sp2 (void)
10397 constraint (inst
.operands
[2].imm
!= 2,
10398 _("only two consecutive VFP SP registers allowed here"));
10399 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10400 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10401 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10405 do_vfp_sp_from_reg (void)
10407 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10408 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10411 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10412 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10416 do_vfp_sp2_from_reg2 (void)
10418 constraint (inst
.operands
[0].imm
!= 2,
10419 _("only two consecutive VFP SP registers allowed here"));
10420 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10421 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10422 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10426 do_vfp_sp_ldst (void)
10428 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10429 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10433 do_vfp_dp_ldst (void)
10435 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10436 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10441 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10443 if (inst
.operands
[0].writeback
)
10444 inst
.instruction
|= WRITE_BACK
;
10446 constraint (ldstm_type
!= VFP_LDSTMIA
,
10447 _("this addressing mode requires base-register writeback"));
10448 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10449 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10450 inst
.instruction
|= inst
.operands
[1].imm
;
10454 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10458 if (inst
.operands
[0].writeback
)
10459 inst
.instruction
|= WRITE_BACK
;
10461 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10462 _("this addressing mode requires base-register writeback"));
10464 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10465 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10467 count
= inst
.operands
[1].imm
<< 1;
10468 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10471 inst
.instruction
|= count
;
10475 do_vfp_sp_ldstmia (void)
10477 vfp_sp_ldstm (VFP_LDSTMIA
);
10481 do_vfp_sp_ldstmdb (void)
10483 vfp_sp_ldstm (VFP_LDSTMDB
);
10487 do_vfp_dp_ldstmia (void)
10489 vfp_dp_ldstm (VFP_LDSTMIA
);
10493 do_vfp_dp_ldstmdb (void)
10495 vfp_dp_ldstm (VFP_LDSTMDB
);
10499 do_vfp_xp_ldstmia (void)
10501 vfp_dp_ldstm (VFP_LDSTMIAX
);
10505 do_vfp_xp_ldstmdb (void)
10507 vfp_dp_ldstm (VFP_LDSTMDBX
);
10511 do_vfp_dp_rd_rm (void)
10513 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10514 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10517 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10518 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10522 do_vfp_dp_rn_rd (void)
10524 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10525 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10529 do_vfp_dp_rd_rn (void)
10531 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10532 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10536 do_vfp_dp_rd_rn_rm (void)
10538 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10539 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10542 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10543 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10544 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10548 do_vfp_dp_rd (void)
10550 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10554 do_vfp_dp_rm_rd_rn (void)
10556 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10557 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10560 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10561 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10562 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10565 /* VFPv3 instructions. */
10567 do_vfp_sp_const (void)
10569 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10570 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10571 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10575 do_vfp_dp_const (void)
10577 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10578 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10579 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10583 vfp_conv (int srcsize
)
10585 int immbits
= srcsize
- inst
.operands
[1].imm
;
10587 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10589 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10590 i.e. immbits must be in range 0 - 16. */
10591 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10594 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10596 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10597 i.e. immbits must be in range 0 - 31. */
10598 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10602 inst
.instruction
|= (immbits
& 1) << 5;
10603 inst
.instruction
|= (immbits
>> 1);
10607 do_vfp_sp_conv_16 (void)
10609 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10614 do_vfp_dp_conv_16 (void)
10616 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10621 do_vfp_sp_conv_32 (void)
10623 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10628 do_vfp_dp_conv_32 (void)
10630 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10634 /* FPA instructions. Also in a logical order. */
10639 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10640 inst
.instruction
|= inst
.operands
[1].reg
;
10644 do_fpa_ldmstm (void)
10646 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10647 switch (inst
.operands
[1].imm
)
10649 case 1: inst
.instruction
|= CP_T_X
; break;
10650 case 2: inst
.instruction
|= CP_T_Y
; break;
10651 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10656 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10658 /* The instruction specified "ea" or "fd", so we can only accept
10659 [Rn]{!}. The instruction does not really support stacking or
10660 unstacking, so we have to emulate these by setting appropriate
10661 bits and offsets. */
10662 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10663 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10664 _("this instruction does not support indexing"));
10666 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10667 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10669 if (!(inst
.instruction
& INDEX_UP
))
10670 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
10672 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10674 inst
.operands
[2].preind
= 0;
10675 inst
.operands
[2].postind
= 1;
10679 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10682 /* iWMMXt instructions: strictly in alphabetical order. */
10685 do_iwmmxt_tandorc (void)
10687 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10691 do_iwmmxt_textrc (void)
10693 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10694 inst
.instruction
|= inst
.operands
[1].imm
;
10698 do_iwmmxt_textrm (void)
10700 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10701 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10702 inst
.instruction
|= inst
.operands
[2].imm
;
10706 do_iwmmxt_tinsr (void)
10708 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10709 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10710 inst
.instruction
|= inst
.operands
[2].imm
;
10714 do_iwmmxt_tmia (void)
10716 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10717 inst
.instruction
|= inst
.operands
[1].reg
;
10718 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10722 do_iwmmxt_waligni (void)
10724 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10725 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10726 inst
.instruction
|= inst
.operands
[2].reg
;
10727 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10731 do_iwmmxt_wmerge (void)
10733 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10734 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10735 inst
.instruction
|= inst
.operands
[2].reg
;
10736 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10740 do_iwmmxt_wmov (void)
10742 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10743 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10744 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10745 inst
.instruction
|= inst
.operands
[1].reg
;
10749 do_iwmmxt_wldstbh (void)
10752 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10754 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10756 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10757 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10761 do_iwmmxt_wldstw (void)
10763 /* RIWR_RIWC clears .isreg for a control register. */
10764 if (!inst
.operands
[0].isreg
)
10766 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10767 inst
.instruction
|= 0xf0000000;
10770 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10771 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10775 do_iwmmxt_wldstd (void)
10777 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10778 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10779 && inst
.operands
[1].immisreg
)
10781 inst
.instruction
&= ~0x1a000ff;
10782 inst
.instruction
|= (0xfU
<< 28);
10783 if (inst
.operands
[1].preind
)
10784 inst
.instruction
|= PRE_INDEX
;
10785 if (!inst
.operands
[1].negative
)
10786 inst
.instruction
|= INDEX_UP
;
10787 if (inst
.operands
[1].writeback
)
10788 inst
.instruction
|= WRITE_BACK
;
10789 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10790 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
10791 inst
.instruction
|= inst
.operands
[1].imm
;
10794 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10798 do_iwmmxt_wshufh (void)
10800 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10801 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10802 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10803 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10807 do_iwmmxt_wzero (void)
10809 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10810 inst
.instruction
|= inst
.operands
[0].reg
;
10811 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10812 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10816 do_iwmmxt_wrwrwr_or_imm5 (void)
10818 if (inst
.operands
[2].isreg
)
10821 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10822 _("immediate operand requires iWMMXt2"));
10824 if (inst
.operands
[2].imm
== 0)
10826 switch ((inst
.instruction
>> 20) & 0xf)
10832 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10833 inst
.operands
[2].imm
= 16;
10834 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10840 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10841 inst
.operands
[2].imm
= 32;
10842 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10849 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10851 wrn
= (inst
.instruction
>> 16) & 0xf;
10852 inst
.instruction
&= 0xff0fff0f;
10853 inst
.instruction
|= wrn
;
10854 /* Bail out here; the instruction is now assembled. */
10859 /* Map 32 -> 0, etc. */
10860 inst
.operands
[2].imm
&= 0x1f;
10861 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10865 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10866 operations first, then control, shift, and load/store. */
10868 /* Insns like "foo X,Y,Z". */
10871 do_mav_triple (void)
10873 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10874 inst
.instruction
|= inst
.operands
[1].reg
;
10875 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10878 /* Insns like "foo W,X,Y,Z".
10879 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10884 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10885 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10886 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10887 inst
.instruction
|= inst
.operands
[3].reg
;
10890 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10892 do_mav_dspsc (void)
10894 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10897 /* Maverick shift immediate instructions.
10898 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10899 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10902 do_mav_shift (void)
10904 int imm
= inst
.operands
[2].imm
;
10906 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10907 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10909 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10910 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10911 Bit 4 should be 0. */
10912 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10914 inst
.instruction
|= imm
;
10917 /* XScale instructions. Also sorted arithmetic before move. */
10919 /* Xscale multiply-accumulate (argument parse)
10922 MIAxycc acc0,Rm,Rs. */
10927 inst
.instruction
|= inst
.operands
[1].reg
;
10928 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10931 /* Xscale move-accumulator-register (argument parse)
10933 MARcc acc0,RdLo,RdHi. */
10938 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10939 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10942 /* Xscale move-register-accumulator (argument parse)
10944 MRAcc RdLo,RdHi,acc0. */
10949 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10950 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10951 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10954 /* Encoding functions relevant only to Thumb. */
10956 /* inst.operands[i] is a shifted-register operand; encode
10957 it into inst.instruction in the format used by Thumb32. */
10960 encode_thumb32_shifted_operand (int i
)
10962 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10963 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10965 constraint (inst
.operands
[i
].immisreg
,
10966 _("shift by register not allowed in thumb mode"));
10967 inst
.instruction
|= inst
.operands
[i
].reg
;
10968 if (shift
== SHIFT_RRX
)
10969 inst
.instruction
|= SHIFT_ROR
<< 4;
10972 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
10973 _("expression too complex"));
10975 constraint (value
> 32
10976 || (value
== 32 && (shift
== SHIFT_LSL
10977 || shift
== SHIFT_ROR
)),
10978 _("shift expression is too large"));
10982 else if (value
== 32)
10985 inst
.instruction
|= shift
<< 4;
10986 inst
.instruction
|= (value
& 0x1c) << 10;
10987 inst
.instruction
|= (value
& 0x03) << 6;
10992 /* inst.operands[i] was set up by parse_address. Encode it into a
10993 Thumb32 format load or store instruction. Reject forms that cannot
10994 be used with such instructions. If is_t is true, reject forms that
10995 cannot be used with a T instruction; if is_d is true, reject forms
10996 that cannot be used with a D instruction. If it is a store insn,
10997 reject PC in Rn. */
11000 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
11002 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
11004 constraint (!inst
.operands
[i
].isreg
,
11005 _("Instruction does not support =N addresses"));
11007 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
11008 if (inst
.operands
[i
].immisreg
)
11010 constraint (is_pc
, BAD_PC_ADDRESSING
);
11011 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
11012 constraint (inst
.operands
[i
].negative
,
11013 _("Thumb does not support negative register indexing"));
11014 constraint (inst
.operands
[i
].postind
,
11015 _("Thumb does not support register post-indexing"));
11016 constraint (inst
.operands
[i
].writeback
,
11017 _("Thumb does not support register indexing with writeback"));
11018 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
11019 _("Thumb supports only LSL in shifted register indexing"));
11021 inst
.instruction
|= inst
.operands
[i
].imm
;
11022 if (inst
.operands
[i
].shifted
)
11024 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11025 _("expression too complex"));
11026 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11027 || inst
.relocs
[0].exp
.X_add_number
> 3,
11028 _("shift out of range"));
11029 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11031 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11033 else if (inst
.operands
[i
].preind
)
11035 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
11036 constraint (is_t
&& inst
.operands
[i
].writeback
,
11037 _("cannot use writeback with this instruction"));
11038 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
11039 BAD_PC_ADDRESSING
);
11043 inst
.instruction
|= 0x01000000;
11044 if (inst
.operands
[i
].writeback
)
11045 inst
.instruction
|= 0x00200000;
11049 inst
.instruction
|= 0x00000c00;
11050 if (inst
.operands
[i
].writeback
)
11051 inst
.instruction
|= 0x00000100;
11053 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11055 else if (inst
.operands
[i
].postind
)
11057 gas_assert (inst
.operands
[i
].writeback
);
11058 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11059 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11062 inst
.instruction
|= 0x00200000;
11064 inst
.instruction
|= 0x00000900;
11065 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11067 else /* unindexed - only for coprocessor */
11068 inst
.error
= _("instruction does not accept unindexed addressing");
11071 /* Table of Thumb instructions which exist in both 16- and 32-bit
11072 encodings (the latter only in post-V6T2 cores). The index is the
11073 value used in the insns table below. When there is more than one
11074 possible 16-bit encoding for the instruction, this table always
11076 Also contains several pseudo-instructions used during relaxation. */
11077 #define T16_32_TAB \
11078 X(_adc, 4140, eb400000), \
11079 X(_adcs, 4140, eb500000), \
11080 X(_add, 1c00, eb000000), \
11081 X(_adds, 1c00, eb100000), \
11082 X(_addi, 0000, f1000000), \
11083 X(_addis, 0000, f1100000), \
11084 X(_add_pc,000f, f20f0000), \
11085 X(_add_sp,000d, f10d0000), \
11086 X(_adr, 000f, f20f0000), \
11087 X(_and, 4000, ea000000), \
11088 X(_ands, 4000, ea100000), \
11089 X(_asr, 1000, fa40f000), \
11090 X(_asrs, 1000, fa50f000), \
11091 X(_b, e000, f000b000), \
11092 X(_bcond, d000, f0008000), \
11093 X(_bf, 0000, f040e001), \
11094 X(_bfcsel,0000, f000e001), \
11095 X(_bfx, 0000, f060e001), \
11096 X(_bfl, 0000, f000c001), \
11097 X(_bflx, 0000, f070e001), \
11098 X(_bic, 4380, ea200000), \
11099 X(_bics, 4380, ea300000), \
11100 X(_cmn, 42c0, eb100f00), \
11101 X(_cmp, 2800, ebb00f00), \
11102 X(_cpsie, b660, f3af8400), \
11103 X(_cpsid, b670, f3af8600), \
11104 X(_cpy, 4600, ea4f0000), \
11105 X(_dec_sp,80dd, f1ad0d00), \
11106 X(_dls, 0000, f040e001), \
11107 X(_eor, 4040, ea800000), \
11108 X(_eors, 4040, ea900000), \
11109 X(_inc_sp,00dd, f10d0d00), \
11110 X(_ldmia, c800, e8900000), \
11111 X(_ldr, 6800, f8500000), \
11112 X(_ldrb, 7800, f8100000), \
11113 X(_ldrh, 8800, f8300000), \
11114 X(_ldrsb, 5600, f9100000), \
11115 X(_ldrsh, 5e00, f9300000), \
11116 X(_ldr_pc,4800, f85f0000), \
11117 X(_ldr_pc2,4800, f85f0000), \
11118 X(_ldr_sp,9800, f85d0000), \
11119 X(_le, 0000, f00fc001), \
11120 X(_lsl, 0000, fa00f000), \
11121 X(_lsls, 0000, fa10f000), \
11122 X(_lsr, 0800, fa20f000), \
11123 X(_lsrs, 0800, fa30f000), \
11124 X(_mov, 2000, ea4f0000), \
11125 X(_movs, 2000, ea5f0000), \
11126 X(_mul, 4340, fb00f000), \
11127 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11128 X(_mvn, 43c0, ea6f0000), \
11129 X(_mvns, 43c0, ea7f0000), \
11130 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11131 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11132 X(_orr, 4300, ea400000), \
11133 X(_orrs, 4300, ea500000), \
11134 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11135 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11136 X(_rev, ba00, fa90f080), \
11137 X(_rev16, ba40, fa90f090), \
11138 X(_revsh, bac0, fa90f0b0), \
11139 X(_ror, 41c0, fa60f000), \
11140 X(_rors, 41c0, fa70f000), \
11141 X(_sbc, 4180, eb600000), \
11142 X(_sbcs, 4180, eb700000), \
11143 X(_stmia, c000, e8800000), \
11144 X(_str, 6000, f8400000), \
11145 X(_strb, 7000, f8000000), \
11146 X(_strh, 8000, f8200000), \
11147 X(_str_sp,9000, f84d0000), \
11148 X(_sub, 1e00, eba00000), \
11149 X(_subs, 1e00, ebb00000), \
11150 X(_subi, 8000, f1a00000), \
11151 X(_subis, 8000, f1b00000), \
11152 X(_sxtb, b240, fa4ff080), \
11153 X(_sxth, b200, fa0ff080), \
11154 X(_tst, 4200, ea100f00), \
11155 X(_uxtb, b2c0, fa5ff080), \
11156 X(_uxth, b280, fa1ff080), \
11157 X(_nop, bf00, f3af8000), \
11158 X(_yield, bf10, f3af8001), \
11159 X(_wfe, bf20, f3af8002), \
11160 X(_wfi, bf30, f3af8003), \
11161 X(_wls, 0000, f040c001), \
11162 X(_sev, bf40, f3af8004), \
11163 X(_sevl, bf50, f3af8005), \
11164 X(_udf, de00, f7f0a000)
11166 /* To catch errors in encoding functions, the codes are all offset by
11167 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11168 as 16-bit instructions. */
11169 #define X(a,b,c) T_MNEM##a
11170 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11173 #define X(a,b,c) 0x##b
11174 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11175 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11178 #define X(a,b,c) 0x##c
11179 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11180 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11181 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11185 /* Thumb instruction encoders, in alphabetical order. */
11187 /* ADDW or SUBW. */
11190 do_t_add_sub_w (void)
11194 Rd
= inst
.operands
[0].reg
;
11195 Rn
= inst
.operands
[1].reg
;
11197 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11198 is the SP-{plus,minus}-immediate form of the instruction. */
11200 constraint (Rd
== REG_PC
, BAD_PC
);
11202 reject_bad_reg (Rd
);
11204 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11205 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11208 /* Parse an add or subtract instruction. We get here with inst.instruction
11209 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11212 do_t_add_sub (void)
11216 Rd
= inst
.operands
[0].reg
;
11217 Rs
= (inst
.operands
[1].present
11218 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11219 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11222 set_pred_insn_type_last ();
11224 if (unified_syntax
)
11227 bfd_boolean narrow
;
11230 flags
= (inst
.instruction
== T_MNEM_adds
11231 || inst
.instruction
== T_MNEM_subs
);
11233 narrow
= !in_pred_block ();
11235 narrow
= in_pred_block ();
11236 if (!inst
.operands
[2].isreg
)
11240 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11241 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11243 add
= (inst
.instruction
== T_MNEM_add
11244 || inst
.instruction
== T_MNEM_adds
);
11246 if (inst
.size_req
!= 4)
11248 /* Attempt to use a narrow opcode, with relaxation if
11250 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11251 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11252 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11253 opcode
= T_MNEM_add_sp
;
11254 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11255 opcode
= T_MNEM_add_pc
;
11256 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11259 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11261 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11265 inst
.instruction
= THUMB_OP16(opcode
);
11266 inst
.instruction
|= (Rd
<< 4) | Rs
;
11267 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11268 || (inst
.relocs
[0].type
11269 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11271 if (inst
.size_req
== 2)
11272 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11274 inst
.relax
= opcode
;
11278 constraint (inst
.size_req
== 2, BAD_HIREG
);
11280 if (inst
.size_req
== 4
11281 || (inst
.size_req
!= 2 && !opcode
))
11283 constraint ((inst
.relocs
[0].type
11284 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11285 && (inst
.relocs
[0].type
11286 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11287 THUMB1_RELOC_ONLY
);
11290 constraint (add
, BAD_PC
);
11291 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11292 _("only SUBS PC, LR, #const allowed"));
11293 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11294 _("expression too complex"));
11295 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11296 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11297 _("immediate value out of range"));
11298 inst
.instruction
= T2_SUBS_PC_LR
11299 | inst
.relocs
[0].exp
.X_add_number
;
11300 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11303 else if (Rs
== REG_PC
)
11305 /* Always use addw/subw. */
11306 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11307 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11311 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11312 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11315 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11317 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11319 inst
.instruction
|= Rd
<< 8;
11320 inst
.instruction
|= Rs
<< 16;
11325 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11326 unsigned int shift
= inst
.operands
[2].shift_kind
;
11328 Rn
= inst
.operands
[2].reg
;
11329 /* See if we can do this with a 16-bit instruction. */
11330 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11332 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11337 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11338 || inst
.instruction
== T_MNEM_add
)
11340 : T_OPCODE_SUB_R3
);
11341 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11345 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11347 /* Thumb-1 cores (except v6-M) require at least one high
11348 register in a narrow non flag setting add. */
11349 if (Rd
> 7 || Rn
> 7
11350 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11351 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11358 inst
.instruction
= T_OPCODE_ADD_HI
;
11359 inst
.instruction
|= (Rd
& 8) << 4;
11360 inst
.instruction
|= (Rd
& 7);
11361 inst
.instruction
|= Rn
<< 3;
11367 constraint (Rd
== REG_PC
, BAD_PC
);
11368 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11369 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11370 constraint (Rs
== REG_PC
, BAD_PC
);
11371 reject_bad_reg (Rn
);
11373 /* If we get here, it can't be done in 16 bits. */
11374 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11375 _("shift must be constant"));
11376 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11377 inst
.instruction
|= Rd
<< 8;
11378 inst
.instruction
|= Rs
<< 16;
11379 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11380 _("shift value over 3 not allowed in thumb mode"));
11381 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11382 _("only LSL shift allowed in thumb mode"));
11383 encode_thumb32_shifted_operand (2);
11388 constraint (inst
.instruction
== T_MNEM_adds
11389 || inst
.instruction
== T_MNEM_subs
,
11392 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11394 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11395 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11398 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11399 ? 0x0000 : 0x8000);
11400 inst
.instruction
|= (Rd
<< 4) | Rs
;
11401 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11405 Rn
= inst
.operands
[2].reg
;
11406 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11408 /* We now have Rd, Rs, and Rn set to registers. */
11409 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11411 /* Can't do this for SUB. */
11412 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11413 inst
.instruction
= T_OPCODE_ADD_HI
;
11414 inst
.instruction
|= (Rd
& 8) << 4;
11415 inst
.instruction
|= (Rd
& 7);
11417 inst
.instruction
|= Rn
<< 3;
11419 inst
.instruction
|= Rs
<< 3;
11421 constraint (1, _("dest must overlap one source register"));
11425 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11426 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11427 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11437 Rd
= inst
.operands
[0].reg
;
11438 reject_bad_reg (Rd
);
11440 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11442 /* Defer to section relaxation. */
11443 inst
.relax
= inst
.instruction
;
11444 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11445 inst
.instruction
|= Rd
<< 4;
11447 else if (unified_syntax
&& inst
.size_req
!= 2)
11449 /* Generate a 32-bit opcode. */
11450 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11451 inst
.instruction
|= Rd
<< 8;
11452 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11453 inst
.relocs
[0].pc_rel
= 1;
11457 /* Generate a 16-bit opcode. */
11458 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11459 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11460 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11461 inst
.relocs
[0].pc_rel
= 1;
11462 inst
.instruction
|= Rd
<< 4;
11465 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11466 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11467 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11468 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11469 inst
.relocs
[0].exp
.X_add_number
+= 1;
11472 /* Arithmetic instructions for which there is just one 16-bit
11473 instruction encoding, and it allows only two low registers.
11474 For maximal compatibility with ARM syntax, we allow three register
11475 operands even when Thumb-32 instructions are not available, as long
11476 as the first two are identical. For instance, both "sbc r0,r1" and
11477 "sbc r0,r0,r1" are allowed. */
11483 Rd
= inst
.operands
[0].reg
;
11484 Rs
= (inst
.operands
[1].present
11485 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11486 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11487 Rn
= inst
.operands
[2].reg
;
11489 reject_bad_reg (Rd
);
11490 reject_bad_reg (Rs
);
11491 if (inst
.operands
[2].isreg
)
11492 reject_bad_reg (Rn
);
11494 if (unified_syntax
)
11496 if (!inst
.operands
[2].isreg
)
11498 /* For an immediate, we always generate a 32-bit opcode;
11499 section relaxation will shrink it later if possible. */
11500 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11501 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11502 inst
.instruction
|= Rd
<< 8;
11503 inst
.instruction
|= Rs
<< 16;
11504 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11508 bfd_boolean narrow
;
11510 /* See if we can do this with a 16-bit instruction. */
11511 if (THUMB_SETS_FLAGS (inst
.instruction
))
11512 narrow
= !in_pred_block ();
11514 narrow
= in_pred_block ();
11516 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11518 if (inst
.operands
[2].shifted
)
11520 if (inst
.size_req
== 4)
11526 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11527 inst
.instruction
|= Rd
;
11528 inst
.instruction
|= Rn
<< 3;
11532 /* If we get here, it can't be done in 16 bits. */
11533 constraint (inst
.operands
[2].shifted
11534 && inst
.operands
[2].immisreg
,
11535 _("shift must be constant"));
11536 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11537 inst
.instruction
|= Rd
<< 8;
11538 inst
.instruction
|= Rs
<< 16;
11539 encode_thumb32_shifted_operand (2);
11544 /* On its face this is a lie - the instruction does set the
11545 flags. However, the only supported mnemonic in this mode
11546 says it doesn't. */
11547 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11549 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11550 _("unshifted register required"));
11551 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11552 constraint (Rd
!= Rs
,
11553 _("dest and source1 must be the same register"));
11555 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11556 inst
.instruction
|= Rd
;
11557 inst
.instruction
|= Rn
<< 3;
11561 /* Similarly, but for instructions where the arithmetic operation is
11562 commutative, so we can allow either of them to be different from
11563 the destination operand in a 16-bit instruction. For instance, all
11564 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11571 Rd
= inst
.operands
[0].reg
;
11572 Rs
= (inst
.operands
[1].present
11573 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11574 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11575 Rn
= inst
.operands
[2].reg
;
11577 reject_bad_reg (Rd
);
11578 reject_bad_reg (Rs
);
11579 if (inst
.operands
[2].isreg
)
11580 reject_bad_reg (Rn
);
11582 if (unified_syntax
)
11584 if (!inst
.operands
[2].isreg
)
11586 /* For an immediate, we always generate a 32-bit opcode;
11587 section relaxation will shrink it later if possible. */
11588 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11589 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11590 inst
.instruction
|= Rd
<< 8;
11591 inst
.instruction
|= Rs
<< 16;
11592 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11596 bfd_boolean narrow
;
11598 /* See if we can do this with a 16-bit instruction. */
11599 if (THUMB_SETS_FLAGS (inst
.instruction
))
11600 narrow
= !in_pred_block ();
11602 narrow
= in_pred_block ();
11604 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11606 if (inst
.operands
[2].shifted
)
11608 if (inst
.size_req
== 4)
11615 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11616 inst
.instruction
|= Rd
;
11617 inst
.instruction
|= Rn
<< 3;
11622 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11623 inst
.instruction
|= Rd
;
11624 inst
.instruction
|= Rs
<< 3;
11629 /* If we get here, it can't be done in 16 bits. */
11630 constraint (inst
.operands
[2].shifted
11631 && inst
.operands
[2].immisreg
,
11632 _("shift must be constant"));
11633 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11634 inst
.instruction
|= Rd
<< 8;
11635 inst
.instruction
|= Rs
<< 16;
11636 encode_thumb32_shifted_operand (2);
11641 /* On its face this is a lie - the instruction does set the
11642 flags. However, the only supported mnemonic in this mode
11643 says it doesn't. */
11644 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11646 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11647 _("unshifted register required"));
11648 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11650 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11651 inst
.instruction
|= Rd
;
11654 inst
.instruction
|= Rn
<< 3;
11656 inst
.instruction
|= Rs
<< 3;
11658 constraint (1, _("dest must overlap one source register"));
11666 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11667 constraint (msb
> 32, _("bit-field extends past end of register"));
11668 /* The instruction encoding stores the LSB and MSB,
11669 not the LSB and width. */
11670 Rd
= inst
.operands
[0].reg
;
11671 reject_bad_reg (Rd
);
11672 inst
.instruction
|= Rd
<< 8;
11673 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11674 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11675 inst
.instruction
|= msb
- 1;
11684 Rd
= inst
.operands
[0].reg
;
11685 reject_bad_reg (Rd
);
11687 /* #0 in second position is alternative syntax for bfc, which is
11688 the same instruction but with REG_PC in the Rm field. */
11689 if (!inst
.operands
[1].isreg
)
11693 Rn
= inst
.operands
[1].reg
;
11694 reject_bad_reg (Rn
);
11697 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11698 constraint (msb
> 32, _("bit-field extends past end of register"));
11699 /* The instruction encoding stores the LSB and MSB,
11700 not the LSB and width. */
11701 inst
.instruction
|= Rd
<< 8;
11702 inst
.instruction
|= Rn
<< 16;
11703 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11704 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11705 inst
.instruction
|= msb
- 1;
11713 Rd
= inst
.operands
[0].reg
;
11714 Rn
= inst
.operands
[1].reg
;
11716 reject_bad_reg (Rd
);
11717 reject_bad_reg (Rn
);
11719 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11720 _("bit-field extends past end of register"));
11721 inst
.instruction
|= Rd
<< 8;
11722 inst
.instruction
|= Rn
<< 16;
11723 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11724 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11725 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11728 /* ARM V5 Thumb BLX (argument parse)
11729 BLX <target_addr> which is BLX(1)
11730 BLX <Rm> which is BLX(2)
11731 Unfortunately, there are two different opcodes for this mnemonic.
11732 So, the insns[].value is not used, and the code here zaps values
11733 into inst.instruction.
11735 ??? How to take advantage of the additional two bits of displacement
11736 available in Thumb32 mode? Need new relocation? */
11741 set_pred_insn_type_last ();
11743 if (inst
.operands
[0].isreg
)
11745 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11746 /* We have a register, so this is BLX(2). */
11747 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11751 /* No register. This must be BLX(1). */
11752 inst
.instruction
= 0xf000e800;
11753 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11762 bfd_reloc_code_real_type reloc
;
11765 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
11767 if (in_pred_block ())
11769 /* Conditional branches inside IT blocks are encoded as unconditional
11771 cond
= COND_ALWAYS
;
11776 if (cond
!= COND_ALWAYS
)
11777 opcode
= T_MNEM_bcond
;
11779 opcode
= inst
.instruction
;
11782 && (inst
.size_req
== 4
11783 || (inst
.size_req
!= 2
11784 && (inst
.operands
[0].hasreloc
11785 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
11787 inst
.instruction
= THUMB_OP32(opcode
);
11788 if (cond
== COND_ALWAYS
)
11789 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11792 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11793 _("selected architecture does not support "
11794 "wide conditional branch instruction"));
11796 gas_assert (cond
!= 0xF);
11797 inst
.instruction
|= cond
<< 22;
11798 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11803 inst
.instruction
= THUMB_OP16(opcode
);
11804 if (cond
== COND_ALWAYS
)
11805 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11808 inst
.instruction
|= cond
<< 8;
11809 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11811 /* Allow section relaxation. */
11812 if (unified_syntax
&& inst
.size_req
!= 2)
11813 inst
.relax
= opcode
;
11815 inst
.relocs
[0].type
= reloc
;
11816 inst
.relocs
[0].pc_rel
= 1;
11819 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11820 between the two is the maximum immediate allowed - which is passed in
11823 do_t_bkpt_hlt1 (int range
)
11825 constraint (inst
.cond
!= COND_ALWAYS
,
11826 _("instruction is always unconditional"));
11827 if (inst
.operands
[0].present
)
11829 constraint (inst
.operands
[0].imm
> range
,
11830 _("immediate value out of range"));
11831 inst
.instruction
|= inst
.operands
[0].imm
;
11834 set_pred_insn_type (NEUTRAL_IT_INSN
);
11840 do_t_bkpt_hlt1 (63);
11846 do_t_bkpt_hlt1 (255);
11850 do_t_branch23 (void)
11852 set_pred_insn_type_last ();
11853 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11855 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11856 this file. We used to simply ignore the PLT reloc type here --
11857 the branch encoding is now needed to deal with TLSCALL relocs.
11858 So if we see a PLT reloc now, put it back to how it used to be to
11859 keep the preexisting behaviour. */
11860 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
11861 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11863 #if defined(OBJ_COFF)
11864 /* If the destination of the branch is a defined symbol which does not have
11865 the THUMB_FUNC attribute, then we must be calling a function which has
11866 the (interfacearm) attribute. We look for the Thumb entry point to that
11867 function and change the branch to refer to that function instead. */
11868 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
11869 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11870 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11871 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11872 inst
.relocs
[0].exp
.X_add_symbol
11873 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
11880 set_pred_insn_type_last ();
11881 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11882 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11883 should cause the alignment to be checked once it is known. This is
11884 because BX PC only works if the instruction is word aligned. */
11892 set_pred_insn_type_last ();
11893 Rm
= inst
.operands
[0].reg
;
11894 reject_bad_reg (Rm
);
11895 inst
.instruction
|= Rm
<< 16;
11904 Rd
= inst
.operands
[0].reg
;
11905 Rm
= inst
.operands
[1].reg
;
11907 reject_bad_reg (Rd
);
11908 reject_bad_reg (Rm
);
11910 inst
.instruction
|= Rd
<< 8;
11911 inst
.instruction
|= Rm
<< 16;
11912 inst
.instruction
|= Rm
;
11918 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11924 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11925 inst
.instruction
|= inst
.operands
[0].imm
;
11931 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11933 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11934 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11936 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11937 inst
.instruction
= 0xf3af8000;
11938 inst
.instruction
|= imod
<< 9;
11939 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11940 if (inst
.operands
[1].present
)
11941 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11945 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11946 && (inst
.operands
[0].imm
& 4),
11947 _("selected processor does not support 'A' form "
11948 "of this instruction"));
11949 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11950 _("Thumb does not support the 2-argument "
11951 "form of this instruction"));
11952 inst
.instruction
|= inst
.operands
[0].imm
;
11956 /* THUMB CPY instruction (argument parse). */
11961 if (inst
.size_req
== 4)
11963 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11964 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11965 inst
.instruction
|= inst
.operands
[1].reg
;
11969 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11970 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11971 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11978 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11979 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11980 inst
.instruction
|= inst
.operands
[0].reg
;
11981 inst
.relocs
[0].pc_rel
= 1;
11982 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11988 inst
.instruction
|= inst
.operands
[0].imm
;
11994 unsigned Rd
, Rn
, Rm
;
11996 Rd
= inst
.operands
[0].reg
;
11997 Rn
= (inst
.operands
[1].present
11998 ? inst
.operands
[1].reg
: Rd
);
11999 Rm
= inst
.operands
[2].reg
;
12001 reject_bad_reg (Rd
);
12002 reject_bad_reg (Rn
);
12003 reject_bad_reg (Rm
);
12005 inst
.instruction
|= Rd
<< 8;
12006 inst
.instruction
|= Rn
<< 16;
12007 inst
.instruction
|= Rm
;
12013 if (unified_syntax
&& inst
.size_req
== 4)
12014 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12016 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12022 unsigned int cond
= inst
.operands
[0].imm
;
12024 set_pred_insn_type (IT_INSN
);
12025 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
12026 now_pred
.cc
= cond
;
12027 now_pred
.warn_deprecated
= FALSE
;
12028 now_pred
.type
= SCALAR_PRED
;
12030 /* If the condition is a negative condition, invert the mask. */
12031 if ((cond
& 0x1) == 0x0)
12033 unsigned int mask
= inst
.instruction
& 0x000f;
12035 if ((mask
& 0x7) == 0)
12037 /* No conversion needed. */
12038 now_pred
.block_length
= 1;
12040 else if ((mask
& 0x3) == 0)
12043 now_pred
.block_length
= 2;
12045 else if ((mask
& 0x1) == 0)
12048 now_pred
.block_length
= 3;
12053 now_pred
.block_length
= 4;
12056 inst
.instruction
&= 0xfff0;
12057 inst
.instruction
|= mask
;
12060 inst
.instruction
|= cond
<< 4;
12063 /* Helper function used for both push/pop and ldm/stm. */
12065 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
12066 bfd_boolean writeback
)
12068 bfd_boolean load
, store
;
12070 gas_assert (base
!= -1 || !do_io
);
12071 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12072 store
= do_io
&& !load
;
12074 if (mask
& (1 << 13))
12075 inst
.error
= _("SP not allowed in register list");
12077 if (do_io
&& (mask
& (1 << base
)) != 0
12079 inst
.error
= _("having the base register in the register list when "
12080 "using write back is UNPREDICTABLE");
12084 if (mask
& (1 << 15))
12086 if (mask
& (1 << 14))
12087 inst
.error
= _("LR and PC should not both be in register list");
12089 set_pred_insn_type_last ();
12094 if (mask
& (1 << 15))
12095 inst
.error
= _("PC not allowed in register list");
12098 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12100 /* Single register transfers implemented as str/ldr. */
12103 if (inst
.instruction
& (1 << 23))
12104 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12106 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12110 if (inst
.instruction
& (1 << 23))
12111 inst
.instruction
= 0x00800000; /* ia -> [base] */
12113 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12116 inst
.instruction
|= 0xf8400000;
12118 inst
.instruction
|= 0x00100000;
12120 mask
= ffs (mask
) - 1;
12123 else if (writeback
)
12124 inst
.instruction
|= WRITE_BACK
;
12126 inst
.instruction
|= mask
;
12128 inst
.instruction
|= base
<< 16;
12134 /* This really doesn't seem worth it. */
12135 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12136 _("expression too complex"));
12137 constraint (inst
.operands
[1].writeback
,
12138 _("Thumb load/store multiple does not support {reglist}^"));
12140 if (unified_syntax
)
12142 bfd_boolean narrow
;
12146 /* See if we can use a 16-bit instruction. */
12147 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12148 && inst
.size_req
!= 4
12149 && !(inst
.operands
[1].imm
& ~0xff))
12151 mask
= 1 << inst
.operands
[0].reg
;
12153 if (inst
.operands
[0].reg
<= 7)
12155 if (inst
.instruction
== T_MNEM_stmia
12156 ? inst
.operands
[0].writeback
12157 : (inst
.operands
[0].writeback
12158 == !(inst
.operands
[1].imm
& mask
)))
12160 if (inst
.instruction
== T_MNEM_stmia
12161 && (inst
.operands
[1].imm
& mask
)
12162 && (inst
.operands
[1].imm
& (mask
- 1)))
12163 as_warn (_("value stored for r%d is UNKNOWN"),
12164 inst
.operands
[0].reg
);
12166 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12167 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12168 inst
.instruction
|= inst
.operands
[1].imm
;
12171 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12173 /* This means 1 register in reg list one of 3 situations:
12174 1. Instruction is stmia, but without writeback.
12175 2. lmdia without writeback, but with Rn not in
12177 3. ldmia with writeback, but with Rn in reglist.
12178 Case 3 is UNPREDICTABLE behaviour, so we handle
12179 case 1 and 2 which can be converted into a 16-bit
12180 str or ldr. The SP cases are handled below. */
12181 unsigned long opcode
;
12182 /* First, record an error for Case 3. */
12183 if (inst
.operands
[1].imm
& mask
12184 && inst
.operands
[0].writeback
)
12186 _("having the base register in the register list when "
12187 "using write back is UNPREDICTABLE");
12189 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12191 inst
.instruction
= THUMB_OP16 (opcode
);
12192 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12193 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12197 else if (inst
.operands
[0] .reg
== REG_SP
)
12199 if (inst
.operands
[0].writeback
)
12202 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12203 ? T_MNEM_push
: T_MNEM_pop
);
12204 inst
.instruction
|= inst
.operands
[1].imm
;
12207 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12210 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12211 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12212 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12220 if (inst
.instruction
< 0xffff)
12221 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12223 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
12224 inst
.operands
[1].imm
,
12225 inst
.operands
[0].writeback
);
12230 constraint (inst
.operands
[0].reg
> 7
12231 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12232 constraint (inst
.instruction
!= T_MNEM_ldmia
12233 && inst
.instruction
!= T_MNEM_stmia
,
12234 _("Thumb-2 instruction only valid in unified syntax"));
12235 if (inst
.instruction
== T_MNEM_stmia
)
12237 if (!inst
.operands
[0].writeback
)
12238 as_warn (_("this instruction will write back the base register"));
12239 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12240 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12241 as_warn (_("value stored for r%d is UNKNOWN"),
12242 inst
.operands
[0].reg
);
12246 if (!inst
.operands
[0].writeback
12247 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12248 as_warn (_("this instruction will write back the base register"));
12249 else if (inst
.operands
[0].writeback
12250 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12251 as_warn (_("this instruction will not write back the base register"));
12254 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12255 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12256 inst
.instruction
|= inst
.operands
[1].imm
;
12263 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12264 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12265 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12266 || inst
.operands
[1].negative
,
12269 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12271 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12272 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12273 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12279 if (!inst
.operands
[1].present
)
12281 constraint (inst
.operands
[0].reg
== REG_LR
,
12282 _("r14 not allowed as first register "
12283 "when second register is omitted"));
12284 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12286 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12289 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12290 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12291 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12297 unsigned long opcode
;
12300 if (inst
.operands
[0].isreg
12301 && !inst
.operands
[0].preind
12302 && inst
.operands
[0].reg
== REG_PC
)
12303 set_pred_insn_type_last ();
12305 opcode
= inst
.instruction
;
12306 if (unified_syntax
)
12308 if (!inst
.operands
[1].isreg
)
12310 if (opcode
<= 0xffff)
12311 inst
.instruction
= THUMB_OP32 (opcode
);
12312 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12315 if (inst
.operands
[1].isreg
12316 && !inst
.operands
[1].writeback
12317 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12318 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12319 && opcode
<= 0xffff
12320 && inst
.size_req
!= 4)
12322 /* Insn may have a 16-bit form. */
12323 Rn
= inst
.operands
[1].reg
;
12324 if (inst
.operands
[1].immisreg
)
12326 inst
.instruction
= THUMB_OP16 (opcode
);
12328 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12330 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12331 reject_bad_reg (inst
.operands
[1].imm
);
12333 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12334 && opcode
!= T_MNEM_ldrsb
)
12335 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12336 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12343 if (inst
.relocs
[0].pc_rel
)
12344 opcode
= T_MNEM_ldr_pc2
;
12346 opcode
= T_MNEM_ldr_pc
;
12350 if (opcode
== T_MNEM_ldr
)
12351 opcode
= T_MNEM_ldr_sp
;
12353 opcode
= T_MNEM_str_sp
;
12355 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12359 inst
.instruction
= inst
.operands
[0].reg
;
12360 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12362 inst
.instruction
|= THUMB_OP16 (opcode
);
12363 if (inst
.size_req
== 2)
12364 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12366 inst
.relax
= opcode
;
12370 /* Definitely a 32-bit variant. */
12372 /* Warning for Erratum 752419. */
12373 if (opcode
== T_MNEM_ldr
12374 && inst
.operands
[0].reg
== REG_SP
12375 && inst
.operands
[1].writeback
== 1
12376 && !inst
.operands
[1].immisreg
)
12378 if (no_cpu_selected ()
12379 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12380 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12381 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12382 as_warn (_("This instruction may be unpredictable "
12383 "if executed on M-profile cores "
12384 "with interrupts enabled."));
12387 /* Do some validations regarding addressing modes. */
12388 if (inst
.operands
[1].immisreg
)
12389 reject_bad_reg (inst
.operands
[1].imm
);
12391 constraint (inst
.operands
[1].writeback
== 1
12392 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12395 inst
.instruction
= THUMB_OP32 (opcode
);
12396 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12397 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12398 check_ldr_r15_aligned ();
12402 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12404 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12406 /* Only [Rn,Rm] is acceptable. */
12407 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12408 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12409 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12410 || inst
.operands
[1].negative
,
12411 _("Thumb does not support this addressing mode"));
12412 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12416 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12417 if (!inst
.operands
[1].isreg
)
12418 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12421 constraint (!inst
.operands
[1].preind
12422 || inst
.operands
[1].shifted
12423 || inst
.operands
[1].writeback
,
12424 _("Thumb does not support this addressing mode"));
12425 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12427 constraint (inst
.instruction
& 0x0600,
12428 _("byte or halfword not valid for base register"));
12429 constraint (inst
.operands
[1].reg
== REG_PC
12430 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12431 _("r15 based store not allowed"));
12432 constraint (inst
.operands
[1].immisreg
,
12433 _("invalid base register for register offset"));
12435 if (inst
.operands
[1].reg
== REG_PC
)
12436 inst
.instruction
= T_OPCODE_LDR_PC
;
12437 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12438 inst
.instruction
= T_OPCODE_LDR_SP
;
12440 inst
.instruction
= T_OPCODE_STR_SP
;
12442 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12443 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12447 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12448 if (!inst
.operands
[1].immisreg
)
12450 /* Immediate offset. */
12451 inst
.instruction
|= inst
.operands
[0].reg
;
12452 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12453 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12457 /* Register offset. */
12458 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12459 constraint (inst
.operands
[1].negative
,
12460 _("Thumb does not support this addressing mode"));
12463 switch (inst
.instruction
)
12465 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12466 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12467 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12468 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12469 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12470 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12471 case 0x5600 /* ldrsb */:
12472 case 0x5e00 /* ldrsh */: break;
12476 inst
.instruction
|= inst
.operands
[0].reg
;
12477 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12478 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12484 if (!inst
.operands
[1].present
)
12486 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12487 constraint (inst
.operands
[0].reg
== REG_LR
,
12488 _("r14 not allowed here"));
12489 constraint (inst
.operands
[0].reg
== REG_R12
,
12490 _("r12 not allowed here"));
12493 if (inst
.operands
[2].writeback
12494 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12495 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12496 as_warn (_("base register written back, and overlaps "
12497 "one of transfer registers"));
12499 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12500 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12501 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12507 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12508 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12514 unsigned Rd
, Rn
, Rm
, Ra
;
12516 Rd
= inst
.operands
[0].reg
;
12517 Rn
= inst
.operands
[1].reg
;
12518 Rm
= inst
.operands
[2].reg
;
12519 Ra
= inst
.operands
[3].reg
;
12521 reject_bad_reg (Rd
);
12522 reject_bad_reg (Rn
);
12523 reject_bad_reg (Rm
);
12524 reject_bad_reg (Ra
);
12526 inst
.instruction
|= Rd
<< 8;
12527 inst
.instruction
|= Rn
<< 16;
12528 inst
.instruction
|= Rm
;
12529 inst
.instruction
|= Ra
<< 12;
12535 unsigned RdLo
, RdHi
, Rn
, Rm
;
12537 RdLo
= inst
.operands
[0].reg
;
12538 RdHi
= inst
.operands
[1].reg
;
12539 Rn
= inst
.operands
[2].reg
;
12540 Rm
= inst
.operands
[3].reg
;
12542 reject_bad_reg (RdLo
);
12543 reject_bad_reg (RdHi
);
12544 reject_bad_reg (Rn
);
12545 reject_bad_reg (Rm
);
12547 inst
.instruction
|= RdLo
<< 12;
12548 inst
.instruction
|= RdHi
<< 8;
12549 inst
.instruction
|= Rn
<< 16;
12550 inst
.instruction
|= Rm
;
12554 do_t_mov_cmp (void)
12558 Rn
= inst
.operands
[0].reg
;
12559 Rm
= inst
.operands
[1].reg
;
12562 set_pred_insn_type_last ();
12564 if (unified_syntax
)
12566 int r0off
= (inst
.instruction
== T_MNEM_mov
12567 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12568 unsigned long opcode
;
12569 bfd_boolean narrow
;
12570 bfd_boolean low_regs
;
12572 low_regs
= (Rn
<= 7 && Rm
<= 7);
12573 opcode
= inst
.instruction
;
12574 if (in_pred_block ())
12575 narrow
= opcode
!= T_MNEM_movs
;
12577 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12578 if (inst
.size_req
== 4
12579 || inst
.operands
[1].shifted
)
12582 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12583 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12584 && !inst
.operands
[1].shifted
12588 inst
.instruction
= T2_SUBS_PC_LR
;
12592 if (opcode
== T_MNEM_cmp
)
12594 constraint (Rn
== REG_PC
, BAD_PC
);
12597 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12599 warn_deprecated_sp (Rm
);
12600 /* R15 was documented as a valid choice for Rm in ARMv6,
12601 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12602 tools reject R15, so we do too. */
12603 constraint (Rm
== REG_PC
, BAD_PC
);
12606 reject_bad_reg (Rm
);
12608 else if (opcode
== T_MNEM_mov
12609 || opcode
== T_MNEM_movs
)
12611 if (inst
.operands
[1].isreg
)
12613 if (opcode
== T_MNEM_movs
)
12615 reject_bad_reg (Rn
);
12616 reject_bad_reg (Rm
);
12620 /* This is mov.n. */
12621 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
12622 && (Rm
== REG_SP
|| Rm
== REG_PC
))
12624 as_tsktsk (_("Use of r%u as a source register is "
12625 "deprecated when r%u is the destination "
12626 "register."), Rm
, Rn
);
12631 /* This is mov.w. */
12632 constraint (Rn
== REG_PC
, BAD_PC
);
12633 constraint (Rm
== REG_PC
, BAD_PC
);
12634 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12635 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12639 reject_bad_reg (Rn
);
12642 if (!inst
.operands
[1].isreg
)
12644 /* Immediate operand. */
12645 if (!in_pred_block () && opcode
== T_MNEM_mov
)
12647 if (low_regs
&& narrow
)
12649 inst
.instruction
= THUMB_OP16 (opcode
);
12650 inst
.instruction
|= Rn
<< 8;
12651 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12652 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12654 if (inst
.size_req
== 2)
12655 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12657 inst
.relax
= opcode
;
12662 constraint ((inst
.relocs
[0].type
12663 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
12664 && (inst
.relocs
[0].type
12665 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
12666 THUMB1_RELOC_ONLY
);
12668 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12669 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12670 inst
.instruction
|= Rn
<< r0off
;
12671 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12674 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12675 && (inst
.instruction
== T_MNEM_mov
12676 || inst
.instruction
== T_MNEM_movs
))
12678 /* Register shifts are encoded as separate shift instructions. */
12679 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12681 if (in_pred_block ())
12686 if (inst
.size_req
== 4)
12689 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12695 switch (inst
.operands
[1].shift_kind
)
12698 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12701 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12704 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12707 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12713 inst
.instruction
= opcode
;
12716 inst
.instruction
|= Rn
;
12717 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12722 inst
.instruction
|= CONDS_BIT
;
12724 inst
.instruction
|= Rn
<< 8;
12725 inst
.instruction
|= Rm
<< 16;
12726 inst
.instruction
|= inst
.operands
[1].imm
;
12731 /* Some mov with immediate shift have narrow variants.
12732 Register shifts are handled above. */
12733 if (low_regs
&& inst
.operands
[1].shifted
12734 && (inst
.instruction
== T_MNEM_mov
12735 || inst
.instruction
== T_MNEM_movs
))
12737 if (in_pred_block ())
12738 narrow
= (inst
.instruction
== T_MNEM_mov
);
12740 narrow
= (inst
.instruction
== T_MNEM_movs
);
12745 switch (inst
.operands
[1].shift_kind
)
12747 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12748 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12749 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12750 default: narrow
= FALSE
; break;
12756 inst
.instruction
|= Rn
;
12757 inst
.instruction
|= Rm
<< 3;
12758 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12762 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12763 inst
.instruction
|= Rn
<< r0off
;
12764 encode_thumb32_shifted_operand (1);
12768 switch (inst
.instruction
)
12771 /* In v4t or v5t a move of two lowregs produces unpredictable
12772 results. Don't allow this. */
12775 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12776 "MOV Rd, Rs with two low registers is not "
12777 "permitted on this architecture");
12778 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12782 inst
.instruction
= T_OPCODE_MOV_HR
;
12783 inst
.instruction
|= (Rn
& 0x8) << 4;
12784 inst
.instruction
|= (Rn
& 0x7);
12785 inst
.instruction
|= Rm
<< 3;
12789 /* We know we have low registers at this point.
12790 Generate LSLS Rd, Rs, #0. */
12791 inst
.instruction
= T_OPCODE_LSL_I
;
12792 inst
.instruction
|= Rn
;
12793 inst
.instruction
|= Rm
<< 3;
12799 inst
.instruction
= T_OPCODE_CMP_LR
;
12800 inst
.instruction
|= Rn
;
12801 inst
.instruction
|= Rm
<< 3;
12805 inst
.instruction
= T_OPCODE_CMP_HR
;
12806 inst
.instruction
|= (Rn
& 0x8) << 4;
12807 inst
.instruction
|= (Rn
& 0x7);
12808 inst
.instruction
|= Rm
<< 3;
12815 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12817 /* PR 10443: Do not silently ignore shifted operands. */
12818 constraint (inst
.operands
[1].shifted
,
12819 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12821 if (inst
.operands
[1].isreg
)
12823 if (Rn
< 8 && Rm
< 8)
12825 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12826 since a MOV instruction produces unpredictable results. */
12827 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12828 inst
.instruction
= T_OPCODE_ADD_I3
;
12830 inst
.instruction
= T_OPCODE_CMP_LR
;
12832 inst
.instruction
|= Rn
;
12833 inst
.instruction
|= Rm
<< 3;
12837 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12838 inst
.instruction
= T_OPCODE_MOV_HR
;
12840 inst
.instruction
= T_OPCODE_CMP_HR
;
12846 constraint (Rn
> 7,
12847 _("only lo regs allowed with immediate"));
12848 inst
.instruction
|= Rn
<< 8;
12849 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12860 top
= (inst
.instruction
& 0x00800000) != 0;
12861 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
12863 constraint (top
, _(":lower16: not allowed in this instruction"));
12864 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
12866 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
12868 constraint (!top
, _(":upper16: not allowed in this instruction"));
12869 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
12872 Rd
= inst
.operands
[0].reg
;
12873 reject_bad_reg (Rd
);
12875 inst
.instruction
|= Rd
<< 8;
12876 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
12878 imm
= inst
.relocs
[0].exp
.X_add_number
;
12879 inst
.instruction
|= (imm
& 0xf000) << 4;
12880 inst
.instruction
|= (imm
& 0x0800) << 15;
12881 inst
.instruction
|= (imm
& 0x0700) << 4;
12882 inst
.instruction
|= (imm
& 0x00ff);
12887 do_t_mvn_tst (void)
12891 Rn
= inst
.operands
[0].reg
;
12892 Rm
= inst
.operands
[1].reg
;
12894 if (inst
.instruction
== T_MNEM_cmp
12895 || inst
.instruction
== T_MNEM_cmn
)
12896 constraint (Rn
== REG_PC
, BAD_PC
);
12898 reject_bad_reg (Rn
);
12899 reject_bad_reg (Rm
);
12901 if (unified_syntax
)
12903 int r0off
= (inst
.instruction
== T_MNEM_mvn
12904 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12905 bfd_boolean narrow
;
12907 if (inst
.size_req
== 4
12908 || inst
.instruction
> 0xffff
12909 || inst
.operands
[1].shifted
12910 || Rn
> 7 || Rm
> 7)
12912 else if (inst
.instruction
== T_MNEM_cmn
12913 || inst
.instruction
== T_MNEM_tst
)
12915 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12916 narrow
= !in_pred_block ();
12918 narrow
= in_pred_block ();
12920 if (!inst
.operands
[1].isreg
)
12922 /* For an immediate, we always generate a 32-bit opcode;
12923 section relaxation will shrink it later if possible. */
12924 if (inst
.instruction
< 0xffff)
12925 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12926 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12927 inst
.instruction
|= Rn
<< r0off
;
12928 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12932 /* See if we can do this with a 16-bit instruction. */
12935 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12936 inst
.instruction
|= Rn
;
12937 inst
.instruction
|= Rm
<< 3;
12941 constraint (inst
.operands
[1].shifted
12942 && inst
.operands
[1].immisreg
,
12943 _("shift must be constant"));
12944 if (inst
.instruction
< 0xffff)
12945 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12946 inst
.instruction
|= Rn
<< r0off
;
12947 encode_thumb32_shifted_operand (1);
12953 constraint (inst
.instruction
> 0xffff
12954 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12955 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12956 _("unshifted register required"));
12957 constraint (Rn
> 7 || Rm
> 7,
12960 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12961 inst
.instruction
|= Rn
;
12962 inst
.instruction
|= Rm
<< 3;
12971 if (do_vfp_nsyn_mrs () == SUCCESS
)
12974 Rd
= inst
.operands
[0].reg
;
12975 reject_bad_reg (Rd
);
12976 inst
.instruction
|= Rd
<< 8;
12978 if (inst
.operands
[1].isreg
)
12980 unsigned br
= inst
.operands
[1].reg
;
12981 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12982 as_bad (_("bad register for mrs"));
12984 inst
.instruction
|= br
& (0xf << 16);
12985 inst
.instruction
|= (br
& 0x300) >> 4;
12986 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12990 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12992 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12994 /* PR gas/12698: The constraint is only applied for m_profile.
12995 If the user has specified -march=all, we want to ignore it as
12996 we are building for any CPU type, including non-m variants. */
12997 bfd_boolean m_profile
=
12998 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12999 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
13000 "not support requested special purpose register"));
13003 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13005 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
13006 _("'APSR', 'CPSR' or 'SPSR' expected"));
13008 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13009 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
13010 inst
.instruction
|= 0xf0000;
13020 if (do_vfp_nsyn_msr () == SUCCESS
)
13023 constraint (!inst
.operands
[1].isreg
,
13024 _("Thumb encoding does not support an immediate here"));
13026 if (inst
.operands
[0].isreg
)
13027 flags
= (int)(inst
.operands
[0].reg
);
13029 flags
= inst
.operands
[0].imm
;
13031 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13033 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13035 /* PR gas/12698: The constraint is only applied for m_profile.
13036 If the user has specified -march=all, we want to ignore it as
13037 we are building for any CPU type, including non-m variants. */
13038 bfd_boolean m_profile
=
13039 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13040 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13041 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13042 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13043 && bits
!= PSR_f
)) && m_profile
,
13044 _("selected processor does not support requested special "
13045 "purpose register"));
13048 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13049 "requested special purpose register"));
13051 Rn
= inst
.operands
[1].reg
;
13052 reject_bad_reg (Rn
);
13054 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13055 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13056 inst
.instruction
|= (flags
& 0x300) >> 4;
13057 inst
.instruction
|= (flags
& 0xff);
13058 inst
.instruction
|= Rn
<< 16;
13064 bfd_boolean narrow
;
13065 unsigned Rd
, Rn
, Rm
;
13067 if (!inst
.operands
[2].present
)
13068 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13070 Rd
= inst
.operands
[0].reg
;
13071 Rn
= inst
.operands
[1].reg
;
13072 Rm
= inst
.operands
[2].reg
;
13074 if (unified_syntax
)
13076 if (inst
.size_req
== 4
13082 else if (inst
.instruction
== T_MNEM_muls
)
13083 narrow
= !in_pred_block ();
13085 narrow
= in_pred_block ();
13089 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13090 constraint (Rn
> 7 || Rm
> 7,
13097 /* 16-bit MULS/Conditional MUL. */
13098 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13099 inst
.instruction
|= Rd
;
13102 inst
.instruction
|= Rm
<< 3;
13104 inst
.instruction
|= Rn
<< 3;
13106 constraint (1, _("dest must overlap one source register"));
13110 constraint (inst
.instruction
!= T_MNEM_mul
,
13111 _("Thumb-2 MUL must not set flags"));
13113 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13114 inst
.instruction
|= Rd
<< 8;
13115 inst
.instruction
|= Rn
<< 16;
13116 inst
.instruction
|= Rm
<< 0;
13118 reject_bad_reg (Rd
);
13119 reject_bad_reg (Rn
);
13120 reject_bad_reg (Rm
);
13127 unsigned RdLo
, RdHi
, Rn
, Rm
;
13129 RdLo
= inst
.operands
[0].reg
;
13130 RdHi
= inst
.operands
[1].reg
;
13131 Rn
= inst
.operands
[2].reg
;
13132 Rm
= inst
.operands
[3].reg
;
13134 reject_bad_reg (RdLo
);
13135 reject_bad_reg (RdHi
);
13136 reject_bad_reg (Rn
);
13137 reject_bad_reg (Rm
);
13139 inst
.instruction
|= RdLo
<< 12;
13140 inst
.instruction
|= RdHi
<< 8;
13141 inst
.instruction
|= Rn
<< 16;
13142 inst
.instruction
|= Rm
;
13145 as_tsktsk (_("rdhi and rdlo must be different"));
13151 set_pred_insn_type (NEUTRAL_IT_INSN
);
13153 if (unified_syntax
)
13155 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13157 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13158 inst
.instruction
|= inst
.operands
[0].imm
;
13162 /* PR9722: Check for Thumb2 availability before
13163 generating a thumb2 nop instruction. */
13164 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13166 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13167 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13170 inst
.instruction
= 0x46c0;
13175 constraint (inst
.operands
[0].present
,
13176 _("Thumb does not support NOP with hints"));
13177 inst
.instruction
= 0x46c0;
13184 if (unified_syntax
)
13186 bfd_boolean narrow
;
13188 if (THUMB_SETS_FLAGS (inst
.instruction
))
13189 narrow
= !in_pred_block ();
13191 narrow
= in_pred_block ();
13192 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13194 if (inst
.size_req
== 4)
13199 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13200 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13201 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13205 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13206 inst
.instruction
|= inst
.operands
[0].reg
;
13207 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13212 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13214 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13216 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13217 inst
.instruction
|= inst
.operands
[0].reg
;
13218 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13227 Rd
= inst
.operands
[0].reg
;
13228 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13230 reject_bad_reg (Rd
);
13231 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13232 reject_bad_reg (Rn
);
13234 inst
.instruction
|= Rd
<< 8;
13235 inst
.instruction
|= Rn
<< 16;
13237 if (!inst
.operands
[2].isreg
)
13239 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13240 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13246 Rm
= inst
.operands
[2].reg
;
13247 reject_bad_reg (Rm
);
13249 constraint (inst
.operands
[2].shifted
13250 && inst
.operands
[2].immisreg
,
13251 _("shift must be constant"));
13252 encode_thumb32_shifted_operand (2);
13259 unsigned Rd
, Rn
, Rm
;
13261 Rd
= inst
.operands
[0].reg
;
13262 Rn
= inst
.operands
[1].reg
;
13263 Rm
= inst
.operands
[2].reg
;
13265 reject_bad_reg (Rd
);
13266 reject_bad_reg (Rn
);
13267 reject_bad_reg (Rm
);
13269 inst
.instruction
|= Rd
<< 8;
13270 inst
.instruction
|= Rn
<< 16;
13271 inst
.instruction
|= Rm
;
13272 if (inst
.operands
[3].present
)
13274 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13275 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13276 _("expression too complex"));
13277 inst
.instruction
|= (val
& 0x1c) << 10;
13278 inst
.instruction
|= (val
& 0x03) << 6;
13285 if (!inst
.operands
[3].present
)
13289 inst
.instruction
&= ~0x00000020;
13291 /* PR 10168. Swap the Rm and Rn registers. */
13292 Rtmp
= inst
.operands
[1].reg
;
13293 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13294 inst
.operands
[2].reg
= Rtmp
;
13302 if (inst
.operands
[0].immisreg
)
13303 reject_bad_reg (inst
.operands
[0].imm
);
13305 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
13309 do_t_push_pop (void)
13313 constraint (inst
.operands
[0].writeback
,
13314 _("push/pop do not support {reglist}^"));
13315 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13316 _("expression too complex"));
13318 mask
= inst
.operands
[0].imm
;
13319 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13320 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13321 else if (inst
.size_req
!= 4
13322 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13323 ? REG_LR
: REG_PC
)))
13325 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13326 inst
.instruction
|= THUMB_PP_PC_LR
;
13327 inst
.instruction
|= mask
& 0xff;
13329 else if (unified_syntax
)
13331 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13332 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13336 inst
.error
= _("invalid register list to push/pop instruction");
13344 if (unified_syntax
)
13345 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13348 inst
.error
= _("invalid register list to push/pop instruction");
13354 do_t_vscclrm (void)
13356 if (inst
.operands
[0].issingle
)
13358 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13359 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13360 inst
.instruction
|= inst
.operands
[0].imm
;
13364 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13365 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13366 inst
.instruction
|= 1 << 8;
13367 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13376 Rd
= inst
.operands
[0].reg
;
13377 Rm
= inst
.operands
[1].reg
;
13379 reject_bad_reg (Rd
);
13380 reject_bad_reg (Rm
);
13382 inst
.instruction
|= Rd
<< 8;
13383 inst
.instruction
|= Rm
<< 16;
13384 inst
.instruction
|= Rm
;
13392 Rd
= inst
.operands
[0].reg
;
13393 Rm
= inst
.operands
[1].reg
;
13395 reject_bad_reg (Rd
);
13396 reject_bad_reg (Rm
);
13398 if (Rd
<= 7 && Rm
<= 7
13399 && inst
.size_req
!= 4)
13401 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13402 inst
.instruction
|= Rd
;
13403 inst
.instruction
|= Rm
<< 3;
13405 else if (unified_syntax
)
13407 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13408 inst
.instruction
|= Rd
<< 8;
13409 inst
.instruction
|= Rm
<< 16;
13410 inst
.instruction
|= Rm
;
13413 inst
.error
= BAD_HIREG
;
13421 Rd
= inst
.operands
[0].reg
;
13422 Rm
= inst
.operands
[1].reg
;
13424 reject_bad_reg (Rd
);
13425 reject_bad_reg (Rm
);
13427 inst
.instruction
|= Rd
<< 8;
13428 inst
.instruction
|= Rm
;
13436 Rd
= inst
.operands
[0].reg
;
13437 Rs
= (inst
.operands
[1].present
13438 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13439 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13441 reject_bad_reg (Rd
);
13442 reject_bad_reg (Rs
);
13443 if (inst
.operands
[2].isreg
)
13444 reject_bad_reg (inst
.operands
[2].reg
);
13446 inst
.instruction
|= Rd
<< 8;
13447 inst
.instruction
|= Rs
<< 16;
13448 if (!inst
.operands
[2].isreg
)
13450 bfd_boolean narrow
;
13452 if ((inst
.instruction
& 0x00100000) != 0)
13453 narrow
= !in_pred_block ();
13455 narrow
= in_pred_block ();
13457 if (Rd
> 7 || Rs
> 7)
13460 if (inst
.size_req
== 4 || !unified_syntax
)
13463 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13464 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13467 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13468 relaxation, but it doesn't seem worth the hassle. */
13471 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13472 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13473 inst
.instruction
|= Rs
<< 3;
13474 inst
.instruction
|= Rd
;
13478 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13479 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13483 encode_thumb32_shifted_operand (2);
13489 if (warn_on_deprecated
13490 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13491 as_tsktsk (_("setend use is deprecated for ARMv8"));
13493 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13494 if (inst
.operands
[0].imm
)
13495 inst
.instruction
|= 0x8;
13501 if (!inst
.operands
[1].present
)
13502 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13504 if (unified_syntax
)
13506 bfd_boolean narrow
;
13509 switch (inst
.instruction
)
13512 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13514 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13516 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13518 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13522 if (THUMB_SETS_FLAGS (inst
.instruction
))
13523 narrow
= !in_pred_block ();
13525 narrow
= in_pred_block ();
13526 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13528 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13530 if (inst
.operands
[2].isreg
13531 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13532 || inst
.operands
[2].reg
> 7))
13534 if (inst
.size_req
== 4)
13537 reject_bad_reg (inst
.operands
[0].reg
);
13538 reject_bad_reg (inst
.operands
[1].reg
);
13542 if (inst
.operands
[2].isreg
)
13544 reject_bad_reg (inst
.operands
[2].reg
);
13545 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13546 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13547 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13548 inst
.instruction
|= inst
.operands
[2].reg
;
13550 /* PR 12854: Error on extraneous shifts. */
13551 constraint (inst
.operands
[2].shifted
,
13552 _("extraneous shift as part of operand to shift insn"));
13556 inst
.operands
[1].shifted
= 1;
13557 inst
.operands
[1].shift_kind
= shift_kind
;
13558 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13559 ? T_MNEM_movs
: T_MNEM_mov
);
13560 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13561 encode_thumb32_shifted_operand (1);
13562 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13563 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13568 if (inst
.operands
[2].isreg
)
13570 switch (shift_kind
)
13572 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13573 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13574 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13575 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13579 inst
.instruction
|= inst
.operands
[0].reg
;
13580 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13582 /* PR 12854: Error on extraneous shifts. */
13583 constraint (inst
.operands
[2].shifted
,
13584 _("extraneous shift as part of operand to shift insn"));
13588 switch (shift_kind
)
13590 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13591 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13592 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13595 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13596 inst
.instruction
|= inst
.operands
[0].reg
;
13597 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13603 constraint (inst
.operands
[0].reg
> 7
13604 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
13605 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13607 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
13609 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
13610 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13611 _("source1 and dest must be same register"));
13613 switch (inst
.instruction
)
13615 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13616 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13617 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13618 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13622 inst
.instruction
|= inst
.operands
[0].reg
;
13623 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13625 /* PR 12854: Error on extraneous shifts. */
13626 constraint (inst
.operands
[2].shifted
,
13627 _("extraneous shift as part of operand to shift insn"));
13631 switch (inst
.instruction
)
13633 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13634 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13635 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13636 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
13639 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13640 inst
.instruction
|= inst
.operands
[0].reg
;
13641 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13649 unsigned Rd
, Rn
, Rm
;
13651 Rd
= inst
.operands
[0].reg
;
13652 Rn
= inst
.operands
[1].reg
;
13653 Rm
= inst
.operands
[2].reg
;
13655 reject_bad_reg (Rd
);
13656 reject_bad_reg (Rn
);
13657 reject_bad_reg (Rm
);
13659 inst
.instruction
|= Rd
<< 8;
13660 inst
.instruction
|= Rn
<< 16;
13661 inst
.instruction
|= Rm
;
13667 unsigned Rd
, Rn
, Rm
;
13669 Rd
= inst
.operands
[0].reg
;
13670 Rm
= inst
.operands
[1].reg
;
13671 Rn
= inst
.operands
[2].reg
;
13673 reject_bad_reg (Rd
);
13674 reject_bad_reg (Rn
);
13675 reject_bad_reg (Rm
);
13677 inst
.instruction
|= Rd
<< 8;
13678 inst
.instruction
|= Rn
<< 16;
13679 inst
.instruction
|= Rm
;
13685 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13686 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13687 _("SMC is not permitted on this architecture"));
13688 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13689 _("expression too complex"));
13690 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13691 inst
.instruction
|= (value
& 0xf000) >> 12;
13692 inst
.instruction
|= (value
& 0x0ff0);
13693 inst
.instruction
|= (value
& 0x000f) << 16;
13694 /* PR gas/15623: SMC instructions must be last in an IT block. */
13695 set_pred_insn_type_last ();
13701 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13703 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13704 inst
.instruction
|= (value
& 0x0fff);
13705 inst
.instruction
|= (value
& 0xf000) << 4;
13709 do_t_ssat_usat (int bias
)
13713 Rd
= inst
.operands
[0].reg
;
13714 Rn
= inst
.operands
[2].reg
;
13716 reject_bad_reg (Rd
);
13717 reject_bad_reg (Rn
);
13719 inst
.instruction
|= Rd
<< 8;
13720 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
13721 inst
.instruction
|= Rn
<< 16;
13723 if (inst
.operands
[3].present
)
13725 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
13727 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13729 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13730 _("expression too complex"));
13732 if (shift_amount
!= 0)
13734 constraint (shift_amount
> 31,
13735 _("shift expression is too large"));
13737 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13738 inst
.instruction
|= 0x00200000; /* sh bit. */
13740 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13741 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13749 do_t_ssat_usat (1);
13757 Rd
= inst
.operands
[0].reg
;
13758 Rn
= inst
.operands
[2].reg
;
13760 reject_bad_reg (Rd
);
13761 reject_bad_reg (Rn
);
13763 inst
.instruction
|= Rd
<< 8;
13764 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13765 inst
.instruction
|= Rn
<< 16;
13771 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13772 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13773 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13774 || inst
.operands
[2].negative
,
13777 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13779 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13780 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13781 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13782 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13788 if (!inst
.operands
[2].present
)
13789 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13791 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13792 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13793 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13796 inst
.instruction
|= inst
.operands
[0].reg
;
13797 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13798 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13799 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13805 unsigned Rd
, Rn
, Rm
;
13807 Rd
= inst
.operands
[0].reg
;
13808 Rn
= inst
.operands
[1].reg
;
13809 Rm
= inst
.operands
[2].reg
;
13811 reject_bad_reg (Rd
);
13812 reject_bad_reg (Rn
);
13813 reject_bad_reg (Rm
);
13815 inst
.instruction
|= Rd
<< 8;
13816 inst
.instruction
|= Rn
<< 16;
13817 inst
.instruction
|= Rm
;
13818 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13826 Rd
= inst
.operands
[0].reg
;
13827 Rm
= inst
.operands
[1].reg
;
13829 reject_bad_reg (Rd
);
13830 reject_bad_reg (Rm
);
13832 if (inst
.instruction
<= 0xffff
13833 && inst
.size_req
!= 4
13834 && Rd
<= 7 && Rm
<= 7
13835 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13837 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13838 inst
.instruction
|= Rd
;
13839 inst
.instruction
|= Rm
<< 3;
13841 else if (unified_syntax
)
13843 if (inst
.instruction
<= 0xffff)
13844 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13845 inst
.instruction
|= Rd
<< 8;
13846 inst
.instruction
|= Rm
;
13847 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13851 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13852 _("Thumb encoding does not support rotation"));
13853 constraint (1, BAD_HIREG
);
13860 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
13869 half
= (inst
.instruction
& 0x10) != 0;
13870 set_pred_insn_type_last ();
13871 constraint (inst
.operands
[0].immisreg
,
13872 _("instruction requires register index"));
13874 Rn
= inst
.operands
[0].reg
;
13875 Rm
= inst
.operands
[0].imm
;
13877 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13878 constraint (Rn
== REG_SP
, BAD_SP
);
13879 reject_bad_reg (Rm
);
13881 constraint (!half
&& inst
.operands
[0].shifted
,
13882 _("instruction does not allow shifted index"));
13883 inst
.instruction
|= (Rn
<< 16) | Rm
;
13889 if (!inst
.operands
[0].present
)
13890 inst
.operands
[0].imm
= 0;
13892 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13894 constraint (inst
.size_req
== 2,
13895 _("immediate value out of range"));
13896 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13897 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13898 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13902 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13903 inst
.instruction
|= inst
.operands
[0].imm
;
13906 set_pred_insn_type (NEUTRAL_IT_INSN
);
13913 do_t_ssat_usat (0);
13921 Rd
= inst
.operands
[0].reg
;
13922 Rn
= inst
.operands
[2].reg
;
13924 reject_bad_reg (Rd
);
13925 reject_bad_reg (Rn
);
13927 inst
.instruction
|= Rd
<< 8;
13928 inst
.instruction
|= inst
.operands
[1].imm
;
13929 inst
.instruction
|= Rn
<< 16;
13932 /* Checking the range of the branch offset (VAL) with NBITS bits
13933 and IS_SIGNED signedness. Also checks the LSB to be 0. */
13935 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
13937 gas_assert (nbits
> 0 && nbits
<= 32);
13940 int cmp
= (1 << (nbits
- 1));
13941 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
13946 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
13952 /* For branches in Armv8.1-M Mainline. */
13954 do_t_branch_future (void)
13956 unsigned long insn
= inst
.instruction
;
13958 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13959 if (inst
.operands
[0].hasreloc
== 0)
13961 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
13962 as_bad (BAD_BRANCH_OFF
);
13964 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
13968 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
13969 inst
.relocs
[0].pc_rel
= 1;
13975 if (inst
.operands
[1].hasreloc
== 0)
13977 int val
= inst
.operands
[1].imm
;
13978 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
13979 as_bad (BAD_BRANCH_OFF
);
13981 int immA
= (val
& 0x0001f000) >> 12;
13982 int immB
= (val
& 0x00000ffc) >> 2;
13983 int immC
= (val
& 0x00000002) >> 1;
13984 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
13988 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
13989 inst
.relocs
[1].pc_rel
= 1;
13994 if (inst
.operands
[1].hasreloc
== 0)
13996 int val
= inst
.operands
[1].imm
;
13997 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
13998 as_bad (BAD_BRANCH_OFF
);
14000 int immA
= (val
& 0x0007f000) >> 12;
14001 int immB
= (val
& 0x00000ffc) >> 2;
14002 int immC
= (val
& 0x00000002) >> 1;
14003 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14007 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
14008 inst
.relocs
[1].pc_rel
= 1;
14012 case T_MNEM_bfcsel
:
14014 if (inst
.operands
[1].hasreloc
== 0)
14016 int val
= inst
.operands
[1].imm
;
14017 int immA
= (val
& 0x00001000) >> 12;
14018 int immB
= (val
& 0x00000ffc) >> 2;
14019 int immC
= (val
& 0x00000002) >> 1;
14020 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14024 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
14025 inst
.relocs
[1].pc_rel
= 1;
14029 if (inst
.operands
[2].hasreloc
== 0)
14031 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
14032 int val2
= inst
.operands
[2].imm
;
14033 int val0
= inst
.operands
[0].imm
& 0x1f;
14034 int diff
= val2
- val0
;
14036 inst
.instruction
|= 1 << 17; /* T bit. */
14037 else if (diff
!= 2)
14038 as_bad (_("out of range label-relative fixup value"));
14042 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14043 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14044 inst
.relocs
[2].pc_rel
= 1;
14048 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14049 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14054 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14061 /* Helper function for do_t_loloop to handle relocations. */
14063 v8_1_loop_reloc (int is_le
)
14065 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14067 int value
= inst
.relocs
[0].exp
.X_add_number
;
14068 value
= (is_le
) ? -value
: value
;
14070 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
14071 as_bad (BAD_BRANCH_OFF
);
14075 immh
= (value
& 0x00000ffc) >> 2;
14076 imml
= (value
& 0x00000002) >> 1;
14078 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14082 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14083 inst
.relocs
[0].pc_rel
= 1;
14087 /* To handle the Scalar Low Overhead Loop instructions
14088 in Armv8.1-M Mainline. */
14092 unsigned long insn
= inst
.instruction
;
14094 set_pred_insn_type (OUTSIDE_PRED_INSN
);
14095 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14101 if (!inst
.operands
[0].present
)
14102 inst
.instruction
|= 1 << 21;
14104 v8_1_loop_reloc (TRUE
);
14108 v8_1_loop_reloc (FALSE
);
14109 /* Fall through. */
14111 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
14112 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
14119 /* MVE instruction encoder helpers. */
14120 #define M_MNEM_vabav 0xee800f01
14121 #define M_MNEM_vmladav 0xeef00e00
14122 #define M_MNEM_vmladava 0xeef00e20
14123 #define M_MNEM_vmladavx 0xeef01e00
14124 #define M_MNEM_vmladavax 0xeef01e20
14125 #define M_MNEM_vmlsdav 0xeef00e01
14126 #define M_MNEM_vmlsdava 0xeef00e21
14127 #define M_MNEM_vmlsdavx 0xeef01e01
14128 #define M_MNEM_vmlsdavax 0xeef01e21
14129 #define M_MNEM_vmullt 0xee011e00
14130 #define M_MNEM_vmullb 0xee010e00
14131 #define M_MNEM_vst20 0xfc801e00
14132 #define M_MNEM_vst21 0xfc801e20
14133 #define M_MNEM_vst40 0xfc801e01
14134 #define M_MNEM_vst41 0xfc801e21
14135 #define M_MNEM_vst42 0xfc801e41
14136 #define M_MNEM_vst43 0xfc801e61
14137 #define M_MNEM_vld20 0xfc901e00
14138 #define M_MNEM_vld21 0xfc901e20
14139 #define M_MNEM_vld40 0xfc901e01
14140 #define M_MNEM_vld41 0xfc901e21
14141 #define M_MNEM_vld42 0xfc901e41
14142 #define M_MNEM_vld43 0xfc901e61
14143 #define M_MNEM_vstrb 0xec000e00
14144 #define M_MNEM_vstrh 0xec000e10
14145 #define M_MNEM_vstrw 0xec000e40
14146 #define M_MNEM_vstrd 0xec000e50
14147 #define M_MNEM_vldrb 0xec100e00
14148 #define M_MNEM_vldrh 0xec100e10
14149 #define M_MNEM_vldrw 0xec100e40
14150 #define M_MNEM_vldrd 0xec100e50
14151 #define M_MNEM_vmovlt 0xeea01f40
14152 #define M_MNEM_vmovlb 0xeea00f40
14153 #define M_MNEM_vmovnt 0xfe311e81
14154 #define M_MNEM_vmovnb 0xfe310e81
14155 #define M_MNEM_vadc 0xee300f00
14156 #define M_MNEM_vadci 0xee301f00
14157 #define M_MNEM_vbrsr 0xfe011e60
14158 #define M_MNEM_vaddlv 0xee890f00
14159 #define M_MNEM_vaddlva 0xee890f20
14160 #define M_MNEM_vaddv 0xeef10f00
14161 #define M_MNEM_vaddva 0xeef10f20
14162 #define M_MNEM_vddup 0xee011f6e
14163 #define M_MNEM_vdwdup 0xee011f60
14164 #define M_MNEM_vidup 0xee010f6e
14165 #define M_MNEM_viwdup 0xee010f60
14166 #define M_MNEM_vmaxv 0xeee20f00
14167 #define M_MNEM_vmaxav 0xeee00f00
14168 #define M_MNEM_vminv 0xeee20f80
14169 #define M_MNEM_vminav 0xeee00f80
14171 /* Neon instruction encoder helpers. */
14173 /* Encodings for the different types for various Neon opcodes. */
14175 /* An "invalid" code for the following tables. */
14178 struct neon_tab_entry
14181 unsigned float_or_poly
;
14182 unsigned scalar_or_imm
;
14185 /* Map overloaded Neon opcodes to their respective encodings. */
14186 #define NEON_ENC_TAB \
14187 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14188 X(vabdl, 0x0800700, N_INV, N_INV), \
14189 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14190 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14191 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14192 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14193 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14194 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14195 X(vaddl, 0x0800000, N_INV, N_INV), \
14196 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14197 X(vsubl, 0x0800200, N_INV, N_INV), \
14198 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14199 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14200 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14201 /* Register variants of the following two instructions are encoded as
14202 vcge / vcgt with the operands reversed. */ \
14203 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14204 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14205 X(vfma, N_INV, 0x0000c10, N_INV), \
14206 X(vfms, N_INV, 0x0200c10, N_INV), \
14207 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14208 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14209 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14210 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14211 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14212 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14213 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14214 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14215 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14216 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14217 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14218 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14219 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14220 X(vshl, 0x0000400, N_INV, 0x0800510), \
14221 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14222 X(vand, 0x0000110, N_INV, 0x0800030), \
14223 X(vbic, 0x0100110, N_INV, 0x0800030), \
14224 X(veor, 0x1000110, N_INV, N_INV), \
14225 X(vorn, 0x0300110, N_INV, 0x0800010), \
14226 X(vorr, 0x0200110, N_INV, 0x0800010), \
14227 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14228 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14229 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14230 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14231 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14232 X(vst1, 0x0000000, 0x0800000, N_INV), \
14233 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14234 X(vst2, 0x0000100, 0x0800100, N_INV), \
14235 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14236 X(vst3, 0x0000200, 0x0800200, N_INV), \
14237 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14238 X(vst4, 0x0000300, 0x0800300, N_INV), \
14239 X(vmovn, 0x1b20200, N_INV, N_INV), \
14240 X(vtrn, 0x1b20080, N_INV, N_INV), \
14241 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14242 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14243 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14244 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14245 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14246 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14247 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14248 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14249 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14250 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14251 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14252 X(vseleq, 0xe000a00, N_INV, N_INV), \
14253 X(vselvs, 0xe100a00, N_INV, N_INV), \
14254 X(vselge, 0xe200a00, N_INV, N_INV), \
14255 X(vselgt, 0xe300a00, N_INV, N_INV), \
14256 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14257 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14258 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14259 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14260 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14261 X(aes, 0x3b00300, N_INV, N_INV), \
14262 X(sha3op, 0x2000c00, N_INV, N_INV), \
14263 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14264 X(sha2op, 0x3ba0380, N_INV, N_INV)
14268 #define X(OPC,I,F,S) N_MNEM_##OPC
14273 static const struct neon_tab_entry neon_enc_tab
[] =
14275 #define X(OPC,I,F,S) { (I), (F), (S) }
14280 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14281 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14282 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14283 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14284 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14285 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14286 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14287 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14288 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14289 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14290 #define NEON_ENC_SINGLE_(X) \
14291 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14292 #define NEON_ENC_DOUBLE_(X) \
14293 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14294 #define NEON_ENC_FPV8_(X) \
14295 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14297 #define NEON_ENCODE(type, inst) \
14300 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14301 inst.is_neon = 1; \
14305 #define check_neon_suffixes \
14308 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14310 as_bad (_("invalid neon suffix for non neon instruction")); \
14316 /* Define shapes for instruction operands. The following mnemonic characters
14317 are used in this table:
14319 F - VFP S<n> register
14320 D - Neon D<n> register
14321 Q - Neon Q<n> register
14325 L - D<n> register list
14327 This table is used to generate various data:
14328 - enumerations of the form NS_DDR to be used as arguments to
14330 - a table classifying shapes into single, double, quad, mixed.
14331 - a table used to drive neon_select_shape. */
14333 #define NEON_SHAPE_DEF \
14334 X(4, (Q, R, R, I), QUAD), \
14335 X(4, (R, R, S, S), QUAD), \
14336 X(4, (S, S, R, R), QUAD), \
14337 X(3, (Q, R, I), QUAD), \
14338 X(3, (I, Q, Q), QUAD), \
14339 X(3, (I, Q, R), QUAD), \
14340 X(3, (R, Q, Q), QUAD), \
14341 X(3, (D, D, D), DOUBLE), \
14342 X(3, (Q, Q, Q), QUAD), \
14343 X(3, (D, D, I), DOUBLE), \
14344 X(3, (Q, Q, I), QUAD), \
14345 X(3, (D, D, S), DOUBLE), \
14346 X(3, (Q, Q, S), QUAD), \
14347 X(3, (Q, Q, R), QUAD), \
14348 X(3, (R, R, Q), QUAD), \
14349 X(2, (R, Q), QUAD), \
14350 X(2, (D, D), DOUBLE), \
14351 X(2, (Q, Q), QUAD), \
14352 X(2, (D, S), DOUBLE), \
14353 X(2, (Q, S), QUAD), \
14354 X(2, (D, R), DOUBLE), \
14355 X(2, (Q, R), QUAD), \
14356 X(2, (D, I), DOUBLE), \
14357 X(2, (Q, I), QUAD), \
14358 X(3, (D, L, D), DOUBLE), \
14359 X(2, (D, Q), MIXED), \
14360 X(2, (Q, D), MIXED), \
14361 X(3, (D, Q, I), MIXED), \
14362 X(3, (Q, D, I), MIXED), \
14363 X(3, (Q, D, D), MIXED), \
14364 X(3, (D, Q, Q), MIXED), \
14365 X(3, (Q, Q, D), MIXED), \
14366 X(3, (Q, D, S), MIXED), \
14367 X(3, (D, Q, S), MIXED), \
14368 X(4, (D, D, D, I), DOUBLE), \
14369 X(4, (Q, Q, Q, I), QUAD), \
14370 X(4, (D, D, S, I), DOUBLE), \
14371 X(4, (Q, Q, S, I), QUAD), \
14372 X(2, (F, F), SINGLE), \
14373 X(3, (F, F, F), SINGLE), \
14374 X(2, (F, I), SINGLE), \
14375 X(2, (F, D), MIXED), \
14376 X(2, (D, F), MIXED), \
14377 X(3, (F, F, I), MIXED), \
14378 X(4, (R, R, F, F), SINGLE), \
14379 X(4, (F, F, R, R), SINGLE), \
14380 X(3, (D, R, R), DOUBLE), \
14381 X(3, (R, R, D), DOUBLE), \
14382 X(2, (S, R), SINGLE), \
14383 X(2, (R, S), SINGLE), \
14384 X(2, (F, R), SINGLE), \
14385 X(2, (R, F), SINGLE), \
14386 /* Half float shape supported so far. */\
14387 X (2, (H, D), MIXED), \
14388 X (2, (D, H), MIXED), \
14389 X (2, (H, F), MIXED), \
14390 X (2, (F, H), MIXED), \
14391 X (2, (H, H), HALF), \
14392 X (2, (H, R), HALF), \
14393 X (2, (R, H), HALF), \
14394 X (2, (H, I), HALF), \
14395 X (3, (H, H, H), HALF), \
14396 X (3, (H, F, I), MIXED), \
14397 X (3, (F, H, I), MIXED), \
14398 X (3, (D, H, H), MIXED), \
14399 X (3, (D, H, S), MIXED)
14401 #define S2(A,B) NS_##A##B
14402 #define S3(A,B,C) NS_##A##B##C
14403 #define S4(A,B,C,D) NS_##A##B##C##D
14405 #define X(N, L, C) S##N L
14418 enum neon_shape_class
14427 #define X(N, L, C) SC_##C
14429 static enum neon_shape_class neon_shape_class
[] =
14448 /* Register widths of above. */
14449 static unsigned neon_shape_el_size
[] =
14461 struct neon_shape_info
14464 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14467 #define S2(A,B) { SE_##A, SE_##B }
14468 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14469 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14471 #define X(N, L, C) { N, S##N L }
14473 static struct neon_shape_info neon_shape_tab
[] =
14483 /* Bit masks used in type checking given instructions.
14484 'N_EQK' means the type must be the same as (or based on in some way) the key
14485 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14486 set, various other bits can be set as well in order to modify the meaning of
14487 the type constraint. */
14489 enum neon_type_mask
14513 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14514 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14515 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14516 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
14517 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
14518 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
14519 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14520 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14521 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14522 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
14523 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
14525 N_MAX_NONSPECIAL
= N_P64
14528 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14530 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14531 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14532 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
14533 #define N_S_32 (N_S8 | N_S16 | N_S32)
14534 #define N_F_16_32 (N_F16 | N_F32)
14535 #define N_SUF_32 (N_SU_32 | N_F_16_32)
14536 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
14537 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
14538 #define N_F_ALL (N_F16 | N_F32 | N_F64)
14539 #define N_I_MVE (N_I8 | N_I16 | N_I32)
14540 #define N_F_MVE (N_F16 | N_F32)
14541 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14543 /* Pass this as the first type argument to neon_check_type to ignore types
14545 #define N_IGNORE_TYPE (N_KEY | N_EQK)
14547 /* Select a "shape" for the current instruction (describing register types or
14548 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14549 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14550 function of operand parsing, so this function doesn't need to be called.
14551 Shapes should be listed in order of decreasing length. */
14553 static enum neon_shape
14554 neon_select_shape (enum neon_shape shape
, ...)
14557 enum neon_shape first_shape
= shape
;
14559 /* Fix missing optional operands. FIXME: we don't know at this point how
14560 many arguments we should have, so this makes the assumption that we have
14561 > 1. This is true of all current Neon opcodes, I think, but may not be
14562 true in the future. */
14563 if (!inst
.operands
[1].present
)
14564 inst
.operands
[1] = inst
.operands
[0];
14566 va_start (ap
, shape
);
14568 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
14573 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
14575 if (!inst
.operands
[j
].present
)
14581 switch (neon_shape_tab
[shape
].el
[j
])
14583 /* If a .f16, .16, .u16, .s16 type specifier is given over
14584 a VFP single precision register operand, it's essentially
14585 means only half of the register is used.
14587 If the type specifier is given after the mnemonics, the
14588 information is stored in inst.vectype. If the type specifier
14589 is given after register operand, the information is stored
14590 in inst.operands[].vectype.
14592 When there is only one type specifier, and all the register
14593 operands are the same type of hardware register, the type
14594 specifier applies to all register operands.
14596 If no type specifier is given, the shape is inferred from
14597 operand information.
14600 vadd.f16 s0, s1, s2: NS_HHH
14601 vabs.f16 s0, s1: NS_HH
14602 vmov.f16 s0, r1: NS_HR
14603 vmov.f16 r0, s1: NS_RH
14604 vcvt.f16 r0, s1: NS_RH
14605 vcvt.f16.s32 s2, s2, #29: NS_HFI
14606 vcvt.f16.s32 s2, s2: NS_HF
14609 if (!(inst
.operands
[j
].isreg
14610 && inst
.operands
[j
].isvec
14611 && inst
.operands
[j
].issingle
14612 && !inst
.operands
[j
].isquad
14613 && ((inst
.vectype
.elems
== 1
14614 && inst
.vectype
.el
[0].size
== 16)
14615 || (inst
.vectype
.elems
> 1
14616 && inst
.vectype
.el
[j
].size
== 16)
14617 || (inst
.vectype
.elems
== 0
14618 && inst
.operands
[j
].vectype
.type
!= NT_invtype
14619 && inst
.operands
[j
].vectype
.size
== 16))))
14624 if (!(inst
.operands
[j
].isreg
14625 && inst
.operands
[j
].isvec
14626 && inst
.operands
[j
].issingle
14627 && !inst
.operands
[j
].isquad
14628 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
14629 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
14630 || (inst
.vectype
.elems
== 0
14631 && (inst
.operands
[j
].vectype
.size
== 32
14632 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
14637 if (!(inst
.operands
[j
].isreg
14638 && inst
.operands
[j
].isvec
14639 && !inst
.operands
[j
].isquad
14640 && !inst
.operands
[j
].issingle
))
14645 if (!(inst
.operands
[j
].isreg
14646 && !inst
.operands
[j
].isvec
))
14651 if (!(inst
.operands
[j
].isreg
14652 && inst
.operands
[j
].isvec
14653 && inst
.operands
[j
].isquad
14654 && !inst
.operands
[j
].issingle
))
14659 if (!(!inst
.operands
[j
].isreg
14660 && !inst
.operands
[j
].isscalar
))
14665 if (!(!inst
.operands
[j
].isreg
14666 && inst
.operands
[j
].isscalar
))
14676 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
14677 /* We've matched all the entries in the shape table, and we don't
14678 have any left over operands which have not been matched. */
14684 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
14685 first_error (_("invalid instruction shape"));
14690 /* True if SHAPE is predominantly a quadword operation (most of the time, this
14691 means the Q bit should be set). */
14694 neon_quad (enum neon_shape shape
)
14696 return neon_shape_class
[shape
] == SC_QUAD
;
14700 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
14703 /* Allow modification to be made to types which are constrained to be
14704 based on the key element, based on bits set alongside N_EQK. */
14705 if ((typebits
& N_EQK
) != 0)
14707 if ((typebits
& N_HLF
) != 0)
14709 else if ((typebits
& N_DBL
) != 0)
14711 if ((typebits
& N_SGN
) != 0)
14712 *g_type
= NT_signed
;
14713 else if ((typebits
& N_UNS
) != 0)
14714 *g_type
= NT_unsigned
;
14715 else if ((typebits
& N_INT
) != 0)
14716 *g_type
= NT_integer
;
14717 else if ((typebits
& N_FLT
) != 0)
14718 *g_type
= NT_float
;
14719 else if ((typebits
& N_SIZ
) != 0)
14720 *g_type
= NT_untyped
;
14724 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
14725 operand type, i.e. the single type specified in a Neon instruction when it
14726 is the only one given. */
14728 static struct neon_type_el
14729 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
14731 struct neon_type_el dest
= *key
;
14733 gas_assert ((thisarg
& N_EQK
) != 0);
14735 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
14740 /* Convert Neon type and size into compact bitmask representation. */
14742 static enum neon_type_mask
14743 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
14750 case 8: return N_8
;
14751 case 16: return N_16
;
14752 case 32: return N_32
;
14753 case 64: return N_64
;
14761 case 8: return N_I8
;
14762 case 16: return N_I16
;
14763 case 32: return N_I32
;
14764 case 64: return N_I64
;
14772 case 16: return N_F16
;
14773 case 32: return N_F32
;
14774 case 64: return N_F64
;
14782 case 8: return N_P8
;
14783 case 16: return N_P16
;
14784 case 64: return N_P64
;
14792 case 8: return N_S8
;
14793 case 16: return N_S16
;
14794 case 32: return N_S32
;
14795 case 64: return N_S64
;
14803 case 8: return N_U8
;
14804 case 16: return N_U16
;
14805 case 32: return N_U32
;
14806 case 64: return N_U64
;
14817 /* Convert compact Neon bitmask type representation to a type and size. Only
14818 handles the case where a single bit is set in the mask. */
14821 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
14822 enum neon_type_mask mask
)
14824 if ((mask
& N_EQK
) != 0)
14827 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
14829 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
14831 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
14833 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
14838 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
14840 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
14841 *type
= NT_unsigned
;
14842 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
14843 *type
= NT_integer
;
14844 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
14845 *type
= NT_untyped
;
14846 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
14848 else if ((mask
& (N_F_ALL
)) != 0)
14856 /* Modify a bitmask of allowed types. This is only needed for type
14860 modify_types_allowed (unsigned allowed
, unsigned mods
)
14863 enum neon_el_type type
;
14869 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
14871 if (el_type_of_type_chk (&type
, &size
,
14872 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
14874 neon_modify_type_size (mods
, &type
, &size
);
14875 destmask
|= type_chk_of_el_type (type
, size
);
14882 /* Check type and return type classification.
14883 The manual states (paraphrase): If one datatype is given, it indicates the
14885 - the second operand, if there is one
14886 - the operand, if there is no second operand
14887 - the result, if there are no operands.
14888 This isn't quite good enough though, so we use a concept of a "key" datatype
14889 which is set on a per-instruction basis, which is the one which matters when
14890 only one data type is written.
14891 Note: this function has side-effects (e.g. filling in missing operands). All
14892 Neon instructions should call it before performing bit encoding. */
14894 static struct neon_type_el
14895 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
14898 unsigned i
, pass
, key_el
= 0;
14899 unsigned types
[NEON_MAX_TYPE_ELS
];
14900 enum neon_el_type k_type
= NT_invtype
;
14901 unsigned k_size
= -1u;
14902 struct neon_type_el badtype
= {NT_invtype
, -1};
14903 unsigned key_allowed
= 0;
14905 /* Optional registers in Neon instructions are always (not) in operand 1.
14906 Fill in the missing operand here, if it was omitted. */
14907 if (els
> 1 && !inst
.operands
[1].present
)
14908 inst
.operands
[1] = inst
.operands
[0];
14910 /* Suck up all the varargs. */
14912 for (i
= 0; i
< els
; i
++)
14914 unsigned thisarg
= va_arg (ap
, unsigned);
14915 if (thisarg
== N_IGNORE_TYPE
)
14920 types
[i
] = thisarg
;
14921 if ((thisarg
& N_KEY
) != 0)
14926 if (inst
.vectype
.elems
> 0)
14927 for (i
= 0; i
< els
; i
++)
14928 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
14930 first_error (_("types specified in both the mnemonic and operands"));
14934 /* Duplicate inst.vectype elements here as necessary.
14935 FIXME: No idea if this is exactly the same as the ARM assembler,
14936 particularly when an insn takes one register and one non-register
14938 if (inst
.vectype
.elems
== 1 && els
> 1)
14941 inst
.vectype
.elems
= els
;
14942 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
14943 for (j
= 0; j
< els
; j
++)
14945 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14948 else if (inst
.vectype
.elems
== 0 && els
> 0)
14951 /* No types were given after the mnemonic, so look for types specified
14952 after each operand. We allow some flexibility here; as long as the
14953 "key" operand has a type, we can infer the others. */
14954 for (j
= 0; j
< els
; j
++)
14955 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
14956 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
14958 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
14960 for (j
= 0; j
< els
; j
++)
14961 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
14962 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14967 first_error (_("operand types can't be inferred"));
14971 else if (inst
.vectype
.elems
!= els
)
14973 first_error (_("type specifier has the wrong number of parts"));
14977 for (pass
= 0; pass
< 2; pass
++)
14979 for (i
= 0; i
< els
; i
++)
14981 unsigned thisarg
= types
[i
];
14982 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
14983 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
14984 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
14985 unsigned g_size
= inst
.vectype
.el
[i
].size
;
14987 /* Decay more-specific signed & unsigned types to sign-insensitive
14988 integer types if sign-specific variants are unavailable. */
14989 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
14990 && (types_allowed
& N_SU_ALL
) == 0)
14991 g_type
= NT_integer
;
14993 /* If only untyped args are allowed, decay any more specific types to
14994 them. Some instructions only care about signs for some element
14995 sizes, so handle that properly. */
14996 if (((types_allowed
& N_UNT
) == 0)
14997 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
14998 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
14999 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
15000 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
15001 g_type
= NT_untyped
;
15005 if ((thisarg
& N_KEY
) != 0)
15009 key_allowed
= thisarg
& ~N_KEY
;
15011 /* Check architecture constraint on FP16 extension. */
15013 && k_type
== NT_float
15014 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15016 inst
.error
= _(BAD_FP16
);
15023 if ((thisarg
& N_VFP
) != 0)
15025 enum neon_shape_el regshape
;
15026 unsigned regwidth
, match
;
15028 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15031 first_error (_("invalid instruction shape"));
15034 regshape
= neon_shape_tab
[ns
].el
[i
];
15035 regwidth
= neon_shape_el_size
[regshape
];
15037 /* In VFP mode, operands must match register widths. If we
15038 have a key operand, use its width, else use the width of
15039 the current operand. */
15045 /* FP16 will use a single precision register. */
15046 if (regwidth
== 32 && match
== 16)
15048 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15052 inst
.error
= _(BAD_FP16
);
15057 if (regwidth
!= match
)
15059 first_error (_("operand size must match register width"));
15064 if ((thisarg
& N_EQK
) == 0)
15066 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15068 if ((given_type
& types_allowed
) == 0)
15070 first_error (BAD_SIMD_TYPE
);
15076 enum neon_el_type mod_k_type
= k_type
;
15077 unsigned mod_k_size
= k_size
;
15078 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15079 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15081 first_error (_("inconsistent types in Neon instruction"));
15089 return inst
.vectype
.el
[key_el
];
15092 /* Neon-style VFP instruction forwarding. */
15094 /* Thumb VFP instructions have 0xE in the condition field. */
15097 do_vfp_cond_or_thumb (void)
15102 inst
.instruction
|= 0xe0000000;
15104 inst
.instruction
|= inst
.cond
<< 28;
15107 /* Look up and encode a simple mnemonic, for use as a helper function for the
15108 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15109 etc. It is assumed that operand parsing has already been done, and that the
15110 operands are in the form expected by the given opcode (this isn't necessarily
15111 the same as the form in which they were parsed, hence some massaging must
15112 take place before this function is called).
15113 Checks current arch version against that in the looked-up opcode. */
15116 do_vfp_nsyn_opcode (const char *opname
)
15118 const struct asm_opcode
*opcode
;
15120 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
15125 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15126 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15133 inst
.instruction
= opcode
->tvalue
;
15134 opcode
->tencode ();
15138 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15139 opcode
->aencode ();
15144 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15146 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15148 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15151 do_vfp_nsyn_opcode ("fadds");
15153 do_vfp_nsyn_opcode ("fsubs");
15155 /* ARMv8.2 fp16 instruction. */
15157 do_scalar_fp16_v82_encode ();
15162 do_vfp_nsyn_opcode ("faddd");
15164 do_vfp_nsyn_opcode ("fsubd");
15168 /* Check operand types to see if this is a VFP instruction, and if so call
15172 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15174 enum neon_shape rs
;
15175 struct neon_type_el et
;
15180 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15181 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15185 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15186 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15187 N_F_ALL
| N_KEY
| N_VFP
);
15194 if (et
.type
!= NT_invtype
)
15205 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15207 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15209 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15212 do_vfp_nsyn_opcode ("fmacs");
15214 do_vfp_nsyn_opcode ("fnmacs");
15216 /* ARMv8.2 fp16 instruction. */
15218 do_scalar_fp16_v82_encode ();
15223 do_vfp_nsyn_opcode ("fmacd");
15225 do_vfp_nsyn_opcode ("fnmacd");
15230 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15232 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15234 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15237 do_vfp_nsyn_opcode ("ffmas");
15239 do_vfp_nsyn_opcode ("ffnmas");
15241 /* ARMv8.2 fp16 instruction. */
15243 do_scalar_fp16_v82_encode ();
15248 do_vfp_nsyn_opcode ("ffmad");
15250 do_vfp_nsyn_opcode ("ffnmad");
15255 do_vfp_nsyn_mul (enum neon_shape rs
)
15257 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15259 do_vfp_nsyn_opcode ("fmuls");
15261 /* ARMv8.2 fp16 instruction. */
15263 do_scalar_fp16_v82_encode ();
15266 do_vfp_nsyn_opcode ("fmuld");
15270 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15272 int is_neg
= (inst
.instruction
& 0x80) != 0;
15273 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15275 if (rs
== NS_FF
|| rs
== NS_HH
)
15278 do_vfp_nsyn_opcode ("fnegs");
15280 do_vfp_nsyn_opcode ("fabss");
15282 /* ARMv8.2 fp16 instruction. */
15284 do_scalar_fp16_v82_encode ();
15289 do_vfp_nsyn_opcode ("fnegd");
15291 do_vfp_nsyn_opcode ("fabsd");
15295 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15296 insns belong to Neon, and are handled elsewhere. */
15299 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15301 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15305 do_vfp_nsyn_opcode ("fldmdbs");
15307 do_vfp_nsyn_opcode ("fldmias");
15312 do_vfp_nsyn_opcode ("fstmdbs");
15314 do_vfp_nsyn_opcode ("fstmias");
15319 do_vfp_nsyn_sqrt (void)
15321 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15322 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15324 if (rs
== NS_FF
|| rs
== NS_HH
)
15326 do_vfp_nsyn_opcode ("fsqrts");
15328 /* ARMv8.2 fp16 instruction. */
15330 do_scalar_fp16_v82_encode ();
15333 do_vfp_nsyn_opcode ("fsqrtd");
15337 do_vfp_nsyn_div (void)
15339 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15340 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15341 N_F_ALL
| N_KEY
| N_VFP
);
15343 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15345 do_vfp_nsyn_opcode ("fdivs");
15347 /* ARMv8.2 fp16 instruction. */
15349 do_scalar_fp16_v82_encode ();
15352 do_vfp_nsyn_opcode ("fdivd");
15356 do_vfp_nsyn_nmul (void)
15358 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15359 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15360 N_F_ALL
| N_KEY
| N_VFP
);
15362 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15364 NEON_ENCODE (SINGLE
, inst
);
15365 do_vfp_sp_dyadic ();
15367 /* ARMv8.2 fp16 instruction. */
15369 do_scalar_fp16_v82_encode ();
15373 NEON_ENCODE (DOUBLE
, inst
);
15374 do_vfp_dp_rd_rn_rm ();
15376 do_vfp_cond_or_thumb ();
15380 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15384 neon_logbits (unsigned x
)
15386 return ffs (x
) - 4;
15389 #define LOW4(R) ((R) & 0xf)
15390 #define HI1(R) (((R) >> 4) & 1)
15393 mve_get_vcmp_vpt_cond (struct neon_type_el et
)
15398 first_error (BAD_EL_TYPE
);
15401 switch (inst
.operands
[0].imm
)
15404 first_error (_("invalid condition"));
15426 /* only accept eq and ne. */
15427 if (inst
.operands
[0].imm
> 1)
15429 first_error (_("invalid condition"));
15432 return inst
.operands
[0].imm
;
15434 if (inst
.operands
[0].imm
== 0x2)
15436 else if (inst
.operands
[0].imm
== 0x8)
15440 first_error (_("invalid condition"));
15444 switch (inst
.operands
[0].imm
)
15447 first_error (_("invalid condition"));
15463 /* Should be unreachable. */
15470 /* We are dealing with a vector predicated block. */
15471 if (inst
.operands
[0].present
)
15473 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15474 struct neon_type_el et
15475 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15478 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15480 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15482 if (et
.type
== NT_invtype
)
15485 if (et
.type
== NT_float
)
15487 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15489 constraint (et
.size
!= 16 && et
.size
!= 32, BAD_EL_TYPE
);
15490 inst
.instruction
|= (et
.size
== 16) << 28;
15491 inst
.instruction
|= 0x3 << 20;
15495 constraint (et
.size
!= 8 && et
.size
!= 16 && et
.size
!= 32,
15497 inst
.instruction
|= 1 << 28;
15498 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15501 if (inst
.operands
[2].isquad
)
15503 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15504 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15505 inst
.instruction
|= (fcond
& 0x2) >> 1;
15509 if (inst
.operands
[2].reg
== REG_SP
)
15510 as_tsktsk (MVE_BAD_SP
);
15511 inst
.instruction
|= 1 << 6;
15512 inst
.instruction
|= (fcond
& 0x2) << 4;
15513 inst
.instruction
|= inst
.operands
[2].reg
;
15515 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15516 inst
.instruction
|= (fcond
& 0x4) << 10;
15517 inst
.instruction
|= (fcond
& 0x1) << 7;
15520 set_pred_insn_type (VPT_INSN
);
15522 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
15523 | ((inst
.instruction
& 0xe000) >> 13);
15524 now_pred
.warn_deprecated
= FALSE
;
15525 now_pred
.type
= VECTOR_PRED
;
15532 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
15533 if (!inst
.operands
[1].isreg
|| !inst
.operands
[1].isquad
)
15534 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
15535 if (!inst
.operands
[2].present
)
15536 first_error (_("MVE vector or ARM register expected"));
15537 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15539 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
15540 if ((inst
.instruction
& 0xffffffff) == N_MNEM_vcmpe
15541 && inst
.operands
[1].isquad
)
15543 inst
.instruction
= N_MNEM_vcmp
;
15547 if (inst
.cond
> COND_ALWAYS
)
15548 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15550 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15552 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15553 struct neon_type_el et
15554 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15557 constraint (rs
== NS_IQR
&& inst
.operands
[2].reg
== REG_PC
15558 && !inst
.operands
[2].iszr
, BAD_PC
);
15560 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15562 inst
.instruction
= 0xee010f00;
15563 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15564 inst
.instruction
|= (fcond
& 0x4) << 10;
15565 inst
.instruction
|= (fcond
& 0x1) << 7;
15566 if (et
.type
== NT_float
)
15568 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15570 inst
.instruction
|= (et
.size
== 16) << 28;
15571 inst
.instruction
|= 0x3 << 20;
15575 inst
.instruction
|= 1 << 28;
15576 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15578 if (inst
.operands
[2].isquad
)
15580 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15581 inst
.instruction
|= (fcond
& 0x2) >> 1;
15582 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15586 if (inst
.operands
[2].reg
== REG_SP
)
15587 as_tsktsk (MVE_BAD_SP
);
15588 inst
.instruction
|= 1 << 6;
15589 inst
.instruction
|= (fcond
& 0x2) << 4;
15590 inst
.instruction
|= inst
.operands
[2].reg
;
15598 do_mve_vmaxa_vmina (void)
15600 if (inst
.cond
> COND_ALWAYS
)
15601 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15603 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15605 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
15606 struct neon_type_el et
15607 = neon_check_type (2, rs
, N_EQK
, N_KEY
| N_S8
| N_S16
| N_S32
);
15609 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15610 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15611 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15612 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15613 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15618 do_mve_vfmas (void)
15620 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
15621 struct neon_type_el et
15622 = neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
, N_EQK
);
15624 if (inst
.cond
> COND_ALWAYS
)
15625 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15627 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15629 if (inst
.operands
[2].reg
== REG_SP
)
15630 as_tsktsk (MVE_BAD_SP
);
15631 else if (inst
.operands
[2].reg
== REG_PC
)
15632 as_tsktsk (MVE_BAD_PC
);
15634 inst
.instruction
|= (et
.size
== 16) << 28;
15635 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15636 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15637 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15638 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15639 inst
.instruction
|= inst
.operands
[2].reg
;
15644 do_mve_viddup (void)
15646 if (inst
.cond
> COND_ALWAYS
)
15647 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15649 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15651 unsigned imm
= inst
.relocs
[0].exp
.X_add_number
;
15652 constraint (imm
!= 1 && imm
!= 2 && imm
!= 4 && imm
!= 8,
15653 _("immediate must be either 1, 2, 4 or 8"));
15655 enum neon_shape rs
;
15656 struct neon_type_el et
;
15658 if (inst
.instruction
== M_MNEM_vddup
|| inst
.instruction
== M_MNEM_vidup
)
15660 rs
= neon_select_shape (NS_QRI
, NS_NULL
);
15661 et
= neon_check_type (2, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
);
15666 constraint ((inst
.operands
[2].reg
% 2) != 1, BAD_EVEN
);
15667 if (inst
.operands
[2].reg
== REG_SP
)
15668 as_tsktsk (MVE_BAD_SP
);
15669 else if (inst
.operands
[2].reg
== REG_PC
)
15670 first_error (BAD_PC
);
15672 rs
= neon_select_shape (NS_QRRI
, NS_NULL
);
15673 et
= neon_check_type (3, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
, N_EQK
);
15674 Rm
= inst
.operands
[2].reg
>> 1;
15676 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15677 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15678 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15679 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15680 inst
.instruction
|= (imm
> 2) << 7;
15681 inst
.instruction
|= Rm
<< 1;
15682 inst
.instruction
|= (imm
== 2 || imm
== 8);
15687 do_mve_vmaxnma_vminnma (void)
15689 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
15690 struct neon_type_el et
15691 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
15693 if (inst
.cond
> COND_ALWAYS
)
15694 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15696 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15698 inst
.instruction
|= (et
.size
== 16) << 28;
15699 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15700 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15701 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15702 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15707 do_mve_vcmul (void)
15709 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
15710 struct neon_type_el et
15711 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F_MVE
| N_KEY
);
15713 if (inst
.cond
> COND_ALWAYS
)
15714 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15716 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15718 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
15719 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
15720 _("immediate out of range"));
15722 if (et
.size
== 32 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
15723 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
15724 as_tsktsk (BAD_MVE_SRCDEST
);
15726 inst
.instruction
|= (et
.size
== 32) << 28;
15727 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15728 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15729 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15730 inst
.instruction
|= (rot
> 90) << 12;
15731 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15732 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15733 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15734 inst
.instruction
|= (rot
== 90 || rot
== 270);
15739 do_vfp_nsyn_cmp (void)
15741 enum neon_shape rs
;
15742 if (!inst
.operands
[0].isreg
)
15749 constraint (inst
.operands
[2].present
, BAD_SYNTAX
);
15750 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
15754 if (inst
.operands
[1].isreg
)
15756 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15757 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15759 if (rs
== NS_FF
|| rs
== NS_HH
)
15761 NEON_ENCODE (SINGLE
, inst
);
15762 do_vfp_sp_monadic ();
15766 NEON_ENCODE (DOUBLE
, inst
);
15767 do_vfp_dp_rd_rm ();
15772 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
15773 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
15775 switch (inst
.instruction
& 0x0fffffff)
15778 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
15781 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
15787 if (rs
== NS_FI
|| rs
== NS_HI
)
15789 NEON_ENCODE (SINGLE
, inst
);
15790 do_vfp_sp_compare_z ();
15794 NEON_ENCODE (DOUBLE
, inst
);
15798 do_vfp_cond_or_thumb ();
15800 /* ARMv8.2 fp16 instruction. */
15801 if (rs
== NS_HI
|| rs
== NS_HH
)
15802 do_scalar_fp16_v82_encode ();
15806 nsyn_insert_sp (void)
15808 inst
.operands
[1] = inst
.operands
[0];
15809 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
15810 inst
.operands
[0].reg
= REG_SP
;
15811 inst
.operands
[0].isreg
= 1;
15812 inst
.operands
[0].writeback
= 1;
15813 inst
.operands
[0].present
= 1;
15817 do_vfp_nsyn_push (void)
15821 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
15822 _("register list must contain at least 1 and at most 16 "
15825 if (inst
.operands
[1].issingle
)
15826 do_vfp_nsyn_opcode ("fstmdbs");
15828 do_vfp_nsyn_opcode ("fstmdbd");
15832 do_vfp_nsyn_pop (void)
15836 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
15837 _("register list must contain at least 1 and at most 16 "
15840 if (inst
.operands
[1].issingle
)
15841 do_vfp_nsyn_opcode ("fldmias");
15843 do_vfp_nsyn_opcode ("fldmiad");
15846 /* Fix up Neon data-processing instructions, ORing in the correct bits for
15847 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
15850 neon_dp_fixup (struct arm_it
* insn
)
15852 unsigned int i
= insn
->instruction
;
15857 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
15868 insn
->instruction
= i
;
15872 mve_encode_qqr (int size
, int U
, int fp
)
15874 if (inst
.operands
[2].reg
== REG_SP
)
15875 as_tsktsk (MVE_BAD_SP
);
15876 else if (inst
.operands
[2].reg
== REG_PC
)
15877 as_tsktsk (MVE_BAD_PC
);
15882 if (((unsigned)inst
.instruction
) == 0xd00)
15883 inst
.instruction
= 0xee300f40;
15885 else if (((unsigned)inst
.instruction
) == 0x200d00)
15886 inst
.instruction
= 0xee301f40;
15888 /* Setting size which is 1 for F16 and 0 for F32. */
15889 inst
.instruction
|= (size
== 16) << 28;
15894 if (((unsigned)inst
.instruction
) == 0x800)
15895 inst
.instruction
= 0xee010f40;
15897 else if (((unsigned)inst
.instruction
) == 0x1000800)
15898 inst
.instruction
= 0xee011f40;
15900 else if (((unsigned)inst
.instruction
) == 0)
15901 inst
.instruction
= 0xee000f40;
15903 else if (((unsigned)inst
.instruction
) == 0x200)
15904 inst
.instruction
= 0xee001f40;
15907 inst
.instruction
|= U
<< 28;
15909 /* Setting bits for size. */
15910 inst
.instruction
|= neon_logbits (size
) << 20;
15912 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15913 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15914 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15915 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15916 inst
.instruction
|= inst
.operands
[2].reg
;
15921 mve_encode_rqq (unsigned bit28
, unsigned size
)
15923 inst
.instruction
|= bit28
<< 28;
15924 inst
.instruction
|= neon_logbits (size
) << 20;
15925 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15926 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
15927 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15928 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15929 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15934 mve_encode_qqq (int ubit
, int size
)
15937 inst
.instruction
|= (ubit
!= 0) << 28;
15938 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15939 inst
.instruction
|= neon_logbits (size
) << 20;
15940 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15941 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15942 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15943 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15944 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15950 mve_encode_rq (unsigned bit28
, unsigned size
)
15952 inst
.instruction
|= bit28
<< 28;
15953 inst
.instruction
|= neon_logbits (size
) << 18;
15954 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
15955 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15959 /* Encode insns with bit pattern:
15961 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15962 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
15964 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
15965 different meaning for some instruction. */
15968 neon_three_same (int isquad
, int ubit
, int size
)
15970 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15971 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15972 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15973 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15974 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15975 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15976 inst
.instruction
|= (isquad
!= 0) << 6;
15977 inst
.instruction
|= (ubit
!= 0) << 24;
15979 inst
.instruction
|= neon_logbits (size
) << 20;
15981 neon_dp_fixup (&inst
);
15984 /* Encode instructions of the form:
15986 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
15987 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
15989 Don't write size if SIZE == -1. */
15992 neon_two_same (int qbit
, int ubit
, int size
)
15994 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15995 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15996 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15997 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15998 inst
.instruction
|= (qbit
!= 0) << 6;
15999 inst
.instruction
|= (ubit
!= 0) << 24;
16002 inst
.instruction
|= neon_logbits (size
) << 18;
16004 neon_dp_fixup (&inst
);
16007 enum vfp_or_neon_is_neon_bits
16010 NEON_CHECK_ARCH
= 2,
16011 NEON_CHECK_ARCH8
= 4
16014 /* Call this function if an instruction which may have belonged to the VFP or
16015 Neon instruction sets, but turned out to be a Neon instruction (due to the
16016 operand types involved, etc.). We have to check and/or fix-up a couple of
16019 - Make sure the user hasn't attempted to make a Neon instruction
16021 - Alter the value in the condition code field if necessary.
16022 - Make sure that the arch supports Neon instructions.
16024 Which of these operations take place depends on bits from enum
16025 vfp_or_neon_is_neon_bits.
16027 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16028 current instruction's condition is COND_ALWAYS, the condition field is
16029 changed to inst.uncond_value. This is necessary because instructions shared
16030 between VFP and Neon may be conditional for the VFP variants only, and the
16031 unconditional Neon version must have, e.g., 0xF in the condition field. */
16034 vfp_or_neon_is_neon (unsigned check
)
16036 /* Conditions are always legal in Thumb mode (IT blocks). */
16037 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
16039 if (inst
.cond
!= COND_ALWAYS
)
16041 first_error (_(BAD_COND
));
16044 if (inst
.uncond_value
!= -1)
16045 inst
.instruction
|= inst
.uncond_value
<< 28;
16049 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
16050 || ((check
& NEON_CHECK_ARCH8
)
16051 && !mark_feature_used (&fpu_neon_ext_armv8
)))
16053 first_error (_(BAD_FPU
));
16061 check_simd_pred_availability (int fp
, unsigned check
)
16063 if (inst
.cond
> COND_ALWAYS
)
16065 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16067 inst
.error
= BAD_FPU
;
16070 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16072 else if (inst
.cond
< COND_ALWAYS
)
16074 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16075 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16076 else if (vfp_or_neon_is_neon (check
) == FAIL
)
16081 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
16082 && vfp_or_neon_is_neon (check
) == FAIL
)
16085 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16086 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16091 /* Neon instruction encoders, in approximate order of appearance. */
16094 do_neon_dyadic_i_su (void)
16096 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16099 enum neon_shape rs
;
16100 struct neon_type_el et
;
16101 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16102 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16104 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16106 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
16110 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16112 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16116 do_neon_dyadic_i64_su (void)
16118 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16119 struct neon_type_el et
= neon_check_type (3, rs
,
16120 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16121 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16125 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
16128 unsigned size
= et
.size
>> 3;
16129 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16130 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16131 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16132 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16133 inst
.instruction
|= (isquad
!= 0) << 6;
16134 inst
.instruction
|= immbits
<< 16;
16135 inst
.instruction
|= (size
>> 3) << 7;
16136 inst
.instruction
|= (size
& 0x7) << 19;
16138 inst
.instruction
|= (uval
!= 0) << 24;
16140 neon_dp_fixup (&inst
);
16144 do_neon_shl_imm (void)
16146 if (!inst
.operands
[2].isreg
)
16148 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16149 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
16150 int imm
= inst
.operands
[2].imm
;
16152 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16153 _("immediate out of range for shift"));
16154 NEON_ENCODE (IMMED
, inst
);
16155 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
16159 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16160 struct neon_type_el et
= neon_check_type (3, rs
,
16161 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16164 /* VSHL/VQSHL 3-register variants have syntax such as:
16166 whereas other 3-register operations encoded by neon_three_same have
16169 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
16171 tmp
= inst
.operands
[2].reg
;
16172 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16173 inst
.operands
[1].reg
= tmp
;
16174 NEON_ENCODE (INTEGER
, inst
);
16175 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16180 do_neon_qshl_imm (void)
16182 if (!inst
.operands
[2].isreg
)
16184 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16185 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16186 int imm
= inst
.operands
[2].imm
;
16188 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16189 _("immediate out of range for shift"));
16190 NEON_ENCODE (IMMED
, inst
);
16191 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
16195 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16196 struct neon_type_el et
= neon_check_type (3, rs
,
16197 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16200 /* See note in do_neon_shl_imm. */
16201 tmp
= inst
.operands
[2].reg
;
16202 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16203 inst
.operands
[1].reg
= tmp
;
16204 NEON_ENCODE (INTEGER
, inst
);
16205 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16210 do_neon_rshl (void)
16212 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16213 struct neon_type_el et
= neon_check_type (3, rs
,
16214 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16217 tmp
= inst
.operands
[2].reg
;
16218 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16219 inst
.operands
[1].reg
= tmp
;
16220 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16224 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
16226 /* Handle .I8 pseudo-instructions. */
16229 /* Unfortunately, this will make everything apart from zero out-of-range.
16230 FIXME is this the intended semantics? There doesn't seem much point in
16231 accepting .I8 if so. */
16232 immediate
|= immediate
<< 8;
16238 if (immediate
== (immediate
& 0x000000ff))
16240 *immbits
= immediate
;
16243 else if (immediate
== (immediate
& 0x0000ff00))
16245 *immbits
= immediate
>> 8;
16248 else if (immediate
== (immediate
& 0x00ff0000))
16250 *immbits
= immediate
>> 16;
16253 else if (immediate
== (immediate
& 0xff000000))
16255 *immbits
= immediate
>> 24;
16258 if ((immediate
& 0xffff) != (immediate
>> 16))
16259 goto bad_immediate
;
16260 immediate
&= 0xffff;
16263 if (immediate
== (immediate
& 0x000000ff))
16265 *immbits
= immediate
;
16268 else if (immediate
== (immediate
& 0x0000ff00))
16270 *immbits
= immediate
>> 8;
16275 first_error (_("immediate value out of range"));
16280 do_neon_logic (void)
16282 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
16284 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16286 && check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
)
16289 else if (rs
!= NS_QQQ
16290 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
16291 first_error (BAD_FPU
);
16293 neon_check_type (3, rs
, N_IGNORE_TYPE
);
16294 /* U bit and size field were set as part of the bitmask. */
16295 NEON_ENCODE (INTEGER
, inst
);
16296 neon_three_same (neon_quad (rs
), 0, -1);
16300 const int three_ops_form
= (inst
.operands
[2].present
16301 && !inst
.operands
[2].isreg
);
16302 const int immoperand
= (three_ops_form
? 2 : 1);
16303 enum neon_shape rs
= (three_ops_form
16304 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
16305 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
16306 /* Because neon_select_shape makes the second operand a copy of the first
16307 if the second operand is not present. */
16309 && check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
)
16312 else if (rs
!= NS_QQI
16313 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
16314 first_error (BAD_FPU
);
16316 struct neon_type_el et
;
16317 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16318 et
= neon_check_type (2, rs
, N_I32
| N_I16
| N_KEY
, N_EQK
);
16320 et
= neon_check_type (2, rs
, N_I8
| N_I16
| N_I32
| N_I64
| N_F32
16323 if (et
.type
== NT_invtype
)
16325 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
16330 if (three_ops_form
)
16331 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16332 _("first and second operands shall be the same register"));
16334 NEON_ENCODE (IMMED
, inst
);
16336 immbits
= inst
.operands
[immoperand
].imm
;
16339 /* .i64 is a pseudo-op, so the immediate must be a repeating
16341 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
16342 inst
.operands
[immoperand
].reg
: 0))
16344 /* Set immbits to an invalid constant. */
16345 immbits
= 0xdeadbeef;
16352 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16356 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16360 /* Pseudo-instruction for VBIC. */
16361 neon_invert_size (&immbits
, 0, et
.size
);
16362 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16366 /* Pseudo-instruction for VORR. */
16367 neon_invert_size (&immbits
, 0, et
.size
);
16368 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16378 inst
.instruction
|= neon_quad (rs
) << 6;
16379 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16380 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16381 inst
.instruction
|= cmode
<< 8;
16382 neon_write_immbits (immbits
);
16384 neon_dp_fixup (&inst
);
16389 do_neon_bitfield (void)
16391 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16392 neon_check_type (3, rs
, N_IGNORE_TYPE
);
16393 neon_three_same (neon_quad (rs
), 0, -1);
16397 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
16400 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
16401 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
16403 if (et
.type
== NT_float
)
16405 NEON_ENCODE (FLOAT
, inst
);
16407 mve_encode_qqr (et
.size
, 0, 1);
16409 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
16413 NEON_ENCODE (INTEGER
, inst
);
16415 mve_encode_qqr (et
.size
, 0, 0);
16417 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
16423 do_neon_dyadic_if_su_d (void)
16425 /* This version only allow D registers, but that constraint is enforced during
16426 operand parsing so we don't need to do anything extra here. */
16427 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
16431 do_neon_dyadic_if_i_d (void)
16433 /* The "untyped" case can't happen. Do this to stop the "U" bit being
16434 affected if we specify unsigned args. */
16435 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
16439 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
16441 constraint (size
< 32, BAD_ADDR_MODE
);
16442 constraint (size
!= elsize
, BAD_EL_TYPE
);
16443 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16444 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
16445 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
16446 _("destination register and offset register may not be the"
16449 int imm
= inst
.relocs
[0].exp
.X_add_number
;
16456 constraint ((imm
% (size
/ 8) != 0)
16457 || imm
> (0x7f << neon_logbits (size
)),
16458 (size
== 32) ? _("immediate must be a multiple of 4 in the"
16459 " range of +/-[0,508]")
16460 : _("immediate must be a multiple of 8 in the"
16461 " range of +/-[0,1016]"));
16462 inst
.instruction
|= 0x11 << 24;
16463 inst
.instruction
|= add
<< 23;
16464 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16465 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
16466 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16467 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16468 inst
.instruction
|= 1 << 12;
16469 inst
.instruction
|= (size
== 64) << 8;
16470 inst
.instruction
&= 0xffffff00;
16471 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16472 inst
.instruction
|= imm
>> neon_logbits (size
);
16476 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
16478 unsigned os
= inst
.operands
[1].imm
>> 5;
16479 constraint (os
!= 0 && size
== 8,
16480 _("can not shift offsets when accessing less than half-word"));
16481 constraint (os
&& os
!= neon_logbits (size
),
16482 _("shift immediate must be 1, 2 or 3 for half-word, word"
16483 " or double-word accesses respectively"));
16484 if (inst
.operands
[1].reg
== REG_PC
)
16485 as_tsktsk (MVE_BAD_PC
);
16490 constraint (elsize
>= 64, BAD_EL_TYPE
);
16493 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
16497 constraint (elsize
!= size
, BAD_EL_TYPE
);
16502 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
16506 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
16507 _("destination register and offset register may not be"
16509 constraint (size
== elsize
&& inst
.vectype
.el
[0].type
!= NT_unsigned
,
16511 constraint (inst
.vectype
.el
[0].type
!= NT_unsigned
16512 && inst
.vectype
.el
[0].type
!= NT_signed
, BAD_EL_TYPE
);
16513 inst
.instruction
|= (inst
.vectype
.el
[0].type
== NT_unsigned
) << 28;
16517 constraint (inst
.vectype
.el
[0].type
!= NT_untyped
, BAD_EL_TYPE
);
16520 inst
.instruction
|= 1 << 23;
16521 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16522 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16523 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16524 inst
.instruction
|= neon_logbits (elsize
) << 7;
16525 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
16526 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
16527 inst
.instruction
|= !!os
;
16531 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
16533 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
16535 constraint (size
>= 64, BAD_ADDR_MODE
);
16539 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
16542 constraint (elsize
!= size
, BAD_EL_TYPE
);
16549 constraint (elsize
!= size
&& type
!= NT_unsigned
16550 && type
!= NT_signed
, BAD_EL_TYPE
);
16554 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
16557 int imm
= inst
.relocs
[0].exp
.X_add_number
;
16565 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
16570 constraint (1, _("immediate must be in the range of +/-[0,127]"));
16573 constraint (1, _("immediate must be a multiple of 2 in the"
16574 " range of +/-[0,254]"));
16577 constraint (1, _("immediate must be a multiple of 4 in the"
16578 " range of +/-[0,508]"));
16583 if (size
!= elsize
)
16585 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
16586 constraint (inst
.operands
[0].reg
> 14,
16587 _("MVE vector register in the range [Q0..Q7] expected"));
16588 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
16589 inst
.instruction
|= (size
== 16) << 19;
16590 inst
.instruction
|= neon_logbits (elsize
) << 7;
16594 if (inst
.operands
[1].reg
== REG_PC
)
16595 as_tsktsk (MVE_BAD_PC
);
16596 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
16597 as_tsktsk (MVE_BAD_SP
);
16598 inst
.instruction
|= 1 << 12;
16599 inst
.instruction
|= neon_logbits (size
) << 7;
16601 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
16602 inst
.instruction
|= add
<< 23;
16603 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16604 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
16605 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16606 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16607 inst
.instruction
&= 0xffffff80;
16608 inst
.instruction
|= imm
>> neon_logbits (size
);
16613 do_mve_vstr_vldr (void)
16618 if (inst
.cond
> COND_ALWAYS
)
16619 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16621 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16623 switch (inst
.instruction
)
16630 /* fall through. */
16636 /* fall through. */
16642 /* fall through. */
16648 /* fall through. */
16653 unsigned elsize
= inst
.vectype
.el
[0].size
;
16655 if (inst
.operands
[1].isquad
)
16657 /* We are dealing with [Q, imm]{!} cases. */
16658 do_mve_vstr_vldr_QI (size
, elsize
, load
);
16662 if (inst
.operands
[1].immisreg
== 2)
16664 /* We are dealing with [R, Q, {UXTW #os}] cases. */
16665 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
16667 else if (!inst
.operands
[1].immisreg
)
16669 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
16670 do_mve_vstr_vldr_RI (size
, elsize
, load
);
16673 constraint (1, BAD_ADDR_MODE
);
16680 do_mve_vst_vld (void)
16682 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16685 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
16686 || inst
.relocs
[0].exp
.X_add_number
!= 0
16687 || inst
.operands
[1].immisreg
!= 0,
16689 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
16690 if (inst
.operands
[1].reg
== REG_PC
)
16691 as_tsktsk (MVE_BAD_PC
);
16692 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
16693 as_tsktsk (MVE_BAD_SP
);
16696 /* These instructions are one of the "exceptions" mentioned in
16697 handle_pred_state. They are MVE instructions that are not VPT compatible
16698 and do not accept a VPT code, thus appending such a code is a syntax
16700 if (inst
.cond
> COND_ALWAYS
)
16701 first_error (BAD_SYNTAX
);
16702 /* If we append a scalar condition code we can set this to
16703 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
16704 else if (inst
.cond
< COND_ALWAYS
)
16705 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16707 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
16709 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16710 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
16711 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16712 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16713 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
16718 do_mve_vaddlv (void)
16720 enum neon_shape rs
= neon_select_shape (NS_RRQ
, NS_NULL
);
16721 struct neon_type_el et
16722 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S32
| N_U32
| N_KEY
);
16724 if (et
.type
== NT_invtype
)
16725 first_error (BAD_EL_TYPE
);
16727 if (inst
.cond
> COND_ALWAYS
)
16728 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16730 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16732 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
16734 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16735 inst
.instruction
|= inst
.operands
[1].reg
<< 19;
16736 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16737 inst
.instruction
|= inst
.operands
[2].reg
;
16742 do_neon_dyadic_if_su (void)
16744 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
16745 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
16748 constraint ((inst
.instruction
== ((unsigned) N_MNEM_vmax
)
16749 || inst
.instruction
== ((unsigned) N_MNEM_vmin
))
16750 && et
.type
== NT_float
16751 && !ARM_CPU_HAS_FEATURE (cpu_variant
,fpu_neon_ext_v1
), BAD_FPU
);
16753 if (check_simd_pred_availability (et
.type
== NT_float
,
16754 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16757 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
16761 do_neon_addsub_if_i (void)
16763 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
16764 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
16767 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
16768 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
16769 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
16771 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
16772 /* If we are parsing Q registers and the element types match MVE, which NEON
16773 also supports, then we must check whether this is an instruction that can
16774 be used by both MVE/NEON. This distinction can be made based on whether
16775 they are predicated or not. */
16776 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
16778 if (check_simd_pred_availability (et
.type
== NT_float
,
16779 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16784 /* If they are either in a D register or are using an unsupported. */
16786 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16790 /* The "untyped" case can't happen. Do this to stop the "U" bit being
16791 affected if we specify unsigned args. */
16792 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
16795 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
16797 V<op> A,B (A is operand 0, B is operand 2)
16802 so handle that case specially. */
16805 neon_exchange_operands (void)
16807 if (inst
.operands
[1].present
)
16809 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
16811 /* Swap operands[1] and operands[2]. */
16812 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
16813 inst
.operands
[1] = inst
.operands
[2];
16814 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
16819 inst
.operands
[1] = inst
.operands
[2];
16820 inst
.operands
[2] = inst
.operands
[0];
16825 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
16827 if (inst
.operands
[2].isreg
)
16830 neon_exchange_operands ();
16831 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
16835 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16836 struct neon_type_el et
= neon_check_type (2, rs
,
16837 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
16839 NEON_ENCODE (IMMED
, inst
);
16840 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16841 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16842 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16843 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16844 inst
.instruction
|= neon_quad (rs
) << 6;
16845 inst
.instruction
|= (et
.type
== NT_float
) << 10;
16846 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16848 neon_dp_fixup (&inst
);
16855 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
16859 do_neon_cmp_inv (void)
16861 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
16867 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
16870 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
16871 scalars, which are encoded in 5 bits, M : Rm.
16872 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
16873 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
16876 Dot Product instructions are similar to multiply instructions except elsize
16877 should always be 32.
16879 This function translates SCALAR, which is GAS's internal encoding of indexed
16880 scalar register, to raw encoding. There is also register and index range
16881 check based on ELSIZE. */
16884 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
16886 unsigned regno
= NEON_SCALAR_REG (scalar
);
16887 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
16892 if (regno
> 7 || elno
> 3)
16894 return regno
| (elno
<< 3);
16897 if (regno
> 15 || elno
> 1)
16899 return regno
| (elno
<< 4);
16903 first_error (_("scalar out of range for multiply instruction"));
16909 /* Encode multiply / multiply-accumulate scalar instructions. */
16912 neon_mul_mac (struct neon_type_el et
, int ubit
)
16916 /* Give a more helpful error message if we have an invalid type. */
16917 if (et
.type
== NT_invtype
)
16920 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
16921 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16922 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16923 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16924 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16925 inst
.instruction
|= LOW4 (scalar
);
16926 inst
.instruction
|= HI1 (scalar
) << 5;
16927 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16928 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16929 inst
.instruction
|= (ubit
!= 0) << 24;
16931 neon_dp_fixup (&inst
);
16935 do_neon_mac_maybe_scalar (void)
16937 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
16940 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16943 if (inst
.operands
[2].isscalar
)
16945 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
16946 struct neon_type_el et
= neon_check_type (3, rs
,
16947 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
16948 NEON_ENCODE (SCALAR
, inst
);
16949 neon_mul_mac (et
, neon_quad (rs
));
16953 /* The "untyped" case can't happen. Do this to stop the "U" bit being
16954 affected if we specify unsigned args. */
16955 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
16960 do_neon_fmac (void)
16962 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_fma
)
16963 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
16966 if (check_simd_pred_availability (1, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
16969 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
16971 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16972 struct neon_type_el et
= neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
,
16977 if (inst
.operands
[2].reg
== REG_SP
)
16978 as_tsktsk (MVE_BAD_SP
);
16979 else if (inst
.operands
[2].reg
== REG_PC
)
16980 as_tsktsk (MVE_BAD_PC
);
16982 inst
.instruction
= 0xee310e40;
16983 inst
.instruction
|= (et
.size
== 16) << 28;
16984 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16985 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16986 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16987 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 6;
16988 inst
.instruction
|= inst
.operands
[2].reg
;
16995 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
16998 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17004 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17005 struct neon_type_el et
= neon_check_type (3, rs
,
17006 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17007 neon_three_same (neon_quad (rs
), 0, et
.size
);
17010 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
17011 same types as the MAC equivalents. The polynomial type for this instruction
17012 is encoded the same as the integer type. */
17017 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
17020 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17023 if (inst
.operands
[2].isscalar
)
17024 do_neon_mac_maybe_scalar ();
17026 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
17030 do_neon_qdmulh (void)
17032 if (inst
.operands
[2].isscalar
)
17034 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17035 struct neon_type_el et
= neon_check_type (3, rs
,
17036 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17037 NEON_ENCODE (SCALAR
, inst
);
17038 neon_mul_mac (et
, neon_quad (rs
));
17042 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17043 struct neon_type_el et
= neon_check_type (3, rs
,
17044 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17045 NEON_ENCODE (INTEGER
, inst
);
17046 /* The U bit (rounding) comes from bit mask. */
17047 neon_three_same (neon_quad (rs
), 0, et
.size
);
17052 do_mve_vaddv (void)
17054 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
17055 struct neon_type_el et
17056 = neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
17058 if (et
.type
== NT_invtype
)
17059 first_error (BAD_EL_TYPE
);
17061 if (inst
.cond
> COND_ALWAYS
)
17062 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17064 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17066 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17068 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
17072 do_mve_vhcadd (void)
17074 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
17075 struct neon_type_el et
17076 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17078 if (inst
.cond
> COND_ALWAYS
)
17079 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17081 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17083 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
17084 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17086 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
17087 as_tsktsk (_("Warning: 32-bit element size and same first and third "
17088 "operand makes instruction UNPREDICTABLE"));
17090 mve_encode_qqq (0, et
.size
);
17091 inst
.instruction
|= (rot
== 270) << 12;
17098 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17099 struct neon_type_el et
17100 = neon_check_type (3, rs
, N_KEY
| N_I32
, N_EQK
, N_EQK
);
17102 if (et
.type
== NT_invtype
)
17103 first_error (BAD_EL_TYPE
);
17105 if (inst
.cond
> COND_ALWAYS
)
17106 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17108 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17110 mve_encode_qqq (0, 64);
17114 do_mve_vbrsr (void)
17116 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17117 struct neon_type_el et
17118 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17120 if (inst
.cond
> COND_ALWAYS
)
17121 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17123 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17125 mve_encode_qqr (et
.size
, 0, 0);
17131 neon_check_type (3, NS_QQQ
, N_EQK
, N_EQK
, N_I32
| N_KEY
);
17133 if (inst
.cond
> COND_ALWAYS
)
17134 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17136 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17138 mve_encode_qqq (1, 64);
17142 do_mve_vmull (void)
17145 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
17146 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
17147 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
17148 && inst
.cond
== COND_ALWAYS
17149 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
17154 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17155 N_SUF_32
| N_F64
| N_P8
17156 | N_P16
| N_I_MVE
| N_KEY
);
17157 if (((et
.type
== NT_poly
) && et
.size
== 8
17158 && ARM_CPU_IS_ANY (cpu_variant
))
17159 || (et
.type
== NT_integer
) || (et
.type
== NT_float
))
17166 constraint (rs
!= NS_QQQ
, BAD_FPU
);
17167 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17168 N_SU_32
| N_P8
| N_P16
| N_KEY
);
17170 /* We are dealing with MVE's vmullt. */
17172 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
17173 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
17174 as_tsktsk (BAD_MVE_SRCDEST
);
17176 if (inst
.cond
> COND_ALWAYS
)
17177 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17179 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17181 if (et
.type
== NT_poly
)
17182 mve_encode_qqq (neon_logbits (et
.size
), 64);
17184 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
17189 inst
.instruction
= N_MNEM_vmul
;
17192 inst
.pred_insn_type
= INSIDE_IT_INSN
;
17197 do_mve_vabav (void)
17199 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
17204 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17207 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
17208 | N_S16
| N_S32
| N_U8
| N_U16
17211 if (inst
.cond
> COND_ALWAYS
)
17212 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17214 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17216 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
17220 do_mve_vmladav (void)
17222 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
17223 struct neon_type_el et
= neon_check_type (3, rs
,
17224 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17226 if (et
.type
== NT_unsigned
17227 && (inst
.instruction
== M_MNEM_vmladavx
17228 || inst
.instruction
== M_MNEM_vmladavax
17229 || inst
.instruction
== M_MNEM_vmlsdav
17230 || inst
.instruction
== M_MNEM_vmlsdava
17231 || inst
.instruction
== M_MNEM_vmlsdavx
17232 || inst
.instruction
== M_MNEM_vmlsdavax
))
17233 first_error (BAD_SIMD_TYPE
);
17235 constraint (inst
.operands
[2].reg
> 14,
17236 _("MVE vector register in the range [Q0..Q7] expected"));
17238 if (inst
.cond
> COND_ALWAYS
)
17239 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17241 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17243 if (inst
.instruction
== M_MNEM_vmlsdav
17244 || inst
.instruction
== M_MNEM_vmlsdava
17245 || inst
.instruction
== M_MNEM_vmlsdavx
17246 || inst
.instruction
== M_MNEM_vmlsdavax
)
17247 inst
.instruction
|= (et
.size
== 8) << 28;
17249 inst
.instruction
|= (et
.size
== 8) << 8;
17251 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
17252 inst
.instruction
|= (et
.size
== 32) << 16;
17256 do_mve_vmaxnmv (void)
17258 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
17259 struct neon_type_el et
17260 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
17262 if (inst
.cond
> COND_ALWAYS
)
17263 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17265 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17267 if (inst
.operands
[0].reg
== REG_SP
)
17268 as_tsktsk (MVE_BAD_SP
);
17269 else if (inst
.operands
[0].reg
== REG_PC
)
17270 as_tsktsk (MVE_BAD_PC
);
17272 mve_encode_rq (et
.size
== 16, 64);
17276 do_mve_vmaxv (void)
17278 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
17279 struct neon_type_el et
;
17281 if (inst
.instruction
== M_MNEM_vmaxv
|| inst
.instruction
== M_MNEM_vminv
)
17282 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
17284 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17286 if (inst
.cond
> COND_ALWAYS
)
17287 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17289 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17291 if (inst
.operands
[0].reg
== REG_SP
)
17292 as_tsktsk (MVE_BAD_SP
);
17293 else if (inst
.operands
[0].reg
== REG_PC
)
17294 as_tsktsk (MVE_BAD_PC
);
17296 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
17301 do_neon_qrdmlah (void)
17303 /* Check we're on the correct architecture. */
17304 if (!mark_feature_used (&fpu_neon_ext_armv8
))
17306 _("instruction form not available on this architecture.");
17307 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
17309 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
17310 record_feature_use (&fpu_neon_ext_v8_1
);
17313 if (inst
.operands
[2].isscalar
)
17315 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17316 struct neon_type_el et
= neon_check_type (3, rs
,
17317 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17318 NEON_ENCODE (SCALAR
, inst
);
17319 neon_mul_mac (et
, neon_quad (rs
));
17323 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17324 struct neon_type_el et
= neon_check_type (3, rs
,
17325 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17326 NEON_ENCODE (INTEGER
, inst
);
17327 /* The U bit (rounding) comes from bit mask. */
17328 neon_three_same (neon_quad (rs
), 0, et
.size
);
17333 do_neon_fcmp_absolute (void)
17335 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17336 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17337 N_F_16_32
| N_KEY
);
17338 /* Size field comes from bit mask. */
17339 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
17343 do_neon_fcmp_absolute_inv (void)
17345 neon_exchange_operands ();
17346 do_neon_fcmp_absolute ();
17350 do_neon_step (void)
17352 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17353 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17354 N_F_16_32
| N_KEY
);
17355 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
17359 do_neon_abs_neg (void)
17361 enum neon_shape rs
;
17362 struct neon_type_el et
;
17364 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
17367 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17368 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
17370 if (check_simd_pred_availability (et
.type
== NT_float
,
17371 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17374 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17375 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17376 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17377 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17378 inst
.instruction
|= neon_quad (rs
) << 6;
17379 inst
.instruction
|= (et
.type
== NT_float
) << 10;
17380 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17382 neon_dp_fixup (&inst
);
17388 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17389 struct neon_type_el et
= neon_check_type (2, rs
,
17390 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
17391 int imm
= inst
.operands
[2].imm
;
17392 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
17393 _("immediate out of range for insert"));
17394 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
17400 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17401 struct neon_type_el et
= neon_check_type (2, rs
,
17402 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
17403 int imm
= inst
.operands
[2].imm
;
17404 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
17405 _("immediate out of range for insert"));
17406 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
17410 do_neon_qshlu_imm (void)
17412 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17413 struct neon_type_el et
= neon_check_type (2, rs
,
17414 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
17415 int imm
= inst
.operands
[2].imm
;
17416 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
17417 _("immediate out of range for shift"));
17418 /* Only encodes the 'U present' variant of the instruction.
17419 In this case, signed types have OP (bit 8) set to 0.
17420 Unsigned types have OP set to 1. */
17421 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
17422 /* The rest of the bits are the same as other immediate shifts. */
17423 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
17427 do_neon_qmovn (void)
17429 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
17430 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
17431 /* Saturating move where operands can be signed or unsigned, and the
17432 destination has the same signedness. */
17433 NEON_ENCODE (INTEGER
, inst
);
17434 if (et
.type
== NT_unsigned
)
17435 inst
.instruction
|= 0xc0;
17437 inst
.instruction
|= 0x80;
17438 neon_two_same (0, 1, et
.size
/ 2);
17442 do_neon_qmovun (void)
17444 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
17445 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
17446 /* Saturating move with unsigned results. Operands must be signed. */
17447 NEON_ENCODE (INTEGER
, inst
);
17448 neon_two_same (0, 1, et
.size
/ 2);
17452 do_neon_rshift_sat_narrow (void)
17454 /* FIXME: Types for narrowing. If operands are signed, results can be signed
17455 or unsigned. If operands are unsigned, results must also be unsigned. */
17456 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
17457 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
17458 int imm
= inst
.operands
[2].imm
;
17459 /* This gets the bounds check, size encoding and immediate bits calculation
17463 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
17464 VQMOVN.I<size> <Dd>, <Qm>. */
17467 inst
.operands
[2].present
= 0;
17468 inst
.instruction
= N_MNEM_vqmovn
;
17473 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
17474 _("immediate out of range"));
17475 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
17479 do_neon_rshift_sat_narrow_u (void)
17481 /* FIXME: Types for narrowing. If operands are signed, results can be signed
17482 or unsigned. If operands are unsigned, results must also be unsigned. */
17483 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
17484 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
17485 int imm
= inst
.operands
[2].imm
;
17486 /* This gets the bounds check, size encoding and immediate bits calculation
17490 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
17491 VQMOVUN.I<size> <Dd>, <Qm>. */
17494 inst
.operands
[2].present
= 0;
17495 inst
.instruction
= N_MNEM_vqmovun
;
17500 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
17501 _("immediate out of range"));
17502 /* FIXME: The manual is kind of unclear about what value U should have in
17503 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
17505 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
17509 do_neon_movn (void)
17511 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
17512 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
17513 NEON_ENCODE (INTEGER
, inst
);
17514 neon_two_same (0, 1, et
.size
/ 2);
17518 do_neon_rshift_narrow (void)
17520 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
17521 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
17522 int imm
= inst
.operands
[2].imm
;
17523 /* This gets the bounds check, size encoding and immediate bits calculation
17527 /* If immediate is zero then we are a pseudo-instruction for
17528 VMOVN.I<size> <Dd>, <Qm> */
17531 inst
.operands
[2].present
= 0;
17532 inst
.instruction
= N_MNEM_vmovn
;
17537 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
17538 _("immediate out of range for narrowing operation"));
17539 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
17543 do_neon_shll (void)
17545 /* FIXME: Type checking when lengthening. */
17546 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
17547 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
17548 unsigned imm
= inst
.operands
[2].imm
;
17550 if (imm
== et
.size
)
17552 /* Maximum shift variant. */
17553 NEON_ENCODE (INTEGER
, inst
);
17554 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17555 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17556 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17557 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17558 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17560 neon_dp_fixup (&inst
);
17564 /* A more-specific type check for non-max versions. */
17565 et
= neon_check_type (2, NS_QDI
,
17566 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
17567 NEON_ENCODE (IMMED
, inst
);
17568 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
17572 /* Check the various types for the VCVT instruction, and return which version
17573 the current instruction is. */
17575 #define CVT_FLAVOUR_VAR \
17576 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
17577 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
17578 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
17579 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
17580 /* Half-precision conversions. */ \
17581 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
17582 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
17583 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
17584 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
17585 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
17586 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
17587 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
17588 Compared with single/double precision variants, only the co-processor \
17589 field is different, so the encoding flow is reused here. */ \
17590 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
17591 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
17592 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
17593 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
17594 /* VFP instructions. */ \
17595 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
17596 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
17597 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
17598 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
17599 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
17600 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
17601 /* VFP instructions with bitshift. */ \
17602 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
17603 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
17604 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
17605 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
17606 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
17607 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
17608 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
17609 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
17611 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
17612 neon_cvt_flavour_##C,
17614 /* The different types of conversions we can do. */
17615 enum neon_cvt_flavour
17618 neon_cvt_flavour_invalid
,
17619 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
17624 static enum neon_cvt_flavour
17625 get_neon_cvt_flavour (enum neon_shape rs
)
17627 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
17628 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
17629 if (et.type != NT_invtype) \
17631 inst.error = NULL; \
17632 return (neon_cvt_flavour_##C); \
17635 struct neon_type_el et
;
17636 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
17637 || rs
== NS_FF
) ? N_VFP
: 0;
17638 /* The instruction versions which take an immediate take one register
17639 argument, which is extended to the width of the full register. Thus the
17640 "source" and "destination" registers must have the same width. Hack that
17641 here by making the size equal to the key (wider, in this case) operand. */
17642 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
17646 return neon_cvt_flavour_invalid
;
17661 /* Neon-syntax VFP conversions. */
17664 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
17666 const char *opname
= 0;
17668 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
17669 || rs
== NS_FHI
|| rs
== NS_HFI
)
17671 /* Conversions with immediate bitshift. */
17672 const char *enc
[] =
17674 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
17680 if (flavour
< (int) ARRAY_SIZE (enc
))
17682 opname
= enc
[flavour
];
17683 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17684 _("operands 0 and 1 must be the same register"));
17685 inst
.operands
[1] = inst
.operands
[2];
17686 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
17691 /* Conversions without bitshift. */
17692 const char *enc
[] =
17694 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
17700 if (flavour
< (int) ARRAY_SIZE (enc
))
17701 opname
= enc
[flavour
];
17705 do_vfp_nsyn_opcode (opname
);
17707 /* ARMv8.2 fp16 VCVT instruction. */
17708 if (flavour
== neon_cvt_flavour_s32_f16
17709 || flavour
== neon_cvt_flavour_u32_f16
17710 || flavour
== neon_cvt_flavour_f16_u32
17711 || flavour
== neon_cvt_flavour_f16_s32
)
17712 do_scalar_fp16_v82_encode ();
17716 do_vfp_nsyn_cvtz (void)
17718 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
17719 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
17720 const char *enc
[] =
17722 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
17728 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
17729 do_vfp_nsyn_opcode (enc
[flavour
]);
17733 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
17734 enum neon_cvt_mode mode
)
17739 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17740 D register operands. */
17741 if (flavour
== neon_cvt_flavour_s32_f64
17742 || flavour
== neon_cvt_flavour_u32_f64
)
17743 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17746 if (flavour
== neon_cvt_flavour_s32_f16
17747 || flavour
== neon_cvt_flavour_u32_f16
)
17748 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
17751 set_pred_insn_type (OUTSIDE_PRED_INSN
);
17755 case neon_cvt_flavour_s32_f64
:
17759 case neon_cvt_flavour_s32_f32
:
17763 case neon_cvt_flavour_s32_f16
:
17767 case neon_cvt_flavour_u32_f64
:
17771 case neon_cvt_flavour_u32_f32
:
17775 case neon_cvt_flavour_u32_f16
:
17780 first_error (_("invalid instruction shape"));
17786 case neon_cvt_mode_a
: rm
= 0; break;
17787 case neon_cvt_mode_n
: rm
= 1; break;
17788 case neon_cvt_mode_p
: rm
= 2; break;
17789 case neon_cvt_mode_m
: rm
= 3; break;
17790 default: first_error (_("invalid rounding mode")); return;
17793 NEON_ENCODE (FPV8
, inst
);
17794 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
17795 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
17796 inst
.instruction
|= sz
<< 8;
17798 /* ARMv8.2 fp16 VCVT instruction. */
17799 if (flavour
== neon_cvt_flavour_s32_f16
17800 ||flavour
== neon_cvt_flavour_u32_f16
)
17801 do_scalar_fp16_v82_encode ();
17802 inst
.instruction
|= op
<< 7;
17803 inst
.instruction
|= rm
<< 16;
17804 inst
.instruction
|= 0xf0000000;
17805 inst
.is_neon
= TRUE
;
17809 do_neon_cvt_1 (enum neon_cvt_mode mode
)
17811 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
17812 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
17813 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
17815 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
17817 if (flavour
== neon_cvt_flavour_invalid
)
17820 /* PR11109: Handle round-to-zero for VCVT conversions. */
17821 if (mode
== neon_cvt_mode_z
17822 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
17823 && (flavour
== neon_cvt_flavour_s16_f16
17824 || flavour
== neon_cvt_flavour_u16_f16
17825 || flavour
== neon_cvt_flavour_s32_f32
17826 || flavour
== neon_cvt_flavour_u32_f32
17827 || flavour
== neon_cvt_flavour_s32_f64
17828 || flavour
== neon_cvt_flavour_u32_f64
)
17829 && (rs
== NS_FD
|| rs
== NS_FF
))
17831 do_vfp_nsyn_cvtz ();
17835 /* ARMv8.2 fp16 VCVT conversions. */
17836 if (mode
== neon_cvt_mode_z
17837 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
17838 && (flavour
== neon_cvt_flavour_s32_f16
17839 || flavour
== neon_cvt_flavour_u32_f16
)
17842 do_vfp_nsyn_cvtz ();
17843 do_scalar_fp16_v82_encode ();
17847 /* VFP rather than Neon conversions. */
17848 if (flavour
>= neon_cvt_flavour_first_fp
)
17850 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
17851 do_vfp_nsyn_cvt (rs
, flavour
);
17853 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
17861 if (mode
== neon_cvt_mode_z
17862 && (flavour
== neon_cvt_flavour_f16_s16
17863 || flavour
== neon_cvt_flavour_f16_u16
17864 || flavour
== neon_cvt_flavour_s16_f16
17865 || flavour
== neon_cvt_flavour_u16_f16
17866 || flavour
== neon_cvt_flavour_f32_u32
17867 || flavour
== neon_cvt_flavour_f32_s32
17868 || flavour
== neon_cvt_flavour_s32_f32
17869 || flavour
== neon_cvt_flavour_u32_f32
))
17871 if (check_simd_pred_availability (1, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17874 else if (mode
== neon_cvt_mode_n
)
17876 /* We are dealing with vcvt with the 'ne' condition. */
17878 inst
.instruction
= N_MNEM_vcvt
;
17879 do_neon_cvt_1 (neon_cvt_mode_z
);
17882 /* fall through. */
17886 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
17887 0x0000100, 0x1000100, 0x0, 0x1000000};
17889 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17890 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17893 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17895 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
17896 _("immediate value out of range"));
17899 case neon_cvt_flavour_f16_s16
:
17900 case neon_cvt_flavour_f16_u16
:
17901 case neon_cvt_flavour_s16_f16
:
17902 case neon_cvt_flavour_u16_f16
:
17903 constraint (inst
.operands
[2].imm
> 16,
17904 _("immediate value out of range"));
17906 case neon_cvt_flavour_f32_u32
:
17907 case neon_cvt_flavour_f32_s32
:
17908 case neon_cvt_flavour_s32_f32
:
17909 case neon_cvt_flavour_u32_f32
:
17910 constraint (inst
.operands
[2].imm
> 32,
17911 _("immediate value out of range"));
17914 inst
.error
= BAD_FPU
;
17919 /* Fixed-point conversion with #0 immediate is encoded as an
17920 integer conversion. */
17921 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
17923 NEON_ENCODE (IMMED
, inst
);
17924 if (flavour
!= neon_cvt_flavour_invalid
)
17925 inst
.instruction
|= enctab
[flavour
];
17926 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17927 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17928 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17929 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17930 inst
.instruction
|= neon_quad (rs
) << 6;
17931 inst
.instruction
|= 1 << 21;
17932 if (flavour
< neon_cvt_flavour_s16_f16
)
17934 inst
.instruction
|= 1 << 21;
17935 immbits
= 32 - inst
.operands
[2].imm
;
17936 inst
.instruction
|= immbits
<< 16;
17940 inst
.instruction
|= 3 << 20;
17941 immbits
= 16 - inst
.operands
[2].imm
;
17942 inst
.instruction
|= immbits
<< 16;
17943 inst
.instruction
&= ~(1 << 9);
17946 neon_dp_fixup (&inst
);
17951 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17952 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
17953 && (flavour
== neon_cvt_flavour_s16_f16
17954 || flavour
== neon_cvt_flavour_u16_f16
17955 || flavour
== neon_cvt_flavour_s32_f32
17956 || flavour
== neon_cvt_flavour_u32_f32
))
17958 if (check_simd_pred_availability (1,
17959 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
17962 else if (mode
== neon_cvt_mode_z
17963 && (flavour
== neon_cvt_flavour_f16_s16
17964 || flavour
== neon_cvt_flavour_f16_u16
17965 || flavour
== neon_cvt_flavour_s16_f16
17966 || flavour
== neon_cvt_flavour_u16_f16
17967 || flavour
== neon_cvt_flavour_f32_u32
17968 || flavour
== neon_cvt_flavour_f32_s32
17969 || flavour
== neon_cvt_flavour_s32_f32
17970 || flavour
== neon_cvt_flavour_u32_f32
))
17972 if (check_simd_pred_availability (1,
17973 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17976 /* fall through. */
17978 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
17981 NEON_ENCODE (FLOAT
, inst
);
17982 if (check_simd_pred_availability (1,
17983 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
17986 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17987 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17988 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17989 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17990 inst
.instruction
|= neon_quad (rs
) << 6;
17991 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
17992 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
17993 inst
.instruction
|= mode
<< 8;
17994 if (flavour
== neon_cvt_flavour_u16_f16
17995 || flavour
== neon_cvt_flavour_s16_f16
)
17996 /* Mask off the original size bits and reencode them. */
17997 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
18000 inst
.instruction
|= 0xfc000000;
18002 inst
.instruction
|= 0xf0000000;
18008 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
18009 0x100, 0x180, 0x0, 0x080};
18011 NEON_ENCODE (INTEGER
, inst
);
18013 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18015 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18019 if (flavour
!= neon_cvt_flavour_invalid
)
18020 inst
.instruction
|= enctab
[flavour
];
18022 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18023 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18024 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18025 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18026 inst
.instruction
|= neon_quad (rs
) << 6;
18027 if (flavour
>= neon_cvt_flavour_s16_f16
18028 && flavour
<= neon_cvt_flavour_f16_u16
)
18029 /* Half precision. */
18030 inst
.instruction
|= 1 << 18;
18032 inst
.instruction
|= 2 << 18;
18034 neon_dp_fixup (&inst
);
18039 /* Half-precision conversions for Advanced SIMD -- neon. */
18042 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18046 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
18048 as_bad (_("operand size must match register width"));
18053 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
18055 as_bad (_("operand size must match register width"));
18060 inst
.instruction
= 0x3b60600;
18062 inst
.instruction
= 0x3b60700;
18064 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18065 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18066 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18067 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18068 neon_dp_fixup (&inst
);
18072 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
18073 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
18074 do_vfp_nsyn_cvt (rs
, flavour
);
18076 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
18081 do_neon_cvtr (void)
18083 do_neon_cvt_1 (neon_cvt_mode_x
);
18089 do_neon_cvt_1 (neon_cvt_mode_z
);
18093 do_neon_cvta (void)
18095 do_neon_cvt_1 (neon_cvt_mode_a
);
18099 do_neon_cvtn (void)
18101 do_neon_cvt_1 (neon_cvt_mode_n
);
18105 do_neon_cvtp (void)
18107 do_neon_cvt_1 (neon_cvt_mode_p
);
18111 do_neon_cvtm (void)
18113 do_neon_cvt_1 (neon_cvt_mode_m
);
18117 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
18120 mark_feature_used (&fpu_vfp_ext_armv8
);
18122 encode_arm_vfp_reg (inst
.operands
[0].reg
,
18123 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
18124 encode_arm_vfp_reg (inst
.operands
[1].reg
,
18125 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
18126 inst
.instruction
|= to
? 0x10000 : 0;
18127 inst
.instruction
|= t
? 0x80 : 0;
18128 inst
.instruction
|= is_double
? 0x100 : 0;
18129 do_vfp_cond_or_thumb ();
18133 do_neon_cvttb_1 (bfd_boolean t
)
18135 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
18136 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
18140 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
18142 int single_to_half
= 0;
18143 if (check_simd_pred_availability (1, NEON_CHECK_ARCH
))
18146 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18148 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18149 && (flavour
== neon_cvt_flavour_u16_f16
18150 || flavour
== neon_cvt_flavour_s16_f16
18151 || flavour
== neon_cvt_flavour_f16_s16
18152 || flavour
== neon_cvt_flavour_f16_u16
18153 || flavour
== neon_cvt_flavour_u32_f32
18154 || flavour
== neon_cvt_flavour_s32_f32
18155 || flavour
== neon_cvt_flavour_f32_s32
18156 || flavour
== neon_cvt_flavour_f32_u32
))
18159 inst
.instruction
= N_MNEM_vcvt
;
18160 set_pred_insn_type (INSIDE_VPT_INSN
);
18161 do_neon_cvt_1 (neon_cvt_mode_z
);
18164 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
18165 single_to_half
= 1;
18166 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
18168 first_error (BAD_FPU
);
18172 inst
.instruction
= 0xee3f0e01;
18173 inst
.instruction
|= single_to_half
<< 28;
18174 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18175 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
18176 inst
.instruction
|= t
<< 12;
18177 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18178 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
18181 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
18184 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
18186 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
18189 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
18191 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
18193 /* The VCVTB and VCVTT instructions with D-register operands
18194 don't work for SP only targets. */
18195 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18199 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
18201 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
18203 /* The VCVTB and VCVTT instructions with D-register operands
18204 don't work for SP only targets. */
18205 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18209 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
18216 do_neon_cvtb (void)
18218 do_neon_cvttb_1 (FALSE
);
18223 do_neon_cvtt (void)
18225 do_neon_cvttb_1 (TRUE
);
18229 neon_move_immediate (void)
18231 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
18232 struct neon_type_el et
= neon_check_type (2, rs
,
18233 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
18234 unsigned immlo
, immhi
= 0, immbits
;
18235 int op
, cmode
, float_p
;
18237 constraint (et
.type
== NT_invtype
,
18238 _("operand size must be specified for immediate VMOV"));
18240 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
18241 op
= (inst
.instruction
& (1 << 5)) != 0;
18243 immlo
= inst
.operands
[1].imm
;
18244 if (inst
.operands
[1].regisimm
)
18245 immhi
= inst
.operands
[1].reg
;
18247 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
18248 _("immediate has bits set outside the operand size"));
18250 float_p
= inst
.operands
[1].immisfloat
;
18252 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
18253 et
.size
, et
.type
)) == FAIL
)
18255 /* Invert relevant bits only. */
18256 neon_invert_size (&immlo
, &immhi
, et
.size
);
18257 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
18258 with one or the other; those cases are caught by
18259 neon_cmode_for_move_imm. */
18261 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
18262 &op
, et
.size
, et
.type
)) == FAIL
)
18264 first_error (_("immediate out of range"));
18269 inst
.instruction
&= ~(1 << 5);
18270 inst
.instruction
|= op
<< 5;
18272 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18273 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18274 inst
.instruction
|= neon_quad (rs
) << 6;
18275 inst
.instruction
|= cmode
<< 8;
18277 neon_write_immbits (immbits
);
18283 if (inst
.operands
[1].isreg
)
18285 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18287 NEON_ENCODE (INTEGER
, inst
);
18288 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18289 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18290 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18291 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18292 inst
.instruction
|= neon_quad (rs
) << 6;
18296 NEON_ENCODE (IMMED
, inst
);
18297 neon_move_immediate ();
18300 neon_dp_fixup (&inst
);
18303 /* Encode instructions of form:
18305 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
18306 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
18309 neon_mixed_length (struct neon_type_el et
, unsigned size
)
18311 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18312 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18313 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
18314 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
18315 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
18316 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
18317 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
18318 inst
.instruction
|= neon_logbits (size
) << 20;
18320 neon_dp_fixup (&inst
);
18324 do_neon_dyadic_long (void)
18326 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
18329 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
18332 NEON_ENCODE (INTEGER
, inst
);
18333 /* FIXME: Type checking for lengthening op. */
18334 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
18335 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
18336 neon_mixed_length (et
, et
.size
);
18338 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18339 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
18341 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
18342 in an IT block with le/lt conditions. */
18344 if (inst
.cond
== 0xf)
18346 else if (inst
.cond
== 0x10)
18349 inst
.pred_insn_type
= INSIDE_IT_INSN
;
18351 if (inst
.instruction
== N_MNEM_vaddl
)
18353 inst
.instruction
= N_MNEM_vadd
;
18354 do_neon_addsub_if_i ();
18356 else if (inst
.instruction
== N_MNEM_vsubl
)
18358 inst
.instruction
= N_MNEM_vsub
;
18359 do_neon_addsub_if_i ();
18361 else if (inst
.instruction
== N_MNEM_vabdl
)
18363 inst
.instruction
= N_MNEM_vabd
;
18364 do_neon_dyadic_if_su ();
18368 first_error (BAD_FPU
);
18372 do_neon_abal (void)
18374 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
18375 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
18376 neon_mixed_length (et
, et
.size
);
18380 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
18382 if (inst
.operands
[2].isscalar
)
18384 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
18385 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
18386 NEON_ENCODE (SCALAR
, inst
);
18387 neon_mul_mac (et
, et
.type
== NT_unsigned
);
18391 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
18392 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
18393 NEON_ENCODE (INTEGER
, inst
);
18394 neon_mixed_length (et
, et
.size
);
18399 do_neon_mac_maybe_scalar_long (void)
18401 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
18404 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
18405 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
18408 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
18410 unsigned regno
= NEON_SCALAR_REG (scalar
);
18411 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
18415 if (regno
> 7 || elno
> 3)
18418 return ((regno
& 0x7)
18419 | ((elno
& 0x1) << 3)
18420 | (((elno
>> 1) & 0x1) << 5));
18424 if (regno
> 15 || elno
> 1)
18427 return (((regno
& 0x1) << 5)
18428 | ((regno
>> 1) & 0x7)
18429 | ((elno
& 0x1) << 3));
18433 first_error (_("scalar out of range for multiply instruction"));
18438 do_neon_fmac_maybe_scalar_long (int subtype
)
18440 enum neon_shape rs
;
18442 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
18443 field (bits[21:20]) has different meaning. For scalar index variant, it's
18444 used to differentiate add and subtract, otherwise it's with fixed value
18448 if (inst
.cond
!= COND_ALWAYS
)
18449 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
18450 "behaviour is UNPREDICTABLE"));
18452 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
18455 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
18458 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
18459 be a scalar index register. */
18460 if (inst
.operands
[2].isscalar
)
18462 high8
= 0xfe000000;
18465 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
18469 high8
= 0xfc000000;
18472 inst
.instruction
|= (0x1 << 23);
18473 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
18476 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
18478 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
18479 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
18480 so we simply pass -1 as size. */
18481 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
18482 neon_three_same (quad_p
, 0, size
);
18484 /* Undo neon_dp_fixup. Redo the high eight bits. */
18485 inst
.instruction
&= 0x00ffffff;
18486 inst
.instruction
|= high8
;
18488 #define LOW1(R) ((R) & 0x1)
18489 #define HI4(R) (((R) >> 1) & 0xf)
18490 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
18491 whether the instruction is in Q form and whether Vm is a scalar indexed
18493 if (inst
.operands
[2].isscalar
)
18496 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
18497 inst
.instruction
&= 0xffffffd0;
18498 inst
.instruction
|= rm
;
18502 /* Redo Rn as well. */
18503 inst
.instruction
&= 0xfff0ff7f;
18504 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
18505 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
18510 /* Redo Rn and Rm. */
18511 inst
.instruction
&= 0xfff0ff50;
18512 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
18513 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
18514 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
18515 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
18520 do_neon_vfmal (void)
18522 return do_neon_fmac_maybe_scalar_long (0);
18526 do_neon_vfmsl (void)
18528 return do_neon_fmac_maybe_scalar_long (1);
18532 do_neon_dyadic_wide (void)
18534 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
18535 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18536 neon_mixed_length (et
, et
.size
);
18540 do_neon_dyadic_narrow (void)
18542 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
18543 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
18544 /* Operand sign is unimportant, and the U bit is part of the opcode,
18545 so force the operand type to integer. */
18546 et
.type
= NT_integer
;
18547 neon_mixed_length (et
, et
.size
/ 2);
18551 do_neon_mul_sat_scalar_long (void)
18553 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
18557 do_neon_vmull (void)
18559 if (inst
.operands
[2].isscalar
)
18560 do_neon_mac_maybe_scalar_long ();
18563 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
18564 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
18566 if (et
.type
== NT_poly
)
18567 NEON_ENCODE (POLY
, inst
);
18569 NEON_ENCODE (INTEGER
, inst
);
18571 /* For polynomial encoding the U bit must be zero, and the size must
18572 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
18573 obviously, as 0b10). */
18576 /* Check we're on the correct architecture. */
18577 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
18579 _("Instruction form not available on this architecture.");
18584 neon_mixed_length (et
, et
.size
);
18591 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
18592 struct neon_type_el et
= neon_check_type (3, rs
,
18593 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18594 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
18596 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
18597 _("shift out of range"));
18598 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18599 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18600 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
18601 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
18602 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
18603 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
18604 inst
.instruction
|= neon_quad (rs
) << 6;
18605 inst
.instruction
|= imm
<< 8;
18607 neon_dp_fixup (&inst
);
18613 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18614 struct neon_type_el et
= neon_check_type (2, rs
,
18615 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18616 unsigned op
= (inst
.instruction
>> 7) & 3;
18617 /* N (width of reversed regions) is encoded as part of the bitmask. We
18618 extract it here to check the elements to be reversed are smaller.
18619 Otherwise we'd get a reserved instruction. */
18620 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
18621 gas_assert (elsize
!= 0);
18622 constraint (et
.size
>= elsize
,
18623 _("elements must be smaller than reversal region"));
18624 neon_two_same (neon_quad (rs
), 1, et
.size
);
18630 if (inst
.operands
[1].isscalar
)
18632 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
18634 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
18635 struct neon_type_el et
= neon_check_type (2, rs
,
18636 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18637 unsigned sizebits
= et
.size
>> 3;
18638 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
18639 int logsize
= neon_logbits (et
.size
);
18640 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
18642 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
18645 NEON_ENCODE (SCALAR
, inst
);
18646 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18647 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18648 inst
.instruction
|= LOW4 (dm
);
18649 inst
.instruction
|= HI1 (dm
) << 5;
18650 inst
.instruction
|= neon_quad (rs
) << 6;
18651 inst
.instruction
|= x
<< 17;
18652 inst
.instruction
|= sizebits
<< 16;
18654 neon_dp_fixup (&inst
);
18658 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
18659 struct neon_type_el et
= neon_check_type (2, rs
,
18660 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
18663 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
))
18667 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
18670 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18672 if (inst
.operands
[1].reg
== REG_SP
)
18673 as_tsktsk (MVE_BAD_SP
);
18674 else if (inst
.operands
[1].reg
== REG_PC
)
18675 as_tsktsk (MVE_BAD_PC
);
18678 /* Duplicate ARM register to lanes of vector. */
18679 NEON_ENCODE (ARMREG
, inst
);
18682 case 8: inst
.instruction
|= 0x400000; break;
18683 case 16: inst
.instruction
|= 0x000020; break;
18684 case 32: inst
.instruction
|= 0x000000; break;
18687 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
18688 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
18689 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
18690 inst
.instruction
|= neon_quad (rs
) << 21;
18691 /* The encoding for this instruction is identical for the ARM and Thumb
18692 variants, except for the condition field. */
18693 do_vfp_cond_or_thumb ();
18698 do_mve_mov (int toQ
)
18700 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18702 if (inst
.cond
> COND_ALWAYS
)
18703 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
18705 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
18714 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
18715 _("Index one must be [2,3] and index two must be two less than"
18717 constraint (inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
18718 _("General purpose registers may not be the same"));
18719 constraint (inst
.operands
[Rt
].reg
== REG_SP
18720 || inst
.operands
[Rt2
].reg
== REG_SP
,
18722 constraint (inst
.operands
[Rt
].reg
== REG_PC
18723 || inst
.operands
[Rt2
].reg
== REG_PC
,
18726 inst
.instruction
= 0xec000f00;
18727 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
18728 inst
.instruction
|= !!toQ
<< 20;
18729 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
18730 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
18731 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
18732 inst
.instruction
|= inst
.operands
[Rt
].reg
;
18738 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18741 if (inst
.cond
> COND_ALWAYS
)
18742 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18744 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18746 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
18749 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18750 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
18751 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18752 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18753 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18758 /* VMOV has particularly many variations. It can be one of:
18759 0. VMOV<c><q> <Qd>, <Qm>
18760 1. VMOV<c><q> <Dd>, <Dm>
18761 (Register operations, which are VORR with Rm = Rn.)
18762 2. VMOV<c><q>.<dt> <Qd>, #<imm>
18763 3. VMOV<c><q>.<dt> <Dd>, #<imm>
18765 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
18766 (ARM register to scalar.)
18767 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
18768 (Two ARM registers to vector.)
18769 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
18770 (Scalar to ARM register.)
18771 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
18772 (Vector to two ARM registers.)
18773 8. VMOV.F32 <Sd>, <Sm>
18774 9. VMOV.F64 <Dd>, <Dm>
18775 (VFP register moves.)
18776 10. VMOV.F32 <Sd>, #imm
18777 11. VMOV.F64 <Dd>, #imm
18778 (VFP float immediate load.)
18779 12. VMOV <Rd>, <Sm>
18780 (VFP single to ARM reg.)
18781 13. VMOV <Sd>, <Rm>
18782 (ARM reg to VFP single.)
18783 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
18784 (Two ARM regs to two VFP singles.)
18785 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
18786 (Two VFP singles to two ARM regs.)
18787 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
18788 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
18789 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
18790 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
18792 These cases can be disambiguated using neon_select_shape, except cases 1/9
18793 and 3/11 which depend on the operand type too.
18795 All the encoded bits are hardcoded by this function.
18797 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
18798 Cases 5, 7 may be used with VFPv2 and above.
18800 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
18801 can specify a type where it doesn't make sense to, and is ignored). */
18806 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
18807 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
18808 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
18809 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
18811 struct neon_type_el et
;
18812 const char *ldconst
= 0;
18816 case NS_DD
: /* case 1/9. */
18817 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
18818 /* It is not an error here if no type is given. */
18820 if (et
.type
== NT_float
&& et
.size
== 64)
18822 do_vfp_nsyn_opcode ("fcpyd");
18825 /* fall through. */
18827 case NS_QQ
: /* case 0/1. */
18829 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18831 /* The architecture manual I have doesn't explicitly state which
18832 value the U bit should have for register->register moves, but
18833 the equivalent VORR instruction has U = 0, so do that. */
18834 inst
.instruction
= 0x0200110;
18835 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18836 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18837 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18838 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18839 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
18840 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
18841 inst
.instruction
|= neon_quad (rs
) << 6;
18843 neon_dp_fixup (&inst
);
18847 case NS_DI
: /* case 3/11. */
18848 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
18850 if (et
.type
== NT_float
&& et
.size
== 64)
18852 /* case 11 (fconstd). */
18853 ldconst
= "fconstd";
18854 goto encode_fconstd
;
18856 /* fall through. */
18858 case NS_QI
: /* case 2/3. */
18859 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18861 inst
.instruction
= 0x0800010;
18862 neon_move_immediate ();
18863 neon_dp_fixup (&inst
);
18866 case NS_SR
: /* case 4. */
18868 unsigned bcdebits
= 0;
18870 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
18871 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
18873 /* .<size> is optional here, defaulting to .32. */
18874 if (inst
.vectype
.elems
== 0
18875 && inst
.operands
[0].vectype
.type
== NT_invtype
18876 && inst
.operands
[1].vectype
.type
== NT_invtype
)
18878 inst
.vectype
.el
[0].type
= NT_untyped
;
18879 inst
.vectype
.el
[0].size
= 32;
18880 inst
.vectype
.elems
= 1;
18883 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
18884 logsize
= neon_logbits (et
.size
);
18888 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18889 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
18894 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
18895 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
18899 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18901 if (inst
.operands
[1].reg
== REG_SP
)
18902 as_tsktsk (MVE_BAD_SP
);
18903 else if (inst
.operands
[1].reg
== REG_PC
)
18904 as_tsktsk (MVE_BAD_PC
);
18906 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
18908 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
18909 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
18914 case 8: bcdebits
= 0x8; break;
18915 case 16: bcdebits
= 0x1; break;
18916 case 32: bcdebits
= 0x0; break;
18920 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
18922 inst
.instruction
= 0xe000b10;
18923 do_vfp_cond_or_thumb ();
18924 inst
.instruction
|= LOW4 (dn
) << 16;
18925 inst
.instruction
|= HI1 (dn
) << 7;
18926 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
18927 inst
.instruction
|= (bcdebits
& 3) << 5;
18928 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
18929 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
18933 case NS_DRR
: /* case 5 (fmdrr). */
18934 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
18935 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
18938 inst
.instruction
= 0xc400b10;
18939 do_vfp_cond_or_thumb ();
18940 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
18941 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
18942 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
18943 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
18946 case NS_RS
: /* case 6. */
18949 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
18950 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
18951 unsigned abcdebits
= 0;
18953 /* .<dt> is optional here, defaulting to .32. */
18954 if (inst
.vectype
.elems
== 0
18955 && inst
.operands
[0].vectype
.type
== NT_invtype
18956 && inst
.operands
[1].vectype
.type
== NT_invtype
)
18958 inst
.vectype
.el
[0].type
= NT_untyped
;
18959 inst
.vectype
.el
[0].size
= 32;
18960 inst
.vectype
.elems
= 1;
18963 et
= neon_check_type (2, NS_NULL
,
18964 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
18965 logsize
= neon_logbits (et
.size
);
18969 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18970 && vfp_or_neon_is_neon (NEON_CHECK_CC
18971 | NEON_CHECK_ARCH
) == FAIL
)
18976 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
18977 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
18981 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18983 if (inst
.operands
[0].reg
== REG_SP
)
18984 as_tsktsk (MVE_BAD_SP
);
18985 else if (inst
.operands
[0].reg
== REG_PC
)
18986 as_tsktsk (MVE_BAD_PC
);
18989 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
18991 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
18992 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
18996 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
18997 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
18998 case 32: abcdebits
= 0x00; break;
19002 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
19003 inst
.instruction
= 0xe100b10;
19004 do_vfp_cond_or_thumb ();
19005 inst
.instruction
|= LOW4 (dn
) << 16;
19006 inst
.instruction
|= HI1 (dn
) << 7;
19007 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
19008 inst
.instruction
|= (abcdebits
& 3) << 5;
19009 inst
.instruction
|= (abcdebits
>> 2) << 21;
19010 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
19014 case NS_RRD
: /* case 7 (fmrrd). */
19015 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19016 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19019 inst
.instruction
= 0xc500b10;
19020 do_vfp_cond_or_thumb ();
19021 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
19022 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
19023 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19024 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19027 case NS_FF
: /* case 8 (fcpys). */
19028 do_vfp_nsyn_opcode ("fcpys");
19032 case NS_FI
: /* case 10 (fconsts). */
19033 ldconst
= "fconsts";
19035 if (!inst
.operands
[1].immisfloat
)
19038 /* Immediate has to fit in 8 bits so float is enough. */
19039 float imm
= (float) inst
.operands
[1].imm
;
19040 memcpy (&new_imm
, &imm
, sizeof (float));
19041 /* But the assembly may have been written to provide an integer
19042 bit pattern that equates to a float, so check that the
19043 conversion has worked. */
19044 if (is_quarter_float (new_imm
))
19046 if (is_quarter_float (inst
.operands
[1].imm
))
19047 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
19049 inst
.operands
[1].imm
= new_imm
;
19050 inst
.operands
[1].immisfloat
= 1;
19054 if (is_quarter_float (inst
.operands
[1].imm
))
19056 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
19057 do_vfp_nsyn_opcode (ldconst
);
19059 /* ARMv8.2 fp16 vmov.f16 instruction. */
19061 do_scalar_fp16_v82_encode ();
19064 first_error (_("immediate out of range"));
19068 case NS_RF
: /* case 12 (fmrs). */
19069 do_vfp_nsyn_opcode ("fmrs");
19070 /* ARMv8.2 fp16 vmov.f16 instruction. */
19072 do_scalar_fp16_v82_encode ();
19076 case NS_FR
: /* case 13 (fmsr). */
19077 do_vfp_nsyn_opcode ("fmsr");
19078 /* ARMv8.2 fp16 vmov.f16 instruction. */
19080 do_scalar_fp16_v82_encode ();
19090 /* The encoders for the fmrrs and fmsrr instructions expect three operands
19091 (one of which is a list), but we have parsed four. Do some fiddling to
19092 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
19094 case NS_RRFF
: /* case 14 (fmrrs). */
19095 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19096 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19098 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
19099 _("VFP registers must be adjacent"));
19100 inst
.operands
[2].imm
= 2;
19101 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
19102 do_vfp_nsyn_opcode ("fmrrs");
19105 case NS_FFRR
: /* case 15 (fmsrr). */
19106 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19107 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19109 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
19110 _("VFP registers must be adjacent"));
19111 inst
.operands
[1] = inst
.operands
[2];
19112 inst
.operands
[2] = inst
.operands
[3];
19113 inst
.operands
[0].imm
= 2;
19114 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
19115 do_vfp_nsyn_opcode ("fmsrr");
19119 /* neon_select_shape has determined that the instruction
19120 shape is wrong and has already set the error message. */
19131 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
19132 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
19133 && !inst
.operands
[2].present
))
19135 inst
.instruction
= 0;
19138 set_pred_insn_type (INSIDE_IT_INSN
);
19143 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19146 if (inst
.cond
!= COND_ALWAYS
)
19147 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
19149 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
19150 | N_S16
| N_U16
| N_KEY
);
19152 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
19153 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19154 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
19155 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19156 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19157 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19162 do_neon_rshift_round_imm (void)
19164 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
19165 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
19166 int imm
= inst
.operands
[2].imm
;
19168 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
19171 inst
.operands
[2].present
= 0;
19176 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
19177 _("immediate out of range for shift"));
19178 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
19183 do_neon_movhf (void)
19185 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
19186 constraint (rs
!= NS_HH
, _("invalid suffix"));
19188 if (inst
.cond
!= COND_ALWAYS
)
19192 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
19193 " the behaviour is UNPREDICTABLE"));
19197 inst
.error
= BAD_COND
;
19202 do_vfp_sp_monadic ();
19205 inst
.instruction
|= 0xf0000000;
19209 do_neon_movl (void)
19211 struct neon_type_el et
= neon_check_type (2, NS_QD
,
19212 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19213 unsigned sizebits
= et
.size
>> 3;
19214 inst
.instruction
|= sizebits
<< 19;
19215 neon_two_same (0, et
.type
== NT_unsigned
, -1);
19221 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19222 struct neon_type_el et
= neon_check_type (2, rs
,
19223 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19224 NEON_ENCODE (INTEGER
, inst
);
19225 neon_two_same (neon_quad (rs
), 1, et
.size
);
19229 do_neon_zip_uzp (void)
19231 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19232 struct neon_type_el et
= neon_check_type (2, rs
,
19233 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19234 if (rs
== NS_DD
&& et
.size
== 32)
19236 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
19237 inst
.instruction
= N_MNEM_vtrn
;
19241 neon_two_same (neon_quad (rs
), 1, et
.size
);
19245 do_neon_sat_abs_neg (void)
19247 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19248 struct neon_type_el et
= neon_check_type (2, rs
,
19249 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
19250 neon_two_same (neon_quad (rs
), 1, et
.size
);
19254 do_neon_pair_long (void)
19256 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19257 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
19258 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
19259 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
19260 neon_two_same (neon_quad (rs
), 1, et
.size
);
19264 do_neon_recip_est (void)
19266 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19267 struct neon_type_el et
= neon_check_type (2, rs
,
19268 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
19269 inst
.instruction
|= (et
.type
== NT_float
) << 8;
19270 neon_two_same (neon_quad (rs
), 1, et
.size
);
19276 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19279 enum neon_shape rs
;
19280 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19281 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19283 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19285 struct neon_type_el et
= neon_check_type (2, rs
,
19286 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
19287 neon_two_same (neon_quad (rs
), 1, et
.size
);
19293 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19296 enum neon_shape rs
;
19297 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19298 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19300 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19302 struct neon_type_el et
= neon_check_type (2, rs
,
19303 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
19304 neon_two_same (neon_quad (rs
), 1, et
.size
);
19310 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19311 struct neon_type_el et
= neon_check_type (2, rs
,
19312 N_EQK
| N_INT
, N_8
| N_KEY
);
19313 neon_two_same (neon_quad (rs
), 1, et
.size
);
19319 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19320 neon_two_same (neon_quad (rs
), 1, -1);
19324 do_neon_tbl_tbx (void)
19326 unsigned listlenbits
;
19327 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
19329 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
19331 first_error (_("bad list length for table lookup"));
19335 listlenbits
= inst
.operands
[1].imm
- 1;
19336 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19337 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19338 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19339 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19340 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19341 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19342 inst
.instruction
|= listlenbits
<< 8;
19344 neon_dp_fixup (&inst
);
19348 do_neon_ldm_stm (void)
19350 /* P, U and L bits are part of bitmask. */
19351 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
19352 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
19354 if (inst
.operands
[1].issingle
)
19356 do_vfp_nsyn_ldm_stm (is_dbmode
);
19360 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
19361 _("writeback (!) must be used for VLDMDB and VSTMDB"));
19363 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
19364 _("register list must contain at least 1 and at most 16 "
19367 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
19368 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
19369 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
19370 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
19372 inst
.instruction
|= offsetbits
;
19374 do_vfp_cond_or_thumb ();
19378 do_neon_ldr_str (void)
19380 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
19382 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
19383 And is UNPREDICTABLE in thumb mode. */
19385 && inst
.operands
[1].reg
== REG_PC
19386 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
19389 inst
.error
= _("Use of PC here is UNPREDICTABLE");
19390 else if (warn_on_deprecated
)
19391 as_tsktsk (_("Use of PC here is deprecated"));
19394 if (inst
.operands
[0].issingle
)
19397 do_vfp_nsyn_opcode ("flds");
19399 do_vfp_nsyn_opcode ("fsts");
19401 /* ARMv8.2 vldr.16/vstr.16 instruction. */
19402 if (inst
.vectype
.el
[0].size
== 16)
19403 do_scalar_fp16_v82_encode ();
19408 do_vfp_nsyn_opcode ("fldd");
19410 do_vfp_nsyn_opcode ("fstd");
19415 do_t_vldr_vstr_sysreg (void)
19417 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
19418 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
19420 /* Use of PC is UNPREDICTABLE. */
19421 if (inst
.operands
[1].reg
== REG_PC
)
19422 inst
.error
= _("Use of PC here is UNPREDICTABLE");
19424 if (inst
.operands
[1].immisreg
)
19425 inst
.error
= _("instruction does not accept register index");
19427 if (!inst
.operands
[1].isreg
)
19428 inst
.error
= _("instruction does not accept PC-relative addressing");
19430 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
19431 inst
.error
= _("immediate value out of range");
19433 inst
.instruction
= 0xec000f80;
19435 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
19436 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
19437 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
19438 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
19442 do_vldr_vstr (void)
19444 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
19446 /* VLDR/VSTR (System Register). */
19449 if (!mark_feature_used (&arm_ext_v8_1m_main
))
19450 as_bad (_("Instruction not permitted on this architecture"));
19452 do_t_vldr_vstr_sysreg ();
19457 if (!mark_feature_used (&fpu_vfp_ext_v1xd
))
19458 as_bad (_("Instruction not permitted on this architecture"));
19459 do_neon_ldr_str ();
19463 /* "interleave" version also handles non-interleaving register VLD1/VST1
19467 do_neon_ld_st_interleave (void)
19469 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
19470 N_8
| N_16
| N_32
| N_64
);
19471 unsigned alignbits
= 0;
19473 /* The bits in this table go:
19474 0: register stride of one (0) or two (1)
19475 1,2: register list length, minus one (1, 2, 3, 4).
19476 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
19477 We use -1 for invalid entries. */
19478 const int typetable
[] =
19480 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
19481 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
19482 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
19483 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
19487 if (et
.type
== NT_invtype
)
19490 if (inst
.operands
[1].immisalign
)
19491 switch (inst
.operands
[1].imm
>> 8)
19493 case 64: alignbits
= 1; break;
19495 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
19496 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
19497 goto bad_alignment
;
19501 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
19502 goto bad_alignment
;
19507 first_error (_("bad alignment"));
19511 inst
.instruction
|= alignbits
<< 4;
19512 inst
.instruction
|= neon_logbits (et
.size
) << 6;
19514 /* Bits [4:6] of the immediate in a list specifier encode register stride
19515 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
19516 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
19517 up the right value for "type" in a table based on this value and the given
19518 list style, then stick it back. */
19519 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
19520 | (((inst
.instruction
>> 8) & 3) << 3);
19522 typebits
= typetable
[idx
];
19524 constraint (typebits
== -1, _("bad list type for instruction"));
19525 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
19528 inst
.instruction
&= ~0xf00;
19529 inst
.instruction
|= typebits
<< 8;
19532 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
19533 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
19534 otherwise. The variable arguments are a list of pairs of legal (size, align)
19535 values, terminated with -1. */
19538 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
19541 int result
= FAIL
, thissize
, thisalign
;
19543 if (!inst
.operands
[1].immisalign
)
19549 va_start (ap
, do_alignment
);
19553 thissize
= va_arg (ap
, int);
19554 if (thissize
== -1)
19556 thisalign
= va_arg (ap
, int);
19558 if (size
== thissize
&& align
== thisalign
)
19561 while (result
!= SUCCESS
);
19565 if (result
== SUCCESS
)
19568 first_error (_("unsupported alignment for instruction"));
19574 do_neon_ld_st_lane (void)
19576 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
19577 int align_good
, do_alignment
= 0;
19578 int logsize
= neon_logbits (et
.size
);
19579 int align
= inst
.operands
[1].imm
>> 8;
19580 int n
= (inst
.instruction
>> 8) & 3;
19581 int max_el
= 64 / et
.size
;
19583 if (et
.type
== NT_invtype
)
19586 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
19587 _("bad list length"));
19588 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
19589 _("scalar index out of range"));
19590 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
19592 _("stride of 2 unavailable when element size is 8"));
19596 case 0: /* VLD1 / VST1. */
19597 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
19599 if (align_good
== FAIL
)
19603 unsigned alignbits
= 0;
19606 case 16: alignbits
= 0x1; break;
19607 case 32: alignbits
= 0x3; break;
19610 inst
.instruction
|= alignbits
<< 4;
19614 case 1: /* VLD2 / VST2. */
19615 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
19616 16, 32, 32, 64, -1);
19617 if (align_good
== FAIL
)
19620 inst
.instruction
|= 1 << 4;
19623 case 2: /* VLD3 / VST3. */
19624 constraint (inst
.operands
[1].immisalign
,
19625 _("can't use alignment with this instruction"));
19628 case 3: /* VLD4 / VST4. */
19629 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
19630 16, 64, 32, 64, 32, 128, -1);
19631 if (align_good
== FAIL
)
19635 unsigned alignbits
= 0;
19638 case 8: alignbits
= 0x1; break;
19639 case 16: alignbits
= 0x1; break;
19640 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
19643 inst
.instruction
|= alignbits
<< 4;
19650 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
19651 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
19652 inst
.instruction
|= 1 << (4 + logsize
);
19654 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
19655 inst
.instruction
|= logsize
<< 10;
19658 /* Encode single n-element structure to all lanes VLD<n> instructions. */
19661 do_neon_ld_dup (void)
19663 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
19664 int align_good
, do_alignment
= 0;
19666 if (et
.type
== NT_invtype
)
19669 switch ((inst
.instruction
>> 8) & 3)
19671 case 0: /* VLD1. */
19672 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
19673 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
19674 &do_alignment
, 16, 16, 32, 32, -1);
19675 if (align_good
== FAIL
)
19677 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
19680 case 2: inst
.instruction
|= 1 << 5; break;
19681 default: first_error (_("bad list length")); return;
19683 inst
.instruction
|= neon_logbits (et
.size
) << 6;
19686 case 1: /* VLD2. */
19687 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
19688 &do_alignment
, 8, 16, 16, 32, 32, 64,
19690 if (align_good
== FAIL
)
19692 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
19693 _("bad list length"));
19694 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
19695 inst
.instruction
|= 1 << 5;
19696 inst
.instruction
|= neon_logbits (et
.size
) << 6;
19699 case 2: /* VLD3. */
19700 constraint (inst
.operands
[1].immisalign
,
19701 _("can't use alignment with this instruction"));
19702 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
19703 _("bad list length"));
19704 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
19705 inst
.instruction
|= 1 << 5;
19706 inst
.instruction
|= neon_logbits (et
.size
) << 6;
19709 case 3: /* VLD4. */
19711 int align
= inst
.operands
[1].imm
>> 8;
19712 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
19713 16, 64, 32, 64, 32, 128, -1);
19714 if (align_good
== FAIL
)
19716 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
19717 _("bad list length"));
19718 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
19719 inst
.instruction
|= 1 << 5;
19720 if (et
.size
== 32 && align
== 128)
19721 inst
.instruction
|= 0x3 << 6;
19723 inst
.instruction
|= neon_logbits (et
.size
) << 6;
19730 inst
.instruction
|= do_alignment
<< 4;
19733 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
19734 apart from bits [11:4]. */
19737 do_neon_ldx_stx (void)
19739 if (inst
.operands
[1].isreg
)
19740 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
19742 switch (NEON_LANE (inst
.operands
[0].imm
))
19744 case NEON_INTERLEAVE_LANES
:
19745 NEON_ENCODE (INTERLV
, inst
);
19746 do_neon_ld_st_interleave ();
19749 case NEON_ALL_LANES
:
19750 NEON_ENCODE (DUP
, inst
);
19751 if (inst
.instruction
== N_INV
)
19753 first_error ("only loads support such operands");
19760 NEON_ENCODE (LANE
, inst
);
19761 do_neon_ld_st_lane ();
19764 /* L bit comes from bit mask. */
19765 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19766 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19767 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
19769 if (inst
.operands
[1].postind
)
19771 int postreg
= inst
.operands
[1].imm
& 0xf;
19772 constraint (!inst
.operands
[1].immisreg
,
19773 _("post-index must be a register"));
19774 constraint (postreg
== 0xd || postreg
== 0xf,
19775 _("bad register for post-index"));
19776 inst
.instruction
|= postreg
;
19780 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
19781 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
19782 || inst
.relocs
[0].exp
.X_add_number
!= 0,
19785 if (inst
.operands
[1].writeback
)
19787 inst
.instruction
|= 0xd;
19790 inst
.instruction
|= 0xf;
19794 inst
.instruction
|= 0xf9000000;
19796 inst
.instruction
|= 0xf4000000;
19801 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
19803 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
19804 D register operands. */
19805 if (neon_shape_class
[rs
] == SC_DOUBLE
)
19806 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19809 NEON_ENCODE (FPV8
, inst
);
19811 if (rs
== NS_FFF
|| rs
== NS_HHH
)
19813 do_vfp_sp_dyadic ();
19815 /* ARMv8.2 fp16 instruction. */
19817 do_scalar_fp16_v82_encode ();
19820 do_vfp_dp_rd_rn_rm ();
19823 inst
.instruction
|= 0x100;
19825 inst
.instruction
|= 0xf0000000;
19831 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19833 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
19834 first_error (_("invalid instruction shape"));
19840 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19841 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19843 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
19846 if (check_simd_pred_availability (1, NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
19849 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
19853 do_vrint_1 (enum neon_cvt_mode mode
)
19855 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
19856 struct neon_type_el et
;
19861 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
19862 D register operands. */
19863 if (neon_shape_class
[rs
] == SC_DOUBLE
)
19864 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19867 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
19869 if (et
.type
!= NT_invtype
)
19871 /* VFP encodings. */
19872 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
19873 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
19874 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19876 NEON_ENCODE (FPV8
, inst
);
19877 if (rs
== NS_FF
|| rs
== NS_HH
)
19878 do_vfp_sp_monadic ();
19880 do_vfp_dp_rd_rm ();
19884 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
19885 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
19886 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
19887 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
19888 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
19889 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
19890 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
19894 inst
.instruction
|= (rs
== NS_DD
) << 8;
19895 do_vfp_cond_or_thumb ();
19897 /* ARMv8.2 fp16 vrint instruction. */
19899 do_scalar_fp16_v82_encode ();
19903 /* Neon encodings (or something broken...). */
19905 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
19907 if (et
.type
== NT_invtype
)
19910 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19911 NEON_ENCODE (FLOAT
, inst
);
19913 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
19916 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19917 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19918 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19919 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19920 inst
.instruction
|= neon_quad (rs
) << 6;
19921 /* Mask off the original size bits and reencode them. */
19922 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
19923 | neon_logbits (et
.size
) << 18);
19927 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
19928 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
19929 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
19930 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
19931 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
19932 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
19933 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
19938 inst
.instruction
|= 0xfc000000;
19940 inst
.instruction
|= 0xf0000000;
19947 do_vrint_1 (neon_cvt_mode_x
);
19953 do_vrint_1 (neon_cvt_mode_z
);
19959 do_vrint_1 (neon_cvt_mode_r
);
19965 do_vrint_1 (neon_cvt_mode_a
);
19971 do_vrint_1 (neon_cvt_mode_n
);
19977 do_vrint_1 (neon_cvt_mode_p
);
19983 do_vrint_1 (neon_cvt_mode_m
);
19987 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
19989 unsigned regno
= NEON_SCALAR_REG (opnd
);
19990 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
19992 if (elsize
== 16 && elno
< 2 && regno
< 16)
19993 return regno
| (elno
<< 4);
19994 else if (elsize
== 32 && elno
== 0)
19997 first_error (_("scalar out of range"));
20004 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
)
20005 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
20006 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
20007 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
20008 _("expression too complex"));
20009 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
20010 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
20011 _("immediate out of range"));
20014 if (check_simd_pred_availability (1, NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
20017 if (inst
.operands
[2].isscalar
)
20019 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
20020 first_error (_("invalid instruction shape"));
20021 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
20022 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
20023 N_KEY
| N_F16
| N_F32
).size
;
20024 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
20026 inst
.instruction
= 0xfe000800;
20027 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20028 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20029 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20030 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20031 inst
.instruction
|= LOW4 (m
);
20032 inst
.instruction
|= HI1 (m
) << 5;
20033 inst
.instruction
|= neon_quad (rs
) << 6;
20034 inst
.instruction
|= rot
<< 20;
20035 inst
.instruction
|= (size
== 32) << 23;
20039 enum neon_shape rs
;
20040 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
20041 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
20043 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
20045 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
20046 N_KEY
| N_F16
| N_F32
).size
;
20047 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
) && size
== 32
20048 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
20049 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
20050 as_tsktsk (BAD_MVE_SRCDEST
);
20052 neon_three_same (neon_quad (rs
), 0, -1);
20053 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
20054 inst
.instruction
|= 0xfc200800;
20055 inst
.instruction
|= rot
<< 23;
20056 inst
.instruction
|= (size
== 32) << 20;
20063 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20064 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
20065 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
20066 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
20067 _("expression too complex"));
20069 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
20070 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
20071 enum neon_shape rs
;
20072 struct neon_type_el et
;
20073 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20075 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
20076 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
);
20080 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
20081 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
| N_I8
20083 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
20084 as_tsktsk (_("Warning: 32-bit element size and same first and third "
20085 "operand makes instruction UNPREDICTABLE"));
20088 if (et
.type
== NT_invtype
)
20091 if (check_simd_pred_availability (et
.type
== NT_float
, NEON_CHECK_ARCH8
20095 if (et
.type
== NT_float
)
20097 neon_three_same (neon_quad (rs
), 0, -1);
20098 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
20099 inst
.instruction
|= 0xfc800800;
20100 inst
.instruction
|= (rot
== 270) << 24;
20101 inst
.instruction
|= (et
.size
== 32) << 20;
20105 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
20106 inst
.instruction
= 0xfe000f00;
20107 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20108 inst
.instruction
|= neon_logbits (et
.size
) << 20;
20109 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20110 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20111 inst
.instruction
|= (rot
== 270) << 12;
20112 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20113 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20114 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20119 /* Dot Product instructions encoding support. */
20122 do_neon_dotproduct (int unsigned_p
)
20124 enum neon_shape rs
;
20125 unsigned scalar_oprd2
= 0;
20128 if (inst
.cond
!= COND_ALWAYS
)
20129 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
20130 "is UNPREDICTABLE"));
20132 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
20135 /* Dot Product instructions are in three-same D/Q register format or the third
20136 operand can be a scalar index register. */
20137 if (inst
.operands
[2].isscalar
)
20139 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
20140 high8
= 0xfe000000;
20141 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
20145 high8
= 0xfc000000;
20146 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
20150 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
20152 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
20154 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
20155 Product instruction, so we pass 0 as the "ubit" parameter. And the
20156 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
20157 neon_three_same (neon_quad (rs
), 0, 32);
20159 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
20160 different NEON three-same encoding. */
20161 inst
.instruction
&= 0x00ffffff;
20162 inst
.instruction
|= high8
;
20163 /* Encode 'U' bit which indicates signedness. */
20164 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
20165 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
20166 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
20167 the instruction encoding. */
20168 if (inst
.operands
[2].isscalar
)
20170 inst
.instruction
&= 0xffffffd0;
20171 inst
.instruction
|= LOW4 (scalar_oprd2
);
20172 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
20176 /* Dot Product instructions for signed integer. */
20179 do_neon_dotproduct_s (void)
20181 return do_neon_dotproduct (0);
20184 /* Dot Product instructions for unsigned integer. */
20187 do_neon_dotproduct_u (void)
20189 return do_neon_dotproduct (1);
20192 /* Crypto v1 instructions. */
20194 do_crypto_2op_1 (unsigned elttype
, int op
)
20196 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20198 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
20204 NEON_ENCODE (INTEGER
, inst
);
20205 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20206 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20207 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20208 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20210 inst
.instruction
|= op
<< 6;
20213 inst
.instruction
|= 0xfc000000;
20215 inst
.instruction
|= 0xf0000000;
20219 do_crypto_3op_1 (int u
, int op
)
20221 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20223 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
20224 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
20229 NEON_ENCODE (INTEGER
, inst
);
20230 neon_three_same (1, u
, 8 << op
);
20236 do_crypto_2op_1 (N_8
, 0);
20242 do_crypto_2op_1 (N_8
, 1);
20248 do_crypto_2op_1 (N_8
, 2);
20254 do_crypto_2op_1 (N_8
, 3);
20260 do_crypto_3op_1 (0, 0);
20266 do_crypto_3op_1 (0, 1);
20272 do_crypto_3op_1 (0, 2);
20278 do_crypto_3op_1 (0, 3);
20284 do_crypto_3op_1 (1, 0);
20290 do_crypto_3op_1 (1, 1);
20294 do_sha256su1 (void)
20296 do_crypto_3op_1 (1, 2);
20302 do_crypto_2op_1 (N_32
, -1);
20308 do_crypto_2op_1 (N_32
, 0);
20312 do_sha256su0 (void)
20314 do_crypto_2op_1 (N_32
, 1);
20318 do_crc32_1 (unsigned int poly
, unsigned int sz
)
20320 unsigned int Rd
= inst
.operands
[0].reg
;
20321 unsigned int Rn
= inst
.operands
[1].reg
;
20322 unsigned int Rm
= inst
.operands
[2].reg
;
20324 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20325 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
20326 inst
.instruction
|= LOW4 (Rn
) << 16;
20327 inst
.instruction
|= LOW4 (Rm
);
20328 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
20329 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
20331 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
20332 as_warn (UNPRED_REG ("r15"));
20374 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20376 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
20377 do_vfp_sp_dp_cvt ();
20378 do_vfp_cond_or_thumb ();
20382 /* Overall per-instruction processing. */
20384 /* We need to be able to fix up arbitrary expressions in some statements.
20385 This is so that we can handle symbols that are an arbitrary distance from
20386 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
20387 which returns part of an address in a form which will be valid for
20388 a data instruction. We do this by pushing the expression into a symbol
20389 in the expr_section, and creating a fix for that. */
20392 fix_new_arm (fragS
* frag
,
20406 /* Create an absolute valued symbol, so we have something to
20407 refer to in the object file. Unfortunately for us, gas's
20408 generic expression parsing will already have folded out
20409 any use of .set foo/.type foo %function that may have
20410 been used to set type information of the target location,
20411 that's being specified symbolically. We have to presume
20412 the user knows what they are doing. */
20416 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
20418 symbol
= symbol_find_or_make (name
);
20419 S_SET_SEGMENT (symbol
, absolute_section
);
20420 symbol_set_frag (symbol
, &zero_address_frag
);
20421 S_SET_VALUE (symbol
, exp
->X_add_number
);
20422 exp
->X_op
= O_symbol
;
20423 exp
->X_add_symbol
= symbol
;
20424 exp
->X_add_number
= 0;
20430 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
20431 (enum bfd_reloc_code_real
) reloc
);
20435 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
20436 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
20440 /* Mark whether the fix is to a THUMB instruction, or an ARM
20442 new_fix
->tc_fix_data
= thumb_mode
;
20445 /* Create a frg for an instruction requiring relaxation. */
20447 output_relax_insn (void)
20453 /* The size of the instruction is unknown, so tie the debug info to the
20454 start of the instruction. */
20455 dwarf2_emit_insn (0);
20457 switch (inst
.relocs
[0].exp
.X_op
)
20460 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
20461 offset
= inst
.relocs
[0].exp
.X_add_number
;
20465 offset
= inst
.relocs
[0].exp
.X_add_number
;
20468 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
20472 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
20473 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
20474 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
20477 /* Write a 32-bit thumb instruction to buf. */
20479 put_thumb32_insn (char * buf
, unsigned long insn
)
20481 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
20482 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
20486 output_inst (const char * str
)
20492 as_bad ("%s -- `%s'", inst
.error
, str
);
20497 output_relax_insn ();
20500 if (inst
.size
== 0)
20503 to
= frag_more (inst
.size
);
20504 /* PR 9814: Record the thumb mode into the current frag so that we know
20505 what type of NOP padding to use, if necessary. We override any previous
20506 setting so that if the mode has changed then the NOPS that we use will
20507 match the encoding of the last instruction in the frag. */
20508 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
20510 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
20512 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
20513 put_thumb32_insn (to
, inst
.instruction
);
20515 else if (inst
.size
> INSN_SIZE
)
20517 gas_assert (inst
.size
== (2 * INSN_SIZE
));
20518 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
20519 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
20522 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
20525 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
20527 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
20528 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
20529 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
20530 inst
.relocs
[r
].type
);
20533 dwarf2_emit_insn (inst
.size
);
20537 output_it_inst (int cond
, int mask
, char * to
)
20539 unsigned long instruction
= 0xbf00;
20542 instruction
|= mask
;
20543 instruction
|= cond
<< 4;
20547 to
= frag_more (2);
20549 dwarf2_emit_insn (2);
20553 md_number_to_chars (to
, instruction
, 2);
20558 /* Tag values used in struct asm_opcode's tag field. */
20561 OT_unconditional
, /* Instruction cannot be conditionalized.
20562 The ARM condition field is still 0xE. */
20563 OT_unconditionalF
, /* Instruction cannot be conditionalized
20564 and carries 0xF in its ARM condition field. */
20565 OT_csuffix
, /* Instruction takes a conditional suffix. */
20566 OT_csuffixF
, /* Some forms of the instruction take a scalar
20567 conditional suffix, others place 0xF where the
20568 condition field would be, others take a vector
20569 conditional suffix. */
20570 OT_cinfix3
, /* Instruction takes a conditional infix,
20571 beginning at character index 3. (In
20572 unified mode, it becomes a suffix.) */
20573 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
20574 tsts, cmps, cmns, and teqs. */
20575 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
20576 character index 3, even in unified mode. Used for
20577 legacy instructions where suffix and infix forms
20578 may be ambiguous. */
20579 OT_csuf_or_in3
, /* Instruction takes either a conditional
20580 suffix or an infix at character index 3. */
20581 OT_odd_infix_unc
, /* This is the unconditional variant of an
20582 instruction that takes a conditional infix
20583 at an unusual position. In unified mode,
20584 this variant will accept a suffix. */
20585 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
20586 are the conditional variants of instructions that
20587 take conditional infixes in unusual positions.
20588 The infix appears at character index
20589 (tag - OT_odd_infix_0). These are not accepted
20590 in unified mode. */
20593 /* Subroutine of md_assemble, responsible for looking up the primary
20594 opcode from the mnemonic the user wrote. STR points to the
20595 beginning of the mnemonic.
20597 This is not simply a hash table lookup, because of conditional
20598 variants. Most instructions have conditional variants, which are
20599 expressed with a _conditional affix_ to the mnemonic. If we were
20600 to encode each conditional variant as a literal string in the opcode
20601 table, it would have approximately 20,000 entries.
20603 Most mnemonics take this affix as a suffix, and in unified syntax,
20604 'most' is upgraded to 'all'. However, in the divided syntax, some
20605 instructions take the affix as an infix, notably the s-variants of
20606 the arithmetic instructions. Of those instructions, all but six
20607 have the infix appear after the third character of the mnemonic.
20609 Accordingly, the algorithm for looking up primary opcodes given
20612 1. Look up the identifier in the opcode table.
20613 If we find a match, go to step U.
20615 2. Look up the last two characters of the identifier in the
20616 conditions table. If we find a match, look up the first N-2
20617 characters of the identifier in the opcode table. If we
20618 find a match, go to step CE.
20620 3. Look up the fourth and fifth characters of the identifier in
20621 the conditions table. If we find a match, extract those
20622 characters from the identifier, and look up the remaining
20623 characters in the opcode table. If we find a match, go
20628 U. Examine the tag field of the opcode structure, in case this is
20629 one of the six instructions with its conditional infix in an
20630 unusual place. If it is, the tag tells us where to find the
20631 infix; look it up in the conditions table and set inst.cond
20632 accordingly. Otherwise, this is an unconditional instruction.
20633 Again set inst.cond accordingly. Return the opcode structure.
20635 CE. Examine the tag field to make sure this is an instruction that
20636 should receive a conditional suffix. If it is not, fail.
20637 Otherwise, set inst.cond from the suffix we already looked up,
20638 and return the opcode structure.
20640 CM. Examine the tag field to make sure this is an instruction that
20641 should receive a conditional infix after the third character.
20642 If it is not, fail. Otherwise, undo the edits to the current
20643 line of input and proceed as for case CE. */
20645 static const struct asm_opcode
*
20646 opcode_lookup (char **str
)
20650 const struct asm_opcode
*opcode
;
20651 const struct asm_cond
*cond
;
20654 /* Scan up to the end of the mnemonic, which must end in white space,
20655 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
20656 for (base
= end
= *str
; *end
!= '\0'; end
++)
20657 if (*end
== ' ' || *end
== '.')
20663 /* Handle a possible width suffix and/or Neon type suffix. */
20668 /* The .w and .n suffixes are only valid if the unified syntax is in
20670 if (unified_syntax
&& end
[1] == 'w')
20672 else if (unified_syntax
&& end
[1] == 'n')
20677 inst
.vectype
.elems
= 0;
20679 *str
= end
+ offset
;
20681 if (end
[offset
] == '.')
20683 /* See if we have a Neon type suffix (possible in either unified or
20684 non-unified ARM syntax mode). */
20685 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
20688 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
20694 /* Look for unaffixed or special-case affixed mnemonic. */
20695 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
20700 if (opcode
->tag
< OT_odd_infix_0
)
20702 inst
.cond
= COND_ALWAYS
;
20706 if (warn_on_deprecated
&& unified_syntax
)
20707 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
20708 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
20709 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
20712 inst
.cond
= cond
->value
;
20715 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20717 /* Cannot have a conditional suffix on a mnemonic of less than a character.
20719 if (end
- base
< 2)
20722 cond
= (const struct asm_cond
*) hash_find_n (arm_vcond_hsh
, affix
, 1);
20723 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
20725 /* If this opcode can not be vector predicated then don't accept it with a
20726 vector predication code. */
20727 if (opcode
&& !opcode
->mayBeVecPred
)
20730 if (!opcode
|| !cond
)
20732 /* Cannot have a conditional suffix on a mnemonic of less than two
20734 if (end
- base
< 3)
20737 /* Look for suffixed mnemonic. */
20739 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
20740 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
20744 if (opcode
&& cond
)
20747 switch (opcode
->tag
)
20749 case OT_cinfix3_legacy
:
20750 /* Ignore conditional suffixes matched on infix only mnemonics. */
20754 case OT_cinfix3_deprecated
:
20755 case OT_odd_infix_unc
:
20756 if (!unified_syntax
)
20758 /* Fall through. */
20762 case OT_csuf_or_in3
:
20763 inst
.cond
= cond
->value
;
20766 case OT_unconditional
:
20767 case OT_unconditionalF
:
20769 inst
.cond
= cond
->value
;
20772 /* Delayed diagnostic. */
20773 inst
.error
= BAD_COND
;
20774 inst
.cond
= COND_ALWAYS
;
20783 /* Cannot have a usual-position infix on a mnemonic of less than
20784 six characters (five would be a suffix). */
20785 if (end
- base
< 6)
20788 /* Look for infixed mnemonic in the usual position. */
20790 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
20794 memcpy (save
, affix
, 2);
20795 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
20796 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
20798 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
20799 memcpy (affix
, save
, 2);
20802 && (opcode
->tag
== OT_cinfix3
20803 || opcode
->tag
== OT_cinfix3_deprecated
20804 || opcode
->tag
== OT_csuf_or_in3
20805 || opcode
->tag
== OT_cinfix3_legacy
))
20808 if (warn_on_deprecated
&& unified_syntax
20809 && (opcode
->tag
== OT_cinfix3
20810 || opcode
->tag
== OT_cinfix3_deprecated
))
20811 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
20813 inst
.cond
= cond
->value
;
20820 /* This function generates an initial IT instruction, leaving its block
20821 virtually open for the new instructions. Eventually,
20822 the mask will be updated by now_pred_add_mask () each time
20823 a new instruction needs to be included in the IT block.
20824 Finally, the block is closed with close_automatic_it_block ().
20825 The block closure can be requested either from md_assemble (),
20826 a tencode (), or due to a label hook. */
20829 new_automatic_it_block (int cond
)
20831 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
20832 now_pred
.mask
= 0x18;
20833 now_pred
.cc
= cond
;
20834 now_pred
.block_length
= 1;
20835 mapping_state (MAP_THUMB
);
20836 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
20837 now_pred
.warn_deprecated
= FALSE
;
20838 now_pred
.insn_cond
= TRUE
;
20841 /* Close an automatic IT block.
20842 See comments in new_automatic_it_block (). */
20845 close_automatic_it_block (void)
20847 now_pred
.mask
= 0x10;
20848 now_pred
.block_length
= 0;
20851 /* Update the mask of the current automatically-generated IT
20852 instruction. See comments in new_automatic_it_block (). */
20855 now_pred_add_mask (int cond
)
20857 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
20858 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
20859 | ((bitvalue) << (nbit)))
20860 const int resulting_bit
= (cond
& 1);
20862 now_pred
.mask
&= 0xf;
20863 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
20865 (5 - now_pred
.block_length
));
20866 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
20868 ((5 - now_pred
.block_length
) - 1));
20869 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
20872 #undef SET_BIT_VALUE
20875 /* The IT blocks handling machinery is accessed through the these functions:
20876 it_fsm_pre_encode () from md_assemble ()
20877 set_pred_insn_type () optional, from the tencode functions
20878 set_pred_insn_type_last () ditto
20879 in_pred_block () ditto
20880 it_fsm_post_encode () from md_assemble ()
20881 force_automatic_it_block_close () from label handling functions
20884 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
20885 initializing the IT insn type with a generic initial value depending
20886 on the inst.condition.
20887 2) During the tencode function, two things may happen:
20888 a) The tencode function overrides the IT insn type by
20889 calling either set_pred_insn_type (type) or
20890 set_pred_insn_type_last ().
20891 b) The tencode function queries the IT block state by
20892 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
20894 Both set_pred_insn_type and in_pred_block run the internal FSM state
20895 handling function (handle_pred_state), because: a) setting the IT insn
20896 type may incur in an invalid state (exiting the function),
20897 and b) querying the state requires the FSM to be updated.
20898 Specifically we want to avoid creating an IT block for conditional
20899 branches, so it_fsm_pre_encode is actually a guess and we can't
20900 determine whether an IT block is required until the tencode () routine
20901 has decided what type of instruction this actually it.
20902 Because of this, if set_pred_insn_type and in_pred_block have to be
20903 used, set_pred_insn_type has to be called first.
20905 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
20906 that determines the insn IT type depending on the inst.cond code.
20907 When a tencode () routine encodes an instruction that can be
20908 either outside an IT block, or, in the case of being inside, has to be
20909 the last one, set_pred_insn_type_last () will determine the proper
20910 IT instruction type based on the inst.cond code. Otherwise,
20911 set_pred_insn_type can be called for overriding that logic or
20912 for covering other cases.
20914 Calling handle_pred_state () may not transition the IT block state to
20915 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
20916 still queried. Instead, if the FSM determines that the state should
20917 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
20918 after the tencode () function: that's what it_fsm_post_encode () does.
20920 Since in_pred_block () calls the state handling function to get an
20921 updated state, an error may occur (due to invalid insns combination).
20922 In that case, inst.error is set.
20923 Therefore, inst.error has to be checked after the execution of
20924 the tencode () routine.
20926 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
20927 any pending state change (if any) that didn't take place in
20928 handle_pred_state () as explained above. */
20931 it_fsm_pre_encode (void)
20933 if (inst
.cond
!= COND_ALWAYS
)
20934 inst
.pred_insn_type
= INSIDE_IT_INSN
;
20936 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
20938 now_pred
.state_handled
= 0;
20941 /* IT state FSM handling function. */
20942 /* MVE instructions and non-MVE instructions are handled differently because of
20943 the introduction of VPT blocks.
20944 Specifications say that any non-MVE instruction inside a VPT block is
20945 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
20946 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
20947 few exceptions we have MVE_UNPREDICABLE_INSN.
20948 The error messages provided depending on the different combinations possible
20949 are described in the cases below:
20950 For 'most' MVE instructions:
20951 1) In an IT block, with an IT code: syntax error
20952 2) In an IT block, with a VPT code: error: must be in a VPT block
20953 3) In an IT block, with no code: warning: UNPREDICTABLE
20954 4) In a VPT block, with an IT code: syntax error
20955 5) In a VPT block, with a VPT code: OK!
20956 6) In a VPT block, with no code: error: missing code
20957 7) Outside a pred block, with an IT code: error: syntax error
20958 8) Outside a pred block, with a VPT code: error: should be in a VPT block
20959 9) Outside a pred block, with no code: OK!
20960 For non-MVE instructions:
20961 10) In an IT block, with an IT code: OK!
20962 11) In an IT block, with a VPT code: syntax error
20963 12) In an IT block, with no code: error: missing code
20964 13) In a VPT block, with an IT code: error: should be in an IT block
20965 14) In a VPT block, with a VPT code: syntax error
20966 15) In a VPT block, with no code: UNPREDICTABLE
20967 16) Outside a pred block, with an IT code: error: should be in an IT block
20968 17) Outside a pred block, with a VPT code: syntax error
20969 18) Outside a pred block, with no code: OK!
20974 handle_pred_state (void)
20976 now_pred
.state_handled
= 1;
20977 now_pred
.insn_cond
= FALSE
;
20979 switch (now_pred
.state
)
20981 case OUTSIDE_PRED_BLOCK
:
20982 switch (inst
.pred_insn_type
)
20984 case MVE_UNPREDICABLE_INSN
:
20985 case MVE_OUTSIDE_PRED_INSN
:
20986 if (inst
.cond
< COND_ALWAYS
)
20988 /* Case 7: Outside a pred block, with an IT code: error: syntax
20990 inst
.error
= BAD_SYNTAX
;
20993 /* Case 9: Outside a pred block, with no code: OK! */
20995 case OUTSIDE_PRED_INSN
:
20996 if (inst
.cond
> COND_ALWAYS
)
20998 /* Case 17: Outside a pred block, with a VPT code: syntax error.
21000 inst
.error
= BAD_SYNTAX
;
21003 /* Case 18: Outside a pred block, with no code: OK! */
21006 case INSIDE_VPT_INSN
:
21007 /* Case 8: Outside a pred block, with a VPT code: error: should be in
21009 inst
.error
= BAD_OUT_VPT
;
21012 case INSIDE_IT_INSN
:
21013 case INSIDE_IT_LAST_INSN
:
21014 if (inst
.cond
< COND_ALWAYS
)
21016 /* Case 16: Outside a pred block, with an IT code: error: should
21017 be in an IT block. */
21018 if (thumb_mode
== 0)
21021 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
21022 as_tsktsk (_("Warning: conditional outside an IT block"\
21027 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
21028 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
21030 /* Automatically generate the IT instruction. */
21031 new_automatic_it_block (inst
.cond
);
21032 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
21033 close_automatic_it_block ();
21037 inst
.error
= BAD_OUT_IT
;
21043 else if (inst
.cond
> COND_ALWAYS
)
21045 /* Case 17: Outside a pred block, with a VPT code: syntax error.
21047 inst
.error
= BAD_SYNTAX
;
21052 case IF_INSIDE_IT_LAST_INSN
:
21053 case NEUTRAL_IT_INSN
:
21057 if (inst
.cond
!= COND_ALWAYS
)
21058 first_error (BAD_SYNTAX
);
21059 now_pred
.state
= MANUAL_PRED_BLOCK
;
21060 now_pred
.block_length
= 0;
21061 now_pred
.type
= VECTOR_PRED
;
21065 now_pred
.state
= MANUAL_PRED_BLOCK
;
21066 now_pred
.block_length
= 0;
21067 now_pred
.type
= SCALAR_PRED
;
21072 case AUTOMATIC_PRED_BLOCK
:
21073 /* Three things may happen now:
21074 a) We should increment current it block size;
21075 b) We should close current it block (closing insn or 4 insns);
21076 c) We should close current it block and start a new one (due
21077 to incompatible conditions or
21078 4 insns-length block reached). */
21080 switch (inst
.pred_insn_type
)
21082 case INSIDE_VPT_INSN
:
21084 case MVE_UNPREDICABLE_INSN
:
21085 case MVE_OUTSIDE_PRED_INSN
:
21087 case OUTSIDE_PRED_INSN
:
21088 /* The closure of the block shall happen immediately,
21089 so any in_pred_block () call reports the block as closed. */
21090 force_automatic_it_block_close ();
21093 case INSIDE_IT_INSN
:
21094 case INSIDE_IT_LAST_INSN
:
21095 case IF_INSIDE_IT_LAST_INSN
:
21096 now_pred
.block_length
++;
21098 if (now_pred
.block_length
> 4
21099 || !now_pred_compatible (inst
.cond
))
21101 force_automatic_it_block_close ();
21102 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
21103 new_automatic_it_block (inst
.cond
);
21107 now_pred
.insn_cond
= TRUE
;
21108 now_pred_add_mask (inst
.cond
);
21111 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
21112 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
21113 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
21114 close_automatic_it_block ();
21117 case NEUTRAL_IT_INSN
:
21118 now_pred
.block_length
++;
21119 now_pred
.insn_cond
= TRUE
;
21121 if (now_pred
.block_length
> 4)
21122 force_automatic_it_block_close ();
21124 now_pred_add_mask (now_pred
.cc
& 1);
21128 close_automatic_it_block ();
21129 now_pred
.state
= MANUAL_PRED_BLOCK
;
21134 case MANUAL_PRED_BLOCK
:
21137 if (now_pred
.type
== SCALAR_PRED
)
21139 /* Check conditional suffixes. */
21140 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
21141 now_pred
.mask
<<= 1;
21142 now_pred
.mask
&= 0x1f;
21143 is_last
= (now_pred
.mask
== 0x10);
21147 now_pred
.cc
^= (now_pred
.mask
>> 4);
21148 cond
= now_pred
.cc
+ 0xf;
21149 now_pred
.mask
<<= 1;
21150 now_pred
.mask
&= 0x1f;
21151 is_last
= now_pred
.mask
== 0x10;
21153 now_pred
.insn_cond
= TRUE
;
21155 switch (inst
.pred_insn_type
)
21157 case OUTSIDE_PRED_INSN
:
21158 if (now_pred
.type
== SCALAR_PRED
)
21160 if (inst
.cond
== COND_ALWAYS
)
21162 /* Case 12: In an IT block, with no code: error: missing
21164 inst
.error
= BAD_NOT_IT
;
21167 else if (inst
.cond
> COND_ALWAYS
)
21169 /* Case 11: In an IT block, with a VPT code: syntax error.
21171 inst
.error
= BAD_SYNTAX
;
21174 else if (thumb_mode
)
21176 /* This is for some special cases where a non-MVE
21177 instruction is not allowed in an IT block, such as cbz,
21178 but are put into one with a condition code.
21179 You could argue this should be a syntax error, but we
21180 gave the 'not allowed in IT block' diagnostic in the
21181 past so we will keep doing so. */
21182 inst
.error
= BAD_NOT_IT
;
21189 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
21190 as_tsktsk (MVE_NOT_VPT
);
21193 case MVE_OUTSIDE_PRED_INSN
:
21194 if (now_pred
.type
== SCALAR_PRED
)
21196 if (inst
.cond
== COND_ALWAYS
)
21198 /* Case 3: In an IT block, with no code: warning:
21200 as_tsktsk (MVE_NOT_IT
);
21203 else if (inst
.cond
< COND_ALWAYS
)
21205 /* Case 1: In an IT block, with an IT code: syntax error.
21207 inst
.error
= BAD_SYNTAX
;
21215 if (inst
.cond
< COND_ALWAYS
)
21217 /* Case 4: In a VPT block, with an IT code: syntax error.
21219 inst
.error
= BAD_SYNTAX
;
21222 else if (inst
.cond
== COND_ALWAYS
)
21224 /* Case 6: In a VPT block, with no code: error: missing
21226 inst
.error
= BAD_NOT_VPT
;
21234 case MVE_UNPREDICABLE_INSN
:
21235 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
21237 case INSIDE_IT_INSN
:
21238 if (inst
.cond
> COND_ALWAYS
)
21240 /* Case 11: In an IT block, with a VPT code: syntax error. */
21241 /* Case 14: In a VPT block, with a VPT code: syntax error. */
21242 inst
.error
= BAD_SYNTAX
;
21245 else if (now_pred
.type
== SCALAR_PRED
)
21247 /* Case 10: In an IT block, with an IT code: OK! */
21248 if (cond
!= inst
.cond
)
21250 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
21257 /* Case 13: In a VPT block, with an IT code: error: should be
21259 inst
.error
= BAD_OUT_IT
;
21264 case INSIDE_VPT_INSN
:
21265 if (now_pred
.type
== SCALAR_PRED
)
21267 /* Case 2: In an IT block, with a VPT code: error: must be in a
21269 inst
.error
= BAD_OUT_VPT
;
21272 /* Case 5: In a VPT block, with a VPT code: OK! */
21273 else if (cond
!= inst
.cond
)
21275 inst
.error
= BAD_VPT_COND
;
21279 case INSIDE_IT_LAST_INSN
:
21280 case IF_INSIDE_IT_LAST_INSN
:
21281 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
21283 /* Case 4: In a VPT block, with an IT code: syntax error. */
21284 /* Case 11: In an IT block, with a VPT code: syntax error. */
21285 inst
.error
= BAD_SYNTAX
;
21288 else if (cond
!= inst
.cond
)
21290 inst
.error
= BAD_IT_COND
;
21295 inst
.error
= BAD_BRANCH
;
21300 case NEUTRAL_IT_INSN
:
21301 /* The BKPT instruction is unconditional even in a IT or VPT
21306 if (now_pred
.type
== SCALAR_PRED
)
21308 inst
.error
= BAD_IT_IT
;
21311 /* fall through. */
21313 if (inst
.cond
== COND_ALWAYS
)
21315 /* Executing a VPT/VPST instruction inside an IT block or a
21316 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
21318 if (now_pred
.type
== SCALAR_PRED
)
21319 as_tsktsk (MVE_NOT_IT
);
21321 as_tsktsk (MVE_NOT_VPT
);
21326 /* VPT/VPST do not accept condition codes. */
21327 inst
.error
= BAD_SYNTAX
;
21338 struct depr_insn_mask
21340 unsigned long pattern
;
21341 unsigned long mask
;
21342 const char* description
;
21345 /* List of 16-bit instruction patterns deprecated in an IT block in
21347 static const struct depr_insn_mask depr_it_insns
[] = {
21348 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
21349 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
21350 { 0xa000, 0xb800, N_("ADR") },
21351 { 0x4800, 0xf800, N_("Literal loads") },
21352 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
21353 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
21354 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
21355 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
21356 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
21361 it_fsm_post_encode (void)
21365 if (!now_pred
.state_handled
)
21366 handle_pred_state ();
21368 if (now_pred
.insn_cond
21369 && !now_pred
.warn_deprecated
21370 && warn_on_deprecated
21371 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
21372 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
21374 if (inst
.instruction
>= 0x10000)
21376 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
21377 "performance deprecated in ARMv8-A and ARMv8-R"));
21378 now_pred
.warn_deprecated
= TRUE
;
21382 const struct depr_insn_mask
*p
= depr_it_insns
;
21384 while (p
->mask
!= 0)
21386 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
21388 as_tsktsk (_("IT blocks containing 16-bit Thumb "
21389 "instructions of the following class are "
21390 "performance deprecated in ARMv8-A and "
21391 "ARMv8-R: %s"), p
->description
);
21392 now_pred
.warn_deprecated
= TRUE
;
21400 if (now_pred
.block_length
> 1)
21402 as_tsktsk (_("IT blocks containing more than one conditional "
21403 "instruction are performance deprecated in ARMv8-A and "
21405 now_pred
.warn_deprecated
= TRUE
;
21409 is_last
= (now_pred
.mask
== 0x10);
21412 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
21418 force_automatic_it_block_close (void)
21420 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
21422 close_automatic_it_block ();
21423 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
21429 in_pred_block (void)
21431 if (!now_pred
.state_handled
)
21432 handle_pred_state ();
21434 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
21437 /* Whether OPCODE only has T32 encoding. Since this function is only used by
21438 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
21439 here, hence the "known" in the function name. */
21442 known_t32_only_insn (const struct asm_opcode
*opcode
)
21444 /* Original Thumb-1 wide instruction. */
21445 if (opcode
->tencode
== do_t_blx
21446 || opcode
->tencode
== do_t_branch23
21447 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
21448 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
21451 /* Wide-only instruction added to ARMv8-M Baseline. */
21452 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
21453 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
21454 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
21455 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
21461 /* Whether wide instruction variant can be used if available for a valid OPCODE
21465 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
21467 if (known_t32_only_insn (opcode
))
21470 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
21471 of variant T3 of B.W is checked in do_t_branch. */
21472 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
21473 && opcode
->tencode
== do_t_branch
)
21476 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
21477 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
21478 && opcode
->tencode
== do_t_mov_cmp
21479 /* Make sure CMP instruction is not affected. */
21480 && opcode
->aencode
== do_mov
)
21483 /* Wide instruction variants of all instructions with narrow *and* wide
21484 variants become available with ARMv6t2. Other opcodes are either
21485 narrow-only or wide-only and are thus available if OPCODE is valid. */
21486 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
21489 /* OPCODE with narrow only instruction variant or wide variant not
21495 md_assemble (char *str
)
21498 const struct asm_opcode
* opcode
;
21500 /* Align the previous label if needed. */
21501 if (last_label_seen
!= NULL
)
21503 symbol_set_frag (last_label_seen
, frag_now
);
21504 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
21505 S_SET_SEGMENT (last_label_seen
, now_seg
);
21508 memset (&inst
, '\0', sizeof (inst
));
21510 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
21511 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
21513 opcode
= opcode_lookup (&p
);
21516 /* It wasn't an instruction, but it might be a register alias of
21517 the form alias .req reg, or a Neon .dn/.qn directive. */
21518 if (! create_register_alias (str
, p
)
21519 && ! create_neon_reg_alias (str
, p
))
21520 as_bad (_("bad instruction `%s'"), str
);
21525 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
21526 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
21528 /* The value which unconditional instructions should have in place of the
21529 condition field. */
21530 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
21534 arm_feature_set variant
;
21536 variant
= cpu_variant
;
21537 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
21538 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
21539 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
21540 /* Check that this instruction is supported for this CPU. */
21541 if (!opcode
->tvariant
21542 || (thumb_mode
== 1
21543 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
21545 if (opcode
->tencode
== do_t_swi
)
21546 as_bad (_("SVC is not permitted on this architecture"));
21548 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
21551 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
21552 && opcode
->tencode
!= do_t_branch
)
21554 as_bad (_("Thumb does not support conditional execution"));
21558 /* Two things are addressed here:
21559 1) Implicit require narrow instructions on Thumb-1.
21560 This avoids relaxation accidentally introducing Thumb-2
21562 2) Reject wide instructions in non Thumb-2 cores.
21564 Only instructions with narrow and wide variants need to be handled
21565 but selecting all non wide-only instructions is easier. */
21566 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
21567 && !t32_insn_ok (variant
, opcode
))
21569 if (inst
.size_req
== 0)
21571 else if (inst
.size_req
== 4)
21573 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
21574 as_bad (_("selected processor does not support 32bit wide "
21575 "variant of instruction `%s'"), str
);
21577 as_bad (_("selected processor does not support `%s' in "
21578 "Thumb-2 mode"), str
);
21583 inst
.instruction
= opcode
->tvalue
;
21585 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
21587 /* Prepare the pred_insn_type for those encodings that don't set
21589 it_fsm_pre_encode ();
21591 opcode
->tencode ();
21593 it_fsm_post_encode ();
21596 if (!(inst
.error
|| inst
.relax
))
21598 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
21599 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
21600 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
21602 as_bad (_("cannot honor width suffix -- `%s'"), str
);
21607 /* Something has gone badly wrong if we try to relax a fixed size
21609 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
21611 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
21612 *opcode
->tvariant
);
21613 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
21614 set those bits when Thumb-2 32-bit instructions are seen. The impact
21615 of relaxable instructions will be considered later after we finish all
21617 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
21618 variant
= arm_arch_none
;
21620 variant
= cpu_variant
;
21621 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
21622 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
21625 check_neon_suffixes
;
21629 mapping_state (MAP_THUMB
);
21632 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
21636 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
21637 is_bx
= (opcode
->aencode
== do_bx
);
21639 /* Check that this instruction is supported for this CPU. */
21640 if (!(is_bx
&& fix_v4bx
)
21641 && !(opcode
->avariant
&&
21642 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
21644 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
21649 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
21653 inst
.instruction
= opcode
->avalue
;
21654 if (opcode
->tag
== OT_unconditionalF
)
21655 inst
.instruction
|= 0xFU
<< 28;
21657 inst
.instruction
|= inst
.cond
<< 28;
21658 inst
.size
= INSN_SIZE
;
21659 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
21661 it_fsm_pre_encode ();
21662 opcode
->aencode ();
21663 it_fsm_post_encode ();
21665 /* Arm mode bx is marked as both v4T and v5 because it's still required
21666 on a hypothetical non-thumb v5 core. */
21668 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
21670 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
21671 *opcode
->avariant
);
21673 check_neon_suffixes
;
21677 mapping_state (MAP_ARM
);
21682 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
21690 check_pred_blocks_finished (void)
21695 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
21696 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
21697 == MANUAL_PRED_BLOCK
)
21699 if (now_pred
.type
== SCALAR_PRED
)
21700 as_warn (_("section '%s' finished with an open IT block."),
21703 as_warn (_("section '%s' finished with an open VPT/VPST block."),
21707 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
21709 if (now_pred
.type
== SCALAR_PRED
)
21710 as_warn (_("file finished with an open IT block."));
21712 as_warn (_("file finished with an open VPT/VPST block."));
21717 /* Various frobbings of labels and their addresses. */
21720 arm_start_line_hook (void)
21722 last_label_seen
= NULL
;
21726 arm_frob_label (symbolS
* sym
)
21728 last_label_seen
= sym
;
21730 ARM_SET_THUMB (sym
, thumb_mode
);
21732 #if defined OBJ_COFF || defined OBJ_ELF
21733 ARM_SET_INTERWORK (sym
, support_interwork
);
21736 force_automatic_it_block_close ();
21738 /* Note - do not allow local symbols (.Lxxx) to be labelled
21739 as Thumb functions. This is because these labels, whilst
21740 they exist inside Thumb code, are not the entry points for
21741 possible ARM->Thumb calls. Also, these labels can be used
21742 as part of a computed goto or switch statement. eg gcc
21743 can generate code that looks like this:
21745 ldr r2, [pc, .Laaa]
21755 The first instruction loads the address of the jump table.
21756 The second instruction converts a table index into a byte offset.
21757 The third instruction gets the jump address out of the table.
21758 The fourth instruction performs the jump.
21760 If the address stored at .Laaa is that of a symbol which has the
21761 Thumb_Func bit set, then the linker will arrange for this address
21762 to have the bottom bit set, which in turn would mean that the
21763 address computation performed by the third instruction would end
21764 up with the bottom bit set. Since the ARM is capable of unaligned
21765 word loads, the instruction would then load the incorrect address
21766 out of the jump table, and chaos would ensue. */
21767 if (label_is_thumb_function_name
21768 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
21769 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
21771 /* When the address of a Thumb function is taken the bottom
21772 bit of that address should be set. This will allow
21773 interworking between Arm and Thumb functions to work
21776 THUMB_SET_FUNC (sym
, 1);
21778 label_is_thumb_function_name
= FALSE
;
21781 dwarf2_emit_label (sym
);
21785 arm_data_in_code (void)
21787 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
21789 *input_line_pointer
= '/';
21790 input_line_pointer
+= 5;
21791 *input_line_pointer
= 0;
21799 arm_canonicalize_symbol_name (char * name
)
21803 if (thumb_mode
&& (len
= strlen (name
)) > 5
21804 && streq (name
+ len
- 5, "/data"))
21805 *(name
+ len
- 5) = 0;
21810 /* Table of all register names defined by default. The user can
21811 define additional names with .req. Note that all register names
21812 should appear in both upper and lowercase variants. Some registers
21813 also have mixed-case names. */
21815 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
21816 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
21817 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
21818 #define REGSET(p,t) \
21819 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
21820 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
21821 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
21822 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
21823 #define REGSETH(p,t) \
21824 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
21825 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
21826 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
21827 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
21828 #define REGSET2(p,t) \
21829 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
21830 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
21831 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
21832 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
21833 #define SPLRBANK(base,bank,t) \
21834 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
21835 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
21836 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
21837 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
21838 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
21839 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
21841 static const struct reg_entry reg_names
[] =
21843 /* ARM integer registers. */
21844 REGSET(r
, RN
), REGSET(R
, RN
),
21846 /* ATPCS synonyms. */
21847 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
21848 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
21849 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
21851 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
21852 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
21853 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
21855 /* Well-known aliases. */
21856 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
21857 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
21859 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
21860 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
21862 /* Defining the new Zero register from ARMv8.1-M. */
21866 /* Coprocessor numbers. */
21867 REGSET(p
, CP
), REGSET(P
, CP
),
21869 /* Coprocessor register numbers. The "cr" variants are for backward
21871 REGSET(c
, CN
), REGSET(C
, CN
),
21872 REGSET(cr
, CN
), REGSET(CR
, CN
),
21874 /* ARM banked registers. */
21875 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
21876 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
21877 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
21878 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
21879 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
21880 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
21881 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
21883 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
21884 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
21885 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
21886 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
21887 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
21888 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
21889 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
21890 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
21892 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
21893 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
21894 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
21895 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
21896 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
21897 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
21898 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
21899 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
21900 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
21902 /* FPA registers. */
21903 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
21904 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
21906 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
21907 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
21909 /* VFP SP registers. */
21910 REGSET(s
,VFS
), REGSET(S
,VFS
),
21911 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
21913 /* VFP DP Registers. */
21914 REGSET(d
,VFD
), REGSET(D
,VFD
),
21915 /* Extra Neon DP registers. */
21916 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
21918 /* Neon QP registers. */
21919 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
21921 /* VFP control registers. */
21922 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
21923 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
21924 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
21925 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
21926 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
21927 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
21928 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
21930 /* Maverick DSP coprocessor registers. */
21931 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
21932 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
21934 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
21935 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
21936 REGDEF(dspsc
,0,DSPSC
),
21938 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
21939 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
21940 REGDEF(DSPSC
,0,DSPSC
),
21942 /* iWMMXt data registers - p0, c0-15. */
21943 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
21945 /* iWMMXt control registers - p1, c0-3. */
21946 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
21947 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
21948 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
21949 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
21951 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
21952 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
21953 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
21954 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
21955 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
21957 /* XScale accumulator registers. */
21958 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
21964 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
21965 within psr_required_here. */
21966 static const struct asm_psr psrs
[] =
21968 /* Backward compatibility notation. Note that "all" is no longer
21969 truly all possible PSR bits. */
21970 {"all", PSR_c
| PSR_f
},
21974 /* Individual flags. */
21980 /* Combinations of flags. */
21981 {"fs", PSR_f
| PSR_s
},
21982 {"fx", PSR_f
| PSR_x
},
21983 {"fc", PSR_f
| PSR_c
},
21984 {"sf", PSR_s
| PSR_f
},
21985 {"sx", PSR_s
| PSR_x
},
21986 {"sc", PSR_s
| PSR_c
},
21987 {"xf", PSR_x
| PSR_f
},
21988 {"xs", PSR_x
| PSR_s
},
21989 {"xc", PSR_x
| PSR_c
},
21990 {"cf", PSR_c
| PSR_f
},
21991 {"cs", PSR_c
| PSR_s
},
21992 {"cx", PSR_c
| PSR_x
},
21993 {"fsx", PSR_f
| PSR_s
| PSR_x
},
21994 {"fsc", PSR_f
| PSR_s
| PSR_c
},
21995 {"fxs", PSR_f
| PSR_x
| PSR_s
},
21996 {"fxc", PSR_f
| PSR_x
| PSR_c
},
21997 {"fcs", PSR_f
| PSR_c
| PSR_s
},
21998 {"fcx", PSR_f
| PSR_c
| PSR_x
},
21999 {"sfx", PSR_s
| PSR_f
| PSR_x
},
22000 {"sfc", PSR_s
| PSR_f
| PSR_c
},
22001 {"sxf", PSR_s
| PSR_x
| PSR_f
},
22002 {"sxc", PSR_s
| PSR_x
| PSR_c
},
22003 {"scf", PSR_s
| PSR_c
| PSR_f
},
22004 {"scx", PSR_s
| PSR_c
| PSR_x
},
22005 {"xfs", PSR_x
| PSR_f
| PSR_s
},
22006 {"xfc", PSR_x
| PSR_f
| PSR_c
},
22007 {"xsf", PSR_x
| PSR_s
| PSR_f
},
22008 {"xsc", PSR_x
| PSR_s
| PSR_c
},
22009 {"xcf", PSR_x
| PSR_c
| PSR_f
},
22010 {"xcs", PSR_x
| PSR_c
| PSR_s
},
22011 {"cfs", PSR_c
| PSR_f
| PSR_s
},
22012 {"cfx", PSR_c
| PSR_f
| PSR_x
},
22013 {"csf", PSR_c
| PSR_s
| PSR_f
},
22014 {"csx", PSR_c
| PSR_s
| PSR_x
},
22015 {"cxf", PSR_c
| PSR_x
| PSR_f
},
22016 {"cxs", PSR_c
| PSR_x
| PSR_s
},
22017 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
22018 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
22019 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
22020 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
22021 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
22022 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
22023 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
22024 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
22025 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
22026 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
22027 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
22028 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
22029 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
22030 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
22031 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
22032 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
22033 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
22034 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
22035 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
22036 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
22037 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
22038 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
22039 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
22040 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
22043 /* Table of V7M psr names. */
22044 static const struct asm_psr v7m_psrs
[] =
22046 {"apsr", 0x0 }, {"APSR", 0x0 },
22047 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
22048 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
22049 {"psr", 0x3 }, {"PSR", 0x3 },
22050 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
22051 {"ipsr", 0x5 }, {"IPSR", 0x5 },
22052 {"epsr", 0x6 }, {"EPSR", 0x6 },
22053 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
22054 {"msp", 0x8 }, {"MSP", 0x8 },
22055 {"psp", 0x9 }, {"PSP", 0x9 },
22056 {"msplim", 0xa }, {"MSPLIM", 0xa },
22057 {"psplim", 0xb }, {"PSPLIM", 0xb },
22058 {"primask", 0x10}, {"PRIMASK", 0x10},
22059 {"basepri", 0x11}, {"BASEPRI", 0x11},
22060 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
22061 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
22062 {"control", 0x14}, {"CONTROL", 0x14},
22063 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
22064 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
22065 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
22066 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
22067 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
22068 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
22069 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
22070 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
22071 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
22074 /* Table of all shift-in-operand names. */
22075 static const struct asm_shift_name shift_names
[] =
22077 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
22078 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
22079 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
22080 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
22081 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
22082 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
22083 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
22086 /* Table of all explicit relocation names. */
22088 static struct reloc_entry reloc_names
[] =
22090 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
22091 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
22092 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
22093 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
22094 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
22095 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
22096 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
22097 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
22098 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
22099 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
22100 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
22101 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
22102 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
22103 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
22104 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
22105 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
22106 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
22107 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
22108 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
22109 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
22110 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
22111 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
22112 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
22113 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
22114 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
22115 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
22116 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
22120 /* Table of all conditional affixes. */
22121 static const struct asm_cond conds
[] =
22125 {"cs", 0x2}, {"hs", 0x2},
22126 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
22139 static const struct asm_cond vconds
[] =
22145 #define UL_BARRIER(L,U,CODE,FEAT) \
22146 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
22147 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
22149 static struct asm_barrier_opt barrier_opt_names
[] =
22151 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
22152 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
22153 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
22154 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
22155 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
22156 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
22157 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
22158 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
22159 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
22160 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
22161 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
22162 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
22163 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
22164 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
22165 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
22166 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
22171 /* Table of ARM-format instructions. */
22173 /* Macros for gluing together operand strings. N.B. In all cases
22174 other than OPS0, the trailing OP_stop comes from default
22175 zero-initialization of the unspecified elements of the array. */
22176 #define OPS0() { OP_stop, }
22177 #define OPS1(a) { OP_##a, }
22178 #define OPS2(a,b) { OP_##a,OP_##b, }
22179 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
22180 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
22181 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
22182 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
22184 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
22185 This is useful when mixing operands for ARM and THUMB, i.e. using the
22186 MIX_ARM_THUMB_OPERANDS macro.
22187 In order to use these macros, prefix the number of operands with _
22189 #define OPS_1(a) { a, }
22190 #define OPS_2(a,b) { a,b, }
22191 #define OPS_3(a,b,c) { a,b,c, }
22192 #define OPS_4(a,b,c,d) { a,b,c,d, }
22193 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
22194 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
22196 /* These macros abstract out the exact format of the mnemonic table and
22197 save some repeated characters. */
22199 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
22200 #define TxCE(mnem, op, top, nops, ops, ae, te) \
22201 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
22202 THUMB_VARIANT, do_##ae, do_##te, 0 }
22204 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
22205 a T_MNEM_xyz enumerator. */
22206 #define TCE(mnem, aop, top, nops, ops, ae, te) \
22207 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
22208 #define tCE(mnem, aop, top, nops, ops, ae, te) \
22209 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
22211 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
22212 infix after the third character. */
22213 #define TxC3(mnem, op, top, nops, ops, ae, te) \
22214 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
22215 THUMB_VARIANT, do_##ae, do_##te, 0 }
22216 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
22217 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
22218 THUMB_VARIANT, do_##ae, do_##te, 0 }
22219 #define TC3(mnem, aop, top, nops, ops, ae, te) \
22220 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
22221 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
22222 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
22223 #define tC3(mnem, aop, top, nops, ops, ae, te) \
22224 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
22225 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
22226 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
22228 /* Mnemonic that cannot be conditionalized. The ARM condition-code
22229 field is still 0xE. Many of the Thumb variants can be executed
22230 conditionally, so this is checked separately. */
22231 #define TUE(mnem, op, top, nops, ops, ae, te) \
22232 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
22233 THUMB_VARIANT, do_##ae, do_##te, 0 }
22235 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
22236 Used by mnemonics that have very minimal differences in the encoding for
22237 ARM and Thumb variants and can be handled in a common function. */
22238 #define TUEc(mnem, op, top, nops, ops, en) \
22239 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
22240 THUMB_VARIANT, do_##en, do_##en, 0 }
22242 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
22243 condition code field. */
22244 #define TUF(mnem, op, top, nops, ops, ae, te) \
22245 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
22246 THUMB_VARIANT, do_##ae, do_##te, 0 }
22248 /* ARM-only variants of all the above. */
22249 #define CE(mnem, op, nops, ops, ae) \
22250 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22252 #define C3(mnem, op, nops, ops, ae) \
22253 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22255 /* Thumb-only variants of TCE and TUE. */
22256 #define ToC(mnem, top, nops, ops, te) \
22257 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
22260 #define ToU(mnem, top, nops, ops, te) \
22261 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
22264 /* T_MNEM_xyz enumerator variants of ToC. */
22265 #define toC(mnem, top, nops, ops, te) \
22266 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
22269 /* T_MNEM_xyz enumerator variants of ToU. */
22270 #define toU(mnem, top, nops, ops, te) \
22271 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
22274 /* Legacy mnemonics that always have conditional infix after the third
22276 #define CL(mnem, op, nops, ops, ae) \
22277 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
22278 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22280 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
22281 #define cCE(mnem, op, nops, ops, ae) \
22282 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
22284 /* mov instructions that are shared between coprocessor and MVE. */
22285 #define mcCE(mnem, op, nops, ops, ae) \
22286 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
22288 /* Legacy coprocessor instructions where conditional infix and conditional
22289 suffix are ambiguous. For consistency this includes all FPA instructions,
22290 not just the potentially ambiguous ones. */
22291 #define cCL(mnem, op, nops, ops, ae) \
22292 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
22293 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
22295 /* Coprocessor, takes either a suffix or a position-3 infix
22296 (for an FPA corner case). */
22297 #define C3E(mnem, op, nops, ops, ae) \
22298 { mnem, OPS##nops ops, OT_csuf_or_in3, \
22299 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
22301 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
22302 { m1 #m2 m3, OPS##nops ops, \
22303 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
22304 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22306 #define CM(m1, m2, op, nops, ops, ae) \
22307 xCM_ (m1, , m2, op, nops, ops, ae), \
22308 xCM_ (m1, eq, m2, op, nops, ops, ae), \
22309 xCM_ (m1, ne, m2, op, nops, ops, ae), \
22310 xCM_ (m1, cs, m2, op, nops, ops, ae), \
22311 xCM_ (m1, hs, m2, op, nops, ops, ae), \
22312 xCM_ (m1, cc, m2, op, nops, ops, ae), \
22313 xCM_ (m1, ul, m2, op, nops, ops, ae), \
22314 xCM_ (m1, lo, m2, op, nops, ops, ae), \
22315 xCM_ (m1, mi, m2, op, nops, ops, ae), \
22316 xCM_ (m1, pl, m2, op, nops, ops, ae), \
22317 xCM_ (m1, vs, m2, op, nops, ops, ae), \
22318 xCM_ (m1, vc, m2, op, nops, ops, ae), \
22319 xCM_ (m1, hi, m2, op, nops, ops, ae), \
22320 xCM_ (m1, ls, m2, op, nops, ops, ae), \
22321 xCM_ (m1, ge, m2, op, nops, ops, ae), \
22322 xCM_ (m1, lt, m2, op, nops, ops, ae), \
22323 xCM_ (m1, gt, m2, op, nops, ops, ae), \
22324 xCM_ (m1, le, m2, op, nops, ops, ae), \
22325 xCM_ (m1, al, m2, op, nops, ops, ae)
22327 #define UE(mnem, op, nops, ops, ae) \
22328 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22330 #define UF(mnem, op, nops, ops, ae) \
22331 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22333 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
22334 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
22335 use the same encoding function for each. */
22336 #define NUF(mnem, op, nops, ops, enc) \
22337 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
22338 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
22340 /* Neon data processing, version which indirects through neon_enc_tab for
22341 the various overloaded versions of opcodes. */
22342 #define nUF(mnem, op, nops, ops, enc) \
22343 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
22344 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
22346 /* Neon insn with conditional suffix for the ARM version, non-overloaded
22348 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
22349 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
22350 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
22352 #define NCE(mnem, op, nops, ops, enc) \
22353 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
22355 #define NCEF(mnem, op, nops, ops, enc) \
22356 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
22358 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
22359 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
22360 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
22361 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
22363 #define nCE(mnem, op, nops, ops, enc) \
22364 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
22366 #define nCEF(mnem, op, nops, ops, enc) \
22367 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
22370 #define mCEF(mnem, op, nops, ops, enc) \
22371 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
22372 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
22375 /* nCEF but for MVE predicated instructions. */
22376 #define mnCEF(mnem, op, nops, ops, enc) \
22377 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
22379 /* nCE but for MVE predicated instructions. */
22380 #define mnCE(mnem, op, nops, ops, enc) \
22381 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
22383 /* NUF but for potentially MVE predicated instructions. */
22384 #define MNUF(mnem, op, nops, ops, enc) \
22385 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
22386 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
22388 /* nUF but for potentially MVE predicated instructions. */
22389 #define mnUF(mnem, op, nops, ops, enc) \
22390 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
22391 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
22393 /* ToC but for potentially MVE predicated instructions. */
22394 #define mToC(mnem, top, nops, ops, te) \
22395 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
22398 /* NCE but for MVE predicated instructions. */
22399 #define MNCE(mnem, op, nops, ops, enc) \
22400 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
22402 /* NCEF but for MVE predicated instructions. */
22403 #define MNCEF(mnem, op, nops, ops, enc) \
22404 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
22407 static const struct asm_opcode insns
[] =
22409 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
22410 #define THUMB_VARIANT & arm_ext_v4t
22411 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22412 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22413 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22414 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22415 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
22416 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
22417 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
22418 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
22419 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22420 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22421 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
22422 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
22423 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22424 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22425 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
22426 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
22428 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
22429 for setting PSR flag bits. They are obsolete in V6 and do not
22430 have Thumb equivalents. */
22431 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
22432 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
22433 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
22434 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
22435 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
22436 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
22437 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
22438 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
22439 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
22441 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
22442 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
22443 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
22444 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
22446 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
22447 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
22448 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
22450 OP_ADDRGLDR
),ldst
, t_ldst
),
22451 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
22453 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22454 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22455 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22456 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22457 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22458 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22460 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
22461 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
22464 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
22465 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
22466 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
22467 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
22469 /* Thumb-compatibility pseudo ops. */
22470 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22471 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22472 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22473 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22474 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22475 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22476 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22477 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22478 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
22479 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
22480 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
22481 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
22483 /* These may simplify to neg. */
22484 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
22485 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
22487 #undef THUMB_VARIANT
22488 #define THUMB_VARIANT & arm_ext_os
22490 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
22491 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
22493 #undef THUMB_VARIANT
22494 #define THUMB_VARIANT & arm_ext_v6
22496 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
22498 /* V1 instructions with no Thumb analogue prior to V6T2. */
22499 #undef THUMB_VARIANT
22500 #define THUMB_VARIANT & arm_ext_v6t2
22502 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
22503 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
22504 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
22506 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
22507 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
22508 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
22509 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
22511 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22512 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22514 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22515 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22517 /* V1 instructions with no Thumb analogue at all. */
22518 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
22519 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
22521 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
22522 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
22523 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
22524 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
22525 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
22526 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
22527 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
22528 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
22531 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
22532 #undef THUMB_VARIANT
22533 #define THUMB_VARIANT & arm_ext_v4t
22535 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
22536 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
22538 #undef THUMB_VARIANT
22539 #define THUMB_VARIANT & arm_ext_v6t2
22541 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
22542 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
22544 /* Generic coprocessor instructions. */
22545 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
22546 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22547 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22548 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22549 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22550 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
22551 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
22554 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
22556 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
22557 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
22560 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
22561 #undef THUMB_VARIANT
22562 #define THUMB_VARIANT & arm_ext_msr
22564 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
22565 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
22568 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
22569 #undef THUMB_VARIANT
22570 #define THUMB_VARIANT & arm_ext_v6t2
22572 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
22573 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
22574 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
22575 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
22576 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
22577 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
22578 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
22579 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
22582 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
22583 #undef THUMB_VARIANT
22584 #define THUMB_VARIANT & arm_ext_v4t
22586 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22587 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22588 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22589 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22590 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22591 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22594 #define ARM_VARIANT & arm_ext_v4t_5
22596 /* ARM Architecture 4T. */
22597 /* Note: bx (and blx) are required on V5, even if the processor does
22598 not support Thumb. */
22599 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
22602 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
22603 #undef THUMB_VARIANT
22604 #define THUMB_VARIANT & arm_ext_v5t
22606 /* Note: blx has 2 variants; the .value coded here is for
22607 BLX(2). Only this variant has conditional execution. */
22608 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
22609 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
22611 #undef THUMB_VARIANT
22612 #define THUMB_VARIANT & arm_ext_v6t2
22614 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
22615 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22616 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22617 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22618 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22619 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
22620 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
22621 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
22624 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
22625 #undef THUMB_VARIANT
22626 #define THUMB_VARIANT & arm_ext_v5exp
22628 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22629 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22630 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22631 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22633 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22634 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22636 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
22637 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
22638 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
22639 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
22641 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22642 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22643 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22644 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22646 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22647 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22649 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
22650 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
22651 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
22652 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
22655 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
22656 #undef THUMB_VARIANT
22657 #define THUMB_VARIANT & arm_ext_v6t2
22659 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
22660 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
22662 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
22663 ADDRGLDRS
), ldrd
, t_ldstd
),
22665 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
22666 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
22669 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
22671 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
22674 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
22675 #undef THUMB_VARIANT
22676 #define THUMB_VARIANT & arm_ext_v6
22678 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
22679 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
22680 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
22681 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
22682 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
22683 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22684 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22685 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22686 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22687 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
22689 #undef THUMB_VARIANT
22690 #define THUMB_VARIANT & arm_ext_v6t2_v8m
22692 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
22693 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
22695 #undef THUMB_VARIANT
22696 #define THUMB_VARIANT & arm_ext_v6t2
22698 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
22699 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
22701 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
22702 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
22704 /* ARM V6 not included in V7M. */
22705 #undef THUMB_VARIANT
22706 #define THUMB_VARIANT & arm_ext_v6_notm
22707 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
22708 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
22709 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
22710 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
22711 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
22712 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
22713 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
22714 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
22715 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
22716 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
22717 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
22718 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
22719 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
22720 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
22721 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
22722 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
22723 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
22724 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
22725 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
22727 /* ARM V6 not included in V7M (eg. integer SIMD). */
22728 #undef THUMB_VARIANT
22729 #define THUMB_VARIANT & arm_ext_v6_dsp
22730 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
22731 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
22732 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22733 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22734 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22735 /* Old name for QASX. */
22736 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22737 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22738 /* Old name for QSAX. */
22739 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22740 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22741 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22742 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22743 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22744 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22745 /* Old name for SASX. */
22746 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22747 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22748 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22749 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22750 /* Old name for SHASX. */
22751 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22752 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22753 /* Old name for SHSAX. */
22754 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22755 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22756 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22757 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22758 /* Old name for SSAX. */
22759 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22760 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22761 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22762 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22763 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22764 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22765 /* Old name for UASX. */
22766 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22767 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22768 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22769 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22770 /* Old name for UHASX. */
22771 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22772 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22773 /* Old name for UHSAX. */
22774 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22775 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22776 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22777 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22778 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22779 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22780 /* Old name for UQASX. */
22781 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22782 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22783 /* Old name for UQSAX. */
22784 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22785 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22786 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22787 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22788 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22789 /* Old name for USAX. */
22790 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22791 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22792 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22793 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22794 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22795 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22796 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22797 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22798 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22799 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22800 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22801 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22802 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22803 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
22804 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
22805 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22806 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22807 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
22808 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
22809 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22810 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22811 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22812 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22813 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22814 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22815 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22816 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22817 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22818 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22819 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
22820 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
22821 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22822 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22823 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
22826 #define ARM_VARIANT & arm_ext_v6k_v6t2
22827 #undef THUMB_VARIANT
22828 #define THUMB_VARIANT & arm_ext_v6k_v6t2
22830 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
22831 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
22832 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
22833 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
22835 #undef THUMB_VARIANT
22836 #define THUMB_VARIANT & arm_ext_v6_notm
22837 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
22839 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
22840 RRnpcb
), strexd
, t_strexd
),
22842 #undef THUMB_VARIANT
22843 #define THUMB_VARIANT & arm_ext_v6t2_v8m
22844 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
22846 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
22848 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
22850 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
22852 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
22855 #define ARM_VARIANT & arm_ext_sec
22856 #undef THUMB_VARIANT
22857 #define THUMB_VARIANT & arm_ext_sec
22859 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
22862 #define ARM_VARIANT & arm_ext_virt
22863 #undef THUMB_VARIANT
22864 #define THUMB_VARIANT & arm_ext_virt
22866 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
22867 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
22870 #define ARM_VARIANT & arm_ext_pan
22871 #undef THUMB_VARIANT
22872 #define THUMB_VARIANT & arm_ext_pan
22874 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
22877 #define ARM_VARIANT & arm_ext_v6t2
22878 #undef THUMB_VARIANT
22879 #define THUMB_VARIANT & arm_ext_v6t2
22881 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
22882 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
22883 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
22884 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
22886 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
22887 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
22889 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
22890 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
22891 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
22892 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
22895 #define ARM_VARIANT & arm_ext_v3
22896 #undef THUMB_VARIANT
22897 #define THUMB_VARIANT & arm_ext_v6t2
22899 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
22900 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
22901 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
22904 #define ARM_VARIANT & arm_ext_v6t2
22905 #undef THUMB_VARIANT
22906 #define THUMB_VARIANT & arm_ext_v6t2_v8m
22907 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
22908 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
22910 /* Thumb-only instructions. */
22912 #define ARM_VARIANT NULL
22913 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
22914 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
22916 /* ARM does not really have an IT instruction, so always allow it.
22917 The opcode is copied from Thumb in order to allow warnings in
22918 -mimplicit-it=[never | arm] modes. */
22920 #define ARM_VARIANT & arm_ext_v1
22921 #undef THUMB_VARIANT
22922 #define THUMB_VARIANT & arm_ext_v6t2
22924 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
22925 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
22926 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
22927 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
22928 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
22929 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
22930 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
22931 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
22932 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
22933 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
22934 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
22935 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
22936 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
22937 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
22938 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
22939 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
22940 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
22941 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
22943 /* Thumb2 only instructions. */
22945 #define ARM_VARIANT NULL
22947 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
22948 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
22949 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
22950 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
22951 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
22952 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
22954 /* Hardware division instructions. */
22956 #define ARM_VARIANT & arm_ext_adiv
22957 #undef THUMB_VARIANT
22958 #define THUMB_VARIANT & arm_ext_div
22960 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
22961 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
22963 /* ARM V6M/V7 instructions. */
22965 #define ARM_VARIANT & arm_ext_barrier
22966 #undef THUMB_VARIANT
22967 #define THUMB_VARIANT & arm_ext_barrier
22969 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
22970 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
22971 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
22973 /* ARM V7 instructions. */
22975 #define ARM_VARIANT & arm_ext_v7
22976 #undef THUMB_VARIANT
22977 #define THUMB_VARIANT & arm_ext_v7
22979 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
22980 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
22983 #define ARM_VARIANT & arm_ext_mp
22984 #undef THUMB_VARIANT
22985 #define THUMB_VARIANT & arm_ext_mp
22987 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
22989 /* AArchv8 instructions. */
22991 #define ARM_VARIANT & arm_ext_v8
22993 /* Instructions shared between armv8-a and armv8-m. */
22994 #undef THUMB_VARIANT
22995 #define THUMB_VARIANT & arm_ext_atomics
22997 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
22998 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
22999 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23000 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
23001 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
23002 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
23003 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23004 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
23005 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23006 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
23008 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
23010 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
23012 #undef THUMB_VARIANT
23013 #define THUMB_VARIANT & arm_ext_v8
23015 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
23016 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
23018 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
23021 /* Defined in V8 but is in undefined encoding space for earlier
23022 architectures. However earlier architectures are required to treat
23023 this instuction as a semihosting trap as well. Hence while not explicitly
23024 defined as such, it is in fact correct to define the instruction for all
23026 #undef THUMB_VARIANT
23027 #define THUMB_VARIANT & arm_ext_v1
23029 #define ARM_VARIANT & arm_ext_v1
23030 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
23032 /* ARMv8 T32 only. */
23034 #define ARM_VARIANT NULL
23035 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
23036 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
23037 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
23039 /* FP for ARMv8. */
23041 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
23042 #undef THUMB_VARIANT
23043 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
23045 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23046 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23047 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23048 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23049 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
23050 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
23051 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
23052 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
23053 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
23054 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
23055 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
23057 /* Crypto v1 extensions. */
23059 #define ARM_VARIANT & fpu_crypto_ext_armv8
23060 #undef THUMB_VARIANT
23061 #define THUMB_VARIANT & fpu_crypto_ext_armv8
23063 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
23064 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
23065 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
23066 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
23067 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
23068 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
23069 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
23070 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
23071 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
23072 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
23073 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
23074 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
23075 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
23076 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
23079 #define ARM_VARIANT & crc_ext_armv8
23080 #undef THUMB_VARIANT
23081 #define THUMB_VARIANT & crc_ext_armv8
23082 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
23083 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
23084 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
23085 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
23086 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
23087 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
23089 /* ARMv8.2 RAS extension. */
23091 #define ARM_VARIANT & arm_ext_ras
23092 #undef THUMB_VARIANT
23093 #define THUMB_VARIANT & arm_ext_ras
23094 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
23097 #define ARM_VARIANT & arm_ext_v8_3
23098 #undef THUMB_VARIANT
23099 #define THUMB_VARIANT & arm_ext_v8_3
23100 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
23103 #define ARM_VARIANT & fpu_neon_ext_dotprod
23104 #undef THUMB_VARIANT
23105 #define THUMB_VARIANT & fpu_neon_ext_dotprod
23106 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
23107 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
23110 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
23111 #undef THUMB_VARIANT
23112 #define THUMB_VARIANT NULL
23114 cCE("wfs", e200110
, 1, (RR
), rd
),
23115 cCE("rfs", e300110
, 1, (RR
), rd
),
23116 cCE("wfc", e400110
, 1, (RR
), rd
),
23117 cCE("rfc", e500110
, 1, (RR
), rd
),
23119 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23120 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23121 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23122 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23124 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23125 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23126 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23127 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23129 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
23130 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
23131 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
23132 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
23133 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
23134 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
23135 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
23136 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
23137 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
23138 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
23139 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
23140 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
23142 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
23143 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
23144 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
23145 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
23146 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
23147 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
23148 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
23149 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
23150 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
23151 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
23152 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
23153 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
23155 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
23156 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
23157 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
23158 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
23159 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
23160 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
23161 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
23162 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
23163 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
23164 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
23165 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
23166 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
23168 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
23169 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
23170 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
23171 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
23172 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
23173 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
23174 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
23175 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
23176 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
23177 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
23178 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
23179 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
23181 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
23182 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
23183 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
23184 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
23185 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
23186 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
23187 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
23188 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
23189 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
23190 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
23191 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
23192 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
23194 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
23195 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
23196 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
23197 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
23198 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
23199 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
23200 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
23201 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
23202 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
23203 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
23204 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
23205 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
23207 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
23208 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
23209 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
23210 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
23211 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
23212 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
23213 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
23214 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
23215 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
23216 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
23217 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
23218 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
23220 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
23221 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
23222 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
23223 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
23224 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
23225 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
23226 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
23227 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
23228 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
23229 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
23230 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
23231 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
23233 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
23234 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
23235 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
23236 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
23237 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
23238 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
23239 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
23240 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
23241 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
23242 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
23243 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
23244 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
23246 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
23247 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
23248 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
23249 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
23250 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
23251 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
23252 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
23253 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
23254 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
23255 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
23256 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
23257 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
23259 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
23260 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
23261 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
23262 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
23263 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
23264 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
23265 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
23266 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
23267 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
23268 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
23269 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
23270 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
23272 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
23273 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
23274 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
23275 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
23276 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
23277 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
23278 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
23279 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
23280 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
23281 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
23282 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
23283 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
23285 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
23286 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
23287 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
23288 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
23289 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
23290 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
23291 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
23292 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
23293 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
23294 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
23295 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
23296 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
23298 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
23299 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
23300 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
23301 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
23302 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
23303 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
23304 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
23305 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
23306 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
23307 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
23308 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
23309 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
23311 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
23312 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
23313 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
23314 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
23315 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
23316 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
23317 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
23318 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
23319 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
23320 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
23321 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
23322 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
23324 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
23325 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
23326 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
23327 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
23328 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
23329 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
23330 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
23331 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
23332 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
23333 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
23334 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
23335 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
23337 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23338 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23339 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23340 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23341 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23342 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23343 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23344 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23345 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23346 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23347 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23348 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23350 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23351 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23352 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23353 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23354 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23355 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23356 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23357 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23358 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23359 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23360 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23361 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23363 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23364 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23365 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23366 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23367 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23368 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23369 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23370 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23371 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23372 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23373 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23374 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23376 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23377 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23378 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23379 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23380 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23381 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23382 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23383 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23384 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23385 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23386 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23387 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23389 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23390 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23391 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23392 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23393 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23394 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23395 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23396 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23397 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23398 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23399 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23400 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23402 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23403 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23404 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23405 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23406 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23407 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23408 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23409 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23410 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23411 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23412 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23413 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23415 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23416 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23417 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23418 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23419 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23420 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23421 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23422 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23423 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23424 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23425 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23426 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23428 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23429 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23430 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23431 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23432 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23433 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23434 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23435 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23436 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23437 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23438 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23439 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23441 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23442 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23443 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23444 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23445 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23446 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23447 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23448 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23449 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23450 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23451 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23452 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23454 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23455 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23456 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23457 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23458 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23459 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23460 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23461 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23462 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23463 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23464 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23465 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23467 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23468 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23469 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23470 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23471 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23472 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23473 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23474 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23475 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23476 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23477 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23478 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23480 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23481 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23482 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23483 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23484 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23485 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23486 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23487 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23488 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23489 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23490 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23491 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23493 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23494 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23495 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23496 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23497 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23498 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23499 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23500 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23501 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23502 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23503 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23504 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23506 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
23507 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
23508 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
23509 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
23511 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
23512 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
23513 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
23514 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
23515 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
23516 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
23517 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
23518 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
23519 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
23520 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
23521 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
23522 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
23524 /* The implementation of the FIX instruction is broken on some
23525 assemblers, in that it accepts a precision specifier as well as a
23526 rounding specifier, despite the fact that this is meaningless.
23527 To be more compatible, we accept it as well, though of course it
23528 does not set any bits. */
23529 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
23530 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
23531 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
23532 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
23533 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
23534 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
23535 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
23536 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
23537 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
23538 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
23539 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
23540 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
23541 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
23543 /* Instructions that were new with the real FPA, call them V2. */
23545 #define ARM_VARIANT & fpu_fpa_ext_v2
23547 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23548 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23549 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23550 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23551 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23552 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23555 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
23557 /* Moves and type conversions. */
23558 cCE("fmstat", ef1fa10
, 0, (), noargs
),
23559 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
23560 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
23561 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23562 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23563 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23564 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23565 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23566 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23567 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
23568 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
23570 /* Memory operations. */
23571 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
23572 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
23573 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
23574 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
23575 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
23576 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
23577 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
23578 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
23579 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
23580 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
23581 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
23582 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
23583 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
23584 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
23585 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
23586 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
23587 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
23588 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
23590 /* Monadic operations. */
23591 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23592 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23593 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23595 /* Dyadic operations. */
23596 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23597 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23598 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23599 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23600 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23601 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23602 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23603 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23604 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23607 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23608 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
23609 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23610 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
23612 /* Double precision load/store are still present on single precision
23613 implementations. */
23614 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
23615 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
23616 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
23617 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
23618 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
23619 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
23620 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
23621 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
23622 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
23623 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
23626 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
23628 /* Moves and type conversions. */
23629 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
23630 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
23631 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
23632 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
23633 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
23634 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
23635 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
23636 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
23637 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
23638 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
23639 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
23640 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
23642 /* Monadic operations. */
23643 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
23644 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
23645 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
23647 /* Dyadic operations. */
23648 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23649 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23650 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23651 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23652 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23653 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23654 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23655 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23656 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23659 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
23660 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
23661 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
23662 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
23664 /* Instructions which may belong to either the Neon or VFP instruction sets.
23665 Individual encoder functions perform additional architecture checks. */
23667 #define ARM_VARIANT & fpu_vfp_ext_v1xd
23668 #undef THUMB_VARIANT
23669 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
23671 /* These mnemonics are unique to VFP. */
23672 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
23673 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
23674 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
23675 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
23676 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
23677 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
23678 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
23679 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
23681 /* Mnemonics shared by Neon and VFP. */
23682 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
23683 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
23684 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
23686 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23687 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23688 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23689 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23690 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23691 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23693 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
23694 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
23695 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
23696 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
23699 /* NOTE: All VMOV encoding is special-cased! */
23700 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
23702 #undef THUMB_VARIANT
23703 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
23704 by different feature bits. Since we are setting the Thumb guard, we can
23705 require Thumb-1 which makes it a nop guard and set the right feature bit in
23706 do_vldr_vstr (). */
23707 #define THUMB_VARIANT & arm_ext_v4t
23708 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
23709 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
23712 #define ARM_VARIANT & arm_ext_fp16
23713 #undef THUMB_VARIANT
23714 #define THUMB_VARIANT & arm_ext_fp16
23715 /* New instructions added from v8.2, allowing the extraction and insertion of
23716 the upper 16 bits of a 32-bit vector register. */
23717 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
23718 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
23720 /* New backported fma/fms instructions optional in v8.2. */
23721 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
23722 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
23724 #undef THUMB_VARIANT
23725 #define THUMB_VARIANT & fpu_neon_ext_v1
23727 #define ARM_VARIANT & fpu_neon_ext_v1
23729 /* Data processing with three registers of the same length. */
23730 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
23731 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
23732 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
23733 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
23734 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
23735 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
23736 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
23737 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
23738 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
23739 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
23740 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
23741 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
23742 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
23743 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
23744 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
23745 /* If not immediate, fall back to neon_dyadic_i64_su.
23746 shl_imm should accept I8 I16 I32 I64,
23747 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
23748 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
23749 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
23750 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
23751 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
23752 /* Logic ops, types optional & ignored. */
23753 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
23754 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
23755 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
23756 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
23757 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
23758 /* Bitfield ops, untyped. */
23759 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
23760 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
23761 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
23762 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
23763 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
23764 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
23765 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
23766 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
23767 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
23768 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
23769 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
23770 back to neon_dyadic_if_su. */
23771 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
23772 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
23773 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
23774 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
23775 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
23776 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
23777 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
23778 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
23779 /* Comparison. Type I8 I16 I32 F32. */
23780 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
23781 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
23782 /* As above, D registers only. */
23783 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
23784 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
23785 /* Int and float variants, signedness unimportant. */
23786 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
23787 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
23788 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
23789 /* Add/sub take types I8 I16 I32 I64 F32. */
23790 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
23791 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
23792 /* vtst takes sizes 8, 16, 32. */
23793 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
23794 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
23795 /* VMUL takes I8 I16 I32 F32 P8. */
23796 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
23797 /* VQD{R}MULH takes S16 S32. */
23798 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
23799 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
23800 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
23801 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
23802 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
23803 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
23804 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
23805 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
23806 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
23807 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
23808 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
23809 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
23810 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
23811 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
23812 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
23813 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
23814 /* ARM v8.1 extension. */
23815 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
23816 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
23817 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
23818 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
23820 /* Two address, int/float. Types S8 S16 S32 F32. */
23821 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
23822 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
23824 /* Data processing with two registers and a shift amount. */
23825 /* Right shifts, and variants with rounding.
23826 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
23827 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
23828 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
23829 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
23830 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
23831 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
23832 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
23833 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
23834 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
23835 /* Shift and insert. Sizes accepted 8 16 32 64. */
23836 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
23837 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
23838 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
23839 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
23840 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
23841 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
23842 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
23843 /* Right shift immediate, saturating & narrowing, with rounding variants.
23844 Types accepted S16 S32 S64 U16 U32 U64. */
23845 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
23846 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
23847 /* As above, unsigned. Types accepted S16 S32 S64. */
23848 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
23849 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
23850 /* Right shift narrowing. Types accepted I16 I32 I64. */
23851 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
23852 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
23853 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
23854 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
23855 /* CVT with optional immediate for fixed-point variant. */
23856 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
23858 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
23859 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
23861 /* Data processing, three registers of different lengths. */
23862 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
23863 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
23864 /* If not scalar, fall back to neon_dyadic_long.
23865 Vector types as above, scalar types S16 S32 U16 U32. */
23866 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
23867 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
23868 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
23869 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
23870 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
23871 /* Dyadic, narrowing insns. Types I16 I32 I64. */
23872 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
23873 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
23874 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
23875 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
23876 /* Saturating doubling multiplies. Types S16 S32. */
23877 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
23878 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
23879 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
23880 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
23881 S16 S32 U16 U32. */
23882 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
23884 /* Extract. Size 8. */
23885 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
23886 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
23888 /* Two registers, miscellaneous. */
23889 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
23890 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
23891 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
23892 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
23893 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
23894 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
23895 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
23896 /* Vector replicate. Sizes 8 16 32. */
23897 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
23898 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
23899 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
23900 /* VMOVN. Types I16 I32 I64. */
23901 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
23902 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
23903 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
23904 /* VQMOVUN. Types S16 S32 S64. */
23905 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
23906 /* VZIP / VUZP. Sizes 8 16 32. */
23907 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
23908 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
23909 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
23910 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
23911 /* VQABS / VQNEG. Types S8 S16 S32. */
23912 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
23913 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
23914 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
23915 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
23916 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
23917 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
23918 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
23919 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
23920 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
23921 /* Reciprocal estimates. Types U32 F16 F32. */
23922 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
23923 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
23924 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
23925 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
23926 /* VCLS. Types S8 S16 S32. */
23927 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
23928 /* VCLZ. Types I8 I16 I32. */
23929 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
23930 /* VCNT. Size 8. */
23931 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
23932 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
23933 /* Two address, untyped. */
23934 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
23935 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
23936 /* VTRN. Sizes 8 16 32. */
23937 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
23938 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
23940 /* Table lookup. Size 8. */
23941 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
23942 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
23944 #undef THUMB_VARIANT
23945 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
23947 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
23949 /* Neon element/structure load/store. */
23950 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23951 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23952 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23953 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23954 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23955 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23956 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23957 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23959 #undef THUMB_VARIANT
23960 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
23962 #define ARM_VARIANT & fpu_vfp_ext_v3xd
23963 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
23964 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
23965 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
23966 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
23967 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
23968 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
23969 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
23970 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
23971 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
23973 #undef THUMB_VARIANT
23974 #define THUMB_VARIANT & fpu_vfp_ext_v3
23976 #define ARM_VARIANT & fpu_vfp_ext_v3
23978 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
23979 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
23980 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
23981 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
23982 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
23983 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
23984 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
23985 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
23986 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
23989 #define ARM_VARIANT & fpu_vfp_ext_fma
23990 #undef THUMB_VARIANT
23991 #define THUMB_VARIANT & fpu_vfp_ext_fma
23992 /* Mnemonics shared by Neon, VFP and MVE. These are included in the
23993 VFP FMA variant; NEON and VFP FMA always includes the NEON
23994 FMA instructions. */
23995 mnCEF(vfma
, _vfma
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_fmac
),
23996 mnCEF(vfms
, _vfms
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), neon_fmac
),
23998 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
23999 the v form should always be used. */
24000 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24001 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24002 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24003 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24004 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24005 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24007 #undef THUMB_VARIANT
24009 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
24011 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24012 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24013 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24014 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24015 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24016 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24017 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
24018 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
24021 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
24023 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
24024 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
24025 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
24026 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
24027 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
24028 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
24029 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
24030 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
24031 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
24032 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24033 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24034 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24035 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24036 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24037 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24038 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
24039 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
24040 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
24041 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
24042 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
24043 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24044 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24045 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24046 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24047 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24048 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24049 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
24050 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
24051 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
24052 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
24053 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
24054 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
24055 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
24056 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
24057 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24058 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24059 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24060 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24061 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24062 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24063 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24064 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24065 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24066 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24067 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24068 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24069 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
24070 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24071 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24072 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24073 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24074 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24075 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24076 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24077 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24078 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24079 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24080 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24081 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24082 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24083 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24084 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24085 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24086 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24087 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24088 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24089 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24090 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24091 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
24092 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
24093 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24094 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24095 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24096 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24097 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24098 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24099 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24100 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24101 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24102 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24103 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24104 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24105 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24106 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24107 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24108 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24109 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24110 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24111 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
24112 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24113 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24114 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24115 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24116 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24117 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24118 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24119 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24120 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24121 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24122 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24123 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24124 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24125 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24126 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24127 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24128 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24129 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24130 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24131 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24132 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24133 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
24134 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24135 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24136 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24137 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24138 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24139 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24140 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24141 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24142 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24143 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24144 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24145 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24146 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24147 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24148 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24149 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24150 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24151 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24152 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24153 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24154 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
24155 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
24156 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24157 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24158 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24159 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24160 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24161 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24162 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24163 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24164 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24165 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24166 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24167 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24168 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24169 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24170 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24171 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24172 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24173 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24174 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24175 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24176 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24177 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24178 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24179 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24180 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24181 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24182 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24183 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24184 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
24187 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
24189 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
24190 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
24191 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
24192 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24193 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24194 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24195 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24196 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24197 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24198 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24199 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24200 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24201 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24202 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24203 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24204 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24205 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24206 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24207 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24208 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24209 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
24210 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24211 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24212 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24213 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24214 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24215 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24216 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24217 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24218 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24219 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24220 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24221 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24222 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24223 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24224 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24225 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24226 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24227 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24228 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24229 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24230 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24231 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24232 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24233 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24234 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24235 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24236 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24237 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24238 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24239 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24240 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24241 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24242 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24243 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24244 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24245 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24248 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
24250 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
24251 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
24252 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
24253 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
24254 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
24255 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
24256 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
24257 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
24258 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
24259 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
24260 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
24261 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
24262 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
24263 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
24264 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
24265 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
24266 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
24267 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
24268 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
24269 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
24270 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
24271 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
24272 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
24273 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
24274 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
24275 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
24276 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
24277 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
24278 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
24279 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
24280 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
24281 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
24282 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
24283 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
24284 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
24285 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
24286 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
24287 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
24288 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
24289 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
24290 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
24291 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
24292 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
24293 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
24294 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
24295 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
24296 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
24297 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
24298 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
24299 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
24300 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
24301 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
24302 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
24303 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
24304 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
24305 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
24306 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
24307 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
24308 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
24309 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
24310 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
24311 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
24312 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
24313 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
24314 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
24315 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
24316 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
24317 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
24318 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
24319 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
24320 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
24321 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
24322 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
24323 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
24324 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
24325 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
24327 /* ARMv8.5-A instructions. */
24329 #define ARM_VARIANT & arm_ext_sb
24330 #undef THUMB_VARIANT
24331 #define THUMB_VARIANT & arm_ext_sb
24332 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
24335 #define ARM_VARIANT & arm_ext_predres
24336 #undef THUMB_VARIANT
24337 #define THUMB_VARIANT & arm_ext_predres
24338 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
24339 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
24340 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
24342 /* ARMv8-M instructions. */
24344 #define ARM_VARIANT NULL
24345 #undef THUMB_VARIANT
24346 #define THUMB_VARIANT & arm_ext_v8m
24347 ToU("sg", e97fe97f
, 0, (), noargs
),
24348 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
24349 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
24350 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
24351 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
24352 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
24353 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
24355 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
24356 instructions behave as nop if no VFP is present. */
24357 #undef THUMB_VARIANT
24358 #define THUMB_VARIANT & arm_ext_v8m_main
24359 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
24360 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
24362 /* Armv8.1-M Mainline instructions. */
24363 #undef THUMB_VARIANT
24364 #define THUMB_VARIANT & arm_ext_v8_1m_main
24365 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
24366 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
24367 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
24368 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
24369 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
24371 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
24372 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
24373 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
24375 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
24376 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
24378 #undef THUMB_VARIANT
24379 #define THUMB_VARIANT & mve_ext
24381 ToC("vpt", ee410f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24382 ToC("vptt", ee018f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24383 ToC("vpte", ee418f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24384 ToC("vpttt", ee014f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24385 ToC("vptte", ee01cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24386 ToC("vptet", ee41cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24387 ToC("vptee", ee414f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24388 ToC("vptttt", ee012f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24389 ToC("vpttte", ee016f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24390 ToC("vpttet", ee01ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24391 ToC("vpttee", ee01af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24392 ToC("vptett", ee41af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24393 ToC("vptete", ee41ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24394 ToC("vpteet", ee416f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24395 ToC("vpteee", ee412f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24397 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
24398 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
24399 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
24400 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
24401 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
24402 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
24403 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
24404 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
24405 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
24406 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
24407 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
24408 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
24409 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
24410 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
24411 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
24413 /* MVE and MVE FP only. */
24414 mToC("vhcadd", ee000f00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vhcadd
),
24415 mCEF(vadc
, _vadc
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
24416 mCEF(vadci
, _vadci
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
24417 mToC("vsbc", fe300f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
24418 mToC("vsbci", fe301f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
24419 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
24420 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
24421 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24422 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24423 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24424 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24425 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24426 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24427 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24428 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24429 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24430 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24432 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
24433 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
24434 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24435 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24436 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24437 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24438 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
24439 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
24440 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24441 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24442 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24443 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24444 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24445 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24446 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24447 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24448 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24449 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24450 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24451 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24453 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
24454 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
24455 mCEF(vbrsr
, _vbrsr
, 3, (RMQ
, RMQ
, RR
), mve_vbrsr
),
24456 mCEF(vaddlv
, _vaddlv
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
24457 mCEF(vaddlva
, _vaddlva
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
24458 mCEF(vaddv
, _vaddv
, 2, (RRe
, RMQ
), mve_vaddv
),
24459 mCEF(vaddva
, _vaddva
, 2, (RRe
, RMQ
), mve_vaddv
),
24460 mCEF(vddup
, _vddup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
24461 mCEF(vdwdup
, _vdwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
24462 mCEF(vidup
, _vidup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
24463 mCEF(viwdup
, _viwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
24464 mToC("vmaxa", ee330e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
24465 mToC("vmina", ee331e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
24466 mCEF(vmaxv
, _vmaxv
, 2, (RR
, RMQ
), mve_vmaxv
),
24467 mCEF(vmaxav
, _vmaxav
, 2, (RR
, RMQ
), mve_vmaxv
),
24468 mCEF(vminv
, _vminv
, 2, (RR
, RMQ
), mve_vmaxv
),
24469 mCEF(vminav
, _vminav
, 2, (RR
, RMQ
), mve_vmaxv
),
24471 #undef THUMB_VARIANT
24472 #define THUMB_VARIANT & mve_fp_ext
24473 mToC("vcmul", ee300e00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vcmul
),
24474 mToC("vfmas", ee311e40
, 3, (RMQ
, RMQ
, RR
), mve_vfmas
),
24475 mToC("vmaxnma", ee3f0e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
24476 mToC("vminnma", ee3f1e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
24477 mToC("vmaxnmv", eeee0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
24478 mToC("vmaxnmav",eeec0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
24479 mToC("vminnmv", eeee0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
24480 mToC("vminnmav",eeec0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
24483 #define ARM_VARIANT & fpu_vfp_ext_v1
24484 #undef THUMB_VARIANT
24485 #define THUMB_VARIANT & arm_ext_v6t2
24487 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24490 #define ARM_VARIANT & fpu_vfp_ext_v1xd
24492 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
24493 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
24494 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
24495 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24497 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
24498 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
24499 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
24501 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
24502 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
24504 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
24505 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
24507 mnCE(vcmp
, _vcmp
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
24508 mnCE(vcmpe
, _vcmpe
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
24511 #define ARM_VARIANT & fpu_vfp_ext_v2
24513 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
24514 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
24515 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
24516 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
24519 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
24520 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
24521 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
24522 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
24523 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
24524 mnUF(vmaxnm
, _vmaxnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
24525 mnUF(vminnm
, _vminnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
24528 #define ARM_VARIANT & fpu_neon_ext_v1
24529 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
24530 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
24531 mnUF(vaddl
, _vaddl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
24532 mnUF(vsubl
, _vsubl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
24533 mnUF(vand
, _vand
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
24534 mnUF(vbic
, _vbic
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
24535 mnUF(vorr
, _vorr
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
24536 mnUF(vorn
, _vorn
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
24537 mnUF(veor
, _veor
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_logic
),
24538 MNUF(vcls
, 1b00400
, 2, (RNDQMQ
, RNDQMQ
), neon_cls
),
24539 MNUF(vclz
, 1b00480
, 2, (RNDQMQ
, RNDQMQ
), neon_clz
),
24540 mnCE(vdup
, _vdup
, 2, (RNDQMQ
, RR_RNSC
), neon_dup
),
24541 MNUF(vhadd
, 00000000, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
24542 MNUF(vrhadd
, 00000100, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_i_su
),
24543 MNUF(vhsub
, 00000200, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
24544 mnUF(vmin
, _vmin
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
24545 mnUF(vmax
, _vmax
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
24548 #define ARM_VARIANT & arm_ext_v8_3
24549 #undef THUMB_VARIANT
24550 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24551 MNUF (vcadd
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ
, EXPi
), vcadd
),
24552 MNUF (vcmla
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ_RNSC
, EXPi
), vcmla
),
24555 #undef THUMB_VARIANT
24587 /* MD interface: bits in the object file. */
24589 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
24590 for use in the a.out file, and stores them in the array pointed to by buf.
24591 This knows about the endian-ness of the target machine and does
24592 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
24593 2 (short) and 4 (long) Floating numbers are put out as a series of
24594 LITTLENUMS (shorts, here at least). */
24597 md_number_to_chars (char * buf
, valueT val
, int n
)
24599 if (target_big_endian
)
24600 number_to_chars_bigendian (buf
, val
, n
);
24602 number_to_chars_littleendian (buf
, val
, n
);
24606 md_chars_to_number (char * buf
, int n
)
24609 unsigned char * where
= (unsigned char *) buf
;
24611 if (target_big_endian
)
24616 result
|= (*where
++ & 255);
24624 result
|= (where
[n
] & 255);
24631 /* MD interface: Sections. */
24633 /* Calculate the maximum variable size (i.e., excluding fr_fix)
24634 that an rs_machine_dependent frag may reach. */
24637 arm_frag_max_var (fragS
*fragp
)
24639 /* We only use rs_machine_dependent for variable-size Thumb instructions,
24640 which are either THUMB_SIZE (2) or INSN_SIZE (4).
24642 Note that we generate relaxable instructions even for cases that don't
24643 really need it, like an immediate that's a trivial constant. So we're
24644 overestimating the instruction size for some of those cases. Rather
24645 than putting more intelligence here, it would probably be better to
24646 avoid generating a relaxation frag in the first place when it can be
24647 determined up front that a short instruction will suffice. */
24649 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
24653 /* Estimate the size of a frag before relaxing. Assume everything fits in
24657 md_estimate_size_before_relax (fragS
* fragp
,
24658 segT segtype ATTRIBUTE_UNUSED
)
24664 /* Convert a machine dependent frag. */
24667 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
24669 unsigned long insn
;
24670 unsigned long old_op
;
24678 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
24680 old_op
= bfd_get_16(abfd
, buf
);
24681 if (fragp
->fr_symbol
)
24683 exp
.X_op
= O_symbol
;
24684 exp
.X_add_symbol
= fragp
->fr_symbol
;
24688 exp
.X_op
= O_constant
;
24690 exp
.X_add_number
= fragp
->fr_offset
;
24691 opcode
= fragp
->fr_subtype
;
24694 case T_MNEM_ldr_pc
:
24695 case T_MNEM_ldr_pc2
:
24696 case T_MNEM_ldr_sp
:
24697 case T_MNEM_str_sp
:
24704 if (fragp
->fr_var
== 4)
24706 insn
= THUMB_OP32 (opcode
);
24707 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
24709 insn
|= (old_op
& 0x700) << 4;
24713 insn
|= (old_op
& 7) << 12;
24714 insn
|= (old_op
& 0x38) << 13;
24716 insn
|= 0x00000c00;
24717 put_thumb32_insn (buf
, insn
);
24718 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
24722 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
24724 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
24727 if (fragp
->fr_var
== 4)
24729 insn
= THUMB_OP32 (opcode
);
24730 insn
|= (old_op
& 0xf0) << 4;
24731 put_thumb32_insn (buf
, insn
);
24732 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
24736 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
24737 exp
.X_add_number
-= 4;
24745 if (fragp
->fr_var
== 4)
24747 int r0off
= (opcode
== T_MNEM_mov
24748 || opcode
== T_MNEM_movs
) ? 0 : 8;
24749 insn
= THUMB_OP32 (opcode
);
24750 insn
= (insn
& 0xe1ffffff) | 0x10000000;
24751 insn
|= (old_op
& 0x700) << r0off
;
24752 put_thumb32_insn (buf
, insn
);
24753 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
24757 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
24762 if (fragp
->fr_var
== 4)
24764 insn
= THUMB_OP32(opcode
);
24765 put_thumb32_insn (buf
, insn
);
24766 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
24769 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
24773 if (fragp
->fr_var
== 4)
24775 insn
= THUMB_OP32(opcode
);
24776 insn
|= (old_op
& 0xf00) << 14;
24777 put_thumb32_insn (buf
, insn
);
24778 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
24781 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
24784 case T_MNEM_add_sp
:
24785 case T_MNEM_add_pc
:
24786 case T_MNEM_inc_sp
:
24787 case T_MNEM_dec_sp
:
24788 if (fragp
->fr_var
== 4)
24790 /* ??? Choose between add and addw. */
24791 insn
= THUMB_OP32 (opcode
);
24792 insn
|= (old_op
& 0xf0) << 4;
24793 put_thumb32_insn (buf
, insn
);
24794 if (opcode
== T_MNEM_add_pc
)
24795 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
24797 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
24800 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
24808 if (fragp
->fr_var
== 4)
24810 insn
= THUMB_OP32 (opcode
);
24811 insn
|= (old_op
& 0xf0) << 4;
24812 insn
|= (old_op
& 0xf) << 16;
24813 put_thumb32_insn (buf
, insn
);
24814 if (insn
& (1 << 20))
24815 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
24817 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
24820 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
24826 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
24827 (enum bfd_reloc_code_real
) reloc_type
);
24828 fixp
->fx_file
= fragp
->fr_file
;
24829 fixp
->fx_line
= fragp
->fr_line
;
24830 fragp
->fr_fix
+= fragp
->fr_var
;
24832 /* Set whether we use thumb-2 ISA based on final relaxation results. */
24833 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
24834 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
24835 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
24838 /* Return the size of a relaxable immediate operand instruction.
24839 SHIFT and SIZE specify the form of the allowable immediate. */
24841 relax_immediate (fragS
*fragp
, int size
, int shift
)
24847 /* ??? Should be able to do better than this. */
24848 if (fragp
->fr_symbol
)
24851 low
= (1 << shift
) - 1;
24852 mask
= (1 << (shift
+ size
)) - (1 << shift
);
24853 offset
= fragp
->fr_offset
;
24854 /* Force misaligned offsets to 32-bit variant. */
24857 if (offset
& ~mask
)
24862 /* Get the address of a symbol during relaxation. */
24864 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
24870 sym
= fragp
->fr_symbol
;
24871 sym_frag
= symbol_get_frag (sym
);
24872 know (S_GET_SEGMENT (sym
) != absolute_section
24873 || sym_frag
== &zero_address_frag
);
24874 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
24876 /* If frag has yet to be reached on this pass, assume it will
24877 move by STRETCH just as we did. If this is not so, it will
24878 be because some frag between grows, and that will force
24882 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
24886 /* Adjust stretch for any alignment frag. Note that if have
24887 been expanding the earlier code, the symbol may be
24888 defined in what appears to be an earlier frag. FIXME:
24889 This doesn't handle the fr_subtype field, which specifies
24890 a maximum number of bytes to skip when doing an
24892 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
24894 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
24897 stretch
= - ((- stretch
)
24898 & ~ ((1 << (int) f
->fr_offset
) - 1));
24900 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
24912 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
24915 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
24920 /* Assume worst case for symbols not known to be in the same section. */
24921 if (fragp
->fr_symbol
== NULL
24922 || !S_IS_DEFINED (fragp
->fr_symbol
)
24923 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
24924 || S_IS_WEAK (fragp
->fr_symbol
))
24927 val
= relaxed_symbol_addr (fragp
, stretch
);
24928 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
24929 addr
= (addr
+ 4) & ~3;
24930 /* Force misaligned targets to 32-bit variant. */
24934 if (val
< 0 || val
> 1020)
24939 /* Return the size of a relaxable add/sub immediate instruction. */
24941 relax_addsub (fragS
*fragp
, asection
*sec
)
24946 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
24947 op
= bfd_get_16(sec
->owner
, buf
);
24948 if ((op
& 0xf) == ((op
>> 4) & 0xf))
24949 return relax_immediate (fragp
, 8, 0);
24951 return relax_immediate (fragp
, 3, 0);
24954 /* Return TRUE iff the definition of symbol S could be pre-empted
24955 (overridden) at link or load time. */
24957 symbol_preemptible (symbolS
*s
)
24959 /* Weak symbols can always be pre-empted. */
24963 /* Non-global symbols cannot be pre-empted. */
24964 if (! S_IS_EXTERNAL (s
))
24968 /* In ELF, a global symbol can be marked protected, or private. In that
24969 case it can't be pre-empted (other definitions in the same link unit
24970 would violate the ODR). */
24971 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
24975 /* Other global symbols might be pre-empted. */
24979 /* Return the size of a relaxable branch instruction. BITS is the
24980 size of the offset field in the narrow instruction. */
24983 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
24989 /* Assume worst case for symbols not known to be in the same section. */
24990 if (!S_IS_DEFINED (fragp
->fr_symbol
)
24991 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
24992 || S_IS_WEAK (fragp
->fr_symbol
))
24996 /* A branch to a function in ARM state will require interworking. */
24997 if (S_IS_DEFINED (fragp
->fr_symbol
)
24998 && ARM_IS_FUNC (fragp
->fr_symbol
))
25002 if (symbol_preemptible (fragp
->fr_symbol
))
25005 val
= relaxed_symbol_addr (fragp
, stretch
);
25006 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
25009 /* Offset is a signed value *2 */
25011 if (val
>= limit
|| val
< -limit
)
25017 /* Relax a machine dependent frag. This returns the amount by which
25018 the current size of the frag should change. */
25021 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
25026 oldsize
= fragp
->fr_var
;
25027 switch (fragp
->fr_subtype
)
25029 case T_MNEM_ldr_pc2
:
25030 newsize
= relax_adr (fragp
, sec
, stretch
);
25032 case T_MNEM_ldr_pc
:
25033 case T_MNEM_ldr_sp
:
25034 case T_MNEM_str_sp
:
25035 newsize
= relax_immediate (fragp
, 8, 2);
25039 newsize
= relax_immediate (fragp
, 5, 2);
25043 newsize
= relax_immediate (fragp
, 5, 1);
25047 newsize
= relax_immediate (fragp
, 5, 0);
25050 newsize
= relax_adr (fragp
, sec
, stretch
);
25056 newsize
= relax_immediate (fragp
, 8, 0);
25059 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
25062 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
25064 case T_MNEM_add_sp
:
25065 case T_MNEM_add_pc
:
25066 newsize
= relax_immediate (fragp
, 8, 2);
25068 case T_MNEM_inc_sp
:
25069 case T_MNEM_dec_sp
:
25070 newsize
= relax_immediate (fragp
, 7, 2);
25076 newsize
= relax_addsub (fragp
, sec
);
25082 fragp
->fr_var
= newsize
;
25083 /* Freeze wide instructions that are at or before the same location as
25084 in the previous pass. This avoids infinite loops.
25085 Don't freeze them unconditionally because targets may be artificially
25086 misaligned by the expansion of preceding frags. */
25087 if (stretch
<= 0 && newsize
> 2)
25089 md_convert_frag (sec
->owner
, sec
, fragp
);
25093 return newsize
- oldsize
;
25096 /* Round up a section size to the appropriate boundary. */
25099 md_section_align (segT segment ATTRIBUTE_UNUSED
,
25105 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
25106 of an rs_align_code fragment. */
25109 arm_handle_align (fragS
* fragP
)
25111 static unsigned char const arm_noop
[2][2][4] =
25114 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
25115 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
25118 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
25119 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
25122 static unsigned char const thumb_noop
[2][2][2] =
25125 {0xc0, 0x46}, /* LE */
25126 {0x46, 0xc0}, /* BE */
25129 {0x00, 0xbf}, /* LE */
25130 {0xbf, 0x00} /* BE */
25133 static unsigned char const wide_thumb_noop
[2][4] =
25134 { /* Wide Thumb-2 */
25135 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
25136 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
25139 unsigned bytes
, fix
, noop_size
;
25141 const unsigned char * noop
;
25142 const unsigned char *narrow_noop
= NULL
;
25147 if (fragP
->fr_type
!= rs_align_code
)
25150 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
25151 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
25154 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
25155 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
25157 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
25159 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
25161 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
25162 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
25164 narrow_noop
= thumb_noop
[1][target_big_endian
];
25165 noop
= wide_thumb_noop
[target_big_endian
];
25168 noop
= thumb_noop
[0][target_big_endian
];
25176 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
25177 ? selected_cpu
: arm_arch_none
,
25179 [target_big_endian
];
25186 fragP
->fr_var
= noop_size
;
25188 if (bytes
& (noop_size
- 1))
25190 fix
= bytes
& (noop_size
- 1);
25192 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
25194 memset (p
, 0, fix
);
25201 if (bytes
& noop_size
)
25203 /* Insert a narrow noop. */
25204 memcpy (p
, narrow_noop
, noop_size
);
25206 bytes
-= noop_size
;
25210 /* Use wide noops for the remainder */
25214 while (bytes
>= noop_size
)
25216 memcpy (p
, noop
, noop_size
);
25218 bytes
-= noop_size
;
25222 fragP
->fr_fix
+= fix
;
25225 /* Called from md_do_align. Used to create an alignment
25226 frag in a code section. */
25229 arm_frag_align_code (int n
, int max
)
25233 /* We assume that there will never be a requirement
25234 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
25235 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
25240 _("alignments greater than %d bytes not supported in .text sections."),
25241 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
25242 as_fatal ("%s", err_msg
);
25245 p
= frag_var (rs_align_code
,
25246 MAX_MEM_FOR_RS_ALIGN_CODE
,
25248 (relax_substateT
) max
,
25255 /* Perform target specific initialisation of a frag.
25256 Note - despite the name this initialisation is not done when the frag
25257 is created, but only when its type is assigned. A frag can be created
25258 and used a long time before its type is set, so beware of assuming that
25259 this initialisation is performed first. */
25263 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
25265 /* Record whether this frag is in an ARM or a THUMB area. */
25266 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
25269 #else /* OBJ_ELF is defined. */
25271 arm_init_frag (fragS
* fragP
, int max_chars
)
25273 bfd_boolean frag_thumb_mode
;
25275 /* If the current ARM vs THUMB mode has not already
25276 been recorded into this frag then do so now. */
25277 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
25278 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
25280 /* PR 21809: Do not set a mapping state for debug sections
25281 - it just confuses other tools. */
25282 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
25285 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
25287 /* Record a mapping symbol for alignment frags. We will delete this
25288 later if the alignment ends up empty. */
25289 switch (fragP
->fr_type
)
25292 case rs_align_test
:
25294 mapping_state_2 (MAP_DATA
, max_chars
);
25296 case rs_align_code
:
25297 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
25304 /* When we change sections we need to issue a new mapping symbol. */
25307 arm_elf_change_section (void)
25309 /* Link an unlinked unwind index table section to the .text section. */
25310 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
25311 && elf_linked_to_section (now_seg
) == NULL
)
25312 elf_linked_to_section (now_seg
) = text_section
;
25316 arm_elf_section_type (const char * str
, size_t len
)
25318 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
25319 return SHT_ARM_EXIDX
;
25324 /* Code to deal with unwinding tables. */
25326 static void add_unwind_adjustsp (offsetT
);
25328 /* Generate any deferred unwind frame offset. */
25331 flush_pending_unwind (void)
25335 offset
= unwind
.pending_offset
;
25336 unwind
.pending_offset
= 0;
25338 add_unwind_adjustsp (offset
);
25341 /* Add an opcode to this list for this function. Two-byte opcodes should
25342 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
25346 add_unwind_opcode (valueT op
, int length
)
25348 /* Add any deferred stack adjustment. */
25349 if (unwind
.pending_offset
)
25350 flush_pending_unwind ();
25352 unwind
.sp_restored
= 0;
25354 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
25356 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
25357 if (unwind
.opcodes
)
25358 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
25359 unwind
.opcode_alloc
);
25361 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
25366 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
25368 unwind
.opcode_count
++;
25372 /* Add unwind opcodes to adjust the stack pointer. */
25375 add_unwind_adjustsp (offsetT offset
)
25379 if (offset
> 0x200)
25381 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
25386 /* Long form: 0xb2, uleb128. */
25387 /* This might not fit in a word so add the individual bytes,
25388 remembering the list is built in reverse order. */
25389 o
= (valueT
) ((offset
- 0x204) >> 2);
25391 add_unwind_opcode (0, 1);
25393 /* Calculate the uleb128 encoding of the offset. */
25397 bytes
[n
] = o
& 0x7f;
25403 /* Add the insn. */
25405 add_unwind_opcode (bytes
[n
- 1], 1);
25406 add_unwind_opcode (0xb2, 1);
25408 else if (offset
> 0x100)
25410 /* Two short opcodes. */
25411 add_unwind_opcode (0x3f, 1);
25412 op
= (offset
- 0x104) >> 2;
25413 add_unwind_opcode (op
, 1);
25415 else if (offset
> 0)
25417 /* Short opcode. */
25418 op
= (offset
- 4) >> 2;
25419 add_unwind_opcode (op
, 1);
25421 else if (offset
< 0)
25424 while (offset
> 0x100)
25426 add_unwind_opcode (0x7f, 1);
25429 op
= ((offset
- 4) >> 2) | 0x40;
25430 add_unwind_opcode (op
, 1);
25434 /* Finish the list of unwind opcodes for this function. */
25437 finish_unwind_opcodes (void)
25441 if (unwind
.fp_used
)
25443 /* Adjust sp as necessary. */
25444 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
25445 flush_pending_unwind ();
25447 /* After restoring sp from the frame pointer. */
25448 op
= 0x90 | unwind
.fp_reg
;
25449 add_unwind_opcode (op
, 1);
25452 flush_pending_unwind ();
25456 /* Start an exception table entry. If idx is nonzero this is an index table
25460 start_unwind_section (const segT text_seg
, int idx
)
25462 const char * text_name
;
25463 const char * prefix
;
25464 const char * prefix_once
;
25465 const char * group_name
;
25473 prefix
= ELF_STRING_ARM_unwind
;
25474 prefix_once
= ELF_STRING_ARM_unwind_once
;
25475 type
= SHT_ARM_EXIDX
;
25479 prefix
= ELF_STRING_ARM_unwind_info
;
25480 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
25481 type
= SHT_PROGBITS
;
25484 text_name
= segment_name (text_seg
);
25485 if (streq (text_name
, ".text"))
25488 if (strncmp (text_name
, ".gnu.linkonce.t.",
25489 strlen (".gnu.linkonce.t.")) == 0)
25491 prefix
= prefix_once
;
25492 text_name
+= strlen (".gnu.linkonce.t.");
25495 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
25501 /* Handle COMDAT group. */
25502 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
25504 group_name
= elf_group_name (text_seg
);
25505 if (group_name
== NULL
)
25507 as_bad (_("Group section `%s' has no group signature"),
25508 segment_name (text_seg
));
25509 ignore_rest_of_line ();
25512 flags
|= SHF_GROUP
;
25516 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
25519 /* Set the section link for index tables. */
25521 elf_linked_to_section (now_seg
) = text_seg
;
25525 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
25526 personality routine data. Returns zero, or the index table value for
25527 an inline entry. */
25530 create_unwind_entry (int have_data
)
25535 /* The current word of data. */
25537 /* The number of bytes left in this word. */
25540 finish_unwind_opcodes ();
25542 /* Remember the current text section. */
25543 unwind
.saved_seg
= now_seg
;
25544 unwind
.saved_subseg
= now_subseg
;
25546 start_unwind_section (now_seg
, 0);
25548 if (unwind
.personality_routine
== NULL
)
25550 if (unwind
.personality_index
== -2)
25553 as_bad (_("handlerdata in cantunwind frame"));
25554 return 1; /* EXIDX_CANTUNWIND. */
25557 /* Use a default personality routine if none is specified. */
25558 if (unwind
.personality_index
== -1)
25560 if (unwind
.opcode_count
> 3)
25561 unwind
.personality_index
= 1;
25563 unwind
.personality_index
= 0;
25566 /* Space for the personality routine entry. */
25567 if (unwind
.personality_index
== 0)
25569 if (unwind
.opcode_count
> 3)
25570 as_bad (_("too many unwind opcodes for personality routine 0"));
25574 /* All the data is inline in the index table. */
25577 while (unwind
.opcode_count
> 0)
25579 unwind
.opcode_count
--;
25580 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
25584 /* Pad with "finish" opcodes. */
25586 data
= (data
<< 8) | 0xb0;
25593 /* We get two opcodes "free" in the first word. */
25594 size
= unwind
.opcode_count
- 2;
25598 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
25599 if (unwind
.personality_index
!= -1)
25601 as_bad (_("attempt to recreate an unwind entry"));
25605 /* An extra byte is required for the opcode count. */
25606 size
= unwind
.opcode_count
+ 1;
25609 size
= (size
+ 3) >> 2;
25611 as_bad (_("too many unwind opcodes"));
25613 frag_align (2, 0, 0);
25614 record_alignment (now_seg
, 2);
25615 unwind
.table_entry
= expr_build_dot ();
25617 /* Allocate the table entry. */
25618 ptr
= frag_more ((size
<< 2) + 4);
25619 /* PR 13449: Zero the table entries in case some of them are not used. */
25620 memset (ptr
, 0, (size
<< 2) + 4);
25621 where
= frag_now_fix () - ((size
<< 2) + 4);
25623 switch (unwind
.personality_index
)
25626 /* ??? Should this be a PLT generating relocation? */
25627 /* Custom personality routine. */
25628 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
25629 BFD_RELOC_ARM_PREL31
);
25634 /* Set the first byte to the number of additional words. */
25635 data
= size
> 0 ? size
- 1 : 0;
25639 /* ABI defined personality routines. */
25641 /* Three opcodes bytes are packed into the first word. */
25648 /* The size and first two opcode bytes go in the first word. */
25649 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
25654 /* Should never happen. */
25658 /* Pack the opcodes into words (MSB first), reversing the list at the same
25660 while (unwind
.opcode_count
> 0)
25664 md_number_to_chars (ptr
, data
, 4);
25669 unwind
.opcode_count
--;
25671 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
25674 /* Finish off the last word. */
25677 /* Pad with "finish" opcodes. */
25679 data
= (data
<< 8) | 0xb0;
25681 md_number_to_chars (ptr
, data
, 4);
25686 /* Add an empty descriptor if there is no user-specified data. */
25687 ptr
= frag_more (4);
25688 md_number_to_chars (ptr
, 0, 4);
25695 /* Initialize the DWARF-2 unwind information for this procedure. */
25698 tc_arm_frame_initial_instructions (void)
25700 cfi_add_CFA_def_cfa (REG_SP
, 0);
25702 #endif /* OBJ_ELF */
25704 /* Convert REGNAME to a DWARF-2 register number. */
25707 tc_arm_regname_to_dw2regnum (char *regname
)
25709 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
25713 /* PR 16694: Allow VFP registers as well. */
25714 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
25718 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
25727 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
25731 exp
.X_op
= O_secrel
;
25732 exp
.X_add_symbol
= symbol
;
25733 exp
.X_add_number
= 0;
25734 emit_expr (&exp
, size
);
25738 /* MD interface: Symbol and relocation handling. */
25740 /* Return the address within the segment that a PC-relative fixup is
25741 relative to. For ARM, PC-relative fixups applied to instructions
25742 are generally relative to the location of the fixup plus 8 bytes.
25743 Thumb branches are offset by 4, and Thumb loads relative to PC
25744 require special handling. */
25747 md_pcrel_from_section (fixS
* fixP
, segT seg
)
25749 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
25751 /* If this is pc-relative and we are going to emit a relocation
25752 then we just want to put out any pipeline compensation that the linker
25753 will need. Otherwise we want to use the calculated base.
25754 For WinCE we skip the bias for externals as well, since this
25755 is how the MS ARM-CE assembler behaves and we want to be compatible. */
25757 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
25758 || (arm_force_relocation (fixP
)
25760 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
25766 switch (fixP
->fx_r_type
)
25768 /* PC relative addressing on the Thumb is slightly odd as the
25769 bottom two bits of the PC are forced to zero for the
25770 calculation. This happens *after* application of the
25771 pipeline offset. However, Thumb adrl already adjusts for
25772 this, so we need not do it again. */
25773 case BFD_RELOC_ARM_THUMB_ADD
:
25776 case BFD_RELOC_ARM_THUMB_OFFSET
:
25777 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
25778 case BFD_RELOC_ARM_T32_ADD_PC12
:
25779 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
25780 return (base
+ 4) & ~3;
25782 /* Thumb branches are simply offset by +4. */
25783 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
25784 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
25785 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
25786 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
25787 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
25788 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
25789 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
25790 case BFD_RELOC_ARM_THUMB_BF17
:
25791 case BFD_RELOC_ARM_THUMB_BF19
:
25792 case BFD_RELOC_ARM_THUMB_BF13
:
25793 case BFD_RELOC_ARM_THUMB_LOOP12
:
25796 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25798 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25799 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25800 && ARM_IS_FUNC (fixP
->fx_addsy
)
25801 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
25802 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
25805 /* BLX is like branches above, but forces the low two bits of PC to
25807 case BFD_RELOC_THUMB_PCREL_BLX
:
25809 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25810 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25811 && THUMB_IS_FUNC (fixP
->fx_addsy
)
25812 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
25813 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
25814 return (base
+ 4) & ~3;
25816 /* ARM mode branches are offset by +8. However, the Windows CE
25817 loader expects the relocation not to take this into account. */
25818 case BFD_RELOC_ARM_PCREL_BLX
:
25820 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25821 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25822 && ARM_IS_FUNC (fixP
->fx_addsy
)
25823 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
25824 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
25827 case BFD_RELOC_ARM_PCREL_CALL
:
25829 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25830 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25831 && THUMB_IS_FUNC (fixP
->fx_addsy
)
25832 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
25833 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
25836 case BFD_RELOC_ARM_PCREL_BRANCH
:
25837 case BFD_RELOC_ARM_PCREL_JUMP
:
25838 case BFD_RELOC_ARM_PLT32
:
25840 /* When handling fixups immediately, because we have already
25841 discovered the value of a symbol, or the address of the frag involved
25842 we must account for the offset by +8, as the OS loader will never see the reloc.
25843 see fixup_segment() in write.c
25844 The S_IS_EXTERNAL test handles the case of global symbols.
25845 Those need the calculated base, not just the pipe compensation the linker will need. */
25847 && fixP
->fx_addsy
!= NULL
25848 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25849 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
25857 /* ARM mode loads relative to PC are also offset by +8. Unlike
25858 branches, the Windows CE loader *does* expect the relocation
25859 to take this into account. */
25860 case BFD_RELOC_ARM_OFFSET_IMM
:
25861 case BFD_RELOC_ARM_OFFSET_IMM8
:
25862 case BFD_RELOC_ARM_HWLITERAL
:
25863 case BFD_RELOC_ARM_LITERAL
:
25864 case BFD_RELOC_ARM_CP_OFF_IMM
:
25868 /* Other PC-relative relocations are un-offset. */
25874 static bfd_boolean flag_warn_syms
= TRUE
;
25877 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
25879 /* PR 18347 - Warn if the user attempts to create a symbol with the same
25880 name as an ARM instruction. Whilst strictly speaking it is allowed, it
25881 does mean that the resulting code might be very confusing to the reader.
25882 Also this warning can be triggered if the user omits an operand before
25883 an immediate address, eg:
25887 GAS treats this as an assignment of the value of the symbol foo to a
25888 symbol LDR, and so (without this code) it will not issue any kind of
25889 warning or error message.
25891 Note - ARM instructions are case-insensitive but the strings in the hash
25892 table are all stored in lower case, so we must first ensure that name is
25894 if (flag_warn_syms
&& arm_ops_hsh
)
25896 char * nbuf
= strdup (name
);
25899 for (p
= nbuf
; *p
; p
++)
25901 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
25903 static struct hash_control
* already_warned
= NULL
;
25905 if (already_warned
== NULL
)
25906 already_warned
= hash_new ();
25907 /* Only warn about the symbol once. To keep the code
25908 simple we let hash_insert do the lookup for us. */
25909 if (hash_insert (already_warned
, nbuf
, NULL
) == NULL
)
25910 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
25919 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
25920 Otherwise we have no need to default values of symbols. */
25923 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
25926 if (name
[0] == '_' && name
[1] == 'G'
25927 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
25931 if (symbol_find (name
))
25932 as_bad (_("GOT already in the symbol table"));
25934 GOT_symbol
= symbol_new (name
, undefined_section
,
25935 (valueT
) 0, & zero_address_frag
);
25945 /* Subroutine of md_apply_fix. Check to see if an immediate can be
25946 computed as two separate immediate values, added together. We
25947 already know that this value cannot be computed by just one ARM
25950 static unsigned int
25951 validate_immediate_twopart (unsigned int val
,
25952 unsigned int * highpart
)
25957 for (i
= 0; i
< 32; i
+= 2)
25958 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
25964 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
25966 else if (a
& 0xff0000)
25968 if (a
& 0xff000000)
25970 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
25974 gas_assert (a
& 0xff000000);
25975 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
25978 return (a
& 0xff) | (i
<< 7);
25985 validate_offset_imm (unsigned int val
, int hwse
)
25987 if ((hwse
&& val
> 255) || val
> 4095)
25992 /* Subroutine of md_apply_fix. Do those data_ops which can take a
25993 negative immediate constant by altering the instruction. A bit of
25998 by inverting the second operand, and
26001 by negating the second operand. */
26004 negate_data_op (unsigned long * instruction
,
26005 unsigned long value
)
26008 unsigned long negated
, inverted
;
26010 negated
= encode_arm_immediate (-value
);
26011 inverted
= encode_arm_immediate (~value
);
26013 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
26016 /* First negates. */
26017 case OPCODE_SUB
: /* ADD <-> SUB */
26018 new_inst
= OPCODE_ADD
;
26023 new_inst
= OPCODE_SUB
;
26027 case OPCODE_CMP
: /* CMP <-> CMN */
26028 new_inst
= OPCODE_CMN
;
26033 new_inst
= OPCODE_CMP
;
26037 /* Now Inverted ops. */
26038 case OPCODE_MOV
: /* MOV <-> MVN */
26039 new_inst
= OPCODE_MVN
;
26044 new_inst
= OPCODE_MOV
;
26048 case OPCODE_AND
: /* AND <-> BIC */
26049 new_inst
= OPCODE_BIC
;
26054 new_inst
= OPCODE_AND
;
26058 case OPCODE_ADC
: /* ADC <-> SBC */
26059 new_inst
= OPCODE_SBC
;
26064 new_inst
= OPCODE_ADC
;
26068 /* We cannot do anything. */
26073 if (value
== (unsigned) FAIL
)
26076 *instruction
&= OPCODE_MASK
;
26077 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
26081 /* Like negate_data_op, but for Thumb-2. */
26083 static unsigned int
26084 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
26088 unsigned int negated
, inverted
;
26090 negated
= encode_thumb32_immediate (-value
);
26091 inverted
= encode_thumb32_immediate (~value
);
26093 rd
= (*instruction
>> 8) & 0xf;
26094 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
26097 /* ADD <-> SUB. Includes CMP <-> CMN. */
26098 case T2_OPCODE_SUB
:
26099 new_inst
= T2_OPCODE_ADD
;
26103 case T2_OPCODE_ADD
:
26104 new_inst
= T2_OPCODE_SUB
;
26108 /* ORR <-> ORN. Includes MOV <-> MVN. */
26109 case T2_OPCODE_ORR
:
26110 new_inst
= T2_OPCODE_ORN
;
26114 case T2_OPCODE_ORN
:
26115 new_inst
= T2_OPCODE_ORR
;
26119 /* AND <-> BIC. TST has no inverted equivalent. */
26120 case T2_OPCODE_AND
:
26121 new_inst
= T2_OPCODE_BIC
;
26128 case T2_OPCODE_BIC
:
26129 new_inst
= T2_OPCODE_AND
;
26134 case T2_OPCODE_ADC
:
26135 new_inst
= T2_OPCODE_SBC
;
26139 case T2_OPCODE_SBC
:
26140 new_inst
= T2_OPCODE_ADC
;
26144 /* We cannot do anything. */
26149 if (value
== (unsigned int)FAIL
)
26152 *instruction
&= T2_OPCODE_MASK
;
26153 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
26157 /* Read a 32-bit thumb instruction from buf. */
26159 static unsigned long
26160 get_thumb32_insn (char * buf
)
26162 unsigned long insn
;
26163 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
26164 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
26169 /* We usually want to set the low bit on the address of thumb function
26170 symbols. In particular .word foo - . should have the low bit set.
26171 Generic code tries to fold the difference of two symbols to
26172 a constant. Prevent this and force a relocation when the first symbols
26173 is a thumb function. */
26176 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
26178 if (op
== O_subtract
26179 && l
->X_op
== O_symbol
26180 && r
->X_op
== O_symbol
26181 && THUMB_IS_FUNC (l
->X_add_symbol
))
26183 l
->X_op
= O_subtract
;
26184 l
->X_op_symbol
= r
->X_add_symbol
;
26185 l
->X_add_number
-= r
->X_add_number
;
26189 /* Process as normal. */
26193 /* Encode Thumb2 unconditional branches and calls. The encoding
26194 for the 2 are identical for the immediate values. */
26197 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
26199 #define T2I1I2MASK ((1 << 13) | (1 << 11))
26202 addressT S
, I1
, I2
, lo
, hi
;
26204 S
= (value
>> 24) & 0x01;
26205 I1
= (value
>> 23) & 0x01;
26206 I2
= (value
>> 22) & 0x01;
26207 hi
= (value
>> 12) & 0x3ff;
26208 lo
= (value
>> 1) & 0x7ff;
26209 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26210 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
26211 newval
|= (S
<< 10) | hi
;
26212 newval2
&= ~T2I1I2MASK
;
26213 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
26214 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26215 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
26219 md_apply_fix (fixS
* fixP
,
26223 offsetT value
= * valP
;
26225 unsigned int newimm
;
26226 unsigned long temp
;
26228 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
26230 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
26232 /* Note whether this will delete the relocation. */
26234 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
26237 /* On a 64-bit host, silently truncate 'value' to 32 bits for
26238 consistency with the behaviour on 32-bit hosts. Remember value
26240 value
&= 0xffffffff;
26241 value
^= 0x80000000;
26242 value
-= 0x80000000;
26245 fixP
->fx_addnumber
= value
;
26247 /* Same treatment for fixP->fx_offset. */
26248 fixP
->fx_offset
&= 0xffffffff;
26249 fixP
->fx_offset
^= 0x80000000;
26250 fixP
->fx_offset
-= 0x80000000;
26252 switch (fixP
->fx_r_type
)
26254 case BFD_RELOC_NONE
:
26255 /* This will need to go in the object file. */
26259 case BFD_RELOC_ARM_IMMEDIATE
:
26260 /* We claim that this fixup has been processed here,
26261 even if in fact we generate an error because we do
26262 not have a reloc for it, so tc_gen_reloc will reject it. */
26265 if (fixP
->fx_addsy
)
26267 const char *msg
= 0;
26269 if (! S_IS_DEFINED (fixP
->fx_addsy
))
26270 msg
= _("undefined symbol %s used as an immediate value");
26271 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
26272 msg
= _("symbol %s is in a different section");
26273 else if (S_IS_WEAK (fixP
->fx_addsy
))
26274 msg
= _("symbol %s is weak and may be overridden later");
26278 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26279 msg
, S_GET_NAME (fixP
->fx_addsy
));
26284 temp
= md_chars_to_number (buf
, INSN_SIZE
);
26286 /* If the offset is negative, we should use encoding A2 for ADR. */
26287 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
26288 newimm
= negate_data_op (&temp
, value
);
26291 newimm
= encode_arm_immediate (value
);
26293 /* If the instruction will fail, see if we can fix things up by
26294 changing the opcode. */
26295 if (newimm
== (unsigned int) FAIL
)
26296 newimm
= negate_data_op (&temp
, value
);
26297 /* MOV accepts both ARM modified immediate (A1 encoding) and
26298 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
26299 When disassembling, MOV is preferred when there is no encoding
26301 if (newimm
== (unsigned int) FAIL
26302 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
26303 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
26304 && !((temp
>> SBIT_SHIFT
) & 0x1)
26305 && value
>= 0 && value
<= 0xffff)
26307 /* Clear bits[23:20] to change encoding from A1 to A2. */
26308 temp
&= 0xff0fffff;
26309 /* Encoding high 4bits imm. Code below will encode the remaining
26311 temp
|= (value
& 0x0000f000) << 4;
26312 newimm
= value
& 0x00000fff;
26316 if (newimm
== (unsigned int) FAIL
)
26318 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26319 _("invalid constant (%lx) after fixup"),
26320 (unsigned long) value
);
26324 newimm
|= (temp
& 0xfffff000);
26325 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
26328 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
26330 unsigned int highpart
= 0;
26331 unsigned int newinsn
= 0xe1a00000; /* nop. */
26333 if (fixP
->fx_addsy
)
26335 const char *msg
= 0;
26337 if (! S_IS_DEFINED (fixP
->fx_addsy
))
26338 msg
= _("undefined symbol %s used as an immediate value");
26339 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
26340 msg
= _("symbol %s is in a different section");
26341 else if (S_IS_WEAK (fixP
->fx_addsy
))
26342 msg
= _("symbol %s is weak and may be overridden later");
26346 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26347 msg
, S_GET_NAME (fixP
->fx_addsy
));
26352 newimm
= encode_arm_immediate (value
);
26353 temp
= md_chars_to_number (buf
, INSN_SIZE
);
26355 /* If the instruction will fail, see if we can fix things up by
26356 changing the opcode. */
26357 if (newimm
== (unsigned int) FAIL
26358 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
26360 /* No ? OK - try using two ADD instructions to generate
26362 newimm
= validate_immediate_twopart (value
, & highpart
);
26364 /* Yes - then make sure that the second instruction is
26366 if (newimm
!= (unsigned int) FAIL
)
26368 /* Still No ? Try using a negated value. */
26369 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
26370 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
26371 /* Otherwise - give up. */
26374 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26375 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
26380 /* Replace the first operand in the 2nd instruction (which
26381 is the PC) with the destination register. We have
26382 already added in the PC in the first instruction and we
26383 do not want to do it again. */
26384 newinsn
&= ~ 0xf0000;
26385 newinsn
|= ((newinsn
& 0x0f000) << 4);
26388 newimm
|= (temp
& 0xfffff000);
26389 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
26391 highpart
|= (newinsn
& 0xfffff000);
26392 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
26396 case BFD_RELOC_ARM_OFFSET_IMM
:
26397 if (!fixP
->fx_done
&& seg
->use_rela_p
)
26399 /* Fall through. */
26401 case BFD_RELOC_ARM_LITERAL
:
26407 if (validate_offset_imm (value
, 0) == FAIL
)
26409 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
26410 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26411 _("invalid literal constant: pool needs to be closer"));
26413 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26414 _("bad immediate value for offset (%ld)"),
26419 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26421 newval
&= 0xfffff000;
26424 newval
&= 0xff7ff000;
26425 newval
|= value
| (sign
? INDEX_UP
: 0);
26427 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26430 case BFD_RELOC_ARM_OFFSET_IMM8
:
26431 case BFD_RELOC_ARM_HWLITERAL
:
26437 if (validate_offset_imm (value
, 1) == FAIL
)
26439 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
26440 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26441 _("invalid literal constant: pool needs to be closer"));
26443 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26444 _("bad immediate value for 8-bit offset (%ld)"),
26449 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26451 newval
&= 0xfffff0f0;
26454 newval
&= 0xff7ff0f0;
26455 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
26457 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26460 case BFD_RELOC_ARM_T32_OFFSET_U8
:
26461 if (value
< 0 || value
> 1020 || value
% 4 != 0)
26462 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26463 _("bad immediate value for offset (%ld)"), (long) value
);
26466 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
26468 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
26471 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
26472 /* This is a complicated relocation used for all varieties of Thumb32
26473 load/store instruction with immediate offset:
26475 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
26476 *4, optional writeback(W)
26477 (doubleword load/store)
26479 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
26480 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
26481 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
26482 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
26483 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
26485 Uppercase letters indicate bits that are already encoded at
26486 this point. Lowercase letters are our problem. For the
26487 second block of instructions, the secondary opcode nybble
26488 (bits 8..11) is present, and bit 23 is zero, even if this is
26489 a PC-relative operation. */
26490 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26492 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
26494 if ((newval
& 0xf0000000) == 0xe0000000)
26496 /* Doubleword load/store: 8-bit offset, scaled by 4. */
26498 newval
|= (1 << 23);
26501 if (value
% 4 != 0)
26503 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26504 _("offset not a multiple of 4"));
26510 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26511 _("offset out of range"));
26516 else if ((newval
& 0x000f0000) == 0x000f0000)
26518 /* PC-relative, 12-bit offset. */
26520 newval
|= (1 << 23);
26525 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26526 _("offset out of range"));
26531 else if ((newval
& 0x00000100) == 0x00000100)
26533 /* Writeback: 8-bit, +/- offset. */
26535 newval
|= (1 << 9);
26540 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26541 _("offset out of range"));
26546 else if ((newval
& 0x00000f00) == 0x00000e00)
26548 /* T-instruction: positive 8-bit offset. */
26549 if (value
< 0 || value
> 0xff)
26551 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26552 _("offset out of range"));
26560 /* Positive 12-bit or negative 8-bit offset. */
26564 newval
|= (1 << 23);
26574 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26575 _("offset out of range"));
26582 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
26583 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
26586 case BFD_RELOC_ARM_SHIFT_IMM
:
26587 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26588 if (((unsigned long) value
) > 32
26590 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
26592 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26593 _("shift expression is too large"));
26598 /* Shifts of zero must be done as lsl. */
26600 else if (value
== 32)
26602 newval
&= 0xfffff07f;
26603 newval
|= (value
& 0x1f) << 7;
26604 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26607 case BFD_RELOC_ARM_T32_IMMEDIATE
:
26608 case BFD_RELOC_ARM_T32_ADD_IMM
:
26609 case BFD_RELOC_ARM_T32_IMM12
:
26610 case BFD_RELOC_ARM_T32_ADD_PC12
:
26611 /* We claim that this fixup has been processed here,
26612 even if in fact we generate an error because we do
26613 not have a reloc for it, so tc_gen_reloc will reject it. */
26617 && ! S_IS_DEFINED (fixP
->fx_addsy
))
26619 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26620 _("undefined symbol %s used as an immediate value"),
26621 S_GET_NAME (fixP
->fx_addsy
));
26625 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26627 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
26630 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
26631 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
26632 Thumb2 modified immediate encoding (T2). */
26633 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
26634 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
26636 newimm
= encode_thumb32_immediate (value
);
26637 if (newimm
== (unsigned int) FAIL
)
26638 newimm
= thumb32_negate_data_op (&newval
, value
);
26640 if (newimm
== (unsigned int) FAIL
)
26642 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
26644 /* Turn add/sum into addw/subw. */
26645 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
26646 newval
= (newval
& 0xfeffffff) | 0x02000000;
26647 /* No flat 12-bit imm encoding for addsw/subsw. */
26648 if ((newval
& 0x00100000) == 0)
26650 /* 12 bit immediate for addw/subw. */
26654 newval
^= 0x00a00000;
26657 newimm
= (unsigned int) FAIL
;
26664 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
26665 UINT16 (T3 encoding), MOVW only accepts UINT16. When
26666 disassembling, MOV is preferred when there is no encoding
26668 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
26669 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
26670 but with the Rn field [19:16] set to 1111. */
26671 && (((newval
>> 16) & 0xf) == 0xf)
26672 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
26673 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
26674 && value
>= 0 && value
<= 0xffff)
26676 /* Toggle bit[25] to change encoding from T2 to T3. */
26678 /* Clear bits[19:16]. */
26679 newval
&= 0xfff0ffff;
26680 /* Encoding high 4bits imm. Code below will encode the
26681 remaining low 12bits. */
26682 newval
|= (value
& 0x0000f000) << 4;
26683 newimm
= value
& 0x00000fff;
26688 if (newimm
== (unsigned int)FAIL
)
26690 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26691 _("invalid constant (%lx) after fixup"),
26692 (unsigned long) value
);
26696 newval
|= (newimm
& 0x800) << 15;
26697 newval
|= (newimm
& 0x700) << 4;
26698 newval
|= (newimm
& 0x0ff);
26700 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
26701 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
26704 case BFD_RELOC_ARM_SMC
:
26705 if (((unsigned long) value
) > 0xffff)
26706 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26707 _("invalid smc expression"));
26708 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26709 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
26710 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26713 case BFD_RELOC_ARM_HVC
:
26714 if (((unsigned long) value
) > 0xffff)
26715 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26716 _("invalid hvc expression"));
26717 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26718 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
26719 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26722 case BFD_RELOC_ARM_SWI
:
26723 if (fixP
->tc_fix_data
!= 0)
26725 if (((unsigned long) value
) > 0xff)
26726 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26727 _("invalid swi expression"));
26728 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26730 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26734 if (((unsigned long) value
) > 0x00ffffff)
26735 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26736 _("invalid swi expression"));
26737 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26739 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26743 case BFD_RELOC_ARM_MULTI
:
26744 if (((unsigned long) value
) > 0xffff)
26745 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26746 _("invalid expression in load/store multiple"));
26747 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
26748 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26752 case BFD_RELOC_ARM_PCREL_CALL
:
26754 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
26756 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26757 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26758 && THUMB_IS_FUNC (fixP
->fx_addsy
))
26759 /* Flip the bl to blx. This is a simple flip
26760 bit here because we generate PCREL_CALL for
26761 unconditional bls. */
26763 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26764 newval
= newval
| 0x10000000;
26765 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26771 goto arm_branch_common
;
26773 case BFD_RELOC_ARM_PCREL_JUMP
:
26774 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
26776 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26777 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26778 && THUMB_IS_FUNC (fixP
->fx_addsy
))
26780 /* This would map to a bl<cond>, b<cond>,
26781 b<always> to a Thumb function. We
26782 need to force a relocation for this particular
26784 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26787 /* Fall through. */
26789 case BFD_RELOC_ARM_PLT32
:
26791 case BFD_RELOC_ARM_PCREL_BRANCH
:
26793 goto arm_branch_common
;
26795 case BFD_RELOC_ARM_PCREL_BLX
:
26798 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
26800 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26801 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26802 && ARM_IS_FUNC (fixP
->fx_addsy
))
26804 /* Flip the blx to a bl and warn. */
26805 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
26806 newval
= 0xeb000000;
26807 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
26808 _("blx to '%s' an ARM ISA state function changed to bl"),
26810 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26816 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
26817 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
26821 /* We are going to store value (shifted right by two) in the
26822 instruction, in a 24 bit, signed field. Bits 26 through 32 either
26823 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
26826 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26827 _("misaligned branch destination"));
26828 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
26829 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
26830 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26832 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26834 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26835 newval
|= (value
>> 2) & 0x00ffffff;
26836 /* Set the H bit on BLX instructions. */
26840 newval
|= 0x01000000;
26842 newval
&= ~0x01000000;
26844 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26848 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
26849 /* CBZ can only branch forward. */
26851 /* Attempts to use CBZ to branch to the next instruction
26852 (which, strictly speaking, are prohibited) will be turned into
26855 FIXME: It may be better to remove the instruction completely and
26856 perform relaxation. */
26859 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26860 newval
= 0xbf00; /* NOP encoding T1 */
26861 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26866 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26868 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26870 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26871 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
26872 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26877 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
26878 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
26879 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26881 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26883 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26884 newval
|= (value
& 0x1ff) >> 1;
26885 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26889 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
26890 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
26891 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26893 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26895 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26896 newval
|= (value
& 0xfff) >> 1;
26897 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26901 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
26903 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26904 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26905 && ARM_IS_FUNC (fixP
->fx_addsy
)
26906 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26908 /* Force a relocation for a branch 20 bits wide. */
26911 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
26912 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26913 _("conditional branch out of range"));
26915 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26918 addressT S
, J1
, J2
, lo
, hi
;
26920 S
= (value
& 0x00100000) >> 20;
26921 J2
= (value
& 0x00080000) >> 19;
26922 J1
= (value
& 0x00040000) >> 18;
26923 hi
= (value
& 0x0003f000) >> 12;
26924 lo
= (value
& 0x00000ffe) >> 1;
26926 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26927 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
26928 newval
|= (S
<< 10) | hi
;
26929 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
26930 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26931 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
26935 case BFD_RELOC_THUMB_PCREL_BLX
:
26936 /* If there is a blx from a thumb state function to
26937 another thumb function flip this to a bl and warn
26941 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26942 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26943 && THUMB_IS_FUNC (fixP
->fx_addsy
))
26945 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
26946 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
26947 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
26949 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
26950 newval
= newval
| 0x1000;
26951 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
26952 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
26957 goto thumb_bl_common
;
26959 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26960 /* A bl from Thumb state ISA to an internal ARM state function
26961 is converted to a blx. */
26963 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26964 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26965 && ARM_IS_FUNC (fixP
->fx_addsy
)
26966 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26968 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
26969 newval
= newval
& ~0x1000;
26970 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
26971 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
26977 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
26978 /* For a BLX instruction, make sure that the relocation is rounded up
26979 to a word boundary. This follows the semantics of the instruction
26980 which specifies that bit 1 of the target address will come from bit
26981 1 of the base address. */
26982 value
= (value
+ 3) & ~ 3;
26985 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
26986 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
26987 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
26990 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
26992 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
26993 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26994 else if ((value
& ~0x1ffffff)
26995 && ((value
& ~0x1ffffff) != ~0x1ffffff))
26996 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26997 _("Thumb2 branch out of range"));
27000 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27001 encode_thumb2_b_bl_offset (buf
, value
);
27005 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27006 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
27007 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27009 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27010 encode_thumb2_b_bl_offset (buf
, value
);
27015 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27020 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27021 md_number_to_chars (buf
, value
, 2);
27025 case BFD_RELOC_ARM_TLS_CALL
:
27026 case BFD_RELOC_ARM_THM_TLS_CALL
:
27027 case BFD_RELOC_ARM_TLS_DESCSEQ
:
27028 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
27029 case BFD_RELOC_ARM_TLS_GOTDESC
:
27030 case BFD_RELOC_ARM_TLS_GD32
:
27031 case BFD_RELOC_ARM_TLS_LE32
:
27032 case BFD_RELOC_ARM_TLS_IE32
:
27033 case BFD_RELOC_ARM_TLS_LDM32
:
27034 case BFD_RELOC_ARM_TLS_LDO32
:
27035 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
27038 /* Same handling as above, but with the arm_fdpic guard. */
27039 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
27040 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
27041 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
27044 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
27048 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27049 _("Relocation supported only in FDPIC mode"));
27053 case BFD_RELOC_ARM_GOT32
:
27054 case BFD_RELOC_ARM_GOTOFF
:
27057 case BFD_RELOC_ARM_GOT_PREL
:
27058 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27059 md_number_to_chars (buf
, value
, 4);
27062 case BFD_RELOC_ARM_TARGET2
:
27063 /* TARGET2 is not partial-inplace, so we need to write the
27064 addend here for REL targets, because it won't be written out
27065 during reloc processing later. */
27066 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27067 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
27070 /* Relocations for FDPIC. */
27071 case BFD_RELOC_ARM_GOTFUNCDESC
:
27072 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
27073 case BFD_RELOC_ARM_FUNCDESC
:
27076 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27077 md_number_to_chars (buf
, 0, 4);
27081 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27082 _("Relocation supported only in FDPIC mode"));
27087 case BFD_RELOC_RVA
:
27089 case BFD_RELOC_ARM_TARGET1
:
27090 case BFD_RELOC_ARM_ROSEGREL32
:
27091 case BFD_RELOC_ARM_SBREL32
:
27092 case BFD_RELOC_32_PCREL
:
27094 case BFD_RELOC_32_SECREL
:
27096 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27098 /* For WinCE we only do this for pcrel fixups. */
27099 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
27101 md_number_to_chars (buf
, value
, 4);
27105 case BFD_RELOC_ARM_PREL31
:
27106 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27108 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
27109 if ((value
^ (value
>> 1)) & 0x40000000)
27111 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27112 _("rel31 relocation overflow"));
27114 newval
|= value
& 0x7fffffff;
27115 md_number_to_chars (buf
, newval
, 4);
27120 case BFD_RELOC_ARM_CP_OFF_IMM
:
27121 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
27122 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
27123 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
27124 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27126 newval
= get_thumb32_insn (buf
);
27127 if ((newval
& 0x0f200f00) == 0x0d000900)
27129 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
27130 has permitted values that are multiples of 2, in the range 0
27132 if (value
< -510 || value
> 510 || (value
& 1))
27133 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27134 _("co-processor offset out of range"));
27136 else if ((newval
& 0xfe001f80) == 0xec000f80)
27138 if (value
< -511 || value
> 512 || (value
& 3))
27139 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27140 _("co-processor offset out of range"));
27142 else if (value
< -1023 || value
> 1023 || (value
& 3))
27143 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27144 _("co-processor offset out of range"));
27149 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
27150 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
27151 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27153 newval
= get_thumb32_insn (buf
);
27156 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
27157 newval
&= 0xffffff80;
27159 newval
&= 0xffffff00;
27163 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
27164 newval
&= 0xff7fff80;
27166 newval
&= 0xff7fff00;
27167 if ((newval
& 0x0f200f00) == 0x0d000900)
27169 /* This is a fp16 vstr/vldr.
27171 It requires the immediate offset in the instruction is shifted
27172 left by 1 to be a half-word offset.
27174 Here, left shift by 1 first, and later right shift by 2
27175 should get the right offset. */
27178 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
27180 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
27181 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
27182 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27184 put_thumb32_insn (buf
, newval
);
27187 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
27188 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
27189 if (value
< -255 || value
> 255)
27190 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27191 _("co-processor offset out of range"));
27193 goto cp_off_common
;
27195 case BFD_RELOC_ARM_THUMB_OFFSET
:
27196 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27197 /* Exactly what ranges, and where the offset is inserted depends
27198 on the type of instruction, we can establish this from the
27200 switch (newval
>> 12)
27202 case 4: /* PC load. */
27203 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
27204 forced to zero for these loads; md_pcrel_from has already
27205 compensated for this. */
27207 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27208 _("invalid offset, target not word aligned (0x%08lX)"),
27209 (((unsigned long) fixP
->fx_frag
->fr_address
27210 + (unsigned long) fixP
->fx_where
) & ~3)
27211 + (unsigned long) value
);
27213 if (value
& ~0x3fc)
27214 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27215 _("invalid offset, value too big (0x%08lX)"),
27218 newval
|= value
>> 2;
27221 case 9: /* SP load/store. */
27222 if (value
& ~0x3fc)
27223 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27224 _("invalid offset, value too big (0x%08lX)"),
27226 newval
|= value
>> 2;
27229 case 6: /* Word load/store. */
27231 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27232 _("invalid offset, value too big (0x%08lX)"),
27234 newval
|= value
<< 4; /* 6 - 2. */
27237 case 7: /* Byte load/store. */
27239 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27240 _("invalid offset, value too big (0x%08lX)"),
27242 newval
|= value
<< 6;
27245 case 8: /* Halfword load/store. */
27247 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27248 _("invalid offset, value too big (0x%08lX)"),
27250 newval
|= value
<< 5; /* 6 - 1. */
27254 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27255 "Unable to process relocation for thumb opcode: %lx",
27256 (unsigned long) newval
);
27259 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27262 case BFD_RELOC_ARM_THUMB_ADD
:
27263 /* This is a complicated relocation, since we use it for all of
27264 the following immediate relocations:
27268 9bit ADD/SUB SP word-aligned
27269 10bit ADD PC/SP word-aligned
27271 The type of instruction being processed is encoded in the
27278 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27280 int rd
= (newval
>> 4) & 0xf;
27281 int rs
= newval
& 0xf;
27282 int subtract
= !!(newval
& 0x8000);
27284 /* Check for HI regs, only very restricted cases allowed:
27285 Adjusting SP, and using PC or SP to get an address. */
27286 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
27287 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
27288 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27289 _("invalid Hi register with immediate"));
27291 /* If value is negative, choose the opposite instruction. */
27295 subtract
= !subtract
;
27297 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27298 _("immediate value out of range"));
27303 if (value
& ~0x1fc)
27304 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27305 _("invalid immediate for stack address calculation"));
27306 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
27307 newval
|= value
>> 2;
27309 else if (rs
== REG_PC
|| rs
== REG_SP
)
27311 /* PR gas/18541. If the addition is for a defined symbol
27312 within range of an ADR instruction then accept it. */
27315 && fixP
->fx_addsy
!= NULL
)
27319 if (! S_IS_DEFINED (fixP
->fx_addsy
)
27320 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
27321 || S_IS_WEAK (fixP
->fx_addsy
))
27323 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27324 _("address calculation needs a strongly defined nearby symbol"));
27328 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27330 /* Round up to the next 4-byte boundary. */
27335 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
27339 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27340 _("symbol too far away"));
27350 if (subtract
|| value
& ~0x3fc)
27351 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27352 _("invalid immediate for address calculation (value = 0x%08lX)"),
27353 (unsigned long) (subtract
? - value
: value
));
27354 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
27356 newval
|= value
>> 2;
27361 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27362 _("immediate value out of range"));
27363 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
27364 newval
|= (rd
<< 8) | value
;
27369 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27370 _("immediate value out of range"));
27371 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
27372 newval
|= rd
| (rs
<< 3) | (value
<< 6);
27375 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27378 case BFD_RELOC_ARM_THUMB_IMM
:
27379 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27380 if (value
< 0 || value
> 255)
27381 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27382 _("invalid immediate: %ld is out of range"),
27385 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27388 case BFD_RELOC_ARM_THUMB_SHIFT
:
27389 /* 5bit shift value (0..32). LSL cannot take 32. */
27390 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
27391 temp
= newval
& 0xf800;
27392 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
27393 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27394 _("invalid shift value: %ld"), (long) value
);
27395 /* Shifts of zero must be encoded as LSL. */
27397 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
27398 /* Shifts of 32 are encoded as zero. */
27399 else if (value
== 32)
27401 newval
|= value
<< 6;
27402 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27405 case BFD_RELOC_VTABLE_INHERIT
:
27406 case BFD_RELOC_VTABLE_ENTRY
:
27410 case BFD_RELOC_ARM_MOVW
:
27411 case BFD_RELOC_ARM_MOVT
:
27412 case BFD_RELOC_ARM_THUMB_MOVW
:
27413 case BFD_RELOC_ARM_THUMB_MOVT
:
27414 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27416 /* REL format relocations are limited to a 16-bit addend. */
27417 if (!fixP
->fx_done
)
27419 if (value
< -0x8000 || value
> 0x7fff)
27420 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27421 _("offset out of range"));
27423 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
27424 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
27429 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
27430 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
27432 newval
= get_thumb32_insn (buf
);
27433 newval
&= 0xfbf08f00;
27434 newval
|= (value
& 0xf000) << 4;
27435 newval
|= (value
& 0x0800) << 15;
27436 newval
|= (value
& 0x0700) << 4;
27437 newval
|= (value
& 0x00ff);
27438 put_thumb32_insn (buf
, newval
);
27442 newval
= md_chars_to_number (buf
, 4);
27443 newval
&= 0xfff0f000;
27444 newval
|= value
& 0x0fff;
27445 newval
|= (value
& 0xf000) << 4;
27446 md_number_to_chars (buf
, newval
, 4);
27451 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
27452 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
27453 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
27454 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
27455 gas_assert (!fixP
->fx_done
);
27458 bfd_boolean is_mov
;
27459 bfd_vma encoded_addend
= value
;
27461 /* Check that addend can be encoded in instruction. */
27462 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
27463 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27464 _("the offset 0x%08lX is not representable"),
27465 (unsigned long) encoded_addend
);
27467 /* Extract the instruction. */
27468 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
27469 is_mov
= (insn
& 0xf800) == 0x2000;
27474 if (!seg
->use_rela_p
)
27475 insn
|= encoded_addend
;
27481 /* Extract the instruction. */
27482 /* Encoding is the following
27487 /* The following conditions must be true :
27492 rd
= (insn
>> 4) & 0xf;
27494 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
27495 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27496 _("Unable to process relocation for thumb opcode: %lx"),
27497 (unsigned long) insn
);
27499 /* Encode as ADD immediate8 thumb 1 code. */
27500 insn
= 0x3000 | (rd
<< 8);
27502 /* Place the encoded addend into the first 8 bits of the
27504 if (!seg
->use_rela_p
)
27505 insn
|= encoded_addend
;
27508 /* Update the instruction. */
27509 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
27513 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
27514 case BFD_RELOC_ARM_ALU_PC_G0
:
27515 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
27516 case BFD_RELOC_ARM_ALU_PC_G1
:
27517 case BFD_RELOC_ARM_ALU_PC_G2
:
27518 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
27519 case BFD_RELOC_ARM_ALU_SB_G0
:
27520 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
27521 case BFD_RELOC_ARM_ALU_SB_G1
:
27522 case BFD_RELOC_ARM_ALU_SB_G2
:
27523 gas_assert (!fixP
->fx_done
);
27524 if (!seg
->use_rela_p
)
27527 bfd_vma encoded_addend
;
27528 bfd_vma addend_abs
= llabs (value
);
27530 /* Check that the absolute value of the addend can be
27531 expressed as an 8-bit constant plus a rotation. */
27532 encoded_addend
= encode_arm_immediate (addend_abs
);
27533 if (encoded_addend
== (unsigned int) FAIL
)
27534 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27535 _("the offset 0x%08lX is not representable"),
27536 (unsigned long) addend_abs
);
27538 /* Extract the instruction. */
27539 insn
= md_chars_to_number (buf
, INSN_SIZE
);
27541 /* If the addend is positive, use an ADD instruction.
27542 Otherwise use a SUB. Take care not to destroy the S bit. */
27543 insn
&= 0xff1fffff;
27549 /* Place the encoded addend into the first 12 bits of the
27551 insn
&= 0xfffff000;
27552 insn
|= encoded_addend
;
27554 /* Update the instruction. */
27555 md_number_to_chars (buf
, insn
, INSN_SIZE
);
27559 case BFD_RELOC_ARM_LDR_PC_G0
:
27560 case BFD_RELOC_ARM_LDR_PC_G1
:
27561 case BFD_RELOC_ARM_LDR_PC_G2
:
27562 case BFD_RELOC_ARM_LDR_SB_G0
:
27563 case BFD_RELOC_ARM_LDR_SB_G1
:
27564 case BFD_RELOC_ARM_LDR_SB_G2
:
27565 gas_assert (!fixP
->fx_done
);
27566 if (!seg
->use_rela_p
)
27569 bfd_vma addend_abs
= llabs (value
);
27571 /* Check that the absolute value of the addend can be
27572 encoded in 12 bits. */
27573 if (addend_abs
>= 0x1000)
27574 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27575 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
27576 (unsigned long) addend_abs
);
27578 /* Extract the instruction. */
27579 insn
= md_chars_to_number (buf
, INSN_SIZE
);
27581 /* If the addend is negative, clear bit 23 of the instruction.
27582 Otherwise set it. */
27584 insn
&= ~(1 << 23);
27588 /* Place the absolute value of the addend into the first 12 bits
27589 of the instruction. */
27590 insn
&= 0xfffff000;
27591 insn
|= addend_abs
;
27593 /* Update the instruction. */
27594 md_number_to_chars (buf
, insn
, INSN_SIZE
);
27598 case BFD_RELOC_ARM_LDRS_PC_G0
:
27599 case BFD_RELOC_ARM_LDRS_PC_G1
:
27600 case BFD_RELOC_ARM_LDRS_PC_G2
:
27601 case BFD_RELOC_ARM_LDRS_SB_G0
:
27602 case BFD_RELOC_ARM_LDRS_SB_G1
:
27603 case BFD_RELOC_ARM_LDRS_SB_G2
:
27604 gas_assert (!fixP
->fx_done
);
27605 if (!seg
->use_rela_p
)
27608 bfd_vma addend_abs
= llabs (value
);
27610 /* Check that the absolute value of the addend can be
27611 encoded in 8 bits. */
27612 if (addend_abs
>= 0x100)
27613 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27614 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
27615 (unsigned long) addend_abs
);
27617 /* Extract the instruction. */
27618 insn
= md_chars_to_number (buf
, INSN_SIZE
);
27620 /* If the addend is negative, clear bit 23 of the instruction.
27621 Otherwise set it. */
27623 insn
&= ~(1 << 23);
27627 /* Place the first four bits of the absolute value of the addend
27628 into the first 4 bits of the instruction, and the remaining
27629 four into bits 8 .. 11. */
27630 insn
&= 0xfffff0f0;
27631 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
27633 /* Update the instruction. */
27634 md_number_to_chars (buf
, insn
, INSN_SIZE
);
27638 case BFD_RELOC_ARM_LDC_PC_G0
:
27639 case BFD_RELOC_ARM_LDC_PC_G1
:
27640 case BFD_RELOC_ARM_LDC_PC_G2
:
27641 case BFD_RELOC_ARM_LDC_SB_G0
:
27642 case BFD_RELOC_ARM_LDC_SB_G1
:
27643 case BFD_RELOC_ARM_LDC_SB_G2
:
27644 gas_assert (!fixP
->fx_done
);
27645 if (!seg
->use_rela_p
)
27648 bfd_vma addend_abs
= llabs (value
);
27650 /* Check that the absolute value of the addend is a multiple of
27651 four and, when divided by four, fits in 8 bits. */
27652 if (addend_abs
& 0x3)
27653 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27654 _("bad offset 0x%08lX (must be word-aligned)"),
27655 (unsigned long) addend_abs
);
27657 if ((addend_abs
>> 2) > 0xff)
27658 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27659 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
27660 (unsigned long) addend_abs
);
27662 /* Extract the instruction. */
27663 insn
= md_chars_to_number (buf
, INSN_SIZE
);
27665 /* If the addend is negative, clear bit 23 of the instruction.
27666 Otherwise set it. */
27668 insn
&= ~(1 << 23);
27672 /* Place the addend (divided by four) into the first eight
27673 bits of the instruction. */
27674 insn
&= 0xfffffff0;
27675 insn
|= addend_abs
>> 2;
27677 /* Update the instruction. */
27678 md_number_to_chars (buf
, insn
, INSN_SIZE
);
27682 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
27684 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27685 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27686 && ARM_IS_FUNC (fixP
->fx_addsy
)
27687 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
27689 /* Force a relocation for a branch 5 bits wide. */
27692 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
27693 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27696 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27698 addressT boff
= value
>> 1;
27700 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27701 newval
|= (boff
<< 7);
27702 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27706 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
27708 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27709 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27710 && ARM_IS_FUNC (fixP
->fx_addsy
)
27711 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
27715 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
27716 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27717 _("branch out of range"));
27719 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27721 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27723 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
27724 addressT diff
= value
- boff
;
27728 newval
|= 1 << 1; /* T bit. */
27730 else if (diff
!= 2)
27732 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27733 _("out of range label-relative fixup value"));
27735 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27739 case BFD_RELOC_ARM_THUMB_BF17
:
27741 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27742 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27743 && ARM_IS_FUNC (fixP
->fx_addsy
)
27744 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
27746 /* Force a relocation for a branch 17 bits wide. */
27750 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
27751 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27754 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27757 addressT immA
, immB
, immC
;
27759 immA
= (value
& 0x0001f000) >> 12;
27760 immB
= (value
& 0x00000ffc) >> 2;
27761 immC
= (value
& 0x00000002) >> 1;
27763 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27764 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27766 newval2
|= (immC
<< 11) | (immB
<< 1);
27767 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27768 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27772 case BFD_RELOC_ARM_THUMB_BF19
:
27774 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27775 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27776 && ARM_IS_FUNC (fixP
->fx_addsy
)
27777 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
27779 /* Force a relocation for a branch 19 bits wide. */
27783 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
27784 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27787 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27790 addressT immA
, immB
, immC
;
27792 immA
= (value
& 0x0007f000) >> 12;
27793 immB
= (value
& 0x00000ffc) >> 2;
27794 immC
= (value
& 0x00000002) >> 1;
27796 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27797 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27799 newval2
|= (immC
<< 11) | (immB
<< 1);
27800 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27801 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27805 case BFD_RELOC_ARM_THUMB_BF13
:
27807 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27808 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27809 && ARM_IS_FUNC (fixP
->fx_addsy
)
27810 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
27812 /* Force a relocation for a branch 13 bits wide. */
27816 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
27817 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27820 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27823 addressT immA
, immB
, immC
;
27825 immA
= (value
& 0x00001000) >> 12;
27826 immB
= (value
& 0x00000ffc) >> 2;
27827 immC
= (value
& 0x00000002) >> 1;
27829 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27830 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27832 newval2
|= (immC
<< 11) | (immB
<< 1);
27833 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27834 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27838 case BFD_RELOC_ARM_THUMB_LOOP12
:
27840 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27841 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27842 && ARM_IS_FUNC (fixP
->fx_addsy
)
27843 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
27845 /* Force a relocation for a branch 12 bits wide. */
27849 bfd_vma insn
= get_thumb32_insn (buf
);
27850 /* le lr, <label> or le <label> */
27851 if (((insn
& 0xffffffff) == 0xf00fc001)
27852 || ((insn
& 0xffffffff) == 0xf02fc001))
27855 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
27856 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27858 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27860 addressT imml
, immh
;
27862 immh
= (value
& 0x00000ffc) >> 2;
27863 imml
= (value
& 0x00000002) >> 1;
27865 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27866 newval
|= (imml
<< 11) | (immh
<< 1);
27867 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
27871 case BFD_RELOC_ARM_V4BX
:
27872 /* This will need to go in the object file. */
27876 case BFD_RELOC_UNUSED
:
27878 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27879 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
27883 /* Translate internal representation of relocation info to BFD target
27887 tc_gen_reloc (asection
*section
, fixS
*fixp
)
27890 bfd_reloc_code_real_type code
;
27892 reloc
= XNEW (arelent
);
27894 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
27895 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
27896 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
27898 if (fixp
->fx_pcrel
)
27900 if (section
->use_rela_p
)
27901 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
27903 fixp
->fx_offset
= reloc
->address
;
27905 reloc
->addend
= fixp
->fx_offset
;
27907 switch (fixp
->fx_r_type
)
27910 if (fixp
->fx_pcrel
)
27912 code
= BFD_RELOC_8_PCREL
;
27915 /* Fall through. */
27918 if (fixp
->fx_pcrel
)
27920 code
= BFD_RELOC_16_PCREL
;
27923 /* Fall through. */
27926 if (fixp
->fx_pcrel
)
27928 code
= BFD_RELOC_32_PCREL
;
27931 /* Fall through. */
27933 case BFD_RELOC_ARM_MOVW
:
27934 if (fixp
->fx_pcrel
)
27936 code
= BFD_RELOC_ARM_MOVW_PCREL
;
27939 /* Fall through. */
27941 case BFD_RELOC_ARM_MOVT
:
27942 if (fixp
->fx_pcrel
)
27944 code
= BFD_RELOC_ARM_MOVT_PCREL
;
27947 /* Fall through. */
27949 case BFD_RELOC_ARM_THUMB_MOVW
:
27950 if (fixp
->fx_pcrel
)
27952 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
27955 /* Fall through. */
27957 case BFD_RELOC_ARM_THUMB_MOVT
:
27958 if (fixp
->fx_pcrel
)
27960 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
27963 /* Fall through. */
27965 case BFD_RELOC_NONE
:
27966 case BFD_RELOC_ARM_PCREL_BRANCH
:
27967 case BFD_RELOC_ARM_PCREL_BLX
:
27968 case BFD_RELOC_RVA
:
27969 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
27970 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
27971 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
27972 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27973 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27974 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27975 case BFD_RELOC_VTABLE_ENTRY
:
27976 case BFD_RELOC_VTABLE_INHERIT
:
27978 case BFD_RELOC_32_SECREL
:
27980 code
= fixp
->fx_r_type
;
27983 case BFD_RELOC_THUMB_PCREL_BLX
:
27985 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
27986 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
27989 code
= BFD_RELOC_THUMB_PCREL_BLX
;
27992 case BFD_RELOC_ARM_LITERAL
:
27993 case BFD_RELOC_ARM_HWLITERAL
:
27994 /* If this is called then the a literal has
27995 been referenced across a section boundary. */
27996 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27997 _("literal referenced across section boundary"));
28001 case BFD_RELOC_ARM_TLS_CALL
:
28002 case BFD_RELOC_ARM_THM_TLS_CALL
:
28003 case BFD_RELOC_ARM_TLS_DESCSEQ
:
28004 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
28005 case BFD_RELOC_ARM_GOT32
:
28006 case BFD_RELOC_ARM_GOTOFF
:
28007 case BFD_RELOC_ARM_GOT_PREL
:
28008 case BFD_RELOC_ARM_PLT32
:
28009 case BFD_RELOC_ARM_TARGET1
:
28010 case BFD_RELOC_ARM_ROSEGREL32
:
28011 case BFD_RELOC_ARM_SBREL32
:
28012 case BFD_RELOC_ARM_PREL31
:
28013 case BFD_RELOC_ARM_TARGET2
:
28014 case BFD_RELOC_ARM_TLS_LDO32
:
28015 case BFD_RELOC_ARM_PCREL_CALL
:
28016 case BFD_RELOC_ARM_PCREL_JUMP
:
28017 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
28018 case BFD_RELOC_ARM_ALU_PC_G0
:
28019 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
28020 case BFD_RELOC_ARM_ALU_PC_G1
:
28021 case BFD_RELOC_ARM_ALU_PC_G2
:
28022 case BFD_RELOC_ARM_LDR_PC_G0
:
28023 case BFD_RELOC_ARM_LDR_PC_G1
:
28024 case BFD_RELOC_ARM_LDR_PC_G2
:
28025 case BFD_RELOC_ARM_LDRS_PC_G0
:
28026 case BFD_RELOC_ARM_LDRS_PC_G1
:
28027 case BFD_RELOC_ARM_LDRS_PC_G2
:
28028 case BFD_RELOC_ARM_LDC_PC_G0
:
28029 case BFD_RELOC_ARM_LDC_PC_G1
:
28030 case BFD_RELOC_ARM_LDC_PC_G2
:
28031 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
28032 case BFD_RELOC_ARM_ALU_SB_G0
:
28033 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
28034 case BFD_RELOC_ARM_ALU_SB_G1
:
28035 case BFD_RELOC_ARM_ALU_SB_G2
:
28036 case BFD_RELOC_ARM_LDR_SB_G0
:
28037 case BFD_RELOC_ARM_LDR_SB_G1
:
28038 case BFD_RELOC_ARM_LDR_SB_G2
:
28039 case BFD_RELOC_ARM_LDRS_SB_G0
:
28040 case BFD_RELOC_ARM_LDRS_SB_G1
:
28041 case BFD_RELOC_ARM_LDRS_SB_G2
:
28042 case BFD_RELOC_ARM_LDC_SB_G0
:
28043 case BFD_RELOC_ARM_LDC_SB_G1
:
28044 case BFD_RELOC_ARM_LDC_SB_G2
:
28045 case BFD_RELOC_ARM_V4BX
:
28046 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
28047 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
28048 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
28049 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
28050 case BFD_RELOC_ARM_GOTFUNCDESC
:
28051 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
28052 case BFD_RELOC_ARM_FUNCDESC
:
28053 case BFD_RELOC_ARM_THUMB_BF17
:
28054 case BFD_RELOC_ARM_THUMB_BF19
:
28055 case BFD_RELOC_ARM_THUMB_BF13
:
28056 code
= fixp
->fx_r_type
;
28059 case BFD_RELOC_ARM_TLS_GOTDESC
:
28060 case BFD_RELOC_ARM_TLS_GD32
:
28061 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
28062 case BFD_RELOC_ARM_TLS_LE32
:
28063 case BFD_RELOC_ARM_TLS_IE32
:
28064 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
28065 case BFD_RELOC_ARM_TLS_LDM32
:
28066 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
28067 /* BFD will include the symbol's address in the addend.
28068 But we don't want that, so subtract it out again here. */
28069 if (!S_IS_COMMON (fixp
->fx_addsy
))
28070 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
28071 code
= fixp
->fx_r_type
;
28075 case BFD_RELOC_ARM_IMMEDIATE
:
28076 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28077 _("internal relocation (type: IMMEDIATE) not fixed up"));
28080 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
28081 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28082 _("ADRL used for a symbol not defined in the same file"));
28085 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
28086 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
28087 case BFD_RELOC_ARM_THUMB_LOOP12
:
28088 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28089 _("%s used for a symbol not defined in the same file"),
28090 bfd_get_reloc_code_name (fixp
->fx_r_type
));
28093 case BFD_RELOC_ARM_OFFSET_IMM
:
28094 if (section
->use_rela_p
)
28096 code
= fixp
->fx_r_type
;
28100 if (fixp
->fx_addsy
!= NULL
28101 && !S_IS_DEFINED (fixp
->fx_addsy
)
28102 && S_IS_LOCAL (fixp
->fx_addsy
))
28104 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28105 _("undefined local label `%s'"),
28106 S_GET_NAME (fixp
->fx_addsy
));
28110 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28111 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
28118 switch (fixp
->fx_r_type
)
28120 case BFD_RELOC_NONE
: type
= "NONE"; break;
28121 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
28122 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
28123 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
28124 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
28125 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
28126 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
28127 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
28128 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
28129 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
28130 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
28131 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
28132 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
28133 default: type
= _("<unknown>"); break;
28135 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28136 _("cannot represent %s relocation in this object file format"),
28143 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
28145 && fixp
->fx_addsy
== GOT_symbol
)
28147 code
= BFD_RELOC_ARM_GOTPC
;
28148 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
28152 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
28154 if (reloc
->howto
== NULL
)
28156 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28157 _("cannot represent %s relocation in this object file format"),
28158 bfd_get_reloc_code_name (code
));
28162 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
28163 vtable entry to be used in the relocation's section offset. */
28164 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
28165 reloc
->address
= fixp
->fx_offset
;
28170 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
28173 cons_fix_new_arm (fragS
* frag
,
28177 bfd_reloc_code_real_type reloc
)
28182 FIXME: @@ Should look at CPU word size. */
28186 reloc
= BFD_RELOC_8
;
28189 reloc
= BFD_RELOC_16
;
28193 reloc
= BFD_RELOC_32
;
28196 reloc
= BFD_RELOC_64
;
28201 if (exp
->X_op
== O_secrel
)
28203 exp
->X_op
= O_symbol
;
28204 reloc
= BFD_RELOC_32_SECREL
;
28208 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
28211 #if defined (OBJ_COFF)
28213 arm_validate_fix (fixS
* fixP
)
28215 /* If the destination of the branch is a defined symbol which does not have
28216 the THUMB_FUNC attribute, then we must be calling a function which has
28217 the (interfacearm) attribute. We look for the Thumb entry point to that
28218 function and change the branch to refer to that function instead. */
28219 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
28220 && fixP
->fx_addsy
!= NULL
28221 && S_IS_DEFINED (fixP
->fx_addsy
)
28222 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
28224 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
28231 arm_force_relocation (struct fix
* fixp
)
28233 #if defined (OBJ_COFF) && defined (TE_PE)
28234 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
28238 /* In case we have a call or a branch to a function in ARM ISA mode from
28239 a thumb function or vice-versa force the relocation. These relocations
28240 are cleared off for some cores that might have blx and simple transformations
28244 switch (fixp
->fx_r_type
)
28246 case BFD_RELOC_ARM_PCREL_JUMP
:
28247 case BFD_RELOC_ARM_PCREL_CALL
:
28248 case BFD_RELOC_THUMB_PCREL_BLX
:
28249 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
28253 case BFD_RELOC_ARM_PCREL_BLX
:
28254 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
28255 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
28256 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
28257 if (ARM_IS_FUNC (fixp
->fx_addsy
))
28266 /* Resolve these relocations even if the symbol is extern or weak.
28267 Technically this is probably wrong due to symbol preemption.
28268 In practice these relocations do not have enough range to be useful
28269 at dynamic link time, and some code (e.g. in the Linux kernel)
28270 expects these references to be resolved. */
28271 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
28272 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
28273 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
28274 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
28275 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
28276 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
28277 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
28278 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
28279 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
28280 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
28281 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
28282 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
28283 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
28284 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
28287 /* Always leave these relocations for the linker. */
28288 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
28289 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
28290 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
28293 /* Always generate relocations against function symbols. */
28294 if (fixp
->fx_r_type
== BFD_RELOC_32
28296 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
28299 return generic_force_reloc (fixp
);
28302 #if defined (OBJ_ELF) || defined (OBJ_COFF)
28303 /* Relocations against function names must be left unadjusted,
28304 so that the linker can use this information to generate interworking
28305 stubs. The MIPS version of this function
28306 also prevents relocations that are mips-16 specific, but I do not
28307 know why it does this.
28310 There is one other problem that ought to be addressed here, but
28311 which currently is not: Taking the address of a label (rather
28312 than a function) and then later jumping to that address. Such
28313 addresses also ought to have their bottom bit set (assuming that
28314 they reside in Thumb code), but at the moment they will not. */
28317 arm_fix_adjustable (fixS
* fixP
)
28319 if (fixP
->fx_addsy
== NULL
)
28322 /* Preserve relocations against symbols with function type. */
28323 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
28326 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
28327 && fixP
->fx_subsy
== NULL
)
28330 /* We need the symbol name for the VTABLE entries. */
28331 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
28332 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
28335 /* Don't allow symbols to be discarded on GOT related relocs. */
28336 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
28337 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
28338 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
28339 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
28340 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
28341 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
28342 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
28343 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
28344 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
28345 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
28346 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
28347 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
28348 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
28349 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
28350 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
28351 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
28352 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
28355 /* Similarly for group relocations. */
28356 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
28357 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
28358 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
28361 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
28362 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
28363 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
28364 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
28365 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
28366 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
28367 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
28368 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
28369 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
28372 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
28373 offsets, so keep these symbols. */
28374 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
28375 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
28380 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
28384 elf32_arm_target_format (void)
28387 return (target_big_endian
28388 ? "elf32-bigarm-symbian"
28389 : "elf32-littlearm-symbian");
28390 #elif defined (TE_VXWORKS)
28391 return (target_big_endian
28392 ? "elf32-bigarm-vxworks"
28393 : "elf32-littlearm-vxworks");
28394 #elif defined (TE_NACL)
28395 return (target_big_endian
28396 ? "elf32-bigarm-nacl"
28397 : "elf32-littlearm-nacl");
28401 if (target_big_endian
)
28402 return "elf32-bigarm-fdpic";
28404 return "elf32-littlearm-fdpic";
28408 if (target_big_endian
)
28409 return "elf32-bigarm";
28411 return "elf32-littlearm";
28417 armelf_frob_symbol (symbolS
* symp
,
28420 elf_frob_symbol (symp
, puntp
);
28424 /* MD interface: Finalization. */
28429 literal_pool
* pool
;
28431 /* Ensure that all the predication blocks are properly closed. */
28432 check_pred_blocks_finished ();
28434 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
28436 /* Put it at the end of the relevant section. */
28437 subseg_set (pool
->section
, pool
->sub_section
);
28439 arm_elf_change_section ();
28446 /* Remove any excess mapping symbols generated for alignment frags in
28447 SEC. We may have created a mapping symbol before a zero byte
28448 alignment; remove it if there's a mapping symbol after the
28451 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
28452 void *dummy ATTRIBUTE_UNUSED
)
28454 segment_info_type
*seginfo
= seg_info (sec
);
28457 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
28460 for (fragp
= seginfo
->frchainP
->frch_root
;
28462 fragp
= fragp
->fr_next
)
28464 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
28465 fragS
*next
= fragp
->fr_next
;
28467 /* Variable-sized frags have been converted to fixed size by
28468 this point. But if this was variable-sized to start with,
28469 there will be a fixed-size frag after it. So don't handle
28471 if (sym
== NULL
|| next
== NULL
)
28474 if (S_GET_VALUE (sym
) < next
->fr_address
)
28475 /* Not at the end of this frag. */
28477 know (S_GET_VALUE (sym
) == next
->fr_address
);
28481 if (next
->tc_frag_data
.first_map
!= NULL
)
28483 /* Next frag starts with a mapping symbol. Discard this
28485 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
28489 if (next
->fr_next
== NULL
)
28491 /* This mapping symbol is at the end of the section. Discard
28493 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
28494 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
28498 /* As long as we have empty frags without any mapping symbols,
28500 /* If the next frag is non-empty and does not start with a
28501 mapping symbol, then this mapping symbol is required. */
28502 if (next
->fr_address
!= next
->fr_next
->fr_address
)
28505 next
= next
->fr_next
;
28507 while (next
!= NULL
);
28512 /* Adjust the symbol table. This marks Thumb symbols as distinct from
28516 arm_adjust_symtab (void)
28521 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
28523 if (ARM_IS_THUMB (sym
))
28525 if (THUMB_IS_FUNC (sym
))
28527 /* Mark the symbol as a Thumb function. */
28528 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
28529 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
28530 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
28532 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
28533 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
28535 as_bad (_("%s: unexpected function type: %d"),
28536 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
28538 else switch (S_GET_STORAGE_CLASS (sym
))
28541 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
28544 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
28547 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
28555 if (ARM_IS_INTERWORK (sym
))
28556 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
28563 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
28565 if (ARM_IS_THUMB (sym
))
28567 elf_symbol_type
* elf_sym
;
28569 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
28570 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
28572 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
28573 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
28575 /* If it's a .thumb_func, declare it as so,
28576 otherwise tag label as .code 16. */
28577 if (THUMB_IS_FUNC (sym
))
28578 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
28579 ST_BRANCH_TO_THUMB
);
28580 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
28581 elf_sym
->internal_elf_sym
.st_info
=
28582 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
28587 /* Remove any overlapping mapping symbols generated by alignment frags. */
28588 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
28589 /* Now do generic ELF adjustments. */
28590 elf_adjust_symtab ();
28594 /* MD interface: Initialization. */
28597 set_constant_flonums (void)
28601 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
28602 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
28606 /* Auto-select Thumb mode if it's the only available instruction set for the
28607 given architecture. */
28610 autoselect_thumb_from_cpu_variant (void)
28612 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
28613 opcode_select (16);
28622 if ( (arm_ops_hsh
= hash_new ()) == NULL
28623 || (arm_cond_hsh
= hash_new ()) == NULL
28624 || (arm_vcond_hsh
= hash_new ()) == NULL
28625 || (arm_shift_hsh
= hash_new ()) == NULL
28626 || (arm_psr_hsh
= hash_new ()) == NULL
28627 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
28628 || (arm_reg_hsh
= hash_new ()) == NULL
28629 || (arm_reloc_hsh
= hash_new ()) == NULL
28630 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
28631 as_fatal (_("virtual memory exhausted"));
28633 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
28634 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
28635 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
28636 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
28637 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
28638 hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, (void *) (vconds
+ i
));
28639 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
28640 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
28641 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
28642 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
28643 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
28644 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
28645 (void *) (v7m_psrs
+ i
));
28646 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
28647 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
28649 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
28651 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
28652 (void *) (barrier_opt_names
+ i
));
28654 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
28656 struct reloc_entry
* entry
= reloc_names
+ i
;
28658 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
28659 /* This makes encode_branch() use the EABI versions of this relocation. */
28660 entry
->reloc
= BFD_RELOC_UNUSED
;
28662 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
28666 set_constant_flonums ();
28668 /* Set the cpu variant based on the command-line options. We prefer
28669 -mcpu= over -march= if both are set (as for GCC); and we prefer
28670 -mfpu= over any other way of setting the floating point unit.
28671 Use of legacy options with new options are faulted. */
28674 if (mcpu_cpu_opt
|| march_cpu_opt
)
28675 as_bad (_("use of old and new-style options to set CPU type"));
28677 selected_arch
= *legacy_cpu
;
28679 else if (mcpu_cpu_opt
)
28681 selected_arch
= *mcpu_cpu_opt
;
28682 selected_ext
= *mcpu_ext_opt
;
28684 else if (march_cpu_opt
)
28686 selected_arch
= *march_cpu_opt
;
28687 selected_ext
= *march_ext_opt
;
28689 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
28694 as_bad (_("use of old and new-style options to set FPU type"));
28696 selected_fpu
= *legacy_fpu
;
28699 selected_fpu
= *mfpu_opt
;
28702 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
28703 || defined (TE_NetBSD) || defined (TE_VXWORKS))
28704 /* Some environments specify a default FPU. If they don't, infer it
28705 from the processor. */
28707 selected_fpu
= *mcpu_fpu_opt
;
28708 else if (march_fpu_opt
)
28709 selected_fpu
= *march_fpu_opt
;
28711 selected_fpu
= fpu_default
;
28715 if (ARM_FEATURE_ZERO (selected_fpu
))
28717 if (!no_cpu_selected ())
28718 selected_fpu
= fpu_default
;
28720 selected_fpu
= fpu_arch_fpa
;
28724 if (ARM_FEATURE_ZERO (selected_arch
))
28726 selected_arch
= cpu_default
;
28727 selected_cpu
= selected_arch
;
28729 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
28731 /* Autodection of feature mode: allow all features in cpu_variant but leave
28732 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
28733 after all instruction have been processed and we can decide what CPU
28734 should be selected. */
28735 if (ARM_FEATURE_ZERO (selected_arch
))
28736 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
28738 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
28741 autoselect_thumb_from_cpu_variant ();
28743 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
28745 #if defined OBJ_COFF || defined OBJ_ELF
28747 unsigned int flags
= 0;
28749 #if defined OBJ_ELF
28750 flags
= meabi_flags
;
28752 switch (meabi_flags
)
28754 case EF_ARM_EABI_UNKNOWN
:
28756 /* Set the flags in the private structure. */
28757 if (uses_apcs_26
) flags
|= F_APCS26
;
28758 if (support_interwork
) flags
|= F_INTERWORK
;
28759 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
28760 if (pic_code
) flags
|= F_PIC
;
28761 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
28762 flags
|= F_SOFT_FLOAT
;
28764 switch (mfloat_abi_opt
)
28766 case ARM_FLOAT_ABI_SOFT
:
28767 case ARM_FLOAT_ABI_SOFTFP
:
28768 flags
|= F_SOFT_FLOAT
;
28771 case ARM_FLOAT_ABI_HARD
:
28772 if (flags
& F_SOFT_FLOAT
)
28773 as_bad (_("hard-float conflicts with specified fpu"));
28777 /* Using pure-endian doubles (even if soft-float). */
28778 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
28779 flags
|= F_VFP_FLOAT
;
28781 #if defined OBJ_ELF
28782 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
28783 flags
|= EF_ARM_MAVERICK_FLOAT
;
28786 case EF_ARM_EABI_VER4
:
28787 case EF_ARM_EABI_VER5
:
28788 /* No additional flags to set. */
28795 bfd_set_private_flags (stdoutput
, flags
);
28797 /* We have run out flags in the COFF header to encode the
28798 status of ATPCS support, so instead we create a dummy,
28799 empty, debug section called .arm.atpcs. */
28804 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
28808 bfd_set_section_flags
28809 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
28810 bfd_set_section_size (stdoutput
, sec
, 0);
28811 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
28817 /* Record the CPU type as well. */
28818 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
28819 mach
= bfd_mach_arm_iWMMXt2
;
28820 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
28821 mach
= bfd_mach_arm_iWMMXt
;
28822 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
28823 mach
= bfd_mach_arm_XScale
;
28824 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
28825 mach
= bfd_mach_arm_ep9312
;
28826 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
28827 mach
= bfd_mach_arm_5TE
;
28828 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
28830 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
28831 mach
= bfd_mach_arm_5T
;
28833 mach
= bfd_mach_arm_5
;
28835 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
28837 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
28838 mach
= bfd_mach_arm_4T
;
28840 mach
= bfd_mach_arm_4
;
28842 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
28843 mach
= bfd_mach_arm_3M
;
28844 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
28845 mach
= bfd_mach_arm_3
;
28846 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
28847 mach
= bfd_mach_arm_2a
;
28848 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
28849 mach
= bfd_mach_arm_2
;
28851 mach
= bfd_mach_arm_unknown
;
28853 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
28856 /* Command line processing. */
28859 Invocation line includes a switch not recognized by the base assembler.
28860 See if it's a processor-specific option.
28862 This routine is somewhat complicated by the need for backwards
28863 compatibility (since older releases of gcc can't be changed).
28864 The new options try to make the interface as compatible as
28867 New options (supported) are:
28869 -mcpu=<cpu name> Assemble for selected processor
28870 -march=<architecture name> Assemble for selected architecture
28871 -mfpu=<fpu architecture> Assemble for selected FPU.
28872 -EB/-mbig-endian Big-endian
28873 -EL/-mlittle-endian Little-endian
28874 -k Generate PIC code
28875 -mthumb Start in Thumb mode
28876 -mthumb-interwork Code supports ARM/Thumb interworking
28878 -m[no-]warn-deprecated Warn about deprecated features
28879 -m[no-]warn-syms Warn when symbols match instructions
28881 For now we will also provide support for:
28883 -mapcs-32 32-bit Program counter
28884 -mapcs-26 26-bit Program counter
28885 -macps-float Floats passed in FP registers
28886 -mapcs-reentrant Reentrant code
28888 (sometime these will probably be replaced with -mapcs=<list of options>
28889 and -matpcs=<list of options>)
28891 The remaining options are only supported for back-wards compatibility.
28892 Cpu variants, the arm part is optional:
28893 -m[arm]1 Currently not supported.
28894 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
28895 -m[arm]3 Arm 3 processor
28896 -m[arm]6[xx], Arm 6 processors
28897 -m[arm]7[xx][t][[d]m] Arm 7 processors
28898 -m[arm]8[10] Arm 8 processors
28899 -m[arm]9[20][tdmi] Arm 9 processors
28900 -mstrongarm[110[0]] StrongARM processors
28901 -mxscale XScale processors
28902 -m[arm]v[2345[t[e]]] Arm architectures
28903 -mall All (except the ARM1)
28905 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
28906 -mfpe-old (No float load/store multiples)
28907 -mvfpxd VFP Single precision
28909 -mno-fpu Disable all floating point instructions
28911 The following CPU names are recognized:
28912 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
28913 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
28914 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
28915 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
28916 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
28917 arm10t arm10e, arm1020t, arm1020e, arm10200e,
28918 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
28922 const char * md_shortopts
= "m:k";
28924 #ifdef ARM_BI_ENDIAN
28925 #define OPTION_EB (OPTION_MD_BASE + 0)
28926 #define OPTION_EL (OPTION_MD_BASE + 1)
28928 #if TARGET_BYTES_BIG_ENDIAN
28929 #define OPTION_EB (OPTION_MD_BASE + 0)
28931 #define OPTION_EL (OPTION_MD_BASE + 1)
28934 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
28935 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
28937 struct option md_longopts
[] =
28940 {"EB", no_argument
, NULL
, OPTION_EB
},
28943 {"EL", no_argument
, NULL
, OPTION_EL
},
28945 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
28947 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
28949 {NULL
, no_argument
, NULL
, 0}
28952 size_t md_longopts_size
= sizeof (md_longopts
);
28954 struct arm_option_table
28956 const char * option
; /* Option name to match. */
28957 const char * help
; /* Help information. */
28958 int * var
; /* Variable to change. */
28959 int value
; /* What to change it to. */
28960 const char * deprecated
; /* If non-null, print this message. */
28963 struct arm_option_table arm_opts
[] =
28965 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
28966 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
28967 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
28968 &support_interwork
, 1, NULL
},
28969 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
28970 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
28971 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
28973 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
28974 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
28975 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
28976 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
28979 /* These are recognized by the assembler, but have no affect on code. */
28980 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
28981 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
28983 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
28984 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
28985 &warn_on_deprecated
, 0, NULL
},
28986 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
28987 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
28988 {NULL
, NULL
, NULL
, 0, NULL
}
28991 struct arm_legacy_option_table
28993 const char * option
; /* Option name to match. */
28994 const arm_feature_set
** var
; /* Variable to change. */
28995 const arm_feature_set value
; /* What to change it to. */
28996 const char * deprecated
; /* If non-null, print this message. */
28999 const struct arm_legacy_option_table arm_legacy_opts
[] =
29001 /* DON'T add any new processors to this list -- we want the whole list
29002 to go away... Add them to the processors table instead. */
29003 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
29004 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
29005 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
29006 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
29007 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
29008 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
29009 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
29010 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
29011 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
29012 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
29013 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
29014 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
29015 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
29016 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
29017 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
29018 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
29019 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
29020 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
29021 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
29022 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
29023 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
29024 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
29025 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
29026 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
29027 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
29028 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
29029 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
29030 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
29031 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
29032 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
29033 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
29034 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
29035 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
29036 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
29037 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
29038 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
29039 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
29040 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
29041 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
29042 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
29043 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
29044 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
29045 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
29046 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
29047 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
29048 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
29049 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
29050 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
29051 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
29052 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
29053 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
29054 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
29055 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
29056 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
29057 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
29058 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
29059 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
29060 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
29061 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
29062 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
29063 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
29064 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
29065 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
29066 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
29067 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
29068 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
29069 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
29070 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
29071 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
29072 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
29073 N_("use -mcpu=strongarm110")},
29074 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
29075 N_("use -mcpu=strongarm1100")},
29076 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
29077 N_("use -mcpu=strongarm1110")},
29078 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
29079 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
29080 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
29082 /* Architecture variants -- don't add any more to this list either. */
29083 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
29084 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
29085 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
29086 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
29087 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
29088 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
29089 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
29090 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
29091 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
29092 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
29093 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
29094 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
29095 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
29096 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
29097 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
29098 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
29099 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
29100 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
29102 /* Floating point variants -- don't add any more to this list either. */
29103 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
29104 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
29105 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
29106 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
29107 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
29109 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
29112 struct arm_cpu_option_table
29116 const arm_feature_set value
;
29117 const arm_feature_set ext
;
29118 /* For some CPUs we assume an FPU unless the user explicitly sets
29120 const arm_feature_set default_fpu
;
29121 /* The canonical name of the CPU, or NULL to use NAME converted to upper
29123 const char * canonical_name
;
29126 /* This list should, at a minimum, contain all the cpu names
29127 recognized by GCC. */
29128 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
29130 static const struct arm_cpu_option_table arm_cpus
[] =
29132 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
29135 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
29138 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
29141 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
29144 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
29147 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
29150 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
29153 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
29156 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
29159 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
29162 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
29165 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
29168 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
29171 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
29174 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
29177 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
29180 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
29183 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
29186 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
29189 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
29192 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
29195 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
29198 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
29201 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
29204 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
29207 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
29210 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
29213 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
29216 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
29219 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
29222 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
29225 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
29228 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
29231 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
29234 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
29237 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
29240 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
29243 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
29246 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
29249 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
29252 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
29255 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
29258 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
29261 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
29264 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
29267 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
29271 /* For V5 or later processors we default to using VFP; but the user
29272 should really set the FPU type explicitly. */
29273 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
29276 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
29279 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
29282 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
29285 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
29288 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
29291 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
29294 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
29297 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
29300 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
29303 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
29306 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
29309 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
29312 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
29315 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
29318 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
29321 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
29324 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
29327 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
29330 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
29333 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
29336 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
29339 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
29342 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
29345 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
29348 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
29351 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
29354 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
29357 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
29360 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
29363 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
29366 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
29369 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
29372 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
29375 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
29378 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
29381 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
29382 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
29384 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
29386 FPU_ARCH_NEON_VFP_V4
),
29387 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
29388 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
29389 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
29390 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
29391 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
29392 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
29393 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
29395 FPU_ARCH_NEON_VFP_V4
),
29396 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
29398 FPU_ARCH_NEON_VFP_V4
),
29399 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
29401 FPU_ARCH_NEON_VFP_V4
),
29402 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
29403 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29404 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29405 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
29406 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29407 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29408 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
29409 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29410 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29411 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
29412 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
29413 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
29414 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
29415 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29416 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29417 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
29418 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29419 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29420 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
29421 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29422 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29423 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
29424 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
29425 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
29426 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
29427 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
29428 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
29429 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
29430 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
29431 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
29432 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
29435 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
29437 FPU_ARCH_VFP_V3D16
),
29438 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
29439 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
29441 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
29442 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
29443 FPU_ARCH_VFP_V3D16
),
29444 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
29445 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
29446 FPU_ARCH_VFP_V3D16
),
29447 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
29448 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29449 FPU_ARCH_NEON_VFP_ARMV8
),
29450 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
29451 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
29453 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
29456 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
29459 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
29462 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
29465 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
29468 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
29471 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
29474 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
29475 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29476 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29477 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
29478 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
29479 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
29480 /* ??? XSCALE is really an architecture. */
29481 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
29485 /* ??? iwmmxt is not a processor. */
29486 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
29489 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
29492 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
29497 ARM_CPU_OPT ("ep9312", "ARM920T",
29498 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
29499 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
29501 /* Marvell processors. */
29502 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
29503 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
29504 FPU_ARCH_VFP_V3D16
),
29505 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
29506 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
29507 FPU_ARCH_NEON_VFP_V4
),
29509 /* APM X-Gene family. */
29510 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
29512 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29513 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
29514 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29515 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29517 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
29521 struct arm_ext_table
29525 const arm_feature_set merge
;
29526 const arm_feature_set clear
;
29529 struct arm_arch_option_table
29533 const arm_feature_set value
;
29534 const arm_feature_set default_fpu
;
29535 const struct arm_ext_table
* ext_table
;
29538 /* Used to add support for +E and +noE extension. */
29539 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
29540 /* Used to add support for a +E extension. */
29541 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
29542 /* Used to add support for a +noE extension. */
29543 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
29545 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
29546 ~0 & ~FPU_ENDIAN_PURE)
29548 static const struct arm_ext_table armv5te_ext_table
[] =
29550 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
29551 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29554 static const struct arm_ext_table armv7_ext_table
[] =
29556 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
29557 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29560 static const struct arm_ext_table armv7ve_ext_table
[] =
29562 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
29563 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
29564 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
29565 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
29566 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
29567 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
29568 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
29570 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
29571 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
29573 /* Aliases for +simd. */
29574 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
29576 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
29577 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
29578 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
29580 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29583 static const struct arm_ext_table armv7a_ext_table
[] =
29585 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
29586 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
29587 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
29588 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
29589 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
29590 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
29591 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
29593 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
29594 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
29596 /* Aliases for +simd. */
29597 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
29598 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
29600 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
29601 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
29603 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
29604 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
29605 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29608 static const struct arm_ext_table armv7r_ext_table
[] =
29610 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
29611 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
29612 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
29613 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
29614 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
29615 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
29616 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
29617 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
29618 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29621 static const struct arm_ext_table armv7em_ext_table
[] =
29623 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
29624 /* Alias for +fp, used to be known as fpv4-sp-d16. */
29625 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
29626 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
29627 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
29628 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
29629 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29632 static const struct arm_ext_table armv8a_ext_table
[] =
29634 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
29635 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
29636 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
29637 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29639 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29640 should use the +simd option to turn on FP. */
29641 ARM_REMOVE ("fp", ALL_FP
),
29642 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
29643 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
29644 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29648 static const struct arm_ext_table armv81a_ext_table
[] =
29650 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
29651 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
29652 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29654 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29655 should use the +simd option to turn on FP. */
29656 ARM_REMOVE ("fp", ALL_FP
),
29657 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
29658 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
29659 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29662 static const struct arm_ext_table armv82a_ext_table
[] =
29664 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
29665 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
29666 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
29667 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
29668 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29669 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
29671 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29672 should use the +simd option to turn on FP. */
29673 ARM_REMOVE ("fp", ALL_FP
),
29674 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
29675 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
29676 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29679 static const struct arm_ext_table armv84a_ext_table
[] =
29681 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
29682 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
29683 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
29684 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29686 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29687 should use the +simd option to turn on FP. */
29688 ARM_REMOVE ("fp", ALL_FP
),
29689 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
29690 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
29691 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29694 static const struct arm_ext_table armv85a_ext_table
[] =
29696 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
29697 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
29698 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
29699 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29701 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29702 should use the +simd option to turn on FP. */
29703 ARM_REMOVE ("fp", ALL_FP
),
29704 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29707 static const struct arm_ext_table armv8m_main_ext_table
[] =
29709 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
29710 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
29711 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
29712 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
29713 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29716 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
29718 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
29719 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
29721 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
29722 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
29725 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
29726 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
29727 ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE
),
29728 ARM_FEATURE_COPROC (FPU_MVE
| FPU_MVE_FP
)),
29730 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
29731 FPU_MVE
| FPU_MVE_FP
| FPU_VFP_V5_SP_D16
|
29732 FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
29733 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29736 static const struct arm_ext_table armv8r_ext_table
[] =
29738 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
29739 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
29740 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
29741 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29742 ARM_REMOVE ("fp", ALL_FP
),
29743 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
29744 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29747 /* This list should, at a minimum, contain all the architecture names
29748 recognized by GCC. */
29749 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
29750 #define ARM_ARCH_OPT2(N, V, DF, ext) \
29751 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
29753 static const struct arm_arch_option_table arm_archs
[] =
29755 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
29756 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
29757 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
29758 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
29759 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
29760 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
29761 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
29762 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
29763 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
29764 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
29765 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
29766 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
29767 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
29768 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
29769 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
29770 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
29771 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
29772 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
29773 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
29774 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
29775 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
29776 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
29777 kept to preserve existing behaviour. */
29778 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
29779 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
29780 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
29781 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
29782 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
29783 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
29784 kept to preserve existing behaviour. */
29785 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
29786 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
29787 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
29788 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
29789 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
29790 /* The official spelling of the ARMv7 profile variants is the dashed form.
29791 Accept the non-dashed form for compatibility with old toolchains. */
29792 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
29793 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
29794 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
29795 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
29796 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
29797 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
29798 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
29799 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
29800 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
29801 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
29803 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
29805 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
29806 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
29807 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
29808 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
29809 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
29810 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
29811 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
29812 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
29813 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
29814 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
29815 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
29817 #undef ARM_ARCH_OPT
29819 /* ISA extensions in the co-processor and main instruction set space. */
29821 struct arm_option_extension_value_table
29825 const arm_feature_set merge_value
;
29826 const arm_feature_set clear_value
;
29827 /* List of architectures for which an extension is available. ARM_ARCH_NONE
29828 indicates that an extension is available for all architectures while
29829 ARM_ANY marks an empty entry. */
29830 const arm_feature_set allowed_archs
[2];
29833 /* The following table must be in alphabetical order with a NULL last entry. */
29835 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
29836 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
29838 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
29839 use the context sensitive approach using arm_ext_table's. */
29840 static const struct arm_option_extension_value_table arm_extensions
[] =
29842 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29843 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
29844 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
29845 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
29846 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
29847 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
29848 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
29850 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
29851 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
29852 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
29853 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
29854 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
29855 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
29856 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
29858 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
29859 | ARM_EXT2_FP16_FML
),
29860 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
29861 | ARM_EXT2_FP16_FML
),
29863 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
29864 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
29865 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
29866 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
29867 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
29868 Thumb divide instruction. Due to this having the same name as the
29869 previous entry, this will be ignored when doing command-line parsing and
29870 only considered by build attribute selection code. */
29871 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
29872 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
29873 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
29874 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
29875 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
29876 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
29877 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
29878 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
29879 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
29880 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
29881 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
29882 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
29883 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
29884 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
29885 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
29886 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
29887 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
29888 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
29889 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
29890 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
29891 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
29893 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
29894 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
29895 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
29896 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
29897 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
29898 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
29899 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
29900 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
29902 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
29903 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
29904 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
29905 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
29906 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
29907 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
29908 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
29909 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
29911 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
29912 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
29913 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
29914 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
29915 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
29919 /* ISA floating-point and Advanced SIMD extensions. */
29920 struct arm_option_fpu_value_table
29923 const arm_feature_set value
;
29926 /* This list should, at a minimum, contain all the fpu names
29927 recognized by GCC. */
29928 static const struct arm_option_fpu_value_table arm_fpus
[] =
29930 {"softfpa", FPU_NONE
},
29931 {"fpe", FPU_ARCH_FPE
},
29932 {"fpe2", FPU_ARCH_FPE
},
29933 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
29934 {"fpa", FPU_ARCH_FPA
},
29935 {"fpa10", FPU_ARCH_FPA
},
29936 {"fpa11", FPU_ARCH_FPA
},
29937 {"arm7500fe", FPU_ARCH_FPA
},
29938 {"softvfp", FPU_ARCH_VFP
},
29939 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
29940 {"vfp", FPU_ARCH_VFP_V2
},
29941 {"vfp9", FPU_ARCH_VFP_V2
},
29942 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
29943 {"vfp10", FPU_ARCH_VFP_V2
},
29944 {"vfp10-r0", FPU_ARCH_VFP_V1
},
29945 {"vfpxd", FPU_ARCH_VFP_V1xD
},
29946 {"vfpv2", FPU_ARCH_VFP_V2
},
29947 {"vfpv3", FPU_ARCH_VFP_V3
},
29948 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
29949 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
29950 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
29951 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
29952 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
29953 {"arm1020t", FPU_ARCH_VFP_V1
},
29954 {"arm1020e", FPU_ARCH_VFP_V2
},
29955 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
29956 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
29957 {"maverick", FPU_ARCH_MAVERICK
},
29958 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
29959 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
29960 {"neon-fp16", FPU_ARCH_NEON_FP16
},
29961 {"vfpv4", FPU_ARCH_VFP_V4
},
29962 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
29963 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
29964 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
29965 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
29966 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
29967 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
29968 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
29969 {"crypto-neon-fp-armv8",
29970 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
29971 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
29972 {"crypto-neon-fp-armv8.1",
29973 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
29974 {NULL
, ARM_ARCH_NONE
}
29977 struct arm_option_value_table
29983 static const struct arm_option_value_table arm_float_abis
[] =
29985 {"hard", ARM_FLOAT_ABI_HARD
},
29986 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
29987 {"soft", ARM_FLOAT_ABI_SOFT
},
29992 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
29993 static const struct arm_option_value_table arm_eabis
[] =
29995 {"gnu", EF_ARM_EABI_UNKNOWN
},
29996 {"4", EF_ARM_EABI_VER4
},
29997 {"5", EF_ARM_EABI_VER5
},
30002 struct arm_long_option_table
30004 const char * option
; /* Substring to match. */
30005 const char * help
; /* Help information. */
30006 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
30007 const char * deprecated
; /* If non-null, print this message. */
30011 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
30012 arm_feature_set
*ext_set
,
30013 const struct arm_ext_table
*ext_table
)
30015 /* We insist on extensions being specified in alphabetical order, and with
30016 extensions being added before being removed. We achieve this by having
30017 the global ARM_EXTENSIONS table in alphabetical order, and using the
30018 ADDING_VALUE variable to indicate whether we are adding an extension (1)
30019 or removing it (0) and only allowing it to change in the order
30021 const struct arm_option_extension_value_table
* opt
= NULL
;
30022 const arm_feature_set arm_any
= ARM_ANY
;
30023 int adding_value
= -1;
30025 while (str
!= NULL
&& *str
!= 0)
30032 as_bad (_("invalid architectural extension"));
30037 ext
= strchr (str
, '+');
30042 len
= strlen (str
);
30044 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
30046 if (adding_value
!= 0)
30049 opt
= arm_extensions
;
30057 if (adding_value
== -1)
30060 opt
= arm_extensions
;
30062 else if (adding_value
!= 1)
30064 as_bad (_("must specify extensions to add before specifying "
30065 "those to remove"));
30072 as_bad (_("missing architectural extension"));
30076 gas_assert (adding_value
!= -1);
30077 gas_assert (opt
!= NULL
);
30079 if (ext_table
!= NULL
)
30081 const struct arm_ext_table
* ext_opt
= ext_table
;
30082 bfd_boolean found
= FALSE
;
30083 for (; ext_opt
->name
!= NULL
; ext_opt
++)
30084 if (ext_opt
->name_len
== len
30085 && strncmp (ext_opt
->name
, str
, len
) == 0)
30089 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
30090 /* TODO: Option not supported. When we remove the
30091 legacy table this case should error out. */
30094 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
30098 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
30099 /* TODO: Option not supported. When we remove the
30100 legacy table this case should error out. */
30102 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
30114 /* Scan over the options table trying to find an exact match. */
30115 for (; opt
->name
!= NULL
; opt
++)
30116 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
30118 int i
, nb_allowed_archs
=
30119 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
30120 /* Check we can apply the extension to this architecture. */
30121 for (i
= 0; i
< nb_allowed_archs
; i
++)
30124 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
30126 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
30129 if (i
== nb_allowed_archs
)
30131 as_bad (_("extension does not apply to the base architecture"));
30135 /* Add or remove the extension. */
30137 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
30139 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
30141 /* Allowing Thumb division instructions for ARMv7 in autodetection
30142 rely on this break so that duplicate extensions (extensions
30143 with the same name as a previous extension in the list) are not
30144 considered for command-line parsing. */
30148 if (opt
->name
== NULL
)
30150 /* Did we fail to find an extension because it wasn't specified in
30151 alphabetical order, or because it does not exist? */
30153 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
30154 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
30157 if (opt
->name
== NULL
)
30158 as_bad (_("unknown architectural extension `%s'"), str
);
30160 as_bad (_("architectural extensions must be specified in "
30161 "alphabetical order"));
30167 /* We should skip the extension we've just matched the next time
30179 arm_parse_cpu (const char *str
)
30181 const struct arm_cpu_option_table
*opt
;
30182 const char *ext
= strchr (str
, '+');
30188 len
= strlen (str
);
30192 as_bad (_("missing cpu name `%s'"), str
);
30196 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
30197 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
30199 mcpu_cpu_opt
= &opt
->value
;
30200 if (mcpu_ext_opt
== NULL
)
30201 mcpu_ext_opt
= XNEW (arm_feature_set
);
30202 *mcpu_ext_opt
= opt
->ext
;
30203 mcpu_fpu_opt
= &opt
->default_fpu
;
30204 if (opt
->canonical_name
)
30206 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
30207 strcpy (selected_cpu_name
, opt
->canonical_name
);
30213 if (len
>= sizeof selected_cpu_name
)
30214 len
= (sizeof selected_cpu_name
) - 1;
30216 for (i
= 0; i
< len
; i
++)
30217 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
30218 selected_cpu_name
[i
] = 0;
30222 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
30227 as_bad (_("unknown cpu `%s'"), str
);
30232 arm_parse_arch (const char *str
)
30234 const struct arm_arch_option_table
*opt
;
30235 const char *ext
= strchr (str
, '+');
30241 len
= strlen (str
);
30245 as_bad (_("missing architecture name `%s'"), str
);
30249 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
30250 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
30252 march_cpu_opt
= &opt
->value
;
30253 if (march_ext_opt
== NULL
)
30254 march_ext_opt
= XNEW (arm_feature_set
);
30255 *march_ext_opt
= arm_arch_none
;
30256 march_fpu_opt
= &opt
->default_fpu
;
30257 strcpy (selected_cpu_name
, opt
->name
);
30260 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
30266 as_bad (_("unknown architecture `%s'\n"), str
);
30271 arm_parse_fpu (const char * str
)
30273 const struct arm_option_fpu_value_table
* opt
;
30275 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
30276 if (streq (opt
->name
, str
))
30278 mfpu_opt
= &opt
->value
;
30282 as_bad (_("unknown floating point format `%s'\n"), str
);
30287 arm_parse_float_abi (const char * str
)
30289 const struct arm_option_value_table
* opt
;
30291 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
30292 if (streq (opt
->name
, str
))
30294 mfloat_abi_opt
= opt
->value
;
30298 as_bad (_("unknown floating point abi `%s'\n"), str
);
30304 arm_parse_eabi (const char * str
)
30306 const struct arm_option_value_table
*opt
;
30308 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
30309 if (streq (opt
->name
, str
))
30311 meabi_flags
= opt
->value
;
30314 as_bad (_("unknown EABI `%s'\n"), str
);
30320 arm_parse_it_mode (const char * str
)
30322 bfd_boolean ret
= TRUE
;
30324 if (streq ("arm", str
))
30325 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
30326 else if (streq ("thumb", str
))
30327 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
30328 else if (streq ("always", str
))
30329 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
30330 else if (streq ("never", str
))
30331 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
30334 as_bad (_("unknown implicit IT mode `%s', should be "\
30335 "arm, thumb, always, or never."), str
);
30343 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
30345 codecomposer_syntax
= TRUE
;
30346 arm_comment_chars
[0] = ';';
30347 arm_line_separator_chars
[0] = 0;
30351 struct arm_long_option_table arm_long_opts
[] =
30353 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
30354 arm_parse_cpu
, NULL
},
30355 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
30356 arm_parse_arch
, NULL
},
30357 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
30358 arm_parse_fpu
, NULL
},
30359 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
30360 arm_parse_float_abi
, NULL
},
30362 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
30363 arm_parse_eabi
, NULL
},
30365 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
30366 arm_parse_it_mode
, NULL
},
30367 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
30368 arm_ccs_mode
, NULL
},
30369 {NULL
, NULL
, 0, NULL
}
30373 md_parse_option (int c
, const char * arg
)
30375 struct arm_option_table
*opt
;
30376 const struct arm_legacy_option_table
*fopt
;
30377 struct arm_long_option_table
*lopt
;
30383 target_big_endian
= 1;
30389 target_big_endian
= 0;
30393 case OPTION_FIX_V4BX
:
30401 #endif /* OBJ_ELF */
30404 /* Listing option. Just ignore these, we don't support additional
30409 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
30411 if (c
== opt
->option
[0]
30412 && ((arg
== NULL
&& opt
->option
[1] == 0)
30413 || streq (arg
, opt
->option
+ 1)))
30415 /* If the option is deprecated, tell the user. */
30416 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
30417 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
30418 arg
? arg
: "", _(opt
->deprecated
));
30420 if (opt
->var
!= NULL
)
30421 *opt
->var
= opt
->value
;
30427 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
30429 if (c
== fopt
->option
[0]
30430 && ((arg
== NULL
&& fopt
->option
[1] == 0)
30431 || streq (arg
, fopt
->option
+ 1)))
30433 /* If the option is deprecated, tell the user. */
30434 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
30435 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
30436 arg
? arg
: "", _(fopt
->deprecated
));
30438 if (fopt
->var
!= NULL
)
30439 *fopt
->var
= &fopt
->value
;
30445 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
30447 /* These options are expected to have an argument. */
30448 if (c
== lopt
->option
[0]
30450 && strncmp (arg
, lopt
->option
+ 1,
30451 strlen (lopt
->option
+ 1)) == 0)
30453 /* If the option is deprecated, tell the user. */
30454 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
30455 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
30456 _(lopt
->deprecated
));
30458 /* Call the sup-option parser. */
30459 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
30470 md_show_usage (FILE * fp
)
30472 struct arm_option_table
*opt
;
30473 struct arm_long_option_table
*lopt
;
30475 fprintf (fp
, _(" ARM-specific assembler options:\n"));
30477 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
30478 if (opt
->help
!= NULL
)
30479 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
30481 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
30482 if (lopt
->help
!= NULL
)
30483 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
30487 -EB assemble code for a big-endian cpu\n"));
30492 -EL assemble code for a little-endian cpu\n"));
30496 --fix-v4bx Allow BX in ARMv4 code\n"));
30500 --fdpic generate an FDPIC object file\n"));
30501 #endif /* OBJ_ELF */
30509 arm_feature_set flags
;
30510 } cpu_arch_ver_table
;
30512 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
30513 chronologically for architectures, with an exception for ARMv6-M and
30514 ARMv6S-M due to legacy reasons. No new architecture should have a
30515 special case. This allows for build attribute selection results to be
30516 stable when new architectures are added. */
30517 static const cpu_arch_ver_table cpu_arch_ver
[] =
30519 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
30520 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
30521 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
30522 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
30523 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
30524 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
30525 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
30526 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
30527 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
30528 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
30529 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
30530 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
30531 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
30532 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
30533 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
30534 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
30535 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
30536 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
30537 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
30538 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
30539 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
30540 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
30541 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
30542 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
30544 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
30545 always selected build attributes to match those of ARMv6-M
30546 (resp. ARMv6S-M). However, due to these architectures being a strict
30547 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
30548 would be selected when fully respecting chronology of architectures.
30549 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
30550 move them before ARMv7 architectures. */
30551 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
30552 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
30554 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
30555 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
30556 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
30557 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
30558 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
30559 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
30560 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
30561 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
30562 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
30563 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
30564 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
30565 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
30566 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
30567 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
30568 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
30569 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
30570 {-1, ARM_ARCH_NONE
}
30573 /* Set an attribute if it has not already been set by the user. */
30576 aeabi_set_attribute_int (int tag
, int value
)
30579 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
30580 || !attributes_set_explicitly
[tag
])
30581 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
30585 aeabi_set_attribute_string (int tag
, const char *value
)
30588 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
30589 || !attributes_set_explicitly
[tag
])
30590 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
30593 /* Return whether features in the *NEEDED feature set are available via
30594 extensions for the architecture whose feature set is *ARCH_FSET. */
30597 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
30598 const arm_feature_set
*needed
)
30600 int i
, nb_allowed_archs
;
30601 arm_feature_set ext_fset
;
30602 const struct arm_option_extension_value_table
*opt
;
30604 ext_fset
= arm_arch_none
;
30605 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
30607 /* Extension does not provide any feature we need. */
30608 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
30612 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
30613 for (i
= 0; i
< nb_allowed_archs
; i
++)
30616 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
30619 /* Extension is available, add it. */
30620 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
30621 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
30625 /* Can we enable all features in *needed? */
30626 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
30629 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
30630 a given architecture feature set *ARCH_EXT_FSET including extension feature
30631 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
30632 - if true, check for an exact match of the architecture modulo extensions;
30633 - otherwise, select build attribute value of the first superset
30634 architecture released so that results remains stable when new architectures
30636 For -march/-mcpu=all the build attribute value of the most featureful
30637 architecture is returned. Tag_CPU_arch_profile result is returned in
30641 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
30642 const arm_feature_set
*ext_fset
,
30643 char *profile
, int exact_match
)
30645 arm_feature_set arch_fset
;
30646 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
30648 /* Select most featureful architecture with all its extensions if building
30649 for -march=all as the feature sets used to set build attributes. */
30650 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
30652 /* Force revisiting of decision for each new architecture. */
30653 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
30655 return TAG_CPU_ARCH_V8
;
30658 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
30660 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
30662 arm_feature_set known_arch_fset
;
30664 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
30667 /* Base architecture match user-specified architecture and
30668 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
30669 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
30674 /* Base architecture match user-specified architecture only
30675 (eg. ARMv6-M in the same case as above). Record it in case we
30676 find a match with above condition. */
30677 else if (p_ver_ret
== NULL
30678 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
30684 /* Architecture has all features wanted. */
30685 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
30687 arm_feature_set added_fset
;
30689 /* Compute features added by this architecture over the one
30690 recorded in p_ver_ret. */
30691 if (p_ver_ret
!= NULL
)
30692 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
30694 /* First architecture that match incl. with extensions, or the
30695 only difference in features over the recorded match is
30696 features that were optional and are now mandatory. */
30697 if (p_ver_ret
== NULL
30698 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
30704 else if (p_ver_ret
== NULL
)
30706 arm_feature_set needed_ext_fset
;
30708 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
30710 /* Architecture has all features needed when using some
30711 extensions. Record it and continue searching in case there
30712 exist an architecture providing all needed features without
30713 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
30715 if (have_ext_for_needed_feat_p (&known_arch_fset
,
30722 if (p_ver_ret
== NULL
)
30726 /* Tag_CPU_arch_profile. */
30727 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
30728 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
30729 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
30730 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
30732 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
30734 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
30738 return p_ver_ret
->val
;
30741 /* Set the public EABI object attributes. */
30744 aeabi_set_public_attributes (void)
30746 char profile
= '\0';
30749 int fp16_optional
= 0;
30750 int skip_exact_match
= 0;
30751 arm_feature_set flags
, flags_arch
, flags_ext
;
30753 /* Autodetection mode, choose the architecture based the instructions
30755 if (no_cpu_selected ())
30757 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
30759 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
30760 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
30762 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
30763 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
30765 /* Code run during relaxation relies on selected_cpu being set. */
30766 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
30767 flags_ext
= arm_arch_none
;
30768 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
30769 selected_ext
= flags_ext
;
30770 selected_cpu
= flags
;
30772 /* Otherwise, choose the architecture based on the capabilities of the
30776 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
30777 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
30778 flags_ext
= selected_ext
;
30779 flags
= selected_cpu
;
30781 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
30783 /* Allow the user to override the reported architecture. */
30784 if (!ARM_FEATURE_ZERO (selected_object_arch
))
30786 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
30787 flags_ext
= arm_arch_none
;
30790 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
30792 /* When this function is run again after relaxation has happened there is no
30793 way to determine whether an architecture or CPU was specified by the user:
30794 - selected_cpu is set above for relaxation to work;
30795 - march_cpu_opt is not set if only -mcpu or .cpu is used;
30796 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
30797 Therefore, if not in -march=all case we first try an exact match and fall
30798 back to autodetection. */
30799 if (!skip_exact_match
)
30800 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
30802 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
30804 as_bad (_("no architecture contains all the instructions used\n"));
30806 /* Tag_CPU_name. */
30807 if (selected_cpu_name
[0])
30811 q
= selected_cpu_name
;
30812 if (strncmp (q
, "armv", 4) == 0)
30817 for (i
= 0; q
[i
]; i
++)
30818 q
[i
] = TOUPPER (q
[i
]);
30820 aeabi_set_attribute_string (Tag_CPU_name
, q
);
30823 /* Tag_CPU_arch. */
30824 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
30826 /* Tag_CPU_arch_profile. */
30827 if (profile
!= '\0')
30828 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
30830 /* Tag_DSP_extension. */
30831 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
30832 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
30834 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
30835 /* Tag_ARM_ISA_use. */
30836 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
30837 || ARM_FEATURE_ZERO (flags_arch
))
30838 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
30840 /* Tag_THUMB_ISA_use. */
30841 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
30842 || ARM_FEATURE_ZERO (flags_arch
))
30846 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
30847 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
30849 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
30853 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
30856 /* Tag_VFP_arch. */
30857 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
30858 aeabi_set_attribute_int (Tag_VFP_arch
,
30859 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
30861 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
30862 aeabi_set_attribute_int (Tag_VFP_arch
,
30863 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
30865 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
30868 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
30870 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
30872 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
30875 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
30876 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
30877 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
30878 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
30879 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
30881 /* Tag_ABI_HardFP_use. */
30882 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
30883 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
30884 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
30886 /* Tag_WMMX_arch. */
30887 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
30888 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
30889 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
30890 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
30892 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
30893 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
30894 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
30895 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
30896 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
30897 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
30899 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
30901 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
30905 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
30910 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
30911 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
30912 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
30913 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
30915 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
30916 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
30917 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
30921 We set Tag_DIV_use to two when integer divide instructions have been used
30922 in ARM state, or when Thumb integer divide instructions have been used,
30923 but we have no architecture profile set, nor have we any ARM instructions.
30925 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
30926 by the base architecture.
30928 For new architectures we will have to check these tests. */
30929 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
30930 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
30931 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
30932 aeabi_set_attribute_int (Tag_DIV_use
, 0);
30933 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
30934 || (profile
== '\0'
30935 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
30936 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
30937 aeabi_set_attribute_int (Tag_DIV_use
, 2);
30939 /* Tag_MP_extension_use. */
30940 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
30941 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
30943 /* Tag Virtualization_use. */
30944 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
30946 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
30949 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
30952 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
30953 finished and free extension feature bits which will not be used anymore. */
30956 arm_md_post_relax (void)
30958 aeabi_set_public_attributes ();
30959 XDELETE (mcpu_ext_opt
);
30960 mcpu_ext_opt
= NULL
;
30961 XDELETE (march_ext_opt
);
30962 march_ext_opt
= NULL
;
30965 /* Add the default contents for the .ARM.attributes section. */
30970 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
30973 aeabi_set_public_attributes ();
30975 #endif /* OBJ_ELF */
30977 /* Parse a .cpu directive. */
30980 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
30982 const struct arm_cpu_option_table
*opt
;
30986 name
= input_line_pointer
;
30987 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
30988 input_line_pointer
++;
30989 saved_char
= *input_line_pointer
;
30990 *input_line_pointer
= 0;
30992 /* Skip the first "all" entry. */
30993 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
30994 if (streq (opt
->name
, name
))
30996 selected_arch
= opt
->value
;
30997 selected_ext
= opt
->ext
;
30998 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
30999 if (opt
->canonical_name
)
31000 strcpy (selected_cpu_name
, opt
->canonical_name
);
31004 for (i
= 0; opt
->name
[i
]; i
++)
31005 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
31007 selected_cpu_name
[i
] = 0;
31009 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
31011 *input_line_pointer
= saved_char
;
31012 demand_empty_rest_of_line ();
31015 as_bad (_("unknown cpu `%s'"), name
);
31016 *input_line_pointer
= saved_char
;
31017 ignore_rest_of_line ();
31020 /* Parse a .arch directive. */
31023 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
31025 const struct arm_arch_option_table
*opt
;
31029 name
= input_line_pointer
;
31030 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31031 input_line_pointer
++;
31032 saved_char
= *input_line_pointer
;
31033 *input_line_pointer
= 0;
31035 /* Skip the first "all" entry. */
31036 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
31037 if (streq (opt
->name
, name
))
31039 selected_arch
= opt
->value
;
31040 selected_ext
= arm_arch_none
;
31041 selected_cpu
= selected_arch
;
31042 strcpy (selected_cpu_name
, opt
->name
);
31043 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
31044 *input_line_pointer
= saved_char
;
31045 demand_empty_rest_of_line ();
31049 as_bad (_("unknown architecture `%s'\n"), name
);
31050 *input_line_pointer
= saved_char
;
31051 ignore_rest_of_line ();
31054 /* Parse a .object_arch directive. */
31057 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
31059 const struct arm_arch_option_table
*opt
;
31063 name
= input_line_pointer
;
31064 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31065 input_line_pointer
++;
31066 saved_char
= *input_line_pointer
;
31067 *input_line_pointer
= 0;
31069 /* Skip the first "all" entry. */
31070 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
31071 if (streq (opt
->name
, name
))
31073 selected_object_arch
= opt
->value
;
31074 *input_line_pointer
= saved_char
;
31075 demand_empty_rest_of_line ();
31079 as_bad (_("unknown architecture `%s'\n"), name
);
31080 *input_line_pointer
= saved_char
;
31081 ignore_rest_of_line ();
31084 /* Parse a .arch_extension directive. */
31087 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
31089 const struct arm_option_extension_value_table
*opt
;
31092 int adding_value
= 1;
31094 name
= input_line_pointer
;
31095 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31096 input_line_pointer
++;
31097 saved_char
= *input_line_pointer
;
31098 *input_line_pointer
= 0;
31100 if (strlen (name
) >= 2
31101 && strncmp (name
, "no", 2) == 0)
31107 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31108 if (streq (opt
->name
, name
))
31110 int i
, nb_allowed_archs
=
31111 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
31112 for (i
= 0; i
< nb_allowed_archs
; i
++)
31115 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
31117 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
31121 if (i
== nb_allowed_archs
)
31123 as_bad (_("architectural extension `%s' is not allowed for the "
31124 "current base architecture"), name
);
31129 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
31132 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
31134 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
31135 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
31136 *input_line_pointer
= saved_char
;
31137 demand_empty_rest_of_line ();
31138 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
31139 on this return so that duplicate extensions (extensions with the
31140 same name as a previous extension in the list) are not considered
31141 for command-line parsing. */
31145 if (opt
->name
== NULL
)
31146 as_bad (_("unknown architecture extension `%s'\n"), name
);
31148 *input_line_pointer
= saved_char
;
31149 ignore_rest_of_line ();
31152 /* Parse a .fpu directive. */
31155 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
31157 const struct arm_option_fpu_value_table
*opt
;
31161 name
= input_line_pointer
;
31162 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31163 input_line_pointer
++;
31164 saved_char
= *input_line_pointer
;
31165 *input_line_pointer
= 0;
31167 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
31168 if (streq (opt
->name
, name
))
31170 selected_fpu
= opt
->value
;
31171 #ifndef CPU_DEFAULT
31172 if (no_cpu_selected ())
31173 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
31176 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
31177 *input_line_pointer
= saved_char
;
31178 demand_empty_rest_of_line ();
31182 as_bad (_("unknown floating point format `%s'\n"), name
);
31183 *input_line_pointer
= saved_char
;
31184 ignore_rest_of_line ();
31187 /* Copy symbol information. */
31190 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
31192 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
31196 /* Given a symbolic attribute NAME, return the proper integer value.
31197 Returns -1 if the attribute is not known. */
31200 arm_convert_symbolic_attribute (const char *name
)
31202 static const struct
31207 attribute_table
[] =
31209 /* When you modify this table you should
31210 also modify the list in doc/c-arm.texi. */
31211 #define T(tag) {#tag, tag}
31212 T (Tag_CPU_raw_name
),
31215 T (Tag_CPU_arch_profile
),
31216 T (Tag_ARM_ISA_use
),
31217 T (Tag_THUMB_ISA_use
),
31221 T (Tag_Advanced_SIMD_arch
),
31222 T (Tag_PCS_config
),
31223 T (Tag_ABI_PCS_R9_use
),
31224 T (Tag_ABI_PCS_RW_data
),
31225 T (Tag_ABI_PCS_RO_data
),
31226 T (Tag_ABI_PCS_GOT_use
),
31227 T (Tag_ABI_PCS_wchar_t
),
31228 T (Tag_ABI_FP_rounding
),
31229 T (Tag_ABI_FP_denormal
),
31230 T (Tag_ABI_FP_exceptions
),
31231 T (Tag_ABI_FP_user_exceptions
),
31232 T (Tag_ABI_FP_number_model
),
31233 T (Tag_ABI_align_needed
),
31234 T (Tag_ABI_align8_needed
),
31235 T (Tag_ABI_align_preserved
),
31236 T (Tag_ABI_align8_preserved
),
31237 T (Tag_ABI_enum_size
),
31238 T (Tag_ABI_HardFP_use
),
31239 T (Tag_ABI_VFP_args
),
31240 T (Tag_ABI_WMMX_args
),
31241 T (Tag_ABI_optimization_goals
),
31242 T (Tag_ABI_FP_optimization_goals
),
31243 T (Tag_compatibility
),
31244 T (Tag_CPU_unaligned_access
),
31245 T (Tag_FP_HP_extension
),
31246 T (Tag_VFP_HP_extension
),
31247 T (Tag_ABI_FP_16bit_format
),
31248 T (Tag_MPextension_use
),
31250 T (Tag_nodefaults
),
31251 T (Tag_also_compatible_with
),
31252 T (Tag_conformance
),
31254 T (Tag_Virtualization_use
),
31255 T (Tag_DSP_extension
),
31257 /* We deliberately do not include Tag_MPextension_use_legacy. */
31265 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
31266 if (streq (name
, attribute_table
[i
].name
))
31267 return attribute_table
[i
].tag
;
31272 /* Apply sym value for relocations only in the case that they are for
31273 local symbols in the same segment as the fixup and you have the
31274 respective architectural feature for blx and simple switches. */
31277 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
31280 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
31281 /* PR 17444: If the local symbol is in a different section then a reloc
31282 will always be generated for it, so applying the symbol value now
31283 will result in a double offset being stored in the relocation. */
31284 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
31285 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
31287 switch (fixP
->fx_r_type
)
31289 case BFD_RELOC_ARM_PCREL_BLX
:
31290 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
31291 if (ARM_IS_FUNC (fixP
->fx_addsy
))
31295 case BFD_RELOC_ARM_PCREL_CALL
:
31296 case BFD_RELOC_THUMB_PCREL_BLX
:
31297 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
31308 #endif /* OBJ_ELF */