1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
5 Modified by David Taylor (dtaylor@armltd.co.uk)
7 This file is part of GAS, the GNU Assembler.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
21 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 /* Need TARGET_CPU. */
38 #include "dwarf2dbg.h"
41 /* Types of processor to assemble for. */
42 #define ARM_1 0x00000001
43 #define ARM_2 0x00000002
44 #define ARM_3 0x00000004
46 #define ARM_6 0x00000008
47 #define ARM_7 ARM_6 /* Same core instruction set. */
48 #define ARM_8 ARM_6 /* Same core instruction set. */
49 #define ARM_9 ARM_6 /* Same core instruction set. */
50 #define ARM_CPU_MASK 0x0000000f
52 /* The following bitmasks control CPU extensions (ARM7 onwards): */
53 #define ARM_EXT_LONGMUL 0x00000010 /* Allow long multiplies. */
54 #define ARM_EXT_HALFWORD 0x00000020 /* Allow half word loads. */
55 #define ARM_EXT_THUMB 0x00000040 /* Allow BX instruction. */
56 #define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */
57 #define ARM_EXT_V5E 0x00000100 /* "El Segundo". */
58 #define ARM_EXT_XSCALE 0x00000200 /* Allow MIA etc. */
60 /* Architectures are the sum of the base and extensions. */
61 #define ARM_ARCH_V3M ARM_EXT_LONGMUL
62 #define ARM_ARCH_V4 (ARM_ARCH_V3M | ARM_EXT_HALFWORD)
63 #define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_EXT_THUMB)
64 #define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5)
65 #define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_EXT_THUMB)
66 #define ARM_ARCH_V5TE (ARM_ARCH_V5T | ARM_EXT_V5E)
67 #define ARM_ARCH_XSCALE (ARM_ARCH_V5TE | ARM_EXT_XSCALE)
69 /* Some useful combinations: */
70 #define ARM_ANY 0x00ffffff
71 #define ARM_2UP (ARM_ANY - ARM_1)
72 #define ARM_ALL ARM_2UP /* Not arm1 only. */
73 #define ARM_3UP 0x00fffffc
74 #define ARM_6UP 0x00fffff8 /* Includes ARM7. */
76 #define FPU_CORE 0x80000000
77 #define FPU_FPA10 0x40000000
78 #define FPU_FPA11 0x40000000
81 /* Some useful combinations. */
82 #define FPU_ALL 0xff000000 /* Note this is ~ARM_ANY. */
83 #define FPU_MEMMULTI 0x7f000000 /* Not fpu_core. */
86 #if defined __XSCALE__
87 #define CPU_DEFAULT (ARM_9 | ARM_ARCH_XSCALE)
90 #define CPU_DEFAULT (ARM_7 | ARM_ARCH_V4T)
92 #define CPU_DEFAULT ARM_ALL
98 #define FPU_DEFAULT FPU_ALL
101 #define streq(a, b) (strcmp (a, b) == 0)
102 #define skip_whitespace(str) while (*(str) == ' ') ++(str)
104 static unsigned long cpu_variant
= CPU_DEFAULT
| FPU_DEFAULT
;
105 static int target_oabi
= 0;
107 #if defined OBJ_COFF || defined OBJ_ELF
108 /* Flags stored in private area of BFD structure. */
109 static boolean uses_apcs_26
= false;
110 static boolean atpcs
= false;
111 static boolean support_interwork
= false;
112 static boolean uses_apcs_float
= false;
113 static boolean pic_code
= false;
116 /* This array holds the chars that always start a comment. If the
117 pre-processor is disabled, these aren't very useful. */
118 CONST
char comment_chars
[] = "@";
120 /* This array holds the chars that only start a comment at the beginning of
121 a line. If the line seems to have the form '# 123 filename'
122 .line and .file directives will appear in the pre-processed output. */
123 /* Note that input_file.c hand checks for '#' at the beginning of the
124 first line of the input file. This is because the compiler outputs
125 #NO_APP at the beginning of its output. */
126 /* Also note that comments like this one will always work. */
127 CONST
char line_comment_chars
[] = "#";
129 CONST
char line_separator_chars
[] = ";";
131 /* Chars that can be used to separate mant
132 from exp in floating point numbers. */
133 CONST
char EXP_CHARS
[] = "eE";
135 /* Chars that mean this number is a floating point constant. */
139 CONST
char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
141 /* Prefix characters that indicate the start of an immediate
143 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
146 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
147 symbolS
* GOT_symbol
;
150 /* Size of relocation record. */
151 CONST
int md_reloc_size
= 8;
153 /* 0: assemble for ARM,
154 1: assemble for Thumb,
155 2: assemble for Thumb even though target CPU does not support thumb
157 static int thumb_mode
= 0;
159 typedef struct arm_fix
167 unsigned long instruction
;
172 bfd_reloc_code_real_type type
;
189 struct asm_shift_properties
191 enum asm_shift_index index
;
192 unsigned long bit_field
;
193 unsigned int allows_0
: 1;
194 unsigned int allows_32
: 1;
197 static const struct asm_shift_properties shift_properties
[] =
199 { SHIFT_LSL
, 0, 1, 0},
200 { SHIFT_LSR
, 0x20, 0, 1},
201 { SHIFT_ASR
, 0x40, 0, 1},
202 { SHIFT_ROR
, 0x60, 0, 0},
203 { SHIFT_RRX
, 0x60, 0, 0}
206 struct asm_shift_name
209 const struct asm_shift_properties
* properties
;
212 static const struct asm_shift_name shift_names
[] =
214 { "asl", shift_properties
+ SHIFT_LSL
},
215 { "lsl", shift_properties
+ SHIFT_LSL
},
216 { "lsr", shift_properties
+ SHIFT_LSR
},
217 { "asr", shift_properties
+ SHIFT_ASR
},
218 { "ror", shift_properties
+ SHIFT_ROR
},
219 { "rrx", shift_properties
+ SHIFT_RRX
},
220 { "ASL", shift_properties
+ SHIFT_LSL
},
221 { "LSL", shift_properties
+ SHIFT_LSL
},
222 { "LSR", shift_properties
+ SHIFT_LSR
},
223 { "ASR", shift_properties
+ SHIFT_ASR
},
224 { "ROR", shift_properties
+ SHIFT_ROR
},
225 { "RRX", shift_properties
+ SHIFT_RRX
}
228 #define NO_SHIFT_RESTRICT 1
229 #define SHIFT_RESTRICT 0
231 #define NUM_FLOAT_VALS 8
233 CONST
char * fp_const
[] =
235 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
238 /* Number of littlenums required to hold an extended precision number. */
239 #define MAX_LITTLENUMS 6
241 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
251 #define CP_T_X 0x00008000
252 #define CP_T_Y 0x00400000
253 #define CP_T_Pre 0x01000000
254 #define CP_T_UD 0x00800000
255 #define CP_T_WB 0x00200000
257 #define CONDS_BIT 0x00100000
258 #define LOAD_BIT 0x00100000
259 #define TRANS_BIT 0x00200000
261 #define DOUBLE_LOAD_FLAG 0x00000001
265 CONST
char * template;
269 /* This is to save a hash look-up in the common case. */
270 #define COND_ALWAYS 0xe0000000
272 static CONST
struct asm_cond conds
[] =
276 {"cs", 0x20000000}, {"hs", 0x20000000},
277 {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000},
292 /* Warning: If the top bit of the set_bits is set, then the standard
293 instruction bitmask is ignored, and the new bitmask is taken from
297 CONST
char * template; /* Basic flag string. */
298 unsigned long set_bits
; /* Bits to set. */
301 static CONST
struct asm_flg s_flag
[] =
307 static CONST
struct asm_flg ldr_flags
[] =
309 {"d", DOUBLE_LOAD_FLAG
},
312 {"bt", 0x00400000 | TRANS_BIT
},
319 static CONST
struct asm_flg str_flags
[] =
321 {"d", DOUBLE_LOAD_FLAG
},
324 {"bt", 0x00400000 | TRANS_BIT
},
329 static CONST
struct asm_flg byte_flag
[] =
335 static CONST
struct asm_flg cmp_flags
[] =
342 static CONST
struct asm_flg ldm_flags
[] =
355 static CONST
struct asm_flg stm_flags
[] =
368 static CONST
struct asm_flg lfm_flags
[] =
375 static CONST
struct asm_flg sfm_flags
[] =
382 static CONST
struct asm_flg round_flags
[] =
390 /* The implementation of the FIX instruction is broken on some assemblers,
391 in that it accepts a precision specifier as well as a rounding specifier,
392 despite the fact that this is meaningless. To be more compatible, we
393 accept it as well, though of course it does not set any bits. */
394 static CONST
struct asm_flg fix_flags
[] =
411 static CONST
struct asm_flg except_flag
[] =
417 static CONST
struct asm_flg cplong_flag
[] =
425 CONST
char * template;
430 /* The bit that distnguishes CPSR and SPSR. */
431 #define SPSR_BIT (1 << 22)
433 /* How many bits to shift the PSR_xxx bits up by. */
436 #define PSR_c (1 << 0)
437 #define PSR_x (1 << 1)
438 #define PSR_s (1 << 2)
439 #define PSR_f (1 << 3)
441 static CONST
struct asm_psr psrs
[] =
443 {"CPSR", true, PSR_c
| PSR_f
},
444 {"CPSR_all", true, PSR_c
| PSR_f
},
445 {"SPSR", false, PSR_c
| PSR_f
},
446 {"SPSR_all", false, PSR_c
| PSR_f
},
447 {"CPSR_flg", true, PSR_f
},
448 {"CPSR_f", true, PSR_f
},
449 {"SPSR_flg", false, PSR_f
},
450 {"SPSR_f", false, PSR_f
},
451 {"CPSR_c", true, PSR_c
},
452 {"CPSR_ctl", true, PSR_c
},
453 {"SPSR_c", false, PSR_c
},
454 {"SPSR_ctl", false, PSR_c
},
455 {"CPSR_x", true, PSR_x
},
456 {"CPSR_s", true, PSR_s
},
457 {"SPSR_x", false, PSR_x
},
458 {"SPSR_s", false, PSR_s
},
459 /* Combinations of flags. */
460 {"CPSR_fs", true, PSR_f
| PSR_s
},
461 {"CPSR_fx", true, PSR_f
| PSR_x
},
462 {"CPSR_fc", true, PSR_f
| PSR_c
},
463 {"CPSR_sf", true, PSR_s
| PSR_f
},
464 {"CPSR_sx", true, PSR_s
| PSR_x
},
465 {"CPSR_sc", true, PSR_s
| PSR_c
},
466 {"CPSR_xf", true, PSR_x
| PSR_f
},
467 {"CPSR_xs", true, PSR_x
| PSR_s
},
468 {"CPSR_xc", true, PSR_x
| PSR_c
},
469 {"CPSR_cf", true, PSR_c
| PSR_f
},
470 {"CPSR_cs", true, PSR_c
| PSR_s
},
471 {"CPSR_cx", true, PSR_c
| PSR_x
},
472 {"CPSR_fsx", true, PSR_f
| PSR_s
| PSR_x
},
473 {"CPSR_fsc", true, PSR_f
| PSR_s
| PSR_c
},
474 {"CPSR_fxs", true, PSR_f
| PSR_x
| PSR_s
},
475 {"CPSR_fxc", true, PSR_f
| PSR_x
| PSR_c
},
476 {"CPSR_fcs", true, PSR_f
| PSR_c
| PSR_s
},
477 {"CPSR_fcx", true, PSR_f
| PSR_c
| PSR_x
},
478 {"CPSR_sfx", true, PSR_s
| PSR_f
| PSR_x
},
479 {"CPSR_sfc", true, PSR_s
| PSR_f
| PSR_c
},
480 {"CPSR_sxf", true, PSR_s
| PSR_x
| PSR_f
},
481 {"CPSR_sxc", true, PSR_s
| PSR_x
| PSR_c
},
482 {"CPSR_scf", true, PSR_s
| PSR_c
| PSR_f
},
483 {"CPSR_scx", true, PSR_s
| PSR_c
| PSR_x
},
484 {"CPSR_xfs", true, PSR_x
| PSR_f
| PSR_s
},
485 {"CPSR_xfc", true, PSR_x
| PSR_f
| PSR_c
},
486 {"CPSR_xsf", true, PSR_x
| PSR_s
| PSR_f
},
487 {"CPSR_xsc", true, PSR_x
| PSR_s
| PSR_c
},
488 {"CPSR_xcf", true, PSR_x
| PSR_c
| PSR_f
},
489 {"CPSR_xcs", true, PSR_x
| PSR_c
| PSR_s
},
490 {"CPSR_cfs", true, PSR_c
| PSR_f
| PSR_s
},
491 {"CPSR_cfx", true, PSR_c
| PSR_f
| PSR_x
},
492 {"CPSR_csf", true, PSR_c
| PSR_s
| PSR_f
},
493 {"CPSR_csx", true, PSR_c
| PSR_s
| PSR_x
},
494 {"CPSR_cxf", true, PSR_c
| PSR_x
| PSR_f
},
495 {"CPSR_cxs", true, PSR_c
| PSR_x
| PSR_s
},
496 {"CPSR_fsxc", true, PSR_f
| PSR_s
| PSR_x
| PSR_c
},
497 {"CPSR_fscx", true, PSR_f
| PSR_s
| PSR_c
| PSR_x
},
498 {"CPSR_fxsc", true, PSR_f
| PSR_x
| PSR_s
| PSR_c
},
499 {"CPSR_fxcs", true, PSR_f
| PSR_x
| PSR_c
| PSR_s
},
500 {"CPSR_fcsx", true, PSR_f
| PSR_c
| PSR_s
| PSR_x
},
501 {"CPSR_fcxs", true, PSR_f
| PSR_c
| PSR_x
| PSR_s
},
502 {"CPSR_sfxc", true, PSR_s
| PSR_f
| PSR_x
| PSR_c
},
503 {"CPSR_sfcx", true, PSR_s
| PSR_f
| PSR_c
| PSR_x
},
504 {"CPSR_sxfc", true, PSR_s
| PSR_x
| PSR_f
| PSR_c
},
505 {"CPSR_sxcf", true, PSR_s
| PSR_x
| PSR_c
| PSR_f
},
506 {"CPSR_scfx", true, PSR_s
| PSR_c
| PSR_f
| PSR_x
},
507 {"CPSR_scxf", true, PSR_s
| PSR_c
| PSR_x
| PSR_f
},
508 {"CPSR_xfsc", true, PSR_x
| PSR_f
| PSR_s
| PSR_c
},
509 {"CPSR_xfcs", true, PSR_x
| PSR_f
| PSR_c
| PSR_s
},
510 {"CPSR_xsfc", true, PSR_x
| PSR_s
| PSR_f
| PSR_c
},
511 {"CPSR_xscf", true, PSR_x
| PSR_s
| PSR_c
| PSR_f
},
512 {"CPSR_xcfs", true, PSR_x
| PSR_c
| PSR_f
| PSR_s
},
513 {"CPSR_xcsf", true, PSR_x
| PSR_c
| PSR_s
| PSR_f
},
514 {"CPSR_cfsx", true, PSR_c
| PSR_f
| PSR_s
| PSR_x
},
515 {"CPSR_cfxs", true, PSR_c
| PSR_f
| PSR_x
| PSR_s
},
516 {"CPSR_csfx", true, PSR_c
| PSR_s
| PSR_f
| PSR_x
},
517 {"CPSR_csxf", true, PSR_c
| PSR_s
| PSR_x
| PSR_f
},
518 {"CPSR_cxfs", true, PSR_c
| PSR_x
| PSR_f
| PSR_s
},
519 {"CPSR_cxsf", true, PSR_c
| PSR_x
| PSR_s
| PSR_f
},
520 {"SPSR_fs", false, PSR_f
| PSR_s
},
521 {"SPSR_fx", false, PSR_f
| PSR_x
},
522 {"SPSR_fc", false, PSR_f
| PSR_c
},
523 {"SPSR_sf", false, PSR_s
| PSR_f
},
524 {"SPSR_sx", false, PSR_s
| PSR_x
},
525 {"SPSR_sc", false, PSR_s
| PSR_c
},
526 {"SPSR_xf", false, PSR_x
| PSR_f
},
527 {"SPSR_xs", false, PSR_x
| PSR_s
},
528 {"SPSR_xc", false, PSR_x
| PSR_c
},
529 {"SPSR_cf", false, PSR_c
| PSR_f
},
530 {"SPSR_cs", false, PSR_c
| PSR_s
},
531 {"SPSR_cx", false, PSR_c
| PSR_x
},
532 {"SPSR_fsx", false, PSR_f
| PSR_s
| PSR_x
},
533 {"SPSR_fsc", false, PSR_f
| PSR_s
| PSR_c
},
534 {"SPSR_fxs", false, PSR_f
| PSR_x
| PSR_s
},
535 {"SPSR_fxc", false, PSR_f
| PSR_x
| PSR_c
},
536 {"SPSR_fcs", false, PSR_f
| PSR_c
| PSR_s
},
537 {"SPSR_fcx", false, PSR_f
| PSR_c
| PSR_x
},
538 {"SPSR_sfx", false, PSR_s
| PSR_f
| PSR_x
},
539 {"SPSR_sfc", false, PSR_s
| PSR_f
| PSR_c
},
540 {"SPSR_sxf", false, PSR_s
| PSR_x
| PSR_f
},
541 {"SPSR_sxc", false, PSR_s
| PSR_x
| PSR_c
},
542 {"SPSR_scf", false, PSR_s
| PSR_c
| PSR_f
},
543 {"SPSR_scx", false, PSR_s
| PSR_c
| PSR_x
},
544 {"SPSR_xfs", false, PSR_x
| PSR_f
| PSR_s
},
545 {"SPSR_xfc", false, PSR_x
| PSR_f
| PSR_c
},
546 {"SPSR_xsf", false, PSR_x
| PSR_s
| PSR_f
},
547 {"SPSR_xsc", false, PSR_x
| PSR_s
| PSR_c
},
548 {"SPSR_xcf", false, PSR_x
| PSR_c
| PSR_f
},
549 {"SPSR_xcs", false, PSR_x
| PSR_c
| PSR_s
},
550 {"SPSR_cfs", false, PSR_c
| PSR_f
| PSR_s
},
551 {"SPSR_cfx", false, PSR_c
| PSR_f
| PSR_x
},
552 {"SPSR_csf", false, PSR_c
| PSR_s
| PSR_f
},
553 {"SPSR_csx", false, PSR_c
| PSR_s
| PSR_x
},
554 {"SPSR_cxf", false, PSR_c
| PSR_x
| PSR_f
},
555 {"SPSR_cxs", false, PSR_c
| PSR_x
| PSR_s
},
556 {"SPSR_fsxc", false, PSR_f
| PSR_s
| PSR_x
| PSR_c
},
557 {"SPSR_fscx", false, PSR_f
| PSR_s
| PSR_c
| PSR_x
},
558 {"SPSR_fxsc", false, PSR_f
| PSR_x
| PSR_s
| PSR_c
},
559 {"SPSR_fxcs", false, PSR_f
| PSR_x
| PSR_c
| PSR_s
},
560 {"SPSR_fcsx", false, PSR_f
| PSR_c
| PSR_s
| PSR_x
},
561 {"SPSR_fcxs", false, PSR_f
| PSR_c
| PSR_x
| PSR_s
},
562 {"SPSR_sfxc", false, PSR_s
| PSR_f
| PSR_x
| PSR_c
},
563 {"SPSR_sfcx", false, PSR_s
| PSR_f
| PSR_c
| PSR_x
},
564 {"SPSR_sxfc", false, PSR_s
| PSR_x
| PSR_f
| PSR_c
},
565 {"SPSR_sxcf", false, PSR_s
| PSR_x
| PSR_c
| PSR_f
},
566 {"SPSR_scfx", false, PSR_s
| PSR_c
| PSR_f
| PSR_x
},
567 {"SPSR_scxf", false, PSR_s
| PSR_c
| PSR_x
| PSR_f
},
568 {"SPSR_xfsc", false, PSR_x
| PSR_f
| PSR_s
| PSR_c
},
569 {"SPSR_xfcs", false, PSR_x
| PSR_f
| PSR_c
| PSR_s
},
570 {"SPSR_xsfc", false, PSR_x
| PSR_s
| PSR_f
| PSR_c
},
571 {"SPSR_xscf", false, PSR_x
| PSR_s
| PSR_c
| PSR_f
},
572 {"SPSR_xcfs", false, PSR_x
| PSR_c
| PSR_f
| PSR_s
},
573 {"SPSR_xcsf", false, PSR_x
| PSR_c
| PSR_s
| PSR_f
},
574 {"SPSR_cfsx", false, PSR_c
| PSR_f
| PSR_s
| PSR_x
},
575 {"SPSR_cfxs", false, PSR_c
| PSR_f
| PSR_x
| PSR_s
},
576 {"SPSR_csfx", false, PSR_c
| PSR_s
| PSR_f
| PSR_x
},
577 {"SPSR_csxf", false, PSR_c
| PSR_s
| PSR_x
| PSR_f
},
578 {"SPSR_cxfs", false, PSR_c
| PSR_x
| PSR_f
| PSR_s
},
579 {"SPSR_cxsf", false, PSR_c
| PSR_x
| PSR_s
| PSR_f
},
582 /* Functions called by parser. */
583 /* ARM instructions. */
584 static void do_arit
PARAMS ((char *, unsigned long));
585 static void do_cmp
PARAMS ((char *, unsigned long));
586 static void do_mov
PARAMS ((char *, unsigned long));
587 static void do_ldst
PARAMS ((char *, unsigned long));
588 static void do_ldmstm
PARAMS ((char *, unsigned long));
589 static void do_branch
PARAMS ((char *, unsigned long));
590 static void do_swi
PARAMS ((char *, unsigned long));
591 /* Pseudo Op codes. */
592 static void do_adr
PARAMS ((char *, unsigned long));
593 static void do_adrl
PARAMS ((char *, unsigned long));
594 static void do_nop
PARAMS ((char *, unsigned long));
596 static void do_mul
PARAMS ((char *, unsigned long));
597 static void do_mla
PARAMS ((char *, unsigned long));
599 static void do_swap
PARAMS ((char *, unsigned long));
601 static void do_msr
PARAMS ((char *, unsigned long));
602 static void do_mrs
PARAMS ((char *, unsigned long));
604 static void do_mull
PARAMS ((char *, unsigned long));
606 static void do_bx
PARAMS ((char *, unsigned long));
608 /* ARM_EXT_XScale. */
609 static void do_mia
PARAMS ((char *, unsigned long));
610 static void do_mar
PARAMS ((char *, unsigned long));
611 static void do_mra
PARAMS ((char *, unsigned long));
612 static void do_pld
PARAMS ((char *, unsigned long));
613 static void do_ldrd
PARAMS ((char *, unsigned long));
616 static void do_blx
PARAMS ((char *, unsigned long));
617 static void do_bkpt
PARAMS ((char *, unsigned long));
618 static void do_clz
PARAMS ((char *, unsigned long));
619 static void do_lstc2
PARAMS ((char *, unsigned long));
620 static void do_cdp2
PARAMS ((char *, unsigned long));
621 static void do_co_reg2
PARAMS ((char *, unsigned long));
623 static void do_t_blx
PARAMS ((char *));
624 static void do_t_bkpt
PARAMS ((char *));
627 static void do_smla
PARAMS ((char *, unsigned long));
628 static void do_smlal
PARAMS ((char *, unsigned long));
629 static void do_smul
PARAMS ((char *, unsigned long));
630 static void do_qadd
PARAMS ((char *, unsigned long));
631 static void do_co_reg2c
PARAMS ((char *, unsigned long));
633 /* Coprocessor Instructions. */
634 static void do_cdp
PARAMS ((char *, unsigned long));
635 static void do_lstc
PARAMS ((char *, unsigned long));
636 static void do_co_reg
PARAMS ((char *, unsigned long));
637 static void do_fp_ctrl
PARAMS ((char *, unsigned long));
638 static void do_fp_ldst
PARAMS ((char *, unsigned long));
639 static void do_fp_ldmstm
PARAMS ((char *, unsigned long));
640 static void do_fp_dyadic
PARAMS ((char *, unsigned long));
641 static void do_fp_monadic
PARAMS ((char *, unsigned long));
642 static void do_fp_cmp
PARAMS ((char *, unsigned long));
643 static void do_fp_from_reg
PARAMS ((char *, unsigned long));
644 static void do_fp_to_reg
PARAMS ((char *, unsigned long));
646 static void fix_new_arm
PARAMS ((fragS
*, int, short, expressionS
*, int, int));
647 static int arm_reg_parse
PARAMS ((char **));
648 static CONST
struct asm_psr
* arm_psr_parse
PARAMS ((char **));
649 static void symbol_locate
PARAMS ((symbolS
*, CONST
char *, segT
, valueT
, fragS
*));
650 static int add_to_lit_pool
PARAMS ((void));
651 static unsigned validate_immediate
PARAMS ((unsigned));
652 static unsigned validate_immediate_twopart
PARAMS ((unsigned int, unsigned int *));
653 static int validate_offset_imm
PARAMS ((unsigned int, int));
654 static void opcode_select
PARAMS ((int));
655 static void end_of_line
PARAMS ((char *));
656 static int reg_required_here
PARAMS ((char **, int));
657 static int psr_required_here
PARAMS ((char **));
658 static int co_proc_number
PARAMS ((char **));
659 static int cp_opc_expr
PARAMS ((char **, int, int));
660 static int cp_reg_required_here
PARAMS ((char **, int));
661 static int fp_reg_required_here
PARAMS ((char **, int));
662 static int cp_address_offset
PARAMS ((char **));
663 static int cp_address_required_here
PARAMS ((char **));
664 static int my_get_float_expression
PARAMS ((char **));
665 static int skip_past_comma
PARAMS ((char **));
666 static int walk_no_bignums
PARAMS ((symbolS
*));
667 static int negate_data_op
PARAMS ((unsigned long *, unsigned long));
668 static int data_op2
PARAMS ((char **));
669 static int fp_op2
PARAMS ((char **));
670 static long reg_list
PARAMS ((char **));
671 static void thumb_load_store
PARAMS ((char *, int, int));
672 static int decode_shift
PARAMS ((char **, int));
673 static int ldst_extend
PARAMS ((char **, int));
674 static void thumb_add_sub
PARAMS ((char *, int));
675 static void insert_reg
PARAMS ((int));
676 static void thumb_shift
PARAMS ((char *, int));
677 static void thumb_mov_compare
PARAMS ((char *, int));
678 static void set_constant_flonums
PARAMS ((void));
679 static valueT md_chars_to_number
PARAMS ((char *, int));
680 static void insert_reg_alias
PARAMS ((char *, int));
681 static void output_inst
PARAMS ((void));
683 static bfd_reloc_code_real_type arm_parse_reloc
PARAMS ((void));
686 /* ARM instructions take 4bytes in the object file, Thumb instructions
690 /* LONGEST_INST is the longest basic instruction name without
691 conditions or flags. ARM7M has 4 of length 5. El Segundo
692 has one basic instruction name of length 7 (SMLALxy). */
693 #define LONGEST_INST 7
697 /* Basic string to match. */
698 CONST
char * template;
700 /* Basic instruction code. */
703 /* Compulsory suffix that must follow conds. If "", then the
704 instruction is not conditional and must have no suffix. */
705 CONST
char * comp_suffix
;
707 /* Bits to toggle if flag 'n' set. */
708 CONST
struct asm_flg
* flags
;
710 /* Which CPU variants this exists for. */
711 unsigned long variants
;
713 /* Function to call to parse args. */
714 void (* parms
) PARAMS ((char *, unsigned long));
717 static CONST
struct asm_opcode insns
[] =
719 /* Intel XScale extensions to ARM V5 ISA. */
720 {"mia", 0x0e200010, NULL
, NULL
, ARM_EXT_XSCALE
, do_mia
},
721 {"miaph", 0x0e280010, NULL
, NULL
, ARM_EXT_XSCALE
, do_mia
},
722 {"miabb", 0x0e2c0010, NULL
, NULL
, ARM_EXT_XSCALE
, do_mia
},
723 {"miabt", 0x0e2d0010, NULL
, NULL
, ARM_EXT_XSCALE
, do_mia
},
724 {"miatb", 0x0e2e0010, NULL
, NULL
, ARM_EXT_XSCALE
, do_mia
},
725 {"miatt", 0x0e2f0010, NULL
, NULL
, ARM_EXT_XSCALE
, do_mia
},
726 {"mar", 0x0c400000, NULL
, NULL
, ARM_EXT_XSCALE
, do_mar
},
727 {"mra", 0x0c500000, NULL
, NULL
, ARM_EXT_XSCALE
, do_mra
},
728 {"pld", 0xf450f000, "", NULL
, ARM_EXT_XSCALE
, do_pld
},
729 {"ldr", 0x000000d0, NULL
, ldr_flags
, ARM_ANY
, do_ldrd
},
730 {"str", 0x000000f0, NULL
, str_flags
, ARM_ANY
, do_ldrd
},
732 /* ARM Instructions. */
733 {"and", 0x00000000, NULL
, s_flag
, ARM_ANY
, do_arit
},
734 {"eor", 0x00200000, NULL
, s_flag
, ARM_ANY
, do_arit
},
735 {"sub", 0x00400000, NULL
, s_flag
, ARM_ANY
, do_arit
},
736 {"rsb", 0x00600000, NULL
, s_flag
, ARM_ANY
, do_arit
},
737 {"add", 0x00800000, NULL
, s_flag
, ARM_ANY
, do_arit
},
738 {"adc", 0x00a00000, NULL
, s_flag
, ARM_ANY
, do_arit
},
739 {"sbc", 0x00c00000, NULL
, s_flag
, ARM_ANY
, do_arit
},
740 {"rsc", 0x00e00000, NULL
, s_flag
, ARM_ANY
, do_arit
},
741 {"orr", 0x01800000, NULL
, s_flag
, ARM_ANY
, do_arit
},
742 {"bic", 0x01c00000, NULL
, s_flag
, ARM_ANY
, do_arit
},
743 {"tst", 0x01000000, NULL
, cmp_flags
, ARM_ANY
, do_cmp
},
744 {"teq", 0x01200000, NULL
, cmp_flags
, ARM_ANY
, do_cmp
},
745 {"cmp", 0x01400000, NULL
, cmp_flags
, ARM_ANY
, do_cmp
},
746 {"cmn", 0x01600000, NULL
, cmp_flags
, ARM_ANY
, do_cmp
},
747 {"mov", 0x01a00000, NULL
, s_flag
, ARM_ANY
, do_mov
},
748 {"mvn", 0x01e00000, NULL
, s_flag
, ARM_ANY
, do_mov
},
749 {"str", 0x04000000, NULL
, str_flags
, ARM_ANY
, do_ldst
},
750 {"ldr", 0x04100000, NULL
, ldr_flags
, ARM_ANY
, do_ldst
},
751 {"stm", 0x08000000, NULL
, stm_flags
, ARM_ANY
, do_ldmstm
},
752 {"ldm", 0x08100000, NULL
, ldm_flags
, ARM_ANY
, do_ldmstm
},
753 {"swi", 0x0f000000, NULL
, NULL
, ARM_ANY
, do_swi
},
755 {"bl", 0x0b000000, NULL
, NULL
, ARM_ANY
, do_branch
},
756 {"b", 0x0a000000, NULL
, NULL
, ARM_ANY
, do_branch
},
758 {"bl", 0x0bfffffe, NULL
, NULL
, ARM_ANY
, do_branch
},
759 {"b", 0x0afffffe, NULL
, NULL
, ARM_ANY
, do_branch
},
763 {"adr", 0x028f0000, NULL
, NULL
, ARM_ANY
, do_adr
},
764 {"adrl", 0x028f0000, NULL
, NULL
, ARM_ANY
, do_adrl
},
765 {"nop", 0x01a00000, NULL
, NULL
, ARM_ANY
, do_nop
},
767 /* ARM 2 multiplies. */
768 {"mul", 0x00000090, NULL
, s_flag
, ARM_2UP
, do_mul
},
769 {"mla", 0x00200090, NULL
, s_flag
, ARM_2UP
, do_mla
},
771 /* ARM 3 - swp instructions. */
772 {"swp", 0x01000090, NULL
, byte_flag
, ARM_3UP
, do_swap
},
774 /* ARM 6 Coprocessor instructions. */
775 {"mrs", 0x010f0000, NULL
, NULL
, ARM_6UP
, do_mrs
},
776 {"msr", 0x0120f000, NULL
, NULL
, ARM_6UP
, do_msr
},
777 /* ScottB: our code uses 0x0128f000 for msr.
778 NickC: but this is wrong because the bits 16 through 19 are
779 handled by the PSR_xxx defines above. */
781 /* ARM 7M long multiplies - need signed/unsigned flags! */
782 {"smull", 0x00c00090, NULL
, s_flag
, ARM_EXT_LONGMUL
, do_mull
},
783 {"umull", 0x00800090, NULL
, s_flag
, ARM_EXT_LONGMUL
, do_mull
},
784 {"smlal", 0x00e00090, NULL
, s_flag
, ARM_EXT_LONGMUL
, do_mull
},
785 {"umlal", 0x00a00090, NULL
, s_flag
, ARM_EXT_LONGMUL
, do_mull
},
787 /* ARM THUMB interworking. */
788 {"bx", 0x012fff10, NULL
, NULL
, ARM_EXT_THUMB
, do_bx
},
790 /* Floating point instructions. */
791 {"wfs", 0x0e200110, NULL
, NULL
, FPU_ALL
, do_fp_ctrl
},
792 {"rfs", 0x0e300110, NULL
, NULL
, FPU_ALL
, do_fp_ctrl
},
793 {"wfc", 0x0e400110, NULL
, NULL
, FPU_ALL
, do_fp_ctrl
},
794 {"rfc", 0x0e500110, NULL
, NULL
, FPU_ALL
, do_fp_ctrl
},
795 {"ldf", 0x0c100100, "sdep", NULL
, FPU_ALL
, do_fp_ldst
},
796 {"stf", 0x0c000100, "sdep", NULL
, FPU_ALL
, do_fp_ldst
},
797 {"lfm", 0x0c100200, NULL
, lfm_flags
, FPU_MEMMULTI
, do_fp_ldmstm
},
798 {"sfm", 0x0c000200, NULL
, sfm_flags
, FPU_MEMMULTI
, do_fp_ldmstm
},
799 {"mvf", 0x0e008100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
800 {"mnf", 0x0e108100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
801 {"abs", 0x0e208100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
802 {"rnd", 0x0e308100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
803 {"sqt", 0x0e408100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
804 {"log", 0x0e508100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
805 {"lgn", 0x0e608100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
806 {"exp", 0x0e708100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
807 {"sin", 0x0e808100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
808 {"cos", 0x0e908100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
809 {"tan", 0x0ea08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
810 {"asn", 0x0eb08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
811 {"acs", 0x0ec08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
812 {"atn", 0x0ed08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
813 {"urd", 0x0ee08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
814 {"nrm", 0x0ef08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
815 {"adf", 0x0e000100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
816 {"suf", 0x0e200100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
817 {"rsf", 0x0e300100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
818 {"muf", 0x0e100100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
819 {"dvf", 0x0e400100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
820 {"rdf", 0x0e500100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
821 {"pow", 0x0e600100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
822 {"rpw", 0x0e700100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
823 {"rmf", 0x0e800100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
824 {"fml", 0x0e900100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
825 {"fdv", 0x0ea00100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
826 {"frd", 0x0eb00100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
827 {"pol", 0x0ec00100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
828 {"cmf", 0x0e90f110, NULL
, except_flag
, FPU_ALL
, do_fp_cmp
},
829 {"cnf", 0x0eb0f110, NULL
, except_flag
, FPU_ALL
, do_fp_cmp
},
830 /* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should not
831 be an optional suffix, but part of the instruction. To be compatible,
833 {"cmfe", 0x0ed0f110, NULL
, NULL
, FPU_ALL
, do_fp_cmp
},
834 {"cnfe", 0x0ef0f110, NULL
, NULL
, FPU_ALL
, do_fp_cmp
},
835 {"flt", 0x0e000110, "sde", round_flags
, FPU_ALL
, do_fp_from_reg
},
836 {"fix", 0x0e100110, NULL
, fix_flags
, FPU_ALL
, do_fp_to_reg
},
838 /* Generic copressor instructions. */
839 {"cdp", 0x0e000000, NULL
, NULL
, ARM_2UP
, do_cdp
},
840 {"ldc", 0x0c100000, NULL
, cplong_flag
, ARM_2UP
, do_lstc
},
841 {"stc", 0x0c000000, NULL
, cplong_flag
, ARM_2UP
, do_lstc
},
842 {"mcr", 0x0e000010, NULL
, NULL
, ARM_2UP
, do_co_reg
},
843 {"mrc", 0x0e100010, NULL
, NULL
, ARM_2UP
, do_co_reg
},
845 /* ARM ISA extension 5. */
846 /* Note: blx is actually 2 opcodes, so the .value is set dynamically.
847 And it's sometimes conditional and sometimes not. */
848 {"blx", 0, NULL
, NULL
, ARM_EXT_V5
, do_blx
},
849 {"clz", 0x016f0f10, NULL
, NULL
, ARM_EXT_V5
, do_clz
},
850 {"bkpt", 0xe1200070, "", NULL
, ARM_EXT_V5
, do_bkpt
},
851 {"ldc2", 0xfc100000, "", cplong_flag
, ARM_EXT_V5
, do_lstc2
},
852 {"stc2", 0xfc000000, "", cplong_flag
, ARM_EXT_V5
, do_lstc2
},
853 {"cdp2", 0xfe000000, "", NULL
, ARM_EXT_V5
, do_cdp2
},
854 {"mcr2", 0xfe000010, "", NULL
, ARM_EXT_V5
, do_co_reg2
},
855 {"mrc2", 0xfe100010, "", NULL
, ARM_EXT_V5
, do_co_reg2
},
857 /* ARM ISA extension 5E, El Segundo. */
858 {"smlabb", 0x01000080, NULL
, NULL
, ARM_EXT_V5E
, do_smla
},
859 {"smlatb", 0x010000a0, NULL
, NULL
, ARM_EXT_V5E
, do_smla
},
860 {"smlabt", 0x010000c0, NULL
, NULL
, ARM_EXT_V5E
, do_smla
},
861 {"smlatt", 0x010000e0, NULL
, NULL
, ARM_EXT_V5E
, do_smla
},
863 {"smlawb", 0x01200080, NULL
, NULL
, ARM_EXT_V5E
, do_smla
},
864 {"smlawt", 0x012000c0, NULL
, NULL
, ARM_EXT_V5E
, do_smla
},
866 {"smlalbb",0x01400080, NULL
, NULL
, ARM_EXT_V5E
, do_smlal
},
867 {"smlaltb",0x014000a0, NULL
, NULL
, ARM_EXT_V5E
, do_smlal
},
868 {"smlalbt",0x014000c0, NULL
, NULL
, ARM_EXT_V5E
, do_smlal
},
869 {"smlaltt",0x014000e0, NULL
, NULL
, ARM_EXT_V5E
, do_smlal
},
871 {"smulbb", 0x01600080, NULL
, NULL
, ARM_EXT_V5E
, do_smul
},
872 {"smultb", 0x016000a0, NULL
, NULL
, ARM_EXT_V5E
, do_smul
},
873 {"smulbt", 0x016000c0, NULL
, NULL
, ARM_EXT_V5E
, do_smul
},
874 {"smultt", 0x016000e0, NULL
, NULL
, ARM_EXT_V5E
, do_smul
},
876 {"smulwb", 0x012000a0, NULL
, NULL
, ARM_EXT_V5E
, do_smul
},
877 {"smulwt", 0x012000e0, NULL
, NULL
, ARM_EXT_V5E
, do_smul
},
879 {"qadd", 0x01000050, NULL
, NULL
, ARM_EXT_V5E
, do_qadd
},
880 {"qdadd", 0x01400050, NULL
, NULL
, ARM_EXT_V5E
, do_qadd
},
881 {"qsub", 0x01200050, NULL
, NULL
, ARM_EXT_V5E
, do_qadd
},
882 {"qdsub", 0x01600050, NULL
, NULL
, ARM_EXT_V5E
, do_qadd
},
884 {"mcrr", 0x0c400000, NULL
, NULL
, ARM_EXT_V5E
, do_co_reg2c
},
885 {"mrrc", 0x0c500000, NULL
, NULL
, ARM_EXT_V5E
, do_co_reg2c
},
888 /* Defines for various bits that we will want to toggle. */
889 #define INST_IMMEDIATE 0x02000000
890 #define OFFSET_REG 0x02000000
891 #define HWOFFSET_IMM 0x00400000
892 #define SHIFT_BY_REG 0x00000010
893 #define PRE_INDEX 0x01000000
894 #define INDEX_UP 0x00800000
895 #define WRITE_BACK 0x00200000
896 #define LDM_TYPE_2_OR_3 0x00400000
898 #define LITERAL_MASK 0xf000f000
899 #define COND_MASK 0xf0000000
900 #define OPCODE_MASK 0xfe1fffff
901 #define DATA_OP_SHIFT 21
903 /* Codes to distinguish the arithmetic instructions. */
914 #define OPCODE_CMP 10
915 #define OPCODE_CMN 11
916 #define OPCODE_ORR 12
917 #define OPCODE_MOV 13
918 #define OPCODE_BIC 14
919 #define OPCODE_MVN 15
921 static void do_t_nop
PARAMS ((char *));
922 static void do_t_arit
PARAMS ((char *));
923 static void do_t_add
PARAMS ((char *));
924 static void do_t_asr
PARAMS ((char *));
925 static void do_t_branch9
PARAMS ((char *));
926 static void do_t_branch12
PARAMS ((char *));
927 static void do_t_branch23
PARAMS ((char *));
928 static void do_t_bx
PARAMS ((char *));
929 static void do_t_compare
PARAMS ((char *));
930 static void do_t_ldmstm
PARAMS ((char *));
931 static void do_t_ldr
PARAMS ((char *));
932 static void do_t_ldrb
PARAMS ((char *));
933 static void do_t_ldrh
PARAMS ((char *));
934 static void do_t_lds
PARAMS ((char *));
935 static void do_t_lsl
PARAMS ((char *));
936 static void do_t_lsr
PARAMS ((char *));
937 static void do_t_mov
PARAMS ((char *));
938 static void do_t_push_pop
PARAMS ((char *));
939 static void do_t_str
PARAMS ((char *));
940 static void do_t_strb
PARAMS ((char *));
941 static void do_t_strh
PARAMS ((char *));
942 static void do_t_sub
PARAMS ((char *));
943 static void do_t_swi
PARAMS ((char *));
944 static void do_t_adr
PARAMS ((char *));
946 #define T_OPCODE_MUL 0x4340
947 #define T_OPCODE_TST 0x4200
948 #define T_OPCODE_CMN 0x42c0
949 #define T_OPCODE_NEG 0x4240
950 #define T_OPCODE_MVN 0x43c0
952 #define T_OPCODE_ADD_R3 0x1800
953 #define T_OPCODE_SUB_R3 0x1a00
954 #define T_OPCODE_ADD_HI 0x4400
955 #define T_OPCODE_ADD_ST 0xb000
956 #define T_OPCODE_SUB_ST 0xb080
957 #define T_OPCODE_ADD_SP 0xa800
958 #define T_OPCODE_ADD_PC 0xa000
959 #define T_OPCODE_ADD_I8 0x3000
960 #define T_OPCODE_SUB_I8 0x3800
961 #define T_OPCODE_ADD_I3 0x1c00
962 #define T_OPCODE_SUB_I3 0x1e00
964 #define T_OPCODE_ASR_R 0x4100
965 #define T_OPCODE_LSL_R 0x4080
966 #define T_OPCODE_LSR_R 0x40c0
967 #define T_OPCODE_ASR_I 0x1000
968 #define T_OPCODE_LSL_I 0x0000
969 #define T_OPCODE_LSR_I 0x0800
971 #define T_OPCODE_MOV_I8 0x2000
972 #define T_OPCODE_CMP_I8 0x2800
973 #define T_OPCODE_CMP_LR 0x4280
974 #define T_OPCODE_MOV_HR 0x4600
975 #define T_OPCODE_CMP_HR 0x4500
977 #define T_OPCODE_LDR_PC 0x4800
978 #define T_OPCODE_LDR_SP 0x9800
979 #define T_OPCODE_STR_SP 0x9000
980 #define T_OPCODE_LDR_IW 0x6800
981 #define T_OPCODE_STR_IW 0x6000
982 #define T_OPCODE_LDR_IH 0x8800
983 #define T_OPCODE_STR_IH 0x8000
984 #define T_OPCODE_LDR_IB 0x7800
985 #define T_OPCODE_STR_IB 0x7000
986 #define T_OPCODE_LDR_RW 0x5800
987 #define T_OPCODE_STR_RW 0x5000
988 #define T_OPCODE_LDR_RH 0x5a00
989 #define T_OPCODE_STR_RH 0x5200
990 #define T_OPCODE_LDR_RB 0x5c00
991 #define T_OPCODE_STR_RB 0x5400
993 #define T_OPCODE_PUSH 0xb400
994 #define T_OPCODE_POP 0xbc00
996 #define T_OPCODE_BRANCH 0xe7fe
998 static int thumb_reg
PARAMS ((char ** str
, int hi_lo
));
1000 #define THUMB_SIZE 2 /* Size of thumb instruction. */
1001 #define THUMB_REG_LO 0x1
1002 #define THUMB_REG_HI 0x2
1003 #define THUMB_REG_ANY 0x3
1005 #define THUMB_H1 0x0080
1006 #define THUMB_H2 0x0040
1012 #define THUMB_MOVE 0
1013 #define THUMB_COMPARE 1
1015 #define THUMB_LOAD 0
1016 #define THUMB_STORE 1
1018 #define THUMB_PP_PC_LR 0x0100
1020 /* These three are used for immediate shifts, do not alter. */
1021 #define THUMB_WORD 2
1022 #define THUMB_HALFWORD 1
1023 #define THUMB_BYTE 0
1027 /* Basic string to match. */
1028 CONST
char * template;
1030 /* Basic instruction code. */
1031 unsigned long value
;
1035 /* Which CPU variants this exists for. */
1036 unsigned long variants
;
1038 /* Function to call to parse args. */
1039 void (* parms
) PARAMS ((char *));
1042 static CONST
struct thumb_opcode tinsns
[] =
1044 {"adc", 0x4140, 2, ARM_EXT_THUMB
, do_t_arit
},
1045 {"add", 0x0000, 2, ARM_EXT_THUMB
, do_t_add
},
1046 {"and", 0x4000, 2, ARM_EXT_THUMB
, do_t_arit
},
1047 {"asr", 0x0000, 2, ARM_EXT_THUMB
, do_t_asr
},
1048 {"b", T_OPCODE_BRANCH
, 2, ARM_EXT_THUMB
, do_t_branch12
},
1049 {"beq", 0xd0fe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1050 {"bne", 0xd1fe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1051 {"bcs", 0xd2fe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1052 {"bhs", 0xd2fe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1053 {"bcc", 0xd3fe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1054 {"bul", 0xd3fe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1055 {"blo", 0xd3fe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1056 {"bmi", 0xd4fe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1057 {"bpl", 0xd5fe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1058 {"bvs", 0xd6fe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1059 {"bvc", 0xd7fe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1060 {"bhi", 0xd8fe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1061 {"bls", 0xd9fe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1062 {"bge", 0xdafe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1063 {"blt", 0xdbfe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1064 {"bgt", 0xdcfe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1065 {"ble", 0xddfe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1066 {"bal", 0xdefe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1067 {"bic", 0x4380, 2, ARM_EXT_THUMB
, do_t_arit
},
1068 {"bl", 0xf7fffffe, 4, ARM_EXT_THUMB
, do_t_branch23
},
1069 {"blx", 0, 0, ARM_EXT_V5
, do_t_blx
},
1070 {"bkpt", 0xbe00, 2, ARM_EXT_V5
, do_t_bkpt
},
1071 {"bx", 0x4700, 2, ARM_EXT_THUMB
, do_t_bx
},
1072 {"cmn", T_OPCODE_CMN
, 2, ARM_EXT_THUMB
, do_t_arit
},
1073 {"cmp", 0x0000, 2, ARM_EXT_THUMB
, do_t_compare
},
1074 {"eor", 0x4040, 2, ARM_EXT_THUMB
, do_t_arit
},
1075 {"ldmia", 0xc800, 2, ARM_EXT_THUMB
, do_t_ldmstm
},
1076 {"ldr", 0x0000, 2, ARM_EXT_THUMB
, do_t_ldr
},
1077 {"ldrb", 0x0000, 2, ARM_EXT_THUMB
, do_t_ldrb
},
1078 {"ldrh", 0x0000, 2, ARM_EXT_THUMB
, do_t_ldrh
},
1079 {"ldrsb", 0x5600, 2, ARM_EXT_THUMB
, do_t_lds
},
1080 {"ldrsh", 0x5e00, 2, ARM_EXT_THUMB
, do_t_lds
},
1081 {"ldsb", 0x5600, 2, ARM_EXT_THUMB
, do_t_lds
},
1082 {"ldsh", 0x5e00, 2, ARM_EXT_THUMB
, do_t_lds
},
1083 {"lsl", 0x0000, 2, ARM_EXT_THUMB
, do_t_lsl
},
1084 {"lsr", 0x0000, 2, ARM_EXT_THUMB
, do_t_lsr
},
1085 {"mov", 0x0000, 2, ARM_EXT_THUMB
, do_t_mov
},
1086 {"mul", T_OPCODE_MUL
, 2, ARM_EXT_THUMB
, do_t_arit
},
1087 {"mvn", T_OPCODE_MVN
, 2, ARM_EXT_THUMB
, do_t_arit
},
1088 {"neg", T_OPCODE_NEG
, 2, ARM_EXT_THUMB
, do_t_arit
},
1089 {"orr", 0x4300, 2, ARM_EXT_THUMB
, do_t_arit
},
1090 {"pop", 0xbc00, 2, ARM_EXT_THUMB
, do_t_push_pop
},
1091 {"push", 0xb400, 2, ARM_EXT_THUMB
, do_t_push_pop
},
1092 {"ror", 0x41c0, 2, ARM_EXT_THUMB
, do_t_arit
},
1093 {"sbc", 0x4180, 2, ARM_EXT_THUMB
, do_t_arit
},
1094 {"stmia", 0xc000, 2, ARM_EXT_THUMB
, do_t_ldmstm
},
1095 {"str", 0x0000, 2, ARM_EXT_THUMB
, do_t_str
},
1096 {"strb", 0x0000, 2, ARM_EXT_THUMB
, do_t_strb
},
1097 {"strh", 0x0000, 2, ARM_EXT_THUMB
, do_t_strh
},
1098 {"swi", 0xdf00, 2, ARM_EXT_THUMB
, do_t_swi
},
1099 {"sub", 0x0000, 2, ARM_EXT_THUMB
, do_t_sub
},
1100 {"tst", T_OPCODE_TST
, 2, ARM_EXT_THUMB
, do_t_arit
},
1102 {"adr", 0x0000, 2, ARM_EXT_THUMB
, do_t_adr
},
1103 {"nop", 0x46C0, 2, ARM_EXT_THUMB
, do_t_nop
}, /* mov r8,r8 */
1112 #define int_register(reg) ((reg) >= 0 && (reg) <= 15)
1113 #define cp_register(reg) ((reg) >= 32 && (reg) <= 47)
1114 #define fp_register(reg) ((reg) >= 16 && (reg) <= 23)
1120 /* These are the standard names. Users can add aliases with .req. */
1121 static CONST
struct reg_entry reg_table
[] =
1123 /* Processor Register Numbers. */
1124 {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
1125 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
1126 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
1127 {"r12", 12}, {"r13", REG_SP
},{"r14", REG_LR
},{"r15", REG_PC
},
1128 /* APCS conventions. */
1129 {"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3},
1130 {"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8},
1131 {"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10},
1132 {"fp", 11}, {"ip", 12}, {"sp", REG_SP
},{"lr", REG_LR
},{"pc", REG_PC
},
1133 /* ATPCS additions to APCS conventions. */
1134 {"wr", 7}, {"v8", 11},
1136 {"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19},
1137 {"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23},
1138 {"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35},
1139 {"c4", 36}, {"c5", 37}, {"c6", 38}, {"c7", 39},
1140 {"c8", 40}, {"c9", 41}, {"c10", 42}, {"c11", 43},
1141 {"c12", 44}, {"c13", 45}, {"c14", 46}, {"c15", 47},
1142 {"cr0", 32}, {"cr1", 33}, {"cr2", 34}, {"cr3", 35},
1143 {"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39},
1144 {"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43},
1145 {"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47},
1146 /* ATPCS additions to float register names. */
1147 {"s0",16}, {"s1",17}, {"s2",18}, {"s3",19},
1148 {"s4",20}, {"s5",21}, {"s6",22}, {"s7",23},
1149 {"d0",16}, {"d1",17}, {"d2",18}, {"d3",19},
1150 {"d4",20}, {"d5",21}, {"d6",22}, {"d7",23},
1151 /* FIXME: At some point we need to add VFP register names. */
1152 /* Array terminator. */
1156 #define BAD_ARGS _("Bad arguments to instruction")
1157 #define BAD_PC _("r15 not allowed here")
1158 #define BAD_FLAGS _("Instruction should not have flags")
1159 #define BAD_COND _("Instruction is not conditional")
1160 #define ERR_NO_ACCUM _("acc0 expected")
1162 static struct hash_control
* arm_ops_hsh
= NULL
;
1163 static struct hash_control
* arm_tops_hsh
= NULL
;
1164 static struct hash_control
* arm_cond_hsh
= NULL
;
1165 static struct hash_control
* arm_shift_hsh
= NULL
;
1166 static struct hash_control
* arm_reg_hsh
= NULL
;
1167 static struct hash_control
* arm_psr_hsh
= NULL
;
1169 /* This table describes all the machine specific pseudo-ops the assembler
1170 has to support. The fields are:
1171 pseudo-op name without dot
1172 function to call to execute this pseudo-op
1173 Integer arg to pass to the function. */
1175 static void s_req
PARAMS ((int));
1176 static void s_align
PARAMS ((int));
1177 static void s_bss
PARAMS ((int));
1178 static void s_even
PARAMS ((int));
1179 static void s_ltorg
PARAMS ((int));
1180 static void s_arm
PARAMS ((int));
1181 static void s_thumb
PARAMS ((int));
1182 static void s_code
PARAMS ((int));
1183 static void s_force_thumb
PARAMS ((int));
1184 static void s_thumb_func
PARAMS ((int));
1185 static void s_thumb_set
PARAMS ((int));
1186 static void arm_s_text
PARAMS ((int));
1187 static void arm_s_data
PARAMS ((int));
1189 static void arm_s_section
PARAMS ((int));
1190 static void s_arm_elf_cons
PARAMS ((int));
1193 static int my_get_expression
PARAMS ((expressionS
*, char **));
1195 CONST pseudo_typeS md_pseudo_table
[] =
1197 /* Never called becasue '.req' does not start line. */
1198 { "req", s_req
, 0 },
1199 { "bss", s_bss
, 0 },
1200 { "align", s_align
, 0 },
1201 { "arm", s_arm
, 0 },
1202 { "thumb", s_thumb
, 0 },
1203 { "code", s_code
, 0 },
1204 { "force_thumb", s_force_thumb
, 0 },
1205 { "thumb_func", s_thumb_func
, 0 },
1206 { "thumb_set", s_thumb_set
, 0 },
1207 { "even", s_even
, 0 },
1208 { "ltorg", s_ltorg
, 0 },
1209 { "pool", s_ltorg
, 0 },
1210 /* Allow for the effect of section changes. */
1211 { "text", arm_s_text
, 0 },
1212 { "data", arm_s_data
, 0 },
1214 { "section", arm_s_section
, 0 },
1215 { "section.s", arm_s_section
, 0 },
1216 { "sect", arm_s_section
, 0 },
1217 { "sect.s", arm_s_section
, 0 },
1218 { "word", s_arm_elf_cons
, 4 },
1219 { "long", s_arm_elf_cons
, 4 },
1220 { "file", dwarf2_directive_file
, 0 },
1221 { "loc", dwarf2_directive_loc
, 0 },
1225 { "extend", float_cons
, 'x' },
1226 { "ldouble", float_cons
, 'x' },
1227 { "packed", float_cons
, 'p' },
1231 /* Stuff needed to resolve the label ambiguity
1241 symbolS
* last_label_seen
;
1242 static int label_is_thumb_function_name
= false;
1244 /* Literal stuff. */
1246 #define MAX_LITERAL_POOL_SIZE 1024
1248 typedef struct literalS
1250 struct expressionS exp
;
1251 struct arm_it
* inst
;
1254 literalT literals
[MAX_LITERAL_POOL_SIZE
];
1256 /* Next free entry in the pool. */
1257 int next_literal_pool_place
= 0;
1259 /* Next literal pool number. */
1260 int lit_pool_num
= 1;
1262 symbolS
* current_poolP
= NULL
;
1269 if (current_poolP
== NULL
)
1270 current_poolP
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1271 (valueT
) 0, &zero_address_frag
);
1273 /* Check if this literal value is already in the pool: */
1274 while (lit_count
< next_literal_pool_place
)
1276 if (literals
[lit_count
].exp
.X_op
== inst
.reloc
.exp
.X_op
1277 && inst
.reloc
.exp
.X_op
== O_constant
1278 && (literals
[lit_count
].exp
.X_add_number
1279 == inst
.reloc
.exp
.X_add_number
)
1280 && literals
[lit_count
].exp
.X_unsigned
== inst
.reloc
.exp
.X_unsigned
)
1283 if (literals
[lit_count
].exp
.X_op
== inst
.reloc
.exp
.X_op
1284 && inst
.reloc
.exp
.X_op
== O_symbol
1285 && (literals
[lit_count
].exp
.X_add_number
1286 == inst
.reloc
.exp
.X_add_number
)
1287 && (literals
[lit_count
].exp
.X_add_symbol
1288 == inst
.reloc
.exp
.X_add_symbol
)
1289 && (literals
[lit_count
].exp
.X_op_symbol
1290 == inst
.reloc
.exp
.X_op_symbol
))
1296 if (lit_count
== next_literal_pool_place
) /* New entry. */
1298 if (next_literal_pool_place
> MAX_LITERAL_POOL_SIZE
)
1300 inst
.error
= _("Literal Pool Overflow");
1304 literals
[next_literal_pool_place
].exp
= inst
.reloc
.exp
;
1305 lit_count
= next_literal_pool_place
++;
1308 inst
.reloc
.exp
.X_op
= O_symbol
;
1309 inst
.reloc
.exp
.X_add_number
= (lit_count
) * 4 - 8;
1310 inst
.reloc
.exp
.X_add_symbol
= current_poolP
;
1315 /* Can't use symbol_new here, so have to create a symbol and then at
1316 a later date assign it a value. Thats what these functions do. */
1319 symbol_locate (symbolP
, name
, segment
, valu
, frag
)
1321 CONST
char * name
; /* It is copied, the caller can modify. */
1322 segT segment
; /* Segment identifier (SEG_<something>). */
1323 valueT valu
; /* Symbol value. */
1324 fragS
* frag
; /* Associated fragment. */
1326 unsigned int name_length
;
1327 char * preserved_copy_of_name
;
1329 name_length
= strlen (name
) + 1; /* +1 for \0. */
1330 obstack_grow (¬es
, name
, name_length
);
1331 preserved_copy_of_name
= obstack_finish (¬es
);
1332 #ifdef STRIP_UNDERSCORE
1333 if (preserved_copy_of_name
[0] == '_')
1334 preserved_copy_of_name
++;
1337 #ifdef tc_canonicalize_symbol_name
1338 preserved_copy_of_name
=
1339 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1342 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1344 S_SET_SEGMENT (symbolP
, segment
);
1345 S_SET_VALUE (symbolP
, valu
);
1346 symbol_clear_list_pointers(symbolP
);
1348 symbol_set_frag (symbolP
, frag
);
1350 /* Link to end of symbol chain. */
1352 extern int symbol_table_frozen
;
1353 if (symbol_table_frozen
)
1357 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
1359 obj_symbol_new_hook (symbolP
);
1361 #ifdef tc_symbol_new_hook
1362 tc_symbol_new_hook (symbolP
);
1366 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1367 #endif /* DEBUG_SYMS */
1370 /* Check that an immediate is valid.
1371 If so, convert it to the right format. */
1374 validate_immediate (val
)
1380 #define rotate_left(v, n) (v << n | v >> (32 - n))
1382 for (i
= 0; i
< 32; i
+= 2)
1383 if ((a
= rotate_left (val
, i
)) <= 0xff)
1384 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
1389 /* Check to see if an immediate can be computed as two seperate immediate
1390 values, added together. We already know that this value cannot be
1391 computed by just one ARM instruction. */
1394 validate_immediate_twopart (val
, highpart
)
1396 unsigned int * highpart
;
1401 for (i
= 0; i
< 32; i
+= 2)
1402 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
1408 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
1410 else if (a
& 0xff0000)
1414 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
1418 assert (a
& 0xff000000);
1419 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
1422 return (a
& 0xff) | (i
<< 7);
1429 validate_offset_imm (val
, hwse
)
1433 if ((hwse
&& val
> 255) || val
> 4095)
1440 int a ATTRIBUTE_UNUSED
;
1442 as_bad (_("Invalid syntax for .req directive."));
1447 int ignore ATTRIBUTE_UNUSED
;
1449 /* We don't support putting frags in the BSS segment, we fake it by
1450 marking in_bss, then looking at s_skip for clues. */
1451 subseg_set (bss_section
, 0);
1452 demand_empty_rest_of_line ();
1457 int ignore ATTRIBUTE_UNUSED
;
1459 /* Never make frag if expect extra pass. */
1461 frag_align (1, 0, 0);
1463 record_alignment (now_seg
, 1);
1465 demand_empty_rest_of_line ();
1470 int ignored ATTRIBUTE_UNUSED
;
1475 if (current_poolP
== NULL
)
1478 /* Align pool as you have word accesses.
1479 Only make a frag if we have to. */
1481 frag_align (2, 0, 0);
1483 record_alignment (now_seg
, 2);
1485 sprintf (sym_name
, "$$lit_\002%x", lit_pool_num
++);
1487 symbol_locate (current_poolP
, sym_name
, now_seg
,
1488 (valueT
) frag_now_fix (), frag_now
);
1489 symbol_table_insert (current_poolP
);
1491 ARM_SET_THUMB (current_poolP
, thumb_mode
);
1493 #if defined OBJ_COFF || defined OBJ_ELF
1494 ARM_SET_INTERWORK (current_poolP
, support_interwork
);
1497 while (lit_count
< next_literal_pool_place
)
1498 /* First output the expression in the instruction to the pool. */
1499 emit_expr (&(literals
[lit_count
++].exp
), 4); /* .word */
1501 next_literal_pool_place
= 0;
1502 current_poolP
= NULL
;
1505 /* Same as s_align_ptwo but align 0 => align 2. */
1509 int unused ATTRIBUTE_UNUSED
;
1512 register long temp_fill
;
1513 long max_alignment
= 15;
1515 temp
= get_absolute_expression ();
1516 if (temp
> max_alignment
)
1517 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
1520 as_bad (_("Alignment negative. 0 assumed."));
1524 if (*input_line_pointer
== ',')
1526 input_line_pointer
++;
1527 temp_fill
= get_absolute_expression ();
1535 /* Only make a frag if we HAVE to. */
1536 if (temp
&& !need_pass_2
)
1537 frag_align (temp
, (int) temp_fill
, 0);
1538 demand_empty_rest_of_line ();
1540 record_alignment (now_seg
, temp
);
1544 s_force_thumb (ignore
)
1545 int ignore ATTRIBUTE_UNUSED
;
1547 /* If we are not already in thumb mode go into it, EVEN if
1548 the target processor does not support thumb instructions.
1549 This is used by gcc/config/arm/lib1funcs.asm for example
1550 to compile interworking support functions even if the
1551 target processor should not support interworking. */
1556 record_alignment (now_seg
, 1);
1559 demand_empty_rest_of_line ();
1563 s_thumb_func (ignore
)
1564 int ignore ATTRIBUTE_UNUSED
;
1569 /* The following label is the name/address of the start of a Thumb function.
1570 We need to know this for the interworking support. */
1571 label_is_thumb_function_name
= true;
1573 demand_empty_rest_of_line ();
1576 /* Perform a .set directive, but also mark the alias as
1577 being a thumb function. */
1583 /* XXX the following is a duplicate of the code for s_set() in read.c
1584 We cannot just call that code as we need to get at the symbol that
1586 register char * name
;
1587 register char delim
;
1588 register char * end_name
;
1589 register symbolS
* symbolP
;
1591 /* Especial apologies for the random logic:
1592 This just grew, and could be parsed much more simply!
1594 name
= input_line_pointer
;
1595 delim
= get_symbol_end ();
1596 end_name
= input_line_pointer
;
1601 if (*input_line_pointer
!= ',')
1604 as_bad (_("Expected comma after name \"%s\""), name
);
1606 ignore_rest_of_line ();
1610 input_line_pointer
++;
1613 if (name
[0] == '.' && name
[1] == '\0')
1615 /* XXX - this should not happen to .thumb_set. */
1619 if ((symbolP
= symbol_find (name
)) == NULL
1620 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
1623 /* When doing symbol listings, play games with dummy fragments living
1624 outside the normal fragment chain to record the file and line info
1626 if (listing
& LISTING_SYMBOLS
)
1628 extern struct list_info_struct
* listing_tail
;
1629 fragS
* dummy_frag
= (fragS
*) xmalloc (sizeof (fragS
));
1631 memset (dummy_frag
, 0, sizeof (fragS
));
1632 dummy_frag
->fr_type
= rs_fill
;
1633 dummy_frag
->line
= listing_tail
;
1634 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
1635 dummy_frag
->fr_symbol
= symbolP
;
1639 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
1642 /* "set" symbols are local unless otherwise specified. */
1643 SF_SET_LOCAL (symbolP
);
1644 #endif /* OBJ_COFF */
1645 } /* Make a new symbol. */
1647 symbol_table_insert (symbolP
);
1652 && S_IS_DEFINED (symbolP
)
1653 && S_GET_SEGMENT (symbolP
) != reg_section
)
1654 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
1656 pseudo_set (symbolP
);
1658 demand_empty_rest_of_line ();
1660 /* XXX Now we come to the Thumb specific bit of code. */
1662 THUMB_SET_FUNC (symbolP
, 1);
1663 ARM_SET_THUMB (symbolP
, 1);
1664 #if defined OBJ_ELF || defined OBJ_COFF
1665 ARM_SET_INTERWORK (symbolP
, support_interwork
);
1669 /* If we change section we must dump the literal pool first. */
1675 if (now_seg
!= text_section
)
1679 obj_elf_text (ignore
);
1689 if (flag_readonly_data_in_text
)
1691 if (now_seg
!= text_section
)
1694 else if (now_seg
!= data_section
)
1698 obj_elf_data (ignore
);
1706 arm_s_section (ignore
)
1711 obj_elf_section (ignore
);
1716 opcode_select (width
)
1724 if (! (cpu_variant
& ARM_EXT_THUMB
))
1725 as_bad (_("selected processor does not support THUMB opcodes"));
1728 /* No need to force the alignment, since we will have been
1729 coming from ARM mode, which is word-aligned. */
1730 record_alignment (now_seg
, 1);
1737 if ((cpu_variant
& ARM_ANY
) == ARM_EXT_THUMB
)
1738 as_bad (_("selected processor does not support ARM opcodes"));
1743 frag_align (2, 0, 0);
1745 record_alignment (now_seg
, 1);
1750 as_bad (_("invalid instruction size selected (%d)"), width
);
1756 int ignore ATTRIBUTE_UNUSED
;
1759 demand_empty_rest_of_line ();
1764 int ignore ATTRIBUTE_UNUSED
;
1767 demand_empty_rest_of_line ();
1772 int unused ATTRIBUTE_UNUSED
;
1776 temp
= get_absolute_expression ();
1781 opcode_select (temp
);
1785 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
1793 skip_whitespace (str
);
1796 inst
.error
= _("Garbage following instruction");
1800 skip_past_comma (str
)
1803 char * p
= * str
, c
;
1806 while ((c
= *p
) == ' ' || c
== ',')
1809 if (c
== ',' && comma
++)
1817 return comma
? SUCCESS
: FAIL
;
1820 /* A standard register must be given at this point.
1821 SHIFT is the place to put it in inst.instruction.
1822 Restores input start point on error.
1823 Returns the reg#, or FAIL. */
1826 reg_required_here (str
, shift
)
1830 static char buff
[128]; /* XXX */
1832 char * start
= * str
;
1834 if ((reg
= arm_reg_parse (str
)) != FAIL
&& int_register (reg
))
1837 inst
.instruction
|= reg
<< shift
;
1841 /* Restore the start point, we may have got a reg of the wrong class. */
1844 /* In the few cases where we might be able to accept something else
1845 this error can be overridden. */
1846 sprintf (buff
, _("Register expected, not '%.100s'"), start
);
1852 static CONST
struct asm_psr
*
1854 register char ** ccp
;
1856 char * start
= * ccp
;
1859 CONST
struct asm_psr
* psr
;
1863 /* Skip to the end of the next word in the input stream. */
1868 while (isalpha (c
) || c
== '_');
1870 /* Terminate the word. */
1873 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
1874 feature for ease of use and backwards compatibility. */
1875 if (!strncmp (start
, "cpsr", 4))
1876 strncpy (start
, "CPSR", 4);
1877 else if (!strncmp (start
, "spsr", 4))
1878 strncpy (start
, "SPSR", 4);
1880 /* Now locate the word in the psr hash table. */
1881 psr
= (CONST
struct asm_psr
*) hash_find (arm_psr_hsh
, start
);
1883 /* Restore the input stream. */
1886 /* If we found a valid match, advance the
1887 stream pointer past the end of the word. */
1893 /* Parse the input looking for a PSR flag. */
1896 psr_required_here (str
)
1899 char * start
= * str
;
1900 CONST
struct asm_psr
* psr
;
1902 psr
= arm_psr_parse (str
);
1906 /* If this is the SPSR that is being modified, set the R bit. */
1908 inst
.instruction
|= SPSR_BIT
;
1910 /* Set the psr flags in the MSR instruction. */
1911 inst
.instruction
|= psr
->field
<< PSR_SHIFT
;
1916 /* In the few cases where we might be able to accept
1917 something else this error can be overridden. */
1918 inst
.error
= _("flag for {c}psr instruction expected");
1920 /* Restore the start point. */
1926 co_proc_number (str
)
1929 int processor
, pchar
;
1931 skip_whitespace (* str
);
1933 /* The data sheet seems to imply that just a number on its own is valid
1934 here, but the RISC iX assembler seems to accept a prefix 'p'. We will
1936 if (**str
== 'p' || **str
== 'P')
1940 if (pchar
>= '0' && pchar
<= '9')
1942 processor
= pchar
- '0';
1943 if (**str
>= '0' && **str
<= '9')
1945 processor
= processor
* 10 + *(*str
)++ - '0';
1948 inst
.error
= _("Illegal co-processor number");
1955 inst
.error
= _("Bad or missing co-processor number");
1959 inst
.instruction
|= processor
<< 8;
1964 cp_opc_expr (str
, where
, length
)
1971 skip_whitespace (* str
);
1973 memset (&expr
, '\0', sizeof (expr
));
1975 if (my_get_expression (&expr
, str
))
1977 if (expr
.X_op
!= O_constant
)
1979 inst
.error
= _("bad or missing expression");
1983 if ((expr
.X_add_number
& ((1 << length
) - 1)) != expr
.X_add_number
)
1985 inst
.error
= _("immediate co-processor expression too large");
1989 inst
.instruction
|= expr
.X_add_number
<< where
;
1994 cp_reg_required_here (str
, where
)
1999 char * start
= *str
;
2001 if ((reg
= arm_reg_parse (str
)) != FAIL
&& cp_register (reg
))
2004 inst
.instruction
|= reg
<< where
;
2008 /* In the few cases where we might be able to accept something else
2009 this error can be overridden. */
2010 inst
.error
= _("Co-processor register expected");
2012 /* Restore the start point. */
2018 fp_reg_required_here (str
, where
)
2023 char * start
= * str
;
2025 if ((reg
= arm_reg_parse (str
)) != FAIL
&& fp_register (reg
))
2028 inst
.instruction
|= reg
<< where
;
2032 /* In the few cases where we might be able to accept something else
2033 this error can be overridden. */
2034 inst
.error
= _("Floating point register expected");
2036 /* Restore the start point. */
2042 cp_address_offset (str
)
2047 skip_whitespace (* str
);
2049 if (! is_immediate_prefix (**str
))
2051 inst
.error
= _("immediate expression expected");
2057 if (my_get_expression (& inst
.reloc
.exp
, str
))
2060 if (inst
.reloc
.exp
.X_op
== O_constant
)
2062 offset
= inst
.reloc
.exp
.X_add_number
;
2066 inst
.error
= _("co-processor address must be word aligned");
2070 if (offset
> 1023 || offset
< -1023)
2072 inst
.error
= _("offset too large");
2077 inst
.instruction
|= INDEX_UP
;
2081 inst
.instruction
|= offset
>> 2;
2084 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
2090 cp_address_required_here (str
)
2102 skip_whitespace (p
);
2104 if ((reg
= reg_required_here (& p
, 16)) == FAIL
)
2107 skip_whitespace (p
);
2113 if (skip_past_comma (& p
) == SUCCESS
)
2116 write_back
= WRITE_BACK
;
2120 inst
.error
= _("pc may not be used in post-increment");
2124 if (cp_address_offset (& p
) == FAIL
)
2128 pre_inc
= PRE_INDEX
| INDEX_UP
;
2132 /* '['Rn, #expr']'[!] */
2134 if (skip_past_comma (& p
) == FAIL
)
2136 inst
.error
= _("pre-indexed expression expected");
2140 pre_inc
= PRE_INDEX
;
2142 if (cp_address_offset (& p
) == FAIL
)
2145 skip_whitespace (p
);
2149 inst
.error
= _("missing ]");
2153 skip_whitespace (p
);
2159 inst
.error
= _("pc may not be used with write-back");
2164 write_back
= WRITE_BACK
;
2170 if (my_get_expression (&inst
.reloc
.exp
, &p
))
2173 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
2174 inst
.reloc
.exp
.X_add_number
-= 8; /* PC rel adjust. */
2175 inst
.reloc
.pc_rel
= 1;
2176 inst
.instruction
|= (REG_PC
<< 16);
2177 pre_inc
= PRE_INDEX
;
2180 inst
.instruction
|= write_back
| pre_inc
;
2188 unsigned long flags
;
2190 /* Do nothing really. */
2191 inst
.instruction
|= flags
; /* This is pointless. */
2199 unsigned long flags
;
2203 /* Only one syntax. */
2204 skip_whitespace (str
);
2206 if (reg_required_here (&str
, 12) == FAIL
)
2208 inst
.error
= BAD_ARGS
;
2212 if (skip_past_comma (&str
) == FAIL
)
2214 inst
.error
= _("comma expected after register name");
2218 skip_whitespace (str
);
2220 if ( strcmp (str
, "CPSR") == 0
2221 || strcmp (str
, "SPSR") == 0
2222 /* Lower case versions for backwards compatability. */
2223 || strcmp (str
, "cpsr") == 0
2224 || strcmp (str
, "spsr") == 0)
2227 /* This is for backwards compatability with older toolchains. */
2228 else if ( strcmp (str
, "cpsr_all") == 0
2229 || strcmp (str
, "spsr_all") == 0)
2233 inst
.error
= _("{C|S}PSR expected");
2237 if (* str
== 's' || * str
== 'S')
2238 inst
.instruction
|= SPSR_BIT
;
2241 inst
.instruction
|= flags
;
2245 /* Two possible forms:
2246 "{C|S}PSR_<field>, Rm",
2247 "{C|S}PSR_f, #expression". */
2252 unsigned long flags
;
2254 skip_whitespace (str
);
2256 if (psr_required_here (& str
) == FAIL
)
2259 if (skip_past_comma (& str
) == FAIL
)
2261 inst
.error
= _("comma missing after psr flags");
2265 skip_whitespace (str
);
2267 if (reg_required_here (& str
, 0) != FAIL
)
2270 inst
.instruction
|= flags
;
2275 if (! is_immediate_prefix (* str
))
2278 _("only a register or immediate value can follow a psr flag");
2285 if (my_get_expression (& inst
.reloc
.exp
, & str
))
2288 _("only a register or immediate value can follow a psr flag");
2292 if ((cpu_variant
& ARM_EXT_V5
) != ARM_EXT_V5
2293 && inst
.instruction
& ((PSR_c
| PSR_x
| PSR_s
) << PSR_SHIFT
))
2295 inst
.error
= _("immediate value cannot be used to set this field");
2299 flags
|= INST_IMMEDIATE
;
2301 if (inst
.reloc
.exp
.X_add_symbol
)
2303 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
2304 inst
.reloc
.pc_rel
= 0;
2308 unsigned value
= validate_immediate (inst
.reloc
.exp
.X_add_number
);
2310 if (value
== (unsigned) FAIL
)
2312 inst
.error
= _("Invalid constant");
2316 inst
.instruction
|= value
;
2320 inst
.instruction
|= flags
;
2324 /* Long Multiply Parser
2325 UMULL RdLo, RdHi, Rm, Rs
2326 SMULL RdLo, RdHi, Rm, Rs
2327 UMLAL RdLo, RdHi, Rm, Rs
2328 SMLAL RdLo, RdHi, Rm, Rs. */
2331 do_mull (str
, flags
)
2333 unsigned long flags
;
2335 int rdlo
, rdhi
, rm
, rs
;
2337 /* Only one format "rdlo, rdhi, rm, rs". */
2338 skip_whitespace (str
);
2340 if ((rdlo
= reg_required_here (&str
, 12)) == FAIL
)
2342 inst
.error
= BAD_ARGS
;
2346 if (skip_past_comma (&str
) == FAIL
2347 || (rdhi
= reg_required_here (&str
, 16)) == FAIL
)
2349 inst
.error
= BAD_ARGS
;
2353 if (skip_past_comma (&str
) == FAIL
2354 || (rm
= reg_required_here (&str
, 0)) == FAIL
)
2356 inst
.error
= BAD_ARGS
;
2360 /* rdhi, rdlo and rm must all be different. */
2361 if (rdlo
== rdhi
|| rdlo
== rm
|| rdhi
== rm
)
2362 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
2364 if (skip_past_comma (&str
) == FAIL
2365 || (rs
= reg_required_here (&str
, 8)) == FAIL
)
2367 inst
.error
= BAD_ARGS
;
2371 if (rdhi
== REG_PC
|| rdhi
== REG_PC
|| rdhi
== REG_PC
|| rdhi
== REG_PC
)
2373 inst
.error
= BAD_PC
;
2377 inst
.instruction
|= flags
;
2385 unsigned long flags
;
2389 /* Only one format "rd, rm, rs". */
2390 skip_whitespace (str
);
2392 if ((rd
= reg_required_here (&str
, 16)) == FAIL
)
2394 inst
.error
= BAD_ARGS
;
2400 inst
.error
= BAD_PC
;
2404 if (skip_past_comma (&str
) == FAIL
2405 || (rm
= reg_required_here (&str
, 0)) == FAIL
)
2407 inst
.error
= BAD_ARGS
;
2413 inst
.error
= BAD_PC
;
2418 as_tsktsk (_("rd and rm should be different in mul"));
2420 if (skip_past_comma (&str
) == FAIL
2421 || (rm
= reg_required_here (&str
, 8)) == FAIL
)
2423 inst
.error
= BAD_ARGS
;
2429 inst
.error
= BAD_PC
;
2433 inst
.instruction
|= flags
;
2441 unsigned long flags
;
2445 /* Only one format "rd, rm, rs, rn". */
2446 skip_whitespace (str
);
2448 if ((rd
= reg_required_here (&str
, 16)) == FAIL
)
2450 inst
.error
= BAD_ARGS
;
2456 inst
.error
= BAD_PC
;
2460 if (skip_past_comma (&str
) == FAIL
2461 || (rm
= reg_required_here (&str
, 0)) == FAIL
)
2463 inst
.error
= BAD_ARGS
;
2469 inst
.error
= BAD_PC
;
2474 as_tsktsk (_("rd and rm should be different in mla"));
2476 if (skip_past_comma (&str
) == FAIL
2477 || (rd
= reg_required_here (&str
, 8)) == FAIL
2478 || skip_past_comma (&str
) == FAIL
2479 || (rm
= reg_required_here (&str
, 12)) == FAIL
)
2481 inst
.error
= BAD_ARGS
;
2485 if (rd
== REG_PC
|| rm
== REG_PC
)
2487 inst
.error
= BAD_PC
;
2491 inst
.instruction
|= flags
;
2496 /* Expects *str -> the characters "acc0", possibly with leading blanks.
2497 Advances *str to the next non-alphanumeric.
2498 Returns 0, or else FAIL (in which case sets inst.error).
2500 (In a future XScale, there may be accumulators other than zero.
2501 At that time this routine and its callers can be upgraded to suit.) */
2504 accum0_required_here (str
)
2507 static char buff
[128]; /* Note the address is taken. Hence, static. */
2510 int result
= 0; /* The accum number. */
2512 skip_whitespace (p
);
2514 *str
= p
; /* Advance caller's string pointer too. */
2519 *--p
= 0; /* Aap nul into input buffer at non-alnum. */
2521 if (! ( streq (*str
, "acc0") || streq (*str
, "ACC0")))
2523 sprintf (buff
, _("acc0 expected, not '%.100s'"), *str
);
2528 *p
= c
; /* Unzap. */
2529 *str
= p
; /* Caller's string pointer to after match. */
2533 /* Expects **str -> after a comma. May be leading blanks.
2534 Advances *str, recognizing a load mode, and setting inst.instruction.
2535 Returns rn, or else FAIL (in which case may set inst.error
2536 and not advance str)
2538 Note: doesn't know Rd, so no err checks that require such knowledge. */
2541 ld_mode_required_here (string
)
2544 char * str
= * string
;
2548 skip_whitespace (str
);
2554 skip_whitespace (str
);
2556 if ((rn
= reg_required_here (& str
, 16)) == FAIL
)
2559 skip_whitespace (str
);
2565 if (skip_past_comma (& str
) == SUCCESS
)
2567 /* [Rn],... (post inc) */
2568 if (ldst_extend (& str
, 1) == FAIL
)
2573 skip_whitespace (str
);
2578 inst
.instruction
|= WRITE_BACK
;
2581 inst
.instruction
|= INDEX_UP
| HWOFFSET_IMM
;
2587 if (skip_past_comma (& str
) == FAIL
)
2589 inst
.error
= _("pre-indexed expression expected");
2595 if (ldst_extend (& str
, 1) == FAIL
)
2598 skip_whitespace (str
);
2600 if (* str
++ != ']')
2602 inst
.error
= _("missing ]");
2606 skip_whitespace (str
);
2611 inst
.instruction
|= WRITE_BACK
;
2615 else if (* str
== '=') /* ldr's "r,=label" syntax */
2616 /* We should never reach here, because <text> = <expression> is
2617 caught gas/read.c read_a_source_file() as a .set operation. */
2619 else /* PC +- 8 bit immediate offset. */
2621 if (my_get_expression (& inst
.reloc
.exp
, & str
))
2624 inst
.instruction
|= HWOFFSET_IMM
; /* The I bit. */
2625 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
2626 inst
.reloc
.exp
.X_add_number
-= 8; /* PC rel adjust. */
2627 inst
.reloc
.pc_rel
= 1;
2628 inst
.instruction
|= (REG_PC
<< 16);
2634 inst
.instruction
|= (pre_inc
? PRE_INDEX
: 0);
2640 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
2641 SMLAxy{cond} Rd,Rm,Rs,Rn
2642 SMLAWy{cond} Rd,Rm,Rs,Rn
2643 Error if any register is R15. */
2646 do_smla (str
, flags
)
2648 unsigned long flags
;
2652 skip_whitespace (str
);
2654 if ((rd
= reg_required_here (& str
, 16)) == FAIL
2655 || skip_past_comma (& str
) == FAIL
2656 || (rm
= reg_required_here (& str
, 0)) == FAIL
2657 || skip_past_comma (& str
) == FAIL
2658 || (rs
= reg_required_here (& str
, 8)) == FAIL
2659 || skip_past_comma (& str
) == FAIL
2660 || (rn
= reg_required_here (& str
, 12)) == FAIL
)
2661 inst
.error
= BAD_ARGS
;
2663 else if (rd
== REG_PC
|| rm
== REG_PC
|| rs
== REG_PC
|| rn
== REG_PC
)
2664 inst
.error
= BAD_PC
;
2667 inst
.error
= BAD_FLAGS
;
2673 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
2674 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
2675 Error if any register is R15.
2676 Warning if Rdlo == Rdhi. */
2679 do_smlal (str
, flags
)
2681 unsigned long flags
;
2683 int rdlo
, rdhi
, rm
, rs
;
2685 skip_whitespace (str
);
2687 if ((rdlo
= reg_required_here (& str
, 12)) == FAIL
2688 || skip_past_comma (& str
) == FAIL
2689 || (rdhi
= reg_required_here (& str
, 16)) == FAIL
2690 || skip_past_comma (& str
) == FAIL
2691 || (rm
= reg_required_here (& str
, 0)) == FAIL
2692 || skip_past_comma (& str
) == FAIL
2693 || (rs
= reg_required_here (& str
, 8)) == FAIL
)
2695 inst
.error
= BAD_ARGS
;
2699 if (rdlo
== REG_PC
|| rdhi
== REG_PC
|| rm
== REG_PC
|| rs
== REG_PC
)
2701 inst
.error
= BAD_PC
;
2706 as_tsktsk (_("rdhi and rdlo must be different"));
2709 inst
.error
= BAD_FLAGS
;
2714 /* ARM V5E (El Segundo) signed-multiply (argument parse)
2715 SMULxy{cond} Rd,Rm,Rs
2716 Error if any register is R15. */
2719 do_smul (str
, flags
)
2721 unsigned long flags
;
2725 skip_whitespace (str
);
2727 if ((rd
= reg_required_here (& str
, 16)) == FAIL
2728 || skip_past_comma (& str
) == FAIL
2729 || (rm
= reg_required_here (& str
, 0)) == FAIL
2730 || skip_past_comma (& str
) == FAIL
2731 || (rs
= reg_required_here (& str
, 8)) == FAIL
)
2732 inst
.error
= BAD_ARGS
;
2734 else if (rd
== REG_PC
|| rm
== REG_PC
|| rs
== REG_PC
)
2735 inst
.error
= BAD_PC
;
2738 inst
.error
= BAD_FLAGS
;
2744 /* ARM V5E (El Segundo) saturating-add/subtract (argument parse)
2745 Q[D]{ADD,SUB}{cond} Rd,Rm,Rn
2746 Error if any register is R15. */
2749 do_qadd (str
, flags
)
2751 unsigned long flags
;
2755 skip_whitespace (str
);
2757 if ((rd
= reg_required_here (& str
, 12)) == FAIL
2758 || skip_past_comma (& str
) == FAIL
2759 || (rm
= reg_required_here (& str
, 0)) == FAIL
2760 || skip_past_comma (& str
) == FAIL
2761 || (rn
= reg_required_here (& str
, 16)) == FAIL
)
2762 inst
.error
= BAD_ARGS
;
2764 else if (rd
== REG_PC
|| rm
== REG_PC
|| rn
== REG_PC
)
2765 inst
.error
= BAD_PC
;
2768 inst
.error
= BAD_FLAGS
;
2774 /* ARM V5E (el Segundo)
2775 MCRRcc <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
2776 MRRCcc <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
2778 These are equivalent to the XScale instructions MAR and MRA,
2779 respectively, when coproc == 0, opcode == 0, and CRm == 0.
2781 Result unpredicatable if Rd or Rn is R15. */
2784 do_co_reg2c (str
, flags
)
2786 unsigned long flags
;
2790 skip_whitespace (str
);
2792 if (co_proc_number (& str
) == FAIL
)
2795 inst
.error
= BAD_ARGS
;
2799 if (skip_past_comma (& str
) == FAIL
2800 || cp_opc_expr (& str
, 4, 4) == FAIL
)
2803 inst
.error
= BAD_ARGS
;
2807 if (skip_past_comma (& str
) == FAIL
2808 || (rd
= reg_required_here (& str
, 12)) == FAIL
)
2811 inst
.error
= BAD_ARGS
;
2815 if (skip_past_comma (& str
) == FAIL
2816 || (rn
= reg_required_here (& str
, 16)) == FAIL
)
2819 inst
.error
= BAD_ARGS
;
2823 /* Unpredictable result if rd or rn is R15. */
2824 if (rd
== REG_PC
|| rn
== REG_PC
)
2826 (_("Warning: Instruction unpredictable when using r15"));
2828 if (skip_past_comma (& str
) == FAIL
2829 || cp_reg_required_here (& str
, 0) == FAIL
)
2832 inst
.error
= BAD_ARGS
;
2837 inst
.error
= BAD_COND
;
2842 /* ARM V5 count-leading-zeroes instruction (argument parse)
2843 CLZ{<cond>} <Rd>, <Rm>
2844 Condition defaults to COND_ALWAYS.
2845 Error if Rd or Rm are R15. */
2850 unsigned long flags
;
2860 skip_whitespace (str
);
2862 if (((rd
= reg_required_here (& str
, 12)) == FAIL
)
2863 || (skip_past_comma (& str
) == FAIL
)
2864 || ((rm
= reg_required_here (& str
, 0)) == FAIL
))
2865 inst
.error
= BAD_ARGS
;
2867 else if (rd
== REG_PC
|| rm
== REG_PC
)
2868 inst
.error
= BAD_PC
;
2874 /* ARM V5 (argument parse)
2875 LDC2{L} <coproc>, <CRd>, <addressing mode>
2876 STC2{L} <coproc>, <CRd>, <addressing mode>
2877 Instruction is not conditional, and has 0xf in the codition field.
2878 Otherwise, it's the same as LDC/STC. */
2881 do_lstc2 (str
, flags
)
2883 unsigned long flags
;
2886 inst
.error
= BAD_COND
;
2888 skip_whitespace (str
);
2890 if (co_proc_number (& str
) == FAIL
)
2893 inst
.error
= BAD_ARGS
;
2895 else if (skip_past_comma (& str
) == FAIL
2896 || cp_reg_required_here (& str
, 12) == FAIL
)
2899 inst
.error
= BAD_ARGS
;
2901 else if (skip_past_comma (& str
) == FAIL
2902 || cp_address_required_here (& str
) == FAIL
)
2905 inst
.error
= BAD_ARGS
;
2911 /* ARM V5 (argument parse)
2912 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>, <opcode_2>
2913 Instruction is not conditional, and has 0xf in the condition field.
2914 Otherwise, it's the same as CDP. */
2917 do_cdp2 (str
, flags
)
2919 unsigned long flags
;
2921 skip_whitespace (str
);
2923 if (co_proc_number (& str
) == FAIL
)
2926 inst
.error
= BAD_ARGS
;
2930 if (skip_past_comma (& str
) == FAIL
2931 || cp_opc_expr (& str
, 20,4) == FAIL
)
2934 inst
.error
= BAD_ARGS
;
2938 if (skip_past_comma (& str
) == FAIL
2939 || cp_reg_required_here (& str
, 12) == FAIL
)
2942 inst
.error
= BAD_ARGS
;
2946 if (skip_past_comma (& str
) == FAIL
2947 || cp_reg_required_here (& str
, 16) == FAIL
)
2950 inst
.error
= BAD_ARGS
;
2954 if (skip_past_comma (& str
) == FAIL
2955 || cp_reg_required_here (& str
, 0) == FAIL
)
2958 inst
.error
= BAD_ARGS
;
2962 if (skip_past_comma (& str
) == SUCCESS
)
2964 if (cp_opc_expr (& str
, 5, 3) == FAIL
)
2967 inst
.error
= BAD_ARGS
;
2973 inst
.error
= BAD_FLAGS
;
2978 /* ARM V5 (argument parse)
2979 MCR2 <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>, <opcode_2>
2980 MRC2 <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>, <opcode_2>
2981 Instruction is not conditional, and has 0xf in the condition field.
2982 Otherwise, it's the same as MCR/MRC. */
2985 do_co_reg2 (str
, flags
)
2987 unsigned long flags
;
2989 skip_whitespace (str
);
2991 if (co_proc_number (& str
) == FAIL
)
2994 inst
.error
= BAD_ARGS
;
2998 if (skip_past_comma (& str
) == FAIL
2999 || cp_opc_expr (& str
, 21, 3) == FAIL
)
3002 inst
.error
= BAD_ARGS
;
3006 if (skip_past_comma (& str
) == FAIL
3007 || reg_required_here (& str
, 12) == FAIL
)
3010 inst
.error
= BAD_ARGS
;
3014 if (skip_past_comma (& str
) == FAIL
3015 || cp_reg_required_here (& str
, 16) == FAIL
)
3018 inst
.error
= BAD_ARGS
;
3022 if (skip_past_comma (& str
) == FAIL
3023 || cp_reg_required_here (& str
, 0) == FAIL
)
3026 inst
.error
= BAD_ARGS
;
3030 if (skip_past_comma (& str
) == SUCCESS
)
3032 if (cp_opc_expr (& str
, 5, 3) == FAIL
)
3035 inst
.error
= BAD_ARGS
;
3041 inst
.error
= BAD_COND
;
3046 /* THUMB V5 breakpoint instruction (argument parse)
3054 unsigned long number
;
3056 skip_whitespace (str
);
3058 /* Allow optional leading '#'. */
3059 if (is_immediate_prefix (*str
))
3062 memset (& expr
, '\0', sizeof (expr
));
3063 if (my_get_expression (& expr
, & str
) || (expr
.X_op
!= O_constant
))
3065 inst
.error
= _("bad or missing expression");
3069 number
= expr
.X_add_number
;
3071 /* Check it fits an 8 bit unsigned. */
3072 if (number
!= (number
& 0xff))
3074 inst
.error
= _("immediate value out of range");
3078 inst
.instruction
|= number
;
3083 /* ARM V5 branch-link-exchange (argument parse) for BLX(1) only.
3084 Expects inst.instruction is set for BLX(1).
3085 Note: this is cloned from do_branch, and the reloc changed to be a
3086 new one that can cope with setting one extra bit (the H bit). */
3089 do_branch25 (str
, flags
)
3091 unsigned long flags ATTRIBUTE_UNUSED
;
3093 if (my_get_expression (& inst
.reloc
.exp
, & str
))
3100 /* ScottB: February 5, 1998 */
3101 /* Check to see of PLT32 reloc required for the instruction. */
3103 /* arm_parse_reloc() works on input_line_pointer.
3104 We actually want to parse the operands to the branch instruction
3105 passed in 'str'. Save the input pointer and restore it later. */
3106 save_in
= input_line_pointer
;
3107 input_line_pointer
= str
;
3109 if (inst
.reloc
.exp
.X_op
== O_symbol
3111 && arm_parse_reloc () == BFD_RELOC_ARM_PLT32
)
3113 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
3114 inst
.reloc
.pc_rel
= 0;
3115 /* Modify str to point to after parsed operands, otherwise
3116 end_of_line() will complain about the (PLT) left in str. */
3117 str
= input_line_pointer
;
3121 inst
.reloc
.type
= BFD_RELOC_ARM_PCREL_BLX
;
3122 inst
.reloc
.pc_rel
= 1;
3125 input_line_pointer
= save_in
;
3128 inst
.reloc
.type
= BFD_RELOC_ARM_PCREL_BLX
;
3129 inst
.reloc
.pc_rel
= 1;
3130 #endif /* OBJ_ELF */
3135 /* ARM V5 branch-link-exchange instruction (argument parse)
3136 BLX <target_addr> ie BLX(1)
3137 BLX{<condition>} <Rm> ie BLX(2)
3138 Unfortunately, there are two different opcodes for this mnemonic.
3139 So, the insns[].value is not used, and the code here zaps values
3140 into inst.instruction.
3141 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
3146 unsigned long flags
;
3157 skip_whitespace (mystr
);
3158 rm
= reg_required_here (& mystr
, 0);
3160 /* The above may set inst.error. Ignore his opinion. */
3165 /* Arg is a register.
3166 Use the condition code our caller put in inst.instruction.
3167 Pass ourselves off as a BX with a funny opcode. */
3168 inst
.instruction
|= 0x012fff30;
3173 /* This must be is BLX <target address>, no condition allowed. */
3174 if (inst
.instruction
!= COND_ALWAYS
)
3176 inst
.error
= BAD_COND
;
3180 inst
.instruction
= 0xfafffffe;
3182 /* Process like a B/BL, but with a different reloc.
3183 Note that B/BL expecte fffffe, not 0, offset in the opcode table. */
3184 do_branch25 (str
, flags
);
3188 /* ARM V5 Thumb BLX (argument parse)
3189 BLX <target_addr> which is BLX(1)
3190 BLX <Rm> which is BLX(2)
3191 Unfortunately, there are two different opcodes for this mnemonic.
3192 So, the tinsns[].value is not used, and the code here zaps values
3193 into inst.instruction. */
3202 skip_whitespace (mystr
);
3203 inst
.instruction
= 0x4780;
3205 /* Note that this call is to the ARM register recognizer. BLX(2)
3206 uses the ARM register space, not the Thumb one, so a call to
3207 thumb_reg() would be wrong. */
3208 rm
= reg_required_here (& mystr
, 3);
3213 /* It's BLX(2). The .instruction was zapped with rm & is final. */
3218 /* No ARM register. This must be BLX(1). Change the .instruction. */
3219 inst
.instruction
= 0xf7ffeffe;
3222 if (my_get_expression (& inst
.reloc
.exp
, & mystr
))
3225 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
3226 inst
.reloc
.pc_rel
= 1;
3229 end_of_line (mystr
);
3232 /* ARM V5 breakpoint instruction (argument parse)
3233 BKPT <16 bit unsigned immediate>
3234 Instruction is not conditional.
3235 The bit pattern given in insns[] has the COND_ALWAYS condition,
3236 and it is an error if the caller tried to override that.
3237 Note "flags" is nonzero if a flag was supplied (which is an error). */
3240 do_bkpt (str
, flags
)
3242 unsigned long flags
;
3245 unsigned long number
;
3247 skip_whitespace (str
);
3249 /* Allow optional leading '#'. */
3250 if (is_immediate_prefix (* str
))
3253 memset (& expr
, '\0', sizeof (expr
));
3255 if (my_get_expression (& expr
, & str
) || (expr
.X_op
!= O_constant
))
3257 inst
.error
= _("bad or missing expression");
3261 number
= expr
.X_add_number
;
3263 /* Check it fits a 16 bit unsigned. */
3264 if (number
!= (number
& 0xffff))
3266 inst
.error
= _("immediate value out of range");
3270 /* Top 12 of 16 bits to bits 19:8. */
3271 inst
.instruction
|= (number
& 0xfff0) << 4;
3273 /* Bottom 4 of 16 bits to bits 3:0. */
3274 inst
.instruction
|= number
& 0xf;
3279 inst
.error
= BAD_FLAGS
;
3282 /* Xscale multiply-accumulate (argument parse)
3285 MIAxycc acc0,Rm,Rs. */
3290 unsigned long flags
;
3298 else if (accum0_required_here (& str
) == FAIL
)
3299 inst
.error
= ERR_NO_ACCUM
;
3301 else if (skip_past_comma (& str
) == FAIL
3302 || (rm
= reg_required_here (& str
, 0)) == FAIL
)
3303 inst
.error
= BAD_ARGS
;
3305 else if (skip_past_comma (& str
) == FAIL
3306 || (rs
= reg_required_here (& str
, 12)) == FAIL
)
3307 inst
.error
= BAD_ARGS
;
3309 /* inst.instruction has now been zapped with both rm and rs. */
3310 else if (rm
== REG_PC
|| rs
== REG_PC
)
3311 inst
.error
= BAD_PC
; /* Undefined result if rm or rs is R15. */
3317 /* Xscale move-accumulator-register (argument parse)
3319 MARcc acc0,RdLo,RdHi. */
3324 unsigned long flags
;
3331 else if (accum0_required_here (& str
) == FAIL
)
3332 inst
.error
= ERR_NO_ACCUM
;
3334 else if (skip_past_comma (& str
) == FAIL
3335 || (rdlo
= reg_required_here (& str
, 12)) == FAIL
)
3336 inst
.error
= BAD_ARGS
;
3338 else if (skip_past_comma (& str
) == FAIL
3339 || (rdhi
= reg_required_here (& str
, 16)) == FAIL
)
3340 inst
.error
= BAD_ARGS
;
3342 /* inst.instruction has now been zapped with both rdlo and rdhi. */
3343 else if (rdlo
== REG_PC
|| rdhi
== REG_PC
)
3344 inst
.error
= BAD_PC
; /* Undefined result if rdlo or rdhi is R15. */
3350 /* Xscale move-register-accumulator (argument parse)
3352 MRAcc RdLo,RdHi,acc0. */
3357 unsigned long flags
;
3368 skip_whitespace (str
);
3370 if ((rdlo
= reg_required_here (& str
, 12)) == FAIL
)
3371 inst
.error
= BAD_ARGS
;
3373 else if (skip_past_comma (& str
) == FAIL
3374 || (rdhi
= reg_required_here (& str
, 16)) == FAIL
)
3375 inst
.error
= BAD_ARGS
;
3377 else if (skip_past_comma (& str
) == FAIL
3378 || accum0_required_here (& str
) == FAIL
)
3379 inst
.error
= ERR_NO_ACCUM
;
3381 /* inst.instruction has now been zapped with both rdlo and rdhi. */
3382 else if (rdlo
== rdhi
)
3383 inst
.error
= BAD_ARGS
; /* Undefined result if 2 writes to same reg. */
3385 else if (rdlo
== REG_PC
|| rdhi
== REG_PC
)
3386 inst
.error
= BAD_PC
; /* Undefined result if rdlo or rdhi is R15. */
3391 /* Xscale: Preload-Cache
3395 Syntactically, like LDR with B=1, W=0, L=1. */
3400 unsigned long flags
;
3410 skip_whitespace (str
);
3414 inst
.error
= _("'[' expected after PLD mnemonic");
3419 skip_whitespace (str
);
3421 if ((rd
= reg_required_here (& str
, 16)) == FAIL
)
3424 skip_whitespace (str
);
3430 skip_whitespace (str
);
3432 if (skip_past_comma (& str
) == SUCCESS
)
3434 if (ldst_extend (& str
, 0) == FAIL
)
3437 else if (* str
== '!') /* [Rn]! */
3439 inst
.error
= _("writeback used in preload instruction");
3443 inst
.instruction
|= INDEX_UP
| PRE_INDEX
;
3445 else /* [Rn, ...] */
3447 if (skip_past_comma (& str
) == FAIL
)
3449 inst
.error
= _("pre-indexed expression expected");
3453 if (ldst_extend (& str
, 0) == FAIL
)
3456 skip_whitespace (str
);
3460 inst
.error
= _("missing ]");
3465 skip_whitespace (str
);
3467 if (* str
== '!') /* [Rn]! */
3469 inst
.error
= _("writeback used in preload instruction");
3473 inst
.instruction
|= PRE_INDEX
;
3479 /* Xscale load-consecutive (argument parse)
3486 do_ldrd (str
, flags
)
3488 unsigned long flags
;
3493 if (flags
!= DOUBLE_LOAD_FLAG
)
3495 /* Change instruction pattern to normal ldr/str. */
3496 if (inst
.instruction
& 0x20)
3497 inst
.instruction
= (inst
.instruction
& COND_MASK
) | 0x04000000; /* str */
3499 inst
.instruction
= (inst
.instruction
& COND_MASK
) | 0x04100000; /* ldr */
3501 /* Perform a normal load/store instruction parse. */
3502 do_ldst (str
, flags
);
3507 if ((cpu_variant
& ARM_EXT_XSCALE
) != ARM_EXT_XSCALE
)
3509 static char buff
[128];
3512 while (isspace (*str
))
3516 /* Deny all knowledge. */
3517 sprintf (buff
, _("bad instruction '%.100s'"), str
);
3522 skip_whitespace (str
);
3524 if ((rd
= reg_required_here (& str
, 12)) == FAIL
)
3526 inst
.error
= BAD_ARGS
;
3530 if (skip_past_comma (& str
) == FAIL
3531 || (rn
= ld_mode_required_here (& str
)) == FAIL
)
3534 inst
.error
= BAD_ARGS
;
3538 /* inst.instruction has now been zapped with Rd and the addressing mode. */
3539 if (rd
& 1) /* Unpredictable result if Rd is odd. */
3541 inst
.error
= _("Destination register must be even");
3545 if (rd
== REG_LR
|| rd
== 12)
3547 inst
.error
= _("r12 or r14 not allowed here");
3551 if (((rd
== rn
) || (rd
+ 1 == rn
))
3553 ((inst
.instruction
& WRITE_BACK
)
3554 || (!(inst
.instruction
& PRE_INDEX
))))
3555 as_warn (_("pre/post-indexing used when modified address register is destination"));
3560 /* Returns the index into fp_values of a floating point number,
3561 or -1 if not in the table. */
3564 my_get_float_expression (str
)
3567 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
3573 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
3575 /* Look for a raw floating point number. */
3576 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
3577 && is_end_of_line
[(unsigned char) *save_in
])
3579 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
3581 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
3583 if (words
[j
] != fp_values
[i
][j
])
3587 if (j
== MAX_LITTLENUMS
)
3595 /* Try and parse a more complex expression, this will probably fail
3596 unless the code uses a floating point prefix (eg "0f"). */
3597 save_in
= input_line_pointer
;
3598 input_line_pointer
= *str
;
3599 if (expression (&exp
) == absolute_section
3600 && exp
.X_op
== O_big
3601 && exp
.X_add_number
< 0)
3603 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
3605 if (gen_to_words (words
, 5, (long) 15) == 0)
3607 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
3609 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
3611 if (words
[j
] != fp_values
[i
][j
])
3615 if (j
== MAX_LITTLENUMS
)
3617 *str
= input_line_pointer
;
3618 input_line_pointer
= save_in
;
3625 *str
= input_line_pointer
;
3626 input_line_pointer
= save_in
;
3630 /* Return true if anything in the expression is a bignum. */
3633 walk_no_bignums (sp
)
3636 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
3639 if (symbol_get_value_expression (sp
)->X_add_symbol
)
3641 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
3642 || (symbol_get_value_expression (sp
)->X_op_symbol
3643 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
3650 my_get_expression (ep
, str
)
3657 save_in
= input_line_pointer
;
3658 input_line_pointer
= *str
;
3659 seg
= expression (ep
);
3662 if (seg
!= absolute_section
3663 && seg
!= text_section
3664 && seg
!= data_section
3665 && seg
!= bss_section
3666 && seg
!= undefined_section
)
3668 inst
.error
= _("bad_segment");
3669 *str
= input_line_pointer
;
3670 input_line_pointer
= save_in
;
3675 /* Get rid of any bignums now, so that we don't generate an error for which
3676 we can't establish a line number later on. Big numbers are never valid
3677 in instructions, which is where this routine is always called. */
3678 if (ep
->X_op
== O_big
3679 || (ep
->X_add_symbol
3680 && (walk_no_bignums (ep
->X_add_symbol
)
3682 && walk_no_bignums (ep
->X_op_symbol
)))))
3684 inst
.error
= _("Invalid constant");
3685 *str
= input_line_pointer
;
3686 input_line_pointer
= save_in
;
3690 *str
= input_line_pointer
;
3691 input_line_pointer
= save_in
;
3695 /* UNRESTRICT should be one if <shift> <register> is permitted for this
3699 decode_shift (str
, unrestrict
)
3703 const struct asm_shift_name
* shift
;
3707 skip_whitespace (* str
);
3709 for (p
= * str
; isalpha (* p
); p
++)
3714 inst
.error
= _("Shift expression expected");
3720 shift
= (const struct asm_shift_name
*) hash_find (arm_shift_hsh
, * str
);
3725 inst
.error
= _("Shift expression expected");
3729 assert (shift
->properties
->index
== shift_properties
[shift
->properties
->index
].index
);
3731 if (shift
->properties
->index
== SHIFT_RRX
)
3734 inst
.instruction
|= shift
->properties
->bit_field
;
3738 skip_whitespace (p
);
3740 if (unrestrict
&& reg_required_here (& p
, 8) != FAIL
)
3742 inst
.instruction
|= shift
->properties
->bit_field
| SHIFT_BY_REG
;
3746 else if (! is_immediate_prefix (* p
))
3748 inst
.error
= (unrestrict
3749 ? _("shift requires register or #expression")
3750 : _("shift requires #expression"));
3758 if (my_get_expression (& inst
.reloc
.exp
, & p
))
3761 /* Validate some simple #expressions. */
3762 if (inst
.reloc
.exp
.X_op
== O_constant
)
3764 unsigned num
= inst
.reloc
.exp
.X_add_number
;
3766 /* Reject operations greater than 32. */
3768 /* Reject a shift of 0 unless the mode allows it. */
3769 || (num
== 0 && shift
->properties
->allows_0
== 0)
3770 /* Reject a shift of 32 unless the mode allows it. */
3771 || (num
== 32 && shift
->properties
->allows_32
== 0)
3774 /* As a special case we allow a shift of zero for
3775 modes that do not support it to be recoded as an
3776 logical shift left of zero (ie nothing). We warn
3777 about this though. */
3780 as_warn (_("Shift of 0 ignored."));
3781 shift
= & shift_names
[0];
3782 assert (shift
->properties
->index
== SHIFT_LSL
);
3786 inst
.error
= _("Invalid immediate shift");
3791 /* Shifts of 32 are encoded as 0, for those shifts that
3796 inst
.instruction
|= (num
<< 7) | shift
->properties
->bit_field
;
3800 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
3801 inst
.reloc
.pc_rel
= 0;
3802 inst
.instruction
|= shift
->properties
->bit_field
;
3809 /* Do those data_ops which can take a negative immediate constant
3810 by altering the instuction. A bit of a hack really.
3814 by inverting the second operand, and
3817 by negating the second operand. */
3820 negate_data_op (instruction
, value
)
3821 unsigned long * instruction
;
3822 unsigned long value
;
3825 unsigned long negated
, inverted
;
3827 negated
= validate_immediate (-value
);
3828 inverted
= validate_immediate (~value
);
3830 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
3833 /* First negates. */
3834 case OPCODE_SUB
: /* ADD <-> SUB */
3835 new_inst
= OPCODE_ADD
;
3840 new_inst
= OPCODE_SUB
;
3844 case OPCODE_CMP
: /* CMP <-> CMN */
3845 new_inst
= OPCODE_CMN
;
3850 new_inst
= OPCODE_CMP
;
3854 /* Now Inverted ops. */
3855 case OPCODE_MOV
: /* MOV <-> MVN */
3856 new_inst
= OPCODE_MVN
;
3861 new_inst
= OPCODE_MOV
;
3865 case OPCODE_AND
: /* AND <-> BIC */
3866 new_inst
= OPCODE_BIC
;
3871 new_inst
= OPCODE_AND
;
3875 case OPCODE_ADC
: /* ADC <-> SBC */
3876 new_inst
= OPCODE_SBC
;
3881 new_inst
= OPCODE_ADC
;
3885 /* We cannot do anything. */
3890 if (value
== (unsigned) FAIL
)
3893 *instruction
&= OPCODE_MASK
;
3894 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
3905 skip_whitespace (* str
);
3907 if (reg_required_here (str
, 0) != FAIL
)
3909 if (skip_past_comma (str
) == SUCCESS
)
3910 /* Shift operation on register. */
3911 return decode_shift (str
, NO_SHIFT_RESTRICT
);
3917 /* Immediate expression. */
3918 if (is_immediate_prefix (**str
))
3923 if (my_get_expression (&inst
.reloc
.exp
, str
))
3926 if (inst
.reloc
.exp
.X_add_symbol
)
3928 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
3929 inst
.reloc
.pc_rel
= 0;
3933 if (skip_past_comma (str
) == SUCCESS
)
3935 /* #x, y -- ie explicit rotation by Y. */
3936 if (my_get_expression (&expr
, str
))
3939 if (expr
.X_op
!= O_constant
)
3941 inst
.error
= _("Constant expression expected");
3945 /* Rotate must be a multiple of 2. */
3946 if (((unsigned) expr
.X_add_number
) > 30
3947 || (expr
.X_add_number
& 1) != 0
3948 || ((unsigned) inst
.reloc
.exp
.X_add_number
) > 255)
3950 inst
.error
= _("Invalid constant");
3953 inst
.instruction
|= INST_IMMEDIATE
;
3954 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
3955 inst
.instruction
|= expr
.X_add_number
<< 7;
3959 /* Implicit rotation, select a suitable one. */
3960 value
= validate_immediate (inst
.reloc
.exp
.X_add_number
);
3964 /* Can't be done. Perhaps the code reads something like
3965 "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be OK. */
3966 if ((value
= negate_data_op (&inst
.instruction
,
3967 inst
.reloc
.exp
.X_add_number
))
3970 inst
.error
= _("Invalid constant");
3975 inst
.instruction
|= value
;
3978 inst
.instruction
|= INST_IMMEDIATE
;
3983 inst
.error
= _("Register or shift expression expected");
3992 skip_whitespace (* str
);
3994 if (fp_reg_required_here (str
, 0) != FAIL
)
3998 /* Immediate expression. */
3999 if (*((*str
)++) == '#')
4005 skip_whitespace (* str
);
4007 /* First try and match exact strings, this is to guarantee
4008 that some formats will work even for cross assembly. */
4010 for (i
= 0; fp_const
[i
]; i
++)
4012 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4016 *str
+= strlen (fp_const
[i
]);
4017 if (is_end_of_line
[(unsigned char) **str
])
4019 inst
.instruction
|= i
+ 8;
4026 /* Just because we didn't get a match doesn't mean that the
4027 constant isn't valid, just that it is in a format that we
4028 don't automatically recognize. Try parsing it with
4029 the standard expression routines. */
4030 if ((i
= my_get_float_expression (str
)) >= 0)
4032 inst
.instruction
|= i
+ 8;
4036 inst
.error
= _("Invalid floating point immediate expression");
4040 _("Floating point register or immediate expression expected");
4046 do_arit (str
, flags
)
4048 unsigned long flags
;
4050 skip_whitespace (str
);
4052 if (reg_required_here (&str
, 12) == FAIL
4053 || skip_past_comma (&str
) == FAIL
4054 || reg_required_here (&str
, 16) == FAIL
4055 || skip_past_comma (&str
) == FAIL
4056 || data_op2 (&str
) == FAIL
)
4059 inst
.error
= BAD_ARGS
;
4063 inst
.instruction
|= flags
;
4071 unsigned long flags
;
4073 /* This is a pseudo-op of the form "adr rd, label" to be converted
4074 into a relative address of the form "add rd, pc, #label-.-8". */
4075 skip_whitespace (str
);
4077 if (reg_required_here (&str
, 12) == FAIL
4078 || skip_past_comma (&str
) == FAIL
4079 || my_get_expression (&inst
.reloc
.exp
, &str
))
4082 inst
.error
= BAD_ARGS
;
4086 /* Frag hacking will turn this into a sub instruction if the offset turns
4087 out to be negative. */
4088 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4089 inst
.reloc
.exp
.X_add_number
-= 8; /* PC relative adjust. */
4090 inst
.reloc
.pc_rel
= 1;
4091 inst
.instruction
|= flags
;
4097 do_adrl (str
, flags
)
4099 unsigned long flags
;
4101 /* This is a pseudo-op of the form "adrl rd, label" to be converted
4102 into a relative address of the form:
4103 add rd, pc, #low(label-.-8)"
4104 add rd, rd, #high(label-.-8)" */
4106 skip_whitespace (str
);
4108 if (reg_required_here (& str
, 12) == FAIL
4109 || skip_past_comma (& str
) == FAIL
4110 || my_get_expression (& inst
.reloc
.exp
, & str
))
4113 inst
.error
= BAD_ARGS
;
4119 /* Frag hacking will turn this into a sub instruction if the offset turns
4120 out to be negative. */
4121 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
4122 inst
.reloc
.exp
.X_add_number
-= 8; /* PC relative adjust */
4123 inst
.reloc
.pc_rel
= 1;
4124 inst
.instruction
|= flags
;
4125 inst
.size
= INSN_SIZE
* 2;
4133 unsigned long flags
;
4135 skip_whitespace (str
);
4137 if (reg_required_here (&str
, 16) == FAIL
)
4140 inst
.error
= BAD_ARGS
;
4144 if (skip_past_comma (&str
) == FAIL
4145 || data_op2 (&str
) == FAIL
)
4148 inst
.error
= BAD_ARGS
;
4152 inst
.instruction
|= flags
;
4153 if ((flags
& 0x0000f000) == 0)
4154 inst
.instruction
|= CONDS_BIT
;
4163 unsigned long flags
;
4165 skip_whitespace (str
);
4167 if (reg_required_here (&str
, 12) == FAIL
)
4170 inst
.error
= BAD_ARGS
;
4174 if (skip_past_comma (&str
) == FAIL
4175 || data_op2 (&str
) == FAIL
)
4178 inst
.error
= BAD_ARGS
;
4182 inst
.instruction
|= flags
;
4188 ldst_extend (str
, hwse
)
4199 if (my_get_expression (& inst
.reloc
.exp
, str
))
4202 if (inst
.reloc
.exp
.X_op
== O_constant
)
4204 int value
= inst
.reloc
.exp
.X_add_number
;
4206 if ((hwse
&& (value
< -255 || value
> 255))
4207 || (value
< -4095 || value
> 4095))
4209 inst
.error
= _("address offset too large");
4219 /* Halfword and signextension instructions have the
4220 immediate value split across bits 11..8 and bits 3..0. */
4222 inst
.instruction
|= (add
| HWOFFSET_IMM
4223 | ((value
>> 4) << 8) | (value
& 0xF));
4225 inst
.instruction
|= add
| value
;
4231 inst
.instruction
|= HWOFFSET_IMM
;
4232 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
4235 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
4236 inst
.reloc
.pc_rel
= 0;
4249 if (reg_required_here (str
, 0) == FAIL
)
4253 inst
.instruction
|= add
;
4256 inst
.instruction
|= add
| OFFSET_REG
;
4257 if (skip_past_comma (str
) == SUCCESS
)
4258 return decode_shift (str
, SHIFT_RESTRICT
);
4266 do_ldst (str
, flags
)
4268 unsigned long flags
;
4275 /* This is not ideal, but it is the simplest way of dealing with the
4276 ARM7T halfword instructions (since they use a different
4277 encoding, but the same mnemonic): */
4278 halfword
= (flags
& 0x80000000) != 0;
4281 /* This is actually a load/store of a halfword, or a
4282 signed-extension load. */
4283 if ((cpu_variant
& ARM_EXT_HALFWORD
) == 0)
4286 = _("Processor does not support halfwords or signed bytes");
4290 inst
.instruction
= ((inst
.instruction
& COND_MASK
)
4291 | (flags
& ~COND_MASK
));
4296 skip_whitespace (str
);
4298 if ((conflict_reg
= reg_required_here (& str
, 12)) == FAIL
)
4301 inst
.error
= BAD_ARGS
;
4305 if (skip_past_comma (& str
) == FAIL
)
4307 inst
.error
= _("Address expected");
4317 skip_whitespace (str
);
4319 if ((reg
= reg_required_here (&str
, 16)) == FAIL
)
4322 /* Conflicts can occur on stores as well as loads. */
4323 conflict_reg
= (conflict_reg
== reg
);
4325 skip_whitespace (str
);
4331 if (skip_past_comma (&str
) == SUCCESS
)
4333 /* [Rn],... (post inc) */
4334 if (ldst_extend (&str
, halfword
) == FAIL
)
4338 if (flags
& TRANS_BIT
)
4339 as_warn (_("Rn and Rd must be different in %s"),
4340 ((inst
.instruction
& LOAD_BIT
)
4341 ? "LDRT" : "STRT"));
4343 as_warn (_("%s register same as write-back base"),
4344 ((inst
.instruction
& LOAD_BIT
)
4345 ? _("destination") : _("source")));
4352 inst
.instruction
|= HWOFFSET_IMM
;
4354 skip_whitespace (str
);
4359 as_warn (_("%s register same as write-back base"),
4360 ((inst
.instruction
& LOAD_BIT
)
4361 ? _("destination") : _("source")));
4363 inst
.instruction
|= WRITE_BACK
;
4367 if (flags
& TRANS_BIT
)
4370 as_warn (_("Rn and Rd must be different in %s"),
4371 ((inst
.instruction
& LOAD_BIT
)
4372 ? "LDRT" : "STRT"));
4381 if (skip_past_comma (&str
) == FAIL
)
4383 inst
.error
= _("pre-indexed expression expected");
4388 if (ldst_extend (&str
, halfword
) == FAIL
)
4391 skip_whitespace (str
);
4395 inst
.error
= _("missing ]");
4399 skip_whitespace (str
);
4404 as_warn (_("%s register same as write-back base"),
4405 ((inst
.instruction
& LOAD_BIT
)
4406 ? _("destination") : _("source")));
4408 inst
.instruction
|= WRITE_BACK
;
4412 else if (*str
== '=')
4414 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
4417 skip_whitespace (str
);
4419 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4422 if (inst
.reloc
.exp
.X_op
!= O_constant
4423 && inst
.reloc
.exp
.X_op
!= O_symbol
)
4425 inst
.error
= _("Constant expression expected");
4429 if (inst
.reloc
.exp
.X_op
== O_constant
4430 && (value
= validate_immediate (inst
.reloc
.exp
.X_add_number
)) != FAIL
)
4432 /* This can be done with a mov instruction. */
4433 inst
.instruction
&= LITERAL_MASK
;
4434 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
4435 inst
.instruction
|= (flags
& COND_MASK
) | (value
& 0xfff);
4441 /* Insert into literal pool. */
4442 if (add_to_lit_pool () == FAIL
)
4445 inst
.error
= _("literal pool insertion failed");
4449 /* Change the instruction exp to point to the pool. */
4452 inst
.instruction
|= HWOFFSET_IMM
;
4453 inst
.reloc
.type
= BFD_RELOC_ARM_HWLITERAL
;
4456 inst
.reloc
.type
= BFD_RELOC_ARM_LITERAL
;
4457 inst
.reloc
.pc_rel
= 1;
4458 inst
.instruction
|= (REG_PC
<< 16);
4464 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4469 inst
.instruction
|= HWOFFSET_IMM
;
4470 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
4473 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
4475 /* PC rel adjust. */
4476 inst
.reloc
.exp
.X_add_number
-= 8;
4478 inst
.reloc
.pc_rel
= 1;
4479 inst
.instruction
|= (REG_PC
<< 16);
4483 if (pre_inc
&& (flags
& TRANS_BIT
))
4484 inst
.error
= _("Pre-increment instruction with translate");
4486 inst
.instruction
|= flags
| (pre_inc
? PRE_INDEX
: 0);
4495 char * str
= * strp
;
4499 /* We come back here if we get ranges concatenated by '+' or '|'. */
4514 skip_whitespace (str
);
4516 if ((reg
= reg_required_here (& str
, -1)) == FAIL
)
4525 inst
.error
= _("Bad range in register list");
4529 for (i
= cur_reg
+ 1; i
< reg
; i
++)
4531 if (range
& (1 << i
))
4533 (_("Warning: Duplicated register (r%d) in register list"),
4541 if (range
& (1 << reg
))
4542 as_tsktsk (_("Warning: Duplicated register (r%d) in register list"),
4544 else if (reg
<= cur_reg
)
4545 as_tsktsk (_("Warning: Register range not in ascending order"));
4550 while (skip_past_comma (&str
) != FAIL
4551 || (in_range
= 1, *str
++ == '-'));
4553 skip_whitespace (str
);
4557 inst
.error
= _("Missing `}'");
4565 if (my_get_expression (&expr
, &str
))
4568 if (expr
.X_op
== O_constant
)
4570 if (expr
.X_add_number
4571 != (expr
.X_add_number
& 0x0000ffff))
4573 inst
.error
= _("invalid register mask");
4577 if ((range
& expr
.X_add_number
) != 0)
4579 int regno
= range
& expr
.X_add_number
;
4582 regno
= (1 << regno
) - 1;
4584 (_("Warning: Duplicated register (r%d) in register list"),
4588 range
|= expr
.X_add_number
;
4592 if (inst
.reloc
.type
!= 0)
4594 inst
.error
= _("expression too complex");
4598 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
4599 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
4600 inst
.reloc
.pc_rel
= 0;
4604 skip_whitespace (str
);
4606 if (*str
== '|' || *str
== '+')
4612 while (another_range
);
4619 do_ldmstm (str
, flags
)
4621 unsigned long flags
;
4626 skip_whitespace (str
);
4628 if ((base_reg
= reg_required_here (&str
, 16)) == FAIL
)
4631 if (base_reg
== REG_PC
)
4633 inst
.error
= _("r15 not allowed as base register");
4637 skip_whitespace (str
);
4641 flags
|= WRITE_BACK
;
4645 if (skip_past_comma (&str
) == FAIL
4646 || (range
= reg_list (&str
)) == FAIL
)
4649 inst
.error
= BAD_ARGS
;
4656 flags
|= LDM_TYPE_2_OR_3
;
4659 inst
.instruction
|= flags
| range
;
4667 unsigned long flags
;
4669 skip_whitespace (str
);
4671 /* Allow optional leading '#'. */
4672 if (is_immediate_prefix (*str
))
4675 if (my_get_expression (& inst
.reloc
.exp
, & str
))
4678 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
4679 inst
.reloc
.pc_rel
= 0;
4680 inst
.instruction
|= flags
;
4688 do_swap (str
, flags
)
4690 unsigned long flags
;
4694 skip_whitespace (str
);
4696 if ((reg
= reg_required_here (&str
, 12)) == FAIL
)
4701 inst
.error
= _("r15 not allowed in swap");
4705 if (skip_past_comma (&str
) == FAIL
4706 || (reg
= reg_required_here (&str
, 0)) == FAIL
)
4709 inst
.error
= BAD_ARGS
;
4715 inst
.error
= _("r15 not allowed in swap");
4719 if (skip_past_comma (&str
) == FAIL
4722 inst
.error
= BAD_ARGS
;
4726 skip_whitespace (str
);
4728 if ((reg
= reg_required_here (&str
, 16)) == FAIL
)
4733 inst
.error
= BAD_PC
;
4737 skip_whitespace (str
);
4741 inst
.error
= _("missing ]");
4745 inst
.instruction
|= flags
;
4751 do_branch (str
, flags
)
4753 unsigned long flags ATTRIBUTE_UNUSED
;
4755 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4762 /* ScottB: February 5, 1998 - Check to see of PLT32 reloc
4763 required for the instruction. */
4765 /* arm_parse_reloc () works on input_line_pointer.
4766 We actually want to parse the operands to the branch instruction
4767 passed in 'str'. Save the input pointer and restore it later. */
4768 save_in
= input_line_pointer
;
4769 input_line_pointer
= str
;
4770 if (inst
.reloc
.exp
.X_op
== O_symbol
4772 && arm_parse_reloc () == BFD_RELOC_ARM_PLT32
)
4774 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
4775 inst
.reloc
.pc_rel
= 0;
4776 /* Modify str to point to after parsed operands, otherwise
4777 end_of_line() will complain about the (PLT) left in str. */
4778 str
= input_line_pointer
;
4782 inst
.reloc
.type
= BFD_RELOC_ARM_PCREL_BRANCH
;
4783 inst
.reloc
.pc_rel
= 1;
4785 input_line_pointer
= save_in
;
4788 inst
.reloc
.type
= BFD_RELOC_ARM_PCREL_BRANCH
;
4789 inst
.reloc
.pc_rel
= 1;
4790 #endif /* OBJ_ELF */
4799 unsigned long flags ATTRIBUTE_UNUSED
;
4803 skip_whitespace (str
);
4805 if ((reg
= reg_required_here (&str
, 0)) == FAIL
)
4807 inst
.error
= BAD_ARGS
;
4811 /* Note - it is not illegal to do a "bx pc". Useless, but not illegal. */
4813 as_tsktsk (_("Use of r15 in bx in ARM mode is not really useful"));
4821 unsigned long flags ATTRIBUTE_UNUSED
;
4823 /* Co-processor data operation.
4824 Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
4825 skip_whitespace (str
);
4827 if (co_proc_number (&str
) == FAIL
)
4830 inst
.error
= BAD_ARGS
;
4834 if (skip_past_comma (&str
) == FAIL
4835 || cp_opc_expr (&str
, 20,4) == FAIL
)
4838 inst
.error
= BAD_ARGS
;
4842 if (skip_past_comma (&str
) == FAIL
4843 || cp_reg_required_here (&str
, 12) == FAIL
)
4846 inst
.error
= BAD_ARGS
;
4850 if (skip_past_comma (&str
) == FAIL
4851 || cp_reg_required_here (&str
, 16) == FAIL
)
4854 inst
.error
= BAD_ARGS
;
4858 if (skip_past_comma (&str
) == FAIL
4859 || cp_reg_required_here (&str
, 0) == FAIL
)
4862 inst
.error
= BAD_ARGS
;
4866 if (skip_past_comma (&str
) == SUCCESS
)
4868 if (cp_opc_expr (&str
, 5, 3) == FAIL
)
4871 inst
.error
= BAD_ARGS
;
4881 do_lstc (str
, flags
)
4883 unsigned long flags
;
4885 /* Co-processor register load/store.
4886 Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
4888 skip_whitespace (str
);
4890 if (co_proc_number (&str
) == FAIL
)
4893 inst
.error
= BAD_ARGS
;
4897 if (skip_past_comma (&str
) == FAIL
4898 || cp_reg_required_here (&str
, 12) == FAIL
)
4901 inst
.error
= BAD_ARGS
;
4905 if (skip_past_comma (&str
) == FAIL
4906 || cp_address_required_here (&str
) == FAIL
)
4909 inst
.error
= BAD_ARGS
;
4913 inst
.instruction
|= flags
;
4919 do_co_reg (str
, flags
)
4921 unsigned long flags
;
4923 /* Co-processor register transfer.
4924 Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
4926 skip_whitespace (str
);
4928 if (co_proc_number (&str
) == FAIL
)
4931 inst
.error
= BAD_ARGS
;
4935 if (skip_past_comma (&str
) == FAIL
4936 || cp_opc_expr (&str
, 21, 3) == FAIL
)
4939 inst
.error
= BAD_ARGS
;
4943 if (skip_past_comma (&str
) == FAIL
4944 || reg_required_here (&str
, 12) == FAIL
)
4947 inst
.error
= BAD_ARGS
;
4951 if (skip_past_comma (&str
) == FAIL
4952 || cp_reg_required_here (&str
, 16) == FAIL
)
4955 inst
.error
= BAD_ARGS
;
4959 if (skip_past_comma (&str
) == FAIL
4960 || cp_reg_required_here (&str
, 0) == FAIL
)
4963 inst
.error
= BAD_ARGS
;
4967 if (skip_past_comma (&str
) == SUCCESS
)
4969 if (cp_opc_expr (&str
, 5, 3) == FAIL
)
4972 inst
.error
= BAD_ARGS
;
4978 inst
.error
= BAD_COND
;
4986 do_fp_ctrl (str
, flags
)
4988 unsigned long flags ATTRIBUTE_UNUSED
;
4990 /* FP control registers.
4991 Format: <WFS|RFS|WFC|RFC>{cond} Rn */
4993 skip_whitespace (str
);
4995 if (reg_required_here (&str
, 12) == FAIL
)
4998 inst
.error
= BAD_ARGS
;
5007 do_fp_ldst (str
, flags
)
5009 unsigned long flags ATTRIBUTE_UNUSED
;
5011 skip_whitespace (str
);
5013 switch (inst
.suffix
)
5018 inst
.instruction
|= CP_T_X
;
5021 inst
.instruction
|= CP_T_Y
;
5024 inst
.instruction
|= CP_T_X
| CP_T_Y
;
5030 if (fp_reg_required_here (&str
, 12) == FAIL
)
5033 inst
.error
= BAD_ARGS
;
5037 if (skip_past_comma (&str
) == FAIL
5038 || cp_address_required_here (&str
) == FAIL
)
5041 inst
.error
= BAD_ARGS
;
5049 do_fp_ldmstm (str
, flags
)
5051 unsigned long flags
;
5055 skip_whitespace (str
);
5057 if (fp_reg_required_here (&str
, 12) == FAIL
)
5060 inst
.error
= BAD_ARGS
;
5064 /* Get Number of registers to transfer. */
5065 if (skip_past_comma (&str
) == FAIL
5066 || my_get_expression (&inst
.reloc
.exp
, &str
))
5069 inst
.error
= _("constant expression expected");
5073 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5075 inst
.error
= _("Constant value required for number of registers");
5079 num_regs
= inst
.reloc
.exp
.X_add_number
;
5081 if (num_regs
< 1 || num_regs
> 4)
5083 inst
.error
= _("number of registers must be in the range [1:4]");
5090 inst
.instruction
|= CP_T_X
;
5093 inst
.instruction
|= CP_T_Y
;
5096 inst
.instruction
|= CP_T_Y
| CP_T_X
;
5110 /* The instruction specified "ea" or "fd", so we can only accept
5111 [Rn]{!}. The instruction does not really support stacking or
5112 unstacking, so we have to emulate these by setting appropriate
5113 bits and offsets. */
5114 if (skip_past_comma (&str
) == FAIL
5118 inst
.error
= BAD_ARGS
;
5123 skip_whitespace (str
);
5125 if ((reg
= reg_required_here (&str
, 16)) == FAIL
)
5128 skip_whitespace (str
);
5132 inst
.error
= BAD_ARGS
;
5144 _("R15 not allowed as base register with write-back");
5151 if (flags
& CP_T_Pre
)
5153 /* Pre-decrement. */
5154 offset
= 3 * num_regs
;
5160 /* Post-increment. */
5164 offset
= 3 * num_regs
;
5168 /* No write-back, so convert this into a standard pre-increment
5169 instruction -- aesthetically more pleasing. */
5170 flags
= CP_T_Pre
| CP_T_UD
;
5175 inst
.instruction
|= flags
| offset
;
5177 else if (skip_past_comma (&str
) == FAIL
5178 || cp_address_required_here (&str
) == FAIL
)
5181 inst
.error
= BAD_ARGS
;
5189 do_fp_dyadic (str
, flags
)
5191 unsigned long flags
;
5193 skip_whitespace (str
);
5195 switch (inst
.suffix
)
5200 inst
.instruction
|= 0x00000080;
5203 inst
.instruction
|= 0x00080000;
5209 if (fp_reg_required_here (&str
, 12) == FAIL
)
5212 inst
.error
= BAD_ARGS
;
5216 if (skip_past_comma (&str
) == FAIL
5217 || fp_reg_required_here (&str
, 16) == FAIL
)
5220 inst
.error
= BAD_ARGS
;
5224 if (skip_past_comma (&str
) == FAIL
5225 || fp_op2 (&str
) == FAIL
)
5228 inst
.error
= BAD_ARGS
;
5232 inst
.instruction
|= flags
;
5238 do_fp_monadic (str
, flags
)
5240 unsigned long flags
;
5242 skip_whitespace (str
);
5244 switch (inst
.suffix
)
5249 inst
.instruction
|= 0x00000080;
5252 inst
.instruction
|= 0x00080000;
5258 if (fp_reg_required_here (&str
, 12) == FAIL
)
5261 inst
.error
= BAD_ARGS
;
5265 if (skip_past_comma (&str
) == FAIL
5266 || fp_op2 (&str
) == FAIL
)
5269 inst
.error
= BAD_ARGS
;
5273 inst
.instruction
|= flags
;
5279 do_fp_cmp (str
, flags
)
5281 unsigned long flags
;
5283 skip_whitespace (str
);
5285 if (fp_reg_required_here (&str
, 16) == FAIL
)
5288 inst
.error
= BAD_ARGS
;
5292 if (skip_past_comma (&str
) == FAIL
5293 || fp_op2 (&str
) == FAIL
)
5296 inst
.error
= BAD_ARGS
;
5300 inst
.instruction
|= flags
;
5306 do_fp_from_reg (str
, flags
)
5308 unsigned long flags
;
5310 skip_whitespace (str
);
5312 switch (inst
.suffix
)
5317 inst
.instruction
|= 0x00000080;
5320 inst
.instruction
|= 0x00080000;
5326 if (fp_reg_required_here (&str
, 16) == FAIL
)
5329 inst
.error
= BAD_ARGS
;
5333 if (skip_past_comma (&str
) == FAIL
5334 || reg_required_here (&str
, 12) == FAIL
)
5337 inst
.error
= BAD_ARGS
;
5341 inst
.instruction
|= flags
;
5347 do_fp_to_reg (str
, flags
)
5349 unsigned long flags
;
5351 skip_whitespace (str
);
5353 if (reg_required_here (&str
, 12) == FAIL
)
5356 if (skip_past_comma (&str
) == FAIL
5357 || fp_reg_required_here (&str
, 0) == FAIL
)
5360 inst
.error
= BAD_ARGS
;
5364 inst
.instruction
|= flags
;
5369 /* Thumb specific routines. */
5371 /* Parse and validate that a register is of the right form, this saves
5372 repeated checking of this information in many similar cases.
5373 Unlike the 32-bit case we do not insert the register into the opcode
5374 here, since the position is often unknown until the full instruction
5378 thumb_reg (strp
, hi_lo
)
5384 if ((reg
= reg_required_here (strp
, -1)) == FAIL
)
5392 inst
.error
= _("lo register required");
5400 inst
.error
= _("hi register required");
5412 /* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode
5416 thumb_add_sub (str
, subtract
)
5420 int Rd
, Rs
, Rn
= FAIL
;
5422 skip_whitespace (str
);
5424 if ((Rd
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
5425 || skip_past_comma (&str
) == FAIL
)
5428 inst
.error
= BAD_ARGS
;
5432 if (is_immediate_prefix (*str
))
5436 if (my_get_expression (&inst
.reloc
.exp
, &str
))
5441 if ((Rs
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
5444 if (skip_past_comma (&str
) == FAIL
)
5446 /* Two operand format, shuffle the registers
5447 and pretend there are 3. */
5451 else if (is_immediate_prefix (*str
))
5454 if (my_get_expression (&inst
.reloc
.exp
, &str
))
5457 else if ((Rn
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
5461 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
5462 for the latter case, EXPR contains the immediate that was found. */
5465 /* All register format. */
5466 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
5470 inst
.error
= _("dest and source1 must be the same register");
5474 /* Can't do this for SUB. */
5477 inst
.error
= _("subtract valid only on lo regs");
5481 inst
.instruction
= (T_OPCODE_ADD_HI
5482 | (Rd
> 7 ? THUMB_H1
: 0)
5483 | (Rn
> 7 ? THUMB_H2
: 0));
5484 inst
.instruction
|= (Rd
& 7) | ((Rn
& 7) << 3);
5488 inst
.instruction
= subtract
? T_OPCODE_SUB_R3
: T_OPCODE_ADD_R3
;
5489 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
5494 /* Immediate expression, now things start to get nasty. */
5496 /* First deal with HI regs, only very restricted cases allowed:
5497 Adjusting SP, and using PC or SP to get an address. */
5498 if ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
5499 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
))
5501 inst
.error
= _("invalid Hi register with immediate");
5505 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5507 /* Value isn't known yet, all we can do is store all the fragments
5508 we know about in the instruction and let the reloc hacking
5510 inst
.instruction
= (subtract
? 0x8000 : 0) | (Rd
<< 4) | Rs
;
5511 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
5515 int offset
= inst
.reloc
.exp
.X_add_number
;
5525 /* Quick check, in case offset is MIN_INT. */
5528 inst
.error
= _("immediate value out of range");
5537 if (offset
& ~0x1fc)
5539 inst
.error
= _("invalid immediate value for stack adjust");
5542 inst
.instruction
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
5543 inst
.instruction
|= offset
>> 2;
5545 else if (Rs
== REG_PC
|| Rs
== REG_SP
)
5548 || (offset
& ~0x3fc))
5550 inst
.error
= _("invalid immediate for address calculation");
5553 inst
.instruction
= (Rs
== REG_PC
? T_OPCODE_ADD_PC
5555 inst
.instruction
|= (Rd
<< 8) | (offset
>> 2);
5561 inst
.error
= _("immediate value out of range");
5564 inst
.instruction
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
5565 inst
.instruction
|= (Rd
<< 8) | offset
;
5571 inst
.error
= _("immediate value out of range");
5574 inst
.instruction
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
5575 inst
.instruction
|= Rd
| (Rs
<< 3) | (offset
<< 6);
5584 thumb_shift (str
, shift
)
5588 int Rd
, Rs
, Rn
= FAIL
;
5590 skip_whitespace (str
);
5592 if ((Rd
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
5593 || skip_past_comma (&str
) == FAIL
)
5596 inst
.error
= BAD_ARGS
;
5600 if (is_immediate_prefix (*str
))
5602 /* Two operand immediate format, set Rs to Rd. */
5605 if (my_get_expression (&inst
.reloc
.exp
, &str
))
5610 if ((Rs
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
5613 if (skip_past_comma (&str
) == FAIL
)
5615 /* Two operand format, shuffle the registers
5616 and pretend there are 3. */
5620 else if (is_immediate_prefix (*str
))
5623 if (my_get_expression (&inst
.reloc
.exp
, &str
))
5626 else if ((Rn
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
5630 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
5631 for the latter case, EXPR contains the immediate that was found. */
5637 inst
.error
= _("source1 and dest must be same register");
5643 case THUMB_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
5644 case THUMB_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
5645 case THUMB_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
5648 inst
.instruction
|= Rd
| (Rn
<< 3);
5654 case THUMB_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
5655 case THUMB_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
5656 case THUMB_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
5659 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5661 /* Value isn't known yet, create a dummy reloc and let reloc
5662 hacking fix it up. */
5663 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
5667 unsigned shift_value
= inst
.reloc
.exp
.X_add_number
;
5669 if (shift_value
> 32 || (shift_value
== 32 && shift
== THUMB_LSL
))
5671 inst
.error
= _("Invalid immediate for shift");
5675 /* Shifts of zero are handled by converting to LSL. */
5676 if (shift_value
== 0)
5677 inst
.instruction
= T_OPCODE_LSL_I
;
5679 /* Shifts of 32 are encoded as a shift of zero. */
5680 if (shift_value
== 32)
5683 inst
.instruction
|= shift_value
<< 6;
5686 inst
.instruction
|= Rd
| (Rs
<< 3);
5693 thumb_mov_compare (str
, move
)
5699 skip_whitespace (str
);
5701 if ((Rd
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
5702 || skip_past_comma (&str
) == FAIL
)
5705 inst
.error
= BAD_ARGS
;
5709 if (is_immediate_prefix (*str
))
5712 if (my_get_expression (&inst
.reloc
.exp
, &str
))
5715 else if ((Rs
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
5720 if (Rs
< 8 && Rd
< 8)
5722 if (move
== THUMB_MOVE
)
5723 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
5724 since a MOV instruction produces unpredictable results. */
5725 inst
.instruction
= T_OPCODE_ADD_I3
;
5727 inst
.instruction
= T_OPCODE_CMP_LR
;
5728 inst
.instruction
|= Rd
| (Rs
<< 3);
5732 if (move
== THUMB_MOVE
)
5733 inst
.instruction
= T_OPCODE_MOV_HR
;
5735 inst
.instruction
= T_OPCODE_CMP_HR
;
5738 inst
.instruction
|= THUMB_H1
;
5741 inst
.instruction
|= THUMB_H2
;
5743 inst
.instruction
|= (Rd
& 7) | ((Rs
& 7) << 3);
5750 inst
.error
= _("only lo regs allowed with immediate");
5754 if (move
== THUMB_MOVE
)
5755 inst
.instruction
= T_OPCODE_MOV_I8
;
5757 inst
.instruction
= T_OPCODE_CMP_I8
;
5759 inst
.instruction
|= Rd
<< 8;
5761 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5762 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
5765 unsigned value
= inst
.reloc
.exp
.X_add_number
;
5769 inst
.error
= _("invalid immediate");
5773 inst
.instruction
|= value
;
5781 thumb_load_store (str
, load_store
, size
)
5786 int Rd
, Rb
, Ro
= FAIL
;
5788 skip_whitespace (str
);
5790 if ((Rd
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
5791 || skip_past_comma (&str
) == FAIL
)
5794 inst
.error
= BAD_ARGS
;
5801 if ((Rb
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
5804 if (skip_past_comma (&str
) != FAIL
)
5806 if (is_immediate_prefix (*str
))
5809 if (my_get_expression (&inst
.reloc
.exp
, &str
))
5812 else if ((Ro
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
5817 inst
.reloc
.exp
.X_op
= O_constant
;
5818 inst
.reloc
.exp
.X_add_number
= 0;
5823 inst
.error
= _("expected ']'");
5828 else if (*str
== '=')
5830 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
5833 skip_whitespace (str
);
5835 if (my_get_expression (& inst
.reloc
.exp
, & str
))
5840 if ( inst
.reloc
.exp
.X_op
!= O_constant
5841 && inst
.reloc
.exp
.X_op
!= O_symbol
)
5843 inst
.error
= "Constant expression expected";
5847 if (inst
.reloc
.exp
.X_op
== O_constant
5848 && ((inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0))
5850 /* This can be done with a mov instruction. */
5852 inst
.instruction
= T_OPCODE_MOV_I8
| (Rd
<< 8);
5853 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
5857 /* Insert into literal pool. */
5858 if (add_to_lit_pool () == FAIL
)
5861 inst
.error
= "literal pool insertion failed";
5865 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
5866 inst
.reloc
.pc_rel
= 1;
5867 inst
.instruction
= T_OPCODE_LDR_PC
| (Rd
<< 8);
5868 /* Adjust ARM pipeline offset to Thumb. */
5869 inst
.reloc
.exp
.X_add_number
+= 4;
5875 if (my_get_expression (&inst
.reloc
.exp
, &str
))
5878 inst
.instruction
= T_OPCODE_LDR_PC
| (Rd
<< 8);
5879 inst
.reloc
.pc_rel
= 1;
5880 inst
.reloc
.exp
.X_add_number
-= 4; /* Pipeline offset. */
5881 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
5886 if (Rb
== REG_PC
|| Rb
== REG_SP
)
5888 if (size
!= THUMB_WORD
)
5890 inst
.error
= _("byte or halfword not valid for base register");
5893 else if (Rb
== REG_PC
&& load_store
!= THUMB_LOAD
)
5895 inst
.error
= _("R15 based store not allowed");
5898 else if (Ro
!= FAIL
)
5900 inst
.error
= _("Invalid base register for register offset");
5905 inst
.instruction
= T_OPCODE_LDR_PC
;
5906 else if (load_store
== THUMB_LOAD
)
5907 inst
.instruction
= T_OPCODE_LDR_SP
;
5909 inst
.instruction
= T_OPCODE_STR_SP
;
5911 inst
.instruction
|= Rd
<< 8;
5912 if (inst
.reloc
.exp
.X_op
== O_constant
)
5914 unsigned offset
= inst
.reloc
.exp
.X_add_number
;
5916 if (offset
& ~0x3fc)
5918 inst
.error
= _("invalid offset");
5922 inst
.instruction
|= offset
>> 2;
5925 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
5929 inst
.error
= _("invalid base register in load/store");
5932 else if (Ro
== FAIL
)
5934 /* Immediate offset. */
5935 if (size
== THUMB_WORD
)
5936 inst
.instruction
= (load_store
== THUMB_LOAD
5937 ? T_OPCODE_LDR_IW
: T_OPCODE_STR_IW
);
5938 else if (size
== THUMB_HALFWORD
)
5939 inst
.instruction
= (load_store
== THUMB_LOAD
5940 ? T_OPCODE_LDR_IH
: T_OPCODE_STR_IH
);
5942 inst
.instruction
= (load_store
== THUMB_LOAD
5943 ? T_OPCODE_LDR_IB
: T_OPCODE_STR_IB
);
5945 inst
.instruction
|= Rd
| (Rb
<< 3);
5947 if (inst
.reloc
.exp
.X_op
== O_constant
)
5949 unsigned offset
= inst
.reloc
.exp
.X_add_number
;
5951 if (offset
& ~(0x1f << size
))
5953 inst
.error
= _("Invalid offset");
5956 inst
.instruction
|= (offset
>> size
) << 6;
5959 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
5963 /* Register offset. */
5964 if (size
== THUMB_WORD
)
5965 inst
.instruction
= (load_store
== THUMB_LOAD
5966 ? T_OPCODE_LDR_RW
: T_OPCODE_STR_RW
);
5967 else if (size
== THUMB_HALFWORD
)
5968 inst
.instruction
= (load_store
== THUMB_LOAD
5969 ? T_OPCODE_LDR_RH
: T_OPCODE_STR_RH
);
5971 inst
.instruction
= (load_store
== THUMB_LOAD
5972 ? T_OPCODE_LDR_RB
: T_OPCODE_STR_RB
);
5974 inst
.instruction
|= Rd
| (Rb
<< 3) | (Ro
<< 6);
5989 /* Handle the Format 4 instructions that do not have equivalents in other
5990 formats. That is, ADC, AND, EOR, SBC, ROR, TST, NEG, CMN, ORR, MUL,
5999 skip_whitespace (str
);
6001 if ((Rd
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
6002 || skip_past_comma (&str
) == FAIL
6003 || (Rs
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
6005 inst
.error
= BAD_ARGS
;
6009 if (skip_past_comma (&str
) != FAIL
)
6011 /* Three operand format not allowed for TST, CMN, NEG and MVN.
6012 (It isn't allowed for CMP either, but that isn't handled by this
6014 if (inst
.instruction
== T_OPCODE_TST
6015 || inst
.instruction
== T_OPCODE_CMN
6016 || inst
.instruction
== T_OPCODE_NEG
6017 || inst
.instruction
== T_OPCODE_MVN
)
6019 inst
.error
= BAD_ARGS
;
6023 if ((Rn
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
6028 inst
.error
= _("dest and source1 one must be the same register");
6034 if (inst
.instruction
== T_OPCODE_MUL
6036 as_tsktsk (_("Rs and Rd must be different in MUL"));
6038 inst
.instruction
|= Rd
| (Rs
<< 3);
6046 thumb_add_sub (str
, 0);
6053 thumb_shift (str
, THUMB_ASR
);
6060 if (my_get_expression (&inst
.reloc
.exp
, &str
))
6062 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
6063 inst
.reloc
.pc_rel
= 1;
6071 if (my_get_expression (&inst
.reloc
.exp
, &str
))
6073 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
6074 inst
.reloc
.pc_rel
= 1;
6078 /* Find the real, Thumb encoded start of a Thumb function. */
6081 find_real_start (symbolP
)
6085 const char * name
= S_GET_NAME (symbolP
);
6086 symbolS
* new_target
;
6088 /* This definiton must agree with the one in gcc/config/arm/thumb.c. */
6089 #define STUB_NAME ".real_start_of"
6094 /* Names that start with '.' are local labels, not function entry points.
6095 The compiler may generate BL instructions to these labels because it
6096 needs to perform a branch to a far away location. */
6100 real_start
= malloc (strlen (name
) + strlen (STUB_NAME
) + 1);
6101 sprintf (real_start
, "%s%s", STUB_NAME
, name
);
6103 new_target
= symbol_find (real_start
);
6105 if (new_target
== NULL
)
6107 as_warn ("Failed to find real start of function: %s\n", name
);
6108 new_target
= symbolP
;
6120 if (my_get_expression (& inst
.reloc
.exp
, & str
))
6123 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
6124 inst
.reloc
.pc_rel
= 1;
6127 /* If the destination of the branch is a defined symbol which does not have
6128 the THUMB_FUNC attribute, then we must be calling a function which has
6129 the (interfacearm) attribute. We look for the Thumb entry point to that
6130 function and change the branch to refer to that function instead. */
6131 if ( inst
.reloc
.exp
.X_op
== O_symbol
6132 && inst
.reloc
.exp
.X_add_symbol
!= NULL
6133 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
6134 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
6135 inst
.reloc
.exp
.X_add_symbol
=
6136 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
6145 skip_whitespace (str
);
6147 if ((reg
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
6150 /* This sets THUMB_H2 from the top bit of reg. */
6151 inst
.instruction
|= reg
<< 3;
6153 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
6154 should cause the alignment to be checked once it is known. This is
6155 because BX PC only works if the instruction is word aligned. */
6164 thumb_mov_compare (str
, THUMB_COMPARE
);
6174 skip_whitespace (str
);
6176 if ((Rb
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
6180 as_warn (_("Inserted missing '!': load/store multiple always writes back base register"));
6184 if (skip_past_comma (&str
) == FAIL
6185 || (range
= reg_list (&str
)) == FAIL
)
6188 inst
.error
= BAD_ARGS
;
6192 if (inst
.reloc
.type
!= BFD_RELOC_NONE
)
6194 /* This really doesn't seem worth it. */
6195 inst
.reloc
.type
= BFD_RELOC_NONE
;
6196 inst
.error
= _("Expression too complex");
6202 inst
.error
= _("only lo-regs valid in load/store multiple");
6206 inst
.instruction
|= (Rb
<< 8) | range
;
6214 thumb_load_store (str
, THUMB_LOAD
, THUMB_WORD
);
6221 thumb_load_store (str
, THUMB_LOAD
, THUMB_BYTE
);
6228 thumb_load_store (str
, THUMB_LOAD
, THUMB_HALFWORD
);
6237 skip_whitespace (str
);
6239 if ((Rd
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
6240 || skip_past_comma (&str
) == FAIL
6242 || (Rb
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
6243 || skip_past_comma (&str
) == FAIL
6244 || (Ro
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
6248 inst
.error
= _("Syntax: ldrs[b] Rd, [Rb, Ro]");
6252 inst
.instruction
|= Rd
| (Rb
<< 3) | (Ro
<< 6);
6260 thumb_shift (str
, THUMB_LSL
);
6267 thumb_shift (str
, THUMB_LSR
);
6274 thumb_mov_compare (str
, THUMB_MOVE
);
6283 skip_whitespace (str
);
6285 if ((range
= reg_list (&str
)) == FAIL
)
6288 inst
.error
= BAD_ARGS
;
6292 if (inst
.reloc
.type
!= BFD_RELOC_NONE
)
6294 /* This really doesn't seem worth it. */
6295 inst
.reloc
.type
= BFD_RELOC_NONE
;
6296 inst
.error
= _("Expression too complex");
6302 if ((inst
.instruction
== T_OPCODE_PUSH
6303 && (range
& ~0xff) == 1 << REG_LR
)
6304 || (inst
.instruction
== T_OPCODE_POP
6305 && (range
& ~0xff) == 1 << REG_PC
))
6307 inst
.instruction
|= THUMB_PP_PC_LR
;
6312 inst
.error
= _("invalid register list to push/pop instruction");
6317 inst
.instruction
|= range
;
6325 thumb_load_store (str
, THUMB_STORE
, THUMB_WORD
);
6332 thumb_load_store (str
, THUMB_STORE
, THUMB_BYTE
);
6339 thumb_load_store (str
, THUMB_STORE
, THUMB_HALFWORD
);
6346 thumb_add_sub (str
, 1);
6353 skip_whitespace (str
);
6355 if (my_get_expression (&inst
.reloc
.exp
, &str
))
6358 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
6369 /* This is a pseudo-op of the form "adr rd, label" to be converted
6370 into a relative address of the form "add rd, pc, #label-.-4". */
6371 skip_whitespace (str
);
6373 /* Store Rd in temporary location inside instruction. */
6374 if ((reg
= reg_required_here (&str
, 4)) == FAIL
6375 || (reg
> 7) /* For Thumb reg must be r0..r7. */
6376 || skip_past_comma (&str
) == FAIL
6377 || my_get_expression (&inst
.reloc
.exp
, &str
))
6380 inst
.error
= BAD_ARGS
;
6384 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
6385 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
6386 inst
.reloc
.pc_rel
= 1;
6387 inst
.instruction
|= REG_PC
; /* Rd is already placed into the instruction. */
6396 int len
= strlen (reg_table
[entry
].name
) + 2;
6397 char * buf
= (char *) xmalloc (len
);
6398 char * buf2
= (char *) xmalloc (len
);
6401 #ifdef REGISTER_PREFIX
6402 buf
[i
++] = REGISTER_PREFIX
;
6405 strcpy (buf
+ i
, reg_table
[entry
].name
);
6407 for (i
= 0; buf
[i
]; i
++)
6408 buf2
[i
] = islower (buf
[i
]) ? toupper (buf
[i
]) : buf
[i
];
6412 hash_insert (arm_reg_hsh
, buf
, (PTR
) & reg_table
[entry
]);
6413 hash_insert (arm_reg_hsh
, buf2
, (PTR
) & reg_table
[entry
]);
6417 insert_reg_alias (str
, regnum
)
6421 struct reg_entry
*new =
6422 (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
6423 char *name
= xmalloc (strlen (str
) + 1);
6427 new->number
= regnum
;
6429 hash_insert (arm_reg_hsh
, name
, (PTR
) new);
6433 set_constant_flonums ()
6437 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
6438 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
6448 if ( (arm_ops_hsh
= hash_new ()) == NULL
6449 || (arm_tops_hsh
= hash_new ()) == NULL
6450 || (arm_cond_hsh
= hash_new ()) == NULL
6451 || (arm_shift_hsh
= hash_new ()) == NULL
6452 || (arm_reg_hsh
= hash_new ()) == NULL
6453 || (arm_psr_hsh
= hash_new ()) == NULL
)
6454 as_fatal (_("Virtual memory exhausted"));
6456 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
6457 hash_insert (arm_ops_hsh
, insns
[i
].template, (PTR
) (insns
+ i
));
6458 for (i
= 0; i
< sizeof (tinsns
) / sizeof (struct thumb_opcode
); i
++)
6459 hash_insert (arm_tops_hsh
, tinsns
[i
].template, (PTR
) (tinsns
+ i
));
6460 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
6461 hash_insert (arm_cond_hsh
, conds
[i
].template, (PTR
) (conds
+ i
));
6462 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
6463 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (PTR
) (shift_names
+ i
));
6464 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
6465 hash_insert (arm_psr_hsh
, psrs
[i
].template, (PTR
) (psrs
+ i
));
6467 for (i
= 0; reg_table
[i
].name
; i
++)
6470 set_constant_flonums ();
6472 #if defined OBJ_COFF || defined OBJ_ELF
6474 unsigned int flags
= 0;
6476 /* Set the flags in the private structure. */
6477 if (uses_apcs_26
) flags
|= F_APCS26
;
6478 if (support_interwork
) flags
|= F_INTERWORK
;
6479 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
6480 if (pic_code
) flags
|= F_PIC
;
6481 if ((cpu_variant
& FPU_ALL
) == FPU_NONE
) flags
|= F_SOFT_FLOAT
;
6483 bfd_set_private_flags (stdoutput
, flags
);
6485 /* We have run out flags in the COFF header to encode the
6486 status of ATPCS support, so instead we create a dummy,
6487 empty, debug section called .arm.atpcs. */
6492 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
6496 bfd_set_section_flags
6497 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
6498 bfd_set_section_size (stdoutput
, sec
, 0);
6499 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
6505 /* Record the CPU type as well. */
6506 switch (cpu_variant
& ARM_CPU_MASK
)
6509 mach
= bfd_mach_arm_2
;
6512 case ARM_3
: /* Also ARM_250. */
6513 mach
= bfd_mach_arm_2a
;
6517 case ARM_6
| ARM_3
| ARM_2
: /* Actually no CPU type defined. */
6518 mach
= bfd_mach_arm_4
;
6521 case ARM_7
: /* Also ARM_6. */
6522 mach
= bfd_mach_arm_3
;
6526 /* Catch special cases. */
6527 if (cpu_variant
& ARM_EXT_XSCALE
)
6528 mach
= bfd_mach_arm_XScale
;
6529 else if (cpu_variant
& ARM_EXT_V5E
)
6530 mach
= bfd_mach_arm_5TE
;
6531 else if (cpu_variant
& ARM_EXT_V5
)
6533 if (cpu_variant
& ARM_EXT_THUMB
)
6534 mach
= bfd_mach_arm_5T
;
6536 mach
= bfd_mach_arm_5
;
6538 else if (cpu_variant
& ARM_EXT_HALFWORD
)
6540 if (cpu_variant
& ARM_EXT_THUMB
)
6541 mach
= bfd_mach_arm_4T
;
6543 mach
= bfd_mach_arm_4
;
6545 else if (cpu_variant
& ARM_EXT_LONGMUL
)
6546 mach
= bfd_mach_arm_3M
;
6548 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
6551 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
6552 for use in the a.out file, and stores them in the array pointed to by buf.
6553 This knows about the endian-ness of the target machine and does
6554 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
6555 2 (short) and 4 (long) Floating numbers are put out as a series of
6556 LITTLENUMS (shorts, here at least). */
6559 md_number_to_chars (buf
, val
, n
)
6564 if (target_big_endian
)
6565 number_to_chars_bigendian (buf
, val
, n
);
6567 number_to_chars_littleendian (buf
, val
, n
);
6571 md_chars_to_number (buf
, n
)
6576 unsigned char * where
= (unsigned char *) buf
;
6578 if (target_big_endian
)
6583 result
|= (*where
++ & 255);
6591 result
|= (where
[n
] & 255);
6598 /* Turn a string in input_line_pointer into a floating point constant
6599 of type TYPE, and store the appropriate bytes in *LITP. The number
6600 of LITTLENUMS emitted is stored in *SIZEP. An error message is
6601 returned, or NULL on OK.
6603 Note that fp constants aren't represent in the normal way on the ARM.
6604 In big endian mode, things are as expected. However, in little endian
6605 mode fp constants are big-endian word-wise, and little-endian byte-wise
6606 within the words. For example, (double) 1.1 in big endian mode is
6607 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
6608 the byte sequence 99 99 f1 3f 9a 99 99 99.
6610 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
6613 md_atof (type
, litP
, sizeP
)
6619 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
6651 return _("Bad call to MD_ATOF()");
6654 t
= atof_ieee (input_line_pointer
, type
, words
);
6656 input_line_pointer
= t
;
6659 if (target_big_endian
)
6661 for (i
= 0; i
< prec
; i
++)
6663 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
6669 /* For a 4 byte float the order of elements in `words' is 1 0. For an
6670 8 byte float the order is 1 0 3 2. */
6671 for (i
= 0; i
< prec
; i
+= 2)
6673 md_number_to_chars (litP
, (valueT
) words
[i
+ 1], 2);
6674 md_number_to_chars (litP
+ 2, (valueT
) words
[i
], 2);
6682 /* The knowledge of the PC's pipeline offset is built into the insns
6686 md_pcrel_from (fixP
)
6690 && S_GET_SEGMENT (fixP
->fx_addsy
) == undefined_section
6691 && fixP
->fx_subsy
== NULL
)
6694 if (fixP
->fx_pcrel
&& (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_ADD
))
6696 /* PC relative addressing on the Thumb is slightly odd
6697 as the bottom two bits of the PC are forced to zero
6698 for the calculation. */
6699 return (fixP
->fx_where
+ fixP
->fx_frag
->fr_address
) & ~3;
6703 /* The pattern was adjusted to accomodate CE's off-by-one fixups,
6704 so we un-adjust here to compensate for the accomodation. */
6705 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
+ 8;
6707 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6711 /* Round up a section size to the appropriate boundary. */
6714 md_section_align (segment
, size
)
6715 segT segment ATTRIBUTE_UNUSED
;
6721 /* Round all sects to multiple of 4. */
6722 return (size
+ 3) & ~3;
6726 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
6727 Otherwise we have no need to default values of symbols. */
6730 md_undefined_symbol (name
)
6731 char * name ATTRIBUTE_UNUSED
;
6734 if (name
[0] == '_' && name
[1] == 'G'
6735 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
6739 if (symbol_find (name
))
6740 as_bad ("GOT already in the symbol table");
6742 GOT_symbol
= symbol_new (name
, undefined_section
,
6743 (valueT
) 0, & zero_address_frag
);
6753 /* arm_reg_parse () := if it looks like a register, return its token and
6754 advance the pointer. */
6758 register char ** ccp
;
6760 char * start
= * ccp
;
6763 struct reg_entry
* reg
;
6765 #ifdef REGISTER_PREFIX
6766 if (*start
!= REGISTER_PREFIX
)
6771 #ifdef OPTIONAL_REGISTER_PREFIX
6772 if (*p
== OPTIONAL_REGISTER_PREFIX
)
6776 if (!isalpha (*p
) || !is_name_beginner (*p
))
6780 while (isalpha (c
) || isdigit (c
) || c
== '_')
6784 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, start
);
6797 md_apply_fix3 (fixP
, val
, seg
)
6802 offsetT value
= * val
;
6804 unsigned int newimm
;
6807 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6808 arm_fix_data
* arm_data
= (arm_fix_data
*) fixP
->tc_fix_data
;
6810 assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
6812 /* Note whether this will delete the relocation. */
6814 /* Patch from REarnshaw to JDavis (disabled for the moment, since it
6815 doesn't work fully.) */
6816 if ((fixP
->fx_addsy
== 0 || symbol_constant_p (fixP
->fx_addsy
))
6819 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
6823 /* If this symbol is in a different section then we need to leave it for
6824 the linker to deal with. Unfortunately, md_pcrel_from can't tell,
6825 so we have to undo it's effects here. */
6828 if (fixP
->fx_addsy
!= NULL
6829 && S_IS_DEFINED (fixP
->fx_addsy
)
6830 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
6833 && (fixP
->fx_r_type
== BFD_RELOC_ARM_PCREL_BRANCH
6834 || fixP
->fx_r_type
== BFD_RELOC_ARM_PCREL_BLX
6838 value
+= md_pcrel_from (fixP
);
6842 /* Remember value for emit_reloc. */
6843 fixP
->fx_addnumber
= value
;
6845 switch (fixP
->fx_r_type
)
6847 case BFD_RELOC_ARM_IMMEDIATE
:
6848 newimm
= validate_immediate (value
);
6849 temp
= md_chars_to_number (buf
, INSN_SIZE
);
6851 /* If the instruction will fail, see if we can fix things up by
6852 changing the opcode. */
6853 if (newimm
== (unsigned int) FAIL
6854 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
6856 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6857 _("invalid constant (%lx) after fixup"),
6858 (unsigned long) value
);
6862 newimm
|= (temp
& 0xfffff000);
6863 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
6866 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
6868 unsigned int highpart
= 0;
6869 unsigned int newinsn
= 0xe1a00000; /* nop. */
6870 newimm
= validate_immediate (value
);
6871 temp
= md_chars_to_number (buf
, INSN_SIZE
);
6873 /* If the instruction will fail, see if we can fix things up by
6874 changing the opcode. */
6875 if (newimm
== (unsigned int) FAIL
6876 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
6878 /* No ? OK - try using two ADD instructions to generate
6880 newimm
= validate_immediate_twopart (value
, & highpart
);
6882 /* Yes - then make sure that the second instruction is
6884 if (newimm
!= (unsigned int) FAIL
)
6886 /* Still No ? Try using a negated value. */
6887 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
6888 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
6889 /* Otherwise - give up. */
6892 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6893 _("Unable to compute ADRL instructions for PC offset of 0x%lx"),
6898 /* Replace the first operand in the 2nd instruction (which
6899 is the PC) with the destination register. We have
6900 already added in the PC in the first instruction and we
6901 do not want to do it again. */
6902 newinsn
&= ~ 0xf0000;
6903 newinsn
|= ((newinsn
& 0x0f000) << 4);
6906 newimm
|= (temp
& 0xfffff000);
6907 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
6909 highpart
|= (newinsn
& 0xfffff000);
6910 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
6914 case BFD_RELOC_ARM_OFFSET_IMM
:
6920 if (validate_offset_imm (value
, 0) == FAIL
)
6922 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6923 _("bad immediate value for offset (%ld)"),
6928 newval
= md_chars_to_number (buf
, INSN_SIZE
);
6929 newval
&= 0xff7ff000;
6930 newval
|= value
| (sign
? INDEX_UP
: 0);
6931 md_number_to_chars (buf
, newval
, INSN_SIZE
);
6934 case BFD_RELOC_ARM_OFFSET_IMM8
:
6935 case BFD_RELOC_ARM_HWLITERAL
:
6941 if (validate_offset_imm (value
, 1) == FAIL
)
6943 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
6944 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6945 _("invalid literal constant: pool needs to be closer"));
6947 as_bad (_("bad immediate value for half-word offset (%ld)"),
6952 newval
= md_chars_to_number (buf
, INSN_SIZE
);
6953 newval
&= 0xff7ff0f0;
6954 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
6955 md_number_to_chars (buf
, newval
, INSN_SIZE
);
6958 case BFD_RELOC_ARM_LITERAL
:
6964 if (validate_offset_imm (value
, 0) == FAIL
)
6966 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6967 _("invalid literal constant: pool needs to be closer"));
6971 newval
= md_chars_to_number (buf
, INSN_SIZE
);
6972 newval
&= 0xff7ff000;
6973 newval
|= value
| (sign
? INDEX_UP
: 0);
6974 md_number_to_chars (buf
, newval
, INSN_SIZE
);
6977 case BFD_RELOC_ARM_SHIFT_IMM
:
6978 newval
= md_chars_to_number (buf
, INSN_SIZE
);
6979 if (((unsigned long) value
) > 32
6981 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
6983 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6984 _("shift expression is too large"));
6989 /* Shifts of zero must be done as lsl. */
6991 else if (value
== 32)
6993 newval
&= 0xfffff07f;
6994 newval
|= (value
& 0x1f) << 7;
6995 md_number_to_chars (buf
, newval
, INSN_SIZE
);
6998 case BFD_RELOC_ARM_SWI
:
6999 if (arm_data
->thumb_mode
)
7001 if (((unsigned long) value
) > 0xff)
7002 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7003 _("Invalid swi expression"));
7004 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xff00;
7006 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
7010 if (((unsigned long) value
) > 0x00ffffff)
7011 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7012 _("Invalid swi expression"));
7013 newval
= md_chars_to_number (buf
, INSN_SIZE
) & 0xff000000;
7015 md_number_to_chars (buf
, newval
, INSN_SIZE
);
7019 case BFD_RELOC_ARM_MULTI
:
7020 if (((unsigned long) value
) > 0xffff)
7021 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7022 _("Invalid expression in load/store multiple"));
7023 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
7024 md_number_to_chars (buf
, newval
, INSN_SIZE
);
7027 case BFD_RELOC_ARM_PCREL_BRANCH
:
7028 newval
= md_chars_to_number (buf
, INSN_SIZE
);
7030 /* Sign-extend a 24-bit number. */
7031 #define SEXT24(x) ((((x) & 0xffffff) ^ (~ 0x7fffff)) + 0x800000)
7035 value
= fixP
->fx_offset
;
7038 /* We are going to store value (shifted right by two) in the
7039 instruction, in a 24 bit, signed field. Thus we need to check
7040 that none of the top 8 bits of the shifted value (top 7 bits of
7041 the unshifted, unsigned value) are set, or that they are all set. */
7042 if ((value
& ~ ((offsetT
) 0x1ffffff)) != 0
7043 && ((value
& ~ ((offsetT
) 0x1ffffff)) != ~ ((offsetT
) 0x1ffffff)))
7046 /* Normally we would be stuck at this point, since we cannot store
7047 the absolute address that is the destination of the branch in the
7048 24 bits of the branch instruction. If however, we happen to know
7049 that the destination of the branch is in the same section as the
7050 branch instruciton itself, then we can compute the relocation for
7051 ourselves and not have to bother the linker with it.
7053 FIXME: The tests for OBJ_ELF and ! target_oabi are only here
7054 because I have not worked out how to do this for OBJ_COFF or
7057 && fixP
->fx_addsy
!= NULL
7058 && S_IS_DEFINED (fixP
->fx_addsy
)
7059 && S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
7061 /* Get pc relative value to go into the branch. */
7064 /* Permit a backward branch provided that enough bits
7065 are set. Allow a forwards branch, provided that
7066 enough bits are clear. */
7067 if ( (value
& ~ ((offsetT
) 0x1ffffff)) == ~ ((offsetT
) 0x1ffffff)
7068 || (value
& ~ ((offsetT
) 0x1ffffff)) == 0)
7072 if (! fixP
->fx_done
)
7074 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7075 _("gas can't handle same-section branch dest >= 0x04000000"));
7079 value
+= SEXT24 (newval
);
7081 if ( (value
& ~ ((offsetT
) 0xffffff)) != 0
7082 && ((value
& ~ ((offsetT
) 0xffffff)) != ~ ((offsetT
) 0xffffff)))
7083 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7084 _("out of range branch"));
7086 newval
= (value
& 0x00ffffff) | (newval
& 0xff000000);
7087 md_number_to_chars (buf
, newval
, INSN_SIZE
);
7090 case BFD_RELOC_ARM_PCREL_BLX
:
7093 newval
= md_chars_to_number (buf
, INSN_SIZE
);
7097 value
= fixP
->fx_offset
;
7099 hbit
= (value
>> 1) & 1;
7100 value
= (value
>> 2) & 0x00ffffff;
7101 value
= (value
+ (newval
& 0x00ffffff)) & 0x00ffffff;
7102 newval
= value
| (newval
& 0xfe000000) | (hbit
<< 24);
7103 md_number_to_chars (buf
, newval
, INSN_SIZE
);
7107 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
7108 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
7110 addressT diff
= (newval
& 0xff) << 1;
7115 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
7116 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7117 _("Branch out of range"));
7118 newval
= (newval
& 0xff00) | ((value
& 0x1ff) >> 1);
7120 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
7123 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
7124 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
7126 addressT diff
= (newval
& 0x7ff) << 1;
7131 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
7132 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7133 _("Branch out of range"));
7134 newval
= (newval
& 0xf800) | ((value
& 0xfff) >> 1);
7136 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
7139 case BFD_RELOC_THUMB_PCREL_BLX
:
7140 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
7145 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
7146 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
7147 diff
= ((newval
& 0x7ff) << 12) | ((newval2
& 0x7ff) << 1);
7148 if (diff
& 0x400000)
7151 value
= fixP
->fx_offset
;
7154 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
7155 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7156 _("Branch with link out of range"));
7158 newval
= (newval
& 0xf800) | ((value
& 0x7fffff) >> 12);
7159 newval2
= (newval2
& 0xf800) | ((value
& 0xfff) >> 1);
7160 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
7161 /* Remove bit zero of the adjusted offset. Bit zero can only be
7162 set if the upper insn is at a half-word boundary, since the
7163 destination address, an ARM instruction, must always be on a
7164 word boundary. The semantics of the BLX (1) instruction, however,
7165 are that bit zero in the offset must always be zero, and the
7166 corresponding bit one in the target address will be set from bit
7167 one of the source address. */
7169 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
7170 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
7175 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
7176 md_number_to_chars (buf
, value
, 1);
7178 else if (!target_oabi
)
7180 value
= fixP
->fx_offset
;
7181 md_number_to_chars (buf
, value
, 1);
7187 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
7188 md_number_to_chars (buf
, value
, 2);
7190 else if (!target_oabi
)
7192 value
= fixP
->fx_offset
;
7193 md_number_to_chars (buf
, value
, 2);
7199 case BFD_RELOC_ARM_GOT32
:
7200 case BFD_RELOC_ARM_GOTOFF
:
7201 md_number_to_chars (buf
, 0, 4);
7207 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
7208 md_number_to_chars (buf
, value
, 4);
7210 else if (!target_oabi
)
7212 value
= fixP
->fx_offset
;
7213 md_number_to_chars (buf
, value
, 4);
7219 case BFD_RELOC_ARM_PLT32
:
7220 /* It appears the instruction is fully prepared at this point. */
7224 case BFD_RELOC_ARM_GOTPC
:
7225 md_number_to_chars (buf
, value
, 4);
7228 case BFD_RELOC_ARM_CP_OFF_IMM
:
7230 if (value
< -1023 || value
> 1023 || (value
& 3))
7231 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7232 _("Illegal value for co-processor offset"));
7235 newval
= md_chars_to_number (buf
, INSN_SIZE
) & 0xff7fff00;
7236 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
7237 md_number_to_chars (buf
, newval
, INSN_SIZE
);
7240 case BFD_RELOC_ARM_THUMB_OFFSET
:
7241 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
7242 /* Exactly what ranges, and where the offset is inserted depends
7243 on the type of instruction, we can establish this from the
7245 switch (newval
>> 12)
7247 case 4: /* PC load. */
7248 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
7249 forced to zero for these loads, so we will need to round
7250 up the offset if the instruction address is not word
7251 aligned (since the final address produced must be, and
7252 we can only describe word-aligned immediate offsets). */
7254 if ((fixP
->fx_frag
->fr_address
+ fixP
->fx_where
+ value
) & 3)
7255 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7256 _("Invalid offset, target not word aligned (0x%08X)"),
7257 (unsigned int) (fixP
->fx_frag
->fr_address
7258 + fixP
->fx_where
+ value
));
7260 if ((value
+ 2) & ~0x3fe)
7261 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7262 _("Invalid offset, value too big (0x%08lX)"), value
);
7264 /* Round up, since pc will be rounded down. */
7265 newval
|= (value
+ 2) >> 2;
7268 case 9: /* SP load/store. */
7270 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7271 _("Invalid offset, value too big (0x%08lX)"), value
);
7272 newval
|= value
>> 2;
7275 case 6: /* Word load/store. */
7277 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7278 _("Invalid offset, value too big (0x%08lX)"), value
);
7279 newval
|= value
<< 4; /* 6 - 2. */
7282 case 7: /* Byte load/store. */
7284 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7285 _("Invalid offset, value too big (0x%08lX)"), value
);
7286 newval
|= value
<< 6;
7289 case 8: /* Halfword load/store. */
7291 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7292 _("Invalid offset, value too big (0x%08lX)"), value
);
7293 newval
|= value
<< 5; /* 6 - 1. */
7297 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7298 "Unable to process relocation for thumb opcode: %lx",
7299 (unsigned long) newval
);
7302 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
7305 case BFD_RELOC_ARM_THUMB_ADD
:
7306 /* This is a complicated relocation, since we use it for all of
7307 the following immediate relocations:
7311 9bit ADD/SUB SP word-aligned
7312 10bit ADD PC/SP word-aligned
7314 The type of instruction being processed is encoded in the
7321 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
7323 int rd
= (newval
>> 4) & 0xf;
7324 int rs
= newval
& 0xf;
7325 int subtract
= newval
& 0x8000;
7330 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7331 _("Invalid immediate for stack address calculation"));
7332 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
7333 newval
|= value
>> 2;
7335 else if (rs
== REG_PC
|| rs
== REG_SP
)
7339 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7340 _("Invalid immediate for address calculation (value = 0x%08lX)"),
7341 (unsigned long) value
);
7342 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
7344 newval
|= value
>> 2;
7349 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7350 _("Invalid 8bit immediate"));
7351 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
7352 newval
|= (rd
<< 8) | value
;
7357 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7358 _("Invalid 3bit immediate"));
7359 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
7360 newval
|= rd
| (rs
<< 3) | (value
<< 6);
7363 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
7366 case BFD_RELOC_ARM_THUMB_IMM
:
7367 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
7368 switch (newval
>> 11)
7370 case 0x04: /* 8bit immediate MOV. */
7371 case 0x05: /* 8bit immediate CMP. */
7372 if (value
< 0 || value
> 255)
7373 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7374 _("Invalid immediate: %ld is too large"),
7382 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
7385 case BFD_RELOC_ARM_THUMB_SHIFT
:
7386 /* 5bit shift value (0..31). */
7387 if (value
< 0 || value
> 31)
7388 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7389 _("Illegal Thumb shift value: %ld"), (long) value
);
7390 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf03f;
7391 newval
|= value
<< 6;
7392 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
7395 case BFD_RELOC_VTABLE_INHERIT
:
7396 case BFD_RELOC_VTABLE_ENTRY
:
7400 case BFD_RELOC_NONE
:
7402 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7403 _("Bad relocation fixup type (%d)"), fixP
->fx_r_type
);
7409 /* Translate internal representation of relocation info to BFD target
7413 tc_gen_reloc (section
, fixp
)
7414 asection
* section ATTRIBUTE_UNUSED
;
7418 bfd_reloc_code_real_type code
;
7420 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
7422 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
7423 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
7424 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7426 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
7428 if (fixp
->fx_pcrel
== 0)
7429 reloc
->addend
= fixp
->fx_offset
;
7431 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
7433 reloc
->addend
= fixp
->fx_offset
;
7436 switch (fixp
->fx_r_type
)
7441 code
= BFD_RELOC_8_PCREL
;
7448 code
= BFD_RELOC_16_PCREL
;
7455 code
= BFD_RELOC_32_PCREL
;
7459 case BFD_RELOC_ARM_PCREL_BRANCH
:
7460 case BFD_RELOC_ARM_PCREL_BLX
:
7462 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
7463 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
7464 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
7465 case BFD_RELOC_THUMB_PCREL_BLX
:
7466 case BFD_RELOC_VTABLE_ENTRY
:
7467 case BFD_RELOC_VTABLE_INHERIT
:
7468 code
= fixp
->fx_r_type
;
7471 case BFD_RELOC_ARM_LITERAL
:
7472 case BFD_RELOC_ARM_HWLITERAL
:
7473 /* If this is called then the a literal has been referenced across
7474 a section boundary - possibly due to an implicit dump. */
7475 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7476 _("Literal referenced across section boundary (Implicit dump?)"));
7480 case BFD_RELOC_ARM_GOT32
:
7481 case BFD_RELOC_ARM_GOTOFF
:
7482 case BFD_RELOC_ARM_PLT32
:
7483 code
= fixp
->fx_r_type
;
7487 case BFD_RELOC_ARM_IMMEDIATE
:
7488 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7489 _("Internal_relocation (type %d) not fixed up (IMMEDIATE)"),
7493 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
7494 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7495 _("ADRL used for a symbol not defined in the same file"));
7498 case BFD_RELOC_ARM_OFFSET_IMM
:
7499 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7500 _("Internal_relocation (type %d) not fixed up (OFFSET_IMM)"),
7508 switch (fixp
->fx_r_type
)
7510 case BFD_RELOC_ARM_IMMEDIATE
: type
= "IMMEDIATE"; break;
7511 case BFD_RELOC_ARM_OFFSET_IMM
: type
= "OFFSET_IMM"; break;
7512 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
7513 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
7514 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
7515 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
7516 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
7517 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
7518 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
7519 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
7520 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
7521 default: type
= _("<unknown>"); break;
7523 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7524 _("Cannot represent %s relocation in this object file format"),
7531 if (code
== BFD_RELOC_32_PCREL
7533 && fixp
->fx_addsy
== GOT_symbol
)
7535 code
= BFD_RELOC_ARM_GOTPC
;
7536 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
7540 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7542 if (reloc
->howto
== NULL
)
7544 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7545 _("Can not represent %s relocation in this object file format"),
7546 bfd_get_reloc_code_name (code
));
7550 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
7551 vtable entry to be used in the relocation's section offset. */
7552 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
7553 reloc
->address
= fixp
->fx_offset
;
7559 md_estimate_size_before_relax (fragP
, segtype
)
7560 fragS
* fragP ATTRIBUTE_UNUSED
;
7561 segT segtype ATTRIBUTE_UNUSED
;
7563 as_fatal (_("md_estimate_size_before_relax\n"));
7568 output_inst
PARAMS ((void))
7574 as_bad (inst
.error
);
7578 to
= frag_more (inst
.size
);
7580 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
7582 assert (inst
.size
== (2 * THUMB_SIZE
));
7583 md_number_to_chars (to
, inst
.instruction
>> 16, THUMB_SIZE
);
7584 md_number_to_chars (to
+ THUMB_SIZE
, inst
.instruction
, THUMB_SIZE
);
7586 else if (inst
.size
> INSN_SIZE
)
7588 assert (inst
.size
== (2 * INSN_SIZE
));
7589 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
7590 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
7593 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
7595 if (inst
.reloc
.type
!= BFD_RELOC_NONE
)
7596 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
7597 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
7601 dwarf2_emit_insn (inst
.size
);
7614 /* Align the instruction.
7615 This may not be the right thing to do but ... */
7619 listing_prev_line (); /* Defined in listing.h. */
7621 /* Align the previous label if needed. */
7622 if (last_label_seen
!= NULL
)
7624 symbol_set_frag (last_label_seen
, frag_now
);
7625 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
7626 S_SET_SEGMENT (last_label_seen
, now_seg
);
7629 memset (&inst
, '\0', sizeof (inst
));
7630 inst
.reloc
.type
= BFD_RELOC_NONE
;
7632 skip_whitespace (str
);
7634 /* Scan up to the end of the op-code, which must end in white space or
7636 for (start
= p
= str
; *p
!= '\0'; p
++)
7642 as_bad (_("No operator -- statement `%s'\n"), str
);
7648 CONST
struct thumb_opcode
* opcode
;
7652 opcode
= (CONST
struct thumb_opcode
*) hash_find (arm_tops_hsh
, str
);
7657 /* Check that this instruction is supported for this CPU. */
7658 if (thumb_mode
== 1 && (opcode
->variants
& cpu_variant
) == 0)
7660 as_bad (_("selected processor does not support this opcode"));
7664 inst
.instruction
= opcode
->value
;
7665 inst
.size
= opcode
->size
;
7666 (*opcode
->parms
) (p
);
7673 CONST
struct asm_opcode
* opcode
;
7674 unsigned long cond_code
;
7676 inst
.size
= INSN_SIZE
;
7677 /* P now points to the end of the opcode, probably white space, but we
7678 have to break the opcode up in case it contains condionals and flags;
7679 keep trying with progressively smaller basic instructions until one
7680 matches, or we run out of opcode. */
7681 q
= (p
- str
> LONGEST_INST
) ? str
+ LONGEST_INST
: p
;
7683 for (; q
!= str
; q
--)
7688 opcode
= (CONST
struct asm_opcode
*) hash_find (arm_ops_hsh
, str
);
7691 if (opcode
&& opcode
->template)
7693 unsigned long flag_bits
= 0;
7696 /* Check that this instruction is supported for this CPU. */
7697 if ((opcode
->variants
& cpu_variant
) == 0)
7700 inst
.instruction
= opcode
->value
;
7701 if (q
== p
) /* Just a simple opcode. */
7703 if (opcode
->comp_suffix
)
7705 if (*opcode
->comp_suffix
!= '\0')
7706 as_bad (_("Opcode `%s' must have suffix from list: <%s>"),
7707 str
, opcode
->comp_suffix
);
7709 /* Not a conditional instruction. */
7710 (*opcode
->parms
) (q
, 0);
7714 /* A conditional instruction with default condition. */
7715 inst
.instruction
|= COND_ALWAYS
;
7716 (*opcode
->parms
) (q
, 0);
7722 /* Not just a simple opcode. Check if extra is a
7727 CONST
struct asm_cond
*cond
;
7731 cond
= (CONST
struct asm_cond
*) hash_find (arm_cond_hsh
, r
);
7735 if (cond
->value
== 0xf0000000)
7737 _("Warning: Use of the 'nv' conditional is deprecated\n"));
7739 cond_code
= cond
->value
;
7743 cond_code
= COND_ALWAYS
;
7746 cond_code
= COND_ALWAYS
;
7748 /* Apply the conditional, or complain it's not allowed. */
7749 if (opcode
->comp_suffix
&& *opcode
->comp_suffix
== '\0')
7751 /* Instruction isn't conditional. */
7752 if (cond_code
!= COND_ALWAYS
)
7754 as_bad (_("Opcode `%s' is unconditional\n"), str
);
7759 /* Instruction is conditional: set the condition into it. */
7760 inst
.instruction
|= cond_code
;
7762 /* If there is a compulsory suffix, it should come here
7763 before any optional flags. */
7764 if (opcode
->comp_suffix
&& *opcode
->comp_suffix
!= '\0')
7766 CONST
char *s
= opcode
->comp_suffix
;
7778 as_bad (_("Opcode `%s' must have suffix from <%s>\n"),
7779 str
, opcode
->comp_suffix
);
7786 /* The remainder, if any should now be flags for the instruction;
7787 Scan these checking each one found with the opcode. */
7791 CONST
struct asm_flg
*flag
= opcode
->flags
;
7800 for (flagno
= 0; flag
[flagno
].template; flagno
++)
7802 if (streq (r
, flag
[flagno
].template))
7804 flag_bits
|= flag
[flagno
].set_bits
;
7810 if (! flag
[flagno
].template)
7817 (*opcode
->parms
) (p
, flag_bits
);
7827 /* It wasn't an instruction, but it might be a register alias of the form
7830 skip_whitespace (q
);
7835 if (*q
&& !strncmp (q
, ".req ", 4))
7841 #ifdef IGNORE_OPCODE_CASE
7842 str
= original_case_string
;
7847 skip_whitespace (q
);
7849 for (r
= q
; *r
!= '\0'; r
++)
7859 regnum
= arm_reg_parse (& q
);
7862 reg
= arm_reg_parse (& str
);
7867 insert_reg_alias (str
, regnum
);
7869 as_warn (_("register '%s' does not exist\n"), q
);
7871 else if (regnum
!= FAIL
)
7874 as_warn (_("ignoring redefinition of register alias '%s'"),
7877 /* Do not warn about redefinitions to the same alias. */
7880 as_warn (_("ignoring redefinition of register alias '%s' to non-existant register '%s'"),
7884 as_warn (_("ignoring incomplete .req pseuso op"));
7891 as_bad (_("bad instruction `%s'"), start
);
7895 Invocation line includes a switch not recognized by the base assembler.
7896 See if it's a processor-specific option. These are:
7897 Cpu variants, the arm part is optional:
7898 -m[arm]1 Currently not supported.
7899 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
7900 -m[arm]3 Arm 3 processor
7901 -m[arm]6[xx], Arm 6 processors
7902 -m[arm]7[xx][t][[d]m] Arm 7 processors
7903 -m[arm]8[10] Arm 8 processors
7904 -m[arm]9[20][tdmi] Arm 9 processors
7905 -mstrongarm[110[0]] StrongARM processors
7906 -mxscale XScale processors
7907 -m[arm]v[2345[t[e]]] Arm architectures
7908 -mall All (except the ARM1)
7910 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
7911 -mfpe-old (No float load/store multiples)
7912 -mno-fpu Disable all floating point instructions
7913 Run-time endian selection:
7915 -EL little endian cpu
7916 ARM Procedure Calling Standard:
7917 -mapcs-32 32 bit APCS
7918 -mapcs-26 26 bit APCS
7919 -mapcs-float Pass floats in float regs
7920 -mapcs-reentrant Position independent code
7921 -mthumb-interwork Code supports Arm/Thumb interworking
7922 -matpcs ARM/Thumb Procedure Call Standard
7923 -moabi Old ELF ABI */
7925 CONST
char * md_shortopts
= "m:k";
7927 struct option md_longopts
[] =
7929 #ifdef ARM_BI_ENDIAN
7930 #define OPTION_EB (OPTION_MD_BASE + 0)
7931 {"EB", no_argument
, NULL
, OPTION_EB
},
7932 #define OPTION_EL (OPTION_MD_BASE + 1)
7933 {"EL", no_argument
, NULL
, OPTION_EL
},
7935 #define OPTION_OABI (OPTION_MD_BASE +2)
7936 {"oabi", no_argument
, NULL
, OPTION_OABI
},
7939 {NULL
, no_argument
, NULL
, 0}
7942 size_t md_longopts_size
= sizeof (md_longopts
);
7945 md_parse_option (c
, arg
)
7953 #ifdef ARM_BI_ENDIAN
7955 target_big_endian
= 1;
7958 target_big_endian
= 0;
7966 if (streq (str
, "fpa10"))
7967 cpu_variant
= (cpu_variant
& ~FPU_ALL
) | FPU_FPA10
;
7968 else if (streq (str
, "fpa11"))
7969 cpu_variant
= (cpu_variant
& ~FPU_ALL
) | FPU_FPA11
;
7970 else if (streq (str
, "fpe-old"))
7971 cpu_variant
= (cpu_variant
& ~FPU_ALL
) | FPU_CORE
;
7977 if (streq (str
, "no-fpu"))
7978 cpu_variant
&= ~FPU_ALL
;
7983 if (streq (str
, "oabi"))
7989 /* Limit assembler to generating only Thumb instructions: */
7990 if (streq (str
, "thumb"))
7992 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_EXT_THUMB
;
7993 cpu_variant
= (cpu_variant
& ~FPU_ALL
) | FPU_NONE
;
7996 else if (streq (str
, "thumb-interwork"))
7998 if ((cpu_variant
& ARM_EXT_THUMB
) == 0)
7999 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_ARCH_V4T
;
8000 #if defined OBJ_COFF || defined OBJ_ELF
8001 support_interwork
= true;
8009 if (streq (str
, "all"))
8011 cpu_variant
= ARM_ALL
| FPU_ALL
;
8014 #if defined OBJ_COFF || defined OBJ_ELF
8015 if (! strncmp (str
, "apcs-", 5))
8017 /* GCC passes on all command line options starting "-mapcs-..."
8018 to us, so we must parse them here. */
8022 if (streq (str
, "32"))
8024 uses_apcs_26
= false;
8027 else if (streq (str
, "26"))
8029 uses_apcs_26
= true;
8032 else if (streq (str
, "frame"))
8034 /* Stack frames are being generated - does not affect
8038 else if (streq (str
, "stack-check"))
8040 /* Stack checking is being performed - does not affect
8041 linkage, but does require that the functions
8042 __rt_stkovf_split_small and __rt_stkovf_split_big be
8043 present in the final link. */
8047 else if (streq (str
, "float"))
8049 /* Floating point arguments are being passed in the floating
8050 point registers. This does affect linking, since this
8051 version of the APCS is incompatible with the version that
8052 passes floating points in the integer registers. */
8054 uses_apcs_float
= true;
8057 else if (streq (str
, "reentrant"))
8059 /* Reentrant code has been generated. This does affect
8060 linking, since there is no point in linking reentrant/
8061 position independent code with absolute position code. */
8066 as_bad (_("Unrecognised APCS switch -m%s"), arg
);
8070 if (! strcmp (str
, "atpcs"))
8076 /* Strip off optional "arm". */
8077 if (! strncmp (str
, "arm", 3))
8083 if (streq (str
, "1"))
8084 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_1
;
8090 if (streq (str
, "2"))
8091 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_2
;
8092 else if (streq (str
, "250"))
8093 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_250
;
8099 if (streq (str
, "3"))
8100 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_3
;
8106 switch (strtol (str
, NULL
, 10))
8113 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_6
;
8121 /* Eat the processor name. */
8122 switch (strtol (str
, & str
, 10))
8135 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_7
;
8141 cpu_variant
|= ARM_ARCH_V4T
;
8145 cpu_variant
|= ARM_EXT_LONGMUL
;
8148 case 'f': /* fe => fp enabled cpu. */
8154 case 'c': /* Left over from 710c processor name. */
8155 case 'd': /* Debug. */
8156 case 'i': /* Embedded ICE. */
8157 /* Included for completeness in ARM processor naming. */
8167 if (streq (str
, "8") || streq (str
, "810"))
8168 cpu_variant
= (cpu_variant
& ~ARM_ANY
)
8169 | ARM_8
| ARM_ARCH_V4
;
8175 if (streq (str
, "9"))
8176 cpu_variant
= (cpu_variant
& ~ARM_ANY
)
8177 | ARM_9
| ARM_ARCH_V4T
;
8178 else if (streq (str
, "920"))
8179 cpu_variant
= (cpu_variant
& ~ARM_ANY
)
8180 | ARM_9
| ARM_ARCH_V4
;
8181 else if (streq (str
, "920t"))
8182 cpu_variant
= (cpu_variant
& ~ARM_ANY
)
8183 | ARM_9
| ARM_ARCH_V4T
;
8184 else if (streq (str
, "9tdmi"))
8185 cpu_variant
= (cpu_variant
& ~ARM_ANY
)
8186 | ARM_9
| ARM_ARCH_V4T
;
8192 if (streq (str
, "strongarm")
8193 || streq (str
, "strongarm110")
8194 || streq (str
, "strongarm1100"))
8195 cpu_variant
= (cpu_variant
& ~ARM_ANY
)
8196 | ARM_8
| ARM_ARCH_V4
;
8202 if (streq (str
, "xscale"))
8203 cpu_variant
= ARM_9
| ARM_ARCH_XSCALE
;
8209 /* Select variant based on architecture rather than
8217 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_3
;
8220 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_2
;
8223 as_bad (_("Invalid architecture variant -m%s"), arg
);
8229 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_7
;
8233 case 'm': cpu_variant
|= ARM_EXT_LONGMUL
; break;
8236 as_bad (_("Invalid architecture variant -m%s"), arg
);
8242 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_7
| ARM_ARCH_V4
;
8246 case 't': cpu_variant
|= ARM_EXT_THUMB
; break;
8249 as_bad (_("Invalid architecture variant -m%s"), arg
);
8255 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_9
| ARM_ARCH_V5
;
8258 case 't': cpu_variant
|= ARM_EXT_THUMB
; break;
8259 case 'e': cpu_variant
|= ARM_EXT_V5E
; break;
8262 as_bad (_("Invalid architecture variant -m%s"), arg
);
8268 as_bad (_("Invalid architecture variant -m%s"), arg
);
8275 as_bad (_("Invalid processor variant -m%s"), arg
);
8281 #if defined OBJ_ELF || defined OBJ_COFF
8299 ARM Specific Assembler Options:\n\
8300 -m[arm][<processor name>] select processor variant\n\
8301 -m[arm]v[2|2a|3|3m|4|4t|5[t][e]] select architecture variant\n\
8302 -mthumb only allow Thumb instructions\n\
8303 -mthumb-interwork mark the assembled code as supporting interworking\n\
8304 -mall allow any instruction\n\
8305 -mfpa10, -mfpa11 select floating point architecture\n\
8306 -mfpe-old don't allow floating-point multiple instructions\n\
8307 -mno-fpu don't allow any floating-point instructions.\n\
8308 -k generate PIC code.\n"));
8309 #if defined OBJ_COFF || defined OBJ_ELF
8311 -mapcs-32, -mapcs-26 specify which ARM Procedure Calling Standard to use\n\
8312 -matpcs use ARM/Thumb Procedure Calling Standard\n\
8313 -mapcs-float floating point args are passed in FP regs\n\
8314 -mapcs-reentrant the code is position independent/reentrant\n"));
8318 -moabi support the old ELF ABI\n"));
8320 #ifdef ARM_BI_ENDIAN
8322 -EB assemble code for a big endian cpu\n\
8323 -EL assemble code for a little endian cpu\n"));
8327 /* We need to be able to fix up arbitrary expressions in some statements.
8328 This is so that we can handle symbols that are an arbitrary distance from
8329 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
8330 which returns part of an address in a form which will be valid for
8331 a data instruction. We do this by pushing the expression into a symbol
8332 in the expr_section, and creating a fix for that. */
8335 fix_new_arm (frag
, where
, size
, exp
, pc_rel
, reloc
)
8344 arm_fix_data
* arm_data
;
8352 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
8356 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
8361 /* Mark whether the fix is to a THUMB instruction, or an ARM
8363 arm_data
= (arm_fix_data
*) obstack_alloc (& notes
, sizeof (arm_fix_data
));
8364 new_fix
->tc_fix_data
= (PTR
) arm_data
;
8365 arm_data
->thumb_mode
= thumb_mode
;
8370 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
8373 cons_fix_new_arm (frag
, where
, size
, exp
)
8379 bfd_reloc_code_real_type type
;
8383 FIXME: @@ Should look at CPU word size. */
8390 type
= BFD_RELOC_16
;
8394 type
= BFD_RELOC_32
;
8397 type
= BFD_RELOC_64
;
8401 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
8404 /* A good place to do this, although this was probably not intended
8405 for this kind of use. We need to dump the literal pool before
8406 references are made to a null symbol pointer. */
8411 if (current_poolP
== NULL
)
8414 /* Put it at the end of text section. */
8415 subseg_set (text_section
, 0);
8417 listing_prev_line ();
8421 arm_start_line_hook ()
8423 last_label_seen
= NULL
;
8427 arm_frob_label (sym
)
8430 last_label_seen
= sym
;
8432 ARM_SET_THUMB (sym
, thumb_mode
);
8434 #if defined OBJ_COFF || defined OBJ_ELF
8435 ARM_SET_INTERWORK (sym
, support_interwork
);
8438 /* Note - do not allow local symbols (.Lxxx) to be labeled
8439 as Thumb functions. This is because these labels, whilst
8440 they exist inside Thumb code, are not the entry points for
8441 possible ARM->Thumb calls. Also, these labels can be used
8442 as part of a computed goto or switch statement. eg gcc
8443 can generate code that looks like this:
8455 The first instruction loads the address of the jump table.
8456 The second instruction converts a table index into a byte offset.
8457 The third instruction gets the jump address out of the table.
8458 The fourth instruction performs the jump.
8460 If the address stored at .Laaa is that of a symbol which has the
8461 Thumb_Func bit set, then the linker will arrange for this address
8462 to have the bottom bit set, which in turn would mean that the
8463 address computation performed by the third instruction would end
8464 up with the bottom bit set. Since the ARM is capable of unaligned
8465 word loads, the instruction would then load the incorrect address
8466 out of the jump table, and chaos would ensue. */
8467 if (label_is_thumb_function_name
8468 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
8469 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
8471 /* When the address of a Thumb function is taken the bottom
8472 bit of that address should be set. This will allow
8473 interworking between Arm and Thumb functions to work
8476 THUMB_SET_FUNC (sym
, 1);
8478 label_is_thumb_function_name
= false;
8482 /* Adjust the symbol table. This marks Thumb symbols as distinct from
8486 arm_adjust_symtab ()
8491 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
8493 if (ARM_IS_THUMB (sym
))
8495 if (THUMB_IS_FUNC (sym
))
8497 /* Mark the symbol as a Thumb function. */
8498 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
8499 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
8500 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
8502 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
8503 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
8505 as_bad (_("%s: unexpected function type: %d"),
8506 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
8508 else switch (S_GET_STORAGE_CLASS (sym
))
8511 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
8514 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
8517 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
8525 if (ARM_IS_INTERWORK (sym
))
8526 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
8533 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
8535 if (ARM_IS_THUMB (sym
))
8537 elf_symbol_type
* elf_sym
;
8539 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
8540 bind
= ELF_ST_BIND (elf_sym
);
8542 /* If it's a .thumb_func, declare it as so,
8543 otherwise tag label as .code 16. */
8544 if (THUMB_IS_FUNC (sym
))
8545 elf_sym
->internal_elf_sym
.st_info
=
8546 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
8548 elf_sym
->internal_elf_sym
.st_info
=
8549 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
8558 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
8560 *input_line_pointer
= '/';
8561 input_line_pointer
+= 5;
8562 *input_line_pointer
= 0;
8570 arm_canonicalize_symbol_name (name
)
8575 if (thumb_mode
&& (len
= strlen (name
)) > 5
8576 && streq (name
+ len
- 5, "/data"))
8577 *(name
+ len
- 5) = 0;
8583 arm_validate_fix (fixP
)
8586 /* If the destination of the branch is a defined symbol which does not have
8587 the THUMB_FUNC attribute, then we must be calling a function which has
8588 the (interfacearm) attribute. We look for the Thumb entry point to that
8589 function and change the branch to refer to that function instead. */
8590 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
8591 && fixP
->fx_addsy
!= NULL
8592 && S_IS_DEFINED (fixP
->fx_addsy
)
8593 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
8595 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
8603 /* This is a little hack to help the gas/arm/adrl.s test. It prevents
8604 local labels from being added to the output symbol table when they
8605 are used with the ADRL pseudo op. The ADRL relocation should always
8606 be resolved before the binbary is emitted, so it is safe to say that
8607 it is adjustable. */
8610 arm_fix_adjustable (fixP
)
8613 if (fixP
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
)
8619 /* Relocations against Thumb function names must be left unadjusted,
8620 so that the linker can use this information to correctly set the
8621 bottom bit of their addresses. The MIPS version of this function
8622 also prevents relocations that are mips-16 specific, but I do not
8623 know why it does this.
8626 There is one other problem that ought to be addressed here, but
8627 which currently is not: Taking the address of a label (rather
8628 than a function) and then later jumping to that address. Such
8629 addresses also ought to have their bottom bit set (assuming that
8630 they reside in Thumb code), but at the moment they will not. */
8633 arm_fix_adjustable (fixP
)
8636 if (fixP
->fx_addsy
== NULL
)
8639 /* Prevent all adjustments to global symbols. */
8640 if (S_IS_EXTERN (fixP
->fx_addsy
))
8643 if (S_IS_WEAK (fixP
->fx_addsy
))
8646 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
8647 && fixP
->fx_subsy
== NULL
)
8650 /* We need the symbol name for the VTABLE entries. */
8651 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
8652 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8659 elf32_arm_target_format ()
8661 if (target_big_endian
)
8664 return "elf32-bigarm-oabi";
8666 return "elf32-bigarm";
8671 return "elf32-littlearm-oabi";
8673 return "elf32-littlearm";
8678 armelf_frob_symbol (symp
, puntp
)
8682 elf_frob_symbol (symp
, puntp
);
8686 arm_force_relocation (fixp
)
8689 if ( fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
8690 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
8691 || fixp
->fx_r_type
== BFD_RELOC_ARM_PCREL_BRANCH
8692 || fixp
->fx_r_type
== BFD_RELOC_ARM_PCREL_BLX
8693 || fixp
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
8694 || fixp
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
)
8700 static bfd_reloc_code_real_type
8710 bfd_reloc_code_real_type reloc
;
8714 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
8715 MAP ("(got)", BFD_RELOC_ARM_GOT32
),
8716 MAP ("(gotoff)", BFD_RELOC_ARM_GOTOFF
),
8717 /* ScottB: Jan 30, 1998 - Added support for parsing "var(PLT)"
8718 branch instructions generated by GCC for PLT relocs. */
8719 MAP ("(plt)", BFD_RELOC_ARM_PLT32
),
8720 { NULL
, 0, BFD_RELOC_UNUSED
}
8724 for (i
= 0, ip
= input_line_pointer
;
8725 i
< sizeof (id
) && (isalnum (*ip
) || ispunct (*ip
));
8727 id
[i
] = tolower (*ip
);
8729 for (i
= 0; reloc_map
[i
].str
; i
++)
8730 if (strncmp (id
, reloc_map
[i
].str
, reloc_map
[i
].len
) == 0)
8733 input_line_pointer
+= reloc_map
[i
].len
;
8735 return reloc_map
[i
].reloc
;
8739 s_arm_elf_cons (nbytes
)
8744 #ifdef md_flush_pending_output
8745 md_flush_pending_output ();
8748 if (is_it_end_of_statement ())
8750 demand_empty_rest_of_line ();
8754 #ifdef md_cons_align
8755 md_cons_align (nbytes
);
8760 bfd_reloc_code_real_type reloc
;
8764 if (exp
.X_op
== O_symbol
8765 && * input_line_pointer
== '('
8766 && (reloc
= arm_parse_reloc ()) != BFD_RELOC_UNUSED
)
8768 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
8769 int size
= bfd_get_reloc_size (howto
);
8772 as_bad ("%s relocations do not fit in %d bytes",
8773 howto
->name
, nbytes
);
8776 register char *p
= frag_more ((int) nbytes
);
8777 int offset
= nbytes
- size
;
8779 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
, size
,
8784 emit_expr (&exp
, (unsigned int) nbytes
);
8786 while (*input_line_pointer
++ == ',');
8788 /* Put terminator back into stream. */
8789 input_line_pointer
--;
8790 demand_empty_rest_of_line ();
8793 #endif /* OBJ_ELF */
8795 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
8796 of an rs_align_code fragment. */
8799 arm_handle_align (fragP
)
8802 static char const arm_noop
[4] = { 0x00, 0x00, 0xa0, 0xe1 };
8803 static char const thumb_noop
[2] = { 0xc0, 0x46 };
8804 static char const arm_bigend_noop
[4] = { 0xe1, 0xa0, 0x00, 0x00 };
8805 static char const thumb_bigend_noop
[2] = { 0x46, 0xc0 };
8807 int bytes
, fix
, noop_size
;
8811 if (fragP
->fr_type
!= rs_align_code
)
8814 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
8815 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
8818 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
8819 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
8821 if (fragP
->tc_frag_data
)
8823 if (target_big_endian
)
8824 noop
= thumb_bigend_noop
;
8827 noop_size
= sizeof (thumb_noop
);
8831 if (target_big_endian
)
8832 noop
= arm_bigend_noop
;
8835 noop_size
= sizeof (arm_noop
);
8838 if (bytes
& (noop_size
- 1))
8840 fix
= bytes
& (noop_size
- 1);
8846 while (bytes
>= noop_size
)
8848 memcpy (p
, noop
, noop_size
);
8854 fragP
->fr_fix
+= fix
;
8855 fragP
->fr_var
= noop_size
;
8858 /* Called from md_do_align. Used to create an alignment
8859 frag in a code section. */
8862 arm_frag_align_code (n
, max
)
8868 /* We assume that there will never be a requirment
8869 to support alignments greater than 32 bytes. */
8870 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
8871 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
8873 p
= frag_var (rs_align_code
,
8874 MAX_MEM_FOR_RS_ALIGN_CODE
,
8876 (relax_substateT
) max
,
8884 /* Perform target specific initialisation of a frag. */
8887 arm_init_frag (fragP
)
8890 /* Record whether this frag is in an ARM or a THUMB area. */
8891 fragP
->tc_frag_data
= thumb_mode
;