1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 #if defined __XSCALE__
101 #define CPU_DEFAULT ARM_ARCH_XSCALE
103 #if defined __thumb__
104 #define CPU_DEFAULT ARM_ARCH_V5T
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 static arm_feature_set cpu_variant
;
130 static arm_feature_set arm_arch_used
;
131 static arm_feature_set thumb_arch_used
;
133 /* Flags stored in private area of BFD structure. */
134 static int uses_apcs_26
= FALSE
;
135 static int atpcs
= FALSE
;
136 static int support_interwork
= FALSE
;
137 static int uses_apcs_float
= FALSE
;
138 static int pic_code
= FALSE
;
139 static int fix_v4bx
= FALSE
;
140 /* Warn on using deprecated features. */
141 static int warn_on_deprecated
= TRUE
;
144 /* Variables that we set while parsing command-line options. Once all
145 options have been read we re-process these values to set the real
147 static const arm_feature_set
*legacy_cpu
= NULL
;
148 static const arm_feature_set
*legacy_fpu
= NULL
;
150 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
151 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
152 static const arm_feature_set
*march_cpu_opt
= NULL
;
153 static const arm_feature_set
*march_fpu_opt
= NULL
;
154 static const arm_feature_set
*mfpu_opt
= NULL
;
155 static const arm_feature_set
*object_arch
= NULL
;
157 /* Constants for known architecture features. */
158 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
159 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
160 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
161 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
162 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
163 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
164 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
165 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
166 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
169 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
172 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
174 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
175 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
176 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
177 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
178 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
179 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
180 static const arm_feature_set arm_ext_v4t_5
=
181 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
182 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
183 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
184 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
185 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
186 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
187 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
188 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
189 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
190 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_m
=
198 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_V7M
, 0);
200 static const arm_feature_set arm_arch_any
= ARM_ANY
;
201 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
202 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
203 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
205 static const arm_feature_set arm_cext_iwmmxt2
=
206 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
207 static const arm_feature_set arm_cext_iwmmxt
=
208 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
209 static const arm_feature_set arm_cext_xscale
=
210 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
211 static const arm_feature_set arm_cext_maverick
=
212 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
213 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
214 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
215 static const arm_feature_set fpu_vfp_ext_v1xd
=
216 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
217 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
218 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
219 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
220 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
221 static const arm_feature_set fpu_vfp_ext_d32
=
222 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
223 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
224 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
225 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
226 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
227 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
228 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
230 static int mfloat_abi_opt
= -1;
231 /* Record user cpu selection for object attributes. */
232 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
233 /* Must be long enough to hold any of the names in arm_cpus. */
234 static char selected_cpu_name
[16];
237 static int meabi_flags
= EABI_DEFAULT
;
239 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
242 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
247 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
252 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
253 symbolS
* GOT_symbol
;
256 /* 0: assemble for ARM,
257 1: assemble for Thumb,
258 2: assemble for Thumb even though target CPU does not support thumb
260 static int thumb_mode
= 0;
261 /* A value distinct from the possible values for thumb_mode that we
262 can use to record whether thumb_mode has been copied into the
263 tc_frag_data field of a frag. */
264 #define MODE_RECORDED (1 << 4)
266 /* Specifies the intrinsic IT insn behavior mode. */
267 enum implicit_it_mode
269 IMPLICIT_IT_MODE_NEVER
= 0x00,
270 IMPLICIT_IT_MODE_ARM
= 0x01,
271 IMPLICIT_IT_MODE_THUMB
= 0x02,
272 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
274 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
276 /* If unified_syntax is true, we are processing the new unified
277 ARM/Thumb syntax. Important differences from the old ARM mode:
279 - Immediate operands do not require a # prefix.
280 - Conditional affixes always appear at the end of the
281 instruction. (For backward compatibility, those instructions
282 that formerly had them in the middle, continue to accept them
284 - The IT instruction may appear, and if it does is validated
285 against subsequent conditional affixes. It does not generate
288 Important differences from the old Thumb mode:
290 - Immediate operands do not require a # prefix.
291 - Most of the V6T2 instructions are only available in unified mode.
292 - The .N and .W suffixes are recognized and honored (it is an error
293 if they cannot be honored).
294 - All instructions set the flags if and only if they have an 's' affix.
295 - Conditional affixes may be used. They are validated against
296 preceding IT instructions. Unlike ARM mode, you cannot use a
297 conditional affix except in the scope of an IT instruction. */
299 static bfd_boolean unified_syntax
= FALSE
;
314 enum neon_el_type type
;
318 #define NEON_MAX_TYPE_ELS 4
322 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
326 enum it_instruction_type
331 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
332 if inside, should be the last one. */
333 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
334 i.e. BKPT and NOP. */
335 IT_INSN
/* The IT insn has been parsed. */
341 unsigned long instruction
;
345 /* "uncond_value" is set to the value in place of the conditional field in
346 unconditional versions of the instruction, or -1 if nothing is
349 struct neon_type vectype
;
350 /* Set to the opcode if the instruction needs relaxation.
351 Zero if the instruction is not relaxed. */
355 bfd_reloc_code_real_type type
;
360 enum it_instruction_type it_insn_type
;
366 struct neon_type_el vectype
;
367 unsigned present
: 1; /* Operand present. */
368 unsigned isreg
: 1; /* Operand was a register. */
369 unsigned immisreg
: 1; /* .imm field is a second register. */
370 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
371 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
372 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
373 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
374 instructions. This allows us to disambiguate ARM <-> vector insns. */
375 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
376 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
377 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
378 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
379 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
380 unsigned writeback
: 1; /* Operand has trailing ! */
381 unsigned preind
: 1; /* Preindexed address. */
382 unsigned postind
: 1; /* Postindexed address. */
383 unsigned negative
: 1; /* Index register was negated. */
384 unsigned shifted
: 1; /* Shift applied to operation. */
385 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
389 static struct arm_it inst
;
391 #define NUM_FLOAT_VALS 8
393 const char * fp_const
[] =
395 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
398 /* Number of littlenums required to hold an extended precision number. */
399 #define MAX_LITTLENUMS 6
401 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
411 #define CP_T_X 0x00008000
412 #define CP_T_Y 0x00400000
414 #define CONDS_BIT 0x00100000
415 #define LOAD_BIT 0x00100000
417 #define DOUBLE_LOAD_FLAG 0x00000001
421 const char * template_name
;
425 #define COND_ALWAYS 0xE
429 const char * template_name
;
433 struct asm_barrier_opt
435 const char * template_name
;
439 /* The bit that distinguishes CPSR and SPSR. */
440 #define SPSR_BIT (1 << 22)
442 /* The individual PSR flag bits. */
443 #define PSR_c (1 << 16)
444 #define PSR_x (1 << 17)
445 #define PSR_s (1 << 18)
446 #define PSR_f (1 << 19)
451 bfd_reloc_code_real_type reloc
;
456 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
457 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
462 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
465 /* Bits for DEFINED field in neon_typed_alias. */
466 #define NTA_HASTYPE 1
467 #define NTA_HASINDEX 2
469 struct neon_typed_alias
471 unsigned char defined
;
473 struct neon_type_el eltype
;
476 /* ARM register categories. This includes coprocessor numbers and various
477 architecture extensions' registers. */
503 /* Structure for a hash table entry for a register.
504 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
505 information which states whether a vector type or index is specified (for a
506 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
510 unsigned char number
;
512 unsigned char builtin
;
513 struct neon_typed_alias
* neon
;
516 /* Diagnostics used when we don't get a register of the expected type. */
517 const char * const reg_expected_msgs
[] =
519 N_("ARM register expected"),
520 N_("bad or missing co-processor number"),
521 N_("co-processor register expected"),
522 N_("FPA register expected"),
523 N_("VFP single precision register expected"),
524 N_("VFP/Neon double precision register expected"),
525 N_("Neon quad precision register expected"),
526 N_("VFP single or double precision register expected"),
527 N_("Neon double or quad precision register expected"),
528 N_("VFP single, double or Neon quad precision register expected"),
529 N_("VFP system register expected"),
530 N_("Maverick MVF register expected"),
531 N_("Maverick MVD register expected"),
532 N_("Maverick MVFX register expected"),
533 N_("Maverick MVDX register expected"),
534 N_("Maverick MVAX register expected"),
535 N_("Maverick DSPSC register expected"),
536 N_("iWMMXt data register expected"),
537 N_("iWMMXt control register expected"),
538 N_("iWMMXt scalar register expected"),
539 N_("XScale accumulator register expected"),
542 /* Some well known registers that we refer to directly elsewhere. */
547 /* ARM instructions take 4bytes in the object file, Thumb instructions
553 /* Basic string to match. */
554 const char * template_name
;
556 /* Parameters to instruction. */
557 unsigned char operands
[8];
559 /* Conditional tag - see opcode_lookup. */
560 unsigned int tag
: 4;
562 /* Basic instruction code. */
563 unsigned int avalue
: 28;
565 /* Thumb-format instruction code. */
568 /* Which architecture variant provides this instruction. */
569 const arm_feature_set
* avariant
;
570 const arm_feature_set
* tvariant
;
572 /* Function to call to encode instruction in ARM format. */
573 void (* aencode
) (void);
575 /* Function to call to encode instruction in Thumb format. */
576 void (* tencode
) (void);
579 /* Defines for various bits that we will want to toggle. */
580 #define INST_IMMEDIATE 0x02000000
581 #define OFFSET_REG 0x02000000
582 #define HWOFFSET_IMM 0x00400000
583 #define SHIFT_BY_REG 0x00000010
584 #define PRE_INDEX 0x01000000
585 #define INDEX_UP 0x00800000
586 #define WRITE_BACK 0x00200000
587 #define LDM_TYPE_2_OR_3 0x00400000
588 #define CPSI_MMOD 0x00020000
590 #define LITERAL_MASK 0xf000f000
591 #define OPCODE_MASK 0xfe1fffff
592 #define V4_STR_BIT 0x00000020
594 #define T2_SUBS_PC_LR 0xf3de8f00
596 #define DATA_OP_SHIFT 21
598 #define T2_OPCODE_MASK 0xfe1fffff
599 #define T2_DATA_OP_SHIFT 21
601 /* Codes to distinguish the arithmetic instructions. */
612 #define OPCODE_CMP 10
613 #define OPCODE_CMN 11
614 #define OPCODE_ORR 12
615 #define OPCODE_MOV 13
616 #define OPCODE_BIC 14
617 #define OPCODE_MVN 15
619 #define T2_OPCODE_AND 0
620 #define T2_OPCODE_BIC 1
621 #define T2_OPCODE_ORR 2
622 #define T2_OPCODE_ORN 3
623 #define T2_OPCODE_EOR 4
624 #define T2_OPCODE_ADD 8
625 #define T2_OPCODE_ADC 10
626 #define T2_OPCODE_SBC 11
627 #define T2_OPCODE_SUB 13
628 #define T2_OPCODE_RSB 14
630 #define T_OPCODE_MUL 0x4340
631 #define T_OPCODE_TST 0x4200
632 #define T_OPCODE_CMN 0x42c0
633 #define T_OPCODE_NEG 0x4240
634 #define T_OPCODE_MVN 0x43c0
636 #define T_OPCODE_ADD_R3 0x1800
637 #define T_OPCODE_SUB_R3 0x1a00
638 #define T_OPCODE_ADD_HI 0x4400
639 #define T_OPCODE_ADD_ST 0xb000
640 #define T_OPCODE_SUB_ST 0xb080
641 #define T_OPCODE_ADD_SP 0xa800
642 #define T_OPCODE_ADD_PC 0xa000
643 #define T_OPCODE_ADD_I8 0x3000
644 #define T_OPCODE_SUB_I8 0x3800
645 #define T_OPCODE_ADD_I3 0x1c00
646 #define T_OPCODE_SUB_I3 0x1e00
648 #define T_OPCODE_ASR_R 0x4100
649 #define T_OPCODE_LSL_R 0x4080
650 #define T_OPCODE_LSR_R 0x40c0
651 #define T_OPCODE_ROR_R 0x41c0
652 #define T_OPCODE_ASR_I 0x1000
653 #define T_OPCODE_LSL_I 0x0000
654 #define T_OPCODE_LSR_I 0x0800
656 #define T_OPCODE_MOV_I8 0x2000
657 #define T_OPCODE_CMP_I8 0x2800
658 #define T_OPCODE_CMP_LR 0x4280
659 #define T_OPCODE_MOV_HR 0x4600
660 #define T_OPCODE_CMP_HR 0x4500
662 #define T_OPCODE_LDR_PC 0x4800
663 #define T_OPCODE_LDR_SP 0x9800
664 #define T_OPCODE_STR_SP 0x9000
665 #define T_OPCODE_LDR_IW 0x6800
666 #define T_OPCODE_STR_IW 0x6000
667 #define T_OPCODE_LDR_IH 0x8800
668 #define T_OPCODE_STR_IH 0x8000
669 #define T_OPCODE_LDR_IB 0x7800
670 #define T_OPCODE_STR_IB 0x7000
671 #define T_OPCODE_LDR_RW 0x5800
672 #define T_OPCODE_STR_RW 0x5000
673 #define T_OPCODE_LDR_RH 0x5a00
674 #define T_OPCODE_STR_RH 0x5200
675 #define T_OPCODE_LDR_RB 0x5c00
676 #define T_OPCODE_STR_RB 0x5400
678 #define T_OPCODE_PUSH 0xb400
679 #define T_OPCODE_POP 0xbc00
681 #define T_OPCODE_BRANCH 0xe000
683 #define THUMB_SIZE 2 /* Size of thumb instruction. */
684 #define THUMB_PP_PC_LR 0x0100
685 #define THUMB_LOAD_BIT 0x0800
686 #define THUMB2_LOAD_BIT 0x00100000
688 #define BAD_ARGS _("bad arguments to instruction")
689 #define BAD_SP _("r13 not allowed here")
690 #define BAD_PC _("r15 not allowed here")
691 #define BAD_COND _("instruction cannot be conditional")
692 #define BAD_OVERLAP _("registers may not be the same")
693 #define BAD_HIREG _("lo register required")
694 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
695 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
696 #define BAD_BRANCH _("branch must be last instruction in IT block")
697 #define BAD_NOT_IT _("instruction not allowed in IT block")
698 #define BAD_FPU _("selected FPU does not support instruction")
699 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
700 #define BAD_IT_COND _("incorrect condition in IT block")
701 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
702 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
704 static struct hash_control
* arm_ops_hsh
;
705 static struct hash_control
* arm_cond_hsh
;
706 static struct hash_control
* arm_shift_hsh
;
707 static struct hash_control
* arm_psr_hsh
;
708 static struct hash_control
* arm_v7m_psr_hsh
;
709 static struct hash_control
* arm_reg_hsh
;
710 static struct hash_control
* arm_reloc_hsh
;
711 static struct hash_control
* arm_barrier_opt_hsh
;
713 /* Stuff needed to resolve the label ambiguity
722 symbolS
* last_label_seen
;
723 static int label_is_thumb_function_name
= FALSE
;
725 /* Literal pool structure. Held on a per-section
726 and per-sub-section basis. */
728 #define MAX_LITERAL_POOL_SIZE 1024
729 typedef struct literal_pool
731 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
732 unsigned int next_free_entry
;
737 struct literal_pool
* next
;
740 /* Pointer to a linked list of literal pools. */
741 literal_pool
* list_of_pools
= NULL
;
744 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
746 static struct current_it now_it
;
750 now_it_compatible (int cond
)
752 return (cond
& ~1) == (now_it
.cc
& ~1);
756 conditional_insn (void)
758 return inst
.cond
!= COND_ALWAYS
;
761 static int in_it_block (void);
763 static int handle_it_state (void);
765 static void force_automatic_it_block_close (void);
767 static void it_fsm_post_encode (void);
769 #define set_it_insn_type(type) \
772 inst.it_insn_type = type; \
773 if (handle_it_state () == FAIL) \
778 #define set_it_insn_type_nonvoid(type, failret) \
781 inst.it_insn_type = type; \
782 if (handle_it_state () == FAIL) \
787 #define set_it_insn_type_last() \
790 if (inst.cond == COND_ALWAYS) \
791 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
793 set_it_insn_type (INSIDE_IT_LAST_INSN); \
799 /* This array holds the chars that always start a comment. If the
800 pre-processor is disabled, these aren't very useful. */
801 const char comment_chars
[] = "@";
803 /* This array holds the chars that only start a comment at the beginning of
804 a line. If the line seems to have the form '# 123 filename'
805 .line and .file directives will appear in the pre-processed output. */
806 /* Note that input_file.c hand checks for '#' at the beginning of the
807 first line of the input file. This is because the compiler outputs
808 #NO_APP at the beginning of its output. */
809 /* Also note that comments like this one will always work. */
810 const char line_comment_chars
[] = "#";
812 const char line_separator_chars
[] = ";";
814 /* Chars that can be used to separate mant
815 from exp in floating point numbers. */
816 const char EXP_CHARS
[] = "eE";
818 /* Chars that mean this number is a floating point constant. */
822 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
824 /* Prefix characters that indicate the start of an immediate
826 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
828 /* Separator character handling. */
830 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
833 skip_past_char (char ** str
, char c
)
844 #define skip_past_comma(str) skip_past_char (str, ',')
846 /* Arithmetic expressions (possibly involving symbols). */
848 /* Return TRUE if anything in the expression is a bignum. */
851 walk_no_bignums (symbolS
* sp
)
853 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
856 if (symbol_get_value_expression (sp
)->X_add_symbol
)
858 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
859 || (symbol_get_value_expression (sp
)->X_op_symbol
860 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
866 static int in_my_get_expression
= 0;
868 /* Third argument to my_get_expression. */
869 #define GE_NO_PREFIX 0
870 #define GE_IMM_PREFIX 1
871 #define GE_OPT_PREFIX 2
872 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
873 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
874 #define GE_OPT_PREFIX_BIG 3
877 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
882 /* In unified syntax, all prefixes are optional. */
884 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
889 case GE_NO_PREFIX
: break;
891 if (!is_immediate_prefix (**str
))
893 inst
.error
= _("immediate expression requires a # prefix");
899 case GE_OPT_PREFIX_BIG
:
900 if (is_immediate_prefix (**str
))
906 memset (ep
, 0, sizeof (expressionS
));
908 save_in
= input_line_pointer
;
909 input_line_pointer
= *str
;
910 in_my_get_expression
= 1;
911 seg
= expression (ep
);
912 in_my_get_expression
= 0;
914 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
916 /* We found a bad or missing expression in md_operand(). */
917 *str
= input_line_pointer
;
918 input_line_pointer
= save_in
;
919 if (inst
.error
== NULL
)
920 inst
.error
= (ep
->X_op
== O_absent
921 ? _("missing expression") :_("bad expression"));
926 if (seg
!= absolute_section
927 && seg
!= text_section
928 && seg
!= data_section
929 && seg
!= bss_section
930 && seg
!= undefined_section
)
932 inst
.error
= _("bad segment");
933 *str
= input_line_pointer
;
934 input_line_pointer
= save_in
;
939 /* Get rid of any bignums now, so that we don't generate an error for which
940 we can't establish a line number later on. Big numbers are never valid
941 in instructions, which is where this routine is always called. */
942 if (prefix_mode
!= GE_OPT_PREFIX_BIG
943 && (ep
->X_op
== O_big
945 && (walk_no_bignums (ep
->X_add_symbol
)
947 && walk_no_bignums (ep
->X_op_symbol
))))))
949 inst
.error
= _("invalid constant");
950 *str
= input_line_pointer
;
951 input_line_pointer
= save_in
;
955 *str
= input_line_pointer
;
956 input_line_pointer
= save_in
;
960 /* Turn a string in input_line_pointer into a floating point constant
961 of type TYPE, and store the appropriate bytes in *LITP. The number
962 of LITTLENUMS emitted is stored in *SIZEP. An error message is
963 returned, or NULL on OK.
965 Note that fp constants aren't represent in the normal way on the ARM.
966 In big endian mode, things are as expected. However, in little endian
967 mode fp constants are big-endian word-wise, and little-endian byte-wise
968 within the words. For example, (double) 1.1 in big endian mode is
969 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
970 the byte sequence 99 99 f1 3f 9a 99 99 99.
972 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
975 md_atof (int type
, char * litP
, int * sizeP
)
978 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1010 return _("Unrecognized or unsupported floating point constant");
1013 t
= atof_ieee (input_line_pointer
, type
, words
);
1015 input_line_pointer
= t
;
1016 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1018 if (target_big_endian
)
1020 for (i
= 0; i
< prec
; i
++)
1022 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1023 litP
+= sizeof (LITTLENUM_TYPE
);
1028 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1029 for (i
= prec
- 1; i
>= 0; i
--)
1031 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1032 litP
+= sizeof (LITTLENUM_TYPE
);
1035 /* For a 4 byte float the order of elements in `words' is 1 0.
1036 For an 8 byte float the order is 1 0 3 2. */
1037 for (i
= 0; i
< prec
; i
+= 2)
1039 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1040 sizeof (LITTLENUM_TYPE
));
1041 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1042 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1043 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1050 /* We handle all bad expressions here, so that we can report the faulty
1051 instruction in the error message. */
1053 md_operand (expressionS
* expr
)
1055 if (in_my_get_expression
)
1056 expr
->X_op
= O_illegal
;
1059 /* Immediate values. */
1061 /* Generic immediate-value read function for use in directives.
1062 Accepts anything that 'expression' can fold to a constant.
1063 *val receives the number. */
1066 immediate_for_directive (int *val
)
1069 exp
.X_op
= O_illegal
;
1071 if (is_immediate_prefix (*input_line_pointer
))
1073 input_line_pointer
++;
1077 if (exp
.X_op
!= O_constant
)
1079 as_bad (_("expected #constant"));
1080 ignore_rest_of_line ();
1083 *val
= exp
.X_add_number
;
1088 /* Register parsing. */
1090 /* Generic register parser. CCP points to what should be the
1091 beginning of a register name. If it is indeed a valid register
1092 name, advance CCP over it and return the reg_entry structure;
1093 otherwise return NULL. Does not issue diagnostics. */
1095 static struct reg_entry
*
1096 arm_reg_parse_multi (char **ccp
)
1100 struct reg_entry
*reg
;
1102 #ifdef REGISTER_PREFIX
1103 if (*start
!= REGISTER_PREFIX
)
1107 #ifdef OPTIONAL_REGISTER_PREFIX
1108 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1113 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1118 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1120 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1130 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1131 enum arm_reg_type type
)
1133 /* Alternative syntaxes are accepted for a few register classes. */
1140 /* Generic coprocessor register names are allowed for these. */
1141 if (reg
&& reg
->type
== REG_TYPE_CN
)
1146 /* For backward compatibility, a bare number is valid here. */
1148 unsigned long processor
= strtoul (start
, ccp
, 10);
1149 if (*ccp
!= start
&& processor
<= 15)
1153 case REG_TYPE_MMXWC
:
1154 /* WC includes WCG. ??? I'm not sure this is true for all
1155 instructions that take WC registers. */
1156 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1167 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1168 return value is the register number or FAIL. */
1171 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1174 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1177 /* Do not allow a scalar (reg+index) to parse as a register. */
1178 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1181 if (reg
&& reg
->type
== type
)
1184 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1191 /* Parse a Neon type specifier. *STR should point at the leading '.'
1192 character. Does no verification at this stage that the type fits the opcode
1199 Can all be legally parsed by this function.
1201 Fills in neon_type struct pointer with parsed information, and updates STR
1202 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1203 type, FAIL if not. */
1206 parse_neon_type (struct neon_type
*type
, char **str
)
1213 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1215 enum neon_el_type thistype
= NT_untyped
;
1216 unsigned thissize
= -1u;
1223 /* Just a size without an explicit type. */
1227 switch (TOLOWER (*ptr
))
1229 case 'i': thistype
= NT_integer
; break;
1230 case 'f': thistype
= NT_float
; break;
1231 case 'p': thistype
= NT_poly
; break;
1232 case 's': thistype
= NT_signed
; break;
1233 case 'u': thistype
= NT_unsigned
; break;
1235 thistype
= NT_float
;
1240 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1246 /* .f is an abbreviation for .f32. */
1247 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1252 thissize
= strtoul (ptr
, &ptr
, 10);
1254 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1257 as_bad (_("bad size %d in type specifier"), thissize
);
1265 type
->el
[type
->elems
].type
= thistype
;
1266 type
->el
[type
->elems
].size
= thissize
;
1271 /* Empty/missing type is not a successful parse. */
1272 if (type
->elems
== 0)
1280 /* Errors may be set multiple times during parsing or bit encoding
1281 (particularly in the Neon bits), but usually the earliest error which is set
1282 will be the most meaningful. Avoid overwriting it with later (cascading)
1283 errors by calling this function. */
1286 first_error (const char *err
)
1292 /* Parse a single type, e.g. ".s32", leading period included. */
1294 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1297 struct neon_type optype
;
1301 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1303 if (optype
.elems
== 1)
1304 *vectype
= optype
.el
[0];
1307 first_error (_("only one type should be specified for operand"));
1313 first_error (_("vector type expected"));
1325 /* Special meanings for indices (which have a range of 0-7), which will fit into
1328 #define NEON_ALL_LANES 15
1329 #define NEON_INTERLEAVE_LANES 14
1331 /* Parse either a register or a scalar, with an optional type. Return the
1332 register number, and optionally fill in the actual type of the register
1333 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1334 type/index information in *TYPEINFO. */
1337 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1338 enum arm_reg_type
*rtype
,
1339 struct neon_typed_alias
*typeinfo
)
1342 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1343 struct neon_typed_alias atype
;
1344 struct neon_type_el parsetype
;
1348 atype
.eltype
.type
= NT_invtype
;
1349 atype
.eltype
.size
= -1;
1351 /* Try alternate syntax for some types of register. Note these are mutually
1352 exclusive with the Neon syntax extensions. */
1355 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1363 /* Undo polymorphism when a set of register types may be accepted. */
1364 if ((type
== REG_TYPE_NDQ
1365 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1366 || (type
== REG_TYPE_VFSD
1367 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1368 || (type
== REG_TYPE_NSDQ
1369 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1370 || reg
->type
== REG_TYPE_NQ
))
1371 || (type
== REG_TYPE_MMXWC
1372 && (reg
->type
== REG_TYPE_MMXWCG
)))
1373 type
= (enum arm_reg_type
) reg
->type
;
1375 if (type
!= reg
->type
)
1381 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1383 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1385 first_error (_("can't redefine type for operand"));
1388 atype
.defined
|= NTA_HASTYPE
;
1389 atype
.eltype
= parsetype
;
1392 if (skip_past_char (&str
, '[') == SUCCESS
)
1394 if (type
!= REG_TYPE_VFD
)
1396 first_error (_("only D registers may be indexed"));
1400 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1402 first_error (_("can't change index for operand"));
1406 atype
.defined
|= NTA_HASINDEX
;
1408 if (skip_past_char (&str
, ']') == SUCCESS
)
1409 atype
.index
= NEON_ALL_LANES
;
1414 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1416 if (exp
.X_op
!= O_constant
)
1418 first_error (_("constant expression required"));
1422 if (skip_past_char (&str
, ']') == FAIL
)
1425 atype
.index
= exp
.X_add_number
;
1440 /* Like arm_reg_parse, but allow allow the following extra features:
1441 - If RTYPE is non-zero, return the (possibly restricted) type of the
1442 register (e.g. Neon double or quad reg when either has been requested).
1443 - If this is a Neon vector type with additional type information, fill
1444 in the struct pointed to by VECTYPE (if non-NULL).
1445 This function will fault on encountering a scalar. */
1448 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1449 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1451 struct neon_typed_alias atype
;
1453 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1458 /* Do not allow a scalar (reg+index) to parse as a register. */
1459 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1461 first_error (_("register operand expected, but got scalar"));
1466 *vectype
= atype
.eltype
;
1473 #define NEON_SCALAR_REG(X) ((X) >> 4)
1474 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1476 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1477 have enough information to be able to do a good job bounds-checking. So, we
1478 just do easy checks here, and do further checks later. */
1481 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1485 struct neon_typed_alias atype
;
1487 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1489 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1492 if (atype
.index
== NEON_ALL_LANES
)
1494 first_error (_("scalar must have an index"));
1497 else if (atype
.index
>= 64 / elsize
)
1499 first_error (_("scalar index out of range"));
1504 *type
= atype
.eltype
;
1508 return reg
* 16 + atype
.index
;
1511 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1514 parse_reg_list (char ** strp
)
1516 char * str
= * strp
;
1520 /* We come back here if we get ranges concatenated by '+' or '|'. */
1535 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1537 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1547 first_error (_("bad range in register list"));
1551 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1553 if (range
& (1 << i
))
1555 (_("Warning: duplicated register (r%d) in register list"),
1563 if (range
& (1 << reg
))
1564 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1566 else if (reg
<= cur_reg
)
1567 as_tsktsk (_("Warning: register range not in ascending order"));
1572 while (skip_past_comma (&str
) != FAIL
1573 || (in_range
= 1, *str
++ == '-'));
1578 first_error (_("missing `}'"));
1586 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1589 if (expr
.X_op
== O_constant
)
1591 if (expr
.X_add_number
1592 != (expr
.X_add_number
& 0x0000ffff))
1594 inst
.error
= _("invalid register mask");
1598 if ((range
& expr
.X_add_number
) != 0)
1600 int regno
= range
& expr
.X_add_number
;
1603 regno
= (1 << regno
) - 1;
1605 (_("Warning: duplicated register (r%d) in register list"),
1609 range
|= expr
.X_add_number
;
1613 if (inst
.reloc
.type
!= 0)
1615 inst
.error
= _("expression too complex");
1619 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1620 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1621 inst
.reloc
.pc_rel
= 0;
1625 if (*str
== '|' || *str
== '+')
1631 while (another_range
);
1637 /* Types of registers in a list. */
1646 /* Parse a VFP register list. If the string is invalid return FAIL.
1647 Otherwise return the number of registers, and set PBASE to the first
1648 register. Parses registers of type ETYPE.
1649 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1650 - Q registers can be used to specify pairs of D registers
1651 - { } can be omitted from around a singleton register list
1652 FIXME: This is not implemented, as it would require backtracking in
1655 This could be done (the meaning isn't really ambiguous), but doesn't
1656 fit in well with the current parsing framework.
1657 - 32 D registers may be used (also true for VFPv3).
1658 FIXME: Types are ignored in these register lists, which is probably a
1662 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1667 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1671 unsigned long mask
= 0;
1676 inst
.error
= _("expecting {");
1685 regtype
= REG_TYPE_VFS
;
1690 regtype
= REG_TYPE_VFD
;
1693 case REGLIST_NEON_D
:
1694 regtype
= REG_TYPE_NDQ
;
1698 if (etype
!= REGLIST_VFP_S
)
1700 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1701 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1705 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1708 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1715 base_reg
= max_regs
;
1719 int setmask
= 1, addregs
= 1;
1721 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1723 if (new_base
== FAIL
)
1725 first_error (_(reg_expected_msgs
[regtype
]));
1729 if (new_base
>= max_regs
)
1731 first_error (_("register out of range in list"));
1735 /* Note: a value of 2 * n is returned for the register Q<n>. */
1736 if (regtype
== REG_TYPE_NQ
)
1742 if (new_base
< base_reg
)
1743 base_reg
= new_base
;
1745 if (mask
& (setmask
<< new_base
))
1747 first_error (_("invalid register list"));
1751 if ((mask
>> new_base
) != 0 && ! warned
)
1753 as_tsktsk (_("register list not in ascending order"));
1757 mask
|= setmask
<< new_base
;
1760 if (*str
== '-') /* We have the start of a range expression */
1766 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1769 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1773 if (high_range
>= max_regs
)
1775 first_error (_("register out of range in list"));
1779 if (regtype
== REG_TYPE_NQ
)
1780 high_range
= high_range
+ 1;
1782 if (high_range
<= new_base
)
1784 inst
.error
= _("register range not in ascending order");
1788 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1790 if (mask
& (setmask
<< new_base
))
1792 inst
.error
= _("invalid register list");
1796 mask
|= setmask
<< new_base
;
1801 while (skip_past_comma (&str
) != FAIL
);
1805 /* Sanity check -- should have raised a parse error above. */
1806 if (count
== 0 || count
> max_regs
)
1811 /* Final test -- the registers must be consecutive. */
1813 for (i
= 0; i
< count
; i
++)
1815 if ((mask
& (1u << i
)) == 0)
1817 inst
.error
= _("non-contiguous register range");
1827 /* True if two alias types are the same. */
1830 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1838 if (a
->defined
!= b
->defined
)
1841 if ((a
->defined
& NTA_HASTYPE
) != 0
1842 && (a
->eltype
.type
!= b
->eltype
.type
1843 || a
->eltype
.size
!= b
->eltype
.size
))
1846 if ((a
->defined
& NTA_HASINDEX
) != 0
1847 && (a
->index
!= b
->index
))
1853 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1854 The base register is put in *PBASE.
1855 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1857 The register stride (minus one) is put in bit 4 of the return value.
1858 Bits [6:5] encode the list length (minus one).
1859 The type of the list elements is put in *ELTYPE, if non-NULL. */
1861 #define NEON_LANE(X) ((X) & 0xf)
1862 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1863 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1866 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1867 struct neon_type_el
*eltype
)
1874 int leading_brace
= 0;
1875 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1877 const char *const incr_error
= _("register stride must be 1 or 2");
1878 const char *const type_error
= _("mismatched element/structure types in list");
1879 struct neon_typed_alias firsttype
;
1881 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1886 struct neon_typed_alias atype
;
1887 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1891 first_error (_(reg_expected_msgs
[rtype
]));
1898 if (rtype
== REG_TYPE_NQ
)
1905 else if (reg_incr
== -1)
1907 reg_incr
= getreg
- base_reg
;
1908 if (reg_incr
< 1 || reg_incr
> 2)
1910 first_error (_(incr_error
));
1914 else if (getreg
!= base_reg
+ reg_incr
* count
)
1916 first_error (_(incr_error
));
1920 if (! neon_alias_types_same (&atype
, &firsttype
))
1922 first_error (_(type_error
));
1926 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1930 struct neon_typed_alias htype
;
1931 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1933 lane
= NEON_INTERLEAVE_LANES
;
1934 else if (lane
!= NEON_INTERLEAVE_LANES
)
1936 first_error (_(type_error
));
1941 else if (reg_incr
!= 1)
1943 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1947 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1950 first_error (_(reg_expected_msgs
[rtype
]));
1953 if (! neon_alias_types_same (&htype
, &firsttype
))
1955 first_error (_(type_error
));
1958 count
+= hireg
+ dregs
- getreg
;
1962 /* If we're using Q registers, we can't use [] or [n] syntax. */
1963 if (rtype
== REG_TYPE_NQ
)
1969 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1973 else if (lane
!= atype
.index
)
1975 first_error (_(type_error
));
1979 else if (lane
== -1)
1980 lane
= NEON_INTERLEAVE_LANES
;
1981 else if (lane
!= NEON_INTERLEAVE_LANES
)
1983 first_error (_(type_error
));
1988 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1990 /* No lane set by [x]. We must be interleaving structures. */
1992 lane
= NEON_INTERLEAVE_LANES
;
1995 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
1996 || (count
> 1 && reg_incr
== -1))
1998 first_error (_("error parsing element/structure list"));
2002 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2004 first_error (_("expected }"));
2012 *eltype
= firsttype
.eltype
;
2017 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2020 /* Parse an explicit relocation suffix on an expression. This is
2021 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2022 arm_reloc_hsh contains no entries, so this function can only
2023 succeed if there is no () after the word. Returns -1 on error,
2024 BFD_RELOC_UNUSED if there wasn't any suffix. */
2026 parse_reloc (char **str
)
2028 struct reloc_entry
*r
;
2032 return BFD_RELOC_UNUSED
;
2037 while (*q
&& *q
!= ')' && *q
!= ',')
2042 if ((r
= (struct reloc_entry
*)
2043 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2050 /* Directives: register aliases. */
2052 static struct reg_entry
*
2053 insert_reg_alias (char *str
, int number
, int type
)
2055 struct reg_entry
*new_reg
;
2058 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2060 if (new_reg
->builtin
)
2061 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2063 /* Only warn about a redefinition if it's not defined as the
2065 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2066 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2071 name
= xstrdup (str
);
2072 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2074 new_reg
->name
= name
;
2075 new_reg
->number
= number
;
2076 new_reg
->type
= type
;
2077 new_reg
->builtin
= FALSE
;
2078 new_reg
->neon
= NULL
;
2080 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2087 insert_neon_reg_alias (char *str
, int number
, int type
,
2088 struct neon_typed_alias
*atype
)
2090 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2094 first_error (_("attempt to redefine typed alias"));
2100 reg
->neon
= (struct neon_typed_alias
*)
2101 xmalloc (sizeof (struct neon_typed_alias
));
2102 *reg
->neon
= *atype
;
2106 /* Look for the .req directive. This is of the form:
2108 new_register_name .req existing_register_name
2110 If we find one, or if it looks sufficiently like one that we want to
2111 handle any error here, return TRUE. Otherwise return FALSE. */
2114 create_register_alias (char * newname
, char *p
)
2116 struct reg_entry
*old
;
2117 char *oldname
, *nbuf
;
2120 /* The input scrubber ensures that whitespace after the mnemonic is
2121 collapsed to single spaces. */
2123 if (strncmp (oldname
, " .req ", 6) != 0)
2127 if (*oldname
== '\0')
2130 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2133 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2137 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2138 the desired alias name, and p points to its end. If not, then
2139 the desired alias name is in the global original_case_string. */
2140 #ifdef TC_CASE_SENSITIVE
2143 newname
= original_case_string
;
2144 nlen
= strlen (newname
);
2147 nbuf
= (char *) alloca (nlen
+ 1);
2148 memcpy (nbuf
, newname
, nlen
);
2151 /* Create aliases under the new name as stated; an all-lowercase
2152 version of the new name; and an all-uppercase version of the new
2154 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2156 for (p
= nbuf
; *p
; p
++)
2159 if (strncmp (nbuf
, newname
, nlen
))
2161 /* If this attempt to create an additional alias fails, do not bother
2162 trying to create the all-lower case alias. We will fail and issue
2163 a second, duplicate error message. This situation arises when the
2164 programmer does something like:
2167 The second .req creates the "Foo" alias but then fails to create
2168 the artificial FOO alias because it has already been created by the
2170 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2174 for (p
= nbuf
; *p
; p
++)
2177 if (strncmp (nbuf
, newname
, nlen
))
2178 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2184 /* Create a Neon typed/indexed register alias using directives, e.g.:
2189 These typed registers can be used instead of the types specified after the
2190 Neon mnemonic, so long as all operands given have types. Types can also be
2191 specified directly, e.g.:
2192 vadd d0.s32, d1.s32, d2.s32 */
2195 create_neon_reg_alias (char *newname
, char *p
)
2197 enum arm_reg_type basetype
;
2198 struct reg_entry
*basereg
;
2199 struct reg_entry mybasereg
;
2200 struct neon_type ntype
;
2201 struct neon_typed_alias typeinfo
;
2202 char *namebuf
, *nameend
;
2205 typeinfo
.defined
= 0;
2206 typeinfo
.eltype
.type
= NT_invtype
;
2207 typeinfo
.eltype
.size
= -1;
2208 typeinfo
.index
= -1;
2212 if (strncmp (p
, " .dn ", 5) == 0)
2213 basetype
= REG_TYPE_VFD
;
2214 else if (strncmp (p
, " .qn ", 5) == 0)
2215 basetype
= REG_TYPE_NQ
;
2224 basereg
= arm_reg_parse_multi (&p
);
2226 if (basereg
&& basereg
->type
!= basetype
)
2228 as_bad (_("bad type for register"));
2232 if (basereg
== NULL
)
2235 /* Try parsing as an integer. */
2236 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2237 if (exp
.X_op
!= O_constant
)
2239 as_bad (_("expression must be constant"));
2242 basereg
= &mybasereg
;
2243 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2249 typeinfo
= *basereg
->neon
;
2251 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2253 /* We got a type. */
2254 if (typeinfo
.defined
& NTA_HASTYPE
)
2256 as_bad (_("can't redefine the type of a register alias"));
2260 typeinfo
.defined
|= NTA_HASTYPE
;
2261 if (ntype
.elems
!= 1)
2263 as_bad (_("you must specify a single type only"));
2266 typeinfo
.eltype
= ntype
.el
[0];
2269 if (skip_past_char (&p
, '[') == SUCCESS
)
2272 /* We got a scalar index. */
2274 if (typeinfo
.defined
& NTA_HASINDEX
)
2276 as_bad (_("can't redefine the index of a scalar alias"));
2280 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2282 if (exp
.X_op
!= O_constant
)
2284 as_bad (_("scalar index must be constant"));
2288 typeinfo
.defined
|= NTA_HASINDEX
;
2289 typeinfo
.index
= exp
.X_add_number
;
2291 if (skip_past_char (&p
, ']') == FAIL
)
2293 as_bad (_("expecting ]"));
2298 namelen
= nameend
- newname
;
2299 namebuf
= (char *) alloca (namelen
+ 1);
2300 strncpy (namebuf
, newname
, namelen
);
2301 namebuf
[namelen
] = '\0';
2303 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2304 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2306 /* Insert name in all uppercase. */
2307 for (p
= namebuf
; *p
; p
++)
2310 if (strncmp (namebuf
, newname
, namelen
))
2311 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2312 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2314 /* Insert name in all lowercase. */
2315 for (p
= namebuf
; *p
; p
++)
2318 if (strncmp (namebuf
, newname
, namelen
))
2319 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2320 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2325 /* Should never be called, as .req goes between the alias and the
2326 register name, not at the beginning of the line. */
2329 s_req (int a ATTRIBUTE_UNUSED
)
2331 as_bad (_("invalid syntax for .req directive"));
2335 s_dn (int a ATTRIBUTE_UNUSED
)
2337 as_bad (_("invalid syntax for .dn directive"));
2341 s_qn (int a ATTRIBUTE_UNUSED
)
2343 as_bad (_("invalid syntax for .qn directive"));
2346 /* The .unreq directive deletes an alias which was previously defined
2347 by .req. For example:
2353 s_unreq (int a ATTRIBUTE_UNUSED
)
2358 name
= input_line_pointer
;
2360 while (*input_line_pointer
!= 0
2361 && *input_line_pointer
!= ' '
2362 && *input_line_pointer
!= '\n')
2363 ++input_line_pointer
;
2365 saved_char
= *input_line_pointer
;
2366 *input_line_pointer
= 0;
2369 as_bad (_("invalid syntax for .unreq directive"));
2372 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2376 as_bad (_("unknown register alias '%s'"), name
);
2377 else if (reg
->builtin
)
2378 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2385 hash_delete (arm_reg_hsh
, name
, FALSE
);
2386 free ((char *) reg
->name
);
2391 /* Also locate the all upper case and all lower case versions.
2392 Do not complain if we cannot find one or the other as it
2393 was probably deleted above. */
2395 nbuf
= strdup (name
);
2396 for (p
= nbuf
; *p
; p
++)
2398 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2401 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2402 free ((char *) reg
->name
);
2408 for (p
= nbuf
; *p
; p
++)
2410 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2413 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2414 free ((char *) reg
->name
);
2424 *input_line_pointer
= saved_char
;
2425 demand_empty_rest_of_line ();
2428 /* Directives: Instruction set selection. */
2431 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2432 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2433 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2434 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2436 /* Create a new mapping symbol for the transition to STATE. */
2439 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2442 const char * symname
;
2449 type
= BSF_NO_FLAGS
;
2453 type
= BSF_NO_FLAGS
;
2457 type
= BSF_NO_FLAGS
;
2463 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2464 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2469 THUMB_SET_FUNC (symbolP
, 0);
2470 ARM_SET_THUMB (symbolP
, 0);
2471 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2475 THUMB_SET_FUNC (symbolP
, 1);
2476 ARM_SET_THUMB (symbolP
, 1);
2477 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2485 /* Save the mapping symbols for future reference. Also check that
2486 we do not place two mapping symbols at the same offset within a
2487 frag. We'll handle overlap between frags in
2488 check_mapping_symbols. */
2491 know (frag
->tc_frag_data
.first_map
== NULL
);
2492 frag
->tc_frag_data
.first_map
= symbolP
;
2494 if (frag
->tc_frag_data
.last_map
!= NULL
)
2495 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) < S_GET_VALUE (symbolP
));
2496 frag
->tc_frag_data
.last_map
= symbolP
;
2499 /* We must sometimes convert a region marked as code to data during
2500 code alignment, if an odd number of bytes have to be padded. The
2501 code mapping symbol is pushed to an aligned address. */
2504 insert_data_mapping_symbol (enum mstate state
,
2505 valueT value
, fragS
*frag
, offsetT bytes
)
2507 /* If there was already a mapping symbol, remove it. */
2508 if (frag
->tc_frag_data
.last_map
!= NULL
2509 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2511 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2515 know (frag
->tc_frag_data
.first_map
== symp
);
2516 frag
->tc_frag_data
.first_map
= NULL
;
2518 frag
->tc_frag_data
.last_map
= NULL
;
2519 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2522 make_mapping_symbol (MAP_DATA
, value
, frag
);
2523 make_mapping_symbol (state
, value
+ bytes
, frag
);
2526 static void mapping_state_2 (enum mstate state
, int max_chars
);
2528 /* Set the mapping state to STATE. Only call this when about to
2529 emit some STATE bytes to the file. */
2532 mapping_state (enum mstate state
)
2534 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2536 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2538 if (mapstate
== state
)
2539 /* The mapping symbol has already been emitted.
2540 There is nothing else to do. */
2542 else if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2543 /* This case will be evaluated later in the next else. */
2545 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2546 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2548 /* Only add the symbol if the offset is > 0:
2549 if we're at the first frag, check it's size > 0;
2550 if we're not at the first frag, then for sure
2551 the offset is > 0. */
2552 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2553 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2556 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2559 mapping_state_2 (state
, 0);
2563 /* Same as mapping_state, but MAX_CHARS bytes have already been
2564 allocated. Put the mapping symbol that far back. */
2567 mapping_state_2 (enum mstate state
, int max_chars
)
2569 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2571 if (!SEG_NORMAL (now_seg
))
2574 if (mapstate
== state
)
2575 /* The mapping symbol has already been emitted.
2576 There is nothing else to do. */
2579 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2580 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2583 #define mapping_state(x) ((void)0)
2584 #define mapping_state_2(x, y) ((void)0)
2587 /* Find the real, Thumb encoded start of a Thumb function. */
2591 find_real_start (symbolS
* symbolP
)
2594 const char * name
= S_GET_NAME (symbolP
);
2595 symbolS
* new_target
;
2597 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2598 #define STUB_NAME ".real_start_of"
2603 /* The compiler may generate BL instructions to local labels because
2604 it needs to perform a branch to a far away location. These labels
2605 do not have a corresponding ".real_start_of" label. We check
2606 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2607 the ".real_start_of" convention for nonlocal branches. */
2608 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2611 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2612 new_target
= symbol_find (real_start
);
2614 if (new_target
== NULL
)
2616 as_warn (_("Failed to find real start of function: %s\n"), name
);
2617 new_target
= symbolP
;
2625 opcode_select (int width
)
2632 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2633 as_bad (_("selected processor does not support THUMB opcodes"));
2636 /* No need to force the alignment, since we will have been
2637 coming from ARM mode, which is word-aligned. */
2638 record_alignment (now_seg
, 1);
2645 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2646 as_bad (_("selected processor does not support ARM opcodes"));
2651 frag_align (2, 0, 0);
2653 record_alignment (now_seg
, 1);
2658 as_bad (_("invalid instruction size selected (%d)"), width
);
2663 s_arm (int ignore ATTRIBUTE_UNUSED
)
2666 demand_empty_rest_of_line ();
2670 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2673 demand_empty_rest_of_line ();
2677 s_code (int unused ATTRIBUTE_UNUSED
)
2681 temp
= get_absolute_expression ();
2686 opcode_select (temp
);
2690 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2695 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2697 /* If we are not already in thumb mode go into it, EVEN if
2698 the target processor does not support thumb instructions.
2699 This is used by gcc/config/arm/lib1funcs.asm for example
2700 to compile interworking support functions even if the
2701 target processor should not support interworking. */
2705 record_alignment (now_seg
, 1);
2708 demand_empty_rest_of_line ();
2712 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2716 /* The following label is the name/address of the start of a Thumb function.
2717 We need to know this for the interworking support. */
2718 label_is_thumb_function_name
= TRUE
;
2721 /* Perform a .set directive, but also mark the alias as
2722 being a thumb function. */
2725 s_thumb_set (int equiv
)
2727 /* XXX the following is a duplicate of the code for s_set() in read.c
2728 We cannot just call that code as we need to get at the symbol that
2735 /* Especial apologies for the random logic:
2736 This just grew, and could be parsed much more simply!
2738 name
= input_line_pointer
;
2739 delim
= get_symbol_end ();
2740 end_name
= input_line_pointer
;
2743 if (*input_line_pointer
!= ',')
2746 as_bad (_("expected comma after name \"%s\""), name
);
2748 ignore_rest_of_line ();
2752 input_line_pointer
++;
2755 if (name
[0] == '.' && name
[1] == '\0')
2757 /* XXX - this should not happen to .thumb_set. */
2761 if ((symbolP
= symbol_find (name
)) == NULL
2762 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2765 /* When doing symbol listings, play games with dummy fragments living
2766 outside the normal fragment chain to record the file and line info
2768 if (listing
& LISTING_SYMBOLS
)
2770 extern struct list_info_struct
* listing_tail
;
2771 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2773 memset (dummy_frag
, 0, sizeof (fragS
));
2774 dummy_frag
->fr_type
= rs_fill
;
2775 dummy_frag
->line
= listing_tail
;
2776 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2777 dummy_frag
->fr_symbol
= symbolP
;
2781 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2784 /* "set" symbols are local unless otherwise specified. */
2785 SF_SET_LOCAL (symbolP
);
2786 #endif /* OBJ_COFF */
2787 } /* Make a new symbol. */
2789 symbol_table_insert (symbolP
);
2794 && S_IS_DEFINED (symbolP
)
2795 && S_GET_SEGMENT (symbolP
) != reg_section
)
2796 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2798 pseudo_set (symbolP
);
2800 demand_empty_rest_of_line ();
2802 /* XXX Now we come to the Thumb specific bit of code. */
2804 THUMB_SET_FUNC (symbolP
, 1);
2805 ARM_SET_THUMB (symbolP
, 1);
2806 #if defined OBJ_ELF || defined OBJ_COFF
2807 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2811 /* Directives: Mode selection. */
2813 /* .syntax [unified|divided] - choose the new unified syntax
2814 (same for Arm and Thumb encoding, modulo slight differences in what
2815 can be represented) or the old divergent syntax for each mode. */
2817 s_syntax (int unused ATTRIBUTE_UNUSED
)
2821 name
= input_line_pointer
;
2822 delim
= get_symbol_end ();
2824 if (!strcasecmp (name
, "unified"))
2825 unified_syntax
= TRUE
;
2826 else if (!strcasecmp (name
, "divided"))
2827 unified_syntax
= FALSE
;
2830 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2833 *input_line_pointer
= delim
;
2834 demand_empty_rest_of_line ();
2837 /* Directives: sectioning and alignment. */
2839 /* Same as s_align_ptwo but align 0 => align 2. */
2842 s_align (int unused ATTRIBUTE_UNUSED
)
2847 long max_alignment
= 15;
2849 temp
= get_absolute_expression ();
2850 if (temp
> max_alignment
)
2851 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2854 as_bad (_("alignment negative. 0 assumed."));
2858 if (*input_line_pointer
== ',')
2860 input_line_pointer
++;
2861 temp_fill
= get_absolute_expression ();
2873 /* Only make a frag if we HAVE to. */
2874 if (temp
&& !need_pass_2
)
2876 if (!fill_p
&& subseg_text_p (now_seg
))
2877 frag_align_code (temp
, 0);
2879 frag_align (temp
, (int) temp_fill
, 0);
2881 demand_empty_rest_of_line ();
2883 record_alignment (now_seg
, temp
);
2887 s_bss (int ignore ATTRIBUTE_UNUSED
)
2889 /* We don't support putting frags in the BSS segment, we fake it by
2890 marking in_bss, then looking at s_skip for clues. */
2891 subseg_set (bss_section
, 0);
2892 demand_empty_rest_of_line ();
2894 #ifdef md_elf_section_change_hook
2895 md_elf_section_change_hook ();
2900 s_even (int ignore ATTRIBUTE_UNUSED
)
2902 /* Never make frag if expect extra pass. */
2904 frag_align (1, 0, 0);
2906 record_alignment (now_seg
, 1);
2908 demand_empty_rest_of_line ();
2911 /* Directives: Literal pools. */
2913 static literal_pool
*
2914 find_literal_pool (void)
2916 literal_pool
* pool
;
2918 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2920 if (pool
->section
== now_seg
2921 && pool
->sub_section
== now_subseg
)
2928 static literal_pool
*
2929 find_or_make_literal_pool (void)
2931 /* Next literal pool ID number. */
2932 static unsigned int latest_pool_num
= 1;
2933 literal_pool
* pool
;
2935 pool
= find_literal_pool ();
2939 /* Create a new pool. */
2940 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
2944 pool
->next_free_entry
= 0;
2945 pool
->section
= now_seg
;
2946 pool
->sub_section
= now_subseg
;
2947 pool
->next
= list_of_pools
;
2948 pool
->symbol
= NULL
;
2950 /* Add it to the list. */
2951 list_of_pools
= pool
;
2954 /* New pools, and emptied pools, will have a NULL symbol. */
2955 if (pool
->symbol
== NULL
)
2957 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2958 (valueT
) 0, &zero_address_frag
);
2959 pool
->id
= latest_pool_num
++;
2966 /* Add the literal in the global 'inst'
2967 structure to the relevant literal pool. */
2970 add_to_lit_pool (void)
2972 literal_pool
* pool
;
2975 pool
= find_or_make_literal_pool ();
2977 /* Check if this literal value is already in the pool. */
2978 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2980 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2981 && (inst
.reloc
.exp
.X_op
== O_constant
)
2982 && (pool
->literals
[entry
].X_add_number
2983 == inst
.reloc
.exp
.X_add_number
)
2984 && (pool
->literals
[entry
].X_unsigned
2985 == inst
.reloc
.exp
.X_unsigned
))
2988 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2989 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2990 && (pool
->literals
[entry
].X_add_number
2991 == inst
.reloc
.exp
.X_add_number
)
2992 && (pool
->literals
[entry
].X_add_symbol
2993 == inst
.reloc
.exp
.X_add_symbol
)
2994 && (pool
->literals
[entry
].X_op_symbol
2995 == inst
.reloc
.exp
.X_op_symbol
))
2999 /* Do we need to create a new entry? */
3000 if (entry
== pool
->next_free_entry
)
3002 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3004 inst
.error
= _("literal pool overflow");
3008 pool
->literals
[entry
] = inst
.reloc
.exp
;
3009 pool
->next_free_entry
+= 1;
3012 inst
.reloc
.exp
.X_op
= O_symbol
;
3013 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3014 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3019 /* Can't use symbol_new here, so have to create a symbol and then at
3020 a later date assign it a value. Thats what these functions do. */
3023 symbol_locate (symbolS
* symbolP
,
3024 const char * name
, /* It is copied, the caller can modify. */
3025 segT segment
, /* Segment identifier (SEG_<something>). */
3026 valueT valu
, /* Symbol value. */
3027 fragS
* frag
) /* Associated fragment. */
3029 unsigned int name_length
;
3030 char * preserved_copy_of_name
;
3032 name_length
= strlen (name
) + 1; /* +1 for \0. */
3033 obstack_grow (¬es
, name
, name_length
);
3034 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3036 #ifdef tc_canonicalize_symbol_name
3037 preserved_copy_of_name
=
3038 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3041 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3043 S_SET_SEGMENT (symbolP
, segment
);
3044 S_SET_VALUE (symbolP
, valu
);
3045 symbol_clear_list_pointers (symbolP
);
3047 symbol_set_frag (symbolP
, frag
);
3049 /* Link to end of symbol chain. */
3051 extern int symbol_table_frozen
;
3053 if (symbol_table_frozen
)
3057 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3059 obj_symbol_new_hook (symbolP
);
3061 #ifdef tc_symbol_new_hook
3062 tc_symbol_new_hook (symbolP
);
3066 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3067 #endif /* DEBUG_SYMS */
3072 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3075 literal_pool
* pool
;
3078 pool
= find_literal_pool ();
3080 || pool
->symbol
== NULL
3081 || pool
->next_free_entry
== 0)
3084 mapping_state (MAP_DATA
);
3086 /* Align pool as you have word accesses.
3087 Only make a frag if we have to. */
3089 frag_align (2, 0, 0);
3091 record_alignment (now_seg
, 2);
3093 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3095 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3096 (valueT
) frag_now_fix (), frag_now
);
3097 symbol_table_insert (pool
->symbol
);
3099 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3101 #if defined OBJ_COFF || defined OBJ_ELF
3102 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3105 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3106 /* First output the expression in the instruction to the pool. */
3107 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3109 /* Mark the pool as empty. */
3110 pool
->next_free_entry
= 0;
3111 pool
->symbol
= NULL
;
3115 /* Forward declarations for functions below, in the MD interface
3117 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3118 static valueT
create_unwind_entry (int);
3119 static void start_unwind_section (const segT
, int);
3120 static void add_unwind_opcode (valueT
, int);
3121 static void flush_pending_unwind (void);
3123 /* Directives: Data. */
3126 s_arm_elf_cons (int nbytes
)
3130 #ifdef md_flush_pending_output
3131 md_flush_pending_output ();
3134 if (is_it_end_of_statement ())
3136 demand_empty_rest_of_line ();
3140 #ifdef md_cons_align
3141 md_cons_align (nbytes
);
3144 mapping_state (MAP_DATA
);
3148 char *base
= input_line_pointer
;
3152 if (exp
.X_op
!= O_symbol
)
3153 emit_expr (&exp
, (unsigned int) nbytes
);
3156 char *before_reloc
= input_line_pointer
;
3157 reloc
= parse_reloc (&input_line_pointer
);
3160 as_bad (_("unrecognized relocation suffix"));
3161 ignore_rest_of_line ();
3164 else if (reloc
== BFD_RELOC_UNUSED
)
3165 emit_expr (&exp
, (unsigned int) nbytes
);
3168 reloc_howto_type
*howto
= (reloc_howto_type
*)
3169 bfd_reloc_type_lookup (stdoutput
,
3170 (bfd_reloc_code_real_type
) reloc
);
3171 int size
= bfd_get_reloc_size (howto
);
3173 if (reloc
== BFD_RELOC_ARM_PLT32
)
3175 as_bad (_("(plt) is only valid on branch targets"));
3176 reloc
= BFD_RELOC_UNUSED
;
3181 as_bad (_("%s relocations do not fit in %d bytes"),
3182 howto
->name
, nbytes
);
3185 /* We've parsed an expression stopping at O_symbol.
3186 But there may be more expression left now that we
3187 have parsed the relocation marker. Parse it again.
3188 XXX Surely there is a cleaner way to do this. */
3189 char *p
= input_line_pointer
;
3191 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3192 memcpy (save_buf
, base
, input_line_pointer
- base
);
3193 memmove (base
+ (input_line_pointer
- before_reloc
),
3194 base
, before_reloc
- base
);
3196 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3198 memcpy (base
, save_buf
, p
- base
);
3200 offset
= nbytes
- size
;
3201 p
= frag_more ((int) nbytes
);
3202 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3203 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3208 while (*input_line_pointer
++ == ',');
3210 /* Put terminator back into stream. */
3211 input_line_pointer
--;
3212 demand_empty_rest_of_line ();
3215 /* Emit an expression containing a 32-bit thumb instruction.
3216 Implementation based on put_thumb32_insn. */
3219 emit_thumb32_expr (expressionS
* exp
)
3221 expressionS exp_high
= *exp
;
3223 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3224 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3225 exp
->X_add_number
&= 0xffff;
3226 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3229 /* Guess the instruction size based on the opcode. */
3232 thumb_insn_size (int opcode
)
3234 if ((unsigned int) opcode
< 0xe800u
)
3236 else if ((unsigned int) opcode
>= 0xe8000000u
)
3243 emit_insn (expressionS
*exp
, int nbytes
)
3247 if (exp
->X_op
== O_constant
)
3252 size
= thumb_insn_size (exp
->X_add_number
);
3256 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3258 as_bad (_(".inst.n operand too big. "\
3259 "Use .inst.w instead"));
3264 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3265 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3267 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3269 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3270 emit_thumb32_expr (exp
);
3272 emit_expr (exp
, (unsigned int) size
);
3274 it_fsm_post_encode ();
3278 as_bad (_("cannot determine Thumb instruction size. " \
3279 "Use .inst.n/.inst.w instead"));
3282 as_bad (_("constant expression required"));
3287 /* Like s_arm_elf_cons but do not use md_cons_align and
3288 set the mapping state to MAP_ARM/MAP_THUMB. */
3291 s_arm_elf_inst (int nbytes
)
3293 if (is_it_end_of_statement ())
3295 demand_empty_rest_of_line ();
3299 /* Calling mapping_state () here will not change ARM/THUMB,
3300 but will ensure not to be in DATA state. */
3303 mapping_state (MAP_THUMB
);
3308 as_bad (_("width suffixes are invalid in ARM mode"));
3309 ignore_rest_of_line ();
3315 mapping_state (MAP_ARM
);
3324 if (! emit_insn (& exp
, nbytes
))
3326 ignore_rest_of_line ();
3330 while (*input_line_pointer
++ == ',');
3332 /* Put terminator back into stream. */
3333 input_line_pointer
--;
3334 demand_empty_rest_of_line ();
3337 /* Parse a .rel31 directive. */
3340 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3347 if (*input_line_pointer
== '1')
3348 highbit
= 0x80000000;
3349 else if (*input_line_pointer
!= '0')
3350 as_bad (_("expected 0 or 1"));
3352 input_line_pointer
++;
3353 if (*input_line_pointer
!= ',')
3354 as_bad (_("missing comma"));
3355 input_line_pointer
++;
3357 #ifdef md_flush_pending_output
3358 md_flush_pending_output ();
3361 #ifdef md_cons_align
3365 mapping_state (MAP_DATA
);
3370 md_number_to_chars (p
, highbit
, 4);
3371 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3372 BFD_RELOC_ARM_PREL31
);
3374 demand_empty_rest_of_line ();
3377 /* Directives: AEABI stack-unwind tables. */
3379 /* Parse an unwind_fnstart directive. Simply records the current location. */
3382 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3384 demand_empty_rest_of_line ();
3385 if (unwind
.proc_start
)
3387 as_bad (_("duplicate .fnstart directive"));
3391 /* Mark the start of the function. */
3392 unwind
.proc_start
= expr_build_dot ();
3394 /* Reset the rest of the unwind info. */
3395 unwind
.opcode_count
= 0;
3396 unwind
.table_entry
= NULL
;
3397 unwind
.personality_routine
= NULL
;
3398 unwind
.personality_index
= -1;
3399 unwind
.frame_size
= 0;
3400 unwind
.fp_offset
= 0;
3401 unwind
.fp_reg
= REG_SP
;
3403 unwind
.sp_restored
= 0;
3407 /* Parse a handlerdata directive. Creates the exception handling table entry
3408 for the function. */
3411 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3413 demand_empty_rest_of_line ();
3414 if (!unwind
.proc_start
)
3415 as_bad (MISSING_FNSTART
);
3417 if (unwind
.table_entry
)
3418 as_bad (_("duplicate .handlerdata directive"));
3420 create_unwind_entry (1);
3423 /* Parse an unwind_fnend directive. Generates the index table entry. */
3426 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3431 unsigned int marked_pr_dependency
;
3433 demand_empty_rest_of_line ();
3435 if (!unwind
.proc_start
)
3437 as_bad (_(".fnend directive without .fnstart"));
3441 /* Add eh table entry. */
3442 if (unwind
.table_entry
== NULL
)
3443 val
= create_unwind_entry (0);
3447 /* Add index table entry. This is two words. */
3448 start_unwind_section (unwind
.saved_seg
, 1);
3449 frag_align (2, 0, 0);
3450 record_alignment (now_seg
, 2);
3452 ptr
= frag_more (8);
3453 where
= frag_now_fix () - 8;
3455 /* Self relative offset of the function start. */
3456 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3457 BFD_RELOC_ARM_PREL31
);
3459 /* Indicate dependency on EHABI-defined personality routines to the
3460 linker, if it hasn't been done already. */
3461 marked_pr_dependency
3462 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3463 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3464 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3466 static const char *const name
[] =
3468 "__aeabi_unwind_cpp_pr0",
3469 "__aeabi_unwind_cpp_pr1",
3470 "__aeabi_unwind_cpp_pr2"
3472 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3473 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3474 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3475 |= 1 << unwind
.personality_index
;
3479 /* Inline exception table entry. */
3480 md_number_to_chars (ptr
+ 4, val
, 4);
3482 /* Self relative offset of the table entry. */
3483 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3484 BFD_RELOC_ARM_PREL31
);
3486 /* Restore the original section. */
3487 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3489 unwind
.proc_start
= NULL
;
3493 /* Parse an unwind_cantunwind directive. */
3496 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3498 demand_empty_rest_of_line ();
3499 if (!unwind
.proc_start
)
3500 as_bad (MISSING_FNSTART
);
3502 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3503 as_bad (_("personality routine specified for cantunwind frame"));
3505 unwind
.personality_index
= -2;
3509 /* Parse a personalityindex directive. */
3512 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3516 if (!unwind
.proc_start
)
3517 as_bad (MISSING_FNSTART
);
3519 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3520 as_bad (_("duplicate .personalityindex directive"));
3524 if (exp
.X_op
!= O_constant
3525 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3527 as_bad (_("bad personality routine number"));
3528 ignore_rest_of_line ();
3532 unwind
.personality_index
= exp
.X_add_number
;
3534 demand_empty_rest_of_line ();
3538 /* Parse a personality directive. */
3541 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3545 if (!unwind
.proc_start
)
3546 as_bad (MISSING_FNSTART
);
3548 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3549 as_bad (_("duplicate .personality directive"));
3551 name
= input_line_pointer
;
3552 c
= get_symbol_end ();
3553 p
= input_line_pointer
;
3554 unwind
.personality_routine
= symbol_find_or_make (name
);
3556 demand_empty_rest_of_line ();
3560 /* Parse a directive saving core registers. */
3563 s_arm_unwind_save_core (void)
3569 range
= parse_reg_list (&input_line_pointer
);
3572 as_bad (_("expected register list"));
3573 ignore_rest_of_line ();
3577 demand_empty_rest_of_line ();
3579 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3580 into .unwind_save {..., sp...}. We aren't bothered about the value of
3581 ip because it is clobbered by calls. */
3582 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3583 && (range
& 0x3000) == 0x1000)
3585 unwind
.opcode_count
--;
3586 unwind
.sp_restored
= 0;
3587 range
= (range
| 0x2000) & ~0x1000;
3588 unwind
.pending_offset
= 0;
3594 /* See if we can use the short opcodes. These pop a block of up to 8
3595 registers starting with r4, plus maybe r14. */
3596 for (n
= 0; n
< 8; n
++)
3598 /* Break at the first non-saved register. */
3599 if ((range
& (1 << (n
+ 4))) == 0)
3602 /* See if there are any other bits set. */
3603 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3605 /* Use the long form. */
3606 op
= 0x8000 | ((range
>> 4) & 0xfff);
3607 add_unwind_opcode (op
, 2);
3611 /* Use the short form. */
3613 op
= 0xa8; /* Pop r14. */
3615 op
= 0xa0; /* Do not pop r14. */
3617 add_unwind_opcode (op
, 1);
3624 op
= 0xb100 | (range
& 0xf);
3625 add_unwind_opcode (op
, 2);
3628 /* Record the number of bytes pushed. */
3629 for (n
= 0; n
< 16; n
++)
3631 if (range
& (1 << n
))
3632 unwind
.frame_size
+= 4;
3637 /* Parse a directive saving FPA registers. */
3640 s_arm_unwind_save_fpa (int reg
)
3646 /* Get Number of registers to transfer. */
3647 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3650 exp
.X_op
= O_illegal
;
3652 if (exp
.X_op
!= O_constant
)
3654 as_bad (_("expected , <constant>"));
3655 ignore_rest_of_line ();
3659 num_regs
= exp
.X_add_number
;
3661 if (num_regs
< 1 || num_regs
> 4)
3663 as_bad (_("number of registers must be in the range [1:4]"));
3664 ignore_rest_of_line ();
3668 demand_empty_rest_of_line ();
3673 op
= 0xb4 | (num_regs
- 1);
3674 add_unwind_opcode (op
, 1);
3679 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3680 add_unwind_opcode (op
, 2);
3682 unwind
.frame_size
+= num_regs
* 12;
3686 /* Parse a directive saving VFP registers for ARMv6 and above. */
3689 s_arm_unwind_save_vfp_armv6 (void)
3694 int num_vfpv3_regs
= 0;
3695 int num_regs_below_16
;
3697 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3700 as_bad (_("expected register list"));
3701 ignore_rest_of_line ();
3705 demand_empty_rest_of_line ();
3707 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3708 than FSTMX/FLDMX-style ones). */
3710 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3712 num_vfpv3_regs
= count
;
3713 else if (start
+ count
> 16)
3714 num_vfpv3_regs
= start
+ count
- 16;
3716 if (num_vfpv3_regs
> 0)
3718 int start_offset
= start
> 16 ? start
- 16 : 0;
3719 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3720 add_unwind_opcode (op
, 2);
3723 /* Generate opcode for registers numbered in the range 0 .. 15. */
3724 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3725 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3726 if (num_regs_below_16
> 0)
3728 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3729 add_unwind_opcode (op
, 2);
3732 unwind
.frame_size
+= count
* 8;
3736 /* Parse a directive saving VFP registers for pre-ARMv6. */
3739 s_arm_unwind_save_vfp (void)
3745 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3748 as_bad (_("expected register list"));
3749 ignore_rest_of_line ();
3753 demand_empty_rest_of_line ();
3758 op
= 0xb8 | (count
- 1);
3759 add_unwind_opcode (op
, 1);
3764 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3765 add_unwind_opcode (op
, 2);
3767 unwind
.frame_size
+= count
* 8 + 4;
3771 /* Parse a directive saving iWMMXt data registers. */
3774 s_arm_unwind_save_mmxwr (void)
3782 if (*input_line_pointer
== '{')
3783 input_line_pointer
++;
3787 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3791 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3796 as_tsktsk (_("register list not in ascending order"));
3799 if (*input_line_pointer
== '-')
3801 input_line_pointer
++;
3802 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3805 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3808 else if (reg
>= hi_reg
)
3810 as_bad (_("bad register range"));
3813 for (; reg
< hi_reg
; reg
++)
3817 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3819 if (*input_line_pointer
== '}')
3820 input_line_pointer
++;
3822 demand_empty_rest_of_line ();
3824 /* Generate any deferred opcodes because we're going to be looking at
3826 flush_pending_unwind ();
3828 for (i
= 0; i
< 16; i
++)
3830 if (mask
& (1 << i
))
3831 unwind
.frame_size
+= 8;
3834 /* Attempt to combine with a previous opcode. We do this because gcc
3835 likes to output separate unwind directives for a single block of
3837 if (unwind
.opcode_count
> 0)
3839 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3840 if ((i
& 0xf8) == 0xc0)
3843 /* Only merge if the blocks are contiguous. */
3846 if ((mask
& 0xfe00) == (1 << 9))
3848 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3849 unwind
.opcode_count
--;
3852 else if (i
== 6 && unwind
.opcode_count
>= 2)
3854 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3858 op
= 0xffff << (reg
- 1);
3860 && ((mask
& op
) == (1u << (reg
- 1))))
3862 op
= (1 << (reg
+ i
+ 1)) - 1;
3863 op
&= ~((1 << reg
) - 1);
3865 unwind
.opcode_count
-= 2;
3872 /* We want to generate opcodes in the order the registers have been
3873 saved, ie. descending order. */
3874 for (reg
= 15; reg
>= -1; reg
--)
3876 /* Save registers in blocks. */
3878 || !(mask
& (1 << reg
)))
3880 /* We found an unsaved reg. Generate opcodes to save the
3887 op
= 0xc0 | (hi_reg
- 10);
3888 add_unwind_opcode (op
, 1);
3893 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3894 add_unwind_opcode (op
, 2);
3903 ignore_rest_of_line ();
3907 s_arm_unwind_save_mmxwcg (void)
3914 if (*input_line_pointer
== '{')
3915 input_line_pointer
++;
3919 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3923 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3929 as_tsktsk (_("register list not in ascending order"));
3932 if (*input_line_pointer
== '-')
3934 input_line_pointer
++;
3935 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3938 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3941 else if (reg
>= hi_reg
)
3943 as_bad (_("bad register range"));
3946 for (; reg
< hi_reg
; reg
++)
3950 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3952 if (*input_line_pointer
== '}')
3953 input_line_pointer
++;
3955 demand_empty_rest_of_line ();
3957 /* Generate any deferred opcodes because we're going to be looking at
3959 flush_pending_unwind ();
3961 for (reg
= 0; reg
< 16; reg
++)
3963 if (mask
& (1 << reg
))
3964 unwind
.frame_size
+= 4;
3967 add_unwind_opcode (op
, 2);
3970 ignore_rest_of_line ();
3974 /* Parse an unwind_save directive.
3975 If the argument is non-zero, this is a .vsave directive. */
3978 s_arm_unwind_save (int arch_v6
)
3981 struct reg_entry
*reg
;
3982 bfd_boolean had_brace
= FALSE
;
3984 if (!unwind
.proc_start
)
3985 as_bad (MISSING_FNSTART
);
3987 /* Figure out what sort of save we have. */
3988 peek
= input_line_pointer
;
3996 reg
= arm_reg_parse_multi (&peek
);
4000 as_bad (_("register expected"));
4001 ignore_rest_of_line ();
4010 as_bad (_("FPA .unwind_save does not take a register list"));
4011 ignore_rest_of_line ();
4014 input_line_pointer
= peek
;
4015 s_arm_unwind_save_fpa (reg
->number
);
4018 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4021 s_arm_unwind_save_vfp_armv6 ();
4023 s_arm_unwind_save_vfp ();
4025 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4026 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4029 as_bad (_(".unwind_save does not support this kind of register"));
4030 ignore_rest_of_line ();
4035 /* Parse an unwind_movsp directive. */
4038 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4044 if (!unwind
.proc_start
)
4045 as_bad (MISSING_FNSTART
);
4047 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4050 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4051 ignore_rest_of_line ();
4055 /* Optional constant. */
4056 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4058 if (immediate_for_directive (&offset
) == FAIL
)
4064 demand_empty_rest_of_line ();
4066 if (reg
== REG_SP
|| reg
== REG_PC
)
4068 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4072 if (unwind
.fp_reg
!= REG_SP
)
4073 as_bad (_("unexpected .unwind_movsp directive"));
4075 /* Generate opcode to restore the value. */
4077 add_unwind_opcode (op
, 1);
4079 /* Record the information for later. */
4080 unwind
.fp_reg
= reg
;
4081 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4082 unwind
.sp_restored
= 1;
4085 /* Parse an unwind_pad directive. */
4088 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4092 if (!unwind
.proc_start
)
4093 as_bad (MISSING_FNSTART
);
4095 if (immediate_for_directive (&offset
) == FAIL
)
4100 as_bad (_("stack increment must be multiple of 4"));
4101 ignore_rest_of_line ();
4105 /* Don't generate any opcodes, just record the details for later. */
4106 unwind
.frame_size
+= offset
;
4107 unwind
.pending_offset
+= offset
;
4109 demand_empty_rest_of_line ();
4112 /* Parse an unwind_setfp directive. */
4115 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4121 if (!unwind
.proc_start
)
4122 as_bad (MISSING_FNSTART
);
4124 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4125 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4128 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4130 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4132 as_bad (_("expected <reg>, <reg>"));
4133 ignore_rest_of_line ();
4137 /* Optional constant. */
4138 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4140 if (immediate_for_directive (&offset
) == FAIL
)
4146 demand_empty_rest_of_line ();
4148 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4150 as_bad (_("register must be either sp or set by a previous"
4151 "unwind_movsp directive"));
4155 /* Don't generate any opcodes, just record the information for later. */
4156 unwind
.fp_reg
= fp_reg
;
4158 if (sp_reg
== REG_SP
)
4159 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4161 unwind
.fp_offset
-= offset
;
4164 /* Parse an unwind_raw directive. */
4167 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4170 /* This is an arbitrary limit. */
4171 unsigned char op
[16];
4174 if (!unwind
.proc_start
)
4175 as_bad (MISSING_FNSTART
);
4178 if (exp
.X_op
== O_constant
4179 && skip_past_comma (&input_line_pointer
) != FAIL
)
4181 unwind
.frame_size
+= exp
.X_add_number
;
4185 exp
.X_op
= O_illegal
;
4187 if (exp
.X_op
!= O_constant
)
4189 as_bad (_("expected <offset>, <opcode>"));
4190 ignore_rest_of_line ();
4196 /* Parse the opcode. */
4201 as_bad (_("unwind opcode too long"));
4202 ignore_rest_of_line ();
4204 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4206 as_bad (_("invalid unwind opcode"));
4207 ignore_rest_of_line ();
4210 op
[count
++] = exp
.X_add_number
;
4212 /* Parse the next byte. */
4213 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4219 /* Add the opcode bytes in reverse order. */
4221 add_unwind_opcode (op
[count
], 1);
4223 demand_empty_rest_of_line ();
4227 /* Parse a .eabi_attribute directive. */
4230 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4232 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4234 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4235 attributes_set_explicitly
[tag
] = 1;
4237 #endif /* OBJ_ELF */
4239 static void s_arm_arch (int);
4240 static void s_arm_object_arch (int);
4241 static void s_arm_cpu (int);
4242 static void s_arm_fpu (int);
4247 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4254 if (exp
.X_op
== O_symbol
)
4255 exp
.X_op
= O_secrel
;
4257 emit_expr (&exp
, 4);
4259 while (*input_line_pointer
++ == ',');
4261 input_line_pointer
--;
4262 demand_empty_rest_of_line ();
4266 /* This table describes all the machine specific pseudo-ops the assembler
4267 has to support. The fields are:
4268 pseudo-op name without dot
4269 function to call to execute this pseudo-op
4270 Integer arg to pass to the function. */
4272 const pseudo_typeS md_pseudo_table
[] =
4274 /* Never called because '.req' does not start a line. */
4275 { "req", s_req
, 0 },
4276 /* Following two are likewise never called. */
4279 { "unreq", s_unreq
, 0 },
4280 { "bss", s_bss
, 0 },
4281 { "align", s_align
, 0 },
4282 { "arm", s_arm
, 0 },
4283 { "thumb", s_thumb
, 0 },
4284 { "code", s_code
, 0 },
4285 { "force_thumb", s_force_thumb
, 0 },
4286 { "thumb_func", s_thumb_func
, 0 },
4287 { "thumb_set", s_thumb_set
, 0 },
4288 { "even", s_even
, 0 },
4289 { "ltorg", s_ltorg
, 0 },
4290 { "pool", s_ltorg
, 0 },
4291 { "syntax", s_syntax
, 0 },
4292 { "cpu", s_arm_cpu
, 0 },
4293 { "arch", s_arm_arch
, 0 },
4294 { "object_arch", s_arm_object_arch
, 0 },
4295 { "fpu", s_arm_fpu
, 0 },
4297 { "word", s_arm_elf_cons
, 4 },
4298 { "long", s_arm_elf_cons
, 4 },
4299 { "inst.n", s_arm_elf_inst
, 2 },
4300 { "inst.w", s_arm_elf_inst
, 4 },
4301 { "inst", s_arm_elf_inst
, 0 },
4302 { "rel31", s_arm_rel31
, 0 },
4303 { "fnstart", s_arm_unwind_fnstart
, 0 },
4304 { "fnend", s_arm_unwind_fnend
, 0 },
4305 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4306 { "personality", s_arm_unwind_personality
, 0 },
4307 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4308 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4309 { "save", s_arm_unwind_save
, 0 },
4310 { "vsave", s_arm_unwind_save
, 1 },
4311 { "movsp", s_arm_unwind_movsp
, 0 },
4312 { "pad", s_arm_unwind_pad
, 0 },
4313 { "setfp", s_arm_unwind_setfp
, 0 },
4314 { "unwind_raw", s_arm_unwind_raw
, 0 },
4315 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4319 /* These are used for dwarf. */
4323 /* These are used for dwarf2. */
4324 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4325 { "loc", dwarf2_directive_loc
, 0 },
4326 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4328 { "extend", float_cons
, 'x' },
4329 { "ldouble", float_cons
, 'x' },
4330 { "packed", float_cons
, 'p' },
4332 {"secrel32", pe_directive_secrel
, 0},
4337 /* Parser functions used exclusively in instruction operands. */
4339 /* Generic immediate-value read function for use in insn parsing.
4340 STR points to the beginning of the immediate (the leading #);
4341 VAL receives the value; if the value is outside [MIN, MAX]
4342 issue an error. PREFIX_OPT is true if the immediate prefix is
4346 parse_immediate (char **str
, int *val
, int min
, int max
,
4347 bfd_boolean prefix_opt
)
4350 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4351 if (exp
.X_op
!= O_constant
)
4353 inst
.error
= _("constant expression required");
4357 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4359 inst
.error
= _("immediate value out of range");
4363 *val
= exp
.X_add_number
;
4367 /* Less-generic immediate-value read function with the possibility of loading a
4368 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4369 instructions. Puts the result directly in inst.operands[i]. */
4372 parse_big_immediate (char **str
, int i
)
4377 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4379 if (exp
.X_op
== O_constant
)
4381 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4382 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4383 O_constant. We have to be careful not to break compilation for
4384 32-bit X_add_number, though. */
4385 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4387 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4388 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4389 inst
.operands
[i
].regisimm
= 1;
4392 else if (exp
.X_op
== O_big
4393 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4394 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4396 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4397 /* Bignums have their least significant bits in
4398 generic_bignum[0]. Make sure we put 32 bits in imm and
4399 32 bits in reg, in a (hopefully) portable way. */
4400 gas_assert (parts
!= 0);
4401 inst
.operands
[i
].imm
= 0;
4402 for (j
= 0; j
< parts
; j
++, idx
++)
4403 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4404 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4405 inst
.operands
[i
].reg
= 0;
4406 for (j
= 0; j
< parts
; j
++, idx
++)
4407 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4408 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4409 inst
.operands
[i
].regisimm
= 1;
4419 /* Returns the pseudo-register number of an FPA immediate constant,
4420 or FAIL if there isn't a valid constant here. */
4423 parse_fpa_immediate (char ** str
)
4425 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4431 /* First try and match exact strings, this is to guarantee
4432 that some formats will work even for cross assembly. */
4434 for (i
= 0; fp_const
[i
]; i
++)
4436 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4440 *str
+= strlen (fp_const
[i
]);
4441 if (is_end_of_line
[(unsigned char) **str
])
4447 /* Just because we didn't get a match doesn't mean that the constant
4448 isn't valid, just that it is in a format that we don't
4449 automatically recognize. Try parsing it with the standard
4450 expression routines. */
4452 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4454 /* Look for a raw floating point number. */
4455 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4456 && is_end_of_line
[(unsigned char) *save_in
])
4458 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4460 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4462 if (words
[j
] != fp_values
[i
][j
])
4466 if (j
== MAX_LITTLENUMS
)
4474 /* Try and parse a more complex expression, this will probably fail
4475 unless the code uses a floating point prefix (eg "0f"). */
4476 save_in
= input_line_pointer
;
4477 input_line_pointer
= *str
;
4478 if (expression (&exp
) == absolute_section
4479 && exp
.X_op
== O_big
4480 && exp
.X_add_number
< 0)
4482 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4484 if (gen_to_words (words
, 5, (long) 15) == 0)
4486 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4488 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4490 if (words
[j
] != fp_values
[i
][j
])
4494 if (j
== MAX_LITTLENUMS
)
4496 *str
= input_line_pointer
;
4497 input_line_pointer
= save_in
;
4504 *str
= input_line_pointer
;
4505 input_line_pointer
= save_in
;
4506 inst
.error
= _("invalid FPA immediate expression");
4510 /* Returns 1 if a number has "quarter-precision" float format
4511 0baBbbbbbc defgh000 00000000 00000000. */
4514 is_quarter_float (unsigned imm
)
4516 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4517 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4520 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4521 0baBbbbbbc defgh000 00000000 00000000.
4522 The zero and minus-zero cases need special handling, since they can't be
4523 encoded in the "quarter-precision" float format, but can nonetheless be
4524 loaded as integer constants. */
4527 parse_qfloat_immediate (char **ccp
, int *immed
)
4531 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4532 int found_fpchar
= 0;
4534 skip_past_char (&str
, '#');
4536 /* We must not accidentally parse an integer as a floating-point number. Make
4537 sure that the value we parse is not an integer by checking for special
4538 characters '.' or 'e'.
4539 FIXME: This is a horrible hack, but doing better is tricky because type
4540 information isn't in a very usable state at parse time. */
4542 skip_whitespace (fpnum
);
4544 if (strncmp (fpnum
, "0x", 2) == 0)
4548 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4549 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4559 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4561 unsigned fpword
= 0;
4564 /* Our FP word must be 32 bits (single-precision FP). */
4565 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4567 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4571 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4584 /* Shift operands. */
4587 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4590 struct asm_shift_name
4593 enum shift_kind kind
;
4596 /* Third argument to parse_shift. */
4597 enum parse_shift_mode
4599 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4600 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4601 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4602 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4603 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4606 /* Parse a <shift> specifier on an ARM data processing instruction.
4607 This has three forms:
4609 (LSL|LSR|ASL|ASR|ROR) Rs
4610 (LSL|LSR|ASL|ASR|ROR) #imm
4613 Note that ASL is assimilated to LSL in the instruction encoding, and
4614 RRX to ROR #0 (which cannot be written as such). */
4617 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4619 const struct asm_shift_name
*shift_name
;
4620 enum shift_kind shift
;
4625 for (p
= *str
; ISALPHA (*p
); p
++)
4630 inst
.error
= _("shift expression expected");
4634 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4637 if (shift_name
== NULL
)
4639 inst
.error
= _("shift expression expected");
4643 shift
= shift_name
->kind
;
4647 case NO_SHIFT_RESTRICT
:
4648 case SHIFT_IMMEDIATE
: break;
4650 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4651 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4653 inst
.error
= _("'LSL' or 'ASR' required");
4658 case SHIFT_LSL_IMMEDIATE
:
4659 if (shift
!= SHIFT_LSL
)
4661 inst
.error
= _("'LSL' required");
4666 case SHIFT_ASR_IMMEDIATE
:
4667 if (shift
!= SHIFT_ASR
)
4669 inst
.error
= _("'ASR' required");
4677 if (shift
!= SHIFT_RRX
)
4679 /* Whitespace can appear here if the next thing is a bare digit. */
4680 skip_whitespace (p
);
4682 if (mode
== NO_SHIFT_RESTRICT
4683 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4685 inst
.operands
[i
].imm
= reg
;
4686 inst
.operands
[i
].immisreg
= 1;
4688 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4691 inst
.operands
[i
].shift_kind
= shift
;
4692 inst
.operands
[i
].shifted
= 1;
4697 /* Parse a <shifter_operand> for an ARM data processing instruction:
4700 #<immediate>, <rotate>
4704 where <shift> is defined by parse_shift above, and <rotate> is a
4705 multiple of 2 between 0 and 30. Validation of immediate operands
4706 is deferred to md_apply_fix. */
4709 parse_shifter_operand (char **str
, int i
)
4714 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4716 inst
.operands
[i
].reg
= value
;
4717 inst
.operands
[i
].isreg
= 1;
4719 /* parse_shift will override this if appropriate */
4720 inst
.reloc
.exp
.X_op
= O_constant
;
4721 inst
.reloc
.exp
.X_add_number
= 0;
4723 if (skip_past_comma (str
) == FAIL
)
4726 /* Shift operation on register. */
4727 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4730 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4733 if (skip_past_comma (str
) == SUCCESS
)
4735 /* #x, y -- ie explicit rotation by Y. */
4736 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
4739 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4741 inst
.error
= _("constant expression expected");
4745 value
= expr
.X_add_number
;
4746 if (value
< 0 || value
> 30 || value
% 2 != 0)
4748 inst
.error
= _("invalid rotation");
4751 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4753 inst
.error
= _("invalid constant");
4757 /* Convert to decoded value. md_apply_fix will put it back. */
4758 inst
.reloc
.exp
.X_add_number
4759 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4760 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4763 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4764 inst
.reloc
.pc_rel
= 0;
4768 /* Group relocation information. Each entry in the table contains the
4769 textual name of the relocation as may appear in assembler source
4770 and must end with a colon.
4771 Along with this textual name are the relocation codes to be used if
4772 the corresponding instruction is an ALU instruction (ADD or SUB only),
4773 an LDR, an LDRS, or an LDC. */
4775 struct group_reloc_table_entry
4786 /* Varieties of non-ALU group relocation. */
4793 static struct group_reloc_table_entry group_reloc_table
[] =
4794 { /* Program counter relative: */
4796 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4801 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4802 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4803 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4804 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4806 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4811 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4812 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4813 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4814 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4816 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4817 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4818 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4819 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4820 /* Section base relative */
4822 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4827 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4828 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4829 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4830 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4832 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4837 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4838 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4839 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4840 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4842 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4843 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4844 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4845 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4847 /* Given the address of a pointer pointing to the textual name of a group
4848 relocation as may appear in assembler source, attempt to find its details
4849 in group_reloc_table. The pointer will be updated to the character after
4850 the trailing colon. On failure, FAIL will be returned; SUCCESS
4851 otherwise. On success, *entry will be updated to point at the relevant
4852 group_reloc_table entry. */
4855 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4858 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4860 int length
= strlen (group_reloc_table
[i
].name
);
4862 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4863 && (*str
)[length
] == ':')
4865 *out
= &group_reloc_table
[i
];
4866 *str
+= (length
+ 1);
4874 /* Parse a <shifter_operand> for an ARM data processing instruction
4875 (as for parse_shifter_operand) where group relocations are allowed:
4878 #<immediate>, <rotate>
4879 #:<group_reloc>:<expression>
4883 where <group_reloc> is one of the strings defined in group_reloc_table.
4884 The hashes are optional.
4886 Everything else is as for parse_shifter_operand. */
4888 static parse_operand_result
4889 parse_shifter_operand_group_reloc (char **str
, int i
)
4891 /* Determine if we have the sequence of characters #: or just :
4892 coming next. If we do, then we check for a group relocation.
4893 If we don't, punt the whole lot to parse_shifter_operand. */
4895 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4896 || (*str
)[0] == ':')
4898 struct group_reloc_table_entry
*entry
;
4900 if ((*str
)[0] == '#')
4905 /* Try to parse a group relocation. Anything else is an error. */
4906 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4908 inst
.error
= _("unknown group relocation");
4909 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4912 /* We now have the group relocation table entry corresponding to
4913 the name in the assembler source. Next, we parse the expression. */
4914 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4915 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4917 /* Record the relocation type (always the ALU variant here). */
4918 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
4919 gas_assert (inst
.reloc
.type
!= 0);
4921 return PARSE_OPERAND_SUCCESS
;
4924 return parse_shifter_operand (str
, i
) == SUCCESS
4925 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4927 /* Never reached. */
4930 /* Parse all forms of an ARM address expression. Information is written
4931 to inst.operands[i] and/or inst.reloc.
4933 Preindexed addressing (.preind=1):
4935 [Rn, #offset] .reg=Rn .reloc.exp=offset
4936 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4937 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4938 .shift_kind=shift .reloc.exp=shift_imm
4940 These three may have a trailing ! which causes .writeback to be set also.
4942 Postindexed addressing (.postind=1, .writeback=1):
4944 [Rn], #offset .reg=Rn .reloc.exp=offset
4945 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4946 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4947 .shift_kind=shift .reloc.exp=shift_imm
4949 Unindexed addressing (.preind=0, .postind=0):
4951 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4955 [Rn]{!} shorthand for [Rn,#0]{!}
4956 =immediate .isreg=0 .reloc.exp=immediate
4957 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4959 It is the caller's responsibility to check for addressing modes not
4960 supported by the instruction, and to set inst.reloc.type. */
4962 static parse_operand_result
4963 parse_address_main (char **str
, int i
, int group_relocations
,
4964 group_reloc_type group_type
)
4969 if (skip_past_char (&p
, '[') == FAIL
)
4971 if (skip_past_char (&p
, '=') == FAIL
)
4973 /* bare address - translate to PC-relative offset */
4974 inst
.reloc
.pc_rel
= 1;
4975 inst
.operands
[i
].reg
= REG_PC
;
4976 inst
.operands
[i
].isreg
= 1;
4977 inst
.operands
[i
].preind
= 1;
4979 /* else a load-constant pseudo op, no special treatment needed here */
4981 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4982 return PARSE_OPERAND_FAIL
;
4985 return PARSE_OPERAND_SUCCESS
;
4988 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4990 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4991 return PARSE_OPERAND_FAIL
;
4993 inst
.operands
[i
].reg
= reg
;
4994 inst
.operands
[i
].isreg
= 1;
4996 if (skip_past_comma (&p
) == SUCCESS
)
4998 inst
.operands
[i
].preind
= 1;
5001 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5003 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5005 inst
.operands
[i
].imm
= reg
;
5006 inst
.operands
[i
].immisreg
= 1;
5008 if (skip_past_comma (&p
) == SUCCESS
)
5009 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5010 return PARSE_OPERAND_FAIL
;
5012 else if (skip_past_char (&p
, ':') == SUCCESS
)
5014 /* FIXME: '@' should be used here, but it's filtered out by generic
5015 code before we get to see it here. This may be subject to
5018 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5019 if (exp
.X_op
!= O_constant
)
5021 inst
.error
= _("alignment must be constant");
5022 return PARSE_OPERAND_FAIL
;
5024 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5025 inst
.operands
[i
].immisalign
= 1;
5026 /* Alignments are not pre-indexes. */
5027 inst
.operands
[i
].preind
= 0;
5031 if (inst
.operands
[i
].negative
)
5033 inst
.operands
[i
].negative
= 0;
5037 if (group_relocations
5038 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5040 struct group_reloc_table_entry
*entry
;
5042 /* Skip over the #: or : sequence. */
5048 /* Try to parse a group relocation. Anything else is an
5050 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5052 inst
.error
= _("unknown group relocation");
5053 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5056 /* We now have the group relocation table entry corresponding to
5057 the name in the assembler source. Next, we parse the
5059 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5060 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5062 /* Record the relocation type. */
5066 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5070 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5074 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5081 if (inst
.reloc
.type
== 0)
5083 inst
.error
= _("this group relocation is not allowed on this instruction");
5084 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5088 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5089 return PARSE_OPERAND_FAIL
;
5093 if (skip_past_char (&p
, ']') == FAIL
)
5095 inst
.error
= _("']' expected");
5096 return PARSE_OPERAND_FAIL
;
5099 if (skip_past_char (&p
, '!') == SUCCESS
)
5100 inst
.operands
[i
].writeback
= 1;
5102 else if (skip_past_comma (&p
) == SUCCESS
)
5104 if (skip_past_char (&p
, '{') == SUCCESS
)
5106 /* [Rn], {expr} - unindexed, with option */
5107 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5108 0, 255, TRUE
) == FAIL
)
5109 return PARSE_OPERAND_FAIL
;
5111 if (skip_past_char (&p
, '}') == FAIL
)
5113 inst
.error
= _("'}' expected at end of 'option' field");
5114 return PARSE_OPERAND_FAIL
;
5116 if (inst
.operands
[i
].preind
)
5118 inst
.error
= _("cannot combine index with option");
5119 return PARSE_OPERAND_FAIL
;
5122 return PARSE_OPERAND_SUCCESS
;
5126 inst
.operands
[i
].postind
= 1;
5127 inst
.operands
[i
].writeback
= 1;
5129 if (inst
.operands
[i
].preind
)
5131 inst
.error
= _("cannot combine pre- and post-indexing");
5132 return PARSE_OPERAND_FAIL
;
5136 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5138 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5140 /* We might be using the immediate for alignment already. If we
5141 are, OR the register number into the low-order bits. */
5142 if (inst
.operands
[i
].immisalign
)
5143 inst
.operands
[i
].imm
|= reg
;
5145 inst
.operands
[i
].imm
= reg
;
5146 inst
.operands
[i
].immisreg
= 1;
5148 if (skip_past_comma (&p
) == SUCCESS
)
5149 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5150 return PARSE_OPERAND_FAIL
;
5154 if (inst
.operands
[i
].negative
)
5156 inst
.operands
[i
].negative
= 0;
5159 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5160 return PARSE_OPERAND_FAIL
;
5165 /* If at this point neither .preind nor .postind is set, we have a
5166 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5167 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5169 inst
.operands
[i
].preind
= 1;
5170 inst
.reloc
.exp
.X_op
= O_constant
;
5171 inst
.reloc
.exp
.X_add_number
= 0;
5174 return PARSE_OPERAND_SUCCESS
;
5178 parse_address (char **str
, int i
)
5180 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5184 static parse_operand_result
5185 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5187 return parse_address_main (str
, i
, 1, type
);
5190 /* Parse an operand for a MOVW or MOVT instruction. */
5192 parse_half (char **str
)
5197 skip_past_char (&p
, '#');
5198 if (strncasecmp (p
, ":lower16:", 9) == 0)
5199 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5200 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5201 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5203 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5206 skip_whitespace (p
);
5209 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5212 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5214 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5216 inst
.error
= _("constant expression expected");
5219 if (inst
.reloc
.exp
.X_add_number
< 0
5220 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5222 inst
.error
= _("immediate value out of range");
5230 /* Miscellaneous. */
5232 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5233 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5235 parse_psr (char **str
)
5238 unsigned long psr_field
;
5239 const struct asm_psr
*psr
;
5242 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5243 feature for ease of use and backwards compatibility. */
5245 if (strncasecmp (p
, "SPSR", 4) == 0)
5246 psr_field
= SPSR_BIT
;
5247 else if (strncasecmp (p
, "CPSR", 4) == 0)
5254 while (ISALNUM (*p
) || *p
== '_');
5256 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5268 /* A suffix follows. */
5274 while (ISALNUM (*p
) || *p
== '_');
5276 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5281 psr_field
|= psr
->field
;
5286 goto error
; /* Garbage after "[CS]PSR". */
5288 psr_field
|= (PSR_c
| PSR_f
);
5294 inst
.error
= _("flag for {c}psr instruction expected");
5298 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5299 value suitable for splatting into the AIF field of the instruction. */
5302 parse_cps_flags (char **str
)
5311 case '\0': case ',':
5314 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5315 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5316 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5319 inst
.error
= _("unrecognized CPS flag");
5324 if (saw_a_flag
== 0)
5326 inst
.error
= _("missing CPS flags");
5334 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5335 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5338 parse_endian_specifier (char **str
)
5343 if (strncasecmp (s
, "BE", 2))
5345 else if (strncasecmp (s
, "LE", 2))
5349 inst
.error
= _("valid endian specifiers are be or le");
5353 if (ISALNUM (s
[2]) || s
[2] == '_')
5355 inst
.error
= _("valid endian specifiers are be or le");
5360 return little_endian
;
5363 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5364 value suitable for poking into the rotate field of an sxt or sxta
5365 instruction, or FAIL on error. */
5368 parse_ror (char **str
)
5373 if (strncasecmp (s
, "ROR", 3) == 0)
5377 inst
.error
= _("missing rotation field after comma");
5381 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5386 case 0: *str
= s
; return 0x0;
5387 case 8: *str
= s
; return 0x1;
5388 case 16: *str
= s
; return 0x2;
5389 case 24: *str
= s
; return 0x3;
5392 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5397 /* Parse a conditional code (from conds[] below). The value returned is in the
5398 range 0 .. 14, or FAIL. */
5400 parse_cond (char **str
)
5403 const struct asm_cond
*c
;
5405 /* Condition codes are always 2 characters, so matching up to
5406 3 characters is sufficient. */
5411 while (ISALPHA (*q
) && n
< 3)
5413 cond
[n
] = TOLOWER (*q
);
5418 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5421 inst
.error
= _("condition required");
5429 /* Parse an option for a barrier instruction. Returns the encoding for the
5432 parse_barrier (char **str
)
5435 const struct asm_barrier_opt
*o
;
5438 while (ISALPHA (*q
))
5441 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5450 /* Parse the operands of a table branch instruction. Similar to a memory
5453 parse_tb (char **str
)
5458 if (skip_past_char (&p
, '[') == FAIL
)
5460 inst
.error
= _("'[' expected");
5464 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5466 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5469 inst
.operands
[0].reg
= reg
;
5471 if (skip_past_comma (&p
) == FAIL
)
5473 inst
.error
= _("',' expected");
5477 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5479 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5482 inst
.operands
[0].imm
= reg
;
5484 if (skip_past_comma (&p
) == SUCCESS
)
5486 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5488 if (inst
.reloc
.exp
.X_add_number
!= 1)
5490 inst
.error
= _("invalid shift");
5493 inst
.operands
[0].shifted
= 1;
5496 if (skip_past_char (&p
, ']') == FAIL
)
5498 inst
.error
= _("']' expected");
5505 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5506 information on the types the operands can take and how they are encoded.
5507 Up to four operands may be read; this function handles setting the
5508 ".present" field for each read operand itself.
5509 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5510 else returns FAIL. */
5513 parse_neon_mov (char **str
, int *which_operand
)
5515 int i
= *which_operand
, val
;
5516 enum arm_reg_type rtype
;
5518 struct neon_type_el optype
;
5520 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5522 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5523 inst
.operands
[i
].reg
= val
;
5524 inst
.operands
[i
].isscalar
= 1;
5525 inst
.operands
[i
].vectype
= optype
;
5526 inst
.operands
[i
++].present
= 1;
5528 if (skip_past_comma (&ptr
) == FAIL
)
5531 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5534 inst
.operands
[i
].reg
= val
;
5535 inst
.operands
[i
].isreg
= 1;
5536 inst
.operands
[i
].present
= 1;
5538 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5541 /* Cases 0, 1, 2, 3, 5 (D only). */
5542 if (skip_past_comma (&ptr
) == FAIL
)
5545 inst
.operands
[i
].reg
= val
;
5546 inst
.operands
[i
].isreg
= 1;
5547 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5548 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5549 inst
.operands
[i
].isvec
= 1;
5550 inst
.operands
[i
].vectype
= optype
;
5551 inst
.operands
[i
++].present
= 1;
5553 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5555 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5556 Case 13: VMOV <Sd>, <Rm> */
5557 inst
.operands
[i
].reg
= val
;
5558 inst
.operands
[i
].isreg
= 1;
5559 inst
.operands
[i
].present
= 1;
5561 if (rtype
== REG_TYPE_NQ
)
5563 first_error (_("can't use Neon quad register here"));
5566 else if (rtype
!= REG_TYPE_VFS
)
5569 if (skip_past_comma (&ptr
) == FAIL
)
5571 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5573 inst
.operands
[i
].reg
= val
;
5574 inst
.operands
[i
].isreg
= 1;
5575 inst
.operands
[i
].present
= 1;
5578 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5581 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5582 Case 1: VMOV<c><q> <Dd>, <Dm>
5583 Case 8: VMOV.F32 <Sd>, <Sm>
5584 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5586 inst
.operands
[i
].reg
= val
;
5587 inst
.operands
[i
].isreg
= 1;
5588 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5589 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5590 inst
.operands
[i
].isvec
= 1;
5591 inst
.operands
[i
].vectype
= optype
;
5592 inst
.operands
[i
].present
= 1;
5594 if (skip_past_comma (&ptr
) == SUCCESS
)
5599 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5602 inst
.operands
[i
].reg
= val
;
5603 inst
.operands
[i
].isreg
= 1;
5604 inst
.operands
[i
++].present
= 1;
5606 if (skip_past_comma (&ptr
) == FAIL
)
5609 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5612 inst
.operands
[i
].reg
= val
;
5613 inst
.operands
[i
].isreg
= 1;
5614 inst
.operands
[i
++].present
= 1;
5617 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5618 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5619 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5620 Case 10: VMOV.F32 <Sd>, #<imm>
5621 Case 11: VMOV.F64 <Dd>, #<imm> */
5622 inst
.operands
[i
].immisfloat
= 1;
5623 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5624 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5625 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5629 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5633 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5636 inst
.operands
[i
].reg
= val
;
5637 inst
.operands
[i
].isreg
= 1;
5638 inst
.operands
[i
++].present
= 1;
5640 if (skip_past_comma (&ptr
) == FAIL
)
5643 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5645 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5646 inst
.operands
[i
].reg
= val
;
5647 inst
.operands
[i
].isscalar
= 1;
5648 inst
.operands
[i
].present
= 1;
5649 inst
.operands
[i
].vectype
= optype
;
5651 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5653 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5654 inst
.operands
[i
].reg
= val
;
5655 inst
.operands
[i
].isreg
= 1;
5656 inst
.operands
[i
++].present
= 1;
5658 if (skip_past_comma (&ptr
) == FAIL
)
5661 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5664 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5668 inst
.operands
[i
].reg
= val
;
5669 inst
.operands
[i
].isreg
= 1;
5670 inst
.operands
[i
].isvec
= 1;
5671 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5672 inst
.operands
[i
].vectype
= optype
;
5673 inst
.operands
[i
].present
= 1;
5675 if (rtype
== REG_TYPE_VFS
)
5679 if (skip_past_comma (&ptr
) == FAIL
)
5681 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5684 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5687 inst
.operands
[i
].reg
= val
;
5688 inst
.operands
[i
].isreg
= 1;
5689 inst
.operands
[i
].isvec
= 1;
5690 inst
.operands
[i
].issingle
= 1;
5691 inst
.operands
[i
].vectype
= optype
;
5692 inst
.operands
[i
].present
= 1;
5695 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5699 inst
.operands
[i
].reg
= val
;
5700 inst
.operands
[i
].isreg
= 1;
5701 inst
.operands
[i
].isvec
= 1;
5702 inst
.operands
[i
].issingle
= 1;
5703 inst
.operands
[i
].vectype
= optype
;
5704 inst
.operands
[i
++].present
= 1;
5709 first_error (_("parse error"));
5713 /* Successfully parsed the operands. Update args. */
5719 first_error (_("expected comma"));
5723 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5727 /* Matcher codes for parse_operands. */
5728 enum operand_parse_code
5730 OP_stop
, /* end of line */
5732 OP_RR
, /* ARM register */
5733 OP_RRnpc
, /* ARM register, not r15 */
5734 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5735 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5736 OP_RCP
, /* Coprocessor number */
5737 OP_RCN
, /* Coprocessor register */
5738 OP_RF
, /* FPA register */
5739 OP_RVS
, /* VFP single precision register */
5740 OP_RVD
, /* VFP double precision register (0..15) */
5741 OP_RND
, /* Neon double precision register (0..31) */
5742 OP_RNQ
, /* Neon quad precision register */
5743 OP_RVSD
, /* VFP single or double precision register */
5744 OP_RNDQ
, /* Neon double or quad precision register */
5745 OP_RNSDQ
, /* Neon single, double or quad precision register */
5746 OP_RNSC
, /* Neon scalar D[X] */
5747 OP_RVC
, /* VFP control register */
5748 OP_RMF
, /* Maverick F register */
5749 OP_RMD
, /* Maverick D register */
5750 OP_RMFX
, /* Maverick FX register */
5751 OP_RMDX
, /* Maverick DX register */
5752 OP_RMAX
, /* Maverick AX register */
5753 OP_RMDS
, /* Maverick DSPSC register */
5754 OP_RIWR
, /* iWMMXt wR register */
5755 OP_RIWC
, /* iWMMXt wC register */
5756 OP_RIWG
, /* iWMMXt wCG register */
5757 OP_RXA
, /* XScale accumulator register */
5759 OP_REGLST
, /* ARM register list */
5760 OP_VRSLST
, /* VFP single-precision register list */
5761 OP_VRDLST
, /* VFP double-precision register list */
5762 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5763 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5764 OP_NSTRLST
, /* Neon element/structure list */
5766 OP_NILO
, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5767 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5768 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5769 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5770 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5771 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5772 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5773 OP_VMOV
, /* Neon VMOV operands. */
5774 OP_RNDQ_IMVNb
,/* Neon D or Q reg, or immediate good for VMVN. */
5775 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5776 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5778 OP_I0
, /* immediate zero */
5779 OP_I7
, /* immediate value 0 .. 7 */
5780 OP_I15
, /* 0 .. 15 */
5781 OP_I16
, /* 1 .. 16 */
5782 OP_I16z
, /* 0 .. 16 */
5783 OP_I31
, /* 0 .. 31 */
5784 OP_I31w
, /* 0 .. 31, optional trailing ! */
5785 OP_I32
, /* 1 .. 32 */
5786 OP_I32z
, /* 0 .. 32 */
5787 OP_I63
, /* 0 .. 63 */
5788 OP_I63s
, /* -64 .. 63 */
5789 OP_I64
, /* 1 .. 64 */
5790 OP_I64z
, /* 0 .. 64 */
5791 OP_I255
, /* 0 .. 255 */
5793 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5794 OP_I7b
, /* 0 .. 7 */
5795 OP_I15b
, /* 0 .. 15 */
5796 OP_I31b
, /* 0 .. 31 */
5798 OP_SH
, /* shifter operand */
5799 OP_SHG
, /* shifter operand with possible group relocation */
5800 OP_ADDR
, /* Memory address expression (any mode) */
5801 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5802 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5803 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5804 OP_EXP
, /* arbitrary expression */
5805 OP_EXPi
, /* same, with optional immediate prefix */
5806 OP_EXPr
, /* same, with optional relocation suffix */
5807 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5809 OP_CPSF
, /* CPS flags */
5810 OP_ENDI
, /* Endianness specifier */
5811 OP_PSR
, /* CPSR/SPSR mask for msr */
5812 OP_COND
, /* conditional code */
5813 OP_TB
, /* Table branch. */
5815 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5816 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5818 OP_RRnpc_I0
, /* ARM register or literal 0 */
5819 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5820 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5821 OP_RF_IF
, /* FPA register or immediate */
5822 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5823 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5825 /* Optional operands. */
5826 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5827 OP_oI31b
, /* 0 .. 31 */
5828 OP_oI32b
, /* 1 .. 32 */
5829 OP_oIffffb
, /* 0 .. 65535 */
5830 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5832 OP_oRR
, /* ARM register */
5833 OP_oRRnpc
, /* ARM register, not the PC */
5834 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5835 OP_oRND
, /* Optional Neon double precision register */
5836 OP_oRNQ
, /* Optional Neon quad precision register */
5837 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5838 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5839 OP_oSHll
, /* LSL immediate */
5840 OP_oSHar
, /* ASR immediate */
5841 OP_oSHllar
, /* LSL or ASR immediate */
5842 OP_oROR
, /* ROR 0/8/16/24 */
5843 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5845 OP_FIRST_OPTIONAL
= OP_oI7b
5848 /* Generic instruction operand parser. This does no encoding and no
5849 semantic validation; it merely squirrels values away in the inst
5850 structure. Returns SUCCESS or FAIL depending on whether the
5851 specified grammar matched. */
5853 parse_operands (char *str
, const unsigned char *pattern
)
5855 unsigned const char *upat
= pattern
;
5856 char *backtrack_pos
= 0;
5857 const char *backtrack_error
= 0;
5858 int i
, val
, backtrack_index
= 0;
5859 enum arm_reg_type rtype
;
5860 parse_operand_result result
;
5862 #define po_char_or_fail(chr) \
5865 if (skip_past_char (&str, chr) == FAIL) \
5870 #define po_reg_or_fail(regtype) \
5873 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5874 & inst.operands[i].vectype); \
5877 first_error (_(reg_expected_msgs[regtype])); \
5880 inst.operands[i].reg = val; \
5881 inst.operands[i].isreg = 1; \
5882 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5883 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5884 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5885 || rtype == REG_TYPE_VFD \
5886 || rtype == REG_TYPE_NQ); \
5890 #define po_reg_or_goto(regtype, label) \
5893 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5894 & inst.operands[i].vectype); \
5898 inst.operands[i].reg = val; \
5899 inst.operands[i].isreg = 1; \
5900 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5901 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5902 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5903 || rtype == REG_TYPE_VFD \
5904 || rtype == REG_TYPE_NQ); \
5908 #define po_imm_or_fail(min, max, popt) \
5911 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5913 inst.operands[i].imm = val; \
5917 #define po_scalar_or_goto(elsz, label) \
5920 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
5923 inst.operands[i].reg = val; \
5924 inst.operands[i].isscalar = 1; \
5928 #define po_misc_or_fail(expr) \
5936 #define po_misc_or_fail_no_backtrack(expr) \
5940 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
5941 backtrack_pos = 0; \
5942 if (result != PARSE_OPERAND_SUCCESS) \
5947 skip_whitespace (str
);
5949 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5951 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5953 /* Remember where we are in case we need to backtrack. */
5954 gas_assert (!backtrack_pos
);
5955 backtrack_pos
= str
;
5956 backtrack_error
= inst
.error
;
5957 backtrack_index
= i
;
5960 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
5961 po_char_or_fail (',');
5969 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5970 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5971 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5972 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5973 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5974 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5976 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5978 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
5980 /* Also accept generic coprocessor regs for unknown registers. */
5982 po_reg_or_fail (REG_TYPE_CN
);
5984 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5985 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5986 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5987 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5988 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5989 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5990 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5991 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5992 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5993 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5995 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
5997 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
5998 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6000 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6002 /* Neon scalar. Using an element size of 8 means that some invalid
6003 scalars are accepted here, so deal with those in later code. */
6004 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6006 /* WARNING: We can expand to two operands here. This has the potential
6007 to totally confuse the backtracking mechanism! It will be OK at
6008 least as long as we don't try to use optional args as well,
6012 po_reg_or_goto (REG_TYPE_NDQ
, try_imm
);
6013 inst
.operands
[i
].present
= 1;
6015 skip_past_comma (&str
);
6016 po_reg_or_goto (REG_TYPE_NDQ
, one_reg_only
);
6019 /* Optional register operand was omitted. Unfortunately, it's in
6020 operands[i-1] and we need it to be in inst.operands[i]. Fix that
6021 here (this is a bit grotty). */
6022 inst
.operands
[i
] = inst
.operands
[i
-1];
6023 inst
.operands
[i
-1].present
= 0;
6026 /* There's a possibility of getting a 64-bit immediate here, so
6027 we need special handling. */
6028 if (parse_big_immediate (&str
, i
) == FAIL
)
6030 inst
.error
= _("immediate value is out of range");
6038 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6041 po_imm_or_fail (0, 0, TRUE
);
6046 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6051 po_scalar_or_goto (8, try_rr
);
6054 po_reg_or_fail (REG_TYPE_RN
);
6060 po_scalar_or_goto (8, try_nsdq
);
6063 po_reg_or_fail (REG_TYPE_NSDQ
);
6069 po_scalar_or_goto (8, try_ndq
);
6072 po_reg_or_fail (REG_TYPE_NDQ
);
6078 po_scalar_or_goto (8, try_vfd
);
6081 po_reg_or_fail (REG_TYPE_VFD
);
6086 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6087 not careful then bad things might happen. */
6088 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6093 po_reg_or_goto (REG_TYPE_NDQ
, try_mvnimm
);
6096 /* There's a possibility of getting a 64-bit immediate here, so
6097 we need special handling. */
6098 if (parse_big_immediate (&str
, i
) == FAIL
)
6100 inst
.error
= _("immediate value is out of range");
6108 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6111 po_imm_or_fail (0, 63, TRUE
);
6116 po_char_or_fail ('[');
6117 po_reg_or_fail (REG_TYPE_RN
);
6118 po_char_or_fail (']');
6123 po_reg_or_fail (REG_TYPE_RN
);
6124 if (skip_past_char (&str
, '!') == SUCCESS
)
6125 inst
.operands
[i
].writeback
= 1;
6129 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6130 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6131 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6132 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6133 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6134 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6135 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6136 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6137 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6138 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6139 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6140 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6142 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6144 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6145 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6147 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6148 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6149 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6151 /* Immediate variants */
6153 po_char_or_fail ('{');
6154 po_imm_or_fail (0, 255, TRUE
);
6155 po_char_or_fail ('}');
6159 /* The expression parser chokes on a trailing !, so we have
6160 to find it first and zap it. */
6163 while (*s
&& *s
!= ',')
6168 inst
.operands
[i
].writeback
= 1;
6170 po_imm_or_fail (0, 31, TRUE
);
6178 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6183 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6188 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6190 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6192 val
= parse_reloc (&str
);
6195 inst
.error
= _("unrecognized relocation suffix");
6198 else if (val
!= BFD_RELOC_UNUSED
)
6200 inst
.operands
[i
].imm
= val
;
6201 inst
.operands
[i
].hasreloc
= 1;
6206 /* Operand for MOVW or MOVT. */
6208 po_misc_or_fail (parse_half (&str
));
6211 /* Register or expression. */
6212 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6213 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6215 /* Register or immediate. */
6216 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6217 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6219 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6221 if (!is_immediate_prefix (*str
))
6224 val
= parse_fpa_immediate (&str
);
6227 /* FPA immediates are encoded as registers 8-15.
6228 parse_fpa_immediate has already applied the offset. */
6229 inst
.operands
[i
].reg
= val
;
6230 inst
.operands
[i
].isreg
= 1;
6233 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6234 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6236 /* Two kinds of register. */
6239 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6241 || (rege
->type
!= REG_TYPE_MMXWR
6242 && rege
->type
!= REG_TYPE_MMXWC
6243 && rege
->type
!= REG_TYPE_MMXWCG
))
6245 inst
.error
= _("iWMMXt data or control register expected");
6248 inst
.operands
[i
].reg
= rege
->number
;
6249 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6255 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6257 || (rege
->type
!= REG_TYPE_MMXWC
6258 && rege
->type
!= REG_TYPE_MMXWCG
))
6260 inst
.error
= _("iWMMXt control register expected");
6263 inst
.operands
[i
].reg
= rege
->number
;
6264 inst
.operands
[i
].isreg
= 1;
6269 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6270 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6271 case OP_oROR
: val
= parse_ror (&str
); break;
6272 case OP_PSR
: val
= parse_psr (&str
); break;
6273 case OP_COND
: val
= parse_cond (&str
); break;
6274 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
6277 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
6278 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
6281 val
= parse_psr (&str
);
6285 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6288 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6290 if (strncasecmp (str
, "APSR_", 5) == 0)
6297 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6298 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6299 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6300 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6301 default: found
= 16;
6305 inst
.operands
[i
].isvec
= 1;
6312 po_misc_or_fail (parse_tb (&str
));
6315 /* Register lists. */
6317 val
= parse_reg_list (&str
);
6320 inst
.operands
[1].writeback
= 1;
6326 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6330 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6334 /* Allow Q registers too. */
6335 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6340 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6342 inst
.operands
[i
].issingle
= 1;
6347 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6352 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6353 &inst
.operands
[i
].vectype
);
6356 /* Addressing modes */
6358 po_misc_or_fail (parse_address (&str
, i
));
6362 po_misc_or_fail_no_backtrack (
6363 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6367 po_misc_or_fail_no_backtrack (
6368 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6372 po_misc_or_fail_no_backtrack (
6373 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6377 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6381 po_misc_or_fail_no_backtrack (
6382 parse_shifter_operand_group_reloc (&str
, i
));
6386 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6390 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6394 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6398 as_fatal (_("unhandled operand code %d"), upat
[i
]);
6401 /* Various value-based sanity checks and shared operations. We
6402 do not signal immediate failures for the register constraints;
6403 this allows a syntax error to take precedence. */
6412 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6413 inst
.error
= BAD_PC
;
6431 inst
.operands
[i
].imm
= val
;
6438 /* If we get here, this operand was successfully parsed. */
6439 inst
.operands
[i
].present
= 1;
6443 inst
.error
= BAD_ARGS
;
6448 /* The parse routine should already have set inst.error, but set a
6449 default here just in case. */
6451 inst
.error
= _("syntax error");
6455 /* Do not backtrack over a trailing optional argument that
6456 absorbed some text. We will only fail again, with the
6457 'garbage following instruction' error message, which is
6458 probably less helpful than the current one. */
6459 if (backtrack_index
== i
&& backtrack_pos
!= str
6460 && upat
[i
+1] == OP_stop
)
6463 inst
.error
= _("syntax error");
6467 /* Try again, skipping the optional argument at backtrack_pos. */
6468 str
= backtrack_pos
;
6469 inst
.error
= backtrack_error
;
6470 inst
.operands
[backtrack_index
].present
= 0;
6471 i
= backtrack_index
;
6475 /* Check that we have parsed all the arguments. */
6476 if (*str
!= '\0' && !inst
.error
)
6477 inst
.error
= _("garbage following instruction");
6479 return inst
.error
? FAIL
: SUCCESS
;
6482 #undef po_char_or_fail
6483 #undef po_reg_or_fail
6484 #undef po_reg_or_goto
6485 #undef po_imm_or_fail
6486 #undef po_scalar_or_fail
6488 /* Shorthand macro for instruction encoding functions issuing errors. */
6489 #define constraint(expr, err) \
6500 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6501 instructions are unpredictable if these registers are used. This
6502 is the BadReg predicate in ARM's Thumb-2 documentation. */
6503 #define reject_bad_reg(reg) \
6505 if (reg == REG_SP || reg == REG_PC) \
6507 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6512 /* If REG is R13 (the stack pointer), warn that its use is
6514 #define warn_deprecated_sp(reg) \
6516 if (warn_on_deprecated && reg == REG_SP) \
6517 as_warn (_("use of r13 is deprecated")); \
6520 /* Functions for operand encoding. ARM, then Thumb. */
6522 #define rotate_left(v, n) (v << n | v >> (32 - n))
6524 /* If VAL can be encoded in the immediate field of an ARM instruction,
6525 return the encoded form. Otherwise, return FAIL. */
6528 encode_arm_immediate (unsigned int val
)
6532 for (i
= 0; i
< 32; i
+= 2)
6533 if ((a
= rotate_left (val
, i
)) <= 0xff)
6534 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6539 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6540 return the encoded form. Otherwise, return FAIL. */
6542 encode_thumb32_immediate (unsigned int val
)
6549 for (i
= 1; i
<= 24; i
++)
6552 if ((val
& ~(0xff << i
)) == 0)
6553 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6557 if (val
== ((a
<< 16) | a
))
6559 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6563 if (val
== ((a
<< 16) | a
))
6564 return 0x200 | (a
>> 8);
6568 /* Encode a VFP SP or DP register number into inst.instruction. */
6571 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6573 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6576 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6579 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6582 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6587 first_error (_("D register out of range for selected VFP version"));
6595 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6599 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6603 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6607 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6611 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6615 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6623 /* Encode a <shift> in an ARM-format instruction. The immediate,
6624 if any, is handled by md_apply_fix. */
6626 encode_arm_shift (int i
)
6628 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6629 inst
.instruction
|= SHIFT_ROR
<< 5;
6632 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6633 if (inst
.operands
[i
].immisreg
)
6635 inst
.instruction
|= SHIFT_BY_REG
;
6636 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6639 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6644 encode_arm_shifter_operand (int i
)
6646 if (inst
.operands
[i
].isreg
)
6648 inst
.instruction
|= inst
.operands
[i
].reg
;
6649 encode_arm_shift (i
);
6652 inst
.instruction
|= INST_IMMEDIATE
;
6655 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6657 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6659 gas_assert (inst
.operands
[i
].isreg
);
6660 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6662 if (inst
.operands
[i
].preind
)
6666 inst
.error
= _("instruction does not accept preindexed addressing");
6669 inst
.instruction
|= PRE_INDEX
;
6670 if (inst
.operands
[i
].writeback
)
6671 inst
.instruction
|= WRITE_BACK
;
6674 else if (inst
.operands
[i
].postind
)
6676 gas_assert (inst
.operands
[i
].writeback
);
6678 inst
.instruction
|= WRITE_BACK
;
6680 else /* unindexed - only for coprocessor */
6682 inst
.error
= _("instruction does not accept unindexed addressing");
6686 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6687 && (((inst
.instruction
& 0x000f0000) >> 16)
6688 == ((inst
.instruction
& 0x0000f000) >> 12)))
6689 as_warn ((inst
.instruction
& LOAD_BIT
)
6690 ? _("destination register same as write-back base")
6691 : _("source register same as write-back base"));
6694 /* inst.operands[i] was set up by parse_address. Encode it into an
6695 ARM-format mode 2 load or store instruction. If is_t is true,
6696 reject forms that cannot be used with a T instruction (i.e. not
6699 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6701 encode_arm_addr_mode_common (i
, is_t
);
6703 if (inst
.operands
[i
].immisreg
)
6705 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6706 inst
.instruction
|= inst
.operands
[i
].imm
;
6707 if (!inst
.operands
[i
].negative
)
6708 inst
.instruction
|= INDEX_UP
;
6709 if (inst
.operands
[i
].shifted
)
6711 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6712 inst
.instruction
|= SHIFT_ROR
<< 5;
6715 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6716 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6720 else /* immediate offset in inst.reloc */
6722 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6723 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6727 /* inst.operands[i] was set up by parse_address. Encode it into an
6728 ARM-format mode 3 load or store instruction. Reject forms that
6729 cannot be used with such instructions. If is_t is true, reject
6730 forms that cannot be used with a T instruction (i.e. not
6733 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6735 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6737 inst
.error
= _("instruction does not accept scaled register index");
6741 encode_arm_addr_mode_common (i
, is_t
);
6743 if (inst
.operands
[i
].immisreg
)
6745 inst
.instruction
|= inst
.operands
[i
].imm
;
6746 if (!inst
.operands
[i
].negative
)
6747 inst
.instruction
|= INDEX_UP
;
6749 else /* immediate offset in inst.reloc */
6751 inst
.instruction
|= HWOFFSET_IMM
;
6752 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6753 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6757 /* inst.operands[i] was set up by parse_address. Encode it into an
6758 ARM-format instruction. Reject all forms which cannot be encoded
6759 into a coprocessor load/store instruction. If wb_ok is false,
6760 reject use of writeback; if unind_ok is false, reject use of
6761 unindexed addressing. If reloc_override is not 0, use it instead
6762 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6763 (in which case it is preserved). */
6766 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6768 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6770 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6772 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6774 gas_assert (!inst
.operands
[i
].writeback
);
6777 inst
.error
= _("instruction does not support unindexed addressing");
6780 inst
.instruction
|= inst
.operands
[i
].imm
;
6781 inst
.instruction
|= INDEX_UP
;
6785 if (inst
.operands
[i
].preind
)
6786 inst
.instruction
|= PRE_INDEX
;
6788 if (inst
.operands
[i
].writeback
)
6790 if (inst
.operands
[i
].reg
== REG_PC
)
6792 inst
.error
= _("pc may not be used with write-back");
6797 inst
.error
= _("instruction does not support writeback");
6800 inst
.instruction
|= WRITE_BACK
;
6804 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
6805 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6806 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6807 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6810 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6812 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6818 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6819 Determine whether it can be performed with a move instruction; if
6820 it can, convert inst.instruction to that move instruction and
6821 return TRUE; if it can't, convert inst.instruction to a literal-pool
6822 load and return FALSE. If this is not a valid thing to do in the
6823 current context, set inst.error and return TRUE.
6825 inst.operands[i] describes the destination register. */
6828 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6833 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6837 if ((inst
.instruction
& tbit
) == 0)
6839 inst
.error
= _("invalid pseudo operation");
6842 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6844 inst
.error
= _("constant expression expected");
6847 if (inst
.reloc
.exp
.X_op
== O_constant
)
6851 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6853 /* This can be done with a mov(1) instruction. */
6854 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6855 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6861 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6864 /* This can be done with a mov instruction. */
6865 inst
.instruction
&= LITERAL_MASK
;
6866 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6867 inst
.instruction
|= value
& 0xfff;
6871 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6874 /* This can be done with a mvn instruction. */
6875 inst
.instruction
&= LITERAL_MASK
;
6876 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6877 inst
.instruction
|= value
& 0xfff;
6883 if (add_to_lit_pool () == FAIL
)
6885 inst
.error
= _("literal pool insertion failed");
6888 inst
.operands
[1].reg
= REG_PC
;
6889 inst
.operands
[1].isreg
= 1;
6890 inst
.operands
[1].preind
= 1;
6891 inst
.reloc
.pc_rel
= 1;
6892 inst
.reloc
.type
= (thumb_p
6893 ? BFD_RELOC_ARM_THUMB_OFFSET
6895 ? BFD_RELOC_ARM_HWLITERAL
6896 : BFD_RELOC_ARM_LITERAL
));
6900 /* Functions for instruction encoding, sorted by sub-architecture.
6901 First some generics; their names are taken from the conventional
6902 bit positions for register arguments in ARM format instructions. */
6912 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6918 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6919 inst
.instruction
|= inst
.operands
[1].reg
;
6925 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6926 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6932 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6933 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6939 unsigned Rn
= inst
.operands
[2].reg
;
6940 /* Enforce restrictions on SWP instruction. */
6941 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6942 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6943 _("Rn must not overlap other operands"));
6944 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6945 inst
.instruction
|= inst
.operands
[1].reg
;
6946 inst
.instruction
|= Rn
<< 16;
6952 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6953 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6954 inst
.instruction
|= inst
.operands
[2].reg
;
6960 inst
.instruction
|= inst
.operands
[0].reg
;
6961 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6962 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6968 inst
.instruction
|= inst
.operands
[0].imm
;
6974 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6975 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6978 /* ARM instructions, in alphabetical order by function name (except
6979 that wrapper functions appear immediately after the function they
6982 /* This is a pseudo-op of the form "adr rd, label" to be converted
6983 into a relative address of the form "add rd, pc, #label-.-8". */
6988 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6990 /* Frag hacking will turn this into a sub instruction if the offset turns
6991 out to be negative. */
6992 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6993 inst
.reloc
.pc_rel
= 1;
6994 inst
.reloc
.exp
.X_add_number
-= 8;
6997 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6998 into a relative address of the form:
6999 add rd, pc, #low(label-.-8)"
7000 add rd, rd, #high(label-.-8)" */
7005 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7007 /* Frag hacking will turn this into a sub instruction if the offset turns
7008 out to be negative. */
7009 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7010 inst
.reloc
.pc_rel
= 1;
7011 inst
.size
= INSN_SIZE
* 2;
7012 inst
.reloc
.exp
.X_add_number
-= 8;
7018 if (!inst
.operands
[1].present
)
7019 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7020 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7021 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7022 encode_arm_shifter_operand (2);
7028 if (inst
.operands
[0].present
)
7030 constraint ((inst
.instruction
& 0xf0) != 0x40
7031 && inst
.operands
[0].imm
!= 0xf,
7032 _("bad barrier type"));
7033 inst
.instruction
|= inst
.operands
[0].imm
;
7036 inst
.instruction
|= 0xf;
7042 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7043 constraint (msb
> 32, _("bit-field extends past end of register"));
7044 /* The instruction encoding stores the LSB and MSB,
7045 not the LSB and width. */
7046 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7047 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7048 inst
.instruction
|= (msb
- 1) << 16;
7056 /* #0 in second position is alternative syntax for bfc, which is
7057 the same instruction but with REG_PC in the Rm field. */
7058 if (!inst
.operands
[1].isreg
)
7059 inst
.operands
[1].reg
= REG_PC
;
7061 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7062 constraint (msb
> 32, _("bit-field extends past end of register"));
7063 /* The instruction encoding stores the LSB and MSB,
7064 not the LSB and width. */
7065 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7066 inst
.instruction
|= inst
.operands
[1].reg
;
7067 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7068 inst
.instruction
|= (msb
- 1) << 16;
7074 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7075 _("bit-field extends past end of register"));
7076 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7077 inst
.instruction
|= inst
.operands
[1].reg
;
7078 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7079 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7082 /* ARM V5 breakpoint instruction (argument parse)
7083 BKPT <16 bit unsigned immediate>
7084 Instruction is not conditional.
7085 The bit pattern given in insns[] has the COND_ALWAYS condition,
7086 and it is an error if the caller tried to override that. */
7091 /* Top 12 of 16 bits to bits 19:8. */
7092 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7094 /* Bottom 4 of 16 bits to bits 3:0. */
7095 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7099 encode_branch (int default_reloc
)
7101 if (inst
.operands
[0].hasreloc
)
7103 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
7104 _("the only suffix valid here is '(plt)'"));
7105 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
7109 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7111 inst
.reloc
.pc_rel
= 1;
7118 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7119 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7122 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7129 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7131 if (inst
.cond
== COND_ALWAYS
)
7132 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7134 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7138 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7141 /* ARM V5 branch-link-exchange instruction (argument parse)
7142 BLX <target_addr> ie BLX(1)
7143 BLX{<condition>} <Rm> ie BLX(2)
7144 Unfortunately, there are two different opcodes for this mnemonic.
7145 So, the insns[].value is not used, and the code here zaps values
7146 into inst.instruction.
7147 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7152 if (inst
.operands
[0].isreg
)
7154 /* Arg is a register; the opcode provided by insns[] is correct.
7155 It is not illegal to do "blx pc", just useless. */
7156 if (inst
.operands
[0].reg
== REG_PC
)
7157 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7159 inst
.instruction
|= inst
.operands
[0].reg
;
7163 /* Arg is an address; this instruction cannot be executed
7164 conditionally, and the opcode must be adjusted.
7165 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7166 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7167 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7168 inst
.instruction
= 0xfa000000;
7169 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7176 bfd_boolean want_reloc
;
7178 if (inst
.operands
[0].reg
== REG_PC
)
7179 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7181 inst
.instruction
|= inst
.operands
[0].reg
;
7182 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7183 it is for ARMv4t or earlier. */
7184 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7185 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7189 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7194 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7198 /* ARM v5TEJ. Jump to Jazelle code. */
7203 if (inst
.operands
[0].reg
== REG_PC
)
7204 as_tsktsk (_("use of r15 in bxj is not really useful"));
7206 inst
.instruction
|= inst
.operands
[0].reg
;
7209 /* Co-processor data operation:
7210 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7211 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7215 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7216 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7217 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7218 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7219 inst
.instruction
|= inst
.operands
[4].reg
;
7220 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7226 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7227 encode_arm_shifter_operand (1);
7230 /* Transfer between coprocessor and ARM registers.
7231 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7236 No special properties. */
7243 Rd
= inst
.operands
[2].reg
;
7246 if (inst
.instruction
== 0xee000010
7247 || inst
.instruction
== 0xfe000010)
7249 reject_bad_reg (Rd
);
7252 constraint (Rd
== REG_SP
, BAD_SP
);
7257 if (inst
.instruction
== 0xe000010)
7258 constraint (Rd
== REG_PC
, BAD_PC
);
7262 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7263 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7264 inst
.instruction
|= Rd
<< 12;
7265 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7266 inst
.instruction
|= inst
.operands
[4].reg
;
7267 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7270 /* Transfer between coprocessor register and pair of ARM registers.
7271 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7276 Two XScale instructions are special cases of these:
7278 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7279 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7281 Result unpredictable if Rd or Rn is R15. */
7288 Rd
= inst
.operands
[2].reg
;
7289 Rn
= inst
.operands
[3].reg
;
7293 reject_bad_reg (Rd
);
7294 reject_bad_reg (Rn
);
7298 constraint (Rd
== REG_PC
, BAD_PC
);
7299 constraint (Rn
== REG_PC
, BAD_PC
);
7302 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7303 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7304 inst
.instruction
|= Rd
<< 12;
7305 inst
.instruction
|= Rn
<< 16;
7306 inst
.instruction
|= inst
.operands
[4].reg
;
7312 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7313 if (inst
.operands
[1].present
)
7315 inst
.instruction
|= CPSI_MMOD
;
7316 inst
.instruction
|= inst
.operands
[1].imm
;
7323 inst
.instruction
|= inst
.operands
[0].imm
;
7329 /* There is no IT instruction in ARM mode. We
7330 process it to do the validation as if in
7331 thumb mode, just in case the code gets
7332 assembled for thumb using the unified syntax. */
7337 set_it_insn_type (IT_INSN
);
7338 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7339 now_it
.cc
= inst
.operands
[0].imm
;
7346 int base_reg
= inst
.operands
[0].reg
;
7347 int range
= inst
.operands
[1].imm
;
7349 inst
.instruction
|= base_reg
<< 16;
7350 inst
.instruction
|= range
;
7352 if (inst
.operands
[1].writeback
)
7353 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7355 if (inst
.operands
[0].writeback
)
7357 inst
.instruction
|= WRITE_BACK
;
7358 /* Check for unpredictable uses of writeback. */
7359 if (inst
.instruction
& LOAD_BIT
)
7361 /* Not allowed in LDM type 2. */
7362 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7363 && ((range
& (1 << REG_PC
)) == 0))
7364 as_warn (_("writeback of base register is UNPREDICTABLE"));
7365 /* Only allowed if base reg not in list for other types. */
7366 else if (range
& (1 << base_reg
))
7367 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7371 /* Not allowed for type 2. */
7372 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7373 as_warn (_("writeback of base register is UNPREDICTABLE"));
7374 /* Only allowed if base reg not in list, or first in list. */
7375 else if ((range
& (1 << base_reg
))
7376 && (range
& ((1 << base_reg
) - 1)))
7377 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7382 /* ARMv5TE load-consecutive (argument parse)
7391 constraint (inst
.operands
[0].reg
% 2 != 0,
7392 _("first destination register must be even"));
7393 constraint (inst
.operands
[1].present
7394 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7395 _("can only load two consecutive registers"));
7396 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7397 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7399 if (!inst
.operands
[1].present
)
7400 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7402 if (inst
.instruction
& LOAD_BIT
)
7404 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7405 register and the first register written; we have to diagnose
7406 overlap between the base and the second register written here. */
7408 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7409 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7410 as_warn (_("base register written back, and overlaps "
7411 "second destination register"));
7413 /* For an index-register load, the index register must not overlap the
7414 destination (even if not write-back). */
7415 else if (inst
.operands
[2].immisreg
7416 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7417 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7418 as_warn (_("index register overlaps destination register"));
7421 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7422 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7428 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7429 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7430 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7431 || inst
.operands
[1].negative
7432 /* This can arise if the programmer has written
7434 or if they have mistakenly used a register name as the last
7437 It is very difficult to distinguish between these two cases
7438 because "rX" might actually be a label. ie the register
7439 name has been occluded by a symbol of the same name. So we
7440 just generate a general 'bad addressing mode' type error
7441 message and leave it up to the programmer to discover the
7442 true cause and fix their mistake. */
7443 || (inst
.operands
[1].reg
== REG_PC
),
7446 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7447 || inst
.reloc
.exp
.X_add_number
!= 0,
7448 _("offset must be zero in ARM encoding"));
7450 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7451 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7452 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7458 constraint (inst
.operands
[0].reg
% 2 != 0,
7459 _("even register required"));
7460 constraint (inst
.operands
[1].present
7461 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7462 _("can only load two consecutive registers"));
7463 /* If op 1 were present and equal to PC, this function wouldn't
7464 have been called in the first place. */
7465 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7467 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7468 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7474 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7475 if (!inst
.operands
[1].isreg
)
7476 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7478 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7484 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7486 if (inst
.operands
[1].preind
)
7488 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7489 || inst
.reloc
.exp
.X_add_number
!= 0,
7490 _("this instruction requires a post-indexed address"));
7492 inst
.operands
[1].preind
= 0;
7493 inst
.operands
[1].postind
= 1;
7494 inst
.operands
[1].writeback
= 1;
7496 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7497 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7500 /* Halfword and signed-byte load/store operations. */
7505 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7506 if (!inst
.operands
[1].isreg
)
7507 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7509 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7515 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7517 if (inst
.operands
[1].preind
)
7519 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7520 || inst
.reloc
.exp
.X_add_number
!= 0,
7521 _("this instruction requires a post-indexed address"));
7523 inst
.operands
[1].preind
= 0;
7524 inst
.operands
[1].postind
= 1;
7525 inst
.operands
[1].writeback
= 1;
7527 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7528 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7531 /* Co-processor register load/store.
7532 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7536 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7537 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7538 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7544 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7545 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7546 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7547 && !(inst
.instruction
& 0x00400000))
7548 as_tsktsk (_("Rd and Rm should be different in mla"));
7550 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7551 inst
.instruction
|= inst
.operands
[1].reg
;
7552 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7553 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7559 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7560 encode_arm_shifter_operand (1);
7563 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7570 top
= (inst
.instruction
& 0x00400000) != 0;
7571 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7572 _(":lower16: not allowed this instruction"));
7573 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7574 _(":upper16: not allowed instruction"));
7575 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7576 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7578 imm
= inst
.reloc
.exp
.X_add_number
;
7579 /* The value is in two pieces: 0:11, 16:19. */
7580 inst
.instruction
|= (imm
& 0x00000fff);
7581 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7585 static void do_vfp_nsyn_opcode (const char *);
7588 do_vfp_nsyn_mrs (void)
7590 if (inst
.operands
[0].isvec
)
7592 if (inst
.operands
[1].reg
!= 1)
7593 first_error (_("operand 1 must be FPSCR"));
7594 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7595 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7596 do_vfp_nsyn_opcode ("fmstat");
7598 else if (inst
.operands
[1].isvec
)
7599 do_vfp_nsyn_opcode ("fmrx");
7607 do_vfp_nsyn_msr (void)
7609 if (inst
.operands
[0].isvec
)
7610 do_vfp_nsyn_opcode ("fmxr");
7620 if (do_vfp_nsyn_mrs () == SUCCESS
)
7623 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7624 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7626 _("'CPSR' or 'SPSR' expected"));
7627 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7628 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7631 /* Two possible forms:
7632 "{C|S}PSR_<field>, Rm",
7633 "{C|S}PSR_f, #expression". */
7638 if (do_vfp_nsyn_msr () == SUCCESS
)
7641 inst
.instruction
|= inst
.operands
[0].imm
;
7642 if (inst
.operands
[1].isreg
)
7643 inst
.instruction
|= inst
.operands
[1].reg
;
7646 inst
.instruction
|= INST_IMMEDIATE
;
7647 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7648 inst
.reloc
.pc_rel
= 0;
7655 if (!inst
.operands
[2].present
)
7656 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7657 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7658 inst
.instruction
|= inst
.operands
[1].reg
;
7659 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7661 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7662 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7663 as_tsktsk (_("Rd and Rm should be different in mul"));
7666 /* Long Multiply Parser
7667 UMULL RdLo, RdHi, Rm, Rs
7668 SMULL RdLo, RdHi, Rm, Rs
7669 UMLAL RdLo, RdHi, Rm, Rs
7670 SMLAL RdLo, RdHi, Rm, Rs. */
7675 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7676 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7677 inst
.instruction
|= inst
.operands
[2].reg
;
7678 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7680 /* rdhi and rdlo must be different. */
7681 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7682 as_tsktsk (_("rdhi and rdlo must be different"));
7684 /* rdhi, rdlo and rm must all be different before armv6. */
7685 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7686 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7687 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7688 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7694 if (inst
.operands
[0].present
7695 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
7697 /* Architectural NOP hints are CPSR sets with no bits selected. */
7698 inst
.instruction
&= 0xf0000000;
7699 inst
.instruction
|= 0x0320f000;
7700 if (inst
.operands
[0].present
)
7701 inst
.instruction
|= inst
.operands
[0].imm
;
7705 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7706 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7707 Condition defaults to COND_ALWAYS.
7708 Error if Rd, Rn or Rm are R15. */
7713 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7714 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7715 inst
.instruction
|= inst
.operands
[2].reg
;
7716 if (inst
.operands
[3].present
)
7717 encode_arm_shift (3);
7720 /* ARM V6 PKHTB (Argument Parse). */
7725 if (!inst
.operands
[3].present
)
7727 /* If the shift specifier is omitted, turn the instruction
7728 into pkhbt rd, rm, rn. */
7729 inst
.instruction
&= 0xfff00010;
7730 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7731 inst
.instruction
|= inst
.operands
[1].reg
;
7732 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7736 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7737 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7738 inst
.instruction
|= inst
.operands
[2].reg
;
7739 encode_arm_shift (3);
7743 /* ARMv5TE: Preload-Cache
7747 Syntactically, like LDR with B=1, W=0, L=1. */
7752 constraint (!inst
.operands
[0].isreg
,
7753 _("'[' expected after PLD mnemonic"));
7754 constraint (inst
.operands
[0].postind
,
7755 _("post-indexed expression used in preload instruction"));
7756 constraint (inst
.operands
[0].writeback
,
7757 _("writeback used in preload instruction"));
7758 constraint (!inst
.operands
[0].preind
,
7759 _("unindexed addressing used in preload instruction"));
7760 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7763 /* ARMv7: PLI <addr_mode> */
7767 constraint (!inst
.operands
[0].isreg
,
7768 _("'[' expected after PLI mnemonic"));
7769 constraint (inst
.operands
[0].postind
,
7770 _("post-indexed expression used in preload instruction"));
7771 constraint (inst
.operands
[0].writeback
,
7772 _("writeback used in preload instruction"));
7773 constraint (!inst
.operands
[0].preind
,
7774 _("unindexed addressing used in preload instruction"));
7775 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7776 inst
.instruction
&= ~PRE_INDEX
;
7782 inst
.operands
[1] = inst
.operands
[0];
7783 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7784 inst
.operands
[0].isreg
= 1;
7785 inst
.operands
[0].writeback
= 1;
7786 inst
.operands
[0].reg
= REG_SP
;
7790 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7791 word at the specified address and the following word
7793 Unconditionally executed.
7794 Error if Rn is R15. */
7799 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7800 if (inst
.operands
[0].writeback
)
7801 inst
.instruction
|= WRITE_BACK
;
7804 /* ARM V6 ssat (argument parse). */
7809 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7810 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7811 inst
.instruction
|= inst
.operands
[2].reg
;
7813 if (inst
.operands
[3].present
)
7814 encode_arm_shift (3);
7817 /* ARM V6 usat (argument parse). */
7822 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7823 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7824 inst
.instruction
|= inst
.operands
[2].reg
;
7826 if (inst
.operands
[3].present
)
7827 encode_arm_shift (3);
7830 /* ARM V6 ssat16 (argument parse). */
7835 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7836 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7837 inst
.instruction
|= inst
.operands
[2].reg
;
7843 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7844 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7845 inst
.instruction
|= inst
.operands
[2].reg
;
7848 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7849 preserving the other bits.
7851 setend <endian_specifier>, where <endian_specifier> is either
7857 if (inst
.operands
[0].imm
)
7858 inst
.instruction
|= 0x200;
7864 unsigned int Rm
= (inst
.operands
[1].present
7865 ? inst
.operands
[1].reg
7866 : inst
.operands
[0].reg
);
7868 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7869 inst
.instruction
|= Rm
;
7870 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7872 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7873 inst
.instruction
|= SHIFT_BY_REG
;
7876 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7882 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7883 inst
.reloc
.pc_rel
= 0;
7889 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7890 inst
.reloc
.pc_rel
= 0;
7893 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7894 SMLAxy{cond} Rd,Rm,Rs,Rn
7895 SMLAWy{cond} Rd,Rm,Rs,Rn
7896 Error if any register is R15. */
7901 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7902 inst
.instruction
|= inst
.operands
[1].reg
;
7903 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7904 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7907 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7908 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7909 Error if any register is R15.
7910 Warning if Rdlo == Rdhi. */
7915 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7916 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7917 inst
.instruction
|= inst
.operands
[2].reg
;
7918 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7920 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7921 as_tsktsk (_("rdhi and rdlo must be different"));
7924 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7925 SMULxy{cond} Rd,Rm,Rs
7926 Error if any register is R15. */
7931 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7932 inst
.instruction
|= inst
.operands
[1].reg
;
7933 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7936 /* ARM V6 srs (argument parse). The variable fields in the encoding are
7937 the same for both ARM and Thumb-2. */
7944 if (inst
.operands
[0].present
)
7946 reg
= inst
.operands
[0].reg
;
7947 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
7952 inst
.instruction
|= reg
<< 16;
7953 inst
.instruction
|= inst
.operands
[1].imm
;
7954 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
7955 inst
.instruction
|= WRITE_BACK
;
7958 /* ARM V6 strex (argument parse). */
7963 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7964 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7965 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7966 || inst
.operands
[2].negative
7967 /* See comment in do_ldrex(). */
7968 || (inst
.operands
[2].reg
== REG_PC
),
7971 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7972 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
7974 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7975 || inst
.reloc
.exp
.X_add_number
!= 0,
7976 _("offset must be zero in ARM encoding"));
7978 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7979 inst
.instruction
|= inst
.operands
[1].reg
;
7980 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7981 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7987 constraint (inst
.operands
[1].reg
% 2 != 0,
7988 _("even register required"));
7989 constraint (inst
.operands
[2].present
7990 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
7991 _("can only store two consecutive registers"));
7992 /* If op 2 were present and equal to PC, this function wouldn't
7993 have been called in the first place. */
7994 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
7996 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7997 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
7998 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8001 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8002 inst
.instruction
|= inst
.operands
[1].reg
;
8003 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8006 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8007 extends it to 32-bits, and adds the result to a value in another
8008 register. You can specify a rotation by 0, 8, 16, or 24 bits
8009 before extracting the 16-bit value.
8010 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8011 Condition defaults to COND_ALWAYS.
8012 Error if any register uses R15. */
8017 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8018 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8019 inst
.instruction
|= inst
.operands
[2].reg
;
8020 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8025 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8026 Condition defaults to COND_ALWAYS.
8027 Error if any register uses R15. */
8032 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8033 inst
.instruction
|= inst
.operands
[1].reg
;
8034 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8037 /* VFP instructions. In a logical order: SP variant first, monad
8038 before dyad, arithmetic then move then load/store. */
8041 do_vfp_sp_monadic (void)
8043 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8044 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8048 do_vfp_sp_dyadic (void)
8050 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8051 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8052 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8056 do_vfp_sp_compare_z (void)
8058 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8062 do_vfp_dp_sp_cvt (void)
8064 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8065 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8069 do_vfp_sp_dp_cvt (void)
8071 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8072 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8076 do_vfp_reg_from_sp (void)
8078 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8079 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8083 do_vfp_reg2_from_sp2 (void)
8085 constraint (inst
.operands
[2].imm
!= 2,
8086 _("only two consecutive VFP SP registers allowed here"));
8087 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8088 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8089 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8093 do_vfp_sp_from_reg (void)
8095 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8096 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8100 do_vfp_sp2_from_reg2 (void)
8102 constraint (inst
.operands
[0].imm
!= 2,
8103 _("only two consecutive VFP SP registers allowed here"));
8104 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8105 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8106 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8110 do_vfp_sp_ldst (void)
8112 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8113 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8117 do_vfp_dp_ldst (void)
8119 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8120 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8125 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8127 if (inst
.operands
[0].writeback
)
8128 inst
.instruction
|= WRITE_BACK
;
8130 constraint (ldstm_type
!= VFP_LDSTMIA
,
8131 _("this addressing mode requires base-register writeback"));
8132 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8133 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8134 inst
.instruction
|= inst
.operands
[1].imm
;
8138 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8142 if (inst
.operands
[0].writeback
)
8143 inst
.instruction
|= WRITE_BACK
;
8145 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8146 _("this addressing mode requires base-register writeback"));
8148 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8149 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8151 count
= inst
.operands
[1].imm
<< 1;
8152 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8155 inst
.instruction
|= count
;
8159 do_vfp_sp_ldstmia (void)
8161 vfp_sp_ldstm (VFP_LDSTMIA
);
8165 do_vfp_sp_ldstmdb (void)
8167 vfp_sp_ldstm (VFP_LDSTMDB
);
8171 do_vfp_dp_ldstmia (void)
8173 vfp_dp_ldstm (VFP_LDSTMIA
);
8177 do_vfp_dp_ldstmdb (void)
8179 vfp_dp_ldstm (VFP_LDSTMDB
);
8183 do_vfp_xp_ldstmia (void)
8185 vfp_dp_ldstm (VFP_LDSTMIAX
);
8189 do_vfp_xp_ldstmdb (void)
8191 vfp_dp_ldstm (VFP_LDSTMDBX
);
8195 do_vfp_dp_rd_rm (void)
8197 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8198 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8202 do_vfp_dp_rn_rd (void)
8204 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8205 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8209 do_vfp_dp_rd_rn (void)
8211 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8212 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8216 do_vfp_dp_rd_rn_rm (void)
8218 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8219 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8220 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8226 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8230 do_vfp_dp_rm_rd_rn (void)
8232 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8233 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8234 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8237 /* VFPv3 instructions. */
8239 do_vfp_sp_const (void)
8241 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8242 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8243 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8247 do_vfp_dp_const (void)
8249 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8250 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8251 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8255 vfp_conv (int srcsize
)
8257 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
8258 inst
.instruction
|= (immbits
& 1) << 5;
8259 inst
.instruction
|= (immbits
>> 1);
8263 do_vfp_sp_conv_16 (void)
8265 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8270 do_vfp_dp_conv_16 (void)
8272 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8277 do_vfp_sp_conv_32 (void)
8279 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8284 do_vfp_dp_conv_32 (void)
8286 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8290 /* FPA instructions. Also in a logical order. */
8295 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8296 inst
.instruction
|= inst
.operands
[1].reg
;
8300 do_fpa_ldmstm (void)
8302 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8303 switch (inst
.operands
[1].imm
)
8305 case 1: inst
.instruction
|= CP_T_X
; break;
8306 case 2: inst
.instruction
|= CP_T_Y
; break;
8307 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8312 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8314 /* The instruction specified "ea" or "fd", so we can only accept
8315 [Rn]{!}. The instruction does not really support stacking or
8316 unstacking, so we have to emulate these by setting appropriate
8317 bits and offsets. */
8318 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8319 || inst
.reloc
.exp
.X_add_number
!= 0,
8320 _("this instruction does not support indexing"));
8322 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8323 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8325 if (!(inst
.instruction
& INDEX_UP
))
8326 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8328 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8330 inst
.operands
[2].preind
= 0;
8331 inst
.operands
[2].postind
= 1;
8335 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8338 /* iWMMXt instructions: strictly in alphabetical order. */
8341 do_iwmmxt_tandorc (void)
8343 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8347 do_iwmmxt_textrc (void)
8349 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8350 inst
.instruction
|= inst
.operands
[1].imm
;
8354 do_iwmmxt_textrm (void)
8356 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8357 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8358 inst
.instruction
|= inst
.operands
[2].imm
;
8362 do_iwmmxt_tinsr (void)
8364 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8365 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8366 inst
.instruction
|= inst
.operands
[2].imm
;
8370 do_iwmmxt_tmia (void)
8372 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8373 inst
.instruction
|= inst
.operands
[1].reg
;
8374 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8378 do_iwmmxt_waligni (void)
8380 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8381 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8382 inst
.instruction
|= inst
.operands
[2].reg
;
8383 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8387 do_iwmmxt_wmerge (void)
8389 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8390 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8391 inst
.instruction
|= inst
.operands
[2].reg
;
8392 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8396 do_iwmmxt_wmov (void)
8398 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8399 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8400 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8401 inst
.instruction
|= inst
.operands
[1].reg
;
8405 do_iwmmxt_wldstbh (void)
8408 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8410 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8412 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8413 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8417 do_iwmmxt_wldstw (void)
8419 /* RIWR_RIWC clears .isreg for a control register. */
8420 if (!inst
.operands
[0].isreg
)
8422 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8423 inst
.instruction
|= 0xf0000000;
8426 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8427 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8431 do_iwmmxt_wldstd (void)
8433 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8434 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8435 && inst
.operands
[1].immisreg
)
8437 inst
.instruction
&= ~0x1a000ff;
8438 inst
.instruction
|= (0xf << 28);
8439 if (inst
.operands
[1].preind
)
8440 inst
.instruction
|= PRE_INDEX
;
8441 if (!inst
.operands
[1].negative
)
8442 inst
.instruction
|= INDEX_UP
;
8443 if (inst
.operands
[1].writeback
)
8444 inst
.instruction
|= WRITE_BACK
;
8445 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8446 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8447 inst
.instruction
|= inst
.operands
[1].imm
;
8450 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8454 do_iwmmxt_wshufh (void)
8456 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8457 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8458 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8459 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8463 do_iwmmxt_wzero (void)
8465 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8466 inst
.instruction
|= inst
.operands
[0].reg
;
8467 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8468 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8472 do_iwmmxt_wrwrwr_or_imm5 (void)
8474 if (inst
.operands
[2].isreg
)
8477 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8478 _("immediate operand requires iWMMXt2"));
8480 if (inst
.operands
[2].imm
== 0)
8482 switch ((inst
.instruction
>> 20) & 0xf)
8488 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8489 inst
.operands
[2].imm
= 16;
8490 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8496 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8497 inst
.operands
[2].imm
= 32;
8498 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8505 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8507 wrn
= (inst
.instruction
>> 16) & 0xf;
8508 inst
.instruction
&= 0xff0fff0f;
8509 inst
.instruction
|= wrn
;
8510 /* Bail out here; the instruction is now assembled. */
8515 /* Map 32 -> 0, etc. */
8516 inst
.operands
[2].imm
&= 0x1f;
8517 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8521 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8522 operations first, then control, shift, and load/store. */
8524 /* Insns like "foo X,Y,Z". */
8527 do_mav_triple (void)
8529 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8530 inst
.instruction
|= inst
.operands
[1].reg
;
8531 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8534 /* Insns like "foo W,X,Y,Z".
8535 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8540 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8541 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8542 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8543 inst
.instruction
|= inst
.operands
[3].reg
;
8546 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8550 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8553 /* Maverick shift immediate instructions.
8554 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8555 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8560 int imm
= inst
.operands
[2].imm
;
8562 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8563 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8565 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8566 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8567 Bit 4 should be 0. */
8568 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8570 inst
.instruction
|= imm
;
8573 /* XScale instructions. Also sorted arithmetic before move. */
8575 /* Xscale multiply-accumulate (argument parse)
8578 MIAxycc acc0,Rm,Rs. */
8583 inst
.instruction
|= inst
.operands
[1].reg
;
8584 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8587 /* Xscale move-accumulator-register (argument parse)
8589 MARcc acc0,RdLo,RdHi. */
8594 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8595 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8598 /* Xscale move-register-accumulator (argument parse)
8600 MRAcc RdLo,RdHi,acc0. */
8605 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8606 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8607 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8610 /* Encoding functions relevant only to Thumb. */
8612 /* inst.operands[i] is a shifted-register operand; encode
8613 it into inst.instruction in the format used by Thumb32. */
8616 encode_thumb32_shifted_operand (int i
)
8618 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8619 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8621 constraint (inst
.operands
[i
].immisreg
,
8622 _("shift by register not allowed in thumb mode"));
8623 inst
.instruction
|= inst
.operands
[i
].reg
;
8624 if (shift
== SHIFT_RRX
)
8625 inst
.instruction
|= SHIFT_ROR
<< 4;
8628 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8629 _("expression too complex"));
8631 constraint (value
> 32
8632 || (value
== 32 && (shift
== SHIFT_LSL
8633 || shift
== SHIFT_ROR
)),
8634 _("shift expression is too large"));
8638 else if (value
== 32)
8641 inst
.instruction
|= shift
<< 4;
8642 inst
.instruction
|= (value
& 0x1c) << 10;
8643 inst
.instruction
|= (value
& 0x03) << 6;
8648 /* inst.operands[i] was set up by parse_address. Encode it into a
8649 Thumb32 format load or store instruction. Reject forms that cannot
8650 be used with such instructions. If is_t is true, reject forms that
8651 cannot be used with a T instruction; if is_d is true, reject forms
8652 that cannot be used with a D instruction. */
8655 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8657 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8659 constraint (!inst
.operands
[i
].isreg
,
8660 _("Instruction does not support =N addresses"));
8662 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8663 if (inst
.operands
[i
].immisreg
)
8665 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
8666 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8667 constraint (inst
.operands
[i
].negative
,
8668 _("Thumb does not support negative register indexing"));
8669 constraint (inst
.operands
[i
].postind
,
8670 _("Thumb does not support register post-indexing"));
8671 constraint (inst
.operands
[i
].writeback
,
8672 _("Thumb does not support register indexing with writeback"));
8673 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8674 _("Thumb supports only LSL in shifted register indexing"));
8676 inst
.instruction
|= inst
.operands
[i
].imm
;
8677 if (inst
.operands
[i
].shifted
)
8679 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8680 _("expression too complex"));
8681 constraint (inst
.reloc
.exp
.X_add_number
< 0
8682 || inst
.reloc
.exp
.X_add_number
> 3,
8683 _("shift out of range"));
8684 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8686 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8688 else if (inst
.operands
[i
].preind
)
8690 constraint (is_pc
&& inst
.operands
[i
].writeback
,
8691 _("cannot use writeback with PC-relative addressing"));
8692 constraint (is_t
&& inst
.operands
[i
].writeback
,
8693 _("cannot use writeback with this instruction"));
8697 inst
.instruction
|= 0x01000000;
8698 if (inst
.operands
[i
].writeback
)
8699 inst
.instruction
|= 0x00200000;
8703 inst
.instruction
|= 0x00000c00;
8704 if (inst
.operands
[i
].writeback
)
8705 inst
.instruction
|= 0x00000100;
8707 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8709 else if (inst
.operands
[i
].postind
)
8711 gas_assert (inst
.operands
[i
].writeback
);
8712 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8713 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8716 inst
.instruction
|= 0x00200000;
8718 inst
.instruction
|= 0x00000900;
8719 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8721 else /* unindexed - only for coprocessor */
8722 inst
.error
= _("instruction does not accept unindexed addressing");
8725 /* Table of Thumb instructions which exist in both 16- and 32-bit
8726 encodings (the latter only in post-V6T2 cores). The index is the
8727 value used in the insns table below. When there is more than one
8728 possible 16-bit encoding for the instruction, this table always
8730 Also contains several pseudo-instructions used during relaxation. */
8731 #define T16_32_TAB \
8732 X(_adc, 4140, eb400000), \
8733 X(_adcs, 4140, eb500000), \
8734 X(_add, 1c00, eb000000), \
8735 X(_adds, 1c00, eb100000), \
8736 X(_addi, 0000, f1000000), \
8737 X(_addis, 0000, f1100000), \
8738 X(_add_pc,000f, f20f0000), \
8739 X(_add_sp,000d, f10d0000), \
8740 X(_adr, 000f, f20f0000), \
8741 X(_and, 4000, ea000000), \
8742 X(_ands, 4000, ea100000), \
8743 X(_asr, 1000, fa40f000), \
8744 X(_asrs, 1000, fa50f000), \
8745 X(_b, e000, f000b000), \
8746 X(_bcond, d000, f0008000), \
8747 X(_bic, 4380, ea200000), \
8748 X(_bics, 4380, ea300000), \
8749 X(_cmn, 42c0, eb100f00), \
8750 X(_cmp, 2800, ebb00f00), \
8751 X(_cpsie, b660, f3af8400), \
8752 X(_cpsid, b670, f3af8600), \
8753 X(_cpy, 4600, ea4f0000), \
8754 X(_dec_sp,80dd, f1ad0d00), \
8755 X(_eor, 4040, ea800000), \
8756 X(_eors, 4040, ea900000), \
8757 X(_inc_sp,00dd, f10d0d00), \
8758 X(_ldmia, c800, e8900000), \
8759 X(_ldr, 6800, f8500000), \
8760 X(_ldrb, 7800, f8100000), \
8761 X(_ldrh, 8800, f8300000), \
8762 X(_ldrsb, 5600, f9100000), \
8763 X(_ldrsh, 5e00, f9300000), \
8764 X(_ldr_pc,4800, f85f0000), \
8765 X(_ldr_pc2,4800, f85f0000), \
8766 X(_ldr_sp,9800, f85d0000), \
8767 X(_lsl, 0000, fa00f000), \
8768 X(_lsls, 0000, fa10f000), \
8769 X(_lsr, 0800, fa20f000), \
8770 X(_lsrs, 0800, fa30f000), \
8771 X(_mov, 2000, ea4f0000), \
8772 X(_movs, 2000, ea5f0000), \
8773 X(_mul, 4340, fb00f000), \
8774 X(_muls, 4340, ffffffff), /* no 32b muls */ \
8775 X(_mvn, 43c0, ea6f0000), \
8776 X(_mvns, 43c0, ea7f0000), \
8777 X(_neg, 4240, f1c00000), /* rsb #0 */ \
8778 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
8779 X(_orr, 4300, ea400000), \
8780 X(_orrs, 4300, ea500000), \
8781 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8782 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
8783 X(_rev, ba00, fa90f080), \
8784 X(_rev16, ba40, fa90f090), \
8785 X(_revsh, bac0, fa90f0b0), \
8786 X(_ror, 41c0, fa60f000), \
8787 X(_rors, 41c0, fa70f000), \
8788 X(_sbc, 4180, eb600000), \
8789 X(_sbcs, 4180, eb700000), \
8790 X(_stmia, c000, e8800000), \
8791 X(_str, 6000, f8400000), \
8792 X(_strb, 7000, f8000000), \
8793 X(_strh, 8000, f8200000), \
8794 X(_str_sp,9000, f84d0000), \
8795 X(_sub, 1e00, eba00000), \
8796 X(_subs, 1e00, ebb00000), \
8797 X(_subi, 8000, f1a00000), \
8798 X(_subis, 8000, f1b00000), \
8799 X(_sxtb, b240, fa4ff080), \
8800 X(_sxth, b200, fa0ff080), \
8801 X(_tst, 4200, ea100f00), \
8802 X(_uxtb, b2c0, fa5ff080), \
8803 X(_uxth, b280, fa1ff080), \
8804 X(_nop, bf00, f3af8000), \
8805 X(_yield, bf10, f3af8001), \
8806 X(_wfe, bf20, f3af8002), \
8807 X(_wfi, bf30, f3af8003), \
8808 X(_sev, bf40, f3af8004),
8810 /* To catch errors in encoding functions, the codes are all offset by
8811 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8812 as 16-bit instructions. */
8813 #define X(a,b,c) T_MNEM##a
8814 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8817 #define X(a,b,c) 0x##b
8818 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8819 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8822 #define X(a,b,c) 0x##c
8823 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8824 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8825 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8829 /* Thumb instruction encoders, in alphabetical order. */
8834 do_t_add_sub_w (void)
8838 Rd
= inst
.operands
[0].reg
;
8839 Rn
= inst
.operands
[1].reg
;
8841 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
8842 is the SP-{plus,minus}-immediate form of the instruction. */
8844 constraint (Rd
== REG_PC
, BAD_PC
);
8846 reject_bad_reg (Rd
);
8848 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8849 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8852 /* Parse an add or subtract instruction. We get here with inst.instruction
8853 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8860 Rd
= inst
.operands
[0].reg
;
8861 Rs
= (inst
.operands
[1].present
8862 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8863 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8866 set_it_insn_type_last ();
8874 flags
= (inst
.instruction
== T_MNEM_adds
8875 || inst
.instruction
== T_MNEM_subs
);
8877 narrow
= !in_it_block ();
8879 narrow
= in_it_block ();
8880 if (!inst
.operands
[2].isreg
)
8884 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
8886 add
= (inst
.instruction
== T_MNEM_add
8887 || inst
.instruction
== T_MNEM_adds
);
8889 if (inst
.size_req
!= 4)
8891 /* Attempt to use a narrow opcode, with relaxation if
8893 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8894 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8895 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8896 opcode
= T_MNEM_add_sp
;
8897 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8898 opcode
= T_MNEM_add_pc
;
8899 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8902 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8904 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8908 inst
.instruction
= THUMB_OP16(opcode
);
8909 inst
.instruction
|= (Rd
<< 4) | Rs
;
8910 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8911 if (inst
.size_req
!= 2)
8912 inst
.relax
= opcode
;
8915 constraint (inst
.size_req
== 2, BAD_HIREG
);
8917 if (inst
.size_req
== 4
8918 || (inst
.size_req
!= 2 && !opcode
))
8922 constraint (add
, BAD_PC
);
8923 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
8924 _("only SUBS PC, LR, #const allowed"));
8925 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8926 _("expression too complex"));
8927 constraint (inst
.reloc
.exp
.X_add_number
< 0
8928 || inst
.reloc
.exp
.X_add_number
> 0xff,
8929 _("immediate value out of range"));
8930 inst
.instruction
= T2_SUBS_PC_LR
8931 | inst
.reloc
.exp
.X_add_number
;
8932 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8935 else if (Rs
== REG_PC
)
8937 /* Always use addw/subw. */
8938 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
8939 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8943 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8944 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
8947 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8949 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
8951 inst
.instruction
|= Rd
<< 8;
8952 inst
.instruction
|= Rs
<< 16;
8957 Rn
= inst
.operands
[2].reg
;
8958 /* See if we can do this with a 16-bit instruction. */
8959 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
8961 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8966 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
8967 || inst
.instruction
== T_MNEM_add
)
8970 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8974 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
8976 /* Thumb-1 cores (except v6-M) require at least one high
8977 register in a narrow non flag setting add. */
8978 if (Rd
> 7 || Rn
> 7
8979 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
8980 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
8987 inst
.instruction
= T_OPCODE_ADD_HI
;
8988 inst
.instruction
|= (Rd
& 8) << 4;
8989 inst
.instruction
|= (Rd
& 7);
8990 inst
.instruction
|= Rn
<< 3;
8996 constraint (Rd
== REG_PC
, BAD_PC
);
8997 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
8998 constraint (Rs
== REG_PC
, BAD_PC
);
8999 reject_bad_reg (Rn
);
9001 /* If we get here, it can't be done in 16 bits. */
9002 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9003 _("shift must be constant"));
9004 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9005 inst
.instruction
|= Rd
<< 8;
9006 inst
.instruction
|= Rs
<< 16;
9007 encode_thumb32_shifted_operand (2);
9012 constraint (inst
.instruction
== T_MNEM_adds
9013 || inst
.instruction
== T_MNEM_subs
,
9016 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9018 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9019 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9022 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9024 inst
.instruction
|= (Rd
<< 4) | Rs
;
9025 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9029 Rn
= inst
.operands
[2].reg
;
9030 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9032 /* We now have Rd, Rs, and Rn set to registers. */
9033 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9035 /* Can't do this for SUB. */
9036 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9037 inst
.instruction
= T_OPCODE_ADD_HI
;
9038 inst
.instruction
|= (Rd
& 8) << 4;
9039 inst
.instruction
|= (Rd
& 7);
9041 inst
.instruction
|= Rn
<< 3;
9043 inst
.instruction
|= Rs
<< 3;
9045 constraint (1, _("dest must overlap one source register"));
9049 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9050 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9051 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9061 Rd
= inst
.operands
[0].reg
;
9062 reject_bad_reg (Rd
);
9064 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9066 /* Defer to section relaxation. */
9067 inst
.relax
= inst
.instruction
;
9068 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9069 inst
.instruction
|= Rd
<< 4;
9071 else if (unified_syntax
&& inst
.size_req
!= 2)
9073 /* Generate a 32-bit opcode. */
9074 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9075 inst
.instruction
|= Rd
<< 8;
9076 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9077 inst
.reloc
.pc_rel
= 1;
9081 /* Generate a 16-bit opcode. */
9082 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9083 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9084 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9085 inst
.reloc
.pc_rel
= 1;
9087 inst
.instruction
|= Rd
<< 4;
9091 /* Arithmetic instructions for which there is just one 16-bit
9092 instruction encoding, and it allows only two low registers.
9093 For maximal compatibility with ARM syntax, we allow three register
9094 operands even when Thumb-32 instructions are not available, as long
9095 as the first two are identical. For instance, both "sbc r0,r1" and
9096 "sbc r0,r0,r1" are allowed. */
9102 Rd
= inst
.operands
[0].reg
;
9103 Rs
= (inst
.operands
[1].present
9104 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9105 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9106 Rn
= inst
.operands
[2].reg
;
9108 reject_bad_reg (Rd
);
9109 reject_bad_reg (Rs
);
9110 if (inst
.operands
[2].isreg
)
9111 reject_bad_reg (Rn
);
9115 if (!inst
.operands
[2].isreg
)
9117 /* For an immediate, we always generate a 32-bit opcode;
9118 section relaxation will shrink it later if possible. */
9119 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9120 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9121 inst
.instruction
|= Rd
<< 8;
9122 inst
.instruction
|= Rs
<< 16;
9123 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9129 /* See if we can do this with a 16-bit instruction. */
9130 if (THUMB_SETS_FLAGS (inst
.instruction
))
9131 narrow
= !in_it_block ();
9133 narrow
= in_it_block ();
9135 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9137 if (inst
.operands
[2].shifted
)
9139 if (inst
.size_req
== 4)
9145 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9146 inst
.instruction
|= Rd
;
9147 inst
.instruction
|= Rn
<< 3;
9151 /* If we get here, it can't be done in 16 bits. */
9152 constraint (inst
.operands
[2].shifted
9153 && inst
.operands
[2].immisreg
,
9154 _("shift must be constant"));
9155 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9156 inst
.instruction
|= Rd
<< 8;
9157 inst
.instruction
|= Rs
<< 16;
9158 encode_thumb32_shifted_operand (2);
9163 /* On its face this is a lie - the instruction does set the
9164 flags. However, the only supported mnemonic in this mode
9166 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9168 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9169 _("unshifted register required"));
9170 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9171 constraint (Rd
!= Rs
,
9172 _("dest and source1 must be the same register"));
9174 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9175 inst
.instruction
|= Rd
;
9176 inst
.instruction
|= Rn
<< 3;
9180 /* Similarly, but for instructions where the arithmetic operation is
9181 commutative, so we can allow either of them to be different from
9182 the destination operand in a 16-bit instruction. For instance, all
9183 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9190 Rd
= inst
.operands
[0].reg
;
9191 Rs
= (inst
.operands
[1].present
9192 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9193 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9194 Rn
= inst
.operands
[2].reg
;
9196 reject_bad_reg (Rd
);
9197 reject_bad_reg (Rs
);
9198 if (inst
.operands
[2].isreg
)
9199 reject_bad_reg (Rn
);
9203 if (!inst
.operands
[2].isreg
)
9205 /* For an immediate, we always generate a 32-bit opcode;
9206 section relaxation will shrink it later if possible. */
9207 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9208 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9209 inst
.instruction
|= Rd
<< 8;
9210 inst
.instruction
|= Rs
<< 16;
9211 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9217 /* See if we can do this with a 16-bit instruction. */
9218 if (THUMB_SETS_FLAGS (inst
.instruction
))
9219 narrow
= !in_it_block ();
9221 narrow
= in_it_block ();
9223 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9225 if (inst
.operands
[2].shifted
)
9227 if (inst
.size_req
== 4)
9234 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9235 inst
.instruction
|= Rd
;
9236 inst
.instruction
|= Rn
<< 3;
9241 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9242 inst
.instruction
|= Rd
;
9243 inst
.instruction
|= Rs
<< 3;
9248 /* If we get here, it can't be done in 16 bits. */
9249 constraint (inst
.operands
[2].shifted
9250 && inst
.operands
[2].immisreg
,
9251 _("shift must be constant"));
9252 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9253 inst
.instruction
|= Rd
<< 8;
9254 inst
.instruction
|= Rs
<< 16;
9255 encode_thumb32_shifted_operand (2);
9260 /* On its face this is a lie - the instruction does set the
9261 flags. However, the only supported mnemonic in this mode
9263 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9265 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9266 _("unshifted register required"));
9267 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9269 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9270 inst
.instruction
|= Rd
;
9273 inst
.instruction
|= Rn
<< 3;
9275 inst
.instruction
|= Rs
<< 3;
9277 constraint (1, _("dest must overlap one source register"));
9284 if (inst
.operands
[0].present
)
9286 constraint ((inst
.instruction
& 0xf0) != 0x40
9287 && inst
.operands
[0].imm
!= 0xf,
9288 _("bad barrier type"));
9289 inst
.instruction
|= inst
.operands
[0].imm
;
9292 inst
.instruction
|= 0xf;
9299 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9300 constraint (msb
> 32, _("bit-field extends past end of register"));
9301 /* The instruction encoding stores the LSB and MSB,
9302 not the LSB and width. */
9303 Rd
= inst
.operands
[0].reg
;
9304 reject_bad_reg (Rd
);
9305 inst
.instruction
|= Rd
<< 8;
9306 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9307 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9308 inst
.instruction
|= msb
- 1;
9317 Rd
= inst
.operands
[0].reg
;
9318 reject_bad_reg (Rd
);
9320 /* #0 in second position is alternative syntax for bfc, which is
9321 the same instruction but with REG_PC in the Rm field. */
9322 if (!inst
.operands
[1].isreg
)
9326 Rn
= inst
.operands
[1].reg
;
9327 reject_bad_reg (Rn
);
9330 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9331 constraint (msb
> 32, _("bit-field extends past end of register"));
9332 /* The instruction encoding stores the LSB and MSB,
9333 not the LSB and width. */
9334 inst
.instruction
|= Rd
<< 8;
9335 inst
.instruction
|= Rn
<< 16;
9336 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9337 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9338 inst
.instruction
|= msb
- 1;
9346 Rd
= inst
.operands
[0].reg
;
9347 Rn
= inst
.operands
[1].reg
;
9349 reject_bad_reg (Rd
);
9350 reject_bad_reg (Rn
);
9352 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9353 _("bit-field extends past end of register"));
9354 inst
.instruction
|= Rd
<< 8;
9355 inst
.instruction
|= Rn
<< 16;
9356 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9357 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9358 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9361 /* ARM V5 Thumb BLX (argument parse)
9362 BLX <target_addr> which is BLX(1)
9363 BLX <Rm> which is BLX(2)
9364 Unfortunately, there are two different opcodes for this mnemonic.
9365 So, the insns[].value is not used, and the code here zaps values
9366 into inst.instruction.
9368 ??? How to take advantage of the additional two bits of displacement
9369 available in Thumb32 mode? Need new relocation? */
9374 set_it_insn_type_last ();
9376 if (inst
.operands
[0].isreg
)
9378 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9379 /* We have a register, so this is BLX(2). */
9380 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9384 /* No register. This must be BLX(1). */
9385 inst
.instruction
= 0xf000e800;
9386 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
9387 inst
.reloc
.pc_rel
= 1;
9398 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9402 /* Conditional branches inside IT blocks are encoded as unconditional
9409 if (cond
!= COND_ALWAYS
)
9410 opcode
= T_MNEM_bcond
;
9412 opcode
= inst
.instruction
;
9414 if (unified_syntax
&& inst
.size_req
== 4)
9416 inst
.instruction
= THUMB_OP32(opcode
);
9417 if (cond
== COND_ALWAYS
)
9418 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9421 gas_assert (cond
!= 0xF);
9422 inst
.instruction
|= cond
<< 22;
9423 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9428 inst
.instruction
= THUMB_OP16(opcode
);
9429 if (cond
== COND_ALWAYS
)
9430 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9433 inst
.instruction
|= cond
<< 8;
9434 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9436 /* Allow section relaxation. */
9437 if (unified_syntax
&& inst
.size_req
!= 2)
9438 inst
.relax
= opcode
;
9441 inst
.reloc
.pc_rel
= 1;
9447 constraint (inst
.cond
!= COND_ALWAYS
,
9448 _("instruction is always unconditional"));
9449 if (inst
.operands
[0].present
)
9451 constraint (inst
.operands
[0].imm
> 255,
9452 _("immediate value out of range"));
9453 inst
.instruction
|= inst
.operands
[0].imm
;
9454 set_it_insn_type (NEUTRAL_IT_INSN
);
9459 do_t_branch23 (void)
9461 set_it_insn_type_last ();
9462 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9463 inst
.reloc
.pc_rel
= 1;
9465 #if defined(OBJ_COFF)
9466 /* If the destination of the branch is a defined symbol which does not have
9467 the THUMB_FUNC attribute, then we must be calling a function which has
9468 the (interfacearm) attribute. We look for the Thumb entry point to that
9469 function and change the branch to refer to that function instead. */
9470 if ( inst
.reloc
.exp
.X_op
== O_symbol
9471 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9472 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9473 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9474 inst
.reloc
.exp
.X_add_symbol
=
9475 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9482 set_it_insn_type_last ();
9483 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9484 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9485 should cause the alignment to be checked once it is known. This is
9486 because BX PC only works if the instruction is word aligned. */
9494 set_it_insn_type_last ();
9495 Rm
= inst
.operands
[0].reg
;
9496 reject_bad_reg (Rm
);
9497 inst
.instruction
|= Rm
<< 16;
9506 Rd
= inst
.operands
[0].reg
;
9507 Rm
= inst
.operands
[1].reg
;
9509 reject_bad_reg (Rd
);
9510 reject_bad_reg (Rm
);
9512 inst
.instruction
|= Rd
<< 8;
9513 inst
.instruction
|= Rm
<< 16;
9514 inst
.instruction
|= Rm
;
9520 set_it_insn_type (OUTSIDE_IT_INSN
);
9521 inst
.instruction
|= inst
.operands
[0].imm
;
9527 set_it_insn_type (OUTSIDE_IT_INSN
);
9529 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9530 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9532 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9533 inst
.instruction
= 0xf3af8000;
9534 inst
.instruction
|= imod
<< 9;
9535 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9536 if (inst
.operands
[1].present
)
9537 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9541 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9542 && (inst
.operands
[0].imm
& 4),
9543 _("selected processor does not support 'A' form "
9544 "of this instruction"));
9545 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9546 _("Thumb does not support the 2-argument "
9547 "form of this instruction"));
9548 inst
.instruction
|= inst
.operands
[0].imm
;
9552 /* THUMB CPY instruction (argument parse). */
9557 if (inst
.size_req
== 4)
9559 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9560 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9561 inst
.instruction
|= inst
.operands
[1].reg
;
9565 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9566 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9567 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9574 set_it_insn_type (OUTSIDE_IT_INSN
);
9575 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9576 inst
.instruction
|= inst
.operands
[0].reg
;
9577 inst
.reloc
.pc_rel
= 1;
9578 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9584 inst
.instruction
|= inst
.operands
[0].imm
;
9590 unsigned Rd
, Rn
, Rm
;
9592 Rd
= inst
.operands
[0].reg
;
9593 Rn
= (inst
.operands
[1].present
9594 ? inst
.operands
[1].reg
: Rd
);
9595 Rm
= inst
.operands
[2].reg
;
9597 reject_bad_reg (Rd
);
9598 reject_bad_reg (Rn
);
9599 reject_bad_reg (Rm
);
9601 inst
.instruction
|= Rd
<< 8;
9602 inst
.instruction
|= Rn
<< 16;
9603 inst
.instruction
|= Rm
;
9609 if (unified_syntax
&& inst
.size_req
== 4)
9610 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9612 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9618 unsigned int cond
= inst
.operands
[0].imm
;
9620 set_it_insn_type (IT_INSN
);
9621 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
9624 /* If the condition is a negative condition, invert the mask. */
9625 if ((cond
& 0x1) == 0x0)
9627 unsigned int mask
= inst
.instruction
& 0x000f;
9629 if ((mask
& 0x7) == 0)
9630 /* no conversion needed */;
9631 else if ((mask
& 0x3) == 0)
9633 else if ((mask
& 0x1) == 0)
9638 inst
.instruction
&= 0xfff0;
9639 inst
.instruction
|= mask
;
9642 inst
.instruction
|= cond
<< 4;
9645 /* Helper function used for both push/pop and ldm/stm. */
9647 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9651 load
= (inst
.instruction
& (1 << 20)) != 0;
9653 if (mask
& (1 << 13))
9654 inst
.error
= _("SP not allowed in register list");
9657 if (mask
& (1 << 15))
9659 if (mask
& (1 << 14))
9660 inst
.error
= _("LR and PC should not both be in register list");
9662 set_it_insn_type_last ();
9665 if ((mask
& (1 << base
)) != 0
9667 as_warn (_("base register should not be in register list "
9668 "when written back"));
9672 if (mask
& (1 << 15))
9673 inst
.error
= _("PC not allowed in register list");
9675 if (mask
& (1 << base
))
9676 as_warn (_("value stored for r%d is UNPREDICTABLE"), base
);
9679 if ((mask
& (mask
- 1)) == 0)
9681 /* Single register transfers implemented as str/ldr. */
9684 if (inst
.instruction
& (1 << 23))
9685 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9687 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9691 if (inst
.instruction
& (1 << 23))
9692 inst
.instruction
= 0x00800000; /* ia -> [base] */
9694 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9697 inst
.instruction
|= 0xf8400000;
9699 inst
.instruction
|= 0x00100000;
9701 mask
= ffs (mask
) - 1;
9705 inst
.instruction
|= WRITE_BACK
;
9707 inst
.instruction
|= mask
;
9708 inst
.instruction
|= base
<< 16;
9714 /* This really doesn't seem worth it. */
9715 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9716 _("expression too complex"));
9717 constraint (inst
.operands
[1].writeback
,
9718 _("Thumb load/store multiple does not support {reglist}^"));
9726 /* See if we can use a 16-bit instruction. */
9727 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9728 && inst
.size_req
!= 4
9729 && !(inst
.operands
[1].imm
& ~0xff))
9731 mask
= 1 << inst
.operands
[0].reg
;
9733 if (inst
.operands
[0].reg
<= 7
9734 && (inst
.instruction
== T_MNEM_stmia
9735 ? inst
.operands
[0].writeback
9736 : (inst
.operands
[0].writeback
9737 == !(inst
.operands
[1].imm
& mask
))))
9739 if (inst
.instruction
== T_MNEM_stmia
9740 && (inst
.operands
[1].imm
& mask
)
9741 && (inst
.operands
[1].imm
& (mask
- 1)))
9742 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9743 inst
.operands
[0].reg
);
9745 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9746 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9747 inst
.instruction
|= inst
.operands
[1].imm
;
9750 else if (inst
.operands
[0] .reg
== REG_SP
9751 && inst
.operands
[0].writeback
)
9753 inst
.instruction
= THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9754 ? T_MNEM_push
: T_MNEM_pop
);
9755 inst
.instruction
|= inst
.operands
[1].imm
;
9762 if (inst
.instruction
< 0xffff)
9763 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9765 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
9766 inst
.operands
[0].writeback
);
9771 constraint (inst
.operands
[0].reg
> 7
9772 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9773 constraint (inst
.instruction
!= T_MNEM_ldmia
9774 && inst
.instruction
!= T_MNEM_stmia
,
9775 _("Thumb-2 instruction only valid in unified syntax"));
9776 if (inst
.instruction
== T_MNEM_stmia
)
9778 if (!inst
.operands
[0].writeback
)
9779 as_warn (_("this instruction will write back the base register"));
9780 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9781 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9782 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9783 inst
.operands
[0].reg
);
9787 if (!inst
.operands
[0].writeback
9788 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9789 as_warn (_("this instruction will write back the base register"));
9790 else if (inst
.operands
[0].writeback
9791 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9792 as_warn (_("this instruction will not write back the base register"));
9795 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9796 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9797 inst
.instruction
|= inst
.operands
[1].imm
;
9804 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9805 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9806 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9807 || inst
.operands
[1].negative
,
9810 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9811 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9812 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9818 if (!inst
.operands
[1].present
)
9820 constraint (inst
.operands
[0].reg
== REG_LR
,
9821 _("r14 not allowed as first register "
9822 "when second register is omitted"));
9823 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9825 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9828 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9829 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9830 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9836 unsigned long opcode
;
9839 if (inst
.operands
[0].isreg
9840 && !inst
.operands
[0].preind
9841 && inst
.operands
[0].reg
== REG_PC
)
9842 set_it_insn_type_last ();
9844 opcode
= inst
.instruction
;
9847 if (!inst
.operands
[1].isreg
)
9849 if (opcode
<= 0xffff)
9850 inst
.instruction
= THUMB_OP32 (opcode
);
9851 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9854 if (inst
.operands
[1].isreg
9855 && !inst
.operands
[1].writeback
9856 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9857 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9859 && inst
.size_req
!= 4)
9861 /* Insn may have a 16-bit form. */
9862 Rn
= inst
.operands
[1].reg
;
9863 if (inst
.operands
[1].immisreg
)
9865 inst
.instruction
= THUMB_OP16 (opcode
);
9867 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9870 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9871 && opcode
!= T_MNEM_ldrsb
)
9872 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9873 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9880 if (inst
.reloc
.pc_rel
)
9881 opcode
= T_MNEM_ldr_pc2
;
9883 opcode
= T_MNEM_ldr_pc
;
9887 if (opcode
== T_MNEM_ldr
)
9888 opcode
= T_MNEM_ldr_sp
;
9890 opcode
= T_MNEM_str_sp
;
9892 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9896 inst
.instruction
= inst
.operands
[0].reg
;
9897 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9899 inst
.instruction
|= THUMB_OP16 (opcode
);
9900 if (inst
.size_req
== 2)
9901 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9903 inst
.relax
= opcode
;
9907 /* Definitely a 32-bit variant. */
9908 inst
.instruction
= THUMB_OP32 (opcode
);
9909 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9910 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9914 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9916 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9918 /* Only [Rn,Rm] is acceptable. */
9919 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9920 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9921 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9922 || inst
.operands
[1].negative
,
9923 _("Thumb does not support this addressing mode"));
9924 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9928 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9929 if (!inst
.operands
[1].isreg
)
9930 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9933 constraint (!inst
.operands
[1].preind
9934 || inst
.operands
[1].shifted
9935 || inst
.operands
[1].writeback
,
9936 _("Thumb does not support this addressing mode"));
9937 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9939 constraint (inst
.instruction
& 0x0600,
9940 _("byte or halfword not valid for base register"));
9941 constraint (inst
.operands
[1].reg
== REG_PC
9942 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9943 _("r15 based store not allowed"));
9944 constraint (inst
.operands
[1].immisreg
,
9945 _("invalid base register for register offset"));
9947 if (inst
.operands
[1].reg
== REG_PC
)
9948 inst
.instruction
= T_OPCODE_LDR_PC
;
9949 else if (inst
.instruction
& THUMB_LOAD_BIT
)
9950 inst
.instruction
= T_OPCODE_LDR_SP
;
9952 inst
.instruction
= T_OPCODE_STR_SP
;
9954 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9955 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9959 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
9960 if (!inst
.operands
[1].immisreg
)
9962 /* Immediate offset. */
9963 inst
.instruction
|= inst
.operands
[0].reg
;
9964 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9965 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9969 /* Register offset. */
9970 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
9971 constraint (inst
.operands
[1].negative
,
9972 _("Thumb does not support this addressing mode"));
9975 switch (inst
.instruction
)
9977 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
9978 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
9979 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
9980 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
9981 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
9982 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
9983 case 0x5600 /* ldrsb */:
9984 case 0x5e00 /* ldrsh */: break;
9988 inst
.instruction
|= inst
.operands
[0].reg
;
9989 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9990 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
9996 if (!inst
.operands
[1].present
)
9998 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9999 constraint (inst
.operands
[0].reg
== REG_LR
,
10000 _("r14 not allowed here"));
10002 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10003 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10004 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10010 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10011 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10017 unsigned Rd
, Rn
, Rm
, Ra
;
10019 Rd
= inst
.operands
[0].reg
;
10020 Rn
= inst
.operands
[1].reg
;
10021 Rm
= inst
.operands
[2].reg
;
10022 Ra
= inst
.operands
[3].reg
;
10024 reject_bad_reg (Rd
);
10025 reject_bad_reg (Rn
);
10026 reject_bad_reg (Rm
);
10027 reject_bad_reg (Ra
);
10029 inst
.instruction
|= Rd
<< 8;
10030 inst
.instruction
|= Rn
<< 16;
10031 inst
.instruction
|= Rm
;
10032 inst
.instruction
|= Ra
<< 12;
10038 unsigned RdLo
, RdHi
, Rn
, Rm
;
10040 RdLo
= inst
.operands
[0].reg
;
10041 RdHi
= inst
.operands
[1].reg
;
10042 Rn
= inst
.operands
[2].reg
;
10043 Rm
= inst
.operands
[3].reg
;
10045 reject_bad_reg (RdLo
);
10046 reject_bad_reg (RdHi
);
10047 reject_bad_reg (Rn
);
10048 reject_bad_reg (Rm
);
10050 inst
.instruction
|= RdLo
<< 12;
10051 inst
.instruction
|= RdHi
<< 8;
10052 inst
.instruction
|= Rn
<< 16;
10053 inst
.instruction
|= Rm
;
10057 do_t_mov_cmp (void)
10061 Rn
= inst
.operands
[0].reg
;
10062 Rm
= inst
.operands
[1].reg
;
10065 set_it_insn_type_last ();
10067 if (unified_syntax
)
10069 int r0off
= (inst
.instruction
== T_MNEM_mov
10070 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10071 unsigned long opcode
;
10072 bfd_boolean narrow
;
10073 bfd_boolean low_regs
;
10075 low_regs
= (Rn
<= 7 && Rm
<= 7);
10076 opcode
= inst
.instruction
;
10077 if (in_it_block ())
10078 narrow
= opcode
!= T_MNEM_movs
;
10080 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10081 if (inst
.size_req
== 4
10082 || inst
.operands
[1].shifted
)
10085 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10086 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10087 && !inst
.operands
[1].shifted
10091 inst
.instruction
= T2_SUBS_PC_LR
;
10095 if (opcode
== T_MNEM_cmp
)
10097 constraint (Rn
== REG_PC
, BAD_PC
);
10100 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10102 warn_deprecated_sp (Rm
);
10103 /* R15 was documented as a valid choice for Rm in ARMv6,
10104 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10105 tools reject R15, so we do too. */
10106 constraint (Rm
== REG_PC
, BAD_PC
);
10109 reject_bad_reg (Rm
);
10111 else if (opcode
== T_MNEM_mov
10112 || opcode
== T_MNEM_movs
)
10114 if (inst
.operands
[1].isreg
)
10116 if (opcode
== T_MNEM_movs
)
10118 reject_bad_reg (Rn
);
10119 reject_bad_reg (Rm
);
10121 else if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10122 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10123 reject_bad_reg (Rm
);
10126 reject_bad_reg (Rn
);
10129 if (!inst
.operands
[1].isreg
)
10131 /* Immediate operand. */
10132 if (!in_it_block () && opcode
== T_MNEM_mov
)
10134 if (low_regs
&& narrow
)
10136 inst
.instruction
= THUMB_OP16 (opcode
);
10137 inst
.instruction
|= Rn
<< 8;
10138 if (inst
.size_req
== 2)
10139 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10141 inst
.relax
= opcode
;
10145 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10146 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10147 inst
.instruction
|= Rn
<< r0off
;
10148 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10151 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10152 && (inst
.instruction
== T_MNEM_mov
10153 || inst
.instruction
== T_MNEM_movs
))
10155 /* Register shifts are encoded as separate shift instructions. */
10156 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10158 if (in_it_block ())
10163 if (inst
.size_req
== 4)
10166 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10172 switch (inst
.operands
[1].shift_kind
)
10175 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10178 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10181 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10184 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10190 inst
.instruction
= opcode
;
10193 inst
.instruction
|= Rn
;
10194 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10199 inst
.instruction
|= CONDS_BIT
;
10201 inst
.instruction
|= Rn
<< 8;
10202 inst
.instruction
|= Rm
<< 16;
10203 inst
.instruction
|= inst
.operands
[1].imm
;
10208 /* Some mov with immediate shift have narrow variants.
10209 Register shifts are handled above. */
10210 if (low_regs
&& inst
.operands
[1].shifted
10211 && (inst
.instruction
== T_MNEM_mov
10212 || inst
.instruction
== T_MNEM_movs
))
10214 if (in_it_block ())
10215 narrow
= (inst
.instruction
== T_MNEM_mov
);
10217 narrow
= (inst
.instruction
== T_MNEM_movs
);
10222 switch (inst
.operands
[1].shift_kind
)
10224 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10225 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10226 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10227 default: narrow
= FALSE
; break;
10233 inst
.instruction
|= Rn
;
10234 inst
.instruction
|= Rm
<< 3;
10235 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10239 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10240 inst
.instruction
|= Rn
<< r0off
;
10241 encode_thumb32_shifted_operand (1);
10245 switch (inst
.instruction
)
10248 inst
.instruction
= T_OPCODE_MOV_HR
;
10249 inst
.instruction
|= (Rn
& 0x8) << 4;
10250 inst
.instruction
|= (Rn
& 0x7);
10251 inst
.instruction
|= Rm
<< 3;
10255 /* We know we have low registers at this point.
10256 Generate ADD Rd, Rs, #0. */
10257 inst
.instruction
= T_OPCODE_ADD_I3
;
10258 inst
.instruction
|= Rn
;
10259 inst
.instruction
|= Rm
<< 3;
10265 inst
.instruction
= T_OPCODE_CMP_LR
;
10266 inst
.instruction
|= Rn
;
10267 inst
.instruction
|= Rm
<< 3;
10271 inst
.instruction
= T_OPCODE_CMP_HR
;
10272 inst
.instruction
|= (Rn
& 0x8) << 4;
10273 inst
.instruction
|= (Rn
& 0x7);
10274 inst
.instruction
|= Rm
<< 3;
10281 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10283 /* PR 10443: Do not silently ignore shifted operands. */
10284 constraint (inst
.operands
[1].shifted
,
10285 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10287 if (inst
.operands
[1].isreg
)
10289 if (Rn
< 8 && Rm
< 8)
10291 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10292 since a MOV instruction produces unpredictable results. */
10293 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10294 inst
.instruction
= T_OPCODE_ADD_I3
;
10296 inst
.instruction
= T_OPCODE_CMP_LR
;
10298 inst
.instruction
|= Rn
;
10299 inst
.instruction
|= Rm
<< 3;
10303 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10304 inst
.instruction
= T_OPCODE_MOV_HR
;
10306 inst
.instruction
= T_OPCODE_CMP_HR
;
10312 constraint (Rn
> 7,
10313 _("only lo regs allowed with immediate"));
10314 inst
.instruction
|= Rn
<< 8;
10315 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10326 top
= (inst
.instruction
& 0x00800000) != 0;
10327 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
10329 constraint (top
, _(":lower16: not allowed this instruction"));
10330 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
10332 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
10334 constraint (!top
, _(":upper16: not allowed this instruction"));
10335 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
10338 Rd
= inst
.operands
[0].reg
;
10339 reject_bad_reg (Rd
);
10341 inst
.instruction
|= Rd
<< 8;
10342 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
10344 imm
= inst
.reloc
.exp
.X_add_number
;
10345 inst
.instruction
|= (imm
& 0xf000) << 4;
10346 inst
.instruction
|= (imm
& 0x0800) << 15;
10347 inst
.instruction
|= (imm
& 0x0700) << 4;
10348 inst
.instruction
|= (imm
& 0x00ff);
10353 do_t_mvn_tst (void)
10357 Rn
= inst
.operands
[0].reg
;
10358 Rm
= inst
.operands
[1].reg
;
10360 if (inst
.instruction
== T_MNEM_cmp
10361 || inst
.instruction
== T_MNEM_cmn
)
10362 constraint (Rn
== REG_PC
, BAD_PC
);
10364 reject_bad_reg (Rn
);
10365 reject_bad_reg (Rm
);
10367 if (unified_syntax
)
10369 int r0off
= (inst
.instruction
== T_MNEM_mvn
10370 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
10371 bfd_boolean narrow
;
10373 if (inst
.size_req
== 4
10374 || inst
.instruction
> 0xffff
10375 || inst
.operands
[1].shifted
10376 || Rn
> 7 || Rm
> 7)
10378 else if (inst
.instruction
== T_MNEM_cmn
)
10380 else if (THUMB_SETS_FLAGS (inst
.instruction
))
10381 narrow
= !in_it_block ();
10383 narrow
= in_it_block ();
10385 if (!inst
.operands
[1].isreg
)
10387 /* For an immediate, we always generate a 32-bit opcode;
10388 section relaxation will shrink it later if possible. */
10389 if (inst
.instruction
< 0xffff)
10390 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10391 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10392 inst
.instruction
|= Rn
<< r0off
;
10393 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10397 /* See if we can do this with a 16-bit instruction. */
10400 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10401 inst
.instruction
|= Rn
;
10402 inst
.instruction
|= Rm
<< 3;
10406 constraint (inst
.operands
[1].shifted
10407 && inst
.operands
[1].immisreg
,
10408 _("shift must be constant"));
10409 if (inst
.instruction
< 0xffff)
10410 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10411 inst
.instruction
|= Rn
<< r0off
;
10412 encode_thumb32_shifted_operand (1);
10418 constraint (inst
.instruction
> 0xffff
10419 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
10420 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
10421 _("unshifted register required"));
10422 constraint (Rn
> 7 || Rm
> 7,
10425 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10426 inst
.instruction
|= Rn
;
10427 inst
.instruction
|= Rm
<< 3;
10437 if (do_vfp_nsyn_mrs () == SUCCESS
)
10440 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
10443 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10444 _("selected processor does not support "
10445 "requested special purpose register"));
10449 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10450 _("selected processor does not support "
10451 "requested special purpose register"));
10452 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10453 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
10454 _("'CPSR' or 'SPSR' expected"));
10457 Rd
= inst
.operands
[0].reg
;
10458 reject_bad_reg (Rd
);
10460 inst
.instruction
|= Rd
<< 8;
10461 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10462 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
10471 if (do_vfp_nsyn_msr () == SUCCESS
)
10474 constraint (!inst
.operands
[1].isreg
,
10475 _("Thumb encoding does not support an immediate here"));
10476 flags
= inst
.operands
[0].imm
;
10479 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10480 _("selected processor does not support "
10481 "requested special purpose register"));
10485 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10486 _("selected processor does not support "
10487 "requested special purpose register"));
10491 Rn
= inst
.operands
[1].reg
;
10492 reject_bad_reg (Rn
);
10494 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10495 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
10496 inst
.instruction
|= (flags
& 0xff);
10497 inst
.instruction
|= Rn
<< 16;
10503 bfd_boolean narrow
;
10504 unsigned Rd
, Rn
, Rm
;
10506 if (!inst
.operands
[2].present
)
10507 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10509 Rd
= inst
.operands
[0].reg
;
10510 Rn
= inst
.operands
[1].reg
;
10511 Rm
= inst
.operands
[2].reg
;
10513 if (unified_syntax
)
10515 if (inst
.size_req
== 4
10521 else if (inst
.instruction
== T_MNEM_muls
)
10522 narrow
= !in_it_block ();
10524 narrow
= in_it_block ();
10528 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
10529 constraint (Rn
> 7 || Rm
> 7,
10536 /* 16-bit MULS/Conditional MUL. */
10537 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10538 inst
.instruction
|= Rd
;
10541 inst
.instruction
|= Rm
<< 3;
10543 inst
.instruction
|= Rn
<< 3;
10545 constraint (1, _("dest must overlap one source register"));
10549 constraint (inst
.instruction
!= T_MNEM_mul
,
10550 _("Thumb-2 MUL must not set flags"));
10552 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10553 inst
.instruction
|= Rd
<< 8;
10554 inst
.instruction
|= Rn
<< 16;
10555 inst
.instruction
|= Rm
<< 0;
10557 reject_bad_reg (Rd
);
10558 reject_bad_reg (Rn
);
10559 reject_bad_reg (Rm
);
10566 unsigned RdLo
, RdHi
, Rn
, Rm
;
10568 RdLo
= inst
.operands
[0].reg
;
10569 RdHi
= inst
.operands
[1].reg
;
10570 Rn
= inst
.operands
[2].reg
;
10571 Rm
= inst
.operands
[3].reg
;
10573 reject_bad_reg (RdLo
);
10574 reject_bad_reg (RdHi
);
10575 reject_bad_reg (Rn
);
10576 reject_bad_reg (Rm
);
10578 inst
.instruction
|= RdLo
<< 12;
10579 inst
.instruction
|= RdHi
<< 8;
10580 inst
.instruction
|= Rn
<< 16;
10581 inst
.instruction
|= Rm
;
10584 as_tsktsk (_("rdhi and rdlo must be different"));
10590 set_it_insn_type (NEUTRAL_IT_INSN
);
10592 if (unified_syntax
)
10594 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
10596 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10597 inst
.instruction
|= inst
.operands
[0].imm
;
10601 /* PR9722: Check for Thumb2 availability before
10602 generating a thumb2 nop instruction. */
10603 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
10605 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10606 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
10609 inst
.instruction
= 0x46c0;
10614 constraint (inst
.operands
[0].present
,
10615 _("Thumb does not support NOP with hints"));
10616 inst
.instruction
= 0x46c0;
10623 if (unified_syntax
)
10625 bfd_boolean narrow
;
10627 if (THUMB_SETS_FLAGS (inst
.instruction
))
10628 narrow
= !in_it_block ();
10630 narrow
= in_it_block ();
10631 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10633 if (inst
.size_req
== 4)
10638 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10639 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10640 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10644 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10645 inst
.instruction
|= inst
.operands
[0].reg
;
10646 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10651 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
10653 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10655 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10656 inst
.instruction
|= inst
.operands
[0].reg
;
10657 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10666 Rd
= inst
.operands
[0].reg
;
10667 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
10669 reject_bad_reg (Rd
);
10670 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
10671 reject_bad_reg (Rn
);
10673 inst
.instruction
|= Rd
<< 8;
10674 inst
.instruction
|= Rn
<< 16;
10676 if (!inst
.operands
[2].isreg
)
10678 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10679 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10685 Rm
= inst
.operands
[2].reg
;
10686 reject_bad_reg (Rm
);
10688 constraint (inst
.operands
[2].shifted
10689 && inst
.operands
[2].immisreg
,
10690 _("shift must be constant"));
10691 encode_thumb32_shifted_operand (2);
10698 unsigned Rd
, Rn
, Rm
;
10700 Rd
= inst
.operands
[0].reg
;
10701 Rn
= inst
.operands
[1].reg
;
10702 Rm
= inst
.operands
[2].reg
;
10704 reject_bad_reg (Rd
);
10705 reject_bad_reg (Rn
);
10706 reject_bad_reg (Rm
);
10708 inst
.instruction
|= Rd
<< 8;
10709 inst
.instruction
|= Rn
<< 16;
10710 inst
.instruction
|= Rm
;
10711 if (inst
.operands
[3].present
)
10713 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
10714 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10715 _("expression too complex"));
10716 inst
.instruction
|= (val
& 0x1c) << 10;
10717 inst
.instruction
|= (val
& 0x03) << 6;
10724 if (!inst
.operands
[3].present
)
10728 inst
.instruction
&= ~0x00000020;
10730 /* PR 10168. Swap the Rm and Rn registers. */
10731 Rtmp
= inst
.operands
[1].reg
;
10732 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
10733 inst
.operands
[2].reg
= Rtmp
;
10741 if (inst
.operands
[0].immisreg
)
10742 reject_bad_reg (inst
.operands
[0].imm
);
10744 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10748 do_t_push_pop (void)
10752 constraint (inst
.operands
[0].writeback
,
10753 _("push/pop do not support {reglist}^"));
10754 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10755 _("expression too complex"));
10757 mask
= inst
.operands
[0].imm
;
10758 if ((mask
& ~0xff) == 0)
10759 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
10760 else if ((inst
.instruction
== T_MNEM_push
10761 && (mask
& ~0xff) == 1 << REG_LR
)
10762 || (inst
.instruction
== T_MNEM_pop
10763 && (mask
& ~0xff) == 1 << REG_PC
))
10765 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10766 inst
.instruction
|= THUMB_PP_PC_LR
;
10767 inst
.instruction
|= mask
& 0xff;
10769 else if (unified_syntax
)
10771 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10772 encode_thumb2_ldmstm (13, mask
, TRUE
);
10776 inst
.error
= _("invalid register list to push/pop instruction");
10786 Rd
= inst
.operands
[0].reg
;
10787 Rm
= inst
.operands
[1].reg
;
10789 reject_bad_reg (Rd
);
10790 reject_bad_reg (Rm
);
10792 inst
.instruction
|= Rd
<< 8;
10793 inst
.instruction
|= Rm
<< 16;
10794 inst
.instruction
|= Rm
;
10802 Rd
= inst
.operands
[0].reg
;
10803 Rm
= inst
.operands
[1].reg
;
10805 reject_bad_reg (Rd
);
10806 reject_bad_reg (Rm
);
10808 if (Rd
<= 7 && Rm
<= 7
10809 && inst
.size_req
!= 4)
10811 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10812 inst
.instruction
|= Rd
;
10813 inst
.instruction
|= Rm
<< 3;
10815 else if (unified_syntax
)
10817 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10818 inst
.instruction
|= Rd
<< 8;
10819 inst
.instruction
|= Rm
<< 16;
10820 inst
.instruction
|= Rm
;
10823 inst
.error
= BAD_HIREG
;
10831 Rd
= inst
.operands
[0].reg
;
10832 Rm
= inst
.operands
[1].reg
;
10834 reject_bad_reg (Rd
);
10835 reject_bad_reg (Rm
);
10837 inst
.instruction
|= Rd
<< 8;
10838 inst
.instruction
|= Rm
;
10846 Rd
= inst
.operands
[0].reg
;
10847 Rs
= (inst
.operands
[1].present
10848 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10849 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10851 reject_bad_reg (Rd
);
10852 reject_bad_reg (Rs
);
10853 if (inst
.operands
[2].isreg
)
10854 reject_bad_reg (inst
.operands
[2].reg
);
10856 inst
.instruction
|= Rd
<< 8;
10857 inst
.instruction
|= Rs
<< 16;
10858 if (!inst
.operands
[2].isreg
)
10860 bfd_boolean narrow
;
10862 if ((inst
.instruction
& 0x00100000) != 0)
10863 narrow
= !in_it_block ();
10865 narrow
= in_it_block ();
10867 if (Rd
> 7 || Rs
> 7)
10870 if (inst
.size_req
== 4 || !unified_syntax
)
10873 if (inst
.reloc
.exp
.X_op
!= O_constant
10874 || inst
.reloc
.exp
.X_add_number
!= 0)
10877 /* Turn rsb #0 into 16-bit neg. We should probably do this via
10878 relaxation, but it doesn't seem worth the hassle. */
10881 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10882 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
10883 inst
.instruction
|= Rs
<< 3;
10884 inst
.instruction
|= Rd
;
10888 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10889 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10893 encode_thumb32_shifted_operand (2);
10899 set_it_insn_type (OUTSIDE_IT_INSN
);
10900 if (inst
.operands
[0].imm
)
10901 inst
.instruction
|= 0x8;
10907 if (!inst
.operands
[1].present
)
10908 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
10910 if (unified_syntax
)
10912 bfd_boolean narrow
;
10915 switch (inst
.instruction
)
10918 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
10920 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
10922 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
10924 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
10928 if (THUMB_SETS_FLAGS (inst
.instruction
))
10929 narrow
= !in_it_block ();
10931 narrow
= in_it_block ();
10932 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10934 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
10936 if (inst
.operands
[2].isreg
10937 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
10938 || inst
.operands
[2].reg
> 7))
10940 if (inst
.size_req
== 4)
10943 reject_bad_reg (inst
.operands
[0].reg
);
10944 reject_bad_reg (inst
.operands
[1].reg
);
10948 if (inst
.operands
[2].isreg
)
10950 reject_bad_reg (inst
.operands
[2].reg
);
10951 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10952 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10953 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10954 inst
.instruction
|= inst
.operands
[2].reg
;
10958 inst
.operands
[1].shifted
= 1;
10959 inst
.operands
[1].shift_kind
= shift_kind
;
10960 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
10961 ? T_MNEM_movs
: T_MNEM_mov
);
10962 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10963 encode_thumb32_shifted_operand (1);
10964 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
10965 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10970 if (inst
.operands
[2].isreg
)
10972 switch (shift_kind
)
10974 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10975 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10976 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10977 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10981 inst
.instruction
|= inst
.operands
[0].reg
;
10982 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10986 switch (shift_kind
)
10988 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10989 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10990 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10993 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10994 inst
.instruction
|= inst
.operands
[0].reg
;
10995 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11001 constraint (inst
.operands
[0].reg
> 7
11002 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11003 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11005 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11007 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11008 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11009 _("source1 and dest must be same register"));
11011 switch (inst
.instruction
)
11013 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11014 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11015 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11016 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11020 inst
.instruction
|= inst
.operands
[0].reg
;
11021 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11025 switch (inst
.instruction
)
11027 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11028 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11029 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11030 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11033 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11034 inst
.instruction
|= inst
.operands
[0].reg
;
11035 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11043 unsigned Rd
, Rn
, Rm
;
11045 Rd
= inst
.operands
[0].reg
;
11046 Rn
= inst
.operands
[1].reg
;
11047 Rm
= inst
.operands
[2].reg
;
11049 reject_bad_reg (Rd
);
11050 reject_bad_reg (Rn
);
11051 reject_bad_reg (Rm
);
11053 inst
.instruction
|= Rd
<< 8;
11054 inst
.instruction
|= Rn
<< 16;
11055 inst
.instruction
|= Rm
;
11061 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11062 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11063 _("expression too complex"));
11064 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11065 inst
.instruction
|= (value
& 0xf000) >> 12;
11066 inst
.instruction
|= (value
& 0x0ff0);
11067 inst
.instruction
|= (value
& 0x000f) << 16;
11071 do_t_ssat_usat (int bias
)
11075 Rd
= inst
.operands
[0].reg
;
11076 Rn
= inst
.operands
[2].reg
;
11078 reject_bad_reg (Rd
);
11079 reject_bad_reg (Rn
);
11081 inst
.instruction
|= Rd
<< 8;
11082 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
11083 inst
.instruction
|= Rn
<< 16;
11085 if (inst
.operands
[3].present
)
11087 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
11089 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11091 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11092 _("expression too complex"));
11094 if (shift_amount
!= 0)
11096 constraint (shift_amount
> 31,
11097 _("shift expression is too large"));
11099 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
11100 inst
.instruction
|= 0x00200000; /* sh bit. */
11102 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
11103 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11111 do_t_ssat_usat (1);
11119 Rd
= inst
.operands
[0].reg
;
11120 Rn
= inst
.operands
[2].reg
;
11122 reject_bad_reg (Rd
);
11123 reject_bad_reg (Rn
);
11125 inst
.instruction
|= Rd
<< 8;
11126 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11127 inst
.instruction
|= Rn
<< 16;
11133 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11134 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11135 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11136 || inst
.operands
[2].negative
,
11139 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11140 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11141 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11142 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11148 if (!inst
.operands
[2].present
)
11149 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11151 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11152 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11153 || inst
.operands
[0].reg
== inst
.operands
[3].reg
11154 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
11157 inst
.instruction
|= inst
.operands
[0].reg
;
11158 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11159 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11160 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11166 unsigned Rd
, Rn
, Rm
;
11168 Rd
= inst
.operands
[0].reg
;
11169 Rn
= inst
.operands
[1].reg
;
11170 Rm
= inst
.operands
[2].reg
;
11172 reject_bad_reg (Rd
);
11173 reject_bad_reg (Rn
);
11174 reject_bad_reg (Rm
);
11176 inst
.instruction
|= Rd
<< 8;
11177 inst
.instruction
|= Rn
<< 16;
11178 inst
.instruction
|= Rm
;
11179 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11187 Rd
= inst
.operands
[0].reg
;
11188 Rm
= inst
.operands
[1].reg
;
11190 reject_bad_reg (Rd
);
11191 reject_bad_reg (Rm
);
11193 if (inst
.instruction
<= 0xffff
11194 && inst
.size_req
!= 4
11195 && Rd
<= 7 && Rm
<= 7
11196 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11198 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11199 inst
.instruction
|= Rd
;
11200 inst
.instruction
|= Rm
<< 3;
11202 else if (unified_syntax
)
11204 if (inst
.instruction
<= 0xffff)
11205 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11206 inst
.instruction
|= Rd
<< 8;
11207 inst
.instruction
|= Rm
;
11208 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11212 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11213 _("Thumb encoding does not support rotation"));
11214 constraint (1, BAD_HIREG
);
11221 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11230 half
= (inst
.instruction
& 0x10) != 0;
11231 set_it_insn_type_last ();
11232 constraint (inst
.operands
[0].immisreg
,
11233 _("instruction requires register index"));
11235 Rn
= inst
.operands
[0].reg
;
11236 Rm
= inst
.operands
[0].imm
;
11238 constraint (Rn
== REG_SP
, BAD_SP
);
11239 reject_bad_reg (Rm
);
11241 constraint (!half
&& inst
.operands
[0].shifted
,
11242 _("instruction does not allow shifted index"));
11243 inst
.instruction
|= (Rn
<< 16) | Rm
;
11249 do_t_ssat_usat (0);
11257 Rd
= inst
.operands
[0].reg
;
11258 Rn
= inst
.operands
[2].reg
;
11260 reject_bad_reg (Rd
);
11261 reject_bad_reg (Rn
);
11263 inst
.instruction
|= Rd
<< 8;
11264 inst
.instruction
|= inst
.operands
[1].imm
;
11265 inst
.instruction
|= Rn
<< 16;
11268 /* Neon instruction encoder helpers. */
11270 /* Encodings for the different types for various Neon opcodes. */
11272 /* An "invalid" code for the following tables. */
11275 struct neon_tab_entry
11278 unsigned float_or_poly
;
11279 unsigned scalar_or_imm
;
11282 /* Map overloaded Neon opcodes to their respective encodings. */
11283 #define NEON_ENC_TAB \
11284 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11285 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11286 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11287 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11288 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11289 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11290 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11291 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11292 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11293 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11294 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11295 /* Register variants of the following two instructions are encoded as
11296 vcge / vcgt with the operands reversed. */ \
11297 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11298 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11299 X(vfma, N_INV, 0x0000c10, N_INV), \
11300 X(vfms, N_INV, 0x0200c10, N_INV), \
11301 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11302 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11303 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11304 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11305 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11306 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11307 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11308 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11309 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11310 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11311 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11312 X(vshl, 0x0000400, N_INV, 0x0800510), \
11313 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11314 X(vand, 0x0000110, N_INV, 0x0800030), \
11315 X(vbic, 0x0100110, N_INV, 0x0800030), \
11316 X(veor, 0x1000110, N_INV, N_INV), \
11317 X(vorn, 0x0300110, N_INV, 0x0800010), \
11318 X(vorr, 0x0200110, N_INV, 0x0800010), \
11319 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11320 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11321 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11322 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11323 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11324 X(vst1, 0x0000000, 0x0800000, N_INV), \
11325 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11326 X(vst2, 0x0000100, 0x0800100, N_INV), \
11327 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11328 X(vst3, 0x0000200, 0x0800200, N_INV), \
11329 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11330 X(vst4, 0x0000300, 0x0800300, N_INV), \
11331 X(vmovn, 0x1b20200, N_INV, N_INV), \
11332 X(vtrn, 0x1b20080, N_INV, N_INV), \
11333 X(vqmovn, 0x1b20200, N_INV, N_INV), \
11334 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11335 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
11336 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
11337 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
11338 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
11339 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
11340 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11341 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
11342 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
11343 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
11347 #define X(OPC,I,F,S) N_MNEM_##OPC
11352 static const struct neon_tab_entry neon_enc_tab
[] =
11354 #define X(OPC,I,F,S) { (I), (F), (S) }
11359 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11360 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11361 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11362 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11363 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11364 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11365 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11366 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11367 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11368 #define NEON_ENC_SINGLE(X) \
11369 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
11370 #define NEON_ENC_DOUBLE(X) \
11371 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
11373 /* Define shapes for instruction operands. The following mnemonic characters
11374 are used in this table:
11376 F - VFP S<n> register
11377 D - Neon D<n> register
11378 Q - Neon Q<n> register
11382 L - D<n> register list
11384 This table is used to generate various data:
11385 - enumerations of the form NS_DDR to be used as arguments to
11387 - a table classifying shapes into single, double, quad, mixed.
11388 - a table used to drive neon_select_shape. */
11390 #define NEON_SHAPE_DEF \
11391 X(3, (D, D, D), DOUBLE), \
11392 X(3, (Q, Q, Q), QUAD), \
11393 X(3, (D, D, I), DOUBLE), \
11394 X(3, (Q, Q, I), QUAD), \
11395 X(3, (D, D, S), DOUBLE), \
11396 X(3, (Q, Q, S), QUAD), \
11397 X(2, (D, D), DOUBLE), \
11398 X(2, (Q, Q), QUAD), \
11399 X(2, (D, S), DOUBLE), \
11400 X(2, (Q, S), QUAD), \
11401 X(2, (D, R), DOUBLE), \
11402 X(2, (Q, R), QUAD), \
11403 X(2, (D, I), DOUBLE), \
11404 X(2, (Q, I), QUAD), \
11405 X(3, (D, L, D), DOUBLE), \
11406 X(2, (D, Q), MIXED), \
11407 X(2, (Q, D), MIXED), \
11408 X(3, (D, Q, I), MIXED), \
11409 X(3, (Q, D, I), MIXED), \
11410 X(3, (Q, D, D), MIXED), \
11411 X(3, (D, Q, Q), MIXED), \
11412 X(3, (Q, Q, D), MIXED), \
11413 X(3, (Q, D, S), MIXED), \
11414 X(3, (D, Q, S), MIXED), \
11415 X(4, (D, D, D, I), DOUBLE), \
11416 X(4, (Q, Q, Q, I), QUAD), \
11417 X(2, (F, F), SINGLE), \
11418 X(3, (F, F, F), SINGLE), \
11419 X(2, (F, I), SINGLE), \
11420 X(2, (F, D), MIXED), \
11421 X(2, (D, F), MIXED), \
11422 X(3, (F, F, I), MIXED), \
11423 X(4, (R, R, F, F), SINGLE), \
11424 X(4, (F, F, R, R), SINGLE), \
11425 X(3, (D, R, R), DOUBLE), \
11426 X(3, (R, R, D), DOUBLE), \
11427 X(2, (S, R), SINGLE), \
11428 X(2, (R, S), SINGLE), \
11429 X(2, (F, R), SINGLE), \
11430 X(2, (R, F), SINGLE)
11432 #define S2(A,B) NS_##A##B
11433 #define S3(A,B,C) NS_##A##B##C
11434 #define S4(A,B,C,D) NS_##A##B##C##D
11436 #define X(N, L, C) S##N L
11449 enum neon_shape_class
11457 #define X(N, L, C) SC_##C
11459 static enum neon_shape_class neon_shape_class
[] =
11477 /* Register widths of above. */
11478 static unsigned neon_shape_el_size
[] =
11489 struct neon_shape_info
11492 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
11495 #define S2(A,B) { SE_##A, SE_##B }
11496 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
11497 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
11499 #define X(N, L, C) { N, S##N L }
11501 static struct neon_shape_info neon_shape_tab
[] =
11511 /* Bit masks used in type checking given instructions.
11512 'N_EQK' means the type must be the same as (or based on in some way) the key
11513 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
11514 set, various other bits can be set as well in order to modify the meaning of
11515 the type constraint. */
11517 enum neon_type_mask
11540 N_KEY
= 0x1000000, /* Key element (main type specifier). */
11541 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
11542 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
11543 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
11544 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
11545 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
11546 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
11547 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
11548 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
11549 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
11551 N_MAX_NONSPECIAL
= N_F64
11554 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
11556 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
11557 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
11558 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
11559 #define N_SUF_32 (N_SU_32 | N_F32)
11560 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
11561 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
11563 /* Pass this as the first type argument to neon_check_type to ignore types
11565 #define N_IGNORE_TYPE (N_KEY | N_EQK)
11567 /* Select a "shape" for the current instruction (describing register types or
11568 sizes) from a list of alternatives. Return NS_NULL if the current instruction
11569 doesn't fit. For non-polymorphic shapes, checking is usually done as a
11570 function of operand parsing, so this function doesn't need to be called.
11571 Shapes should be listed in order of decreasing length. */
11573 static enum neon_shape
11574 neon_select_shape (enum neon_shape shape
, ...)
11577 enum neon_shape first_shape
= shape
;
11579 /* Fix missing optional operands. FIXME: we don't know at this point how
11580 many arguments we should have, so this makes the assumption that we have
11581 > 1. This is true of all current Neon opcodes, I think, but may not be
11582 true in the future. */
11583 if (!inst
.operands
[1].present
)
11584 inst
.operands
[1] = inst
.operands
[0];
11586 va_start (ap
, shape
);
11588 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
11593 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
11595 if (!inst
.operands
[j
].present
)
11601 switch (neon_shape_tab
[shape
].el
[j
])
11604 if (!(inst
.operands
[j
].isreg
11605 && inst
.operands
[j
].isvec
11606 && inst
.operands
[j
].issingle
11607 && !inst
.operands
[j
].isquad
))
11612 if (!(inst
.operands
[j
].isreg
11613 && inst
.operands
[j
].isvec
11614 && !inst
.operands
[j
].isquad
11615 && !inst
.operands
[j
].issingle
))
11620 if (!(inst
.operands
[j
].isreg
11621 && !inst
.operands
[j
].isvec
))
11626 if (!(inst
.operands
[j
].isreg
11627 && inst
.operands
[j
].isvec
11628 && inst
.operands
[j
].isquad
11629 && !inst
.operands
[j
].issingle
))
11634 if (!(!inst
.operands
[j
].isreg
11635 && !inst
.operands
[j
].isscalar
))
11640 if (!(!inst
.operands
[j
].isreg
11641 && inst
.operands
[j
].isscalar
))
11655 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
11656 first_error (_("invalid instruction shape"));
11661 /* True if SHAPE is predominantly a quadword operation (most of the time, this
11662 means the Q bit should be set). */
11665 neon_quad (enum neon_shape shape
)
11667 return neon_shape_class
[shape
] == SC_QUAD
;
11671 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
11674 /* Allow modification to be made to types which are constrained to be
11675 based on the key element, based on bits set alongside N_EQK. */
11676 if ((typebits
& N_EQK
) != 0)
11678 if ((typebits
& N_HLF
) != 0)
11680 else if ((typebits
& N_DBL
) != 0)
11682 if ((typebits
& N_SGN
) != 0)
11683 *g_type
= NT_signed
;
11684 else if ((typebits
& N_UNS
) != 0)
11685 *g_type
= NT_unsigned
;
11686 else if ((typebits
& N_INT
) != 0)
11687 *g_type
= NT_integer
;
11688 else if ((typebits
& N_FLT
) != 0)
11689 *g_type
= NT_float
;
11690 else if ((typebits
& N_SIZ
) != 0)
11691 *g_type
= NT_untyped
;
11695 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
11696 operand type, i.e. the single type specified in a Neon instruction when it
11697 is the only one given. */
11699 static struct neon_type_el
11700 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
11702 struct neon_type_el dest
= *key
;
11704 gas_assert ((thisarg
& N_EQK
) != 0);
11706 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
11711 /* Convert Neon type and size into compact bitmask representation. */
11713 static enum neon_type_mask
11714 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
11721 case 8: return N_8
;
11722 case 16: return N_16
;
11723 case 32: return N_32
;
11724 case 64: return N_64
;
11732 case 8: return N_I8
;
11733 case 16: return N_I16
;
11734 case 32: return N_I32
;
11735 case 64: return N_I64
;
11743 case 16: return N_F16
;
11744 case 32: return N_F32
;
11745 case 64: return N_F64
;
11753 case 8: return N_P8
;
11754 case 16: return N_P16
;
11762 case 8: return N_S8
;
11763 case 16: return N_S16
;
11764 case 32: return N_S32
;
11765 case 64: return N_S64
;
11773 case 8: return N_U8
;
11774 case 16: return N_U16
;
11775 case 32: return N_U32
;
11776 case 64: return N_U64
;
11787 /* Convert compact Neon bitmask type representation to a type and size. Only
11788 handles the case where a single bit is set in the mask. */
11791 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
11792 enum neon_type_mask mask
)
11794 if ((mask
& N_EQK
) != 0)
11797 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
11799 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
11801 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
11803 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
11808 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
11810 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
11811 *type
= NT_unsigned
;
11812 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
11813 *type
= NT_integer
;
11814 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
11815 *type
= NT_untyped
;
11816 else if ((mask
& (N_P8
| N_P16
)) != 0)
11818 else if ((mask
& (N_F32
| N_F64
)) != 0)
11826 /* Modify a bitmask of allowed types. This is only needed for type
11830 modify_types_allowed (unsigned allowed
, unsigned mods
)
11833 enum neon_el_type type
;
11839 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
11841 if (el_type_of_type_chk (&type
, &size
,
11842 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
11844 neon_modify_type_size (mods
, &type
, &size
);
11845 destmask
|= type_chk_of_el_type (type
, size
);
11852 /* Check type and return type classification.
11853 The manual states (paraphrase): If one datatype is given, it indicates the
11855 - the second operand, if there is one
11856 - the operand, if there is no second operand
11857 - the result, if there are no operands.
11858 This isn't quite good enough though, so we use a concept of a "key" datatype
11859 which is set on a per-instruction basis, which is the one which matters when
11860 only one data type is written.
11861 Note: this function has side-effects (e.g. filling in missing operands). All
11862 Neon instructions should call it before performing bit encoding. */
11864 static struct neon_type_el
11865 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
11868 unsigned i
, pass
, key_el
= 0;
11869 unsigned types
[NEON_MAX_TYPE_ELS
];
11870 enum neon_el_type k_type
= NT_invtype
;
11871 unsigned k_size
= -1u;
11872 struct neon_type_el badtype
= {NT_invtype
, -1};
11873 unsigned key_allowed
= 0;
11875 /* Optional registers in Neon instructions are always (not) in operand 1.
11876 Fill in the missing operand here, if it was omitted. */
11877 if (els
> 1 && !inst
.operands
[1].present
)
11878 inst
.operands
[1] = inst
.operands
[0];
11880 /* Suck up all the varargs. */
11882 for (i
= 0; i
< els
; i
++)
11884 unsigned thisarg
= va_arg (ap
, unsigned);
11885 if (thisarg
== N_IGNORE_TYPE
)
11890 types
[i
] = thisarg
;
11891 if ((thisarg
& N_KEY
) != 0)
11896 if (inst
.vectype
.elems
> 0)
11897 for (i
= 0; i
< els
; i
++)
11898 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
11900 first_error (_("types specified in both the mnemonic and operands"));
11904 /* Duplicate inst.vectype elements here as necessary.
11905 FIXME: No idea if this is exactly the same as the ARM assembler,
11906 particularly when an insn takes one register and one non-register
11908 if (inst
.vectype
.elems
== 1 && els
> 1)
11911 inst
.vectype
.elems
= els
;
11912 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
11913 for (j
= 0; j
< els
; j
++)
11915 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11918 else if (inst
.vectype
.elems
== 0 && els
> 0)
11921 /* No types were given after the mnemonic, so look for types specified
11922 after each operand. We allow some flexibility here; as long as the
11923 "key" operand has a type, we can infer the others. */
11924 for (j
= 0; j
< els
; j
++)
11925 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
11926 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
11928 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
11930 for (j
= 0; j
< els
; j
++)
11931 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
11932 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11937 first_error (_("operand types can't be inferred"));
11941 else if (inst
.vectype
.elems
!= els
)
11943 first_error (_("type specifier has the wrong number of parts"));
11947 for (pass
= 0; pass
< 2; pass
++)
11949 for (i
= 0; i
< els
; i
++)
11951 unsigned thisarg
= types
[i
];
11952 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
11953 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
11954 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
11955 unsigned g_size
= inst
.vectype
.el
[i
].size
;
11957 /* Decay more-specific signed & unsigned types to sign-insensitive
11958 integer types if sign-specific variants are unavailable. */
11959 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
11960 && (types_allowed
& N_SU_ALL
) == 0)
11961 g_type
= NT_integer
;
11963 /* If only untyped args are allowed, decay any more specific types to
11964 them. Some instructions only care about signs for some element
11965 sizes, so handle that properly. */
11966 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
11967 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
11968 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
11969 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
11970 g_type
= NT_untyped
;
11974 if ((thisarg
& N_KEY
) != 0)
11978 key_allowed
= thisarg
& ~N_KEY
;
11983 if ((thisarg
& N_VFP
) != 0)
11985 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
11986 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
11988 /* In VFP mode, operands must match register widths. If we
11989 have a key operand, use its width, else use the width of
11990 the current operand. */
11996 if (regwidth
!= match
)
11998 first_error (_("operand size must match register width"));
12003 if ((thisarg
& N_EQK
) == 0)
12005 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
12007 if ((given_type
& types_allowed
) == 0)
12009 first_error (_("bad type in Neon instruction"));
12015 enum neon_el_type mod_k_type
= k_type
;
12016 unsigned mod_k_size
= k_size
;
12017 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
12018 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
12020 first_error (_("inconsistent types in Neon instruction"));
12028 return inst
.vectype
.el
[key_el
];
12031 /* Neon-style VFP instruction forwarding. */
12033 /* Thumb VFP instructions have 0xE in the condition field. */
12036 do_vfp_cond_or_thumb (void)
12039 inst
.instruction
|= 0xe0000000;
12041 inst
.instruction
|= inst
.cond
<< 28;
12044 /* Look up and encode a simple mnemonic, for use as a helper function for the
12045 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12046 etc. It is assumed that operand parsing has already been done, and that the
12047 operands are in the form expected by the given opcode (this isn't necessarily
12048 the same as the form in which they were parsed, hence some massaging must
12049 take place before this function is called).
12050 Checks current arch version against that in the looked-up opcode. */
12053 do_vfp_nsyn_opcode (const char *opname
)
12055 const struct asm_opcode
*opcode
;
12057 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
12062 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
12063 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
12068 inst
.instruction
= opcode
->tvalue
;
12069 opcode
->tencode ();
12073 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
12074 opcode
->aencode ();
12079 do_vfp_nsyn_add_sub (enum neon_shape rs
)
12081 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
12086 do_vfp_nsyn_opcode ("fadds");
12088 do_vfp_nsyn_opcode ("fsubs");
12093 do_vfp_nsyn_opcode ("faddd");
12095 do_vfp_nsyn_opcode ("fsubd");
12099 /* Check operand types to see if this is a VFP instruction, and if so call
12103 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
12105 enum neon_shape rs
;
12106 struct neon_type_el et
;
12111 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12112 et
= neon_check_type (2, rs
,
12113 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12117 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12118 et
= neon_check_type (3, rs
,
12119 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12126 if (et
.type
!= NT_invtype
)
12138 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12140 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12145 do_vfp_nsyn_opcode ("fmacs");
12147 do_vfp_nsyn_opcode ("fnmacs");
12152 do_vfp_nsyn_opcode ("fmacd");
12154 do_vfp_nsyn_opcode ("fnmacd");
12159 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
12161 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
12166 do_vfp_nsyn_opcode ("ffmas");
12168 do_vfp_nsyn_opcode ("ffnmas");
12173 do_vfp_nsyn_opcode ("ffmad");
12175 do_vfp_nsyn_opcode ("ffnmad");
12180 do_vfp_nsyn_mul (enum neon_shape rs
)
12183 do_vfp_nsyn_opcode ("fmuls");
12185 do_vfp_nsyn_opcode ("fmuld");
12189 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12191 int is_neg
= (inst
.instruction
& 0x80) != 0;
12192 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12197 do_vfp_nsyn_opcode ("fnegs");
12199 do_vfp_nsyn_opcode ("fabss");
12204 do_vfp_nsyn_opcode ("fnegd");
12206 do_vfp_nsyn_opcode ("fabsd");
12210 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12211 insns belong to Neon, and are handled elsewhere. */
12214 do_vfp_nsyn_ldm_stm (int is_dbmode
)
12216 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
12220 do_vfp_nsyn_opcode ("fldmdbs");
12222 do_vfp_nsyn_opcode ("fldmias");
12227 do_vfp_nsyn_opcode ("fstmdbs");
12229 do_vfp_nsyn_opcode ("fstmias");
12234 do_vfp_nsyn_sqrt (void)
12236 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12237 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12240 do_vfp_nsyn_opcode ("fsqrts");
12242 do_vfp_nsyn_opcode ("fsqrtd");
12246 do_vfp_nsyn_div (void)
12248 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12249 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12250 N_F32
| N_F64
| N_KEY
| N_VFP
);
12253 do_vfp_nsyn_opcode ("fdivs");
12255 do_vfp_nsyn_opcode ("fdivd");
12259 do_vfp_nsyn_nmul (void)
12261 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12262 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12263 N_F32
| N_F64
| N_KEY
| N_VFP
);
12267 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
12268 do_vfp_sp_dyadic ();
12272 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
12273 do_vfp_dp_rd_rn_rm ();
12275 do_vfp_cond_or_thumb ();
12279 do_vfp_nsyn_cmp (void)
12281 if (inst
.operands
[1].isreg
)
12283 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12284 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12288 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
12289 do_vfp_sp_monadic ();
12293 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
12294 do_vfp_dp_rd_rm ();
12299 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
12300 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
12302 switch (inst
.instruction
& 0x0fffffff)
12305 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
12308 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
12316 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
12317 do_vfp_sp_compare_z ();
12321 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
12325 do_vfp_cond_or_thumb ();
12329 nsyn_insert_sp (void)
12331 inst
.operands
[1] = inst
.operands
[0];
12332 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
12333 inst
.operands
[0].reg
= REG_SP
;
12334 inst
.operands
[0].isreg
= 1;
12335 inst
.operands
[0].writeback
= 1;
12336 inst
.operands
[0].present
= 1;
12340 do_vfp_nsyn_push (void)
12343 if (inst
.operands
[1].issingle
)
12344 do_vfp_nsyn_opcode ("fstmdbs");
12346 do_vfp_nsyn_opcode ("fstmdbd");
12350 do_vfp_nsyn_pop (void)
12353 if (inst
.operands
[1].issingle
)
12354 do_vfp_nsyn_opcode ("fldmias");
12356 do_vfp_nsyn_opcode ("fldmiad");
12359 /* Fix up Neon data-processing instructions, ORing in the correct bits for
12360 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
12363 neon_dp_fixup (unsigned i
)
12367 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
12381 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
12385 neon_logbits (unsigned x
)
12387 return ffs (x
) - 4;
12390 #define LOW4(R) ((R) & 0xf)
12391 #define HI1(R) (((R) >> 4) & 1)
12393 /* Encode insns with bit pattern:
12395 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12396 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
12398 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
12399 different meaning for some instruction. */
12402 neon_three_same (int isquad
, int ubit
, int size
)
12404 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12405 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12406 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12407 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12408 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12409 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12410 inst
.instruction
|= (isquad
!= 0) << 6;
12411 inst
.instruction
|= (ubit
!= 0) << 24;
12413 inst
.instruction
|= neon_logbits (size
) << 20;
12415 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12418 /* Encode instructions of the form:
12420 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
12421 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
12423 Don't write size if SIZE == -1. */
12426 neon_two_same (int qbit
, int ubit
, int size
)
12428 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12429 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12430 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12431 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12432 inst
.instruction
|= (qbit
!= 0) << 6;
12433 inst
.instruction
|= (ubit
!= 0) << 24;
12436 inst
.instruction
|= neon_logbits (size
) << 18;
12438 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12441 /* Neon instruction encoders, in approximate order of appearance. */
12444 do_neon_dyadic_i_su (void)
12446 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12447 struct neon_type_el et
= neon_check_type (3, rs
,
12448 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
12449 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12453 do_neon_dyadic_i64_su (void)
12455 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12456 struct neon_type_el et
= neon_check_type (3, rs
,
12457 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12458 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12462 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
12465 unsigned size
= et
.size
>> 3;
12466 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12467 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12468 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12469 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12470 inst
.instruction
|= (isquad
!= 0) << 6;
12471 inst
.instruction
|= immbits
<< 16;
12472 inst
.instruction
|= (size
>> 3) << 7;
12473 inst
.instruction
|= (size
& 0x7) << 19;
12475 inst
.instruction
|= (uval
!= 0) << 24;
12477 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12481 do_neon_shl_imm (void)
12483 if (!inst
.operands
[2].isreg
)
12485 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12486 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
12487 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12488 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
12492 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12493 struct neon_type_el et
= neon_check_type (3, rs
,
12494 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12497 /* VSHL/VQSHL 3-register variants have syntax such as:
12499 whereas other 3-register operations encoded by neon_three_same have
12502 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
12504 tmp
= inst
.operands
[2].reg
;
12505 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12506 inst
.operands
[1].reg
= tmp
;
12507 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12508 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12513 do_neon_qshl_imm (void)
12515 if (!inst
.operands
[2].isreg
)
12517 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12518 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12520 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12521 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12522 inst
.operands
[2].imm
);
12526 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12527 struct neon_type_el et
= neon_check_type (3, rs
,
12528 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12531 /* See note in do_neon_shl_imm. */
12532 tmp
= inst
.operands
[2].reg
;
12533 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12534 inst
.operands
[1].reg
= tmp
;
12535 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12536 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12541 do_neon_rshl (void)
12543 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12544 struct neon_type_el et
= neon_check_type (3, rs
,
12545 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12548 tmp
= inst
.operands
[2].reg
;
12549 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12550 inst
.operands
[1].reg
= tmp
;
12551 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12555 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
12557 /* Handle .I8 pseudo-instructions. */
12560 /* Unfortunately, this will make everything apart from zero out-of-range.
12561 FIXME is this the intended semantics? There doesn't seem much point in
12562 accepting .I8 if so. */
12563 immediate
|= immediate
<< 8;
12569 if (immediate
== (immediate
& 0x000000ff))
12571 *immbits
= immediate
;
12574 else if (immediate
== (immediate
& 0x0000ff00))
12576 *immbits
= immediate
>> 8;
12579 else if (immediate
== (immediate
& 0x00ff0000))
12581 *immbits
= immediate
>> 16;
12584 else if (immediate
== (immediate
& 0xff000000))
12586 *immbits
= immediate
>> 24;
12589 if ((immediate
& 0xffff) != (immediate
>> 16))
12590 goto bad_immediate
;
12591 immediate
&= 0xffff;
12594 if (immediate
== (immediate
& 0x000000ff))
12596 *immbits
= immediate
;
12599 else if (immediate
== (immediate
& 0x0000ff00))
12601 *immbits
= immediate
>> 8;
12606 first_error (_("immediate value out of range"));
12610 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
12614 neon_bits_same_in_bytes (unsigned imm
)
12616 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
12617 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
12618 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
12619 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
12622 /* For immediate of above form, return 0bABCD. */
12625 neon_squash_bits (unsigned imm
)
12627 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
12628 | ((imm
& 0x01000000) >> 21);
12631 /* Compress quarter-float representation to 0b...000 abcdefgh. */
12634 neon_qfloat_bits (unsigned imm
)
12636 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
12639 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
12640 the instruction. *OP is passed as the initial value of the op field, and
12641 may be set to a different value depending on the constant (i.e.
12642 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
12643 MVN). If the immediate looks like a repeated pattern then also
12644 try smaller element sizes. */
12647 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
12648 unsigned *immbits
, int *op
, int size
,
12649 enum neon_el_type type
)
12651 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
12653 if (type
== NT_float
&& !float_p
)
12656 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
12658 if (size
!= 32 || *op
== 1)
12660 *immbits
= neon_qfloat_bits (immlo
);
12666 if (neon_bits_same_in_bytes (immhi
)
12667 && neon_bits_same_in_bytes (immlo
))
12671 *immbits
= (neon_squash_bits (immhi
) << 4)
12672 | neon_squash_bits (immlo
);
12677 if (immhi
!= immlo
)
12683 if (immlo
== (immlo
& 0x000000ff))
12688 else if (immlo
== (immlo
& 0x0000ff00))
12690 *immbits
= immlo
>> 8;
12693 else if (immlo
== (immlo
& 0x00ff0000))
12695 *immbits
= immlo
>> 16;
12698 else if (immlo
== (immlo
& 0xff000000))
12700 *immbits
= immlo
>> 24;
12703 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
12705 *immbits
= (immlo
>> 8) & 0xff;
12708 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
12710 *immbits
= (immlo
>> 16) & 0xff;
12714 if ((immlo
& 0xffff) != (immlo
>> 16))
12721 if (immlo
== (immlo
& 0x000000ff))
12726 else if (immlo
== (immlo
& 0x0000ff00))
12728 *immbits
= immlo
>> 8;
12732 if ((immlo
& 0xff) != (immlo
>> 8))
12737 if (immlo
== (immlo
& 0x000000ff))
12739 /* Don't allow MVN with 8-bit immediate. */
12749 /* Write immediate bits [7:0] to the following locations:
12751 |28/24|23 19|18 16|15 4|3 0|
12752 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
12754 This function is used by VMOV/VMVN/VORR/VBIC. */
12757 neon_write_immbits (unsigned immbits
)
12759 inst
.instruction
|= immbits
& 0xf;
12760 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
12761 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
12764 /* Invert low-order SIZE bits of XHI:XLO. */
12767 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
12769 unsigned immlo
= xlo
? *xlo
: 0;
12770 unsigned immhi
= xhi
? *xhi
: 0;
12775 immlo
= (~immlo
) & 0xff;
12779 immlo
= (~immlo
) & 0xffff;
12783 immhi
= (~immhi
) & 0xffffffff;
12784 /* fall through. */
12787 immlo
= (~immlo
) & 0xffffffff;
12802 do_neon_logic (void)
12804 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
12806 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12807 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12808 /* U bit and size field were set as part of the bitmask. */
12809 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12810 neon_three_same (neon_quad (rs
), 0, -1);
12814 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12815 struct neon_type_el et
= neon_check_type (2, rs
,
12816 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12817 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
12821 if (et
.type
== NT_invtype
)
12824 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12826 immbits
= inst
.operands
[1].imm
;
12829 /* .i64 is a pseudo-op, so the immediate must be a repeating
12831 if (immbits
!= (inst
.operands
[1].regisimm
?
12832 inst
.operands
[1].reg
: 0))
12834 /* Set immbits to an invalid constant. */
12835 immbits
= 0xdeadbeef;
12842 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12846 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12850 /* Pseudo-instruction for VBIC. */
12851 neon_invert_size (&immbits
, 0, et
.size
);
12852 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12856 /* Pseudo-instruction for VORR. */
12857 neon_invert_size (&immbits
, 0, et
.size
);
12858 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12868 inst
.instruction
|= neon_quad (rs
) << 6;
12869 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12870 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12871 inst
.instruction
|= cmode
<< 8;
12872 neon_write_immbits (immbits
);
12874 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12879 do_neon_bitfield (void)
12881 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12882 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12883 neon_three_same (neon_quad (rs
), 0, -1);
12887 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
12890 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12891 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
12893 if (et
.type
== NT_float
)
12895 inst
.instruction
= NEON_ENC_FLOAT (inst
.instruction
);
12896 neon_three_same (neon_quad (rs
), 0, -1);
12900 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12901 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
12906 do_neon_dyadic_if_su (void)
12908 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12912 do_neon_dyadic_if_su_d (void)
12914 /* This version only allow D registers, but that constraint is enforced during
12915 operand parsing so we don't need to do anything extra here. */
12916 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12920 do_neon_dyadic_if_i_d (void)
12922 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12923 affected if we specify unsigned args. */
12924 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12927 enum vfp_or_neon_is_neon_bits
12930 NEON_CHECK_ARCH
= 2
12933 /* Call this function if an instruction which may have belonged to the VFP or
12934 Neon instruction sets, but turned out to be a Neon instruction (due to the
12935 operand types involved, etc.). We have to check and/or fix-up a couple of
12938 - Make sure the user hasn't attempted to make a Neon instruction
12940 - Alter the value in the condition code field if necessary.
12941 - Make sure that the arch supports Neon instructions.
12943 Which of these operations take place depends on bits from enum
12944 vfp_or_neon_is_neon_bits.
12946 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
12947 current instruction's condition is COND_ALWAYS, the condition field is
12948 changed to inst.uncond_value. This is necessary because instructions shared
12949 between VFP and Neon may be conditional for the VFP variants only, and the
12950 unconditional Neon version must have, e.g., 0xF in the condition field. */
12953 vfp_or_neon_is_neon (unsigned check
)
12955 /* Conditions are always legal in Thumb mode (IT blocks). */
12956 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
12958 if (inst
.cond
!= COND_ALWAYS
)
12960 first_error (_(BAD_COND
));
12963 if (inst
.uncond_value
!= -1)
12964 inst
.instruction
|= inst
.uncond_value
<< 28;
12967 if ((check
& NEON_CHECK_ARCH
)
12968 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
12970 first_error (_(BAD_FPU
));
12978 do_neon_addsub_if_i (void)
12980 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
12983 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12986 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12987 affected if we specify unsigned args. */
12988 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
12991 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
12993 V<op> A,B (A is operand 0, B is operand 2)
12998 so handle that case specially. */
13001 neon_exchange_operands (void)
13003 void *scratch
= alloca (sizeof (inst
.operands
[0]));
13004 if (inst
.operands
[1].present
)
13006 /* Swap operands[1] and operands[2]. */
13007 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
13008 inst
.operands
[1] = inst
.operands
[2];
13009 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
13013 inst
.operands
[1] = inst
.operands
[2];
13014 inst
.operands
[2] = inst
.operands
[0];
13019 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
13021 if (inst
.operands
[2].isreg
)
13024 neon_exchange_operands ();
13025 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
13029 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13030 struct neon_type_el et
= neon_check_type (2, rs
,
13031 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
13033 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13034 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13035 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13036 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13037 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13038 inst
.instruction
|= neon_quad (rs
) << 6;
13039 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13040 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13042 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13049 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
13053 do_neon_cmp_inv (void)
13055 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
13061 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
13064 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13065 scalars, which are encoded in 5 bits, M : Rm.
13066 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13067 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13071 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
13073 unsigned regno
= NEON_SCALAR_REG (scalar
);
13074 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
13079 if (regno
> 7 || elno
> 3)
13081 return regno
| (elno
<< 3);
13084 if (regno
> 15 || elno
> 1)
13086 return regno
| (elno
<< 4);
13090 first_error (_("scalar out of range for multiply instruction"));
13096 /* Encode multiply / multiply-accumulate scalar instructions. */
13099 neon_mul_mac (struct neon_type_el et
, int ubit
)
13103 /* Give a more helpful error message if we have an invalid type. */
13104 if (et
.type
== NT_invtype
)
13107 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
13108 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13109 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13110 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13111 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13112 inst
.instruction
|= LOW4 (scalar
);
13113 inst
.instruction
|= HI1 (scalar
) << 5;
13114 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13115 inst
.instruction
|= neon_logbits (et
.size
) << 20;
13116 inst
.instruction
|= (ubit
!= 0) << 24;
13118 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13122 do_neon_mac_maybe_scalar (void)
13124 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
13127 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13130 if (inst
.operands
[2].isscalar
)
13132 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13133 struct neon_type_el et
= neon_check_type (3, rs
,
13134 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13135 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13136 neon_mul_mac (et
, neon_quad (rs
));
13140 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13141 affected if we specify unsigned args. */
13142 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13147 do_neon_fmac (void)
13149 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
13152 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13155 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13161 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13162 struct neon_type_el et
= neon_check_type (3, rs
,
13163 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13164 neon_three_same (neon_quad (rs
), 0, et
.size
);
13167 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13168 same types as the MAC equivalents. The polynomial type for this instruction
13169 is encoded the same as the integer type. */
13174 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13177 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13180 if (inst
.operands
[2].isscalar
)
13181 do_neon_mac_maybe_scalar ();
13183 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13187 do_neon_qdmulh (void)
13189 if (inst
.operands
[2].isscalar
)
13191 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13192 struct neon_type_el et
= neon_check_type (3, rs
,
13193 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13194 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13195 neon_mul_mac (et
, neon_quad (rs
));
13199 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13200 struct neon_type_el et
= neon_check_type (3, rs
,
13201 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13202 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13203 /* The U bit (rounding) comes from bit mask. */
13204 neon_three_same (neon_quad (rs
), 0, et
.size
);
13209 do_neon_fcmp_absolute (void)
13211 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13212 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13213 /* Size field comes from bit mask. */
13214 neon_three_same (neon_quad (rs
), 1, -1);
13218 do_neon_fcmp_absolute_inv (void)
13220 neon_exchange_operands ();
13221 do_neon_fcmp_absolute ();
13225 do_neon_step (void)
13227 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13228 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13229 neon_three_same (neon_quad (rs
), 0, -1);
13233 do_neon_abs_neg (void)
13235 enum neon_shape rs
;
13236 struct neon_type_el et
;
13238 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
13241 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13244 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13245 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
13247 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13248 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13249 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13250 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13251 inst
.instruction
|= neon_quad (rs
) << 6;
13252 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13253 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13255 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13261 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13262 struct neon_type_el et
= neon_check_type (2, rs
,
13263 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13264 int imm
= inst
.operands
[2].imm
;
13265 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13266 _("immediate out of range for insert"));
13267 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13273 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13274 struct neon_type_el et
= neon_check_type (2, rs
,
13275 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13276 int imm
= inst
.operands
[2].imm
;
13277 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13278 _("immediate out of range for insert"));
13279 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
13283 do_neon_qshlu_imm (void)
13285 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13286 struct neon_type_el et
= neon_check_type (2, rs
,
13287 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
13288 int imm
= inst
.operands
[2].imm
;
13289 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13290 _("immediate out of range for shift"));
13291 /* Only encodes the 'U present' variant of the instruction.
13292 In this case, signed types have OP (bit 8) set to 0.
13293 Unsigned types have OP set to 1. */
13294 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
13295 /* The rest of the bits are the same as other immediate shifts. */
13296 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13300 do_neon_qmovn (void)
13302 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13303 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13304 /* Saturating move where operands can be signed or unsigned, and the
13305 destination has the same signedness. */
13306 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13307 if (et
.type
== NT_unsigned
)
13308 inst
.instruction
|= 0xc0;
13310 inst
.instruction
|= 0x80;
13311 neon_two_same (0, 1, et
.size
/ 2);
13315 do_neon_qmovun (void)
13317 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13318 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13319 /* Saturating move with unsigned results. Operands must be signed. */
13320 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13321 neon_two_same (0, 1, et
.size
/ 2);
13325 do_neon_rshift_sat_narrow (void)
13327 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13328 or unsigned. If operands are unsigned, results must also be unsigned. */
13329 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13330 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13331 int imm
= inst
.operands
[2].imm
;
13332 /* This gets the bounds check, size encoding and immediate bits calculation
13336 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
13337 VQMOVN.I<size> <Dd>, <Qm>. */
13340 inst
.operands
[2].present
= 0;
13341 inst
.instruction
= N_MNEM_vqmovn
;
13346 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13347 _("immediate out of range"));
13348 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
13352 do_neon_rshift_sat_narrow_u (void)
13354 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13355 or unsigned. If operands are unsigned, results must also be unsigned. */
13356 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13357 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13358 int imm
= inst
.operands
[2].imm
;
13359 /* This gets the bounds check, size encoding and immediate bits calculation
13363 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
13364 VQMOVUN.I<size> <Dd>, <Qm>. */
13367 inst
.operands
[2].present
= 0;
13368 inst
.instruction
= N_MNEM_vqmovun
;
13373 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13374 _("immediate out of range"));
13375 /* FIXME: The manual is kind of unclear about what value U should have in
13376 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
13378 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
13382 do_neon_movn (void)
13384 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13385 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13386 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13387 neon_two_same (0, 1, et
.size
/ 2);
13391 do_neon_rshift_narrow (void)
13393 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13394 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13395 int imm
= inst
.operands
[2].imm
;
13396 /* This gets the bounds check, size encoding and immediate bits calculation
13400 /* If immediate is zero then we are a pseudo-instruction for
13401 VMOVN.I<size> <Dd>, <Qm> */
13404 inst
.operands
[2].present
= 0;
13405 inst
.instruction
= N_MNEM_vmovn
;
13410 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13411 _("immediate out of range for narrowing operation"));
13412 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
13416 do_neon_shll (void)
13418 /* FIXME: Type checking when lengthening. */
13419 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
13420 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
13421 unsigned imm
= inst
.operands
[2].imm
;
13423 if (imm
== et
.size
)
13425 /* Maximum shift variant. */
13426 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13427 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13428 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13429 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13430 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13431 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13433 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13437 /* A more-specific type check for non-max versions. */
13438 et
= neon_check_type (2, NS_QDI
,
13439 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13440 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13441 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
13445 /* Check the various types for the VCVT instruction, and return which version
13446 the current instruction is. */
13449 neon_cvt_flavour (enum neon_shape rs
)
13451 #define CVT_VAR(C,X,Y) \
13452 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
13453 if (et.type != NT_invtype) \
13455 inst.error = NULL; \
13458 struct neon_type_el et
;
13459 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
13460 || rs
== NS_FF
) ? N_VFP
: 0;
13461 /* The instruction versions which take an immediate take one register
13462 argument, which is extended to the width of the full register. Thus the
13463 "source" and "destination" registers must have the same width. Hack that
13464 here by making the size equal to the key (wider, in this case) operand. */
13465 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
13467 CVT_VAR (0, N_S32
, N_F32
);
13468 CVT_VAR (1, N_U32
, N_F32
);
13469 CVT_VAR (2, N_F32
, N_S32
);
13470 CVT_VAR (3, N_F32
, N_U32
);
13471 /* Half-precision conversions. */
13472 CVT_VAR (4, N_F32
, N_F16
);
13473 CVT_VAR (5, N_F16
, N_F32
);
13477 /* VFP instructions. */
13478 CVT_VAR (6, N_F32
, N_F64
);
13479 CVT_VAR (7, N_F64
, N_F32
);
13480 CVT_VAR (8, N_S32
, N_F64
| key
);
13481 CVT_VAR (9, N_U32
, N_F64
| key
);
13482 CVT_VAR (10, N_F64
| key
, N_S32
);
13483 CVT_VAR (11, N_F64
| key
, N_U32
);
13484 /* VFP instructions with bitshift. */
13485 CVT_VAR (12, N_F32
| key
, N_S16
);
13486 CVT_VAR (13, N_F32
| key
, N_U16
);
13487 CVT_VAR (14, N_F64
| key
, N_S16
);
13488 CVT_VAR (15, N_F64
| key
, N_U16
);
13489 CVT_VAR (16, N_S16
, N_F32
| key
);
13490 CVT_VAR (17, N_U16
, N_F32
| key
);
13491 CVT_VAR (18, N_S16
, N_F64
| key
);
13492 CVT_VAR (19, N_U16
, N_F64
| key
);
13498 /* Neon-syntax VFP conversions. */
13501 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
13503 const char *opname
= 0;
13505 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
13507 /* Conversions with immediate bitshift. */
13508 const char *enc
[] =
13532 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13534 opname
= enc
[flavour
];
13535 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13536 _("operands 0 and 1 must be the same register"));
13537 inst
.operands
[1] = inst
.operands
[2];
13538 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
13543 /* Conversions without bitshift. */
13544 const char *enc
[] =
13560 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13561 opname
= enc
[flavour
];
13565 do_vfp_nsyn_opcode (opname
);
13569 do_vfp_nsyn_cvtz (void)
13571 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
13572 int flavour
= neon_cvt_flavour (rs
);
13573 const char *enc
[] =
13587 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
13588 do_vfp_nsyn_opcode (enc
[flavour
]);
13594 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
13595 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
13596 int flavour
= neon_cvt_flavour (rs
);
13598 /* VFP rather than Neon conversions. */
13601 do_vfp_nsyn_cvt (rs
, flavour
);
13611 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
13613 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13616 /* Fixed-point conversion with #0 immediate is encoded as an
13617 integer conversion. */
13618 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
13620 immbits
= 32 - inst
.operands
[2].imm
;
13621 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13623 inst
.instruction
|= enctab
[flavour
];
13624 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13625 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13626 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13627 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13628 inst
.instruction
|= neon_quad (rs
) << 6;
13629 inst
.instruction
|= 1 << 21;
13630 inst
.instruction
|= immbits
<< 16;
13632 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13640 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
13642 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13644 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13648 inst
.instruction
|= enctab
[flavour
];
13650 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13651 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13652 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13653 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13654 inst
.instruction
|= neon_quad (rs
) << 6;
13655 inst
.instruction
|= 2 << 18;
13657 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13661 /* Half-precision conversions for Advanced SIMD -- neon. */
13666 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
13668 as_bad (_("operand size must match register width"));
13673 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
13675 as_bad (_("operand size must match register width"));
13680 inst
.instruction
= 0x3b60600;
13682 inst
.instruction
= 0x3b60700;
13684 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13685 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13686 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13687 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13688 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13692 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
13693 do_vfp_nsyn_cvt (rs
, flavour
);
13698 do_neon_cvtb (void)
13700 inst
.instruction
= 0xeb20a40;
13702 /* The sizes are attached to the mnemonic. */
13703 if (inst
.vectype
.el
[0].type
!= NT_invtype
13704 && inst
.vectype
.el
[0].size
== 16)
13705 inst
.instruction
|= 0x00010000;
13707 /* Programmer's syntax: the sizes are attached to the operands. */
13708 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
13709 && inst
.operands
[0].vectype
.size
== 16)
13710 inst
.instruction
|= 0x00010000;
13712 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
13713 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
13714 do_vfp_cond_or_thumb ();
13719 do_neon_cvtt (void)
13722 inst
.instruction
|= 0x80;
13726 neon_move_immediate (void)
13728 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
13729 struct neon_type_el et
= neon_check_type (2, rs
,
13730 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13731 unsigned immlo
, immhi
= 0, immbits
;
13732 int op
, cmode
, float_p
;
13734 constraint (et
.type
== NT_invtype
,
13735 _("operand size must be specified for immediate VMOV"));
13737 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
13738 op
= (inst
.instruction
& (1 << 5)) != 0;
13740 immlo
= inst
.operands
[1].imm
;
13741 if (inst
.operands
[1].regisimm
)
13742 immhi
= inst
.operands
[1].reg
;
13744 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
13745 _("immediate has bits set outside the operand size"));
13747 float_p
= inst
.operands
[1].immisfloat
;
13749 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
13750 et
.size
, et
.type
)) == FAIL
)
13752 /* Invert relevant bits only. */
13753 neon_invert_size (&immlo
, &immhi
, et
.size
);
13754 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
13755 with one or the other; those cases are caught by
13756 neon_cmode_for_move_imm. */
13758 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
13759 &op
, et
.size
, et
.type
)) == FAIL
)
13761 first_error (_("immediate out of range"));
13766 inst
.instruction
&= ~(1 << 5);
13767 inst
.instruction
|= op
<< 5;
13769 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13770 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13771 inst
.instruction
|= neon_quad (rs
) << 6;
13772 inst
.instruction
|= cmode
<< 8;
13774 neon_write_immbits (immbits
);
13780 if (inst
.operands
[1].isreg
)
13782 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13784 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13785 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13786 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13787 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13788 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13789 inst
.instruction
|= neon_quad (rs
) << 6;
13793 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13794 neon_move_immediate ();
13797 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13800 /* Encode instructions of form:
13802 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13803 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
13806 neon_mixed_length (struct neon_type_el et
, unsigned size
)
13808 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13809 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13810 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13811 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13812 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13813 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13814 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
13815 inst
.instruction
|= neon_logbits (size
) << 20;
13817 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13821 do_neon_dyadic_long (void)
13823 /* FIXME: Type checking for lengthening op. */
13824 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13825 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
13826 neon_mixed_length (et
, et
.size
);
13830 do_neon_abal (void)
13832 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13833 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
13834 neon_mixed_length (et
, et
.size
);
13838 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
13840 if (inst
.operands
[2].isscalar
)
13842 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
13843 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
13844 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13845 neon_mul_mac (et
, et
.type
== NT_unsigned
);
13849 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13850 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
13851 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13852 neon_mixed_length (et
, et
.size
);
13857 do_neon_mac_maybe_scalar_long (void)
13859 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
13863 do_neon_dyadic_wide (void)
13865 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
13866 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13867 neon_mixed_length (et
, et
.size
);
13871 do_neon_dyadic_narrow (void)
13873 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13874 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
13875 /* Operand sign is unimportant, and the U bit is part of the opcode,
13876 so force the operand type to integer. */
13877 et
.type
= NT_integer
;
13878 neon_mixed_length (et
, et
.size
/ 2);
13882 do_neon_mul_sat_scalar_long (void)
13884 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
13888 do_neon_vmull (void)
13890 if (inst
.operands
[2].isscalar
)
13891 do_neon_mac_maybe_scalar_long ();
13894 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13895 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
13896 if (et
.type
== NT_poly
)
13897 inst
.instruction
= NEON_ENC_POLY (inst
.instruction
);
13899 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13900 /* For polynomial encoding, size field must be 0b00 and the U bit must be
13901 zero. Should be OK as-is. */
13902 neon_mixed_length (et
, et
.size
);
13909 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
13910 struct neon_type_el et
= neon_check_type (3, rs
,
13911 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13912 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
13914 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
13915 _("shift out of range"));
13916 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13917 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13918 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13919 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13920 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13921 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13922 inst
.instruction
|= neon_quad (rs
) << 6;
13923 inst
.instruction
|= imm
<< 8;
13925 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13931 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13932 struct neon_type_el et
= neon_check_type (2, rs
,
13933 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13934 unsigned op
= (inst
.instruction
>> 7) & 3;
13935 /* N (width of reversed regions) is encoded as part of the bitmask. We
13936 extract it here to check the elements to be reversed are smaller.
13937 Otherwise we'd get a reserved instruction. */
13938 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
13939 gas_assert (elsize
!= 0);
13940 constraint (et
.size
>= elsize
,
13941 _("elements must be smaller than reversal region"));
13942 neon_two_same (neon_quad (rs
), 1, et
.size
);
13948 if (inst
.operands
[1].isscalar
)
13950 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
13951 struct neon_type_el et
= neon_check_type (2, rs
,
13952 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13953 unsigned sizebits
= et
.size
>> 3;
13954 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
13955 int logsize
= neon_logbits (et
.size
);
13956 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
13958 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
13961 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13962 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13963 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13964 inst
.instruction
|= LOW4 (dm
);
13965 inst
.instruction
|= HI1 (dm
) << 5;
13966 inst
.instruction
|= neon_quad (rs
) << 6;
13967 inst
.instruction
|= x
<< 17;
13968 inst
.instruction
|= sizebits
<< 16;
13970 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13974 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
13975 struct neon_type_el et
= neon_check_type (2, rs
,
13976 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13977 /* Duplicate ARM register to lanes of vector. */
13978 inst
.instruction
= NEON_ENC_ARMREG (inst
.instruction
);
13981 case 8: inst
.instruction
|= 0x400000; break;
13982 case 16: inst
.instruction
|= 0x000020; break;
13983 case 32: inst
.instruction
|= 0x000000; break;
13986 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13987 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
13988 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
13989 inst
.instruction
|= neon_quad (rs
) << 21;
13990 /* The encoding for this instruction is identical for the ARM and Thumb
13991 variants, except for the condition field. */
13992 do_vfp_cond_or_thumb ();
13996 /* VMOV has particularly many variations. It can be one of:
13997 0. VMOV<c><q> <Qd>, <Qm>
13998 1. VMOV<c><q> <Dd>, <Dm>
13999 (Register operations, which are VORR with Rm = Rn.)
14000 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14001 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14003 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14004 (ARM register to scalar.)
14005 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14006 (Two ARM registers to vector.)
14007 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14008 (Scalar to ARM register.)
14009 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14010 (Vector to two ARM registers.)
14011 8. VMOV.F32 <Sd>, <Sm>
14012 9. VMOV.F64 <Dd>, <Dm>
14013 (VFP register moves.)
14014 10. VMOV.F32 <Sd>, #imm
14015 11. VMOV.F64 <Dd>, #imm
14016 (VFP float immediate load.)
14017 12. VMOV <Rd>, <Sm>
14018 (VFP single to ARM reg.)
14019 13. VMOV <Sd>, <Rm>
14020 (ARM reg to VFP single.)
14021 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14022 (Two ARM regs to two VFP singles.)
14023 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14024 (Two VFP singles to two ARM regs.)
14026 These cases can be disambiguated using neon_select_shape, except cases 1/9
14027 and 3/11 which depend on the operand type too.
14029 All the encoded bits are hardcoded by this function.
14031 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14032 Cases 5, 7 may be used with VFPv2 and above.
14034 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14035 can specify a type where it doesn't make sense to, and is ignored). */
14040 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
14041 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
14043 struct neon_type_el et
;
14044 const char *ldconst
= 0;
14048 case NS_DD
: /* case 1/9. */
14049 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14050 /* It is not an error here if no type is given. */
14052 if (et
.type
== NT_float
&& et
.size
== 64)
14054 do_vfp_nsyn_opcode ("fcpyd");
14057 /* fall through. */
14059 case NS_QQ
: /* case 0/1. */
14061 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14063 /* The architecture manual I have doesn't explicitly state which
14064 value the U bit should have for register->register moves, but
14065 the equivalent VORR instruction has U = 0, so do that. */
14066 inst
.instruction
= 0x0200110;
14067 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14068 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14069 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14070 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14071 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14072 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14073 inst
.instruction
|= neon_quad (rs
) << 6;
14075 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
14079 case NS_DI
: /* case 3/11. */
14080 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14082 if (et
.type
== NT_float
&& et
.size
== 64)
14084 /* case 11 (fconstd). */
14085 ldconst
= "fconstd";
14086 goto encode_fconstd
;
14088 /* fall through. */
14090 case NS_QI
: /* case 2/3. */
14091 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14093 inst
.instruction
= 0x0800010;
14094 neon_move_immediate ();
14095 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
14098 case NS_SR
: /* case 4. */
14100 unsigned bcdebits
= 0;
14101 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
14102 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14103 int logsize
= neon_logbits (et
.size
);
14104 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
14105 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
14107 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14109 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14110 && et
.size
!= 32, _(BAD_FPU
));
14111 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14112 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14116 case 8: bcdebits
= 0x8; break;
14117 case 16: bcdebits
= 0x1; break;
14118 case 32: bcdebits
= 0x0; break;
14122 bcdebits
|= x
<< logsize
;
14124 inst
.instruction
= 0xe000b10;
14125 do_vfp_cond_or_thumb ();
14126 inst
.instruction
|= LOW4 (dn
) << 16;
14127 inst
.instruction
|= HI1 (dn
) << 7;
14128 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14129 inst
.instruction
|= (bcdebits
& 3) << 5;
14130 inst
.instruction
|= (bcdebits
>> 2) << 21;
14134 case NS_DRR
: /* case 5 (fmdrr). */
14135 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14138 inst
.instruction
= 0xc400b10;
14139 do_vfp_cond_or_thumb ();
14140 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
14141 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
14142 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14143 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14146 case NS_RS
: /* case 6. */
14148 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
14149 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14150 unsigned logsize
= neon_logbits (et
.size
);
14151 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14152 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14153 unsigned abcdebits
= 0;
14155 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14157 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14158 && et
.size
!= 32, _(BAD_FPU
));
14159 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14160 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14164 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14165 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14166 case 32: abcdebits
= 0x00; break;
14170 abcdebits
|= x
<< logsize
;
14171 inst
.instruction
= 0xe100b10;
14172 do_vfp_cond_or_thumb ();
14173 inst
.instruction
|= LOW4 (dn
) << 16;
14174 inst
.instruction
|= HI1 (dn
) << 7;
14175 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14176 inst
.instruction
|= (abcdebits
& 3) << 5;
14177 inst
.instruction
|= (abcdebits
>> 2) << 21;
14181 case NS_RRD
: /* case 7 (fmrrd). */
14182 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14185 inst
.instruction
= 0xc500b10;
14186 do_vfp_cond_or_thumb ();
14187 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14188 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14189 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14190 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14193 case NS_FF
: /* case 8 (fcpys). */
14194 do_vfp_nsyn_opcode ("fcpys");
14197 case NS_FI
: /* case 10 (fconsts). */
14198 ldconst
= "fconsts";
14200 if (is_quarter_float (inst
.operands
[1].imm
))
14202 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
14203 do_vfp_nsyn_opcode (ldconst
);
14206 first_error (_("immediate out of range"));
14209 case NS_RF
: /* case 12 (fmrs). */
14210 do_vfp_nsyn_opcode ("fmrs");
14213 case NS_FR
: /* case 13 (fmsr). */
14214 do_vfp_nsyn_opcode ("fmsr");
14217 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14218 (one of which is a list), but we have parsed four. Do some fiddling to
14219 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14221 case NS_RRFF
: /* case 14 (fmrrs). */
14222 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
14223 _("VFP registers must be adjacent"));
14224 inst
.operands
[2].imm
= 2;
14225 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14226 do_vfp_nsyn_opcode ("fmrrs");
14229 case NS_FFRR
: /* case 15 (fmsrr). */
14230 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
14231 _("VFP registers must be adjacent"));
14232 inst
.operands
[1] = inst
.operands
[2];
14233 inst
.operands
[2] = inst
.operands
[3];
14234 inst
.operands
[0].imm
= 2;
14235 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14236 do_vfp_nsyn_opcode ("fmsrr");
14245 do_neon_rshift_round_imm (void)
14247 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14248 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14249 int imm
= inst
.operands
[2].imm
;
14251 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14254 inst
.operands
[2].present
= 0;
14259 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14260 _("immediate out of range for shift"));
14261 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
14266 do_neon_movl (void)
14268 struct neon_type_el et
= neon_check_type (2, NS_QD
,
14269 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14270 unsigned sizebits
= et
.size
>> 3;
14271 inst
.instruction
|= sizebits
<< 19;
14272 neon_two_same (0, et
.type
== NT_unsigned
, -1);
14278 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14279 struct neon_type_el et
= neon_check_type (2, rs
,
14280 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14281 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
14282 neon_two_same (neon_quad (rs
), 1, et
.size
);
14286 do_neon_zip_uzp (void)
14288 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14289 struct neon_type_el et
= neon_check_type (2, rs
,
14290 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14291 if (rs
== NS_DD
&& et
.size
== 32)
14293 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
14294 inst
.instruction
= N_MNEM_vtrn
;
14298 neon_two_same (neon_quad (rs
), 1, et
.size
);
14302 do_neon_sat_abs_neg (void)
14304 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14305 struct neon_type_el et
= neon_check_type (2, rs
,
14306 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14307 neon_two_same (neon_quad (rs
), 1, et
.size
);
14311 do_neon_pair_long (void)
14313 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14314 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
14315 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
14316 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
14317 neon_two_same (neon_quad (rs
), 1, et
.size
);
14321 do_neon_recip_est (void)
14323 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14324 struct neon_type_el et
= neon_check_type (2, rs
,
14325 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
14326 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14327 neon_two_same (neon_quad (rs
), 1, et
.size
);
14333 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14334 struct neon_type_el et
= neon_check_type (2, rs
,
14335 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14336 neon_two_same (neon_quad (rs
), 1, et
.size
);
14342 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14343 struct neon_type_el et
= neon_check_type (2, rs
,
14344 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
14345 neon_two_same (neon_quad (rs
), 1, et
.size
);
14351 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14352 struct neon_type_el et
= neon_check_type (2, rs
,
14353 N_EQK
| N_INT
, N_8
| N_KEY
);
14354 neon_two_same (neon_quad (rs
), 1, et
.size
);
14360 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14361 neon_two_same (neon_quad (rs
), 1, -1);
14365 do_neon_tbl_tbx (void)
14367 unsigned listlenbits
;
14368 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
14370 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
14372 first_error (_("bad list length for table lookup"));
14376 listlenbits
= inst
.operands
[1].imm
- 1;
14377 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14378 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14379 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14380 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14381 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14382 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14383 inst
.instruction
|= listlenbits
<< 8;
14385 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
14389 do_neon_ldm_stm (void)
14391 /* P, U and L bits are part of bitmask. */
14392 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
14393 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
14395 if (inst
.operands
[1].issingle
)
14397 do_vfp_nsyn_ldm_stm (is_dbmode
);
14401 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
14402 _("writeback (!) must be used for VLDMDB and VSTMDB"));
14404 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14405 _("register list must contain at least 1 and at most 16 "
14408 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14409 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
14410 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14411 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
14413 inst
.instruction
|= offsetbits
;
14415 do_vfp_cond_or_thumb ();
14419 do_neon_ldr_str (void)
14421 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
14423 if (inst
.operands
[0].issingle
)
14426 do_vfp_nsyn_opcode ("flds");
14428 do_vfp_nsyn_opcode ("fsts");
14433 do_vfp_nsyn_opcode ("fldd");
14435 do_vfp_nsyn_opcode ("fstd");
14439 /* "interleave" version also handles non-interleaving register VLD1/VST1
14443 do_neon_ld_st_interleave (void)
14445 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
14446 N_8
| N_16
| N_32
| N_64
);
14447 unsigned alignbits
= 0;
14449 /* The bits in this table go:
14450 0: register stride of one (0) or two (1)
14451 1,2: register list length, minus one (1, 2, 3, 4).
14452 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
14453 We use -1 for invalid entries. */
14454 const int typetable
[] =
14456 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
14457 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
14458 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
14459 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
14463 if (et
.type
== NT_invtype
)
14466 if (inst
.operands
[1].immisalign
)
14467 switch (inst
.operands
[1].imm
>> 8)
14469 case 64: alignbits
= 1; break;
14471 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
14472 goto bad_alignment
;
14476 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
14477 goto bad_alignment
;
14482 first_error (_("bad alignment"));
14486 inst
.instruction
|= alignbits
<< 4;
14487 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14489 /* Bits [4:6] of the immediate in a list specifier encode register stride
14490 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
14491 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
14492 up the right value for "type" in a table based on this value and the given
14493 list style, then stick it back. */
14494 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
14495 | (((inst
.instruction
>> 8) & 3) << 3);
14497 typebits
= typetable
[idx
];
14499 constraint (typebits
== -1, _("bad list type for instruction"));
14501 inst
.instruction
&= ~0xf00;
14502 inst
.instruction
|= typebits
<< 8;
14505 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
14506 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
14507 otherwise. The variable arguments are a list of pairs of legal (size, align)
14508 values, terminated with -1. */
14511 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
14514 int result
= FAIL
, thissize
, thisalign
;
14516 if (!inst
.operands
[1].immisalign
)
14522 va_start (ap
, do_align
);
14526 thissize
= va_arg (ap
, int);
14527 if (thissize
== -1)
14529 thisalign
= va_arg (ap
, int);
14531 if (size
== thissize
&& align
== thisalign
)
14534 while (result
!= SUCCESS
);
14538 if (result
== SUCCESS
)
14541 first_error (_("unsupported alignment for instruction"));
14547 do_neon_ld_st_lane (void)
14549 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14550 int align_good
, do_align
= 0;
14551 int logsize
= neon_logbits (et
.size
);
14552 int align
= inst
.operands
[1].imm
>> 8;
14553 int n
= (inst
.instruction
>> 8) & 3;
14554 int max_el
= 64 / et
.size
;
14556 if (et
.type
== NT_invtype
)
14559 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
14560 _("bad list length"));
14561 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
14562 _("scalar index out of range"));
14563 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
14565 _("stride of 2 unavailable when element size is 8"));
14569 case 0: /* VLD1 / VST1. */
14570 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
14572 if (align_good
== FAIL
)
14576 unsigned alignbits
= 0;
14579 case 16: alignbits
= 0x1; break;
14580 case 32: alignbits
= 0x3; break;
14583 inst
.instruction
|= alignbits
<< 4;
14587 case 1: /* VLD2 / VST2. */
14588 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
14590 if (align_good
== FAIL
)
14593 inst
.instruction
|= 1 << 4;
14596 case 2: /* VLD3 / VST3. */
14597 constraint (inst
.operands
[1].immisalign
,
14598 _("can't use alignment with this instruction"));
14601 case 3: /* VLD4 / VST4. */
14602 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14603 16, 64, 32, 64, 32, 128, -1);
14604 if (align_good
== FAIL
)
14608 unsigned alignbits
= 0;
14611 case 8: alignbits
= 0x1; break;
14612 case 16: alignbits
= 0x1; break;
14613 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
14616 inst
.instruction
|= alignbits
<< 4;
14623 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
14624 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14625 inst
.instruction
|= 1 << (4 + logsize
);
14627 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
14628 inst
.instruction
|= logsize
<< 10;
14631 /* Encode single n-element structure to all lanes VLD<n> instructions. */
14634 do_neon_ld_dup (void)
14636 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14637 int align_good
, do_align
= 0;
14639 if (et
.type
== NT_invtype
)
14642 switch ((inst
.instruction
>> 8) & 3)
14644 case 0: /* VLD1. */
14645 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
14646 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14647 &do_align
, 16, 16, 32, 32, -1);
14648 if (align_good
== FAIL
)
14650 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
14653 case 2: inst
.instruction
|= 1 << 5; break;
14654 default: first_error (_("bad list length")); return;
14656 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14659 case 1: /* VLD2. */
14660 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14661 &do_align
, 8, 16, 16, 32, 32, 64, -1);
14662 if (align_good
== FAIL
)
14664 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
14665 _("bad list length"));
14666 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14667 inst
.instruction
|= 1 << 5;
14668 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14671 case 2: /* VLD3. */
14672 constraint (inst
.operands
[1].immisalign
,
14673 _("can't use alignment with this instruction"));
14674 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
14675 _("bad list length"));
14676 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14677 inst
.instruction
|= 1 << 5;
14678 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14681 case 3: /* VLD4. */
14683 int align
= inst
.operands
[1].imm
>> 8;
14684 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14685 16, 64, 32, 64, 32, 128, -1);
14686 if (align_good
== FAIL
)
14688 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
14689 _("bad list length"));
14690 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14691 inst
.instruction
|= 1 << 5;
14692 if (et
.size
== 32 && align
== 128)
14693 inst
.instruction
|= 0x3 << 6;
14695 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14702 inst
.instruction
|= do_align
<< 4;
14705 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
14706 apart from bits [11:4]. */
14709 do_neon_ldx_stx (void)
14711 switch (NEON_LANE (inst
.operands
[0].imm
))
14713 case NEON_INTERLEAVE_LANES
:
14714 inst
.instruction
= NEON_ENC_INTERLV (inst
.instruction
);
14715 do_neon_ld_st_interleave ();
14718 case NEON_ALL_LANES
:
14719 inst
.instruction
= NEON_ENC_DUP (inst
.instruction
);
14724 inst
.instruction
= NEON_ENC_LANE (inst
.instruction
);
14725 do_neon_ld_st_lane ();
14728 /* L bit comes from bit mask. */
14729 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14730 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14731 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14733 if (inst
.operands
[1].postind
)
14735 int postreg
= inst
.operands
[1].imm
& 0xf;
14736 constraint (!inst
.operands
[1].immisreg
,
14737 _("post-index must be a register"));
14738 constraint (postreg
== 0xd || postreg
== 0xf,
14739 _("bad register for post-index"));
14740 inst
.instruction
|= postreg
;
14742 else if (inst
.operands
[1].writeback
)
14744 inst
.instruction
|= 0xd;
14747 inst
.instruction
|= 0xf;
14750 inst
.instruction
|= 0xf9000000;
14752 inst
.instruction
|= 0xf4000000;
14755 /* Overall per-instruction processing. */
14757 /* We need to be able to fix up arbitrary expressions in some statements.
14758 This is so that we can handle symbols that are an arbitrary distance from
14759 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
14760 which returns part of an address in a form which will be valid for
14761 a data instruction. We do this by pushing the expression into a symbol
14762 in the expr_section, and creating a fix for that. */
14765 fix_new_arm (fragS
* frag
,
14780 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
14781 (enum bfd_reloc_code_real
) reloc
);
14785 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
14786 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
14790 /* Mark whether the fix is to a THUMB instruction, or an ARM
14792 new_fix
->tc_fix_data
= thumb_mode
;
14795 /* Create a frg for an instruction requiring relaxation. */
14797 output_relax_insn (void)
14803 /* The size of the instruction is unknown, so tie the debug info to the
14804 start of the instruction. */
14805 dwarf2_emit_insn (0);
14807 switch (inst
.reloc
.exp
.X_op
)
14810 sym
= inst
.reloc
.exp
.X_add_symbol
;
14811 offset
= inst
.reloc
.exp
.X_add_number
;
14815 offset
= inst
.reloc
.exp
.X_add_number
;
14818 sym
= make_expr_symbol (&inst
.reloc
.exp
);
14822 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
14823 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
14824 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
14827 /* Write a 32-bit thumb instruction to buf. */
14829 put_thumb32_insn (char * buf
, unsigned long insn
)
14831 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
14832 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
14836 output_inst (const char * str
)
14842 as_bad ("%s -- `%s'", inst
.error
, str
);
14847 output_relax_insn ();
14850 if (inst
.size
== 0)
14853 to
= frag_more (inst
.size
);
14854 /* PR 9814: Record the thumb mode into the current frag so that we know
14855 what type of NOP padding to use, if necessary. We override any previous
14856 setting so that if the mode has changed then the NOPS that we use will
14857 match the encoding of the last instruction in the frag. */
14858 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
14860 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
14862 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
14863 put_thumb32_insn (to
, inst
.instruction
);
14865 else if (inst
.size
> INSN_SIZE
)
14867 gas_assert (inst
.size
== (2 * INSN_SIZE
));
14868 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
14869 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
14872 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
14874 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
14875 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
14876 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
14879 dwarf2_emit_insn (inst
.size
);
14883 output_it_inst (int cond
, int mask
, char * to
)
14885 unsigned long instruction
= 0xbf00;
14888 instruction
|= mask
;
14889 instruction
|= cond
<< 4;
14893 to
= frag_more (2);
14895 dwarf2_emit_insn (2);
14899 md_number_to_chars (to
, instruction
, 2);
14904 /* Tag values used in struct asm_opcode's tag field. */
14907 OT_unconditional
, /* Instruction cannot be conditionalized.
14908 The ARM condition field is still 0xE. */
14909 OT_unconditionalF
, /* Instruction cannot be conditionalized
14910 and carries 0xF in its ARM condition field. */
14911 OT_csuffix
, /* Instruction takes a conditional suffix. */
14912 OT_csuffixF
, /* Some forms of the instruction take a conditional
14913 suffix, others place 0xF where the condition field
14915 OT_cinfix3
, /* Instruction takes a conditional infix,
14916 beginning at character index 3. (In
14917 unified mode, it becomes a suffix.) */
14918 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
14919 tsts, cmps, cmns, and teqs. */
14920 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
14921 character index 3, even in unified mode. Used for
14922 legacy instructions where suffix and infix forms
14923 may be ambiguous. */
14924 OT_csuf_or_in3
, /* Instruction takes either a conditional
14925 suffix or an infix at character index 3. */
14926 OT_odd_infix_unc
, /* This is the unconditional variant of an
14927 instruction that takes a conditional infix
14928 at an unusual position. In unified mode,
14929 this variant will accept a suffix. */
14930 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
14931 are the conditional variants of instructions that
14932 take conditional infixes in unusual positions.
14933 The infix appears at character index
14934 (tag - OT_odd_infix_0). These are not accepted
14935 in unified mode. */
14938 /* Subroutine of md_assemble, responsible for looking up the primary
14939 opcode from the mnemonic the user wrote. STR points to the
14940 beginning of the mnemonic.
14942 This is not simply a hash table lookup, because of conditional
14943 variants. Most instructions have conditional variants, which are
14944 expressed with a _conditional affix_ to the mnemonic. If we were
14945 to encode each conditional variant as a literal string in the opcode
14946 table, it would have approximately 20,000 entries.
14948 Most mnemonics take this affix as a suffix, and in unified syntax,
14949 'most' is upgraded to 'all'. However, in the divided syntax, some
14950 instructions take the affix as an infix, notably the s-variants of
14951 the arithmetic instructions. Of those instructions, all but six
14952 have the infix appear after the third character of the mnemonic.
14954 Accordingly, the algorithm for looking up primary opcodes given
14957 1. Look up the identifier in the opcode table.
14958 If we find a match, go to step U.
14960 2. Look up the last two characters of the identifier in the
14961 conditions table. If we find a match, look up the first N-2
14962 characters of the identifier in the opcode table. If we
14963 find a match, go to step CE.
14965 3. Look up the fourth and fifth characters of the identifier in
14966 the conditions table. If we find a match, extract those
14967 characters from the identifier, and look up the remaining
14968 characters in the opcode table. If we find a match, go
14973 U. Examine the tag field of the opcode structure, in case this is
14974 one of the six instructions with its conditional infix in an
14975 unusual place. If it is, the tag tells us where to find the
14976 infix; look it up in the conditions table and set inst.cond
14977 accordingly. Otherwise, this is an unconditional instruction.
14978 Again set inst.cond accordingly. Return the opcode structure.
14980 CE. Examine the tag field to make sure this is an instruction that
14981 should receive a conditional suffix. If it is not, fail.
14982 Otherwise, set inst.cond from the suffix we already looked up,
14983 and return the opcode structure.
14985 CM. Examine the tag field to make sure this is an instruction that
14986 should receive a conditional infix after the third character.
14987 If it is not, fail. Otherwise, undo the edits to the current
14988 line of input and proceed as for case CE. */
14990 static const struct asm_opcode
*
14991 opcode_lookup (char **str
)
14995 const struct asm_opcode
*opcode
;
14996 const struct asm_cond
*cond
;
14999 /* Scan up to the end of the mnemonic, which must end in white space,
15000 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15001 for (base
= end
= *str
; *end
!= '\0'; end
++)
15002 if (*end
== ' ' || *end
== '.')
15008 /* Handle a possible width suffix and/or Neon type suffix. */
15013 /* The .w and .n suffixes are only valid if the unified syntax is in
15015 if (unified_syntax
&& end
[1] == 'w')
15017 else if (unified_syntax
&& end
[1] == 'n')
15022 inst
.vectype
.elems
= 0;
15024 *str
= end
+ offset
;
15026 if (end
[offset
] == '.')
15028 /* See if we have a Neon type suffix (possible in either unified or
15029 non-unified ARM syntax mode). */
15030 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
15033 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
15039 /* Look for unaffixed or special-case affixed mnemonic. */
15040 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15045 if (opcode
->tag
< OT_odd_infix_0
)
15047 inst
.cond
= COND_ALWAYS
;
15051 if (warn_on_deprecated
&& unified_syntax
)
15052 as_warn (_("conditional infixes are deprecated in unified syntax"));
15053 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
15054 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15057 inst
.cond
= cond
->value
;
15061 /* Cannot have a conditional suffix on a mnemonic of less than two
15063 if (end
- base
< 3)
15066 /* Look for suffixed mnemonic. */
15068 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15069 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15071 if (opcode
&& cond
)
15074 switch (opcode
->tag
)
15076 case OT_cinfix3_legacy
:
15077 /* Ignore conditional suffixes matched on infix only mnemonics. */
15081 case OT_cinfix3_deprecated
:
15082 case OT_odd_infix_unc
:
15083 if (!unified_syntax
)
15085 /* else fall through */
15089 case OT_csuf_or_in3
:
15090 inst
.cond
= cond
->value
;
15093 case OT_unconditional
:
15094 case OT_unconditionalF
:
15096 inst
.cond
= cond
->value
;
15099 /* Delayed diagnostic. */
15100 inst
.error
= BAD_COND
;
15101 inst
.cond
= COND_ALWAYS
;
15110 /* Cannot have a usual-position infix on a mnemonic of less than
15111 six characters (five would be a suffix). */
15112 if (end
- base
< 6)
15115 /* Look for infixed mnemonic in the usual position. */
15117 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15121 memcpy (save
, affix
, 2);
15122 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
15123 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15125 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
15126 memcpy (affix
, save
, 2);
15129 && (opcode
->tag
== OT_cinfix3
15130 || opcode
->tag
== OT_cinfix3_deprecated
15131 || opcode
->tag
== OT_csuf_or_in3
15132 || opcode
->tag
== OT_cinfix3_legacy
))
15135 if (warn_on_deprecated
&& unified_syntax
15136 && (opcode
->tag
== OT_cinfix3
15137 || opcode
->tag
== OT_cinfix3_deprecated
))
15138 as_warn (_("conditional infixes are deprecated in unified syntax"));
15140 inst
.cond
= cond
->value
;
15147 /* This function generates an initial IT instruction, leaving its block
15148 virtually open for the new instructions. Eventually,
15149 the mask will be updated by now_it_add_mask () each time
15150 a new instruction needs to be included in the IT block.
15151 Finally, the block is closed with close_automatic_it_block ().
15152 The block closure can be requested either from md_assemble (),
15153 a tencode (), or due to a label hook. */
15156 new_automatic_it_block (int cond
)
15158 now_it
.state
= AUTOMATIC_IT_BLOCK
;
15159 now_it
.mask
= 0x18;
15161 now_it
.block_length
= 1;
15162 mapping_state (MAP_THUMB
);
15163 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
15166 /* Close an automatic IT block.
15167 See comments in new_automatic_it_block (). */
15170 close_automatic_it_block (void)
15172 now_it
.mask
= 0x10;
15173 now_it
.block_length
= 0;
15176 /* Update the mask of the current automatically-generated IT
15177 instruction. See comments in new_automatic_it_block (). */
15180 now_it_add_mask (int cond
)
15182 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15183 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15184 | ((bitvalue) << (nbit)))
15185 const int resulting_bit
= (cond
& 1);
15187 now_it
.mask
&= 0xf;
15188 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15190 (5 - now_it
.block_length
));
15191 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15193 ((5 - now_it
.block_length
) - 1) );
15194 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
15197 #undef SET_BIT_VALUE
15200 /* The IT blocks handling machinery is accessed through the these functions:
15201 it_fsm_pre_encode () from md_assemble ()
15202 set_it_insn_type () optional, from the tencode functions
15203 set_it_insn_type_last () ditto
15204 in_it_block () ditto
15205 it_fsm_post_encode () from md_assemble ()
15206 force_automatic_it_block_close () from label habdling functions
15209 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15210 initializing the IT insn type with a generic initial value depending
15211 on the inst.condition.
15212 2) During the tencode function, two things may happen:
15213 a) The tencode function overrides the IT insn type by
15214 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15215 b) The tencode function queries the IT block state by
15216 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15218 Both set_it_insn_type and in_it_block run the internal FSM state
15219 handling function (handle_it_state), because: a) setting the IT insn
15220 type may incur in an invalid state (exiting the function),
15221 and b) querying the state requires the FSM to be updated.
15222 Specifically we want to avoid creating an IT block for conditional
15223 branches, so it_fsm_pre_encode is actually a guess and we can't
15224 determine whether an IT block is required until the tencode () routine
15225 has decided what type of instruction this actually it.
15226 Because of this, if set_it_insn_type and in_it_block have to be used,
15227 set_it_insn_type has to be called first.
15229 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15230 determines the insn IT type depending on the inst.cond code.
15231 When a tencode () routine encodes an instruction that can be
15232 either outside an IT block, or, in the case of being inside, has to be
15233 the last one, set_it_insn_type_last () will determine the proper
15234 IT instruction type based on the inst.cond code. Otherwise,
15235 set_it_insn_type can be called for overriding that logic or
15236 for covering other cases.
15238 Calling handle_it_state () may not transition the IT block state to
15239 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
15240 still queried. Instead, if the FSM determines that the state should
15241 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
15242 after the tencode () function: that's what it_fsm_post_encode () does.
15244 Since in_it_block () calls the state handling function to get an
15245 updated state, an error may occur (due to invalid insns combination).
15246 In that case, inst.error is set.
15247 Therefore, inst.error has to be checked after the execution of
15248 the tencode () routine.
15250 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
15251 any pending state change (if any) that didn't take place in
15252 handle_it_state () as explained above. */
15255 it_fsm_pre_encode (void)
15257 if (inst
.cond
!= COND_ALWAYS
)
15258 inst
.it_insn_type
= INSIDE_IT_INSN
;
15260 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
15262 now_it
.state_handled
= 0;
15265 /* IT state FSM handling function. */
15268 handle_it_state (void)
15270 now_it
.state_handled
= 1;
15272 switch (now_it
.state
)
15274 case OUTSIDE_IT_BLOCK
:
15275 switch (inst
.it_insn_type
)
15277 case OUTSIDE_IT_INSN
:
15280 case INSIDE_IT_INSN
:
15281 case INSIDE_IT_LAST_INSN
:
15282 if (thumb_mode
== 0)
15285 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
15286 as_tsktsk (_("Warning: conditional outside an IT block"\
15291 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
15292 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
15294 /* Automatically generate the IT instruction. */
15295 new_automatic_it_block (inst
.cond
);
15296 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
15297 close_automatic_it_block ();
15301 inst
.error
= BAD_OUT_IT
;
15307 case IF_INSIDE_IT_LAST_INSN
:
15308 case NEUTRAL_IT_INSN
:
15312 now_it
.state
= MANUAL_IT_BLOCK
;
15313 now_it
.block_length
= 0;
15318 case AUTOMATIC_IT_BLOCK
:
15319 /* Three things may happen now:
15320 a) We should increment current it block size;
15321 b) We should close current it block (closing insn or 4 insns);
15322 c) We should close current it block and start a new one (due
15323 to incompatible conditions or
15324 4 insns-length block reached). */
15326 switch (inst
.it_insn_type
)
15328 case OUTSIDE_IT_INSN
:
15329 /* The closure of the block shall happen immediatelly,
15330 so any in_it_block () call reports the block as closed. */
15331 force_automatic_it_block_close ();
15334 case INSIDE_IT_INSN
:
15335 case INSIDE_IT_LAST_INSN
:
15336 case IF_INSIDE_IT_LAST_INSN
:
15337 now_it
.block_length
++;
15339 if (now_it
.block_length
> 4
15340 || !now_it_compatible (inst
.cond
))
15342 force_automatic_it_block_close ();
15343 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
15344 new_automatic_it_block (inst
.cond
);
15348 now_it_add_mask (inst
.cond
);
15351 if (now_it
.state
== AUTOMATIC_IT_BLOCK
15352 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
15353 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
15354 close_automatic_it_block ();
15357 case NEUTRAL_IT_INSN
:
15358 now_it
.block_length
++;
15360 if (now_it
.block_length
> 4)
15361 force_automatic_it_block_close ();
15363 now_it_add_mask (now_it
.cc
& 1);
15367 close_automatic_it_block ();
15368 now_it
.state
= MANUAL_IT_BLOCK
;
15373 case MANUAL_IT_BLOCK
:
15375 /* Check conditional suffixes. */
15376 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
15379 now_it
.mask
&= 0x1f;
15380 is_last
= (now_it
.mask
== 0x10);
15382 switch (inst
.it_insn_type
)
15384 case OUTSIDE_IT_INSN
:
15385 inst
.error
= BAD_NOT_IT
;
15388 case INSIDE_IT_INSN
:
15389 if (cond
!= inst
.cond
)
15391 inst
.error
= BAD_IT_COND
;
15396 case INSIDE_IT_LAST_INSN
:
15397 case IF_INSIDE_IT_LAST_INSN
:
15398 if (cond
!= inst
.cond
)
15400 inst
.error
= BAD_IT_COND
;
15405 inst
.error
= BAD_BRANCH
;
15410 case NEUTRAL_IT_INSN
:
15411 /* The BKPT instruction is unconditional even in an IT block. */
15415 inst
.error
= BAD_IT_IT
;
15426 it_fsm_post_encode (void)
15430 if (!now_it
.state_handled
)
15431 handle_it_state ();
15433 is_last
= (now_it
.mask
== 0x10);
15436 now_it
.state
= OUTSIDE_IT_BLOCK
;
15442 force_automatic_it_block_close (void)
15444 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
15446 close_automatic_it_block ();
15447 now_it
.state
= OUTSIDE_IT_BLOCK
;
15455 if (!now_it
.state_handled
)
15456 handle_it_state ();
15458 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
15462 md_assemble (char *str
)
15465 const struct asm_opcode
* opcode
;
15467 /* Align the previous label if needed. */
15468 if (last_label_seen
!= NULL
)
15470 symbol_set_frag (last_label_seen
, frag_now
);
15471 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
15472 S_SET_SEGMENT (last_label_seen
, now_seg
);
15475 memset (&inst
, '\0', sizeof (inst
));
15476 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
15478 opcode
= opcode_lookup (&p
);
15481 /* It wasn't an instruction, but it might be a register alias of
15482 the form alias .req reg, or a Neon .dn/.qn directive. */
15483 if (! create_register_alias (str
, p
)
15484 && ! create_neon_reg_alias (str
, p
))
15485 as_bad (_("bad instruction `%s'"), str
);
15490 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
15491 as_warn (_("s suffix on comparison instruction is deprecated"));
15493 /* The value which unconditional instructions should have in place of the
15494 condition field. */
15495 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
15499 arm_feature_set variant
;
15501 variant
= cpu_variant
;
15502 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
15503 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
15504 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
15505 /* Check that this instruction is supported for this CPU. */
15506 if (!opcode
->tvariant
15507 || (thumb_mode
== 1
15508 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
15510 as_bad (_("selected processor does not support `%s'"), str
);
15513 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
15514 && opcode
->tencode
!= do_t_branch
)
15516 as_bad (_("Thumb does not support conditional execution"));
15520 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
15522 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
15523 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
15524 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
15526 /* Two things are addressed here.
15527 1) Implicit require narrow instructions on Thumb-1.
15528 This avoids relaxation accidentally introducing Thumb-2
15530 2) Reject wide instructions in non Thumb-2 cores. */
15531 if (inst
.size_req
== 0)
15533 else if (inst
.size_req
== 4)
15535 as_bad (_("selected processor does not support `%s'"), str
);
15541 inst
.instruction
= opcode
->tvalue
;
15543 if (!parse_operands (p
, opcode
->operands
))
15545 /* Prepare the it_insn_type for those encodings that don't set
15547 it_fsm_pre_encode ();
15549 opcode
->tencode ();
15551 it_fsm_post_encode ();
15554 if (!(inst
.error
|| inst
.relax
))
15556 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
15557 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
15558 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
15560 as_bad (_("cannot honor width suffix -- `%s'"), str
);
15565 /* Something has gone badly wrong if we try to relax a fixed size
15567 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
15569 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15570 *opcode
->tvariant
);
15571 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
15572 set those bits when Thumb-2 32-bit instructions are seen. ie.
15573 anything other than bl/blx and v6-M instructions.
15574 This is overly pessimistic for relaxable instructions. */
15575 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
15577 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
15578 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
15579 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15584 mapping_state (MAP_THUMB
);
15587 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
15591 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
15592 is_bx
= (opcode
->aencode
== do_bx
);
15594 /* Check that this instruction is supported for this CPU. */
15595 if (!(is_bx
&& fix_v4bx
)
15596 && !(opcode
->avariant
&&
15597 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
15599 as_bad (_("selected processor does not support `%s'"), str
);
15604 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
15608 inst
.instruction
= opcode
->avalue
;
15609 if (opcode
->tag
== OT_unconditionalF
)
15610 inst
.instruction
|= 0xF << 28;
15612 inst
.instruction
|= inst
.cond
<< 28;
15613 inst
.size
= INSN_SIZE
;
15614 if (!parse_operands (p
, opcode
->operands
))
15616 it_fsm_pre_encode ();
15617 opcode
->aencode ();
15618 it_fsm_post_encode ();
15620 /* Arm mode bx is marked as both v4T and v5 because it's still required
15621 on a hypothetical non-thumb v5 core. */
15623 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
15625 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
15626 *opcode
->avariant
);
15629 mapping_state (MAP_ARM
);
15634 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
15642 check_it_blocks_finished (void)
15647 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
15648 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
15649 == MANUAL_IT_BLOCK
)
15651 as_warn (_("section '%s' finished with an open IT block."),
15655 if (now_it
.state
== MANUAL_IT_BLOCK
)
15656 as_warn (_("file finished with an open IT block."));
15660 /* Various frobbings of labels and their addresses. */
15663 arm_start_line_hook (void)
15665 last_label_seen
= NULL
;
15669 arm_frob_label (symbolS
* sym
)
15671 last_label_seen
= sym
;
15673 ARM_SET_THUMB (sym
, thumb_mode
);
15675 #if defined OBJ_COFF || defined OBJ_ELF
15676 ARM_SET_INTERWORK (sym
, support_interwork
);
15679 force_automatic_it_block_close ();
15681 /* Note - do not allow local symbols (.Lxxx) to be labelled
15682 as Thumb functions. This is because these labels, whilst
15683 they exist inside Thumb code, are not the entry points for
15684 possible ARM->Thumb calls. Also, these labels can be used
15685 as part of a computed goto or switch statement. eg gcc
15686 can generate code that looks like this:
15688 ldr r2, [pc, .Laaa]
15698 The first instruction loads the address of the jump table.
15699 The second instruction converts a table index into a byte offset.
15700 The third instruction gets the jump address out of the table.
15701 The fourth instruction performs the jump.
15703 If the address stored at .Laaa is that of a symbol which has the
15704 Thumb_Func bit set, then the linker will arrange for this address
15705 to have the bottom bit set, which in turn would mean that the
15706 address computation performed by the third instruction would end
15707 up with the bottom bit set. Since the ARM is capable of unaligned
15708 word loads, the instruction would then load the incorrect address
15709 out of the jump table, and chaos would ensue. */
15710 if (label_is_thumb_function_name
15711 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
15712 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
15714 /* When the address of a Thumb function is taken the bottom
15715 bit of that address should be set. This will allow
15716 interworking between Arm and Thumb functions to work
15719 THUMB_SET_FUNC (sym
, 1);
15721 label_is_thumb_function_name
= FALSE
;
15724 dwarf2_emit_label (sym
);
15728 arm_data_in_code (void)
15730 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
15732 *input_line_pointer
= '/';
15733 input_line_pointer
+= 5;
15734 *input_line_pointer
= 0;
15742 arm_canonicalize_symbol_name (char * name
)
15746 if (thumb_mode
&& (len
= strlen (name
)) > 5
15747 && streq (name
+ len
- 5, "/data"))
15748 *(name
+ len
- 5) = 0;
15753 /* Table of all register names defined by default. The user can
15754 define additional names with .req. Note that all register names
15755 should appear in both upper and lowercase variants. Some registers
15756 also have mixed-case names. */
15758 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
15759 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
15760 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
15761 #define REGSET(p,t) \
15762 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
15763 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
15764 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
15765 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
15766 #define REGSETH(p,t) \
15767 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
15768 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
15769 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
15770 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
15771 #define REGSET2(p,t) \
15772 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
15773 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
15774 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
15775 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
15777 static const struct reg_entry reg_names
[] =
15779 /* ARM integer registers. */
15780 REGSET(r
, RN
), REGSET(R
, RN
),
15782 /* ATPCS synonyms. */
15783 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
15784 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
15785 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
15787 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
15788 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
15789 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
15791 /* Well-known aliases. */
15792 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
15793 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
15795 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
15796 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
15798 /* Coprocessor numbers. */
15799 REGSET(p
, CP
), REGSET(P
, CP
),
15801 /* Coprocessor register numbers. The "cr" variants are for backward
15803 REGSET(c
, CN
), REGSET(C
, CN
),
15804 REGSET(cr
, CN
), REGSET(CR
, CN
),
15806 /* FPA registers. */
15807 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
15808 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
15810 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
15811 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
15813 /* VFP SP registers. */
15814 REGSET(s
,VFS
), REGSET(S
,VFS
),
15815 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
15817 /* VFP DP Registers. */
15818 REGSET(d
,VFD
), REGSET(D
,VFD
),
15819 /* Extra Neon DP registers. */
15820 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
15822 /* Neon QP registers. */
15823 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
15825 /* VFP control registers. */
15826 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
15827 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
15828 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
15829 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
15830 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
15831 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
15833 /* Maverick DSP coprocessor registers. */
15834 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
15835 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
15837 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
15838 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
15839 REGDEF(dspsc
,0,DSPSC
),
15841 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
15842 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
15843 REGDEF(DSPSC
,0,DSPSC
),
15845 /* iWMMXt data registers - p0, c0-15. */
15846 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
15848 /* iWMMXt control registers - p1, c0-3. */
15849 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
15850 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
15851 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
15852 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
15854 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
15855 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
15856 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
15857 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
15858 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
15860 /* XScale accumulator registers. */
15861 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
15867 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
15868 within psr_required_here. */
15869 static const struct asm_psr psrs
[] =
15871 /* Backward compatibility notation. Note that "all" is no longer
15872 truly all possible PSR bits. */
15873 {"all", PSR_c
| PSR_f
},
15877 /* Individual flags. */
15882 /* Combinations of flags. */
15883 {"fs", PSR_f
| PSR_s
},
15884 {"fx", PSR_f
| PSR_x
},
15885 {"fc", PSR_f
| PSR_c
},
15886 {"sf", PSR_s
| PSR_f
},
15887 {"sx", PSR_s
| PSR_x
},
15888 {"sc", PSR_s
| PSR_c
},
15889 {"xf", PSR_x
| PSR_f
},
15890 {"xs", PSR_x
| PSR_s
},
15891 {"xc", PSR_x
| PSR_c
},
15892 {"cf", PSR_c
| PSR_f
},
15893 {"cs", PSR_c
| PSR_s
},
15894 {"cx", PSR_c
| PSR_x
},
15895 {"fsx", PSR_f
| PSR_s
| PSR_x
},
15896 {"fsc", PSR_f
| PSR_s
| PSR_c
},
15897 {"fxs", PSR_f
| PSR_x
| PSR_s
},
15898 {"fxc", PSR_f
| PSR_x
| PSR_c
},
15899 {"fcs", PSR_f
| PSR_c
| PSR_s
},
15900 {"fcx", PSR_f
| PSR_c
| PSR_x
},
15901 {"sfx", PSR_s
| PSR_f
| PSR_x
},
15902 {"sfc", PSR_s
| PSR_f
| PSR_c
},
15903 {"sxf", PSR_s
| PSR_x
| PSR_f
},
15904 {"sxc", PSR_s
| PSR_x
| PSR_c
},
15905 {"scf", PSR_s
| PSR_c
| PSR_f
},
15906 {"scx", PSR_s
| PSR_c
| PSR_x
},
15907 {"xfs", PSR_x
| PSR_f
| PSR_s
},
15908 {"xfc", PSR_x
| PSR_f
| PSR_c
},
15909 {"xsf", PSR_x
| PSR_s
| PSR_f
},
15910 {"xsc", PSR_x
| PSR_s
| PSR_c
},
15911 {"xcf", PSR_x
| PSR_c
| PSR_f
},
15912 {"xcs", PSR_x
| PSR_c
| PSR_s
},
15913 {"cfs", PSR_c
| PSR_f
| PSR_s
},
15914 {"cfx", PSR_c
| PSR_f
| PSR_x
},
15915 {"csf", PSR_c
| PSR_s
| PSR_f
},
15916 {"csx", PSR_c
| PSR_s
| PSR_x
},
15917 {"cxf", PSR_c
| PSR_x
| PSR_f
},
15918 {"cxs", PSR_c
| PSR_x
| PSR_s
},
15919 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
15920 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
15921 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
15922 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
15923 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
15924 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
15925 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
15926 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
15927 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
15928 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
15929 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
15930 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
15931 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
15932 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
15933 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
15934 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
15935 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
15936 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
15937 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
15938 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
15939 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
15940 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
15941 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
15942 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
15945 /* Table of V7M psr names. */
15946 static const struct asm_psr v7m_psrs
[] =
15948 {"apsr", 0 }, {"APSR", 0 },
15949 {"iapsr", 1 }, {"IAPSR", 1 },
15950 {"eapsr", 2 }, {"EAPSR", 2 },
15951 {"psr", 3 }, {"PSR", 3 },
15952 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
15953 {"ipsr", 5 }, {"IPSR", 5 },
15954 {"epsr", 6 }, {"EPSR", 6 },
15955 {"iepsr", 7 }, {"IEPSR", 7 },
15956 {"msp", 8 }, {"MSP", 8 },
15957 {"psp", 9 }, {"PSP", 9 },
15958 {"primask", 16}, {"PRIMASK", 16},
15959 {"basepri", 17}, {"BASEPRI", 17},
15960 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
15961 {"faultmask", 19}, {"FAULTMASK", 19},
15962 {"control", 20}, {"CONTROL", 20}
15965 /* Table of all shift-in-operand names. */
15966 static const struct asm_shift_name shift_names
[] =
15968 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
15969 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
15970 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
15971 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
15972 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
15973 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
15976 /* Table of all explicit relocation names. */
15978 static struct reloc_entry reloc_names
[] =
15980 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
15981 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
15982 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
15983 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
15984 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
15985 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
15986 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
15987 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
15988 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
15989 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
15990 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
15994 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
15995 static const struct asm_cond conds
[] =
15999 {"cs", 0x2}, {"hs", 0x2},
16000 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16014 static struct asm_barrier_opt barrier_opt_names
[] =
16022 /* Table of ARM-format instructions. */
16024 /* Macros for gluing together operand strings. N.B. In all cases
16025 other than OPS0, the trailing OP_stop comes from default
16026 zero-initialization of the unspecified elements of the array. */
16027 #define OPS0() { OP_stop, }
16028 #define OPS1(a) { OP_##a, }
16029 #define OPS2(a,b) { OP_##a,OP_##b, }
16030 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16031 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16032 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16033 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16035 /* These macros abstract out the exact format of the mnemonic table and
16036 save some repeated characters. */
16038 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16039 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16040 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16041 THUMB_VARIANT, do_##ae, do_##te }
16043 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16044 a T_MNEM_xyz enumerator. */
16045 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16046 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16047 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16048 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16050 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16051 infix after the third character. */
16052 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16053 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16054 THUMB_VARIANT, do_##ae, do_##te }
16055 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16056 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16057 THUMB_VARIANT, do_##ae, do_##te }
16058 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16059 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16060 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16061 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16062 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16063 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16064 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16065 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16067 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16068 appear in the condition table. */
16069 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16070 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16071 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16073 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16074 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16075 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16076 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16077 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16078 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16079 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16080 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16081 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16082 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16083 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16084 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16085 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16086 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16087 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16088 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16089 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16090 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16091 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16092 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16094 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16095 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16096 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16097 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16099 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16100 field is still 0xE. Many of the Thumb variants can be executed
16101 conditionally, so this is checked separately. */
16102 #define TUE(mnem, op, top, nops, ops, ae, te) \
16103 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16104 THUMB_VARIANT, do_##ae, do_##te }
16106 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16107 condition code field. */
16108 #define TUF(mnem, op, top, nops, ops, ae, te) \
16109 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16110 THUMB_VARIANT, do_##ae, do_##te }
16112 /* ARM-only variants of all the above. */
16113 #define CE(mnem, op, nops, ops, ae) \
16114 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16116 #define C3(mnem, op, nops, ops, ae) \
16117 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16119 /* Legacy mnemonics that always have conditional infix after the third
16121 #define CL(mnem, op, nops, ops, ae) \
16122 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16123 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16125 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16126 #define cCE(mnem, op, nops, ops, ae) \
16127 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16129 /* Legacy coprocessor instructions where conditional infix and conditional
16130 suffix are ambiguous. For consistency this includes all FPA instructions,
16131 not just the potentially ambiguous ones. */
16132 #define cCL(mnem, op, nops, ops, ae) \
16133 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16134 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16136 /* Coprocessor, takes either a suffix or a position-3 infix
16137 (for an FPA corner case). */
16138 #define C3E(mnem, op, nops, ops, ae) \
16139 { mnem, OPS##nops ops, OT_csuf_or_in3, \
16140 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16142 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
16143 { m1 #m2 m3, OPS##nops ops, \
16144 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16145 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16147 #define CM(m1, m2, op, nops, ops, ae) \
16148 xCM_ (m1, , m2, op, nops, ops, ae), \
16149 xCM_ (m1, eq, m2, op, nops, ops, ae), \
16150 xCM_ (m1, ne, m2, op, nops, ops, ae), \
16151 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16152 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16153 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16154 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16155 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16156 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16157 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16158 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16159 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16160 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16161 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16162 xCM_ (m1, ge, m2, op, nops, ops, ae), \
16163 xCM_ (m1, lt, m2, op, nops, ops, ae), \
16164 xCM_ (m1, gt, m2, op, nops, ops, ae), \
16165 xCM_ (m1, le, m2, op, nops, ops, ae), \
16166 xCM_ (m1, al, m2, op, nops, ops, ae)
16168 #define UE(mnem, op, nops, ops, ae) \
16169 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16171 #define UF(mnem, op, nops, ops, ae) \
16172 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16174 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
16175 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
16176 use the same encoding function for each. */
16177 #define NUF(mnem, op, nops, ops, enc) \
16178 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
16179 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16181 /* Neon data processing, version which indirects through neon_enc_tab for
16182 the various overloaded versions of opcodes. */
16183 #define nUF(mnem, op, nops, ops, enc) \
16184 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
16185 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16187 /* Neon insn with conditional suffix for the ARM version, non-overloaded
16189 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
16190 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
16191 THUMB_VARIANT, do_##enc, do_##enc }
16193 #define NCE(mnem, op, nops, ops, enc) \
16194 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16196 #define NCEF(mnem, op, nops, ops, enc) \
16197 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16199 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
16200 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
16201 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
16202 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16204 #define nCE(mnem, op, nops, ops, enc) \
16205 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16207 #define nCEF(mnem, op, nops, ops, enc) \
16208 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16212 /* Thumb-only, unconditional. */
16213 #define UT(mnem, op, nops, ops, te) TUE (mnem, 0, op, nops, ops, 0, te)
16215 static const struct asm_opcode insns
[] =
16217 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
16218 #define THUMB_VARIANT &arm_ext_v4t
16219 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16220 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16221 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16222 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16223 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16224 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16225 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16226 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16227 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16228 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16229 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16230 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16231 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16232 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16233 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16234 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16236 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
16237 for setting PSR flag bits. They are obsolete in V6 and do not
16238 have Thumb equivalents. */
16239 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16240 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16241 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
16242 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16243 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16244 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
16245 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16246 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16247 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
16249 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16250 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16251 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16252 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16254 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16255 tC3("ldrb", 4500000, _ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16256 tCE("str", 4000000, _str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16257 tC3("strb", 4400000, _strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16259 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16260 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16261 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16262 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16263 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16264 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16266 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16267 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16268 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
16269 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
16272 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
16273 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
16274 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
16276 /* Thumb-compatibility pseudo ops. */
16277 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16278 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16279 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16280 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16281 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16282 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16283 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16284 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16285 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
16286 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
16287 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
16288 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
16290 /* These may simplify to neg. */
16291 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16292 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16294 #undef THUMB_VARIANT
16295 #define THUMB_VARIANT & arm_ext_v6
16297 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
16299 /* V1 instructions with no Thumb analogue prior to V6T2. */
16300 #undef THUMB_VARIANT
16301 #define THUMB_VARIANT & arm_ext_v6t2
16303 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16304 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16305 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
16307 TC3("ldrt", 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16308 TC3("ldrbt", 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16309 TC3("strt", 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16310 TC3("strbt", 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16312 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16313 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16315 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16316 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16318 /* V1 instructions with no Thumb analogue at all. */
16319 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
16320 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
16322 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16323 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16324 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16325 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16326 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16327 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16328 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16329 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16332 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
16333 #undef THUMB_VARIANT
16334 #define THUMB_VARIANT & arm_ext_v4t
16336 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16337 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16339 #undef THUMB_VARIANT
16340 #define THUMB_VARIANT & arm_ext_v6t2
16342 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16343 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
16345 /* Generic coprocessor instructions. */
16346 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16347 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16348 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16349 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16350 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16351 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16352 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16355 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
16357 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16358 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16361 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
16362 #undef THUMB_VARIANT
16363 #define THUMB_VARIANT & arm_ext_msr
16365 TCE("mrs", 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
16366 TCE("msr", 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
16369 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
16370 #undef THUMB_VARIANT
16371 #define THUMB_VARIANT & arm_ext_v6t2
16373 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16374 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16375 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16376 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16377 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16378 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16379 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16380 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16383 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
16384 #undef THUMB_VARIANT
16385 #define THUMB_VARIANT & arm_ext_v4t
16387 tC3("ldrh", 01000b0
, _ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16388 tC3("strh", 00000b0
, _strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16389 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16390 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16391 tCM("ld","sh", 01000f0
, _ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16392 tCM("ld","sb", 01000d0
, _ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16395 #define ARM_VARIANT & arm_ext_v4t_5
16397 /* ARM Architecture 4T. */
16398 /* Note: bx (and blx) are required on V5, even if the processor does
16399 not support Thumb. */
16400 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
16403 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
16404 #undef THUMB_VARIANT
16405 #define THUMB_VARIANT & arm_ext_v5t
16407 /* Note: blx has 2 variants; the .value coded here is for
16408 BLX(2). Only this variant has conditional execution. */
16409 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
16410 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
16412 #undef THUMB_VARIANT
16413 #define THUMB_VARIANT & arm_ext_v6t2
16415 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
16416 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16417 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16418 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16419 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16420 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16421 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16422 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16425 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
16427 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16428 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16429 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16430 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16432 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16433 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16435 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16436 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16437 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16438 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16440 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16441 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16442 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16443 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16445 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16446 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16448 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
16449 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
16450 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
16451 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
16454 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
16456 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
16457 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
16458 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
16460 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16461 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16464 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
16466 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
16469 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
16470 #undef THUMB_VARIANT
16471 #define THUMB_VARIANT & arm_ext_v6
16473 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16474 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16475 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16476 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16477 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16478 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16479 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16480 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16481 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16482 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
16484 #undef THUMB_VARIANT
16485 #define THUMB_VARIANT & arm_ext_v6t2
16487 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
16488 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
16489 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16490 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16492 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
16493 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
16495 /* ARM V6 not included in V7M (eg. integer SIMD). */
16496 #undef THUMB_VARIANT
16497 #define THUMB_VARIANT & arm_ext_v6_notm
16499 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
16500 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
16501 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
16502 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16503 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16504 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16505 /* Old name for QASX. */
16506 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16507 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16508 /* Old name for QSAX. */
16509 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16510 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16511 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16512 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16513 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16514 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16515 /* Old name for SASX. */
16516 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16517 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16518 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16519 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16520 /* Old name for SHASX. */
16521 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16522 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16523 /* Old name for SHSAX. */
16524 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16525 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16526 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16527 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16528 /* Old name for SSAX. */
16529 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16530 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16531 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16532 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16533 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16534 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16535 /* Old name for UASX. */
16536 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16537 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16538 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16539 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16540 /* Old name for UHASX. */
16541 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16542 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16543 /* Old name for UHSAX. */
16544 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16545 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16546 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16547 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16548 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16549 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16550 /* Old name for UQASX. */
16551 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16552 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16553 /* Old name for UQSAX. */
16554 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16555 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16556 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16557 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16558 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16559 /* Old name for USAX. */
16560 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16561 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16562 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16563 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
16564 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
16565 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16566 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16567 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
16568 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
16569 TUF("rfeed", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16570 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16571 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16572 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16573 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16574 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16575 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16576 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16577 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16578 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16579 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16580 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16581 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16582 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16583 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16584 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16585 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16586 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16587 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16588 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16589 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16590 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16591 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16592 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16593 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16594 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16595 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16596 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16597 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
16598 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
16599 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
16600 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
16601 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
16602 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
16603 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16604 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16605 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
16608 #define ARM_VARIANT & arm_ext_v6k
16609 #undef THUMB_VARIANT
16610 #define THUMB_VARIANT & arm_ext_v6k
16612 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
16613 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
16614 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
16615 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
16617 #undef THUMB_VARIANT
16618 #define THUMB_VARIANT & arm_ext_v6_notm
16620 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
16621 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
16623 #undef THUMB_VARIANT
16624 #define THUMB_VARIANT & arm_ext_v6t2
16626 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
16627 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
16628 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
16629 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
16630 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
16633 #define ARM_VARIANT & arm_ext_v6z
16635 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
16638 #define ARM_VARIANT & arm_ext_v6t2
16640 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
16641 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
16642 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
16643 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
16645 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16646 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
16647 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
16648 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
16650 TC3("ldrht", 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16651 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16652 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16653 TC3("strht", 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16655 UT("cbnz", b900
, 2, (RR
, EXP
), t_cbz
),
16656 UT("cbz", b100
, 2, (RR
, EXP
), t_cbz
),
16658 /* ARM does not really have an IT instruction, so always allow it.
16659 The opcode is copied from Thumb in order to allow warnings in
16660 -mimplicit-it=[never | arm] modes. */
16662 #define ARM_VARIANT & arm_ext_v1
16664 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
16665 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
16666 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
16667 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
16668 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
16669 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
16670 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
16671 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
16672 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
16673 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
16674 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
16675 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
16676 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
16677 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
16678 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
16679 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
16680 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
16681 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
16683 /* Thumb2 only instructions. */
16685 #define ARM_VARIANT NULL
16687 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
16688 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
16689 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
16690 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
16691 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
16692 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
16694 /* Thumb-2 hardware division instructions (R and M profiles only). */
16695 #undef THUMB_VARIANT
16696 #define THUMB_VARIANT & arm_ext_div
16698 TCE("sdiv", 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
16699 TCE("udiv", 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
16701 /* ARM V6M/V7 instructions. */
16703 #define ARM_VARIANT & arm_ext_barrier
16704 #undef THUMB_VARIANT
16705 #define THUMB_VARIANT & arm_ext_barrier
16707 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
16708 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
16709 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
16711 /* ARM V7 instructions. */
16713 #define ARM_VARIANT & arm_ext_v7
16714 #undef THUMB_VARIANT
16715 #define THUMB_VARIANT & arm_ext_v7
16717 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
16718 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
16721 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
16723 cCE("wfs", e200110
, 1, (RR
), rd
),
16724 cCE("rfs", e300110
, 1, (RR
), rd
),
16725 cCE("wfc", e400110
, 1, (RR
), rd
),
16726 cCE("rfc", e500110
, 1, (RR
), rd
),
16728 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16729 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16730 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16731 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16733 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16734 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16735 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16736 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16738 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
16739 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
16740 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
16741 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
16742 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
16743 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
16744 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
16745 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
16746 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
16747 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
16748 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
16749 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
16751 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
16752 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
16753 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
16754 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
16755 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
16756 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
16757 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
16758 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
16759 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
16760 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
16761 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
16762 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
16764 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
16765 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
16766 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
16767 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
16768 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
16769 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
16770 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
16771 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
16772 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
16773 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
16774 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
16775 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
16777 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
16778 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
16779 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
16780 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
16781 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
16782 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
16783 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
16784 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
16785 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
16786 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
16787 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
16788 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
16790 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
16791 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
16792 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
16793 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
16794 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
16795 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
16796 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
16797 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
16798 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
16799 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
16800 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
16801 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
16803 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
16804 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
16805 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
16806 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
16807 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
16808 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
16809 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
16810 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
16811 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
16812 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
16813 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
16814 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
16816 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
16817 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
16818 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
16819 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
16820 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
16821 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
16822 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
16823 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
16824 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
16825 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
16826 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
16827 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
16829 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
16830 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
16831 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
16832 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
16833 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
16834 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
16835 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
16836 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
16837 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
16838 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
16839 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
16840 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
16842 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
16843 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
16844 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
16845 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
16846 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
16847 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
16848 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
16849 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
16850 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
16851 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
16852 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
16853 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
16855 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
16856 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
16857 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
16858 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
16859 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
16860 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
16861 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
16862 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
16863 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
16864 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
16865 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
16866 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
16868 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
16869 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
16870 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
16871 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
16872 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
16873 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
16874 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
16875 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
16876 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
16877 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
16878 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
16879 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
16881 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
16882 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
16883 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
16884 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
16885 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
16886 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
16887 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
16888 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
16889 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
16890 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
16891 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
16892 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
16894 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
16895 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
16896 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
16897 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
16898 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
16899 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
16900 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
16901 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
16902 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
16903 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
16904 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
16905 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
16907 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
16908 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
16909 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
16910 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
16911 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
16912 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
16913 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
16914 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
16915 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
16916 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
16917 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
16918 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
16920 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
16921 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
16922 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
16923 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
16924 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
16925 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
16926 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
16927 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
16928 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
16929 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
16930 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
16931 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
16933 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
16934 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
16935 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
16936 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
16937 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
16938 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
16939 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
16940 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
16941 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
16942 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
16943 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
16944 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
16946 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16947 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16948 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16949 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16950 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16951 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16952 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16953 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16954 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16955 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16956 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16957 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16959 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16960 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16961 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16962 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16963 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16964 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16965 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16966 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16967 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16968 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16969 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16970 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16972 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16973 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16974 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16975 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16976 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16977 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16978 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16979 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16980 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16981 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16982 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16983 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16985 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16986 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16987 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16988 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16989 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16990 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16991 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16992 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16993 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16994 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16995 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16996 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16998 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16999 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17000 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17001 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17002 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17003 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17004 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17005 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17006 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17007 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17008 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17009 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17011 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17012 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17013 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17014 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17015 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17016 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17017 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17018 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17019 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17020 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17021 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17022 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17024 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17025 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17026 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17027 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17028 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17029 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17030 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17031 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17032 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17033 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17034 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17035 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17037 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17038 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17039 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17040 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17041 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17042 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17043 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17044 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17045 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17046 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17047 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17048 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17050 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17051 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17052 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17053 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17054 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17055 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17056 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17057 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17058 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17059 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17060 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17061 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17063 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17064 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17065 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17066 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17067 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17068 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17069 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17070 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17071 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17072 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17073 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17074 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17076 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17077 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17078 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17079 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17080 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17081 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17082 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17083 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17084 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17085 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17086 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17087 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17089 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17090 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17091 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17092 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17093 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17094 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17095 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17096 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17097 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17098 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17099 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17100 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17102 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17103 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17104 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17105 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17106 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17107 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17108 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17109 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17110 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17111 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17112 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17113 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17115 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17116 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17117 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17118 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17120 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
17121 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
17122 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
17123 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
17124 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
17125 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
17126 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
17127 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
17128 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
17129 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
17130 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
17131 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
17133 /* The implementation of the FIX instruction is broken on some
17134 assemblers, in that it accepts a precision specifier as well as a
17135 rounding specifier, despite the fact that this is meaningless.
17136 To be more compatible, we accept it as well, though of course it
17137 does not set any bits. */
17138 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
17139 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
17140 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
17141 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
17142 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
17143 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
17144 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
17145 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
17146 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
17147 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
17148 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
17149 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
17150 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
17152 /* Instructions that were new with the real FPA, call them V2. */
17154 #define ARM_VARIANT & fpu_fpa_ext_v2
17156 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17157 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17158 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17159 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17160 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17161 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17164 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
17166 /* Moves and type conversions. */
17167 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17168 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
17169 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
17170 cCE("fmstat", ef1fa10
, 0, (), noargs
),
17171 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17172 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17173 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17174 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17175 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17176 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17177 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
17178 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
17180 /* Memory operations. */
17181 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17182 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17183 cCE("fldmias", c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17184 cCE("fldmfds", c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17185 cCE("fldmdbs", d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17186 cCE("fldmeas", d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17187 cCE("fldmiax", c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17188 cCE("fldmfdx", c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17189 cCE("fldmdbx", d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17190 cCE("fldmeax", d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17191 cCE("fstmias", c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17192 cCE("fstmeas", c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17193 cCE("fstmdbs", d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17194 cCE("fstmfds", d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17195 cCE("fstmiax", c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17196 cCE("fstmeax", c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17197 cCE("fstmdbx", d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17198 cCE("fstmfdx", d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17200 /* Monadic operations. */
17201 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17202 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17203 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17205 /* Dyadic operations. */
17206 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17207 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17208 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17209 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17210 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17211 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17212 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17213 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17214 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17217 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17218 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
17219 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17220 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
17222 /* Double precision load/store are still present on single precision
17223 implementations. */
17224 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17225 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17226 cCE("fldmiad", c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17227 cCE("fldmfdd", c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17228 cCE("fldmdbd", d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17229 cCE("fldmead", d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17230 cCE("fstmiad", c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17231 cCE("fstmead", c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17232 cCE("fstmdbd", d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17233 cCE("fstmfdd", d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17236 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
17238 /* Moves and type conversions. */
17239 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17240 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17241 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17242 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17243 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17244 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17245 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17246 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17247 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17248 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17249 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17250 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17251 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17253 /* Monadic operations. */
17254 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17255 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17256 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17258 /* Dyadic operations. */
17259 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17260 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17261 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17262 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17263 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17264 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17265 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17266 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17267 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17270 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17271 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
17272 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17273 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
17276 #define ARM_VARIANT & fpu_vfp_ext_v2
17278 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
17279 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
17280 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
17281 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
17283 /* Instructions which may belong to either the Neon or VFP instruction sets.
17284 Individual encoder functions perform additional architecture checks. */
17286 #define ARM_VARIANT & fpu_vfp_ext_v1xd
17287 #undef THUMB_VARIANT
17288 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
17290 /* These mnemonics are unique to VFP. */
17291 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
17292 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
17293 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17294 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17295 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17296 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17297 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17298 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
17299 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
17300 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
17302 /* Mnemonics shared by Neon and VFP. */
17303 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
17304 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17305 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17307 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17308 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17310 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17311 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17313 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17314 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17315 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17316 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17317 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17318 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17319 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17320 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17322 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
17323 nCEF(vcvtb
, _vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
17324 nCEF(vcvtt
, _vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
17327 /* NOTE: All VMOV encoding is special-cased! */
17328 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
17329 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
17331 #undef THUMB_VARIANT
17332 #define THUMB_VARIANT & fpu_neon_ext_v1
17334 #define ARM_VARIANT & fpu_neon_ext_v1
17336 /* Data processing with three registers of the same length. */
17337 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
17338 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
17339 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
17340 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17341 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17342 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17343 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17344 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17345 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17346 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
17347 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17348 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17349 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17350 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17351 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17352 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17353 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17354 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17355 /* If not immediate, fall back to neon_dyadic_i64_su.
17356 shl_imm should accept I8 I16 I32 I64,
17357 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
17358 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
17359 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
17360 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
17361 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
17362 /* Logic ops, types optional & ignored. */
17363 nUF(vand
, _vand
, 2, (RNDQ
, NILO
), neon_logic
),
17364 nUF(vandq
, _vand
, 2, (RNQ
, NILO
), neon_logic
),
17365 nUF(vbic
, _vbic
, 2, (RNDQ
, NILO
), neon_logic
),
17366 nUF(vbicq
, _vbic
, 2, (RNQ
, NILO
), neon_logic
),
17367 nUF(vorr
, _vorr
, 2, (RNDQ
, NILO
), neon_logic
),
17368 nUF(vorrq
, _vorr
, 2, (RNQ
, NILO
), neon_logic
),
17369 nUF(vorn
, _vorn
, 2, (RNDQ
, NILO
), neon_logic
),
17370 nUF(vornq
, _vorn
, 2, (RNQ
, NILO
), neon_logic
),
17371 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
17372 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
17373 /* Bitfield ops, untyped. */
17374 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17375 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17376 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17377 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17378 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17379 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17380 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
17381 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17382 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17383 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17384 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17385 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17386 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17387 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
17388 back to neon_dyadic_if_su. */
17389 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17390 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17391 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17392 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17393 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17394 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17395 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17396 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17397 /* Comparison. Type I8 I16 I32 F32. */
17398 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
17399 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
17400 /* As above, D registers only. */
17401 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17402 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17403 /* Int and float variants, signedness unimportant. */
17404 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17405 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17406 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
17407 /* Add/sub take types I8 I16 I32 I64 F32. */
17408 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17409 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17410 /* vtst takes sizes 8, 16, 32. */
17411 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
17412 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
17413 /* VMUL takes I8 I16 I32 F32 P8. */
17414 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
17415 /* VQD{R}MULH takes S16 S32. */
17416 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17417 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17418 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17419 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17420 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17421 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17422 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17423 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17424 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17425 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17426 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17427 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17428 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17429 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17430 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17431 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17433 /* Two address, int/float. Types S8 S16 S32 F32. */
17434 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17435 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17437 /* Data processing with two registers and a shift amount. */
17438 /* Right shifts, and variants with rounding.
17439 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
17440 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17441 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17442 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17443 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17444 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17445 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17446 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17447 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17448 /* Shift and insert. Sizes accepted 8 16 32 64. */
17449 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
17450 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
17451 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
17452 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
17453 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
17454 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
17455 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
17456 /* Right shift immediate, saturating & narrowing, with rounding variants.
17457 Types accepted S16 S32 S64 U16 U32 U64. */
17458 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17459 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17460 /* As above, unsigned. Types accepted S16 S32 S64. */
17461 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17462 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17463 /* Right shift narrowing. Types accepted I16 I32 I64. */
17464 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17465 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17466 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
17467 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
17468 /* CVT with optional immediate for fixed-point variant. */
17469 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
17471 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_IMVNb
), neon_mvn
),
17472 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_IMVNb
), neon_mvn
),
17474 /* Data processing, three registers of different lengths. */
17475 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
17476 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
17477 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17478 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17479 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17480 /* If not scalar, fall back to neon_dyadic_long.
17481 Vector types as above, scalar types S16 S32 U16 U32. */
17482 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17483 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17484 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
17485 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17486 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17487 /* Dyadic, narrowing insns. Types I16 I32 I64. */
17488 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17489 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17490 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17491 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17492 /* Saturating doubling multiplies. Types S16 S32. */
17493 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17494 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17495 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17496 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
17497 S16 S32 U16 U32. */
17498 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
17500 /* Extract. Size 8. */
17501 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
17502 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
17504 /* Two registers, miscellaneous. */
17505 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
17506 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
17507 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
17508 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
17509 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
17510 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
17511 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
17512 /* Vector replicate. Sizes 8 16 32. */
17513 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
17514 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
17515 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
17516 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
17517 /* VMOVN. Types I16 I32 I64. */
17518 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
17519 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
17520 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
17521 /* VQMOVUN. Types S16 S32 S64. */
17522 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
17523 /* VZIP / VUZP. Sizes 8 16 32. */
17524 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17525 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17526 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17527 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17528 /* VQABS / VQNEG. Types S8 S16 S32. */
17529 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17530 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17531 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17532 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17533 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
17534 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17535 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
17536 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17537 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
17538 /* Reciprocal estimates. Types U32 F32. */
17539 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17540 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
17541 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17542 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
17543 /* VCLS. Types S8 S16 S32. */
17544 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
17545 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
17546 /* VCLZ. Types I8 I16 I32. */
17547 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
17548 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
17549 /* VCNT. Size 8. */
17550 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
17551 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
17552 /* Two address, untyped. */
17553 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
17554 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
17555 /* VTRN. Sizes 8 16 32. */
17556 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
17557 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
17559 /* Table lookup. Size 8. */
17560 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17561 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17563 #undef THUMB_VARIANT
17564 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
17566 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
17568 /* Neon element/structure load/store. */
17569 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17570 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17571 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17572 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17573 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17574 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17575 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17576 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17578 #undef THUMB_VARIANT
17579 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
17581 #define ARM_VARIANT &fpu_vfp_ext_v3xd
17582 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
17583 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17584 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17585 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17586 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17587 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17588 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17589 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17590 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17592 #undef THUMB_VARIANT
17593 #define THUMB_VARIANT & fpu_vfp_ext_v3
17595 #define ARM_VARIANT & fpu_vfp_ext_v3
17597 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
17598 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17599 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17600 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17601 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17602 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17603 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17604 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17605 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17608 #define ARM_VARIANT &fpu_vfp_ext_fma
17609 #undef THUMB_VARIANT
17610 #define THUMB_VARIANT &fpu_vfp_ext_fma
17611 /* Mnemonics shared by Neon and VFP. These are included in the
17612 VFP FMA variant; NEON and VFP FMA always includes the NEON
17613 FMA instructions. */
17614 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
17615 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
17616 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
17617 the v form should always be used. */
17618 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17619 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17620 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17621 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17622 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17623 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17625 #undef THUMB_VARIANT
17627 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
17629 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17630 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17631 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17632 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17633 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17634 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17635 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
17636 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
17639 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
17641 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
17642 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
17643 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
17644 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
17645 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
17646 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
17647 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
17648 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
17649 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
17650 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17651 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17652 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17653 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17654 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17655 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17656 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17657 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17658 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17659 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
17660 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
17661 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17662 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17663 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17664 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17665 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17666 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17667 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
17668 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
17669 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
17670 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
17671 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
17672 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
17673 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
17674 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
17675 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17676 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17677 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17678 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17679 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17680 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17681 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17682 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17683 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17684 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17685 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17686 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17687 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
17688 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17689 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17690 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17691 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17692 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17693 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17694 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17695 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17696 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17697 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17698 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17699 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17700 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17701 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17702 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17703 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17704 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17705 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17706 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17707 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17708 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17709 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
17710 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
17711 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17712 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17713 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17714 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17715 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17716 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17717 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17718 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17719 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17720 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17721 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17722 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17723 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17724 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17725 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17726 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17727 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17728 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17729 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
17730 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17731 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17732 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17733 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17734 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17735 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17736 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17737 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17738 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17739 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17740 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17741 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17742 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17743 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17744 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17745 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17746 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17747 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17748 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17749 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17750 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17751 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
17752 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17753 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17754 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17755 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17756 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17757 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17758 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17759 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17760 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17761 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17762 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17763 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17764 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17765 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17766 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17767 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17768 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17769 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17770 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17771 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17772 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
17773 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
17774 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17775 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17776 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17777 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17778 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17779 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17780 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17781 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17782 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17783 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17784 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17785 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17786 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17787 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17788 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17789 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17790 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17791 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17792 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17793 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17794 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17795 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17796 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17797 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17798 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17799 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17800 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17801 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17802 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
17805 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
17807 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
17808 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
17809 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
17810 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17811 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17812 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17813 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17814 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17815 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17816 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17817 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17818 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17819 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17820 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17821 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17822 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17823 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17824 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17825 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17826 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17827 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
17828 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17829 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17830 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17831 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17832 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17833 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17834 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17835 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17836 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17837 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17838 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17839 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17840 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17841 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17842 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17843 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17844 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17845 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17846 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17847 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17848 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17849 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17850 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17851 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17852 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17853 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17854 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17855 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17856 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17857 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17858 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17859 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17860 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17861 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17862 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17863 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17866 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
17868 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
17869 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
17870 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
17871 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
17872 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
17873 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
17874 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
17875 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
17876 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
17877 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
17878 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
17879 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
17880 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
17881 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
17882 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
17883 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
17884 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
17885 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
17886 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
17887 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
17888 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
17889 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
17890 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
17891 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
17892 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
17893 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
17894 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
17895 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
17896 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
17897 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
17898 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
17899 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
17900 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
17901 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
17902 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
17903 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
17904 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
17905 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
17906 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
17907 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
17908 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
17909 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
17910 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
17911 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
17912 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
17913 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
17914 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
17915 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
17916 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
17917 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
17918 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
17919 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
17920 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
17921 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
17922 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
17923 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
17924 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
17925 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
17926 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
17927 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
17928 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
17929 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
17930 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
17931 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
17932 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17933 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
17934 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17935 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
17936 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17937 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
17938 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17939 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17940 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
17941 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
17942 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
17943 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
17946 #undef THUMB_VARIANT
17973 /* MD interface: bits in the object file. */
17975 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
17976 for use in the a.out file, and stores them in the array pointed to by buf.
17977 This knows about the endian-ness of the target machine and does
17978 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
17979 2 (short) and 4 (long) Floating numbers are put out as a series of
17980 LITTLENUMS (shorts, here at least). */
17983 md_number_to_chars (char * buf
, valueT val
, int n
)
17985 if (target_big_endian
)
17986 number_to_chars_bigendian (buf
, val
, n
);
17988 number_to_chars_littleendian (buf
, val
, n
);
17992 md_chars_to_number (char * buf
, int n
)
17995 unsigned char * where
= (unsigned char *) buf
;
17997 if (target_big_endian
)
18002 result
|= (*where
++ & 255);
18010 result
|= (where
[n
] & 255);
18017 /* MD interface: Sections. */
18019 /* Estimate the size of a frag before relaxing. Assume everything fits in
18023 md_estimate_size_before_relax (fragS
* fragp
,
18024 segT segtype ATTRIBUTE_UNUSED
)
18030 /* Convert a machine dependent frag. */
18033 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
18035 unsigned long insn
;
18036 unsigned long old_op
;
18044 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18046 old_op
= bfd_get_16(abfd
, buf
);
18047 if (fragp
->fr_symbol
)
18049 exp
.X_op
= O_symbol
;
18050 exp
.X_add_symbol
= fragp
->fr_symbol
;
18054 exp
.X_op
= O_constant
;
18056 exp
.X_add_number
= fragp
->fr_offset
;
18057 opcode
= fragp
->fr_subtype
;
18060 case T_MNEM_ldr_pc
:
18061 case T_MNEM_ldr_pc2
:
18062 case T_MNEM_ldr_sp
:
18063 case T_MNEM_str_sp
:
18070 if (fragp
->fr_var
== 4)
18072 insn
= THUMB_OP32 (opcode
);
18073 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
18075 insn
|= (old_op
& 0x700) << 4;
18079 insn
|= (old_op
& 7) << 12;
18080 insn
|= (old_op
& 0x38) << 13;
18082 insn
|= 0x00000c00;
18083 put_thumb32_insn (buf
, insn
);
18084 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
18088 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
18090 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
18093 if (fragp
->fr_var
== 4)
18095 insn
= THUMB_OP32 (opcode
);
18096 insn
|= (old_op
& 0xf0) << 4;
18097 put_thumb32_insn (buf
, insn
);
18098 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
18102 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18103 exp
.X_add_number
-= 4;
18111 if (fragp
->fr_var
== 4)
18113 int r0off
= (opcode
== T_MNEM_mov
18114 || opcode
== T_MNEM_movs
) ? 0 : 8;
18115 insn
= THUMB_OP32 (opcode
);
18116 insn
= (insn
& 0xe1ffffff) | 0x10000000;
18117 insn
|= (old_op
& 0x700) << r0off
;
18118 put_thumb32_insn (buf
, insn
);
18119 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18123 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
18128 if (fragp
->fr_var
== 4)
18130 insn
= THUMB_OP32(opcode
);
18131 put_thumb32_insn (buf
, insn
);
18132 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
18135 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
18139 if (fragp
->fr_var
== 4)
18141 insn
= THUMB_OP32(opcode
);
18142 insn
|= (old_op
& 0xf00) << 14;
18143 put_thumb32_insn (buf
, insn
);
18144 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
18147 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
18150 case T_MNEM_add_sp
:
18151 case T_MNEM_add_pc
:
18152 case T_MNEM_inc_sp
:
18153 case T_MNEM_dec_sp
:
18154 if (fragp
->fr_var
== 4)
18156 /* ??? Choose between add and addw. */
18157 insn
= THUMB_OP32 (opcode
);
18158 insn
|= (old_op
& 0xf0) << 4;
18159 put_thumb32_insn (buf
, insn
);
18160 if (opcode
== T_MNEM_add_pc
)
18161 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
18163 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18166 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18174 if (fragp
->fr_var
== 4)
18176 insn
= THUMB_OP32 (opcode
);
18177 insn
|= (old_op
& 0xf0) << 4;
18178 insn
|= (old_op
& 0xf) << 16;
18179 put_thumb32_insn (buf
, insn
);
18180 if (insn
& (1 << 20))
18181 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18183 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18186 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18192 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
18193 (enum bfd_reloc_code_real
) reloc_type
);
18194 fixp
->fx_file
= fragp
->fr_file
;
18195 fixp
->fx_line
= fragp
->fr_line
;
18196 fragp
->fr_fix
+= fragp
->fr_var
;
18199 /* Return the size of a relaxable immediate operand instruction.
18200 SHIFT and SIZE specify the form of the allowable immediate. */
18202 relax_immediate (fragS
*fragp
, int size
, int shift
)
18208 /* ??? Should be able to do better than this. */
18209 if (fragp
->fr_symbol
)
18212 low
= (1 << shift
) - 1;
18213 mask
= (1 << (shift
+ size
)) - (1 << shift
);
18214 offset
= fragp
->fr_offset
;
18215 /* Force misaligned offsets to 32-bit variant. */
18218 if (offset
& ~mask
)
18223 /* Get the address of a symbol during relaxation. */
18225 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
18231 sym
= fragp
->fr_symbol
;
18232 sym_frag
= symbol_get_frag (sym
);
18233 know (S_GET_SEGMENT (sym
) != absolute_section
18234 || sym_frag
== &zero_address_frag
);
18235 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
18237 /* If frag has yet to be reached on this pass, assume it will
18238 move by STRETCH just as we did. If this is not so, it will
18239 be because some frag between grows, and that will force
18243 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
18247 /* Adjust stretch for any alignment frag. Note that if have
18248 been expanding the earlier code, the symbol may be
18249 defined in what appears to be an earlier frag. FIXME:
18250 This doesn't handle the fr_subtype field, which specifies
18251 a maximum number of bytes to skip when doing an
18253 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
18255 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
18258 stretch
= - ((- stretch
)
18259 & ~ ((1 << (int) f
->fr_offset
) - 1));
18261 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
18273 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
18276 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
18281 /* Assume worst case for symbols not known to be in the same section. */
18282 if (!S_IS_DEFINED (fragp
->fr_symbol
)
18283 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
18286 val
= relaxed_symbol_addr (fragp
, stretch
);
18287 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18288 addr
= (addr
+ 4) & ~3;
18289 /* Force misaligned targets to 32-bit variant. */
18293 if (val
< 0 || val
> 1020)
18298 /* Return the size of a relaxable add/sub immediate instruction. */
18300 relax_addsub (fragS
*fragp
, asection
*sec
)
18305 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18306 op
= bfd_get_16(sec
->owner
, buf
);
18307 if ((op
& 0xf) == ((op
>> 4) & 0xf))
18308 return relax_immediate (fragp
, 8, 0);
18310 return relax_immediate (fragp
, 3, 0);
18314 /* Return the size of a relaxable branch instruction. BITS is the
18315 size of the offset field in the narrow instruction. */
18318 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
18324 /* Assume worst case for symbols not known to be in the same section. */
18325 if (!S_IS_DEFINED (fragp
->fr_symbol
)
18326 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
18330 if (S_IS_DEFINED (fragp
->fr_symbol
)
18331 && ARM_IS_FUNC (fragp
->fr_symbol
))
18335 val
= relaxed_symbol_addr (fragp
, stretch
);
18336 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18339 /* Offset is a signed value *2 */
18341 if (val
>= limit
|| val
< -limit
)
18347 /* Relax a machine dependent frag. This returns the amount by which
18348 the current size of the frag should change. */
18351 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18356 oldsize
= fragp
->fr_var
;
18357 switch (fragp
->fr_subtype
)
18359 case T_MNEM_ldr_pc2
:
18360 newsize
= relax_adr (fragp
, sec
, stretch
);
18362 case T_MNEM_ldr_pc
:
18363 case T_MNEM_ldr_sp
:
18364 case T_MNEM_str_sp
:
18365 newsize
= relax_immediate (fragp
, 8, 2);
18369 newsize
= relax_immediate (fragp
, 5, 2);
18373 newsize
= relax_immediate (fragp
, 5, 1);
18377 newsize
= relax_immediate (fragp
, 5, 0);
18380 newsize
= relax_adr (fragp
, sec
, stretch
);
18386 newsize
= relax_immediate (fragp
, 8, 0);
18389 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
18392 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
18394 case T_MNEM_add_sp
:
18395 case T_MNEM_add_pc
:
18396 newsize
= relax_immediate (fragp
, 8, 2);
18398 case T_MNEM_inc_sp
:
18399 case T_MNEM_dec_sp
:
18400 newsize
= relax_immediate (fragp
, 7, 2);
18406 newsize
= relax_addsub (fragp
, sec
);
18412 fragp
->fr_var
= newsize
;
18413 /* Freeze wide instructions that are at or before the same location as
18414 in the previous pass. This avoids infinite loops.
18415 Don't freeze them unconditionally because targets may be artificially
18416 misaligned by the expansion of preceding frags. */
18417 if (stretch
<= 0 && newsize
> 2)
18419 md_convert_frag (sec
->owner
, sec
, fragp
);
18423 return newsize
- oldsize
;
18426 /* Round up a section size to the appropriate boundary. */
18429 md_section_align (segT segment ATTRIBUTE_UNUSED
,
18432 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
18433 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
18435 /* For a.out, force the section size to be aligned. If we don't do
18436 this, BFD will align it for us, but it will not write out the
18437 final bytes of the section. This may be a bug in BFD, but it is
18438 easier to fix it here since that is how the other a.out targets
18442 align
= bfd_get_section_alignment (stdoutput
, segment
);
18443 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
18450 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
18451 of an rs_align_code fragment. */
18454 arm_handle_align (fragS
* fragP
)
18456 static char const arm_noop
[2][2][4] =
18459 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
18460 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
18463 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
18464 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
18467 static char const thumb_noop
[2][2][2] =
18470 {0xc0, 0x46}, /* LE */
18471 {0x46, 0xc0}, /* BE */
18474 {0x00, 0xbf}, /* LE */
18475 {0xbf, 0x00} /* BE */
18478 static char const wide_thumb_noop
[2][4] =
18479 { /* Wide Thumb-2 */
18480 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
18481 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
18484 unsigned bytes
, fix
, noop_size
;
18487 const char *narrow_noop
= NULL
;
18492 if (fragP
->fr_type
!= rs_align_code
)
18495 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
18496 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
18499 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18500 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
18503 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
18506 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
18508 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
18510 narrow_noop
= thumb_noop
[1][target_big_endian
];
18511 noop
= wide_thumb_noop
[target_big_endian
];
18514 noop
= thumb_noop
[0][target_big_endian
];
18522 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
18523 [target_big_endian
];
18530 fragP
->fr_var
= noop_size
;
18532 if (bytes
& (noop_size
- 1))
18534 fix
= bytes
& (noop_size
- 1);
18536 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
18538 memset (p
, 0, fix
);
18545 if (bytes
& noop_size
)
18547 /* Insert a narrow noop. */
18548 memcpy (p
, narrow_noop
, noop_size
);
18550 bytes
-= noop_size
;
18554 /* Use wide noops for the remainder */
18558 while (bytes
>= noop_size
)
18560 memcpy (p
, noop
, noop_size
);
18562 bytes
-= noop_size
;
18566 fragP
->fr_fix
+= fix
;
18569 /* Called from md_do_align. Used to create an alignment
18570 frag in a code section. */
18573 arm_frag_align_code (int n
, int max
)
18577 /* We assume that there will never be a requirement
18578 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
18579 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18584 _("alignments greater than %d bytes not supported in .text sections."),
18585 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
18586 as_fatal ("%s", err_msg
);
18589 p
= frag_var (rs_align_code
,
18590 MAX_MEM_FOR_RS_ALIGN_CODE
,
18592 (relax_substateT
) max
,
18599 /* Perform target specific initialisation of a frag.
18600 Note - despite the name this initialisation is not done when the frag
18601 is created, but only when its type is assigned. A frag can be created
18602 and used a long time before its type is set, so beware of assuming that
18603 this initialisationis performed first. */
18607 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
18609 /* Record whether this frag is in an ARM or a THUMB area. */
18610 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
;
18613 #else /* OBJ_ELF is defined. */
18615 arm_init_frag (fragS
* fragP
, int max_chars
)
18617 /* If the current ARM vs THUMB mode has not already
18618 been recorded into this frag then do so now. */
18619 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
18621 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18623 /* Record a mapping symbol for alignment frags. We will delete this
18624 later if the alignment ends up empty. */
18625 switch (fragP
->fr_type
)
18628 case rs_align_test
:
18630 mapping_state_2 (MAP_DATA
, max_chars
);
18632 case rs_align_code
:
18633 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
18641 /* When we change sections we need to issue a new mapping symbol. */
18644 arm_elf_change_section (void)
18646 /* Link an unlinked unwind index table section to the .text section. */
18647 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
18648 && elf_linked_to_section (now_seg
) == NULL
)
18649 elf_linked_to_section (now_seg
) = text_section
;
18653 arm_elf_section_type (const char * str
, size_t len
)
18655 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
18656 return SHT_ARM_EXIDX
;
18661 /* Code to deal with unwinding tables. */
18663 static void add_unwind_adjustsp (offsetT
);
18665 /* Generate any deferred unwind frame offset. */
18668 flush_pending_unwind (void)
18672 offset
= unwind
.pending_offset
;
18673 unwind
.pending_offset
= 0;
18675 add_unwind_adjustsp (offset
);
18678 /* Add an opcode to this list for this function. Two-byte opcodes should
18679 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
18683 add_unwind_opcode (valueT op
, int length
)
18685 /* Add any deferred stack adjustment. */
18686 if (unwind
.pending_offset
)
18687 flush_pending_unwind ();
18689 unwind
.sp_restored
= 0;
18691 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
18693 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
18694 if (unwind
.opcodes
)
18695 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
18696 unwind
.opcode_alloc
);
18698 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
18703 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
18705 unwind
.opcode_count
++;
18709 /* Add unwind opcodes to adjust the stack pointer. */
18712 add_unwind_adjustsp (offsetT offset
)
18716 if (offset
> 0x200)
18718 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
18723 /* Long form: 0xb2, uleb128. */
18724 /* This might not fit in a word so add the individual bytes,
18725 remembering the list is built in reverse order. */
18726 o
= (valueT
) ((offset
- 0x204) >> 2);
18728 add_unwind_opcode (0, 1);
18730 /* Calculate the uleb128 encoding of the offset. */
18734 bytes
[n
] = o
& 0x7f;
18740 /* Add the insn. */
18742 add_unwind_opcode (bytes
[n
- 1], 1);
18743 add_unwind_opcode (0xb2, 1);
18745 else if (offset
> 0x100)
18747 /* Two short opcodes. */
18748 add_unwind_opcode (0x3f, 1);
18749 op
= (offset
- 0x104) >> 2;
18750 add_unwind_opcode (op
, 1);
18752 else if (offset
> 0)
18754 /* Short opcode. */
18755 op
= (offset
- 4) >> 2;
18756 add_unwind_opcode (op
, 1);
18758 else if (offset
< 0)
18761 while (offset
> 0x100)
18763 add_unwind_opcode (0x7f, 1);
18766 op
= ((offset
- 4) >> 2) | 0x40;
18767 add_unwind_opcode (op
, 1);
18771 /* Finish the list of unwind opcodes for this function. */
18773 finish_unwind_opcodes (void)
18777 if (unwind
.fp_used
)
18779 /* Adjust sp as necessary. */
18780 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
18781 flush_pending_unwind ();
18783 /* After restoring sp from the frame pointer. */
18784 op
= 0x90 | unwind
.fp_reg
;
18785 add_unwind_opcode (op
, 1);
18788 flush_pending_unwind ();
18792 /* Start an exception table entry. If idx is nonzero this is an index table
18796 start_unwind_section (const segT text_seg
, int idx
)
18798 const char * text_name
;
18799 const char * prefix
;
18800 const char * prefix_once
;
18801 const char * group_name
;
18805 size_t sec_name_len
;
18812 prefix
= ELF_STRING_ARM_unwind
;
18813 prefix_once
= ELF_STRING_ARM_unwind_once
;
18814 type
= SHT_ARM_EXIDX
;
18818 prefix
= ELF_STRING_ARM_unwind_info
;
18819 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
18820 type
= SHT_PROGBITS
;
18823 text_name
= segment_name (text_seg
);
18824 if (streq (text_name
, ".text"))
18827 if (strncmp (text_name
, ".gnu.linkonce.t.",
18828 strlen (".gnu.linkonce.t.")) == 0)
18830 prefix
= prefix_once
;
18831 text_name
+= strlen (".gnu.linkonce.t.");
18834 prefix_len
= strlen (prefix
);
18835 text_len
= strlen (text_name
);
18836 sec_name_len
= prefix_len
+ text_len
;
18837 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
18838 memcpy (sec_name
, prefix
, prefix_len
);
18839 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
18840 sec_name
[prefix_len
+ text_len
] = '\0';
18846 /* Handle COMDAT group. */
18847 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
18849 group_name
= elf_group_name (text_seg
);
18850 if (group_name
== NULL
)
18852 as_bad (_("Group section `%s' has no group signature"),
18853 segment_name (text_seg
));
18854 ignore_rest_of_line ();
18857 flags
|= SHF_GROUP
;
18861 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
18863 /* Set the section link for index tables. */
18865 elf_linked_to_section (now_seg
) = text_seg
;
18869 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
18870 personality routine data. Returns zero, or the index table value for
18871 and inline entry. */
18874 create_unwind_entry (int have_data
)
18879 /* The current word of data. */
18881 /* The number of bytes left in this word. */
18884 finish_unwind_opcodes ();
18886 /* Remember the current text section. */
18887 unwind
.saved_seg
= now_seg
;
18888 unwind
.saved_subseg
= now_subseg
;
18890 start_unwind_section (now_seg
, 0);
18892 if (unwind
.personality_routine
== NULL
)
18894 if (unwind
.personality_index
== -2)
18897 as_bad (_("handlerdata in cantunwind frame"));
18898 return 1; /* EXIDX_CANTUNWIND. */
18901 /* Use a default personality routine if none is specified. */
18902 if (unwind
.personality_index
== -1)
18904 if (unwind
.opcode_count
> 3)
18905 unwind
.personality_index
= 1;
18907 unwind
.personality_index
= 0;
18910 /* Space for the personality routine entry. */
18911 if (unwind
.personality_index
== 0)
18913 if (unwind
.opcode_count
> 3)
18914 as_bad (_("too many unwind opcodes for personality routine 0"));
18918 /* All the data is inline in the index table. */
18921 while (unwind
.opcode_count
> 0)
18923 unwind
.opcode_count
--;
18924 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
18928 /* Pad with "finish" opcodes. */
18930 data
= (data
<< 8) | 0xb0;
18937 /* We get two opcodes "free" in the first word. */
18938 size
= unwind
.opcode_count
- 2;
18941 /* An extra byte is required for the opcode count. */
18942 size
= unwind
.opcode_count
+ 1;
18944 size
= (size
+ 3) >> 2;
18946 as_bad (_("too many unwind opcodes"));
18948 frag_align (2, 0, 0);
18949 record_alignment (now_seg
, 2);
18950 unwind
.table_entry
= expr_build_dot ();
18952 /* Allocate the table entry. */
18953 ptr
= frag_more ((size
<< 2) + 4);
18954 where
= frag_now_fix () - ((size
<< 2) + 4);
18956 switch (unwind
.personality_index
)
18959 /* ??? Should this be a PLT generating relocation? */
18960 /* Custom personality routine. */
18961 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
18962 BFD_RELOC_ARM_PREL31
);
18967 /* Set the first byte to the number of additional words. */
18972 /* ABI defined personality routines. */
18974 /* Three opcodes bytes are packed into the first word. */
18981 /* The size and first two opcode bytes go in the first word. */
18982 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
18987 /* Should never happen. */
18991 /* Pack the opcodes into words (MSB first), reversing the list at the same
18993 while (unwind
.opcode_count
> 0)
18997 md_number_to_chars (ptr
, data
, 4);
19002 unwind
.opcode_count
--;
19004 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19007 /* Finish off the last word. */
19010 /* Pad with "finish" opcodes. */
19012 data
= (data
<< 8) | 0xb0;
19014 md_number_to_chars (ptr
, data
, 4);
19019 /* Add an empty descriptor if there is no user-specified data. */
19020 ptr
= frag_more (4);
19021 md_number_to_chars (ptr
, 0, 4);
19028 /* Initialize the DWARF-2 unwind information for this procedure. */
19031 tc_arm_frame_initial_instructions (void)
19033 cfi_add_CFA_def_cfa (REG_SP
, 0);
19035 #endif /* OBJ_ELF */
19037 /* Convert REGNAME to a DWARF-2 register number. */
19040 tc_arm_regname_to_dw2regnum (char *regname
)
19042 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
19052 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
19056 expr
.X_op
= O_secrel
;
19057 expr
.X_add_symbol
= symbol
;
19058 expr
.X_add_number
= 0;
19059 emit_expr (&expr
, size
);
19063 /* MD interface: Symbol and relocation handling. */
19065 /* Return the address within the segment that a PC-relative fixup is
19066 relative to. For ARM, PC-relative fixups applied to instructions
19067 are generally relative to the location of the fixup plus 8 bytes.
19068 Thumb branches are offset by 4, and Thumb loads relative to PC
19069 require special handling. */
19072 md_pcrel_from_section (fixS
* fixP
, segT seg
)
19074 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19076 /* If this is pc-relative and we are going to emit a relocation
19077 then we just want to put out any pipeline compensation that the linker
19078 will need. Otherwise we want to use the calculated base.
19079 For WinCE we skip the bias for externals as well, since this
19080 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19082 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19083 || (arm_force_relocation (fixP
)
19085 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19091 switch (fixP
->fx_r_type
)
19093 /* PC relative addressing on the Thumb is slightly odd as the
19094 bottom two bits of the PC are forced to zero for the
19095 calculation. This happens *after* application of the
19096 pipeline offset. However, Thumb adrl already adjusts for
19097 this, so we need not do it again. */
19098 case BFD_RELOC_ARM_THUMB_ADD
:
19101 case BFD_RELOC_ARM_THUMB_OFFSET
:
19102 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19103 case BFD_RELOC_ARM_T32_ADD_PC12
:
19104 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
19105 return (base
+ 4) & ~3;
19107 /* Thumb branches are simply offset by +4. */
19108 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19109 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19110 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19111 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19112 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19115 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19117 && ARM_IS_FUNC (fixP
->fx_addsy
)
19118 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19119 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19122 /* BLX is like branches above, but forces the low two bits of PC to
19124 case BFD_RELOC_THUMB_PCREL_BLX
:
19126 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19127 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19128 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19129 return (base
+ 4) & ~3;
19131 /* ARM mode branches are offset by +8. However, the Windows CE
19132 loader expects the relocation not to take this into account. */
19133 case BFD_RELOC_ARM_PCREL_BLX
:
19135 && ARM_IS_FUNC (fixP
->fx_addsy
)
19136 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19137 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19140 case BFD_RELOC_ARM_PCREL_CALL
:
19142 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19143 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19144 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19147 case BFD_RELOC_ARM_PCREL_BRANCH
:
19148 case BFD_RELOC_ARM_PCREL_JUMP
:
19149 case BFD_RELOC_ARM_PLT32
:
19151 /* When handling fixups immediately, because we have already
19152 discovered the value of a symbol, or the address of the frag involved
19153 we must account for the offset by +8, as the OS loader will never see the reloc.
19154 see fixup_segment() in write.c
19155 The S_IS_EXTERNAL test handles the case of global symbols.
19156 Those need the calculated base, not just the pipe compensation the linker will need. */
19158 && fixP
->fx_addsy
!= NULL
19159 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19160 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
19168 /* ARM mode loads relative to PC are also offset by +8. Unlike
19169 branches, the Windows CE loader *does* expect the relocation
19170 to take this into account. */
19171 case BFD_RELOC_ARM_OFFSET_IMM
:
19172 case BFD_RELOC_ARM_OFFSET_IMM8
:
19173 case BFD_RELOC_ARM_HWLITERAL
:
19174 case BFD_RELOC_ARM_LITERAL
:
19175 case BFD_RELOC_ARM_CP_OFF_IMM
:
19179 /* Other PC-relative relocations are un-offset. */
19185 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
19186 Otherwise we have no need to default values of symbols. */
19189 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
19192 if (name
[0] == '_' && name
[1] == 'G'
19193 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
19197 if (symbol_find (name
))
19198 as_bad (_("GOT already in the symbol table"));
19200 GOT_symbol
= symbol_new (name
, undefined_section
,
19201 (valueT
) 0, & zero_address_frag
);
19211 /* Subroutine of md_apply_fix. Check to see if an immediate can be
19212 computed as two separate immediate values, added together. We
19213 already know that this value cannot be computed by just one ARM
19216 static unsigned int
19217 validate_immediate_twopart (unsigned int val
,
19218 unsigned int * highpart
)
19223 for (i
= 0; i
< 32; i
+= 2)
19224 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
19230 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
19232 else if (a
& 0xff0000)
19234 if (a
& 0xff000000)
19236 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
19240 gas_assert (a
& 0xff000000);
19241 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
19244 return (a
& 0xff) | (i
<< 7);
19251 validate_offset_imm (unsigned int val
, int hwse
)
19253 if ((hwse
&& val
> 255) || val
> 4095)
19258 /* Subroutine of md_apply_fix. Do those data_ops which can take a
19259 negative immediate constant by altering the instruction. A bit of
19264 by inverting the second operand, and
19267 by negating the second operand. */
19270 negate_data_op (unsigned long * instruction
,
19271 unsigned long value
)
19274 unsigned long negated
, inverted
;
19276 negated
= encode_arm_immediate (-value
);
19277 inverted
= encode_arm_immediate (~value
);
19279 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
19282 /* First negates. */
19283 case OPCODE_SUB
: /* ADD <-> SUB */
19284 new_inst
= OPCODE_ADD
;
19289 new_inst
= OPCODE_SUB
;
19293 case OPCODE_CMP
: /* CMP <-> CMN */
19294 new_inst
= OPCODE_CMN
;
19299 new_inst
= OPCODE_CMP
;
19303 /* Now Inverted ops. */
19304 case OPCODE_MOV
: /* MOV <-> MVN */
19305 new_inst
= OPCODE_MVN
;
19310 new_inst
= OPCODE_MOV
;
19314 case OPCODE_AND
: /* AND <-> BIC */
19315 new_inst
= OPCODE_BIC
;
19320 new_inst
= OPCODE_AND
;
19324 case OPCODE_ADC
: /* ADC <-> SBC */
19325 new_inst
= OPCODE_SBC
;
19330 new_inst
= OPCODE_ADC
;
19334 /* We cannot do anything. */
19339 if (value
== (unsigned) FAIL
)
19342 *instruction
&= OPCODE_MASK
;
19343 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
19347 /* Like negate_data_op, but for Thumb-2. */
19349 static unsigned int
19350 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
19354 unsigned int negated
, inverted
;
19356 negated
= encode_thumb32_immediate (-value
);
19357 inverted
= encode_thumb32_immediate (~value
);
19359 rd
= (*instruction
>> 8) & 0xf;
19360 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
19363 /* ADD <-> SUB. Includes CMP <-> CMN. */
19364 case T2_OPCODE_SUB
:
19365 new_inst
= T2_OPCODE_ADD
;
19369 case T2_OPCODE_ADD
:
19370 new_inst
= T2_OPCODE_SUB
;
19374 /* ORR <-> ORN. Includes MOV <-> MVN. */
19375 case T2_OPCODE_ORR
:
19376 new_inst
= T2_OPCODE_ORN
;
19380 case T2_OPCODE_ORN
:
19381 new_inst
= T2_OPCODE_ORR
;
19385 /* AND <-> BIC. TST has no inverted equivalent. */
19386 case T2_OPCODE_AND
:
19387 new_inst
= T2_OPCODE_BIC
;
19394 case T2_OPCODE_BIC
:
19395 new_inst
= T2_OPCODE_AND
;
19400 case T2_OPCODE_ADC
:
19401 new_inst
= T2_OPCODE_SBC
;
19405 case T2_OPCODE_SBC
:
19406 new_inst
= T2_OPCODE_ADC
;
19410 /* We cannot do anything. */
19415 if (value
== (unsigned int)FAIL
)
19418 *instruction
&= T2_OPCODE_MASK
;
19419 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
19423 /* Read a 32-bit thumb instruction from buf. */
19424 static unsigned long
19425 get_thumb32_insn (char * buf
)
19427 unsigned long insn
;
19428 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
19429 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19435 /* We usually want to set the low bit on the address of thumb function
19436 symbols. In particular .word foo - . should have the low bit set.
19437 Generic code tries to fold the difference of two symbols to
19438 a constant. Prevent this and force a relocation when the first symbols
19439 is a thumb function. */
19442 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
19444 if (op
== O_subtract
19445 && l
->X_op
== O_symbol
19446 && r
->X_op
== O_symbol
19447 && THUMB_IS_FUNC (l
->X_add_symbol
))
19449 l
->X_op
= O_subtract
;
19450 l
->X_op_symbol
= r
->X_add_symbol
;
19451 l
->X_add_number
-= r
->X_add_number
;
19455 /* Process as normal. */
19460 md_apply_fix (fixS
* fixP
,
19464 offsetT value
= * valP
;
19466 unsigned int newimm
;
19467 unsigned long temp
;
19469 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
19471 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
19473 /* Note whether this will delete the relocation. */
19475 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
19478 /* On a 64-bit host, silently truncate 'value' to 32 bits for
19479 consistency with the behaviour on 32-bit hosts. Remember value
19481 value
&= 0xffffffff;
19482 value
^= 0x80000000;
19483 value
-= 0x80000000;
19486 fixP
->fx_addnumber
= value
;
19488 /* Same treatment for fixP->fx_offset. */
19489 fixP
->fx_offset
&= 0xffffffff;
19490 fixP
->fx_offset
^= 0x80000000;
19491 fixP
->fx_offset
-= 0x80000000;
19493 switch (fixP
->fx_r_type
)
19495 case BFD_RELOC_NONE
:
19496 /* This will need to go in the object file. */
19500 case BFD_RELOC_ARM_IMMEDIATE
:
19501 /* We claim that this fixup has been processed here,
19502 even if in fact we generate an error because we do
19503 not have a reloc for it, so tc_gen_reloc will reject it. */
19507 && ! S_IS_DEFINED (fixP
->fx_addsy
))
19509 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19510 _("undefined symbol %s used as an immediate value"),
19511 S_GET_NAME (fixP
->fx_addsy
));
19516 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19518 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19519 _("symbol %s is in a different section"),
19520 S_GET_NAME (fixP
->fx_addsy
));
19524 newimm
= encode_arm_immediate (value
);
19525 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19527 /* If the instruction will fail, see if we can fix things up by
19528 changing the opcode. */
19529 if (newimm
== (unsigned int) FAIL
19530 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
19532 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19533 _("invalid constant (%lx) after fixup"),
19534 (unsigned long) value
);
19538 newimm
|= (temp
& 0xfffff000);
19539 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19542 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
19544 unsigned int highpart
= 0;
19545 unsigned int newinsn
= 0xe1a00000; /* nop. */
19548 && ! S_IS_DEFINED (fixP
->fx_addsy
))
19550 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19551 _("undefined symbol %s used as an immediate value"),
19552 S_GET_NAME (fixP
->fx_addsy
));
19557 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19559 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19560 _("symbol %s is in a different section"),
19561 S_GET_NAME (fixP
->fx_addsy
));
19565 newimm
= encode_arm_immediate (value
);
19566 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19568 /* If the instruction will fail, see if we can fix things up by
19569 changing the opcode. */
19570 if (newimm
== (unsigned int) FAIL
19571 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
19573 /* No ? OK - try using two ADD instructions to generate
19575 newimm
= validate_immediate_twopart (value
, & highpart
);
19577 /* Yes - then make sure that the second instruction is
19579 if (newimm
!= (unsigned int) FAIL
)
19581 /* Still No ? Try using a negated value. */
19582 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
19583 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
19584 /* Otherwise - give up. */
19587 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19588 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
19593 /* Replace the first operand in the 2nd instruction (which
19594 is the PC) with the destination register. We have
19595 already added in the PC in the first instruction and we
19596 do not want to do it again. */
19597 newinsn
&= ~ 0xf0000;
19598 newinsn
|= ((newinsn
& 0x0f000) << 4);
19601 newimm
|= (temp
& 0xfffff000);
19602 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19604 highpart
|= (newinsn
& 0xfffff000);
19605 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
19609 case BFD_RELOC_ARM_OFFSET_IMM
:
19610 if (!fixP
->fx_done
&& seg
->use_rela_p
)
19613 case BFD_RELOC_ARM_LITERAL
:
19619 if (validate_offset_imm (value
, 0) == FAIL
)
19621 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
19622 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19623 _("invalid literal constant: pool needs to be closer"));
19625 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19626 _("bad immediate value for offset (%ld)"),
19631 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19632 newval
&= 0xff7ff000;
19633 newval
|= value
| (sign
? INDEX_UP
: 0);
19634 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19637 case BFD_RELOC_ARM_OFFSET_IMM8
:
19638 case BFD_RELOC_ARM_HWLITERAL
:
19644 if (validate_offset_imm (value
, 1) == FAIL
)
19646 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
19647 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19648 _("invalid literal constant: pool needs to be closer"));
19650 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
19655 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19656 newval
&= 0xff7ff0f0;
19657 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
19658 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19661 case BFD_RELOC_ARM_T32_OFFSET_U8
:
19662 if (value
< 0 || value
> 1020 || value
% 4 != 0)
19663 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19664 _("bad immediate value for offset (%ld)"), (long) value
);
19667 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
19669 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
19672 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19673 /* This is a complicated relocation used for all varieties of Thumb32
19674 load/store instruction with immediate offset:
19676 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
19677 *4, optional writeback(W)
19678 (doubleword load/store)
19680 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
19681 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
19682 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
19683 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
19684 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
19686 Uppercase letters indicate bits that are already encoded at
19687 this point. Lowercase letters are our problem. For the
19688 second block of instructions, the secondary opcode nybble
19689 (bits 8..11) is present, and bit 23 is zero, even if this is
19690 a PC-relative operation. */
19691 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19693 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
19695 if ((newval
& 0xf0000000) == 0xe0000000)
19697 /* Doubleword load/store: 8-bit offset, scaled by 4. */
19699 newval
|= (1 << 23);
19702 if (value
% 4 != 0)
19704 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19705 _("offset not a multiple of 4"));
19711 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19712 _("offset out of range"));
19717 else if ((newval
& 0x000f0000) == 0x000f0000)
19719 /* PC-relative, 12-bit offset. */
19721 newval
|= (1 << 23);
19726 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19727 _("offset out of range"));
19732 else if ((newval
& 0x00000100) == 0x00000100)
19734 /* Writeback: 8-bit, +/- offset. */
19736 newval
|= (1 << 9);
19741 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19742 _("offset out of range"));
19747 else if ((newval
& 0x00000f00) == 0x00000e00)
19749 /* T-instruction: positive 8-bit offset. */
19750 if (value
< 0 || value
> 0xff)
19752 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19753 _("offset out of range"));
19761 /* Positive 12-bit or negative 8-bit offset. */
19765 newval
|= (1 << 23);
19775 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19776 _("offset out of range"));
19783 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
19784 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
19787 case BFD_RELOC_ARM_SHIFT_IMM
:
19788 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19789 if (((unsigned long) value
) > 32
19791 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
19793 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19794 _("shift expression is too large"));
19799 /* Shifts of zero must be done as lsl. */
19801 else if (value
== 32)
19803 newval
&= 0xfffff07f;
19804 newval
|= (value
& 0x1f) << 7;
19805 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19808 case BFD_RELOC_ARM_T32_IMMEDIATE
:
19809 case BFD_RELOC_ARM_T32_ADD_IMM
:
19810 case BFD_RELOC_ARM_T32_IMM12
:
19811 case BFD_RELOC_ARM_T32_ADD_PC12
:
19812 /* We claim that this fixup has been processed here,
19813 even if in fact we generate an error because we do
19814 not have a reloc for it, so tc_gen_reloc will reject it. */
19818 && ! S_IS_DEFINED (fixP
->fx_addsy
))
19820 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19821 _("undefined symbol %s used as an immediate value"),
19822 S_GET_NAME (fixP
->fx_addsy
));
19826 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19828 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
19831 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
19832 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
19834 newimm
= encode_thumb32_immediate (value
);
19835 if (newimm
== (unsigned int) FAIL
)
19836 newimm
= thumb32_negate_data_op (&newval
, value
);
19838 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
19839 && newimm
== (unsigned int) FAIL
)
19841 /* Turn add/sum into addw/subw. */
19842 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
19843 newval
= (newval
& 0xfeffffff) | 0x02000000;
19845 /* 12 bit immediate for addw/subw. */
19849 newval
^= 0x00a00000;
19852 newimm
= (unsigned int) FAIL
;
19857 if (newimm
== (unsigned int)FAIL
)
19859 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19860 _("invalid constant (%lx) after fixup"),
19861 (unsigned long) value
);
19865 newval
|= (newimm
& 0x800) << 15;
19866 newval
|= (newimm
& 0x700) << 4;
19867 newval
|= (newimm
& 0x0ff);
19869 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
19870 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
19873 case BFD_RELOC_ARM_SMC
:
19874 if (((unsigned long) value
) > 0xffff)
19875 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19876 _("invalid smc expression"));
19877 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19878 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
19879 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19882 case BFD_RELOC_ARM_SWI
:
19883 if (fixP
->tc_fix_data
!= 0)
19885 if (((unsigned long) value
) > 0xff)
19886 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19887 _("invalid swi expression"));
19888 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19890 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19894 if (((unsigned long) value
) > 0x00ffffff)
19895 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19896 _("invalid swi expression"));
19897 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19899 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19903 case BFD_RELOC_ARM_MULTI
:
19904 if (((unsigned long) value
) > 0xffff)
19905 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19906 _("invalid expression in load/store multiple"));
19907 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
19908 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19912 case BFD_RELOC_ARM_PCREL_CALL
:
19914 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
19916 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19917 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19918 && THUMB_IS_FUNC (fixP
->fx_addsy
))
19919 /* Flip the bl to blx. This is a simple flip
19920 bit here because we generate PCREL_CALL for
19921 unconditional bls. */
19923 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19924 newval
= newval
| 0x10000000;
19925 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19931 goto arm_branch_common
;
19933 case BFD_RELOC_ARM_PCREL_JUMP
:
19934 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
19936 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19937 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19938 && THUMB_IS_FUNC (fixP
->fx_addsy
))
19940 /* This would map to a bl<cond>, b<cond>,
19941 b<always> to a Thumb function. We
19942 need to force a relocation for this particular
19944 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19948 case BFD_RELOC_ARM_PLT32
:
19950 case BFD_RELOC_ARM_PCREL_BRANCH
:
19952 goto arm_branch_common
;
19954 case BFD_RELOC_ARM_PCREL_BLX
:
19957 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
19959 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19960 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19961 && ARM_IS_FUNC (fixP
->fx_addsy
))
19963 /* Flip the blx to a bl and warn. */
19964 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
19965 newval
= 0xeb000000;
19966 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
19967 _("blx to '%s' an ARM ISA state function changed to bl"),
19969 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19975 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
19976 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
19980 /* We are going to store value (shifted right by two) in the
19981 instruction, in a 24 bit, signed field. Bits 26 through 32 either
19982 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
19983 also be be clear. */
19985 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19986 _("misaligned branch destination"));
19987 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
19988 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
19989 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19990 _("branch out of range"));
19992 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19994 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19995 newval
|= (value
>> 2) & 0x00ffffff;
19996 /* Set the H bit on BLX instructions. */
20000 newval
|= 0x01000000;
20002 newval
&= ~0x01000000;
20004 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20008 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
20009 /* CBZ can only branch forward. */
20011 /* Attempts to use CBZ to branch to the next instruction
20012 (which, strictly speaking, are prohibited) will be turned into
20015 FIXME: It may be better to remove the instruction completely and
20016 perform relaxation. */
20019 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20020 newval
= 0xbf00; /* NOP encoding T1 */
20021 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20026 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20027 _("branch out of range"));
20029 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20031 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20032 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
20033 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20038 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
20039 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
20040 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20041 _("branch out of range"));
20043 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20045 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20046 newval
|= (value
& 0x1ff) >> 1;
20047 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20051 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
20052 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
20053 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20054 _("branch out of range"));
20056 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20058 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20059 newval
|= (value
& 0xfff) >> 1;
20060 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20064 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20066 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20067 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20068 && S_IS_DEFINED (fixP
->fx_addsy
)
20069 && ARM_IS_FUNC (fixP
->fx_addsy
)
20070 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20072 /* Force a relocation for a branch 20 bits wide. */
20075 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
20076 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20077 _("conditional branch out of range"));
20079 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20082 addressT S
, J1
, J2
, lo
, hi
;
20084 S
= (value
& 0x00100000) >> 20;
20085 J2
= (value
& 0x00080000) >> 19;
20086 J1
= (value
& 0x00040000) >> 18;
20087 hi
= (value
& 0x0003f000) >> 12;
20088 lo
= (value
& 0x00000ffe) >> 1;
20090 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20091 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20092 newval
|= (S
<< 10) | hi
;
20093 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
20094 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20095 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20099 case BFD_RELOC_THUMB_PCREL_BLX
:
20101 /* If there is a blx from a thumb state function to
20102 another thumb function flip this to a bl and warn
20106 && S_IS_DEFINED (fixP
->fx_addsy
)
20107 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20108 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20109 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20111 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20112 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20113 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
20115 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20116 newval
= newval
| 0x1000;
20117 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20118 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20123 goto thumb_bl_common
;
20125 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20127 /* A bl from Thumb state ISA to an internal ARM state function
20128 is converted to a blx. */
20130 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20131 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20132 && S_IS_DEFINED (fixP
->fx_addsy
)
20133 && ARM_IS_FUNC (fixP
->fx_addsy
)
20134 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20136 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20137 newval
= newval
& ~0x1000;
20138 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20139 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
20146 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
20147 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20148 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20151 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
20152 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20153 _("branch out of range"));
20155 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20156 /* For a BLX instruction, make sure that the relocation is rounded up
20157 to a word boundary. This follows the semantics of the instruction
20158 which specifies that bit 1 of the target address will come from bit
20159 1 of the base address. */
20160 value
= (value
+ 1) & ~ 1;
20162 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20166 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20167 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20168 newval
|= (value
& 0x7fffff) >> 12;
20169 newval2
|= (value
& 0xfff) >> 1;
20170 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20171 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20175 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20176 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
20177 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20178 _("branch out of range"));
20180 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20183 addressT S
, I1
, I2
, lo
, hi
;
20185 S
= (value
& 0x01000000) >> 24;
20186 I1
= (value
& 0x00800000) >> 23;
20187 I2
= (value
& 0x00400000) >> 22;
20188 hi
= (value
& 0x003ff000) >> 12;
20189 lo
= (value
& 0x00000ffe) >> 1;
20194 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20195 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20196 newval
|= (S
<< 10) | hi
;
20197 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
20198 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20199 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20204 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20205 md_number_to_chars (buf
, value
, 1);
20209 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20210 md_number_to_chars (buf
, value
, 2);
20214 case BFD_RELOC_ARM_TLS_GD32
:
20215 case BFD_RELOC_ARM_TLS_LE32
:
20216 case BFD_RELOC_ARM_TLS_IE32
:
20217 case BFD_RELOC_ARM_TLS_LDM32
:
20218 case BFD_RELOC_ARM_TLS_LDO32
:
20219 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
20222 case BFD_RELOC_ARM_GOT32
:
20223 case BFD_RELOC_ARM_GOTOFF
:
20224 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20225 md_number_to_chars (buf
, 0, 4);
20228 case BFD_RELOC_ARM_TARGET2
:
20229 /* TARGET2 is not partial-inplace, so we need to write the
20230 addend here for REL targets, because it won't be written out
20231 during reloc processing later. */
20232 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20233 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
20237 case BFD_RELOC_RVA
:
20239 case BFD_RELOC_ARM_TARGET1
:
20240 case BFD_RELOC_ARM_ROSEGREL32
:
20241 case BFD_RELOC_ARM_SBREL32
:
20242 case BFD_RELOC_32_PCREL
:
20244 case BFD_RELOC_32_SECREL
:
20246 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20248 /* For WinCE we only do this for pcrel fixups. */
20249 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
20251 md_number_to_chars (buf
, value
, 4);
20255 case BFD_RELOC_ARM_PREL31
:
20256 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20258 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
20259 if ((value
^ (value
>> 1)) & 0x40000000)
20261 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20262 _("rel31 relocation overflow"));
20264 newval
|= value
& 0x7fffffff;
20265 md_number_to_chars (buf
, newval
, 4);
20270 case BFD_RELOC_ARM_CP_OFF_IMM
:
20271 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
20272 if (value
< -1023 || value
> 1023 || (value
& 3))
20273 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20274 _("co-processor offset out of range"));
20279 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20280 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20281 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20283 newval
= get_thumb32_insn (buf
);
20284 newval
&= 0xff7fff00;
20285 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
20286 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20287 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20288 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20290 put_thumb32_insn (buf
, newval
);
20293 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
20294 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
20295 if (value
< -255 || value
> 255)
20296 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20297 _("co-processor offset out of range"));
20299 goto cp_off_common
;
20301 case BFD_RELOC_ARM_THUMB_OFFSET
:
20302 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20303 /* Exactly what ranges, and where the offset is inserted depends
20304 on the type of instruction, we can establish this from the
20306 switch (newval
>> 12)
20308 case 4: /* PC load. */
20309 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
20310 forced to zero for these loads; md_pcrel_from has already
20311 compensated for this. */
20313 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20314 _("invalid offset, target not word aligned (0x%08lX)"),
20315 (((unsigned long) fixP
->fx_frag
->fr_address
20316 + (unsigned long) fixP
->fx_where
) & ~3)
20317 + (unsigned long) value
);
20319 if (value
& ~0x3fc)
20320 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20321 _("invalid offset, value too big (0x%08lX)"),
20324 newval
|= value
>> 2;
20327 case 9: /* SP load/store. */
20328 if (value
& ~0x3fc)
20329 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20330 _("invalid offset, value too big (0x%08lX)"),
20332 newval
|= value
>> 2;
20335 case 6: /* Word load/store. */
20337 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20338 _("invalid offset, value too big (0x%08lX)"),
20340 newval
|= value
<< 4; /* 6 - 2. */
20343 case 7: /* Byte load/store. */
20345 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20346 _("invalid offset, value too big (0x%08lX)"),
20348 newval
|= value
<< 6;
20351 case 8: /* Halfword load/store. */
20353 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20354 _("invalid offset, value too big (0x%08lX)"),
20356 newval
|= value
<< 5; /* 6 - 1. */
20360 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20361 "Unable to process relocation for thumb opcode: %lx",
20362 (unsigned long) newval
);
20365 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20368 case BFD_RELOC_ARM_THUMB_ADD
:
20369 /* This is a complicated relocation, since we use it for all of
20370 the following immediate relocations:
20374 9bit ADD/SUB SP word-aligned
20375 10bit ADD PC/SP word-aligned
20377 The type of instruction being processed is encoded in the
20384 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20386 int rd
= (newval
>> 4) & 0xf;
20387 int rs
= newval
& 0xf;
20388 int subtract
= !!(newval
& 0x8000);
20390 /* Check for HI regs, only very restricted cases allowed:
20391 Adjusting SP, and using PC or SP to get an address. */
20392 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
20393 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
20394 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20395 _("invalid Hi register with immediate"));
20397 /* If value is negative, choose the opposite instruction. */
20401 subtract
= !subtract
;
20403 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20404 _("immediate value out of range"));
20409 if (value
& ~0x1fc)
20410 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20411 _("invalid immediate for stack address calculation"));
20412 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
20413 newval
|= value
>> 2;
20415 else if (rs
== REG_PC
|| rs
== REG_SP
)
20417 if (subtract
|| value
& ~0x3fc)
20418 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20419 _("invalid immediate for address calculation (value = 0x%08lX)"),
20420 (unsigned long) value
);
20421 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
20423 newval
|= value
>> 2;
20428 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20429 _("immediate value out of range"));
20430 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
20431 newval
|= (rd
<< 8) | value
;
20436 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20437 _("immediate value out of range"));
20438 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
20439 newval
|= rd
| (rs
<< 3) | (value
<< 6);
20442 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20445 case BFD_RELOC_ARM_THUMB_IMM
:
20446 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20447 if (value
< 0 || value
> 255)
20448 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20449 _("invalid immediate: %ld is out of range"),
20452 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20455 case BFD_RELOC_ARM_THUMB_SHIFT
:
20456 /* 5bit shift value (0..32). LSL cannot take 32. */
20457 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
20458 temp
= newval
& 0xf800;
20459 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
20460 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20461 _("invalid shift value: %ld"), (long) value
);
20462 /* Shifts of zero must be encoded as LSL. */
20464 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
20465 /* Shifts of 32 are encoded as zero. */
20466 else if (value
== 32)
20468 newval
|= value
<< 6;
20469 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20472 case BFD_RELOC_VTABLE_INHERIT
:
20473 case BFD_RELOC_VTABLE_ENTRY
:
20477 case BFD_RELOC_ARM_MOVW
:
20478 case BFD_RELOC_ARM_MOVT
:
20479 case BFD_RELOC_ARM_THUMB_MOVW
:
20480 case BFD_RELOC_ARM_THUMB_MOVT
:
20481 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20483 /* REL format relocations are limited to a 16-bit addend. */
20484 if (!fixP
->fx_done
)
20486 if (value
< -0x8000 || value
> 0x7fff)
20487 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20488 _("offset out of range"));
20490 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
20491 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20496 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
20497 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20499 newval
= get_thumb32_insn (buf
);
20500 newval
&= 0xfbf08f00;
20501 newval
|= (value
& 0xf000) << 4;
20502 newval
|= (value
& 0x0800) << 15;
20503 newval
|= (value
& 0x0700) << 4;
20504 newval
|= (value
& 0x00ff);
20505 put_thumb32_insn (buf
, newval
);
20509 newval
= md_chars_to_number (buf
, 4);
20510 newval
&= 0xfff0f000;
20511 newval
|= value
& 0x0fff;
20512 newval
|= (value
& 0xf000) << 4;
20513 md_number_to_chars (buf
, newval
, 4);
20518 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
20519 case BFD_RELOC_ARM_ALU_PC_G0
:
20520 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
20521 case BFD_RELOC_ARM_ALU_PC_G1
:
20522 case BFD_RELOC_ARM_ALU_PC_G2
:
20523 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
20524 case BFD_RELOC_ARM_ALU_SB_G0
:
20525 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
20526 case BFD_RELOC_ARM_ALU_SB_G1
:
20527 case BFD_RELOC_ARM_ALU_SB_G2
:
20528 gas_assert (!fixP
->fx_done
);
20529 if (!seg
->use_rela_p
)
20532 bfd_vma encoded_addend
;
20533 bfd_vma addend_abs
= abs (value
);
20535 /* Check that the absolute value of the addend can be
20536 expressed as an 8-bit constant plus a rotation. */
20537 encoded_addend
= encode_arm_immediate (addend_abs
);
20538 if (encoded_addend
== (unsigned int) FAIL
)
20539 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20540 _("the offset 0x%08lX is not representable"),
20541 (unsigned long) addend_abs
);
20543 /* Extract the instruction. */
20544 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20546 /* If the addend is positive, use an ADD instruction.
20547 Otherwise use a SUB. Take care not to destroy the S bit. */
20548 insn
&= 0xff1fffff;
20554 /* Place the encoded addend into the first 12 bits of the
20556 insn
&= 0xfffff000;
20557 insn
|= encoded_addend
;
20559 /* Update the instruction. */
20560 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20564 case BFD_RELOC_ARM_LDR_PC_G0
:
20565 case BFD_RELOC_ARM_LDR_PC_G1
:
20566 case BFD_RELOC_ARM_LDR_PC_G2
:
20567 case BFD_RELOC_ARM_LDR_SB_G0
:
20568 case BFD_RELOC_ARM_LDR_SB_G1
:
20569 case BFD_RELOC_ARM_LDR_SB_G2
:
20570 gas_assert (!fixP
->fx_done
);
20571 if (!seg
->use_rela_p
)
20574 bfd_vma addend_abs
= abs (value
);
20576 /* Check that the absolute value of the addend can be
20577 encoded in 12 bits. */
20578 if (addend_abs
>= 0x1000)
20579 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20580 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
20581 (unsigned long) addend_abs
);
20583 /* Extract the instruction. */
20584 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20586 /* If the addend is negative, clear bit 23 of the instruction.
20587 Otherwise set it. */
20589 insn
&= ~(1 << 23);
20593 /* Place the absolute value of the addend into the first 12 bits
20594 of the instruction. */
20595 insn
&= 0xfffff000;
20596 insn
|= addend_abs
;
20598 /* Update the instruction. */
20599 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20603 case BFD_RELOC_ARM_LDRS_PC_G0
:
20604 case BFD_RELOC_ARM_LDRS_PC_G1
:
20605 case BFD_RELOC_ARM_LDRS_PC_G2
:
20606 case BFD_RELOC_ARM_LDRS_SB_G0
:
20607 case BFD_RELOC_ARM_LDRS_SB_G1
:
20608 case BFD_RELOC_ARM_LDRS_SB_G2
:
20609 gas_assert (!fixP
->fx_done
);
20610 if (!seg
->use_rela_p
)
20613 bfd_vma addend_abs
= abs (value
);
20615 /* Check that the absolute value of the addend can be
20616 encoded in 8 bits. */
20617 if (addend_abs
>= 0x100)
20618 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20619 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
20620 (unsigned long) addend_abs
);
20622 /* Extract the instruction. */
20623 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20625 /* If the addend is negative, clear bit 23 of the instruction.
20626 Otherwise set it. */
20628 insn
&= ~(1 << 23);
20632 /* Place the first four bits of the absolute value of the addend
20633 into the first 4 bits of the instruction, and the remaining
20634 four into bits 8 .. 11. */
20635 insn
&= 0xfffff0f0;
20636 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
20638 /* Update the instruction. */
20639 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20643 case BFD_RELOC_ARM_LDC_PC_G0
:
20644 case BFD_RELOC_ARM_LDC_PC_G1
:
20645 case BFD_RELOC_ARM_LDC_PC_G2
:
20646 case BFD_RELOC_ARM_LDC_SB_G0
:
20647 case BFD_RELOC_ARM_LDC_SB_G1
:
20648 case BFD_RELOC_ARM_LDC_SB_G2
:
20649 gas_assert (!fixP
->fx_done
);
20650 if (!seg
->use_rela_p
)
20653 bfd_vma addend_abs
= abs (value
);
20655 /* Check that the absolute value of the addend is a multiple of
20656 four and, when divided by four, fits in 8 bits. */
20657 if (addend_abs
& 0x3)
20658 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20659 _("bad offset 0x%08lX (must be word-aligned)"),
20660 (unsigned long) addend_abs
);
20662 if ((addend_abs
>> 2) > 0xff)
20663 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20664 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
20665 (unsigned long) addend_abs
);
20667 /* Extract the instruction. */
20668 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20670 /* If the addend is negative, clear bit 23 of the instruction.
20671 Otherwise set it. */
20673 insn
&= ~(1 << 23);
20677 /* Place the addend (divided by four) into the first eight
20678 bits of the instruction. */
20679 insn
&= 0xfffffff0;
20680 insn
|= addend_abs
>> 2;
20682 /* Update the instruction. */
20683 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20687 case BFD_RELOC_ARM_V4BX
:
20688 /* This will need to go in the object file. */
20692 case BFD_RELOC_UNUSED
:
20694 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20695 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
20699 /* Translate internal representation of relocation info to BFD target
20703 tc_gen_reloc (asection
*section
, fixS
*fixp
)
20706 bfd_reloc_code_real_type code
;
20708 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
20710 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
20711 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
20712 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
20714 if (fixp
->fx_pcrel
)
20716 if (section
->use_rela_p
)
20717 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
20719 fixp
->fx_offset
= reloc
->address
;
20721 reloc
->addend
= fixp
->fx_offset
;
20723 switch (fixp
->fx_r_type
)
20726 if (fixp
->fx_pcrel
)
20728 code
= BFD_RELOC_8_PCREL
;
20733 if (fixp
->fx_pcrel
)
20735 code
= BFD_RELOC_16_PCREL
;
20740 if (fixp
->fx_pcrel
)
20742 code
= BFD_RELOC_32_PCREL
;
20746 case BFD_RELOC_ARM_MOVW
:
20747 if (fixp
->fx_pcrel
)
20749 code
= BFD_RELOC_ARM_MOVW_PCREL
;
20753 case BFD_RELOC_ARM_MOVT
:
20754 if (fixp
->fx_pcrel
)
20756 code
= BFD_RELOC_ARM_MOVT_PCREL
;
20760 case BFD_RELOC_ARM_THUMB_MOVW
:
20761 if (fixp
->fx_pcrel
)
20763 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
20767 case BFD_RELOC_ARM_THUMB_MOVT
:
20768 if (fixp
->fx_pcrel
)
20770 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
20774 case BFD_RELOC_NONE
:
20775 case BFD_RELOC_ARM_PCREL_BRANCH
:
20776 case BFD_RELOC_ARM_PCREL_BLX
:
20777 case BFD_RELOC_RVA
:
20778 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
20779 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
20780 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
20781 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20782 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20783 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20784 case BFD_RELOC_VTABLE_ENTRY
:
20785 case BFD_RELOC_VTABLE_INHERIT
:
20787 case BFD_RELOC_32_SECREL
:
20789 code
= fixp
->fx_r_type
;
20792 case BFD_RELOC_THUMB_PCREL_BLX
:
20794 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20795 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20798 code
= BFD_RELOC_THUMB_PCREL_BLX
;
20801 case BFD_RELOC_ARM_LITERAL
:
20802 case BFD_RELOC_ARM_HWLITERAL
:
20803 /* If this is called then the a literal has
20804 been referenced across a section boundary. */
20805 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20806 _("literal referenced across section boundary"));
20810 case BFD_RELOC_ARM_GOT32
:
20811 case BFD_RELOC_ARM_GOTOFF
:
20812 case BFD_RELOC_ARM_PLT32
:
20813 case BFD_RELOC_ARM_TARGET1
:
20814 case BFD_RELOC_ARM_ROSEGREL32
:
20815 case BFD_RELOC_ARM_SBREL32
:
20816 case BFD_RELOC_ARM_PREL31
:
20817 case BFD_RELOC_ARM_TARGET2
:
20818 case BFD_RELOC_ARM_TLS_LE32
:
20819 case BFD_RELOC_ARM_TLS_LDO32
:
20820 case BFD_RELOC_ARM_PCREL_CALL
:
20821 case BFD_RELOC_ARM_PCREL_JUMP
:
20822 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
20823 case BFD_RELOC_ARM_ALU_PC_G0
:
20824 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
20825 case BFD_RELOC_ARM_ALU_PC_G1
:
20826 case BFD_RELOC_ARM_ALU_PC_G2
:
20827 case BFD_RELOC_ARM_LDR_PC_G0
:
20828 case BFD_RELOC_ARM_LDR_PC_G1
:
20829 case BFD_RELOC_ARM_LDR_PC_G2
:
20830 case BFD_RELOC_ARM_LDRS_PC_G0
:
20831 case BFD_RELOC_ARM_LDRS_PC_G1
:
20832 case BFD_RELOC_ARM_LDRS_PC_G2
:
20833 case BFD_RELOC_ARM_LDC_PC_G0
:
20834 case BFD_RELOC_ARM_LDC_PC_G1
:
20835 case BFD_RELOC_ARM_LDC_PC_G2
:
20836 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
20837 case BFD_RELOC_ARM_ALU_SB_G0
:
20838 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
20839 case BFD_RELOC_ARM_ALU_SB_G1
:
20840 case BFD_RELOC_ARM_ALU_SB_G2
:
20841 case BFD_RELOC_ARM_LDR_SB_G0
:
20842 case BFD_RELOC_ARM_LDR_SB_G1
:
20843 case BFD_RELOC_ARM_LDR_SB_G2
:
20844 case BFD_RELOC_ARM_LDRS_SB_G0
:
20845 case BFD_RELOC_ARM_LDRS_SB_G1
:
20846 case BFD_RELOC_ARM_LDRS_SB_G2
:
20847 case BFD_RELOC_ARM_LDC_SB_G0
:
20848 case BFD_RELOC_ARM_LDC_SB_G1
:
20849 case BFD_RELOC_ARM_LDC_SB_G2
:
20850 case BFD_RELOC_ARM_V4BX
:
20851 code
= fixp
->fx_r_type
;
20854 case BFD_RELOC_ARM_TLS_GD32
:
20855 case BFD_RELOC_ARM_TLS_IE32
:
20856 case BFD_RELOC_ARM_TLS_LDM32
:
20857 /* BFD will include the symbol's address in the addend.
20858 But we don't want that, so subtract it out again here. */
20859 if (!S_IS_COMMON (fixp
->fx_addsy
))
20860 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
20861 code
= fixp
->fx_r_type
;
20865 case BFD_RELOC_ARM_IMMEDIATE
:
20866 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20867 _("internal relocation (type: IMMEDIATE) not fixed up"));
20870 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
20871 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20872 _("ADRL used for a symbol not defined in the same file"));
20875 case BFD_RELOC_ARM_OFFSET_IMM
:
20876 if (section
->use_rela_p
)
20878 code
= fixp
->fx_r_type
;
20882 if (fixp
->fx_addsy
!= NULL
20883 && !S_IS_DEFINED (fixp
->fx_addsy
)
20884 && S_IS_LOCAL (fixp
->fx_addsy
))
20886 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20887 _("undefined local label `%s'"),
20888 S_GET_NAME (fixp
->fx_addsy
));
20892 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20893 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
20900 switch (fixp
->fx_r_type
)
20902 case BFD_RELOC_NONE
: type
= "NONE"; break;
20903 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
20904 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
20905 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
20906 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
20907 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
20908 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
20909 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
20910 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
20911 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
20912 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
20913 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
20914 default: type
= _("<unknown>"); break;
20916 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20917 _("cannot represent %s relocation in this object file format"),
20924 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
20926 && fixp
->fx_addsy
== GOT_symbol
)
20928 code
= BFD_RELOC_ARM_GOTPC
;
20929 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
20933 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
20935 if (reloc
->howto
== NULL
)
20937 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20938 _("cannot represent %s relocation in this object file format"),
20939 bfd_get_reloc_code_name (code
));
20943 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
20944 vtable entry to be used in the relocation's section offset. */
20945 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
20946 reloc
->address
= fixp
->fx_offset
;
20951 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
20954 cons_fix_new_arm (fragS
* frag
,
20959 bfd_reloc_code_real_type type
;
20963 FIXME: @@ Should look at CPU word size. */
20967 type
= BFD_RELOC_8
;
20970 type
= BFD_RELOC_16
;
20974 type
= BFD_RELOC_32
;
20977 type
= BFD_RELOC_64
;
20982 if (exp
->X_op
== O_secrel
)
20984 exp
->X_op
= O_symbol
;
20985 type
= BFD_RELOC_32_SECREL
;
20989 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
20992 #if defined (OBJ_COFF)
20994 arm_validate_fix (fixS
* fixP
)
20996 /* If the destination of the branch is a defined symbol which does not have
20997 the THUMB_FUNC attribute, then we must be calling a function which has
20998 the (interfacearm) attribute. We look for the Thumb entry point to that
20999 function and change the branch to refer to that function instead. */
21000 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
21001 && fixP
->fx_addsy
!= NULL
21002 && S_IS_DEFINED (fixP
->fx_addsy
)
21003 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
21005 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
21012 arm_force_relocation (struct fix
* fixp
)
21014 #if defined (OBJ_COFF) && defined (TE_PE)
21015 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
21019 /* In case we have a call or a branch to a function in ARM ISA mode from
21020 a thumb function or vice-versa force the relocation. These relocations
21021 are cleared off for some cores that might have blx and simple transformations
21025 switch (fixp
->fx_r_type
)
21027 case BFD_RELOC_ARM_PCREL_JUMP
:
21028 case BFD_RELOC_ARM_PCREL_CALL
:
21029 case BFD_RELOC_THUMB_PCREL_BLX
:
21030 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
21034 case BFD_RELOC_ARM_PCREL_BLX
:
21035 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21036 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21037 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21038 if (ARM_IS_FUNC (fixp
->fx_addsy
))
21047 /* Resolve these relocations even if the symbol is extern or weak. */
21048 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
21049 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
21050 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
21051 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
21052 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
21053 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
21054 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
21057 /* Always leave these relocations for the linker. */
21058 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21059 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21060 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21063 /* Always generate relocations against function symbols. */
21064 if (fixp
->fx_r_type
== BFD_RELOC_32
21066 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
21069 return generic_force_reloc (fixp
);
21072 #if defined (OBJ_ELF) || defined (OBJ_COFF)
21073 /* Relocations against function names must be left unadjusted,
21074 so that the linker can use this information to generate interworking
21075 stubs. The MIPS version of this function
21076 also prevents relocations that are mips-16 specific, but I do not
21077 know why it does this.
21080 There is one other problem that ought to be addressed here, but
21081 which currently is not: Taking the address of a label (rather
21082 than a function) and then later jumping to that address. Such
21083 addresses also ought to have their bottom bit set (assuming that
21084 they reside in Thumb code), but at the moment they will not. */
21087 arm_fix_adjustable (fixS
* fixP
)
21089 if (fixP
->fx_addsy
== NULL
)
21092 /* Preserve relocations against symbols with function type. */
21093 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
21096 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
21097 && fixP
->fx_subsy
== NULL
)
21100 /* We need the symbol name for the VTABLE entries. */
21101 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
21102 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21105 /* Don't allow symbols to be discarded on GOT related relocs. */
21106 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
21107 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
21108 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
21109 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
21110 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
21111 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
21112 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
21113 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
21114 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
21117 /* Similarly for group relocations. */
21118 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21119 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21120 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21123 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
21124 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
21125 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21126 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
21127 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
21128 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21129 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
21130 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
21131 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
21136 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
21141 elf32_arm_target_format (void)
21144 return (target_big_endian
21145 ? "elf32-bigarm-symbian"
21146 : "elf32-littlearm-symbian");
21147 #elif defined (TE_VXWORKS)
21148 return (target_big_endian
21149 ? "elf32-bigarm-vxworks"
21150 : "elf32-littlearm-vxworks");
21152 if (target_big_endian
)
21153 return "elf32-bigarm";
21155 return "elf32-littlearm";
21160 armelf_frob_symbol (symbolS
* symp
,
21163 elf_frob_symbol (symp
, puntp
);
21167 /* MD interface: Finalization. */
21172 literal_pool
* pool
;
21174 /* Ensure that all the IT blocks are properly closed. */
21175 check_it_blocks_finished ();
21177 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
21179 /* Put it at the end of the relevant section. */
21180 subseg_set (pool
->section
, pool
->sub_section
);
21182 arm_elf_change_section ();
21189 /* Remove any excess mapping symbols generated for alignment frags in
21190 SEC. We may have created a mapping symbol before a zero byte
21191 alignment; remove it if there's a mapping symbol after the
21194 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
21195 void *dummy ATTRIBUTE_UNUSED
)
21197 segment_info_type
*seginfo
= seg_info (sec
);
21200 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
21203 for (fragp
= seginfo
->frchainP
->frch_root
;
21205 fragp
= fragp
->fr_next
)
21207 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
21208 fragS
*next
= fragp
->fr_next
;
21210 /* Variable-sized frags have been converted to fixed size by
21211 this point. But if this was variable-sized to start with,
21212 there will be a fixed-size frag after it. So don't handle
21214 if (sym
== NULL
|| next
== NULL
)
21217 if (S_GET_VALUE (sym
) < next
->fr_address
)
21218 /* Not at the end of this frag. */
21220 know (S_GET_VALUE (sym
) == next
->fr_address
);
21224 if (next
->tc_frag_data
.first_map
!= NULL
)
21226 /* Next frag starts with a mapping symbol. Discard this
21228 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21232 if (next
->fr_next
== NULL
)
21234 /* This mapping symbol is at the end of the section. Discard
21236 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
21237 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21241 /* As long as we have empty frags without any mapping symbols,
21243 /* If the next frag is non-empty and does not start with a
21244 mapping symbol, then this mapping symbol is required. */
21245 if (next
->fr_address
!= next
->fr_next
->fr_address
)
21248 next
= next
->fr_next
;
21250 while (next
!= NULL
);
21255 /* Adjust the symbol table. This marks Thumb symbols as distinct from
21259 arm_adjust_symtab (void)
21264 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21266 if (ARM_IS_THUMB (sym
))
21268 if (THUMB_IS_FUNC (sym
))
21270 /* Mark the symbol as a Thumb function. */
21271 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
21272 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
21273 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
21275 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
21276 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
21278 as_bad (_("%s: unexpected function type: %d"),
21279 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
21281 else switch (S_GET_STORAGE_CLASS (sym
))
21284 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
21287 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
21290 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
21298 if (ARM_IS_INTERWORK (sym
))
21299 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
21306 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21308 if (ARM_IS_THUMB (sym
))
21310 elf_symbol_type
* elf_sym
;
21312 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
21313 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
21315 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
21316 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
21318 /* If it's a .thumb_func, declare it as so,
21319 otherwise tag label as .code 16. */
21320 if (THUMB_IS_FUNC (sym
))
21321 elf_sym
->internal_elf_sym
.st_info
=
21322 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
21323 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
21324 elf_sym
->internal_elf_sym
.st_info
=
21325 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
21330 /* Remove any overlapping mapping symbols generated by alignment frags. */
21331 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
21335 /* MD interface: Initialization. */
21338 set_constant_flonums (void)
21342 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
21343 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
21347 /* Auto-select Thumb mode if it's the only available instruction set for the
21348 given architecture. */
21351 autoselect_thumb_from_cpu_variant (void)
21353 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
21354 opcode_select (16);
21363 if ( (arm_ops_hsh
= hash_new ()) == NULL
21364 || (arm_cond_hsh
= hash_new ()) == NULL
21365 || (arm_shift_hsh
= hash_new ()) == NULL
21366 || (arm_psr_hsh
= hash_new ()) == NULL
21367 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
21368 || (arm_reg_hsh
= hash_new ()) == NULL
21369 || (arm_reloc_hsh
= hash_new ()) == NULL
21370 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
21371 as_fatal (_("virtual memory exhausted"));
21373 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
21374 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
21375 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
21376 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
21377 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
21378 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
21379 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
21380 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
21381 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
21382 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
21383 (void *) (v7m_psrs
+ i
));
21384 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
21385 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
21387 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
21389 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
21390 (void *) (barrier_opt_names
+ i
));
21392 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
21393 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
21396 set_constant_flonums ();
21398 /* Set the cpu variant based on the command-line options. We prefer
21399 -mcpu= over -march= if both are set (as for GCC); and we prefer
21400 -mfpu= over any other way of setting the floating point unit.
21401 Use of legacy options with new options are faulted. */
21404 if (mcpu_cpu_opt
|| march_cpu_opt
)
21405 as_bad (_("use of old and new-style options to set CPU type"));
21407 mcpu_cpu_opt
= legacy_cpu
;
21409 else if (!mcpu_cpu_opt
)
21410 mcpu_cpu_opt
= march_cpu_opt
;
21415 as_bad (_("use of old and new-style options to set FPU type"));
21417 mfpu_opt
= legacy_fpu
;
21419 else if (!mfpu_opt
)
21421 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
21422 || defined (TE_NetBSD) || defined (TE_VXWORKS))
21423 /* Some environments specify a default FPU. If they don't, infer it
21424 from the processor. */
21426 mfpu_opt
= mcpu_fpu_opt
;
21428 mfpu_opt
= march_fpu_opt
;
21430 mfpu_opt
= &fpu_default
;
21436 if (mcpu_cpu_opt
!= NULL
)
21437 mfpu_opt
= &fpu_default
;
21438 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
21439 mfpu_opt
= &fpu_arch_vfp_v2
;
21441 mfpu_opt
= &fpu_arch_fpa
;
21447 mcpu_cpu_opt
= &cpu_default
;
21448 selected_cpu
= cpu_default
;
21452 selected_cpu
= *mcpu_cpu_opt
;
21454 mcpu_cpu_opt
= &arm_arch_any
;
21457 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21459 autoselect_thumb_from_cpu_variant ();
21461 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
21463 #if defined OBJ_COFF || defined OBJ_ELF
21465 unsigned int flags
= 0;
21467 #if defined OBJ_ELF
21468 flags
= meabi_flags
;
21470 switch (meabi_flags
)
21472 case EF_ARM_EABI_UNKNOWN
:
21474 /* Set the flags in the private structure. */
21475 if (uses_apcs_26
) flags
|= F_APCS26
;
21476 if (support_interwork
) flags
|= F_INTERWORK
;
21477 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
21478 if (pic_code
) flags
|= F_PIC
;
21479 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
21480 flags
|= F_SOFT_FLOAT
;
21482 switch (mfloat_abi_opt
)
21484 case ARM_FLOAT_ABI_SOFT
:
21485 case ARM_FLOAT_ABI_SOFTFP
:
21486 flags
|= F_SOFT_FLOAT
;
21489 case ARM_FLOAT_ABI_HARD
:
21490 if (flags
& F_SOFT_FLOAT
)
21491 as_bad (_("hard-float conflicts with specified fpu"));
21495 /* Using pure-endian doubles (even if soft-float). */
21496 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
21497 flags
|= F_VFP_FLOAT
;
21499 #if defined OBJ_ELF
21500 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
21501 flags
|= EF_ARM_MAVERICK_FLOAT
;
21504 case EF_ARM_EABI_VER4
:
21505 case EF_ARM_EABI_VER5
:
21506 /* No additional flags to set. */
21513 bfd_set_private_flags (stdoutput
, flags
);
21515 /* We have run out flags in the COFF header to encode the
21516 status of ATPCS support, so instead we create a dummy,
21517 empty, debug section called .arm.atpcs. */
21522 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
21526 bfd_set_section_flags
21527 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
21528 bfd_set_section_size (stdoutput
, sec
, 0);
21529 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
21535 /* Record the CPU type as well. */
21536 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
21537 mach
= bfd_mach_arm_iWMMXt2
;
21538 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
21539 mach
= bfd_mach_arm_iWMMXt
;
21540 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
21541 mach
= bfd_mach_arm_XScale
;
21542 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
21543 mach
= bfd_mach_arm_ep9312
;
21544 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
21545 mach
= bfd_mach_arm_5TE
;
21546 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
21548 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21549 mach
= bfd_mach_arm_5T
;
21551 mach
= bfd_mach_arm_5
;
21553 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
21555 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21556 mach
= bfd_mach_arm_4T
;
21558 mach
= bfd_mach_arm_4
;
21560 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
21561 mach
= bfd_mach_arm_3M
;
21562 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
21563 mach
= bfd_mach_arm_3
;
21564 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
21565 mach
= bfd_mach_arm_2a
;
21566 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
21567 mach
= bfd_mach_arm_2
;
21569 mach
= bfd_mach_arm_unknown
;
21571 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
21574 /* Command line processing. */
21577 Invocation line includes a switch not recognized by the base assembler.
21578 See if it's a processor-specific option.
21580 This routine is somewhat complicated by the need for backwards
21581 compatibility (since older releases of gcc can't be changed).
21582 The new options try to make the interface as compatible as
21585 New options (supported) are:
21587 -mcpu=<cpu name> Assemble for selected processor
21588 -march=<architecture name> Assemble for selected architecture
21589 -mfpu=<fpu architecture> Assemble for selected FPU.
21590 -EB/-mbig-endian Big-endian
21591 -EL/-mlittle-endian Little-endian
21592 -k Generate PIC code
21593 -mthumb Start in Thumb mode
21594 -mthumb-interwork Code supports ARM/Thumb interworking
21596 -m[no-]warn-deprecated Warn about deprecated features
21598 For now we will also provide support for:
21600 -mapcs-32 32-bit Program counter
21601 -mapcs-26 26-bit Program counter
21602 -macps-float Floats passed in FP registers
21603 -mapcs-reentrant Reentrant code
21605 (sometime these will probably be replaced with -mapcs=<list of options>
21606 and -matpcs=<list of options>)
21608 The remaining options are only supported for back-wards compatibility.
21609 Cpu variants, the arm part is optional:
21610 -m[arm]1 Currently not supported.
21611 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
21612 -m[arm]3 Arm 3 processor
21613 -m[arm]6[xx], Arm 6 processors
21614 -m[arm]7[xx][t][[d]m] Arm 7 processors
21615 -m[arm]8[10] Arm 8 processors
21616 -m[arm]9[20][tdmi] Arm 9 processors
21617 -mstrongarm[110[0]] StrongARM processors
21618 -mxscale XScale processors
21619 -m[arm]v[2345[t[e]]] Arm architectures
21620 -mall All (except the ARM1)
21622 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
21623 -mfpe-old (No float load/store multiples)
21624 -mvfpxd VFP Single precision
21626 -mno-fpu Disable all floating point instructions
21628 The following CPU names are recognized:
21629 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
21630 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
21631 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
21632 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
21633 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
21634 arm10t arm10e, arm1020t, arm1020e, arm10200e,
21635 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
21639 const char * md_shortopts
= "m:k";
21641 #ifdef ARM_BI_ENDIAN
21642 #define OPTION_EB (OPTION_MD_BASE + 0)
21643 #define OPTION_EL (OPTION_MD_BASE + 1)
21645 #if TARGET_BYTES_BIG_ENDIAN
21646 #define OPTION_EB (OPTION_MD_BASE + 0)
21648 #define OPTION_EL (OPTION_MD_BASE + 1)
21651 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
21653 struct option md_longopts
[] =
21656 {"EB", no_argument
, NULL
, OPTION_EB
},
21659 {"EL", no_argument
, NULL
, OPTION_EL
},
21661 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
21662 {NULL
, no_argument
, NULL
, 0}
21665 size_t md_longopts_size
= sizeof (md_longopts
);
21667 struct arm_option_table
21669 char *option
; /* Option name to match. */
21670 char *help
; /* Help information. */
21671 int *var
; /* Variable to change. */
21672 int value
; /* What to change it to. */
21673 char *deprecated
; /* If non-null, print this message. */
21676 struct arm_option_table arm_opts
[] =
21678 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
21679 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
21680 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
21681 &support_interwork
, 1, NULL
},
21682 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
21683 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
21684 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
21686 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
21687 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
21688 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
21689 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
21692 /* These are recognized by the assembler, but have no affect on code. */
21693 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
21694 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
21696 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
21697 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
21698 &warn_on_deprecated
, 0, NULL
},
21699 {NULL
, NULL
, NULL
, 0, NULL
}
21702 struct arm_legacy_option_table
21704 char *option
; /* Option name to match. */
21705 const arm_feature_set
**var
; /* Variable to change. */
21706 const arm_feature_set value
; /* What to change it to. */
21707 char *deprecated
; /* If non-null, print this message. */
21710 const struct arm_legacy_option_table arm_legacy_opts
[] =
21712 /* DON'T add any new processors to this list -- we want the whole list
21713 to go away... Add them to the processors table instead. */
21714 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
21715 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
21716 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
21717 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
21718 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
21719 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
21720 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
21721 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
21722 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
21723 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
21724 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
21725 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
21726 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
21727 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
21728 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
21729 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
21730 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
21731 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
21732 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
21733 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
21734 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
21735 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
21736 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
21737 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
21738 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
21739 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
21740 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
21741 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
21742 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
21743 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
21744 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
21745 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
21746 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
21747 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
21748 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
21749 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
21750 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
21751 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
21752 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
21753 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
21754 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
21755 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
21756 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
21757 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
21758 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
21759 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
21760 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21761 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21762 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21763 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21764 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
21765 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
21766 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
21767 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
21768 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
21769 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
21770 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
21771 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
21772 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
21773 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
21774 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
21775 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
21776 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
21777 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
21778 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
21779 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
21780 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
21781 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
21782 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
21783 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
21784 N_("use -mcpu=strongarm110")},
21785 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
21786 N_("use -mcpu=strongarm1100")},
21787 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
21788 N_("use -mcpu=strongarm1110")},
21789 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
21790 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
21791 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
21793 /* Architecture variants -- don't add any more to this list either. */
21794 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
21795 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
21796 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
21797 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
21798 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
21799 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
21800 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
21801 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
21802 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
21803 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
21804 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
21805 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
21806 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
21807 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
21808 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
21809 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
21810 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
21811 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
21813 /* Floating point variants -- don't add any more to this list either. */
21814 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
21815 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
21816 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
21817 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
21818 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
21820 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
21823 struct arm_cpu_option_table
21826 const arm_feature_set value
;
21827 /* For some CPUs we assume an FPU unless the user explicitly sets
21829 const arm_feature_set default_fpu
;
21830 /* The canonical name of the CPU, or NULL to use NAME converted to upper
21832 const char *canonical_name
;
21835 /* This list should, at a minimum, contain all the cpu names
21836 recognized by GCC. */
21837 static const struct arm_cpu_option_table arm_cpus
[] =
21839 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
21840 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
21841 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
21842 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
21843 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
21844 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21845 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21846 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21847 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21848 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21849 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21850 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
21851 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21852 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
21853 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21854 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
21855 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21856 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21857 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21858 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21859 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21860 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21861 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21862 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21863 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21864 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21865 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21866 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21867 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21868 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21869 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21870 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21871 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21872 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21873 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21874 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21875 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21876 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21877 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21878 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
21879 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21880 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21881 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21882 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21883 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21884 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21885 /* For V5 or later processors we default to using VFP; but the user
21886 should really set the FPU type explicitly. */
21887 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
21888 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21889 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
21890 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
21891 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
21892 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
21893 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
21894 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21895 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
21896 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
21897 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21898 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21899 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
21900 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
21901 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21902 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
21903 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
21904 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21905 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21906 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
21907 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
21908 {"fa626te", ARM_ARCH_V5TE
, FPU_NONE
, NULL
},
21909 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21910 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
21911 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
21912 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
21913 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
21914 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
21915 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
21916 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
21917 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
21918 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
21919 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
21920 {"cortex-a5", ARM_ARCH_V7A
, FPU_NONE
, NULL
},
21921 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
21922 | FPU_NEON_EXT_V1
),
21924 {"cortex-a9", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
21925 | FPU_NEON_EXT_V1
),
21927 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
21928 {"cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
, NULL
},
21929 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
21930 {"cortex-m1", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
21931 {"cortex-m0", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
21932 /* ??? XSCALE is really an architecture. */
21933 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
21934 /* ??? iwmmxt is not a processor. */
21935 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
21936 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
21937 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
21939 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
21940 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
21943 struct arm_arch_option_table
21946 const arm_feature_set value
;
21947 const arm_feature_set default_fpu
;
21950 /* This list should, at a minimum, contain all the architecture names
21951 recognized by GCC. */
21952 static const struct arm_arch_option_table arm_archs
[] =
21954 {"all", ARM_ANY
, FPU_ARCH_FPA
},
21955 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
21956 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
21957 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
21958 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
21959 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
21960 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
21961 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
21962 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
21963 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
21964 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
21965 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
21966 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
21967 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
21968 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
21969 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
21970 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
21971 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
21972 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
21973 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
21974 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
21975 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
21976 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
21977 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
21978 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
21979 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
21980 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
21981 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
21982 /* The official spelling of the ARMv7 profile variants is the dashed form.
21983 Accept the non-dashed form for compatibility with old toolchains. */
21984 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
21985 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
21986 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
21987 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
21988 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
21989 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
21990 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
21991 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
21992 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
21993 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
21996 /* ISA extensions in the co-processor space. */
21997 struct arm_option_cpu_value_table
22000 const arm_feature_set value
;
22003 static const struct arm_option_cpu_value_table arm_extensions
[] =
22005 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
22006 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
22007 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
22008 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
22009 {NULL
, ARM_ARCH_NONE
}
22012 /* This list should, at a minimum, contain all the fpu names
22013 recognized by GCC. */
22014 static const struct arm_option_cpu_value_table arm_fpus
[] =
22016 {"softfpa", FPU_NONE
},
22017 {"fpe", FPU_ARCH_FPE
},
22018 {"fpe2", FPU_ARCH_FPE
},
22019 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
22020 {"fpa", FPU_ARCH_FPA
},
22021 {"fpa10", FPU_ARCH_FPA
},
22022 {"fpa11", FPU_ARCH_FPA
},
22023 {"arm7500fe", FPU_ARCH_FPA
},
22024 {"softvfp", FPU_ARCH_VFP
},
22025 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
22026 {"vfp", FPU_ARCH_VFP_V2
},
22027 {"vfp9", FPU_ARCH_VFP_V2
},
22028 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
22029 {"vfp10", FPU_ARCH_VFP_V2
},
22030 {"vfp10-r0", FPU_ARCH_VFP_V1
},
22031 {"vfpxd", FPU_ARCH_VFP_V1xD
},
22032 {"vfpv2", FPU_ARCH_VFP_V2
},
22033 {"vfpv3", FPU_ARCH_VFP_V3
},
22034 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
22035 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
22036 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
22037 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
22038 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
22039 {"arm1020t", FPU_ARCH_VFP_V1
},
22040 {"arm1020e", FPU_ARCH_VFP_V2
},
22041 {"arm1136jfs", FPU_ARCH_VFP_V2
},
22042 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
22043 {"maverick", FPU_ARCH_MAVERICK
},
22044 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
22045 {"neon-fp16", FPU_ARCH_NEON_FP16
},
22046 {"vfpv4", FPU_ARCH_VFP_V4
},
22047 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
22048 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
22049 {NULL
, ARM_ARCH_NONE
}
22052 struct arm_option_value_table
22058 static const struct arm_option_value_table arm_float_abis
[] =
22060 {"hard", ARM_FLOAT_ABI_HARD
},
22061 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
22062 {"soft", ARM_FLOAT_ABI_SOFT
},
22067 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
22068 static const struct arm_option_value_table arm_eabis
[] =
22070 {"gnu", EF_ARM_EABI_UNKNOWN
},
22071 {"4", EF_ARM_EABI_VER4
},
22072 {"5", EF_ARM_EABI_VER5
},
22077 struct arm_long_option_table
22079 char * option
; /* Substring to match. */
22080 char * help
; /* Help information. */
22081 int (* func
) (char * subopt
); /* Function to decode sub-option. */
22082 char * deprecated
; /* If non-null, print this message. */
22086 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
22088 arm_feature_set
*ext_set
= (arm_feature_set
*)
22089 xmalloc (sizeof (arm_feature_set
));
22091 /* Copy the feature set, so that we can modify it. */
22092 *ext_set
= **opt_p
;
22095 while (str
!= NULL
&& *str
!= 0)
22097 const struct arm_option_cpu_value_table
* opt
;
22103 as_bad (_("invalid architectural extension"));
22108 ext
= strchr (str
, '+');
22111 optlen
= ext
- str
;
22113 optlen
= strlen (str
);
22117 as_bad (_("missing architectural extension"));
22121 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
22122 if (strncmp (opt
->name
, str
, optlen
) == 0)
22124 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
22128 if (opt
->name
== NULL
)
22130 as_bad (_("unknown architectural extension `%s'"), str
);
22141 arm_parse_cpu (char * str
)
22143 const struct arm_cpu_option_table
* opt
;
22144 char * ext
= strchr (str
, '+');
22148 optlen
= ext
- str
;
22150 optlen
= strlen (str
);
22154 as_bad (_("missing cpu name `%s'"), str
);
22158 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
22159 if (strncmp (opt
->name
, str
, optlen
) == 0)
22161 mcpu_cpu_opt
= &opt
->value
;
22162 mcpu_fpu_opt
= &opt
->default_fpu
;
22163 if (opt
->canonical_name
)
22164 strcpy (selected_cpu_name
, opt
->canonical_name
);
22169 for (i
= 0; i
< optlen
; i
++)
22170 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22171 selected_cpu_name
[i
] = 0;
22175 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
22180 as_bad (_("unknown cpu `%s'"), str
);
22185 arm_parse_arch (char * str
)
22187 const struct arm_arch_option_table
*opt
;
22188 char *ext
= strchr (str
, '+');
22192 optlen
= ext
- str
;
22194 optlen
= strlen (str
);
22198 as_bad (_("missing architecture name `%s'"), str
);
22202 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
22203 if (streq (opt
->name
, str
))
22205 march_cpu_opt
= &opt
->value
;
22206 march_fpu_opt
= &opt
->default_fpu
;
22207 strcpy (selected_cpu_name
, opt
->name
);
22210 return arm_parse_extension (ext
, &march_cpu_opt
);
22215 as_bad (_("unknown architecture `%s'\n"), str
);
22220 arm_parse_fpu (char * str
)
22222 const struct arm_option_cpu_value_table
* opt
;
22224 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22225 if (streq (opt
->name
, str
))
22227 mfpu_opt
= &opt
->value
;
22231 as_bad (_("unknown floating point format `%s'\n"), str
);
22236 arm_parse_float_abi (char * str
)
22238 const struct arm_option_value_table
* opt
;
22240 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
22241 if (streq (opt
->name
, str
))
22243 mfloat_abi_opt
= opt
->value
;
22247 as_bad (_("unknown floating point abi `%s'\n"), str
);
22253 arm_parse_eabi (char * str
)
22255 const struct arm_option_value_table
*opt
;
22257 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
22258 if (streq (opt
->name
, str
))
22260 meabi_flags
= opt
->value
;
22263 as_bad (_("unknown EABI `%s'\n"), str
);
22269 arm_parse_it_mode (char * str
)
22271 bfd_boolean ret
= TRUE
;
22273 if (streq ("arm", str
))
22274 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
22275 else if (streq ("thumb", str
))
22276 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
22277 else if (streq ("always", str
))
22278 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
22279 else if (streq ("never", str
))
22280 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
22283 as_bad (_("unknown implicit IT mode `%s', should be "\
22284 "arm, thumb, always, or never."), str
);
22291 struct arm_long_option_table arm_long_opts
[] =
22293 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
22294 arm_parse_cpu
, NULL
},
22295 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
22296 arm_parse_arch
, NULL
},
22297 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
22298 arm_parse_fpu
, NULL
},
22299 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
22300 arm_parse_float_abi
, NULL
},
22302 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
22303 arm_parse_eabi
, NULL
},
22305 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
22306 arm_parse_it_mode
, NULL
},
22307 {NULL
, NULL
, 0, NULL
}
22311 md_parse_option (int c
, char * arg
)
22313 struct arm_option_table
*opt
;
22314 const struct arm_legacy_option_table
*fopt
;
22315 struct arm_long_option_table
*lopt
;
22321 target_big_endian
= 1;
22327 target_big_endian
= 0;
22331 case OPTION_FIX_V4BX
:
22336 /* Listing option. Just ignore these, we don't support additional
22341 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22343 if (c
== opt
->option
[0]
22344 && ((arg
== NULL
&& opt
->option
[1] == 0)
22345 || streq (arg
, opt
->option
+ 1)))
22347 /* If the option is deprecated, tell the user. */
22348 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
22349 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22350 arg
? arg
: "", _(opt
->deprecated
));
22352 if (opt
->var
!= NULL
)
22353 *opt
->var
= opt
->value
;
22359 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
22361 if (c
== fopt
->option
[0]
22362 && ((arg
== NULL
&& fopt
->option
[1] == 0)
22363 || streq (arg
, fopt
->option
+ 1)))
22365 /* If the option is deprecated, tell the user. */
22366 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
22367 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22368 arg
? arg
: "", _(fopt
->deprecated
));
22370 if (fopt
->var
!= NULL
)
22371 *fopt
->var
= &fopt
->value
;
22377 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22379 /* These options are expected to have an argument. */
22380 if (c
== lopt
->option
[0]
22382 && strncmp (arg
, lopt
->option
+ 1,
22383 strlen (lopt
->option
+ 1)) == 0)
22385 /* If the option is deprecated, tell the user. */
22386 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
22387 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
22388 _(lopt
->deprecated
));
22390 /* Call the sup-option parser. */
22391 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
22402 md_show_usage (FILE * fp
)
22404 struct arm_option_table
*opt
;
22405 struct arm_long_option_table
*lopt
;
22407 fprintf (fp
, _(" ARM-specific assembler options:\n"));
22409 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22410 if (opt
->help
!= NULL
)
22411 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
22413 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22414 if (lopt
->help
!= NULL
)
22415 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
22419 -EB assemble code for a big-endian cpu\n"));
22424 -EL assemble code for a little-endian cpu\n"));
22428 --fix-v4bx Allow BX in ARMv4 code\n"));
22436 arm_feature_set flags
;
22437 } cpu_arch_ver_table
;
22439 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
22440 least features first. */
22441 static const cpu_arch_ver_table cpu_arch_ver
[] =
22447 {4, ARM_ARCH_V5TE
},
22448 {5, ARM_ARCH_V5TEJ
},
22452 {11, ARM_ARCH_V6M
},
22453 {8, ARM_ARCH_V6T2
},
22454 {10, ARM_ARCH_V7A
},
22455 {10, ARM_ARCH_V7R
},
22456 {10, ARM_ARCH_V7M
},
22460 /* Set an attribute if it has not already been set by the user. */
22462 aeabi_set_attribute_int (int tag
, int value
)
22465 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22466 || !attributes_set_explicitly
[tag
])
22467 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
22471 aeabi_set_attribute_string (int tag
, const char *value
)
22474 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22475 || !attributes_set_explicitly
[tag
])
22476 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
22479 /* Set the public EABI object attributes. */
22481 aeabi_set_public_attributes (void)
22484 arm_feature_set flags
;
22485 arm_feature_set tmp
;
22486 const cpu_arch_ver_table
*p
;
22488 /* Choose the architecture based on the capabilities of the requested cpu
22489 (if any) and/or the instructions actually used. */
22490 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
22491 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
22492 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
22493 /*Allow the user to override the reported architecture. */
22496 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
22497 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
22502 for (p
= cpu_arch_ver
; p
->val
; p
++)
22504 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
22507 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
22511 /* Tag_CPU_name. */
22512 if (selected_cpu_name
[0])
22516 p
= selected_cpu_name
;
22517 if (strncmp (p
, "armv", 4) == 0)
22522 for (i
= 0; p
[i
]; i
++)
22523 p
[i
] = TOUPPER (p
[i
]);
22525 aeabi_set_attribute_string (Tag_CPU_name
, p
);
22528 /* Tag_CPU_arch. */
22529 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
22531 /* Tag_CPU_arch_profile. */
22532 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
22533 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
22534 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
22535 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
22536 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
22537 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
22539 /* Tag_ARM_ISA_use. */
22540 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
22542 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
22544 /* Tag_THUMB_ISA_use. */
22545 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
22547 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
22548 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
22550 /* Tag_VFP_arch. */
22551 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
22552 aeabi_set_attribute_int (Tag_VFP_arch
,
22553 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
22555 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
22556 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
22557 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3
))
22558 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
22559 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
22560 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
22561 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
22562 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
22563 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
22565 /* Tag_WMMX_arch. */
22566 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
22567 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
22568 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
22569 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
22571 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
22572 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
22573 aeabi_set_attribute_int
22574 (Tag_Advanced_SIMD_arch
, (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
)
22577 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
22578 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
))
22579 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
22582 /* Add the default contents for the .ARM.attributes section. */
22586 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
22589 aeabi_set_public_attributes ();
22591 #endif /* OBJ_ELF */
22594 /* Parse a .cpu directive. */
22597 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
22599 const struct arm_cpu_option_table
*opt
;
22603 name
= input_line_pointer
;
22604 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22605 input_line_pointer
++;
22606 saved_char
= *input_line_pointer
;
22607 *input_line_pointer
= 0;
22609 /* Skip the first "all" entry. */
22610 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
22611 if (streq (opt
->name
, name
))
22613 mcpu_cpu_opt
= &opt
->value
;
22614 selected_cpu
= opt
->value
;
22615 if (opt
->canonical_name
)
22616 strcpy (selected_cpu_name
, opt
->canonical_name
);
22620 for (i
= 0; opt
->name
[i
]; i
++)
22621 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22622 selected_cpu_name
[i
] = 0;
22624 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22625 *input_line_pointer
= saved_char
;
22626 demand_empty_rest_of_line ();
22629 as_bad (_("unknown cpu `%s'"), name
);
22630 *input_line_pointer
= saved_char
;
22631 ignore_rest_of_line ();
22635 /* Parse a .arch directive. */
22638 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
22640 const struct arm_arch_option_table
*opt
;
22644 name
= input_line_pointer
;
22645 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22646 input_line_pointer
++;
22647 saved_char
= *input_line_pointer
;
22648 *input_line_pointer
= 0;
22650 /* Skip the first "all" entry. */
22651 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
22652 if (streq (opt
->name
, name
))
22654 mcpu_cpu_opt
= &opt
->value
;
22655 selected_cpu
= opt
->value
;
22656 strcpy (selected_cpu_name
, opt
->name
);
22657 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22658 *input_line_pointer
= saved_char
;
22659 demand_empty_rest_of_line ();
22663 as_bad (_("unknown architecture `%s'\n"), name
);
22664 *input_line_pointer
= saved_char
;
22665 ignore_rest_of_line ();
22669 /* Parse a .object_arch directive. */
22672 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
22674 const struct arm_arch_option_table
*opt
;
22678 name
= input_line_pointer
;
22679 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22680 input_line_pointer
++;
22681 saved_char
= *input_line_pointer
;
22682 *input_line_pointer
= 0;
22684 /* Skip the first "all" entry. */
22685 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
22686 if (streq (opt
->name
, name
))
22688 object_arch
= &opt
->value
;
22689 *input_line_pointer
= saved_char
;
22690 demand_empty_rest_of_line ();
22694 as_bad (_("unknown architecture `%s'\n"), name
);
22695 *input_line_pointer
= saved_char
;
22696 ignore_rest_of_line ();
22699 /* Parse a .fpu directive. */
22702 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
22704 const struct arm_option_cpu_value_table
*opt
;
22708 name
= input_line_pointer
;
22709 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22710 input_line_pointer
++;
22711 saved_char
= *input_line_pointer
;
22712 *input_line_pointer
= 0;
22714 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22715 if (streq (opt
->name
, name
))
22717 mfpu_opt
= &opt
->value
;
22718 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22719 *input_line_pointer
= saved_char
;
22720 demand_empty_rest_of_line ();
22724 as_bad (_("unknown floating point format `%s'\n"), name
);
22725 *input_line_pointer
= saved_char
;
22726 ignore_rest_of_line ();
22729 /* Copy symbol information. */
22732 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
22734 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
22738 /* Given a symbolic attribute NAME, return the proper integer value.
22739 Returns -1 if the attribute is not known. */
22742 arm_convert_symbolic_attribute (const char *name
)
22744 static const struct
22749 attribute_table
[] =
22751 /* When you modify this table you should
22752 also modify the list in doc/c-arm.texi. */
22753 #define T(tag) {#tag, tag}
22754 T (Tag_CPU_raw_name
),
22757 T (Tag_CPU_arch_profile
),
22758 T (Tag_ARM_ISA_use
),
22759 T (Tag_THUMB_ISA_use
),
22762 T (Tag_Advanced_SIMD_arch
),
22763 T (Tag_PCS_config
),
22764 T (Tag_ABI_PCS_R9_use
),
22765 T (Tag_ABI_PCS_RW_data
),
22766 T (Tag_ABI_PCS_RO_data
),
22767 T (Tag_ABI_PCS_GOT_use
),
22768 T (Tag_ABI_PCS_wchar_t
),
22769 T (Tag_ABI_FP_rounding
),
22770 T (Tag_ABI_FP_denormal
),
22771 T (Tag_ABI_FP_exceptions
),
22772 T (Tag_ABI_FP_user_exceptions
),
22773 T (Tag_ABI_FP_number_model
),
22774 T (Tag_ABI_align8_needed
),
22775 T (Tag_ABI_align8_preserved
),
22776 T (Tag_ABI_enum_size
),
22777 T (Tag_ABI_HardFP_use
),
22778 T (Tag_ABI_VFP_args
),
22779 T (Tag_ABI_WMMX_args
),
22780 T (Tag_ABI_optimization_goals
),
22781 T (Tag_ABI_FP_optimization_goals
),
22782 T (Tag_compatibility
),
22783 T (Tag_CPU_unaligned_access
),
22784 T (Tag_VFP_HP_extension
),
22785 T (Tag_ABI_FP_16bit_format
),
22786 T (Tag_nodefaults
),
22787 T (Tag_also_compatible_with
),
22788 T (Tag_conformance
),
22790 T (Tag_Virtualization_use
),
22791 T (Tag_MPextension_use
)
22799 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
22800 if (streq (name
, attribute_table
[i
].name
))
22801 return attribute_table
[i
].tag
;
22807 /* Apply sym value for relocations only in the case that
22808 they are for local symbols and you have the respective
22809 architectural feature for blx and simple switches. */
22811 arm_apply_sym_value (struct fix
* fixP
)
22814 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22815 && !S_IS_EXTERNAL (fixP
->fx_addsy
))
22817 switch (fixP
->fx_r_type
)
22819 case BFD_RELOC_ARM_PCREL_BLX
:
22820 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22821 if (ARM_IS_FUNC (fixP
->fx_addsy
))
22825 case BFD_RELOC_ARM_PCREL_CALL
:
22826 case BFD_RELOC_THUMB_PCREL_BLX
:
22827 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
22838 #endif /* OBJ_ELF */