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Preserve copy of case clobber opcodes so that .req pseudo op works
[binutils-gdb.git] / gas / config / tc-arm.c
1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994, 95, 96, 97, 98, 1999, 2000
3 Free Software Foundation, Inc.
4 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
5 Modified by David Taylor (dtaylor@armltd.co.uk)
6
7 This file is part of GAS, the GNU Assembler.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
21 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 02111-1307, USA. */
23
24 #include <ctype.h>
25 #include <string.h>
26 #define NO_RELOC 0
27 #include "as.h"
28
29 /* Need TARGET_CPU. */
30 #include "config.h"
31 #include "subsegs.h"
32 #include "obstack.h"
33 #include "symbols.h"
34 #include "listing.h"
35
36 #ifdef OBJ_ELF
37 #include "elf/arm.h"
38 #endif
39
40 /* Types of processor to assemble for. */
41 #define ARM_1 0x00000001
42 #define ARM_2 0x00000002
43 #define ARM_3 0x00000004
44 #define ARM_250 ARM_3
45 #define ARM_6 0x00000008
46 #define ARM_7 ARM_6 /* Same core instruction set. */
47 #define ARM_8 ARM_6 /* Same core instruction set. */
48 #define ARM_9 ARM_6 /* Same core instruction set. */
49 #define ARM_CPU_MASK 0x0000000f
50
51 /* The following bitmasks control CPU extensions (ARM7 onwards): */
52 #define ARM_LONGMUL 0x00000010 /* Allow long multiplies. */
53 #define ARM_HALFWORD 0x00000020 /* Allow half word loads. */
54 #define ARM_THUMB 0x00000040 /* Allow BX instruction. */
55 #define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */
56
57 /* Architectures are the sum of the base and extensions. */
58 #define ARM_ARCH_V4 (ARM_7 | ARM_LONGMUL | ARM_HALFWORD)
59 #define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_THUMB)
60 #define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5)
61 #define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_THUMB)
62
63 /* Some useful combinations: */
64 #define ARM_ANY 0x00ffffff
65 #define ARM_2UP (ARM_ANY - ARM_1)
66 #define ARM_ALL ARM_2UP /* Not arm1 only. */
67 #define ARM_3UP 0x00fffffc
68 #define ARM_6UP 0x00fffff8 /* Includes ARM7. */
69
70 #define FPU_CORE 0x80000000
71 #define FPU_FPA10 0x40000000
72 #define FPU_FPA11 0x40000000
73 #define FPU_NONE 0
74
75 /* Some useful combinations. */
76 #define FPU_ALL 0xff000000 /* Note this is ~ARM_ANY. */
77 #define FPU_MEMMULTI 0x7f000000 /* Not fpu_core. */
78
79 #ifndef CPU_DEFAULT
80 #if defined __thumb__
81 #define CPU_DEFAULT (ARM_ARCH_V4 | ARM_THUMB)
82 #else
83 #define CPU_DEFAULT ARM_ALL
84 #endif
85 #endif
86
87 #ifndef FPU_DEFAULT
88 #define FPU_DEFAULT FPU_ALL
89 #endif
90
91 #define streq(a, b) (strcmp (a, b) == 0)
92 #define skip_whitespace(str) while (*(str) == ' ') ++(str)
93
94 static unsigned long cpu_variant = CPU_DEFAULT | FPU_DEFAULT;
95 static int target_oabi = 0;
96
97 #if defined OBJ_COFF || defined OBJ_ELF
98 /* Flags stored in private area of BFD structure. */
99 static boolean uses_apcs_26 = false;
100 static boolean support_interwork = false;
101 static boolean uses_apcs_float = false;
102 static boolean pic_code = false;
103 #endif
104
105 /* This array holds the chars that always start a comment. If the
106 pre-processor is disabled, these aren't very useful. */
107 CONST char comment_chars[] = "@";
108
109 /* This array holds the chars that only start a comment at the beginning of
110 a line. If the line seems to have the form '# 123 filename'
111 .line and .file directives will appear in the pre-processed output. */
112 /* Note that input_file.c hand checks for '#' at the beginning of the
113 first line of the input file. This is because the compiler outputs
114 #NO_APP at the beginning of its output. */
115 /* Also note that comments like this one will always work. */
116 CONST char line_comment_chars[] = "#";
117
118 CONST char line_separator_chars[] = ";";
119
120 /* Chars that can be used to separate mant
121 from exp in floating point numbers. */
122 CONST char EXP_CHARS[] = "eE";
123
124 /* Chars that mean this number is a floating point constant. */
125 /* As in 0f12.456 */
126 /* or 0d1.2345e12 */
127
128 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
129
130 /* Prefix characters that indicate the start of an immediate
131 value. */
132 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
133
134 #ifdef OBJ_ELF
135 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
136 symbolS * GOT_symbol;
137 #endif
138
139 /* Size of relocation record. */
140 CONST int md_reloc_size = 8;
141
142 /* 0: assemble for ARM,
143 1: assemble for Thumb,
144 2: assemble for Thumb even though target CPU does not support thumb
145 instructions. */
146 static int thumb_mode = 0;
147
148 typedef struct arm_fix
149 {
150 int thumb_mode;
151 } arm_fix_data;
152
153 struct arm_it
154 {
155 CONST char * error;
156 unsigned long instruction;
157 int suffix;
158 int size;
159 struct
160 {
161 bfd_reloc_code_real_type type;
162 expressionS exp;
163 int pc_rel;
164 } reloc;
165 };
166
167 struct arm_it inst;
168
169 enum asm_shift_index
170 {
171 SHIFT_LSL = 0,
172 SHIFT_LSR,
173 SHIFT_ASR,
174 SHIFT_ROR,
175 SHIFT_RRX
176 };
177
178 struct asm_shift_properties
179 {
180 enum asm_shift_index index;
181 unsigned long bit_field;
182 unsigned int allows_0 : 1;
183 unsigned int allows_32 : 1;
184 };
185
186 static const struct asm_shift_properties shift_properties [] =
187 {
188 { SHIFT_LSL, 0, 1, 0},
189 { SHIFT_LSR, 0x20, 0, 1},
190 { SHIFT_ASR, 0x40, 0, 1},
191 { SHIFT_ROR, 0x60, 0, 0},
192 { SHIFT_RRX, 0x60, 0, 0}
193 };
194
195 struct asm_shift_name
196 {
197 const char * name;
198 const struct asm_shift_properties * properties;
199 };
200
201 static const struct asm_shift_name shift_names [] =
202 {
203 { "asl", shift_properties + SHIFT_LSL },
204 { "lsl", shift_properties + SHIFT_LSL },
205 { "lsr", shift_properties + SHIFT_LSR },
206 { "asr", shift_properties + SHIFT_ASR },
207 { "ror", shift_properties + SHIFT_ROR },
208 { "rrx", shift_properties + SHIFT_RRX },
209 { "ASL", shift_properties + SHIFT_LSL },
210 { "LSL", shift_properties + SHIFT_LSL },
211 { "LSR", shift_properties + SHIFT_LSR },
212 { "ASR", shift_properties + SHIFT_ASR },
213 { "ROR", shift_properties + SHIFT_ROR },
214 { "RRX", shift_properties + SHIFT_RRX }
215 };
216
217 #define NO_SHIFT_RESTRICT 1
218 #define SHIFT_RESTRICT 0
219
220 #define NUM_FLOAT_VALS 8
221
222 CONST char * fp_const[] =
223 {
224 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
225 };
226
227 /* Number of littlenums required to hold an extended precision number. */
228 #define MAX_LITTLENUMS 6
229
230 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
231
232 #define FAIL (-1)
233 #define SUCCESS (0)
234
235 #define SUFF_S 1
236 #define SUFF_D 2
237 #define SUFF_E 3
238 #define SUFF_P 4
239
240 #define CP_T_X 0x00008000
241 #define CP_T_Y 0x00400000
242 #define CP_T_Pre 0x01000000
243 #define CP_T_UD 0x00800000
244 #define CP_T_WB 0x00200000
245
246 #define CONDS_BIT (0x00100000)
247 #define LOAD_BIT (0x00100000)
248 #define TRANS_BIT (0x00200000)
249
250 struct asm_cond
251 {
252 CONST char * template;
253 unsigned long value;
254 };
255
256 /* This is to save a hash look-up in the common case. */
257 #define COND_ALWAYS 0xe0000000
258
259 static CONST struct asm_cond conds[] =
260 {
261 {"eq", 0x00000000},
262 {"ne", 0x10000000},
263 {"cs", 0x20000000}, {"hs", 0x20000000},
264 {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000},
265 {"mi", 0x40000000},
266 {"pl", 0x50000000},
267 {"vs", 0x60000000},
268 {"vc", 0x70000000},
269 {"hi", 0x80000000},
270 {"ls", 0x90000000},
271 {"ge", 0xa0000000},
272 {"lt", 0xb0000000},
273 {"gt", 0xc0000000},
274 {"le", 0xd0000000},
275 {"al", 0xe0000000},
276 {"nv", 0xf0000000}
277 };
278
279 /* Warning: If the top bit of the set_bits is set, then the standard
280 instruction bitmask is ignored, and the new bitmask is taken from
281 the set_bits: */
282 struct asm_flg
283 {
284 CONST char * template; /* Basic flag string. */
285 unsigned long set_bits; /* Bits to set. */
286 };
287
288 static CONST struct asm_flg s_flag[] =
289 {
290 {"s", CONDS_BIT},
291 {NULL, 0}
292 };
293
294 static CONST struct asm_flg ldr_flags[] =
295 {
296 {"b", 0x00400000},
297 {"t", TRANS_BIT},
298 {"bt", 0x00400000 | TRANS_BIT},
299 {"h", 0x801000b0},
300 {"sh", 0x801000f0},
301 {"sb", 0x801000d0},
302 {NULL, 0}
303 };
304
305 static CONST struct asm_flg str_flags[] =
306 {
307 {"b", 0x00400000},
308 {"t", TRANS_BIT},
309 {"bt", 0x00400000 | TRANS_BIT},
310 {"h", 0x800000b0},
311 {NULL, 0}
312 };
313
314 static CONST struct asm_flg byte_flag[] =
315 {
316 {"b", 0x00400000},
317 {NULL, 0}
318 };
319
320 static CONST struct asm_flg cmp_flags[] =
321 {
322 {"s", CONDS_BIT},
323 {"p", 0x0010f000},
324 {NULL, 0}
325 };
326
327 static CONST struct asm_flg ldm_flags[] =
328 {
329 {"ed", 0x01800000},
330 {"fd", 0x00800000},
331 {"ea", 0x01000000},
332 {"fa", 0x08000000},
333 {"ib", 0x01800000},
334 {"ia", 0x00800000},
335 {"db", 0x01000000},
336 {"da", 0x08000000},
337 {NULL, 0}
338 };
339
340 static CONST struct asm_flg stm_flags[] =
341 {
342 {"ed", 0x08000000},
343 {"fd", 0x01000000},
344 {"ea", 0x00800000},
345 {"fa", 0x01800000},
346 {"ib", 0x01800000},
347 {"ia", 0x00800000},
348 {"db", 0x01000000},
349 {"da", 0x08000000},
350 {NULL, 0}
351 };
352
353 static CONST struct asm_flg lfm_flags[] =
354 {
355 {"fd", 0x00800000},
356 {"ea", 0x01000000},
357 {NULL, 0}
358 };
359
360 static CONST struct asm_flg sfm_flags[] =
361 {
362 {"fd", 0x01000000},
363 {"ea", 0x00800000},
364 {NULL, 0}
365 };
366
367 static CONST struct asm_flg round_flags[] =
368 {
369 {"p", 0x00000020},
370 {"m", 0x00000040},
371 {"z", 0x00000060},
372 {NULL, 0}
373 };
374
375 /* The implementation of the FIX instruction is broken on some assemblers,
376 in that it accepts a precision specifier as well as a rounding specifier,
377 despite the fact that this is meaningless. To be more compatible, we
378 accept it as well, though of course it does not set any bits. */
379 static CONST struct asm_flg fix_flags[] =
380 {
381 {"p", 0x00000020},
382 {"m", 0x00000040},
383 {"z", 0x00000060},
384 {"sp", 0x00000020},
385 {"sm", 0x00000040},
386 {"sz", 0x00000060},
387 {"dp", 0x00000020},
388 {"dm", 0x00000040},
389 {"dz", 0x00000060},
390 {"ep", 0x00000020},
391 {"em", 0x00000040},
392 {"ez", 0x00000060},
393 {NULL, 0}
394 };
395
396 static CONST struct asm_flg except_flag[] =
397 {
398 {"e", 0x00400000},
399 {NULL, 0}
400 };
401
402 static CONST struct asm_flg cplong_flag[] =
403 {
404 {"l", 0x00400000},
405 {NULL, 0}
406 };
407
408 struct asm_psr
409 {
410 CONST char * template;
411 boolean cpsr;
412 unsigned long field;
413 };
414
415 /* The bit that distnguishes CPSR and SPSR. */
416 #define SPSR_BIT (1 << 22)
417
418 /* How many bits to shift the PSR_xxx bits up by. */
419 #define PSR_SHIFT 16
420
421 #define PSR_c (1 << 0)
422 #define PSR_x (1 << 1)
423 #define PSR_s (1 << 2)
424 #define PSR_f (1 << 3)
425
426 static CONST struct asm_psr psrs[] =
427 {
428 {"CPSR", true, PSR_c | PSR_f},
429 {"CPSR_all", true, PSR_c | PSR_f},
430 {"SPSR", false, PSR_c | PSR_f},
431 {"SPSR_all", false, PSR_c | PSR_f},
432 {"CPSR_flg", true, PSR_f},
433 {"CPSR_f", true, PSR_f},
434 {"SPSR_flg", false, PSR_f},
435 {"SPSR_f", false, PSR_f},
436 {"CPSR_c", true, PSR_c},
437 {"CPSR_ctl", true, PSR_c},
438 {"SPSR_c", false, PSR_c},
439 {"SPSR_ctl", false, PSR_c},
440 {"CPSR_x", true, PSR_x},
441 {"CPSR_s", true, PSR_s},
442 {"SPSR_x", false, PSR_x},
443 {"SPSR_s", false, PSR_s},
444 /* Combinations of flags. */
445 {"CPSR_fs", true, PSR_f | PSR_s},
446 {"CPSR_fx", true, PSR_f | PSR_x},
447 {"CPSR_fc", true, PSR_f | PSR_c},
448 {"CPSR_sf", true, PSR_s | PSR_f},
449 {"CPSR_sx", true, PSR_s | PSR_x},
450 {"CPSR_sc", true, PSR_s | PSR_c},
451 {"CPSR_xf", true, PSR_x | PSR_f},
452 {"CPSR_xs", true, PSR_x | PSR_s},
453 {"CPSR_xc", true, PSR_x | PSR_c},
454 {"CPSR_cf", true, PSR_c | PSR_f},
455 {"CPSR_cs", true, PSR_c | PSR_s},
456 {"CPSR_cx", true, PSR_c | PSR_x},
457 {"CPSR_fsx", true, PSR_f | PSR_s | PSR_x},
458 {"CPSR_fsc", true, PSR_f | PSR_s | PSR_c},
459 {"CPSR_fxs", true, PSR_f | PSR_x | PSR_s},
460 {"CPSR_fxc", true, PSR_f | PSR_x | PSR_c},
461 {"CPSR_fcs", true, PSR_f | PSR_c | PSR_s},
462 {"CPSR_fcx", true, PSR_f | PSR_c | PSR_x},
463 {"CPSR_sfx", true, PSR_s | PSR_f | PSR_x},
464 {"CPSR_sfc", true, PSR_s | PSR_f | PSR_c},
465 {"CPSR_sxf", true, PSR_s | PSR_x | PSR_f},
466 {"CPSR_sxc", true, PSR_s | PSR_x | PSR_c},
467 {"CPSR_scf", true, PSR_s | PSR_c | PSR_f},
468 {"CPSR_scx", true, PSR_s | PSR_c | PSR_x},
469 {"CPSR_xfs", true, PSR_x | PSR_f | PSR_s},
470 {"CPSR_xfc", true, PSR_x | PSR_f | PSR_c},
471 {"CPSR_xsf", true, PSR_x | PSR_s | PSR_f},
472 {"CPSR_xsc", true, PSR_x | PSR_s | PSR_c},
473 {"CPSR_xcf", true, PSR_x | PSR_c | PSR_f},
474 {"CPSR_xcs", true, PSR_x | PSR_c | PSR_s},
475 {"CPSR_cfs", true, PSR_c | PSR_f | PSR_s},
476 {"CPSR_cfx", true, PSR_c | PSR_f | PSR_x},
477 {"CPSR_csf", true, PSR_c | PSR_s | PSR_f},
478 {"CPSR_csx", true, PSR_c | PSR_s | PSR_x},
479 {"CPSR_cxf", true, PSR_c | PSR_x | PSR_f},
480 {"CPSR_cxs", true, PSR_c | PSR_x | PSR_s},
481 {"CPSR_fsxc", true, PSR_f | PSR_s | PSR_x | PSR_c},
482 {"CPSR_fscx", true, PSR_f | PSR_s | PSR_c | PSR_x},
483 {"CPSR_fxsc", true, PSR_f | PSR_x | PSR_s | PSR_c},
484 {"CPSR_fxcs", true, PSR_f | PSR_x | PSR_c | PSR_s},
485 {"CPSR_fcsx", true, PSR_f | PSR_c | PSR_s | PSR_x},
486 {"CPSR_fcxs", true, PSR_f | PSR_c | PSR_x | PSR_s},
487 {"CPSR_sfxc", true, PSR_s | PSR_f | PSR_x | PSR_c},
488 {"CPSR_sfcx", true, PSR_s | PSR_f | PSR_c | PSR_x},
489 {"CPSR_sxfc", true, PSR_s | PSR_x | PSR_f | PSR_c},
490 {"CPSR_sxcf", true, PSR_s | PSR_x | PSR_c | PSR_f},
491 {"CPSR_scfx", true, PSR_s | PSR_c | PSR_f | PSR_x},
492 {"CPSR_scxf", true, PSR_s | PSR_c | PSR_x | PSR_f},
493 {"CPSR_xfsc", true, PSR_x | PSR_f | PSR_s | PSR_c},
494 {"CPSR_xfcs", true, PSR_x | PSR_f | PSR_c | PSR_s},
495 {"CPSR_xsfc", true, PSR_x | PSR_s | PSR_f | PSR_c},
496 {"CPSR_xscf", true, PSR_x | PSR_s | PSR_c | PSR_f},
497 {"CPSR_xcfs", true, PSR_x | PSR_c | PSR_f | PSR_s},
498 {"CPSR_xcsf", true, PSR_x | PSR_c | PSR_s | PSR_f},
499 {"CPSR_cfsx", true, PSR_c | PSR_f | PSR_s | PSR_x},
500 {"CPSR_cfxs", true, PSR_c | PSR_f | PSR_x | PSR_s},
501 {"CPSR_csfx", true, PSR_c | PSR_s | PSR_f | PSR_x},
502 {"CPSR_csxf", true, PSR_c | PSR_s | PSR_x | PSR_f},
503 {"CPSR_cxfs", true, PSR_c | PSR_x | PSR_f | PSR_s},
504 {"CPSR_cxsf", true, PSR_c | PSR_x | PSR_s | PSR_f},
505 {"SPSR_fs", false, PSR_f | PSR_s},
506 {"SPSR_fx", false, PSR_f | PSR_x},
507 {"SPSR_fc", false, PSR_f | PSR_c},
508 {"SPSR_sf", false, PSR_s | PSR_f},
509 {"SPSR_sx", false, PSR_s | PSR_x},
510 {"SPSR_sc", false, PSR_s | PSR_c},
511 {"SPSR_xf", false, PSR_x | PSR_f},
512 {"SPSR_xs", false, PSR_x | PSR_s},
513 {"SPSR_xc", false, PSR_x | PSR_c},
514 {"SPSR_cf", false, PSR_c | PSR_f},
515 {"SPSR_cs", false, PSR_c | PSR_s},
516 {"SPSR_cx", false, PSR_c | PSR_x},
517 {"SPSR_fsx", false, PSR_f | PSR_s | PSR_x},
518 {"SPSR_fsc", false, PSR_f | PSR_s | PSR_c},
519 {"SPSR_fxs", false, PSR_f | PSR_x | PSR_s},
520 {"SPSR_fxc", false, PSR_f | PSR_x | PSR_c},
521 {"SPSR_fcs", false, PSR_f | PSR_c | PSR_s},
522 {"SPSR_fcx", false, PSR_f | PSR_c | PSR_x},
523 {"SPSR_sfx", false, PSR_s | PSR_f | PSR_x},
524 {"SPSR_sfc", false, PSR_s | PSR_f | PSR_c},
525 {"SPSR_sxf", false, PSR_s | PSR_x | PSR_f},
526 {"SPSR_sxc", false, PSR_s | PSR_x | PSR_c},
527 {"SPSR_scf", false, PSR_s | PSR_c | PSR_f},
528 {"SPSR_scx", false, PSR_s | PSR_c | PSR_x},
529 {"SPSR_xfs", false, PSR_x | PSR_f | PSR_s},
530 {"SPSR_xfc", false, PSR_x | PSR_f | PSR_c},
531 {"SPSR_xsf", false, PSR_x | PSR_s | PSR_f},
532 {"SPSR_xsc", false, PSR_x | PSR_s | PSR_c},
533 {"SPSR_xcf", false, PSR_x | PSR_c | PSR_f},
534 {"SPSR_xcs", false, PSR_x | PSR_c | PSR_s},
535 {"SPSR_cfs", false, PSR_c | PSR_f | PSR_s},
536 {"SPSR_cfx", false, PSR_c | PSR_f | PSR_x},
537 {"SPSR_csf", false, PSR_c | PSR_s | PSR_f},
538 {"SPSR_csx", false, PSR_c | PSR_s | PSR_x},
539 {"SPSR_cxf", false, PSR_c | PSR_x | PSR_f},
540 {"SPSR_cxs", false, PSR_c | PSR_x | PSR_s},
541 {"SPSR_fsxc", false, PSR_f | PSR_s | PSR_x | PSR_c},
542 {"SPSR_fscx", false, PSR_f | PSR_s | PSR_c | PSR_x},
543 {"SPSR_fxsc", false, PSR_f | PSR_x | PSR_s | PSR_c},
544 {"SPSR_fxcs", false, PSR_f | PSR_x | PSR_c | PSR_s},
545 {"SPSR_fcsx", false, PSR_f | PSR_c | PSR_s | PSR_x},
546 {"SPSR_fcxs", false, PSR_f | PSR_c | PSR_x | PSR_s},
547 {"SPSR_sfxc", false, PSR_s | PSR_f | PSR_x | PSR_c},
548 {"SPSR_sfcx", false, PSR_s | PSR_f | PSR_c | PSR_x},
549 {"SPSR_sxfc", false, PSR_s | PSR_x | PSR_f | PSR_c},
550 {"SPSR_sxcf", false, PSR_s | PSR_x | PSR_c | PSR_f},
551 {"SPSR_scfx", false, PSR_s | PSR_c | PSR_f | PSR_x},
552 {"SPSR_scxf", false, PSR_s | PSR_c | PSR_x | PSR_f},
553 {"SPSR_xfsc", false, PSR_x | PSR_f | PSR_s | PSR_c},
554 {"SPSR_xfcs", false, PSR_x | PSR_f | PSR_c | PSR_s},
555 {"SPSR_xsfc", false, PSR_x | PSR_s | PSR_f | PSR_c},
556 {"SPSR_xscf", false, PSR_x | PSR_s | PSR_c | PSR_f},
557 {"SPSR_xcfs", false, PSR_x | PSR_c | PSR_f | PSR_s},
558 {"SPSR_xcsf", false, PSR_x | PSR_c | PSR_s | PSR_f},
559 {"SPSR_cfsx", false, PSR_c | PSR_f | PSR_s | PSR_x},
560 {"SPSR_cfxs", false, PSR_c | PSR_f | PSR_x | PSR_s},
561 {"SPSR_csfx", false, PSR_c | PSR_s | PSR_f | PSR_x},
562 {"SPSR_csxf", false, PSR_c | PSR_s | PSR_x | PSR_f},
563 {"SPSR_cxfs", false, PSR_c | PSR_x | PSR_f | PSR_s},
564 {"SPSR_cxsf", false, PSR_c | PSR_x | PSR_s | PSR_f},
565 };
566
567 /* Functions called by parser. */
568 /* ARM instructions. */
569 static void do_arit PARAMS ((char *, unsigned long));
570 static void do_cmp PARAMS ((char *, unsigned long));
571 static void do_mov PARAMS ((char *, unsigned long));
572 static void do_ldst PARAMS ((char *, unsigned long));
573 static void do_ldmstm PARAMS ((char *, unsigned long));
574 static void do_branch PARAMS ((char *, unsigned long));
575 static void do_swi PARAMS ((char *, unsigned long));
576 /* Pseudo Op codes. */
577 static void do_adr PARAMS ((char *, unsigned long));
578 static void do_adrl PARAMS ((char *, unsigned long));
579 static void do_nop PARAMS ((char *, unsigned long));
580 /* ARM 2. */
581 static void do_mul PARAMS ((char *, unsigned long));
582 static void do_mla PARAMS ((char *, unsigned long));
583 /* ARM 3. */
584 static void do_swap PARAMS ((char *, unsigned long));
585 /* ARM 6. */
586 static void do_msr PARAMS ((char *, unsigned long));
587 static void do_mrs PARAMS ((char *, unsigned long));
588 /* ARM 7M. */
589 static void do_mull PARAMS ((char *, unsigned long));
590 /* ARM THUMB. */
591 static void do_bx PARAMS ((char *, unsigned long));
592
593 /* Coprocessor Instructions. */
594 static void do_cdp PARAMS ((char *, unsigned long));
595 static void do_lstc PARAMS ((char *, unsigned long));
596 static void do_co_reg PARAMS ((char *, unsigned long));
597 static void do_fp_ctrl PARAMS ((char *, unsigned long));
598 static void do_fp_ldst PARAMS ((char *, unsigned long));
599 static void do_fp_ldmstm PARAMS ((char *, unsigned long));
600 static void do_fp_dyadic PARAMS ((char *, unsigned long));
601 static void do_fp_monadic PARAMS ((char *, unsigned long));
602 static void do_fp_cmp PARAMS ((char *, unsigned long));
603 static void do_fp_from_reg PARAMS ((char *, unsigned long));
604 static void do_fp_to_reg PARAMS ((char *, unsigned long));
605
606 static void fix_new_arm PARAMS ((fragS *, int, short, expressionS *, int, int));
607 static int arm_reg_parse PARAMS ((char **));
608 static CONST struct asm_psr * arm_psr_parse PARAMS ((char **));
609 static void symbol_locate PARAMS ((symbolS *, CONST char *, segT, valueT, fragS *));
610 static int add_to_lit_pool PARAMS ((void));
611 static unsigned validate_immediate PARAMS ((unsigned));
612 static unsigned validate_immediate_twopart PARAMS ((unsigned int, unsigned int *));
613 static int validate_offset_imm PARAMS ((unsigned int, int));
614 static void opcode_select PARAMS ((int));
615 static void end_of_line PARAMS ((char *));
616 static int reg_required_here PARAMS ((char **, int));
617 static int psr_required_here PARAMS ((char **));
618 static int co_proc_number PARAMS ((char **));
619 static int cp_opc_expr PARAMS ((char **, int, int));
620 static int cp_reg_required_here PARAMS ((char **, int));
621 static int fp_reg_required_here PARAMS ((char **, int));
622 static int cp_address_offset PARAMS ((char **));
623 static int cp_address_required_here PARAMS ((char **));
624 static int my_get_float_expression PARAMS ((char **));
625 static int skip_past_comma PARAMS ((char **));
626 static int walk_no_bignums PARAMS ((symbolS *));
627 static int negate_data_op PARAMS ((unsigned long *, unsigned long));
628 static int data_op2 PARAMS ((char **));
629 static int fp_op2 PARAMS ((char **));
630 static long reg_list PARAMS ((char **));
631 static void thumb_load_store PARAMS ((char *, int, int));
632 static int decode_shift PARAMS ((char **, int));
633 static int ldst_extend PARAMS ((char **, int));
634 static void thumb_add_sub PARAMS ((char *, int));
635 static void insert_reg PARAMS ((int));
636 static void thumb_shift PARAMS ((char *, int));
637 static void thumb_mov_compare PARAMS ((char *, int));
638 static void set_constant_flonums PARAMS ((void));
639 static valueT md_chars_to_number PARAMS ((char *, int));
640 static void insert_reg_alias PARAMS ((char *, int));
641 static void output_inst PARAMS ((void));
642 #ifdef OBJ_ELF
643 static bfd_reloc_code_real_type arm_parse_reloc PARAMS ((void));
644 #endif
645
646 /* ARM instructions take 4bytes in the object file, Thumb instructions
647 take 2: */
648 #define INSN_SIZE 4
649
650 /* LONGEST_INST is the longest basic instruction name without conditions or
651 flags. ARM7M has 4 of length 5. */
652
653 #define LONGEST_INST 5
654
655 struct asm_opcode
656 {
657 /* Basic string to match. */
658 CONST char * template;
659
660 /* Basic instruction code. */
661 unsigned long value;
662
663 /* Compulsory suffix that must follow conds. If "", then the
664 instruction is not conditional and must have no suffix. */
665 CONST char * comp_suffix;
666
667 /* Bits to toggle if flag 'n' set. */
668 CONST struct asm_flg * flags;
669
670 /* Which CPU variants this exists for. */
671 unsigned long variants;
672
673 /* Function to call to parse args. */
674 void (* parms) PARAMS ((char *, unsigned long));
675 };
676
677 static CONST struct asm_opcode insns[] =
678 {
679 /* ARM Instructions. */
680 {"and", 0x00000000, NULL, s_flag, ARM_ANY, do_arit},
681 {"eor", 0x00200000, NULL, s_flag, ARM_ANY, do_arit},
682 {"sub", 0x00400000, NULL, s_flag, ARM_ANY, do_arit},
683 {"rsb", 0x00600000, NULL, s_flag, ARM_ANY, do_arit},
684 {"add", 0x00800000, NULL, s_flag, ARM_ANY, do_arit},
685 {"adc", 0x00a00000, NULL, s_flag, ARM_ANY, do_arit},
686 {"sbc", 0x00c00000, NULL, s_flag, ARM_ANY, do_arit},
687 {"rsc", 0x00e00000, NULL, s_flag, ARM_ANY, do_arit},
688 {"orr", 0x01800000, NULL, s_flag, ARM_ANY, do_arit},
689 {"bic", 0x01c00000, NULL, s_flag, ARM_ANY, do_arit},
690 {"tst", 0x01000000, NULL, cmp_flags, ARM_ANY, do_cmp},
691 {"teq", 0x01200000, NULL, cmp_flags, ARM_ANY, do_cmp},
692 {"cmp", 0x01400000, NULL, cmp_flags, ARM_ANY, do_cmp},
693 {"cmn", 0x01600000, NULL, cmp_flags, ARM_ANY, do_cmp},
694 {"mov", 0x01a00000, NULL, s_flag, ARM_ANY, do_mov},
695 {"mvn", 0x01e00000, NULL, s_flag, ARM_ANY, do_mov},
696 {"str", 0x04000000, NULL, str_flags, ARM_ANY, do_ldst},
697 {"ldr", 0x04100000, NULL, ldr_flags, ARM_ANY, do_ldst},
698 {"stm", 0x08000000, NULL, stm_flags, ARM_ANY, do_ldmstm},
699 {"ldm", 0x08100000, NULL, ldm_flags, ARM_ANY, do_ldmstm},
700 {"swi", 0x0f000000, NULL, NULL, ARM_ANY, do_swi},
701 #ifdef TE_WINCE
702 {"bl", 0x0b000000, NULL, NULL, ARM_ANY, do_branch},
703 {"b", 0x0a000000, NULL, NULL, ARM_ANY, do_branch},
704 #else
705 {"bl", 0x0bfffffe, NULL, NULL, ARM_ANY, do_branch},
706 {"b", 0x0afffffe, NULL, NULL, ARM_ANY, do_branch},
707 #endif
708
709 /* Pseudo ops. */
710 {"adr", 0x028f0000, NULL, NULL, ARM_ANY, do_adr},
711 {"adrl", 0x028f0000, NULL, NULL, ARM_ANY, do_adrl},
712 {"nop", 0x01a00000, NULL, NULL, ARM_ANY, do_nop},
713
714 /* ARM 2 multiplies. */
715 {"mul", 0x00000090, NULL, s_flag, ARM_2UP, do_mul},
716 {"mla", 0x00200090, NULL, s_flag, ARM_2UP, do_mla},
717
718 /* ARM 3 - swp instructions. */
719 {"swp", 0x01000090, NULL, byte_flag, ARM_3UP, do_swap},
720
721 /* ARM 6 Coprocessor instructions. */
722 {"mrs", 0x010f0000, NULL, NULL, ARM_6UP, do_mrs},
723 {"msr", 0x0120f000, NULL, NULL, ARM_6UP, do_msr},
724 /* ScottB: our code uses 0x0128f000 for msr.
725 NickC: but this is wrong because the bits 16 through 19 are
726 handled by the PSR_xxx defines above. */
727
728 /* ARM 7M long multiplies - need signed/unsigned flags! */
729 {"smull", 0x00c00090, NULL, s_flag, ARM_LONGMUL, do_mull},
730 {"umull", 0x00800090, NULL, s_flag, ARM_LONGMUL, do_mull},
731 {"smlal", 0x00e00090, NULL, s_flag, ARM_LONGMUL, do_mull},
732 {"umlal", 0x00a00090, NULL, s_flag, ARM_LONGMUL, do_mull},
733
734 /* ARM THUMB interworking. */
735 {"bx", 0x012fff10, NULL, NULL, ARM_THUMB, do_bx},
736
737 /* Floating point instructions. */
738 {"wfs", 0x0e200110, NULL, NULL, FPU_ALL, do_fp_ctrl},
739 {"rfs", 0x0e300110, NULL, NULL, FPU_ALL, do_fp_ctrl},
740 {"wfc", 0x0e400110, NULL, NULL, FPU_ALL, do_fp_ctrl},
741 {"rfc", 0x0e500110, NULL, NULL, FPU_ALL, do_fp_ctrl},
742 {"ldf", 0x0c100100, "sdep", NULL, FPU_ALL, do_fp_ldst},
743 {"stf", 0x0c000100, "sdep", NULL, FPU_ALL, do_fp_ldst},
744 {"lfm", 0x0c100200, NULL, lfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
745 {"sfm", 0x0c000200, NULL, sfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
746 {"mvf", 0x0e008100, "sde", round_flags, FPU_ALL, do_fp_monadic},
747 {"mnf", 0x0e108100, "sde", round_flags, FPU_ALL, do_fp_monadic},
748 {"abs", 0x0e208100, "sde", round_flags, FPU_ALL, do_fp_monadic},
749 {"rnd", 0x0e308100, "sde", round_flags, FPU_ALL, do_fp_monadic},
750 {"sqt", 0x0e408100, "sde", round_flags, FPU_ALL, do_fp_monadic},
751 {"log", 0x0e508100, "sde", round_flags, FPU_ALL, do_fp_monadic},
752 {"lgn", 0x0e608100, "sde", round_flags, FPU_ALL, do_fp_monadic},
753 {"exp", 0x0e708100, "sde", round_flags, FPU_ALL, do_fp_monadic},
754 {"sin", 0x0e808100, "sde", round_flags, FPU_ALL, do_fp_monadic},
755 {"cos", 0x0e908100, "sde", round_flags, FPU_ALL, do_fp_monadic},
756 {"tan", 0x0ea08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
757 {"asn", 0x0eb08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
758 {"acs", 0x0ec08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
759 {"atn", 0x0ed08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
760 {"urd", 0x0ee08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
761 {"nrm", 0x0ef08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
762 {"adf", 0x0e000100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
763 {"suf", 0x0e200100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
764 {"rsf", 0x0e300100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
765 {"muf", 0x0e100100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
766 {"dvf", 0x0e400100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
767 {"rdf", 0x0e500100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
768 {"pow", 0x0e600100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
769 {"rpw", 0x0e700100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
770 {"rmf", 0x0e800100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
771 {"fml", 0x0e900100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
772 {"fdv", 0x0ea00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
773 {"frd", 0x0eb00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
774 {"pol", 0x0ec00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
775 {"cmf", 0x0e90f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
776 {"cnf", 0x0eb0f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
777 /* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should not
778 be an optional suffix, but part of the instruction. To be compatible,
779 we accept either. */
780 {"cmfe", 0x0ed0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
781 {"cnfe", 0x0ef0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
782 {"flt", 0x0e000110, "sde", round_flags, FPU_ALL, do_fp_from_reg},
783 {"fix", 0x0e100110, NULL, fix_flags, FPU_ALL, do_fp_to_reg},
784
785 /* Generic copressor instructions. */
786 {"cdp", 0x0e000000, NULL, NULL, ARM_2UP, do_cdp},
787 {"ldc", 0x0c100000, NULL, cplong_flag, ARM_2UP, do_lstc},
788 {"stc", 0x0c000000, NULL, cplong_flag, ARM_2UP, do_lstc},
789 {"mcr", 0x0e000010, NULL, NULL, ARM_2UP, do_co_reg},
790 {"mrc", 0x0e100010, NULL, NULL, ARM_2UP, do_co_reg},
791 };
792
793 /* Defines for various bits that we will want to toggle. */
794 #define INST_IMMEDIATE 0x02000000
795 #define OFFSET_REG 0x02000000
796 #define HWOFFSET_IMM 0x00400000
797 #define SHIFT_BY_REG 0x00000010
798 #define PRE_INDEX 0x01000000
799 #define INDEX_UP 0x00800000
800 #define WRITE_BACK 0x00200000
801 #define LDM_TYPE_2_OR_3 0x00400000
802
803 #define LITERAL_MASK 0xf000f000
804 #define COND_MASK 0xf0000000
805 #define OPCODE_MASK 0xfe1fffff
806 #define DATA_OP_SHIFT 21
807
808 /* Codes to distinguish the arithmetic instructions. */
809 #define OPCODE_AND 0
810 #define OPCODE_EOR 1
811 #define OPCODE_SUB 2
812 #define OPCODE_RSB 3
813 #define OPCODE_ADD 4
814 #define OPCODE_ADC 5
815 #define OPCODE_SBC 6
816 #define OPCODE_RSC 7
817 #define OPCODE_TST 8
818 #define OPCODE_TEQ 9
819 #define OPCODE_CMP 10
820 #define OPCODE_CMN 11
821 #define OPCODE_ORR 12
822 #define OPCODE_MOV 13
823 #define OPCODE_BIC 14
824 #define OPCODE_MVN 15
825
826 static void do_t_nop PARAMS ((char *));
827 static void do_t_arit PARAMS ((char *));
828 static void do_t_add PARAMS ((char *));
829 static void do_t_asr PARAMS ((char *));
830 static void do_t_branch9 PARAMS ((char *));
831 static void do_t_branch12 PARAMS ((char *));
832 static void do_t_branch23 PARAMS ((char *));
833 static void do_t_bx PARAMS ((char *));
834 static void do_t_compare PARAMS ((char *));
835 static void do_t_ldmstm PARAMS ((char *));
836 static void do_t_ldr PARAMS ((char *));
837 static void do_t_ldrb PARAMS ((char *));
838 static void do_t_ldrh PARAMS ((char *));
839 static void do_t_lds PARAMS ((char *));
840 static void do_t_lsl PARAMS ((char *));
841 static void do_t_lsr PARAMS ((char *));
842 static void do_t_mov PARAMS ((char *));
843 static void do_t_push_pop PARAMS ((char *));
844 static void do_t_str PARAMS ((char *));
845 static void do_t_strb PARAMS ((char *));
846 static void do_t_strh PARAMS ((char *));
847 static void do_t_sub PARAMS ((char *));
848 static void do_t_swi PARAMS ((char *));
849 static void do_t_adr PARAMS ((char *));
850
851 #define T_OPCODE_MUL 0x4340
852 #define T_OPCODE_TST 0x4200
853 #define T_OPCODE_CMN 0x42c0
854 #define T_OPCODE_NEG 0x4240
855 #define T_OPCODE_MVN 0x43c0
856
857 #define T_OPCODE_ADD_R3 0x1800
858 #define T_OPCODE_SUB_R3 0x1a00
859 #define T_OPCODE_ADD_HI 0x4400
860 #define T_OPCODE_ADD_ST 0xb000
861 #define T_OPCODE_SUB_ST 0xb080
862 #define T_OPCODE_ADD_SP 0xa800
863 #define T_OPCODE_ADD_PC 0xa000
864 #define T_OPCODE_ADD_I8 0x3000
865 #define T_OPCODE_SUB_I8 0x3800
866 #define T_OPCODE_ADD_I3 0x1c00
867 #define T_OPCODE_SUB_I3 0x1e00
868
869 #define T_OPCODE_ASR_R 0x4100
870 #define T_OPCODE_LSL_R 0x4080
871 #define T_OPCODE_LSR_R 0x40c0
872 #define T_OPCODE_ASR_I 0x1000
873 #define T_OPCODE_LSL_I 0x0000
874 #define T_OPCODE_LSR_I 0x0800
875
876 #define T_OPCODE_MOV_I8 0x2000
877 #define T_OPCODE_CMP_I8 0x2800
878 #define T_OPCODE_CMP_LR 0x4280
879 #define T_OPCODE_MOV_HR 0x4600
880 #define T_OPCODE_CMP_HR 0x4500
881
882 #define T_OPCODE_LDR_PC 0x4800
883 #define T_OPCODE_LDR_SP 0x9800
884 #define T_OPCODE_STR_SP 0x9000
885 #define T_OPCODE_LDR_IW 0x6800
886 #define T_OPCODE_STR_IW 0x6000
887 #define T_OPCODE_LDR_IH 0x8800
888 #define T_OPCODE_STR_IH 0x8000
889 #define T_OPCODE_LDR_IB 0x7800
890 #define T_OPCODE_STR_IB 0x7000
891 #define T_OPCODE_LDR_RW 0x5800
892 #define T_OPCODE_STR_RW 0x5000
893 #define T_OPCODE_LDR_RH 0x5a00
894 #define T_OPCODE_STR_RH 0x5200
895 #define T_OPCODE_LDR_RB 0x5c00
896 #define T_OPCODE_STR_RB 0x5400
897
898 #define T_OPCODE_PUSH 0xb400
899 #define T_OPCODE_POP 0xbc00
900
901 #define T_OPCODE_BRANCH 0xe7fe
902
903 static int thumb_reg PARAMS ((char ** str, int hi_lo));
904
905 #define THUMB_SIZE 2 /* Size of thumb instruction. */
906 #define THUMB_REG_LO 0x1
907 #define THUMB_REG_HI 0x2
908 #define THUMB_REG_ANY 0x3
909
910 #define THUMB_H1 0x0080
911 #define THUMB_H2 0x0040
912
913 #define THUMB_ASR 0
914 #define THUMB_LSL 1
915 #define THUMB_LSR 2
916
917 #define THUMB_MOVE 0
918 #define THUMB_COMPARE 1
919
920 #define THUMB_LOAD 0
921 #define THUMB_STORE 1
922
923 #define THUMB_PP_PC_LR 0x0100
924
925 /* These three are used for immediate shifts, do not alter. */
926 #define THUMB_WORD 2
927 #define THUMB_HALFWORD 1
928 #define THUMB_BYTE 0
929
930 struct thumb_opcode
931 {
932 /* Basic string to match. */
933 CONST char * template;
934
935 /* Basic instruction code. */
936 unsigned long value;
937
938 int size;
939
940 /* Which CPU variants this exists for. */
941 unsigned long variants;
942
943 /* Function to call to parse args. */
944 void (* parms) PARAMS ((char *));
945 };
946
947 static CONST struct thumb_opcode tinsns[] =
948 {
949 {"adc", 0x4140, 2, ARM_THUMB, do_t_arit},
950 {"add", 0x0000, 2, ARM_THUMB, do_t_add},
951 {"and", 0x4000, 2, ARM_THUMB, do_t_arit},
952 {"asr", 0x0000, 2, ARM_THUMB, do_t_asr},
953 {"b", T_OPCODE_BRANCH, 2, ARM_THUMB, do_t_branch12},
954 {"beq", 0xd0fe, 2, ARM_THUMB, do_t_branch9},
955 {"bne", 0xd1fe, 2, ARM_THUMB, do_t_branch9},
956 {"bcs", 0xd2fe, 2, ARM_THUMB, do_t_branch9},
957 {"bhs", 0xd2fe, 2, ARM_THUMB, do_t_branch9},
958 {"bcc", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
959 {"bul", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
960 {"blo", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
961 {"bmi", 0xd4fe, 2, ARM_THUMB, do_t_branch9},
962 {"bpl", 0xd5fe, 2, ARM_THUMB, do_t_branch9},
963 {"bvs", 0xd6fe, 2, ARM_THUMB, do_t_branch9},
964 {"bvc", 0xd7fe, 2, ARM_THUMB, do_t_branch9},
965 {"bhi", 0xd8fe, 2, ARM_THUMB, do_t_branch9},
966 {"bls", 0xd9fe, 2, ARM_THUMB, do_t_branch9},
967 {"bge", 0xdafe, 2, ARM_THUMB, do_t_branch9},
968 {"blt", 0xdbfe, 2, ARM_THUMB, do_t_branch9},
969 {"bgt", 0xdcfe, 2, ARM_THUMB, do_t_branch9},
970 {"ble", 0xddfe, 2, ARM_THUMB, do_t_branch9},
971 {"bal", 0xdefe, 2, ARM_THUMB, do_t_branch9},
972 {"bic", 0x4380, 2, ARM_THUMB, do_t_arit},
973 {"bl", 0xf7fffffe, 4, ARM_THUMB, do_t_branch23},
974 {"bx", 0x4700, 2, ARM_THUMB, do_t_bx},
975 {"cmn", T_OPCODE_CMN, 2, ARM_THUMB, do_t_arit},
976 {"cmp", 0x0000, 2, ARM_THUMB, do_t_compare},
977 {"eor", 0x4040, 2, ARM_THUMB, do_t_arit},
978 {"ldmia", 0xc800, 2, ARM_THUMB, do_t_ldmstm},
979 {"ldr", 0x0000, 2, ARM_THUMB, do_t_ldr},
980 {"ldrb", 0x0000, 2, ARM_THUMB, do_t_ldrb},
981 {"ldrh", 0x0000, 2, ARM_THUMB, do_t_ldrh},
982 {"ldrsb", 0x5600, 2, ARM_THUMB, do_t_lds},
983 {"ldrsh", 0x5e00, 2, ARM_THUMB, do_t_lds},
984 {"ldsb", 0x5600, 2, ARM_THUMB, do_t_lds},
985 {"ldsh", 0x5e00, 2, ARM_THUMB, do_t_lds},
986 {"lsl", 0x0000, 2, ARM_THUMB, do_t_lsl},
987 {"lsr", 0x0000, 2, ARM_THUMB, do_t_lsr},
988 {"mov", 0x0000, 2, ARM_THUMB, do_t_mov},
989 {"mul", T_OPCODE_MUL, 2, ARM_THUMB, do_t_arit},
990 {"mvn", T_OPCODE_MVN, 2, ARM_THUMB, do_t_arit},
991 {"neg", T_OPCODE_NEG, 2, ARM_THUMB, do_t_arit},
992 {"orr", 0x4300, 2, ARM_THUMB, do_t_arit},
993 {"pop", 0xbc00, 2, ARM_THUMB, do_t_push_pop},
994 {"push", 0xb400, 2, ARM_THUMB, do_t_push_pop},
995 {"ror", 0x41c0, 2, ARM_THUMB, do_t_arit},
996 {"sbc", 0x4180, 2, ARM_THUMB, do_t_arit},
997 {"stmia", 0xc000, 2, ARM_THUMB, do_t_ldmstm},
998 {"str", 0x0000, 2, ARM_THUMB, do_t_str},
999 {"strb", 0x0000, 2, ARM_THUMB, do_t_strb},
1000 {"strh", 0x0000, 2, ARM_THUMB, do_t_strh},
1001 {"swi", 0xdf00, 2, ARM_THUMB, do_t_swi},
1002 {"sub", 0x0000, 2, ARM_THUMB, do_t_sub},
1003 {"tst", T_OPCODE_TST, 2, ARM_THUMB, do_t_arit},
1004 /* Pseudo ops: */
1005 {"adr", 0x0000, 2, ARM_THUMB, do_t_adr},
1006 {"nop", 0x46C0, 2, ARM_THUMB, do_t_nop}, /* mov r8,r8 */
1007 };
1008
1009 struct reg_entry
1010 {
1011 CONST char * name;
1012 int number;
1013 };
1014
1015 #define int_register(reg) ((reg) >= 0 && (reg) <= 15)
1016 #define cp_register(reg) ((reg) >= 32 && (reg) <= 47)
1017 #define fp_register(reg) ((reg) >= 16 && (reg) <= 23)
1018
1019 #define REG_PC 15
1020 #define REG_LR 14
1021 #define REG_SP 13
1022
1023 /* These are the standard names. Users can add aliases with .req. */
1024 static CONST struct reg_entry reg_table[] =
1025 {
1026 /* Processor Register Numbers. */
1027 {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
1028 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
1029 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
1030 {"r12", 12}, {"r13", REG_SP},{"r14", REG_LR},{"r15", REG_PC},
1031 /* APCS conventions. */
1032 {"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3},
1033 {"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8},
1034 {"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10},
1035 {"fp", 11}, {"ip", 12}, {"sp", REG_SP},{"lr", REG_LR},{"pc", REG_PC},
1036 /* ATPCS additions to APCS conventions. */
1037 {"wr", 7}, {"v8", 11},
1038 /* FP Registers. */
1039 {"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19},
1040 {"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23},
1041 {"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35},
1042 {"c4", 36}, {"c5", 37}, {"c6", 38}, {"c7", 39},
1043 {"c8", 40}, {"c9", 41}, {"c10", 42}, {"c11", 43},
1044 {"c12", 44}, {"c13", 45}, {"c14", 46}, {"c15", 47},
1045 {"cr0", 32}, {"cr1", 33}, {"cr2", 34}, {"cr3", 35},
1046 {"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39},
1047 {"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43},
1048 {"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47},
1049 /* ATPCS additions to float register names. */
1050 {"s0",16}, {"s1",17}, {"s2",18}, {"s3",19},
1051 {"s4",20}, {"s5",21}, {"s6",22}, {"s7",23},
1052 {"d0",16}, {"d1",17}, {"d2",18}, {"d3",19},
1053 {"d4",20}, {"d5",21}, {"d6",22}, {"d7",23},
1054 /* FIXME: At some point we need to add VFP register names. */
1055 /* Array terminator. */
1056 {NULL, 0}
1057 };
1058
1059 #define BAD_ARGS _("Bad arguments to instruction")
1060 #define BAD_PC _("r15 not allowed here")
1061 #define BAD_FLAGS _("Instruction should not have flags")
1062 #define BAD_COND _("Instruction is not conditional")
1063
1064 static struct hash_control * arm_ops_hsh = NULL;
1065 static struct hash_control * arm_tops_hsh = NULL;
1066 static struct hash_control * arm_cond_hsh = NULL;
1067 static struct hash_control * arm_shift_hsh = NULL;
1068 static struct hash_control * arm_reg_hsh = NULL;
1069 static struct hash_control * arm_psr_hsh = NULL;
1070
1071 /* This table describes all the machine specific pseudo-ops the assembler
1072 has to support. The fields are:
1073 pseudo-op name without dot
1074 function to call to execute this pseudo-op
1075 Integer arg to pass to the function. */
1076
1077 static void s_req PARAMS ((int));
1078 static void s_align PARAMS ((int));
1079 static void s_bss PARAMS ((int));
1080 static void s_even PARAMS ((int));
1081 static void s_ltorg PARAMS ((int));
1082 static void s_arm PARAMS ((int));
1083 static void s_thumb PARAMS ((int));
1084 static void s_code PARAMS ((int));
1085 static void s_force_thumb PARAMS ((int));
1086 static void s_thumb_func PARAMS ((int));
1087 static void s_thumb_set PARAMS ((int));
1088 static void arm_s_text PARAMS ((int));
1089 static void arm_s_data PARAMS ((int));
1090 #ifdef OBJ_ELF
1091 static void arm_s_section PARAMS ((int));
1092 static void s_arm_elf_cons PARAMS ((int));
1093 #endif
1094
1095 static int my_get_expression PARAMS ((expressionS *, char **));
1096
1097 CONST pseudo_typeS md_pseudo_table[] =
1098 {
1099 /* Never called becasue '.req' does not start line. */
1100 { "req", s_req, 0 },
1101 { "bss", s_bss, 0 },
1102 { "align", s_align, 0 },
1103 { "arm", s_arm, 0 },
1104 { "thumb", s_thumb, 0 },
1105 { "code", s_code, 0 },
1106 { "force_thumb", s_force_thumb, 0 },
1107 { "thumb_func", s_thumb_func, 0 },
1108 { "thumb_set", s_thumb_set, 0 },
1109 { "even", s_even, 0 },
1110 { "ltorg", s_ltorg, 0 },
1111 { "pool", s_ltorg, 0 },
1112 /* Allow for the effect of section changes. */
1113 { "text", arm_s_text, 0 },
1114 { "data", arm_s_data, 0 },
1115 #ifdef OBJ_ELF
1116 { "section", arm_s_section, 0 },
1117 { "section.s", arm_s_section, 0 },
1118 { "sect", arm_s_section, 0 },
1119 { "sect.s", arm_s_section, 0 },
1120 { "word", s_arm_elf_cons, 4 },
1121 { "long", s_arm_elf_cons, 4 },
1122 #else
1123 { "word", cons, 4},
1124 #endif
1125 { "extend", float_cons, 'x' },
1126 { "ldouble", float_cons, 'x' },
1127 { "packed", float_cons, 'p' },
1128 { 0, 0, 0 }
1129 };
1130
1131 /* Stuff needed to resolve the label ambiguity
1132 As:
1133 ...
1134 label: <insn>
1135 may differ from:
1136 ...
1137 label:
1138 <insn>
1139 */
1140
1141 symbolS * last_label_seen;
1142 static int label_is_thumb_function_name = false;
1143
1144 /* Literal stuff. */
1145
1146 #define MAX_LITERAL_POOL_SIZE 1024
1147
1148 typedef struct literalS
1149 {
1150 struct expressionS exp;
1151 struct arm_it * inst;
1152 } literalT;
1153
1154 literalT literals[MAX_LITERAL_POOL_SIZE];
1155
1156 /* Next free entry in the pool. */
1157 int next_literal_pool_place = 0;
1158
1159 /* Next literal pool number. */
1160 int lit_pool_num = 1;
1161
1162 symbolS * current_poolP = NULL;
1163
1164 static int
1165 add_to_lit_pool ()
1166 {
1167 int lit_count = 0;
1168
1169 if (current_poolP == NULL)
1170 current_poolP = symbol_create (FAKE_LABEL_NAME, undefined_section,
1171 (valueT) 0, &zero_address_frag);
1172
1173 /* Check if this literal value is already in the pool: */
1174 while (lit_count < next_literal_pool_place)
1175 {
1176 if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op
1177 && inst.reloc.exp.X_op == O_constant
1178 && (literals[lit_count].exp.X_add_number
1179 == inst.reloc.exp.X_add_number)
1180 && literals[lit_count].exp.X_unsigned == inst.reloc.exp.X_unsigned)
1181 break;
1182 lit_count++;
1183 }
1184
1185 if (lit_count == next_literal_pool_place) /* New entry. */
1186 {
1187 if (next_literal_pool_place > MAX_LITERAL_POOL_SIZE)
1188 {
1189 inst.error = _("Literal Pool Overflow");
1190 return FAIL;
1191 }
1192
1193 literals[next_literal_pool_place].exp = inst.reloc.exp;
1194 lit_count = next_literal_pool_place++;
1195 }
1196
1197 inst.reloc.exp.X_op = O_symbol;
1198 inst.reloc.exp.X_add_number = (lit_count) * 4 - 8;
1199 inst.reloc.exp.X_add_symbol = current_poolP;
1200
1201 return SUCCESS;
1202 }
1203
1204 /* Can't use symbol_new here, so have to create a symbol and then at
1205 a later date assign it a value. Thats what these functions do. */
1206
1207 static void
1208 symbol_locate (symbolP, name, segment, valu, frag)
1209 symbolS * symbolP;
1210 CONST char * name; /* It is copied, the caller can modify. */
1211 segT segment; /* Segment identifier (SEG_<something>). */
1212 valueT valu; /* Symbol value. */
1213 fragS * frag; /* Associated fragment. */
1214 {
1215 unsigned int name_length;
1216 char * preserved_copy_of_name;
1217
1218 name_length = strlen (name) + 1; /* +1 for \0. */
1219 obstack_grow (&notes, name, name_length);
1220 preserved_copy_of_name = obstack_finish (&notes);
1221 #ifdef STRIP_UNDERSCORE
1222 if (preserved_copy_of_name[0] == '_')
1223 preserved_copy_of_name++;
1224 #endif
1225
1226 #ifdef tc_canonicalize_symbol_name
1227 preserved_copy_of_name =
1228 tc_canonicalize_symbol_name (preserved_copy_of_name);
1229 #endif
1230
1231 S_SET_NAME (symbolP, preserved_copy_of_name);
1232
1233 S_SET_SEGMENT (symbolP, segment);
1234 S_SET_VALUE (symbolP, valu);
1235 symbol_clear_list_pointers(symbolP);
1236
1237 symbol_set_frag (symbolP, frag);
1238
1239 /* Link to end of symbol chain. */
1240 {
1241 extern int symbol_table_frozen;
1242 if (symbol_table_frozen)
1243 abort ();
1244 }
1245
1246 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
1247
1248 obj_symbol_new_hook (symbolP);
1249
1250 #ifdef tc_symbol_new_hook
1251 tc_symbol_new_hook (symbolP);
1252 #endif
1253
1254 #ifdef DEBUG_SYMS
1255 verify_symbol_chain (symbol_rootP, symbol_lastP);
1256 #endif /* DEBUG_SYMS */
1257 }
1258
1259 /* Check that an immediate is valid.
1260 If so, convert it to the right format. */
1261
1262 static unsigned int
1263 validate_immediate (val)
1264 unsigned int val;
1265 {
1266 unsigned int a;
1267 unsigned int i;
1268
1269 #define rotate_left(v, n) (v << n | v >> (32 - n))
1270
1271 for (i = 0; i < 32; i += 2)
1272 if ((a = rotate_left (val, i)) <= 0xff)
1273 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
1274
1275 return FAIL;
1276 }
1277
1278 /* Check to see if an immediate can be computed as two seperate immediate
1279 values, added together. We already know that this value cannot be
1280 computed by just one ARM instruction. */
1281
1282 static unsigned int
1283 validate_immediate_twopart (val, highpart)
1284 unsigned int val;
1285 unsigned int * highpart;
1286 {
1287 unsigned int a;
1288 unsigned int i;
1289
1290 for (i = 0; i < 32; i += 2)
1291 if (((a = rotate_left (val, i)) & 0xff) != 0)
1292 {
1293 if (a & 0xff00)
1294 {
1295 if (a & ~ 0xffff)
1296 continue;
1297 * highpart = (a >> 8) | ((i + 24) << 7);
1298 }
1299 else if (a & 0xff0000)
1300 {
1301 if (a & 0xff000000)
1302 continue;
1303 * highpart = (a >> 16) | ((i + 16) << 7);
1304 }
1305 else
1306 {
1307 assert (a & 0xff000000);
1308 * highpart = (a >> 24) | ((i + 8) << 7);
1309 }
1310
1311 return (a & 0xff) | (i << 7);
1312 }
1313
1314 return FAIL;
1315 }
1316
1317 static int
1318 validate_offset_imm (val, hwse)
1319 unsigned int val;
1320 int hwse;
1321 {
1322 if ((hwse && val > 255) || val > 4095)
1323 return FAIL;
1324 return val;
1325 }
1326
1327 static void
1328 s_req (a)
1329 int a ATTRIBUTE_UNUSED;
1330 {
1331 as_bad (_("Invalid syntax for .req directive."));
1332 }
1333
1334 static void
1335 s_bss (ignore)
1336 int ignore ATTRIBUTE_UNUSED;
1337 {
1338 /* We don't support putting frags in the BSS segment, we fake it by
1339 marking in_bss, then looking at s_skip for clues. */
1340 subseg_set (bss_section, 0);
1341 demand_empty_rest_of_line ();
1342 }
1343
1344 static void
1345 s_even (ignore)
1346 int ignore ATTRIBUTE_UNUSED;
1347 {
1348 /* Never make frag if expect extra pass. */
1349 if (!need_pass_2)
1350 frag_align (1, 0, 0);
1351
1352 record_alignment (now_seg, 1);
1353
1354 demand_empty_rest_of_line ();
1355 }
1356
1357 static void
1358 s_ltorg (ignored)
1359 int ignored ATTRIBUTE_UNUSED;
1360 {
1361 int lit_count = 0;
1362 char sym_name[20];
1363
1364 if (current_poolP == NULL)
1365 return;
1366
1367 /* Align pool as you have word accesses.
1368 Only make a frag if we have to. */
1369 if (!need_pass_2)
1370 frag_align (2, 0, 0);
1371
1372 record_alignment (now_seg, 2);
1373
1374 sprintf (sym_name, "$$lit_\002%x", lit_pool_num++);
1375
1376 symbol_locate (current_poolP, sym_name, now_seg,
1377 (valueT) frag_now_fix (), frag_now);
1378 symbol_table_insert (current_poolP);
1379
1380 ARM_SET_THUMB (current_poolP, thumb_mode);
1381
1382 #if defined OBJ_COFF || defined OBJ_ELF
1383 ARM_SET_INTERWORK (current_poolP, support_interwork);
1384 #endif
1385
1386 while (lit_count < next_literal_pool_place)
1387 /* First output the expression in the instruction to the pool. */
1388 emit_expr (&(literals[lit_count++].exp), 4); /* .word */
1389
1390 next_literal_pool_place = 0;
1391 current_poolP = NULL;
1392 }
1393
1394 /* Same as s_align_ptwo but align 0 => align 2. */
1395
1396 static void
1397 s_align (unused)
1398 int unused ATTRIBUTE_UNUSED;
1399 {
1400 register int temp;
1401 register long temp_fill;
1402 long max_alignment = 15;
1403
1404 temp = get_absolute_expression ();
1405 if (temp > max_alignment)
1406 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
1407 else if (temp < 0)
1408 {
1409 as_bad (_("Alignment negative. 0 assumed."));
1410 temp = 0;
1411 }
1412
1413 if (*input_line_pointer == ',')
1414 {
1415 input_line_pointer++;
1416 temp_fill = get_absolute_expression ();
1417 }
1418 else
1419 temp_fill = 0;
1420
1421 if (!temp)
1422 temp = 2;
1423
1424 /* Only make a frag if we HAVE to. */
1425 if (temp && !need_pass_2)
1426 frag_align (temp, (int) temp_fill, 0);
1427 demand_empty_rest_of_line ();
1428
1429 record_alignment (now_seg, temp);
1430 }
1431
1432 static void
1433 s_force_thumb (ignore)
1434 int ignore ATTRIBUTE_UNUSED;
1435 {
1436 /* If we are not already in thumb mode go into it, EVEN if
1437 the target processor does not support thumb instructions.
1438 This is used by gcc/config/arm/lib1funcs.asm for example
1439 to compile interworking support functions even if the
1440 target processor should not support interworking. */
1441 if (! thumb_mode)
1442 {
1443 thumb_mode = 2;
1444
1445 record_alignment (now_seg, 1);
1446 }
1447
1448 demand_empty_rest_of_line ();
1449 }
1450
1451 static void
1452 s_thumb_func (ignore)
1453 int ignore ATTRIBUTE_UNUSED;
1454 {
1455 if (! thumb_mode)
1456 opcode_select (16);
1457
1458 /* The following label is the name/address of the start of a Thumb function.
1459 We need to know this for the interworking support. */
1460 label_is_thumb_function_name = true;
1461
1462 demand_empty_rest_of_line ();
1463 }
1464
1465 /* Perform a .set directive, but also mark the alias as
1466 being a thumb function. */
1467
1468 static void
1469 s_thumb_set (equiv)
1470 int equiv;
1471 {
1472 /* XXX the following is a duplicate of the code for s_set() in read.c
1473 We cannot just call that code as we need to get at the symbol that
1474 is created. */
1475 register char * name;
1476 register char delim;
1477 register char * end_name;
1478 register symbolS * symbolP;
1479
1480 /* Especial apologies for the random logic:
1481 This just grew, and could be parsed much more simply!
1482 Dean - in haste. */
1483 name = input_line_pointer;
1484 delim = get_symbol_end ();
1485 end_name = input_line_pointer;
1486 *end_name = delim;
1487
1488 SKIP_WHITESPACE ();
1489
1490 if (*input_line_pointer != ',')
1491 {
1492 *end_name = 0;
1493 as_bad (_("Expected comma after name \"%s\""), name);
1494 *end_name = delim;
1495 ignore_rest_of_line ();
1496 return;
1497 }
1498
1499 input_line_pointer++;
1500 *end_name = 0;
1501
1502 if (name[0] == '.' && name[1] == '\0')
1503 {
1504 /* XXX - this should not happen to .thumb_set. */
1505 abort ();
1506 }
1507
1508 if ((symbolP = symbol_find (name)) == NULL
1509 && (symbolP = md_undefined_symbol (name)) == NULL)
1510 {
1511 #ifndef NO_LISTING
1512 /* When doing symbol listings, play games with dummy fragments living
1513 outside the normal fragment chain to record the file and line info
1514 for this symbol. */
1515 if (listing & LISTING_SYMBOLS)
1516 {
1517 extern struct list_info_struct * listing_tail;
1518 fragS * dummy_frag = (fragS *) xmalloc (sizeof (fragS));
1519
1520 memset (dummy_frag, 0, sizeof (fragS));
1521 dummy_frag->fr_type = rs_fill;
1522 dummy_frag->line = listing_tail;
1523 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
1524 dummy_frag->fr_symbol = symbolP;
1525 }
1526 else
1527 #endif
1528 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
1529
1530 #ifdef OBJ_COFF
1531 /* "set" symbols are local unless otherwise specified. */
1532 SF_SET_LOCAL (symbolP);
1533 #endif /* OBJ_COFF */
1534 } /* Make a new symbol. */
1535
1536 symbol_table_insert (symbolP);
1537
1538 * end_name = delim;
1539
1540 if (equiv
1541 && S_IS_DEFINED (symbolP)
1542 && S_GET_SEGMENT (symbolP) != reg_section)
1543 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
1544
1545 pseudo_set (symbolP);
1546
1547 demand_empty_rest_of_line ();
1548
1549 /* XXX Now we come to the Thumb specific bit of code. */
1550
1551 THUMB_SET_FUNC (symbolP, 1);
1552 ARM_SET_THUMB (symbolP, 1);
1553 #if defined OBJ_ELF || defined OBJ_COFF
1554 ARM_SET_INTERWORK (symbolP, support_interwork);
1555 #endif
1556 }
1557
1558 /* If we change section we must dump the literal pool first. */
1559
1560 static void
1561 arm_s_text (ignore)
1562 int ignore;
1563 {
1564 if (now_seg != text_section)
1565 s_ltorg (0);
1566
1567 #ifdef OBJ_ELF
1568 obj_elf_text (ignore);
1569 #else
1570 s_text (ignore);
1571 #endif
1572 }
1573
1574 static void
1575 arm_s_data (ignore)
1576 int ignore;
1577 {
1578 if (flag_readonly_data_in_text)
1579 {
1580 if (now_seg != text_section)
1581 s_ltorg (0);
1582 }
1583 else if (now_seg != data_section)
1584 s_ltorg (0);
1585
1586 #ifdef OBJ_ELF
1587 obj_elf_data (ignore);
1588 #else
1589 s_data (ignore);
1590 #endif
1591 }
1592
1593 #ifdef OBJ_ELF
1594 static void
1595 arm_s_section (ignore)
1596 int ignore;
1597 {
1598 s_ltorg (0);
1599
1600 obj_elf_section (ignore);
1601 }
1602 #endif
1603
1604 static void
1605 opcode_select (width)
1606 int width;
1607 {
1608 switch (width)
1609 {
1610 case 16:
1611 if (! thumb_mode)
1612 {
1613 if (! (cpu_variant & ARM_THUMB))
1614 as_bad (_("selected processor does not support THUMB opcodes"));
1615
1616 thumb_mode = 1;
1617 /* No need to force the alignment, since we will have been
1618 coming from ARM mode, which is word-aligned. */
1619 record_alignment (now_seg, 1);
1620 }
1621 break;
1622
1623 case 32:
1624 if (thumb_mode)
1625 {
1626 if ((cpu_variant & ARM_ANY) == ARM_THUMB)
1627 as_bad (_("selected processor does not support ARM opcodes"));
1628
1629 thumb_mode = 0;
1630
1631 if (!need_pass_2)
1632 frag_align (2, 0, 0);
1633
1634 record_alignment (now_seg, 1);
1635 }
1636 break;
1637
1638 default:
1639 as_bad (_("invalid instruction size selected (%d)"), width);
1640 }
1641 }
1642
1643 static void
1644 s_arm (ignore)
1645 int ignore ATTRIBUTE_UNUSED;
1646 {
1647 opcode_select (32);
1648 demand_empty_rest_of_line ();
1649 }
1650
1651 static void
1652 s_thumb (ignore)
1653 int ignore ATTRIBUTE_UNUSED;
1654 {
1655 opcode_select (16);
1656 demand_empty_rest_of_line ();
1657 }
1658
1659 static void
1660 s_code (unused)
1661 int unused ATTRIBUTE_UNUSED;
1662 {
1663 register int temp;
1664
1665 temp = get_absolute_expression ();
1666 switch (temp)
1667 {
1668 case 16:
1669 case 32:
1670 opcode_select (temp);
1671 break;
1672
1673 default:
1674 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
1675 }
1676 }
1677
1678 static void
1679 end_of_line (str)
1680 char * str;
1681 {
1682 skip_whitespace (str);
1683
1684 if (* str != '\0')
1685 inst.error = _("Garbage following instruction");
1686 }
1687
1688 static int
1689 skip_past_comma (str)
1690 char ** str;
1691 {
1692 char * p = * str, c;
1693 int comma = 0;
1694
1695 while ((c = *p) == ' ' || c == ',')
1696 {
1697 p++;
1698 if (c == ',' && comma++)
1699 return FAIL;
1700 }
1701
1702 if (c == '\0')
1703 return FAIL;
1704
1705 *str = p;
1706 return comma ? SUCCESS : FAIL;
1707 }
1708
1709 /* A standard register must be given at this point.
1710 SHIFT is the place to put it in inst.instruction.
1711 Restores input start point on error.
1712 Returns the reg#, or FAIL. */
1713
1714 static int
1715 reg_required_here (str, shift)
1716 char ** str;
1717 int shift;
1718 {
1719 static char buff [128]; /* XXX */
1720 int reg;
1721 char * start = * str;
1722
1723 if ((reg = arm_reg_parse (str)) != FAIL && int_register (reg))
1724 {
1725 if (shift >= 0)
1726 inst.instruction |= reg << shift;
1727 return reg;
1728 }
1729
1730 /* Restore the start point, we may have got a reg of the wrong class. */
1731 *str = start;
1732
1733 /* In the few cases where we might be able to accept something else
1734 this error can be overridden. */
1735 sprintf (buff, _("Register expected, not '%.100s'"), start);
1736 inst.error = buff;
1737
1738 return FAIL;
1739 }
1740
1741 static CONST struct asm_psr *
1742 arm_psr_parse (ccp)
1743 register char ** ccp;
1744 {
1745 char * start = * ccp;
1746 char c;
1747 char * p;
1748 CONST struct asm_psr * psr;
1749
1750 p = start;
1751
1752 /* Skip to the end of the next word in the input stream. */
1753 do
1754 {
1755 c = *p++;
1756 }
1757 while (isalpha (c) || c == '_');
1758
1759 /* Terminate the word. */
1760 *--p = 0;
1761
1762 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
1763 feature for ease of use and backwards compatibility. */
1764 if (!strncmp (start, "cpsr", 4))
1765 strncpy (start, "CPSR", 4);
1766 else if (!strncmp (start, "spsr", 4))
1767 strncpy (start, "SPSR", 4);
1768
1769 /* Now locate the word in the psr hash table. */
1770 psr = (CONST struct asm_psr *) hash_find (arm_psr_hsh, start);
1771
1772 /* Restore the input stream. */
1773 *p = c;
1774
1775 /* If we found a valid match, advance the
1776 stream pointer past the end of the word. */
1777 *ccp = p;
1778
1779 return psr;
1780 }
1781
1782 /* Parse the input looking for a PSR flag. */
1783
1784 static int
1785 psr_required_here (str)
1786 char ** str;
1787 {
1788 char * start = * str;
1789 CONST struct asm_psr * psr;
1790
1791 psr = arm_psr_parse (str);
1792
1793 if (psr)
1794 {
1795 /* If this is the SPSR that is being modified, set the R bit. */
1796 if (! psr->cpsr)
1797 inst.instruction |= SPSR_BIT;
1798
1799 /* Set the psr flags in the MSR instruction. */
1800 inst.instruction |= psr->field << PSR_SHIFT;
1801
1802 return SUCCESS;
1803 }
1804
1805 /* In the few cases where we might be able to accept
1806 something else this error can be overridden. */
1807 inst.error = _("flag for {c}psr instruction expected");
1808
1809 /* Restore the start point. */
1810 *str = start;
1811 return FAIL;
1812 }
1813
1814 static int
1815 co_proc_number (str)
1816 char ** str;
1817 {
1818 int processor, pchar;
1819
1820 skip_whitespace (* str);
1821
1822 /* The data sheet seems to imply that just a number on its own is valid
1823 here, but the RISC iX assembler seems to accept a prefix 'p'. We will
1824 accept either. */
1825 if (**str == 'p' || **str == 'P')
1826 (*str)++;
1827
1828 pchar = *(*str)++;
1829 if (pchar >= '0' && pchar <= '9')
1830 {
1831 processor = pchar - '0';
1832 if (**str >= '0' && **str <= '9')
1833 {
1834 processor = processor * 10 + *(*str)++ - '0';
1835 if (processor > 15)
1836 {
1837 inst.error = _("Illegal co-processor number");
1838 return FAIL;
1839 }
1840 }
1841 }
1842 else
1843 {
1844 inst.error = _("Bad or missing co-processor number");
1845 return FAIL;
1846 }
1847
1848 inst.instruction |= processor << 8;
1849 return SUCCESS;
1850 }
1851
1852 static int
1853 cp_opc_expr (str, where, length)
1854 char ** str;
1855 int where;
1856 int length;
1857 {
1858 expressionS expr;
1859
1860 skip_whitespace (* str);
1861
1862 memset (&expr, '\0', sizeof (expr));
1863
1864 if (my_get_expression (&expr, str))
1865 return FAIL;
1866 if (expr.X_op != O_constant)
1867 {
1868 inst.error = _("bad or missing expression");
1869 return FAIL;
1870 }
1871
1872 if ((expr.X_add_number & ((1 << length) - 1)) != expr.X_add_number)
1873 {
1874 inst.error = _("immediate co-processor expression too large");
1875 return FAIL;
1876 }
1877
1878 inst.instruction |= expr.X_add_number << where;
1879 return SUCCESS;
1880 }
1881
1882 static int
1883 cp_reg_required_here (str, where)
1884 char ** str;
1885 int where;
1886 {
1887 int reg;
1888 char * start = *str;
1889
1890 if ((reg = arm_reg_parse (str)) != FAIL && cp_register (reg))
1891 {
1892 reg &= 15;
1893 inst.instruction |= reg << where;
1894 return reg;
1895 }
1896
1897 /* In the few cases where we might be able to accept something else
1898 this error can be overridden. */
1899 inst.error = _("Co-processor register expected");
1900
1901 /* Restore the start point. */
1902 *str = start;
1903 return FAIL;
1904 }
1905
1906 static int
1907 fp_reg_required_here (str, where)
1908 char ** str;
1909 int where;
1910 {
1911 int reg;
1912 char * start = * str;
1913
1914 if ((reg = arm_reg_parse (str)) != FAIL && fp_register (reg))
1915 {
1916 reg &= 7;
1917 inst.instruction |= reg << where;
1918 return reg;
1919 }
1920
1921 /* In the few cases where we might be able to accept something else
1922 this error can be overridden. */
1923 inst.error = _("Floating point register expected");
1924
1925 /* Restore the start point. */
1926 *str = start;
1927 return FAIL;
1928 }
1929
1930 static int
1931 cp_address_offset (str)
1932 char ** str;
1933 {
1934 int offset;
1935
1936 skip_whitespace (* str);
1937
1938 if (! is_immediate_prefix (**str))
1939 {
1940 inst.error = _("immediate expression expected");
1941 return FAIL;
1942 }
1943
1944 (*str)++;
1945
1946 if (my_get_expression (& inst.reloc.exp, str))
1947 return FAIL;
1948
1949 if (inst.reloc.exp.X_op == O_constant)
1950 {
1951 offset = inst.reloc.exp.X_add_number;
1952
1953 if (offset & 3)
1954 {
1955 inst.error = _("co-processor address must be word aligned");
1956 return FAIL;
1957 }
1958
1959 if (offset > 1023 || offset < -1023)
1960 {
1961 inst.error = _("offset too large");
1962 return FAIL;
1963 }
1964
1965 if (offset >= 0)
1966 inst.instruction |= INDEX_UP;
1967 else
1968 offset = -offset;
1969
1970 inst.instruction |= offset >> 2;
1971 }
1972 else
1973 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
1974
1975 return SUCCESS;
1976 }
1977
1978 static int
1979 cp_address_required_here (str)
1980 char ** str;
1981 {
1982 char * p = * str;
1983 int pre_inc = 0;
1984 int write_back = 0;
1985
1986 if (*p == '[')
1987 {
1988 int reg;
1989
1990 p++;
1991 skip_whitespace (p);
1992
1993 if ((reg = reg_required_here (& p, 16)) == FAIL)
1994 return FAIL;
1995
1996 skip_whitespace (p);
1997
1998 if (*p == ']')
1999 {
2000 p++;
2001
2002 if (skip_past_comma (& p) == SUCCESS)
2003 {
2004 /* [Rn], #expr */
2005 write_back = WRITE_BACK;
2006
2007 if (reg == REG_PC)
2008 {
2009 inst.error = _("pc may not be used in post-increment");
2010 return FAIL;
2011 }
2012
2013 if (cp_address_offset (& p) == FAIL)
2014 return FAIL;
2015 }
2016 else
2017 pre_inc = PRE_INDEX | INDEX_UP;
2018 }
2019 else
2020 {
2021 /* '['Rn, #expr']'[!] */
2022
2023 if (skip_past_comma (& p) == FAIL)
2024 {
2025 inst.error = _("pre-indexed expression expected");
2026 return FAIL;
2027 }
2028
2029 pre_inc = PRE_INDEX;
2030
2031 if (cp_address_offset (& p) == FAIL)
2032 return FAIL;
2033
2034 skip_whitespace (p);
2035
2036 if (*p++ != ']')
2037 {
2038 inst.error = _("missing ]");
2039 return FAIL;
2040 }
2041
2042 skip_whitespace (p);
2043
2044 if (*p == '!')
2045 {
2046 if (reg == REG_PC)
2047 {
2048 inst.error = _("pc may not be used with write-back");
2049 return FAIL;
2050 }
2051
2052 p++;
2053 write_back = WRITE_BACK;
2054 }
2055 }
2056 }
2057 else
2058 {
2059 if (my_get_expression (&inst.reloc.exp, &p))
2060 return FAIL;
2061
2062 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
2063 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust. */
2064 inst.reloc.pc_rel = 1;
2065 inst.instruction |= (REG_PC << 16);
2066 pre_inc = PRE_INDEX;
2067 }
2068
2069 inst.instruction |= write_back | pre_inc;
2070 *str = p;
2071 return SUCCESS;
2072 }
2073
2074 static void
2075 do_nop (str, flags)
2076 char * str;
2077 unsigned long flags;
2078 {
2079 /* Do nothing really. */
2080 inst.instruction |= flags; /* This is pointless. */
2081 end_of_line (str);
2082 return;
2083 }
2084
2085 static void
2086 do_mrs (str, flags)
2087 char *str;
2088 unsigned long flags;
2089 {
2090 int skip = 0;
2091
2092 /* Only one syntax. */
2093 skip_whitespace (str);
2094
2095 if (reg_required_here (&str, 12) == FAIL)
2096 {
2097 inst.error = BAD_ARGS;
2098 return;
2099 }
2100
2101 if (skip_past_comma (&str) == FAIL)
2102 {
2103 inst.error = _("comma expected after register name");
2104 return;
2105 }
2106
2107 skip_whitespace (str);
2108
2109 if ( strcmp (str, "CPSR") == 0
2110 || strcmp (str, "SPSR") == 0
2111 /* Lower case versions for backwards compatability. */
2112 || strcmp (str, "cpsr") == 0
2113 || strcmp (str, "spsr") == 0)
2114 skip = 4;
2115
2116 /* This is for backwards compatability with older toolchains. */
2117 else if ( strcmp (str, "cpsr_all") == 0
2118 || strcmp (str, "spsr_all") == 0)
2119 skip = 8;
2120 else
2121 {
2122 inst.error = _("{C|S}PSR expected");
2123 return;
2124 }
2125
2126 if (* str == 's' || * str == 'S')
2127 inst.instruction |= SPSR_BIT;
2128 str += skip;
2129
2130 inst.instruction |= flags;
2131 end_of_line (str);
2132 }
2133
2134 /* Two possible forms:
2135 "{C|S}PSR_<field>, Rm",
2136 "{C|S}PSR_f, #expression". */
2137
2138 static void
2139 do_msr (str, flags)
2140 char * str;
2141 unsigned long flags;
2142 {
2143 skip_whitespace (str);
2144
2145 if (psr_required_here (& str) == FAIL)
2146 return;
2147
2148 if (skip_past_comma (& str) == FAIL)
2149 {
2150 inst.error = _("comma missing after psr flags");
2151 return;
2152 }
2153
2154 skip_whitespace (str);
2155
2156 if (reg_required_here (& str, 0) != FAIL)
2157 {
2158 inst.error = NULL;
2159 inst.instruction |= flags;
2160 end_of_line (str);
2161 return;
2162 }
2163
2164 if (! is_immediate_prefix (* str))
2165 {
2166 inst.error =
2167 _("only a register or immediate value can follow a psr flag");
2168 return;
2169 }
2170
2171 str ++;
2172 inst.error = NULL;
2173
2174 if (my_get_expression (& inst.reloc.exp, & str))
2175 {
2176 inst.error =
2177 _("only a register or immediate value can follow a psr flag");
2178 return;
2179 }
2180
2181 if (inst.instruction & ((PSR_c | PSR_x | PSR_s) << PSR_SHIFT))
2182 {
2183 inst.error = _("only flag field of psr can be set with immediate value");
2184 return;
2185 }
2186
2187 flags |= INST_IMMEDIATE;
2188
2189 if (inst.reloc.exp.X_add_symbol)
2190 {
2191 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2192 inst.reloc.pc_rel = 0;
2193 }
2194 else
2195 {
2196 unsigned value = validate_immediate (inst.reloc.exp.X_add_number);
2197
2198 if (value == (unsigned) FAIL)
2199 {
2200 inst.error = _("Invalid constant");
2201 return;
2202 }
2203
2204 inst.instruction |= value;
2205 }
2206
2207 inst.error = NULL;
2208 inst.instruction |= flags;
2209 end_of_line (str);
2210 }
2211
2212 /* Long Multiply Parser
2213 UMULL RdLo, RdHi, Rm, Rs
2214 SMULL RdLo, RdHi, Rm, Rs
2215 UMLAL RdLo, RdHi, Rm, Rs
2216 SMLAL RdLo, RdHi, Rm, Rs. */
2217
2218 static void
2219 do_mull (str, flags)
2220 char * str;
2221 unsigned long flags;
2222 {
2223 int rdlo, rdhi, rm, rs;
2224
2225 /* Only one format "rdlo, rdhi, rm, rs". */
2226 skip_whitespace (str);
2227
2228 if ((rdlo = reg_required_here (&str, 12)) == FAIL)
2229 {
2230 inst.error = BAD_ARGS;
2231 return;
2232 }
2233
2234 if (skip_past_comma (&str) == FAIL
2235 || (rdhi = reg_required_here (&str, 16)) == FAIL)
2236 {
2237 inst.error = BAD_ARGS;
2238 return;
2239 }
2240
2241 if (skip_past_comma (&str) == FAIL
2242 || (rm = reg_required_here (&str, 0)) == FAIL)
2243 {
2244 inst.error = BAD_ARGS;
2245 return;
2246 }
2247
2248 /* rdhi, rdlo and rm must all be different. */
2249 if (rdlo == rdhi || rdlo == rm || rdhi == rm)
2250 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
2251
2252 if (skip_past_comma (&str) == FAIL
2253 || (rs = reg_required_here (&str, 8)) == FAIL)
2254 {
2255 inst.error = BAD_ARGS;
2256 return;
2257 }
2258
2259 if (rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC)
2260 {
2261 inst.error = BAD_PC;
2262 return;
2263 }
2264
2265 inst.instruction |= flags;
2266 end_of_line (str);
2267 return;
2268 }
2269
2270 static void
2271 do_mul (str, flags)
2272 char * str;
2273 unsigned long flags;
2274 {
2275 int rd, rm;
2276
2277 /* Only one format "rd, rm, rs". */
2278 skip_whitespace (str);
2279
2280 if ((rd = reg_required_here (&str, 16)) == FAIL)
2281 {
2282 inst.error = BAD_ARGS;
2283 return;
2284 }
2285
2286 if (rd == REG_PC)
2287 {
2288 inst.error = BAD_PC;
2289 return;
2290 }
2291
2292 if (skip_past_comma (&str) == FAIL
2293 || (rm = reg_required_here (&str, 0)) == FAIL)
2294 {
2295 inst.error = BAD_ARGS;
2296 return;
2297 }
2298
2299 if (rm == REG_PC)
2300 {
2301 inst.error = BAD_PC;
2302 return;
2303 }
2304
2305 if (rm == rd)
2306 as_tsktsk (_("rd and rm should be different in mul"));
2307
2308 if (skip_past_comma (&str) == FAIL
2309 || (rm = reg_required_here (&str, 8)) == FAIL)
2310 {
2311 inst.error = BAD_ARGS;
2312 return;
2313 }
2314
2315 if (rm == REG_PC)
2316 {
2317 inst.error = BAD_PC;
2318 return;
2319 }
2320
2321 inst.instruction |= flags;
2322 end_of_line (str);
2323 return;
2324 }
2325
2326 static void
2327 do_mla (str, flags)
2328 char * str;
2329 unsigned long flags;
2330 {
2331 int rd, rm;
2332
2333 /* Only one format "rd, rm, rs, rn". */
2334 skip_whitespace (str);
2335
2336 if ((rd = reg_required_here (&str, 16)) == FAIL)
2337 {
2338 inst.error = BAD_ARGS;
2339 return;
2340 }
2341
2342 if (rd == REG_PC)
2343 {
2344 inst.error = BAD_PC;
2345 return;
2346 }
2347
2348 if (skip_past_comma (&str) == FAIL
2349 || (rm = reg_required_here (&str, 0)) == FAIL)
2350 {
2351 inst.error = BAD_ARGS;
2352 return;
2353 }
2354
2355 if (rm == REG_PC)
2356 {
2357 inst.error = BAD_PC;
2358 return;
2359 }
2360
2361 if (rm == rd)
2362 as_tsktsk (_("rd and rm should be different in mla"));
2363
2364 if (skip_past_comma (&str) == FAIL
2365 || (rd = reg_required_here (&str, 8)) == FAIL
2366 || skip_past_comma (&str) == FAIL
2367 || (rm = reg_required_here (&str, 12)) == FAIL)
2368 {
2369 inst.error = BAD_ARGS;
2370 return;
2371 }
2372
2373 if (rd == REG_PC || rm == REG_PC)
2374 {
2375 inst.error = BAD_PC;
2376 return;
2377 }
2378
2379 inst.instruction |= flags;
2380 end_of_line (str);
2381 return;
2382 }
2383
2384 /* Returns the index into fp_values of a floating point number,
2385 or -1 if not in the table. */
2386
2387 static int
2388 my_get_float_expression (str)
2389 char ** str;
2390 {
2391 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2392 char * save_in;
2393 expressionS exp;
2394 int i;
2395 int j;
2396
2397 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
2398
2399 /* Look for a raw floating point number. */
2400 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
2401 && is_end_of_line[(unsigned char) *save_in])
2402 {
2403 for (i = 0; i < NUM_FLOAT_VALS; i++)
2404 {
2405 for (j = 0; j < MAX_LITTLENUMS; j++)
2406 {
2407 if (words[j] != fp_values[i][j])
2408 break;
2409 }
2410
2411 if (j == MAX_LITTLENUMS)
2412 {
2413 *str = save_in;
2414 return i;
2415 }
2416 }
2417 }
2418
2419 /* Try and parse a more complex expression, this will probably fail
2420 unless the code uses a floating point prefix (eg "0f"). */
2421 save_in = input_line_pointer;
2422 input_line_pointer = *str;
2423 if (expression (&exp) == absolute_section
2424 && exp.X_op == O_big
2425 && exp.X_add_number < 0)
2426 {
2427 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
2428 Ditto for 15. */
2429 if (gen_to_words (words, 5, (long) 15) == 0)
2430 {
2431 for (i = 0; i < NUM_FLOAT_VALS; i++)
2432 {
2433 for (j = 0; j < MAX_LITTLENUMS; j++)
2434 {
2435 if (words[j] != fp_values[i][j])
2436 break;
2437 }
2438
2439 if (j == MAX_LITTLENUMS)
2440 {
2441 *str = input_line_pointer;
2442 input_line_pointer = save_in;
2443 return i;
2444 }
2445 }
2446 }
2447 }
2448
2449 *str = input_line_pointer;
2450 input_line_pointer = save_in;
2451 return -1;
2452 }
2453
2454 /* Return true if anything in the expression is a bignum. */
2455
2456 static int
2457 walk_no_bignums (sp)
2458 symbolS * sp;
2459 {
2460 if (symbol_get_value_expression (sp)->X_op == O_big)
2461 return 1;
2462
2463 if (symbol_get_value_expression (sp)->X_add_symbol)
2464 {
2465 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
2466 || (symbol_get_value_expression (sp)->X_op_symbol
2467 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
2468 }
2469
2470 return 0;
2471 }
2472
2473 static int
2474 my_get_expression (ep, str)
2475 expressionS * ep;
2476 char ** str;
2477 {
2478 char * save_in;
2479 segT seg;
2480
2481 save_in = input_line_pointer;
2482 input_line_pointer = *str;
2483 seg = expression (ep);
2484
2485 #ifdef OBJ_AOUT
2486 if (seg != absolute_section
2487 && seg != text_section
2488 && seg != data_section
2489 && seg != bss_section
2490 && seg != undefined_section)
2491 {
2492 inst.error = _("bad_segment");
2493 *str = input_line_pointer;
2494 input_line_pointer = save_in;
2495 return 1;
2496 }
2497 #endif
2498
2499 /* Get rid of any bignums now, so that we don't generate an error for which
2500 we can't establish a line number later on. Big numbers are never valid
2501 in instructions, which is where this routine is always called. */
2502 if (ep->X_op == O_big
2503 || (ep->X_add_symbol
2504 && (walk_no_bignums (ep->X_add_symbol)
2505 || (ep->X_op_symbol
2506 && walk_no_bignums (ep->X_op_symbol)))))
2507 {
2508 inst.error = _("Invalid constant");
2509 *str = input_line_pointer;
2510 input_line_pointer = save_in;
2511 return 1;
2512 }
2513
2514 *str = input_line_pointer;
2515 input_line_pointer = save_in;
2516 return 0;
2517 }
2518
2519 /* UNRESTRICT should be one if <shift> <register> is permitted for this
2520 instruction. */
2521
2522 static int
2523 decode_shift (str, unrestrict)
2524 char ** str;
2525 int unrestrict;
2526 {
2527 const struct asm_shift_name * shift;
2528 char * p;
2529 char c;
2530
2531 skip_whitespace (* str);
2532
2533 for (p = * str; isalpha (* p); p ++)
2534 ;
2535
2536 if (p == * str)
2537 {
2538 inst.error = _("Shift expression expected");
2539 return FAIL;
2540 }
2541
2542 c = * p;
2543 * p = '\0';
2544 shift = (const struct asm_shift_name *) hash_find (arm_shift_hsh, * str);
2545 * p = c;
2546
2547 if (shift == NULL)
2548 {
2549 inst.error = _("Shift expression expected");
2550 return FAIL;
2551 }
2552
2553 assert (shift->properties->index == shift_properties[shift->properties->index].index);
2554
2555 if (shift->properties->index == SHIFT_RRX)
2556 {
2557 * str = p;
2558 inst.instruction |= shift->properties->bit_field;
2559 return SUCCESS;
2560 }
2561
2562 skip_whitespace (p);
2563
2564 if (unrestrict && reg_required_here (& p, 8) != FAIL)
2565 {
2566 inst.instruction |= shift->properties->bit_field | SHIFT_BY_REG;
2567 * str = p;
2568 return SUCCESS;
2569 }
2570 else if (! is_immediate_prefix (* p))
2571 {
2572 inst.error = (unrestrict
2573 ? _("shift requires register or #expression")
2574 : _("shift requires #expression"));
2575 * str = p;
2576 return FAIL;
2577 }
2578
2579 inst.error = NULL;
2580 p ++;
2581
2582 if (my_get_expression (& inst.reloc.exp, & p))
2583 return FAIL;
2584
2585 /* Validate some simple #expressions. */
2586 if (inst.reloc.exp.X_op == O_constant)
2587 {
2588 unsigned num = inst.reloc.exp.X_add_number;
2589
2590 /* Reject operations greater than 32. */
2591 if (num > 32
2592 /* Reject a shift of 0 unless the mode allows it. */
2593 || (num == 0 && shift->properties->allows_0 == 0)
2594 /* Reject a shift of 32 unless the mode allows it. */
2595 || (num == 32 && shift->properties->allows_32 == 0)
2596 )
2597 {
2598 /* As a special case we allow a shift of zero for
2599 modes that do not support it to be recoded as an
2600 logical shift left of zero (ie nothing). We warn
2601 about this though. */
2602 if (num == 0)
2603 {
2604 as_warn (_("Shift of 0 ignored."));
2605 shift = & shift_names[0];
2606 assert (shift->properties->index == SHIFT_LSL);
2607 }
2608 else
2609 {
2610 inst.error = _("Invalid immediate shift");
2611 return FAIL;
2612 }
2613 }
2614
2615 /* Shifts of 32 are encoded as 0, for those shifts that
2616 support it. */
2617 if (num == 32)
2618 num = 0;
2619
2620 inst.instruction |= (num << 7) | shift->properties->bit_field;
2621 }
2622 else
2623 {
2624 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
2625 inst.reloc.pc_rel = 0;
2626 inst.instruction |= shift->properties->bit_field;
2627 }
2628
2629 * str = p;
2630 return SUCCESS;
2631 }
2632
2633 /* Do those data_ops which can take a negative immediate constant
2634 by altering the instuction. A bit of a hack really.
2635 MOV <-> MVN
2636 AND <-> BIC
2637 ADC <-> SBC
2638 by inverting the second operand, and
2639 ADD <-> SUB
2640 CMP <-> CMN
2641 by negating the second operand. */
2642
2643 static int
2644 negate_data_op (instruction, value)
2645 unsigned long * instruction;
2646 unsigned long value;
2647 {
2648 int op, new_inst;
2649 unsigned long negated, inverted;
2650
2651 negated = validate_immediate (-value);
2652 inverted = validate_immediate (~value);
2653
2654 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
2655 switch (op)
2656 {
2657 /* First negates. */
2658 case OPCODE_SUB: /* ADD <-> SUB */
2659 new_inst = OPCODE_ADD;
2660 value = negated;
2661 break;
2662
2663 case OPCODE_ADD:
2664 new_inst = OPCODE_SUB;
2665 value = negated;
2666 break;
2667
2668 case OPCODE_CMP: /* CMP <-> CMN */
2669 new_inst = OPCODE_CMN;
2670 value = negated;
2671 break;
2672
2673 case OPCODE_CMN:
2674 new_inst = OPCODE_CMP;
2675 value = negated;
2676 break;
2677
2678 /* Now Inverted ops. */
2679 case OPCODE_MOV: /* MOV <-> MVN */
2680 new_inst = OPCODE_MVN;
2681 value = inverted;
2682 break;
2683
2684 case OPCODE_MVN:
2685 new_inst = OPCODE_MOV;
2686 value = inverted;
2687 break;
2688
2689 case OPCODE_AND: /* AND <-> BIC */
2690 new_inst = OPCODE_BIC;
2691 value = inverted;
2692 break;
2693
2694 case OPCODE_BIC:
2695 new_inst = OPCODE_AND;
2696 value = inverted;
2697 break;
2698
2699 case OPCODE_ADC: /* ADC <-> SBC */
2700 new_inst = OPCODE_SBC;
2701 value = inverted;
2702 break;
2703
2704 case OPCODE_SBC:
2705 new_inst = OPCODE_ADC;
2706 value = inverted;
2707 break;
2708
2709 /* We cannot do anything. */
2710 default:
2711 return FAIL;
2712 }
2713
2714 if (value == (unsigned) FAIL)
2715 return FAIL;
2716
2717 *instruction &= OPCODE_MASK;
2718 *instruction |= new_inst << DATA_OP_SHIFT;
2719 return value;
2720 }
2721
2722 static int
2723 data_op2 (str)
2724 char ** str;
2725 {
2726 int value;
2727 expressionS expr;
2728
2729 skip_whitespace (* str);
2730
2731 if (reg_required_here (str, 0) != FAIL)
2732 {
2733 if (skip_past_comma (str) == SUCCESS)
2734 /* Shift operation on register. */
2735 return decode_shift (str, NO_SHIFT_RESTRICT);
2736
2737 return SUCCESS;
2738 }
2739 else
2740 {
2741 /* Immediate expression. */
2742 if (is_immediate_prefix (**str))
2743 {
2744 (*str)++;
2745 inst.error = NULL;
2746
2747 if (my_get_expression (&inst.reloc.exp, str))
2748 return FAIL;
2749
2750 if (inst.reloc.exp.X_add_symbol)
2751 {
2752 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2753 inst.reloc.pc_rel = 0;
2754 }
2755 else
2756 {
2757 if (skip_past_comma (str) == SUCCESS)
2758 {
2759 /* #x, y -- ie explicit rotation by Y. */
2760 if (my_get_expression (&expr, str))
2761 return FAIL;
2762
2763 if (expr.X_op != O_constant)
2764 {
2765 inst.error = _("Constant expression expected");
2766 return FAIL;
2767 }
2768
2769 /* Rotate must be a multiple of 2. */
2770 if (((unsigned) expr.X_add_number) > 30
2771 || (expr.X_add_number & 1) != 0
2772 || ((unsigned) inst.reloc.exp.X_add_number) > 255)
2773 {
2774 inst.error = _("Invalid constant");
2775 return FAIL;
2776 }
2777 inst.instruction |= INST_IMMEDIATE;
2778 inst.instruction |= inst.reloc.exp.X_add_number;
2779 inst.instruction |= expr.X_add_number << 7;
2780 return SUCCESS;
2781 }
2782
2783 /* Implicit rotation, select a suitable one. */
2784 value = validate_immediate (inst.reloc.exp.X_add_number);
2785
2786 if (value == FAIL)
2787 {
2788 /* Can't be done. Perhaps the code reads something like
2789 "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be OK. */
2790 if ((value = negate_data_op (&inst.instruction,
2791 inst.reloc.exp.X_add_number))
2792 == FAIL)
2793 {
2794 inst.error = _("Invalid constant");
2795 return FAIL;
2796 }
2797 }
2798
2799 inst.instruction |= value;
2800 }
2801
2802 inst.instruction |= INST_IMMEDIATE;
2803 return SUCCESS;
2804 }
2805
2806 (*str)++;
2807 inst.error = _("Register or shift expression expected");
2808 return FAIL;
2809 }
2810 }
2811
2812 static int
2813 fp_op2 (str)
2814 char ** str;
2815 {
2816 skip_whitespace (* str);
2817
2818 if (fp_reg_required_here (str, 0) != FAIL)
2819 return SUCCESS;
2820 else
2821 {
2822 /* Immediate expression. */
2823 if (*((*str)++) == '#')
2824 {
2825 int i;
2826
2827 inst.error = NULL;
2828
2829 skip_whitespace (* str);
2830
2831 /* First try and match exact strings, this is to guarantee
2832 that some formats will work even for cross assembly. */
2833
2834 for (i = 0; fp_const[i]; i++)
2835 {
2836 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
2837 {
2838 char *start = *str;
2839
2840 *str += strlen (fp_const[i]);
2841 if (is_end_of_line[(unsigned char) **str])
2842 {
2843 inst.instruction |= i + 8;
2844 return SUCCESS;
2845 }
2846 *str = start;
2847 }
2848 }
2849
2850 /* Just because we didn't get a match doesn't mean that the
2851 constant isn't valid, just that it is in a format that we
2852 don't automatically recognize. Try parsing it with
2853 the standard expression routines. */
2854 if ((i = my_get_float_expression (str)) >= 0)
2855 {
2856 inst.instruction |= i + 8;
2857 return SUCCESS;
2858 }
2859
2860 inst.error = _("Invalid floating point immediate expression");
2861 return FAIL;
2862 }
2863 inst.error =
2864 _("Floating point register or immediate expression expected");
2865 return FAIL;
2866 }
2867 }
2868
2869 static void
2870 do_arit (str, flags)
2871 char * str;
2872 unsigned long flags;
2873 {
2874 skip_whitespace (str);
2875
2876 if (reg_required_here (&str, 12) == FAIL
2877 || skip_past_comma (&str) == FAIL
2878 || reg_required_here (&str, 16) == FAIL
2879 || skip_past_comma (&str) == FAIL
2880 || data_op2 (&str) == FAIL)
2881 {
2882 if (!inst.error)
2883 inst.error = BAD_ARGS;
2884 return;
2885 }
2886
2887 inst.instruction |= flags;
2888 end_of_line (str);
2889 return;
2890 }
2891
2892 static void
2893 do_adr (str, flags)
2894 char * str;
2895 unsigned long flags;
2896 {
2897 /* This is a pseudo-op of the form "adr rd, label" to be converted
2898 into a relative address of the form "add rd, pc, #label-.-8". */
2899 skip_whitespace (str);
2900
2901 if (reg_required_here (&str, 12) == FAIL
2902 || skip_past_comma (&str) == FAIL
2903 || my_get_expression (&inst.reloc.exp, &str))
2904 {
2905 if (!inst.error)
2906 inst.error = BAD_ARGS;
2907 return;
2908 }
2909
2910 /* Frag hacking will turn this into a sub instruction if the offset turns
2911 out to be negative. */
2912 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2913 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust. */
2914 inst.reloc.pc_rel = 1;
2915 inst.instruction |= flags;
2916
2917 end_of_line (str);
2918 }
2919
2920 static void
2921 do_adrl (str, flags)
2922 char * str;
2923 unsigned long flags;
2924 {
2925 /* This is a pseudo-op of the form "adrl rd, label" to be converted
2926 into a relative address of the form:
2927 add rd, pc, #low(label-.-8)"
2928 add rd, rd, #high(label-.-8)" */
2929
2930 skip_whitespace (str);
2931
2932 if (reg_required_here (& str, 12) == FAIL
2933 || skip_past_comma (& str) == FAIL
2934 || my_get_expression (& inst.reloc.exp, & str))
2935 {
2936 if (!inst.error)
2937 inst.error = BAD_ARGS;
2938 return;
2939 }
2940
2941 end_of_line (str);
2942
2943 /* Frag hacking will turn this into a sub instruction if the offset turns
2944 out to be negative. */
2945 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
2946 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
2947 inst.reloc.pc_rel = 1;
2948 inst.instruction |= flags;
2949 inst.size = INSN_SIZE * 2;
2950
2951 return;
2952 }
2953
2954 static void
2955 do_cmp (str, flags)
2956 char * str;
2957 unsigned long flags;
2958 {
2959 skip_whitespace (str);
2960
2961 if (reg_required_here (&str, 16) == FAIL)
2962 {
2963 if (!inst.error)
2964 inst.error = BAD_ARGS;
2965 return;
2966 }
2967
2968 if (skip_past_comma (&str) == FAIL
2969 || data_op2 (&str) == FAIL)
2970 {
2971 if (!inst.error)
2972 inst.error = BAD_ARGS;
2973 return;
2974 }
2975
2976 inst.instruction |= flags;
2977 if ((flags & 0x0000f000) == 0)
2978 inst.instruction |= CONDS_BIT;
2979
2980 end_of_line (str);
2981 return;
2982 }
2983
2984 static void
2985 do_mov (str, flags)
2986 char * str;
2987 unsigned long flags;
2988 {
2989 skip_whitespace (str);
2990
2991 if (reg_required_here (&str, 12) == FAIL)
2992 {
2993 if (!inst.error)
2994 inst.error = BAD_ARGS;
2995 return;
2996 }
2997
2998 if (skip_past_comma (&str) == FAIL
2999 || data_op2 (&str) == FAIL)
3000 {
3001 if (!inst.error)
3002 inst.error = BAD_ARGS;
3003 return;
3004 }
3005
3006 inst.instruction |= flags;
3007 end_of_line (str);
3008 return;
3009 }
3010
3011 static int
3012 ldst_extend (str, hwse)
3013 char ** str;
3014 int hwse;
3015 {
3016 int add = INDEX_UP;
3017
3018 switch (**str)
3019 {
3020 case '#':
3021 case '$':
3022 (*str)++;
3023 if (my_get_expression (& inst.reloc.exp, str))
3024 return FAIL;
3025
3026 if (inst.reloc.exp.X_op == O_constant)
3027 {
3028 int value = inst.reloc.exp.X_add_number;
3029
3030 if ((hwse && (value < -255 || value > 255))
3031 || (value < -4095 || value > 4095))
3032 {
3033 inst.error = _("address offset too large");
3034 return FAIL;
3035 }
3036
3037 if (value < 0)
3038 {
3039 value = -value;
3040 add = 0;
3041 }
3042
3043 /* Halfword and signextension instructions have the
3044 immediate value split across bits 11..8 and bits 3..0. */
3045 if (hwse)
3046 inst.instruction |= (add | HWOFFSET_IMM
3047 | ((value >> 4) << 8) | (value & 0xF));
3048 else
3049 inst.instruction |= add | value;
3050 }
3051 else
3052 {
3053 if (hwse)
3054 {
3055 inst.instruction |= HWOFFSET_IMM;
3056 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
3057 }
3058 else
3059 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
3060 inst.reloc.pc_rel = 0;
3061 }
3062 return SUCCESS;
3063
3064 case '-':
3065 add = 0;
3066 /* Fall through. */
3067
3068 case '+':
3069 (*str)++;
3070 /* Fall through. */
3071
3072 default:
3073 if (reg_required_here (str, 0) == FAIL)
3074 return FAIL;
3075
3076 if (hwse)
3077 inst.instruction |= add;
3078 else
3079 {
3080 inst.instruction |= add | OFFSET_REG;
3081 if (skip_past_comma (str) == SUCCESS)
3082 return decode_shift (str, SHIFT_RESTRICT);
3083 }
3084
3085 return SUCCESS;
3086 }
3087 }
3088
3089 static void
3090 do_ldst (str, flags)
3091 char * str;
3092 unsigned long flags;
3093 {
3094 int halfword = 0;
3095 int pre_inc = 0;
3096 int conflict_reg;
3097 int value;
3098
3099 /* This is not ideal, but it is the simplest way of dealing with the
3100 ARM7T halfword instructions (since they use a different
3101 encoding, but the same mnemonic): */
3102 halfword = (flags & 0x80000000) != 0;
3103 if (halfword)
3104 {
3105 /* This is actually a load/store of a halfword, or a
3106 signed-extension load. */
3107 if ((cpu_variant & ARM_HALFWORD) == 0)
3108 {
3109 inst.error
3110 = _("Processor does not support halfwords or signed bytes");
3111 return;
3112 }
3113
3114 inst.instruction = ((inst.instruction & COND_MASK)
3115 | (flags & ~COND_MASK));
3116
3117 flags = 0;
3118 }
3119
3120 skip_whitespace (str);
3121
3122 if ((conflict_reg = reg_required_here (& str, 12)) == FAIL)
3123 {
3124 if (!inst.error)
3125 inst.error = BAD_ARGS;
3126 return;
3127 }
3128
3129 if (skip_past_comma (& str) == FAIL)
3130 {
3131 inst.error = _("Address expected");
3132 return;
3133 }
3134
3135 if (*str == '[')
3136 {
3137 int reg;
3138
3139 str++;
3140
3141 skip_whitespace (str);
3142
3143 if ((reg = reg_required_here (&str, 16)) == FAIL)
3144 return;
3145
3146 /* Conflicts can occur on stores as well as loads. */
3147 conflict_reg = (conflict_reg == reg);
3148
3149 skip_whitespace (str);
3150
3151 if (*str == ']')
3152 {
3153 str ++;
3154
3155 if (skip_past_comma (&str) == SUCCESS)
3156 {
3157 /* [Rn],... (post inc) */
3158 if (ldst_extend (&str, halfword) == FAIL)
3159 return;
3160 if (conflict_reg)
3161 as_warn (_("%s register same as write-back base"),
3162 ((inst.instruction & LOAD_BIT)
3163 ? _("destination") : _("source")));
3164 }
3165 else
3166 {
3167 /* [Rn] */
3168 if (halfword)
3169 inst.instruction |= HWOFFSET_IMM;
3170
3171 skip_whitespace (str);
3172
3173 if (*str == '!')
3174 {
3175 if (conflict_reg)
3176 as_warn (_("%s register same as write-back base"),
3177 ((inst.instruction & LOAD_BIT)
3178 ? _("destination") : _("source")));
3179 str++;
3180 inst.instruction |= WRITE_BACK;
3181 }
3182
3183 flags |= INDEX_UP;
3184 if (! (flags & TRANS_BIT))
3185 pre_inc = 1;
3186 }
3187 }
3188 else
3189 {
3190 /* [Rn,...] */
3191 if (skip_past_comma (&str) == FAIL)
3192 {
3193 inst.error = _("pre-indexed expression expected");
3194 return;
3195 }
3196
3197 pre_inc = 1;
3198 if (ldst_extend (&str, halfword) == FAIL)
3199 return;
3200
3201 skip_whitespace (str);
3202
3203 if (*str++ != ']')
3204 {
3205 inst.error = _("missing ]");
3206 return;
3207 }
3208
3209 skip_whitespace (str);
3210
3211 if (*str == '!')
3212 {
3213 if (conflict_reg)
3214 as_warn (_("%s register same as write-back base"),
3215 ((inst.instruction & LOAD_BIT)
3216 ? _("destination") : _("source")));
3217 str++;
3218 inst.instruction |= WRITE_BACK;
3219 }
3220 }
3221 }
3222 else if (*str == '=')
3223 {
3224 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
3225 str++;
3226
3227 skip_whitespace (str);
3228
3229 if (my_get_expression (&inst.reloc.exp, &str))
3230 return;
3231
3232 if (inst.reloc.exp.X_op != O_constant
3233 && inst.reloc.exp.X_op != O_symbol)
3234 {
3235 inst.error = _("Constant expression expected");
3236 return;
3237 }
3238
3239 if (inst.reloc.exp.X_op == O_constant
3240 && (value = validate_immediate (inst.reloc.exp.X_add_number)) != FAIL)
3241 {
3242 /* This can be done with a mov instruction. */
3243 inst.instruction &= LITERAL_MASK;
3244 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
3245 inst.instruction |= (flags & COND_MASK) | (value & 0xfff);
3246 end_of_line (str);
3247 return;
3248 }
3249 else
3250 {
3251 /* Insert into literal pool. */
3252 if (add_to_lit_pool () == FAIL)
3253 {
3254 if (!inst.error)
3255 inst.error = _("literal pool insertion failed");
3256 return;
3257 }
3258
3259 /* Change the instruction exp to point to the pool. */
3260 if (halfword)
3261 {
3262 inst.instruction |= HWOFFSET_IMM;
3263 inst.reloc.type = BFD_RELOC_ARM_HWLITERAL;
3264 }
3265 else
3266 inst.reloc.type = BFD_RELOC_ARM_LITERAL;
3267 inst.reloc.pc_rel = 1;
3268 inst.instruction |= (REG_PC << 16);
3269 pre_inc = 1;
3270 }
3271 }
3272 else
3273 {
3274 if (my_get_expression (&inst.reloc.exp, &str))
3275 return;
3276
3277 if (halfword)
3278 {
3279 inst.instruction |= HWOFFSET_IMM;
3280 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
3281 }
3282 else
3283 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
3284 #ifndef TE_WINCE
3285 /* PC rel adjust. */
3286 inst.reloc.exp.X_add_number -= 8;
3287 #endif
3288 inst.reloc.pc_rel = 1;
3289 inst.instruction |= (REG_PC << 16);
3290 pre_inc = 1;
3291 }
3292
3293 if (pre_inc && (flags & TRANS_BIT))
3294 inst.error = _("Pre-increment instruction with translate");
3295
3296 inst.instruction |= flags | (pre_inc ? PRE_INDEX : 0);
3297 end_of_line (str);
3298 return;
3299 }
3300
3301 static long
3302 reg_list (strp)
3303 char ** strp;
3304 {
3305 char * str = * strp;
3306 long range = 0;
3307 int another_range;
3308
3309 /* We come back here if we get ranges concatenated by '+' or '|'. */
3310 do
3311 {
3312 another_range = 0;
3313
3314 if (*str == '{')
3315 {
3316 int in_range = 0;
3317 int cur_reg = -1;
3318
3319 str++;
3320 do
3321 {
3322 int reg;
3323
3324 skip_whitespace (str);
3325
3326 if ((reg = reg_required_here (& str, -1)) == FAIL)
3327 return FAIL;
3328
3329 if (in_range)
3330 {
3331 int i;
3332
3333 if (reg <= cur_reg)
3334 {
3335 inst.error = _("Bad range in register list");
3336 return FAIL;
3337 }
3338
3339 for (i = cur_reg + 1; i < reg; i++)
3340 {
3341 if (range & (1 << i))
3342 as_tsktsk
3343 (_("Warning: Duplicated register (r%d) in register list"),
3344 i);
3345 else
3346 range |= 1 << i;
3347 }
3348 in_range = 0;
3349 }
3350
3351 if (range & (1 << reg))
3352 as_tsktsk (_("Warning: Duplicated register (r%d) in register list"),
3353 reg);
3354 else if (reg <= cur_reg)
3355 as_tsktsk (_("Warning: Register range not in ascending order"));
3356
3357 range |= 1 << reg;
3358 cur_reg = reg;
3359 }
3360 while (skip_past_comma (&str) != FAIL
3361 || (in_range = 1, *str++ == '-'));
3362 str--;
3363 skip_whitespace (str);
3364
3365 if (*str++ != '}')
3366 {
3367 inst.error = _("Missing `}'");
3368 return FAIL;
3369 }
3370 }
3371 else
3372 {
3373 expressionS expr;
3374
3375 if (my_get_expression (&expr, &str))
3376 return FAIL;
3377
3378 if (expr.X_op == O_constant)
3379 {
3380 if (expr.X_add_number
3381 != (expr.X_add_number & 0x0000ffff))
3382 {
3383 inst.error = _("invalid register mask");
3384 return FAIL;
3385 }
3386
3387 if ((range & expr.X_add_number) != 0)
3388 {
3389 int regno = range & expr.X_add_number;
3390
3391 regno &= -regno;
3392 regno = (1 << regno) - 1;
3393 as_tsktsk
3394 (_("Warning: Duplicated register (r%d) in register list"),
3395 regno);
3396 }
3397
3398 range |= expr.X_add_number;
3399 }
3400 else
3401 {
3402 if (inst.reloc.type != 0)
3403 {
3404 inst.error = _("expression too complex");
3405 return FAIL;
3406 }
3407
3408 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
3409 inst.reloc.type = BFD_RELOC_ARM_MULTI;
3410 inst.reloc.pc_rel = 0;
3411 }
3412 }
3413
3414 skip_whitespace (str);
3415
3416 if (*str == '|' || *str == '+')
3417 {
3418 str++;
3419 another_range = 1;
3420 }
3421 }
3422 while (another_range);
3423
3424 *strp = str;
3425 return range;
3426 }
3427
3428 static void
3429 do_ldmstm (str, flags)
3430 char * str;
3431 unsigned long flags;
3432 {
3433 int base_reg;
3434 long range;
3435
3436 skip_whitespace (str);
3437
3438 if ((base_reg = reg_required_here (&str, 16)) == FAIL)
3439 return;
3440
3441 if (base_reg == REG_PC)
3442 {
3443 inst.error = _("r15 not allowed as base register");
3444 return;
3445 }
3446
3447 skip_whitespace (str);
3448
3449 if (*str == '!')
3450 {
3451 flags |= WRITE_BACK;
3452 str++;
3453 }
3454
3455 if (skip_past_comma (&str) == FAIL
3456 || (range = reg_list (&str)) == FAIL)
3457 {
3458 if (! inst.error)
3459 inst.error = BAD_ARGS;
3460 return;
3461 }
3462
3463 if (*str == '^')
3464 {
3465 str++;
3466 flags |= LDM_TYPE_2_OR_3;
3467 }
3468
3469 inst.instruction |= flags | range;
3470 end_of_line (str);
3471 return;
3472 }
3473
3474 static void
3475 do_swi (str, flags)
3476 char * str;
3477 unsigned long flags;
3478 {
3479 skip_whitespace (str);
3480
3481 /* Allow optional leading '#'. */
3482 if (is_immediate_prefix (*str))
3483 str++;
3484
3485 if (my_get_expression (& inst.reloc.exp, & str))
3486 return;
3487
3488 inst.reloc.type = BFD_RELOC_ARM_SWI;
3489 inst.reloc.pc_rel = 0;
3490 inst.instruction |= flags;
3491
3492 end_of_line (str);
3493
3494 return;
3495 }
3496
3497 static void
3498 do_swap (str, flags)
3499 char * str;
3500 unsigned long flags;
3501 {
3502 int reg;
3503
3504 skip_whitespace (str);
3505
3506 if ((reg = reg_required_here (&str, 12)) == FAIL)
3507 return;
3508
3509 if (reg == REG_PC)
3510 {
3511 inst.error = _("r15 not allowed in swap");
3512 return;
3513 }
3514
3515 if (skip_past_comma (&str) == FAIL
3516 || (reg = reg_required_here (&str, 0)) == FAIL)
3517 {
3518 if (!inst.error)
3519 inst.error = BAD_ARGS;
3520 return;
3521 }
3522
3523 if (reg == REG_PC)
3524 {
3525 inst.error = _("r15 not allowed in swap");
3526 return;
3527 }
3528
3529 if (skip_past_comma (&str) == FAIL
3530 || *str++ != '[')
3531 {
3532 inst.error = BAD_ARGS;
3533 return;
3534 }
3535
3536 skip_whitespace (str);
3537
3538 if ((reg = reg_required_here (&str, 16)) == FAIL)
3539 return;
3540
3541 if (reg == REG_PC)
3542 {
3543 inst.error = BAD_PC;
3544 return;
3545 }
3546
3547 skip_whitespace (str);
3548
3549 if (*str++ != ']')
3550 {
3551 inst.error = _("missing ]");
3552 return;
3553 }
3554
3555 inst.instruction |= flags;
3556 end_of_line (str);
3557 return;
3558 }
3559
3560 static void
3561 do_branch (str, flags)
3562 char * str;
3563 unsigned long flags ATTRIBUTE_UNUSED;
3564 {
3565 if (my_get_expression (&inst.reloc.exp, &str))
3566 return;
3567
3568 #ifdef OBJ_ELF
3569 {
3570 char * save_in;
3571
3572 /* ScottB: February 5, 1998 - Check to see of PLT32 reloc
3573 required for the instruction. */
3574
3575 /* arm_parse_reloc () works on input_line_pointer.
3576 We actually want to parse the operands to the branch instruction
3577 passed in 'str'. Save the input pointer and restore it later. */
3578 save_in = input_line_pointer;
3579 input_line_pointer = str;
3580 if (inst.reloc.exp.X_op == O_symbol
3581 && *str == '('
3582 && arm_parse_reloc () == BFD_RELOC_ARM_PLT32)
3583 {
3584 inst.reloc.type = BFD_RELOC_ARM_PLT32;
3585 inst.reloc.pc_rel = 0;
3586 /* Modify str to point to after parsed operands, otherwise
3587 end_of_line() will complain about the (PLT) left in str. */
3588 str = input_line_pointer;
3589 }
3590 else
3591 {
3592 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
3593 inst.reloc.pc_rel = 1;
3594 }
3595 input_line_pointer = save_in;
3596 }
3597 #else
3598 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
3599 inst.reloc.pc_rel = 1;
3600 #endif /* OBJ_ELF */
3601
3602 end_of_line (str);
3603 return;
3604 }
3605
3606 static void
3607 do_bx (str, flags)
3608 char * str;
3609 unsigned long flags ATTRIBUTE_UNUSED;
3610 {
3611 int reg;
3612
3613 skip_whitespace (str);
3614
3615 if ((reg = reg_required_here (&str, 0)) == FAIL)
3616 {
3617 inst.error = BAD_ARGS;
3618 return;
3619 }
3620
3621 /* Note - it is not illegal to do a "bx pc". Useless, but not illegal. */
3622 if (reg == REG_PC)
3623 as_tsktsk (_("Use of r15 in bx in ARM mode is not really useful"));
3624
3625 end_of_line (str);
3626 }
3627
3628 static void
3629 do_cdp (str, flags)
3630 char * str;
3631 unsigned long flags ATTRIBUTE_UNUSED;
3632 {
3633 /* Co-processor data operation.
3634 Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
3635 skip_whitespace (str);
3636
3637 if (co_proc_number (&str) == FAIL)
3638 {
3639 if (!inst.error)
3640 inst.error = BAD_ARGS;
3641 return;
3642 }
3643
3644 if (skip_past_comma (&str) == FAIL
3645 || cp_opc_expr (&str, 20,4) == FAIL)
3646 {
3647 if (!inst.error)
3648 inst.error = BAD_ARGS;
3649 return;
3650 }
3651
3652 if (skip_past_comma (&str) == FAIL
3653 || cp_reg_required_here (&str, 12) == FAIL)
3654 {
3655 if (!inst.error)
3656 inst.error = BAD_ARGS;
3657 return;
3658 }
3659
3660 if (skip_past_comma (&str) == FAIL
3661 || cp_reg_required_here (&str, 16) == FAIL)
3662 {
3663 if (!inst.error)
3664 inst.error = BAD_ARGS;
3665 return;
3666 }
3667
3668 if (skip_past_comma (&str) == FAIL
3669 || cp_reg_required_here (&str, 0) == FAIL)
3670 {
3671 if (!inst.error)
3672 inst.error = BAD_ARGS;
3673 return;
3674 }
3675
3676 if (skip_past_comma (&str) == SUCCESS)
3677 {
3678 if (cp_opc_expr (&str, 5, 3) == FAIL)
3679 {
3680 if (!inst.error)
3681 inst.error = BAD_ARGS;
3682 return;
3683 }
3684 }
3685
3686 end_of_line (str);
3687 return;
3688 }
3689
3690 static void
3691 do_lstc (str, flags)
3692 char * str;
3693 unsigned long flags;
3694 {
3695 /* Co-processor register load/store.
3696 Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
3697
3698 skip_whitespace (str);
3699
3700 if (co_proc_number (&str) == FAIL)
3701 {
3702 if (!inst.error)
3703 inst.error = BAD_ARGS;
3704 return;
3705 }
3706
3707 if (skip_past_comma (&str) == FAIL
3708 || cp_reg_required_here (&str, 12) == FAIL)
3709 {
3710 if (!inst.error)
3711 inst.error = BAD_ARGS;
3712 return;
3713 }
3714
3715 if (skip_past_comma (&str) == FAIL
3716 || cp_address_required_here (&str) == FAIL)
3717 {
3718 if (! inst.error)
3719 inst.error = BAD_ARGS;
3720 return;
3721 }
3722
3723 inst.instruction |= flags;
3724 end_of_line (str);
3725 return;
3726 }
3727
3728 static void
3729 do_co_reg (str, flags)
3730 char * str;
3731 unsigned long flags;
3732 {
3733 /* Co-processor register transfer.
3734 Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
3735
3736 skip_whitespace (str);
3737
3738 if (co_proc_number (&str) == FAIL)
3739 {
3740 if (!inst.error)
3741 inst.error = BAD_ARGS;
3742 return;
3743 }
3744
3745 if (skip_past_comma (&str) == FAIL
3746 || cp_opc_expr (&str, 21, 3) == FAIL)
3747 {
3748 if (!inst.error)
3749 inst.error = BAD_ARGS;
3750 return;
3751 }
3752
3753 if (skip_past_comma (&str) == FAIL
3754 || reg_required_here (&str, 12) == FAIL)
3755 {
3756 if (!inst.error)
3757 inst.error = BAD_ARGS;
3758 return;
3759 }
3760
3761 if (skip_past_comma (&str) == FAIL
3762 || cp_reg_required_here (&str, 16) == FAIL)
3763 {
3764 if (!inst.error)
3765 inst.error = BAD_ARGS;
3766 return;
3767 }
3768
3769 if (skip_past_comma (&str) == FAIL
3770 || cp_reg_required_here (&str, 0) == FAIL)
3771 {
3772 if (!inst.error)
3773 inst.error = BAD_ARGS;
3774 return;
3775 }
3776
3777 if (skip_past_comma (&str) == SUCCESS)
3778 {
3779 if (cp_opc_expr (&str, 5, 3) == FAIL)
3780 {
3781 if (!inst.error)
3782 inst.error = BAD_ARGS;
3783 return;
3784 }
3785 }
3786 if (flags)
3787 {
3788 inst.error = BAD_COND;
3789 }
3790
3791 end_of_line (str);
3792 return;
3793 }
3794
3795 static void
3796 do_fp_ctrl (str, flags)
3797 char * str;
3798 unsigned long flags ATTRIBUTE_UNUSED;
3799 {
3800 /* FP control registers.
3801 Format: <WFS|RFS|WFC|RFC>{cond} Rn */
3802
3803 skip_whitespace (str);
3804
3805 if (reg_required_here (&str, 12) == FAIL)
3806 {
3807 if (!inst.error)
3808 inst.error = BAD_ARGS;
3809 return;
3810 }
3811
3812 end_of_line (str);
3813 return;
3814 }
3815
3816 static void
3817 do_fp_ldst (str, flags)
3818 char * str;
3819 unsigned long flags ATTRIBUTE_UNUSED;
3820 {
3821 skip_whitespace (str);
3822
3823 switch (inst.suffix)
3824 {
3825 case SUFF_S:
3826 break;
3827 case SUFF_D:
3828 inst.instruction |= CP_T_X;
3829 break;
3830 case SUFF_E:
3831 inst.instruction |= CP_T_Y;
3832 break;
3833 case SUFF_P:
3834 inst.instruction |= CP_T_X | CP_T_Y;
3835 break;
3836 default:
3837 abort ();
3838 }
3839
3840 if (fp_reg_required_here (&str, 12) == FAIL)
3841 {
3842 if (!inst.error)
3843 inst.error = BAD_ARGS;
3844 return;
3845 }
3846
3847 if (skip_past_comma (&str) == FAIL
3848 || cp_address_required_here (&str) == FAIL)
3849 {
3850 if (!inst.error)
3851 inst.error = BAD_ARGS;
3852 return;
3853 }
3854
3855 end_of_line (str);
3856 }
3857
3858 static void
3859 do_fp_ldmstm (str, flags)
3860 char * str;
3861 unsigned long flags;
3862 {
3863 int num_regs;
3864
3865 skip_whitespace (str);
3866
3867 if (fp_reg_required_here (&str, 12) == FAIL)
3868 {
3869 if (! inst.error)
3870 inst.error = BAD_ARGS;
3871 return;
3872 }
3873
3874 /* Get Number of registers to transfer. */
3875 if (skip_past_comma (&str) == FAIL
3876 || my_get_expression (&inst.reloc.exp, &str))
3877 {
3878 if (! inst.error)
3879 inst.error = _("constant expression expected");
3880 return;
3881 }
3882
3883 if (inst.reloc.exp.X_op != O_constant)
3884 {
3885 inst.error = _("Constant value required for number of registers");
3886 return;
3887 }
3888
3889 num_regs = inst.reloc.exp.X_add_number;
3890
3891 if (num_regs < 1 || num_regs > 4)
3892 {
3893 inst.error = _("number of registers must be in the range [1:4]");
3894 return;
3895 }
3896
3897 switch (num_regs)
3898 {
3899 case 1:
3900 inst.instruction |= CP_T_X;
3901 break;
3902 case 2:
3903 inst.instruction |= CP_T_Y;
3904 break;
3905 case 3:
3906 inst.instruction |= CP_T_Y | CP_T_X;
3907 break;
3908 case 4:
3909 break;
3910 default:
3911 abort ();
3912 }
3913
3914 if (flags)
3915 {
3916 int reg;
3917 int write_back;
3918 int offset;
3919
3920 /* The instruction specified "ea" or "fd", so we can only accept
3921 [Rn]{!}. The instruction does not really support stacking or
3922 unstacking, so we have to emulate these by setting appropriate
3923 bits and offsets. */
3924 if (skip_past_comma (&str) == FAIL
3925 || *str != '[')
3926 {
3927 if (! inst.error)
3928 inst.error = BAD_ARGS;
3929 return;
3930 }
3931
3932 str++;
3933 skip_whitespace (str);
3934
3935 if ((reg = reg_required_here (&str, 16)) == FAIL)
3936 return;
3937
3938 skip_whitespace (str);
3939
3940 if (*str != ']')
3941 {
3942 inst.error = BAD_ARGS;
3943 return;
3944 }
3945
3946 str++;
3947 if (*str == '!')
3948 {
3949 write_back = 1;
3950 str++;
3951 if (reg == REG_PC)
3952 {
3953 inst.error =
3954 _("R15 not allowed as base register with write-back");
3955 return;
3956 }
3957 }
3958 else
3959 write_back = 0;
3960
3961 if (flags & CP_T_Pre)
3962 {
3963 /* Pre-decrement. */
3964 offset = 3 * num_regs;
3965 if (write_back)
3966 flags |= CP_T_WB;
3967 }
3968 else
3969 {
3970 /* Post-increment. */
3971 if (write_back)
3972 {
3973 flags |= CP_T_WB;
3974 offset = 3 * num_regs;
3975 }
3976 else
3977 {
3978 /* No write-back, so convert this into a standard pre-increment
3979 instruction -- aesthetically more pleasing. */
3980 flags = CP_T_Pre | CP_T_UD;
3981 offset = 0;
3982 }
3983 }
3984
3985 inst.instruction |= flags | offset;
3986 }
3987 else if (skip_past_comma (&str) == FAIL
3988 || cp_address_required_here (&str) == FAIL)
3989 {
3990 if (! inst.error)
3991 inst.error = BAD_ARGS;
3992 return;
3993 }
3994
3995 end_of_line (str);
3996 }
3997
3998 static void
3999 do_fp_dyadic (str, flags)
4000 char * str;
4001 unsigned long flags;
4002 {
4003 skip_whitespace (str);
4004
4005 switch (inst.suffix)
4006 {
4007 case SUFF_S:
4008 break;
4009 case SUFF_D:
4010 inst.instruction |= 0x00000080;
4011 break;
4012 case SUFF_E:
4013 inst.instruction |= 0x00080000;
4014 break;
4015 default:
4016 abort ();
4017 }
4018
4019 if (fp_reg_required_here (&str, 12) == FAIL)
4020 {
4021 if (! inst.error)
4022 inst.error = BAD_ARGS;
4023 return;
4024 }
4025
4026 if (skip_past_comma (&str) == FAIL
4027 || fp_reg_required_here (&str, 16) == FAIL)
4028 {
4029 if (! inst.error)
4030 inst.error = BAD_ARGS;
4031 return;
4032 }
4033
4034 if (skip_past_comma (&str) == FAIL
4035 || fp_op2 (&str) == FAIL)
4036 {
4037 if (! inst.error)
4038 inst.error = BAD_ARGS;
4039 return;
4040 }
4041
4042 inst.instruction |= flags;
4043 end_of_line (str);
4044 return;
4045 }
4046
4047 static void
4048 do_fp_monadic (str, flags)
4049 char * str;
4050 unsigned long flags;
4051 {
4052 skip_whitespace (str);
4053
4054 switch (inst.suffix)
4055 {
4056 case SUFF_S:
4057 break;
4058 case SUFF_D:
4059 inst.instruction |= 0x00000080;
4060 break;
4061 case SUFF_E:
4062 inst.instruction |= 0x00080000;
4063 break;
4064 default:
4065 abort ();
4066 }
4067
4068 if (fp_reg_required_here (&str, 12) == FAIL)
4069 {
4070 if (! inst.error)
4071 inst.error = BAD_ARGS;
4072 return;
4073 }
4074
4075 if (skip_past_comma (&str) == FAIL
4076 || fp_op2 (&str) == FAIL)
4077 {
4078 if (! inst.error)
4079 inst.error = BAD_ARGS;
4080 return;
4081 }
4082
4083 inst.instruction |= flags;
4084 end_of_line (str);
4085 return;
4086 }
4087
4088 static void
4089 do_fp_cmp (str, flags)
4090 char * str;
4091 unsigned long flags;
4092 {
4093 skip_whitespace (str);
4094
4095 if (fp_reg_required_here (&str, 16) == FAIL)
4096 {
4097 if (! inst.error)
4098 inst.error = BAD_ARGS;
4099 return;
4100 }
4101
4102 if (skip_past_comma (&str) == FAIL
4103 || fp_op2 (&str) == FAIL)
4104 {
4105 if (! inst.error)
4106 inst.error = BAD_ARGS;
4107 return;
4108 }
4109
4110 inst.instruction |= flags;
4111 end_of_line (str);
4112 return;
4113 }
4114
4115 static void
4116 do_fp_from_reg (str, flags)
4117 char * str;
4118 unsigned long flags;
4119 {
4120 skip_whitespace (str);
4121
4122 switch (inst.suffix)
4123 {
4124 case SUFF_S:
4125 break;
4126 case SUFF_D:
4127 inst.instruction |= 0x00000080;
4128 break;
4129 case SUFF_E:
4130 inst.instruction |= 0x00080000;
4131 break;
4132 default:
4133 abort ();
4134 }
4135
4136 if (fp_reg_required_here (&str, 16) == FAIL)
4137 {
4138 if (! inst.error)
4139 inst.error = BAD_ARGS;
4140 return;
4141 }
4142
4143 if (skip_past_comma (&str) == FAIL
4144 || reg_required_here (&str, 12) == FAIL)
4145 {
4146 if (! inst.error)
4147 inst.error = BAD_ARGS;
4148 return;
4149 }
4150
4151 inst.instruction |= flags;
4152 end_of_line (str);
4153 return;
4154 }
4155
4156 static void
4157 do_fp_to_reg (str, flags)
4158 char * str;
4159 unsigned long flags;
4160 {
4161 skip_whitespace (str);
4162
4163 if (reg_required_here (&str, 12) == FAIL)
4164 return;
4165
4166 if (skip_past_comma (&str) == FAIL
4167 || fp_reg_required_here (&str, 0) == FAIL)
4168 {
4169 if (! inst.error)
4170 inst.error = BAD_ARGS;
4171 return;
4172 }
4173
4174 inst.instruction |= flags;
4175 end_of_line (str);
4176 return;
4177 }
4178
4179 /* Thumb specific routines. */
4180
4181 /* Parse and validate that a register is of the right form, this saves
4182 repeated checking of this information in many similar cases.
4183 Unlike the 32-bit case we do not insert the register into the opcode
4184 here, since the position is often unknown until the full instruction
4185 has been parsed. */
4186
4187 static int
4188 thumb_reg (strp, hi_lo)
4189 char ** strp;
4190 int hi_lo;
4191 {
4192 int reg;
4193
4194 if ((reg = reg_required_here (strp, -1)) == FAIL)
4195 return FAIL;
4196
4197 switch (hi_lo)
4198 {
4199 case THUMB_REG_LO:
4200 if (reg > 7)
4201 {
4202 inst.error = _("lo register required");
4203 return FAIL;
4204 }
4205 break;
4206
4207 case THUMB_REG_HI:
4208 if (reg < 8)
4209 {
4210 inst.error = _("hi register required");
4211 return FAIL;
4212 }
4213 break;
4214
4215 default:
4216 break;
4217 }
4218
4219 return reg;
4220 }
4221
4222 /* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode
4223 was SUB. */
4224
4225 static void
4226 thumb_add_sub (str, subtract)
4227 char * str;
4228 int subtract;
4229 {
4230 int Rd, Rs, Rn = FAIL;
4231
4232 skip_whitespace (str);
4233
4234 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
4235 || skip_past_comma (&str) == FAIL)
4236 {
4237 if (! inst.error)
4238 inst.error = BAD_ARGS;
4239 return;
4240 }
4241
4242 if (is_immediate_prefix (*str))
4243 {
4244 Rs = Rd;
4245 str++;
4246 if (my_get_expression (&inst.reloc.exp, &str))
4247 return;
4248 }
4249 else
4250 {
4251 if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4252 return;
4253
4254 if (skip_past_comma (&str) == FAIL)
4255 {
4256 /* Two operand format, shuffle the registers
4257 and pretend there are 3. */
4258 Rn = Rs;
4259 Rs = Rd;
4260 }
4261 else if (is_immediate_prefix (*str))
4262 {
4263 str++;
4264 if (my_get_expression (&inst.reloc.exp, &str))
4265 return;
4266 }
4267 else if ((Rn = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4268 return;
4269 }
4270
4271 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
4272 for the latter case, EXPR contains the immediate that was found. */
4273 if (Rn != FAIL)
4274 {
4275 /* All register format. */
4276 if (Rd > 7 || Rs > 7 || Rn > 7)
4277 {
4278 if (Rs != Rd)
4279 {
4280 inst.error = _("dest and source1 must be the same register");
4281 return;
4282 }
4283
4284 /* Can't do this for SUB. */
4285 if (subtract)
4286 {
4287 inst.error = _("subtract valid only on lo regs");
4288 return;
4289 }
4290
4291 inst.instruction = (T_OPCODE_ADD_HI
4292 | (Rd > 7 ? THUMB_H1 : 0)
4293 | (Rn > 7 ? THUMB_H2 : 0));
4294 inst.instruction |= (Rd & 7) | ((Rn & 7) << 3);
4295 }
4296 else
4297 {
4298 inst.instruction = subtract ? T_OPCODE_SUB_R3 : T_OPCODE_ADD_R3;
4299 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
4300 }
4301 }
4302 else
4303 {
4304 /* Immediate expression, now things start to get nasty. */
4305
4306 /* First deal with HI regs, only very restricted cases allowed:
4307 Adjusting SP, and using PC or SP to get an address. */
4308 if ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
4309 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC))
4310 {
4311 inst.error = _("invalid Hi register with immediate");
4312 return;
4313 }
4314
4315 if (inst.reloc.exp.X_op != O_constant)
4316 {
4317 /* Value isn't known yet, all we can do is store all the fragments
4318 we know about in the instruction and let the reloc hacking
4319 work it all out. */
4320 inst.instruction = (subtract ? 0x8000 : 0) | (Rd << 4) | Rs;
4321 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
4322 }
4323 else
4324 {
4325 int offset = inst.reloc.exp.X_add_number;
4326
4327 if (subtract)
4328 offset = -offset;
4329
4330 if (offset < 0)
4331 {
4332 offset = -offset;
4333 subtract = 1;
4334
4335 /* Quick check, in case offset is MIN_INT. */
4336 if (offset < 0)
4337 {
4338 inst.error = _("immediate value out of range");
4339 return;
4340 }
4341 }
4342 else
4343 subtract = 0;
4344
4345 if (Rd == REG_SP)
4346 {
4347 if (offset & ~0x1fc)
4348 {
4349 inst.error = _("invalid immediate value for stack adjust");
4350 return;
4351 }
4352 inst.instruction = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
4353 inst.instruction |= offset >> 2;
4354 }
4355 else if (Rs == REG_PC || Rs == REG_SP)
4356 {
4357 if (subtract
4358 || (offset & ~0x3fc))
4359 {
4360 inst.error = _("invalid immediate for address calculation");
4361 return;
4362 }
4363 inst.instruction = (Rs == REG_PC ? T_OPCODE_ADD_PC
4364 : T_OPCODE_ADD_SP);
4365 inst.instruction |= (Rd << 8) | (offset >> 2);
4366 }
4367 else if (Rs == Rd)
4368 {
4369 if (offset & ~0xff)
4370 {
4371 inst.error = _("immediate value out of range");
4372 return;
4373 }
4374 inst.instruction = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
4375 inst.instruction |= (Rd << 8) | offset;
4376 }
4377 else
4378 {
4379 if (offset & ~0x7)
4380 {
4381 inst.error = _("immediate value out of range");
4382 return;
4383 }
4384 inst.instruction = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
4385 inst.instruction |= Rd | (Rs << 3) | (offset << 6);
4386 }
4387 }
4388 }
4389
4390 end_of_line (str);
4391 }
4392
4393 static void
4394 thumb_shift (str, shift)
4395 char * str;
4396 int shift;
4397 {
4398 int Rd, Rs, Rn = FAIL;
4399
4400 skip_whitespace (str);
4401
4402 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4403 || skip_past_comma (&str) == FAIL)
4404 {
4405 if (! inst.error)
4406 inst.error = BAD_ARGS;
4407 return;
4408 }
4409
4410 if (is_immediate_prefix (*str))
4411 {
4412 /* Two operand immediate format, set Rs to Rd. */
4413 Rs = Rd;
4414 str ++;
4415 if (my_get_expression (&inst.reloc.exp, &str))
4416 return;
4417 }
4418 else
4419 {
4420 if ((Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4421 return;
4422
4423 if (skip_past_comma (&str) == FAIL)
4424 {
4425 /* Two operand format, shuffle the registers
4426 and pretend there are 3. */
4427 Rn = Rs;
4428 Rs = Rd;
4429 }
4430 else if (is_immediate_prefix (*str))
4431 {
4432 str++;
4433 if (my_get_expression (&inst.reloc.exp, &str))
4434 return;
4435 }
4436 else if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4437 return;
4438 }
4439
4440 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
4441 for the latter case, EXPR contains the immediate that was found. */
4442
4443 if (Rn != FAIL)
4444 {
4445 if (Rs != Rd)
4446 {
4447 inst.error = _("source1 and dest must be same register");
4448 return;
4449 }
4450
4451 switch (shift)
4452 {
4453 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_R; break;
4454 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_R; break;
4455 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_R; break;
4456 }
4457
4458 inst.instruction |= Rd | (Rn << 3);
4459 }
4460 else
4461 {
4462 switch (shift)
4463 {
4464 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_I; break;
4465 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_I; break;
4466 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_I; break;
4467 }
4468
4469 if (inst.reloc.exp.X_op != O_constant)
4470 {
4471 /* Value isn't known yet, create a dummy reloc and let reloc
4472 hacking fix it up. */
4473 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
4474 }
4475 else
4476 {
4477 unsigned shift_value = inst.reloc.exp.X_add_number;
4478
4479 if (shift_value > 32 || (shift_value == 32 && shift == THUMB_LSL))
4480 {
4481 inst.error = _("Invalid immediate for shift");
4482 return;
4483 }
4484
4485 /* Shifts of zero are handled by converting to LSL. */
4486 if (shift_value == 0)
4487 inst.instruction = T_OPCODE_LSL_I;
4488
4489 /* Shifts of 32 are encoded as a shift of zero. */
4490 if (shift_value == 32)
4491 shift_value = 0;
4492
4493 inst.instruction |= shift_value << 6;
4494 }
4495
4496 inst.instruction |= Rd | (Rs << 3);
4497 }
4498
4499 end_of_line (str);
4500 }
4501
4502 static void
4503 thumb_mov_compare (str, move)
4504 char * str;
4505 int move;
4506 {
4507 int Rd, Rs = FAIL;
4508
4509 skip_whitespace (str);
4510
4511 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
4512 || skip_past_comma (&str) == FAIL)
4513 {
4514 if (! inst.error)
4515 inst.error = BAD_ARGS;
4516 return;
4517 }
4518
4519 if (is_immediate_prefix (*str))
4520 {
4521 str++;
4522 if (my_get_expression (&inst.reloc.exp, &str))
4523 return;
4524 }
4525 else if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4526 return;
4527
4528 if (Rs != FAIL)
4529 {
4530 if (Rs < 8 && Rd < 8)
4531 {
4532 if (move == THUMB_MOVE)
4533 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
4534 since a MOV instruction produces unpredictable results. */
4535 inst.instruction = T_OPCODE_ADD_I3;
4536 else
4537 inst.instruction = T_OPCODE_CMP_LR;
4538 inst.instruction |= Rd | (Rs << 3);
4539 }
4540 else
4541 {
4542 if (move == THUMB_MOVE)
4543 inst.instruction = T_OPCODE_MOV_HR;
4544 else
4545 inst.instruction = T_OPCODE_CMP_HR;
4546
4547 if (Rd > 7)
4548 inst.instruction |= THUMB_H1;
4549
4550 if (Rs > 7)
4551 inst.instruction |= THUMB_H2;
4552
4553 inst.instruction |= (Rd & 7) | ((Rs & 7) << 3);
4554 }
4555 }
4556 else
4557 {
4558 if (Rd > 7)
4559 {
4560 inst.error = _("only lo regs allowed with immediate");
4561 return;
4562 }
4563
4564 if (move == THUMB_MOVE)
4565 inst.instruction = T_OPCODE_MOV_I8;
4566 else
4567 inst.instruction = T_OPCODE_CMP_I8;
4568
4569 inst.instruction |= Rd << 8;
4570
4571 if (inst.reloc.exp.X_op != O_constant)
4572 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
4573 else
4574 {
4575 unsigned value = inst.reloc.exp.X_add_number;
4576
4577 if (value > 255)
4578 {
4579 inst.error = _("invalid immediate");
4580 return;
4581 }
4582
4583 inst.instruction |= value;
4584 }
4585 }
4586
4587 end_of_line (str);
4588 }
4589
4590 static void
4591 thumb_load_store (str, load_store, size)
4592 char * str;
4593 int load_store;
4594 int size;
4595 {
4596 int Rd, Rb, Ro = FAIL;
4597
4598 skip_whitespace (str);
4599
4600 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4601 || skip_past_comma (&str) == FAIL)
4602 {
4603 if (! inst.error)
4604 inst.error = BAD_ARGS;
4605 return;
4606 }
4607
4608 if (*str == '[')
4609 {
4610 str++;
4611 if ((Rb = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4612 return;
4613
4614 if (skip_past_comma (&str) != FAIL)
4615 {
4616 if (is_immediate_prefix (*str))
4617 {
4618 str++;
4619 if (my_get_expression (&inst.reloc.exp, &str))
4620 return;
4621 }
4622 else if ((Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4623 return;
4624 }
4625 else
4626 {
4627 inst.reloc.exp.X_op = O_constant;
4628 inst.reloc.exp.X_add_number = 0;
4629 }
4630
4631 if (*str != ']')
4632 {
4633 inst.error = _("expected ']'");
4634 return;
4635 }
4636 str++;
4637 }
4638 else if (*str == '=')
4639 {
4640 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
4641 str++;
4642
4643 skip_whitespace (str);
4644
4645 if (my_get_expression (& inst.reloc.exp, & str))
4646 return;
4647
4648 end_of_line (str);
4649
4650 if ( inst.reloc.exp.X_op != O_constant
4651 && inst.reloc.exp.X_op != O_symbol)
4652 {
4653 inst.error = "Constant expression expected";
4654 return;
4655 }
4656
4657 if (inst.reloc.exp.X_op == O_constant
4658 && ((inst.reloc.exp.X_add_number & ~0xFF) == 0))
4659 {
4660 /* This can be done with a mov instruction. */
4661
4662 inst.instruction = T_OPCODE_MOV_I8 | (Rd << 8);
4663 inst.instruction |= inst.reloc.exp.X_add_number;
4664 return;
4665 }
4666
4667 /* Insert into literal pool. */
4668 if (add_to_lit_pool () == FAIL)
4669 {
4670 if (!inst.error)
4671 inst.error = "literal pool insertion failed";
4672 return;
4673 }
4674
4675 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4676 inst.reloc.pc_rel = 1;
4677 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
4678 /* Adjust ARM pipeline offset to Thumb. */
4679 inst.reloc.exp.X_add_number += 4;
4680
4681 return;
4682 }
4683 else
4684 {
4685 if (my_get_expression (&inst.reloc.exp, &str))
4686 return;
4687
4688 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
4689 inst.reloc.pc_rel = 1;
4690 inst.reloc.exp.X_add_number -= 4; /* Pipeline offset. */
4691 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4692 end_of_line (str);
4693 return;
4694 }
4695
4696 if (Rb == REG_PC || Rb == REG_SP)
4697 {
4698 if (size != THUMB_WORD)
4699 {
4700 inst.error = _("byte or halfword not valid for base register");
4701 return;
4702 }
4703 else if (Rb == REG_PC && load_store != THUMB_LOAD)
4704 {
4705 inst.error = _("R15 based store not allowed");
4706 return;
4707 }
4708 else if (Ro != FAIL)
4709 {
4710 inst.error = _("Invalid base register for register offset");
4711 return;
4712 }
4713
4714 if (Rb == REG_PC)
4715 inst.instruction = T_OPCODE_LDR_PC;
4716 else if (load_store == THUMB_LOAD)
4717 inst.instruction = T_OPCODE_LDR_SP;
4718 else
4719 inst.instruction = T_OPCODE_STR_SP;
4720
4721 inst.instruction |= Rd << 8;
4722 if (inst.reloc.exp.X_op == O_constant)
4723 {
4724 unsigned offset = inst.reloc.exp.X_add_number;
4725
4726 if (offset & ~0x3fc)
4727 {
4728 inst.error = _("invalid offset");
4729 return;
4730 }
4731
4732 inst.instruction |= offset >> 2;
4733 }
4734 else
4735 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4736 }
4737 else if (Rb > 7)
4738 {
4739 inst.error = _("invalid base register in load/store");
4740 return;
4741 }
4742 else if (Ro == FAIL)
4743 {
4744 /* Immediate offset. */
4745 if (size == THUMB_WORD)
4746 inst.instruction = (load_store == THUMB_LOAD
4747 ? T_OPCODE_LDR_IW : T_OPCODE_STR_IW);
4748 else if (size == THUMB_HALFWORD)
4749 inst.instruction = (load_store == THUMB_LOAD
4750 ? T_OPCODE_LDR_IH : T_OPCODE_STR_IH);
4751 else
4752 inst.instruction = (load_store == THUMB_LOAD
4753 ? T_OPCODE_LDR_IB : T_OPCODE_STR_IB);
4754
4755 inst.instruction |= Rd | (Rb << 3);
4756
4757 if (inst.reloc.exp.X_op == O_constant)
4758 {
4759 unsigned offset = inst.reloc.exp.X_add_number;
4760
4761 if (offset & ~(0x1f << size))
4762 {
4763 inst.error = _("Invalid offset");
4764 return;
4765 }
4766 inst.instruction |= (offset >> size) << 6;
4767 }
4768 else
4769 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4770 }
4771 else
4772 {
4773 /* Register offset. */
4774 if (size == THUMB_WORD)
4775 inst.instruction = (load_store == THUMB_LOAD
4776 ? T_OPCODE_LDR_RW : T_OPCODE_STR_RW);
4777 else if (size == THUMB_HALFWORD)
4778 inst.instruction = (load_store == THUMB_LOAD
4779 ? T_OPCODE_LDR_RH : T_OPCODE_STR_RH);
4780 else
4781 inst.instruction = (load_store == THUMB_LOAD
4782 ? T_OPCODE_LDR_RB : T_OPCODE_STR_RB);
4783
4784 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
4785 }
4786
4787 end_of_line (str);
4788 }
4789
4790 static void
4791 do_t_nop (str)
4792 char * str;
4793 {
4794 /* Do nothing. */
4795 end_of_line (str);
4796 return;
4797 }
4798
4799 /* Handle the Format 4 instructions that do not have equivalents in other
4800 formats. That is, ADC, AND, EOR, SBC, ROR, TST, NEG, CMN, ORR, MUL,
4801 BIC and MVN. */
4802
4803 static void
4804 do_t_arit (str)
4805 char * str;
4806 {
4807 int Rd, Rs, Rn;
4808
4809 skip_whitespace (str);
4810
4811 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4812 || skip_past_comma (&str) == FAIL
4813 || (Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4814 {
4815 inst.error = BAD_ARGS;
4816 return;
4817 }
4818
4819 if (skip_past_comma (&str) != FAIL)
4820 {
4821 /* Three operand format not allowed for TST, CMN, NEG and MVN.
4822 (It isn't allowed for CMP either, but that isn't handled by this
4823 function.) */
4824 if (inst.instruction == T_OPCODE_TST
4825 || inst.instruction == T_OPCODE_CMN
4826 || inst.instruction == T_OPCODE_NEG
4827 || inst.instruction == T_OPCODE_MVN)
4828 {
4829 inst.error = BAD_ARGS;
4830 return;
4831 }
4832
4833 if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4834 return;
4835
4836 if (Rs != Rd)
4837 {
4838 inst.error = _("dest and source1 one must be the same register");
4839 return;
4840 }
4841 Rs = Rn;
4842 }
4843
4844 if (inst.instruction == T_OPCODE_MUL
4845 && Rs == Rd)
4846 as_tsktsk (_("Rs and Rd must be different in MUL"));
4847
4848 inst.instruction |= Rd | (Rs << 3);
4849 end_of_line (str);
4850 }
4851
4852 static void
4853 do_t_add (str)
4854 char * str;
4855 {
4856 thumb_add_sub (str, 0);
4857 }
4858
4859 static void
4860 do_t_asr (str)
4861 char * str;
4862 {
4863 thumb_shift (str, THUMB_ASR);
4864 }
4865
4866 static void
4867 do_t_branch9 (str)
4868 char * str;
4869 {
4870 if (my_get_expression (&inst.reloc.exp, &str))
4871 return;
4872 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
4873 inst.reloc.pc_rel = 1;
4874 end_of_line (str);
4875 }
4876
4877 static void
4878 do_t_branch12 (str)
4879 char * str;
4880 {
4881 if (my_get_expression (&inst.reloc.exp, &str))
4882 return;
4883 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
4884 inst.reloc.pc_rel = 1;
4885 end_of_line (str);
4886 }
4887
4888 /* Find the real, Thumb encoded start of a Thumb function. */
4889
4890 static symbolS *
4891 find_real_start (symbolP)
4892 symbolS * symbolP;
4893 {
4894 char * real_start;
4895 const char * name = S_GET_NAME (symbolP);
4896 symbolS * new_target;
4897
4898 /* This definiton must agree with the one in gcc/config/arm/thumb.c. */
4899 #define STUB_NAME ".real_start_of"
4900
4901 if (name == NULL)
4902 abort ();
4903
4904 /* Names that start with '.' are local labels, not function entry points.
4905 The compiler may generate BL instructions to these labels because it
4906 needs to perform a branch to a far away location. */
4907 if (name[0] == '.')
4908 return symbolP;
4909
4910 real_start = malloc (strlen (name) + strlen (STUB_NAME) + 1);
4911 sprintf (real_start, "%s%s", STUB_NAME, name);
4912
4913 new_target = symbol_find (real_start);
4914
4915 if (new_target == NULL)
4916 {
4917 as_warn ("Failed to find real start of function: %s\n", name);
4918 new_target = symbolP;
4919 }
4920
4921 free (real_start);
4922
4923 return new_target;
4924 }
4925
4926 static void
4927 do_t_branch23 (str)
4928 char * str;
4929 {
4930 if (my_get_expression (& inst.reloc.exp, & str))
4931 return;
4932
4933 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
4934 inst.reloc.pc_rel = 1;
4935 end_of_line (str);
4936
4937 /* If the destination of the branch is a defined symbol which does not have
4938 the THUMB_FUNC attribute, then we must be calling a function which has
4939 the (interfacearm) attribute. We look for the Thumb entry point to that
4940 function and change the branch to refer to that function instead. */
4941 if ( inst.reloc.exp.X_op == O_symbol
4942 && inst.reloc.exp.X_add_symbol != NULL
4943 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
4944 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
4945 inst.reloc.exp.X_add_symbol =
4946 find_real_start (inst.reloc.exp.X_add_symbol);
4947 }
4948
4949 static void
4950 do_t_bx (str)
4951 char * str;
4952 {
4953 int reg;
4954
4955 skip_whitespace (str);
4956
4957 if ((reg = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4958 return;
4959
4960 /* This sets THUMB_H2 from the top bit of reg. */
4961 inst.instruction |= reg << 3;
4962
4963 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
4964 should cause the alignment to be checked once it is known. This is
4965 because BX PC only works if the instruction is word aligned. */
4966
4967 end_of_line (str);
4968 }
4969
4970 static void
4971 do_t_compare (str)
4972 char * str;
4973 {
4974 thumb_mov_compare (str, THUMB_COMPARE);
4975 }
4976
4977 static void
4978 do_t_ldmstm (str)
4979 char * str;
4980 {
4981 int Rb;
4982 long range;
4983
4984 skip_whitespace (str);
4985
4986 if ((Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4987 return;
4988
4989 if (*str != '!')
4990 as_warn (_("Inserted missing '!': load/store multiple always writes back base register"));
4991 else
4992 str++;
4993
4994 if (skip_past_comma (&str) == FAIL
4995 || (range = reg_list (&str)) == FAIL)
4996 {
4997 if (! inst.error)
4998 inst.error = BAD_ARGS;
4999 return;
5000 }
5001
5002 if (inst.reloc.type != BFD_RELOC_NONE)
5003 {
5004 /* This really doesn't seem worth it. */
5005 inst.reloc.type = BFD_RELOC_NONE;
5006 inst.error = _("Expression too complex");
5007 return;
5008 }
5009
5010 if (range & ~0xff)
5011 {
5012 inst.error = _("only lo-regs valid in load/store multiple");
5013 return;
5014 }
5015
5016 inst.instruction |= (Rb << 8) | range;
5017 end_of_line (str);
5018 }
5019
5020 static void
5021 do_t_ldr (str)
5022 char * str;
5023 {
5024 thumb_load_store (str, THUMB_LOAD, THUMB_WORD);
5025 }
5026
5027 static void
5028 do_t_ldrb (str)
5029 char * str;
5030 {
5031 thumb_load_store (str, THUMB_LOAD, THUMB_BYTE);
5032 }
5033
5034 static void
5035 do_t_ldrh (str)
5036 char * str;
5037 {
5038 thumb_load_store (str, THUMB_LOAD, THUMB_HALFWORD);
5039 }
5040
5041 static void
5042 do_t_lds (str)
5043 char * str;
5044 {
5045 int Rd, Rb, Ro;
5046
5047 skip_whitespace (str);
5048
5049 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
5050 || skip_past_comma (&str) == FAIL
5051 || *str++ != '['
5052 || (Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL
5053 || skip_past_comma (&str) == FAIL
5054 || (Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL
5055 || *str++ != ']')
5056 {
5057 if (! inst.error)
5058 inst.error = _("Syntax: ldrs[b] Rd, [Rb, Ro]");
5059 return;
5060 }
5061
5062 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
5063 end_of_line (str);
5064 }
5065
5066 static void
5067 do_t_lsl (str)
5068 char * str;
5069 {
5070 thumb_shift (str, THUMB_LSL);
5071 }
5072
5073 static void
5074 do_t_lsr (str)
5075 char * str;
5076 {
5077 thumb_shift (str, THUMB_LSR);
5078 }
5079
5080 static void
5081 do_t_mov (str)
5082 char * str;
5083 {
5084 thumb_mov_compare (str, THUMB_MOVE);
5085 }
5086
5087 static void
5088 do_t_push_pop (str)
5089 char * str;
5090 {
5091 long range;
5092
5093 skip_whitespace (str);
5094
5095 if ((range = reg_list (&str)) == FAIL)
5096 {
5097 if (! inst.error)
5098 inst.error = BAD_ARGS;
5099 return;
5100 }
5101
5102 if (inst.reloc.type != BFD_RELOC_NONE)
5103 {
5104 /* This really doesn't seem worth it. */
5105 inst.reloc.type = BFD_RELOC_NONE;
5106 inst.error = _("Expression too complex");
5107 return;
5108 }
5109
5110 if (range & ~0xff)
5111 {
5112 if ((inst.instruction == T_OPCODE_PUSH
5113 && (range & ~0xff) == 1 << REG_LR)
5114 || (inst.instruction == T_OPCODE_POP
5115 && (range & ~0xff) == 1 << REG_PC))
5116 {
5117 inst.instruction |= THUMB_PP_PC_LR;
5118 range &= 0xff;
5119 }
5120 else
5121 {
5122 inst.error = _("invalid register list to push/pop instruction");
5123 return;
5124 }
5125 }
5126
5127 inst.instruction |= range;
5128 end_of_line (str);
5129 }
5130
5131 static void
5132 do_t_str (str)
5133 char * str;
5134 {
5135 thumb_load_store (str, THUMB_STORE, THUMB_WORD);
5136 }
5137
5138 static void
5139 do_t_strb (str)
5140 char * str;
5141 {
5142 thumb_load_store (str, THUMB_STORE, THUMB_BYTE);
5143 }
5144
5145 static void
5146 do_t_strh (str)
5147 char * str;
5148 {
5149 thumb_load_store (str, THUMB_STORE, THUMB_HALFWORD);
5150 }
5151
5152 static void
5153 do_t_sub (str)
5154 char * str;
5155 {
5156 thumb_add_sub (str, 1);
5157 }
5158
5159 static void
5160 do_t_swi (str)
5161 char * str;
5162 {
5163 skip_whitespace (str);
5164
5165 if (my_get_expression (&inst.reloc.exp, &str))
5166 return;
5167
5168 inst.reloc.type = BFD_RELOC_ARM_SWI;
5169 end_of_line (str);
5170 return;
5171 }
5172
5173 static void
5174 do_t_adr (str)
5175 char * str;
5176 {
5177 int reg;
5178
5179 /* This is a pseudo-op of the form "adr rd, label" to be converted
5180 into a relative address of the form "add rd, pc, #label-.-4". */
5181 skip_whitespace (str);
5182
5183 /* Store Rd in temporary location inside instruction. */
5184 if ((reg = reg_required_here (&str, 4)) == FAIL
5185 || (reg > 7) /* For Thumb reg must be r0..r7. */
5186 || skip_past_comma (&str) == FAIL
5187 || my_get_expression (&inst.reloc.exp, &str))
5188 {
5189 if (!inst.error)
5190 inst.error = BAD_ARGS;
5191 return;
5192 }
5193
5194 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
5195 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
5196 inst.reloc.pc_rel = 1;
5197 inst.instruction |= REG_PC; /* Rd is already placed into the instruction. */
5198
5199 end_of_line (str);
5200 }
5201
5202 static void
5203 insert_reg (entry)
5204 int entry;
5205 {
5206 int len = strlen (reg_table[entry].name) + 2;
5207 char * buf = (char *) xmalloc (len);
5208 char * buf2 = (char *) xmalloc (len);
5209 int i = 0;
5210
5211 #ifdef REGISTER_PREFIX
5212 buf[i++] = REGISTER_PREFIX;
5213 #endif
5214
5215 strcpy (buf + i, reg_table[entry].name);
5216
5217 for (i = 0; buf[i]; i++)
5218 buf2[i] = islower (buf[i]) ? toupper (buf[i]) : buf[i];
5219
5220 buf2[i] = '\0';
5221
5222 hash_insert (arm_reg_hsh, buf, (PTR) & reg_table[entry]);
5223 hash_insert (arm_reg_hsh, buf2, (PTR) & reg_table[entry]);
5224 }
5225
5226 static void
5227 insert_reg_alias (str, regnum)
5228 char *str;
5229 int regnum;
5230 {
5231 struct reg_entry *new =
5232 (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
5233 char *name = xmalloc (strlen (str) + 1);
5234 strcpy (name, str);
5235
5236 new->name = name;
5237 new->number = regnum;
5238
5239 hash_insert (arm_reg_hsh, name, (PTR) new);
5240 }
5241
5242 static void
5243 set_constant_flonums ()
5244 {
5245 int i;
5246
5247 for (i = 0; i < NUM_FLOAT_VALS; i++)
5248 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
5249 abort ();
5250 }
5251
5252 void
5253 md_begin ()
5254 {
5255 unsigned mach;
5256 unsigned int i;
5257
5258 if ( (arm_ops_hsh = hash_new ()) == NULL
5259 || (arm_tops_hsh = hash_new ()) == NULL
5260 || (arm_cond_hsh = hash_new ()) == NULL
5261 || (arm_shift_hsh = hash_new ()) == NULL
5262 || (arm_reg_hsh = hash_new ()) == NULL
5263 || (arm_psr_hsh = hash_new ()) == NULL)
5264 as_fatal (_("Virtual memory exhausted"));
5265
5266 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
5267 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
5268 for (i = 0; i < sizeof (tinsns) / sizeof (struct thumb_opcode); i++)
5269 hash_insert (arm_tops_hsh, tinsns[i].template, (PTR) (tinsns + i));
5270 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
5271 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
5272 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
5273 hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i));
5274 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
5275 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
5276
5277 for (i = 0; reg_table[i].name; i++)
5278 insert_reg (i);
5279
5280 set_constant_flonums ();
5281
5282 #if defined OBJ_COFF || defined OBJ_ELF
5283 {
5284 unsigned int flags = 0;
5285
5286 /* Set the flags in the private structure. */
5287 if (uses_apcs_26) flags |= F_APCS26;
5288 if (support_interwork) flags |= F_INTERWORK;
5289 if (uses_apcs_float) flags |= F_APCS_FLOAT;
5290 if (pic_code) flags |= F_PIC;
5291 if ((cpu_variant & FPU_ALL) == FPU_NONE) flags |= F_SOFT_FLOAT;
5292
5293 bfd_set_private_flags (stdoutput, flags);
5294 }
5295 #endif
5296
5297 /* Record the CPU type as well. */
5298 switch (cpu_variant & ARM_CPU_MASK)
5299 {
5300 case ARM_2:
5301 mach = bfd_mach_arm_2;
5302 break;
5303
5304 case ARM_3: /* Also ARM_250. */
5305 mach = bfd_mach_arm_2a;
5306 break;
5307
5308 default:
5309 case ARM_6 | ARM_3 | ARM_2: /* Actually no CPU type defined. */
5310 mach = bfd_mach_arm_4;
5311 break;
5312
5313 case ARM_7: /* Also ARM_6. */
5314 mach = bfd_mach_arm_3;
5315 break;
5316 }
5317
5318 /* Catch special cases. */
5319 if (cpu_variant != (FPU_DEFAULT | CPU_DEFAULT))
5320 {
5321 if (cpu_variant & (ARM_EXT_V5 & ARM_THUMB))
5322 mach = bfd_mach_arm_5T;
5323 else if (cpu_variant & ARM_EXT_V5)
5324 mach = bfd_mach_arm_5;
5325 else if (cpu_variant & ARM_THUMB)
5326 mach = bfd_mach_arm_4T;
5327 else if ((cpu_variant & ARM_ARCH_V4) == ARM_ARCH_V4)
5328 mach = bfd_mach_arm_4;
5329 else if (cpu_variant & ARM_LONGMUL)
5330 mach = bfd_mach_arm_3M;
5331 }
5332
5333 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
5334 }
5335
5336 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
5337 for use in the a.out file, and stores them in the array pointed to by buf.
5338 This knows about the endian-ness of the target machine and does
5339 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
5340 2 (short) and 4 (long) Floating numbers are put out as a series of
5341 LITTLENUMS (shorts, here at least). */
5342
5343 void
5344 md_number_to_chars (buf, val, n)
5345 char * buf;
5346 valueT val;
5347 int n;
5348 {
5349 if (target_big_endian)
5350 number_to_chars_bigendian (buf, val, n);
5351 else
5352 number_to_chars_littleendian (buf, val, n);
5353 }
5354
5355 static valueT
5356 md_chars_to_number (buf, n)
5357 char * buf;
5358 int n;
5359 {
5360 valueT result = 0;
5361 unsigned char * where = (unsigned char *) buf;
5362
5363 if (target_big_endian)
5364 {
5365 while (n--)
5366 {
5367 result <<= 8;
5368 result |= (*where++ & 255);
5369 }
5370 }
5371 else
5372 {
5373 while (n--)
5374 {
5375 result <<= 8;
5376 result |= (where[n] & 255);
5377 }
5378 }
5379
5380 return result;
5381 }
5382
5383 /* Turn a string in input_line_pointer into a floating point constant
5384 of type TYPE, and store the appropriate bytes in *LITP. The number
5385 of LITTLENUMS emitted is stored in *SIZEP. An error message is
5386 returned, or NULL on OK.
5387
5388 Note that fp constants aren't represent in the normal way on the ARM.
5389 In big endian mode, things are as expected. However, in little endian
5390 mode fp constants are big-endian word-wise, and little-endian byte-wise
5391 within the words. For example, (double) 1.1 in big endian mode is
5392 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
5393 the byte sequence 99 99 f1 3f 9a 99 99 99.
5394
5395 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
5396
5397 char *
5398 md_atof (type, litP, sizeP)
5399 char type;
5400 char * litP;
5401 int * sizeP;
5402 {
5403 int prec;
5404 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5405 char *t;
5406 int i;
5407
5408 switch (type)
5409 {
5410 case 'f':
5411 case 'F':
5412 case 's':
5413 case 'S':
5414 prec = 2;
5415 break;
5416
5417 case 'd':
5418 case 'D':
5419 case 'r':
5420 case 'R':
5421 prec = 4;
5422 break;
5423
5424 case 'x':
5425 case 'X':
5426 prec = 6;
5427 break;
5428
5429 case 'p':
5430 case 'P':
5431 prec = 6;
5432 break;
5433
5434 default:
5435 *sizeP = 0;
5436 return _("Bad call to MD_ATOF()");
5437 }
5438
5439 t = atof_ieee (input_line_pointer, type, words);
5440 if (t)
5441 input_line_pointer = t;
5442 *sizeP = prec * 2;
5443
5444 if (target_big_endian)
5445 {
5446 for (i = 0; i < prec; i++)
5447 {
5448 md_number_to_chars (litP, (valueT) words[i], 2);
5449 litP += 2;
5450 }
5451 }
5452 else
5453 {
5454 /* For a 4 byte float the order of elements in `words' is 1 0. For an
5455 8 byte float the order is 1 0 3 2. */
5456 for (i = 0; i < prec; i += 2)
5457 {
5458 md_number_to_chars (litP, (valueT) words[i + 1], 2);
5459 md_number_to_chars (litP + 2, (valueT) words[i], 2);
5460 litP += 4;
5461 }
5462 }
5463
5464 return 0;
5465 }
5466
5467 /* The knowledge of the PC's pipeline offset is built into the insns
5468 themselves. */
5469
5470 long
5471 md_pcrel_from (fixP)
5472 fixS * fixP;
5473 {
5474 if (fixP->fx_addsy
5475 && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section
5476 && fixP->fx_subsy == NULL)
5477 return 0;
5478
5479 if (fixP->fx_pcrel && (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_ADD))
5480 {
5481 /* PC relative addressing on the Thumb is slightly odd
5482 as the bottom two bits of the PC are forced to zero
5483 for the calculation. */
5484 return (fixP->fx_where + fixP->fx_frag->fr_address) & ~3;
5485 }
5486
5487 #ifdef TE_WINCE
5488 /* The pattern was adjusted to accomodate CE's off-by-one fixups,
5489 so we un-adjust here to compensate for the accomodation. */
5490 return fixP->fx_where + fixP->fx_frag->fr_address + 8;
5491 #else
5492 return fixP->fx_where + fixP->fx_frag->fr_address;
5493 #endif
5494 }
5495
5496 /* Round up a section size to the appropriate boundary. */
5497
5498 valueT
5499 md_section_align (segment, size)
5500 segT segment ATTRIBUTE_UNUSED;
5501 valueT size;
5502 {
5503 #ifdef OBJ_ELF
5504 return size;
5505 #else
5506 /* Round all sects to multiple of 4. */
5507 return (size + 3) & ~3;
5508 #endif
5509 }
5510
5511 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
5512 Otherwise we have no need to default values of symbols. */
5513
5514 symbolS *
5515 md_undefined_symbol (name)
5516 char * name ATTRIBUTE_UNUSED;
5517 {
5518 #ifdef OBJ_ELF
5519 if (name[0] == '_' && name[1] == 'G'
5520 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
5521 {
5522 if (!GOT_symbol)
5523 {
5524 if (symbol_find (name))
5525 as_bad ("GOT already in the symbol table");
5526
5527 GOT_symbol = symbol_new (name, undefined_section,
5528 (valueT) 0, & zero_address_frag);
5529 }
5530
5531 return GOT_symbol;
5532 }
5533 #endif
5534
5535 return 0;
5536 }
5537
5538 /* arm_reg_parse () := if it looks like a register, return its token and
5539 advance the pointer. */
5540
5541 static int
5542 arm_reg_parse (ccp)
5543 register char ** ccp;
5544 {
5545 char * start = * ccp;
5546 char c;
5547 char * p;
5548 struct reg_entry * reg;
5549
5550 #ifdef REGISTER_PREFIX
5551 if (*start != REGISTER_PREFIX)
5552 return FAIL;
5553 p = start + 1;
5554 #else
5555 p = start;
5556 #ifdef OPTIONAL_REGISTER_PREFIX
5557 if (*p == OPTIONAL_REGISTER_PREFIX)
5558 p++, start++;
5559 #endif
5560 #endif
5561 if (!isalpha (*p) || !is_name_beginner (*p))
5562 return FAIL;
5563
5564 c = *p++;
5565 while (isalpha (c) || isdigit (c) || c == '_')
5566 c = *p++;
5567
5568 *--p = 0;
5569 reg = (struct reg_entry *) hash_find (arm_reg_hsh, start);
5570 *p = c;
5571
5572 if (reg)
5573 {
5574 *ccp = p;
5575 return reg->number;
5576 }
5577
5578 return FAIL;
5579 }
5580
5581 int
5582 md_apply_fix3 (fixP, val, seg)
5583 fixS * fixP;
5584 valueT * val;
5585 segT seg;
5586 {
5587 offsetT value = * val;
5588 offsetT newval;
5589 unsigned int newimm;
5590 unsigned long temp;
5591 int sign;
5592 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
5593 arm_fix_data * arm_data = (arm_fix_data *) fixP->tc_fix_data;
5594
5595 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
5596
5597 /* Note whether this will delete the relocation. */
5598 #if 0
5599 /* Patch from REarnshaw to JDavis (disabled for the moment, since it
5600 doesn't work fully.) */
5601 if ((fixP->fx_addsy == 0 || symbol_constant_p (fixP->fx_addsy))
5602 && !fixP->fx_pcrel)
5603 #else
5604 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
5605 #endif
5606 fixP->fx_done = 1;
5607
5608 /* If this symbol is in a different section then we need to leave it for
5609 the linker to deal with. Unfortunately, md_pcrel_from can't tell,
5610 so we have to undo it's effects here. */
5611 if (fixP->fx_pcrel)
5612 {
5613 if (fixP->fx_addsy != NULL
5614 && S_IS_DEFINED (fixP->fx_addsy)
5615 && S_GET_SEGMENT (fixP->fx_addsy) != seg)
5616 {
5617 if (target_oabi
5618 && (fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
5619 || fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
5620 ))
5621 value = 0;
5622 else
5623 value += md_pcrel_from (fixP);
5624 }
5625 }
5626
5627 /* Remember value for emit_reloc. */
5628 fixP->fx_addnumber = value;
5629
5630 switch (fixP->fx_r_type)
5631 {
5632 case BFD_RELOC_ARM_IMMEDIATE:
5633 newimm = validate_immediate (value);
5634 temp = md_chars_to_number (buf, INSN_SIZE);
5635
5636 /* If the instruction will fail, see if we can fix things up by
5637 changing the opcode. */
5638 if (newimm == (unsigned int) FAIL
5639 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
5640 {
5641 as_bad_where (fixP->fx_file, fixP->fx_line,
5642 _("invalid constant (%lx) after fixup"),
5643 (unsigned long) value);
5644 break;
5645 }
5646
5647 newimm |= (temp & 0xfffff000);
5648 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
5649 break;
5650
5651 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
5652 {
5653 unsigned int highpart = 0;
5654 unsigned int newinsn = 0xe1a00000; /* nop. */
5655 newimm = validate_immediate (value);
5656 temp = md_chars_to_number (buf, INSN_SIZE);
5657
5658 /* If the instruction will fail, see if we can fix things up by
5659 changing the opcode. */
5660 if (newimm == (unsigned int) FAIL
5661 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
5662 {
5663 /* No ? OK - try using two ADD instructions to generate
5664 the value. */
5665 newimm = validate_immediate_twopart (value, & highpart);
5666
5667 /* Yes - then make sure that the second instruction is
5668 also an add. */
5669 if (newimm != (unsigned int) FAIL)
5670 newinsn = temp;
5671 /* Still No ? Try using a negated value. */
5672 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
5673 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
5674 /* Otherwise - give up. */
5675 else
5676 {
5677 as_bad_where (fixP->fx_file, fixP->fx_line,
5678 _("Unable to compute ADRL instructions for PC offset of 0x%x"),
5679 value);
5680 break;
5681 }
5682
5683 /* Replace the first operand in the 2nd instruction (which
5684 is the PC) with the destination register. We have
5685 already added in the PC in the first instruction and we
5686 do not want to do it again. */
5687 newinsn &= ~ 0xf0000;
5688 newinsn |= ((newinsn & 0x0f000) << 4);
5689 }
5690
5691 newimm |= (temp & 0xfffff000);
5692 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
5693
5694 highpart |= (newinsn & 0xfffff000);
5695 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
5696 }
5697 break;
5698
5699 case BFD_RELOC_ARM_OFFSET_IMM:
5700 sign = value >= 0;
5701
5702 if (value < 0)
5703 value = - value;
5704
5705 if (validate_offset_imm (value, 0) == FAIL)
5706 {
5707 as_bad_where (fixP->fx_file, fixP->fx_line,
5708 _("bad immediate value for offset (%ld)"),
5709 (long) value);
5710 break;
5711 }
5712
5713 newval = md_chars_to_number (buf, INSN_SIZE);
5714 newval &= 0xff7ff000;
5715 newval |= value | (sign ? INDEX_UP : 0);
5716 md_number_to_chars (buf, newval, INSN_SIZE);
5717 break;
5718
5719 case BFD_RELOC_ARM_OFFSET_IMM8:
5720 case BFD_RELOC_ARM_HWLITERAL:
5721 sign = value >= 0;
5722
5723 if (value < 0)
5724 value = - value;
5725
5726 if (validate_offset_imm (value, 1) == FAIL)
5727 {
5728 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
5729 as_bad_where (fixP->fx_file, fixP->fx_line,
5730 _("invalid literal constant: pool needs to be closer"));
5731 else
5732 as_bad (_("bad immediate value for half-word offset (%ld)"),
5733 (long) value);
5734 break;
5735 }
5736
5737 newval = md_chars_to_number (buf, INSN_SIZE);
5738 newval &= 0xff7ff0f0;
5739 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
5740 md_number_to_chars (buf, newval, INSN_SIZE);
5741 break;
5742
5743 case BFD_RELOC_ARM_LITERAL:
5744 sign = value >= 0;
5745
5746 if (value < 0)
5747 value = - value;
5748
5749 if (validate_offset_imm (value, 0) == FAIL)
5750 {
5751 as_bad_where (fixP->fx_file, fixP->fx_line,
5752 _("invalid literal constant: pool needs to be closer"));
5753 break;
5754 }
5755
5756 newval = md_chars_to_number (buf, INSN_SIZE);
5757 newval &= 0xff7ff000;
5758 newval |= value | (sign ? INDEX_UP : 0);
5759 md_number_to_chars (buf, newval, INSN_SIZE);
5760 break;
5761
5762 case BFD_RELOC_ARM_SHIFT_IMM:
5763 newval = md_chars_to_number (buf, INSN_SIZE);
5764 if (((unsigned long) value) > 32
5765 || (value == 32
5766 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
5767 {
5768 as_bad_where (fixP->fx_file, fixP->fx_line,
5769 _("shift expression is too large"));
5770 break;
5771 }
5772
5773 if (value == 0)
5774 /* Shifts of zero must be done as lsl. */
5775 newval &= ~0x60;
5776 else if (value == 32)
5777 value = 0;
5778 newval &= 0xfffff07f;
5779 newval |= (value & 0x1f) << 7;
5780 md_number_to_chars (buf, newval, INSN_SIZE);
5781 break;
5782
5783 case BFD_RELOC_ARM_SWI:
5784 if (arm_data->thumb_mode)
5785 {
5786 if (((unsigned long) value) > 0xff)
5787 as_bad_where (fixP->fx_file, fixP->fx_line,
5788 _("Invalid swi expression"));
5789 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xff00;
5790 newval |= value;
5791 md_number_to_chars (buf, newval, THUMB_SIZE);
5792 }
5793 else
5794 {
5795 if (((unsigned long) value) > 0x00ffffff)
5796 as_bad_where (fixP->fx_file, fixP->fx_line,
5797 _("Invalid swi expression"));
5798 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff000000;
5799 newval |= value;
5800 md_number_to_chars (buf, newval, INSN_SIZE);
5801 }
5802 break;
5803
5804 case BFD_RELOC_ARM_MULTI:
5805 if (((unsigned long) value) > 0xffff)
5806 as_bad_where (fixP->fx_file, fixP->fx_line,
5807 _("Invalid expression in load/store multiple"));
5808 newval = value | md_chars_to_number (buf, INSN_SIZE);
5809 md_number_to_chars (buf, newval, INSN_SIZE);
5810 break;
5811
5812 case BFD_RELOC_ARM_PCREL_BRANCH:
5813 newval = md_chars_to_number (buf, INSN_SIZE);
5814
5815 /* Sign-extend a 24-bit number. */
5816 #define SEXT24(x) ((((x) & 0xffffff) ^ (~ 0x7fffff)) + 0x800000)
5817
5818 #ifdef OBJ_ELF
5819 if (! target_oabi)
5820 value = fixP->fx_offset;
5821 #endif
5822
5823 /* We are going to store value (shifted right by two) in the
5824 instruction, in a 24 bit, signed field. Thus we need to check
5825 that none of the top 8 bits of the shifted value (top 7 bits of
5826 the unshifted, unsigned value) are set, or that they are all set. */
5827 if ((value & ~ ((offsetT) 0x1ffffff)) != 0
5828 && ((value & ~ ((offsetT) 0x1ffffff)) != ~ ((offsetT) 0x1ffffff)))
5829 {
5830 #ifdef OBJ_ELF
5831 /* Normally we would be stuck at this point, since we cannot store
5832 the absolute address that is the destination of the branch in the
5833 24 bits of the branch instruction. If however, we happen to know
5834 that the destination of the branch is in the same section as the
5835 branch instruciton itself, then we can compute the relocation for
5836 ourselves and not have to bother the linker with it.
5837
5838 FIXME: The tests for OBJ_ELF and ! target_oabi are only here
5839 because I have not worked out how to do this for OBJ_COFF or
5840 target_oabi. */
5841 if (! target_oabi
5842 && fixP->fx_addsy != NULL
5843 && S_IS_DEFINED (fixP->fx_addsy)
5844 && S_GET_SEGMENT (fixP->fx_addsy) == seg)
5845 {
5846 /* Get pc relative value to go into the branch. */
5847 value = * val;
5848
5849 /* Permit a backward branch provided that enough bits
5850 are set. Allow a forwards branch, provided that
5851 enough bits are clear. */
5852 if ( (value & ~ ((offsetT) 0x1ffffff)) == ~ ((offsetT) 0x1ffffff)
5853 || (value & ~ ((offsetT) 0x1ffffff)) == 0)
5854 fixP->fx_done = 1;
5855 }
5856
5857 if (! fixP->fx_done)
5858 #endif
5859 as_bad_where (fixP->fx_file, fixP->fx_line,
5860 _("gas can't handle same-section branch dest >= 0x04000000"));
5861 }
5862
5863 value >>= 2;
5864 value += SEXT24 (newval);
5865
5866 if ( (value & ~ ((offsetT) 0xffffff)) != 0
5867 && ((value & ~ ((offsetT) 0xffffff)) != ~ ((offsetT) 0xffffff)))
5868 as_bad_where (fixP->fx_file, fixP->fx_line,
5869 _("out of range branch"));
5870
5871 newval = (value & 0x00ffffff) | (newval & 0xff000000);
5872 md_number_to_chars (buf, newval, INSN_SIZE);
5873 break;
5874
5875 case BFD_RELOC_ARM_PCREL_BLX:
5876 {
5877 offsetT hbit;
5878 newval = md_chars_to_number (buf, INSN_SIZE);
5879
5880 #ifdef OBJ_ELF
5881 if (! target_oabi)
5882 value = fixP->fx_offset;
5883 #endif
5884 hbit = (value >> 1) & 1;
5885 value = (value >> 2) & 0x00ffffff;
5886 value = (value + (newval & 0x00ffffff)) & 0x00ffffff;
5887 newval = value | (newval & 0xfe000000) | (hbit << 24);
5888 md_number_to_chars (buf, newval, INSN_SIZE);
5889 }
5890 break;
5891
5892 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
5893 newval = md_chars_to_number (buf, THUMB_SIZE);
5894 {
5895 addressT diff = (newval & 0xff) << 1;
5896 if (diff & 0x100)
5897 diff |= ~0xff;
5898
5899 value += diff;
5900 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
5901 as_bad_where (fixP->fx_file, fixP->fx_line,
5902 _("Branch out of range"));
5903 newval = (newval & 0xff00) | ((value & 0x1ff) >> 1);
5904 }
5905 md_number_to_chars (buf, newval, THUMB_SIZE);
5906 break;
5907
5908 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
5909 newval = md_chars_to_number (buf, THUMB_SIZE);
5910 {
5911 addressT diff = (newval & 0x7ff) << 1;
5912 if (diff & 0x800)
5913 diff |= ~0x7ff;
5914
5915 value += diff;
5916 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
5917 as_bad_where (fixP->fx_file, fixP->fx_line,
5918 _("Branch out of range"));
5919 newval = (newval & 0xf800) | ((value & 0xfff) >> 1);
5920 }
5921 md_number_to_chars (buf, newval, THUMB_SIZE);
5922 break;
5923
5924 case BFD_RELOC_THUMB_PCREL_BLX:
5925 case BFD_RELOC_THUMB_PCREL_BRANCH23:
5926 {
5927 offsetT newval2;
5928 addressT diff;
5929
5930 newval = md_chars_to_number (buf, THUMB_SIZE);
5931 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
5932 diff = ((newval & 0x7ff) << 12) | ((newval2 & 0x7ff) << 1);
5933 if (diff & 0x400000)
5934 diff |= ~0x3fffff;
5935 #ifdef OBJ_ELF
5936 value = fixP->fx_offset;
5937 #endif
5938 value += diff;
5939 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
5940 as_bad_where (fixP->fx_file, fixP->fx_line,
5941 _("Branch with link out of range"));
5942
5943 newval = (newval & 0xf800) | ((value & 0x7fffff) >> 12);
5944 newval2 = (newval2 & 0xf800) | ((value & 0xfff) >> 1);
5945 md_number_to_chars (buf, newval, THUMB_SIZE);
5946 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
5947 }
5948 break;
5949
5950 case BFD_RELOC_8:
5951 if (fixP->fx_done || fixP->fx_pcrel)
5952 md_number_to_chars (buf, value, 1);
5953 #ifdef OBJ_ELF
5954 else if (!target_oabi)
5955 {
5956 value = fixP->fx_offset;
5957 md_number_to_chars (buf, value, 1);
5958 }
5959 #endif
5960 break;
5961
5962 case BFD_RELOC_16:
5963 if (fixP->fx_done || fixP->fx_pcrel)
5964 md_number_to_chars (buf, value, 2);
5965 #ifdef OBJ_ELF
5966 else if (!target_oabi)
5967 {
5968 value = fixP->fx_offset;
5969 md_number_to_chars (buf, value, 2);
5970 }
5971 #endif
5972 break;
5973
5974 #ifdef OBJ_ELF
5975 case BFD_RELOC_ARM_GOT32:
5976 case BFD_RELOC_ARM_GOTOFF:
5977 md_number_to_chars (buf, 0, 4);
5978 break;
5979 #endif
5980
5981 case BFD_RELOC_RVA:
5982 case BFD_RELOC_32:
5983 if (fixP->fx_done || fixP->fx_pcrel)
5984 md_number_to_chars (buf, value, 4);
5985 #ifdef OBJ_ELF
5986 else if (!target_oabi)
5987 {
5988 value = fixP->fx_offset;
5989 md_number_to_chars (buf, value, 4);
5990 }
5991 #endif
5992 break;
5993
5994 #ifdef OBJ_ELF
5995 case BFD_RELOC_ARM_PLT32:
5996 /* It appears the instruction is fully prepared at this point. */
5997 break;
5998 #endif
5999
6000 case BFD_RELOC_ARM_GOTPC:
6001 md_number_to_chars (buf, value, 4);
6002 break;
6003
6004 case BFD_RELOC_ARM_CP_OFF_IMM:
6005 sign = value >= 0;
6006 if (value < -1023 || value > 1023 || (value & 3))
6007 as_bad_where (fixP->fx_file, fixP->fx_line,
6008 _("Illegal value for co-processor offset"));
6009 if (value < 0)
6010 value = -value;
6011 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
6012 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
6013 md_number_to_chars (buf, newval, INSN_SIZE);
6014 break;
6015
6016 case BFD_RELOC_ARM_THUMB_OFFSET:
6017 newval = md_chars_to_number (buf, THUMB_SIZE);
6018 /* Exactly what ranges, and where the offset is inserted depends
6019 on the type of instruction, we can establish this from the
6020 top 4 bits. */
6021 switch (newval >> 12)
6022 {
6023 case 4: /* PC load. */
6024 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
6025 forced to zero for these loads, so we will need to round
6026 up the offset if the instruction address is not word
6027 aligned (since the final address produced must be, and
6028 we can only describe word-aligned immediate offsets). */
6029
6030 if ((fixP->fx_frag->fr_address + fixP->fx_where + value) & 3)
6031 as_bad_where (fixP->fx_file, fixP->fx_line,
6032 _("Invalid offset, target not word aligned (0x%08X)"),
6033 (unsigned int) (fixP->fx_frag->fr_address
6034 + fixP->fx_where + value));
6035
6036 if ((value + 2) & ~0x3fe)
6037 as_bad_where (fixP->fx_file, fixP->fx_line,
6038 _("Invalid offset, value too big (0x%08X)"), value);
6039
6040 /* Round up, since pc will be rounded down. */
6041 newval |= (value + 2) >> 2;
6042 break;
6043
6044 case 9: /* SP load/store. */
6045 if (value & ~0x3fc)
6046 as_bad_where (fixP->fx_file, fixP->fx_line,
6047 _("Invalid offset, value too big (0x%08X)"), value);
6048 newval |= value >> 2;
6049 break;
6050
6051 case 6: /* Word load/store. */
6052 if (value & ~0x7c)
6053 as_bad_where (fixP->fx_file, fixP->fx_line,
6054 _("Invalid offset, value too big (0x%08X)"), value);
6055 newval |= value << 4; /* 6 - 2. */
6056 break;
6057
6058 case 7: /* Byte load/store. */
6059 if (value & ~0x1f)
6060 as_bad_where (fixP->fx_file, fixP->fx_line,
6061 _("Invalid offset, value too big (0x%08X)"), value);
6062 newval |= value << 6;
6063 break;
6064
6065 case 8: /* Halfword load/store. */
6066 if (value & ~0x3e)
6067 as_bad_where (fixP->fx_file, fixP->fx_line,
6068 _("Invalid offset, value too big (0x%08X)"), value);
6069 newval |= value << 5; /* 6 - 1. */
6070 break;
6071
6072 default:
6073 as_bad_where (fixP->fx_file, fixP->fx_line,
6074 "Unable to process relocation for thumb opcode: %lx",
6075 (unsigned long) newval);
6076 break;
6077 }
6078 md_number_to_chars (buf, newval, THUMB_SIZE);
6079 break;
6080
6081 case BFD_RELOC_ARM_THUMB_ADD:
6082 /* This is a complicated relocation, since we use it for all of
6083 the following immediate relocations:
6084
6085 3bit ADD/SUB
6086 8bit ADD/SUB
6087 9bit ADD/SUB SP word-aligned
6088 10bit ADD PC/SP word-aligned
6089
6090 The type of instruction being processed is encoded in the
6091 instruction field:
6092
6093 0x8000 SUB
6094 0x00F0 Rd
6095 0x000F Rs
6096 */
6097 newval = md_chars_to_number (buf, THUMB_SIZE);
6098 {
6099 int rd = (newval >> 4) & 0xf;
6100 int rs = newval & 0xf;
6101 int subtract = newval & 0x8000;
6102
6103 if (rd == REG_SP)
6104 {
6105 if (value & ~0x1fc)
6106 as_bad_where (fixP->fx_file, fixP->fx_line,
6107 _("Invalid immediate for stack address calculation"));
6108 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
6109 newval |= value >> 2;
6110 }
6111 else if (rs == REG_PC || rs == REG_SP)
6112 {
6113 if (subtract ||
6114 value & ~0x3fc)
6115 as_bad_where (fixP->fx_file, fixP->fx_line,
6116 _("Invalid immediate for address calculation (value = 0x%08lX)"),
6117 (unsigned long) value);
6118 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
6119 newval |= rd << 8;
6120 newval |= value >> 2;
6121 }
6122 else if (rs == rd)
6123 {
6124 if (value & ~0xff)
6125 as_bad_where (fixP->fx_file, fixP->fx_line,
6126 _("Invalid 8bit immediate"));
6127 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
6128 newval |= (rd << 8) | value;
6129 }
6130 else
6131 {
6132 if (value & ~0x7)
6133 as_bad_where (fixP->fx_file, fixP->fx_line,
6134 _("Invalid 3bit immediate"));
6135 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
6136 newval |= rd | (rs << 3) | (value << 6);
6137 }
6138 }
6139 md_number_to_chars (buf, newval, THUMB_SIZE);
6140 break;
6141
6142 case BFD_RELOC_ARM_THUMB_IMM:
6143 newval = md_chars_to_number (buf, THUMB_SIZE);
6144 switch (newval >> 11)
6145 {
6146 case 0x04: /* 8bit immediate MOV. */
6147 case 0x05: /* 8bit immediate CMP. */
6148 if (value < 0 || value > 255)
6149 as_bad_where (fixP->fx_file, fixP->fx_line,
6150 _("Invalid immediate: %ld is too large"),
6151 (long) value);
6152 newval |= value;
6153 break;
6154
6155 default:
6156 abort ();
6157 }
6158 md_number_to_chars (buf, newval, THUMB_SIZE);
6159 break;
6160
6161 case BFD_RELOC_ARM_THUMB_SHIFT:
6162 /* 5bit shift value (0..31). */
6163 if (value < 0 || value > 31)
6164 as_bad_where (fixP->fx_file, fixP->fx_line,
6165 _("Illegal Thumb shift value: %ld"), (long) value);
6166 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf03f;
6167 newval |= value << 6;
6168 md_number_to_chars (buf, newval, THUMB_SIZE);
6169 break;
6170
6171 case BFD_RELOC_VTABLE_INHERIT:
6172 case BFD_RELOC_VTABLE_ENTRY:
6173 fixP->fx_done = 0;
6174 return 1;
6175
6176 case BFD_RELOC_NONE:
6177 default:
6178 as_bad_where (fixP->fx_file, fixP->fx_line,
6179 _("Bad relocation fixup type (%d)"), fixP->fx_r_type);
6180 }
6181
6182 return 1;
6183 }
6184
6185 /* Translate internal representation of relocation info to BFD target
6186 format. */
6187
6188 arelent *
6189 tc_gen_reloc (section, fixp)
6190 asection * section ATTRIBUTE_UNUSED;
6191 fixS * fixp;
6192 {
6193 arelent * reloc;
6194 bfd_reloc_code_real_type code;
6195
6196 reloc = (arelent *) xmalloc (sizeof (arelent));
6197
6198 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6199 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
6200 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
6201
6202 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
6203 #ifndef OBJ_ELF
6204 if (fixp->fx_pcrel == 0)
6205 reloc->addend = fixp->fx_offset;
6206 else
6207 reloc->addend = fixp->fx_offset = reloc->address;
6208 #else /* OBJ_ELF */
6209 reloc->addend = fixp->fx_offset;
6210 #endif
6211
6212 switch (fixp->fx_r_type)
6213 {
6214 case BFD_RELOC_8:
6215 if (fixp->fx_pcrel)
6216 {
6217 code = BFD_RELOC_8_PCREL;
6218 break;
6219 }
6220
6221 case BFD_RELOC_16:
6222 if (fixp->fx_pcrel)
6223 {
6224 code = BFD_RELOC_16_PCREL;
6225 break;
6226 }
6227
6228 case BFD_RELOC_32:
6229 if (fixp->fx_pcrel)
6230 {
6231 code = BFD_RELOC_32_PCREL;
6232 break;
6233 }
6234
6235 case BFD_RELOC_ARM_PCREL_BRANCH:
6236 case BFD_RELOC_ARM_PCREL_BLX:
6237 case BFD_RELOC_RVA:
6238 case BFD_RELOC_THUMB_PCREL_BRANCH9:
6239 case BFD_RELOC_THUMB_PCREL_BRANCH12:
6240 case BFD_RELOC_THUMB_PCREL_BRANCH23:
6241 case BFD_RELOC_THUMB_PCREL_BLX:
6242 case BFD_RELOC_VTABLE_ENTRY:
6243 case BFD_RELOC_VTABLE_INHERIT:
6244 code = fixp->fx_r_type;
6245 break;
6246
6247 case BFD_RELOC_ARM_LITERAL:
6248 case BFD_RELOC_ARM_HWLITERAL:
6249 /* If this is called then the a literal has been referenced across
6250 a section boundary - possibly due to an implicit dump. */
6251 as_bad_where (fixp->fx_file, fixp->fx_line,
6252 _("Literal referenced across section boundary (Implicit dump?)"));
6253 return NULL;
6254
6255 #ifdef OBJ_ELF
6256 case BFD_RELOC_ARM_GOT32:
6257 case BFD_RELOC_ARM_GOTOFF:
6258 case BFD_RELOC_ARM_PLT32:
6259 code = fixp->fx_r_type;
6260 break;
6261 #endif
6262
6263 case BFD_RELOC_ARM_IMMEDIATE:
6264 as_bad_where (fixp->fx_file, fixp->fx_line,
6265 _("Internal_relocation (type %d) not fixed up (IMMEDIATE)"),
6266 fixp->fx_r_type);
6267 return NULL;
6268
6269 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
6270 as_bad_where (fixp->fx_file, fixp->fx_line,
6271 _("ADRL used for a symbol not defined in the same file"),
6272 fixp->fx_r_type);
6273 return NULL;
6274
6275 case BFD_RELOC_ARM_OFFSET_IMM:
6276 as_bad_where (fixp->fx_file, fixp->fx_line,
6277 _("Internal_relocation (type %d) not fixed up (OFFSET_IMM)"),
6278 fixp->fx_r_type);
6279 return NULL;
6280
6281 default:
6282 {
6283 char * type;
6284
6285 switch (fixp->fx_r_type)
6286 {
6287 case BFD_RELOC_ARM_IMMEDIATE: type = "IMMEDIATE"; break;
6288 case BFD_RELOC_ARM_OFFSET_IMM: type = "OFFSET_IMM"; break;
6289 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
6290 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
6291 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
6292 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
6293 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
6294 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
6295 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
6296 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
6297 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
6298 default: type = _("<unknown>"); break;
6299 }
6300 as_bad_where (fixp->fx_file, fixp->fx_line,
6301 _("Can not represent %s relocation in this object file format (%d)"),
6302 type, fixp->fx_pcrel);
6303 return NULL;
6304 }
6305 }
6306
6307 #ifdef OBJ_ELF
6308 if (code == BFD_RELOC_32_PCREL
6309 && GOT_symbol
6310 && fixp->fx_addsy == GOT_symbol)
6311 {
6312 code = BFD_RELOC_ARM_GOTPC;
6313 reloc->addend = fixp->fx_offset = reloc->address;
6314 }
6315 #endif
6316
6317 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
6318
6319 if (reloc->howto == NULL)
6320 {
6321 as_bad_where (fixp->fx_file, fixp->fx_line,
6322 _("Can not represent %s relocation in this object file format"),
6323 bfd_get_reloc_code_name (code));
6324 return NULL;
6325 }
6326
6327 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
6328 vtable entry to be used in the relocation's section offset. */
6329 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6330 reloc->address = fixp->fx_offset;
6331
6332 return reloc;
6333 }
6334
6335 int
6336 md_estimate_size_before_relax (fragP, segtype)
6337 fragS * fragP ATTRIBUTE_UNUSED;
6338 segT segtype ATTRIBUTE_UNUSED;
6339 {
6340 as_fatal (_("md_estimate_size_before_relax\n"));
6341 return 1;
6342 }
6343
6344 static void
6345 output_inst PARAMS ((void))
6346 {
6347 char * to = NULL;
6348
6349 if (inst.error)
6350 {
6351 as_bad (inst.error);
6352 return;
6353 }
6354
6355 to = frag_more (inst.size);
6356
6357 if (thumb_mode && (inst.size > THUMB_SIZE))
6358 {
6359 assert (inst.size == (2 * THUMB_SIZE));
6360 md_number_to_chars (to, inst.instruction >> 16, THUMB_SIZE);
6361 md_number_to_chars (to + THUMB_SIZE, inst.instruction, THUMB_SIZE);
6362 }
6363 else if (inst.size > INSN_SIZE)
6364 {
6365 assert (inst.size == (2 * INSN_SIZE));
6366 md_number_to_chars (to, inst.instruction, INSN_SIZE);
6367 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
6368 }
6369 else
6370 md_number_to_chars (to, inst.instruction, inst.size);
6371
6372 if (inst.reloc.type != BFD_RELOC_NONE)
6373 fix_new_arm (frag_now, to - frag_now->fr_literal,
6374 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
6375 inst.reloc.type);
6376 #ifdef OBJ_ELF
6377 if (debug_type == DEBUG_DWARF2)
6378 dwarf2_generate_asm_lineno (inst.size);
6379 #endif
6380 return;
6381 }
6382
6383 void
6384 md_assemble (str)
6385 char * str;
6386 {
6387 char c;
6388 char * p;
6389 char * q;
6390 char * start;
6391
6392 /* Align the instruction.
6393 This may not be the right thing to do but ... */
6394 #if 0
6395 arm_align (2, 0);
6396 #endif
6397 listing_prev_line (); /* Defined in listing.h. */
6398
6399 /* Align the previous label if needed. */
6400 if (last_label_seen != NULL)
6401 {
6402 symbol_set_frag (last_label_seen, frag_now);
6403 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
6404 S_SET_SEGMENT (last_label_seen, now_seg);
6405 }
6406
6407 memset (&inst, '\0', sizeof (inst));
6408 inst.reloc.type = BFD_RELOC_NONE;
6409
6410 skip_whitespace (str);
6411
6412 /* Scan up to the end of the op-code, which must end in white space or
6413 end of string. */
6414 for (start = p = str; *p != '\0'; p++)
6415 if (*p == ' ')
6416 break;
6417
6418 if (p == str)
6419 {
6420 as_bad (_("No operator -- statement `%s'\n"), str);
6421 return;
6422 }
6423
6424 if (thumb_mode)
6425 {
6426 CONST struct thumb_opcode * opcode;
6427
6428 c = *p;
6429 *p = '\0';
6430 opcode = (CONST struct thumb_opcode *) hash_find (arm_tops_hsh, str);
6431 *p = c;
6432
6433 if (opcode)
6434 {
6435 /* Check that this instruction is supported for this CPU. */
6436 if (thumb_mode == 1 && (opcode->variants & cpu_variant) == 0)
6437 {
6438 as_bad (_("selected processor does not support this opcode"));
6439 return;
6440 }
6441
6442 inst.instruction = opcode->value;
6443 inst.size = opcode->size;
6444 (*opcode->parms) (p);
6445 output_inst ();
6446 return;
6447 }
6448 }
6449 else
6450 {
6451 CONST struct asm_opcode * opcode;
6452 unsigned long cond_code;
6453
6454 inst.size = INSN_SIZE;
6455 /* P now points to the end of the opcode, probably white space, but we
6456 have to break the opcode up in case it contains condionals and flags;
6457 keep trying with progressively smaller basic instructions until one
6458 matches, or we run out of opcode. */
6459 q = (p - str > LONGEST_INST) ? str + LONGEST_INST : p;
6460
6461 for (; q != str; q--)
6462 {
6463 c = *q;
6464 *q = '\0';
6465
6466 opcode = (CONST struct asm_opcode *) hash_find (arm_ops_hsh, str);
6467 *q = c;
6468
6469 if (opcode && opcode->template)
6470 {
6471 unsigned long flag_bits = 0;
6472 char * r;
6473
6474 /* Check that this instruction is supported for this CPU. */
6475 if ((opcode->variants & cpu_variant) == 0)
6476 goto try_shorter;
6477
6478 inst.instruction = opcode->value;
6479 if (q == p) /* Just a simple opcode. */
6480 {
6481 if (opcode->comp_suffix)
6482 {
6483 if (*opcode->comp_suffix != '\0')
6484 as_bad (_("Opcode `%s' must have suffix from list: <%s>"),
6485 str, opcode->comp_suffix);
6486 else
6487 /* Not a conditional instruction. */
6488 (*opcode->parms) (q, 0);
6489 }
6490 else
6491 {
6492 /* A conditional instruction with default condition. */
6493 inst.instruction |= COND_ALWAYS;
6494 (*opcode->parms) (q, 0);
6495 }
6496 output_inst ();
6497 return;
6498 }
6499
6500 /* Not just a simple opcode. Check if extra is a
6501 conditional. */
6502 r = q;
6503 if (p - r >= 2)
6504 {
6505 CONST struct asm_cond *cond;
6506 char d = *(r + 2);
6507
6508 *(r + 2) = '\0';
6509 cond = (CONST struct asm_cond *) hash_find (arm_cond_hsh, r);
6510 *(r + 2) = d;
6511 if (cond)
6512 {
6513 if (cond->value == 0xf0000000)
6514 as_tsktsk (
6515 _("Warning: Use of the 'nv' conditional is deprecated\n"));
6516
6517 cond_code = cond->value;
6518 r += 2;
6519 }
6520 else
6521 cond_code = COND_ALWAYS;
6522 }
6523 else
6524 cond_code = COND_ALWAYS;
6525
6526 /* Apply the conditional, or complain it's not allowed. */
6527 if (opcode->comp_suffix && *opcode->comp_suffix == '\0')
6528 {
6529 /* Instruction isn't conditional. */
6530 if (cond_code != COND_ALWAYS)
6531 {
6532 as_bad (_("Opcode `%s' is unconditional\n"), str);
6533 return;
6534 }
6535 }
6536 else
6537 /* Instruction is conditional: set the condition into it. */
6538 inst.instruction |= cond_code;
6539
6540 /* If there is a compulsory suffix, it should come here
6541 before any optional flags. */
6542 if (opcode->comp_suffix && *opcode->comp_suffix != '\0')
6543 {
6544 CONST char *s = opcode->comp_suffix;
6545
6546 while (*s)
6547 {
6548 inst.suffix++;
6549 if (*r == *s)
6550 break;
6551 s++;
6552 }
6553
6554 if (*s == '\0')
6555 {
6556 as_bad (_("Opcode `%s' must have suffix from <%s>\n"),
6557 str, opcode->comp_suffix);
6558 return;
6559 }
6560
6561 r++;
6562 }
6563
6564 /* The remainder, if any should now be flags for the instruction;
6565 Scan these checking each one found with the opcode. */
6566 if (r != p)
6567 {
6568 char d;
6569 CONST struct asm_flg *flag = opcode->flags;
6570
6571 if (flag)
6572 {
6573 int flagno;
6574
6575 d = *p;
6576 *p = '\0';
6577
6578 for (flagno = 0; flag[flagno].template; flagno++)
6579 {
6580 if (streq (r, flag[flagno].template))
6581 {
6582 flag_bits |= flag[flagno].set_bits;
6583 break;
6584 }
6585 }
6586
6587 *p = d;
6588 if (! flag[flagno].template)
6589 goto try_shorter;
6590 }
6591 else
6592 goto try_shorter;
6593 }
6594
6595 (*opcode->parms) (p, flag_bits);
6596 output_inst ();
6597 return;
6598 }
6599
6600 try_shorter:
6601 ;
6602 }
6603 }
6604
6605 /* It wasn't an instruction, but it might be a register alias of the form
6606 alias .req reg. */
6607 q = p;
6608 skip_whitespace (q);
6609
6610 c = *p;
6611 *p = '\0';
6612
6613 if (*q && !strncmp (q, ".req ", 4))
6614 {
6615 int reg;
6616 char * copy_of_str;
6617 char * r;
6618
6619 #ifdef IGNORE_OPCODE_CASE
6620 str = original_case_string;
6621 #endif
6622 copy_of_str = str;
6623
6624 q += 4;
6625 skip_whitespace (q);
6626
6627 for (r = q; *r != '\0'; r++)
6628 if (*r == ' ')
6629 break;
6630
6631 if (r != q)
6632 {
6633 int regnum;
6634 char d = *r;
6635
6636 *r = '\0';
6637 regnum = arm_reg_parse (& q);
6638 *r = d;
6639
6640 reg = arm_reg_parse (& str);
6641
6642 if (reg == FAIL)
6643 {
6644 if (regnum != FAIL)
6645 insert_reg_alias (str, regnum);
6646 else
6647 as_warn (_("register '%s' does not exist\n"), q);
6648 }
6649 else if (regnum != FAIL)
6650 {
6651 if (reg != regnum)
6652 as_warn (_("ignoring redefinition of register alias '%s'"),
6653 copy_of_str);
6654
6655 /* Do not warn about redefinitions to the same alias. */
6656 }
6657 else
6658 as_warn (_("ignoring redefinition of register alias '%s' to non-existant register '%s'"),
6659 copy_of_str, q);
6660 }
6661 else
6662 as_warn (_("ignoring incomplete .req pseuso op"));
6663
6664 *p = c;
6665 return;
6666 }
6667
6668 *p = c;
6669 as_bad (_("bad instruction `%s'"), start);
6670 }
6671
6672 /* md_parse_option
6673 Invocation line includes a switch not recognized by the base assembler.
6674 See if it's a processor-specific option. These are:
6675 Cpu variants, the arm part is optional:
6676 -m[arm]1 Currently not supported.
6677 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
6678 -m[arm]3 Arm 3 processor
6679 -m[arm]6[xx], Arm 6 processors
6680 -m[arm]7[xx][t][[d]m] Arm 7 processors
6681 -m[arm]8[10] Arm 8 processors
6682 -m[arm]9[20][tdmi] Arm 9 processors
6683 -mstrongarm[110[0]] StrongARM processors
6684 -m[arm]v[2345[t]] Arm architectures
6685 -mall All (except the ARM1)
6686 FP variants:
6687 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
6688 -mfpe-old (No float load/store multiples)
6689 -mno-fpu Disable all floating point instructions
6690 Run-time endian selection:
6691 -EB big endian cpu
6692 -EL little endian cpu
6693 ARM Procedure Calling Standard:
6694 -mapcs-32 32 bit APCS
6695 -mapcs-26 26 bit APCS
6696 -mapcs-float Pass floats in float regs
6697 -mapcs-reentrant Position independent code
6698 -mthumb-interwork Code supports Arm/Thumb interworking
6699 -moabi Old ELF ABI */
6700
6701 CONST char * md_shortopts = "m:k";
6702
6703 struct option md_longopts[] =
6704 {
6705 #ifdef ARM_BI_ENDIAN
6706 #define OPTION_EB (OPTION_MD_BASE + 0)
6707 {"EB", no_argument, NULL, OPTION_EB},
6708 #define OPTION_EL (OPTION_MD_BASE + 1)
6709 {"EL", no_argument, NULL, OPTION_EL},
6710 #ifdef OBJ_ELF
6711 #define OPTION_OABI (OPTION_MD_BASE +2)
6712 {"oabi", no_argument, NULL, OPTION_OABI},
6713 #endif
6714 #endif
6715 {NULL, no_argument, NULL, 0}
6716 };
6717
6718 size_t md_longopts_size = sizeof (md_longopts);
6719
6720 int
6721 md_parse_option (c, arg)
6722 int c;
6723 char * arg;
6724 {
6725 char * str = arg;
6726
6727 switch (c)
6728 {
6729 #ifdef ARM_BI_ENDIAN
6730 case OPTION_EB:
6731 target_big_endian = 1;
6732 break;
6733 case OPTION_EL:
6734 target_big_endian = 0;
6735 break;
6736 #endif
6737
6738 case 'm':
6739 switch (*str)
6740 {
6741 case 'f':
6742 if (streq (str, "fpa10"))
6743 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA10;
6744 else if (streq (str, "fpa11"))
6745 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA11;
6746 else if (streq (str, "fpe-old"))
6747 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_CORE;
6748 else
6749 goto bad;
6750 break;
6751
6752 case 'n':
6753 if (streq (str, "no-fpu"))
6754 cpu_variant &= ~FPU_ALL;
6755 break;
6756
6757 #ifdef OBJ_ELF
6758 case 'o':
6759 if (streq (str, "oabi"))
6760 target_oabi = true;
6761 break;
6762 #endif
6763
6764 case 't':
6765 /* Limit assembler to generating only Thumb instructions: */
6766 if (streq (str, "thumb"))
6767 {
6768 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_THUMB;
6769 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_NONE;
6770 thumb_mode = 1;
6771 }
6772 else if (streq (str, "thumb-interwork"))
6773 {
6774 if ((cpu_variant & ARM_THUMB) == 0)
6775 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4T;
6776 #if defined OBJ_COFF || defined OBJ_ELF
6777 support_interwork = true;
6778 #endif
6779 }
6780 else
6781 goto bad;
6782 break;
6783
6784 default:
6785 if (streq (str, "all"))
6786 {
6787 cpu_variant = ARM_ALL | FPU_ALL;
6788 return 1;
6789 }
6790 #if defined OBJ_COFF || defined OBJ_ELF
6791 if (! strncmp (str, "apcs-", 5))
6792 {
6793 /* GCC passes on all command line options starting "-mapcs-..."
6794 to us, so we must parse them here. */
6795
6796 str += 5;
6797
6798 if (streq (str, "32"))
6799 {
6800 uses_apcs_26 = false;
6801 return 1;
6802 }
6803 else if (streq (str, "26"))
6804 {
6805 uses_apcs_26 = true;
6806 return 1;
6807 }
6808 else if (streq (str, "frame"))
6809 {
6810 /* Stack frames are being generated - does not affect
6811 linkage of code. */
6812 return 1;
6813 }
6814 else if (streq (str, "stack-check"))
6815 {
6816 /* Stack checking is being performed - does not affect
6817 linkage, but does require that the functions
6818 __rt_stkovf_split_small and __rt_stkovf_split_big be
6819 present in the final link. */
6820
6821 return 1;
6822 }
6823 else if (streq (str, "float"))
6824 {
6825 /* Floating point arguments are being passed in the floating
6826 point registers. This does affect linking, since this
6827 version of the APCS is incompatible with the version that
6828 passes floating points in the integer registers. */
6829
6830 uses_apcs_float = true;
6831 return 1;
6832 }
6833 else if (streq (str, "reentrant"))
6834 {
6835 /* Reentrant code has been generated. This does affect
6836 linking, since there is no point in linking reentrant/
6837 position independent code with absolute position code. */
6838 pic_code = true;
6839 return 1;
6840 }
6841
6842 as_bad (_("Unrecognised APCS switch -m%s"), arg);
6843 return 0;
6844 }
6845 #endif
6846 /* Strip off optional "arm". */
6847 if (! strncmp (str, "arm", 3))
6848 str += 3;
6849
6850 switch (*str)
6851 {
6852 case '1':
6853 if (streq (str, "1"))
6854 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_1;
6855 else
6856 goto bad;
6857 break;
6858
6859 case '2':
6860 if (streq (str, "2"))
6861 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
6862 else if (streq (str, "250"))
6863 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_250;
6864 else
6865 goto bad;
6866 break;
6867
6868 case '3':
6869 if (streq (str, "3"))
6870 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
6871 else
6872 goto bad;
6873 break;
6874
6875 case '6':
6876 switch (strtol (str, NULL, 10))
6877 {
6878 case 6:
6879 case 60:
6880 case 600:
6881 case 610:
6882 case 620:
6883 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_6;
6884 break;
6885 default:
6886 goto bad;
6887 }
6888 break;
6889
6890 case '7':
6891 /* Eat the processor name. */
6892 switch (strtol (str, & str, 10))
6893 {
6894 case 7:
6895 case 70:
6896 case 700:
6897 case 710:
6898 case 720:
6899 case 7100:
6900 case 7500:
6901 break;
6902 default:
6903 goto bad;
6904 }
6905 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
6906 for (; *str; str++)
6907 {
6908 switch (*str)
6909 {
6910 case 't':
6911 cpu_variant |= (ARM_THUMB | ARM_ARCH_V4);
6912 break;
6913
6914 case 'm':
6915 cpu_variant |= ARM_LONGMUL;
6916 break;
6917
6918 case 'f': /* fe => fp enabled cpu. */
6919 if (str[1] == 'e')
6920 ++ str;
6921 else
6922 goto bad;
6923
6924 case 'c': /* Left over from 710c processor name. */
6925 case 'd': /* Debug. */
6926 case 'i': /* Embedded ICE. */
6927 /* Included for completeness in ARM processor naming. */
6928 break;
6929
6930 default:
6931 goto bad;
6932 }
6933 }
6934 break;
6935
6936 case '8':
6937 if (streq (str, "8") || streq (str, "810"))
6938 cpu_variant = (cpu_variant & ~ARM_ANY)
6939 | ARM_8 | ARM_ARCH_V4 | ARM_LONGMUL;
6940 else
6941 goto bad;
6942 break;
6943
6944 case '9':
6945 if (streq (str, "9"))
6946 cpu_variant = (cpu_variant & ~ARM_ANY)
6947 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6948 else if (streq (str, "920"))
6949 cpu_variant = (cpu_variant & ~ARM_ANY)
6950 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL;
6951 else if (streq (str, "920t"))
6952 cpu_variant = (cpu_variant & ~ARM_ANY)
6953 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6954 else if (streq (str, "9tdmi"))
6955 cpu_variant = (cpu_variant & ~ARM_ANY)
6956 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6957 else
6958 goto bad;
6959 break;
6960
6961 case 's':
6962 if (streq (str, "strongarm")
6963 || streq (str, "strongarm110")
6964 || streq (str, "strongarm1100"))
6965 cpu_variant = (cpu_variant & ~ARM_ANY)
6966 | ARM_8 | ARM_ARCH_V4 | ARM_LONGMUL;
6967 else
6968 goto bad;
6969 break;
6970
6971 case 'v':
6972 /* Select variant based on architecture rather than
6973 processor. */
6974 switch (*++str)
6975 {
6976 case '2':
6977 switch (*++str)
6978 {
6979 case 'a':
6980 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
6981 break;
6982 case 0:
6983 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
6984 break;
6985 default:
6986 as_bad (_("Invalid architecture variant -m%s"), arg);
6987 break;
6988 }
6989 break;
6990
6991 case '3':
6992 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
6993
6994 switch (*++str)
6995 {
6996 case 'm': cpu_variant |= ARM_LONGMUL; break;
6997 case 0: break;
6998 default:
6999 as_bad (_("Invalid architecture variant -m%s"), arg);
7000 break;
7001 }
7002 break;
7003
7004 case '4':
7005 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4;
7006
7007 switch (*++str)
7008 {
7009 case 't': cpu_variant |= ARM_THUMB; break;
7010 case 0: break;
7011 default:
7012 as_bad (_("Invalid architecture variant -m%s"), arg);
7013 break;
7014 }
7015 break;
7016
7017 case '5':
7018 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V5;
7019 switch (*++str)
7020 {
7021 case 't': cpu_variant |= ARM_THUMB; break;
7022 case 0: break;
7023 default:
7024 as_bad (_("Invalid architecture variant -m%s"), arg);
7025 break;
7026 }
7027 break;
7028
7029 default:
7030 as_bad (_("Invalid architecture variant -m%s"), arg);
7031 break;
7032 }
7033 break;
7034
7035 default:
7036 bad:
7037 as_bad (_("Invalid processor variant -m%s"), arg);
7038 return 0;
7039 }
7040 }
7041 break;
7042
7043 #if defined OBJ_ELF || defined OBJ_COFF
7044 case 'k':
7045 pic_code = 1;
7046 break;
7047 #endif
7048
7049 default:
7050 return 0;
7051 }
7052
7053 return 1;
7054 }
7055
7056 void
7057 md_show_usage (fp)
7058 FILE * fp;
7059 {
7060 fprintf (fp, _("\
7061 ARM Specific Assembler Options:\n\
7062 -m[arm][<processor name>] select processor variant\n\
7063 -m[arm]v[2|2a|3|3m|4|4t|5[t][e]] select architecture variant\n\
7064 -mthumb only allow Thumb instructions\n\
7065 -mthumb-interwork mark the assembled code as supporting interworking\n\
7066 -mall allow any instruction\n\
7067 -mfpa10, -mfpa11 select floating point architecture\n\
7068 -mfpe-old don't allow floating-point multiple instructions\n\
7069 -mno-fpu don't allow any floating-point instructions.\n\
7070 -k generate PIC code.\n"));
7071 #if defined OBJ_COFF || defined OBJ_ELF
7072 fprintf (fp, _("\
7073 -mapcs-32, -mapcs-26 specify which ARM Procedure Calling Standard to use\n\
7074 -mapcs-float floating point args are passed in FP regs\n\
7075 -mapcs-reentrant the code is position independent/reentrant\n"));
7076 #endif
7077 #ifdef OBJ_ELF
7078 fprintf (fp, _("\
7079 -moabi support the old ELF ABI\n"));
7080 #endif
7081 #ifdef ARM_BI_ENDIAN
7082 fprintf (fp, _("\
7083 -EB assemble code for a big endian cpu\n\
7084 -EL assemble code for a little endian cpu\n"));
7085 #endif
7086 }
7087
7088 /* We need to be able to fix up arbitrary expressions in some statements.
7089 This is so that we can handle symbols that are an arbitrary distance from
7090 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
7091 which returns part of an address in a form which will be valid for
7092 a data instruction. We do this by pushing the expression into a symbol
7093 in the expr_section, and creating a fix for that. */
7094
7095 static void
7096 fix_new_arm (frag, where, size, exp, pc_rel, reloc)
7097 fragS * frag;
7098 int where;
7099 short int size;
7100 expressionS * exp;
7101 int pc_rel;
7102 int reloc;
7103 {
7104 fixS * new_fix;
7105 arm_fix_data * arm_data;
7106
7107 switch (exp->X_op)
7108 {
7109 case O_constant:
7110 case O_symbol:
7111 case O_add:
7112 case O_subtract:
7113 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
7114 break;
7115
7116 default:
7117 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
7118 pc_rel, reloc);
7119 break;
7120 }
7121
7122 /* Mark whether the fix is to a THUMB instruction, or an ARM
7123 instruction. */
7124 arm_data = (arm_fix_data *) obstack_alloc (& notes, sizeof (arm_fix_data));
7125 new_fix->tc_fix_data = (PTR) arm_data;
7126 arm_data->thumb_mode = thumb_mode;
7127
7128 return;
7129 }
7130
7131 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
7132
7133 void
7134 cons_fix_new_arm (frag, where, size, exp)
7135 fragS * frag;
7136 int where;
7137 int size;
7138 expressionS * exp;
7139 {
7140 bfd_reloc_code_real_type type;
7141 int pcrel = 0;
7142
7143 /* Pick a reloc.
7144 FIXME: @@ Should look at CPU word size. */
7145 switch (size)
7146 {
7147 case 1:
7148 type = BFD_RELOC_8;
7149 break;
7150 case 2:
7151 type = BFD_RELOC_16;
7152 break;
7153 case 4:
7154 default:
7155 type = BFD_RELOC_32;
7156 break;
7157 case 8:
7158 type = BFD_RELOC_64;
7159 break;
7160 }
7161
7162 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
7163 }
7164
7165 /* A good place to do this, although this was probably not intended
7166 for this kind of use. We need to dump the literal pool before
7167 references are made to a null symbol pointer. */
7168
7169 void
7170 arm_cleanup ()
7171 {
7172 if (current_poolP == NULL)
7173 return;
7174
7175 /* Put it at the end of text section. */
7176 subseg_set (text_section, 0);
7177 s_ltorg (0);
7178 listing_prev_line ();
7179 }
7180
7181 void
7182 arm_start_line_hook ()
7183 {
7184 last_label_seen = NULL;
7185 }
7186
7187 void
7188 arm_frob_label (sym)
7189 symbolS * sym;
7190 {
7191 last_label_seen = sym;
7192
7193 ARM_SET_THUMB (sym, thumb_mode);
7194
7195 #if defined OBJ_COFF || defined OBJ_ELF
7196 ARM_SET_INTERWORK (sym, support_interwork);
7197 #endif
7198
7199 if (label_is_thumb_function_name)
7200 {
7201 /* When the address of a Thumb function is taken the bottom
7202 bit of that address should be set. This will allow
7203 interworking between Arm and Thumb functions to work
7204 correctly. */
7205
7206 THUMB_SET_FUNC (sym, 1);
7207
7208 label_is_thumb_function_name = false;
7209 }
7210 }
7211
7212 /* Adjust the symbol table. This marks Thumb symbols as distinct from
7213 ARM ones. */
7214
7215 void
7216 arm_adjust_symtab ()
7217 {
7218 #ifdef OBJ_COFF
7219 symbolS * sym;
7220
7221 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
7222 {
7223 if (ARM_IS_THUMB (sym))
7224 {
7225 if (THUMB_IS_FUNC (sym))
7226 {
7227 /* Mark the symbol as a Thumb function. */
7228 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
7229 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
7230 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
7231
7232 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
7233 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
7234 else
7235 as_bad (_("%s: unexpected function type: %d"),
7236 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
7237 }
7238 else switch (S_GET_STORAGE_CLASS (sym))
7239 {
7240 case C_EXT:
7241 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
7242 break;
7243 case C_STAT:
7244 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
7245 break;
7246 case C_LABEL:
7247 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
7248 break;
7249 default:
7250 /* Do nothing. */
7251 break;
7252 }
7253 }
7254
7255 if (ARM_IS_INTERWORK (sym))
7256 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
7257 }
7258 #endif
7259 #ifdef OBJ_ELF
7260 symbolS * sym;
7261 char bind;
7262
7263 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
7264 {
7265 if (ARM_IS_THUMB (sym))
7266 {
7267 elf_symbol_type * elf_sym;
7268
7269 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
7270 bind = ELF_ST_BIND (elf_sym);
7271
7272 /* If it's a .thumb_func, declare it as so,
7273 otherwise tag label as .code 16. */
7274 if (THUMB_IS_FUNC (sym))
7275 elf_sym->internal_elf_sym.st_info =
7276 ELF_ST_INFO (bind, STT_ARM_TFUNC);
7277 else
7278 elf_sym->internal_elf_sym.st_info =
7279 ELF_ST_INFO (bind, STT_ARM_16BIT);
7280 }
7281 }
7282 #endif
7283 }
7284
7285 int
7286 arm_data_in_code ()
7287 {
7288 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
7289 {
7290 *input_line_pointer = '/';
7291 input_line_pointer += 5;
7292 *input_line_pointer = 0;
7293 return 1;
7294 }
7295
7296 return 0;
7297 }
7298
7299 char *
7300 arm_canonicalize_symbol_name (name)
7301 char * name;
7302 {
7303 int len;
7304
7305 if (thumb_mode && (len = strlen (name)) > 5
7306 && streq (name + len - 5, "/data"))
7307 *(name + len - 5) = 0;
7308
7309 return name;
7310 }
7311
7312 boolean
7313 arm_validate_fix (fixP)
7314 fixS * fixP;
7315 {
7316 /* If the destination of the branch is a defined symbol which does not have
7317 the THUMB_FUNC attribute, then we must be calling a function which has
7318 the (interfacearm) attribute. We look for the Thumb entry point to that
7319 function and change the branch to refer to that function instead. */
7320 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
7321 && fixP->fx_addsy != NULL
7322 && S_IS_DEFINED (fixP->fx_addsy)
7323 && ! THUMB_IS_FUNC (fixP->fx_addsy))
7324 {
7325 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
7326 return true;
7327 }
7328
7329 return false;
7330 }
7331
7332 #ifdef OBJ_ELF
7333 /* Relocations against Thumb function names must be left unadjusted,
7334 so that the linker can use this information to correctly set the
7335 bottom bit of their addresses. The MIPS version of this function
7336 also prevents relocations that are mips-16 specific, but I do not
7337 know why it does this.
7338
7339 FIXME:
7340 There is one other problem that ought to be addressed here, but
7341 which currently is not: Taking the address of a label (rather
7342 than a function) and then later jumping to that address. Such
7343 addresses also ought to have their bottom bit set (assuming that
7344 they reside in Thumb code), but at the moment they will not. */
7345
7346 boolean
7347 arm_fix_adjustable (fixP)
7348 fixS * fixP;
7349 {
7350 if (fixP->fx_addsy == NULL)
7351 return 1;
7352
7353 /* Prevent all adjustments to global symbols. */
7354 if (S_IS_EXTERN (fixP->fx_addsy))
7355 return 0;
7356
7357 if (S_IS_WEAK (fixP->fx_addsy))
7358 return 0;
7359
7360 if (THUMB_IS_FUNC (fixP->fx_addsy)
7361 && fixP->fx_subsy == NULL)
7362 return 0;
7363
7364 /* We need the symbol name for the VTABLE entries. */
7365 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
7366 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7367 return 0;
7368
7369 return 1;
7370 }
7371
7372 const char *
7373 elf32_arm_target_format ()
7374 {
7375 if (target_big_endian)
7376 {
7377 if (target_oabi)
7378 return "elf32-bigarm-oabi";
7379 else
7380 return "elf32-bigarm";
7381 }
7382 else
7383 {
7384 if (target_oabi)
7385 return "elf32-littlearm-oabi";
7386 else
7387 return "elf32-littlearm";
7388 }
7389 }
7390
7391 void
7392 armelf_frob_symbol (symp, puntp)
7393 symbolS * symp;
7394 int * puntp;
7395 {
7396 elf_frob_symbol (symp, puntp);
7397 }
7398
7399 int
7400 arm_force_relocation (fixp)
7401 struct fix * fixp;
7402 {
7403 if ( fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
7404 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
7405 || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
7406 || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
7407 || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX
7408 || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23)
7409 return 1;
7410
7411 return 0;
7412 }
7413
7414 static bfd_reloc_code_real_type
7415 arm_parse_reloc ()
7416 {
7417 char id [16];
7418 char * ip;
7419 unsigned int i;
7420 static struct
7421 {
7422 char * str;
7423 int len;
7424 bfd_reloc_code_real_type reloc;
7425 }
7426 reloc_map[] =
7427 {
7428 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
7429 MAP ("(got)", BFD_RELOC_ARM_GOT32),
7430 MAP ("(gotoff)", BFD_RELOC_ARM_GOTOFF),
7431 /* ScottB: Jan 30, 1998 - Added support for parsing "var(PLT)"
7432 branch instructions generated by GCC for PLT relocs. */
7433 MAP ("(plt)", BFD_RELOC_ARM_PLT32),
7434 { NULL, 0, BFD_RELOC_UNUSED }
7435 #undef MAP
7436 };
7437
7438 for (i = 0, ip = input_line_pointer;
7439 i < sizeof (id) && (isalnum (*ip) || ispunct (*ip));
7440 i++, ip++)
7441 id[i] = tolower (*ip);
7442
7443 for (i = 0; reloc_map[i].str; i++)
7444 if (strncmp (id, reloc_map[i].str, reloc_map[i].len) == 0)
7445 break;
7446
7447 input_line_pointer += reloc_map[i].len;
7448
7449 return reloc_map[i].reloc;
7450 }
7451
7452 static void
7453 s_arm_elf_cons (nbytes)
7454 int nbytes;
7455 {
7456 expressionS exp;
7457
7458 #ifdef md_flush_pending_output
7459 md_flush_pending_output ();
7460 #endif
7461
7462 if (is_it_end_of_statement ())
7463 {
7464 demand_empty_rest_of_line ();
7465 return;
7466 }
7467
7468 #ifdef md_cons_align
7469 md_cons_align (nbytes);
7470 #endif
7471
7472 do
7473 {
7474 bfd_reloc_code_real_type reloc;
7475
7476 expression (& exp);
7477
7478 if (exp.X_op == O_symbol
7479 && * input_line_pointer == '('
7480 && (reloc = arm_parse_reloc ()) != BFD_RELOC_UNUSED)
7481 {
7482 reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc);
7483 int size = bfd_get_reloc_size (howto);
7484
7485 if (size > nbytes)
7486 as_bad ("%s relocations do not fit in %d bytes",
7487 howto->name, nbytes);
7488 else
7489 {
7490 register char *p = frag_more ((int) nbytes);
7491 int offset = nbytes - size;
7492
7493 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
7494 &exp, 0, reloc);
7495 }
7496 }
7497 else
7498 emit_expr (&exp, (unsigned int) nbytes);
7499 }
7500 while (*input_line_pointer++ == ',');
7501
7502 /* Put terminator back into stream. */
7503 input_line_pointer --;
7504 demand_empty_rest_of_line ();
7505 }
7506
7507 /* Stuff to do after assembling all of the source file. */
7508
7509 void
7510 arm_end_of_source ()
7511 {
7512 if (debug_type == DEBUG_DWARF2)
7513 dwarf2_finish ();
7514 }
7515
7516 #endif /* OBJ_ELF */