1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
45 #define WARN_DEPRECATED 1
48 /* Must be at least the size of the largest unwind opcode (currently two). */
49 #define ARM_OPCODE_CHUNK_SIZE 8
51 /* This structure holds the unwinding state. */
56 symbolS
* table_entry
;
57 symbolS
* personality_routine
;
58 int personality_index
;
59 /* The segment containing the function. */
62 /* Opcodes generated from this function. */
63 unsigned char * opcodes
;
66 /* The number of bytes pushed to the stack. */
68 /* We don't add stack adjustment opcodes immediately so that we can merge
69 multiple adjustments. We can also omit the final adjustment
70 when using a frame pointer. */
71 offsetT pending_offset
;
72 /* These two fields are set by both unwind_movsp and unwind_setfp. They
73 hold the reg+offset to use when restoring sp from a frame pointer. */
76 /* Nonzero if an unwind_setfp directive has been seen. */
78 /* Nonzero if the last opcode restores sp from fp_reg. */
79 unsigned sp_restored
:1;
82 /* Bit N indicates that an R_ARM_NONE relocation has been output for
83 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
84 emitted only once per section, to save unnecessary bloat. */
85 static unsigned int marked_pr_dependency
= 0;
89 /* Results from operand parsing worker functions. */
93 PARSE_OPERAND_SUCCESS
,
95 PARSE_OPERAND_FAIL_NO_BACKTRACK
96 } parse_operand_result
;
101 ARM_FLOAT_ABI_SOFTFP
,
105 /* Types of processor to assemble for. */
107 #if defined __XSCALE__
108 #define CPU_DEFAULT ARM_ARCH_XSCALE
110 #if defined __thumb__
111 #define CPU_DEFAULT ARM_ARCH_V5T
118 # define FPU_DEFAULT FPU_ARCH_FPA
119 # elif defined (TE_NetBSD)
121 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
123 /* Legacy a.out format. */
124 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
126 # elif defined (TE_VXWORKS)
127 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
129 /* For backwards compatibility, default to FPA. */
130 # define FPU_DEFAULT FPU_ARCH_FPA
132 #endif /* ifndef FPU_DEFAULT */
134 #define streq(a, b) (strcmp (a, b) == 0)
136 static arm_feature_set cpu_variant
;
137 static arm_feature_set arm_arch_used
;
138 static arm_feature_set thumb_arch_used
;
140 /* Flags stored in private area of BFD structure. */
141 static int uses_apcs_26
= FALSE
;
142 static int atpcs
= FALSE
;
143 static int support_interwork
= FALSE
;
144 static int uses_apcs_float
= FALSE
;
145 static int pic_code
= FALSE
;
147 /* Variables that we set while parsing command-line options. Once all
148 options have been read we re-process these values to set the real
150 static const arm_feature_set
*legacy_cpu
= NULL
;
151 static const arm_feature_set
*legacy_fpu
= NULL
;
153 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
154 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
155 static const arm_feature_set
*march_cpu_opt
= NULL
;
156 static const arm_feature_set
*march_fpu_opt
= NULL
;
157 static const arm_feature_set
*mfpu_opt
= NULL
;
158 static const arm_feature_set
*object_arch
= NULL
;
160 /* Constants for known architecture features. */
161 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
162 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
163 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
164 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
165 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
166 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
167 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
168 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
169 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
172 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
175 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
176 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
177 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
178 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
179 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
180 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
181 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
182 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
183 static const arm_feature_set arm_ext_v4t_5
=
184 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
185 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
186 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
187 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
188 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
189 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
190 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
191 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
192 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
193 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
194 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
195 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
196 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
197 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
198 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
200 static const arm_feature_set arm_arch_any
= ARM_ANY
;
201 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
202 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
203 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
205 static const arm_feature_set arm_cext_iwmmxt2
=
206 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
207 static const arm_feature_set arm_cext_iwmmxt
=
208 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
209 static const arm_feature_set arm_cext_xscale
=
210 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
211 static const arm_feature_set arm_cext_maverick
=
212 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
213 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
214 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
215 static const arm_feature_set fpu_vfp_ext_v1xd
=
216 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
217 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
218 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
219 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
220 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
221 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
222 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
224 static int mfloat_abi_opt
= -1;
225 /* Record user cpu selection for object attributes. */
226 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
227 /* Must be long enough to hold any of the names in arm_cpus. */
228 static char selected_cpu_name
[16];
231 static int meabi_flags
= EABI_DEFAULT
;
233 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
239 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
244 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
245 symbolS
* GOT_symbol
;
248 /* 0: assemble for ARM,
249 1: assemble for Thumb,
250 2: assemble for Thumb even though target CPU does not support thumb
252 static int thumb_mode
= 0;
254 /* If unified_syntax is true, we are processing the new unified
255 ARM/Thumb syntax. Important differences from the old ARM mode:
257 - Immediate operands do not require a # prefix.
258 - Conditional affixes always appear at the end of the
259 instruction. (For backward compatibility, those instructions
260 that formerly had them in the middle, continue to accept them
262 - The IT instruction may appear, and if it does is validated
263 against subsequent conditional affixes. It does not generate
266 Important differences from the old Thumb mode:
268 - Immediate operands do not require a # prefix.
269 - Most of the V6T2 instructions are only available in unified mode.
270 - The .N and .W suffixes are recognized and honored (it is an error
271 if they cannot be honored).
272 - All instructions set the flags if and only if they have an 's' affix.
273 - Conditional affixes may be used. They are validated against
274 preceding IT instructions. Unlike ARM mode, you cannot use a
275 conditional affix except in the scope of an IT instruction. */
277 static bfd_boolean unified_syntax
= FALSE
;
292 enum neon_el_type type
;
296 #define NEON_MAX_TYPE_ELS 4
300 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
307 unsigned long instruction
;
311 /* "uncond_value" is set to the value in place of the conditional field in
312 unconditional versions of the instruction, or -1 if nothing is
315 struct neon_type vectype
;
316 /* Set to the opcode if the instruction needs relaxation.
317 Zero if the instruction is not relaxed. */
321 bfd_reloc_code_real_type type
;
330 struct neon_type_el vectype
;
331 unsigned present
: 1; /* Operand present. */
332 unsigned isreg
: 1; /* Operand was a register. */
333 unsigned immisreg
: 1; /* .imm field is a second register. */
334 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
335 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
336 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
337 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
338 instructions. This allows us to disambiguate ARM <-> vector insns. */
339 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
340 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
341 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
342 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
343 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
344 unsigned writeback
: 1; /* Operand has trailing ! */
345 unsigned preind
: 1; /* Preindexed address. */
346 unsigned postind
: 1; /* Postindexed address. */
347 unsigned negative
: 1; /* Index register was negated. */
348 unsigned shifted
: 1; /* Shift applied to operation. */
349 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
353 static struct arm_it inst
;
355 #define NUM_FLOAT_VALS 8
357 const char * fp_const
[] =
359 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
362 /* Number of littlenums required to hold an extended precision number. */
363 #define MAX_LITTLENUMS 6
365 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
375 #define CP_T_X 0x00008000
376 #define CP_T_Y 0x00400000
378 #define CONDS_BIT 0x00100000
379 #define LOAD_BIT 0x00100000
381 #define DOUBLE_LOAD_FLAG 0x00000001
385 const char * template;
389 #define COND_ALWAYS 0xE
393 const char *template;
397 struct asm_barrier_opt
399 const char *template;
403 /* The bit that distinguishes CPSR and SPSR. */
404 #define SPSR_BIT (1 << 22)
406 /* The individual PSR flag bits. */
407 #define PSR_c (1 << 16)
408 #define PSR_x (1 << 17)
409 #define PSR_s (1 << 18)
410 #define PSR_f (1 << 19)
415 bfd_reloc_code_real_type reloc
;
420 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
421 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
426 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
429 /* Bits for DEFINED field in neon_typed_alias. */
430 #define NTA_HASTYPE 1
431 #define NTA_HASINDEX 2
433 struct neon_typed_alias
435 unsigned char defined
;
437 struct neon_type_el eltype
;
440 /* ARM register categories. This includes coprocessor numbers and various
441 architecture extensions' registers. */
467 /* Structure for a hash table entry for a register.
468 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
469 information which states whether a vector type or index is specified (for a
470 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
474 unsigned char number
;
476 unsigned char builtin
;
477 struct neon_typed_alias
*neon
;
480 /* Diagnostics used when we don't get a register of the expected type. */
481 const char *const reg_expected_msgs
[] =
483 N_("ARM register expected"),
484 N_("bad or missing co-processor number"),
485 N_("co-processor register expected"),
486 N_("FPA register expected"),
487 N_("VFP single precision register expected"),
488 N_("VFP/Neon double precision register expected"),
489 N_("Neon quad precision register expected"),
490 N_("VFP single or double precision register expected"),
491 N_("Neon double or quad precision register expected"),
492 N_("VFP single, double or Neon quad precision register expected"),
493 N_("VFP system register expected"),
494 N_("Maverick MVF register expected"),
495 N_("Maverick MVD register expected"),
496 N_("Maverick MVFX register expected"),
497 N_("Maverick MVDX register expected"),
498 N_("Maverick MVAX register expected"),
499 N_("Maverick DSPSC register expected"),
500 N_("iWMMXt data register expected"),
501 N_("iWMMXt control register expected"),
502 N_("iWMMXt scalar register expected"),
503 N_("XScale accumulator register expected"),
506 /* Some well known registers that we refer to directly elsewhere. */
511 /* ARM instructions take 4bytes in the object file, Thumb instructions
517 /* Basic string to match. */
518 const char *template;
520 /* Parameters to instruction. */
521 unsigned char operands
[8];
523 /* Conditional tag - see opcode_lookup. */
524 unsigned int tag
: 4;
526 /* Basic instruction code. */
527 unsigned int avalue
: 28;
529 /* Thumb-format instruction code. */
532 /* Which architecture variant provides this instruction. */
533 const arm_feature_set
*avariant
;
534 const arm_feature_set
*tvariant
;
536 /* Function to call to encode instruction in ARM format. */
537 void (* aencode
) (void);
539 /* Function to call to encode instruction in Thumb format. */
540 void (* tencode
) (void);
543 /* Defines for various bits that we will want to toggle. */
544 #define INST_IMMEDIATE 0x02000000
545 #define OFFSET_REG 0x02000000
546 #define HWOFFSET_IMM 0x00400000
547 #define SHIFT_BY_REG 0x00000010
548 #define PRE_INDEX 0x01000000
549 #define INDEX_UP 0x00800000
550 #define WRITE_BACK 0x00200000
551 #define LDM_TYPE_2_OR_3 0x00400000
552 #define CPSI_MMOD 0x00020000
554 #define LITERAL_MASK 0xf000f000
555 #define OPCODE_MASK 0xfe1fffff
556 #define V4_STR_BIT 0x00000020
558 #define DATA_OP_SHIFT 21
560 #define T2_OPCODE_MASK 0xfe1fffff
561 #define T2_DATA_OP_SHIFT 21
563 /* Codes to distinguish the arithmetic instructions. */
574 #define OPCODE_CMP 10
575 #define OPCODE_CMN 11
576 #define OPCODE_ORR 12
577 #define OPCODE_MOV 13
578 #define OPCODE_BIC 14
579 #define OPCODE_MVN 15
581 #define T2_OPCODE_AND 0
582 #define T2_OPCODE_BIC 1
583 #define T2_OPCODE_ORR 2
584 #define T2_OPCODE_ORN 3
585 #define T2_OPCODE_EOR 4
586 #define T2_OPCODE_ADD 8
587 #define T2_OPCODE_ADC 10
588 #define T2_OPCODE_SBC 11
589 #define T2_OPCODE_SUB 13
590 #define T2_OPCODE_RSB 14
592 #define T_OPCODE_MUL 0x4340
593 #define T_OPCODE_TST 0x4200
594 #define T_OPCODE_CMN 0x42c0
595 #define T_OPCODE_NEG 0x4240
596 #define T_OPCODE_MVN 0x43c0
598 #define T_OPCODE_ADD_R3 0x1800
599 #define T_OPCODE_SUB_R3 0x1a00
600 #define T_OPCODE_ADD_HI 0x4400
601 #define T_OPCODE_ADD_ST 0xb000
602 #define T_OPCODE_SUB_ST 0xb080
603 #define T_OPCODE_ADD_SP 0xa800
604 #define T_OPCODE_ADD_PC 0xa000
605 #define T_OPCODE_ADD_I8 0x3000
606 #define T_OPCODE_SUB_I8 0x3800
607 #define T_OPCODE_ADD_I3 0x1c00
608 #define T_OPCODE_SUB_I3 0x1e00
610 #define T_OPCODE_ASR_R 0x4100
611 #define T_OPCODE_LSL_R 0x4080
612 #define T_OPCODE_LSR_R 0x40c0
613 #define T_OPCODE_ROR_R 0x41c0
614 #define T_OPCODE_ASR_I 0x1000
615 #define T_OPCODE_LSL_I 0x0000
616 #define T_OPCODE_LSR_I 0x0800
618 #define T_OPCODE_MOV_I8 0x2000
619 #define T_OPCODE_CMP_I8 0x2800
620 #define T_OPCODE_CMP_LR 0x4280
621 #define T_OPCODE_MOV_HR 0x4600
622 #define T_OPCODE_CMP_HR 0x4500
624 #define T_OPCODE_LDR_PC 0x4800
625 #define T_OPCODE_LDR_SP 0x9800
626 #define T_OPCODE_STR_SP 0x9000
627 #define T_OPCODE_LDR_IW 0x6800
628 #define T_OPCODE_STR_IW 0x6000
629 #define T_OPCODE_LDR_IH 0x8800
630 #define T_OPCODE_STR_IH 0x8000
631 #define T_OPCODE_LDR_IB 0x7800
632 #define T_OPCODE_STR_IB 0x7000
633 #define T_OPCODE_LDR_RW 0x5800
634 #define T_OPCODE_STR_RW 0x5000
635 #define T_OPCODE_LDR_RH 0x5a00
636 #define T_OPCODE_STR_RH 0x5200
637 #define T_OPCODE_LDR_RB 0x5c00
638 #define T_OPCODE_STR_RB 0x5400
640 #define T_OPCODE_PUSH 0xb400
641 #define T_OPCODE_POP 0xbc00
643 #define T_OPCODE_BRANCH 0xe000
645 #define THUMB_SIZE 2 /* Size of thumb instruction. */
646 #define THUMB_PP_PC_LR 0x0100
647 #define THUMB_LOAD_BIT 0x0800
648 #define THUMB2_LOAD_BIT 0x00100000
650 #define BAD_ARGS _("bad arguments to instruction")
651 #define BAD_PC _("r15 not allowed here")
652 #define BAD_COND _("instruction cannot be conditional")
653 #define BAD_OVERLAP _("registers may not be the same")
654 #define BAD_HIREG _("lo register required")
655 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
656 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
657 #define BAD_BRANCH _("branch must be last instruction in IT block")
658 #define BAD_NOT_IT _("instruction not allowed in IT block")
659 #define BAD_FPU _("selected FPU does not support instruction")
661 static struct hash_control
*arm_ops_hsh
;
662 static struct hash_control
*arm_cond_hsh
;
663 static struct hash_control
*arm_shift_hsh
;
664 static struct hash_control
*arm_psr_hsh
;
665 static struct hash_control
*arm_v7m_psr_hsh
;
666 static struct hash_control
*arm_reg_hsh
;
667 static struct hash_control
*arm_reloc_hsh
;
668 static struct hash_control
*arm_barrier_opt_hsh
;
670 /* Stuff needed to resolve the label ambiguity
680 symbolS
* last_label_seen
;
681 static int label_is_thumb_function_name
= FALSE
;
683 /* Literal pool structure. Held on a per-section
684 and per-sub-section basis. */
686 #define MAX_LITERAL_POOL_SIZE 1024
687 typedef struct literal_pool
689 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
690 unsigned int next_free_entry
;
695 struct literal_pool
* next
;
698 /* Pointer to a linked list of literal pools. */
699 literal_pool
* list_of_pools
= NULL
;
701 /* State variables for IT block handling. */
702 static bfd_boolean current_it_mask
= 0;
703 static int current_cc
;
708 /* This array holds the chars that always start a comment. If the
709 pre-processor is disabled, these aren't very useful. */
710 const char comment_chars
[] = "@";
712 /* This array holds the chars that only start a comment at the beginning of
713 a line. If the line seems to have the form '# 123 filename'
714 .line and .file directives will appear in the pre-processed output. */
715 /* Note that input_file.c hand checks for '#' at the beginning of the
716 first line of the input file. This is because the compiler outputs
717 #NO_APP at the beginning of its output. */
718 /* Also note that comments like this one will always work. */
719 const char line_comment_chars
[] = "#";
721 const char line_separator_chars
[] = ";";
723 /* Chars that can be used to separate mant
724 from exp in floating point numbers. */
725 const char EXP_CHARS
[] = "eE";
727 /* Chars that mean this number is a floating point constant. */
731 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
733 /* Prefix characters that indicate the start of an immediate
735 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
737 /* Separator character handling. */
739 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
742 skip_past_char (char ** str
, char c
)
752 #define skip_past_comma(str) skip_past_char (str, ',')
754 /* Arithmetic expressions (possibly involving symbols). */
756 /* Return TRUE if anything in the expression is a bignum. */
759 walk_no_bignums (symbolS
* sp
)
761 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
764 if (symbol_get_value_expression (sp
)->X_add_symbol
)
766 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
767 || (symbol_get_value_expression (sp
)->X_op_symbol
768 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
774 static int in_my_get_expression
= 0;
776 /* Third argument to my_get_expression. */
777 #define GE_NO_PREFIX 0
778 #define GE_IMM_PREFIX 1
779 #define GE_OPT_PREFIX 2
780 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
781 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
782 #define GE_OPT_PREFIX_BIG 3
785 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
790 /* In unified syntax, all prefixes are optional. */
792 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
797 case GE_NO_PREFIX
: break;
799 if (!is_immediate_prefix (**str
))
801 inst
.error
= _("immediate expression requires a # prefix");
807 case GE_OPT_PREFIX_BIG
:
808 if (is_immediate_prefix (**str
))
814 memset (ep
, 0, sizeof (expressionS
));
816 save_in
= input_line_pointer
;
817 input_line_pointer
= *str
;
818 in_my_get_expression
= 1;
819 seg
= expression (ep
);
820 in_my_get_expression
= 0;
822 if (ep
->X_op
== O_illegal
)
824 /* We found a bad expression in md_operand(). */
825 *str
= input_line_pointer
;
826 input_line_pointer
= save_in
;
827 if (inst
.error
== NULL
)
828 inst
.error
= _("bad expression");
833 if (seg
!= absolute_section
834 && seg
!= text_section
835 && seg
!= data_section
836 && seg
!= bss_section
837 && seg
!= undefined_section
)
839 inst
.error
= _("bad segment");
840 *str
= input_line_pointer
;
841 input_line_pointer
= save_in
;
846 /* Get rid of any bignums now, so that we don't generate an error for which
847 we can't establish a line number later on. Big numbers are never valid
848 in instructions, which is where this routine is always called. */
849 if (prefix_mode
!= GE_OPT_PREFIX_BIG
850 && (ep
->X_op
== O_big
852 && (walk_no_bignums (ep
->X_add_symbol
)
854 && walk_no_bignums (ep
->X_op_symbol
))))))
856 inst
.error
= _("invalid constant");
857 *str
= input_line_pointer
;
858 input_line_pointer
= save_in
;
862 *str
= input_line_pointer
;
863 input_line_pointer
= save_in
;
867 /* Turn a string in input_line_pointer into a floating point constant
868 of type TYPE, and store the appropriate bytes in *LITP. The number
869 of LITTLENUMS emitted is stored in *SIZEP. An error message is
870 returned, or NULL on OK.
872 Note that fp constants aren't represent in the normal way on the ARM.
873 In big endian mode, things are as expected. However, in little endian
874 mode fp constants are big-endian word-wise, and little-endian byte-wise
875 within the words. For example, (double) 1.1 in big endian mode is
876 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
877 the byte sequence 99 99 f1 3f 9a 99 99 99.
879 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
882 md_atof (int type
, char * litP
, int * sizeP
)
885 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
917 return _("bad call to MD_ATOF()");
920 t
= atof_ieee (input_line_pointer
, type
, words
);
922 input_line_pointer
= t
;
925 if (target_big_endian
)
927 for (i
= 0; i
< prec
; i
++)
929 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
935 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
936 for (i
= prec
- 1; i
>= 0; i
--)
938 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
942 /* For a 4 byte float the order of elements in `words' is 1 0.
943 For an 8 byte float the order is 1 0 3 2. */
944 for (i
= 0; i
< prec
; i
+= 2)
946 md_number_to_chars (litP
, (valueT
) words
[i
+ 1], 2);
947 md_number_to_chars (litP
+ 2, (valueT
) words
[i
], 2);
955 /* We handle all bad expressions here, so that we can report the faulty
956 instruction in the error message. */
958 md_operand (expressionS
* expr
)
960 if (in_my_get_expression
)
961 expr
->X_op
= O_illegal
;
964 /* Immediate values. */
966 /* Generic immediate-value read function for use in directives.
967 Accepts anything that 'expression' can fold to a constant.
968 *val receives the number. */
971 immediate_for_directive (int *val
)
974 exp
.X_op
= O_illegal
;
976 if (is_immediate_prefix (*input_line_pointer
))
978 input_line_pointer
++;
982 if (exp
.X_op
!= O_constant
)
984 as_bad (_("expected #constant"));
985 ignore_rest_of_line ();
988 *val
= exp
.X_add_number
;
993 /* Register parsing. */
995 /* Generic register parser. CCP points to what should be the
996 beginning of a register name. If it is indeed a valid register
997 name, advance CCP over it and return the reg_entry structure;
998 otherwise return NULL. Does not issue diagnostics. */
1000 static struct reg_entry
*
1001 arm_reg_parse_multi (char **ccp
)
1005 struct reg_entry
*reg
;
1007 #ifdef REGISTER_PREFIX
1008 if (*start
!= REGISTER_PREFIX
)
1012 #ifdef OPTIONAL_REGISTER_PREFIX
1013 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1018 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1023 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1025 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1035 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1036 enum arm_reg_type type
)
1038 /* Alternative syntaxes are accepted for a few register classes. */
1045 /* Generic coprocessor register names are allowed for these. */
1046 if (reg
&& reg
->type
== REG_TYPE_CN
)
1051 /* For backward compatibility, a bare number is valid here. */
1053 unsigned long processor
= strtoul (start
, ccp
, 10);
1054 if (*ccp
!= start
&& processor
<= 15)
1058 case REG_TYPE_MMXWC
:
1059 /* WC includes WCG. ??? I'm not sure this is true for all
1060 instructions that take WC registers. */
1061 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1072 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1073 return value is the register number or FAIL. */
1076 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1079 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1082 /* Do not allow a scalar (reg+index) to parse as a register. */
1083 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1086 if (reg
&& reg
->type
== type
)
1089 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1096 /* Parse a Neon type specifier. *STR should point at the leading '.'
1097 character. Does no verification at this stage that the type fits the opcode
1104 Can all be legally parsed by this function.
1106 Fills in neon_type struct pointer with parsed information, and updates STR
1107 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1108 type, FAIL if not. */
1111 parse_neon_type (struct neon_type
*type
, char **str
)
1118 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1120 enum neon_el_type thistype
= NT_untyped
;
1121 unsigned thissize
= -1u;
1128 /* Just a size without an explicit type. */
1132 switch (TOLOWER (*ptr
))
1134 case 'i': thistype
= NT_integer
; break;
1135 case 'f': thistype
= NT_float
; break;
1136 case 'p': thistype
= NT_poly
; break;
1137 case 's': thistype
= NT_signed
; break;
1138 case 'u': thistype
= NT_unsigned
; break;
1140 thistype
= NT_float
;
1145 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1151 /* .f is an abbreviation for .f32. */
1152 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1157 thissize
= strtoul (ptr
, &ptr
, 10);
1159 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1162 as_bad (_("bad size %d in type specifier"), thissize
);
1170 type
->el
[type
->elems
].type
= thistype
;
1171 type
->el
[type
->elems
].size
= thissize
;
1176 /* Empty/missing type is not a successful parse. */
1177 if (type
->elems
== 0)
1185 /* Errors may be set multiple times during parsing or bit encoding
1186 (particularly in the Neon bits), but usually the earliest error which is set
1187 will be the most meaningful. Avoid overwriting it with later (cascading)
1188 errors by calling this function. */
1191 first_error (const char *err
)
1197 /* Parse a single type, e.g. ".s32", leading period included. */
1199 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1202 struct neon_type optype
;
1206 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1208 if (optype
.elems
== 1)
1209 *vectype
= optype
.el
[0];
1212 first_error (_("only one type should be specified for operand"));
1218 first_error (_("vector type expected"));
1230 /* Special meanings for indices (which have a range of 0-7), which will fit into
1233 #define NEON_ALL_LANES 15
1234 #define NEON_INTERLEAVE_LANES 14
1236 /* Parse either a register or a scalar, with an optional type. Return the
1237 register number, and optionally fill in the actual type of the register
1238 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1239 type/index information in *TYPEINFO. */
1242 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1243 enum arm_reg_type
*rtype
,
1244 struct neon_typed_alias
*typeinfo
)
1247 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1248 struct neon_typed_alias atype
;
1249 struct neon_type_el parsetype
;
1253 atype
.eltype
.type
= NT_invtype
;
1254 atype
.eltype
.size
= -1;
1256 /* Try alternate syntax for some types of register. Note these are mutually
1257 exclusive with the Neon syntax extensions. */
1260 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1268 /* Undo polymorphism when a set of register types may be accepted. */
1269 if ((type
== REG_TYPE_NDQ
1270 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1271 || (type
== REG_TYPE_VFSD
1272 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1273 || (type
== REG_TYPE_NSDQ
1274 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1275 || reg
->type
== REG_TYPE_NQ
))
1276 || (type
== REG_TYPE_MMXWC
1277 && (reg
->type
== REG_TYPE_MMXWCG
)))
1280 if (type
!= reg
->type
)
1286 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1288 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1290 first_error (_("can't redefine type for operand"));
1293 atype
.defined
|= NTA_HASTYPE
;
1294 atype
.eltype
= parsetype
;
1297 if (skip_past_char (&str
, '[') == SUCCESS
)
1299 if (type
!= REG_TYPE_VFD
)
1301 first_error (_("only D registers may be indexed"));
1305 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1307 first_error (_("can't change index for operand"));
1311 atype
.defined
|= NTA_HASINDEX
;
1313 if (skip_past_char (&str
, ']') == SUCCESS
)
1314 atype
.index
= NEON_ALL_LANES
;
1319 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1321 if (exp
.X_op
!= O_constant
)
1323 first_error (_("constant expression required"));
1327 if (skip_past_char (&str
, ']') == FAIL
)
1330 atype
.index
= exp
.X_add_number
;
1345 /* Like arm_reg_parse, but allow allow the following extra features:
1346 - If RTYPE is non-zero, return the (possibly restricted) type of the
1347 register (e.g. Neon double or quad reg when either has been requested).
1348 - If this is a Neon vector type with additional type information, fill
1349 in the struct pointed to by VECTYPE (if non-NULL).
1350 This function will fault on encountering a scalar.
1354 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1355 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1357 struct neon_typed_alias atype
;
1359 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1364 /* Do not allow a scalar (reg+index) to parse as a register. */
1365 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1367 first_error (_("register operand expected, but got scalar"));
1372 *vectype
= atype
.eltype
;
1379 #define NEON_SCALAR_REG(X) ((X) >> 4)
1380 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1382 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1383 have enough information to be able to do a good job bounds-checking. So, we
1384 just do easy checks here, and do further checks later. */
1387 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1391 struct neon_typed_alias atype
;
1393 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1395 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1398 if (atype
.index
== NEON_ALL_LANES
)
1400 first_error (_("scalar must have an index"));
1403 else if (atype
.index
>= 64 / elsize
)
1405 first_error (_("scalar index out of range"));
1410 *type
= atype
.eltype
;
1414 return reg
* 16 + atype
.index
;
1417 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1419 parse_reg_list (char ** strp
)
1421 char * str
= * strp
;
1425 /* We come back here if we get ranges concatenated by '+' or '|'. */
1440 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1442 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1452 first_error (_("bad range in register list"));
1456 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1458 if (range
& (1 << i
))
1460 (_("Warning: duplicated register (r%d) in register list"),
1468 if (range
& (1 << reg
))
1469 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1471 else if (reg
<= cur_reg
)
1472 as_tsktsk (_("Warning: register range not in ascending order"));
1477 while (skip_past_comma (&str
) != FAIL
1478 || (in_range
= 1, *str
++ == '-'));
1483 first_error (_("missing `}'"));
1491 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1494 if (expr
.X_op
== O_constant
)
1496 if (expr
.X_add_number
1497 != (expr
.X_add_number
& 0x0000ffff))
1499 inst
.error
= _("invalid register mask");
1503 if ((range
& expr
.X_add_number
) != 0)
1505 int regno
= range
& expr
.X_add_number
;
1508 regno
= (1 << regno
) - 1;
1510 (_("Warning: duplicated register (r%d) in register list"),
1514 range
|= expr
.X_add_number
;
1518 if (inst
.reloc
.type
!= 0)
1520 inst
.error
= _("expression too complex");
1524 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1525 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1526 inst
.reloc
.pc_rel
= 0;
1530 if (*str
== '|' || *str
== '+')
1536 while (another_range
);
1542 /* Types of registers in a list. */
1551 /* Parse a VFP register list. If the string is invalid return FAIL.
1552 Otherwise return the number of registers, and set PBASE to the first
1553 register. Parses registers of type ETYPE.
1554 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1555 - Q registers can be used to specify pairs of D registers
1556 - { } can be omitted from around a singleton register list
1557 FIXME: This is not implemented, as it would require backtracking in
1560 This could be done (the meaning isn't really ambiguous), but doesn't
1561 fit in well with the current parsing framework.
1562 - 32 D registers may be used (also true for VFPv3).
1563 FIXME: Types are ignored in these register lists, which is probably a
1567 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1572 enum arm_reg_type regtype
= 0;
1576 unsigned long mask
= 0;
1581 inst
.error
= _("expecting {");
1590 regtype
= REG_TYPE_VFS
;
1595 regtype
= REG_TYPE_VFD
;
1598 case REGLIST_NEON_D
:
1599 regtype
= REG_TYPE_NDQ
;
1603 if (etype
!= REGLIST_VFP_S
)
1605 /* VFPv3 allows 32 D registers. */
1606 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
1610 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1613 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1620 base_reg
= max_regs
;
1624 int setmask
= 1, addregs
= 1;
1626 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1628 if (new_base
== FAIL
)
1630 first_error (_(reg_expected_msgs
[regtype
]));
1634 if (new_base
>= max_regs
)
1636 first_error (_("register out of range in list"));
1640 /* Note: a value of 2 * n is returned for the register Q<n>. */
1641 if (regtype
== REG_TYPE_NQ
)
1647 if (new_base
< base_reg
)
1648 base_reg
= new_base
;
1650 if (mask
& (setmask
<< new_base
))
1652 first_error (_("invalid register list"));
1656 if ((mask
>> new_base
) != 0 && ! warned
)
1658 as_tsktsk (_("register list not in ascending order"));
1662 mask
|= setmask
<< new_base
;
1665 if (*str
== '-') /* We have the start of a range expression */
1671 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1674 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1678 if (high_range
>= max_regs
)
1680 first_error (_("register out of range in list"));
1684 if (regtype
== REG_TYPE_NQ
)
1685 high_range
= high_range
+ 1;
1687 if (high_range
<= new_base
)
1689 inst
.error
= _("register range not in ascending order");
1693 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1695 if (mask
& (setmask
<< new_base
))
1697 inst
.error
= _("invalid register list");
1701 mask
|= setmask
<< new_base
;
1706 while (skip_past_comma (&str
) != FAIL
);
1710 /* Sanity check -- should have raised a parse error above. */
1711 if (count
== 0 || count
> max_regs
)
1716 /* Final test -- the registers must be consecutive. */
1718 for (i
= 0; i
< count
; i
++)
1720 if ((mask
& (1u << i
)) == 0)
1722 inst
.error
= _("non-contiguous register range");
1732 /* True if two alias types are the same. */
1735 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1743 if (a
->defined
!= b
->defined
)
1746 if ((a
->defined
& NTA_HASTYPE
) != 0
1747 && (a
->eltype
.type
!= b
->eltype
.type
1748 || a
->eltype
.size
!= b
->eltype
.size
))
1751 if ((a
->defined
& NTA_HASINDEX
) != 0
1752 && (a
->index
!= b
->index
))
1758 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1759 The base register is put in *PBASE.
1760 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1762 The register stride (minus one) is put in bit 4 of the return value.
1763 Bits [6:5] encode the list length (minus one).
1764 The type of the list elements is put in *ELTYPE, if non-NULL. */
1766 #define NEON_LANE(X) ((X) & 0xf)
1767 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1768 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1771 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1772 struct neon_type_el
*eltype
)
1779 int leading_brace
= 0;
1780 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1782 const char *const incr_error
= "register stride must be 1 or 2";
1783 const char *const type_error
= "mismatched element/structure types in list";
1784 struct neon_typed_alias firsttype
;
1786 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1791 struct neon_typed_alias atype
;
1792 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1796 first_error (_(reg_expected_msgs
[rtype
]));
1803 if (rtype
== REG_TYPE_NQ
)
1810 else if (reg_incr
== -1)
1812 reg_incr
= getreg
- base_reg
;
1813 if (reg_incr
< 1 || reg_incr
> 2)
1815 first_error (_(incr_error
));
1819 else if (getreg
!= base_reg
+ reg_incr
* count
)
1821 first_error (_(incr_error
));
1825 if (!neon_alias_types_same (&atype
, &firsttype
))
1827 first_error (_(type_error
));
1831 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1835 struct neon_typed_alias htype
;
1836 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1838 lane
= NEON_INTERLEAVE_LANES
;
1839 else if (lane
!= NEON_INTERLEAVE_LANES
)
1841 first_error (_(type_error
));
1846 else if (reg_incr
!= 1)
1848 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1852 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1855 first_error (_(reg_expected_msgs
[rtype
]));
1858 if (!neon_alias_types_same (&htype
, &firsttype
))
1860 first_error (_(type_error
));
1863 count
+= hireg
+ dregs
- getreg
;
1867 /* If we're using Q registers, we can't use [] or [n] syntax. */
1868 if (rtype
== REG_TYPE_NQ
)
1874 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1878 else if (lane
!= atype
.index
)
1880 first_error (_(type_error
));
1884 else if (lane
== -1)
1885 lane
= NEON_INTERLEAVE_LANES
;
1886 else if (lane
!= NEON_INTERLEAVE_LANES
)
1888 first_error (_(type_error
));
1893 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1895 /* No lane set by [x]. We must be interleaving structures. */
1897 lane
= NEON_INTERLEAVE_LANES
;
1900 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
1901 || (count
> 1 && reg_incr
== -1))
1903 first_error (_("error parsing element/structure list"));
1907 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
1909 first_error (_("expected }"));
1917 *eltype
= firsttype
.eltype
;
1922 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
1925 /* Parse an explicit relocation suffix on an expression. This is
1926 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1927 arm_reloc_hsh contains no entries, so this function can only
1928 succeed if there is no () after the word. Returns -1 on error,
1929 BFD_RELOC_UNUSED if there wasn't any suffix. */
1931 parse_reloc (char **str
)
1933 struct reloc_entry
*r
;
1937 return BFD_RELOC_UNUSED
;
1942 while (*q
&& *q
!= ')' && *q
!= ',')
1947 if ((r
= hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
1954 /* Directives: register aliases. */
1956 static struct reg_entry
*
1957 insert_reg_alias (char *str
, int number
, int type
)
1959 struct reg_entry
*new;
1962 if ((new = hash_find (arm_reg_hsh
, str
)) != 0)
1965 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
1967 /* Only warn about a redefinition if it's not defined as the
1969 else if (new->number
!= number
|| new->type
!= type
)
1970 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1975 name
= xstrdup (str
);
1976 new = xmalloc (sizeof (struct reg_entry
));
1979 new->number
= number
;
1981 new->builtin
= FALSE
;
1984 if (hash_insert (arm_reg_hsh
, name
, (PTR
) new))
1991 insert_neon_reg_alias (char *str
, int number
, int type
,
1992 struct neon_typed_alias
*atype
)
1994 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
1998 first_error (_("attempt to redefine typed alias"));
2004 reg
->neon
= xmalloc (sizeof (struct neon_typed_alias
));
2005 *reg
->neon
= *atype
;
2009 /* Look for the .req directive. This is of the form:
2011 new_register_name .req existing_register_name
2013 If we find one, or if it looks sufficiently like one that we want to
2014 handle any error here, return non-zero. Otherwise return zero. */
2017 create_register_alias (char * newname
, char *p
)
2019 struct reg_entry
*old
;
2020 char *oldname
, *nbuf
;
2023 /* The input scrubber ensures that whitespace after the mnemonic is
2024 collapsed to single spaces. */
2026 if (strncmp (oldname
, " .req ", 6) != 0)
2030 if (*oldname
== '\0')
2033 old
= hash_find (arm_reg_hsh
, oldname
);
2036 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2040 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2041 the desired alias name, and p points to its end. If not, then
2042 the desired alias name is in the global original_case_string. */
2043 #ifdef TC_CASE_SENSITIVE
2046 newname
= original_case_string
;
2047 nlen
= strlen (newname
);
2050 nbuf
= alloca (nlen
+ 1);
2051 memcpy (nbuf
, newname
, nlen
);
2054 /* Create aliases under the new name as stated; an all-lowercase
2055 version of the new name; and an all-uppercase version of the new
2057 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2059 for (p
= nbuf
; *p
; p
++)
2062 if (strncmp (nbuf
, newname
, nlen
))
2063 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2065 for (p
= nbuf
; *p
; p
++)
2068 if (strncmp (nbuf
, newname
, nlen
))
2069 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2074 /* Create a Neon typed/indexed register alias using directives, e.g.:
2079 These typed registers can be used instead of the types specified after the
2080 Neon mnemonic, so long as all operands given have types. Types can also be
2081 specified directly, e.g.:
2082 vadd d0.s32, d1.s32, d2.s32
2086 create_neon_reg_alias (char *newname
, char *p
)
2088 enum arm_reg_type basetype
;
2089 struct reg_entry
*basereg
;
2090 struct reg_entry mybasereg
;
2091 struct neon_type ntype
;
2092 struct neon_typed_alias typeinfo
;
2093 char *namebuf
, *nameend
;
2096 typeinfo
.defined
= 0;
2097 typeinfo
.eltype
.type
= NT_invtype
;
2098 typeinfo
.eltype
.size
= -1;
2099 typeinfo
.index
= -1;
2103 if (strncmp (p
, " .dn ", 5) == 0)
2104 basetype
= REG_TYPE_VFD
;
2105 else if (strncmp (p
, " .qn ", 5) == 0)
2106 basetype
= REG_TYPE_NQ
;
2115 basereg
= arm_reg_parse_multi (&p
);
2117 if (basereg
&& basereg
->type
!= basetype
)
2119 as_bad (_("bad type for register"));
2123 if (basereg
== NULL
)
2126 /* Try parsing as an integer. */
2127 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2128 if (exp
.X_op
!= O_constant
)
2130 as_bad (_("expression must be constant"));
2133 basereg
= &mybasereg
;
2134 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2140 typeinfo
= *basereg
->neon
;
2142 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2144 /* We got a type. */
2145 if (typeinfo
.defined
& NTA_HASTYPE
)
2147 as_bad (_("can't redefine the type of a register alias"));
2151 typeinfo
.defined
|= NTA_HASTYPE
;
2152 if (ntype
.elems
!= 1)
2154 as_bad (_("you must specify a single type only"));
2157 typeinfo
.eltype
= ntype
.el
[0];
2160 if (skip_past_char (&p
, '[') == SUCCESS
)
2163 /* We got a scalar index. */
2165 if (typeinfo
.defined
& NTA_HASINDEX
)
2167 as_bad (_("can't redefine the index of a scalar alias"));
2171 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2173 if (exp
.X_op
!= O_constant
)
2175 as_bad (_("scalar index must be constant"));
2179 typeinfo
.defined
|= NTA_HASINDEX
;
2180 typeinfo
.index
= exp
.X_add_number
;
2182 if (skip_past_char (&p
, ']') == FAIL
)
2184 as_bad (_("expecting ]"));
2189 namelen
= nameend
- newname
;
2190 namebuf
= alloca (namelen
+ 1);
2191 strncpy (namebuf
, newname
, namelen
);
2192 namebuf
[namelen
] = '\0';
2194 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2195 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2197 /* Insert name in all uppercase. */
2198 for (p
= namebuf
; *p
; p
++)
2201 if (strncmp (namebuf
, newname
, namelen
))
2202 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2203 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2205 /* Insert name in all lowercase. */
2206 for (p
= namebuf
; *p
; p
++)
2209 if (strncmp (namebuf
, newname
, namelen
))
2210 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2211 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2216 /* Should never be called, as .req goes between the alias and the
2217 register name, not at the beginning of the line. */
2219 s_req (int a ATTRIBUTE_UNUSED
)
2221 as_bad (_("invalid syntax for .req directive"));
2225 s_dn (int a ATTRIBUTE_UNUSED
)
2227 as_bad (_("invalid syntax for .dn directive"));
2231 s_qn (int a ATTRIBUTE_UNUSED
)
2233 as_bad (_("invalid syntax for .qn directive"));
2236 /* The .unreq directive deletes an alias which was previously defined
2237 by .req. For example:
2243 s_unreq (int a ATTRIBUTE_UNUSED
)
2248 name
= input_line_pointer
;
2250 while (*input_line_pointer
!= 0
2251 && *input_line_pointer
!= ' '
2252 && *input_line_pointer
!= '\n')
2253 ++input_line_pointer
;
2255 saved_char
= *input_line_pointer
;
2256 *input_line_pointer
= 0;
2259 as_bad (_("invalid syntax for .unreq directive"));
2262 struct reg_entry
*reg
= hash_find (arm_reg_hsh
, name
);
2265 as_bad (_("unknown register alias '%s'"), name
);
2266 else if (reg
->builtin
)
2267 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2271 hash_delete (arm_reg_hsh
, name
);
2272 free ((char *) reg
->name
);
2279 *input_line_pointer
= saved_char
;
2280 demand_empty_rest_of_line ();
2283 /* Directives: Instruction set selection. */
2286 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2287 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2288 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2289 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2291 static enum mstate mapstate
= MAP_UNDEFINED
;
2294 mapping_state (enum mstate state
)
2297 const char * symname
;
2300 if (mapstate
== state
)
2301 /* The mapping symbol has already been emitted.
2302 There is nothing else to do. */
2311 type
= BSF_NO_FLAGS
;
2315 type
= BSF_NO_FLAGS
;
2319 type
= BSF_NO_FLAGS
;
2327 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2329 symbolP
= symbol_new (symname
, now_seg
, (valueT
) frag_now_fix (), frag_now
);
2330 symbol_table_insert (symbolP
);
2331 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2336 THUMB_SET_FUNC (symbolP
, 0);
2337 ARM_SET_THUMB (symbolP
, 0);
2338 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2342 THUMB_SET_FUNC (symbolP
, 1);
2343 ARM_SET_THUMB (symbolP
, 1);
2344 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2353 #define mapping_state(x) /* nothing */
2356 /* Find the real, Thumb encoded start of a Thumb function. */
2359 find_real_start (symbolS
* symbolP
)
2362 const char * name
= S_GET_NAME (symbolP
);
2363 symbolS
* new_target
;
2365 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2366 #define STUB_NAME ".real_start_of"
2371 /* The compiler may generate BL instructions to local labels because
2372 it needs to perform a branch to a far away location. These labels
2373 do not have a corresponding ".real_start_of" label. We check
2374 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2375 the ".real_start_of" convention for nonlocal branches. */
2376 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2379 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2380 new_target
= symbol_find (real_start
);
2382 if (new_target
== NULL
)
2384 as_warn ("Failed to find real start of function: %s\n", name
);
2385 new_target
= symbolP
;
2392 opcode_select (int width
)
2399 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2400 as_bad (_("selected processor does not support THUMB opcodes"));
2403 /* No need to force the alignment, since we will have been
2404 coming from ARM mode, which is word-aligned. */
2405 record_alignment (now_seg
, 1);
2407 mapping_state (MAP_THUMB
);
2413 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2414 as_bad (_("selected processor does not support ARM opcodes"));
2419 frag_align (2, 0, 0);
2421 record_alignment (now_seg
, 1);
2423 mapping_state (MAP_ARM
);
2427 as_bad (_("invalid instruction size selected (%d)"), width
);
2432 s_arm (int ignore ATTRIBUTE_UNUSED
)
2435 demand_empty_rest_of_line ();
2439 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2442 demand_empty_rest_of_line ();
2446 s_code (int unused ATTRIBUTE_UNUSED
)
2450 temp
= get_absolute_expression ();
2455 opcode_select (temp
);
2459 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2464 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2466 /* If we are not already in thumb mode go into it, EVEN if
2467 the target processor does not support thumb instructions.
2468 This is used by gcc/config/arm/lib1funcs.asm for example
2469 to compile interworking support functions even if the
2470 target processor should not support interworking. */
2474 record_alignment (now_seg
, 1);
2477 demand_empty_rest_of_line ();
2481 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2485 /* The following label is the name/address of the start of a Thumb function.
2486 We need to know this for the interworking support. */
2487 label_is_thumb_function_name
= TRUE
;
2490 /* Perform a .set directive, but also mark the alias as
2491 being a thumb function. */
2494 s_thumb_set (int equiv
)
2496 /* XXX the following is a duplicate of the code for s_set() in read.c
2497 We cannot just call that code as we need to get at the symbol that
2504 /* Especial apologies for the random logic:
2505 This just grew, and could be parsed much more simply!
2507 name
= input_line_pointer
;
2508 delim
= get_symbol_end ();
2509 end_name
= input_line_pointer
;
2512 if (*input_line_pointer
!= ',')
2515 as_bad (_("expected comma after name \"%s\""), name
);
2517 ignore_rest_of_line ();
2521 input_line_pointer
++;
2524 if (name
[0] == '.' && name
[1] == '\0')
2526 /* XXX - this should not happen to .thumb_set. */
2530 if ((symbolP
= symbol_find (name
)) == NULL
2531 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2534 /* When doing symbol listings, play games with dummy fragments living
2535 outside the normal fragment chain to record the file and line info
2537 if (listing
& LISTING_SYMBOLS
)
2539 extern struct list_info_struct
* listing_tail
;
2540 fragS
* dummy_frag
= xmalloc (sizeof (fragS
));
2542 memset (dummy_frag
, 0, sizeof (fragS
));
2543 dummy_frag
->fr_type
= rs_fill
;
2544 dummy_frag
->line
= listing_tail
;
2545 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2546 dummy_frag
->fr_symbol
= symbolP
;
2550 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2553 /* "set" symbols are local unless otherwise specified. */
2554 SF_SET_LOCAL (symbolP
);
2555 #endif /* OBJ_COFF */
2556 } /* Make a new symbol. */
2558 symbol_table_insert (symbolP
);
2563 && S_IS_DEFINED (symbolP
)
2564 && S_GET_SEGMENT (symbolP
) != reg_section
)
2565 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2567 pseudo_set (symbolP
);
2569 demand_empty_rest_of_line ();
2571 /* XXX Now we come to the Thumb specific bit of code. */
2573 THUMB_SET_FUNC (symbolP
, 1);
2574 ARM_SET_THUMB (symbolP
, 1);
2575 #if defined OBJ_ELF || defined OBJ_COFF
2576 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2580 /* Directives: Mode selection. */
2582 /* .syntax [unified|divided] - choose the new unified syntax
2583 (same for Arm and Thumb encoding, modulo slight differences in what
2584 can be represented) or the old divergent syntax for each mode. */
2586 s_syntax (int unused ATTRIBUTE_UNUSED
)
2590 name
= input_line_pointer
;
2591 delim
= get_symbol_end ();
2593 if (!strcasecmp (name
, "unified"))
2594 unified_syntax
= TRUE
;
2595 else if (!strcasecmp (name
, "divided"))
2596 unified_syntax
= FALSE
;
2599 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2602 *input_line_pointer
= delim
;
2603 demand_empty_rest_of_line ();
2606 /* Directives: sectioning and alignment. */
2608 /* Same as s_align_ptwo but align 0 => align 2. */
2611 s_align (int unused ATTRIBUTE_UNUSED
)
2615 long max_alignment
= 15;
2617 temp
= get_absolute_expression ();
2618 if (temp
> max_alignment
)
2619 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2622 as_bad (_("alignment negative. 0 assumed."));
2626 if (*input_line_pointer
== ',')
2628 input_line_pointer
++;
2629 temp_fill
= get_absolute_expression ();
2637 /* Only make a frag if we HAVE to. */
2638 if (temp
&& !need_pass_2
)
2639 frag_align (temp
, (int) temp_fill
, 0);
2640 demand_empty_rest_of_line ();
2642 record_alignment (now_seg
, temp
);
2646 s_bss (int ignore ATTRIBUTE_UNUSED
)
2648 /* We don't support putting frags in the BSS segment, we fake it by
2649 marking in_bss, then looking at s_skip for clues. */
2650 subseg_set (bss_section
, 0);
2651 demand_empty_rest_of_line ();
2652 mapping_state (MAP_DATA
);
2656 s_even (int ignore ATTRIBUTE_UNUSED
)
2658 /* Never make frag if expect extra pass. */
2660 frag_align (1, 0, 0);
2662 record_alignment (now_seg
, 1);
2664 demand_empty_rest_of_line ();
2667 /* Directives: Literal pools. */
2669 static literal_pool
*
2670 find_literal_pool (void)
2672 literal_pool
* pool
;
2674 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2676 if (pool
->section
== now_seg
2677 && pool
->sub_section
== now_subseg
)
2684 static literal_pool
*
2685 find_or_make_literal_pool (void)
2687 /* Next literal pool ID number. */
2688 static unsigned int latest_pool_num
= 1;
2689 literal_pool
* pool
;
2691 pool
= find_literal_pool ();
2695 /* Create a new pool. */
2696 pool
= xmalloc (sizeof (* pool
));
2700 pool
->next_free_entry
= 0;
2701 pool
->section
= now_seg
;
2702 pool
->sub_section
= now_subseg
;
2703 pool
->next
= list_of_pools
;
2704 pool
->symbol
= NULL
;
2706 /* Add it to the list. */
2707 list_of_pools
= pool
;
2710 /* New pools, and emptied pools, will have a NULL symbol. */
2711 if (pool
->symbol
== NULL
)
2713 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2714 (valueT
) 0, &zero_address_frag
);
2715 pool
->id
= latest_pool_num
++;
2722 /* Add the literal in the global 'inst'
2723 structure to the relevent literal pool. */
2726 add_to_lit_pool (void)
2728 literal_pool
* pool
;
2731 pool
= find_or_make_literal_pool ();
2733 /* Check if this literal value is already in the pool. */
2734 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2736 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2737 && (inst
.reloc
.exp
.X_op
== O_constant
)
2738 && (pool
->literals
[entry
].X_add_number
2739 == inst
.reloc
.exp
.X_add_number
)
2740 && (pool
->literals
[entry
].X_unsigned
2741 == inst
.reloc
.exp
.X_unsigned
))
2744 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2745 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2746 && (pool
->literals
[entry
].X_add_number
2747 == inst
.reloc
.exp
.X_add_number
)
2748 && (pool
->literals
[entry
].X_add_symbol
2749 == inst
.reloc
.exp
.X_add_symbol
)
2750 && (pool
->literals
[entry
].X_op_symbol
2751 == inst
.reloc
.exp
.X_op_symbol
))
2755 /* Do we need to create a new entry? */
2756 if (entry
== pool
->next_free_entry
)
2758 if (entry
>= MAX_LITERAL_POOL_SIZE
)
2760 inst
.error
= _("literal pool overflow");
2764 pool
->literals
[entry
] = inst
.reloc
.exp
;
2765 pool
->next_free_entry
+= 1;
2768 inst
.reloc
.exp
.X_op
= O_symbol
;
2769 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
2770 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
2775 /* Can't use symbol_new here, so have to create a symbol and then at
2776 a later date assign it a value. Thats what these functions do. */
2779 symbol_locate (symbolS
* symbolP
,
2780 const char * name
, /* It is copied, the caller can modify. */
2781 segT segment
, /* Segment identifier (SEG_<something>). */
2782 valueT valu
, /* Symbol value. */
2783 fragS
* frag
) /* Associated fragment. */
2785 unsigned int name_length
;
2786 char * preserved_copy_of_name
;
2788 name_length
= strlen (name
) + 1; /* +1 for \0. */
2789 obstack_grow (¬es
, name
, name_length
);
2790 preserved_copy_of_name
= obstack_finish (¬es
);
2792 #ifdef tc_canonicalize_symbol_name
2793 preserved_copy_of_name
=
2794 tc_canonicalize_symbol_name (preserved_copy_of_name
);
2797 S_SET_NAME (symbolP
, preserved_copy_of_name
);
2799 S_SET_SEGMENT (symbolP
, segment
);
2800 S_SET_VALUE (symbolP
, valu
);
2801 symbol_clear_list_pointers (symbolP
);
2803 symbol_set_frag (symbolP
, frag
);
2805 /* Link to end of symbol chain. */
2807 extern int symbol_table_frozen
;
2809 if (symbol_table_frozen
)
2813 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
2815 obj_symbol_new_hook (symbolP
);
2817 #ifdef tc_symbol_new_hook
2818 tc_symbol_new_hook (symbolP
);
2822 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
2823 #endif /* DEBUG_SYMS */
2828 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
2831 literal_pool
* pool
;
2834 pool
= find_literal_pool ();
2836 || pool
->symbol
== NULL
2837 || pool
->next_free_entry
== 0)
2840 mapping_state (MAP_DATA
);
2842 /* Align pool as you have word accesses.
2843 Only make a frag if we have to. */
2845 frag_align (2, 0, 0);
2847 record_alignment (now_seg
, 2);
2849 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
2851 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
2852 (valueT
) frag_now_fix (), frag_now
);
2853 symbol_table_insert (pool
->symbol
);
2855 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
2857 #if defined OBJ_COFF || defined OBJ_ELF
2858 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
2861 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2862 /* First output the expression in the instruction to the pool. */
2863 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
2865 /* Mark the pool as empty. */
2866 pool
->next_free_entry
= 0;
2867 pool
->symbol
= NULL
;
2871 /* Forward declarations for functions below, in the MD interface
2873 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
2874 static valueT
create_unwind_entry (int);
2875 static void start_unwind_section (const segT
, int);
2876 static void add_unwind_opcode (valueT
, int);
2877 static void flush_pending_unwind (void);
2879 /* Directives: Data. */
2882 s_arm_elf_cons (int nbytes
)
2886 #ifdef md_flush_pending_output
2887 md_flush_pending_output ();
2890 if (is_it_end_of_statement ())
2892 demand_empty_rest_of_line ();
2896 #ifdef md_cons_align
2897 md_cons_align (nbytes
);
2900 mapping_state (MAP_DATA
);
2904 char *base
= input_line_pointer
;
2908 if (exp
.X_op
!= O_symbol
)
2909 emit_expr (&exp
, (unsigned int) nbytes
);
2912 char *before_reloc
= input_line_pointer
;
2913 reloc
= parse_reloc (&input_line_pointer
);
2916 as_bad (_("unrecognized relocation suffix"));
2917 ignore_rest_of_line ();
2920 else if (reloc
== BFD_RELOC_UNUSED
)
2921 emit_expr (&exp
, (unsigned int) nbytes
);
2924 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
2925 int size
= bfd_get_reloc_size (howto
);
2927 if (reloc
== BFD_RELOC_ARM_PLT32
)
2929 as_bad (_("(plt) is only valid on branch targets"));
2930 reloc
= BFD_RELOC_UNUSED
;
2935 as_bad (_("%s relocations do not fit in %d bytes"),
2936 howto
->name
, nbytes
);
2939 /* We've parsed an expression stopping at O_symbol.
2940 But there may be more expression left now that we
2941 have parsed the relocation marker. Parse it again.
2942 XXX Surely there is a cleaner way to do this. */
2943 char *p
= input_line_pointer
;
2945 char *save_buf
= alloca (input_line_pointer
- base
);
2946 memcpy (save_buf
, base
, input_line_pointer
- base
);
2947 memmove (base
+ (input_line_pointer
- before_reloc
),
2948 base
, before_reloc
- base
);
2950 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
2952 memcpy (base
, save_buf
, p
- base
);
2954 offset
= nbytes
- size
;
2955 p
= frag_more ((int) nbytes
);
2956 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
2957 size
, &exp
, 0, reloc
);
2962 while (*input_line_pointer
++ == ',');
2964 /* Put terminator back into stream. */
2965 input_line_pointer
--;
2966 demand_empty_rest_of_line ();
2970 /* Parse a .rel31 directive. */
2973 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
2980 if (*input_line_pointer
== '1')
2981 highbit
= 0x80000000;
2982 else if (*input_line_pointer
!= '0')
2983 as_bad (_("expected 0 or 1"));
2985 input_line_pointer
++;
2986 if (*input_line_pointer
!= ',')
2987 as_bad (_("missing comma"));
2988 input_line_pointer
++;
2990 #ifdef md_flush_pending_output
2991 md_flush_pending_output ();
2994 #ifdef md_cons_align
2998 mapping_state (MAP_DATA
);
3003 md_number_to_chars (p
, highbit
, 4);
3004 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3005 BFD_RELOC_ARM_PREL31
);
3007 demand_empty_rest_of_line ();
3010 /* Directives: AEABI stack-unwind tables. */
3012 /* Parse an unwind_fnstart directive. Simply records the current location. */
3015 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3017 demand_empty_rest_of_line ();
3018 /* Mark the start of the function. */
3019 unwind
.proc_start
= expr_build_dot ();
3021 /* Reset the rest of the unwind info. */
3022 unwind
.opcode_count
= 0;
3023 unwind
.table_entry
= NULL
;
3024 unwind
.personality_routine
= NULL
;
3025 unwind
.personality_index
= -1;
3026 unwind
.frame_size
= 0;
3027 unwind
.fp_offset
= 0;
3030 unwind
.sp_restored
= 0;
3034 /* Parse a handlerdata directive. Creates the exception handling table entry
3035 for the function. */
3038 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3040 demand_empty_rest_of_line ();
3041 if (unwind
.table_entry
)
3042 as_bad (_("dupicate .handlerdata directive"));
3044 create_unwind_entry (1);
3047 /* Parse an unwind_fnend directive. Generates the index table entry. */
3050 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3056 demand_empty_rest_of_line ();
3058 /* Add eh table entry. */
3059 if (unwind
.table_entry
== NULL
)
3060 val
= create_unwind_entry (0);
3064 /* Add index table entry. This is two words. */
3065 start_unwind_section (unwind
.saved_seg
, 1);
3066 frag_align (2, 0, 0);
3067 record_alignment (now_seg
, 2);
3069 ptr
= frag_more (8);
3070 where
= frag_now_fix () - 8;
3072 /* Self relative offset of the function start. */
3073 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3074 BFD_RELOC_ARM_PREL31
);
3076 /* Indicate dependency on EHABI-defined personality routines to the
3077 linker, if it hasn't been done already. */
3078 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3079 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3081 static const char *const name
[] = {
3082 "__aeabi_unwind_cpp_pr0",
3083 "__aeabi_unwind_cpp_pr1",
3084 "__aeabi_unwind_cpp_pr2"
3086 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3087 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3088 marked_pr_dependency
|= 1 << unwind
.personality_index
;
3089 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3090 = marked_pr_dependency
;
3094 /* Inline exception table entry. */
3095 md_number_to_chars (ptr
+ 4, val
, 4);
3097 /* Self relative offset of the table entry. */
3098 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3099 BFD_RELOC_ARM_PREL31
);
3101 /* Restore the original section. */
3102 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3106 /* Parse an unwind_cantunwind directive. */
3109 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3111 demand_empty_rest_of_line ();
3112 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3113 as_bad (_("personality routine specified for cantunwind frame"));
3115 unwind
.personality_index
= -2;
3119 /* Parse a personalityindex directive. */
3122 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3126 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3127 as_bad (_("duplicate .personalityindex directive"));
3131 if (exp
.X_op
!= O_constant
3132 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3134 as_bad (_("bad personality routine number"));
3135 ignore_rest_of_line ();
3139 unwind
.personality_index
= exp
.X_add_number
;
3141 demand_empty_rest_of_line ();
3145 /* Parse a personality directive. */
3148 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3152 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3153 as_bad (_("duplicate .personality directive"));
3155 name
= input_line_pointer
;
3156 c
= get_symbol_end ();
3157 p
= input_line_pointer
;
3158 unwind
.personality_routine
= symbol_find_or_make (name
);
3160 demand_empty_rest_of_line ();
3164 /* Parse a directive saving core registers. */
3167 s_arm_unwind_save_core (void)
3173 range
= parse_reg_list (&input_line_pointer
);
3176 as_bad (_("expected register list"));
3177 ignore_rest_of_line ();
3181 demand_empty_rest_of_line ();
3183 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3184 into .unwind_save {..., sp...}. We aren't bothered about the value of
3185 ip because it is clobbered by calls. */
3186 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3187 && (range
& 0x3000) == 0x1000)
3189 unwind
.opcode_count
--;
3190 unwind
.sp_restored
= 0;
3191 range
= (range
| 0x2000) & ~0x1000;
3192 unwind
.pending_offset
= 0;
3198 /* See if we can use the short opcodes. These pop a block of up to 8
3199 registers starting with r4, plus maybe r14. */
3200 for (n
= 0; n
< 8; n
++)
3202 /* Break at the first non-saved register. */
3203 if ((range
& (1 << (n
+ 4))) == 0)
3206 /* See if there are any other bits set. */
3207 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3209 /* Use the long form. */
3210 op
= 0x8000 | ((range
>> 4) & 0xfff);
3211 add_unwind_opcode (op
, 2);
3215 /* Use the short form. */
3217 op
= 0xa8; /* Pop r14. */
3219 op
= 0xa0; /* Do not pop r14. */
3221 add_unwind_opcode (op
, 1);
3228 op
= 0xb100 | (range
& 0xf);
3229 add_unwind_opcode (op
, 2);
3232 /* Record the number of bytes pushed. */
3233 for (n
= 0; n
< 16; n
++)
3235 if (range
& (1 << n
))
3236 unwind
.frame_size
+= 4;
3241 /* Parse a directive saving FPA registers. */
3244 s_arm_unwind_save_fpa (int reg
)
3250 /* Get Number of registers to transfer. */
3251 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3254 exp
.X_op
= O_illegal
;
3256 if (exp
.X_op
!= O_constant
)
3258 as_bad (_("expected , <constant>"));
3259 ignore_rest_of_line ();
3263 num_regs
= exp
.X_add_number
;
3265 if (num_regs
< 1 || num_regs
> 4)
3267 as_bad (_("number of registers must be in the range [1:4]"));
3268 ignore_rest_of_line ();
3272 demand_empty_rest_of_line ();
3277 op
= 0xb4 | (num_regs
- 1);
3278 add_unwind_opcode (op
, 1);
3283 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3284 add_unwind_opcode (op
, 2);
3286 unwind
.frame_size
+= num_regs
* 12;
3290 /* Parse a directive saving VFP registers for ARMv6 and above. */
3293 s_arm_unwind_save_vfp_armv6 (void)
3298 int num_vfpv3_regs
= 0;
3299 int num_regs_below_16
;
3301 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3304 as_bad (_("expected register list"));
3305 ignore_rest_of_line ();
3309 demand_empty_rest_of_line ();
3311 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3312 than FSTMX/FLDMX-style ones). */
3314 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3316 num_vfpv3_regs
= count
;
3317 else if (start
+ count
> 16)
3318 num_vfpv3_regs
= start
+ count
- 16;
3320 if (num_vfpv3_regs
> 0)
3322 int start_offset
= start
> 16 ? start
- 16 : 0;
3323 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3324 add_unwind_opcode (op
, 2);
3327 /* Generate opcode for registers numbered in the range 0 .. 15. */
3328 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3329 assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3330 if (num_regs_below_16
> 0)
3332 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3333 add_unwind_opcode (op
, 2);
3336 unwind
.frame_size
+= count
* 8;
3340 /* Parse a directive saving VFP registers for pre-ARMv6. */
3343 s_arm_unwind_save_vfp (void)
3349 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3352 as_bad (_("expected register list"));
3353 ignore_rest_of_line ();
3357 demand_empty_rest_of_line ();
3362 op
= 0xb8 | (count
- 1);
3363 add_unwind_opcode (op
, 1);
3368 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3369 add_unwind_opcode (op
, 2);
3371 unwind
.frame_size
+= count
* 8 + 4;
3375 /* Parse a directive saving iWMMXt data registers. */
3378 s_arm_unwind_save_mmxwr (void)
3386 if (*input_line_pointer
== '{')
3387 input_line_pointer
++;
3391 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3395 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3400 as_tsktsk (_("register list not in ascending order"));
3403 if (*input_line_pointer
== '-')
3405 input_line_pointer
++;
3406 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3409 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3412 else if (reg
>= hi_reg
)
3414 as_bad (_("bad register range"));
3417 for (; reg
< hi_reg
; reg
++)
3421 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3423 if (*input_line_pointer
== '}')
3424 input_line_pointer
++;
3426 demand_empty_rest_of_line ();
3428 /* Generate any deferred opcodes because we're going to be looking at
3430 flush_pending_unwind ();
3432 for (i
= 0; i
< 16; i
++)
3434 if (mask
& (1 << i
))
3435 unwind
.frame_size
+= 8;
3438 /* Attempt to combine with a previous opcode. We do this because gcc
3439 likes to output separate unwind directives for a single block of
3441 if (unwind
.opcode_count
> 0)
3443 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3444 if ((i
& 0xf8) == 0xc0)
3447 /* Only merge if the blocks are contiguous. */
3450 if ((mask
& 0xfe00) == (1 << 9))
3452 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3453 unwind
.opcode_count
--;
3456 else if (i
== 6 && unwind
.opcode_count
>= 2)
3458 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3462 op
= 0xffff << (reg
- 1);
3464 && ((mask
& op
) == (1u << (reg
- 1))))
3466 op
= (1 << (reg
+ i
+ 1)) - 1;
3467 op
&= ~((1 << reg
) - 1);
3469 unwind
.opcode_count
-= 2;
3476 /* We want to generate opcodes in the order the registers have been
3477 saved, ie. descending order. */
3478 for (reg
= 15; reg
>= -1; reg
--)
3480 /* Save registers in blocks. */
3482 || !(mask
& (1 << reg
)))
3484 /* We found an unsaved reg. Generate opcodes to save the
3485 preceeding block. */
3491 op
= 0xc0 | (hi_reg
- 10);
3492 add_unwind_opcode (op
, 1);
3497 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3498 add_unwind_opcode (op
, 2);
3507 ignore_rest_of_line ();
3511 s_arm_unwind_save_mmxwcg (void)
3518 if (*input_line_pointer
== '{')
3519 input_line_pointer
++;
3523 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3527 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3533 as_tsktsk (_("register list not in ascending order"));
3536 if (*input_line_pointer
== '-')
3538 input_line_pointer
++;
3539 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3542 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3545 else if (reg
>= hi_reg
)
3547 as_bad (_("bad register range"));
3550 for (; reg
< hi_reg
; reg
++)
3554 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3556 if (*input_line_pointer
== '}')
3557 input_line_pointer
++;
3559 demand_empty_rest_of_line ();
3561 /* Generate any deferred opcodes because we're going to be looking at
3563 flush_pending_unwind ();
3565 for (reg
= 0; reg
< 16; reg
++)
3567 if (mask
& (1 << reg
))
3568 unwind
.frame_size
+= 4;
3571 add_unwind_opcode (op
, 2);
3574 ignore_rest_of_line ();
3578 /* Parse an unwind_save directive.
3579 If the argument is non-zero, this is a .vsave directive. */
3582 s_arm_unwind_save (int arch_v6
)
3585 struct reg_entry
*reg
;
3586 bfd_boolean had_brace
= FALSE
;
3588 /* Figure out what sort of save we have. */
3589 peek
= input_line_pointer
;
3597 reg
= arm_reg_parse_multi (&peek
);
3601 as_bad (_("register expected"));
3602 ignore_rest_of_line ();
3611 as_bad (_("FPA .unwind_save does not take a register list"));
3612 ignore_rest_of_line ();
3615 s_arm_unwind_save_fpa (reg
->number
);
3618 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
3621 s_arm_unwind_save_vfp_armv6 ();
3623 s_arm_unwind_save_vfp ();
3625 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
3626 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
3629 as_bad (_(".unwind_save does not support this kind of register"));
3630 ignore_rest_of_line ();
3635 /* Parse an unwind_movsp directive. */
3638 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
3644 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3647 as_bad (_(reg_expected_msgs
[REG_TYPE_RN
]));
3648 ignore_rest_of_line ();
3652 /* Optional constant. */
3653 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3655 if (immediate_for_directive (&offset
) == FAIL
)
3661 demand_empty_rest_of_line ();
3663 if (reg
== REG_SP
|| reg
== REG_PC
)
3665 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
3669 if (unwind
.fp_reg
!= REG_SP
)
3670 as_bad (_("unexpected .unwind_movsp directive"));
3672 /* Generate opcode to restore the value. */
3674 add_unwind_opcode (op
, 1);
3676 /* Record the information for later. */
3677 unwind
.fp_reg
= reg
;
3678 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3679 unwind
.sp_restored
= 1;
3682 /* Parse an unwind_pad directive. */
3685 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
3689 if (immediate_for_directive (&offset
) == FAIL
)
3694 as_bad (_("stack increment must be multiple of 4"));
3695 ignore_rest_of_line ();
3699 /* Don't generate any opcodes, just record the details for later. */
3700 unwind
.frame_size
+= offset
;
3701 unwind
.pending_offset
+= offset
;
3703 demand_empty_rest_of_line ();
3706 /* Parse an unwind_setfp directive. */
3709 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
3715 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3716 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3719 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3721 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
3723 as_bad (_("expected <reg>, <reg>"));
3724 ignore_rest_of_line ();
3728 /* Optional constant. */
3729 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3731 if (immediate_for_directive (&offset
) == FAIL
)
3737 demand_empty_rest_of_line ();
3739 if (sp_reg
!= 13 && sp_reg
!= unwind
.fp_reg
)
3741 as_bad (_("register must be either sp or set by a previous"
3742 "unwind_movsp directive"));
3746 /* Don't generate any opcodes, just record the information for later. */
3747 unwind
.fp_reg
= fp_reg
;
3750 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3752 unwind
.fp_offset
-= offset
;
3755 /* Parse an unwind_raw directive. */
3758 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
3761 /* This is an arbitrary limit. */
3762 unsigned char op
[16];
3766 if (exp
.X_op
== O_constant
3767 && skip_past_comma (&input_line_pointer
) != FAIL
)
3769 unwind
.frame_size
+= exp
.X_add_number
;
3773 exp
.X_op
= O_illegal
;
3775 if (exp
.X_op
!= O_constant
)
3777 as_bad (_("expected <offset>, <opcode>"));
3778 ignore_rest_of_line ();
3784 /* Parse the opcode. */
3789 as_bad (_("unwind opcode too long"));
3790 ignore_rest_of_line ();
3792 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
3794 as_bad (_("invalid unwind opcode"));
3795 ignore_rest_of_line ();
3798 op
[count
++] = exp
.X_add_number
;
3800 /* Parse the next byte. */
3801 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3807 /* Add the opcode bytes in reverse order. */
3809 add_unwind_opcode (op
[count
], 1);
3811 demand_empty_rest_of_line ();
3815 /* Parse a .eabi_attribute directive. */
3818 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
3821 bfd_boolean is_string
;
3828 if (exp
.X_op
!= O_constant
)
3831 tag
= exp
.X_add_number
;
3832 if (tag
== 4 || tag
== 5 || tag
== 32 || (tag
> 32 && (tag
& 1) != 0))
3837 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3839 if (tag
== 32 || !is_string
)
3842 if (exp
.X_op
!= O_constant
)
3844 as_bad (_("expected numeric constant"));
3845 ignore_rest_of_line ();
3848 i
= exp
.X_add_number
;
3850 if (tag
== Tag_compatibility
3851 && skip_past_comma (&input_line_pointer
) == FAIL
)
3853 as_bad (_("expected comma"));
3854 ignore_rest_of_line ();
3859 skip_whitespace(input_line_pointer
);
3860 if (*input_line_pointer
!= '"')
3862 input_line_pointer
++;
3863 s
= input_line_pointer
;
3864 while (*input_line_pointer
&& *input_line_pointer
!= '"')
3865 input_line_pointer
++;
3866 if (*input_line_pointer
!= '"')
3868 saved_char
= *input_line_pointer
;
3869 *input_line_pointer
= 0;
3877 if (tag
== Tag_compatibility
)
3878 elf32_arm_add_eabi_attr_compat (stdoutput
, i
, s
);
3880 elf32_arm_add_eabi_attr_string (stdoutput
, tag
, s
);
3882 elf32_arm_add_eabi_attr_int (stdoutput
, tag
, i
);
3886 *input_line_pointer
= saved_char
;
3887 input_line_pointer
++;
3889 demand_empty_rest_of_line ();
3892 as_bad (_("bad string constant"));
3893 ignore_rest_of_line ();
3896 as_bad (_("expected <tag> , <value>"));
3897 ignore_rest_of_line ();
3899 #endif /* OBJ_ELF */
3901 static void s_arm_arch (int);
3902 static void s_arm_object_arch (int);
3903 static void s_arm_cpu (int);
3904 static void s_arm_fpu (int);
3909 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
3916 if (exp
.X_op
== O_symbol
)
3917 exp
.X_op
= O_secrel
;
3919 emit_expr (&exp
, 4);
3921 while (*input_line_pointer
++ == ',');
3923 input_line_pointer
--;
3924 demand_empty_rest_of_line ();
3928 /* This table describes all the machine specific pseudo-ops the assembler
3929 has to support. The fields are:
3930 pseudo-op name without dot
3931 function to call to execute this pseudo-op
3932 Integer arg to pass to the function. */
3934 const pseudo_typeS md_pseudo_table
[] =
3936 /* Never called because '.req' does not start a line. */
3937 { "req", s_req
, 0 },
3938 /* Following two are likewise never called. */
3941 { "unreq", s_unreq
, 0 },
3942 { "bss", s_bss
, 0 },
3943 { "align", s_align
, 0 },
3944 { "arm", s_arm
, 0 },
3945 { "thumb", s_thumb
, 0 },
3946 { "code", s_code
, 0 },
3947 { "force_thumb", s_force_thumb
, 0 },
3948 { "thumb_func", s_thumb_func
, 0 },
3949 { "thumb_set", s_thumb_set
, 0 },
3950 { "even", s_even
, 0 },
3951 { "ltorg", s_ltorg
, 0 },
3952 { "pool", s_ltorg
, 0 },
3953 { "syntax", s_syntax
, 0 },
3954 { "cpu", s_arm_cpu
, 0 },
3955 { "arch", s_arm_arch
, 0 },
3956 { "object_arch", s_arm_object_arch
, 0 },
3957 { "fpu", s_arm_fpu
, 0 },
3959 { "word", s_arm_elf_cons
, 4 },
3960 { "long", s_arm_elf_cons
, 4 },
3961 { "rel31", s_arm_rel31
, 0 },
3962 { "fnstart", s_arm_unwind_fnstart
, 0 },
3963 { "fnend", s_arm_unwind_fnend
, 0 },
3964 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
3965 { "personality", s_arm_unwind_personality
, 0 },
3966 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
3967 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
3968 { "save", s_arm_unwind_save
, 0 },
3969 { "vsave", s_arm_unwind_save
, 1 },
3970 { "movsp", s_arm_unwind_movsp
, 0 },
3971 { "pad", s_arm_unwind_pad
, 0 },
3972 { "setfp", s_arm_unwind_setfp
, 0 },
3973 { "unwind_raw", s_arm_unwind_raw
, 0 },
3974 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
3978 /* These are used for dwarf. */
3982 /* These are used for dwarf2. */
3983 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
3984 { "loc", dwarf2_directive_loc
, 0 },
3985 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
3987 { "extend", float_cons
, 'x' },
3988 { "ldouble", float_cons
, 'x' },
3989 { "packed", float_cons
, 'p' },
3991 {"secrel32", pe_directive_secrel
, 0},
3996 /* Parser functions used exclusively in instruction operands. */
3998 /* Generic immediate-value read function for use in insn parsing.
3999 STR points to the beginning of the immediate (the leading #);
4000 VAL receives the value; if the value is outside [MIN, MAX]
4001 issue an error. PREFIX_OPT is true if the immediate prefix is
4005 parse_immediate (char **str
, int *val
, int min
, int max
,
4006 bfd_boolean prefix_opt
)
4009 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4010 if (exp
.X_op
!= O_constant
)
4012 inst
.error
= _("constant expression required");
4016 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4018 inst
.error
= _("immediate value out of range");
4022 *val
= exp
.X_add_number
;
4026 /* Less-generic immediate-value read function with the possibility of loading a
4027 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4028 instructions. Puts the result directly in inst.operands[i]. */
4031 parse_big_immediate (char **str
, int i
)
4036 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4038 if (exp
.X_op
== O_constant
)
4040 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4041 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4042 O_constant. We have to be careful not to break compilation for
4043 32-bit X_add_number, though. */
4044 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4046 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4047 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4048 inst
.operands
[i
].regisimm
= 1;
4051 else if (exp
.X_op
== O_big
4052 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4053 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4055 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4056 /* Bignums have their least significant bits in
4057 generic_bignum[0]. Make sure we put 32 bits in imm and
4058 32 bits in reg, in a (hopefully) portable way. */
4059 assert (parts
!= 0);
4060 inst
.operands
[i
].imm
= 0;
4061 for (j
= 0; j
< parts
; j
++, idx
++)
4062 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4063 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4064 inst
.operands
[i
].reg
= 0;
4065 for (j
= 0; j
< parts
; j
++, idx
++)
4066 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4067 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4068 inst
.operands
[i
].regisimm
= 1;
4078 /* Returns the pseudo-register number of an FPA immediate constant,
4079 or FAIL if there isn't a valid constant here. */
4082 parse_fpa_immediate (char ** str
)
4084 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4090 /* First try and match exact strings, this is to guarantee
4091 that some formats will work even for cross assembly. */
4093 for (i
= 0; fp_const
[i
]; i
++)
4095 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4099 *str
+= strlen (fp_const
[i
]);
4100 if (is_end_of_line
[(unsigned char) **str
])
4106 /* Just because we didn't get a match doesn't mean that the constant
4107 isn't valid, just that it is in a format that we don't
4108 automatically recognize. Try parsing it with the standard
4109 expression routines. */
4111 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4113 /* Look for a raw floating point number. */
4114 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4115 && is_end_of_line
[(unsigned char) *save_in
])
4117 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4119 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4121 if (words
[j
] != fp_values
[i
][j
])
4125 if (j
== MAX_LITTLENUMS
)
4133 /* Try and parse a more complex expression, this will probably fail
4134 unless the code uses a floating point prefix (eg "0f"). */
4135 save_in
= input_line_pointer
;
4136 input_line_pointer
= *str
;
4137 if (expression (&exp
) == absolute_section
4138 && exp
.X_op
== O_big
4139 && exp
.X_add_number
< 0)
4141 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4143 if (gen_to_words (words
, 5, (long) 15) == 0)
4145 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4147 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4149 if (words
[j
] != fp_values
[i
][j
])
4153 if (j
== MAX_LITTLENUMS
)
4155 *str
= input_line_pointer
;
4156 input_line_pointer
= save_in
;
4163 *str
= input_line_pointer
;
4164 input_line_pointer
= save_in
;
4165 inst
.error
= _("invalid FPA immediate expression");
4169 /* Returns 1 if a number has "quarter-precision" float format
4170 0baBbbbbbc defgh000 00000000 00000000. */
4173 is_quarter_float (unsigned imm
)
4175 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4176 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4179 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4180 0baBbbbbbc defgh000 00000000 00000000.
4181 The zero and minus-zero cases need special handling, since they can't be
4182 encoded in the "quarter-precision" float format, but can nonetheless be
4183 loaded as integer constants. */
4186 parse_qfloat_immediate (char **ccp
, int *immed
)
4190 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4191 int found_fpchar
= 0;
4193 skip_past_char (&str
, '#');
4195 /* We must not accidentally parse an integer as a floating-point number. Make
4196 sure that the value we parse is not an integer by checking for special
4197 characters '.' or 'e'.
4198 FIXME: This is a horrible hack, but doing better is tricky because type
4199 information isn't in a very usable state at parse time. */
4201 skip_whitespace (fpnum
);
4203 if (strncmp (fpnum
, "0x", 2) == 0)
4207 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4208 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4218 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4220 unsigned fpword
= 0;
4223 /* Our FP word must be 32 bits (single-precision FP). */
4224 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4226 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4230 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4243 /* Shift operands. */
4246 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4249 struct asm_shift_name
4252 enum shift_kind kind
;
4255 /* Third argument to parse_shift. */
4256 enum parse_shift_mode
4258 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4259 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4260 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4261 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4262 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4265 /* Parse a <shift> specifier on an ARM data processing instruction.
4266 This has three forms:
4268 (LSL|LSR|ASL|ASR|ROR) Rs
4269 (LSL|LSR|ASL|ASR|ROR) #imm
4272 Note that ASL is assimilated to LSL in the instruction encoding, and
4273 RRX to ROR #0 (which cannot be written as such). */
4276 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4278 const struct asm_shift_name
*shift_name
;
4279 enum shift_kind shift
;
4284 for (p
= *str
; ISALPHA (*p
); p
++)
4289 inst
.error
= _("shift expression expected");
4293 shift_name
= hash_find_n (arm_shift_hsh
, *str
, p
- *str
);
4295 if (shift_name
== NULL
)
4297 inst
.error
= _("shift expression expected");
4301 shift
= shift_name
->kind
;
4305 case NO_SHIFT_RESTRICT
:
4306 case SHIFT_IMMEDIATE
: break;
4308 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4309 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4311 inst
.error
= _("'LSL' or 'ASR' required");
4316 case SHIFT_LSL_IMMEDIATE
:
4317 if (shift
!= SHIFT_LSL
)
4319 inst
.error
= _("'LSL' required");
4324 case SHIFT_ASR_IMMEDIATE
:
4325 if (shift
!= SHIFT_ASR
)
4327 inst
.error
= _("'ASR' required");
4335 if (shift
!= SHIFT_RRX
)
4337 /* Whitespace can appear here if the next thing is a bare digit. */
4338 skip_whitespace (p
);
4340 if (mode
== NO_SHIFT_RESTRICT
4341 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4343 inst
.operands
[i
].imm
= reg
;
4344 inst
.operands
[i
].immisreg
= 1;
4346 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4349 inst
.operands
[i
].shift_kind
= shift
;
4350 inst
.operands
[i
].shifted
= 1;
4355 /* Parse a <shifter_operand> for an ARM data processing instruction:
4358 #<immediate>, <rotate>
4362 where <shift> is defined by parse_shift above, and <rotate> is a
4363 multiple of 2 between 0 and 30. Validation of immediate operands
4364 is deferred to md_apply_fix. */
4367 parse_shifter_operand (char **str
, int i
)
4372 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4374 inst
.operands
[i
].reg
= value
;
4375 inst
.operands
[i
].isreg
= 1;
4377 /* parse_shift will override this if appropriate */
4378 inst
.reloc
.exp
.X_op
= O_constant
;
4379 inst
.reloc
.exp
.X_add_number
= 0;
4381 if (skip_past_comma (str
) == FAIL
)
4384 /* Shift operation on register. */
4385 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4388 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4391 if (skip_past_comma (str
) == SUCCESS
)
4393 /* #x, y -- ie explicit rotation by Y. */
4394 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
4397 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4399 inst
.error
= _("constant expression expected");
4403 value
= expr
.X_add_number
;
4404 if (value
< 0 || value
> 30 || value
% 2 != 0)
4406 inst
.error
= _("invalid rotation");
4409 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4411 inst
.error
= _("invalid constant");
4415 /* Convert to decoded value. md_apply_fix will put it back. */
4416 inst
.reloc
.exp
.X_add_number
4417 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4418 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4421 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4422 inst
.reloc
.pc_rel
= 0;
4426 /* Group relocation information. Each entry in the table contains the
4427 textual name of the relocation as may appear in assembler source
4428 and must end with a colon.
4429 Along with this textual name are the relocation codes to be used if
4430 the corresponding instruction is an ALU instruction (ADD or SUB only),
4431 an LDR, an LDRS, or an LDC. */
4433 struct group_reloc_table_entry
4444 /* Varieties of non-ALU group relocation. */
4451 static struct group_reloc_table_entry group_reloc_table
[] =
4452 { /* Program counter relative: */
4454 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4459 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4460 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4461 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4462 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4464 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4469 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4470 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4471 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4472 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4474 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4475 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4476 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4477 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4478 /* Section base relative */
4480 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4485 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4486 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4487 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4488 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4490 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4495 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4496 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4497 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4498 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4500 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4501 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4502 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4503 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4505 /* Given the address of a pointer pointing to the textual name of a group
4506 relocation as may appear in assembler source, attempt to find its details
4507 in group_reloc_table. The pointer will be updated to the character after
4508 the trailing colon. On failure, FAIL will be returned; SUCCESS
4509 otherwise. On success, *entry will be updated to point at the relevant
4510 group_reloc_table entry. */
4513 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4516 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4518 int length
= strlen (group_reloc_table
[i
].name
);
4520 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0 &&
4521 (*str
)[length
] == ':')
4523 *out
= &group_reloc_table
[i
];
4524 *str
+= (length
+ 1);
4532 /* Parse a <shifter_operand> for an ARM data processing instruction
4533 (as for parse_shifter_operand) where group relocations are allowed:
4536 #<immediate>, <rotate>
4537 #:<group_reloc>:<expression>
4541 where <group_reloc> is one of the strings defined in group_reloc_table.
4542 The hashes are optional.
4544 Everything else is as for parse_shifter_operand. */
4546 static parse_operand_result
4547 parse_shifter_operand_group_reloc (char **str
, int i
)
4549 /* Determine if we have the sequence of characters #: or just :
4550 coming next. If we do, then we check for a group relocation.
4551 If we don't, punt the whole lot to parse_shifter_operand. */
4553 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4554 || (*str
)[0] == ':')
4556 struct group_reloc_table_entry
*entry
;
4558 if ((*str
)[0] == '#')
4563 /* Try to parse a group relocation. Anything else is an error. */
4564 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4566 inst
.error
= _("unknown group relocation");
4567 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4570 /* We now have the group relocation table entry corresponding to
4571 the name in the assembler source. Next, we parse the expression. */
4572 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4573 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4575 /* Record the relocation type (always the ALU variant here). */
4576 inst
.reloc
.type
= entry
->alu_code
;
4577 assert (inst
.reloc
.type
!= 0);
4579 return PARSE_OPERAND_SUCCESS
;
4582 return parse_shifter_operand (str
, i
) == SUCCESS
4583 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4585 /* Never reached. */
4588 /* Parse all forms of an ARM address expression. Information is written
4589 to inst.operands[i] and/or inst.reloc.
4591 Preindexed addressing (.preind=1):
4593 [Rn, #offset] .reg=Rn .reloc.exp=offset
4594 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4595 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4596 .shift_kind=shift .reloc.exp=shift_imm
4598 These three may have a trailing ! which causes .writeback to be set also.
4600 Postindexed addressing (.postind=1, .writeback=1):
4602 [Rn], #offset .reg=Rn .reloc.exp=offset
4603 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4604 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4605 .shift_kind=shift .reloc.exp=shift_imm
4607 Unindexed addressing (.preind=0, .postind=0):
4609 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4613 [Rn]{!} shorthand for [Rn,#0]{!}
4614 =immediate .isreg=0 .reloc.exp=immediate
4615 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4617 It is the caller's responsibility to check for addressing modes not
4618 supported by the instruction, and to set inst.reloc.type. */
4620 static parse_operand_result
4621 parse_address_main (char **str
, int i
, int group_relocations
,
4622 group_reloc_type group_type
)
4627 if (skip_past_char (&p
, '[') == FAIL
)
4629 if (skip_past_char (&p
, '=') == FAIL
)
4631 /* bare address - translate to PC-relative offset */
4632 inst
.reloc
.pc_rel
= 1;
4633 inst
.operands
[i
].reg
= REG_PC
;
4634 inst
.operands
[i
].isreg
= 1;
4635 inst
.operands
[i
].preind
= 1;
4637 /* else a load-constant pseudo op, no special treatment needed here */
4639 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4640 return PARSE_OPERAND_FAIL
;
4643 return PARSE_OPERAND_SUCCESS
;
4646 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4648 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4649 return PARSE_OPERAND_FAIL
;
4651 inst
.operands
[i
].reg
= reg
;
4652 inst
.operands
[i
].isreg
= 1;
4654 if (skip_past_comma (&p
) == SUCCESS
)
4656 inst
.operands
[i
].preind
= 1;
4659 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4661 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4663 inst
.operands
[i
].imm
= reg
;
4664 inst
.operands
[i
].immisreg
= 1;
4666 if (skip_past_comma (&p
) == SUCCESS
)
4667 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4668 return PARSE_OPERAND_FAIL
;
4670 else if (skip_past_char (&p
, ':') == SUCCESS
)
4672 /* FIXME: '@' should be used here, but it's filtered out by generic
4673 code before we get to see it here. This may be subject to
4676 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4677 if (exp
.X_op
!= O_constant
)
4679 inst
.error
= _("alignment must be constant");
4680 return PARSE_OPERAND_FAIL
;
4682 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4683 inst
.operands
[i
].immisalign
= 1;
4684 /* Alignments are not pre-indexes. */
4685 inst
.operands
[i
].preind
= 0;
4689 if (inst
.operands
[i
].negative
)
4691 inst
.operands
[i
].negative
= 0;
4695 if (group_relocations
&&
4696 ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
4699 struct group_reloc_table_entry
*entry
;
4701 /* Skip over the #: or : sequence. */
4707 /* Try to parse a group relocation. Anything else is an
4709 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
4711 inst
.error
= _("unknown group relocation");
4712 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4715 /* We now have the group relocation table entry corresponding to
4716 the name in the assembler source. Next, we parse the
4718 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4719 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4721 /* Record the relocation type. */
4725 inst
.reloc
.type
= entry
->ldr_code
;
4729 inst
.reloc
.type
= entry
->ldrs_code
;
4733 inst
.reloc
.type
= entry
->ldc_code
;
4740 if (inst
.reloc
.type
== 0)
4742 inst
.error
= _("this group relocation is not allowed on this instruction");
4743 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4747 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4748 return PARSE_OPERAND_FAIL
;
4752 if (skip_past_char (&p
, ']') == FAIL
)
4754 inst
.error
= _("']' expected");
4755 return PARSE_OPERAND_FAIL
;
4758 if (skip_past_char (&p
, '!') == SUCCESS
)
4759 inst
.operands
[i
].writeback
= 1;
4761 else if (skip_past_comma (&p
) == SUCCESS
)
4763 if (skip_past_char (&p
, '{') == SUCCESS
)
4765 /* [Rn], {expr} - unindexed, with option */
4766 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
4767 0, 255, TRUE
) == FAIL
)
4768 return PARSE_OPERAND_FAIL
;
4770 if (skip_past_char (&p
, '}') == FAIL
)
4772 inst
.error
= _("'}' expected at end of 'option' field");
4773 return PARSE_OPERAND_FAIL
;
4775 if (inst
.operands
[i
].preind
)
4777 inst
.error
= _("cannot combine index with option");
4778 return PARSE_OPERAND_FAIL
;
4781 return PARSE_OPERAND_SUCCESS
;
4785 inst
.operands
[i
].postind
= 1;
4786 inst
.operands
[i
].writeback
= 1;
4788 if (inst
.operands
[i
].preind
)
4790 inst
.error
= _("cannot combine pre- and post-indexing");
4791 return PARSE_OPERAND_FAIL
;
4795 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4797 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4799 /* We might be using the immediate for alignment already. If we
4800 are, OR the register number into the low-order bits. */
4801 if (inst
.operands
[i
].immisalign
)
4802 inst
.operands
[i
].imm
|= reg
;
4804 inst
.operands
[i
].imm
= reg
;
4805 inst
.operands
[i
].immisreg
= 1;
4807 if (skip_past_comma (&p
) == SUCCESS
)
4808 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4809 return PARSE_OPERAND_FAIL
;
4813 if (inst
.operands
[i
].negative
)
4815 inst
.operands
[i
].negative
= 0;
4818 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4819 return PARSE_OPERAND_FAIL
;
4824 /* If at this point neither .preind nor .postind is set, we have a
4825 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
4826 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
4828 inst
.operands
[i
].preind
= 1;
4829 inst
.reloc
.exp
.X_op
= O_constant
;
4830 inst
.reloc
.exp
.X_add_number
= 0;
4833 return PARSE_OPERAND_SUCCESS
;
4837 parse_address (char **str
, int i
)
4839 return parse_address_main (str
, i
, 0, 0) == PARSE_OPERAND_SUCCESS
4843 static parse_operand_result
4844 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
4846 return parse_address_main (str
, i
, 1, type
);
4849 /* Parse an operand for a MOVW or MOVT instruction. */
4851 parse_half (char **str
)
4856 skip_past_char (&p
, '#');
4857 if (strncasecmp (p
, ":lower16:", 9) == 0)
4858 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
4859 else if (strncasecmp (p
, ":upper16:", 9) == 0)
4860 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
4862 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4868 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4871 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4873 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4875 inst
.error
= _("constant expression expected");
4878 if (inst
.reloc
.exp
.X_add_number
< 0
4879 || inst
.reloc
.exp
.X_add_number
> 0xffff)
4881 inst
.error
= _("immediate value out of range");
4889 /* Miscellaneous. */
4891 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
4892 or a bitmask suitable to be or-ed into the ARM msr instruction. */
4894 parse_psr (char **str
)
4897 unsigned long psr_field
;
4898 const struct asm_psr
*psr
;
4901 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
4902 feature for ease of use and backwards compatibility. */
4904 if (strncasecmp (p
, "SPSR", 4) == 0)
4905 psr_field
= SPSR_BIT
;
4906 else if (strncasecmp (p
, "CPSR", 4) == 0)
4913 while (ISALNUM (*p
) || *p
== '_');
4915 psr
= hash_find_n (arm_v7m_psr_hsh
, start
, p
- start
);
4926 /* A suffix follows. */
4932 while (ISALNUM (*p
) || *p
== '_');
4934 psr
= hash_find_n (arm_psr_hsh
, start
, p
- start
);
4938 psr_field
|= psr
->field
;
4943 goto error
; /* Garbage after "[CS]PSR". */
4945 psr_field
|= (PSR_c
| PSR_f
);
4951 inst
.error
= _("flag for {c}psr instruction expected");
4955 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
4956 value suitable for splatting into the AIF field of the instruction. */
4959 parse_cps_flags (char **str
)
4968 case '\0': case ',':
4971 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
4972 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
4973 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
4976 inst
.error
= _("unrecognized CPS flag");
4981 if (saw_a_flag
== 0)
4983 inst
.error
= _("missing CPS flags");
4991 /* Parse an endian specifier ("BE" or "LE", case insensitive);
4992 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
4995 parse_endian_specifier (char **str
)
5000 if (strncasecmp (s
, "BE", 2))
5002 else if (strncasecmp (s
, "LE", 2))
5006 inst
.error
= _("valid endian specifiers are be or le");
5010 if (ISALNUM (s
[2]) || s
[2] == '_')
5012 inst
.error
= _("valid endian specifiers are be or le");
5017 return little_endian
;
5020 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5021 value suitable for poking into the rotate field of an sxt or sxta
5022 instruction, or FAIL on error. */
5025 parse_ror (char **str
)
5030 if (strncasecmp (s
, "ROR", 3) == 0)
5034 inst
.error
= _("missing rotation field after comma");
5038 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5043 case 0: *str
= s
; return 0x0;
5044 case 8: *str
= s
; return 0x1;
5045 case 16: *str
= s
; return 0x2;
5046 case 24: *str
= s
; return 0x3;
5049 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5054 /* Parse a conditional code (from conds[] below). The value returned is in the
5055 range 0 .. 14, or FAIL. */
5057 parse_cond (char **str
)
5060 const struct asm_cond
*c
;
5063 while (ISALPHA (*q
))
5066 c
= hash_find_n (arm_cond_hsh
, p
, q
- p
);
5069 inst
.error
= _("condition required");
5077 /* Parse an option for a barrier instruction. Returns the encoding for the
5080 parse_barrier (char **str
)
5083 const struct asm_barrier_opt
*o
;
5086 while (ISALPHA (*q
))
5089 o
= hash_find_n (arm_barrier_opt_hsh
, p
, q
- p
);
5097 /* Parse the operands of a table branch instruction. Similar to a memory
5100 parse_tb (char **str
)
5105 if (skip_past_char (&p
, '[') == FAIL
)
5107 inst
.error
= _("'[' expected");
5111 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5113 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5116 inst
.operands
[0].reg
= reg
;
5118 if (skip_past_comma (&p
) == FAIL
)
5120 inst
.error
= _("',' expected");
5124 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5126 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5129 inst
.operands
[0].imm
= reg
;
5131 if (skip_past_comma (&p
) == SUCCESS
)
5133 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5135 if (inst
.reloc
.exp
.X_add_number
!= 1)
5137 inst
.error
= _("invalid shift");
5140 inst
.operands
[0].shifted
= 1;
5143 if (skip_past_char (&p
, ']') == FAIL
)
5145 inst
.error
= _("']' expected");
5152 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5153 information on the types the operands can take and how they are encoded.
5154 Up to four operands may be read; this function handles setting the
5155 ".present" field for each read operand itself.
5156 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5157 else returns FAIL. */
5160 parse_neon_mov (char **str
, int *which_operand
)
5162 int i
= *which_operand
, val
;
5163 enum arm_reg_type rtype
;
5165 struct neon_type_el optype
;
5167 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5169 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5170 inst
.operands
[i
].reg
= val
;
5171 inst
.operands
[i
].isscalar
= 1;
5172 inst
.operands
[i
].vectype
= optype
;
5173 inst
.operands
[i
++].present
= 1;
5175 if (skip_past_comma (&ptr
) == FAIL
)
5178 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5181 inst
.operands
[i
].reg
= val
;
5182 inst
.operands
[i
].isreg
= 1;
5183 inst
.operands
[i
].present
= 1;
5185 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5188 /* Cases 0, 1, 2, 3, 5 (D only). */
5189 if (skip_past_comma (&ptr
) == FAIL
)
5192 inst
.operands
[i
].reg
= val
;
5193 inst
.operands
[i
].isreg
= 1;
5194 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5195 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5196 inst
.operands
[i
].isvec
= 1;
5197 inst
.operands
[i
].vectype
= optype
;
5198 inst
.operands
[i
++].present
= 1;
5200 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5202 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5203 Case 13: VMOV <Sd>, <Rm> */
5204 inst
.operands
[i
].reg
= val
;
5205 inst
.operands
[i
].isreg
= 1;
5206 inst
.operands
[i
].present
= 1;
5208 if (rtype
== REG_TYPE_NQ
)
5210 first_error (_("can't use Neon quad register here"));
5213 else if (rtype
!= REG_TYPE_VFS
)
5216 if (skip_past_comma (&ptr
) == FAIL
)
5218 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5220 inst
.operands
[i
].reg
= val
;
5221 inst
.operands
[i
].isreg
= 1;
5222 inst
.operands
[i
].present
= 1;
5225 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5226 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5227 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5228 Case 10: VMOV.F32 <Sd>, #<imm>
5229 Case 11: VMOV.F64 <Dd>, #<imm> */
5230 inst
.operands
[i
].immisfloat
= 1;
5231 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5232 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5233 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5235 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5238 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5239 Case 1: VMOV<c><q> <Dd>, <Dm>
5240 Case 8: VMOV.F32 <Sd>, <Sm>
5241 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5243 inst
.operands
[i
].reg
= val
;
5244 inst
.operands
[i
].isreg
= 1;
5245 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5246 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5247 inst
.operands
[i
].isvec
= 1;
5248 inst
.operands
[i
].vectype
= optype
;
5249 inst
.operands
[i
].present
= 1;
5251 if (skip_past_comma (&ptr
) == SUCCESS
)
5256 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5259 inst
.operands
[i
].reg
= val
;
5260 inst
.operands
[i
].isreg
= 1;
5261 inst
.operands
[i
++].present
= 1;
5263 if (skip_past_comma (&ptr
) == FAIL
)
5266 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5269 inst
.operands
[i
].reg
= val
;
5270 inst
.operands
[i
].isreg
= 1;
5271 inst
.operands
[i
++].present
= 1;
5276 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5280 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5283 inst
.operands
[i
].reg
= val
;
5284 inst
.operands
[i
].isreg
= 1;
5285 inst
.operands
[i
++].present
= 1;
5287 if (skip_past_comma (&ptr
) == FAIL
)
5290 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5292 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5293 inst
.operands
[i
].reg
= val
;
5294 inst
.operands
[i
].isscalar
= 1;
5295 inst
.operands
[i
].present
= 1;
5296 inst
.operands
[i
].vectype
= optype
;
5298 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5300 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5301 inst
.operands
[i
].reg
= val
;
5302 inst
.operands
[i
].isreg
= 1;
5303 inst
.operands
[i
++].present
= 1;
5305 if (skip_past_comma (&ptr
) == FAIL
)
5308 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5311 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5315 inst
.operands
[i
].reg
= val
;
5316 inst
.operands
[i
].isreg
= 1;
5317 inst
.operands
[i
].isvec
= 1;
5318 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5319 inst
.operands
[i
].vectype
= optype
;
5320 inst
.operands
[i
].present
= 1;
5322 if (rtype
== REG_TYPE_VFS
)
5326 if (skip_past_comma (&ptr
) == FAIL
)
5328 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5331 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5334 inst
.operands
[i
].reg
= val
;
5335 inst
.operands
[i
].isreg
= 1;
5336 inst
.operands
[i
].isvec
= 1;
5337 inst
.operands
[i
].issingle
= 1;
5338 inst
.operands
[i
].vectype
= optype
;
5339 inst
.operands
[i
].present
= 1;
5342 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5346 inst
.operands
[i
].reg
= val
;
5347 inst
.operands
[i
].isreg
= 1;
5348 inst
.operands
[i
].isvec
= 1;
5349 inst
.operands
[i
].issingle
= 1;
5350 inst
.operands
[i
].vectype
= optype
;
5351 inst
.operands
[i
++].present
= 1;
5356 first_error (_("parse error"));
5360 /* Successfully parsed the operands. Update args. */
5366 first_error (_("expected comma"));
5370 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5374 /* Matcher codes for parse_operands. */
5375 enum operand_parse_code
5377 OP_stop
, /* end of line */
5379 OP_RR
, /* ARM register */
5380 OP_RRnpc
, /* ARM register, not r15 */
5381 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5382 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5383 OP_RCP
, /* Coprocessor number */
5384 OP_RCN
, /* Coprocessor register */
5385 OP_RF
, /* FPA register */
5386 OP_RVS
, /* VFP single precision register */
5387 OP_RVD
, /* VFP double precision register (0..15) */
5388 OP_RND
, /* Neon double precision register (0..31) */
5389 OP_RNQ
, /* Neon quad precision register */
5390 OP_RVSD
, /* VFP single or double precision register */
5391 OP_RNDQ
, /* Neon double or quad precision register */
5392 OP_RNSDQ
, /* Neon single, double or quad precision register */
5393 OP_RNSC
, /* Neon scalar D[X] */
5394 OP_RVC
, /* VFP control register */
5395 OP_RMF
, /* Maverick F register */
5396 OP_RMD
, /* Maverick D register */
5397 OP_RMFX
, /* Maverick FX register */
5398 OP_RMDX
, /* Maverick DX register */
5399 OP_RMAX
, /* Maverick AX register */
5400 OP_RMDS
, /* Maverick DSPSC register */
5401 OP_RIWR
, /* iWMMXt wR register */
5402 OP_RIWC
, /* iWMMXt wC register */
5403 OP_RIWG
, /* iWMMXt wCG register */
5404 OP_RXA
, /* XScale accumulator register */
5406 OP_REGLST
, /* ARM register list */
5407 OP_VRSLST
, /* VFP single-precision register list */
5408 OP_VRDLST
, /* VFP double-precision register list */
5409 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5410 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5411 OP_NSTRLST
, /* Neon element/structure list */
5413 OP_NILO
, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5414 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5415 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5416 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5417 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5418 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5419 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5420 OP_VMOV
, /* Neon VMOV operands. */
5421 OP_RNDQ_IMVNb
,/* Neon D or Q reg, or immediate good for VMVN. */
5422 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5423 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5425 OP_I0
, /* immediate zero */
5426 OP_I7
, /* immediate value 0 .. 7 */
5427 OP_I15
, /* 0 .. 15 */
5428 OP_I16
, /* 1 .. 16 */
5429 OP_I16z
, /* 0 .. 16 */
5430 OP_I31
, /* 0 .. 31 */
5431 OP_I31w
, /* 0 .. 31, optional trailing ! */
5432 OP_I32
, /* 1 .. 32 */
5433 OP_I32z
, /* 0 .. 32 */
5434 OP_I63
, /* 0 .. 63 */
5435 OP_I63s
, /* -64 .. 63 */
5436 OP_I64
, /* 1 .. 64 */
5437 OP_I64z
, /* 0 .. 64 */
5438 OP_I255
, /* 0 .. 255 */
5440 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5441 OP_I7b
, /* 0 .. 7 */
5442 OP_I15b
, /* 0 .. 15 */
5443 OP_I31b
, /* 0 .. 31 */
5445 OP_SH
, /* shifter operand */
5446 OP_SHG
, /* shifter operand with possible group relocation */
5447 OP_ADDR
, /* Memory address expression (any mode) */
5448 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5449 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5450 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5451 OP_EXP
, /* arbitrary expression */
5452 OP_EXPi
, /* same, with optional immediate prefix */
5453 OP_EXPr
, /* same, with optional relocation suffix */
5454 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5456 OP_CPSF
, /* CPS flags */
5457 OP_ENDI
, /* Endianness specifier */
5458 OP_PSR
, /* CPSR/SPSR mask for msr */
5459 OP_COND
, /* conditional code */
5460 OP_TB
, /* Table branch. */
5462 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5463 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5465 OP_RRnpc_I0
, /* ARM register or literal 0 */
5466 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5467 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5468 OP_RF_IF
, /* FPA register or immediate */
5469 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5470 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5472 /* Optional operands. */
5473 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5474 OP_oI31b
, /* 0 .. 31 */
5475 OP_oI32b
, /* 1 .. 32 */
5476 OP_oIffffb
, /* 0 .. 65535 */
5477 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5479 OP_oRR
, /* ARM register */
5480 OP_oRRnpc
, /* ARM register, not the PC */
5481 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5482 OP_oRND
, /* Optional Neon double precision register */
5483 OP_oRNQ
, /* Optional Neon quad precision register */
5484 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5485 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5486 OP_oSHll
, /* LSL immediate */
5487 OP_oSHar
, /* ASR immediate */
5488 OP_oSHllar
, /* LSL or ASR immediate */
5489 OP_oROR
, /* ROR 0/8/16/24 */
5490 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5492 OP_FIRST_OPTIONAL
= OP_oI7b
5495 /* Generic instruction operand parser. This does no encoding and no
5496 semantic validation; it merely squirrels values away in the inst
5497 structure. Returns SUCCESS or FAIL depending on whether the
5498 specified grammar matched. */
5500 parse_operands (char *str
, const unsigned char *pattern
)
5502 unsigned const char *upat
= pattern
;
5503 char *backtrack_pos
= 0;
5504 const char *backtrack_error
= 0;
5505 int i
, val
, backtrack_index
= 0;
5506 enum arm_reg_type rtype
;
5507 parse_operand_result result
;
5509 #define po_char_or_fail(chr) do { \
5510 if (skip_past_char (&str, chr) == FAIL) \
5514 #define po_reg_or_fail(regtype) do { \
5515 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5516 &inst.operands[i].vectype); \
5519 first_error (_(reg_expected_msgs[regtype])); \
5522 inst.operands[i].reg = val; \
5523 inst.operands[i].isreg = 1; \
5524 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5525 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5526 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5527 || rtype == REG_TYPE_VFD \
5528 || rtype == REG_TYPE_NQ); \
5531 #define po_reg_or_goto(regtype, label) do { \
5532 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5533 &inst.operands[i].vectype); \
5537 inst.operands[i].reg = val; \
5538 inst.operands[i].isreg = 1; \
5539 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5540 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5541 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5542 || rtype == REG_TYPE_VFD \
5543 || rtype == REG_TYPE_NQ); \
5546 #define po_imm_or_fail(min, max, popt) do { \
5547 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5549 inst.operands[i].imm = val; \
5552 #define po_scalar_or_goto(elsz, label) do { \
5553 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \
5556 inst.operands[i].reg = val; \
5557 inst.operands[i].isscalar = 1; \
5560 #define po_misc_or_fail(expr) do { \
5565 #define po_misc_or_fail_no_backtrack(expr) do { \
5567 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
5568 backtrack_pos = 0; \
5569 if (result != PARSE_OPERAND_SUCCESS) \
5573 skip_whitespace (str
);
5575 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5577 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5579 /* Remember where we are in case we need to backtrack. */
5580 assert (!backtrack_pos
);
5581 backtrack_pos
= str
;
5582 backtrack_error
= inst
.error
;
5583 backtrack_index
= i
;
5586 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
5587 po_char_or_fail (',');
5595 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5596 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5597 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5598 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5599 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5600 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5602 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5603 case OP_RVC
: po_reg_or_fail (REG_TYPE_VFC
); break;
5604 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5605 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5606 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5607 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5608 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5609 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5610 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5611 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5612 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5613 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5615 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
5617 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
5618 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
5620 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
5622 /* Neon scalar. Using an element size of 8 means that some invalid
5623 scalars are accepted here, so deal with those in later code. */
5624 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
5626 /* WARNING: We can expand to two operands here. This has the potential
5627 to totally confuse the backtracking mechanism! It will be OK at
5628 least as long as we don't try to use optional args as well,
5632 po_reg_or_goto (REG_TYPE_NDQ
, try_imm
);
5633 inst
.operands
[i
].present
= 1;
5635 skip_past_comma (&str
);
5636 po_reg_or_goto (REG_TYPE_NDQ
, one_reg_only
);
5639 /* Optional register operand was omitted. Unfortunately, it's in
5640 operands[i-1] and we need it to be in inst.operands[i]. Fix that
5641 here (this is a bit grotty). */
5642 inst
.operands
[i
] = inst
.operands
[i
-1];
5643 inst
.operands
[i
-1].present
= 0;
5646 /* There's a possibility of getting a 64-bit immediate here, so
5647 we need special handling. */
5648 if (parse_big_immediate (&str
, i
) == FAIL
)
5650 inst
.error
= _("immediate value is out of range");
5658 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
5661 po_imm_or_fail (0, 0, TRUE
);
5666 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
5671 po_scalar_or_goto (8, try_rr
);
5674 po_reg_or_fail (REG_TYPE_RN
);
5680 po_scalar_or_goto (8, try_nsdq
);
5683 po_reg_or_fail (REG_TYPE_NSDQ
);
5689 po_scalar_or_goto (8, try_ndq
);
5692 po_reg_or_fail (REG_TYPE_NDQ
);
5698 po_scalar_or_goto (8, try_vfd
);
5701 po_reg_or_fail (REG_TYPE_VFD
);
5706 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
5707 not careful then bad things might happen. */
5708 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
5713 po_reg_or_goto (REG_TYPE_NDQ
, try_mvnimm
);
5716 /* There's a possibility of getting a 64-bit immediate here, so
5717 we need special handling. */
5718 if (parse_big_immediate (&str
, i
) == FAIL
)
5720 inst
.error
= _("immediate value is out of range");
5728 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
5731 po_imm_or_fail (0, 63, TRUE
);
5736 po_char_or_fail ('[');
5737 po_reg_or_fail (REG_TYPE_RN
);
5738 po_char_or_fail (']');
5743 po_reg_or_fail (REG_TYPE_RN
);
5744 if (skip_past_char (&str
, '!') == SUCCESS
)
5745 inst
.operands
[i
].writeback
= 1;
5749 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
5750 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
5751 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
5752 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
5753 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
5754 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
5755 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
5756 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
5757 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
5758 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
5759 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
5760 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
5762 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
5764 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
5765 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
5767 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
5768 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
5769 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
5771 /* Immediate variants */
5773 po_char_or_fail ('{');
5774 po_imm_or_fail (0, 255, TRUE
);
5775 po_char_or_fail ('}');
5779 /* The expression parser chokes on a trailing !, so we have
5780 to find it first and zap it. */
5783 while (*s
&& *s
!= ',')
5788 inst
.operands
[i
].writeback
= 1;
5790 po_imm_or_fail (0, 31, TRUE
);
5798 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5803 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5808 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5810 if (inst
.reloc
.exp
.X_op
== O_symbol
)
5812 val
= parse_reloc (&str
);
5815 inst
.error
= _("unrecognized relocation suffix");
5818 else if (val
!= BFD_RELOC_UNUSED
)
5820 inst
.operands
[i
].imm
= val
;
5821 inst
.operands
[i
].hasreloc
= 1;
5826 /* Operand for MOVW or MOVT. */
5828 po_misc_or_fail (parse_half (&str
));
5831 /* Register or expression */
5832 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
5833 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
5835 /* Register or immediate */
5836 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
5837 I0
: po_imm_or_fail (0, 0, FALSE
); break;
5839 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
5841 if (!is_immediate_prefix (*str
))
5844 val
= parse_fpa_immediate (&str
);
5847 /* FPA immediates are encoded as registers 8-15.
5848 parse_fpa_immediate has already applied the offset. */
5849 inst
.operands
[i
].reg
= val
;
5850 inst
.operands
[i
].isreg
= 1;
5853 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
5854 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
5856 /* Two kinds of register */
5859 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5861 || (rege
->type
!= REG_TYPE_MMXWR
5862 && rege
->type
!= REG_TYPE_MMXWC
5863 && rege
->type
!= REG_TYPE_MMXWCG
))
5865 inst
.error
= _("iWMMXt data or control register expected");
5868 inst
.operands
[i
].reg
= rege
->number
;
5869 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
5875 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5877 || (rege
->type
!= REG_TYPE_MMXWC
5878 && rege
->type
!= REG_TYPE_MMXWCG
))
5880 inst
.error
= _("iWMMXt control register expected");
5883 inst
.operands
[i
].reg
= rege
->number
;
5884 inst
.operands
[i
].isreg
= 1;
5889 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
5890 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
5891 case OP_oROR
: val
= parse_ror (&str
); break;
5892 case OP_PSR
: val
= parse_psr (&str
); break;
5893 case OP_COND
: val
= parse_cond (&str
); break;
5894 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
5897 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
5898 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
5901 val
= parse_psr (&str
);
5905 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
5908 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
5910 if (strncasecmp (str
, "APSR_", 5) == 0)
5917 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
5918 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
5919 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
5920 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
5921 default: found
= 16;
5925 inst
.operands
[i
].isvec
= 1;
5932 po_misc_or_fail (parse_tb (&str
));
5935 /* Register lists */
5937 val
= parse_reg_list (&str
);
5940 inst
.operands
[1].writeback
= 1;
5946 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
5950 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
5954 /* Allow Q registers too. */
5955 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5960 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5962 inst
.operands
[i
].issingle
= 1;
5967 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5972 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
5973 &inst
.operands
[i
].vectype
);
5976 /* Addressing modes */
5978 po_misc_or_fail (parse_address (&str
, i
));
5982 po_misc_or_fail_no_backtrack (
5983 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
5987 po_misc_or_fail_no_backtrack (
5988 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
5992 po_misc_or_fail_no_backtrack (
5993 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
5997 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6001 po_misc_or_fail_no_backtrack (
6002 parse_shifter_operand_group_reloc (&str
, i
));
6006 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6010 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6014 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6018 as_fatal ("unhandled operand code %d", upat
[i
]);
6021 /* Various value-based sanity checks and shared operations. We
6022 do not signal immediate failures for the register constraints;
6023 this allows a syntax error to take precedence. */
6032 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6033 inst
.error
= BAD_PC
;
6051 inst
.operands
[i
].imm
= val
;
6058 /* If we get here, this operand was successfully parsed. */
6059 inst
.operands
[i
].present
= 1;
6063 inst
.error
= BAD_ARGS
;
6068 /* The parse routine should already have set inst.error, but set a
6069 defaut here just in case. */
6071 inst
.error
= _("syntax error");
6075 /* Do not backtrack over a trailing optional argument that
6076 absorbed some text. We will only fail again, with the
6077 'garbage following instruction' error message, which is
6078 probably less helpful than the current one. */
6079 if (backtrack_index
== i
&& backtrack_pos
!= str
6080 && upat
[i
+1] == OP_stop
)
6083 inst
.error
= _("syntax error");
6087 /* Try again, skipping the optional argument at backtrack_pos. */
6088 str
= backtrack_pos
;
6089 inst
.error
= backtrack_error
;
6090 inst
.operands
[backtrack_index
].present
= 0;
6091 i
= backtrack_index
;
6095 /* Check that we have parsed all the arguments. */
6096 if (*str
!= '\0' && !inst
.error
)
6097 inst
.error
= _("garbage following instruction");
6099 return inst
.error
? FAIL
: SUCCESS
;
6102 #undef po_char_or_fail
6103 #undef po_reg_or_fail
6104 #undef po_reg_or_goto
6105 #undef po_imm_or_fail
6106 #undef po_scalar_or_fail
6108 /* Shorthand macro for instruction encoding functions issuing errors. */
6109 #define constraint(expr, err) do { \
6117 /* Functions for operand encoding. ARM, then Thumb. */
6119 #define rotate_left(v, n) (v << n | v >> (32 - n))
6121 /* If VAL can be encoded in the immediate field of an ARM instruction,
6122 return the encoded form. Otherwise, return FAIL. */
6125 encode_arm_immediate (unsigned int val
)
6129 for (i
= 0; i
< 32; i
+= 2)
6130 if ((a
= rotate_left (val
, i
)) <= 0xff)
6131 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6136 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6137 return the encoded form. Otherwise, return FAIL. */
6139 encode_thumb32_immediate (unsigned int val
)
6146 for (i
= 1; i
<= 24; i
++)
6149 if ((val
& ~(0xff << i
)) == 0)
6150 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6154 if (val
== ((a
<< 16) | a
))
6156 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6160 if (val
== ((a
<< 16) | a
))
6161 return 0x200 | (a
>> 8);
6165 /* Encode a VFP SP or DP register number into inst.instruction. */
6168 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6170 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6173 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
6176 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6179 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6184 first_error (_("D register out of range for selected VFP version"));
6192 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6196 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6200 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6204 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6208 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6212 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6220 /* Encode a <shift> in an ARM-format instruction. The immediate,
6221 if any, is handled by md_apply_fix. */
6223 encode_arm_shift (int i
)
6225 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6226 inst
.instruction
|= SHIFT_ROR
<< 5;
6229 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6230 if (inst
.operands
[i
].immisreg
)
6232 inst
.instruction
|= SHIFT_BY_REG
;
6233 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6236 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6241 encode_arm_shifter_operand (int i
)
6243 if (inst
.operands
[i
].isreg
)
6245 inst
.instruction
|= inst
.operands
[i
].reg
;
6246 encode_arm_shift (i
);
6249 inst
.instruction
|= INST_IMMEDIATE
;
6252 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6254 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6256 assert (inst
.operands
[i
].isreg
);
6257 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6259 if (inst
.operands
[i
].preind
)
6263 inst
.error
= _("instruction does not accept preindexed addressing");
6266 inst
.instruction
|= PRE_INDEX
;
6267 if (inst
.operands
[i
].writeback
)
6268 inst
.instruction
|= WRITE_BACK
;
6271 else if (inst
.operands
[i
].postind
)
6273 assert (inst
.operands
[i
].writeback
);
6275 inst
.instruction
|= WRITE_BACK
;
6277 else /* unindexed - only for coprocessor */
6279 inst
.error
= _("instruction does not accept unindexed addressing");
6283 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6284 && (((inst
.instruction
& 0x000f0000) >> 16)
6285 == ((inst
.instruction
& 0x0000f000) >> 12)))
6286 as_warn ((inst
.instruction
& LOAD_BIT
)
6287 ? _("destination register same as write-back base")
6288 : _("source register same as write-back base"));
6291 /* inst.operands[i] was set up by parse_address. Encode it into an
6292 ARM-format mode 2 load or store instruction. If is_t is true,
6293 reject forms that cannot be used with a T instruction (i.e. not
6296 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6298 encode_arm_addr_mode_common (i
, is_t
);
6300 if (inst
.operands
[i
].immisreg
)
6302 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6303 inst
.instruction
|= inst
.operands
[i
].imm
;
6304 if (!inst
.operands
[i
].negative
)
6305 inst
.instruction
|= INDEX_UP
;
6306 if (inst
.operands
[i
].shifted
)
6308 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6309 inst
.instruction
|= SHIFT_ROR
<< 5;
6312 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6313 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6317 else /* immediate offset in inst.reloc */
6319 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6320 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6324 /* inst.operands[i] was set up by parse_address. Encode it into an
6325 ARM-format mode 3 load or store instruction. Reject forms that
6326 cannot be used with such instructions. If is_t is true, reject
6327 forms that cannot be used with a T instruction (i.e. not
6330 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6332 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6334 inst
.error
= _("instruction does not accept scaled register index");
6338 encode_arm_addr_mode_common (i
, is_t
);
6340 if (inst
.operands
[i
].immisreg
)
6342 inst
.instruction
|= inst
.operands
[i
].imm
;
6343 if (!inst
.operands
[i
].negative
)
6344 inst
.instruction
|= INDEX_UP
;
6346 else /* immediate offset in inst.reloc */
6348 inst
.instruction
|= HWOFFSET_IMM
;
6349 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6350 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6354 /* inst.operands[i] was set up by parse_address. Encode it into an
6355 ARM-format instruction. Reject all forms which cannot be encoded
6356 into a coprocessor load/store instruction. If wb_ok is false,
6357 reject use of writeback; if unind_ok is false, reject use of
6358 unindexed addressing. If reloc_override is not 0, use it instead
6359 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6360 (in which case it is preserved). */
6363 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6365 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6367 assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6369 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6371 assert (!inst
.operands
[i
].writeback
);
6374 inst
.error
= _("instruction does not support unindexed addressing");
6377 inst
.instruction
|= inst
.operands
[i
].imm
;
6378 inst
.instruction
|= INDEX_UP
;
6382 if (inst
.operands
[i
].preind
)
6383 inst
.instruction
|= PRE_INDEX
;
6385 if (inst
.operands
[i
].writeback
)
6387 if (inst
.operands
[i
].reg
== REG_PC
)
6389 inst
.error
= _("pc may not be used with write-back");
6394 inst
.error
= _("instruction does not support writeback");
6397 inst
.instruction
|= WRITE_BACK
;
6401 inst
.reloc
.type
= reloc_override
;
6402 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6403 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6404 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6407 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6409 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6415 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6416 Determine whether it can be performed with a move instruction; if
6417 it can, convert inst.instruction to that move instruction and
6418 return 1; if it can't, convert inst.instruction to a literal-pool
6419 load and return 0. If this is not a valid thing to do in the
6420 current context, set inst.error and return 1.
6422 inst.operands[i] describes the destination register. */
6425 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6430 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6434 if ((inst
.instruction
& tbit
) == 0)
6436 inst
.error
= _("invalid pseudo operation");
6439 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6441 inst
.error
= _("constant expression expected");
6444 if (inst
.reloc
.exp
.X_op
== O_constant
)
6448 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6450 /* This can be done with a mov(1) instruction. */
6451 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6452 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6458 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6461 /* This can be done with a mov instruction. */
6462 inst
.instruction
&= LITERAL_MASK
;
6463 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6464 inst
.instruction
|= value
& 0xfff;
6468 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6471 /* This can be done with a mvn instruction. */
6472 inst
.instruction
&= LITERAL_MASK
;
6473 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6474 inst
.instruction
|= value
& 0xfff;
6480 if (add_to_lit_pool () == FAIL
)
6482 inst
.error
= _("literal pool insertion failed");
6485 inst
.operands
[1].reg
= REG_PC
;
6486 inst
.operands
[1].isreg
= 1;
6487 inst
.operands
[1].preind
= 1;
6488 inst
.reloc
.pc_rel
= 1;
6489 inst
.reloc
.type
= (thumb_p
6490 ? BFD_RELOC_ARM_THUMB_OFFSET
6492 ? BFD_RELOC_ARM_HWLITERAL
6493 : BFD_RELOC_ARM_LITERAL
));
6497 /* Functions for instruction encoding, sorted by subarchitecture.
6498 First some generics; their names are taken from the conventional
6499 bit positions for register arguments in ARM format instructions. */
6509 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6515 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6516 inst
.instruction
|= inst
.operands
[1].reg
;
6522 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6523 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6529 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6530 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6536 unsigned Rn
= inst
.operands
[2].reg
;
6537 /* Enforce restrictions on SWP instruction. */
6538 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6539 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6540 _("Rn must not overlap other operands"));
6541 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6542 inst
.instruction
|= inst
.operands
[1].reg
;
6543 inst
.instruction
|= Rn
<< 16;
6549 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6550 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6551 inst
.instruction
|= inst
.operands
[2].reg
;
6557 inst
.instruction
|= inst
.operands
[0].reg
;
6558 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6559 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6565 inst
.instruction
|= inst
.operands
[0].imm
;
6571 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6572 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6575 /* ARM instructions, in alphabetical order by function name (except
6576 that wrapper functions appear immediately after the function they
6579 /* This is a pseudo-op of the form "adr rd, label" to be converted
6580 into a relative address of the form "add rd, pc, #label-.-8". */
6585 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6587 /* Frag hacking will turn this into a sub instruction if the offset turns
6588 out to be negative. */
6589 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6590 inst
.reloc
.pc_rel
= 1;
6591 inst
.reloc
.exp
.X_add_number
-= 8;
6594 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6595 into a relative address of the form:
6596 add rd, pc, #low(label-.-8)"
6597 add rd, rd, #high(label-.-8)" */
6602 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6604 /* Frag hacking will turn this into a sub instruction if the offset turns
6605 out to be negative. */
6606 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
6607 inst
.reloc
.pc_rel
= 1;
6608 inst
.size
= INSN_SIZE
* 2;
6609 inst
.reloc
.exp
.X_add_number
-= 8;
6615 if (!inst
.operands
[1].present
)
6616 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
6617 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6618 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6619 encode_arm_shifter_operand (2);
6625 if (inst
.operands
[0].present
)
6627 constraint ((inst
.instruction
& 0xf0) != 0x40
6628 && inst
.operands
[0].imm
!= 0xf,
6629 "bad barrier type");
6630 inst
.instruction
|= inst
.operands
[0].imm
;
6633 inst
.instruction
|= 0xf;
6639 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
6640 constraint (msb
> 32, _("bit-field extends past end of register"));
6641 /* The instruction encoding stores the LSB and MSB,
6642 not the LSB and width. */
6643 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6644 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
6645 inst
.instruction
|= (msb
- 1) << 16;
6653 /* #0 in second position is alternative syntax for bfc, which is
6654 the same instruction but with REG_PC in the Rm field. */
6655 if (!inst
.operands
[1].isreg
)
6656 inst
.operands
[1].reg
= REG_PC
;
6658 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
6659 constraint (msb
> 32, _("bit-field extends past end of register"));
6660 /* The instruction encoding stores the LSB and MSB,
6661 not the LSB and width. */
6662 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6663 inst
.instruction
|= inst
.operands
[1].reg
;
6664 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6665 inst
.instruction
|= (msb
- 1) << 16;
6671 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
6672 _("bit-field extends past end of register"));
6673 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6674 inst
.instruction
|= inst
.operands
[1].reg
;
6675 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6676 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
6679 /* ARM V5 breakpoint instruction (argument parse)
6680 BKPT <16 bit unsigned immediate>
6681 Instruction is not conditional.
6682 The bit pattern given in insns[] has the COND_ALWAYS condition,
6683 and it is an error if the caller tried to override that. */
6688 /* Top 12 of 16 bits to bits 19:8. */
6689 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
6691 /* Bottom 4 of 16 bits to bits 3:0. */
6692 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
6696 encode_branch (int default_reloc
)
6698 if (inst
.operands
[0].hasreloc
)
6700 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
6701 _("the only suffix valid here is '(plt)'"));
6702 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
6706 inst
.reloc
.type
= default_reloc
;
6708 inst
.reloc
.pc_rel
= 1;
6715 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6716 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6719 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6726 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6728 if (inst
.cond
== COND_ALWAYS
)
6729 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6731 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6735 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6738 /* ARM V5 branch-link-exchange instruction (argument parse)
6739 BLX <target_addr> ie BLX(1)
6740 BLX{<condition>} <Rm> ie BLX(2)
6741 Unfortunately, there are two different opcodes for this mnemonic.
6742 So, the insns[].value is not used, and the code here zaps values
6743 into inst.instruction.
6744 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
6749 if (inst
.operands
[0].isreg
)
6751 /* Arg is a register; the opcode provided by insns[] is correct.
6752 It is not illegal to do "blx pc", just useless. */
6753 if (inst
.operands
[0].reg
== REG_PC
)
6754 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
6756 inst
.instruction
|= inst
.operands
[0].reg
;
6760 /* Arg is an address; this instruction cannot be executed
6761 conditionally, and the opcode must be adjusted. */
6762 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
6763 inst
.instruction
= 0xfa000000;
6765 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6766 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6769 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
6776 if (inst
.operands
[0].reg
== REG_PC
)
6777 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
6779 inst
.instruction
|= inst
.operands
[0].reg
;
6783 /* ARM v5TEJ. Jump to Jazelle code. */
6788 if (inst
.operands
[0].reg
== REG_PC
)
6789 as_tsktsk (_("use of r15 in bxj is not really useful"));
6791 inst
.instruction
|= inst
.operands
[0].reg
;
6794 /* Co-processor data operation:
6795 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
6796 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
6800 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6801 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
6802 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6803 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6804 inst
.instruction
|= inst
.operands
[4].reg
;
6805 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6811 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6812 encode_arm_shifter_operand (1);
6815 /* Transfer between coprocessor and ARM registers.
6816 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
6821 No special properties. */
6826 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6827 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
6828 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6829 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6830 inst
.instruction
|= inst
.operands
[4].reg
;
6831 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6834 /* Transfer between coprocessor register and pair of ARM registers.
6835 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6840 Two XScale instructions are special cases of these:
6842 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
6843 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
6845 Result unpredicatable if Rd or Rn is R15. */
6850 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6851 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
6852 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6853 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6854 inst
.instruction
|= inst
.operands
[4].reg
;
6860 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
6861 if (inst
.operands
[1].present
)
6863 inst
.instruction
|= CPSI_MMOD
;
6864 inst
.instruction
|= inst
.operands
[1].imm
;
6871 inst
.instruction
|= inst
.operands
[0].imm
;
6877 /* There is no IT instruction in ARM mode. We
6878 process it but do not generate code for it. */
6885 int base_reg
= inst
.operands
[0].reg
;
6886 int range
= inst
.operands
[1].imm
;
6888 inst
.instruction
|= base_reg
<< 16;
6889 inst
.instruction
|= range
;
6891 if (inst
.operands
[1].writeback
)
6892 inst
.instruction
|= LDM_TYPE_2_OR_3
;
6894 if (inst
.operands
[0].writeback
)
6896 inst
.instruction
|= WRITE_BACK
;
6897 /* Check for unpredictable uses of writeback. */
6898 if (inst
.instruction
& LOAD_BIT
)
6900 /* Not allowed in LDM type 2. */
6901 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
6902 && ((range
& (1 << REG_PC
)) == 0))
6903 as_warn (_("writeback of base register is UNPREDICTABLE"));
6904 /* Only allowed if base reg not in list for other types. */
6905 else if (range
& (1 << base_reg
))
6906 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
6910 /* Not allowed for type 2. */
6911 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
6912 as_warn (_("writeback of base register is UNPREDICTABLE"));
6913 /* Only allowed if base reg not in list, or first in list. */
6914 else if ((range
& (1 << base_reg
))
6915 && (range
& ((1 << base_reg
) - 1)))
6916 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
6921 /* ARMv5TE load-consecutive (argument parse)
6930 constraint (inst
.operands
[0].reg
% 2 != 0,
6931 _("first destination register must be even"));
6932 constraint (inst
.operands
[1].present
6933 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
6934 _("can only load two consecutive registers"));
6935 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
6936 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
6938 if (!inst
.operands
[1].present
)
6939 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
6941 if (inst
.instruction
& LOAD_BIT
)
6943 /* encode_arm_addr_mode_3 will diagnose overlap between the base
6944 register and the first register written; we have to diagnose
6945 overlap between the base and the second register written here. */
6947 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
6948 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
6949 as_warn (_("base register written back, and overlaps "
6950 "second destination register"));
6952 /* For an index-register load, the index register must not overlap the
6953 destination (even if not write-back). */
6954 else if (inst
.operands
[2].immisreg
6955 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
6956 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
6957 as_warn (_("index register overlaps destination register"));
6960 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6961 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
6967 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
6968 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
6969 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
6970 || inst
.operands
[1].negative
6971 /* This can arise if the programmer has written
6973 or if they have mistakenly used a register name as the last
6976 It is very difficult to distinguish between these two cases
6977 because "rX" might actually be a label. ie the register
6978 name has been occluded by a symbol of the same name. So we
6979 just generate a general 'bad addressing mode' type error
6980 message and leave it up to the programmer to discover the
6981 true cause and fix their mistake. */
6982 || (inst
.operands
[1].reg
== REG_PC
),
6985 constraint (inst
.reloc
.exp
.X_op
!= O_constant
6986 || inst
.reloc
.exp
.X_add_number
!= 0,
6987 _("offset must be zero in ARM encoding"));
6989 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6990 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6991 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6997 constraint (inst
.operands
[0].reg
% 2 != 0,
6998 _("even register required"));
6999 constraint (inst
.operands
[1].present
7000 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7001 _("can only load two consecutive registers"));
7002 /* If op 1 were present and equal to PC, this function wouldn't
7003 have been called in the first place. */
7004 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7006 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7007 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7013 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7014 if (!inst
.operands
[1].isreg
)
7015 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7017 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7023 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7025 if (inst
.operands
[1].preind
)
7027 constraint (inst
.reloc
.exp
.X_op
!= O_constant
||
7028 inst
.reloc
.exp
.X_add_number
!= 0,
7029 _("this instruction requires a post-indexed address"));
7031 inst
.operands
[1].preind
= 0;
7032 inst
.operands
[1].postind
= 1;
7033 inst
.operands
[1].writeback
= 1;
7035 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7036 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7039 /* Halfword and signed-byte load/store operations. */
7044 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7045 if (!inst
.operands
[1].isreg
)
7046 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7048 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7054 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7056 if (inst
.operands
[1].preind
)
7058 constraint (inst
.reloc
.exp
.X_op
!= O_constant
||
7059 inst
.reloc
.exp
.X_add_number
!= 0,
7060 _("this instruction requires a post-indexed address"));
7062 inst
.operands
[1].preind
= 0;
7063 inst
.operands
[1].postind
= 1;
7064 inst
.operands
[1].writeback
= 1;
7066 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7067 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7070 /* Co-processor register load/store.
7071 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7075 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7076 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7077 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7083 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7084 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7085 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7086 && !(inst
.instruction
& 0x00400000))
7087 as_tsktsk (_("Rd and Rm should be different in mla"));
7089 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7090 inst
.instruction
|= inst
.operands
[1].reg
;
7091 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7092 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7098 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7099 encode_arm_shifter_operand (1);
7102 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7109 top
= (inst
.instruction
& 0x00400000) != 0;
7110 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7111 _(":lower16: not allowed this instruction"));
7112 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7113 _(":upper16: not allowed instruction"));
7114 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7115 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7117 imm
= inst
.reloc
.exp
.X_add_number
;
7118 /* The value is in two pieces: 0:11, 16:19. */
7119 inst
.instruction
|= (imm
& 0x00000fff);
7120 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7124 static void do_vfp_nsyn_opcode (const char *);
7127 do_vfp_nsyn_mrs (void)
7129 if (inst
.operands
[0].isvec
)
7131 if (inst
.operands
[1].reg
!= 1)
7132 first_error (_("operand 1 must be FPSCR"));
7133 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7134 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7135 do_vfp_nsyn_opcode ("fmstat");
7137 else if (inst
.operands
[1].isvec
)
7138 do_vfp_nsyn_opcode ("fmrx");
7146 do_vfp_nsyn_msr (void)
7148 if (inst
.operands
[0].isvec
)
7149 do_vfp_nsyn_opcode ("fmxr");
7159 if (do_vfp_nsyn_mrs () == SUCCESS
)
7162 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7163 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7165 _("'CPSR' or 'SPSR' expected"));
7166 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7167 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7170 /* Two possible forms:
7171 "{C|S}PSR_<field>, Rm",
7172 "{C|S}PSR_f, #expression". */
7177 if (do_vfp_nsyn_msr () == SUCCESS
)
7180 inst
.instruction
|= inst
.operands
[0].imm
;
7181 if (inst
.operands
[1].isreg
)
7182 inst
.instruction
|= inst
.operands
[1].reg
;
7185 inst
.instruction
|= INST_IMMEDIATE
;
7186 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7187 inst
.reloc
.pc_rel
= 0;
7194 if (!inst
.operands
[2].present
)
7195 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7196 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7197 inst
.instruction
|= inst
.operands
[1].reg
;
7198 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7200 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7201 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7202 as_tsktsk (_("Rd and Rm should be different in mul"));
7205 /* Long Multiply Parser
7206 UMULL RdLo, RdHi, Rm, Rs
7207 SMULL RdLo, RdHi, Rm, Rs
7208 UMLAL RdLo, RdHi, Rm, Rs
7209 SMLAL RdLo, RdHi, Rm, Rs. */
7214 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7215 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7216 inst
.instruction
|= inst
.operands
[2].reg
;
7217 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7219 /* rdhi, rdlo and rm must all be different. */
7220 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7221 || inst
.operands
[0].reg
== inst
.operands
[2].reg
7222 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7223 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7229 if (inst
.operands
[0].present
)
7231 /* Architectural NOP hints are CPSR sets with no bits selected. */
7232 inst
.instruction
&= 0xf0000000;
7233 inst
.instruction
|= 0x0320f000 + inst
.operands
[0].imm
;
7237 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7238 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7239 Condition defaults to COND_ALWAYS.
7240 Error if Rd, Rn or Rm are R15. */
7245 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7246 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7247 inst
.instruction
|= inst
.operands
[2].reg
;
7248 if (inst
.operands
[3].present
)
7249 encode_arm_shift (3);
7252 /* ARM V6 PKHTB (Argument Parse). */
7257 if (!inst
.operands
[3].present
)
7259 /* If the shift specifier is omitted, turn the instruction
7260 into pkhbt rd, rm, rn. */
7261 inst
.instruction
&= 0xfff00010;
7262 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7263 inst
.instruction
|= inst
.operands
[1].reg
;
7264 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7268 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7269 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7270 inst
.instruction
|= inst
.operands
[2].reg
;
7271 encode_arm_shift (3);
7275 /* ARMv5TE: Preload-Cache
7279 Syntactically, like LDR with B=1, W=0, L=1. */
7284 constraint (!inst
.operands
[0].isreg
,
7285 _("'[' expected after PLD mnemonic"));
7286 constraint (inst
.operands
[0].postind
,
7287 _("post-indexed expression used in preload instruction"));
7288 constraint (inst
.operands
[0].writeback
,
7289 _("writeback used in preload instruction"));
7290 constraint (!inst
.operands
[0].preind
,
7291 _("unindexed addressing used in preload instruction"));
7292 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7295 /* ARMv7: PLI <addr_mode> */
7299 constraint (!inst
.operands
[0].isreg
,
7300 _("'[' expected after PLI mnemonic"));
7301 constraint (inst
.operands
[0].postind
,
7302 _("post-indexed expression used in preload instruction"));
7303 constraint (inst
.operands
[0].writeback
,
7304 _("writeback used in preload instruction"));
7305 constraint (!inst
.operands
[0].preind
,
7306 _("unindexed addressing used in preload instruction"));
7307 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7308 inst
.instruction
&= ~PRE_INDEX
;
7314 inst
.operands
[1] = inst
.operands
[0];
7315 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7316 inst
.operands
[0].isreg
= 1;
7317 inst
.operands
[0].writeback
= 1;
7318 inst
.operands
[0].reg
= REG_SP
;
7322 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7323 word at the specified address and the following word
7325 Unconditionally executed.
7326 Error if Rn is R15. */
7331 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7332 if (inst
.operands
[0].writeback
)
7333 inst
.instruction
|= WRITE_BACK
;
7336 /* ARM V6 ssat (argument parse). */
7341 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7342 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7343 inst
.instruction
|= inst
.operands
[2].reg
;
7345 if (inst
.operands
[3].present
)
7346 encode_arm_shift (3);
7349 /* ARM V6 usat (argument parse). */
7354 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7355 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7356 inst
.instruction
|= inst
.operands
[2].reg
;
7358 if (inst
.operands
[3].present
)
7359 encode_arm_shift (3);
7362 /* ARM V6 ssat16 (argument parse). */
7367 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7368 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7369 inst
.instruction
|= inst
.operands
[2].reg
;
7375 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7376 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7377 inst
.instruction
|= inst
.operands
[2].reg
;
7380 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7381 preserving the other bits.
7383 setend <endian_specifier>, where <endian_specifier> is either
7389 if (inst
.operands
[0].imm
)
7390 inst
.instruction
|= 0x200;
7396 unsigned int Rm
= (inst
.operands
[1].present
7397 ? inst
.operands
[1].reg
7398 : inst
.operands
[0].reg
);
7400 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7401 inst
.instruction
|= Rm
;
7402 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7404 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7405 inst
.instruction
|= SHIFT_BY_REG
;
7408 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7414 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7415 inst
.reloc
.pc_rel
= 0;
7421 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7422 inst
.reloc
.pc_rel
= 0;
7425 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7426 SMLAxy{cond} Rd,Rm,Rs,Rn
7427 SMLAWy{cond} Rd,Rm,Rs,Rn
7428 Error if any register is R15. */
7433 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7434 inst
.instruction
|= inst
.operands
[1].reg
;
7435 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7436 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7439 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7440 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7441 Error if any register is R15.
7442 Warning if Rdlo == Rdhi. */
7447 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7448 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7449 inst
.instruction
|= inst
.operands
[2].reg
;
7450 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7452 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7453 as_tsktsk (_("rdhi and rdlo must be different"));
7456 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7457 SMULxy{cond} Rd,Rm,Rs
7458 Error if any register is R15. */
7463 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7464 inst
.instruction
|= inst
.operands
[1].reg
;
7465 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7468 /* ARM V6 srs (argument parse). The variable fields in the encoding are
7469 the same for both ARM and Thumb-2. */
7476 if (inst
.operands
[0].present
)
7478 reg
= inst
.operands
[0].reg
;
7479 constraint (reg
!= 13, _("SRS base register must be r13"));
7484 inst
.instruction
|= reg
<< 16;
7485 inst
.instruction
|= inst
.operands
[1].imm
;
7486 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
7487 inst
.instruction
|= WRITE_BACK
;
7490 /* ARM V6 strex (argument parse). */
7495 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7496 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7497 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7498 || inst
.operands
[2].negative
7499 /* See comment in do_ldrex(). */
7500 || (inst
.operands
[2].reg
== REG_PC
),
7503 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7504 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
7506 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7507 || inst
.reloc
.exp
.X_add_number
!= 0,
7508 _("offset must be zero in ARM encoding"));
7510 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7511 inst
.instruction
|= inst
.operands
[1].reg
;
7512 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7513 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7519 constraint (inst
.operands
[1].reg
% 2 != 0,
7520 _("even register required"));
7521 constraint (inst
.operands
[2].present
7522 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
7523 _("can only store two consecutive registers"));
7524 /* If op 2 were present and equal to PC, this function wouldn't
7525 have been called in the first place. */
7526 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
7528 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7529 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
7530 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
7533 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7534 inst
.instruction
|= inst
.operands
[1].reg
;
7535 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7538 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7539 extends it to 32-bits, and adds the result to a value in another
7540 register. You can specify a rotation by 0, 8, 16, or 24 bits
7541 before extracting the 16-bit value.
7542 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7543 Condition defaults to COND_ALWAYS.
7544 Error if any register uses R15. */
7549 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7550 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7551 inst
.instruction
|= inst
.operands
[2].reg
;
7552 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
7557 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
7558 Condition defaults to COND_ALWAYS.
7559 Error if any register uses R15. */
7564 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7565 inst
.instruction
|= inst
.operands
[1].reg
;
7566 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
7569 /* VFP instructions. In a logical order: SP variant first, monad
7570 before dyad, arithmetic then move then load/store. */
7573 do_vfp_sp_monadic (void)
7575 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7576 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7580 do_vfp_sp_dyadic (void)
7582 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7583 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7584 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7588 do_vfp_sp_compare_z (void)
7590 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7594 do_vfp_dp_sp_cvt (void)
7596 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7597 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7601 do_vfp_sp_dp_cvt (void)
7603 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7604 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7608 do_vfp_reg_from_sp (void)
7610 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7611 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7615 do_vfp_reg2_from_sp2 (void)
7617 constraint (inst
.operands
[2].imm
!= 2,
7618 _("only two consecutive VFP SP registers allowed here"));
7619 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7620 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7621 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7625 do_vfp_sp_from_reg (void)
7627 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
7628 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7632 do_vfp_sp2_from_reg2 (void)
7634 constraint (inst
.operands
[0].imm
!= 2,
7635 _("only two consecutive VFP SP registers allowed here"));
7636 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
7637 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7638 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7642 do_vfp_sp_ldst (void)
7644 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7645 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7649 do_vfp_dp_ldst (void)
7651 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7652 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7657 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
7659 if (inst
.operands
[0].writeback
)
7660 inst
.instruction
|= WRITE_BACK
;
7662 constraint (ldstm_type
!= VFP_LDSTMIA
,
7663 _("this addressing mode requires base-register writeback"));
7664 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7665 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
7666 inst
.instruction
|= inst
.operands
[1].imm
;
7670 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
7674 if (inst
.operands
[0].writeback
)
7675 inst
.instruction
|= WRITE_BACK
;
7677 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
7678 _("this addressing mode requires base-register writeback"));
7680 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7681 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7683 count
= inst
.operands
[1].imm
<< 1;
7684 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
7687 inst
.instruction
|= count
;
7691 do_vfp_sp_ldstmia (void)
7693 vfp_sp_ldstm (VFP_LDSTMIA
);
7697 do_vfp_sp_ldstmdb (void)
7699 vfp_sp_ldstm (VFP_LDSTMDB
);
7703 do_vfp_dp_ldstmia (void)
7705 vfp_dp_ldstm (VFP_LDSTMIA
);
7709 do_vfp_dp_ldstmdb (void)
7711 vfp_dp_ldstm (VFP_LDSTMDB
);
7715 do_vfp_xp_ldstmia (void)
7717 vfp_dp_ldstm (VFP_LDSTMIAX
);
7721 do_vfp_xp_ldstmdb (void)
7723 vfp_dp_ldstm (VFP_LDSTMDBX
);
7727 do_vfp_dp_rd_rm (void)
7729 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7730 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7734 do_vfp_dp_rn_rd (void)
7736 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
7737 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7741 do_vfp_dp_rd_rn (void)
7743 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7744 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7748 do_vfp_dp_rd_rn_rm (void)
7750 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7751 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7752 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
7758 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7762 do_vfp_dp_rm_rd_rn (void)
7764 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
7765 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7766 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
7769 /* VFPv3 instructions. */
7771 do_vfp_sp_const (void)
7773 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7774 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
7775 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
7779 do_vfp_dp_const (void)
7781 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7782 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
7783 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
7787 vfp_conv (int srcsize
)
7789 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
7790 inst
.instruction
|= (immbits
& 1) << 5;
7791 inst
.instruction
|= (immbits
>> 1);
7795 do_vfp_sp_conv_16 (void)
7797 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7802 do_vfp_dp_conv_16 (void)
7804 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7809 do_vfp_sp_conv_32 (void)
7811 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7816 do_vfp_dp_conv_32 (void)
7818 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7823 /* FPA instructions. Also in a logical order. */
7828 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7829 inst
.instruction
|= inst
.operands
[1].reg
;
7833 do_fpa_ldmstm (void)
7835 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7836 switch (inst
.operands
[1].imm
)
7838 case 1: inst
.instruction
|= CP_T_X
; break;
7839 case 2: inst
.instruction
|= CP_T_Y
; break;
7840 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
7845 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
7847 /* The instruction specified "ea" or "fd", so we can only accept
7848 [Rn]{!}. The instruction does not really support stacking or
7849 unstacking, so we have to emulate these by setting appropriate
7850 bits and offsets. */
7851 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7852 || inst
.reloc
.exp
.X_add_number
!= 0,
7853 _("this instruction does not support indexing"));
7855 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
7856 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
7858 if (!(inst
.instruction
& INDEX_UP
))
7859 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
7861 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
7863 inst
.operands
[2].preind
= 0;
7864 inst
.operands
[2].postind
= 1;
7868 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7872 /* iWMMXt instructions: strictly in alphabetical order. */
7875 do_iwmmxt_tandorc (void)
7877 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
7881 do_iwmmxt_textrc (void)
7883 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7884 inst
.instruction
|= inst
.operands
[1].imm
;
7888 do_iwmmxt_textrm (void)
7890 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7891 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7892 inst
.instruction
|= inst
.operands
[2].imm
;
7896 do_iwmmxt_tinsr (void)
7898 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7899 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7900 inst
.instruction
|= inst
.operands
[2].imm
;
7904 do_iwmmxt_tmia (void)
7906 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
7907 inst
.instruction
|= inst
.operands
[1].reg
;
7908 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7912 do_iwmmxt_waligni (void)
7914 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7915 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7916 inst
.instruction
|= inst
.operands
[2].reg
;
7917 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
7921 do_iwmmxt_wmerge (void)
7923 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7924 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7925 inst
.instruction
|= inst
.operands
[2].reg
;
7926 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
7930 do_iwmmxt_wmov (void)
7932 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
7933 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7934 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7935 inst
.instruction
|= inst
.operands
[1].reg
;
7939 do_iwmmxt_wldstbh (void)
7942 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7944 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
7946 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
7947 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
7951 do_iwmmxt_wldstw (void)
7953 /* RIWR_RIWC clears .isreg for a control register. */
7954 if (!inst
.operands
[0].isreg
)
7956 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7957 inst
.instruction
|= 0xf0000000;
7960 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7961 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7965 do_iwmmxt_wldstd (void)
7967 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7968 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
7969 && inst
.operands
[1].immisreg
)
7971 inst
.instruction
&= ~0x1a000ff;
7972 inst
.instruction
|= (0xf << 28);
7973 if (inst
.operands
[1].preind
)
7974 inst
.instruction
|= PRE_INDEX
;
7975 if (!inst
.operands
[1].negative
)
7976 inst
.instruction
|= INDEX_UP
;
7977 if (inst
.operands
[1].writeback
)
7978 inst
.instruction
|= WRITE_BACK
;
7979 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7980 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
7981 inst
.instruction
|= inst
.operands
[1].imm
;
7984 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
7988 do_iwmmxt_wshufh (void)
7990 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7991 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7992 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
7993 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
7997 do_iwmmxt_wzero (void)
7999 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8000 inst
.instruction
|= inst
.operands
[0].reg
;
8001 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8002 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8006 do_iwmmxt_wrwrwr_or_imm5 (void)
8008 if (inst
.operands
[2].isreg
)
8011 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8012 _("immediate operand requires iWMMXt2"));
8014 if (inst
.operands
[2].imm
== 0)
8016 switch ((inst
.instruction
>> 20) & 0xf)
8022 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8023 inst
.operands
[2].imm
= 16;
8024 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8030 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8031 inst
.operands
[2].imm
= 32;
8032 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8039 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8041 wrn
= (inst
.instruction
>> 16) & 0xf;
8042 inst
.instruction
&= 0xff0fff0f;
8043 inst
.instruction
|= wrn
;
8044 /* Bail out here; the instruction is now assembled. */
8049 /* Map 32 -> 0, etc. */
8050 inst
.operands
[2].imm
&= 0x1f;
8051 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8055 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8056 operations first, then control, shift, and load/store. */
8058 /* Insns like "foo X,Y,Z". */
8061 do_mav_triple (void)
8063 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8064 inst
.instruction
|= inst
.operands
[1].reg
;
8065 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8068 /* Insns like "foo W,X,Y,Z".
8069 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8074 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8075 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8076 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8077 inst
.instruction
|= inst
.operands
[3].reg
;
8080 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8084 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8087 /* Maverick shift immediate instructions.
8088 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8089 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8094 int imm
= inst
.operands
[2].imm
;
8096 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8097 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8099 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8100 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8101 Bit 4 should be 0. */
8102 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8104 inst
.instruction
|= imm
;
8107 /* XScale instructions. Also sorted arithmetic before move. */
8109 /* Xscale multiply-accumulate (argument parse)
8112 MIAxycc acc0,Rm,Rs. */
8117 inst
.instruction
|= inst
.operands
[1].reg
;
8118 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8121 /* Xscale move-accumulator-register (argument parse)
8123 MARcc acc0,RdLo,RdHi. */
8128 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8129 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8132 /* Xscale move-register-accumulator (argument parse)
8134 MRAcc RdLo,RdHi,acc0. */
8139 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8140 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8141 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8144 /* Encoding functions relevant only to Thumb. */
8146 /* inst.operands[i] is a shifted-register operand; encode
8147 it into inst.instruction in the format used by Thumb32. */
8150 encode_thumb32_shifted_operand (int i
)
8152 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8153 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8155 constraint (inst
.operands
[i
].immisreg
,
8156 _("shift by register not allowed in thumb mode"));
8157 inst
.instruction
|= inst
.operands
[i
].reg
;
8158 if (shift
== SHIFT_RRX
)
8159 inst
.instruction
|= SHIFT_ROR
<< 4;
8162 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8163 _("expression too complex"));
8165 constraint (value
> 32
8166 || (value
== 32 && (shift
== SHIFT_LSL
8167 || shift
== SHIFT_ROR
)),
8168 _("shift expression is too large"));
8172 else if (value
== 32)
8175 inst
.instruction
|= shift
<< 4;
8176 inst
.instruction
|= (value
& 0x1c) << 10;
8177 inst
.instruction
|= (value
& 0x03) << 6;
8182 /* inst.operands[i] was set up by parse_address. Encode it into a
8183 Thumb32 format load or store instruction. Reject forms that cannot
8184 be used with such instructions. If is_t is true, reject forms that
8185 cannot be used with a T instruction; if is_d is true, reject forms
8186 that cannot be used with a D instruction. */
8189 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8191 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8193 constraint (!inst
.operands
[i
].isreg
,
8194 _("Instruction does not support =N addresses"));
8196 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8197 if (inst
.operands
[i
].immisreg
)
8199 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
8200 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8201 constraint (inst
.operands
[i
].negative
,
8202 _("Thumb does not support negative register indexing"));
8203 constraint (inst
.operands
[i
].postind
,
8204 _("Thumb does not support register post-indexing"));
8205 constraint (inst
.operands
[i
].writeback
,
8206 _("Thumb does not support register indexing with writeback"));
8207 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8208 _("Thumb supports only LSL in shifted register indexing"));
8210 inst
.instruction
|= inst
.operands
[i
].imm
;
8211 if (inst
.operands
[i
].shifted
)
8213 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8214 _("expression too complex"));
8215 constraint (inst
.reloc
.exp
.X_add_number
< 0
8216 || inst
.reloc
.exp
.X_add_number
> 3,
8217 _("shift out of range"));
8218 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8220 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8222 else if (inst
.operands
[i
].preind
)
8224 constraint (is_pc
&& inst
.operands
[i
].writeback
,
8225 _("cannot use writeback with PC-relative addressing"));
8226 constraint (is_t
&& inst
.operands
[i
].writeback
,
8227 _("cannot use writeback with this instruction"));
8231 inst
.instruction
|= 0x01000000;
8232 if (inst
.operands
[i
].writeback
)
8233 inst
.instruction
|= 0x00200000;
8237 inst
.instruction
|= 0x00000c00;
8238 if (inst
.operands
[i
].writeback
)
8239 inst
.instruction
|= 0x00000100;
8241 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8243 else if (inst
.operands
[i
].postind
)
8245 assert (inst
.operands
[i
].writeback
);
8246 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8247 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8250 inst
.instruction
|= 0x00200000;
8252 inst
.instruction
|= 0x00000900;
8253 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8255 else /* unindexed - only for coprocessor */
8256 inst
.error
= _("instruction does not accept unindexed addressing");
8259 /* Table of Thumb instructions which exist in both 16- and 32-bit
8260 encodings (the latter only in post-V6T2 cores). The index is the
8261 value used in the insns table below. When there is more than one
8262 possible 16-bit encoding for the instruction, this table always
8264 Also contains several pseudo-instructions used during relaxation. */
8265 #define T16_32_TAB \
8266 X(adc, 4140, eb400000), \
8267 X(adcs, 4140, eb500000), \
8268 X(add, 1c00, eb000000), \
8269 X(adds, 1c00, eb100000), \
8270 X(addi, 0000, f1000000), \
8271 X(addis, 0000, f1100000), \
8272 X(add_pc,000f, f20f0000), \
8273 X(add_sp,000d, f10d0000), \
8274 X(adr, 000f, f20f0000), \
8275 X(and, 4000, ea000000), \
8276 X(ands, 4000, ea100000), \
8277 X(asr, 1000, fa40f000), \
8278 X(asrs, 1000, fa50f000), \
8279 X(b, e000, f000b000), \
8280 X(bcond, d000, f0008000), \
8281 X(bic, 4380, ea200000), \
8282 X(bics, 4380, ea300000), \
8283 X(cmn, 42c0, eb100f00), \
8284 X(cmp, 2800, ebb00f00), \
8285 X(cpsie, b660, f3af8400), \
8286 X(cpsid, b670, f3af8600), \
8287 X(cpy, 4600, ea4f0000), \
8288 X(dec_sp,80dd, f1ad0d00), \
8289 X(eor, 4040, ea800000), \
8290 X(eors, 4040, ea900000), \
8291 X(inc_sp,00dd, f10d0d00), \
8292 X(ldmia, c800, e8900000), \
8293 X(ldr, 6800, f8500000), \
8294 X(ldrb, 7800, f8100000), \
8295 X(ldrh, 8800, f8300000), \
8296 X(ldrsb, 5600, f9100000), \
8297 X(ldrsh, 5e00, f9300000), \
8298 X(ldr_pc,4800, f85f0000), \
8299 X(ldr_pc2,4800, f85f0000), \
8300 X(ldr_sp,9800, f85d0000), \
8301 X(lsl, 0000, fa00f000), \
8302 X(lsls, 0000, fa10f000), \
8303 X(lsr, 0800, fa20f000), \
8304 X(lsrs, 0800, fa30f000), \
8305 X(mov, 2000, ea4f0000), \
8306 X(movs, 2000, ea5f0000), \
8307 X(mul, 4340, fb00f000), \
8308 X(muls, 4340, ffffffff), /* no 32b muls */ \
8309 X(mvn, 43c0, ea6f0000), \
8310 X(mvns, 43c0, ea7f0000), \
8311 X(neg, 4240, f1c00000), /* rsb #0 */ \
8312 X(negs, 4240, f1d00000), /* rsbs #0 */ \
8313 X(orr, 4300, ea400000), \
8314 X(orrs, 4300, ea500000), \
8315 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8316 X(push, b400, e92d0000), /* stmdb sp!,... */ \
8317 X(rev, ba00, fa90f080), \
8318 X(rev16, ba40, fa90f090), \
8319 X(revsh, bac0, fa90f0b0), \
8320 X(ror, 41c0, fa60f000), \
8321 X(rors, 41c0, fa70f000), \
8322 X(sbc, 4180, eb600000), \
8323 X(sbcs, 4180, eb700000), \
8324 X(stmia, c000, e8800000), \
8325 X(str, 6000, f8400000), \
8326 X(strb, 7000, f8000000), \
8327 X(strh, 8000, f8200000), \
8328 X(str_sp,9000, f84d0000), \
8329 X(sub, 1e00, eba00000), \
8330 X(subs, 1e00, ebb00000), \
8331 X(subi, 8000, f1a00000), \
8332 X(subis, 8000, f1b00000), \
8333 X(sxtb, b240, fa4ff080), \
8334 X(sxth, b200, fa0ff080), \
8335 X(tst, 4200, ea100f00), \
8336 X(uxtb, b2c0, fa5ff080), \
8337 X(uxth, b280, fa1ff080), \
8338 X(nop, bf00, f3af8000), \
8339 X(yield, bf10, f3af8001), \
8340 X(wfe, bf20, f3af8002), \
8341 X(wfi, bf30, f3af8003), \
8342 X(sev, bf40, f3af9004), /* typo, 8004? */
8344 /* To catch errors in encoding functions, the codes are all offset by
8345 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8346 as 16-bit instructions. */
8347 #define X(a,b,c) T_MNEM_##a
8348 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8351 #define X(a,b,c) 0x##b
8352 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8353 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8356 #define X(a,b,c) 0x##c
8357 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8358 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8359 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8363 /* Thumb instruction encoders, in alphabetical order. */
8367 do_t_add_sub_w (void)
8371 Rd
= inst
.operands
[0].reg
;
8372 Rn
= inst
.operands
[1].reg
;
8374 constraint (Rd
== 15, _("PC not allowed as destination"));
8375 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8376 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8379 /* Parse an add or subtract instruction. We get here with inst.instruction
8380 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8387 Rd
= inst
.operands
[0].reg
;
8388 Rs
= (inst
.operands
[1].present
8389 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8390 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8398 flags
= (inst
.instruction
== T_MNEM_adds
8399 || inst
.instruction
== T_MNEM_subs
);
8401 narrow
= (current_it_mask
== 0);
8403 narrow
= (current_it_mask
!= 0);
8404 if (!inst
.operands
[2].isreg
)
8408 add
= (inst
.instruction
== T_MNEM_add
8409 || inst
.instruction
== T_MNEM_adds
);
8411 if (inst
.size_req
!= 4)
8413 /* Attempt to use a narrow opcode, with relaxation if
8415 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8416 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8417 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8418 opcode
= T_MNEM_add_sp
;
8419 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8420 opcode
= T_MNEM_add_pc
;
8421 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8424 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8426 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8430 inst
.instruction
= THUMB_OP16(opcode
);
8431 inst
.instruction
|= (Rd
<< 4) | Rs
;
8432 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8433 if (inst
.size_req
!= 2)
8434 inst
.relax
= opcode
;
8437 constraint (inst
.size_req
== 2, BAD_HIREG
);
8439 if (inst
.size_req
== 4
8440 || (inst
.size_req
!= 2 && !opcode
))
8444 /* Always use addw/subw. */
8445 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
8446 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8450 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8451 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
8454 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8456 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
8458 inst
.instruction
|= Rd
<< 8;
8459 inst
.instruction
|= Rs
<< 16;
8464 Rn
= inst
.operands
[2].reg
;
8465 /* See if we can do this with a 16-bit instruction. */
8466 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
8468 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8473 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
8474 || inst
.instruction
== T_MNEM_add
)
8477 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8481 if (inst
.instruction
== T_MNEM_add
)
8485 inst
.instruction
= T_OPCODE_ADD_HI
;
8486 inst
.instruction
|= (Rd
& 8) << 4;
8487 inst
.instruction
|= (Rd
& 7);
8488 inst
.instruction
|= Rn
<< 3;
8491 /* ... because addition is commutative! */
8494 inst
.instruction
= T_OPCODE_ADD_HI
;
8495 inst
.instruction
|= (Rd
& 8) << 4;
8496 inst
.instruction
|= (Rd
& 7);
8497 inst
.instruction
|= Rs
<< 3;
8502 /* If we get here, it can't be done in 16 bits. */
8503 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
8504 _("shift must be constant"));
8505 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8506 inst
.instruction
|= Rd
<< 8;
8507 inst
.instruction
|= Rs
<< 16;
8508 encode_thumb32_shifted_operand (2);
8513 constraint (inst
.instruction
== T_MNEM_adds
8514 || inst
.instruction
== T_MNEM_subs
,
8517 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
8519 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
8520 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
8523 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8525 inst
.instruction
|= (Rd
<< 4) | Rs
;
8526 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8530 Rn
= inst
.operands
[2].reg
;
8531 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
8533 /* We now have Rd, Rs, and Rn set to registers. */
8534 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8536 /* Can't do this for SUB. */
8537 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
8538 inst
.instruction
= T_OPCODE_ADD_HI
;
8539 inst
.instruction
|= (Rd
& 8) << 4;
8540 inst
.instruction
|= (Rd
& 7);
8542 inst
.instruction
|= Rn
<< 3;
8544 inst
.instruction
|= Rs
<< 3;
8546 constraint (1, _("dest must overlap one source register"));
8550 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8551 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
8552 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8560 if (unified_syntax
&& inst
.size_req
== 0 && inst
.operands
[0].reg
<= 7)
8562 /* Defer to section relaxation. */
8563 inst
.relax
= inst
.instruction
;
8564 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8565 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8567 else if (unified_syntax
&& inst
.size_req
!= 2)
8569 /* Generate a 32-bit opcode. */
8570 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8571 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8572 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
8573 inst
.reloc
.pc_rel
= 1;
8577 /* Generate a 16-bit opcode. */
8578 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8579 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8580 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
8581 inst
.reloc
.pc_rel
= 1;
8583 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8587 /* Arithmetic instructions for which there is just one 16-bit
8588 instruction encoding, and it allows only two low registers.
8589 For maximal compatibility with ARM syntax, we allow three register
8590 operands even when Thumb-32 instructions are not available, as long
8591 as the first two are identical. For instance, both "sbc r0,r1" and
8592 "sbc r0,r0,r1" are allowed. */
8598 Rd
= inst
.operands
[0].reg
;
8599 Rs
= (inst
.operands
[1].present
8600 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8601 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8602 Rn
= inst
.operands
[2].reg
;
8606 if (!inst
.operands
[2].isreg
)
8608 /* For an immediate, we always generate a 32-bit opcode;
8609 section relaxation will shrink it later if possible. */
8610 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8611 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8612 inst
.instruction
|= Rd
<< 8;
8613 inst
.instruction
|= Rs
<< 16;
8614 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8620 /* See if we can do this with a 16-bit instruction. */
8621 if (THUMB_SETS_FLAGS (inst
.instruction
))
8622 narrow
= current_it_mask
== 0;
8624 narrow
= current_it_mask
!= 0;
8626 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8628 if (inst
.operands
[2].shifted
)
8630 if (inst
.size_req
== 4)
8636 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8637 inst
.instruction
|= Rd
;
8638 inst
.instruction
|= Rn
<< 3;
8642 /* If we get here, it can't be done in 16 bits. */
8643 constraint (inst
.operands
[2].shifted
8644 && inst
.operands
[2].immisreg
,
8645 _("shift must be constant"));
8646 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8647 inst
.instruction
|= Rd
<< 8;
8648 inst
.instruction
|= Rs
<< 16;
8649 encode_thumb32_shifted_operand (2);
8654 /* On its face this is a lie - the instruction does set the
8655 flags. However, the only supported mnemonic in this mode
8657 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8659 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8660 _("unshifted register required"));
8661 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8662 constraint (Rd
!= Rs
,
8663 _("dest and source1 must be the same register"));
8665 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8666 inst
.instruction
|= Rd
;
8667 inst
.instruction
|= Rn
<< 3;
8671 /* Similarly, but for instructions where the arithmetic operation is
8672 commutative, so we can allow either of them to be different from
8673 the destination operand in a 16-bit instruction. For instance, all
8674 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
8681 Rd
= inst
.operands
[0].reg
;
8682 Rs
= (inst
.operands
[1].present
8683 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8684 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8685 Rn
= inst
.operands
[2].reg
;
8689 if (!inst
.operands
[2].isreg
)
8691 /* For an immediate, we always generate a 32-bit opcode;
8692 section relaxation will shrink it later if possible. */
8693 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8694 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8695 inst
.instruction
|= Rd
<< 8;
8696 inst
.instruction
|= Rs
<< 16;
8697 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8703 /* See if we can do this with a 16-bit instruction. */
8704 if (THUMB_SETS_FLAGS (inst
.instruction
))
8705 narrow
= current_it_mask
== 0;
8707 narrow
= current_it_mask
!= 0;
8709 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8711 if (inst
.operands
[2].shifted
)
8713 if (inst
.size_req
== 4)
8720 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8721 inst
.instruction
|= Rd
;
8722 inst
.instruction
|= Rn
<< 3;
8727 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8728 inst
.instruction
|= Rd
;
8729 inst
.instruction
|= Rs
<< 3;
8734 /* If we get here, it can't be done in 16 bits. */
8735 constraint (inst
.operands
[2].shifted
8736 && inst
.operands
[2].immisreg
,
8737 _("shift must be constant"));
8738 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8739 inst
.instruction
|= Rd
<< 8;
8740 inst
.instruction
|= Rs
<< 16;
8741 encode_thumb32_shifted_operand (2);
8746 /* On its face this is a lie - the instruction does set the
8747 flags. However, the only supported mnemonic in this mode
8749 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8751 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8752 _("unshifted register required"));
8753 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8755 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8756 inst
.instruction
|= Rd
;
8759 inst
.instruction
|= Rn
<< 3;
8761 inst
.instruction
|= Rs
<< 3;
8763 constraint (1, _("dest must overlap one source register"));
8770 if (inst
.operands
[0].present
)
8772 constraint ((inst
.instruction
& 0xf0) != 0x40
8773 && inst
.operands
[0].imm
!= 0xf,
8774 "bad barrier type");
8775 inst
.instruction
|= inst
.operands
[0].imm
;
8778 inst
.instruction
|= 0xf;
8784 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8785 constraint (msb
> 32, _("bit-field extends past end of register"));
8786 /* The instruction encoding stores the LSB and MSB,
8787 not the LSB and width. */
8788 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8789 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
8790 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
8791 inst
.instruction
|= msb
- 1;
8799 /* #0 in second position is alternative syntax for bfc, which is
8800 the same instruction but with REG_PC in the Rm field. */
8801 if (!inst
.operands
[1].isreg
)
8802 inst
.operands
[1].reg
= REG_PC
;
8804 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8805 constraint (msb
> 32, _("bit-field extends past end of register"));
8806 /* The instruction encoding stores the LSB and MSB,
8807 not the LSB and width. */
8808 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8809 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8810 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8811 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8812 inst
.instruction
|= msb
- 1;
8818 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8819 _("bit-field extends past end of register"));
8820 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8821 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8822 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8823 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8824 inst
.instruction
|= inst
.operands
[3].imm
- 1;
8827 /* ARM V5 Thumb BLX (argument parse)
8828 BLX <target_addr> which is BLX(1)
8829 BLX <Rm> which is BLX(2)
8830 Unfortunately, there are two different opcodes for this mnemonic.
8831 So, the insns[].value is not used, and the code here zaps values
8832 into inst.instruction.
8834 ??? How to take advantage of the additional two bits of displacement
8835 available in Thumb32 mode? Need new relocation? */
8840 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8841 if (inst
.operands
[0].isreg
)
8842 /* We have a register, so this is BLX(2). */
8843 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8846 /* No register. This must be BLX(1). */
8847 inst
.instruction
= 0xf000e800;
8849 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8850 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8853 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
8854 inst
.reloc
.pc_rel
= 1;
8864 if (current_it_mask
)
8866 /* Conditional branches inside IT blocks are encoded as unconditional
8869 /* A branch must be the last instruction in an IT block. */
8870 constraint (current_it_mask
!= 0x10, BAD_BRANCH
);
8875 if (cond
!= COND_ALWAYS
)
8876 opcode
= T_MNEM_bcond
;
8878 opcode
= inst
.instruction
;
8880 if (unified_syntax
&& inst
.size_req
== 4)
8882 inst
.instruction
= THUMB_OP32(opcode
);
8883 if (cond
== COND_ALWAYS
)
8884 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
8887 assert (cond
!= 0xF);
8888 inst
.instruction
|= cond
<< 22;
8889 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
8894 inst
.instruction
= THUMB_OP16(opcode
);
8895 if (cond
== COND_ALWAYS
)
8896 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
8899 inst
.instruction
|= cond
<< 8;
8900 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
8902 /* Allow section relaxation. */
8903 if (unified_syntax
&& inst
.size_req
!= 2)
8904 inst
.relax
= opcode
;
8907 inst
.reloc
.pc_rel
= 1;
8913 constraint (inst
.cond
!= COND_ALWAYS
,
8914 _("instruction is always unconditional"));
8915 if (inst
.operands
[0].present
)
8917 constraint (inst
.operands
[0].imm
> 255,
8918 _("immediate value out of range"));
8919 inst
.instruction
|= inst
.operands
[0].imm
;
8924 do_t_branch23 (void)
8926 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8927 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8928 inst
.reloc
.pc_rel
= 1;
8930 /* If the destination of the branch is a defined symbol which does not have
8931 the THUMB_FUNC attribute, then we must be calling a function which has
8932 the (interfacearm) attribute. We look for the Thumb entry point to that
8933 function and change the branch to refer to that function instead. */
8934 if ( inst
.reloc
.exp
.X_op
== O_symbol
8935 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8936 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8937 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8938 inst
.reloc
.exp
.X_add_symbol
=
8939 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
8945 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8946 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8947 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
8948 should cause the alignment to be checked once it is known. This is
8949 because BX PC only works if the instruction is word aligned. */
8955 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8956 if (inst
.operands
[0].reg
== REG_PC
)
8957 as_tsktsk (_("use of r15 in bxj is not really useful"));
8959 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8965 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8966 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8967 inst
.instruction
|= inst
.operands
[1].reg
;
8973 constraint (current_it_mask
, BAD_NOT_IT
);
8974 inst
.instruction
|= inst
.operands
[0].imm
;
8980 constraint (current_it_mask
, BAD_NOT_IT
);
8982 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
8983 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
8985 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
8986 inst
.instruction
= 0xf3af8000;
8987 inst
.instruction
|= imod
<< 9;
8988 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
8989 if (inst
.operands
[1].present
)
8990 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
8994 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
8995 && (inst
.operands
[0].imm
& 4),
8996 _("selected processor does not support 'A' form "
8997 "of this instruction"));
8998 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
8999 _("Thumb does not support the 2-argument "
9000 "form of this instruction"));
9001 inst
.instruction
|= inst
.operands
[0].imm
;
9005 /* THUMB CPY instruction (argument parse). */
9010 if (inst
.size_req
== 4)
9012 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9013 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9014 inst
.instruction
|= inst
.operands
[1].reg
;
9018 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9019 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9020 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9027 constraint (current_it_mask
, BAD_NOT_IT
);
9028 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9029 inst
.instruction
|= inst
.operands
[0].reg
;
9030 inst
.reloc
.pc_rel
= 1;
9031 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9037 inst
.instruction
|= inst
.operands
[0].imm
;
9043 if (!inst
.operands
[1].present
)
9044 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9045 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9046 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9047 inst
.instruction
|= inst
.operands
[2].reg
;
9053 if (unified_syntax
&& inst
.size_req
== 4)
9054 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9056 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9062 unsigned int cond
= inst
.operands
[0].imm
;
9064 constraint (current_it_mask
, BAD_NOT_IT
);
9065 current_it_mask
= (inst
.instruction
& 0xf) | 0x10;
9068 /* If the condition is a negative condition, invert the mask. */
9069 if ((cond
& 0x1) == 0x0)
9071 unsigned int mask
= inst
.instruction
& 0x000f;
9073 if ((mask
& 0x7) == 0)
9074 /* no conversion needed */;
9075 else if ((mask
& 0x3) == 0)
9077 else if ((mask
& 0x1) == 0)
9082 inst
.instruction
&= 0xfff0;
9083 inst
.instruction
|= mask
;
9086 inst
.instruction
|= cond
<< 4;
9089 /* Helper function used for both push/pop and ldm/stm. */
9091 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9095 load
= (inst
.instruction
& (1 << 20)) != 0;
9097 if (mask
& (1 << 13))
9098 inst
.error
= _("SP not allowed in register list");
9101 if (mask
& (1 << 14)
9102 && mask
& (1 << 15))
9103 inst
.error
= _("LR and PC should not both be in register list");
9105 if ((mask
& (1 << base
)) != 0
9107 as_warn (_("base register should not be in register list "
9108 "when written back"));
9112 if (mask
& (1 << 15))
9113 inst
.error
= _("PC not allowed in register list");
9115 if (mask
& (1 << base
))
9116 as_warn (_("value stored for r%d is UNPREDICTABLE"), base
);
9119 if ((mask
& (mask
- 1)) == 0)
9121 /* Single register transfers implemented as str/ldr. */
9124 if (inst
.instruction
& (1 << 23))
9125 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9127 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9131 if (inst
.instruction
& (1 << 23))
9132 inst
.instruction
= 0x00800000; /* ia -> [base] */
9134 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9137 inst
.instruction
|= 0xf8400000;
9139 inst
.instruction
|= 0x00100000;
9141 mask
= ffs(mask
) - 1;
9145 inst
.instruction
|= WRITE_BACK
;
9147 inst
.instruction
|= mask
;
9148 inst
.instruction
|= base
<< 16;
9154 /* This really doesn't seem worth it. */
9155 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9156 _("expression too complex"));
9157 constraint (inst
.operands
[1].writeback
,
9158 _("Thumb load/store multiple does not support {reglist}^"));
9166 /* See if we can use a 16-bit instruction. */
9167 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9168 && inst
.size_req
!= 4
9169 && !(inst
.operands
[1].imm
& ~0xff))
9171 mask
= 1 << inst
.operands
[0].reg
;
9173 if (inst
.operands
[0].reg
<= 7
9174 && (inst
.instruction
== T_MNEM_stmia
9175 ? inst
.operands
[0].writeback
9176 : (inst
.operands
[0].writeback
9177 == !(inst
.operands
[1].imm
& mask
))))
9179 if (inst
.instruction
== T_MNEM_stmia
9180 && (inst
.operands
[1].imm
& mask
)
9181 && (inst
.operands
[1].imm
& (mask
- 1)))
9182 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9183 inst
.operands
[0].reg
);
9185 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9186 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9187 inst
.instruction
|= inst
.operands
[1].imm
;
9190 else if (inst
.operands
[0] .reg
== REG_SP
9191 && inst
.operands
[0].writeback
)
9193 inst
.instruction
= THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9194 ? T_MNEM_push
: T_MNEM_pop
);
9195 inst
.instruction
|= inst
.operands
[1].imm
;
9202 if (inst
.instruction
< 0xffff)
9203 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9205 encode_thumb2_ldmstm(inst
.operands
[0].reg
, inst
.operands
[1].imm
,
9206 inst
.operands
[0].writeback
);
9211 constraint (inst
.operands
[0].reg
> 7
9212 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9213 constraint (inst
.instruction
!= T_MNEM_ldmia
9214 && inst
.instruction
!= T_MNEM_stmia
,
9215 _("Thumb-2 instruction only valid in unified syntax"));
9216 if (inst
.instruction
== T_MNEM_stmia
)
9218 if (!inst
.operands
[0].writeback
)
9219 as_warn (_("this instruction will write back the base register"));
9220 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9221 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9222 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9223 inst
.operands
[0].reg
);
9227 if (!inst
.operands
[0].writeback
9228 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9229 as_warn (_("this instruction will write back the base register"));
9230 else if (inst
.operands
[0].writeback
9231 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9232 as_warn (_("this instruction will not write back the base register"));
9235 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9236 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9237 inst
.instruction
|= inst
.operands
[1].imm
;
9244 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9245 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9246 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9247 || inst
.operands
[1].negative
,
9250 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9251 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9252 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9258 if (!inst
.operands
[1].present
)
9260 constraint (inst
.operands
[0].reg
== REG_LR
,
9261 _("r14 not allowed as first register "
9262 "when second register is omitted"));
9263 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9265 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9268 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9269 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9270 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9276 unsigned long opcode
;
9279 opcode
= inst
.instruction
;
9282 if (!inst
.operands
[1].isreg
)
9284 if (opcode
<= 0xffff)
9285 inst
.instruction
= THUMB_OP32 (opcode
);
9286 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9289 if (inst
.operands
[1].isreg
9290 && !inst
.operands
[1].writeback
9291 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9292 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9294 && inst
.size_req
!= 4)
9296 /* Insn may have a 16-bit form. */
9297 Rn
= inst
.operands
[1].reg
;
9298 if (inst
.operands
[1].immisreg
)
9300 inst
.instruction
= THUMB_OP16 (opcode
);
9302 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9305 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9306 && opcode
!= T_MNEM_ldrsb
)
9307 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9308 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9315 if (inst
.reloc
.pc_rel
)
9316 opcode
= T_MNEM_ldr_pc2
;
9318 opcode
= T_MNEM_ldr_pc
;
9322 if (opcode
== T_MNEM_ldr
)
9323 opcode
= T_MNEM_ldr_sp
;
9325 opcode
= T_MNEM_str_sp
;
9327 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9331 inst
.instruction
= inst
.operands
[0].reg
;
9332 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9334 inst
.instruction
|= THUMB_OP16 (opcode
);
9335 if (inst
.size_req
== 2)
9336 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9338 inst
.relax
= opcode
;
9342 /* Definitely a 32-bit variant. */
9343 inst
.instruction
= THUMB_OP32 (opcode
);
9344 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9345 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9349 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9351 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9353 /* Only [Rn,Rm] is acceptable. */
9354 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9355 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9356 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9357 || inst
.operands
[1].negative
,
9358 _("Thumb does not support this addressing mode"));
9359 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9363 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9364 if (!inst
.operands
[1].isreg
)
9365 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9368 constraint (!inst
.operands
[1].preind
9369 || inst
.operands
[1].shifted
9370 || inst
.operands
[1].writeback
,
9371 _("Thumb does not support this addressing mode"));
9372 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9374 constraint (inst
.instruction
& 0x0600,
9375 _("byte or halfword not valid for base register"));
9376 constraint (inst
.operands
[1].reg
== REG_PC
9377 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9378 _("r15 based store not allowed"));
9379 constraint (inst
.operands
[1].immisreg
,
9380 _("invalid base register for register offset"));
9382 if (inst
.operands
[1].reg
== REG_PC
)
9383 inst
.instruction
= T_OPCODE_LDR_PC
;
9384 else if (inst
.instruction
& THUMB_LOAD_BIT
)
9385 inst
.instruction
= T_OPCODE_LDR_SP
;
9387 inst
.instruction
= T_OPCODE_STR_SP
;
9389 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9390 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9394 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
9395 if (!inst
.operands
[1].immisreg
)
9397 /* Immediate offset. */
9398 inst
.instruction
|= inst
.operands
[0].reg
;
9399 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9400 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9404 /* Register offset. */
9405 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
9406 constraint (inst
.operands
[1].negative
,
9407 _("Thumb does not support this addressing mode"));
9410 switch (inst
.instruction
)
9412 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
9413 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
9414 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
9415 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
9416 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
9417 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
9418 case 0x5600 /* ldrsb */:
9419 case 0x5e00 /* ldrsh */: break;
9423 inst
.instruction
|= inst
.operands
[0].reg
;
9424 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9425 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
9431 if (!inst
.operands
[1].present
)
9433 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9434 constraint (inst
.operands
[0].reg
== REG_LR
,
9435 _("r14 not allowed here"));
9437 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9438 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9439 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
9446 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9447 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
9453 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9454 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9455 inst
.instruction
|= inst
.operands
[2].reg
;
9456 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9462 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9463 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9464 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9465 inst
.instruction
|= inst
.operands
[3].reg
;
9473 int r0off
= (inst
.instruction
== T_MNEM_mov
9474 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
9475 unsigned long opcode
;
9477 bfd_boolean low_regs
;
9479 low_regs
= (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7);
9480 opcode
= inst
.instruction
;
9481 if (current_it_mask
)
9482 narrow
= opcode
!= T_MNEM_movs
;
9484 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
9485 if (inst
.size_req
== 4
9486 || inst
.operands
[1].shifted
)
9489 if (!inst
.operands
[1].isreg
)
9491 /* Immediate operand. */
9492 if (current_it_mask
== 0 && opcode
== T_MNEM_mov
)
9494 if (low_regs
&& narrow
)
9496 inst
.instruction
= THUMB_OP16 (opcode
);
9497 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9498 if (inst
.size_req
== 2)
9499 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9501 inst
.relax
= opcode
;
9505 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9506 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9507 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9508 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9513 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9514 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9515 encode_thumb32_shifted_operand (1);
9518 switch (inst
.instruction
)
9521 inst
.instruction
= T_OPCODE_MOV_HR
;
9522 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9523 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9524 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9528 /* We know we have low registers at this point.
9529 Generate ADD Rd, Rs, #0. */
9530 inst
.instruction
= T_OPCODE_ADD_I3
;
9531 inst
.instruction
|= inst
.operands
[0].reg
;
9532 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9538 inst
.instruction
= T_OPCODE_CMP_LR
;
9539 inst
.instruction
|= inst
.operands
[0].reg
;
9540 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9544 inst
.instruction
= T_OPCODE_CMP_HR
;
9545 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9546 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9547 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9554 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9555 if (inst
.operands
[1].isreg
)
9557 if (inst
.operands
[0].reg
< 8 && inst
.operands
[1].reg
< 8)
9559 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
9560 since a MOV instruction produces unpredictable results. */
9561 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9562 inst
.instruction
= T_OPCODE_ADD_I3
;
9564 inst
.instruction
= T_OPCODE_CMP_LR
;
9566 inst
.instruction
|= inst
.operands
[0].reg
;
9567 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9571 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9572 inst
.instruction
= T_OPCODE_MOV_HR
;
9574 inst
.instruction
= T_OPCODE_CMP_HR
;
9580 constraint (inst
.operands
[0].reg
> 7,
9581 _("only lo regs allowed with immediate"));
9582 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9583 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9593 top
= (inst
.instruction
& 0x00800000) != 0;
9594 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
9596 constraint (top
, _(":lower16: not allowed this instruction"));
9597 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
9599 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
9601 constraint (!top
, _(":upper16: not allowed this instruction"));
9602 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
9605 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9606 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9608 imm
= inst
.reloc
.exp
.X_add_number
;
9609 inst
.instruction
|= (imm
& 0xf000) << 4;
9610 inst
.instruction
|= (imm
& 0x0800) << 15;
9611 inst
.instruction
|= (imm
& 0x0700) << 4;
9612 inst
.instruction
|= (imm
& 0x00ff);
9621 int r0off
= (inst
.instruction
== T_MNEM_mvn
9622 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
9625 if (inst
.size_req
== 4
9626 || inst
.instruction
> 0xffff
9627 || inst
.operands
[1].shifted
9628 || inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9630 else if (inst
.instruction
== T_MNEM_cmn
)
9632 else if (THUMB_SETS_FLAGS (inst
.instruction
))
9633 narrow
= (current_it_mask
== 0);
9635 narrow
= (current_it_mask
!= 0);
9637 if (!inst
.operands
[1].isreg
)
9639 /* For an immediate, we always generate a 32-bit opcode;
9640 section relaxation will shrink it later if possible. */
9641 if (inst
.instruction
< 0xffff)
9642 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9643 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9644 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9645 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9649 /* See if we can do this with a 16-bit instruction. */
9652 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9653 inst
.instruction
|= inst
.operands
[0].reg
;
9654 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9658 constraint (inst
.operands
[1].shifted
9659 && inst
.operands
[1].immisreg
,
9660 _("shift must be constant"));
9661 if (inst
.instruction
< 0xffff)
9662 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9663 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9664 encode_thumb32_shifted_operand (1);
9670 constraint (inst
.instruction
> 0xffff
9671 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
9672 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
9673 _("unshifted register required"));
9674 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9677 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9678 inst
.instruction
|= inst
.operands
[0].reg
;
9679 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9688 if (do_vfp_nsyn_mrs () == SUCCESS
)
9691 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
9694 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
9695 _("selected processor does not support "
9696 "requested special purpose register"));
9700 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9701 _("selected processor does not support "
9702 "requested special purpose register %x"));
9703 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9704 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
9705 _("'CPSR' or 'SPSR' expected"));
9708 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9709 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9710 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
9718 if (do_vfp_nsyn_msr () == SUCCESS
)
9721 constraint (!inst
.operands
[1].isreg
,
9722 _("Thumb encoding does not support an immediate here"));
9723 flags
= inst
.operands
[0].imm
;
9726 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9727 _("selected processor does not support "
9728 "requested special purpose register"));
9732 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
9733 _("selected processor does not support "
9734 "requested special purpose register"));
9737 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9738 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
9739 inst
.instruction
|= (flags
& 0xff);
9740 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9746 if (!inst
.operands
[2].present
)
9747 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9749 /* There is no 32-bit MULS and no 16-bit MUL. */
9750 if (unified_syntax
&& inst
.instruction
== T_MNEM_mul
)
9752 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9753 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9754 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9755 inst
.instruction
|= inst
.operands
[2].reg
<< 0;
9759 constraint (!unified_syntax
9760 && inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
9761 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9764 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9765 inst
.instruction
|= inst
.operands
[0].reg
;
9767 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9768 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9769 else if (inst
.operands
[0].reg
== inst
.operands
[2].reg
)
9770 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9772 constraint (1, _("dest must overlap one source register"));
9779 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9780 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9781 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9782 inst
.instruction
|= inst
.operands
[3].reg
;
9784 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9785 as_tsktsk (_("rdhi and rdlo must be different"));
9793 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
9795 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9796 inst
.instruction
|= inst
.operands
[0].imm
;
9800 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9801 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
9806 constraint (inst
.operands
[0].present
,
9807 _("Thumb does not support NOP with hints"));
9808 inst
.instruction
= 0x46c0;
9819 if (THUMB_SETS_FLAGS (inst
.instruction
))
9820 narrow
= (current_it_mask
== 0);
9822 narrow
= (current_it_mask
!= 0);
9823 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9825 if (inst
.size_req
== 4)
9830 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9831 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9832 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9836 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9837 inst
.instruction
|= inst
.operands
[0].reg
;
9838 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9843 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9845 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9847 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9848 inst
.instruction
|= inst
.operands
[0].reg
;
9849 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9856 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9857 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9858 inst
.instruction
|= inst
.operands
[2].reg
;
9859 if (inst
.operands
[3].present
)
9861 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
9862 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9863 _("expression too complex"));
9864 inst
.instruction
|= (val
& 0x1c) << 10;
9865 inst
.instruction
|= (val
& 0x03) << 6;
9872 if (!inst
.operands
[3].present
)
9873 inst
.instruction
&= ~0x00000020;
9880 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9884 do_t_push_pop (void)
9888 constraint (inst
.operands
[0].writeback
,
9889 _("push/pop do not support {reglist}^"));
9890 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9891 _("expression too complex"));
9893 mask
= inst
.operands
[0].imm
;
9894 if ((mask
& ~0xff) == 0)
9895 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
9896 else if ((inst
.instruction
== T_MNEM_push
9897 && (mask
& ~0xff) == 1 << REG_LR
)
9898 || (inst
.instruction
== T_MNEM_pop
9899 && (mask
& ~0xff) == 1 << REG_PC
))
9901 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9902 inst
.instruction
|= THUMB_PP_PC_LR
;
9903 inst
.instruction
|= mask
& 0xff;
9905 else if (unified_syntax
)
9907 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9908 encode_thumb2_ldmstm(13, mask
, TRUE
);
9912 inst
.error
= _("invalid register list to push/pop instruction");
9920 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9921 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9927 if (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
9928 && inst
.size_req
!= 4)
9930 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9931 inst
.instruction
|= inst
.operands
[0].reg
;
9932 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9934 else if (unified_syntax
)
9936 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9937 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9938 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9939 inst
.instruction
|= inst
.operands
[1].reg
;
9942 inst
.error
= BAD_HIREG
;
9950 Rd
= inst
.operands
[0].reg
;
9951 Rs
= (inst
.operands
[1].present
9952 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9953 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9955 inst
.instruction
|= Rd
<< 8;
9956 inst
.instruction
|= Rs
<< 16;
9957 if (!inst
.operands
[2].isreg
)
9959 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9960 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9963 encode_thumb32_shifted_operand (2);
9969 constraint (current_it_mask
, BAD_NOT_IT
);
9970 if (inst
.operands
[0].imm
)
9971 inst
.instruction
|= 0x8;
9977 if (!inst
.operands
[1].present
)
9978 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9985 switch (inst
.instruction
)
9988 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
9990 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
9992 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
9994 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
9998 if (THUMB_SETS_FLAGS (inst
.instruction
))
9999 narrow
= (current_it_mask
== 0);
10001 narrow
= (current_it_mask
!= 0);
10002 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10004 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
10006 if (inst
.operands
[2].isreg
10007 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
10008 || inst
.operands
[2].reg
> 7))
10010 if (inst
.size_req
== 4)
10015 if (inst
.operands
[2].isreg
)
10017 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10018 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10019 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10020 inst
.instruction
|= inst
.operands
[2].reg
;
10024 inst
.operands
[1].shifted
= 1;
10025 inst
.operands
[1].shift_kind
= shift_kind
;
10026 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
10027 ? T_MNEM_movs
: T_MNEM_mov
);
10028 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10029 encode_thumb32_shifted_operand (1);
10030 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
10031 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10036 if (inst
.operands
[2].isreg
)
10038 switch (shift_kind
)
10040 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10041 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10042 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10043 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10047 inst
.instruction
|= inst
.operands
[0].reg
;
10048 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10052 switch (shift_kind
)
10054 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10055 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10056 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10059 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10060 inst
.instruction
|= inst
.operands
[0].reg
;
10061 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10067 constraint (inst
.operands
[0].reg
> 7
10068 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
10069 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10071 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
10073 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
10074 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
10075 _("source1 and dest must be same register"));
10077 switch (inst
.instruction
)
10079 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10080 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10081 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10082 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10086 inst
.instruction
|= inst
.operands
[0].reg
;
10087 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10091 switch (inst
.instruction
)
10093 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10094 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10095 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10096 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
10099 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10100 inst
.instruction
|= inst
.operands
[0].reg
;
10101 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10109 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10110 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10111 inst
.instruction
|= inst
.operands
[2].reg
;
10117 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10118 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10119 _("expression too complex"));
10120 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10121 inst
.instruction
|= (value
& 0xf000) >> 12;
10122 inst
.instruction
|= (value
& 0x0ff0);
10123 inst
.instruction
|= (value
& 0x000f) << 16;
10129 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10130 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10131 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10133 if (inst
.operands
[3].present
)
10135 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10136 _("expression too complex"));
10138 if (inst
.reloc
.exp
.X_add_number
!= 0)
10140 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10141 inst
.instruction
|= 0x00200000; /* sh bit */
10142 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10143 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10145 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10152 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10153 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10154 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10160 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10161 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10162 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10163 || inst
.operands
[2].negative
,
10166 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10167 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10168 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10169 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10175 if (!inst
.operands
[2].present
)
10176 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
10178 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10179 || inst
.operands
[0].reg
== inst
.operands
[2].reg
10180 || inst
.operands
[0].reg
== inst
.operands
[3].reg
10181 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
10184 inst
.instruction
|= inst
.operands
[0].reg
;
10185 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10186 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10187 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10193 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10194 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10195 inst
.instruction
|= inst
.operands
[2].reg
;
10196 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
10202 if (inst
.instruction
<= 0xffff && inst
.size_req
!= 4
10203 && inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
10204 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
10206 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10207 inst
.instruction
|= inst
.operands
[0].reg
;
10208 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10210 else if (unified_syntax
)
10212 if (inst
.instruction
<= 0xffff)
10213 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10214 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10215 inst
.instruction
|= inst
.operands
[1].reg
;
10216 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
10220 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
10221 _("Thumb encoding does not support rotation"));
10222 constraint (1, BAD_HIREG
);
10229 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
10237 half
= (inst
.instruction
& 0x10) != 0;
10238 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
10239 constraint (inst
.operands
[0].immisreg
,
10240 _("instruction requires register index"));
10241 constraint (inst
.operands
[0].imm
== 15,
10242 _("PC is not a valid index register"));
10243 constraint (!half
&& inst
.operands
[0].shifted
,
10244 _("instruction does not allow shifted index"));
10245 inst
.instruction
|= (inst
.operands
[0].reg
<< 16) | inst
.operands
[0].imm
;
10251 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10252 inst
.instruction
|= inst
.operands
[1].imm
;
10253 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10255 if (inst
.operands
[3].present
)
10257 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10258 _("expression too complex"));
10259 if (inst
.reloc
.exp
.X_add_number
!= 0)
10261 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10262 inst
.instruction
|= 0x00200000; /* sh bit */
10264 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10265 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10267 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10274 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10275 inst
.instruction
|= inst
.operands
[1].imm
;
10276 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10279 /* Neon instruction encoder helpers. */
10281 /* Encodings for the different types for various Neon opcodes. */
10283 /* An "invalid" code for the following tables. */
10286 struct neon_tab_entry
10289 unsigned float_or_poly
;
10290 unsigned scalar_or_imm
;
10293 /* Map overloaded Neon opcodes to their respective encodings. */
10294 #define NEON_ENC_TAB \
10295 X(vabd, 0x0000700, 0x1200d00, N_INV), \
10296 X(vmax, 0x0000600, 0x0000f00, N_INV), \
10297 X(vmin, 0x0000610, 0x0200f00, N_INV), \
10298 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
10299 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
10300 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
10301 X(vadd, 0x0000800, 0x0000d00, N_INV), \
10302 X(vsub, 0x1000800, 0x0200d00, N_INV), \
10303 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
10304 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
10305 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
10306 /* Register variants of the following two instructions are encoded as
10307 vcge / vcgt with the operands reversed. */ \
10308 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
10309 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
10310 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
10311 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
10312 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
10313 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
10314 X(vmlal, 0x0800800, N_INV, 0x0800240), \
10315 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
10316 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
10317 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
10318 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
10319 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
10320 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
10321 X(vshl, 0x0000400, N_INV, 0x0800510), \
10322 X(vqshl, 0x0000410, N_INV, 0x0800710), \
10323 X(vand, 0x0000110, N_INV, 0x0800030), \
10324 X(vbic, 0x0100110, N_INV, 0x0800030), \
10325 X(veor, 0x1000110, N_INV, N_INV), \
10326 X(vorn, 0x0300110, N_INV, 0x0800010), \
10327 X(vorr, 0x0200110, N_INV, 0x0800010), \
10328 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
10329 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
10330 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
10331 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
10332 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
10333 X(vst1, 0x0000000, 0x0800000, N_INV), \
10334 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
10335 X(vst2, 0x0000100, 0x0800100, N_INV), \
10336 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
10337 X(vst3, 0x0000200, 0x0800200, N_INV), \
10338 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
10339 X(vst4, 0x0000300, 0x0800300, N_INV), \
10340 X(vmovn, 0x1b20200, N_INV, N_INV), \
10341 X(vtrn, 0x1b20080, N_INV, N_INV), \
10342 X(vqmovn, 0x1b20200, N_INV, N_INV), \
10343 X(vqmovun, 0x1b20240, N_INV, N_INV), \
10344 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
10345 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \
10346 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \
10347 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
10348 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
10349 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
10350 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
10354 #define X(OPC,I,F,S) N_MNEM_##OPC
10359 static const struct neon_tab_entry neon_enc_tab
[] =
10361 #define X(OPC,I,F,S) { (I), (F), (S) }
10366 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10367 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10368 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10369 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10370 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10371 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10372 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10373 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10374 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10375 #define NEON_ENC_SINGLE(X) \
10376 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
10377 #define NEON_ENC_DOUBLE(X) \
10378 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
10380 /* Define shapes for instruction operands. The following mnemonic characters
10381 are used in this table:
10383 F - VFP S<n> register
10384 D - Neon D<n> register
10385 Q - Neon Q<n> register
10389 L - D<n> register list
10391 This table is used to generate various data:
10392 - enumerations of the form NS_DDR to be used as arguments to
10394 - a table classifying shapes into single, double, quad, mixed.
10395 - a table used to drive neon_select_shape.
10398 #define NEON_SHAPE_DEF \
10399 X(3, (D, D, D), DOUBLE), \
10400 X(3, (Q, Q, Q), QUAD), \
10401 X(3, (D, D, I), DOUBLE), \
10402 X(3, (Q, Q, I), QUAD), \
10403 X(3, (D, D, S), DOUBLE), \
10404 X(3, (Q, Q, S), QUAD), \
10405 X(2, (D, D), DOUBLE), \
10406 X(2, (Q, Q), QUAD), \
10407 X(2, (D, S), DOUBLE), \
10408 X(2, (Q, S), QUAD), \
10409 X(2, (D, R), DOUBLE), \
10410 X(2, (Q, R), QUAD), \
10411 X(2, (D, I), DOUBLE), \
10412 X(2, (Q, I), QUAD), \
10413 X(3, (D, L, D), DOUBLE), \
10414 X(2, (D, Q), MIXED), \
10415 X(2, (Q, D), MIXED), \
10416 X(3, (D, Q, I), MIXED), \
10417 X(3, (Q, D, I), MIXED), \
10418 X(3, (Q, D, D), MIXED), \
10419 X(3, (D, Q, Q), MIXED), \
10420 X(3, (Q, Q, D), MIXED), \
10421 X(3, (Q, D, S), MIXED), \
10422 X(3, (D, Q, S), MIXED), \
10423 X(4, (D, D, D, I), DOUBLE), \
10424 X(4, (Q, Q, Q, I), QUAD), \
10425 X(2, (F, F), SINGLE), \
10426 X(3, (F, F, F), SINGLE), \
10427 X(2, (F, I), SINGLE), \
10428 X(2, (F, D), MIXED), \
10429 X(2, (D, F), MIXED), \
10430 X(3, (F, F, I), MIXED), \
10431 X(4, (R, R, F, F), SINGLE), \
10432 X(4, (F, F, R, R), SINGLE), \
10433 X(3, (D, R, R), DOUBLE), \
10434 X(3, (R, R, D), DOUBLE), \
10435 X(2, (S, R), SINGLE), \
10436 X(2, (R, S), SINGLE), \
10437 X(2, (F, R), SINGLE), \
10438 X(2, (R, F), SINGLE)
10440 #define S2(A,B) NS_##A##B
10441 #define S3(A,B,C) NS_##A##B##C
10442 #define S4(A,B,C,D) NS_##A##B##C##D
10444 #define X(N, L, C) S##N L
10457 enum neon_shape_class
10465 #define X(N, L, C) SC_##C
10467 static enum neon_shape_class neon_shape_class
[] =
10485 /* Register widths of above. */
10486 static unsigned neon_shape_el_size
[] =
10497 struct neon_shape_info
10500 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
10503 #define S2(A,B) { SE_##A, SE_##B }
10504 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
10505 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
10507 #define X(N, L, C) { N, S##N L }
10509 static struct neon_shape_info neon_shape_tab
[] =
10519 /* Bit masks used in type checking given instructions.
10520 'N_EQK' means the type must be the same as (or based on in some way) the key
10521 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
10522 set, various other bits can be set as well in order to modify the meaning of
10523 the type constraint. */
10525 enum neon_type_mask
10547 N_KEY
= 0x100000, /* key element (main type specifier). */
10548 N_EQK
= 0x200000, /* given operand has the same type & size as the key. */
10549 N_VFP
= 0x400000, /* VFP mode: operand size must match register width. */
10550 N_DBL
= 0x000001, /* if N_EQK, this operand is twice the size. */
10551 N_HLF
= 0x000002, /* if N_EQK, this operand is half the size. */
10552 N_SGN
= 0x000004, /* if N_EQK, this operand is forced to be signed. */
10553 N_UNS
= 0x000008, /* if N_EQK, this operand is forced to be unsigned. */
10554 N_INT
= 0x000010, /* if N_EQK, this operand is forced to be integer. */
10555 N_FLT
= 0x000020, /* if N_EQK, this operand is forced to be float. */
10556 N_SIZ
= 0x000040, /* if N_EQK, this operand is forced to be size-only. */
10558 N_MAX_NONSPECIAL
= N_F64
10561 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
10563 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
10564 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
10565 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
10566 #define N_SUF_32 (N_SU_32 | N_F32)
10567 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
10568 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
10570 /* Pass this as the first type argument to neon_check_type to ignore types
10572 #define N_IGNORE_TYPE (N_KEY | N_EQK)
10574 /* Select a "shape" for the current instruction (describing register types or
10575 sizes) from a list of alternatives. Return NS_NULL if the current instruction
10576 doesn't fit. For non-polymorphic shapes, checking is usually done as a
10577 function of operand parsing, so this function doesn't need to be called.
10578 Shapes should be listed in order of decreasing length. */
10580 static enum neon_shape
10581 neon_select_shape (enum neon_shape shape
, ...)
10584 enum neon_shape first_shape
= shape
;
10586 /* Fix missing optional operands. FIXME: we don't know at this point how
10587 many arguments we should have, so this makes the assumption that we have
10588 > 1. This is true of all current Neon opcodes, I think, but may not be
10589 true in the future. */
10590 if (!inst
.operands
[1].present
)
10591 inst
.operands
[1] = inst
.operands
[0];
10593 va_start (ap
, shape
);
10595 for (; shape
!= NS_NULL
; shape
= va_arg (ap
, int))
10600 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
10602 if (!inst
.operands
[j
].present
)
10608 switch (neon_shape_tab
[shape
].el
[j
])
10611 if (!(inst
.operands
[j
].isreg
10612 && inst
.operands
[j
].isvec
10613 && inst
.operands
[j
].issingle
10614 && !inst
.operands
[j
].isquad
))
10619 if (!(inst
.operands
[j
].isreg
10620 && inst
.operands
[j
].isvec
10621 && !inst
.operands
[j
].isquad
10622 && !inst
.operands
[j
].issingle
))
10627 if (!(inst
.operands
[j
].isreg
10628 && !inst
.operands
[j
].isvec
))
10633 if (!(inst
.operands
[j
].isreg
10634 && inst
.operands
[j
].isvec
10635 && inst
.operands
[j
].isquad
10636 && !inst
.operands
[j
].issingle
))
10641 if (!(!inst
.operands
[j
].isreg
10642 && !inst
.operands
[j
].isscalar
))
10647 if (!(!inst
.operands
[j
].isreg
10648 && inst
.operands
[j
].isscalar
))
10662 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
10663 first_error (_("invalid instruction shape"));
10668 /* True if SHAPE is predominantly a quadword operation (most of the time, this
10669 means the Q bit should be set). */
10672 neon_quad (enum neon_shape shape
)
10674 return neon_shape_class
[shape
] == SC_QUAD
;
10678 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
10681 /* Allow modification to be made to types which are constrained to be
10682 based on the key element, based on bits set alongside N_EQK. */
10683 if ((typebits
& N_EQK
) != 0)
10685 if ((typebits
& N_HLF
) != 0)
10687 else if ((typebits
& N_DBL
) != 0)
10689 if ((typebits
& N_SGN
) != 0)
10690 *g_type
= NT_signed
;
10691 else if ((typebits
& N_UNS
) != 0)
10692 *g_type
= NT_unsigned
;
10693 else if ((typebits
& N_INT
) != 0)
10694 *g_type
= NT_integer
;
10695 else if ((typebits
& N_FLT
) != 0)
10696 *g_type
= NT_float
;
10697 else if ((typebits
& N_SIZ
) != 0)
10698 *g_type
= NT_untyped
;
10702 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
10703 operand type, i.e. the single type specified in a Neon instruction when it
10704 is the only one given. */
10706 static struct neon_type_el
10707 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
10709 struct neon_type_el dest
= *key
;
10711 assert ((thisarg
& N_EQK
) != 0);
10713 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
10718 /* Convert Neon type and size into compact bitmask representation. */
10720 static enum neon_type_mask
10721 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
10728 case 8: return N_8
;
10729 case 16: return N_16
;
10730 case 32: return N_32
;
10731 case 64: return N_64
;
10739 case 8: return N_I8
;
10740 case 16: return N_I16
;
10741 case 32: return N_I32
;
10742 case 64: return N_I64
;
10750 case 32: return N_F32
;
10751 case 64: return N_F64
;
10759 case 8: return N_P8
;
10760 case 16: return N_P16
;
10768 case 8: return N_S8
;
10769 case 16: return N_S16
;
10770 case 32: return N_S32
;
10771 case 64: return N_S64
;
10779 case 8: return N_U8
;
10780 case 16: return N_U16
;
10781 case 32: return N_U32
;
10782 case 64: return N_U64
;
10793 /* Convert compact Neon bitmask type representation to a type and size. Only
10794 handles the case where a single bit is set in the mask. */
10797 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
10798 enum neon_type_mask mask
)
10800 if ((mask
& N_EQK
) != 0)
10803 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
10805 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
10807 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
10809 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
10814 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
10816 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
10817 *type
= NT_unsigned
;
10818 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
10819 *type
= NT_integer
;
10820 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
10821 *type
= NT_untyped
;
10822 else if ((mask
& (N_P8
| N_P16
)) != 0)
10824 else if ((mask
& (N_F32
| N_F64
)) != 0)
10832 /* Modify a bitmask of allowed types. This is only needed for type
10836 modify_types_allowed (unsigned allowed
, unsigned mods
)
10839 enum neon_el_type type
;
10845 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
10847 if (el_type_of_type_chk (&type
, &size
, allowed
& i
) == SUCCESS
)
10849 neon_modify_type_size (mods
, &type
, &size
);
10850 destmask
|= type_chk_of_el_type (type
, size
);
10857 /* Check type and return type classification.
10858 The manual states (paraphrase): If one datatype is given, it indicates the
10860 - the second operand, if there is one
10861 - the operand, if there is no second operand
10862 - the result, if there are no operands.
10863 This isn't quite good enough though, so we use a concept of a "key" datatype
10864 which is set on a per-instruction basis, which is the one which matters when
10865 only one data type is written.
10866 Note: this function has side-effects (e.g. filling in missing operands). All
10867 Neon instructions should call it before performing bit encoding. */
10869 static struct neon_type_el
10870 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
10873 unsigned i
, pass
, key_el
= 0;
10874 unsigned types
[NEON_MAX_TYPE_ELS
];
10875 enum neon_el_type k_type
= NT_invtype
;
10876 unsigned k_size
= -1u;
10877 struct neon_type_el badtype
= {NT_invtype
, -1};
10878 unsigned key_allowed
= 0;
10880 /* Optional registers in Neon instructions are always (not) in operand 1.
10881 Fill in the missing operand here, if it was omitted. */
10882 if (els
> 1 && !inst
.operands
[1].present
)
10883 inst
.operands
[1] = inst
.operands
[0];
10885 /* Suck up all the varargs. */
10887 for (i
= 0; i
< els
; i
++)
10889 unsigned thisarg
= va_arg (ap
, unsigned);
10890 if (thisarg
== N_IGNORE_TYPE
)
10895 types
[i
] = thisarg
;
10896 if ((thisarg
& N_KEY
) != 0)
10901 if (inst
.vectype
.elems
> 0)
10902 for (i
= 0; i
< els
; i
++)
10903 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
10905 first_error (_("types specified in both the mnemonic and operands"));
10909 /* Duplicate inst.vectype elements here as necessary.
10910 FIXME: No idea if this is exactly the same as the ARM assembler,
10911 particularly when an insn takes one register and one non-register
10913 if (inst
.vectype
.elems
== 1 && els
> 1)
10916 inst
.vectype
.elems
= els
;
10917 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
10918 for (j
= 0; j
< els
; j
++)
10920 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
10923 else if (inst
.vectype
.elems
== 0 && els
> 0)
10926 /* No types were given after the mnemonic, so look for types specified
10927 after each operand. We allow some flexibility here; as long as the
10928 "key" operand has a type, we can infer the others. */
10929 for (j
= 0; j
< els
; j
++)
10930 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
10931 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
10933 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
10935 for (j
= 0; j
< els
; j
++)
10936 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
10937 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
10942 first_error (_("operand types can't be inferred"));
10946 else if (inst
.vectype
.elems
!= els
)
10948 first_error (_("type specifier has the wrong number of parts"));
10952 for (pass
= 0; pass
< 2; pass
++)
10954 for (i
= 0; i
< els
; i
++)
10956 unsigned thisarg
= types
[i
];
10957 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
10958 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
10959 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
10960 unsigned g_size
= inst
.vectype
.el
[i
].size
;
10962 /* Decay more-specific signed & unsigned types to sign-insensitive
10963 integer types if sign-specific variants are unavailable. */
10964 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
10965 && (types_allowed
& N_SU_ALL
) == 0)
10966 g_type
= NT_integer
;
10968 /* If only untyped args are allowed, decay any more specific types to
10969 them. Some instructions only care about signs for some element
10970 sizes, so handle that properly. */
10971 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
10972 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
10973 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
10974 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
10975 g_type
= NT_untyped
;
10979 if ((thisarg
& N_KEY
) != 0)
10983 key_allowed
= thisarg
& ~N_KEY
;
10988 if ((thisarg
& N_VFP
) != 0)
10990 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
10991 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
10993 /* In VFP mode, operands must match register widths. If we
10994 have a key operand, use its width, else use the width of
10995 the current operand. */
11001 if (regwidth
!= match
)
11003 first_error (_("operand size must match register width"));
11008 if ((thisarg
& N_EQK
) == 0)
11010 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
11012 if ((given_type
& types_allowed
) == 0)
11014 first_error (_("bad type in Neon instruction"));
11020 enum neon_el_type mod_k_type
= k_type
;
11021 unsigned mod_k_size
= k_size
;
11022 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
11023 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
11025 first_error (_("inconsistent types in Neon instruction"));
11033 return inst
.vectype
.el
[key_el
];
11036 /* Neon-style VFP instruction forwarding. */
11038 /* Thumb VFP instructions have 0xE in the condition field. */
11041 do_vfp_cond_or_thumb (void)
11044 inst
.instruction
|= 0xe0000000;
11046 inst
.instruction
|= inst
.cond
<< 28;
11049 /* Look up and encode a simple mnemonic, for use as a helper function for the
11050 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
11051 etc. It is assumed that operand parsing has already been done, and that the
11052 operands are in the form expected by the given opcode (this isn't necessarily
11053 the same as the form in which they were parsed, hence some massaging must
11054 take place before this function is called).
11055 Checks current arch version against that in the looked-up opcode. */
11058 do_vfp_nsyn_opcode (const char *opname
)
11060 const struct asm_opcode
*opcode
;
11062 opcode
= hash_find (arm_ops_hsh
, opname
);
11067 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
11068 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
11073 inst
.instruction
= opcode
->tvalue
;
11074 opcode
->tencode ();
11078 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
11079 opcode
->aencode ();
11084 do_vfp_nsyn_add_sub (enum neon_shape rs
)
11086 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
11091 do_vfp_nsyn_opcode ("fadds");
11093 do_vfp_nsyn_opcode ("fsubs");
11098 do_vfp_nsyn_opcode ("faddd");
11100 do_vfp_nsyn_opcode ("fsubd");
11104 /* Check operand types to see if this is a VFP instruction, and if so call
11108 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
11110 enum neon_shape rs
;
11111 struct neon_type_el et
;
11116 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11117 et
= neon_check_type (2, rs
,
11118 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11122 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11123 et
= neon_check_type (3, rs
,
11124 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11131 if (et
.type
!= NT_invtype
)
11143 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
11145 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
11150 do_vfp_nsyn_opcode ("fmacs");
11152 do_vfp_nsyn_opcode ("fmscs");
11157 do_vfp_nsyn_opcode ("fmacd");
11159 do_vfp_nsyn_opcode ("fmscd");
11164 do_vfp_nsyn_mul (enum neon_shape rs
)
11167 do_vfp_nsyn_opcode ("fmuls");
11169 do_vfp_nsyn_opcode ("fmuld");
11173 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
11175 int is_neg
= (inst
.instruction
& 0x80) != 0;
11176 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
11181 do_vfp_nsyn_opcode ("fnegs");
11183 do_vfp_nsyn_opcode ("fabss");
11188 do_vfp_nsyn_opcode ("fnegd");
11190 do_vfp_nsyn_opcode ("fabsd");
11194 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
11195 insns belong to Neon, and are handled elsewhere. */
11198 do_vfp_nsyn_ldm_stm (int is_dbmode
)
11200 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
11204 do_vfp_nsyn_opcode ("fldmdbs");
11206 do_vfp_nsyn_opcode ("fldmias");
11211 do_vfp_nsyn_opcode ("fstmdbs");
11213 do_vfp_nsyn_opcode ("fstmias");
11218 do_vfp_nsyn_sqrt (void)
11220 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11221 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11224 do_vfp_nsyn_opcode ("fsqrts");
11226 do_vfp_nsyn_opcode ("fsqrtd");
11230 do_vfp_nsyn_div (void)
11232 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11233 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11234 N_F32
| N_F64
| N_KEY
| N_VFP
);
11237 do_vfp_nsyn_opcode ("fdivs");
11239 do_vfp_nsyn_opcode ("fdivd");
11243 do_vfp_nsyn_nmul (void)
11245 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11246 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11247 N_F32
| N_F64
| N_KEY
| N_VFP
);
11251 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11252 do_vfp_sp_dyadic ();
11256 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11257 do_vfp_dp_rd_rn_rm ();
11259 do_vfp_cond_or_thumb ();
11263 do_vfp_nsyn_cmp (void)
11265 if (inst
.operands
[1].isreg
)
11267 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11268 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11272 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11273 do_vfp_sp_monadic ();
11277 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11278 do_vfp_dp_rd_rm ();
11283 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
11284 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
11286 switch (inst
.instruction
& 0x0fffffff)
11289 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
11292 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
11300 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11301 do_vfp_sp_compare_z ();
11305 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11309 do_vfp_cond_or_thumb ();
11313 nsyn_insert_sp (void)
11315 inst
.operands
[1] = inst
.operands
[0];
11316 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
11317 inst
.operands
[0].reg
= 13;
11318 inst
.operands
[0].isreg
= 1;
11319 inst
.operands
[0].writeback
= 1;
11320 inst
.operands
[0].present
= 1;
11324 do_vfp_nsyn_push (void)
11327 if (inst
.operands
[1].issingle
)
11328 do_vfp_nsyn_opcode ("fstmdbs");
11330 do_vfp_nsyn_opcode ("fstmdbd");
11334 do_vfp_nsyn_pop (void)
11337 if (inst
.operands
[1].issingle
)
11338 do_vfp_nsyn_opcode ("fldmias");
11340 do_vfp_nsyn_opcode ("fldmiad");
11343 /* Fix up Neon data-processing instructions, ORing in the correct bits for
11344 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
11347 neon_dp_fixup (unsigned i
)
11351 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
11365 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
11369 neon_logbits (unsigned x
)
11371 return ffs (x
) - 4;
11374 #define LOW4(R) ((R) & 0xf)
11375 #define HI1(R) (((R) >> 4) & 1)
11377 /* Encode insns with bit pattern:
11379 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
11380 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
11382 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
11383 different meaning for some instruction. */
11386 neon_three_same (int isquad
, int ubit
, int size
)
11388 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11389 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11390 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
11391 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
11392 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
11393 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
11394 inst
.instruction
|= (isquad
!= 0) << 6;
11395 inst
.instruction
|= (ubit
!= 0) << 24;
11397 inst
.instruction
|= neon_logbits (size
) << 20;
11399 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11402 /* Encode instructions of the form:
11404 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
11405 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
11407 Don't write size if SIZE == -1. */
11410 neon_two_same (int qbit
, int ubit
, int size
)
11412 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11413 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11414 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11415 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11416 inst
.instruction
|= (qbit
!= 0) << 6;
11417 inst
.instruction
|= (ubit
!= 0) << 24;
11420 inst
.instruction
|= neon_logbits (size
) << 18;
11422 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11425 /* Neon instruction encoders, in approximate order of appearance. */
11428 do_neon_dyadic_i_su (void)
11430 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11431 struct neon_type_el et
= neon_check_type (3, rs
,
11432 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
11433 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11437 do_neon_dyadic_i64_su (void)
11439 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11440 struct neon_type_el et
= neon_check_type (3, rs
,
11441 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11442 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11446 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
11449 unsigned size
= et
.size
>> 3;
11450 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11451 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11452 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11453 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11454 inst
.instruction
|= (isquad
!= 0) << 6;
11455 inst
.instruction
|= immbits
<< 16;
11456 inst
.instruction
|= (size
>> 3) << 7;
11457 inst
.instruction
|= (size
& 0x7) << 19;
11459 inst
.instruction
|= (uval
!= 0) << 24;
11461 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11465 do_neon_shl_imm (void)
11467 if (!inst
.operands
[2].isreg
)
11469 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11470 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
11471 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11472 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
11476 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11477 struct neon_type_el et
= neon_check_type (3, rs
,
11478 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11481 /* VSHL/VQSHL 3-register variants have syntax such as:
11483 whereas other 3-register operations encoded by neon_three_same have
11486 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
11488 tmp
= inst
.operands
[2].reg
;
11489 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11490 inst
.operands
[1].reg
= tmp
;
11491 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11492 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11497 do_neon_qshl_imm (void)
11499 if (!inst
.operands
[2].isreg
)
11501 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11502 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
11504 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11505 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
11506 inst
.operands
[2].imm
);
11510 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11511 struct neon_type_el et
= neon_check_type (3, rs
,
11512 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11515 /* See note in do_neon_shl_imm. */
11516 tmp
= inst
.operands
[2].reg
;
11517 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11518 inst
.operands
[1].reg
= tmp
;
11519 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11520 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11525 do_neon_rshl (void)
11527 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11528 struct neon_type_el et
= neon_check_type (3, rs
,
11529 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11532 tmp
= inst
.operands
[2].reg
;
11533 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11534 inst
.operands
[1].reg
= tmp
;
11535 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11539 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
11541 /* Handle .I8 pseudo-instructions. */
11544 /* Unfortunately, this will make everything apart from zero out-of-range.
11545 FIXME is this the intended semantics? There doesn't seem much point in
11546 accepting .I8 if so. */
11547 immediate
|= immediate
<< 8;
11553 if (immediate
== (immediate
& 0x000000ff))
11555 *immbits
= immediate
;
11558 else if (immediate
== (immediate
& 0x0000ff00))
11560 *immbits
= immediate
>> 8;
11563 else if (immediate
== (immediate
& 0x00ff0000))
11565 *immbits
= immediate
>> 16;
11568 else if (immediate
== (immediate
& 0xff000000))
11570 *immbits
= immediate
>> 24;
11573 if ((immediate
& 0xffff) != (immediate
>> 16))
11574 goto bad_immediate
;
11575 immediate
&= 0xffff;
11578 if (immediate
== (immediate
& 0x000000ff))
11580 *immbits
= immediate
;
11583 else if (immediate
== (immediate
& 0x0000ff00))
11585 *immbits
= immediate
>> 8;
11590 first_error (_("immediate value out of range"));
11594 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
11598 neon_bits_same_in_bytes (unsigned imm
)
11600 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
11601 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
11602 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
11603 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
11606 /* For immediate of above form, return 0bABCD. */
11609 neon_squash_bits (unsigned imm
)
11611 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
11612 | ((imm
& 0x01000000) >> 21);
11615 /* Compress quarter-float representation to 0b...000 abcdefgh. */
11618 neon_qfloat_bits (unsigned imm
)
11620 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
11623 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
11624 the instruction. *OP is passed as the initial value of the op field, and
11625 may be set to a different value depending on the constant (i.e.
11626 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
11627 MVN). If the immediate looks like a repeated parttern then also
11628 try smaller element sizes. */
11631 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
11632 unsigned *immbits
, int *op
, int size
,
11633 enum neon_el_type type
)
11635 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
11637 if (type
== NT_float
&& !float_p
)
11640 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
11642 if (size
!= 32 || *op
== 1)
11644 *immbits
= neon_qfloat_bits (immlo
);
11650 if (neon_bits_same_in_bytes (immhi
)
11651 && neon_bits_same_in_bytes (immlo
))
11655 *immbits
= (neon_squash_bits (immhi
) << 4)
11656 | neon_squash_bits (immlo
);
11661 if (immhi
!= immlo
)
11667 if (immlo
== (immlo
& 0x000000ff))
11672 else if (immlo
== (immlo
& 0x0000ff00))
11674 *immbits
= immlo
>> 8;
11677 else if (immlo
== (immlo
& 0x00ff0000))
11679 *immbits
= immlo
>> 16;
11682 else if (immlo
== (immlo
& 0xff000000))
11684 *immbits
= immlo
>> 24;
11687 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
11689 *immbits
= (immlo
>> 8) & 0xff;
11692 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
11694 *immbits
= (immlo
>> 16) & 0xff;
11698 if ((immlo
& 0xffff) != (immlo
>> 16))
11705 if (immlo
== (immlo
& 0x000000ff))
11710 else if (immlo
== (immlo
& 0x0000ff00))
11712 *immbits
= immlo
>> 8;
11716 if ((immlo
& 0xff) != (immlo
>> 8))
11721 if (immlo
== (immlo
& 0x000000ff))
11723 /* Don't allow MVN with 8-bit immediate. */
11733 /* Write immediate bits [7:0] to the following locations:
11735 |28/24|23 19|18 16|15 4|3 0|
11736 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
11738 This function is used by VMOV/VMVN/VORR/VBIC. */
11741 neon_write_immbits (unsigned immbits
)
11743 inst
.instruction
|= immbits
& 0xf;
11744 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
11745 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
11748 /* Invert low-order SIZE bits of XHI:XLO. */
11751 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
11753 unsigned immlo
= xlo
? *xlo
: 0;
11754 unsigned immhi
= xhi
? *xhi
: 0;
11759 immlo
= (~immlo
) & 0xff;
11763 immlo
= (~immlo
) & 0xffff;
11767 immhi
= (~immhi
) & 0xffffffff;
11768 /* fall through. */
11771 immlo
= (~immlo
) & 0xffffffff;
11786 do_neon_logic (void)
11788 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
11790 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11791 neon_check_type (3, rs
, N_IGNORE_TYPE
);
11792 /* U bit and size field were set as part of the bitmask. */
11793 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11794 neon_three_same (neon_quad (rs
), 0, -1);
11798 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
11799 struct neon_type_el et
= neon_check_type (2, rs
,
11800 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
11801 enum neon_opc opcode
= inst
.instruction
& 0x0fffffff;
11805 if (et
.type
== NT_invtype
)
11808 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11810 immbits
= inst
.operands
[1].imm
;
11813 /* .i64 is a pseudo-op, so the immediate must be a repeating
11815 if (immbits
!= (inst
.operands
[1].regisimm
?
11816 inst
.operands
[1].reg
: 0))
11818 /* Set immbits to an invalid constant. */
11819 immbits
= 0xdeadbeef;
11826 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11830 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11834 /* Pseudo-instruction for VBIC. */
11835 neon_invert_size (&immbits
, 0, et
.size
);
11836 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11840 /* Pseudo-instruction for VORR. */
11841 neon_invert_size (&immbits
, 0, et
.size
);
11842 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11852 inst
.instruction
|= neon_quad (rs
) << 6;
11853 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11854 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11855 inst
.instruction
|= cmode
<< 8;
11856 neon_write_immbits (immbits
);
11858 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11863 do_neon_bitfield (void)
11865 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11866 neon_check_type (3, rs
, N_IGNORE_TYPE
);
11867 neon_three_same (neon_quad (rs
), 0, -1);
11871 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
11874 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11875 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
11877 if (et
.type
== NT_float
)
11879 inst
.instruction
= NEON_ENC_FLOAT (inst
.instruction
);
11880 neon_three_same (neon_quad (rs
), 0, -1);
11884 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11885 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
11890 do_neon_dyadic_if_su (void)
11892 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
11896 do_neon_dyadic_if_su_d (void)
11898 /* This version only allow D registers, but that constraint is enforced during
11899 operand parsing so we don't need to do anything extra here. */
11900 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
11904 do_neon_dyadic_if_i_d (void)
11906 /* The "untyped" case can't happen. Do this to stop the "U" bit being
11907 affected if we specify unsigned args. */
11908 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
11911 enum vfp_or_neon_is_neon_bits
11914 NEON_CHECK_ARCH
= 2
11917 /* Call this function if an instruction which may have belonged to the VFP or
11918 Neon instruction sets, but turned out to be a Neon instruction (due to the
11919 operand types involved, etc.). We have to check and/or fix-up a couple of
11922 - Make sure the user hasn't attempted to make a Neon instruction
11924 - Alter the value in the condition code field if necessary.
11925 - Make sure that the arch supports Neon instructions.
11927 Which of these operations take place depends on bits from enum
11928 vfp_or_neon_is_neon_bits.
11930 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
11931 current instruction's condition is COND_ALWAYS, the condition field is
11932 changed to inst.uncond_value. This is necessary because instructions shared
11933 between VFP and Neon may be conditional for the VFP variants only, and the
11934 unconditional Neon version must have, e.g., 0xF in the condition field. */
11937 vfp_or_neon_is_neon (unsigned check
)
11939 /* Conditions are always legal in Thumb mode (IT blocks). */
11940 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
11942 if (inst
.cond
!= COND_ALWAYS
)
11944 first_error (_(BAD_COND
));
11947 if (inst
.uncond_value
!= -1)
11948 inst
.instruction
|= inst
.uncond_value
<< 28;
11951 if ((check
& NEON_CHECK_ARCH
)
11952 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
11954 first_error (_(BAD_FPU
));
11962 do_neon_addsub_if_i (void)
11964 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
11967 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11970 /* The "untyped" case can't happen. Do this to stop the "U" bit being
11971 affected if we specify unsigned args. */
11972 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
11975 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
11977 V<op> A,B (A is operand 0, B is operand 2)
11982 so handle that case specially. */
11985 neon_exchange_operands (void)
11987 void *scratch
= alloca (sizeof (inst
.operands
[0]));
11988 if (inst
.operands
[1].present
)
11990 /* Swap operands[1] and operands[2]. */
11991 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
11992 inst
.operands
[1] = inst
.operands
[2];
11993 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
11997 inst
.operands
[1] = inst
.operands
[2];
11998 inst
.operands
[2] = inst
.operands
[0];
12003 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
12005 if (inst
.operands
[2].isreg
)
12008 neon_exchange_operands ();
12009 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
12013 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12014 struct neon_type_el et
= neon_check_type (2, rs
,
12015 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
12017 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12018 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12019 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12020 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12021 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12022 inst
.instruction
|= neon_quad (rs
) << 6;
12023 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12024 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12026 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12033 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
12037 do_neon_cmp_inv (void)
12039 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
12045 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
12048 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
12049 scalars, which are encoded in 5 bits, M : Rm.
12050 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
12051 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
12055 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
12057 unsigned regno
= NEON_SCALAR_REG (scalar
);
12058 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
12063 if (regno
> 7 || elno
> 3)
12065 return regno
| (elno
<< 3);
12068 if (regno
> 15 || elno
> 1)
12070 return regno
| (elno
<< 4);
12074 first_error (_("scalar out of range for multiply instruction"));
12080 /* Encode multiply / multiply-accumulate scalar instructions. */
12083 neon_mul_mac (struct neon_type_el et
, int ubit
)
12087 /* Give a more helpful error message if we have an invalid type. */
12088 if (et
.type
== NT_invtype
)
12091 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
12092 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12093 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12094 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12095 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12096 inst
.instruction
|= LOW4 (scalar
);
12097 inst
.instruction
|= HI1 (scalar
) << 5;
12098 inst
.instruction
|= (et
.type
== NT_float
) << 8;
12099 inst
.instruction
|= neon_logbits (et
.size
) << 20;
12100 inst
.instruction
|= (ubit
!= 0) << 24;
12102 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12106 do_neon_mac_maybe_scalar (void)
12108 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
12111 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12114 if (inst
.operands
[2].isscalar
)
12116 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
12117 struct neon_type_el et
= neon_check_type (3, rs
,
12118 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
12119 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12120 neon_mul_mac (et
, neon_quad (rs
));
12124 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12125 affected if we specify unsigned args. */
12126 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12133 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12134 struct neon_type_el et
= neon_check_type (3, rs
,
12135 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12136 neon_three_same (neon_quad (rs
), 0, et
.size
);
12139 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
12140 same types as the MAC equivalents. The polynomial type for this instruction
12141 is encoded the same as the integer type. */
12146 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
12149 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12152 if (inst
.operands
[2].isscalar
)
12153 do_neon_mac_maybe_scalar ();
12155 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
12159 do_neon_qdmulh (void)
12161 if (inst
.operands
[2].isscalar
)
12163 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
12164 struct neon_type_el et
= neon_check_type (3, rs
,
12165 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
12166 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12167 neon_mul_mac (et
, neon_quad (rs
));
12171 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12172 struct neon_type_el et
= neon_check_type (3, rs
,
12173 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
12174 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12175 /* The U bit (rounding) comes from bit mask. */
12176 neon_three_same (neon_quad (rs
), 0, et
.size
);
12181 do_neon_fcmp_absolute (void)
12183 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12184 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12185 /* Size field comes from bit mask. */
12186 neon_three_same (neon_quad (rs
), 1, -1);
12190 do_neon_fcmp_absolute_inv (void)
12192 neon_exchange_operands ();
12193 do_neon_fcmp_absolute ();
12197 do_neon_step (void)
12199 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12200 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12201 neon_three_same (neon_quad (rs
), 0, -1);
12205 do_neon_abs_neg (void)
12207 enum neon_shape rs
;
12208 struct neon_type_el et
;
12210 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
12213 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12216 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12217 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
12219 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12220 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12221 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12222 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12223 inst
.instruction
|= neon_quad (rs
) << 6;
12224 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12225 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12227 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12233 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12234 struct neon_type_el et
= neon_check_type (2, rs
,
12235 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12236 int imm
= inst
.operands
[2].imm
;
12237 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12238 _("immediate out of range for insert"));
12239 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12245 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12246 struct neon_type_el et
= neon_check_type (2, rs
,
12247 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12248 int imm
= inst
.operands
[2].imm
;
12249 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12250 _("immediate out of range for insert"));
12251 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
12255 do_neon_qshlu_imm (void)
12257 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12258 struct neon_type_el et
= neon_check_type (2, rs
,
12259 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
12260 int imm
= inst
.operands
[2].imm
;
12261 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12262 _("immediate out of range for shift"));
12263 /* Only encodes the 'U present' variant of the instruction.
12264 In this case, signed types have OP (bit 8) set to 0.
12265 Unsigned types have OP set to 1. */
12266 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
12267 /* The rest of the bits are the same as other immediate shifts. */
12268 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12272 do_neon_qmovn (void)
12274 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12275 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12276 /* Saturating move where operands can be signed or unsigned, and the
12277 destination has the same signedness. */
12278 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12279 if (et
.type
== NT_unsigned
)
12280 inst
.instruction
|= 0xc0;
12282 inst
.instruction
|= 0x80;
12283 neon_two_same (0, 1, et
.size
/ 2);
12287 do_neon_qmovun (void)
12289 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12290 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12291 /* Saturating move with unsigned results. Operands must be signed. */
12292 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12293 neon_two_same (0, 1, et
.size
/ 2);
12297 do_neon_rshift_sat_narrow (void)
12299 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12300 or unsigned. If operands are unsigned, results must also be unsigned. */
12301 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12302 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12303 int imm
= inst
.operands
[2].imm
;
12304 /* This gets the bounds check, size encoding and immediate bits calculation
12308 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
12309 VQMOVN.I<size> <Dd>, <Qm>. */
12312 inst
.operands
[2].present
= 0;
12313 inst
.instruction
= N_MNEM_vqmovn
;
12318 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12319 _("immediate out of range"));
12320 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
12324 do_neon_rshift_sat_narrow_u (void)
12326 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12327 or unsigned. If operands are unsigned, results must also be unsigned. */
12328 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12329 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12330 int imm
= inst
.operands
[2].imm
;
12331 /* This gets the bounds check, size encoding and immediate bits calculation
12335 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
12336 VQMOVUN.I<size> <Dd>, <Qm>. */
12339 inst
.operands
[2].present
= 0;
12340 inst
.instruction
= N_MNEM_vqmovun
;
12345 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12346 _("immediate out of range"));
12347 /* FIXME: The manual is kind of unclear about what value U should have in
12348 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
12350 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
12354 do_neon_movn (void)
12356 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12357 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12358 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12359 neon_two_same (0, 1, et
.size
/ 2);
12363 do_neon_rshift_narrow (void)
12365 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12366 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12367 int imm
= inst
.operands
[2].imm
;
12368 /* This gets the bounds check, size encoding and immediate bits calculation
12372 /* If immediate is zero then we are a pseudo-instruction for
12373 VMOVN.I<size> <Dd>, <Qm> */
12376 inst
.operands
[2].present
= 0;
12377 inst
.instruction
= N_MNEM_vmovn
;
12382 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12383 _("immediate out of range for narrowing operation"));
12384 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
12388 do_neon_shll (void)
12390 /* FIXME: Type checking when lengthening. */
12391 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
12392 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
12393 unsigned imm
= inst
.operands
[2].imm
;
12395 if (imm
== et
.size
)
12397 /* Maximum shift variant. */
12398 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12399 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12400 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12401 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12402 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12403 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12405 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12409 /* A more-specific type check for non-max versions. */
12410 et
= neon_check_type (2, NS_QDI
,
12411 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12412 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12413 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
12417 /* Check the various types for the VCVT instruction, and return which version
12418 the current instruction is. */
12421 neon_cvt_flavour (enum neon_shape rs
)
12423 #define CVT_VAR(C,X,Y) \
12424 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
12425 if (et.type != NT_invtype) \
12427 inst.error = NULL; \
12430 struct neon_type_el et
;
12431 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
12432 || rs
== NS_FF
) ? N_VFP
: 0;
12433 /* The instruction versions which take an immediate take one register
12434 argument, which is extended to the width of the full register. Thus the
12435 "source" and "destination" registers must have the same width. Hack that
12436 here by making the size equal to the key (wider, in this case) operand. */
12437 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
12439 CVT_VAR (0, N_S32
, N_F32
);
12440 CVT_VAR (1, N_U32
, N_F32
);
12441 CVT_VAR (2, N_F32
, N_S32
);
12442 CVT_VAR (3, N_F32
, N_U32
);
12446 /* VFP instructions. */
12447 CVT_VAR (4, N_F32
, N_F64
);
12448 CVT_VAR (5, N_F64
, N_F32
);
12449 CVT_VAR (6, N_S32
, N_F64
| key
);
12450 CVT_VAR (7, N_U32
, N_F64
| key
);
12451 CVT_VAR (8, N_F64
| key
, N_S32
);
12452 CVT_VAR (9, N_F64
| key
, N_U32
);
12453 /* VFP instructions with bitshift. */
12454 CVT_VAR (10, N_F32
| key
, N_S16
);
12455 CVT_VAR (11, N_F32
| key
, N_U16
);
12456 CVT_VAR (12, N_F64
| key
, N_S16
);
12457 CVT_VAR (13, N_F64
| key
, N_U16
);
12458 CVT_VAR (14, N_S16
, N_F32
| key
);
12459 CVT_VAR (15, N_U16
, N_F32
| key
);
12460 CVT_VAR (16, N_S16
, N_F64
| key
);
12461 CVT_VAR (17, N_U16
, N_F64
| key
);
12467 /* Neon-syntax VFP conversions. */
12470 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
12472 const char *opname
= 0;
12474 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
12476 /* Conversions with immediate bitshift. */
12477 const char *enc
[] =
12499 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12501 opname
= enc
[flavour
];
12502 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12503 _("operands 0 and 1 must be the same register"));
12504 inst
.operands
[1] = inst
.operands
[2];
12505 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
12510 /* Conversions without bitshift. */
12511 const char *enc
[] =
12525 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12526 opname
= enc
[flavour
];
12530 do_vfp_nsyn_opcode (opname
);
12534 do_vfp_nsyn_cvtz (void)
12536 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
12537 int flavour
= neon_cvt_flavour (rs
);
12538 const char *enc
[] =
12550 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
12551 do_vfp_nsyn_opcode (enc
[flavour
]);
12557 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
12558 NS_FD
, NS_DF
, NS_FF
, NS_NULL
);
12559 int flavour
= neon_cvt_flavour (rs
);
12561 /* VFP rather than Neon conversions. */
12564 do_vfp_nsyn_cvt (rs
, flavour
);
12573 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12576 /* Fixed-point conversion with #0 immediate is encoded as an
12577 integer conversion. */
12578 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
12580 unsigned immbits
= 32 - inst
.operands
[2].imm
;
12581 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
12582 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12584 inst
.instruction
|= enctab
[flavour
];
12585 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12586 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12587 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12588 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12589 inst
.instruction
|= neon_quad (rs
) << 6;
12590 inst
.instruction
|= 1 << 21;
12591 inst
.instruction
|= immbits
<< 16;
12593 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12601 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
12603 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12605 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12609 inst
.instruction
|= enctab
[flavour
];
12611 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12612 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12613 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12614 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12615 inst
.instruction
|= neon_quad (rs
) << 6;
12616 inst
.instruction
|= 2 << 18;
12618 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12623 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
12624 do_vfp_nsyn_cvt (rs
, flavour
);
12629 neon_move_immediate (void)
12631 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12632 struct neon_type_el et
= neon_check_type (2, rs
,
12633 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12634 unsigned immlo
, immhi
= 0, immbits
;
12635 int op
, cmode
, float_p
;
12637 constraint (et
.type
== NT_invtype
,
12638 _("operand size must be specified for immediate VMOV"));
12640 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
12641 op
= (inst
.instruction
& (1 << 5)) != 0;
12643 immlo
= inst
.operands
[1].imm
;
12644 if (inst
.operands
[1].regisimm
)
12645 immhi
= inst
.operands
[1].reg
;
12647 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
12648 _("immediate has bits set outside the operand size"));
12650 float_p
= inst
.operands
[1].immisfloat
;
12652 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
12653 et
.size
, et
.type
)) == FAIL
)
12655 /* Invert relevant bits only. */
12656 neon_invert_size (&immlo
, &immhi
, et
.size
);
12657 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
12658 with one or the other; those cases are caught by
12659 neon_cmode_for_move_imm. */
12661 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
12662 &op
, et
.size
, et
.type
)) == FAIL
)
12664 first_error (_("immediate out of range"));
12669 inst
.instruction
&= ~(1 << 5);
12670 inst
.instruction
|= op
<< 5;
12672 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12673 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12674 inst
.instruction
|= neon_quad (rs
) << 6;
12675 inst
.instruction
|= cmode
<< 8;
12677 neon_write_immbits (immbits
);
12683 if (inst
.operands
[1].isreg
)
12685 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12687 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12688 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12689 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12690 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12691 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12692 inst
.instruction
|= neon_quad (rs
) << 6;
12696 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12697 neon_move_immediate ();
12700 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12703 /* Encode instructions of form:
12705 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12706 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm |
12711 neon_mixed_length (struct neon_type_el et
, unsigned size
)
12713 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12714 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12715 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12716 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12717 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12718 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12719 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
12720 inst
.instruction
|= neon_logbits (size
) << 20;
12722 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12726 do_neon_dyadic_long (void)
12728 /* FIXME: Type checking for lengthening op. */
12729 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12730 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12731 neon_mixed_length (et
, et
.size
);
12735 do_neon_abal (void)
12737 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12738 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12739 neon_mixed_length (et
, et
.size
);
12743 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
12745 if (inst
.operands
[2].isscalar
)
12747 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
12748 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
12749 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12750 neon_mul_mac (et
, et
.type
== NT_unsigned
);
12754 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12755 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
12756 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12757 neon_mixed_length (et
, et
.size
);
12762 do_neon_mac_maybe_scalar_long (void)
12764 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
12768 do_neon_dyadic_wide (void)
12770 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
12771 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12772 neon_mixed_length (et
, et
.size
);
12776 do_neon_dyadic_narrow (void)
12778 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12779 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
12780 /* Operand sign is unimportant, and the U bit is part of the opcode,
12781 so force the operand type to integer. */
12782 et
.type
= NT_integer
;
12783 neon_mixed_length (et
, et
.size
/ 2);
12787 do_neon_mul_sat_scalar_long (void)
12789 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
12793 do_neon_vmull (void)
12795 if (inst
.operands
[2].isscalar
)
12796 do_neon_mac_maybe_scalar_long ();
12799 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12800 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
12801 if (et
.type
== NT_poly
)
12802 inst
.instruction
= NEON_ENC_POLY (inst
.instruction
);
12804 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12805 /* For polynomial encoding, size field must be 0b00 and the U bit must be
12806 zero. Should be OK as-is. */
12807 neon_mixed_length (et
, et
.size
);
12814 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
12815 struct neon_type_el et
= neon_check_type (3, rs
,
12816 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12817 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
12818 constraint (imm
>= (neon_quad (rs
) ? 16 : 8), _("shift out of range"));
12819 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12820 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12821 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12822 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12823 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12824 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12825 inst
.instruction
|= neon_quad (rs
) << 6;
12826 inst
.instruction
|= imm
<< 8;
12828 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12834 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12835 struct neon_type_el et
= neon_check_type (2, rs
,
12836 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12837 unsigned op
= (inst
.instruction
>> 7) & 3;
12838 /* N (width of reversed regions) is encoded as part of the bitmask. We
12839 extract it here to check the elements to be reversed are smaller.
12840 Otherwise we'd get a reserved instruction. */
12841 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
12842 assert (elsize
!= 0);
12843 constraint (et
.size
>= elsize
,
12844 _("elements must be smaller than reversal region"));
12845 neon_two_same (neon_quad (rs
), 1, et
.size
);
12851 if (inst
.operands
[1].isscalar
)
12853 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
12854 struct neon_type_el et
= neon_check_type (2, rs
,
12855 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12856 unsigned sizebits
= et
.size
>> 3;
12857 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
12858 int logsize
= neon_logbits (et
.size
);
12859 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
12861 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
12864 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12865 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12866 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12867 inst
.instruction
|= LOW4 (dm
);
12868 inst
.instruction
|= HI1 (dm
) << 5;
12869 inst
.instruction
|= neon_quad (rs
) << 6;
12870 inst
.instruction
|= x
<< 17;
12871 inst
.instruction
|= sizebits
<< 16;
12873 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12877 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
12878 struct neon_type_el et
= neon_check_type (2, rs
,
12879 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
12880 /* Duplicate ARM register to lanes of vector. */
12881 inst
.instruction
= NEON_ENC_ARMREG (inst
.instruction
);
12884 case 8: inst
.instruction
|= 0x400000; break;
12885 case 16: inst
.instruction
|= 0x000020; break;
12886 case 32: inst
.instruction
|= 0x000000; break;
12889 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
12890 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
12891 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
12892 inst
.instruction
|= neon_quad (rs
) << 21;
12893 /* The encoding for this instruction is identical for the ARM and Thumb
12894 variants, except for the condition field. */
12895 do_vfp_cond_or_thumb ();
12899 /* VMOV has particularly many variations. It can be one of:
12900 0. VMOV<c><q> <Qd>, <Qm>
12901 1. VMOV<c><q> <Dd>, <Dm>
12902 (Register operations, which are VORR with Rm = Rn.)
12903 2. VMOV<c><q>.<dt> <Qd>, #<imm>
12904 3. VMOV<c><q>.<dt> <Dd>, #<imm>
12906 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
12907 (ARM register to scalar.)
12908 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
12909 (Two ARM registers to vector.)
12910 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
12911 (Scalar to ARM register.)
12912 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
12913 (Vector to two ARM registers.)
12914 8. VMOV.F32 <Sd>, <Sm>
12915 9. VMOV.F64 <Dd>, <Dm>
12916 (VFP register moves.)
12917 10. VMOV.F32 <Sd>, #imm
12918 11. VMOV.F64 <Dd>, #imm
12919 (VFP float immediate load.)
12920 12. VMOV <Rd>, <Sm>
12921 (VFP single to ARM reg.)
12922 13. VMOV <Sd>, <Rm>
12923 (ARM reg to VFP single.)
12924 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
12925 (Two ARM regs to two VFP singles.)
12926 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
12927 (Two VFP singles to two ARM regs.)
12929 These cases can be disambiguated using neon_select_shape, except cases 1/9
12930 and 3/11 which depend on the operand type too.
12932 All the encoded bits are hardcoded by this function.
12934 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
12935 Cases 5, 7 may be used with VFPv2 and above.
12937 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
12938 can specify a type where it doesn't make sense to, and is ignored).
12944 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
12945 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
12947 struct neon_type_el et
;
12948 const char *ldconst
= 0;
12952 case NS_DD
: /* case 1/9. */
12953 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
12954 /* It is not an error here if no type is given. */
12956 if (et
.type
== NT_float
&& et
.size
== 64)
12958 do_vfp_nsyn_opcode ("fcpyd");
12961 /* fall through. */
12963 case NS_QQ
: /* case 0/1. */
12965 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12967 /* The architecture manual I have doesn't explicitly state which
12968 value the U bit should have for register->register moves, but
12969 the equivalent VORR instruction has U = 0, so do that. */
12970 inst
.instruction
= 0x0200110;
12971 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12972 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12973 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12974 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12975 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12976 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12977 inst
.instruction
|= neon_quad (rs
) << 6;
12979 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12983 case NS_DI
: /* case 3/11. */
12984 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
12986 if (et
.type
== NT_float
&& et
.size
== 64)
12988 /* case 11 (fconstd). */
12989 ldconst
= "fconstd";
12990 goto encode_fconstd
;
12992 /* fall through. */
12994 case NS_QI
: /* case 2/3. */
12995 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12997 inst
.instruction
= 0x0800010;
12998 neon_move_immediate ();
12999 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13002 case NS_SR
: /* case 4. */
13004 unsigned bcdebits
= 0;
13005 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
13006 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13007 int logsize
= neon_logbits (et
.size
);
13008 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
13009 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
13011 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
13013 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
13014 && et
.size
!= 32, _(BAD_FPU
));
13015 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
13016 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
13020 case 8: bcdebits
= 0x8; break;
13021 case 16: bcdebits
= 0x1; break;
13022 case 32: bcdebits
= 0x0; break;
13026 bcdebits
|= x
<< logsize
;
13028 inst
.instruction
= 0xe000b10;
13029 do_vfp_cond_or_thumb ();
13030 inst
.instruction
|= LOW4 (dn
) << 16;
13031 inst
.instruction
|= HI1 (dn
) << 7;
13032 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13033 inst
.instruction
|= (bcdebits
& 3) << 5;
13034 inst
.instruction
|= (bcdebits
>> 2) << 21;
13038 case NS_DRR
: /* case 5 (fmdrr). */
13039 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
13042 inst
.instruction
= 0xc400b10;
13043 do_vfp_cond_or_thumb ();
13044 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
13045 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
13046 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13047 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13050 case NS_RS
: /* case 6. */
13052 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
13053 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
13054 unsigned logsize
= neon_logbits (et
.size
);
13055 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
13056 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
13057 unsigned abcdebits
= 0;
13059 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
13061 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
13062 && et
.size
!= 32, _(BAD_FPU
));
13063 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
13064 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
13068 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
13069 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
13070 case 32: abcdebits
= 0x00; break;
13074 abcdebits
|= x
<< logsize
;
13075 inst
.instruction
= 0xe100b10;
13076 do_vfp_cond_or_thumb ();
13077 inst
.instruction
|= LOW4 (dn
) << 16;
13078 inst
.instruction
|= HI1 (dn
) << 7;
13079 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
13080 inst
.instruction
|= (abcdebits
& 3) << 5;
13081 inst
.instruction
|= (abcdebits
>> 2) << 21;
13085 case NS_RRD
: /* case 7 (fmrrd). */
13086 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
13089 inst
.instruction
= 0xc500b10;
13090 do_vfp_cond_or_thumb ();
13091 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
13092 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13093 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13094 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13097 case NS_FF
: /* case 8 (fcpys). */
13098 do_vfp_nsyn_opcode ("fcpys");
13101 case NS_FI
: /* case 10 (fconsts). */
13102 ldconst
= "fconsts";
13104 if (is_quarter_float (inst
.operands
[1].imm
))
13106 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
13107 do_vfp_nsyn_opcode (ldconst
);
13110 first_error (_("immediate out of range"));
13113 case NS_RF
: /* case 12 (fmrs). */
13114 do_vfp_nsyn_opcode ("fmrs");
13117 case NS_FR
: /* case 13 (fmsr). */
13118 do_vfp_nsyn_opcode ("fmsr");
13121 /* The encoders for the fmrrs and fmsrr instructions expect three operands
13122 (one of which is a list), but we have parsed four. Do some fiddling to
13123 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
13125 case NS_RRFF
: /* case 14 (fmrrs). */
13126 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
13127 _("VFP registers must be adjacent"));
13128 inst
.operands
[2].imm
= 2;
13129 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
13130 do_vfp_nsyn_opcode ("fmrrs");
13133 case NS_FFRR
: /* case 15 (fmsrr). */
13134 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
13135 _("VFP registers must be adjacent"));
13136 inst
.operands
[1] = inst
.operands
[2];
13137 inst
.operands
[2] = inst
.operands
[3];
13138 inst
.operands
[0].imm
= 2;
13139 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
13140 do_vfp_nsyn_opcode ("fmsrr");
13149 do_neon_rshift_round_imm (void)
13151 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13152 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
13153 int imm
= inst
.operands
[2].imm
;
13155 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
13158 inst
.operands
[2].present
= 0;
13163 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13164 _("immediate out of range for shift"));
13165 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
13170 do_neon_movl (void)
13172 struct neon_type_el et
= neon_check_type (2, NS_QD
,
13173 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13174 unsigned sizebits
= et
.size
>> 3;
13175 inst
.instruction
|= sizebits
<< 19;
13176 neon_two_same (0, et
.type
== NT_unsigned
, -1);
13182 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13183 struct neon_type_el et
= neon_check_type (2, rs
,
13184 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13185 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13186 neon_two_same (neon_quad (rs
), 1, et
.size
);
13190 do_neon_zip_uzp (void)
13192 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13193 struct neon_type_el et
= neon_check_type (2, rs
,
13194 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13195 if (rs
== NS_DD
&& et
.size
== 32)
13197 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
13198 inst
.instruction
= N_MNEM_vtrn
;
13202 neon_two_same (neon_quad (rs
), 1, et
.size
);
13206 do_neon_sat_abs_neg (void)
13208 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13209 struct neon_type_el et
= neon_check_type (2, rs
,
13210 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13211 neon_two_same (neon_quad (rs
), 1, et
.size
);
13215 do_neon_pair_long (void)
13217 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13218 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
13219 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
13220 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
13221 neon_two_same (neon_quad (rs
), 1, et
.size
);
13225 do_neon_recip_est (void)
13227 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13228 struct neon_type_el et
= neon_check_type (2, rs
,
13229 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
13230 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13231 neon_two_same (neon_quad (rs
), 1, et
.size
);
13237 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13238 struct neon_type_el et
= neon_check_type (2, rs
,
13239 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13240 neon_two_same (neon_quad (rs
), 1, et
.size
);
13246 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13247 struct neon_type_el et
= neon_check_type (2, rs
,
13248 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
13249 neon_two_same (neon_quad (rs
), 1, et
.size
);
13255 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13256 struct neon_type_el et
= neon_check_type (2, rs
,
13257 N_EQK
| N_INT
, N_8
| N_KEY
);
13258 neon_two_same (neon_quad (rs
), 1, et
.size
);
13264 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13265 neon_two_same (neon_quad (rs
), 1, -1);
13269 do_neon_tbl_tbx (void)
13271 unsigned listlenbits
;
13272 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
13274 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
13276 first_error (_("bad list length for table lookup"));
13280 listlenbits
= inst
.operands
[1].imm
- 1;
13281 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13282 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13283 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13284 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13285 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13286 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13287 inst
.instruction
|= listlenbits
<< 8;
13289 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13293 do_neon_ldm_stm (void)
13295 /* P, U and L bits are part of bitmask. */
13296 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
13297 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
13299 if (inst
.operands
[1].issingle
)
13301 do_vfp_nsyn_ldm_stm (is_dbmode
);
13305 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
13306 _("writeback (!) must be used for VLDMDB and VSTMDB"));
13308 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
13309 _("register list must contain at least 1 and at most 16 "
13312 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
13313 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
13314 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13315 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
13317 inst
.instruction
|= offsetbits
;
13319 do_vfp_cond_or_thumb ();
13323 do_neon_ldr_str (void)
13325 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
13327 if (inst
.operands
[0].issingle
)
13330 do_vfp_nsyn_opcode ("flds");
13332 do_vfp_nsyn_opcode ("fsts");
13337 do_vfp_nsyn_opcode ("fldd");
13339 do_vfp_nsyn_opcode ("fstd");
13343 /* "interleave" version also handles non-interleaving register VLD1/VST1
13347 do_neon_ld_st_interleave (void)
13349 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
13350 N_8
| N_16
| N_32
| N_64
);
13351 unsigned alignbits
= 0;
13353 /* The bits in this table go:
13354 0: register stride of one (0) or two (1)
13355 1,2: register list length, minus one (1, 2, 3, 4).
13356 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
13357 We use -1 for invalid entries. */
13358 const int typetable
[] =
13360 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
13361 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
13362 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
13363 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
13367 if (et
.type
== NT_invtype
)
13370 if (inst
.operands
[1].immisalign
)
13371 switch (inst
.operands
[1].imm
>> 8)
13373 case 64: alignbits
= 1; break;
13375 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13376 goto bad_alignment
;
13380 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13381 goto bad_alignment
;
13386 first_error (_("bad alignment"));
13390 inst
.instruction
|= alignbits
<< 4;
13391 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13393 /* Bits [4:6] of the immediate in a list specifier encode register stride
13394 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
13395 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
13396 up the right value for "type" in a table based on this value and the given
13397 list style, then stick it back. */
13398 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
13399 | (((inst
.instruction
>> 8) & 3) << 3);
13401 typebits
= typetable
[idx
];
13403 constraint (typebits
== -1, _("bad list type for instruction"));
13405 inst
.instruction
&= ~0xf00;
13406 inst
.instruction
|= typebits
<< 8;
13409 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
13410 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
13411 otherwise. The variable arguments are a list of pairs of legal (size, align)
13412 values, terminated with -1. */
13415 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
13418 int result
= FAIL
, thissize
, thisalign
;
13420 if (!inst
.operands
[1].immisalign
)
13426 va_start (ap
, do_align
);
13430 thissize
= va_arg (ap
, int);
13431 if (thissize
== -1)
13433 thisalign
= va_arg (ap
, int);
13435 if (size
== thissize
&& align
== thisalign
)
13438 while (result
!= SUCCESS
);
13442 if (result
== SUCCESS
)
13445 first_error (_("unsupported alignment for instruction"));
13451 do_neon_ld_st_lane (void)
13453 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13454 int align_good
, do_align
= 0;
13455 int logsize
= neon_logbits (et
.size
);
13456 int align
= inst
.operands
[1].imm
>> 8;
13457 int n
= (inst
.instruction
>> 8) & 3;
13458 int max_el
= 64 / et
.size
;
13460 if (et
.type
== NT_invtype
)
13463 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
13464 _("bad list length"));
13465 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
13466 _("scalar index out of range"));
13467 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
13469 _("stride of 2 unavailable when element size is 8"));
13473 case 0: /* VLD1 / VST1. */
13474 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
13476 if (align_good
== FAIL
)
13480 unsigned alignbits
= 0;
13483 case 16: alignbits
= 0x1; break;
13484 case 32: alignbits
= 0x3; break;
13487 inst
.instruction
|= alignbits
<< 4;
13491 case 1: /* VLD2 / VST2. */
13492 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
13494 if (align_good
== FAIL
)
13497 inst
.instruction
|= 1 << 4;
13500 case 2: /* VLD3 / VST3. */
13501 constraint (inst
.operands
[1].immisalign
,
13502 _("can't use alignment with this instruction"));
13505 case 3: /* VLD4 / VST4. */
13506 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13507 16, 64, 32, 64, 32, 128, -1);
13508 if (align_good
== FAIL
)
13512 unsigned alignbits
= 0;
13515 case 8: alignbits
= 0x1; break;
13516 case 16: alignbits
= 0x1; break;
13517 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
13520 inst
.instruction
|= alignbits
<< 4;
13527 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
13528 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13529 inst
.instruction
|= 1 << (4 + logsize
);
13531 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
13532 inst
.instruction
|= logsize
<< 10;
13535 /* Encode single n-element structure to all lanes VLD<n> instructions. */
13538 do_neon_ld_dup (void)
13540 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13541 int align_good
, do_align
= 0;
13543 if (et
.type
== NT_invtype
)
13546 switch ((inst
.instruction
>> 8) & 3)
13548 case 0: /* VLD1. */
13549 assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
13550 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13551 &do_align
, 16, 16, 32, 32, -1);
13552 if (align_good
== FAIL
)
13554 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
13557 case 2: inst
.instruction
|= 1 << 5; break;
13558 default: first_error (_("bad list length")); return;
13560 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13563 case 1: /* VLD2. */
13564 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13565 &do_align
, 8, 16, 16, 32, 32, 64, -1);
13566 if (align_good
== FAIL
)
13568 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
13569 _("bad list length"));
13570 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13571 inst
.instruction
|= 1 << 5;
13572 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13575 case 2: /* VLD3. */
13576 constraint (inst
.operands
[1].immisalign
,
13577 _("can't use alignment with this instruction"));
13578 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
13579 _("bad list length"));
13580 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13581 inst
.instruction
|= 1 << 5;
13582 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13585 case 3: /* VLD4. */
13587 int align
= inst
.operands
[1].imm
>> 8;
13588 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13589 16, 64, 32, 64, 32, 128, -1);
13590 if (align_good
== FAIL
)
13592 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
13593 _("bad list length"));
13594 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13595 inst
.instruction
|= 1 << 5;
13596 if (et
.size
== 32 && align
== 128)
13597 inst
.instruction
|= 0x3 << 6;
13599 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13606 inst
.instruction
|= do_align
<< 4;
13609 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
13610 apart from bits [11:4]. */
13613 do_neon_ldx_stx (void)
13615 switch (NEON_LANE (inst
.operands
[0].imm
))
13617 case NEON_INTERLEAVE_LANES
:
13618 inst
.instruction
= NEON_ENC_INTERLV (inst
.instruction
);
13619 do_neon_ld_st_interleave ();
13622 case NEON_ALL_LANES
:
13623 inst
.instruction
= NEON_ENC_DUP (inst
.instruction
);
13628 inst
.instruction
= NEON_ENC_LANE (inst
.instruction
);
13629 do_neon_ld_st_lane ();
13632 /* L bit comes from bit mask. */
13633 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13634 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13635 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13637 if (inst
.operands
[1].postind
)
13639 int postreg
= inst
.operands
[1].imm
& 0xf;
13640 constraint (!inst
.operands
[1].immisreg
,
13641 _("post-index must be a register"));
13642 constraint (postreg
== 0xd || postreg
== 0xf,
13643 _("bad register for post-index"));
13644 inst
.instruction
|= postreg
;
13646 else if (inst
.operands
[1].writeback
)
13648 inst
.instruction
|= 0xd;
13651 inst
.instruction
|= 0xf;
13654 inst
.instruction
|= 0xf9000000;
13656 inst
.instruction
|= 0xf4000000;
13660 /* Overall per-instruction processing. */
13662 /* We need to be able to fix up arbitrary expressions in some statements.
13663 This is so that we can handle symbols that are an arbitrary distance from
13664 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
13665 which returns part of an address in a form which will be valid for
13666 a data instruction. We do this by pushing the expression into a symbol
13667 in the expr_section, and creating a fix for that. */
13670 fix_new_arm (fragS
* frag
,
13685 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
13689 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
13694 /* Mark whether the fix is to a THUMB instruction, or an ARM
13696 new_fix
->tc_fix_data
= thumb_mode
;
13699 /* Create a frg for an instruction requiring relaxation. */
13701 output_relax_insn (void)
13707 /* The size of the instruction is unknown, so tie the debug info to the
13708 start of the instruction. */
13709 dwarf2_emit_insn (0);
13711 switch (inst
.reloc
.exp
.X_op
)
13714 sym
= inst
.reloc
.exp
.X_add_symbol
;
13715 offset
= inst
.reloc
.exp
.X_add_number
;
13719 offset
= inst
.reloc
.exp
.X_add_number
;
13722 sym
= make_expr_symbol (&inst
.reloc
.exp
);
13726 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
13727 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
13728 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
13731 /* Write a 32-bit thumb instruction to buf. */
13733 put_thumb32_insn (char * buf
, unsigned long insn
)
13735 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
13736 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
13740 output_inst (const char * str
)
13746 as_bad ("%s -- `%s'", inst
.error
, str
);
13750 output_relax_insn();
13753 if (inst
.size
== 0)
13756 to
= frag_more (inst
.size
);
13758 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
13760 assert (inst
.size
== (2 * THUMB_SIZE
));
13761 put_thumb32_insn (to
, inst
.instruction
);
13763 else if (inst
.size
> INSN_SIZE
)
13765 assert (inst
.size
== (2 * INSN_SIZE
));
13766 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
13767 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
13770 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
13772 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
13773 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
13774 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
13777 dwarf2_emit_insn (inst
.size
);
13780 /* Tag values used in struct asm_opcode's tag field. */
13783 OT_unconditional
, /* Instruction cannot be conditionalized.
13784 The ARM condition field is still 0xE. */
13785 OT_unconditionalF
, /* Instruction cannot be conditionalized
13786 and carries 0xF in its ARM condition field. */
13787 OT_csuffix
, /* Instruction takes a conditional suffix. */
13788 OT_csuffixF
, /* Some forms of the instruction take a conditional
13789 suffix, others place 0xF where the condition field
13791 OT_cinfix3
, /* Instruction takes a conditional infix,
13792 beginning at character index 3. (In
13793 unified mode, it becomes a suffix.) */
13794 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
13795 tsts, cmps, cmns, and teqs. */
13796 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
13797 character index 3, even in unified mode. Used for
13798 legacy instructions where suffix and infix forms
13799 may be ambiguous. */
13800 OT_csuf_or_in3
, /* Instruction takes either a conditional
13801 suffix or an infix at character index 3. */
13802 OT_odd_infix_unc
, /* This is the unconditional variant of an
13803 instruction that takes a conditional infix
13804 at an unusual position. In unified mode,
13805 this variant will accept a suffix. */
13806 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
13807 are the conditional variants of instructions that
13808 take conditional infixes in unusual positions.
13809 The infix appears at character index
13810 (tag - OT_odd_infix_0). These are not accepted
13811 in unified mode. */
13814 /* Subroutine of md_assemble, responsible for looking up the primary
13815 opcode from the mnemonic the user wrote. STR points to the
13816 beginning of the mnemonic.
13818 This is not simply a hash table lookup, because of conditional
13819 variants. Most instructions have conditional variants, which are
13820 expressed with a _conditional affix_ to the mnemonic. If we were
13821 to encode each conditional variant as a literal string in the opcode
13822 table, it would have approximately 20,000 entries.
13824 Most mnemonics take this affix as a suffix, and in unified syntax,
13825 'most' is upgraded to 'all'. However, in the divided syntax, some
13826 instructions take the affix as an infix, notably the s-variants of
13827 the arithmetic instructions. Of those instructions, all but six
13828 have the infix appear after the third character of the mnemonic.
13830 Accordingly, the algorithm for looking up primary opcodes given
13833 1. Look up the identifier in the opcode table.
13834 If we find a match, go to step U.
13836 2. Look up the last two characters of the identifier in the
13837 conditions table. If we find a match, look up the first N-2
13838 characters of the identifier in the opcode table. If we
13839 find a match, go to step CE.
13841 3. Look up the fourth and fifth characters of the identifier in
13842 the conditions table. If we find a match, extract those
13843 characters from the identifier, and look up the remaining
13844 characters in the opcode table. If we find a match, go
13849 U. Examine the tag field of the opcode structure, in case this is
13850 one of the six instructions with its conditional infix in an
13851 unusual place. If it is, the tag tells us where to find the
13852 infix; look it up in the conditions table and set inst.cond
13853 accordingly. Otherwise, this is an unconditional instruction.
13854 Again set inst.cond accordingly. Return the opcode structure.
13856 CE. Examine the tag field to make sure this is an instruction that
13857 should receive a conditional suffix. If it is not, fail.
13858 Otherwise, set inst.cond from the suffix we already looked up,
13859 and return the opcode structure.
13861 CM. Examine the tag field to make sure this is an instruction that
13862 should receive a conditional infix after the third character.
13863 If it is not, fail. Otherwise, undo the edits to the current
13864 line of input and proceed as for case CE. */
13866 static const struct asm_opcode
*
13867 opcode_lookup (char **str
)
13871 const struct asm_opcode
*opcode
;
13872 const struct asm_cond
*cond
;
13874 bfd_boolean neon_supported
;
13876 neon_supported
= ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
);
13878 /* Scan up to the end of the mnemonic, which must end in white space,
13879 '.' (in unified mode, or for Neon instructions), or end of string. */
13880 for (base
= end
= *str
; *end
!= '\0'; end
++)
13881 if (*end
== ' ' || ((unified_syntax
|| neon_supported
) && *end
== '.'))
13887 /* Handle a possible width suffix and/or Neon type suffix. */
13892 /* The .w and .n suffixes are only valid if the unified syntax is in
13894 if (unified_syntax
&& end
[1] == 'w')
13896 else if (unified_syntax
&& end
[1] == 'n')
13901 inst
.vectype
.elems
= 0;
13903 *str
= end
+ offset
;
13905 if (end
[offset
] == '.')
13907 /* See if we have a Neon type suffix (possible in either unified or
13908 non-unified ARM syntax mode). */
13909 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
13912 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
13918 /* Look for unaffixed or special-case affixed mnemonic. */
13919 opcode
= hash_find_n (arm_ops_hsh
, base
, end
- base
);
13923 if (opcode
->tag
< OT_odd_infix_0
)
13925 inst
.cond
= COND_ALWAYS
;
13929 if (unified_syntax
)
13930 as_warn (_("conditional infixes are deprecated in unified syntax"));
13931 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
13932 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
13935 inst
.cond
= cond
->value
;
13939 /* Cannot have a conditional suffix on a mnemonic of less than two
13941 if (end
- base
< 3)
13944 /* Look for suffixed mnemonic. */
13946 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
13947 opcode
= hash_find_n (arm_ops_hsh
, base
, affix
- base
);
13948 if (opcode
&& cond
)
13951 switch (opcode
->tag
)
13953 case OT_cinfix3_legacy
:
13954 /* Ignore conditional suffixes matched on infix only mnemonics. */
13958 case OT_cinfix3_deprecated
:
13959 case OT_odd_infix_unc
:
13960 if (!unified_syntax
)
13962 /* else fall through */
13966 case OT_csuf_or_in3
:
13967 inst
.cond
= cond
->value
;
13970 case OT_unconditional
:
13971 case OT_unconditionalF
:
13974 inst
.cond
= cond
->value
;
13978 /* delayed diagnostic */
13979 inst
.error
= BAD_COND
;
13980 inst
.cond
= COND_ALWAYS
;
13989 /* Cannot have a usual-position infix on a mnemonic of less than
13990 six characters (five would be a suffix). */
13991 if (end
- base
< 6)
13994 /* Look for infixed mnemonic in the usual position. */
13996 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14000 memcpy (save
, affix
, 2);
14001 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
14002 opcode
= hash_find_n (arm_ops_hsh
, base
, (end
- base
) - 2);
14003 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
14004 memcpy (affix
, save
, 2);
14007 && (opcode
->tag
== OT_cinfix3
14008 || opcode
->tag
== OT_cinfix3_deprecated
14009 || opcode
->tag
== OT_csuf_or_in3
14010 || opcode
->tag
== OT_cinfix3_legacy
))
14014 && (opcode
->tag
== OT_cinfix3
14015 || opcode
->tag
== OT_cinfix3_deprecated
))
14016 as_warn (_("conditional infixes are deprecated in unified syntax"));
14018 inst
.cond
= cond
->value
;
14026 md_assemble (char *str
)
14029 const struct asm_opcode
* opcode
;
14031 /* Align the previous label if needed. */
14032 if (last_label_seen
!= NULL
)
14034 symbol_set_frag (last_label_seen
, frag_now
);
14035 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
14036 S_SET_SEGMENT (last_label_seen
, now_seg
);
14039 memset (&inst
, '\0', sizeof (inst
));
14040 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
14042 opcode
= opcode_lookup (&p
);
14045 /* It wasn't an instruction, but it might be a register alias of
14046 the form alias .req reg, or a Neon .dn/.qn directive. */
14047 if (!create_register_alias (str
, p
)
14048 && !create_neon_reg_alias (str
, p
))
14049 as_bad (_("bad instruction `%s'"), str
);
14054 if (opcode
->tag
== OT_cinfix3_deprecated
)
14055 as_warn (_("s suffix on comparison instruction is deprecated"));
14057 /* The value which unconditional instructions should have in place of the
14058 condition field. */
14059 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
14063 arm_feature_set variant
;
14065 variant
= cpu_variant
;
14066 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
14067 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
14068 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
14069 /* Check that this instruction is supported for this CPU. */
14070 if (!opcode
->tvariant
14071 || (thumb_mode
== 1
14072 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
14074 as_bad (_("selected processor does not support `%s'"), str
);
14077 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
14078 && opcode
->tencode
!= do_t_branch
)
14080 as_bad (_("Thumb does not support conditional execution"));
14084 /* Check conditional suffixes. */
14085 if (current_it_mask
)
14088 cond
= current_cc
^ ((current_it_mask
>> 4) & 1) ^ 1;
14089 current_it_mask
<<= 1;
14090 current_it_mask
&= 0x1f;
14091 /* The BKPT instruction is unconditional even in an IT block. */
14093 && cond
!= inst
.cond
&& opcode
->tencode
!= do_t_bkpt
)
14095 as_bad (_("incorrect condition in IT block"));
14099 else if (inst
.cond
!= COND_ALWAYS
&& opcode
->tencode
!= do_t_branch
)
14101 as_bad (_("thumb conditional instrunction not in IT block"));
14105 mapping_state (MAP_THUMB
);
14106 inst
.instruction
= opcode
->tvalue
;
14108 if (!parse_operands (p
, opcode
->operands
))
14109 opcode
->tencode ();
14111 /* Clear current_it_mask at the end of an IT block. */
14112 if (current_it_mask
== 0x10)
14113 current_it_mask
= 0;
14115 if (!(inst
.error
|| inst
.relax
))
14117 assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
14118 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
14119 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
14121 as_bad (_("cannot honor width suffix -- `%s'"), str
);
14125 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
14126 *opcode
->tvariant
);
14127 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
14128 set those bits when Thumb-2 32-bit instructions are seen. ie.
14129 anything other than bl/blx.
14130 This is overly pessimistic for relaxable instructions. */
14131 if ((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
14133 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
14136 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
14138 /* Check that this instruction is supported for this CPU. */
14139 if (!opcode
->avariant
||
14140 !ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
))
14142 as_bad (_("selected processor does not support `%s'"), str
);
14147 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
14151 mapping_state (MAP_ARM
);
14152 inst
.instruction
= opcode
->avalue
;
14153 if (opcode
->tag
== OT_unconditionalF
)
14154 inst
.instruction
|= 0xF << 28;
14156 inst
.instruction
|= inst
.cond
<< 28;
14157 inst
.size
= INSN_SIZE
;
14158 if (!parse_operands (p
, opcode
->operands
))
14159 opcode
->aencode ();
14160 /* Arm mode bx is marked as both v4T and v5 because it's still required
14161 on a hypothetical non-thumb v5 core. */
14162 if (ARM_CPU_HAS_FEATURE (*opcode
->avariant
, arm_ext_v4t
)
14163 || ARM_CPU_HAS_FEATURE (*opcode
->avariant
, arm_ext_v5
))
14164 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
14166 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
14167 *opcode
->avariant
);
14171 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
14178 /* Various frobbings of labels and their addresses. */
14181 arm_start_line_hook (void)
14183 last_label_seen
= NULL
;
14187 arm_frob_label (symbolS
* sym
)
14189 last_label_seen
= sym
;
14191 ARM_SET_THUMB (sym
, thumb_mode
);
14193 #if defined OBJ_COFF || defined OBJ_ELF
14194 ARM_SET_INTERWORK (sym
, support_interwork
);
14197 /* Note - do not allow local symbols (.Lxxx) to be labeled
14198 as Thumb functions. This is because these labels, whilst
14199 they exist inside Thumb code, are not the entry points for
14200 possible ARM->Thumb calls. Also, these labels can be used
14201 as part of a computed goto or switch statement. eg gcc
14202 can generate code that looks like this:
14204 ldr r2, [pc, .Laaa]
14214 The first instruction loads the address of the jump table.
14215 The second instruction converts a table index into a byte offset.
14216 The third instruction gets the jump address out of the table.
14217 The fourth instruction performs the jump.
14219 If the address stored at .Laaa is that of a symbol which has the
14220 Thumb_Func bit set, then the linker will arrange for this address
14221 to have the bottom bit set, which in turn would mean that the
14222 address computation performed by the third instruction would end
14223 up with the bottom bit set. Since the ARM is capable of unaligned
14224 word loads, the instruction would then load the incorrect address
14225 out of the jump table, and chaos would ensue. */
14226 if (label_is_thumb_function_name
14227 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
14228 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
14230 /* When the address of a Thumb function is taken the bottom
14231 bit of that address should be set. This will allow
14232 interworking between Arm and Thumb functions to work
14235 THUMB_SET_FUNC (sym
, 1);
14237 label_is_thumb_function_name
= FALSE
;
14240 dwarf2_emit_label (sym
);
14244 arm_data_in_code (void)
14246 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
14248 *input_line_pointer
= '/';
14249 input_line_pointer
+= 5;
14250 *input_line_pointer
= 0;
14258 arm_canonicalize_symbol_name (char * name
)
14262 if (thumb_mode
&& (len
= strlen (name
)) > 5
14263 && streq (name
+ len
- 5, "/data"))
14264 *(name
+ len
- 5) = 0;
14269 /* Table of all register names defined by default. The user can
14270 define additional names with .req. Note that all register names
14271 should appear in both upper and lowercase variants. Some registers
14272 also have mixed-case names. */
14274 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
14275 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
14276 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
14277 #define REGSET(p,t) \
14278 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
14279 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
14280 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
14281 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
14282 #define REGSETH(p,t) \
14283 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
14284 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
14285 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
14286 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
14287 #define REGSET2(p,t) \
14288 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
14289 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
14290 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
14291 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
14293 static const struct reg_entry reg_names
[] =
14295 /* ARM integer registers. */
14296 REGSET(r
, RN
), REGSET(R
, RN
),
14298 /* ATPCS synonyms. */
14299 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
14300 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
14301 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
14303 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
14304 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
14305 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
14307 /* Well-known aliases. */
14308 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
14309 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
14311 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
14312 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
14314 /* Coprocessor numbers. */
14315 REGSET(p
, CP
), REGSET(P
, CP
),
14317 /* Coprocessor register numbers. The "cr" variants are for backward
14319 REGSET(c
, CN
), REGSET(C
, CN
),
14320 REGSET(cr
, CN
), REGSET(CR
, CN
),
14322 /* FPA registers. */
14323 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
14324 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
14326 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
14327 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
14329 /* VFP SP registers. */
14330 REGSET(s
,VFS
), REGSET(S
,VFS
),
14331 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
14333 /* VFP DP Registers. */
14334 REGSET(d
,VFD
), REGSET(D
,VFD
),
14335 /* Extra Neon DP registers. */
14336 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
14338 /* Neon QP registers. */
14339 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
14341 /* VFP control registers. */
14342 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
14343 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
14345 /* Maverick DSP coprocessor registers. */
14346 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
14347 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
14349 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
14350 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
14351 REGDEF(dspsc
,0,DSPSC
),
14353 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
14354 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
14355 REGDEF(DSPSC
,0,DSPSC
),
14357 /* iWMMXt data registers - p0, c0-15. */
14358 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
14360 /* iWMMXt control registers - p1, c0-3. */
14361 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
14362 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
14363 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
14364 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
14366 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
14367 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
14368 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
14369 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
14370 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
14372 /* XScale accumulator registers. */
14373 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
14379 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
14380 within psr_required_here. */
14381 static const struct asm_psr psrs
[] =
14383 /* Backward compatibility notation. Note that "all" is no longer
14384 truly all possible PSR bits. */
14385 {"all", PSR_c
| PSR_f
},
14389 /* Individual flags. */
14394 /* Combinations of flags. */
14395 {"fs", PSR_f
| PSR_s
},
14396 {"fx", PSR_f
| PSR_x
},
14397 {"fc", PSR_f
| PSR_c
},
14398 {"sf", PSR_s
| PSR_f
},
14399 {"sx", PSR_s
| PSR_x
},
14400 {"sc", PSR_s
| PSR_c
},
14401 {"xf", PSR_x
| PSR_f
},
14402 {"xs", PSR_x
| PSR_s
},
14403 {"xc", PSR_x
| PSR_c
},
14404 {"cf", PSR_c
| PSR_f
},
14405 {"cs", PSR_c
| PSR_s
},
14406 {"cx", PSR_c
| PSR_x
},
14407 {"fsx", PSR_f
| PSR_s
| PSR_x
},
14408 {"fsc", PSR_f
| PSR_s
| PSR_c
},
14409 {"fxs", PSR_f
| PSR_x
| PSR_s
},
14410 {"fxc", PSR_f
| PSR_x
| PSR_c
},
14411 {"fcs", PSR_f
| PSR_c
| PSR_s
},
14412 {"fcx", PSR_f
| PSR_c
| PSR_x
},
14413 {"sfx", PSR_s
| PSR_f
| PSR_x
},
14414 {"sfc", PSR_s
| PSR_f
| PSR_c
},
14415 {"sxf", PSR_s
| PSR_x
| PSR_f
},
14416 {"sxc", PSR_s
| PSR_x
| PSR_c
},
14417 {"scf", PSR_s
| PSR_c
| PSR_f
},
14418 {"scx", PSR_s
| PSR_c
| PSR_x
},
14419 {"xfs", PSR_x
| PSR_f
| PSR_s
},
14420 {"xfc", PSR_x
| PSR_f
| PSR_c
},
14421 {"xsf", PSR_x
| PSR_s
| PSR_f
},
14422 {"xsc", PSR_x
| PSR_s
| PSR_c
},
14423 {"xcf", PSR_x
| PSR_c
| PSR_f
},
14424 {"xcs", PSR_x
| PSR_c
| PSR_s
},
14425 {"cfs", PSR_c
| PSR_f
| PSR_s
},
14426 {"cfx", PSR_c
| PSR_f
| PSR_x
},
14427 {"csf", PSR_c
| PSR_s
| PSR_f
},
14428 {"csx", PSR_c
| PSR_s
| PSR_x
},
14429 {"cxf", PSR_c
| PSR_x
| PSR_f
},
14430 {"cxs", PSR_c
| PSR_x
| PSR_s
},
14431 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
14432 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
14433 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
14434 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
14435 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
14436 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
14437 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
14438 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
14439 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
14440 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
14441 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
14442 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
14443 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
14444 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
14445 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
14446 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
14447 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
14448 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
14449 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
14450 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
14451 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
14452 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
14453 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
14454 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
14457 /* Table of V7M psr names. */
14458 static const struct asm_psr v7m_psrs
[] =
14471 {"basepri_max", 18},
14476 /* Table of all shift-in-operand names. */
14477 static const struct asm_shift_name shift_names
[] =
14479 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
14480 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
14481 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
14482 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
14483 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
14484 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
14487 /* Table of all explicit relocation names. */
14489 static struct reloc_entry reloc_names
[] =
14491 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
14492 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
14493 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
14494 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
14495 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
14496 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
14497 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
14498 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
14499 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
14500 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
14501 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
14505 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
14506 static const struct asm_cond conds
[] =
14510 {"cs", 0x2}, {"hs", 0x2},
14511 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
14525 static struct asm_barrier_opt barrier_opt_names
[] =
14533 /* Table of ARM-format instructions. */
14535 /* Macros for gluing together operand strings. N.B. In all cases
14536 other than OPS0, the trailing OP_stop comes from default
14537 zero-initialization of the unspecified elements of the array. */
14538 #define OPS0() { OP_stop, }
14539 #define OPS1(a) { OP_##a, }
14540 #define OPS2(a,b) { OP_##a,OP_##b, }
14541 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
14542 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
14543 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
14544 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
14546 /* These macros abstract out the exact format of the mnemonic table and
14547 save some repeated characters. */
14549 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
14550 #define TxCE(mnem, op, top, nops, ops, ae, te) \
14551 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
14552 THUMB_VARIANT, do_##ae, do_##te }
14554 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
14555 a T_MNEM_xyz enumerator. */
14556 #define TCE(mnem, aop, top, nops, ops, ae, te) \
14557 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
14558 #define tCE(mnem, aop, top, nops, ops, ae, te) \
14559 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14561 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
14562 infix after the third character. */
14563 #define TxC3(mnem, op, top, nops, ops, ae, te) \
14564 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
14565 THUMB_VARIANT, do_##ae, do_##te }
14566 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
14567 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
14568 THUMB_VARIANT, do_##ae, do_##te }
14569 #define TC3(mnem, aop, top, nops, ops, ae, te) \
14570 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
14571 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
14572 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
14573 #define tC3(mnem, aop, top, nops, ops, ae, te) \
14574 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14575 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
14576 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14578 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
14579 appear in the condition table. */
14580 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
14581 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14582 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
14584 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
14585 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
14586 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
14587 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
14588 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
14589 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
14590 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
14591 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
14592 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
14593 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
14594 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
14595 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
14596 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
14597 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
14598 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
14599 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
14600 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
14601 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
14602 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
14603 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
14605 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
14606 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
14607 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
14608 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
14610 /* Mnemonic that cannot be conditionalized. The ARM condition-code
14611 field is still 0xE. Many of the Thumb variants can be executed
14612 conditionally, so this is checked separately. */
14613 #define TUE(mnem, op, top, nops, ops, ae, te) \
14614 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
14615 THUMB_VARIANT, do_##ae, do_##te }
14617 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
14618 condition code field. */
14619 #define TUF(mnem, op, top, nops, ops, ae, te) \
14620 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
14621 THUMB_VARIANT, do_##ae, do_##te }
14623 /* ARM-only variants of all the above. */
14624 #define CE(mnem, op, nops, ops, ae) \
14625 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14627 #define C3(mnem, op, nops, ops, ae) \
14628 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14630 /* Legacy mnemonics that always have conditional infix after the third
14632 #define CL(mnem, op, nops, ops, ae) \
14633 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14634 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14636 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
14637 #define cCE(mnem, op, nops, ops, ae) \
14638 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14640 /* Legacy coprocessor instructions where conditional infix and conditional
14641 suffix are ambiguous. For consistency this includes all FPA instructions,
14642 not just the potentially ambiguous ones. */
14643 #define cCL(mnem, op, nops, ops, ae) \
14644 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14645 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14647 /* Coprocessor, takes either a suffix or a position-3 infix
14648 (for an FPA corner case). */
14649 #define C3E(mnem, op, nops, ops, ae) \
14650 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
14651 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14653 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
14654 { #m1 #m2 #m3, OPS##nops ops, \
14655 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14656 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14658 #define CM(m1, m2, op, nops, ops, ae) \
14659 xCM_(m1, , m2, op, nops, ops, ae), \
14660 xCM_(m1, eq, m2, op, nops, ops, ae), \
14661 xCM_(m1, ne, m2, op, nops, ops, ae), \
14662 xCM_(m1, cs, m2, op, nops, ops, ae), \
14663 xCM_(m1, hs, m2, op, nops, ops, ae), \
14664 xCM_(m1, cc, m2, op, nops, ops, ae), \
14665 xCM_(m1, ul, m2, op, nops, ops, ae), \
14666 xCM_(m1, lo, m2, op, nops, ops, ae), \
14667 xCM_(m1, mi, m2, op, nops, ops, ae), \
14668 xCM_(m1, pl, m2, op, nops, ops, ae), \
14669 xCM_(m1, vs, m2, op, nops, ops, ae), \
14670 xCM_(m1, vc, m2, op, nops, ops, ae), \
14671 xCM_(m1, hi, m2, op, nops, ops, ae), \
14672 xCM_(m1, ls, m2, op, nops, ops, ae), \
14673 xCM_(m1, ge, m2, op, nops, ops, ae), \
14674 xCM_(m1, lt, m2, op, nops, ops, ae), \
14675 xCM_(m1, gt, m2, op, nops, ops, ae), \
14676 xCM_(m1, le, m2, op, nops, ops, ae), \
14677 xCM_(m1, al, m2, op, nops, ops, ae)
14679 #define UE(mnem, op, nops, ops, ae) \
14680 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14682 #define UF(mnem, op, nops, ops, ae) \
14683 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14685 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
14686 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
14687 use the same encoding function for each. */
14688 #define NUF(mnem, op, nops, ops, enc) \
14689 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
14690 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14692 /* Neon data processing, version which indirects through neon_enc_tab for
14693 the various overloaded versions of opcodes. */
14694 #define nUF(mnem, op, nops, ops, enc) \
14695 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \
14696 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14698 /* Neon insn with conditional suffix for the ARM version, non-overloaded
14700 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
14701 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
14702 THUMB_VARIANT, do_##enc, do_##enc }
14704 #define NCE(mnem, op, nops, ops, enc) \
14705 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14707 #define NCEF(mnem, op, nops, ops, enc) \
14708 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14710 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
14711 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
14712 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \
14713 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14715 #define nCE(mnem, op, nops, ops, enc) \
14716 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14718 #define nCEF(mnem, op, nops, ops, enc) \
14719 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14723 /* Thumb-only, unconditional. */
14724 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
14726 static const struct asm_opcode insns
[] =
14728 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
14729 #define THUMB_VARIANT &arm_ext_v4t
14730 tCE(and, 0000000, and, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14731 tC3(ands
, 0100000, ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14732 tCE(eor
, 0200000, eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14733 tC3(eors
, 0300000, eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14734 tCE(sub
, 0400000, sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14735 tC3(subs
, 0500000, subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14736 tCE(add
, 0800000, add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14737 tC3(adds
, 0900000, adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14738 tCE(adc
, 0a00000
, adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14739 tC3(adcs
, 0b00000, adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14740 tCE(sbc
, 0c00000
, sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14741 tC3(sbcs
, 0d00000
, sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14742 tCE(orr
, 1800000, orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14743 tC3(orrs
, 1900000, orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14744 tCE(bic
, 1c00000
, bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14745 tC3(bics
, 1d00000
, bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14747 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
14748 for setting PSR flag bits. They are obsolete in V6 and do not
14749 have Thumb equivalents. */
14750 tCE(tst
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14751 tC3w(tsts
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14752 CL(tstp
, 110f000
, 2, (RR
, SH
), cmp
),
14753 tCE(cmp
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14754 tC3w(cmps
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14755 CL(cmpp
, 150f000
, 2, (RR
, SH
), cmp
),
14756 tCE(cmn
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14757 tC3w(cmns
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14758 CL(cmnp
, 170f000
, 2, (RR
, SH
), cmp
),
14760 tCE(mov
, 1a00000
, mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14761 tC3(movs
, 1b00000
, movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14762 tCE(mvn
, 1e00000
, mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14763 tC3(mvns
, 1f00000
, mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14765 tCE(ldr
, 4100000, ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14766 tC3(ldrb
, 4500000, ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14767 tCE(str
, 4000000, str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14768 tC3(strb
, 4400000, strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14770 tCE(stm
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14771 tC3(stmia
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14772 tC3(stmea
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14773 tCE(ldm
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14774 tC3(ldmia
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14775 tC3(ldmfd
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14777 TCE(swi
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14778 TCE(svc
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14779 tCE(b
, a000000
, b
, 1, (EXPr
), branch
, t_branch
),
14780 TCE(bl
, b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
14783 tCE(adr
, 28f0000
, adr
, 2, (RR
, EXP
), adr
, t_adr
),
14784 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
14785 tCE(nop
, 1a00000
, nop
, 1, (oI255c
), nop
, t_nop
),
14787 /* Thumb-compatibility pseudo ops. */
14788 tCE(lsl
, 1a00000
, lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14789 tC3(lsls
, 1b00000
, lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14790 tCE(lsr
, 1a00020
, lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14791 tC3(lsrs
, 1b00020
, lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14792 tCE(asr
, 1a00040
, asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14793 tC3(asrs
, 1b00040
, asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14794 tCE(ror
, 1a00060
, ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14795 tC3(rors
, 1b00060
, rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14796 tCE(neg
, 2600000, neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
14797 tC3(negs
, 2700000, negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
14798 tCE(push
, 92d0000
, push
, 1, (REGLST
), push_pop
, t_push_pop
),
14799 tCE(pop
, 8bd0000
, pop
, 1, (REGLST
), push_pop
, t_push_pop
),
14801 #undef THUMB_VARIANT
14802 #define THUMB_VARIANT &arm_ext_v6
14803 TCE(cpy
, 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
14805 /* V1 instructions with no Thumb analogue prior to V6T2. */
14806 #undef THUMB_VARIANT
14807 #define THUMB_VARIANT &arm_ext_v6t2
14808 TCE(rsb
, 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14809 TC3(rsbs
, 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14810 TCE(teq
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14811 TC3w(teqs
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14812 CL(teqp
, 130f000
, 2, (RR
, SH
), cmp
),
14814 TC3(ldrt
, 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14815 TC3(ldrbt
, 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14816 TC3(strt
, 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14817 TC3(strbt
, 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14819 TC3(stmdb
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14820 TC3(stmfd
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14822 TC3(ldmdb
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14823 TC3(ldmea
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14825 /* V1 instructions with no Thumb analogue at all. */
14826 CE(rsc
, 0e00000
, 3, (RR
, oRR
, SH
), arit
),
14827 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
14829 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
14830 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
14831 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
14832 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
14833 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
14834 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
14835 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
14836 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
14839 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
14840 #undef THUMB_VARIANT
14841 #define THUMB_VARIANT &arm_ext_v4t
14842 tCE(mul
, 0000090, mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
14843 tC3(muls
, 0100090, muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
14845 #undef THUMB_VARIANT
14846 #define THUMB_VARIANT &arm_ext_v6t2
14847 TCE(mla
, 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
14848 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
14850 /* Generic coprocessor instructions. */
14851 TCE(cdp
, e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
14852 TCE(ldc
, c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14853 TC3(ldcl
, c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14854 TCE(stc
, c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14855 TC3(stcl
, c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14856 TCE(mcr
, e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14857 TCE(mrc
, e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14860 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
14861 CE(swp
, 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
14862 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
14865 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
14866 TCE(mrs
, 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
14867 TCE(msr
, 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
14870 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
14871 TCE(smull
, 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14872 CM(smull
,s
, 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14873 TCE(umull
, 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14874 CM(umull
,s
, 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14875 TCE(smlal
, 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14876 CM(smlal
,s
, 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14877 TCE(umlal
, 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14878 CM(umlal
,s
, 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14881 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
14882 #undef THUMB_VARIANT
14883 #define THUMB_VARIANT &arm_ext_v4t
14884 tC3(ldrh
, 01000b0
, ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14885 tC3(strh
, 00000b0
, strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14886 tC3(ldrsh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14887 tC3(ldrsb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14888 tCM(ld
,sh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14889 tCM(ld
,sb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14892 #define ARM_VARIANT &arm_ext_v4t_5
14893 /* ARM Architecture 4T. */
14894 /* Note: bx (and blx) are required on V5, even if the processor does
14895 not support Thumb. */
14896 TCE(bx
, 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
14899 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
14900 #undef THUMB_VARIANT
14901 #define THUMB_VARIANT &arm_ext_v5t
14902 /* Note: blx has 2 variants; the .value coded here is for
14903 BLX(2). Only this variant has conditional execution. */
14904 TCE(blx
, 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
14905 TUE(bkpt
, 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
14907 #undef THUMB_VARIANT
14908 #define THUMB_VARIANT &arm_ext_v6t2
14909 TCE(clz
, 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
14910 TUF(ldc2
, c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14911 TUF(ldc2l
, c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14912 TUF(stc2
, c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14913 TUF(stc2l
, c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14914 TUF(cdp2
, e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
14915 TUF(mcr2
, e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14916 TUF(mrc2
, e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14919 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
14920 TCE(smlabb
, 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14921 TCE(smlatb
, 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14922 TCE(smlabt
, 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14923 TCE(smlatt
, 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14925 TCE(smlawb
, 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14926 TCE(smlawt
, 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14928 TCE(smlalbb
, 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14929 TCE(smlaltb
, 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14930 TCE(smlalbt
, 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14931 TCE(smlaltt
, 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14933 TCE(smulbb
, 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14934 TCE(smultb
, 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14935 TCE(smulbt
, 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14936 TCE(smultt
, 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14938 TCE(smulwb
, 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14939 TCE(smulwt
, 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14941 TCE(qadd
, 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14942 TCE(qdadd
, 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14943 TCE(qsub
, 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14944 TCE(qdsub
, 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14947 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
14948 TUF(pld
, 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
14949 TC3(ldrd
, 00000d0
, e9500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
14950 TC3(strd
, 00000f0
, e9400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
14952 TCE(mcrr
, c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14953 TCE(mrrc
, c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14956 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
14957 TCE(bxj
, 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
14960 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
14961 #undef THUMB_VARIANT
14962 #define THUMB_VARIANT &arm_ext_v6
14963 TUF(cpsie
, 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
14964 TUF(cpsid
, 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
14965 tCE(rev
, 6bf0f30
, rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
14966 tCE(rev16
, 6bf0fb0
, rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
14967 tCE(revsh
, 6ff0fb0
, revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
14968 tCE(sxth
, 6bf0070
, sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14969 tCE(uxth
, 6ff0070
, uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14970 tCE(sxtb
, 6af0070
, sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14971 tCE(uxtb
, 6ef0070
, uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14972 TUF(setend
, 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
14974 #undef THUMB_VARIANT
14975 #define THUMB_VARIANT &arm_ext_v6t2
14976 TCE(ldrex
, 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
14977 TUF(mcrr2
, c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14978 TUF(mrrc2
, c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14980 TCE(ssat
, 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
14981 TCE(usat
, 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
14983 /* ARM V6 not included in V7M (eg. integer SIMD). */
14984 #undef THUMB_VARIANT
14985 #define THUMB_VARIANT &arm_ext_v6_notm
14986 TUF(cps
, 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
14987 TCE(pkhbt
, 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
14988 TCE(pkhtb
, 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
14989 TCE(qadd16
, 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14990 TCE(qadd8
, 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14991 TCE(qaddsubx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14992 TCE(qsub16
, 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14993 TCE(qsub8
, 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14994 TCE(qsubaddx
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14995 TCE(sadd16
, 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14996 TCE(sadd8
, 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14997 TCE(saddsubx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14998 TCE(shadd16
, 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14999 TCE(shadd8
, 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15000 TCE(shaddsubx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15001 TCE(shsub16
, 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15002 TCE(shsub8
, 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15003 TCE(shsubaddx
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15004 TCE(ssub16
, 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15005 TCE(ssub8
, 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15006 TCE(ssubaddx
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15007 TCE(uadd16
, 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15008 TCE(uadd8
, 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15009 TCE(uaddsubx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15010 TCE(uhadd16
, 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15011 TCE(uhadd8
, 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15012 TCE(uhaddsubx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15013 TCE(uhsub16
, 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15014 TCE(uhsub8
, 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15015 TCE(uhsubaddx
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15016 TCE(uqadd16
, 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15017 TCE(uqadd8
, 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15018 TCE(uqaddsubx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15019 TCE(uqsub16
, 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15020 TCE(uqsub8
, 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15021 TCE(uqsubaddx
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15022 TCE(usub16
, 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15023 TCE(usub8
, 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15024 TCE(usubaddx
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15025 TUF(rfeia
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
15026 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
15027 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
15028 TUF(rfedb
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
15029 TUF(rfefd
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
15030 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
15031 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
15032 TUF(rfeed
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
15033 TCE(sxtah
, 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15034 TCE(sxtab16
, 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15035 TCE(sxtab
, 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15036 TCE(sxtb16
, 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15037 TCE(uxtah
, 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15038 TCE(uxtab16
, 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15039 TCE(uxtab
, 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15040 TCE(uxtb16
, 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15041 TCE(sel
, 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15042 TCE(smlad
, 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15043 TCE(smladx
, 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15044 TCE(smlald
, 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15045 TCE(smlaldx
, 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15046 TCE(smlsd
, 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15047 TCE(smlsdx
, 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15048 TCE(smlsld
, 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15049 TCE(smlsldx
, 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15050 TCE(smmla
, 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15051 TCE(smmlar
, 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15052 TCE(smmls
, 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15053 TCE(smmlsr
, 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15054 TCE(smmul
, 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15055 TCE(smmulr
, 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15056 TCE(smuad
, 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15057 TCE(smuadx
, 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15058 TCE(smusd
, 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15059 TCE(smusdx
, 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15060 TUF(srsia
, 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
15061 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
15062 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
15063 TUF(srsdb
, 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
15064 TCE(ssat16
, 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
15065 TCE(strex
, 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
15066 TCE(umaal
, 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
15067 TCE(usad8
, 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15068 TCE(usada8
, 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15069 TCE(usat16
, 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
15072 #define ARM_VARIANT &arm_ext_v6k
15073 #undef THUMB_VARIANT
15074 #define THUMB_VARIANT &arm_ext_v6k
15075 tCE(yield
, 320f001
, yield
, 0, (), noargs
, t_hint
),
15076 tCE(wfe
, 320f002
, wfe
, 0, (), noargs
, t_hint
),
15077 tCE(wfi
, 320f003
, wfi
, 0, (), noargs
, t_hint
),
15078 tCE(sev
, 320f004
, sev
, 0, (), noargs
, t_hint
),
15080 #undef THUMB_VARIANT
15081 #define THUMB_VARIANT &arm_ext_v6_notm
15082 TCE(ldrexd
, 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
15083 TCE(strexd
, 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
15085 #undef THUMB_VARIANT
15086 #define THUMB_VARIANT &arm_ext_v6t2
15087 TCE(ldrexb
, 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
15088 TCE(ldrexh
, 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
15089 TCE(strexb
, 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
15090 TCE(strexh
, 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
15091 TUF(clrex
, 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
15094 #define ARM_VARIANT &arm_ext_v6z
15095 TCE(smc
, 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
15098 #define ARM_VARIANT &arm_ext_v6t2
15099 TCE(bfc
, 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
15100 TCE(bfi
, 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
15101 TCE(sbfx
, 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
15102 TCE(ubfx
, 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
15104 TCE(mls
, 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
15105 TCE(movw
, 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
15106 TCE(movt
, 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
15107 TCE(rbit
, 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
15109 TC3(ldrht
, 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15110 TC3(ldrsht
, 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15111 TC3(ldrsbt
, 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15112 TC3(strht
, 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15114 UT(cbnz
, b900
, 2, (RR
, EXP
), t_cbz
),
15115 UT(cbz
, b100
, 2, (RR
, EXP
), t_cbz
),
15116 /* ARM does not really have an IT instruction, so always allow it. */
15118 #define ARM_VARIANT &arm_ext_v1
15119 TUE(it
, 0, bf08
, 1, (COND
), it
, t_it
),
15120 TUE(itt
, 0, bf0c
, 1, (COND
), it
, t_it
),
15121 TUE(ite
, 0, bf04
, 1, (COND
), it
, t_it
),
15122 TUE(ittt
, 0, bf0e
, 1, (COND
), it
, t_it
),
15123 TUE(itet
, 0, bf06
, 1, (COND
), it
, t_it
),
15124 TUE(itte
, 0, bf0a
, 1, (COND
), it
, t_it
),
15125 TUE(itee
, 0, bf02
, 1, (COND
), it
, t_it
),
15126 TUE(itttt
, 0, bf0f
, 1, (COND
), it
, t_it
),
15127 TUE(itett
, 0, bf07
, 1, (COND
), it
, t_it
),
15128 TUE(ittet
, 0, bf0b
, 1, (COND
), it
, t_it
),
15129 TUE(iteet
, 0, bf03
, 1, (COND
), it
, t_it
),
15130 TUE(ittte
, 0, bf0d
, 1, (COND
), it
, t_it
),
15131 TUE(itete
, 0, bf05
, 1, (COND
), it
, t_it
),
15132 TUE(ittee
, 0, bf09
, 1, (COND
), it
, t_it
),
15133 TUE(iteee
, 0, bf01
, 1, (COND
), it
, t_it
),
15135 /* Thumb2 only instructions. */
15137 #define ARM_VARIANT NULL
15139 TCE(addw
, 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
15140 TCE(subw
, 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
15141 TCE(tbb
, 0, e8d0f000
, 1, (TB
), 0, t_tb
),
15142 TCE(tbh
, 0, e8d0f010
, 1, (TB
), 0, t_tb
),
15144 /* Thumb-2 hardware division instructions (R and M profiles only). */
15145 #undef THUMB_VARIANT
15146 #define THUMB_VARIANT &arm_ext_div
15147 TCE(sdiv
, 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
15148 TCE(udiv
, 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
15150 /* ARM V7 instructions. */
15152 #define ARM_VARIANT &arm_ext_v7
15153 #undef THUMB_VARIANT
15154 #define THUMB_VARIANT &arm_ext_v7
15155 TUF(pli
, 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
15156 TCE(dbg
, 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
15157 TUF(dmb
, 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
15158 TUF(dsb
, 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
15159 TUF(isb
, 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
15162 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
15163 cCE(wfs
, e200110
, 1, (RR
), rd
),
15164 cCE(rfs
, e300110
, 1, (RR
), rd
),
15165 cCE(wfc
, e400110
, 1, (RR
), rd
),
15166 cCE(rfc
, e500110
, 1, (RR
), rd
),
15168 cCL(ldfs
, c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15169 cCL(ldfd
, c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15170 cCL(ldfe
, c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15171 cCL(ldfp
, c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15173 cCL(stfs
, c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15174 cCL(stfd
, c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15175 cCL(stfe
, c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15176 cCL(stfp
, c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15178 cCL(mvfs
, e008100
, 2, (RF
, RF_IF
), rd_rm
),
15179 cCL(mvfsp
, e008120
, 2, (RF
, RF_IF
), rd_rm
),
15180 cCL(mvfsm
, e008140
, 2, (RF
, RF_IF
), rd_rm
),
15181 cCL(mvfsz
, e008160
, 2, (RF
, RF_IF
), rd_rm
),
15182 cCL(mvfd
, e008180
, 2, (RF
, RF_IF
), rd_rm
),
15183 cCL(mvfdp
, e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
15184 cCL(mvfdm
, e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
15185 cCL(mvfdz
, e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
15186 cCL(mvfe
, e088100
, 2, (RF
, RF_IF
), rd_rm
),
15187 cCL(mvfep
, e088120
, 2, (RF
, RF_IF
), rd_rm
),
15188 cCL(mvfem
, e088140
, 2, (RF
, RF_IF
), rd_rm
),
15189 cCL(mvfez
, e088160
, 2, (RF
, RF_IF
), rd_rm
),
15191 cCL(mnfs
, e108100
, 2, (RF
, RF_IF
), rd_rm
),
15192 cCL(mnfsp
, e108120
, 2, (RF
, RF_IF
), rd_rm
),
15193 cCL(mnfsm
, e108140
, 2, (RF
, RF_IF
), rd_rm
),
15194 cCL(mnfsz
, e108160
, 2, (RF
, RF_IF
), rd_rm
),
15195 cCL(mnfd
, e108180
, 2, (RF
, RF_IF
), rd_rm
),
15196 cCL(mnfdp
, e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
15197 cCL(mnfdm
, e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
15198 cCL(mnfdz
, e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
15199 cCL(mnfe
, e188100
, 2, (RF
, RF_IF
), rd_rm
),
15200 cCL(mnfep
, e188120
, 2, (RF
, RF_IF
), rd_rm
),
15201 cCL(mnfem
, e188140
, 2, (RF
, RF_IF
), rd_rm
),
15202 cCL(mnfez
, e188160
, 2, (RF
, RF_IF
), rd_rm
),
15204 cCL(abss
, e208100
, 2, (RF
, RF_IF
), rd_rm
),
15205 cCL(abssp
, e208120
, 2, (RF
, RF_IF
), rd_rm
),
15206 cCL(abssm
, e208140
, 2, (RF
, RF_IF
), rd_rm
),
15207 cCL(abssz
, e208160
, 2, (RF
, RF_IF
), rd_rm
),
15208 cCL(absd
, e208180
, 2, (RF
, RF_IF
), rd_rm
),
15209 cCL(absdp
, e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
15210 cCL(absdm
, e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
15211 cCL(absdz
, e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
15212 cCL(abse
, e288100
, 2, (RF
, RF_IF
), rd_rm
),
15213 cCL(absep
, e288120
, 2, (RF
, RF_IF
), rd_rm
),
15214 cCL(absem
, e288140
, 2, (RF
, RF_IF
), rd_rm
),
15215 cCL(absez
, e288160
, 2, (RF
, RF_IF
), rd_rm
),
15217 cCL(rnds
, e308100
, 2, (RF
, RF_IF
), rd_rm
),
15218 cCL(rndsp
, e308120
, 2, (RF
, RF_IF
), rd_rm
),
15219 cCL(rndsm
, e308140
, 2, (RF
, RF_IF
), rd_rm
),
15220 cCL(rndsz
, e308160
, 2, (RF
, RF_IF
), rd_rm
),
15221 cCL(rndd
, e308180
, 2, (RF
, RF_IF
), rd_rm
),
15222 cCL(rnddp
, e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
15223 cCL(rnddm
, e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
15224 cCL(rnddz
, e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
15225 cCL(rnde
, e388100
, 2, (RF
, RF_IF
), rd_rm
),
15226 cCL(rndep
, e388120
, 2, (RF
, RF_IF
), rd_rm
),
15227 cCL(rndem
, e388140
, 2, (RF
, RF_IF
), rd_rm
),
15228 cCL(rndez
, e388160
, 2, (RF
, RF_IF
), rd_rm
),
15230 cCL(sqts
, e408100
, 2, (RF
, RF_IF
), rd_rm
),
15231 cCL(sqtsp
, e408120
, 2, (RF
, RF_IF
), rd_rm
),
15232 cCL(sqtsm
, e408140
, 2, (RF
, RF_IF
), rd_rm
),
15233 cCL(sqtsz
, e408160
, 2, (RF
, RF_IF
), rd_rm
),
15234 cCL(sqtd
, e408180
, 2, (RF
, RF_IF
), rd_rm
),
15235 cCL(sqtdp
, e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
15236 cCL(sqtdm
, e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
15237 cCL(sqtdz
, e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
15238 cCL(sqte
, e488100
, 2, (RF
, RF_IF
), rd_rm
),
15239 cCL(sqtep
, e488120
, 2, (RF
, RF_IF
), rd_rm
),
15240 cCL(sqtem
, e488140
, 2, (RF
, RF_IF
), rd_rm
),
15241 cCL(sqtez
, e488160
, 2, (RF
, RF_IF
), rd_rm
),
15243 cCL(logs
, e508100
, 2, (RF
, RF_IF
), rd_rm
),
15244 cCL(logsp
, e508120
, 2, (RF
, RF_IF
), rd_rm
),
15245 cCL(logsm
, e508140
, 2, (RF
, RF_IF
), rd_rm
),
15246 cCL(logsz
, e508160
, 2, (RF
, RF_IF
), rd_rm
),
15247 cCL(logd
, e508180
, 2, (RF
, RF_IF
), rd_rm
),
15248 cCL(logdp
, e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
15249 cCL(logdm
, e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
15250 cCL(logdz
, e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
15251 cCL(loge
, e588100
, 2, (RF
, RF_IF
), rd_rm
),
15252 cCL(logep
, e588120
, 2, (RF
, RF_IF
), rd_rm
),
15253 cCL(logem
, e588140
, 2, (RF
, RF_IF
), rd_rm
),
15254 cCL(logez
, e588160
, 2, (RF
, RF_IF
), rd_rm
),
15256 cCL(lgns
, e608100
, 2, (RF
, RF_IF
), rd_rm
),
15257 cCL(lgnsp
, e608120
, 2, (RF
, RF_IF
), rd_rm
),
15258 cCL(lgnsm
, e608140
, 2, (RF
, RF_IF
), rd_rm
),
15259 cCL(lgnsz
, e608160
, 2, (RF
, RF_IF
), rd_rm
),
15260 cCL(lgnd
, e608180
, 2, (RF
, RF_IF
), rd_rm
),
15261 cCL(lgndp
, e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
15262 cCL(lgndm
, e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
15263 cCL(lgndz
, e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
15264 cCL(lgne
, e688100
, 2, (RF
, RF_IF
), rd_rm
),
15265 cCL(lgnep
, e688120
, 2, (RF
, RF_IF
), rd_rm
),
15266 cCL(lgnem
, e688140
, 2, (RF
, RF_IF
), rd_rm
),
15267 cCL(lgnez
, e688160
, 2, (RF
, RF_IF
), rd_rm
),
15269 cCL(exps
, e708100
, 2, (RF
, RF_IF
), rd_rm
),
15270 cCL(expsp
, e708120
, 2, (RF
, RF_IF
), rd_rm
),
15271 cCL(expsm
, e708140
, 2, (RF
, RF_IF
), rd_rm
),
15272 cCL(expsz
, e708160
, 2, (RF
, RF_IF
), rd_rm
),
15273 cCL(expd
, e708180
, 2, (RF
, RF_IF
), rd_rm
),
15274 cCL(expdp
, e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
15275 cCL(expdm
, e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
15276 cCL(expdz
, e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
15277 cCL(expe
, e788100
, 2, (RF
, RF_IF
), rd_rm
),
15278 cCL(expep
, e788120
, 2, (RF
, RF_IF
), rd_rm
),
15279 cCL(expem
, e788140
, 2, (RF
, RF_IF
), rd_rm
),
15280 cCL(expdz
, e788160
, 2, (RF
, RF_IF
), rd_rm
),
15282 cCL(sins
, e808100
, 2, (RF
, RF_IF
), rd_rm
),
15283 cCL(sinsp
, e808120
, 2, (RF
, RF_IF
), rd_rm
),
15284 cCL(sinsm
, e808140
, 2, (RF
, RF_IF
), rd_rm
),
15285 cCL(sinsz
, e808160
, 2, (RF
, RF_IF
), rd_rm
),
15286 cCL(sind
, e808180
, 2, (RF
, RF_IF
), rd_rm
),
15287 cCL(sindp
, e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
15288 cCL(sindm
, e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
15289 cCL(sindz
, e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
15290 cCL(sine
, e888100
, 2, (RF
, RF_IF
), rd_rm
),
15291 cCL(sinep
, e888120
, 2, (RF
, RF_IF
), rd_rm
),
15292 cCL(sinem
, e888140
, 2, (RF
, RF_IF
), rd_rm
),
15293 cCL(sinez
, e888160
, 2, (RF
, RF_IF
), rd_rm
),
15295 cCL(coss
, e908100
, 2, (RF
, RF_IF
), rd_rm
),
15296 cCL(cossp
, e908120
, 2, (RF
, RF_IF
), rd_rm
),
15297 cCL(cossm
, e908140
, 2, (RF
, RF_IF
), rd_rm
),
15298 cCL(cossz
, e908160
, 2, (RF
, RF_IF
), rd_rm
),
15299 cCL(cosd
, e908180
, 2, (RF
, RF_IF
), rd_rm
),
15300 cCL(cosdp
, e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
15301 cCL(cosdm
, e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
15302 cCL(cosdz
, e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
15303 cCL(cose
, e988100
, 2, (RF
, RF_IF
), rd_rm
),
15304 cCL(cosep
, e988120
, 2, (RF
, RF_IF
), rd_rm
),
15305 cCL(cosem
, e988140
, 2, (RF
, RF_IF
), rd_rm
),
15306 cCL(cosez
, e988160
, 2, (RF
, RF_IF
), rd_rm
),
15308 cCL(tans
, ea08100
, 2, (RF
, RF_IF
), rd_rm
),
15309 cCL(tansp
, ea08120
, 2, (RF
, RF_IF
), rd_rm
),
15310 cCL(tansm
, ea08140
, 2, (RF
, RF_IF
), rd_rm
),
15311 cCL(tansz
, ea08160
, 2, (RF
, RF_IF
), rd_rm
),
15312 cCL(tand
, ea08180
, 2, (RF
, RF_IF
), rd_rm
),
15313 cCL(tandp
, ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
15314 cCL(tandm
, ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
15315 cCL(tandz
, ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
15316 cCL(tane
, ea88100
, 2, (RF
, RF_IF
), rd_rm
),
15317 cCL(tanep
, ea88120
, 2, (RF
, RF_IF
), rd_rm
),
15318 cCL(tanem
, ea88140
, 2, (RF
, RF_IF
), rd_rm
),
15319 cCL(tanez
, ea88160
, 2, (RF
, RF_IF
), rd_rm
),
15321 cCL(asns
, eb08100
, 2, (RF
, RF_IF
), rd_rm
),
15322 cCL(asnsp
, eb08120
, 2, (RF
, RF_IF
), rd_rm
),
15323 cCL(asnsm
, eb08140
, 2, (RF
, RF_IF
), rd_rm
),
15324 cCL(asnsz
, eb08160
, 2, (RF
, RF_IF
), rd_rm
),
15325 cCL(asnd
, eb08180
, 2, (RF
, RF_IF
), rd_rm
),
15326 cCL(asndp
, eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
15327 cCL(asndm
, eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
15328 cCL(asndz
, eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
15329 cCL(asne
, eb88100
, 2, (RF
, RF_IF
), rd_rm
),
15330 cCL(asnep
, eb88120
, 2, (RF
, RF_IF
), rd_rm
),
15331 cCL(asnem
, eb88140
, 2, (RF
, RF_IF
), rd_rm
),
15332 cCL(asnez
, eb88160
, 2, (RF
, RF_IF
), rd_rm
),
15334 cCL(acss
, ec08100
, 2, (RF
, RF_IF
), rd_rm
),
15335 cCL(acssp
, ec08120
, 2, (RF
, RF_IF
), rd_rm
),
15336 cCL(acssm
, ec08140
, 2, (RF
, RF_IF
), rd_rm
),
15337 cCL(acssz
, ec08160
, 2, (RF
, RF_IF
), rd_rm
),
15338 cCL(acsd
, ec08180
, 2, (RF
, RF_IF
), rd_rm
),
15339 cCL(acsdp
, ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
15340 cCL(acsdm
, ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
15341 cCL(acsdz
, ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
15342 cCL(acse
, ec88100
, 2, (RF
, RF_IF
), rd_rm
),
15343 cCL(acsep
, ec88120
, 2, (RF
, RF_IF
), rd_rm
),
15344 cCL(acsem
, ec88140
, 2, (RF
, RF_IF
), rd_rm
),
15345 cCL(acsez
, ec88160
, 2, (RF
, RF_IF
), rd_rm
),
15347 cCL(atns
, ed08100
, 2, (RF
, RF_IF
), rd_rm
),
15348 cCL(atnsp
, ed08120
, 2, (RF
, RF_IF
), rd_rm
),
15349 cCL(atnsm
, ed08140
, 2, (RF
, RF_IF
), rd_rm
),
15350 cCL(atnsz
, ed08160
, 2, (RF
, RF_IF
), rd_rm
),
15351 cCL(atnd
, ed08180
, 2, (RF
, RF_IF
), rd_rm
),
15352 cCL(atndp
, ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
15353 cCL(atndm
, ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
15354 cCL(atndz
, ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
15355 cCL(atne
, ed88100
, 2, (RF
, RF_IF
), rd_rm
),
15356 cCL(atnep
, ed88120
, 2, (RF
, RF_IF
), rd_rm
),
15357 cCL(atnem
, ed88140
, 2, (RF
, RF_IF
), rd_rm
),
15358 cCL(atnez
, ed88160
, 2, (RF
, RF_IF
), rd_rm
),
15360 cCL(urds
, ee08100
, 2, (RF
, RF_IF
), rd_rm
),
15361 cCL(urdsp
, ee08120
, 2, (RF
, RF_IF
), rd_rm
),
15362 cCL(urdsm
, ee08140
, 2, (RF
, RF_IF
), rd_rm
),
15363 cCL(urdsz
, ee08160
, 2, (RF
, RF_IF
), rd_rm
),
15364 cCL(urdd
, ee08180
, 2, (RF
, RF_IF
), rd_rm
),
15365 cCL(urddp
, ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
15366 cCL(urddm
, ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
15367 cCL(urddz
, ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
15368 cCL(urde
, ee88100
, 2, (RF
, RF_IF
), rd_rm
),
15369 cCL(urdep
, ee88120
, 2, (RF
, RF_IF
), rd_rm
),
15370 cCL(urdem
, ee88140
, 2, (RF
, RF_IF
), rd_rm
),
15371 cCL(urdez
, ee88160
, 2, (RF
, RF_IF
), rd_rm
),
15373 cCL(nrms
, ef08100
, 2, (RF
, RF_IF
), rd_rm
),
15374 cCL(nrmsp
, ef08120
, 2, (RF
, RF_IF
), rd_rm
),
15375 cCL(nrmsm
, ef08140
, 2, (RF
, RF_IF
), rd_rm
),
15376 cCL(nrmsz
, ef08160
, 2, (RF
, RF_IF
), rd_rm
),
15377 cCL(nrmd
, ef08180
, 2, (RF
, RF_IF
), rd_rm
),
15378 cCL(nrmdp
, ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
15379 cCL(nrmdm
, ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
15380 cCL(nrmdz
, ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
15381 cCL(nrme
, ef88100
, 2, (RF
, RF_IF
), rd_rm
),
15382 cCL(nrmep
, ef88120
, 2, (RF
, RF_IF
), rd_rm
),
15383 cCL(nrmem
, ef88140
, 2, (RF
, RF_IF
), rd_rm
),
15384 cCL(nrmez
, ef88160
, 2, (RF
, RF_IF
), rd_rm
),
15386 cCL(adfs
, e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15387 cCL(adfsp
, e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15388 cCL(adfsm
, e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15389 cCL(adfsz
, e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15390 cCL(adfd
, e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15391 cCL(adfdp
, e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15392 cCL(adfdm
, e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15393 cCL(adfdz
, e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15394 cCL(adfe
, e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15395 cCL(adfep
, e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15396 cCL(adfem
, e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15397 cCL(adfez
, e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15399 cCL(sufs
, e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15400 cCL(sufsp
, e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15401 cCL(sufsm
, e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15402 cCL(sufsz
, e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15403 cCL(sufd
, e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15404 cCL(sufdp
, e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15405 cCL(sufdm
, e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15406 cCL(sufdz
, e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15407 cCL(sufe
, e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15408 cCL(sufep
, e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15409 cCL(sufem
, e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15410 cCL(sufez
, e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15412 cCL(rsfs
, e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15413 cCL(rsfsp
, e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15414 cCL(rsfsm
, e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15415 cCL(rsfsz
, e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15416 cCL(rsfd
, e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15417 cCL(rsfdp
, e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15418 cCL(rsfdm
, e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15419 cCL(rsfdz
, e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15420 cCL(rsfe
, e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15421 cCL(rsfep
, e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15422 cCL(rsfem
, e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15423 cCL(rsfez
, e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15425 cCL(mufs
, e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15426 cCL(mufsp
, e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15427 cCL(mufsm
, e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15428 cCL(mufsz
, e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15429 cCL(mufd
, e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15430 cCL(mufdp
, e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15431 cCL(mufdm
, e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15432 cCL(mufdz
, e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15433 cCL(mufe
, e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15434 cCL(mufep
, e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15435 cCL(mufem
, e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15436 cCL(mufez
, e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15438 cCL(dvfs
, e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15439 cCL(dvfsp
, e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15440 cCL(dvfsm
, e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15441 cCL(dvfsz
, e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15442 cCL(dvfd
, e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15443 cCL(dvfdp
, e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15444 cCL(dvfdm
, e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15445 cCL(dvfdz
, e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15446 cCL(dvfe
, e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15447 cCL(dvfep
, e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15448 cCL(dvfem
, e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15449 cCL(dvfez
, e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15451 cCL(rdfs
, e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15452 cCL(rdfsp
, e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15453 cCL(rdfsm
, e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15454 cCL(rdfsz
, e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15455 cCL(rdfd
, e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15456 cCL(rdfdp
, e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15457 cCL(rdfdm
, e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15458 cCL(rdfdz
, e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15459 cCL(rdfe
, e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15460 cCL(rdfep
, e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15461 cCL(rdfem
, e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15462 cCL(rdfez
, e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15464 cCL(pows
, e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15465 cCL(powsp
, e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15466 cCL(powsm
, e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15467 cCL(powsz
, e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15468 cCL(powd
, e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15469 cCL(powdp
, e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15470 cCL(powdm
, e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15471 cCL(powdz
, e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15472 cCL(powe
, e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15473 cCL(powep
, e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15474 cCL(powem
, e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15475 cCL(powez
, e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15477 cCL(rpws
, e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15478 cCL(rpwsp
, e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15479 cCL(rpwsm
, e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15480 cCL(rpwsz
, e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15481 cCL(rpwd
, e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15482 cCL(rpwdp
, e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15483 cCL(rpwdm
, e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15484 cCL(rpwdz
, e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15485 cCL(rpwe
, e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15486 cCL(rpwep
, e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15487 cCL(rpwem
, e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15488 cCL(rpwez
, e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15490 cCL(rmfs
, e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15491 cCL(rmfsp
, e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15492 cCL(rmfsm
, e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15493 cCL(rmfsz
, e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15494 cCL(rmfd
, e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15495 cCL(rmfdp
, e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15496 cCL(rmfdm
, e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15497 cCL(rmfdz
, e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15498 cCL(rmfe
, e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15499 cCL(rmfep
, e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15500 cCL(rmfem
, e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15501 cCL(rmfez
, e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15503 cCL(fmls
, e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15504 cCL(fmlsp
, e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15505 cCL(fmlsm
, e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15506 cCL(fmlsz
, e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15507 cCL(fmld
, e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15508 cCL(fmldp
, e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15509 cCL(fmldm
, e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15510 cCL(fmldz
, e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15511 cCL(fmle
, e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15512 cCL(fmlep
, e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15513 cCL(fmlem
, e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15514 cCL(fmlez
, e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15516 cCL(fdvs
, ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15517 cCL(fdvsp
, ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15518 cCL(fdvsm
, ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15519 cCL(fdvsz
, ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15520 cCL(fdvd
, ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15521 cCL(fdvdp
, ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15522 cCL(fdvdm
, ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15523 cCL(fdvdz
, ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15524 cCL(fdve
, ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15525 cCL(fdvep
, ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15526 cCL(fdvem
, ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15527 cCL(fdvez
, ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15529 cCL(frds
, eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15530 cCL(frdsp
, eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15531 cCL(frdsm
, eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15532 cCL(frdsz
, eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15533 cCL(frdd
, eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15534 cCL(frddp
, eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15535 cCL(frddm
, eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15536 cCL(frddz
, eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15537 cCL(frde
, eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15538 cCL(frdep
, eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15539 cCL(frdem
, eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15540 cCL(frdez
, eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15542 cCL(pols
, ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15543 cCL(polsp
, ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15544 cCL(polsm
, ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15545 cCL(polsz
, ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15546 cCL(pold
, ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15547 cCL(poldp
, ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15548 cCL(poldm
, ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15549 cCL(poldz
, ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15550 cCL(pole
, ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15551 cCL(polep
, ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15552 cCL(polem
, ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15553 cCL(polez
, ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15555 cCE(cmf
, e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15556 C3E(cmfe
, ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15557 cCE(cnf
, eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15558 C3E(cnfe
, ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15560 cCL(flts
, e000110
, 2, (RF
, RR
), rn_rd
),
15561 cCL(fltsp
, e000130
, 2, (RF
, RR
), rn_rd
),
15562 cCL(fltsm
, e000150
, 2, (RF
, RR
), rn_rd
),
15563 cCL(fltsz
, e000170
, 2, (RF
, RR
), rn_rd
),
15564 cCL(fltd
, e000190
, 2, (RF
, RR
), rn_rd
),
15565 cCL(fltdp
, e0001b0
, 2, (RF
, RR
), rn_rd
),
15566 cCL(fltdm
, e0001d0
, 2, (RF
, RR
), rn_rd
),
15567 cCL(fltdz
, e0001f0
, 2, (RF
, RR
), rn_rd
),
15568 cCL(flte
, e080110
, 2, (RF
, RR
), rn_rd
),
15569 cCL(fltep
, e080130
, 2, (RF
, RR
), rn_rd
),
15570 cCL(fltem
, e080150
, 2, (RF
, RR
), rn_rd
),
15571 cCL(fltez
, e080170
, 2, (RF
, RR
), rn_rd
),
15573 /* The implementation of the FIX instruction is broken on some
15574 assemblers, in that it accepts a precision specifier as well as a
15575 rounding specifier, despite the fact that this is meaningless.
15576 To be more compatible, we accept it as well, though of course it
15577 does not set any bits. */
15578 cCE(fix
, e100110
, 2, (RR
, RF
), rd_rm
),
15579 cCL(fixp
, e100130
, 2, (RR
, RF
), rd_rm
),
15580 cCL(fixm
, e100150
, 2, (RR
, RF
), rd_rm
),
15581 cCL(fixz
, e100170
, 2, (RR
, RF
), rd_rm
),
15582 cCL(fixsp
, e100130
, 2, (RR
, RF
), rd_rm
),
15583 cCL(fixsm
, e100150
, 2, (RR
, RF
), rd_rm
),
15584 cCL(fixsz
, e100170
, 2, (RR
, RF
), rd_rm
),
15585 cCL(fixdp
, e100130
, 2, (RR
, RF
), rd_rm
),
15586 cCL(fixdm
, e100150
, 2, (RR
, RF
), rd_rm
),
15587 cCL(fixdz
, e100170
, 2, (RR
, RF
), rd_rm
),
15588 cCL(fixep
, e100130
, 2, (RR
, RF
), rd_rm
),
15589 cCL(fixem
, e100150
, 2, (RR
, RF
), rd_rm
),
15590 cCL(fixez
, e100170
, 2, (RR
, RF
), rd_rm
),
15592 /* Instructions that were new with the real FPA, call them V2. */
15594 #define ARM_VARIANT &fpu_fpa_ext_v2
15595 cCE(lfm
, c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15596 cCL(lfmfd
, c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15597 cCL(lfmea
, d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15598 cCE(sfm
, c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15599 cCL(sfmfd
, d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15600 cCL(sfmea
, c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15603 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
15604 /* Moves and type conversions. */
15605 cCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15606 cCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
15607 cCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
15608 cCE(fmstat
, ef1fa10
, 0, (), noargs
),
15609 cCE(fsitos
, eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15610 cCE(fuitos
, eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15611 cCE(ftosis
, ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15612 cCE(ftosizs
, ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15613 cCE(ftouis
, ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15614 cCE(ftouizs
, ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15615 cCE(fmrx
, ef00a10
, 2, (RR
, RVC
), rd_rn
),
15616 cCE(fmxr
, ee00a10
, 2, (RVC
, RR
), rn_rd
),
15618 /* Memory operations. */
15619 cCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15620 cCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15621 cCE(fldmias
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15622 cCE(fldmfds
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15623 cCE(fldmdbs
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15624 cCE(fldmeas
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15625 cCE(fldmiax
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15626 cCE(fldmfdx
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15627 cCE(fldmdbx
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15628 cCE(fldmeax
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15629 cCE(fstmias
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15630 cCE(fstmeas
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15631 cCE(fstmdbs
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15632 cCE(fstmfds
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15633 cCE(fstmiax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15634 cCE(fstmeax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15635 cCE(fstmdbx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15636 cCE(fstmfdx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15638 /* Monadic operations. */
15639 cCE(fabss
, eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15640 cCE(fnegs
, eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15641 cCE(fsqrts
, eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15643 /* Dyadic operations. */
15644 cCE(fadds
, e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15645 cCE(fsubs
, e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15646 cCE(fmuls
, e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15647 cCE(fdivs
, e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15648 cCE(fmacs
, e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15649 cCE(fmscs
, e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15650 cCE(fnmuls
, e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15651 cCE(fnmacs
, e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15652 cCE(fnmscs
, e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15655 cCE(fcmps
, eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15656 cCE(fcmpzs
, eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
15657 cCE(fcmpes
, eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15658 cCE(fcmpezs
, eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
15661 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
15662 /* Moves and type conversions. */
15663 cCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15664 cCE(fcvtds
, eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15665 cCE(fcvtsd
, eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15666 cCE(fmdhr
, e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15667 cCE(fmdlr
, e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15668 cCE(fmrdh
, e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15669 cCE(fmrdl
, e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15670 cCE(fsitod
, eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15671 cCE(fuitod
, eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15672 cCE(ftosid
, ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15673 cCE(ftosizd
, ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15674 cCE(ftouid
, ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15675 cCE(ftouizd
, ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15677 /* Memory operations. */
15678 cCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15679 cCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15680 cCE(fldmiad
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15681 cCE(fldmfdd
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15682 cCE(fldmdbd
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15683 cCE(fldmead
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15684 cCE(fstmiad
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15685 cCE(fstmead
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15686 cCE(fstmdbd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15687 cCE(fstmfdd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15689 /* Monadic operations. */
15690 cCE(fabsd
, eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15691 cCE(fnegd
, eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15692 cCE(fsqrtd
, eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15694 /* Dyadic operations. */
15695 cCE(faddd
, e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15696 cCE(fsubd
, e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15697 cCE(fmuld
, e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15698 cCE(fdivd
, e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15699 cCE(fmacd
, e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15700 cCE(fmscd
, e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15701 cCE(fnmuld
, e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15702 cCE(fnmacd
, e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15703 cCE(fnmscd
, e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15706 cCE(fcmpd
, eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15707 cCE(fcmpzd
, eb50b40
, 1, (RVD
), vfp_dp_rd
),
15708 cCE(fcmped
, eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15709 cCE(fcmpezd
, eb50bc0
, 1, (RVD
), vfp_dp_rd
),
15712 #define ARM_VARIANT &fpu_vfp_ext_v2
15713 cCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
15714 cCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
15715 cCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
15716 cCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
15718 /* Instructions which may belong to either the Neon or VFP instruction sets.
15719 Individual encoder functions perform additional architecture checks. */
15721 #define ARM_VARIANT &fpu_vfp_ext_v1xd
15722 #undef THUMB_VARIANT
15723 #define THUMB_VARIANT &fpu_vfp_ext_v1xd
15724 /* These mnemonics are unique to VFP. */
15725 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
15726 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
15727 nCE(vnmul
, vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15728 nCE(vnmla
, vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15729 nCE(vnmls
, vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15730 nCE(vcmp
, vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15731 nCE(vcmpe
, vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15732 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
15733 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
15734 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
15736 /* Mnemonics shared by Neon and VFP. */
15737 nCEF(vmul
, vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
15738 nCEF(vmla
, vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15739 nCEF(vmls
, vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15741 nCEF(vadd
, vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15742 nCEF(vsub
, vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15744 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15745 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15747 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15748 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15749 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15750 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15751 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15752 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15753 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15754 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15756 nCEF(vcvt
, vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
15758 /* NOTE: All VMOV encoding is special-cased! */
15759 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
15760 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
15762 #undef THUMB_VARIANT
15763 #define THUMB_VARIANT &fpu_neon_ext_v1
15765 #define ARM_VARIANT &fpu_neon_ext_v1
15766 /* Data processing with three registers of the same length. */
15767 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
15768 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
15769 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
15770 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15771 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15772 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15773 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15774 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15775 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15776 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
15777 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15778 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15779 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15780 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15781 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
15782 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
15783 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
15784 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
15785 /* If not immediate, fall back to neon_dyadic_i64_su.
15786 shl_imm should accept I8 I16 I32 I64,
15787 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
15788 nUF(vshl
, vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
15789 nUF(vshlq
, vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
15790 nUF(vqshl
, vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
15791 nUF(vqshlq
, vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
15792 /* Logic ops, types optional & ignored. */
15793 nUF(vand
, vand
, 2, (RNDQ
, NILO
), neon_logic
),
15794 nUF(vandq
, vand
, 2, (RNQ
, NILO
), neon_logic
),
15795 nUF(vbic
, vbic
, 2, (RNDQ
, NILO
), neon_logic
),
15796 nUF(vbicq
, vbic
, 2, (RNQ
, NILO
), neon_logic
),
15797 nUF(vorr
, vorr
, 2, (RNDQ
, NILO
), neon_logic
),
15798 nUF(vorrq
, vorr
, 2, (RNQ
, NILO
), neon_logic
),
15799 nUF(vorn
, vorn
, 2, (RNDQ
, NILO
), neon_logic
),
15800 nUF(vornq
, vorn
, 2, (RNQ
, NILO
), neon_logic
),
15801 nUF(veor
, veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
15802 nUF(veorq
, veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
15803 /* Bitfield ops, untyped. */
15804 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15805 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15806 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15807 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15808 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15809 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15810 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
15811 nUF(vabd
, vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15812 nUF(vabdq
, vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15813 nUF(vmax
, vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15814 nUF(vmaxq
, vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15815 nUF(vmin
, vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15816 nUF(vminq
, vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15817 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
15818 back to neon_dyadic_if_su. */
15819 nUF(vcge
, vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
15820 nUF(vcgeq
, vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
15821 nUF(vcgt
, vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
15822 nUF(vcgtq
, vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
15823 nUF(vclt
, vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
15824 nUF(vcltq
, vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
15825 nUF(vcle
, vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
15826 nUF(vcleq
, vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
15827 /* Comparison. Type I8 I16 I32 F32. */
15828 nUF(vceq
, vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
15829 nUF(vceqq
, vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
15830 /* As above, D registers only. */
15831 nUF(vpmax
, vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
15832 nUF(vpmin
, vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
15833 /* Int and float variants, signedness unimportant. */
15834 nUF(vmlaq
, vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
15835 nUF(vmlsq
, vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
15836 nUF(vpadd
, vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
15837 /* Add/sub take types I8 I16 I32 I64 F32. */
15838 nUF(vaddq
, vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
15839 nUF(vsubq
, vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
15840 /* vtst takes sizes 8, 16, 32. */
15841 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
15842 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
15843 /* VMUL takes I8 I16 I32 F32 P8. */
15844 nUF(vmulq
, vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
15845 /* VQD{R}MULH takes S16 S32. */
15846 nUF(vqdmulh
, vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
15847 nUF(vqdmulhq
, vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
15848 nUF(vqrdmulh
, vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
15849 nUF(vqrdmulhq
, vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
15850 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
15851 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
15852 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
15853 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
15854 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
15855 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
15856 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
15857 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
15858 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
15859 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
15860 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
15861 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
15863 /* Two address, int/float. Types S8 S16 S32 F32. */
15864 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
15865 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
15867 /* Data processing with two registers and a shift amount. */
15868 /* Right shifts, and variants with rounding.
15869 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
15870 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
15871 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
15872 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
15873 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
15874 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
15875 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
15876 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
15877 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
15878 /* Shift and insert. Sizes accepted 8 16 32 64. */
15879 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
15880 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
15881 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
15882 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
15883 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
15884 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
15885 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
15886 /* Right shift immediate, saturating & narrowing, with rounding variants.
15887 Types accepted S16 S32 S64 U16 U32 U64. */
15888 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
15889 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
15890 /* As above, unsigned. Types accepted S16 S32 S64. */
15891 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
15892 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
15893 /* Right shift narrowing. Types accepted I16 I32 I64. */
15894 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
15895 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
15896 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
15897 nUF(vshll
, vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
15898 /* CVT with optional immediate for fixed-point variant. */
15899 nUF(vcvtq
, vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
15901 nUF(vmvn
, vmvn
, 2, (RNDQ
, RNDQ_IMVNb
), neon_mvn
),
15902 nUF(vmvnq
, vmvn
, 2, (RNQ
, RNDQ_IMVNb
), neon_mvn
),
15904 /* Data processing, three registers of different lengths. */
15905 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
15906 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
15907 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
15908 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
15909 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
15910 /* If not scalar, fall back to neon_dyadic_long.
15911 Vector types as above, scalar types S16 S32 U16 U32. */
15912 nUF(vmlal
, vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
15913 nUF(vmlsl
, vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
15914 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
15915 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
15916 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
15917 /* Dyadic, narrowing insns. Types I16 I32 I64. */
15918 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15919 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15920 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15921 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15922 /* Saturating doubling multiplies. Types S16 S32. */
15923 nUF(vqdmlal
, vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
15924 nUF(vqdmlsl
, vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
15925 nUF(vqdmull
, vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
15926 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
15927 S16 S32 U16 U32. */
15928 nUF(vmull
, vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
15930 /* Extract. Size 8. */
15931 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
15932 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
15934 /* Two registers, miscellaneous. */
15935 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
15936 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
15937 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
15938 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
15939 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
15940 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
15941 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
15942 /* Vector replicate. Sizes 8 16 32. */
15943 nCE(vdup
, vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
15944 nCE(vdupq
, vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
15945 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
15946 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
15947 /* VMOVN. Types I16 I32 I64. */
15948 nUF(vmovn
, vmovn
, 2, (RND
, RNQ
), neon_movn
),
15949 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
15950 nUF(vqmovn
, vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
15951 /* VQMOVUN. Types S16 S32 S64. */
15952 nUF(vqmovun
, vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
15953 /* VZIP / VUZP. Sizes 8 16 32. */
15954 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
15955 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
15956 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
15957 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
15958 /* VQABS / VQNEG. Types S8 S16 S32. */
15959 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
15960 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
15961 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
15962 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
15963 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
15964 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
15965 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
15966 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
15967 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
15968 /* Reciprocal estimates. Types U32 F32. */
15969 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
15970 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
15971 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
15972 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
15973 /* VCLS. Types S8 S16 S32. */
15974 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
15975 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
15976 /* VCLZ. Types I8 I16 I32. */
15977 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
15978 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
15979 /* VCNT. Size 8. */
15980 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
15981 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
15982 /* Two address, untyped. */
15983 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
15984 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
15985 /* VTRN. Sizes 8 16 32. */
15986 nUF(vtrn
, vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
15987 nUF(vtrnq
, vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
15989 /* Table lookup. Size 8. */
15990 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
15991 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
15993 #undef THUMB_VARIANT
15994 #define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
15996 #define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
15997 /* Neon element/structure load/store. */
15998 nUF(vld1
, vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15999 nUF(vst1
, vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16000 nUF(vld2
, vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16001 nUF(vst2
, vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16002 nUF(vld3
, vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16003 nUF(vst3
, vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16004 nUF(vld4
, vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16005 nUF(vst4
, vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16007 #undef THUMB_VARIANT
16008 #define THUMB_VARIANT &fpu_vfp_ext_v3
16010 #define ARM_VARIANT &fpu_vfp_ext_v3
16011 cCE(fconsts
, eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
16012 cCE(fconstd
, eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
16013 cCE(fshtos
, eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16014 cCE(fshtod
, eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16015 cCE(fsltos
, eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16016 cCE(fsltod
, eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16017 cCE(fuhtos
, ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16018 cCE(fuhtod
, ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16019 cCE(fultos
, ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16020 cCE(fultod
, ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16021 cCE(ftoshs
, ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16022 cCE(ftoshd
, ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16023 cCE(ftosls
, ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16024 cCE(ftosld
, ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16025 cCE(ftouhs
, ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16026 cCE(ftouhd
, ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16027 cCE(ftouls
, ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16028 cCE(ftould
, ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16030 #undef THUMB_VARIANT
16032 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
16033 cCE(mia
, e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16034 cCE(miaph
, e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16035 cCE(miabb
, e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16036 cCE(miabt
, e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16037 cCE(miatb
, e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16038 cCE(miatt
, e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16039 cCE(mar
, c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
16040 cCE(mra
, c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
16043 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
16044 cCE(tandcb
, e13f130
, 1, (RR
), iwmmxt_tandorc
),
16045 cCE(tandch
, e53f130
, 1, (RR
), iwmmxt_tandorc
),
16046 cCE(tandcw
, e93f130
, 1, (RR
), iwmmxt_tandorc
),
16047 cCE(tbcstb
, e400010
, 2, (RIWR
, RR
), rn_rd
),
16048 cCE(tbcsth
, e400050
, 2, (RIWR
, RR
), rn_rd
),
16049 cCE(tbcstw
, e400090
, 2, (RIWR
, RR
), rn_rd
),
16050 cCE(textrcb
, e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
16051 cCE(textrch
, e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
16052 cCE(textrcw
, e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
16053 cCE(textrmub
, e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16054 cCE(textrmuh
, e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16055 cCE(textrmuw
, e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16056 cCE(textrmsb
, e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16057 cCE(textrmsh
, e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16058 cCE(textrmsw
, e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16059 cCE(tinsrb
, e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16060 cCE(tinsrh
, e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16061 cCE(tinsrw
, e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16062 cCE(tmcr
, e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
16063 cCE(tmcrr
, c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
16064 cCE(tmia
, e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16065 cCE(tmiaph
, e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16066 cCE(tmiabb
, e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16067 cCE(tmiabt
, e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16068 cCE(tmiatb
, e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16069 cCE(tmiatt
, e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16070 cCE(tmovmskb
, e100030
, 2, (RR
, RIWR
), rd_rn
),
16071 cCE(tmovmskh
, e500030
, 2, (RR
, RIWR
), rd_rn
),
16072 cCE(tmovmskw
, e900030
, 2, (RR
, RIWR
), rd_rn
),
16073 cCE(tmrc
, e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
16074 cCE(tmrrc
, c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
16075 cCE(torcb
, e13f150
, 1, (RR
), iwmmxt_tandorc
),
16076 cCE(torch
, e53f150
, 1, (RR
), iwmmxt_tandorc
),
16077 cCE(torcw
, e93f150
, 1, (RR
), iwmmxt_tandorc
),
16078 cCE(waccb
, e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16079 cCE(wacch
, e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16080 cCE(waccw
, e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16081 cCE(waddbss
, e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16082 cCE(waddb
, e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16083 cCE(waddbus
, e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16084 cCE(waddhss
, e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16085 cCE(waddh
, e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16086 cCE(waddhus
, e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16087 cCE(waddwss
, eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16088 cCE(waddw
, e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16089 cCE(waddwus
, e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16090 cCE(waligni
, e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
16091 cCE(walignr0
, e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16092 cCE(walignr1
, e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16093 cCE(walignr2
, ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16094 cCE(walignr3
, eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16095 cCE(wand
, e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16096 cCE(wandn
, e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16097 cCE(wavg2b
, e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16098 cCE(wavg2br
, e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16099 cCE(wavg2h
, ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16100 cCE(wavg2hr
, ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16101 cCE(wcmpeqb
, e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16102 cCE(wcmpeqh
, e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16103 cCE(wcmpeqw
, e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16104 cCE(wcmpgtub
, e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16105 cCE(wcmpgtuh
, e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16106 cCE(wcmpgtuw
, e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16107 cCE(wcmpgtsb
, e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16108 cCE(wcmpgtsh
, e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16109 cCE(wcmpgtsw
, eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16110 cCE(wldrb
, c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16111 cCE(wldrh
, c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16112 cCE(wldrw
, c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
16113 cCE(wldrd
, c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
16114 cCE(wmacs
, e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16115 cCE(wmacsz
, e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16116 cCE(wmacu
, e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16117 cCE(wmacuz
, e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16118 cCE(wmadds
, ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16119 cCE(wmaddu
, e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16120 cCE(wmaxsb
, e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16121 cCE(wmaxsh
, e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16122 cCE(wmaxsw
, ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16123 cCE(wmaxub
, e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16124 cCE(wmaxuh
, e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16125 cCE(wmaxuw
, e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16126 cCE(wminsb
, e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16127 cCE(wminsh
, e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16128 cCE(wminsw
, eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16129 cCE(wminub
, e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16130 cCE(wminuh
, e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16131 cCE(wminuw
, e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16132 cCE(wmov
, e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
16133 cCE(wmulsm
, e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16134 cCE(wmulsl
, e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16135 cCE(wmulum
, e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16136 cCE(wmulul
, e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16137 cCE(wor
, e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16138 cCE(wpackhss
, e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16139 cCE(wpackhus
, e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16140 cCE(wpackwss
, eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16141 cCE(wpackwus
, e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16142 cCE(wpackdss
, ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16143 cCE(wpackdus
, ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16144 cCE(wrorh
, e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16145 cCE(wrorhg
, e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16146 cCE(wrorw
, eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16147 cCE(wrorwg
, eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16148 cCE(wrord
, ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16149 cCE(wrordg
, ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16150 cCE(wsadb
, e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16151 cCE(wsadbz
, e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16152 cCE(wsadh
, e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16153 cCE(wsadhz
, e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16154 cCE(wshufh
, e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
16155 cCE(wsllh
, e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16156 cCE(wsllhg
, e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16157 cCE(wsllw
, e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16158 cCE(wsllwg
, e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16159 cCE(wslld
, ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16160 cCE(wslldg
, ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16161 cCE(wsrah
, e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16162 cCE(wsrahg
, e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16163 cCE(wsraw
, e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16164 cCE(wsrawg
, e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16165 cCE(wsrad
, ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16166 cCE(wsradg
, ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16167 cCE(wsrlh
, e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16168 cCE(wsrlhg
, e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16169 cCE(wsrlw
, ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16170 cCE(wsrlwg
, ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16171 cCE(wsrld
, ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16172 cCE(wsrldg
, ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16173 cCE(wstrb
, c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16174 cCE(wstrh
, c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16175 cCE(wstrw
, c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
16176 cCE(wstrd
, c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
16177 cCE(wsubbss
, e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16178 cCE(wsubb
, e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16179 cCE(wsubbus
, e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16180 cCE(wsubhss
, e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16181 cCE(wsubh
, e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16182 cCE(wsubhus
, e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16183 cCE(wsubwss
, eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16184 cCE(wsubw
, e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16185 cCE(wsubwus
, e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16186 cCE(wunpckehub
,e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16187 cCE(wunpckehuh
,e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16188 cCE(wunpckehuw
,e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16189 cCE(wunpckehsb
,e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16190 cCE(wunpckehsh
,e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16191 cCE(wunpckehsw
,ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16192 cCE(wunpckihb
, e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16193 cCE(wunpckihh
, e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16194 cCE(wunpckihw
, e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16195 cCE(wunpckelub
,e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16196 cCE(wunpckeluh
,e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16197 cCE(wunpckeluw
,e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16198 cCE(wunpckelsb
,e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16199 cCE(wunpckelsh
,e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16200 cCE(wunpckelsw
,ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16201 cCE(wunpckilb
, e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16202 cCE(wunpckilh
, e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16203 cCE(wunpckilw
, e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16204 cCE(wxor
, e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16205 cCE(wzero
, e300000
, 1, (RIWR
), iwmmxt_wzero
),
16208 #define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
16209 cCE(torvscb
, e13f190
, 1, (RR
), iwmmxt_tandorc
),
16210 cCE(torvsch
, e53f190
, 1, (RR
), iwmmxt_tandorc
),
16211 cCE(torvscw
, e93f190
, 1, (RR
), iwmmxt_tandorc
),
16212 cCE(wabsb
, e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16213 cCE(wabsh
, e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16214 cCE(wabsw
, ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16215 cCE(wabsdiffb
, e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16216 cCE(wabsdiffh
, e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16217 cCE(wabsdiffw
, e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16218 cCE(waddbhusl
, e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16219 cCE(waddbhusm
, e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16220 cCE(waddhc
, e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16221 cCE(waddwc
, ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16222 cCE(waddsubhx
, ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16223 cCE(wavg4
, e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16224 cCE(wavg4r
, e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16225 cCE(wmaddsn
, ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16226 cCE(wmaddsx
, eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16227 cCE(wmaddun
, ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16228 cCE(wmaddux
, e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16229 cCE(wmerge
, e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
16230 cCE(wmiabb
, e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16231 cCE(wmiabt
, e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16232 cCE(wmiatb
, e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16233 cCE(wmiatt
, e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16234 cCE(wmiabbn
, e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16235 cCE(wmiabtn
, e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16236 cCE(wmiatbn
, e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16237 cCE(wmiattn
, e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16238 cCE(wmiawbb
, e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16239 cCE(wmiawbt
, e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16240 cCE(wmiawtb
, ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16241 cCE(wmiawtt
, eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16242 cCE(wmiawbbn
, ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16243 cCE(wmiawbtn
, ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16244 cCE(wmiawtbn
, ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16245 cCE(wmiawttn
, ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16246 cCE(wmulsmr
, ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16247 cCE(wmulumr
, ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16248 cCE(wmulwumr
, ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16249 cCE(wmulwsmr
, ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16250 cCE(wmulwum
, ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16251 cCE(wmulwsm
, ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16252 cCE(wmulwl
, eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16253 cCE(wqmiabb
, e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16254 cCE(wqmiabt
, e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16255 cCE(wqmiatb
, ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16256 cCE(wqmiatt
, eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16257 cCE(wqmiabbn
, ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16258 cCE(wqmiabtn
, ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16259 cCE(wqmiatbn
, ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16260 cCE(wqmiattn
, ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16261 cCE(wqmulm
, e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16262 cCE(wqmulmr
, e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16263 cCE(wqmulwm
, ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16264 cCE(wqmulwmr
, ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16265 cCE(wsubaddhx
, ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16268 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
16269 cCE(cfldrs
, c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
16270 cCE(cfldrd
, c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
16271 cCE(cfldr32
, c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
16272 cCE(cfldr64
, c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
16273 cCE(cfstrs
, c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
16274 cCE(cfstrd
, c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
16275 cCE(cfstr32
, c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
16276 cCE(cfstr64
, c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
16277 cCE(cfmvsr
, e000450
, 2, (RMF
, RR
), rn_rd
),
16278 cCE(cfmvrs
, e100450
, 2, (RR
, RMF
), rd_rn
),
16279 cCE(cfmvdlr
, e000410
, 2, (RMD
, RR
), rn_rd
),
16280 cCE(cfmvrdl
, e100410
, 2, (RR
, RMD
), rd_rn
),
16281 cCE(cfmvdhr
, e000430
, 2, (RMD
, RR
), rn_rd
),
16282 cCE(cfmvrdh
, e100430
, 2, (RR
, RMD
), rd_rn
),
16283 cCE(cfmv64lr
, e000510
, 2, (RMDX
, RR
), rn_rd
),
16284 cCE(cfmvr64l
, e100510
, 2, (RR
, RMDX
), rd_rn
),
16285 cCE(cfmv64hr
, e000530
, 2, (RMDX
, RR
), rn_rd
),
16286 cCE(cfmvr64h
, e100530
, 2, (RR
, RMDX
), rd_rn
),
16287 cCE(cfmval32
, e200440
, 2, (RMAX
, RMFX
), rd_rn
),
16288 cCE(cfmv32al
, e100440
, 2, (RMFX
, RMAX
), rd_rn
),
16289 cCE(cfmvam32
, e200460
, 2, (RMAX
, RMFX
), rd_rn
),
16290 cCE(cfmv32am
, e100460
, 2, (RMFX
, RMAX
), rd_rn
),
16291 cCE(cfmvah32
, e200480
, 2, (RMAX
, RMFX
), rd_rn
),
16292 cCE(cfmv32ah
, e100480
, 2, (RMFX
, RMAX
), rd_rn
),
16293 cCE(cfmva32
, e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
16294 cCE(cfmv32a
, e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
16295 cCE(cfmva64
, e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
16296 cCE(cfmv64a
, e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
16297 cCE(cfmvsc32
, e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
16298 cCE(cfmv32sc
, e1004e0
, 2, (RMDX
, RMDS
), rd
),
16299 cCE(cfcpys
, e000400
, 2, (RMF
, RMF
), rd_rn
),
16300 cCE(cfcpyd
, e000420
, 2, (RMD
, RMD
), rd_rn
),
16301 cCE(cfcvtsd
, e000460
, 2, (RMD
, RMF
), rd_rn
),
16302 cCE(cfcvtds
, e000440
, 2, (RMF
, RMD
), rd_rn
),
16303 cCE(cfcvt32s
, e000480
, 2, (RMF
, RMFX
), rd_rn
),
16304 cCE(cfcvt32d
, e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
16305 cCE(cfcvt64s
, e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
16306 cCE(cfcvt64d
, e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
16307 cCE(cfcvts32
, e100580
, 2, (RMFX
, RMF
), rd_rn
),
16308 cCE(cfcvtd32
, e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
16309 cCE(cftruncs32
,e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
16310 cCE(cftruncd32
,e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
16311 cCE(cfrshl32
, e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
16312 cCE(cfrshl64
, e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
16313 cCE(cfsh32
, e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
16314 cCE(cfsh64
, e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
16315 cCE(cfcmps
, e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
16316 cCE(cfcmpd
, e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
16317 cCE(cfcmp32
, e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
16318 cCE(cfcmp64
, e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
16319 cCE(cfabss
, e300400
, 2, (RMF
, RMF
), rd_rn
),
16320 cCE(cfabsd
, e300420
, 2, (RMD
, RMD
), rd_rn
),
16321 cCE(cfnegs
, e300440
, 2, (RMF
, RMF
), rd_rn
),
16322 cCE(cfnegd
, e300460
, 2, (RMD
, RMD
), rd_rn
),
16323 cCE(cfadds
, e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16324 cCE(cfaddd
, e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16325 cCE(cfsubs
, e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16326 cCE(cfsubd
, e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16327 cCE(cfmuls
, e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16328 cCE(cfmuld
, e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16329 cCE(cfabs32
, e300500
, 2, (RMFX
, RMFX
), rd_rn
),
16330 cCE(cfabs64
, e300520
, 2, (RMDX
, RMDX
), rd_rn
),
16331 cCE(cfneg32
, e300540
, 2, (RMFX
, RMFX
), rd_rn
),
16332 cCE(cfneg64
, e300560
, 2, (RMDX
, RMDX
), rd_rn
),
16333 cCE(cfadd32
, e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16334 cCE(cfadd64
, e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16335 cCE(cfsub32
, e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16336 cCE(cfsub64
, e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16337 cCE(cfmul32
, e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16338 cCE(cfmul64
, e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16339 cCE(cfmac32
, e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16340 cCE(cfmsc32
, e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16341 cCE(cfmadd32
, e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
16342 cCE(cfmsub32
, e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
16343 cCE(cfmadda32
, e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
16344 cCE(cfmsuba32
, e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
16347 #undef THUMB_VARIANT
16374 /* MD interface: bits in the object file. */
16376 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
16377 for use in the a.out file, and stores them in the array pointed to by buf.
16378 This knows about the endian-ness of the target machine and does
16379 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
16380 2 (short) and 4 (long) Floating numbers are put out as a series of
16381 LITTLENUMS (shorts, here at least). */
16384 md_number_to_chars (char * buf
, valueT val
, int n
)
16386 if (target_big_endian
)
16387 number_to_chars_bigendian (buf
, val
, n
);
16389 number_to_chars_littleendian (buf
, val
, n
);
16393 md_chars_to_number (char * buf
, int n
)
16396 unsigned char * where
= (unsigned char *) buf
;
16398 if (target_big_endian
)
16403 result
|= (*where
++ & 255);
16411 result
|= (where
[n
] & 255);
16418 /* MD interface: Sections. */
16420 /* Estimate the size of a frag before relaxing. Assume everything fits in
16424 md_estimate_size_before_relax (fragS
* fragp
,
16425 segT segtype ATTRIBUTE_UNUSED
)
16431 /* Convert a machine dependent frag. */
16434 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
16436 unsigned long insn
;
16437 unsigned long old_op
;
16445 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16447 old_op
= bfd_get_16(abfd
, buf
);
16448 if (fragp
->fr_symbol
) {
16449 exp
.X_op
= O_symbol
;
16450 exp
.X_add_symbol
= fragp
->fr_symbol
;
16452 exp
.X_op
= O_constant
;
16454 exp
.X_add_number
= fragp
->fr_offset
;
16455 opcode
= fragp
->fr_subtype
;
16458 case T_MNEM_ldr_pc
:
16459 case T_MNEM_ldr_pc2
:
16460 case T_MNEM_ldr_sp
:
16461 case T_MNEM_str_sp
:
16468 if (fragp
->fr_var
== 4)
16470 insn
= THUMB_OP32(opcode
);
16471 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
16473 insn
|= (old_op
& 0x700) << 4;
16477 insn
|= (old_op
& 7) << 12;
16478 insn
|= (old_op
& 0x38) << 13;
16480 insn
|= 0x00000c00;
16481 put_thumb32_insn (buf
, insn
);
16482 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
16486 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
16488 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
16491 if (fragp
->fr_var
== 4)
16493 insn
= THUMB_OP32 (opcode
);
16494 insn
|= (old_op
& 0xf0) << 4;
16495 put_thumb32_insn (buf
, insn
);
16496 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
16500 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16501 exp
.X_add_number
-= 4;
16509 if (fragp
->fr_var
== 4)
16511 int r0off
= (opcode
== T_MNEM_mov
16512 || opcode
== T_MNEM_movs
) ? 0 : 8;
16513 insn
= THUMB_OP32 (opcode
);
16514 insn
= (insn
& 0xe1ffffff) | 0x10000000;
16515 insn
|= (old_op
& 0x700) << r0off
;
16516 put_thumb32_insn (buf
, insn
);
16517 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16521 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
16526 if (fragp
->fr_var
== 4)
16528 insn
= THUMB_OP32(opcode
);
16529 put_thumb32_insn (buf
, insn
);
16530 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
16533 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
16537 if (fragp
->fr_var
== 4)
16539 insn
= THUMB_OP32(opcode
);
16540 insn
|= (old_op
& 0xf00) << 14;
16541 put_thumb32_insn (buf
, insn
);
16542 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
16545 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
16548 case T_MNEM_add_sp
:
16549 case T_MNEM_add_pc
:
16550 case T_MNEM_inc_sp
:
16551 case T_MNEM_dec_sp
:
16552 if (fragp
->fr_var
== 4)
16554 /* ??? Choose between add and addw. */
16555 insn
= THUMB_OP32 (opcode
);
16556 insn
|= (old_op
& 0xf0) << 4;
16557 put_thumb32_insn (buf
, insn
);
16558 if (opcode
== T_MNEM_add_pc
)
16559 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
16561 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16564 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16572 if (fragp
->fr_var
== 4)
16574 insn
= THUMB_OP32 (opcode
);
16575 insn
|= (old_op
& 0xf0) << 4;
16576 insn
|= (old_op
& 0xf) << 16;
16577 put_thumb32_insn (buf
, insn
);
16578 if (insn
& (1 << 20))
16579 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16581 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16584 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16590 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
16592 fixp
->fx_file
= fragp
->fr_file
;
16593 fixp
->fx_line
= fragp
->fr_line
;
16594 fragp
->fr_fix
+= fragp
->fr_var
;
16597 /* Return the size of a relaxable immediate operand instruction.
16598 SHIFT and SIZE specify the form of the allowable immediate. */
16600 relax_immediate (fragS
*fragp
, int size
, int shift
)
16606 /* ??? Should be able to do better than this. */
16607 if (fragp
->fr_symbol
)
16610 low
= (1 << shift
) - 1;
16611 mask
= (1 << (shift
+ size
)) - (1 << shift
);
16612 offset
= fragp
->fr_offset
;
16613 /* Force misaligned offsets to 32-bit variant. */
16616 if (offset
& ~mask
)
16621 /* Get the address of a symbol during relaxation. */
16623 relaxed_symbol_addr(fragS
*fragp
, long stretch
)
16629 sym
= fragp
->fr_symbol
;
16630 sym_frag
= symbol_get_frag (sym
);
16631 know (S_GET_SEGMENT (sym
) != absolute_section
16632 || sym_frag
== &zero_address_frag
);
16633 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
16635 /* If frag has yet to be reached on this pass, assume it will
16636 move by STRETCH just as we did. If this is not so, it will
16637 be because some frag between grows, and that will force
16641 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
16647 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
16650 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
16655 /* Assume worst case for symbols not known to be in the same section. */
16656 if (!S_IS_DEFINED(fragp
->fr_symbol
)
16657 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16660 val
= relaxed_symbol_addr(fragp
, stretch
);
16661 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16662 addr
= (addr
+ 4) & ~3;
16663 /* Force misaligned targets to 32-bit variant. */
16667 if (val
< 0 || val
> 1020)
16672 /* Return the size of a relaxable add/sub immediate instruction. */
16674 relax_addsub (fragS
*fragp
, asection
*sec
)
16679 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16680 op
= bfd_get_16(sec
->owner
, buf
);
16681 if ((op
& 0xf) == ((op
>> 4) & 0xf))
16682 return relax_immediate (fragp
, 8, 0);
16684 return relax_immediate (fragp
, 3, 0);
16688 /* Return the size of a relaxable branch instruction. BITS is the
16689 size of the offset field in the narrow instruction. */
16692 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
16698 /* Assume worst case for symbols not known to be in the same section. */
16699 if (!S_IS_DEFINED(fragp
->fr_symbol
)
16700 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16703 val
= relaxed_symbol_addr(fragp
, stretch
);
16704 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16707 /* Offset is a signed value *2 */
16709 if (val
>= limit
|| val
< -limit
)
16715 /* Relax a machine dependent frag. This returns the amount by which
16716 the current size of the frag should change. */
16719 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
16724 oldsize
= fragp
->fr_var
;
16725 switch (fragp
->fr_subtype
)
16727 case T_MNEM_ldr_pc2
:
16728 newsize
= relax_adr(fragp
, sec
, stretch
);
16730 case T_MNEM_ldr_pc
:
16731 case T_MNEM_ldr_sp
:
16732 case T_MNEM_str_sp
:
16733 newsize
= relax_immediate(fragp
, 8, 2);
16737 newsize
= relax_immediate(fragp
, 5, 2);
16741 newsize
= relax_immediate(fragp
, 5, 1);
16745 newsize
= relax_immediate(fragp
, 5, 0);
16748 newsize
= relax_adr(fragp
, sec
, stretch
);
16754 newsize
= relax_immediate(fragp
, 8, 0);
16757 newsize
= relax_branch(fragp
, sec
, 11, stretch
);
16760 newsize
= relax_branch(fragp
, sec
, 8, stretch
);
16762 case T_MNEM_add_sp
:
16763 case T_MNEM_add_pc
:
16764 newsize
= relax_immediate (fragp
, 8, 2);
16766 case T_MNEM_inc_sp
:
16767 case T_MNEM_dec_sp
:
16768 newsize
= relax_immediate (fragp
, 7, 2);
16774 newsize
= relax_addsub (fragp
, sec
);
16780 fragp
->fr_var
= newsize
;
16781 /* Freeze wide instructions that are at or before the same location as
16782 in the previous pass. This avoids infinite loops.
16783 Don't freeze them unconditionally because targets may be artificialy
16784 misaligned by the expansion of preceeding frags. */
16785 if (stretch
<= 0 && newsize
> 2)
16787 md_convert_frag (sec
->owner
, sec
, fragp
);
16791 return newsize
- oldsize
;
16794 /* Round up a section size to the appropriate boundary. */
16797 md_section_align (segT segment ATTRIBUTE_UNUSED
,
16800 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
16801 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
16803 /* For a.out, force the section size to be aligned. If we don't do
16804 this, BFD will align it for us, but it will not write out the
16805 final bytes of the section. This may be a bug in BFD, but it is
16806 easier to fix it here since that is how the other a.out targets
16810 align
= bfd_get_section_alignment (stdoutput
, segment
);
16811 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
16818 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
16819 of an rs_align_code fragment. */
16822 arm_handle_align (fragS
* fragP
)
16824 static char const arm_noop
[4] = { 0x00, 0x00, 0xa0, 0xe1 };
16825 static char const thumb_noop
[2] = { 0xc0, 0x46 };
16826 static char const arm_bigend_noop
[4] = { 0xe1, 0xa0, 0x00, 0x00 };
16827 static char const thumb_bigend_noop
[2] = { 0x46, 0xc0 };
16829 int bytes
, fix
, noop_size
;
16833 if (fragP
->fr_type
!= rs_align_code
)
16836 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
16837 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
16840 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
16841 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
16843 if (fragP
->tc_frag_data
)
16845 if (target_big_endian
)
16846 noop
= thumb_bigend_noop
;
16849 noop_size
= sizeof (thumb_noop
);
16853 if (target_big_endian
)
16854 noop
= arm_bigend_noop
;
16857 noop_size
= sizeof (arm_noop
);
16860 if (bytes
& (noop_size
- 1))
16862 fix
= bytes
& (noop_size
- 1);
16863 memset (p
, 0, fix
);
16868 while (bytes
>= noop_size
)
16870 memcpy (p
, noop
, noop_size
);
16872 bytes
-= noop_size
;
16876 fragP
->fr_fix
+= fix
;
16877 fragP
->fr_var
= noop_size
;
16880 /* Called from md_do_align. Used to create an alignment
16881 frag in a code section. */
16884 arm_frag_align_code (int n
, int max
)
16888 /* We assume that there will never be a requirement
16889 to support alignments greater than 32 bytes. */
16890 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
16891 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
16893 p
= frag_var (rs_align_code
,
16894 MAX_MEM_FOR_RS_ALIGN_CODE
,
16896 (relax_substateT
) max
,
16903 /* Perform target specific initialisation of a frag. */
16906 arm_init_frag (fragS
* fragP
)
16908 /* Record whether this frag is in an ARM or a THUMB area. */
16909 fragP
->tc_frag_data
= thumb_mode
;
16913 /* When we change sections we need to issue a new mapping symbol. */
16916 arm_elf_change_section (void)
16919 segment_info_type
*seginfo
;
16921 /* Link an unlinked unwind index table section to the .text section. */
16922 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
16923 && elf_linked_to_section (now_seg
) == NULL
)
16924 elf_linked_to_section (now_seg
) = text_section
;
16926 if (!SEG_NORMAL (now_seg
))
16929 flags
= bfd_get_section_flags (stdoutput
, now_seg
);
16931 /* We can ignore sections that only contain debug info. */
16932 if ((flags
& SEC_ALLOC
) == 0)
16935 seginfo
= seg_info (now_seg
);
16936 mapstate
= seginfo
->tc_segment_info_data
.mapstate
;
16937 marked_pr_dependency
= seginfo
->tc_segment_info_data
.marked_pr_dependency
;
16941 arm_elf_section_type (const char * str
, size_t len
)
16943 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
16944 return SHT_ARM_EXIDX
;
16949 /* Code to deal with unwinding tables. */
16951 static void add_unwind_adjustsp (offsetT
);
16953 /* Cenerate and deferred unwind frame offset. */
16956 flush_pending_unwind (void)
16960 offset
= unwind
.pending_offset
;
16961 unwind
.pending_offset
= 0;
16963 add_unwind_adjustsp (offset
);
16966 /* Add an opcode to this list for this function. Two-byte opcodes should
16967 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
16971 add_unwind_opcode (valueT op
, int length
)
16973 /* Add any deferred stack adjustment. */
16974 if (unwind
.pending_offset
)
16975 flush_pending_unwind ();
16977 unwind
.sp_restored
= 0;
16979 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
16981 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
16982 if (unwind
.opcodes
)
16983 unwind
.opcodes
= xrealloc (unwind
.opcodes
,
16984 unwind
.opcode_alloc
);
16986 unwind
.opcodes
= xmalloc (unwind
.opcode_alloc
);
16991 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
16993 unwind
.opcode_count
++;
16997 /* Add unwind opcodes to adjust the stack pointer. */
17000 add_unwind_adjustsp (offsetT offset
)
17004 if (offset
> 0x200)
17006 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
17011 /* Long form: 0xb2, uleb128. */
17012 /* This might not fit in a word so add the individual bytes,
17013 remembering the list is built in reverse order. */
17014 o
= (valueT
) ((offset
- 0x204) >> 2);
17016 add_unwind_opcode (0, 1);
17018 /* Calculate the uleb128 encoding of the offset. */
17022 bytes
[n
] = o
& 0x7f;
17028 /* Add the insn. */
17030 add_unwind_opcode (bytes
[n
- 1], 1);
17031 add_unwind_opcode (0xb2, 1);
17033 else if (offset
> 0x100)
17035 /* Two short opcodes. */
17036 add_unwind_opcode (0x3f, 1);
17037 op
= (offset
- 0x104) >> 2;
17038 add_unwind_opcode (op
, 1);
17040 else if (offset
> 0)
17042 /* Short opcode. */
17043 op
= (offset
- 4) >> 2;
17044 add_unwind_opcode (op
, 1);
17046 else if (offset
< 0)
17049 while (offset
> 0x100)
17051 add_unwind_opcode (0x7f, 1);
17054 op
= ((offset
- 4) >> 2) | 0x40;
17055 add_unwind_opcode (op
, 1);
17059 /* Finish the list of unwind opcodes for this function. */
17061 finish_unwind_opcodes (void)
17065 if (unwind
.fp_used
)
17067 /* Adjust sp as necessary. */
17068 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
17069 flush_pending_unwind ();
17071 /* After restoring sp from the frame pointer. */
17072 op
= 0x90 | unwind
.fp_reg
;
17073 add_unwind_opcode (op
, 1);
17076 flush_pending_unwind ();
17080 /* Start an exception table entry. If idx is nonzero this is an index table
17084 start_unwind_section (const segT text_seg
, int idx
)
17086 const char * text_name
;
17087 const char * prefix
;
17088 const char * prefix_once
;
17089 const char * group_name
;
17093 size_t sec_name_len
;
17100 prefix
= ELF_STRING_ARM_unwind
;
17101 prefix_once
= ELF_STRING_ARM_unwind_once
;
17102 type
= SHT_ARM_EXIDX
;
17106 prefix
= ELF_STRING_ARM_unwind_info
;
17107 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
17108 type
= SHT_PROGBITS
;
17111 text_name
= segment_name (text_seg
);
17112 if (streq (text_name
, ".text"))
17115 if (strncmp (text_name
, ".gnu.linkonce.t.",
17116 strlen (".gnu.linkonce.t.")) == 0)
17118 prefix
= prefix_once
;
17119 text_name
+= strlen (".gnu.linkonce.t.");
17122 prefix_len
= strlen (prefix
);
17123 text_len
= strlen (text_name
);
17124 sec_name_len
= prefix_len
+ text_len
;
17125 sec_name
= xmalloc (sec_name_len
+ 1);
17126 memcpy (sec_name
, prefix
, prefix_len
);
17127 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
17128 sec_name
[prefix_len
+ text_len
] = '\0';
17134 /* Handle COMDAT group. */
17135 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
17137 group_name
= elf_group_name (text_seg
);
17138 if (group_name
== NULL
)
17140 as_bad ("Group section `%s' has no group signature",
17141 segment_name (text_seg
));
17142 ignore_rest_of_line ();
17145 flags
|= SHF_GROUP
;
17149 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
17151 /* Set the setion link for index tables. */
17153 elf_linked_to_section (now_seg
) = text_seg
;
17157 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
17158 personality routine data. Returns zero, or the index table value for
17159 and inline entry. */
17162 create_unwind_entry (int have_data
)
17167 /* The current word of data. */
17169 /* The number of bytes left in this word. */
17172 finish_unwind_opcodes ();
17174 /* Remember the current text section. */
17175 unwind
.saved_seg
= now_seg
;
17176 unwind
.saved_subseg
= now_subseg
;
17178 start_unwind_section (now_seg
, 0);
17180 if (unwind
.personality_routine
== NULL
)
17182 if (unwind
.personality_index
== -2)
17185 as_bad (_("handerdata in cantunwind frame"));
17186 return 1; /* EXIDX_CANTUNWIND. */
17189 /* Use a default personality routine if none is specified. */
17190 if (unwind
.personality_index
== -1)
17192 if (unwind
.opcode_count
> 3)
17193 unwind
.personality_index
= 1;
17195 unwind
.personality_index
= 0;
17198 /* Space for the personality routine entry. */
17199 if (unwind
.personality_index
== 0)
17201 if (unwind
.opcode_count
> 3)
17202 as_bad (_("too many unwind opcodes for personality routine 0"));
17206 /* All the data is inline in the index table. */
17209 while (unwind
.opcode_count
> 0)
17211 unwind
.opcode_count
--;
17212 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
17216 /* Pad with "finish" opcodes. */
17218 data
= (data
<< 8) | 0xb0;
17225 /* We get two opcodes "free" in the first word. */
17226 size
= unwind
.opcode_count
- 2;
17229 /* An extra byte is required for the opcode count. */
17230 size
= unwind
.opcode_count
+ 1;
17232 size
= (size
+ 3) >> 2;
17234 as_bad (_("too many unwind opcodes"));
17236 frag_align (2, 0, 0);
17237 record_alignment (now_seg
, 2);
17238 unwind
.table_entry
= expr_build_dot ();
17240 /* Allocate the table entry. */
17241 ptr
= frag_more ((size
<< 2) + 4);
17242 where
= frag_now_fix () - ((size
<< 2) + 4);
17244 switch (unwind
.personality_index
)
17247 /* ??? Should this be a PLT generating relocation? */
17248 /* Custom personality routine. */
17249 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
17250 BFD_RELOC_ARM_PREL31
);
17255 /* Set the first byte to the number of additional words. */
17260 /* ABI defined personality routines. */
17262 /* Three opcodes bytes are packed into the first word. */
17269 /* The size and first two opcode bytes go in the first word. */
17270 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
17275 /* Should never happen. */
17279 /* Pack the opcodes into words (MSB first), reversing the list at the same
17281 while (unwind
.opcode_count
> 0)
17285 md_number_to_chars (ptr
, data
, 4);
17290 unwind
.opcode_count
--;
17292 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
17295 /* Finish off the last word. */
17298 /* Pad with "finish" opcodes. */
17300 data
= (data
<< 8) | 0xb0;
17302 md_number_to_chars (ptr
, data
, 4);
17307 /* Add an empty descriptor if there is no user-specified data. */
17308 ptr
= frag_more (4);
17309 md_number_to_chars (ptr
, 0, 4);
17316 /* Initialize the DWARF-2 unwind information for this procedure. */
17319 tc_arm_frame_initial_instructions (void)
17321 cfi_add_CFA_def_cfa (REG_SP
, 0);
17323 #endif /* OBJ_ELF */
17325 /* Convert REGNAME to a DWARF-2 register number. */
17328 tc_arm_regname_to_dw2regnum (char *regname
)
17330 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
17340 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
17344 expr
.X_op
= O_secrel
;
17345 expr
.X_add_symbol
= symbol
;
17346 expr
.X_add_number
= 0;
17347 emit_expr (&expr
, size
);
17351 /* MD interface: Symbol and relocation handling. */
17353 /* Return the address within the segment that a PC-relative fixup is
17354 relative to. For ARM, PC-relative fixups applied to instructions
17355 are generally relative to the location of the fixup plus 8 bytes.
17356 Thumb branches are offset by 4, and Thumb loads relative to PC
17357 require special handling. */
17360 md_pcrel_from_section (fixS
* fixP
, segT seg
)
17362 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
17364 /* If this is pc-relative and we are going to emit a relocation
17365 then we just want to put out any pipeline compensation that the linker
17366 will need. Otherwise we want to use the calculated base.
17367 For WinCE we skip the bias for externals as well, since this
17368 is how the MS ARM-CE assembler behaves and we want to be compatible. */
17370 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
17371 || (arm_force_relocation (fixP
)
17373 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
17378 switch (fixP
->fx_r_type
)
17380 /* PC relative addressing on the Thumb is slightly odd as the
17381 bottom two bits of the PC are forced to zero for the
17382 calculation. This happens *after* application of the
17383 pipeline offset. However, Thumb adrl already adjusts for
17384 this, so we need not do it again. */
17385 case BFD_RELOC_ARM_THUMB_ADD
:
17388 case BFD_RELOC_ARM_THUMB_OFFSET
:
17389 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
17390 case BFD_RELOC_ARM_T32_ADD_PC12
:
17391 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
17392 return (base
+ 4) & ~3;
17394 /* Thumb branches are simply offset by +4. */
17395 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
17396 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
17397 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
17398 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
17399 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
17400 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
17401 case BFD_RELOC_THUMB_PCREL_BLX
:
17404 /* ARM mode branches are offset by +8. However, the Windows CE
17405 loader expects the relocation not to take this into account. */
17406 case BFD_RELOC_ARM_PCREL_BRANCH
:
17407 case BFD_RELOC_ARM_PCREL_CALL
:
17408 case BFD_RELOC_ARM_PCREL_JUMP
:
17409 case BFD_RELOC_ARM_PCREL_BLX
:
17410 case BFD_RELOC_ARM_PLT32
:
17412 /* When handling fixups immediately, because we have already
17413 discovered the value of a symbol, or the address of the frag involved
17414 we must account for the offset by +8, as the OS loader will never see the reloc.
17415 see fixup_segment() in write.c
17416 The S_IS_EXTERNAL test handles the case of global symbols.
17417 Those need the calculated base, not just the pipe compensation the linker will need. */
17419 && fixP
->fx_addsy
!= NULL
17420 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
17421 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
17428 /* ARM mode loads relative to PC are also offset by +8. Unlike
17429 branches, the Windows CE loader *does* expect the relocation
17430 to take this into account. */
17431 case BFD_RELOC_ARM_OFFSET_IMM
:
17432 case BFD_RELOC_ARM_OFFSET_IMM8
:
17433 case BFD_RELOC_ARM_HWLITERAL
:
17434 case BFD_RELOC_ARM_LITERAL
:
17435 case BFD_RELOC_ARM_CP_OFF_IMM
:
17439 /* Other PC-relative relocations are un-offset. */
17445 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
17446 Otherwise we have no need to default values of symbols. */
17449 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
17452 if (name
[0] == '_' && name
[1] == 'G'
17453 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
17457 if (symbol_find (name
))
17458 as_bad ("GOT already in the symbol table");
17460 GOT_symbol
= symbol_new (name
, undefined_section
,
17461 (valueT
) 0, & zero_address_frag
);
17471 /* Subroutine of md_apply_fix. Check to see if an immediate can be
17472 computed as two separate immediate values, added together. We
17473 already know that this value cannot be computed by just one ARM
17476 static unsigned int
17477 validate_immediate_twopart (unsigned int val
,
17478 unsigned int * highpart
)
17483 for (i
= 0; i
< 32; i
+= 2)
17484 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
17490 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
17492 else if (a
& 0xff0000)
17494 if (a
& 0xff000000)
17496 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
17500 assert (a
& 0xff000000);
17501 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
17504 return (a
& 0xff) | (i
<< 7);
17511 validate_offset_imm (unsigned int val
, int hwse
)
17513 if ((hwse
&& val
> 255) || val
> 4095)
17518 /* Subroutine of md_apply_fix. Do those data_ops which can take a
17519 negative immediate constant by altering the instruction. A bit of
17524 by inverting the second operand, and
17527 by negating the second operand. */
17530 negate_data_op (unsigned long * instruction
,
17531 unsigned long value
)
17534 unsigned long negated
, inverted
;
17536 negated
= encode_arm_immediate (-value
);
17537 inverted
= encode_arm_immediate (~value
);
17539 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
17542 /* First negates. */
17543 case OPCODE_SUB
: /* ADD <-> SUB */
17544 new_inst
= OPCODE_ADD
;
17549 new_inst
= OPCODE_SUB
;
17553 case OPCODE_CMP
: /* CMP <-> CMN */
17554 new_inst
= OPCODE_CMN
;
17559 new_inst
= OPCODE_CMP
;
17563 /* Now Inverted ops. */
17564 case OPCODE_MOV
: /* MOV <-> MVN */
17565 new_inst
= OPCODE_MVN
;
17570 new_inst
= OPCODE_MOV
;
17574 case OPCODE_AND
: /* AND <-> BIC */
17575 new_inst
= OPCODE_BIC
;
17580 new_inst
= OPCODE_AND
;
17584 case OPCODE_ADC
: /* ADC <-> SBC */
17585 new_inst
= OPCODE_SBC
;
17590 new_inst
= OPCODE_ADC
;
17594 /* We cannot do anything. */
17599 if (value
== (unsigned) FAIL
)
17602 *instruction
&= OPCODE_MASK
;
17603 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
17607 /* Like negate_data_op, but for Thumb-2. */
17609 static unsigned int
17610 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
17614 unsigned int negated
, inverted
;
17616 negated
= encode_thumb32_immediate (-value
);
17617 inverted
= encode_thumb32_immediate (~value
);
17619 rd
= (*instruction
>> 8) & 0xf;
17620 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
17623 /* ADD <-> SUB. Includes CMP <-> CMN. */
17624 case T2_OPCODE_SUB
:
17625 new_inst
= T2_OPCODE_ADD
;
17629 case T2_OPCODE_ADD
:
17630 new_inst
= T2_OPCODE_SUB
;
17634 /* ORR <-> ORN. Includes MOV <-> MVN. */
17635 case T2_OPCODE_ORR
:
17636 new_inst
= T2_OPCODE_ORN
;
17640 case T2_OPCODE_ORN
:
17641 new_inst
= T2_OPCODE_ORR
;
17645 /* AND <-> BIC. TST has no inverted equivalent. */
17646 case T2_OPCODE_AND
:
17647 new_inst
= T2_OPCODE_BIC
;
17654 case T2_OPCODE_BIC
:
17655 new_inst
= T2_OPCODE_AND
;
17660 case T2_OPCODE_ADC
:
17661 new_inst
= T2_OPCODE_SBC
;
17665 case T2_OPCODE_SBC
:
17666 new_inst
= T2_OPCODE_ADC
;
17670 /* We cannot do anything. */
17675 if (value
== (unsigned int)FAIL
)
17678 *instruction
&= T2_OPCODE_MASK
;
17679 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
17683 /* Read a 32-bit thumb instruction from buf. */
17684 static unsigned long
17685 get_thumb32_insn (char * buf
)
17687 unsigned long insn
;
17688 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
17689 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17695 /* We usually want to set the low bit on the address of thumb function
17696 symbols. In particular .word foo - . should have the low bit set.
17697 Generic code tries to fold the difference of two symbols to
17698 a constant. Prevent this and force a relocation when the first symbols
17699 is a thumb function. */
17701 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
17703 if (op
== O_subtract
17704 && l
->X_op
== O_symbol
17705 && r
->X_op
== O_symbol
17706 && THUMB_IS_FUNC (l
->X_add_symbol
))
17708 l
->X_op
= O_subtract
;
17709 l
->X_op_symbol
= r
->X_add_symbol
;
17710 l
->X_add_number
-= r
->X_add_number
;
17713 /* Process as normal. */
17718 md_apply_fix (fixS
* fixP
,
17722 offsetT value
= * valP
;
17724 unsigned int newimm
;
17725 unsigned long temp
;
17727 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
17729 assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
17731 /* Note whether this will delete the relocation. */
17733 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
17736 /* On a 64-bit host, silently truncate 'value' to 32 bits for
17737 consistency with the behavior on 32-bit hosts. Remember value
17739 value
&= 0xffffffff;
17740 value
^= 0x80000000;
17741 value
-= 0x80000000;
17744 fixP
->fx_addnumber
= value
;
17746 /* Same treatment for fixP->fx_offset. */
17747 fixP
->fx_offset
&= 0xffffffff;
17748 fixP
->fx_offset
^= 0x80000000;
17749 fixP
->fx_offset
-= 0x80000000;
17751 switch (fixP
->fx_r_type
)
17753 case BFD_RELOC_NONE
:
17754 /* This will need to go in the object file. */
17758 case BFD_RELOC_ARM_IMMEDIATE
:
17759 /* We claim that this fixup has been processed here,
17760 even if in fact we generate an error because we do
17761 not have a reloc for it, so tc_gen_reloc will reject it. */
17765 && ! S_IS_DEFINED (fixP
->fx_addsy
))
17767 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17768 _("undefined symbol %s used as an immediate value"),
17769 S_GET_NAME (fixP
->fx_addsy
));
17773 newimm
= encode_arm_immediate (value
);
17774 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17776 /* If the instruction will fail, see if we can fix things up by
17777 changing the opcode. */
17778 if (newimm
== (unsigned int) FAIL
17779 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
17781 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17782 _("invalid constant (%lx) after fixup"),
17783 (unsigned long) value
);
17787 newimm
|= (temp
& 0xfffff000);
17788 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
17791 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
17793 unsigned int highpart
= 0;
17794 unsigned int newinsn
= 0xe1a00000; /* nop. */
17796 newimm
= encode_arm_immediate (value
);
17797 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17799 /* If the instruction will fail, see if we can fix things up by
17800 changing the opcode. */
17801 if (newimm
== (unsigned int) FAIL
17802 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
17804 /* No ? OK - try using two ADD instructions to generate
17806 newimm
= validate_immediate_twopart (value
, & highpart
);
17808 /* Yes - then make sure that the second instruction is
17810 if (newimm
!= (unsigned int) FAIL
)
17812 /* Still No ? Try using a negated value. */
17813 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
17814 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
17815 /* Otherwise - give up. */
17818 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17819 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
17824 /* Replace the first operand in the 2nd instruction (which
17825 is the PC) with the destination register. We have
17826 already added in the PC in the first instruction and we
17827 do not want to do it again. */
17828 newinsn
&= ~ 0xf0000;
17829 newinsn
|= ((newinsn
& 0x0f000) << 4);
17832 newimm
|= (temp
& 0xfffff000);
17833 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
17835 highpart
|= (newinsn
& 0xfffff000);
17836 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
17840 case BFD_RELOC_ARM_OFFSET_IMM
:
17841 if (!fixP
->fx_done
&& seg
->use_rela_p
)
17844 case BFD_RELOC_ARM_LITERAL
:
17850 if (validate_offset_imm (value
, 0) == FAIL
)
17852 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
17853 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17854 _("invalid literal constant: pool needs to be closer"));
17856 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17857 _("bad immediate value for offset (%ld)"),
17862 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17863 newval
&= 0xff7ff000;
17864 newval
|= value
| (sign
? INDEX_UP
: 0);
17865 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17868 case BFD_RELOC_ARM_OFFSET_IMM8
:
17869 case BFD_RELOC_ARM_HWLITERAL
:
17875 if (validate_offset_imm (value
, 1) == FAIL
)
17877 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
17878 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17879 _("invalid literal constant: pool needs to be closer"));
17881 as_bad (_("bad immediate value for half-word offset (%ld)"),
17886 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17887 newval
&= 0xff7ff0f0;
17888 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
17889 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17892 case BFD_RELOC_ARM_T32_OFFSET_U8
:
17893 if (value
< 0 || value
> 1020 || value
% 4 != 0)
17894 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17895 _("bad immediate value for offset (%ld)"), (long) value
);
17898 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
17900 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
17903 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
17904 /* This is a complicated relocation used for all varieties of Thumb32
17905 load/store instruction with immediate offset:
17907 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
17908 *4, optional writeback(W)
17909 (doubleword load/store)
17911 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
17912 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
17913 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
17914 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
17915 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
17917 Uppercase letters indicate bits that are already encoded at
17918 this point. Lowercase letters are our problem. For the
17919 second block of instructions, the secondary opcode nybble
17920 (bits 8..11) is present, and bit 23 is zero, even if this is
17921 a PC-relative operation. */
17922 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17924 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
17926 if ((newval
& 0xf0000000) == 0xe0000000)
17928 /* Doubleword load/store: 8-bit offset, scaled by 4. */
17930 newval
|= (1 << 23);
17933 if (value
% 4 != 0)
17935 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17936 _("offset not a multiple of 4"));
17942 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17943 _("offset out of range"));
17948 else if ((newval
& 0x000f0000) == 0x000f0000)
17950 /* PC-relative, 12-bit offset. */
17952 newval
|= (1 << 23);
17957 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17958 _("offset out of range"));
17963 else if ((newval
& 0x00000100) == 0x00000100)
17965 /* Writeback: 8-bit, +/- offset. */
17967 newval
|= (1 << 9);
17972 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17973 _("offset out of range"));
17978 else if ((newval
& 0x00000f00) == 0x00000e00)
17980 /* T-instruction: positive 8-bit offset. */
17981 if (value
< 0 || value
> 0xff)
17983 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17984 _("offset out of range"));
17992 /* Positive 12-bit or negative 8-bit offset. */
17996 newval
|= (1 << 23);
18006 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18007 _("offset out of range"));
18014 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
18015 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
18018 case BFD_RELOC_ARM_SHIFT_IMM
:
18019 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18020 if (((unsigned long) value
) > 32
18022 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
18024 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18025 _("shift expression is too large"));
18030 /* Shifts of zero must be done as lsl. */
18032 else if (value
== 32)
18034 newval
&= 0xfffff07f;
18035 newval
|= (value
& 0x1f) << 7;
18036 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18039 case BFD_RELOC_ARM_T32_IMMEDIATE
:
18040 case BFD_RELOC_ARM_T32_ADD_IMM
:
18041 case BFD_RELOC_ARM_T32_IMM12
:
18042 case BFD_RELOC_ARM_T32_ADD_PC12
:
18043 /* We claim that this fixup has been processed here,
18044 even if in fact we generate an error because we do
18045 not have a reloc for it, so tc_gen_reloc will reject it. */
18049 && ! S_IS_DEFINED (fixP
->fx_addsy
))
18051 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18052 _("undefined symbol %s used as an immediate value"),
18053 S_GET_NAME (fixP
->fx_addsy
));
18057 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18059 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
18062 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
18063 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
18065 newimm
= encode_thumb32_immediate (value
);
18066 if (newimm
== (unsigned int) FAIL
)
18067 newimm
= thumb32_negate_data_op (&newval
, value
);
18069 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
18070 && newimm
== (unsigned int) FAIL
)
18072 /* Turn add/sum into addw/subw. */
18073 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
18074 newval
= (newval
& 0xfeffffff) | 0x02000000;
18076 /* 12 bit immediate for addw/subw. */
18080 newval
^= 0x00a00000;
18083 newimm
= (unsigned int) FAIL
;
18088 if (newimm
== (unsigned int)FAIL
)
18090 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18091 _("invalid constant (%lx) after fixup"),
18092 (unsigned long) value
);
18096 newval
|= (newimm
& 0x800) << 15;
18097 newval
|= (newimm
& 0x700) << 4;
18098 newval
|= (newimm
& 0x0ff);
18100 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
18101 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
18104 case BFD_RELOC_ARM_SMC
:
18105 if (((unsigned long) value
) > 0xffff)
18106 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18107 _("invalid smc expression"));
18108 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18109 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
18110 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18113 case BFD_RELOC_ARM_SWI
:
18114 if (fixP
->tc_fix_data
!= 0)
18116 if (((unsigned long) value
) > 0xff)
18117 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18118 _("invalid swi expression"));
18119 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18121 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18125 if (((unsigned long) value
) > 0x00ffffff)
18126 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18127 _("invalid swi expression"));
18128 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18130 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18134 case BFD_RELOC_ARM_MULTI
:
18135 if (((unsigned long) value
) > 0xffff)
18136 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18137 _("invalid expression in load/store multiple"));
18138 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
18139 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18143 case BFD_RELOC_ARM_PCREL_CALL
:
18144 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18145 if ((newval
& 0xf0000000) == 0xf0000000)
18149 goto arm_branch_common
;
18151 case BFD_RELOC_ARM_PCREL_JUMP
:
18152 case BFD_RELOC_ARM_PLT32
:
18154 case BFD_RELOC_ARM_PCREL_BRANCH
:
18156 goto arm_branch_common
;
18158 case BFD_RELOC_ARM_PCREL_BLX
:
18161 /* We are going to store value (shifted right by two) in the
18162 instruction, in a 24 bit, signed field. Bits 26 through 32 either
18163 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
18164 also be be clear. */
18166 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18167 _("misaligned branch destination"));
18168 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
18169 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
18170 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18171 _("branch out of range"));
18173 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18175 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18176 newval
|= (value
>> 2) & 0x00ffffff;
18177 /* Set the H bit on BLX instructions. */
18181 newval
|= 0x01000000;
18183 newval
&= ~0x01000000;
18185 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18189 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
18190 /* CBZ can only branch forward. */
18192 /* Attempts to use CBZ to branch to the next instruction
18193 (which, strictly speaking, are prohibited) will be turned into
18196 FIXME: It may be better to remove the instruction completely and
18197 perform relaxation. */
18200 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18201 newval
= 0xbf00; /* NOP encoding T1 */
18202 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18207 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18208 _("branch out of range"));
18210 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18212 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18213 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
18214 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18219 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
18220 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
18221 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18222 _("branch out of range"));
18224 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18226 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18227 newval
|= (value
& 0x1ff) >> 1;
18228 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18232 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
18233 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
18234 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18235 _("branch out of range"));
18237 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18239 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18240 newval
|= (value
& 0xfff) >> 1;
18241 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18245 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
18246 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
18247 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18248 _("conditional branch out of range"));
18250 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18253 addressT S
, J1
, J2
, lo
, hi
;
18255 S
= (value
& 0x00100000) >> 20;
18256 J2
= (value
& 0x00080000) >> 19;
18257 J1
= (value
& 0x00040000) >> 18;
18258 hi
= (value
& 0x0003f000) >> 12;
18259 lo
= (value
& 0x00000ffe) >> 1;
18261 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18262 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18263 newval
|= (S
<< 10) | hi
;
18264 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
18265 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18266 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18270 case BFD_RELOC_THUMB_PCREL_BLX
:
18271 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
18272 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
18273 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18274 _("branch out of range"));
18276 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
18277 /* For a BLX instruction, make sure that the relocation is rounded up
18278 to a word boundary. This follows the semantics of the instruction
18279 which specifies that bit 1 of the target address will come from bit
18280 1 of the base address. */
18281 value
= (value
+ 1) & ~ 1;
18283 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18287 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18288 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18289 newval
|= (value
& 0x7fffff) >> 12;
18290 newval2
|= (value
& 0xfff) >> 1;
18291 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18292 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18296 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
18297 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
18298 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18299 _("branch out of range"));
18301 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18304 addressT S
, I1
, I2
, lo
, hi
;
18306 S
= (value
& 0x01000000) >> 24;
18307 I1
= (value
& 0x00800000) >> 23;
18308 I2
= (value
& 0x00400000) >> 22;
18309 hi
= (value
& 0x003ff000) >> 12;
18310 lo
= (value
& 0x00000ffe) >> 1;
18315 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18316 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18317 newval
|= (S
<< 10) | hi
;
18318 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
18319 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18320 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18325 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18326 md_number_to_chars (buf
, value
, 1);
18330 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18331 md_number_to_chars (buf
, value
, 2);
18335 case BFD_RELOC_ARM_TLS_GD32
:
18336 case BFD_RELOC_ARM_TLS_LE32
:
18337 case BFD_RELOC_ARM_TLS_IE32
:
18338 case BFD_RELOC_ARM_TLS_LDM32
:
18339 case BFD_RELOC_ARM_TLS_LDO32
:
18340 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
18343 case BFD_RELOC_ARM_GOT32
:
18344 case BFD_RELOC_ARM_GOTOFF
:
18345 case BFD_RELOC_ARM_TARGET2
:
18346 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18347 md_number_to_chars (buf
, 0, 4);
18351 case BFD_RELOC_RVA
:
18353 case BFD_RELOC_ARM_TARGET1
:
18354 case BFD_RELOC_ARM_ROSEGREL32
:
18355 case BFD_RELOC_ARM_SBREL32
:
18356 case BFD_RELOC_32_PCREL
:
18358 case BFD_RELOC_32_SECREL
:
18360 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18362 /* For WinCE we only do this for pcrel fixups. */
18363 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
18365 md_number_to_chars (buf
, value
, 4);
18369 case BFD_RELOC_ARM_PREL31
:
18370 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18372 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
18373 if ((value
^ (value
>> 1)) & 0x40000000)
18375 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18376 _("rel31 relocation overflow"));
18378 newval
|= value
& 0x7fffffff;
18379 md_number_to_chars (buf
, newval
, 4);
18384 case BFD_RELOC_ARM_CP_OFF_IMM
:
18385 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
18386 if (value
< -1023 || value
> 1023 || (value
& 3))
18387 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18388 _("co-processor offset out of range"));
18393 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18394 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18395 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18397 newval
= get_thumb32_insn (buf
);
18398 newval
&= 0xff7fff00;
18399 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
18400 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18401 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18402 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18404 put_thumb32_insn (buf
, newval
);
18407 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
18408 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
18409 if (value
< -255 || value
> 255)
18410 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18411 _("co-processor offset out of range"));
18413 goto cp_off_common
;
18415 case BFD_RELOC_ARM_THUMB_OFFSET
:
18416 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18417 /* Exactly what ranges, and where the offset is inserted depends
18418 on the type of instruction, we can establish this from the
18420 switch (newval
>> 12)
18422 case 4: /* PC load. */
18423 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
18424 forced to zero for these loads; md_pcrel_from has already
18425 compensated for this. */
18427 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18428 _("invalid offset, target not word aligned (0x%08lX)"),
18429 (((unsigned long) fixP
->fx_frag
->fr_address
18430 + (unsigned long) fixP
->fx_where
) & ~3)
18431 + (unsigned long) value
);
18433 if (value
& ~0x3fc)
18434 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18435 _("invalid offset, value too big (0x%08lX)"),
18438 newval
|= value
>> 2;
18441 case 9: /* SP load/store. */
18442 if (value
& ~0x3fc)
18443 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18444 _("invalid offset, value too big (0x%08lX)"),
18446 newval
|= value
>> 2;
18449 case 6: /* Word load/store. */
18451 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18452 _("invalid offset, value too big (0x%08lX)"),
18454 newval
|= value
<< 4; /* 6 - 2. */
18457 case 7: /* Byte load/store. */
18459 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18460 _("invalid offset, value too big (0x%08lX)"),
18462 newval
|= value
<< 6;
18465 case 8: /* Halfword load/store. */
18467 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18468 _("invalid offset, value too big (0x%08lX)"),
18470 newval
|= value
<< 5; /* 6 - 1. */
18474 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18475 "Unable to process relocation for thumb opcode: %lx",
18476 (unsigned long) newval
);
18479 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18482 case BFD_RELOC_ARM_THUMB_ADD
:
18483 /* This is a complicated relocation, since we use it for all of
18484 the following immediate relocations:
18488 9bit ADD/SUB SP word-aligned
18489 10bit ADD PC/SP word-aligned
18491 The type of instruction being processed is encoded in the
18498 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18500 int rd
= (newval
>> 4) & 0xf;
18501 int rs
= newval
& 0xf;
18502 int subtract
= !!(newval
& 0x8000);
18504 /* Check for HI regs, only very restricted cases allowed:
18505 Adjusting SP, and using PC or SP to get an address. */
18506 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
18507 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
18508 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18509 _("invalid Hi register with immediate"));
18511 /* If value is negative, choose the opposite instruction. */
18515 subtract
= !subtract
;
18517 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18518 _("immediate value out of range"));
18523 if (value
& ~0x1fc)
18524 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18525 _("invalid immediate for stack address calculation"));
18526 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
18527 newval
|= value
>> 2;
18529 else if (rs
== REG_PC
|| rs
== REG_SP
)
18531 if (subtract
|| value
& ~0x3fc)
18532 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18533 _("invalid immediate for address calculation (value = 0x%08lX)"),
18534 (unsigned long) value
);
18535 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
18537 newval
|= value
>> 2;
18542 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18543 _("immediate value out of range"));
18544 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
18545 newval
|= (rd
<< 8) | value
;
18550 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18551 _("immediate value out of range"));
18552 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
18553 newval
|= rd
| (rs
<< 3) | (value
<< 6);
18556 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18559 case BFD_RELOC_ARM_THUMB_IMM
:
18560 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18561 if (value
< 0 || value
> 255)
18562 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18563 _("invalid immediate: %ld is too large"),
18566 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18569 case BFD_RELOC_ARM_THUMB_SHIFT
:
18570 /* 5bit shift value (0..32). LSL cannot take 32. */
18571 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
18572 temp
= newval
& 0xf800;
18573 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
18574 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18575 _("invalid shift value: %ld"), (long) value
);
18576 /* Shifts of zero must be encoded as LSL. */
18578 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
18579 /* Shifts of 32 are encoded as zero. */
18580 else if (value
== 32)
18582 newval
|= value
<< 6;
18583 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18586 case BFD_RELOC_VTABLE_INHERIT
:
18587 case BFD_RELOC_VTABLE_ENTRY
:
18591 case BFD_RELOC_ARM_MOVW
:
18592 case BFD_RELOC_ARM_MOVT
:
18593 case BFD_RELOC_ARM_THUMB_MOVW
:
18594 case BFD_RELOC_ARM_THUMB_MOVT
:
18595 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18597 /* REL format relocations are limited to a 16-bit addend. */
18598 if (!fixP
->fx_done
)
18600 if (value
< -0x1000 || value
> 0xffff)
18601 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18602 _("offset too big"));
18604 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
18605 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18610 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
18611 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18613 newval
= get_thumb32_insn (buf
);
18614 newval
&= 0xfbf08f00;
18615 newval
|= (value
& 0xf000) << 4;
18616 newval
|= (value
& 0x0800) << 15;
18617 newval
|= (value
& 0x0700) << 4;
18618 newval
|= (value
& 0x00ff);
18619 put_thumb32_insn (buf
, newval
);
18623 newval
= md_chars_to_number (buf
, 4);
18624 newval
&= 0xfff0f000;
18625 newval
|= value
& 0x0fff;
18626 newval
|= (value
& 0xf000) << 4;
18627 md_number_to_chars (buf
, newval
, 4);
18632 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
18633 case BFD_RELOC_ARM_ALU_PC_G0
:
18634 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
18635 case BFD_RELOC_ARM_ALU_PC_G1
:
18636 case BFD_RELOC_ARM_ALU_PC_G2
:
18637 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
18638 case BFD_RELOC_ARM_ALU_SB_G0
:
18639 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
18640 case BFD_RELOC_ARM_ALU_SB_G1
:
18641 case BFD_RELOC_ARM_ALU_SB_G2
:
18642 assert (!fixP
->fx_done
);
18643 if (!seg
->use_rela_p
)
18646 bfd_vma encoded_addend
;
18647 bfd_vma addend_abs
= abs (value
);
18649 /* Check that the absolute value of the addend can be
18650 expressed as an 8-bit constant plus a rotation. */
18651 encoded_addend
= encode_arm_immediate (addend_abs
);
18652 if (encoded_addend
== (unsigned int) FAIL
)
18653 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18654 _("the offset 0x%08lX is not representable"),
18657 /* Extract the instruction. */
18658 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18660 /* If the addend is positive, use an ADD instruction.
18661 Otherwise use a SUB. Take care not to destroy the S bit. */
18662 insn
&= 0xff1fffff;
18668 /* Place the encoded addend into the first 12 bits of the
18670 insn
&= 0xfffff000;
18671 insn
|= encoded_addend
;
18673 /* Update the instruction. */
18674 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18678 case BFD_RELOC_ARM_LDR_PC_G0
:
18679 case BFD_RELOC_ARM_LDR_PC_G1
:
18680 case BFD_RELOC_ARM_LDR_PC_G2
:
18681 case BFD_RELOC_ARM_LDR_SB_G0
:
18682 case BFD_RELOC_ARM_LDR_SB_G1
:
18683 case BFD_RELOC_ARM_LDR_SB_G2
:
18684 assert (!fixP
->fx_done
);
18685 if (!seg
->use_rela_p
)
18688 bfd_vma addend_abs
= abs (value
);
18690 /* Check that the absolute value of the addend can be
18691 encoded in 12 bits. */
18692 if (addend_abs
>= 0x1000)
18693 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18694 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
18697 /* Extract the instruction. */
18698 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18700 /* If the addend is negative, clear bit 23 of the instruction.
18701 Otherwise set it. */
18703 insn
&= ~(1 << 23);
18707 /* Place the absolute value of the addend into the first 12 bits
18708 of the instruction. */
18709 insn
&= 0xfffff000;
18710 insn
|= addend_abs
;
18712 /* Update the instruction. */
18713 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18717 case BFD_RELOC_ARM_LDRS_PC_G0
:
18718 case BFD_RELOC_ARM_LDRS_PC_G1
:
18719 case BFD_RELOC_ARM_LDRS_PC_G2
:
18720 case BFD_RELOC_ARM_LDRS_SB_G0
:
18721 case BFD_RELOC_ARM_LDRS_SB_G1
:
18722 case BFD_RELOC_ARM_LDRS_SB_G2
:
18723 assert (!fixP
->fx_done
);
18724 if (!seg
->use_rela_p
)
18727 bfd_vma addend_abs
= abs (value
);
18729 /* Check that the absolute value of the addend can be
18730 encoded in 8 bits. */
18731 if (addend_abs
>= 0x100)
18732 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18733 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
18736 /* Extract the instruction. */
18737 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18739 /* If the addend is negative, clear bit 23 of the instruction.
18740 Otherwise set it. */
18742 insn
&= ~(1 << 23);
18746 /* Place the first four bits of the absolute value of the addend
18747 into the first 4 bits of the instruction, and the remaining
18748 four into bits 8 .. 11. */
18749 insn
&= 0xfffff0f0;
18750 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
18752 /* Update the instruction. */
18753 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18757 case BFD_RELOC_ARM_LDC_PC_G0
:
18758 case BFD_RELOC_ARM_LDC_PC_G1
:
18759 case BFD_RELOC_ARM_LDC_PC_G2
:
18760 case BFD_RELOC_ARM_LDC_SB_G0
:
18761 case BFD_RELOC_ARM_LDC_SB_G1
:
18762 case BFD_RELOC_ARM_LDC_SB_G2
:
18763 assert (!fixP
->fx_done
);
18764 if (!seg
->use_rela_p
)
18767 bfd_vma addend_abs
= abs (value
);
18769 /* Check that the absolute value of the addend is a multiple of
18770 four and, when divided by four, fits in 8 bits. */
18771 if (addend_abs
& 0x3)
18772 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18773 _("bad offset 0x%08lX (must be word-aligned)"),
18776 if ((addend_abs
>> 2) > 0xff)
18777 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18778 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
18781 /* Extract the instruction. */
18782 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18784 /* If the addend is negative, clear bit 23 of the instruction.
18785 Otherwise set it. */
18787 insn
&= ~(1 << 23);
18791 /* Place the addend (divided by four) into the first eight
18792 bits of the instruction. */
18793 insn
&= 0xfffffff0;
18794 insn
|= addend_abs
>> 2;
18796 /* Update the instruction. */
18797 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18801 case BFD_RELOC_UNUSED
:
18803 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18804 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
18808 /* Translate internal representation of relocation info to BFD target
18812 tc_gen_reloc (asection
*section
, fixS
*fixp
)
18815 bfd_reloc_code_real_type code
;
18817 reloc
= xmalloc (sizeof (arelent
));
18819 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
18820 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18821 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18823 if (fixp
->fx_pcrel
)
18825 if (section
->use_rela_p
)
18826 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
18828 fixp
->fx_offset
= reloc
->address
;
18830 reloc
->addend
= fixp
->fx_offset
;
18832 switch (fixp
->fx_r_type
)
18835 if (fixp
->fx_pcrel
)
18837 code
= BFD_RELOC_8_PCREL
;
18842 if (fixp
->fx_pcrel
)
18844 code
= BFD_RELOC_16_PCREL
;
18849 if (fixp
->fx_pcrel
)
18851 code
= BFD_RELOC_32_PCREL
;
18855 case BFD_RELOC_ARM_MOVW
:
18856 if (fixp
->fx_pcrel
)
18858 code
= BFD_RELOC_ARM_MOVW_PCREL
;
18862 case BFD_RELOC_ARM_MOVT
:
18863 if (fixp
->fx_pcrel
)
18865 code
= BFD_RELOC_ARM_MOVT_PCREL
;
18869 case BFD_RELOC_ARM_THUMB_MOVW
:
18870 if (fixp
->fx_pcrel
)
18872 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
18876 case BFD_RELOC_ARM_THUMB_MOVT
:
18877 if (fixp
->fx_pcrel
)
18879 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
18883 case BFD_RELOC_NONE
:
18884 case BFD_RELOC_ARM_PCREL_BRANCH
:
18885 case BFD_RELOC_ARM_PCREL_BLX
:
18886 case BFD_RELOC_RVA
:
18887 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
18888 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
18889 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
18890 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
18891 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
18892 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
18893 case BFD_RELOC_THUMB_PCREL_BLX
:
18894 case BFD_RELOC_VTABLE_ENTRY
:
18895 case BFD_RELOC_VTABLE_INHERIT
:
18897 case BFD_RELOC_32_SECREL
:
18899 code
= fixp
->fx_r_type
;
18902 case BFD_RELOC_ARM_LITERAL
:
18903 case BFD_RELOC_ARM_HWLITERAL
:
18904 /* If this is called then the a literal has
18905 been referenced across a section boundary. */
18906 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18907 _("literal referenced across section boundary"));
18911 case BFD_RELOC_ARM_GOT32
:
18912 case BFD_RELOC_ARM_GOTOFF
:
18913 case BFD_RELOC_ARM_PLT32
:
18914 case BFD_RELOC_ARM_TARGET1
:
18915 case BFD_RELOC_ARM_ROSEGREL32
:
18916 case BFD_RELOC_ARM_SBREL32
:
18917 case BFD_RELOC_ARM_PREL31
:
18918 case BFD_RELOC_ARM_TARGET2
:
18919 case BFD_RELOC_ARM_TLS_LE32
:
18920 case BFD_RELOC_ARM_TLS_LDO32
:
18921 case BFD_RELOC_ARM_PCREL_CALL
:
18922 case BFD_RELOC_ARM_PCREL_JUMP
:
18923 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
18924 case BFD_RELOC_ARM_ALU_PC_G0
:
18925 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
18926 case BFD_RELOC_ARM_ALU_PC_G1
:
18927 case BFD_RELOC_ARM_ALU_PC_G2
:
18928 case BFD_RELOC_ARM_LDR_PC_G0
:
18929 case BFD_RELOC_ARM_LDR_PC_G1
:
18930 case BFD_RELOC_ARM_LDR_PC_G2
:
18931 case BFD_RELOC_ARM_LDRS_PC_G0
:
18932 case BFD_RELOC_ARM_LDRS_PC_G1
:
18933 case BFD_RELOC_ARM_LDRS_PC_G2
:
18934 case BFD_RELOC_ARM_LDC_PC_G0
:
18935 case BFD_RELOC_ARM_LDC_PC_G1
:
18936 case BFD_RELOC_ARM_LDC_PC_G2
:
18937 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
18938 case BFD_RELOC_ARM_ALU_SB_G0
:
18939 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
18940 case BFD_RELOC_ARM_ALU_SB_G1
:
18941 case BFD_RELOC_ARM_ALU_SB_G2
:
18942 case BFD_RELOC_ARM_LDR_SB_G0
:
18943 case BFD_RELOC_ARM_LDR_SB_G1
:
18944 case BFD_RELOC_ARM_LDR_SB_G2
:
18945 case BFD_RELOC_ARM_LDRS_SB_G0
:
18946 case BFD_RELOC_ARM_LDRS_SB_G1
:
18947 case BFD_RELOC_ARM_LDRS_SB_G2
:
18948 case BFD_RELOC_ARM_LDC_SB_G0
:
18949 case BFD_RELOC_ARM_LDC_SB_G1
:
18950 case BFD_RELOC_ARM_LDC_SB_G2
:
18951 code
= fixp
->fx_r_type
;
18954 case BFD_RELOC_ARM_TLS_GD32
:
18955 case BFD_RELOC_ARM_TLS_IE32
:
18956 case BFD_RELOC_ARM_TLS_LDM32
:
18957 /* BFD will include the symbol's address in the addend.
18958 But we don't want that, so subtract it out again here. */
18959 if (!S_IS_COMMON (fixp
->fx_addsy
))
18960 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
18961 code
= fixp
->fx_r_type
;
18965 case BFD_RELOC_ARM_IMMEDIATE
:
18966 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18967 _("internal relocation (type: IMMEDIATE) not fixed up"));
18970 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
18971 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18972 _("ADRL used for a symbol not defined in the same file"));
18975 case BFD_RELOC_ARM_OFFSET_IMM
:
18976 if (section
->use_rela_p
)
18978 code
= fixp
->fx_r_type
;
18982 if (fixp
->fx_addsy
!= NULL
18983 && !S_IS_DEFINED (fixp
->fx_addsy
)
18984 && S_IS_LOCAL (fixp
->fx_addsy
))
18986 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18987 _("undefined local label `%s'"),
18988 S_GET_NAME (fixp
->fx_addsy
));
18992 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18993 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
19000 switch (fixp
->fx_r_type
)
19002 case BFD_RELOC_NONE
: type
= "NONE"; break;
19003 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
19004 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
19005 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
19006 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
19007 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
19008 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
19009 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
19010 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
19011 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
19012 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
19013 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
19014 default: type
= _("<unknown>"); break;
19016 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19017 _("cannot represent %s relocation in this object file format"),
19024 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
19026 && fixp
->fx_addsy
== GOT_symbol
)
19028 code
= BFD_RELOC_ARM_GOTPC
;
19029 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
19033 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
19035 if (reloc
->howto
== NULL
)
19037 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19038 _("cannot represent %s relocation in this object file format"),
19039 bfd_get_reloc_code_name (code
));
19043 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
19044 vtable entry to be used in the relocation's section offset. */
19045 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
19046 reloc
->address
= fixp
->fx_offset
;
19051 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
19054 cons_fix_new_arm (fragS
* frag
,
19059 bfd_reloc_code_real_type type
;
19063 FIXME: @@ Should look at CPU word size. */
19067 type
= BFD_RELOC_8
;
19070 type
= BFD_RELOC_16
;
19074 type
= BFD_RELOC_32
;
19077 type
= BFD_RELOC_64
;
19082 if (exp
->X_op
== O_secrel
)
19084 exp
->X_op
= O_symbol
;
19085 type
= BFD_RELOC_32_SECREL
;
19089 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
19092 #if defined OBJ_COFF || defined OBJ_ELF
19094 arm_validate_fix (fixS
* fixP
)
19096 /* If the destination of the branch is a defined symbol which does not have
19097 the THUMB_FUNC attribute, then we must be calling a function which has
19098 the (interfacearm) attribute. We look for the Thumb entry point to that
19099 function and change the branch to refer to that function instead. */
19100 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
19101 && fixP
->fx_addsy
!= NULL
19102 && S_IS_DEFINED (fixP
->fx_addsy
)
19103 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
19105 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
19111 arm_force_relocation (struct fix
* fixp
)
19113 #if defined (OBJ_COFF) && defined (TE_PE)
19114 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
19118 /* Resolve these relocations even if the symbol is extern or weak. */
19119 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
19120 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
19121 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
19122 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
19123 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
19124 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
19125 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
19128 /* Always leave these relocations for the linker. */
19129 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
19130 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
19131 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
19134 /* Always generate relocations against function symbols. */
19135 if (fixp
->fx_r_type
== BFD_RELOC_32
19137 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
19140 return generic_force_reloc (fixp
);
19143 #if defined (OBJ_ELF) || defined (OBJ_COFF)
19144 /* Relocations against function names must be left unadjusted,
19145 so that the linker can use this information to generate interworking
19146 stubs. The MIPS version of this function
19147 also prevents relocations that are mips-16 specific, but I do not
19148 know why it does this.
19151 There is one other problem that ought to be addressed here, but
19152 which currently is not: Taking the address of a label (rather
19153 than a function) and then later jumping to that address. Such
19154 addresses also ought to have their bottom bit set (assuming that
19155 they reside in Thumb code), but at the moment they will not. */
19158 arm_fix_adjustable (fixS
* fixP
)
19160 if (fixP
->fx_addsy
== NULL
)
19163 /* Preserve relocations against symbols with function type. */
19164 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
19167 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
19168 && fixP
->fx_subsy
== NULL
)
19171 /* We need the symbol name for the VTABLE entries. */
19172 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
19173 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
19176 /* Don't allow symbols to be discarded on GOT related relocs. */
19177 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
19178 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
19179 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
19180 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
19181 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
19182 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
19183 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
19184 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
19185 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
19188 /* Similarly for group relocations. */
19189 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
19190 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
19191 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
19196 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
19201 elf32_arm_target_format (void)
19204 return (target_big_endian
19205 ? "elf32-bigarm-symbian"
19206 : "elf32-littlearm-symbian");
19207 #elif defined (TE_VXWORKS)
19208 return (target_big_endian
19209 ? "elf32-bigarm-vxworks"
19210 : "elf32-littlearm-vxworks");
19212 if (target_big_endian
)
19213 return "elf32-bigarm";
19215 return "elf32-littlearm";
19220 armelf_frob_symbol (symbolS
* symp
,
19223 elf_frob_symbol (symp
, puntp
);
19227 /* MD interface: Finalization. */
19229 /* A good place to do this, although this was probably not intended
19230 for this kind of use. We need to dump the literal pool before
19231 references are made to a null symbol pointer. */
19236 literal_pool
* pool
;
19238 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
19240 /* Put it at the end of the relevent section. */
19241 subseg_set (pool
->section
, pool
->sub_section
);
19243 arm_elf_change_section ();
19249 /* Adjust the symbol table. This marks Thumb symbols as distinct from
19253 arm_adjust_symtab (void)
19258 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
19260 if (ARM_IS_THUMB (sym
))
19262 if (THUMB_IS_FUNC (sym
))
19264 /* Mark the symbol as a Thumb function. */
19265 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
19266 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
19267 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
19269 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
19270 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
19272 as_bad (_("%s: unexpected function type: %d"),
19273 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
19275 else switch (S_GET_STORAGE_CLASS (sym
))
19278 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
19281 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
19284 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
19292 if (ARM_IS_INTERWORK (sym
))
19293 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
19300 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
19302 if (ARM_IS_THUMB (sym
))
19304 elf_symbol_type
* elf_sym
;
19306 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
19307 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
19309 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
19310 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
19312 /* If it's a .thumb_func, declare it as so,
19313 otherwise tag label as .code 16. */
19314 if (THUMB_IS_FUNC (sym
))
19315 elf_sym
->internal_elf_sym
.st_info
=
19316 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
19317 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
19318 elf_sym
->internal_elf_sym
.st_info
=
19319 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
19326 /* MD interface: Initialization. */
19329 set_constant_flonums (void)
19333 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
19334 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
19338 /* Auto-select Thumb mode if it's the only available instruction set for the
19339 given architecture. */
19342 autoselect_thumb_from_cpu_variant (void)
19344 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
19345 opcode_select (16);
19354 if ( (arm_ops_hsh
= hash_new ()) == NULL
19355 || (arm_cond_hsh
= hash_new ()) == NULL
19356 || (arm_shift_hsh
= hash_new ()) == NULL
19357 || (arm_psr_hsh
= hash_new ()) == NULL
19358 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
19359 || (arm_reg_hsh
= hash_new ()) == NULL
19360 || (arm_reloc_hsh
= hash_new ()) == NULL
19361 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
19362 as_fatal (_("virtual memory exhausted"));
19364 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
19365 hash_insert (arm_ops_hsh
, insns
[i
].template, (PTR
) (insns
+ i
));
19366 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
19367 hash_insert (arm_cond_hsh
, conds
[i
].template, (PTR
) (conds
+ i
));
19368 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
19369 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (PTR
) (shift_names
+ i
));
19370 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
19371 hash_insert (arm_psr_hsh
, psrs
[i
].template, (PTR
) (psrs
+ i
));
19372 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
19373 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template, (PTR
) (v7m_psrs
+ i
));
19374 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
19375 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (PTR
) (reg_names
+ i
));
19377 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
19379 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template,
19380 (PTR
) (barrier_opt_names
+ i
));
19382 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
19383 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (PTR
) (reloc_names
+ i
));
19386 set_constant_flonums ();
19388 /* Set the cpu variant based on the command-line options. We prefer
19389 -mcpu= over -march= if both are set (as for GCC); and we prefer
19390 -mfpu= over any other way of setting the floating point unit.
19391 Use of legacy options with new options are faulted. */
19394 if (mcpu_cpu_opt
|| march_cpu_opt
)
19395 as_bad (_("use of old and new-style options to set CPU type"));
19397 mcpu_cpu_opt
= legacy_cpu
;
19399 else if (!mcpu_cpu_opt
)
19400 mcpu_cpu_opt
= march_cpu_opt
;
19405 as_bad (_("use of old and new-style options to set FPU type"));
19407 mfpu_opt
= legacy_fpu
;
19409 else if (!mfpu_opt
)
19411 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
19412 /* Some environments specify a default FPU. If they don't, infer it
19413 from the processor. */
19415 mfpu_opt
= mcpu_fpu_opt
;
19417 mfpu_opt
= march_fpu_opt
;
19419 mfpu_opt
= &fpu_default
;
19425 if (mcpu_cpu_opt
!= NULL
)
19426 mfpu_opt
= &fpu_default
;
19427 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
19428 mfpu_opt
= &fpu_arch_vfp_v2
;
19430 mfpu_opt
= &fpu_arch_fpa
;
19436 mcpu_cpu_opt
= &cpu_default
;
19437 selected_cpu
= cpu_default
;
19441 selected_cpu
= *mcpu_cpu_opt
;
19443 mcpu_cpu_opt
= &arm_arch_any
;
19446 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
19448 autoselect_thumb_from_cpu_variant ();
19450 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
19452 #if defined OBJ_COFF || defined OBJ_ELF
19454 unsigned int flags
= 0;
19456 #if defined OBJ_ELF
19457 flags
= meabi_flags
;
19459 switch (meabi_flags
)
19461 case EF_ARM_EABI_UNKNOWN
:
19463 /* Set the flags in the private structure. */
19464 if (uses_apcs_26
) flags
|= F_APCS26
;
19465 if (support_interwork
) flags
|= F_INTERWORK
;
19466 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
19467 if (pic_code
) flags
|= F_PIC
;
19468 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
19469 flags
|= F_SOFT_FLOAT
;
19471 switch (mfloat_abi_opt
)
19473 case ARM_FLOAT_ABI_SOFT
:
19474 case ARM_FLOAT_ABI_SOFTFP
:
19475 flags
|= F_SOFT_FLOAT
;
19478 case ARM_FLOAT_ABI_HARD
:
19479 if (flags
& F_SOFT_FLOAT
)
19480 as_bad (_("hard-float conflicts with specified fpu"));
19484 /* Using pure-endian doubles (even if soft-float). */
19485 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
19486 flags
|= F_VFP_FLOAT
;
19488 #if defined OBJ_ELF
19489 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
19490 flags
|= EF_ARM_MAVERICK_FLOAT
;
19493 case EF_ARM_EABI_VER4
:
19494 case EF_ARM_EABI_VER5
:
19495 /* No additional flags to set. */
19502 bfd_set_private_flags (stdoutput
, flags
);
19504 /* We have run out flags in the COFF header to encode the
19505 status of ATPCS support, so instead we create a dummy,
19506 empty, debug section called .arm.atpcs. */
19511 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
19515 bfd_set_section_flags
19516 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
19517 bfd_set_section_size (stdoutput
, sec
, 0);
19518 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
19524 /* Record the CPU type as well. */
19525 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
19526 mach
= bfd_mach_arm_iWMMXt2
;
19527 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
19528 mach
= bfd_mach_arm_iWMMXt
;
19529 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
19530 mach
= bfd_mach_arm_XScale
;
19531 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
19532 mach
= bfd_mach_arm_ep9312
;
19533 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
19534 mach
= bfd_mach_arm_5TE
;
19535 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
19537 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19538 mach
= bfd_mach_arm_5T
;
19540 mach
= bfd_mach_arm_5
;
19542 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
19544 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19545 mach
= bfd_mach_arm_4T
;
19547 mach
= bfd_mach_arm_4
;
19549 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
19550 mach
= bfd_mach_arm_3M
;
19551 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
19552 mach
= bfd_mach_arm_3
;
19553 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
19554 mach
= bfd_mach_arm_2a
;
19555 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
19556 mach
= bfd_mach_arm_2
;
19558 mach
= bfd_mach_arm_unknown
;
19560 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
19563 /* Command line processing. */
19566 Invocation line includes a switch not recognized by the base assembler.
19567 See if it's a processor-specific option.
19569 This routine is somewhat complicated by the need for backwards
19570 compatibility (since older releases of gcc can't be changed).
19571 The new options try to make the interface as compatible as
19574 New options (supported) are:
19576 -mcpu=<cpu name> Assemble for selected processor
19577 -march=<architecture name> Assemble for selected architecture
19578 -mfpu=<fpu architecture> Assemble for selected FPU.
19579 -EB/-mbig-endian Big-endian
19580 -EL/-mlittle-endian Little-endian
19581 -k Generate PIC code
19582 -mthumb Start in Thumb mode
19583 -mthumb-interwork Code supports ARM/Thumb interworking
19585 For now we will also provide support for:
19587 -mapcs-32 32-bit Program counter
19588 -mapcs-26 26-bit Program counter
19589 -macps-float Floats passed in FP registers
19590 -mapcs-reentrant Reentrant code
19592 (sometime these will probably be replaced with -mapcs=<list of options>
19593 and -matpcs=<list of options>)
19595 The remaining options are only supported for back-wards compatibility.
19596 Cpu variants, the arm part is optional:
19597 -m[arm]1 Currently not supported.
19598 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
19599 -m[arm]3 Arm 3 processor
19600 -m[arm]6[xx], Arm 6 processors
19601 -m[arm]7[xx][t][[d]m] Arm 7 processors
19602 -m[arm]8[10] Arm 8 processors
19603 -m[arm]9[20][tdmi] Arm 9 processors
19604 -mstrongarm[110[0]] StrongARM processors
19605 -mxscale XScale processors
19606 -m[arm]v[2345[t[e]]] Arm architectures
19607 -mall All (except the ARM1)
19609 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
19610 -mfpe-old (No float load/store multiples)
19611 -mvfpxd VFP Single precision
19613 -mno-fpu Disable all floating point instructions
19615 The following CPU names are recognized:
19616 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
19617 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
19618 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
19619 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
19620 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
19621 arm10t arm10e, arm1020t, arm1020e, arm10200e,
19622 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
19626 const char * md_shortopts
= "m:k";
19628 #ifdef ARM_BI_ENDIAN
19629 #define OPTION_EB (OPTION_MD_BASE + 0)
19630 #define OPTION_EL (OPTION_MD_BASE + 1)
19632 #if TARGET_BYTES_BIG_ENDIAN
19633 #define OPTION_EB (OPTION_MD_BASE + 0)
19635 #define OPTION_EL (OPTION_MD_BASE + 1)
19639 struct option md_longopts
[] =
19642 {"EB", no_argument
, NULL
, OPTION_EB
},
19645 {"EL", no_argument
, NULL
, OPTION_EL
},
19647 {NULL
, no_argument
, NULL
, 0}
19650 size_t md_longopts_size
= sizeof (md_longopts
);
19652 struct arm_option_table
19654 char *option
; /* Option name to match. */
19655 char *help
; /* Help information. */
19656 int *var
; /* Variable to change. */
19657 int value
; /* What to change it to. */
19658 char *deprecated
; /* If non-null, print this message. */
19661 struct arm_option_table arm_opts
[] =
19663 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
19664 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
19665 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
19666 &support_interwork
, 1, NULL
},
19667 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
19668 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
19669 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
19671 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
19672 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
19673 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
19674 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
19677 /* These are recognized by the assembler, but have no affect on code. */
19678 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
19679 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
19680 {NULL
, NULL
, NULL
, 0, NULL
}
19683 struct arm_legacy_option_table
19685 char *option
; /* Option name to match. */
19686 const arm_feature_set
**var
; /* Variable to change. */
19687 const arm_feature_set value
; /* What to change it to. */
19688 char *deprecated
; /* If non-null, print this message. */
19691 const struct arm_legacy_option_table arm_legacy_opts
[] =
19693 /* DON'T add any new processors to this list -- we want the whole list
19694 to go away... Add them to the processors table instead. */
19695 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19696 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19697 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19698 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19699 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19700 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19701 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19702 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19703 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19704 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19705 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19706 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19707 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19708 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19709 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19710 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19711 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19712 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19713 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19714 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19715 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19716 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19717 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19718 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19719 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19720 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19721 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19722 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19723 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19724 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19725 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19726 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19727 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19728 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19729 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19730 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19731 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19732 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19733 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19734 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19735 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19736 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19737 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19738 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19739 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19740 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19741 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19742 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19743 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19744 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19745 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19746 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19747 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19748 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19749 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19750 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19751 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19752 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19753 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19754 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19755 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19756 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19757 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19758 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19759 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19760 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19761 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19762 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19763 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
19764 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
19765 N_("use -mcpu=strongarm110")},
19766 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
19767 N_("use -mcpu=strongarm1100")},
19768 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
19769 N_("use -mcpu=strongarm1110")},
19770 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
19771 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
19772 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
19774 /* Architecture variants -- don't add any more to this list either. */
19775 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19776 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19777 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19778 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19779 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19780 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19781 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19782 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19783 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19784 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19785 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
19786 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
19787 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
19788 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
19789 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
19790 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
19791 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
19792 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
19794 /* Floating point variants -- don't add any more to this list either. */
19795 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
19796 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
19797 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
19798 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
19799 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
19801 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
19804 struct arm_cpu_option_table
19807 const arm_feature_set value
;
19808 /* For some CPUs we assume an FPU unless the user explicitly sets
19810 const arm_feature_set default_fpu
;
19811 /* The canonical name of the CPU, or NULL to use NAME converted to upper
19813 const char *canonical_name
;
19816 /* This list should, at a minimum, contain all the cpu names
19817 recognized by GCC. */
19818 static const struct arm_cpu_option_table arm_cpus
[] =
19820 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
19821 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
19822 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
19823 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
19824 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
19825 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19826 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19827 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19828 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19829 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19830 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19831 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
19832 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19833 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
19834 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19835 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
19836 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19837 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19838 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19839 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19840 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19841 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19842 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19843 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19844 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19845 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19846 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19847 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19848 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19849 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19850 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19851 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19852 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19853 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19854 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19855 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19856 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19857 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19858 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19859 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
19860 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19861 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19862 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19863 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19864 /* For V5 or later processors we default to using VFP; but the user
19865 should really set the FPU type explicitly. */
19866 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
19867 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19868 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
19869 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
19870 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
19871 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
19872 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
19873 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19874 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
19875 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
19876 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19877 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19878 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
19879 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
19880 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19881 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
19882 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
19883 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19884 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19885 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
19886 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
19887 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
19888 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
19889 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
19890 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
19891 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
19892 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
19893 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
19894 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
19895 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
19896 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
19897 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE(0, FPU_VFP_V3
19898 | FPU_NEON_EXT_V1
),
19900 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
19901 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
19902 /* ??? XSCALE is really an architecture. */
19903 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
19904 /* ??? iwmmxt is not a processor. */
19905 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
19906 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
19907 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
19909 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
19910 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
19913 struct arm_arch_option_table
19916 const arm_feature_set value
;
19917 const arm_feature_set default_fpu
;
19920 /* This list should, at a minimum, contain all the architecture names
19921 recognized by GCC. */
19922 static const struct arm_arch_option_table arm_archs
[] =
19924 {"all", ARM_ANY
, FPU_ARCH_FPA
},
19925 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
19926 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
19927 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
19928 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
19929 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
19930 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
19931 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
19932 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
19933 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
19934 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
19935 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
19936 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
19937 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
19938 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
19939 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
19940 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
19941 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
19942 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
19943 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
19944 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
19945 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
19946 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
19947 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
19948 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
19949 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
19950 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
19951 /* The official spelling of the ARMv7 profile variants is the dashed form.
19952 Accept the non-dashed form for compatibility with old toolchains. */
19953 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
19954 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
19955 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
19956 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
19957 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
19958 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
19959 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
19960 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
19961 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
19962 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
19965 /* ISA extensions in the co-processor space. */
19966 struct arm_option_cpu_value_table
19969 const arm_feature_set value
;
19972 static const struct arm_option_cpu_value_table arm_extensions
[] =
19974 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
19975 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
19976 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
19977 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
19978 {NULL
, ARM_ARCH_NONE
}
19981 /* This list should, at a minimum, contain all the fpu names
19982 recognized by GCC. */
19983 static const struct arm_option_cpu_value_table arm_fpus
[] =
19985 {"softfpa", FPU_NONE
},
19986 {"fpe", FPU_ARCH_FPE
},
19987 {"fpe2", FPU_ARCH_FPE
},
19988 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
19989 {"fpa", FPU_ARCH_FPA
},
19990 {"fpa10", FPU_ARCH_FPA
},
19991 {"fpa11", FPU_ARCH_FPA
},
19992 {"arm7500fe", FPU_ARCH_FPA
},
19993 {"softvfp", FPU_ARCH_VFP
},
19994 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
19995 {"vfp", FPU_ARCH_VFP_V2
},
19996 {"vfp9", FPU_ARCH_VFP_V2
},
19997 {"vfp3", FPU_ARCH_VFP_V3
},
19998 {"vfp10", FPU_ARCH_VFP_V2
},
19999 {"vfp10-r0", FPU_ARCH_VFP_V1
},
20000 {"vfpxd", FPU_ARCH_VFP_V1xD
},
20001 {"arm1020t", FPU_ARCH_VFP_V1
},
20002 {"arm1020e", FPU_ARCH_VFP_V2
},
20003 {"arm1136jfs", FPU_ARCH_VFP_V2
},
20004 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
20005 {"maverick", FPU_ARCH_MAVERICK
},
20006 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
20007 {NULL
, ARM_ARCH_NONE
}
20010 struct arm_option_value_table
20016 static const struct arm_option_value_table arm_float_abis
[] =
20018 {"hard", ARM_FLOAT_ABI_HARD
},
20019 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
20020 {"soft", ARM_FLOAT_ABI_SOFT
},
20025 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
20026 static const struct arm_option_value_table arm_eabis
[] =
20028 {"gnu", EF_ARM_EABI_UNKNOWN
},
20029 {"4", EF_ARM_EABI_VER4
},
20030 {"5", EF_ARM_EABI_VER5
},
20035 struct arm_long_option_table
20037 char * option
; /* Substring to match. */
20038 char * help
; /* Help information. */
20039 int (* func
) (char * subopt
); /* Function to decode sub-option. */
20040 char * deprecated
; /* If non-null, print this message. */
20044 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
20046 arm_feature_set
*ext_set
= xmalloc (sizeof (arm_feature_set
));
20048 /* Copy the feature set, so that we can modify it. */
20049 *ext_set
= **opt_p
;
20052 while (str
!= NULL
&& *str
!= 0)
20054 const struct arm_option_cpu_value_table
* opt
;
20060 as_bad (_("invalid architectural extension"));
20065 ext
= strchr (str
, '+');
20068 optlen
= ext
- str
;
20070 optlen
= strlen (str
);
20074 as_bad (_("missing architectural extension"));
20078 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
20079 if (strncmp (opt
->name
, str
, optlen
) == 0)
20081 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
20085 if (opt
->name
== NULL
)
20087 as_bad (_("unknown architectural extnsion `%s'"), str
);
20098 arm_parse_cpu (char * str
)
20100 const struct arm_cpu_option_table
* opt
;
20101 char * ext
= strchr (str
, '+');
20105 optlen
= ext
- str
;
20107 optlen
= strlen (str
);
20111 as_bad (_("missing cpu name `%s'"), str
);
20115 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
20116 if (strncmp (opt
->name
, str
, optlen
) == 0)
20118 mcpu_cpu_opt
= &opt
->value
;
20119 mcpu_fpu_opt
= &opt
->default_fpu
;
20120 if (opt
->canonical_name
)
20121 strcpy(selected_cpu_name
, opt
->canonical_name
);
20125 for (i
= 0; i
< optlen
; i
++)
20126 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20127 selected_cpu_name
[i
] = 0;
20131 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
20136 as_bad (_("unknown cpu `%s'"), str
);
20141 arm_parse_arch (char * str
)
20143 const struct arm_arch_option_table
*opt
;
20144 char *ext
= strchr (str
, '+');
20148 optlen
= ext
- str
;
20150 optlen
= strlen (str
);
20154 as_bad (_("missing architecture name `%s'"), str
);
20158 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
20159 if (streq (opt
->name
, str
))
20161 march_cpu_opt
= &opt
->value
;
20162 march_fpu_opt
= &opt
->default_fpu
;
20163 strcpy(selected_cpu_name
, opt
->name
);
20166 return arm_parse_extension (ext
, &march_cpu_opt
);
20171 as_bad (_("unknown architecture `%s'\n"), str
);
20176 arm_parse_fpu (char * str
)
20178 const struct arm_option_cpu_value_table
* opt
;
20180 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
20181 if (streq (opt
->name
, str
))
20183 mfpu_opt
= &opt
->value
;
20187 as_bad (_("unknown floating point format `%s'\n"), str
);
20192 arm_parse_float_abi (char * str
)
20194 const struct arm_option_value_table
* opt
;
20196 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
20197 if (streq (opt
->name
, str
))
20199 mfloat_abi_opt
= opt
->value
;
20203 as_bad (_("unknown floating point abi `%s'\n"), str
);
20209 arm_parse_eabi (char * str
)
20211 const struct arm_option_value_table
*opt
;
20213 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
20214 if (streq (opt
->name
, str
))
20216 meabi_flags
= opt
->value
;
20219 as_bad (_("unknown EABI `%s'\n"), str
);
20224 struct arm_long_option_table arm_long_opts
[] =
20226 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
20227 arm_parse_cpu
, NULL
},
20228 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
20229 arm_parse_arch
, NULL
},
20230 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
20231 arm_parse_fpu
, NULL
},
20232 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
20233 arm_parse_float_abi
, NULL
},
20235 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
20236 arm_parse_eabi
, NULL
},
20238 {NULL
, NULL
, 0, NULL
}
20242 md_parse_option (int c
, char * arg
)
20244 struct arm_option_table
*opt
;
20245 const struct arm_legacy_option_table
*fopt
;
20246 struct arm_long_option_table
*lopt
;
20252 target_big_endian
= 1;
20258 target_big_endian
= 0;
20263 /* Listing option. Just ignore these, we don't support additional
20268 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
20270 if (c
== opt
->option
[0]
20271 && ((arg
== NULL
&& opt
->option
[1] == 0)
20272 || streq (arg
, opt
->option
+ 1)))
20274 #if WARN_DEPRECATED
20275 /* If the option is deprecated, tell the user. */
20276 if (opt
->deprecated
!= NULL
)
20277 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
20278 arg
? arg
: "", _(opt
->deprecated
));
20281 if (opt
->var
!= NULL
)
20282 *opt
->var
= opt
->value
;
20288 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
20290 if (c
== fopt
->option
[0]
20291 && ((arg
== NULL
&& fopt
->option
[1] == 0)
20292 || streq (arg
, fopt
->option
+ 1)))
20294 #if WARN_DEPRECATED
20295 /* If the option is deprecated, tell the user. */
20296 if (fopt
->deprecated
!= NULL
)
20297 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
20298 arg
? arg
: "", _(fopt
->deprecated
));
20301 if (fopt
->var
!= NULL
)
20302 *fopt
->var
= &fopt
->value
;
20308 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
20310 /* These options are expected to have an argument. */
20311 if (c
== lopt
->option
[0]
20313 && strncmp (arg
, lopt
->option
+ 1,
20314 strlen (lopt
->option
+ 1)) == 0)
20316 #if WARN_DEPRECATED
20317 /* If the option is deprecated, tell the user. */
20318 if (lopt
->deprecated
!= NULL
)
20319 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
20320 _(lopt
->deprecated
));
20323 /* Call the sup-option parser. */
20324 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
20335 md_show_usage (FILE * fp
)
20337 struct arm_option_table
*opt
;
20338 struct arm_long_option_table
*lopt
;
20340 fprintf (fp
, _(" ARM-specific assembler options:\n"));
20342 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
20343 if (opt
->help
!= NULL
)
20344 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
20346 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
20347 if (lopt
->help
!= NULL
)
20348 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
20352 -EB assemble code for a big-endian cpu\n"));
20357 -EL assemble code for a little-endian cpu\n"));
20366 arm_feature_set flags
;
20367 } cpu_arch_ver_table
;
20369 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
20370 least features first. */
20371 static const cpu_arch_ver_table cpu_arch_ver
[] =
20376 {4, ARM_ARCH_V5TE
},
20377 {5, ARM_ARCH_V5TEJ
},
20381 {9, ARM_ARCH_V6T2
},
20382 {10, ARM_ARCH_V7A
},
20383 {10, ARM_ARCH_V7R
},
20384 {10, ARM_ARCH_V7M
},
20388 /* Set the public EABI object attributes. */
20390 aeabi_set_public_attributes (void)
20393 arm_feature_set flags
;
20394 arm_feature_set tmp
;
20395 const cpu_arch_ver_table
*p
;
20397 /* Choose the architecture based on the capabilities of the requested cpu
20398 (if any) and/or the instructions actually used. */
20399 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
20400 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
20401 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
20402 /*Allow the user to override the reported architecture. */
20405 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
20406 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
20411 for (p
= cpu_arch_ver
; p
->val
; p
++)
20413 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
20416 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
20420 /* Tag_CPU_name. */
20421 if (selected_cpu_name
[0])
20425 p
= selected_cpu_name
;
20426 if (strncmp(p
, "armv", 4) == 0)
20431 for (i
= 0; p
[i
]; i
++)
20432 p
[i
] = TOUPPER (p
[i
]);
20434 elf32_arm_add_eabi_attr_string (stdoutput
, 5, p
);
20436 /* Tag_CPU_arch. */
20437 elf32_arm_add_eabi_attr_int (stdoutput
, 6, arch
);
20438 /* Tag_CPU_arch_profile. */
20439 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
20440 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'A');
20441 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
20442 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'R');
20443 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
))
20444 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'M');
20445 /* Tag_ARM_ISA_use. */
20446 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_full
))
20447 elf32_arm_add_eabi_attr_int (stdoutput
, 8, 1);
20448 /* Tag_THUMB_ISA_use. */
20449 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_full
))
20450 elf32_arm_add_eabi_attr_int (stdoutput
, 9,
20451 ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
) ? 2 : 1);
20452 /* Tag_VFP_arch. */
20453 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v3
)
20454 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v3
))
20455 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 3);
20456 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v2
)
20457 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v2
))
20458 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 2);
20459 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1
)
20460 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1
)
20461 || ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1xd
)
20462 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1xd
))
20463 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 1);
20464 /* Tag_WMMX_arch. */
20465 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_cext_iwmmxt
)
20466 || ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_cext_iwmmxt
))
20467 elf32_arm_add_eabi_attr_int (stdoutput
, 11, 1);
20468 /* Tag_NEON_arch. */
20469 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_neon_ext_v1
)
20470 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_neon_ext_v1
))
20471 elf32_arm_add_eabi_attr_int (stdoutput
, 12, 1);
20474 /* Add the .ARM.attributes section. */
20483 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
20486 aeabi_set_public_attributes ();
20487 size
= elf32_arm_eabi_attr_size (stdoutput
);
20488 s
= subseg_new (".ARM.attributes", 0);
20489 bfd_set_section_flags (stdoutput
, s
, SEC_READONLY
| SEC_DATA
);
20490 addr
= frag_now_fix ();
20491 p
= frag_more (size
);
20492 elf32_arm_set_eabi_attr_contents (stdoutput
, (bfd_byte
*)p
, size
);
20494 #endif /* OBJ_ELF */
20497 /* Parse a .cpu directive. */
20500 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
20502 const struct arm_cpu_option_table
*opt
;
20506 name
= input_line_pointer
;
20507 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20508 input_line_pointer
++;
20509 saved_char
= *input_line_pointer
;
20510 *input_line_pointer
= 0;
20512 /* Skip the first "all" entry. */
20513 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
20514 if (streq (opt
->name
, name
))
20516 mcpu_cpu_opt
= &opt
->value
;
20517 selected_cpu
= opt
->value
;
20518 if (opt
->canonical_name
)
20519 strcpy(selected_cpu_name
, opt
->canonical_name
);
20523 for (i
= 0; opt
->name
[i
]; i
++)
20524 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20525 selected_cpu_name
[i
] = 0;
20527 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20528 *input_line_pointer
= saved_char
;
20529 demand_empty_rest_of_line ();
20532 as_bad (_("unknown cpu `%s'"), name
);
20533 *input_line_pointer
= saved_char
;
20534 ignore_rest_of_line ();
20538 /* Parse a .arch directive. */
20541 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
20543 const struct arm_arch_option_table
*opt
;
20547 name
= input_line_pointer
;
20548 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20549 input_line_pointer
++;
20550 saved_char
= *input_line_pointer
;
20551 *input_line_pointer
= 0;
20553 /* Skip the first "all" entry. */
20554 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
20555 if (streq (opt
->name
, name
))
20557 mcpu_cpu_opt
= &opt
->value
;
20558 selected_cpu
= opt
->value
;
20559 strcpy(selected_cpu_name
, opt
->name
);
20560 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20561 *input_line_pointer
= saved_char
;
20562 demand_empty_rest_of_line ();
20566 as_bad (_("unknown architecture `%s'\n"), name
);
20567 *input_line_pointer
= saved_char
;
20568 ignore_rest_of_line ();
20572 /* Parse a .object_arch directive. */
20575 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
20577 const struct arm_arch_option_table
*opt
;
20581 name
= input_line_pointer
;
20582 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20583 input_line_pointer
++;
20584 saved_char
= *input_line_pointer
;
20585 *input_line_pointer
= 0;
20587 /* Skip the first "all" entry. */
20588 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
20589 if (streq (opt
->name
, name
))
20591 object_arch
= &opt
->value
;
20592 *input_line_pointer
= saved_char
;
20593 demand_empty_rest_of_line ();
20597 as_bad (_("unknown architecture `%s'\n"), name
);
20598 *input_line_pointer
= saved_char
;
20599 ignore_rest_of_line ();
20603 /* Parse a .fpu directive. */
20606 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
20608 const struct arm_option_cpu_value_table
*opt
;
20612 name
= input_line_pointer
;
20613 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20614 input_line_pointer
++;
20615 saved_char
= *input_line_pointer
;
20616 *input_line_pointer
= 0;
20618 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
20619 if (streq (opt
->name
, name
))
20621 mfpu_opt
= &opt
->value
;
20622 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20623 *input_line_pointer
= saved_char
;
20624 demand_empty_rest_of_line ();
20628 as_bad (_("unknown floating point format `%s'\n"), name
);
20629 *input_line_pointer
= saved_char
;
20630 ignore_rest_of_line ();
20633 /* Copy symbol information. */
20635 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
20637 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);