1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dwarf2dbg.h"
41 #include "dw2gencfi.h"
44 /* XXX Set this to 1 after the next binutils release. */
45 #define WARN_DEPRECATED 0
48 /* Must be at least the size of the largest unwind opcode (currently two). */
49 #define ARM_OPCODE_CHUNK_SIZE 8
51 /* This structure holds the unwinding state. */
56 symbolS
* table_entry
;
57 symbolS
* personality_routine
;
58 int personality_index
;
59 /* The segment containing the function. */
62 /* Opcodes generated from this function. */
63 unsigned char * opcodes
;
66 /* The number of bytes pushed to the stack. */
68 /* We don't add stack adjustment opcodes immediately so that we can merge
69 multiple adjustments. We can also omit the final adjustment
70 when using a frame pointer. */
71 offsetT pending_offset
;
72 /* These two fields are set by both unwind_movsp and unwind_setfp. They
73 hold the reg+offset to use when restoring sp from a frame pointer. */
76 /* Nonzero if an unwind_setfp directive has been seen. */
78 /* Nonzero if the last opcode restores sp from fp_reg. */
79 unsigned sp_restored
:1;
82 /* Bit N indicates that an R_ARM_NONE relocation has been output for
83 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
84 emitted only once per section, to save unnecessary bloat. */
85 static unsigned int marked_pr_dependency
= 0;
89 /* Results from operand parsing worker functions. */
93 PARSE_OPERAND_SUCCESS
,
95 PARSE_OPERAND_FAIL_NO_BACKTRACK
96 } parse_operand_result
;
101 ARM_FLOAT_ABI_SOFTFP
,
105 /* Types of processor to assemble for. */
107 #if defined __XSCALE__
108 #define CPU_DEFAULT ARM_ARCH_XSCALE
110 #if defined __thumb__
111 #define CPU_DEFAULT ARM_ARCH_V5T
118 # define FPU_DEFAULT FPU_ARCH_FPA
119 # elif defined (TE_NetBSD)
121 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
123 /* Legacy a.out format. */
124 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
126 # elif defined (TE_VXWORKS)
127 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
129 /* For backwards compatibility, default to FPA. */
130 # define FPU_DEFAULT FPU_ARCH_FPA
132 #endif /* ifndef FPU_DEFAULT */
134 #define streq(a, b) (strcmp (a, b) == 0)
136 static arm_feature_set cpu_variant
;
137 static arm_feature_set arm_arch_used
;
138 static arm_feature_set thumb_arch_used
;
140 /* Flags stored in private area of BFD structure. */
141 static int uses_apcs_26
= FALSE
;
142 static int atpcs
= FALSE
;
143 static int support_interwork
= FALSE
;
144 static int uses_apcs_float
= FALSE
;
145 static int pic_code
= FALSE
;
147 /* Variables that we set while parsing command-line options. Once all
148 options have been read we re-process these values to set the real
150 static const arm_feature_set
*legacy_cpu
= NULL
;
151 static const arm_feature_set
*legacy_fpu
= NULL
;
153 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
154 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
155 static const arm_feature_set
*march_cpu_opt
= NULL
;
156 static const arm_feature_set
*march_fpu_opt
= NULL
;
157 static const arm_feature_set
*mfpu_opt
= NULL
;
159 /* Constants for known architecture features. */
160 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
161 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
162 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
163 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
164 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
165 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
166 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
167 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
168 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
171 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
174 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
175 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
176 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
177 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
178 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
179 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
180 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
181 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
182 static const arm_feature_set arm_ext_v4t_5
=
183 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
184 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
185 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
186 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
187 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
188 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
189 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
190 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
191 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
192 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
199 static const arm_feature_set arm_arch_any
= ARM_ANY
;
200 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
201 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
202 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
204 static const arm_feature_set arm_cext_iwmmxt
=
205 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
206 static const arm_feature_set arm_cext_xscale
=
207 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
208 static const arm_feature_set arm_cext_maverick
=
209 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
210 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
211 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
212 static const arm_feature_set fpu_vfp_ext_v1xd
=
213 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
214 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
215 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
216 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
217 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
218 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
219 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
221 static int mfloat_abi_opt
= -1;
222 /* Record user cpu selection for object attributes. */
223 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
224 /* Must be long enough to hold any of the names in arm_cpus. */
225 static char selected_cpu_name
[16];
228 static int meabi_flags
= EABI_DEFAULT
;
230 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
235 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
236 symbolS
* GOT_symbol
;
239 /* 0: assemble for ARM,
240 1: assemble for Thumb,
241 2: assemble for Thumb even though target CPU does not support thumb
243 static int thumb_mode
= 0;
245 /* If unified_syntax is true, we are processing the new unified
246 ARM/Thumb syntax. Important differences from the old ARM mode:
248 - Immediate operands do not require a # prefix.
249 - Conditional affixes always appear at the end of the
250 instruction. (For backward compatibility, those instructions
251 that formerly had them in the middle, continue to accept them
253 - The IT instruction may appear, and if it does is validated
254 against subsequent conditional affixes. It does not generate
257 Important differences from the old Thumb mode:
259 - Immediate operands do not require a # prefix.
260 - Most of the V6T2 instructions are only available in unified mode.
261 - The .N and .W suffixes are recognized and honored (it is an error
262 if they cannot be honored).
263 - All instructions set the flags if and only if they have an 's' affix.
264 - Conditional affixes may be used. They are validated against
265 preceding IT instructions. Unlike ARM mode, you cannot use a
266 conditional affix except in the scope of an IT instruction. */
268 static bfd_boolean unified_syntax
= FALSE
;
283 enum neon_el_type type
;
287 #define NEON_MAX_TYPE_ELS 4
291 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
298 unsigned long instruction
;
302 /* "uncond_value" is set to the value in place of the conditional field in
303 unconditional versions of the instruction, or -1 if nothing is
306 struct neon_type vectype
;
307 /* Set to the opcode if the instruction needs relaxation.
308 Zero if the instruction is not relaxed. */
312 bfd_reloc_code_real_type type
;
321 struct neon_type_el vectype
;
322 unsigned present
: 1; /* Operand present. */
323 unsigned isreg
: 1; /* Operand was a register. */
324 unsigned immisreg
: 1; /* .imm field is a second register. */
325 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
326 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
327 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
328 instructions. This allows us to disambiguate ARM <-> vector insns. */
329 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
330 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
331 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
332 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
333 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
334 unsigned writeback
: 1; /* Operand has trailing ! */
335 unsigned preind
: 1; /* Preindexed address. */
336 unsigned postind
: 1; /* Postindexed address. */
337 unsigned negative
: 1; /* Index register was negated. */
338 unsigned shifted
: 1; /* Shift applied to operation. */
339 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
343 static struct arm_it inst
;
345 #define NUM_FLOAT_VALS 8
347 const char * fp_const
[] =
349 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
352 /* Number of littlenums required to hold an extended precision number. */
353 #define MAX_LITTLENUMS 6
355 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
365 #define CP_T_X 0x00008000
366 #define CP_T_Y 0x00400000
368 #define CONDS_BIT 0x00100000
369 #define LOAD_BIT 0x00100000
371 #define DOUBLE_LOAD_FLAG 0x00000001
375 const char * template;
379 #define COND_ALWAYS 0xE
383 const char *template;
387 struct asm_barrier_opt
389 const char *template;
393 /* The bit that distinguishes CPSR and SPSR. */
394 #define SPSR_BIT (1 << 22)
396 /* The individual PSR flag bits. */
397 #define PSR_c (1 << 16)
398 #define PSR_x (1 << 17)
399 #define PSR_s (1 << 18)
400 #define PSR_f (1 << 19)
405 bfd_reloc_code_real_type reloc
;
410 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
411 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
416 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
419 /* Bits for DEFINED field in neon_typed_alias. */
420 #define NTA_HASTYPE 1
421 #define NTA_HASINDEX 2
423 struct neon_typed_alias
425 unsigned char defined
;
427 struct neon_type_el eltype
;
430 /* ARM register categories. This includes coprocessor numbers and various
431 architecture extensions' registers. */
457 /* Structure for a hash table entry for a register.
458 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
459 information which states whether a vector type or index is specified (for a
460 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
464 unsigned char number
;
466 unsigned char builtin
;
467 struct neon_typed_alias
*neon
;
470 /* Diagnostics used when we don't get a register of the expected type. */
471 const char *const reg_expected_msgs
[] =
473 N_("ARM register expected"),
474 N_("bad or missing co-processor number"),
475 N_("co-processor register expected"),
476 N_("FPA register expected"),
477 N_("VFP single precision register expected"),
478 N_("VFP/Neon double precision register expected"),
479 N_("Neon quad precision register expected"),
480 N_("VFP single or double precision register expected"),
481 N_("Neon double or quad precision register expected"),
482 N_("VFP single, double or Neon quad precision register expected"),
483 N_("VFP system register expected"),
484 N_("Maverick MVF register expected"),
485 N_("Maverick MVD register expected"),
486 N_("Maverick MVFX register expected"),
487 N_("Maverick MVDX register expected"),
488 N_("Maverick MVAX register expected"),
489 N_("Maverick DSPSC register expected"),
490 N_("iWMMXt data register expected"),
491 N_("iWMMXt control register expected"),
492 N_("iWMMXt scalar register expected"),
493 N_("XScale accumulator register expected"),
496 /* Some well known registers that we refer to directly elsewhere. */
501 /* ARM instructions take 4bytes in the object file, Thumb instructions
507 /* Basic string to match. */
508 const char *template;
510 /* Parameters to instruction. */
511 unsigned char operands
[8];
513 /* Conditional tag - see opcode_lookup. */
514 unsigned int tag
: 4;
516 /* Basic instruction code. */
517 unsigned int avalue
: 28;
519 /* Thumb-format instruction code. */
522 /* Which architecture variant provides this instruction. */
523 const arm_feature_set
*avariant
;
524 const arm_feature_set
*tvariant
;
526 /* Function to call to encode instruction in ARM format. */
527 void (* aencode
) (void);
529 /* Function to call to encode instruction in Thumb format. */
530 void (* tencode
) (void);
533 /* Defines for various bits that we will want to toggle. */
534 #define INST_IMMEDIATE 0x02000000
535 #define OFFSET_REG 0x02000000
536 #define HWOFFSET_IMM 0x00400000
537 #define SHIFT_BY_REG 0x00000010
538 #define PRE_INDEX 0x01000000
539 #define INDEX_UP 0x00800000
540 #define WRITE_BACK 0x00200000
541 #define LDM_TYPE_2_OR_3 0x00400000
543 #define LITERAL_MASK 0xf000f000
544 #define OPCODE_MASK 0xfe1fffff
545 #define V4_STR_BIT 0x00000020
547 #define DATA_OP_SHIFT 21
549 #define T2_OPCODE_MASK 0xfe1fffff
550 #define T2_DATA_OP_SHIFT 21
552 /* Codes to distinguish the arithmetic instructions. */
563 #define OPCODE_CMP 10
564 #define OPCODE_CMN 11
565 #define OPCODE_ORR 12
566 #define OPCODE_MOV 13
567 #define OPCODE_BIC 14
568 #define OPCODE_MVN 15
570 #define T2_OPCODE_AND 0
571 #define T2_OPCODE_BIC 1
572 #define T2_OPCODE_ORR 2
573 #define T2_OPCODE_ORN 3
574 #define T2_OPCODE_EOR 4
575 #define T2_OPCODE_ADD 8
576 #define T2_OPCODE_ADC 10
577 #define T2_OPCODE_SBC 11
578 #define T2_OPCODE_SUB 13
579 #define T2_OPCODE_RSB 14
581 #define T_OPCODE_MUL 0x4340
582 #define T_OPCODE_TST 0x4200
583 #define T_OPCODE_CMN 0x42c0
584 #define T_OPCODE_NEG 0x4240
585 #define T_OPCODE_MVN 0x43c0
587 #define T_OPCODE_ADD_R3 0x1800
588 #define T_OPCODE_SUB_R3 0x1a00
589 #define T_OPCODE_ADD_HI 0x4400
590 #define T_OPCODE_ADD_ST 0xb000
591 #define T_OPCODE_SUB_ST 0xb080
592 #define T_OPCODE_ADD_SP 0xa800
593 #define T_OPCODE_ADD_PC 0xa000
594 #define T_OPCODE_ADD_I8 0x3000
595 #define T_OPCODE_SUB_I8 0x3800
596 #define T_OPCODE_ADD_I3 0x1c00
597 #define T_OPCODE_SUB_I3 0x1e00
599 #define T_OPCODE_ASR_R 0x4100
600 #define T_OPCODE_LSL_R 0x4080
601 #define T_OPCODE_LSR_R 0x40c0
602 #define T_OPCODE_ROR_R 0x41c0
603 #define T_OPCODE_ASR_I 0x1000
604 #define T_OPCODE_LSL_I 0x0000
605 #define T_OPCODE_LSR_I 0x0800
607 #define T_OPCODE_MOV_I8 0x2000
608 #define T_OPCODE_CMP_I8 0x2800
609 #define T_OPCODE_CMP_LR 0x4280
610 #define T_OPCODE_MOV_HR 0x4600
611 #define T_OPCODE_CMP_HR 0x4500
613 #define T_OPCODE_LDR_PC 0x4800
614 #define T_OPCODE_LDR_SP 0x9800
615 #define T_OPCODE_STR_SP 0x9000
616 #define T_OPCODE_LDR_IW 0x6800
617 #define T_OPCODE_STR_IW 0x6000
618 #define T_OPCODE_LDR_IH 0x8800
619 #define T_OPCODE_STR_IH 0x8000
620 #define T_OPCODE_LDR_IB 0x7800
621 #define T_OPCODE_STR_IB 0x7000
622 #define T_OPCODE_LDR_RW 0x5800
623 #define T_OPCODE_STR_RW 0x5000
624 #define T_OPCODE_LDR_RH 0x5a00
625 #define T_OPCODE_STR_RH 0x5200
626 #define T_OPCODE_LDR_RB 0x5c00
627 #define T_OPCODE_STR_RB 0x5400
629 #define T_OPCODE_PUSH 0xb400
630 #define T_OPCODE_POP 0xbc00
632 #define T_OPCODE_BRANCH 0xe000
634 #define THUMB_SIZE 2 /* Size of thumb instruction. */
635 #define THUMB_PP_PC_LR 0x0100
636 #define THUMB_LOAD_BIT 0x0800
637 #define THUMB2_LOAD_BIT 0x00100000
639 #define BAD_ARGS _("bad arguments to instruction")
640 #define BAD_PC _("r15 not allowed here")
641 #define BAD_COND _("instruction cannot be conditional")
642 #define BAD_OVERLAP _("registers may not be the same")
643 #define BAD_HIREG _("lo register required")
644 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
645 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
646 #define BAD_BRANCH _("branch must be last instruction in IT block")
647 #define BAD_NOT_IT _("instruction not allowed in IT block")
648 #define BAD_FPU _("selected FPU does not support instruction")
650 static struct hash_control
*arm_ops_hsh
;
651 static struct hash_control
*arm_cond_hsh
;
652 static struct hash_control
*arm_shift_hsh
;
653 static struct hash_control
*arm_psr_hsh
;
654 static struct hash_control
*arm_v7m_psr_hsh
;
655 static struct hash_control
*arm_reg_hsh
;
656 static struct hash_control
*arm_reloc_hsh
;
657 static struct hash_control
*arm_barrier_opt_hsh
;
659 /* Stuff needed to resolve the label ambiguity
669 symbolS
* last_label_seen
;
670 static int label_is_thumb_function_name
= FALSE
;
672 /* Literal pool structure. Held on a per-section
673 and per-sub-section basis. */
675 #define MAX_LITERAL_POOL_SIZE 1024
676 typedef struct literal_pool
678 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
679 unsigned int next_free_entry
;
684 struct literal_pool
* next
;
687 /* Pointer to a linked list of literal pools. */
688 literal_pool
* list_of_pools
= NULL
;
690 /* State variables for IT block handling. */
691 static bfd_boolean current_it_mask
= 0;
692 static int current_cc
;
697 /* This array holds the chars that always start a comment. If the
698 pre-processor is disabled, these aren't very useful. */
699 const char comment_chars
[] = "@";
701 /* This array holds the chars that only start a comment at the beginning of
702 a line. If the line seems to have the form '# 123 filename'
703 .line and .file directives will appear in the pre-processed output. */
704 /* Note that input_file.c hand checks for '#' at the beginning of the
705 first line of the input file. This is because the compiler outputs
706 #NO_APP at the beginning of its output. */
707 /* Also note that comments like this one will always work. */
708 const char line_comment_chars
[] = "#";
710 const char line_separator_chars
[] = ";";
712 /* Chars that can be used to separate mant
713 from exp in floating point numbers. */
714 const char EXP_CHARS
[] = "eE";
716 /* Chars that mean this number is a floating point constant. */
720 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
722 /* Prefix characters that indicate the start of an immediate
724 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
726 /* Separator character handling. */
728 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
731 skip_past_char (char ** str
, char c
)
741 #define skip_past_comma(str) skip_past_char (str, ',')
743 /* Arithmetic expressions (possibly involving symbols). */
745 /* Return TRUE if anything in the expression is a bignum. */
748 walk_no_bignums (symbolS
* sp
)
750 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
753 if (symbol_get_value_expression (sp
)->X_add_symbol
)
755 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
756 || (symbol_get_value_expression (sp
)->X_op_symbol
757 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
763 static int in_my_get_expression
= 0;
765 /* Third argument to my_get_expression. */
766 #define GE_NO_PREFIX 0
767 #define GE_IMM_PREFIX 1
768 #define GE_OPT_PREFIX 2
769 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
770 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
771 #define GE_OPT_PREFIX_BIG 3
774 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
779 /* In unified syntax, all prefixes are optional. */
781 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
786 case GE_NO_PREFIX
: break;
788 if (!is_immediate_prefix (**str
))
790 inst
.error
= _("immediate expression requires a # prefix");
796 case GE_OPT_PREFIX_BIG
:
797 if (is_immediate_prefix (**str
))
803 memset (ep
, 0, sizeof (expressionS
));
805 save_in
= input_line_pointer
;
806 input_line_pointer
= *str
;
807 in_my_get_expression
= 1;
808 seg
= expression (ep
);
809 in_my_get_expression
= 0;
811 if (ep
->X_op
== O_illegal
)
813 /* We found a bad expression in md_operand(). */
814 *str
= input_line_pointer
;
815 input_line_pointer
= save_in
;
816 if (inst
.error
== NULL
)
817 inst
.error
= _("bad expression");
822 if (seg
!= absolute_section
823 && seg
!= text_section
824 && seg
!= data_section
825 && seg
!= bss_section
826 && seg
!= undefined_section
)
828 inst
.error
= _("bad segment");
829 *str
= input_line_pointer
;
830 input_line_pointer
= save_in
;
835 /* Get rid of any bignums now, so that we don't generate an error for which
836 we can't establish a line number later on. Big numbers are never valid
837 in instructions, which is where this routine is always called. */
838 if (prefix_mode
!= GE_OPT_PREFIX_BIG
839 && (ep
->X_op
== O_big
841 && (walk_no_bignums (ep
->X_add_symbol
)
843 && walk_no_bignums (ep
->X_op_symbol
))))))
845 inst
.error
= _("invalid constant");
846 *str
= input_line_pointer
;
847 input_line_pointer
= save_in
;
851 *str
= input_line_pointer
;
852 input_line_pointer
= save_in
;
856 /* Turn a string in input_line_pointer into a floating point constant
857 of type TYPE, and store the appropriate bytes in *LITP. The number
858 of LITTLENUMS emitted is stored in *SIZEP. An error message is
859 returned, or NULL on OK.
861 Note that fp constants aren't represent in the normal way on the ARM.
862 In big endian mode, things are as expected. However, in little endian
863 mode fp constants are big-endian word-wise, and little-endian byte-wise
864 within the words. For example, (double) 1.1 in big endian mode is
865 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
866 the byte sequence 99 99 f1 3f 9a 99 99 99.
868 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
871 md_atof (int type
, char * litP
, int * sizeP
)
874 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
906 return _("bad call to MD_ATOF()");
909 t
= atof_ieee (input_line_pointer
, type
, words
);
911 input_line_pointer
= t
;
914 if (target_big_endian
)
916 for (i
= 0; i
< prec
; i
++)
918 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
924 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
925 for (i
= prec
- 1; i
>= 0; i
--)
927 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
931 /* For a 4 byte float the order of elements in `words' is 1 0.
932 For an 8 byte float the order is 1 0 3 2. */
933 for (i
= 0; i
< prec
; i
+= 2)
935 md_number_to_chars (litP
, (valueT
) words
[i
+ 1], 2);
936 md_number_to_chars (litP
+ 2, (valueT
) words
[i
], 2);
944 /* We handle all bad expressions here, so that we can report the faulty
945 instruction in the error message. */
947 md_operand (expressionS
* expr
)
949 if (in_my_get_expression
)
950 expr
->X_op
= O_illegal
;
953 /* Immediate values. */
955 /* Generic immediate-value read function for use in directives.
956 Accepts anything that 'expression' can fold to a constant.
957 *val receives the number. */
960 immediate_for_directive (int *val
)
963 exp
.X_op
= O_illegal
;
965 if (is_immediate_prefix (*input_line_pointer
))
967 input_line_pointer
++;
971 if (exp
.X_op
!= O_constant
)
973 as_bad (_("expected #constant"));
974 ignore_rest_of_line ();
977 *val
= exp
.X_add_number
;
982 /* Register parsing. */
984 /* Generic register parser. CCP points to what should be the
985 beginning of a register name. If it is indeed a valid register
986 name, advance CCP over it and return the reg_entry structure;
987 otherwise return NULL. Does not issue diagnostics. */
989 static struct reg_entry
*
990 arm_reg_parse_multi (char **ccp
)
994 struct reg_entry
*reg
;
996 #ifdef REGISTER_PREFIX
997 if (*start
!= REGISTER_PREFIX
)
1001 #ifdef OPTIONAL_REGISTER_PREFIX
1002 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1007 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1012 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1014 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1024 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1025 enum arm_reg_type type
)
1027 /* Alternative syntaxes are accepted for a few register classes. */
1034 /* Generic coprocessor register names are allowed for these. */
1035 if (reg
&& reg
->type
== REG_TYPE_CN
)
1040 /* For backward compatibility, a bare number is valid here. */
1042 unsigned long processor
= strtoul (start
, ccp
, 10);
1043 if (*ccp
!= start
&& processor
<= 15)
1047 case REG_TYPE_MMXWC
:
1048 /* WC includes WCG. ??? I'm not sure this is true for all
1049 instructions that take WC registers. */
1050 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1061 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1062 return value is the register number or FAIL. */
1065 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1068 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1071 /* Do not allow a scalar (reg+index) to parse as a register. */
1072 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1075 if (reg
&& reg
->type
== type
)
1078 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1085 /* Parse a Neon type specifier. *STR should point at the leading '.'
1086 character. Does no verification at this stage that the type fits the opcode
1093 Can all be legally parsed by this function.
1095 Fills in neon_type struct pointer with parsed information, and updates STR
1096 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1097 type, FAIL if not. */
1100 parse_neon_type (struct neon_type
*type
, char **str
)
1107 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1109 enum neon_el_type thistype
= NT_untyped
;
1110 unsigned thissize
= -1u;
1117 /* Just a size without an explicit type. */
1121 switch (TOLOWER (*ptr
))
1123 case 'i': thistype
= NT_integer
; break;
1124 case 'f': thistype
= NT_float
; break;
1125 case 'p': thistype
= NT_poly
; break;
1126 case 's': thistype
= NT_signed
; break;
1127 case 'u': thistype
= NT_unsigned
; break;
1129 thistype
= NT_float
;
1134 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1140 /* .f is an abbreviation for .f32. */
1141 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1146 thissize
= strtoul (ptr
, &ptr
, 10);
1148 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1151 as_bad (_("bad size %d in type specifier"), thissize
);
1159 type
->el
[type
->elems
].type
= thistype
;
1160 type
->el
[type
->elems
].size
= thissize
;
1165 /* Empty/missing type is not a successful parse. */
1166 if (type
->elems
== 0)
1174 /* Errors may be set multiple times during parsing or bit encoding
1175 (particularly in the Neon bits), but usually the earliest error which is set
1176 will be the most meaningful. Avoid overwriting it with later (cascading)
1177 errors by calling this function. */
1180 first_error (const char *err
)
1186 /* Parse a single type, e.g. ".s32", leading period included. */
1188 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1191 struct neon_type optype
;
1195 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1197 if (optype
.elems
== 1)
1198 *vectype
= optype
.el
[0];
1201 first_error (_("only one type should be specified for operand"));
1207 first_error (_("vector type expected"));
1219 /* Special meanings for indices (which have a range of 0-7), which will fit into
1222 #define NEON_ALL_LANES 15
1223 #define NEON_INTERLEAVE_LANES 14
1225 /* Parse either a register or a scalar, with an optional type. Return the
1226 register number, and optionally fill in the actual type of the register
1227 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1228 type/index information in *TYPEINFO. */
1231 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1232 enum arm_reg_type
*rtype
,
1233 struct neon_typed_alias
*typeinfo
)
1236 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1237 struct neon_typed_alias atype
;
1238 struct neon_type_el parsetype
;
1242 atype
.eltype
.type
= NT_invtype
;
1243 atype
.eltype
.size
= -1;
1245 /* Try alternate syntax for some types of register. Note these are mutually
1246 exclusive with the Neon syntax extensions. */
1249 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1257 /* Undo polymorphism when a set of register types may be accepted. */
1258 if ((type
== REG_TYPE_NDQ
1259 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1260 || (type
== REG_TYPE_VFSD
1261 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1262 || (type
== REG_TYPE_NSDQ
1263 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1264 || reg
->type
== REG_TYPE_NQ
)))
1267 if (type
!= reg
->type
)
1273 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1275 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1277 first_error (_("can't redefine type for operand"));
1280 atype
.defined
|= NTA_HASTYPE
;
1281 atype
.eltype
= parsetype
;
1284 if (skip_past_char (&str
, '[') == SUCCESS
)
1286 if (type
!= REG_TYPE_VFD
)
1288 first_error (_("only D registers may be indexed"));
1292 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1294 first_error (_("can't change index for operand"));
1298 atype
.defined
|= NTA_HASINDEX
;
1300 if (skip_past_char (&str
, ']') == SUCCESS
)
1301 atype
.index
= NEON_ALL_LANES
;
1306 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1308 if (exp
.X_op
!= O_constant
)
1310 first_error (_("constant expression required"));
1314 if (skip_past_char (&str
, ']') == FAIL
)
1317 atype
.index
= exp
.X_add_number
;
1332 /* Like arm_reg_parse, but allow allow the following extra features:
1333 - If RTYPE is non-zero, return the (possibly restricted) type of the
1334 register (e.g. Neon double or quad reg when either has been requested).
1335 - If this is a Neon vector type with additional type information, fill
1336 in the struct pointed to by VECTYPE (if non-NULL).
1337 This function will fault on encountering a scalar.
1341 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1342 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1344 struct neon_typed_alias atype
;
1346 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1351 /* Do not allow a scalar (reg+index) to parse as a register. */
1352 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1354 first_error (_("register operand expected, but got scalar"));
1359 *vectype
= atype
.eltype
;
1366 #define NEON_SCALAR_REG(X) ((X) >> 4)
1367 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1369 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1370 have enough information to be able to do a good job bounds-checking. So, we
1371 just do easy checks here, and do further checks later. */
1374 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1378 struct neon_typed_alias atype
;
1380 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1382 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1385 if (atype
.index
== NEON_ALL_LANES
)
1387 first_error (_("scalar must have an index"));
1390 else if (atype
.index
>= 64 / elsize
)
1392 first_error (_("scalar index out of range"));
1397 *type
= atype
.eltype
;
1401 return reg
* 16 + atype
.index
;
1404 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1406 parse_reg_list (char ** strp
)
1408 char * str
= * strp
;
1412 /* We come back here if we get ranges concatenated by '+' or '|'. */
1427 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1429 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1439 first_error (_("bad range in register list"));
1443 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1445 if (range
& (1 << i
))
1447 (_("Warning: duplicated register (r%d) in register list"),
1455 if (range
& (1 << reg
))
1456 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1458 else if (reg
<= cur_reg
)
1459 as_tsktsk (_("Warning: register range not in ascending order"));
1464 while (skip_past_comma (&str
) != FAIL
1465 || (in_range
= 1, *str
++ == '-'));
1470 first_error (_("missing `}'"));
1478 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1481 if (expr
.X_op
== O_constant
)
1483 if (expr
.X_add_number
1484 != (expr
.X_add_number
& 0x0000ffff))
1486 inst
.error
= _("invalid register mask");
1490 if ((range
& expr
.X_add_number
) != 0)
1492 int regno
= range
& expr
.X_add_number
;
1495 regno
= (1 << regno
) - 1;
1497 (_("Warning: duplicated register (r%d) in register list"),
1501 range
|= expr
.X_add_number
;
1505 if (inst
.reloc
.type
!= 0)
1507 inst
.error
= _("expression too complex");
1511 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1512 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1513 inst
.reloc
.pc_rel
= 0;
1517 if (*str
== '|' || *str
== '+')
1523 while (another_range
);
1529 /* Types of registers in a list. */
1538 /* Parse a VFP register list. If the string is invalid return FAIL.
1539 Otherwise return the number of registers, and set PBASE to the first
1540 register. Parses registers of type ETYPE.
1541 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1542 - Q registers can be used to specify pairs of D registers
1543 - { } can be omitted from around a singleton register list
1544 FIXME: This is not implemented, as it would require backtracking in
1547 This could be done (the meaning isn't really ambiguous), but doesn't
1548 fit in well with the current parsing framework.
1549 - 32 D registers may be used (also true for VFPv3).
1550 FIXME: Types are ignored in these register lists, which is probably a
1554 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1559 enum arm_reg_type regtype
= 0;
1563 unsigned long mask
= 0;
1568 inst
.error
= _("expecting {");
1577 regtype
= REG_TYPE_VFS
;
1582 regtype
= REG_TYPE_VFD
;
1585 case REGLIST_NEON_D
:
1586 regtype
= REG_TYPE_NDQ
;
1590 if (etype
!= REGLIST_VFP_S
)
1592 /* VFPv3 allows 32 D registers. */
1593 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
1597 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1600 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1607 base_reg
= max_regs
;
1611 int setmask
= 1, addregs
= 1;
1613 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1615 if (new_base
== FAIL
)
1617 first_error (_(reg_expected_msgs
[regtype
]));
1621 if (new_base
>= max_regs
)
1623 first_error (_("register out of range in list"));
1627 /* Note: a value of 2 * n is returned for the register Q<n>. */
1628 if (regtype
== REG_TYPE_NQ
)
1634 if (new_base
< base_reg
)
1635 base_reg
= new_base
;
1637 if (mask
& (setmask
<< new_base
))
1639 first_error (_("invalid register list"));
1643 if ((mask
>> new_base
) != 0 && ! warned
)
1645 as_tsktsk (_("register list not in ascending order"));
1649 mask
|= setmask
<< new_base
;
1652 if (*str
== '-') /* We have the start of a range expression */
1658 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1661 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1665 if (high_range
>= max_regs
)
1667 first_error (_("register out of range in list"));
1671 if (regtype
== REG_TYPE_NQ
)
1672 high_range
= high_range
+ 1;
1674 if (high_range
<= new_base
)
1676 inst
.error
= _("register range not in ascending order");
1680 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1682 if (mask
& (setmask
<< new_base
))
1684 inst
.error
= _("invalid register list");
1688 mask
|= setmask
<< new_base
;
1693 while (skip_past_comma (&str
) != FAIL
);
1697 /* Sanity check -- should have raised a parse error above. */
1698 if (count
== 0 || count
> max_regs
)
1703 /* Final test -- the registers must be consecutive. */
1705 for (i
= 0; i
< count
; i
++)
1707 if ((mask
& (1u << i
)) == 0)
1709 inst
.error
= _("non-contiguous register range");
1719 /* True if two alias types are the same. */
1722 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1730 if (a
->defined
!= b
->defined
)
1733 if ((a
->defined
& NTA_HASTYPE
) != 0
1734 && (a
->eltype
.type
!= b
->eltype
.type
1735 || a
->eltype
.size
!= b
->eltype
.size
))
1738 if ((a
->defined
& NTA_HASINDEX
) != 0
1739 && (a
->index
!= b
->index
))
1745 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1746 The base register is put in *PBASE.
1747 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1749 The register stride (minus one) is put in bit 4 of the return value.
1750 Bits [6:5] encode the list length (minus one).
1751 The type of the list elements is put in *ELTYPE, if non-NULL. */
1753 #define NEON_LANE(X) ((X) & 0xf)
1754 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1755 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1758 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1759 struct neon_type_el
*eltype
)
1766 int leading_brace
= 0;
1767 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1769 const char *const incr_error
= "register stride must be 1 or 2";
1770 const char *const type_error
= "mismatched element/structure types in list";
1771 struct neon_typed_alias firsttype
;
1773 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1778 struct neon_typed_alias atype
;
1779 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1783 first_error (_(reg_expected_msgs
[rtype
]));
1790 if (rtype
== REG_TYPE_NQ
)
1797 else if (reg_incr
== -1)
1799 reg_incr
= getreg
- base_reg
;
1800 if (reg_incr
< 1 || reg_incr
> 2)
1802 first_error (_(incr_error
));
1806 else if (getreg
!= base_reg
+ reg_incr
* count
)
1808 first_error (_(incr_error
));
1812 if (!neon_alias_types_same (&atype
, &firsttype
))
1814 first_error (_(type_error
));
1818 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1822 struct neon_typed_alias htype
;
1823 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1825 lane
= NEON_INTERLEAVE_LANES
;
1826 else if (lane
!= NEON_INTERLEAVE_LANES
)
1828 first_error (_(type_error
));
1833 else if (reg_incr
!= 1)
1835 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1839 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1842 first_error (_(reg_expected_msgs
[rtype
]));
1845 if (!neon_alias_types_same (&htype
, &firsttype
))
1847 first_error (_(type_error
));
1850 count
+= hireg
+ dregs
- getreg
;
1854 /* If we're using Q registers, we can't use [] or [n] syntax. */
1855 if (rtype
== REG_TYPE_NQ
)
1861 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1865 else if (lane
!= atype
.index
)
1867 first_error (_(type_error
));
1871 else if (lane
== -1)
1872 lane
= NEON_INTERLEAVE_LANES
;
1873 else if (lane
!= NEON_INTERLEAVE_LANES
)
1875 first_error (_(type_error
));
1880 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1882 /* No lane set by [x]. We must be interleaving structures. */
1884 lane
= NEON_INTERLEAVE_LANES
;
1887 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
1888 || (count
> 1 && reg_incr
== -1))
1890 first_error (_("error parsing element/structure list"));
1894 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
1896 first_error (_("expected }"));
1904 *eltype
= firsttype
.eltype
;
1909 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
1912 /* Parse an explicit relocation suffix on an expression. This is
1913 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1914 arm_reloc_hsh contains no entries, so this function can only
1915 succeed if there is no () after the word. Returns -1 on error,
1916 BFD_RELOC_UNUSED if there wasn't any suffix. */
1918 parse_reloc (char **str
)
1920 struct reloc_entry
*r
;
1924 return BFD_RELOC_UNUSED
;
1929 while (*q
&& *q
!= ')' && *q
!= ',')
1934 if ((r
= hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
1941 /* Directives: register aliases. */
1943 static struct reg_entry
*
1944 insert_reg_alias (char *str
, int number
, int type
)
1946 struct reg_entry
*new;
1949 if ((new = hash_find (arm_reg_hsh
, str
)) != 0)
1952 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
1954 /* Only warn about a redefinition if it's not defined as the
1956 else if (new->number
!= number
|| new->type
!= type
)
1957 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1962 name
= xstrdup (str
);
1963 new = xmalloc (sizeof (struct reg_entry
));
1966 new->number
= number
;
1968 new->builtin
= FALSE
;
1971 if (hash_insert (arm_reg_hsh
, name
, (PTR
) new))
1978 insert_neon_reg_alias (char *str
, int number
, int type
,
1979 struct neon_typed_alias
*atype
)
1981 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
1985 first_error (_("attempt to redefine typed alias"));
1991 reg
->neon
= xmalloc (sizeof (struct neon_typed_alias
));
1992 *reg
->neon
= *atype
;
1996 /* Look for the .req directive. This is of the form:
1998 new_register_name .req existing_register_name
2000 If we find one, or if it looks sufficiently like one that we want to
2001 handle any error here, return non-zero. Otherwise return zero. */
2004 create_register_alias (char * newname
, char *p
)
2006 struct reg_entry
*old
;
2007 char *oldname
, *nbuf
;
2010 /* The input scrubber ensures that whitespace after the mnemonic is
2011 collapsed to single spaces. */
2013 if (strncmp (oldname
, " .req ", 6) != 0)
2017 if (*oldname
== '\0')
2020 old
= hash_find (arm_reg_hsh
, oldname
);
2023 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2027 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2028 the desired alias name, and p points to its end. If not, then
2029 the desired alias name is in the global original_case_string. */
2030 #ifdef TC_CASE_SENSITIVE
2033 newname
= original_case_string
;
2034 nlen
= strlen (newname
);
2037 nbuf
= alloca (nlen
+ 1);
2038 memcpy (nbuf
, newname
, nlen
);
2041 /* Create aliases under the new name as stated; an all-lowercase
2042 version of the new name; and an all-uppercase version of the new
2044 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2046 for (p
= nbuf
; *p
; p
++)
2049 if (strncmp (nbuf
, newname
, nlen
))
2050 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2052 for (p
= nbuf
; *p
; p
++)
2055 if (strncmp (nbuf
, newname
, nlen
))
2056 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2061 /* Create a Neon typed/indexed register alias using directives, e.g.:
2066 These typed registers can be used instead of the types specified after the
2067 Neon mnemonic, so long as all operands given have types. Types can also be
2068 specified directly, e.g.:
2069 vadd d0.s32, d1.s32, d2.s32
2073 create_neon_reg_alias (char *newname
, char *p
)
2075 enum arm_reg_type basetype
;
2076 struct reg_entry
*basereg
;
2077 struct reg_entry mybasereg
;
2078 struct neon_type ntype
;
2079 struct neon_typed_alias typeinfo
;
2080 char *namebuf
, *nameend
;
2083 typeinfo
.defined
= 0;
2084 typeinfo
.eltype
.type
= NT_invtype
;
2085 typeinfo
.eltype
.size
= -1;
2086 typeinfo
.index
= -1;
2090 if (strncmp (p
, " .dn ", 5) == 0)
2091 basetype
= REG_TYPE_VFD
;
2092 else if (strncmp (p
, " .qn ", 5) == 0)
2093 basetype
= REG_TYPE_NQ
;
2102 basereg
= arm_reg_parse_multi (&p
);
2104 if (basereg
&& basereg
->type
!= basetype
)
2106 as_bad (_("bad type for register"));
2110 if (basereg
== NULL
)
2113 /* Try parsing as an integer. */
2114 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2115 if (exp
.X_op
!= O_constant
)
2117 as_bad (_("expression must be constant"));
2120 basereg
= &mybasereg
;
2121 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2127 typeinfo
= *basereg
->neon
;
2129 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2131 /* We got a type. */
2132 if (typeinfo
.defined
& NTA_HASTYPE
)
2134 as_bad (_("can't redefine the type of a register alias"));
2138 typeinfo
.defined
|= NTA_HASTYPE
;
2139 if (ntype
.elems
!= 1)
2141 as_bad (_("you must specify a single type only"));
2144 typeinfo
.eltype
= ntype
.el
[0];
2147 if (skip_past_char (&p
, '[') == SUCCESS
)
2150 /* We got a scalar index. */
2152 if (typeinfo
.defined
& NTA_HASINDEX
)
2154 as_bad (_("can't redefine the index of a scalar alias"));
2158 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2160 if (exp
.X_op
!= O_constant
)
2162 as_bad (_("scalar index must be constant"));
2166 typeinfo
.defined
|= NTA_HASINDEX
;
2167 typeinfo
.index
= exp
.X_add_number
;
2169 if (skip_past_char (&p
, ']') == FAIL
)
2171 as_bad (_("expecting ]"));
2176 namelen
= nameend
- newname
;
2177 namebuf
= alloca (namelen
+ 1);
2178 strncpy (namebuf
, newname
, namelen
);
2179 namebuf
[namelen
] = '\0';
2181 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2182 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2184 /* Insert name in all uppercase. */
2185 for (p
= namebuf
; *p
; p
++)
2188 if (strncmp (namebuf
, newname
, namelen
))
2189 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2190 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2192 /* Insert name in all lowercase. */
2193 for (p
= namebuf
; *p
; p
++)
2196 if (strncmp (namebuf
, newname
, namelen
))
2197 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2198 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2203 /* Should never be called, as .req goes between the alias and the
2204 register name, not at the beginning of the line. */
2206 s_req (int a ATTRIBUTE_UNUSED
)
2208 as_bad (_("invalid syntax for .req directive"));
2212 s_dn (int a ATTRIBUTE_UNUSED
)
2214 as_bad (_("invalid syntax for .dn directive"));
2218 s_qn (int a ATTRIBUTE_UNUSED
)
2220 as_bad (_("invalid syntax for .qn directive"));
2223 /* The .unreq directive deletes an alias which was previously defined
2224 by .req. For example:
2230 s_unreq (int a ATTRIBUTE_UNUSED
)
2235 name
= input_line_pointer
;
2237 while (*input_line_pointer
!= 0
2238 && *input_line_pointer
!= ' '
2239 && *input_line_pointer
!= '\n')
2240 ++input_line_pointer
;
2242 saved_char
= *input_line_pointer
;
2243 *input_line_pointer
= 0;
2246 as_bad (_("invalid syntax for .unreq directive"));
2249 struct reg_entry
*reg
= hash_find (arm_reg_hsh
, name
);
2252 as_bad (_("unknown register alias '%s'"), name
);
2253 else if (reg
->builtin
)
2254 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2258 hash_delete (arm_reg_hsh
, name
);
2259 free ((char *) reg
->name
);
2266 *input_line_pointer
= saved_char
;
2267 demand_empty_rest_of_line ();
2270 /* Directives: Instruction set selection. */
2273 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2274 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2275 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2276 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2278 static enum mstate mapstate
= MAP_UNDEFINED
;
2281 mapping_state (enum mstate state
)
2284 const char * symname
;
2287 if (mapstate
== state
)
2288 /* The mapping symbol has already been emitted.
2289 There is nothing else to do. */
2298 type
= BSF_NO_FLAGS
;
2302 type
= BSF_NO_FLAGS
;
2306 type
= BSF_NO_FLAGS
;
2314 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2316 symbolP
= symbol_new (symname
, now_seg
, (valueT
) frag_now_fix (), frag_now
);
2317 symbol_table_insert (symbolP
);
2318 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2323 THUMB_SET_FUNC (symbolP
, 0);
2324 ARM_SET_THUMB (symbolP
, 0);
2325 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2329 THUMB_SET_FUNC (symbolP
, 1);
2330 ARM_SET_THUMB (symbolP
, 1);
2331 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2340 #define mapping_state(x) /* nothing */
2343 /* Find the real, Thumb encoded start of a Thumb function. */
2346 find_real_start (symbolS
* symbolP
)
2349 const char * name
= S_GET_NAME (symbolP
);
2350 symbolS
* new_target
;
2352 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2353 #define STUB_NAME ".real_start_of"
2358 /* The compiler may generate BL instructions to local labels because
2359 it needs to perform a branch to a far away location. These labels
2360 do not have a corresponding ".real_start_of" label. We check
2361 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2362 the ".real_start_of" convention for nonlocal branches. */
2363 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2366 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2367 new_target
= symbol_find (real_start
);
2369 if (new_target
== NULL
)
2371 as_warn ("Failed to find real start of function: %s\n", name
);
2372 new_target
= symbolP
;
2379 opcode_select (int width
)
2386 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2387 as_bad (_("selected processor does not support THUMB opcodes"));
2390 /* No need to force the alignment, since we will have been
2391 coming from ARM mode, which is word-aligned. */
2392 record_alignment (now_seg
, 1);
2394 mapping_state (MAP_THUMB
);
2400 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2401 as_bad (_("selected processor does not support ARM opcodes"));
2406 frag_align (2, 0, 0);
2408 record_alignment (now_seg
, 1);
2410 mapping_state (MAP_ARM
);
2414 as_bad (_("invalid instruction size selected (%d)"), width
);
2419 s_arm (int ignore ATTRIBUTE_UNUSED
)
2422 demand_empty_rest_of_line ();
2426 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2429 demand_empty_rest_of_line ();
2433 s_code (int unused ATTRIBUTE_UNUSED
)
2437 temp
= get_absolute_expression ();
2442 opcode_select (temp
);
2446 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2451 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2453 /* If we are not already in thumb mode go into it, EVEN if
2454 the target processor does not support thumb instructions.
2455 This is used by gcc/config/arm/lib1funcs.asm for example
2456 to compile interworking support functions even if the
2457 target processor should not support interworking. */
2461 record_alignment (now_seg
, 1);
2464 demand_empty_rest_of_line ();
2468 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2472 /* The following label is the name/address of the start of a Thumb function.
2473 We need to know this for the interworking support. */
2474 label_is_thumb_function_name
= TRUE
;
2477 /* Perform a .set directive, but also mark the alias as
2478 being a thumb function. */
2481 s_thumb_set (int equiv
)
2483 /* XXX the following is a duplicate of the code for s_set() in read.c
2484 We cannot just call that code as we need to get at the symbol that
2491 /* Especial apologies for the random logic:
2492 This just grew, and could be parsed much more simply!
2494 name
= input_line_pointer
;
2495 delim
= get_symbol_end ();
2496 end_name
= input_line_pointer
;
2499 if (*input_line_pointer
!= ',')
2502 as_bad (_("expected comma after name \"%s\""), name
);
2504 ignore_rest_of_line ();
2508 input_line_pointer
++;
2511 if (name
[0] == '.' && name
[1] == '\0')
2513 /* XXX - this should not happen to .thumb_set. */
2517 if ((symbolP
= symbol_find (name
)) == NULL
2518 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2521 /* When doing symbol listings, play games with dummy fragments living
2522 outside the normal fragment chain to record the file and line info
2524 if (listing
& LISTING_SYMBOLS
)
2526 extern struct list_info_struct
* listing_tail
;
2527 fragS
* dummy_frag
= xmalloc (sizeof (fragS
));
2529 memset (dummy_frag
, 0, sizeof (fragS
));
2530 dummy_frag
->fr_type
= rs_fill
;
2531 dummy_frag
->line
= listing_tail
;
2532 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2533 dummy_frag
->fr_symbol
= symbolP
;
2537 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2540 /* "set" symbols are local unless otherwise specified. */
2541 SF_SET_LOCAL (symbolP
);
2542 #endif /* OBJ_COFF */
2543 } /* Make a new symbol. */
2545 symbol_table_insert (symbolP
);
2550 && S_IS_DEFINED (symbolP
)
2551 && S_GET_SEGMENT (symbolP
) != reg_section
)
2552 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2554 pseudo_set (symbolP
);
2556 demand_empty_rest_of_line ();
2558 /* XXX Now we come to the Thumb specific bit of code. */
2560 THUMB_SET_FUNC (symbolP
, 1);
2561 ARM_SET_THUMB (symbolP
, 1);
2562 #if defined OBJ_ELF || defined OBJ_COFF
2563 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2567 /* Directives: Mode selection. */
2569 /* .syntax [unified|divided] - choose the new unified syntax
2570 (same for Arm and Thumb encoding, modulo slight differences in what
2571 can be represented) or the old divergent syntax for each mode. */
2573 s_syntax (int unused ATTRIBUTE_UNUSED
)
2577 name
= input_line_pointer
;
2578 delim
= get_symbol_end ();
2580 if (!strcasecmp (name
, "unified"))
2581 unified_syntax
= TRUE
;
2582 else if (!strcasecmp (name
, "divided"))
2583 unified_syntax
= FALSE
;
2586 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2589 *input_line_pointer
= delim
;
2590 demand_empty_rest_of_line ();
2593 /* Directives: sectioning and alignment. */
2595 /* Same as s_align_ptwo but align 0 => align 2. */
2598 s_align (int unused ATTRIBUTE_UNUSED
)
2602 long max_alignment
= 15;
2604 temp
= get_absolute_expression ();
2605 if (temp
> max_alignment
)
2606 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2609 as_bad (_("alignment negative. 0 assumed."));
2613 if (*input_line_pointer
== ',')
2615 input_line_pointer
++;
2616 temp_fill
= get_absolute_expression ();
2624 /* Only make a frag if we HAVE to. */
2625 if (temp
&& !need_pass_2
)
2626 frag_align (temp
, (int) temp_fill
, 0);
2627 demand_empty_rest_of_line ();
2629 record_alignment (now_seg
, temp
);
2633 s_bss (int ignore ATTRIBUTE_UNUSED
)
2635 /* We don't support putting frags in the BSS segment, we fake it by
2636 marking in_bss, then looking at s_skip for clues. */
2637 subseg_set (bss_section
, 0);
2638 demand_empty_rest_of_line ();
2639 mapping_state (MAP_DATA
);
2643 s_even (int ignore ATTRIBUTE_UNUSED
)
2645 /* Never make frag if expect extra pass. */
2647 frag_align (1, 0, 0);
2649 record_alignment (now_seg
, 1);
2651 demand_empty_rest_of_line ();
2654 /* Directives: Literal pools. */
2656 static literal_pool
*
2657 find_literal_pool (void)
2659 literal_pool
* pool
;
2661 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2663 if (pool
->section
== now_seg
2664 && pool
->sub_section
== now_subseg
)
2671 static literal_pool
*
2672 find_or_make_literal_pool (void)
2674 /* Next literal pool ID number. */
2675 static unsigned int latest_pool_num
= 1;
2676 literal_pool
* pool
;
2678 pool
= find_literal_pool ();
2682 /* Create a new pool. */
2683 pool
= xmalloc (sizeof (* pool
));
2687 pool
->next_free_entry
= 0;
2688 pool
->section
= now_seg
;
2689 pool
->sub_section
= now_subseg
;
2690 pool
->next
= list_of_pools
;
2691 pool
->symbol
= NULL
;
2693 /* Add it to the list. */
2694 list_of_pools
= pool
;
2697 /* New pools, and emptied pools, will have a NULL symbol. */
2698 if (pool
->symbol
== NULL
)
2700 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2701 (valueT
) 0, &zero_address_frag
);
2702 pool
->id
= latest_pool_num
++;
2709 /* Add the literal in the global 'inst'
2710 structure to the relevent literal pool. */
2713 add_to_lit_pool (void)
2715 literal_pool
* pool
;
2718 pool
= find_or_make_literal_pool ();
2720 /* Check if this literal value is already in the pool. */
2721 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2723 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2724 && (inst
.reloc
.exp
.X_op
== O_constant
)
2725 && (pool
->literals
[entry
].X_add_number
2726 == inst
.reloc
.exp
.X_add_number
)
2727 && (pool
->literals
[entry
].X_unsigned
2728 == inst
.reloc
.exp
.X_unsigned
))
2731 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2732 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2733 && (pool
->literals
[entry
].X_add_number
2734 == inst
.reloc
.exp
.X_add_number
)
2735 && (pool
->literals
[entry
].X_add_symbol
2736 == inst
.reloc
.exp
.X_add_symbol
)
2737 && (pool
->literals
[entry
].X_op_symbol
2738 == inst
.reloc
.exp
.X_op_symbol
))
2742 /* Do we need to create a new entry? */
2743 if (entry
== pool
->next_free_entry
)
2745 if (entry
>= MAX_LITERAL_POOL_SIZE
)
2747 inst
.error
= _("literal pool overflow");
2751 pool
->literals
[entry
] = inst
.reloc
.exp
;
2752 pool
->next_free_entry
+= 1;
2755 inst
.reloc
.exp
.X_op
= O_symbol
;
2756 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
2757 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
2762 /* Can't use symbol_new here, so have to create a symbol and then at
2763 a later date assign it a value. Thats what these functions do. */
2766 symbol_locate (symbolS
* symbolP
,
2767 const char * name
, /* It is copied, the caller can modify. */
2768 segT segment
, /* Segment identifier (SEG_<something>). */
2769 valueT valu
, /* Symbol value. */
2770 fragS
* frag
) /* Associated fragment. */
2772 unsigned int name_length
;
2773 char * preserved_copy_of_name
;
2775 name_length
= strlen (name
) + 1; /* +1 for \0. */
2776 obstack_grow (¬es
, name
, name_length
);
2777 preserved_copy_of_name
= obstack_finish (¬es
);
2779 #ifdef tc_canonicalize_symbol_name
2780 preserved_copy_of_name
=
2781 tc_canonicalize_symbol_name (preserved_copy_of_name
);
2784 S_SET_NAME (symbolP
, preserved_copy_of_name
);
2786 S_SET_SEGMENT (symbolP
, segment
);
2787 S_SET_VALUE (symbolP
, valu
);
2788 symbol_clear_list_pointers (symbolP
);
2790 symbol_set_frag (symbolP
, frag
);
2792 /* Link to end of symbol chain. */
2794 extern int symbol_table_frozen
;
2796 if (symbol_table_frozen
)
2800 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
2802 obj_symbol_new_hook (symbolP
);
2804 #ifdef tc_symbol_new_hook
2805 tc_symbol_new_hook (symbolP
);
2809 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
2810 #endif /* DEBUG_SYMS */
2815 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
2818 literal_pool
* pool
;
2821 pool
= find_literal_pool ();
2823 || pool
->symbol
== NULL
2824 || pool
->next_free_entry
== 0)
2827 mapping_state (MAP_DATA
);
2829 /* Align pool as you have word accesses.
2830 Only make a frag if we have to. */
2832 frag_align (2, 0, 0);
2834 record_alignment (now_seg
, 2);
2836 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
2838 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
2839 (valueT
) frag_now_fix (), frag_now
);
2840 symbol_table_insert (pool
->symbol
);
2842 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
2844 #if defined OBJ_COFF || defined OBJ_ELF
2845 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
2848 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2849 /* First output the expression in the instruction to the pool. */
2850 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
2852 /* Mark the pool as empty. */
2853 pool
->next_free_entry
= 0;
2854 pool
->symbol
= NULL
;
2858 /* Forward declarations for functions below, in the MD interface
2860 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
2861 static valueT
create_unwind_entry (int);
2862 static void start_unwind_section (const segT
, int);
2863 static void add_unwind_opcode (valueT
, int);
2864 static void flush_pending_unwind (void);
2866 /* Directives: Data. */
2869 s_arm_elf_cons (int nbytes
)
2873 #ifdef md_flush_pending_output
2874 md_flush_pending_output ();
2877 if (is_it_end_of_statement ())
2879 demand_empty_rest_of_line ();
2883 #ifdef md_cons_align
2884 md_cons_align (nbytes
);
2887 mapping_state (MAP_DATA
);
2891 char *base
= input_line_pointer
;
2895 if (exp
.X_op
!= O_symbol
)
2896 emit_expr (&exp
, (unsigned int) nbytes
);
2899 char *before_reloc
= input_line_pointer
;
2900 reloc
= parse_reloc (&input_line_pointer
);
2903 as_bad (_("unrecognized relocation suffix"));
2904 ignore_rest_of_line ();
2907 else if (reloc
== BFD_RELOC_UNUSED
)
2908 emit_expr (&exp
, (unsigned int) nbytes
);
2911 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
2912 int size
= bfd_get_reloc_size (howto
);
2914 if (reloc
== BFD_RELOC_ARM_PLT32
)
2916 as_bad (_("(plt) is only valid on branch targets"));
2917 reloc
= BFD_RELOC_UNUSED
;
2922 as_bad (_("%s relocations do not fit in %d bytes"),
2923 howto
->name
, nbytes
);
2926 /* We've parsed an expression stopping at O_symbol.
2927 But there may be more expression left now that we
2928 have parsed the relocation marker. Parse it again.
2929 XXX Surely there is a cleaner way to do this. */
2930 char *p
= input_line_pointer
;
2932 char *save_buf
= alloca (input_line_pointer
- base
);
2933 memcpy (save_buf
, base
, input_line_pointer
- base
);
2934 memmove (base
+ (input_line_pointer
- before_reloc
),
2935 base
, before_reloc
- base
);
2937 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
2939 memcpy (base
, save_buf
, p
- base
);
2941 offset
= nbytes
- size
;
2942 p
= frag_more ((int) nbytes
);
2943 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
2944 size
, &exp
, 0, reloc
);
2949 while (*input_line_pointer
++ == ',');
2951 /* Put terminator back into stream. */
2952 input_line_pointer
--;
2953 demand_empty_rest_of_line ();
2957 /* Parse a .rel31 directive. */
2960 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
2967 if (*input_line_pointer
== '1')
2968 highbit
= 0x80000000;
2969 else if (*input_line_pointer
!= '0')
2970 as_bad (_("expected 0 or 1"));
2972 input_line_pointer
++;
2973 if (*input_line_pointer
!= ',')
2974 as_bad (_("missing comma"));
2975 input_line_pointer
++;
2977 #ifdef md_flush_pending_output
2978 md_flush_pending_output ();
2981 #ifdef md_cons_align
2985 mapping_state (MAP_DATA
);
2990 md_number_to_chars (p
, highbit
, 4);
2991 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
2992 BFD_RELOC_ARM_PREL31
);
2994 demand_empty_rest_of_line ();
2997 /* Directives: AEABI stack-unwind tables. */
2999 /* Parse an unwind_fnstart directive. Simply records the current location. */
3002 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3004 demand_empty_rest_of_line ();
3005 /* Mark the start of the function. */
3006 unwind
.proc_start
= expr_build_dot ();
3008 /* Reset the rest of the unwind info. */
3009 unwind
.opcode_count
= 0;
3010 unwind
.table_entry
= NULL
;
3011 unwind
.personality_routine
= NULL
;
3012 unwind
.personality_index
= -1;
3013 unwind
.frame_size
= 0;
3014 unwind
.fp_offset
= 0;
3017 unwind
.sp_restored
= 0;
3021 /* Parse a handlerdata directive. Creates the exception handling table entry
3022 for the function. */
3025 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3027 demand_empty_rest_of_line ();
3028 if (unwind
.table_entry
)
3029 as_bad (_("dupicate .handlerdata directive"));
3031 create_unwind_entry (1);
3034 /* Parse an unwind_fnend directive. Generates the index table entry. */
3037 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3043 demand_empty_rest_of_line ();
3045 /* Add eh table entry. */
3046 if (unwind
.table_entry
== NULL
)
3047 val
= create_unwind_entry (0);
3051 /* Add index table entry. This is two words. */
3052 start_unwind_section (unwind
.saved_seg
, 1);
3053 frag_align (2, 0, 0);
3054 record_alignment (now_seg
, 2);
3056 ptr
= frag_more (8);
3057 where
= frag_now_fix () - 8;
3059 /* Self relative offset of the function start. */
3060 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3061 BFD_RELOC_ARM_PREL31
);
3063 /* Indicate dependency on EHABI-defined personality routines to the
3064 linker, if it hasn't been done already. */
3065 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3066 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3068 static const char *const name
[] = {
3069 "__aeabi_unwind_cpp_pr0",
3070 "__aeabi_unwind_cpp_pr1",
3071 "__aeabi_unwind_cpp_pr2"
3073 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3074 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3075 marked_pr_dependency
|= 1 << unwind
.personality_index
;
3076 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3077 = marked_pr_dependency
;
3081 /* Inline exception table entry. */
3082 md_number_to_chars (ptr
+ 4, val
, 4);
3084 /* Self relative offset of the table entry. */
3085 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3086 BFD_RELOC_ARM_PREL31
);
3088 /* Restore the original section. */
3089 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3093 /* Parse an unwind_cantunwind directive. */
3096 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3098 demand_empty_rest_of_line ();
3099 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3100 as_bad (_("personality routine specified for cantunwind frame"));
3102 unwind
.personality_index
= -2;
3106 /* Parse a personalityindex directive. */
3109 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3113 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3114 as_bad (_("duplicate .personalityindex directive"));
3118 if (exp
.X_op
!= O_constant
3119 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3121 as_bad (_("bad personality routine number"));
3122 ignore_rest_of_line ();
3126 unwind
.personality_index
= exp
.X_add_number
;
3128 demand_empty_rest_of_line ();
3132 /* Parse a personality directive. */
3135 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3139 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3140 as_bad (_("duplicate .personality directive"));
3142 name
= input_line_pointer
;
3143 c
= get_symbol_end ();
3144 p
= input_line_pointer
;
3145 unwind
.personality_routine
= symbol_find_or_make (name
);
3147 demand_empty_rest_of_line ();
3151 /* Parse a directive saving core registers. */
3154 s_arm_unwind_save_core (void)
3160 range
= parse_reg_list (&input_line_pointer
);
3163 as_bad (_("expected register list"));
3164 ignore_rest_of_line ();
3168 demand_empty_rest_of_line ();
3170 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3171 into .unwind_save {..., sp...}. We aren't bothered about the value of
3172 ip because it is clobbered by calls. */
3173 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3174 && (range
& 0x3000) == 0x1000)
3176 unwind
.opcode_count
--;
3177 unwind
.sp_restored
= 0;
3178 range
= (range
| 0x2000) & ~0x1000;
3179 unwind
.pending_offset
= 0;
3185 /* See if we can use the short opcodes. These pop a block of up to 8
3186 registers starting with r4, plus maybe r14. */
3187 for (n
= 0; n
< 8; n
++)
3189 /* Break at the first non-saved register. */
3190 if ((range
& (1 << (n
+ 4))) == 0)
3193 /* See if there are any other bits set. */
3194 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3196 /* Use the long form. */
3197 op
= 0x8000 | ((range
>> 4) & 0xfff);
3198 add_unwind_opcode (op
, 2);
3202 /* Use the short form. */
3204 op
= 0xa8; /* Pop r14. */
3206 op
= 0xa0; /* Do not pop r14. */
3208 add_unwind_opcode (op
, 1);
3215 op
= 0xb100 | (range
& 0xf);
3216 add_unwind_opcode (op
, 2);
3219 /* Record the number of bytes pushed. */
3220 for (n
= 0; n
< 16; n
++)
3222 if (range
& (1 << n
))
3223 unwind
.frame_size
+= 4;
3228 /* Parse a directive saving FPA registers. */
3231 s_arm_unwind_save_fpa (int reg
)
3237 /* Get Number of registers to transfer. */
3238 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3241 exp
.X_op
= O_illegal
;
3243 if (exp
.X_op
!= O_constant
)
3245 as_bad (_("expected , <constant>"));
3246 ignore_rest_of_line ();
3250 num_regs
= exp
.X_add_number
;
3252 if (num_regs
< 1 || num_regs
> 4)
3254 as_bad (_("number of registers must be in the range [1:4]"));
3255 ignore_rest_of_line ();
3259 demand_empty_rest_of_line ();
3264 op
= 0xb4 | (num_regs
- 1);
3265 add_unwind_opcode (op
, 1);
3270 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3271 add_unwind_opcode (op
, 2);
3273 unwind
.frame_size
+= num_regs
* 12;
3277 /* Parse a directive saving VFP registers for ARMv6 and above. */
3280 s_arm_unwind_save_vfp_armv6 (void)
3285 int num_vfpv3_regs
= 0;
3286 int num_regs_below_16
;
3288 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3291 as_bad (_("expected register list"));
3292 ignore_rest_of_line ();
3296 demand_empty_rest_of_line ();
3298 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3299 than FSTMX/FLDMX-style ones). */
3301 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3303 num_vfpv3_regs
= count
;
3304 else if (start
+ count
> 16)
3305 num_vfpv3_regs
= start
+ count
- 16;
3307 if (num_vfpv3_regs
> 0)
3309 int start_offset
= start
> 16 ? start
- 16 : 0;
3310 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3311 add_unwind_opcode (op
, 2);
3314 /* Generate opcode for registers numbered in the range 0 .. 15. */
3315 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3316 assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3317 if (num_regs_below_16
> 0)
3319 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3320 add_unwind_opcode (op
, 2);
3323 unwind
.frame_size
+= count
* 8;
3327 /* Parse a directive saving VFP registers for pre-ARMv6. */
3330 s_arm_unwind_save_vfp (void)
3336 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3339 as_bad (_("expected register list"));
3340 ignore_rest_of_line ();
3344 demand_empty_rest_of_line ();
3349 op
= 0xb8 | (count
- 1);
3350 add_unwind_opcode (op
, 1);
3355 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3356 add_unwind_opcode (op
, 2);
3358 unwind
.frame_size
+= count
* 8 + 4;
3362 /* Parse a directive saving iWMMXt data registers. */
3365 s_arm_unwind_save_mmxwr (void)
3373 if (*input_line_pointer
== '{')
3374 input_line_pointer
++;
3378 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3382 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3387 as_tsktsk (_("register list not in ascending order"));
3390 if (*input_line_pointer
== '-')
3392 input_line_pointer
++;
3393 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3396 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3399 else if (reg
>= hi_reg
)
3401 as_bad (_("bad register range"));
3404 for (; reg
< hi_reg
; reg
++)
3408 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3410 if (*input_line_pointer
== '}')
3411 input_line_pointer
++;
3413 demand_empty_rest_of_line ();
3415 /* Generate any deferred opcodes because we're going to be looking at
3417 flush_pending_unwind ();
3419 for (i
= 0; i
< 16; i
++)
3421 if (mask
& (1 << i
))
3422 unwind
.frame_size
+= 8;
3425 /* Attempt to combine with a previous opcode. We do this because gcc
3426 likes to output separate unwind directives for a single block of
3428 if (unwind
.opcode_count
> 0)
3430 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3431 if ((i
& 0xf8) == 0xc0)
3434 /* Only merge if the blocks are contiguous. */
3437 if ((mask
& 0xfe00) == (1 << 9))
3439 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3440 unwind
.opcode_count
--;
3443 else if (i
== 6 && unwind
.opcode_count
>= 2)
3445 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3449 op
= 0xffff << (reg
- 1);
3451 || ((mask
& op
) == (1u << (reg
- 1))))
3453 op
= (1 << (reg
+ i
+ 1)) - 1;
3454 op
&= ~((1 << reg
) - 1);
3456 unwind
.opcode_count
-= 2;
3463 /* We want to generate opcodes in the order the registers have been
3464 saved, ie. descending order. */
3465 for (reg
= 15; reg
>= -1; reg
--)
3467 /* Save registers in blocks. */
3469 || !(mask
& (1 << reg
)))
3471 /* We found an unsaved reg. Generate opcodes to save the
3472 preceeding block. */
3478 op
= 0xc0 | (hi_reg
- 10);
3479 add_unwind_opcode (op
, 1);
3484 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3485 add_unwind_opcode (op
, 2);
3494 ignore_rest_of_line ();
3498 s_arm_unwind_save_mmxwcg (void)
3505 if (*input_line_pointer
== '{')
3506 input_line_pointer
++;
3510 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3514 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3520 as_tsktsk (_("register list not in ascending order"));
3523 if (*input_line_pointer
== '-')
3525 input_line_pointer
++;
3526 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3529 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3532 else if (reg
>= hi_reg
)
3534 as_bad (_("bad register range"));
3537 for (; reg
< hi_reg
; reg
++)
3541 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3543 if (*input_line_pointer
== '}')
3544 input_line_pointer
++;
3546 demand_empty_rest_of_line ();
3548 /* Generate any deferred opcodes because we're going to be looking at
3550 flush_pending_unwind ();
3552 for (reg
= 0; reg
< 16; reg
++)
3554 if (mask
& (1 << reg
))
3555 unwind
.frame_size
+= 4;
3558 add_unwind_opcode (op
, 2);
3561 ignore_rest_of_line ();
3565 /* Parse an unwind_save directive.
3566 If the argument is non-zero, this is a .vsave directive. */
3569 s_arm_unwind_save (int arch_v6
)
3572 struct reg_entry
*reg
;
3573 bfd_boolean had_brace
= FALSE
;
3575 /* Figure out what sort of save we have. */
3576 peek
= input_line_pointer
;
3584 reg
= arm_reg_parse_multi (&peek
);
3588 as_bad (_("register expected"));
3589 ignore_rest_of_line ();
3598 as_bad (_("FPA .unwind_save does not take a register list"));
3599 ignore_rest_of_line ();
3602 s_arm_unwind_save_fpa (reg
->number
);
3605 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
3608 s_arm_unwind_save_vfp_armv6 ();
3610 s_arm_unwind_save_vfp ();
3612 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
3613 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
3616 as_bad (_(".unwind_save does not support this kind of register"));
3617 ignore_rest_of_line ();
3622 /* Parse an unwind_movsp directive. */
3625 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
3630 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3633 as_bad (_(reg_expected_msgs
[REG_TYPE_RN
]));
3634 ignore_rest_of_line ();
3637 demand_empty_rest_of_line ();
3639 if (reg
== REG_SP
|| reg
== REG_PC
)
3641 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
3645 if (unwind
.fp_reg
!= REG_SP
)
3646 as_bad (_("unexpected .unwind_movsp directive"));
3648 /* Generate opcode to restore the value. */
3650 add_unwind_opcode (op
, 1);
3652 /* Record the information for later. */
3653 unwind
.fp_reg
= reg
;
3654 unwind
.fp_offset
= unwind
.frame_size
;
3655 unwind
.sp_restored
= 1;
3658 /* Parse an unwind_pad directive. */
3661 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
3665 if (immediate_for_directive (&offset
) == FAIL
)
3670 as_bad (_("stack increment must be multiple of 4"));
3671 ignore_rest_of_line ();
3675 /* Don't generate any opcodes, just record the details for later. */
3676 unwind
.frame_size
+= offset
;
3677 unwind
.pending_offset
+= offset
;
3679 demand_empty_rest_of_line ();
3682 /* Parse an unwind_setfp directive. */
3685 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
3691 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3692 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3695 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3697 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
3699 as_bad (_("expected <reg>, <reg>"));
3700 ignore_rest_of_line ();
3704 /* Optional constant. */
3705 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3707 if (immediate_for_directive (&offset
) == FAIL
)
3713 demand_empty_rest_of_line ();
3715 if (sp_reg
!= 13 && sp_reg
!= unwind
.fp_reg
)
3717 as_bad (_("register must be either sp or set by a previous"
3718 "unwind_movsp directive"));
3722 /* Don't generate any opcodes, just record the information for later. */
3723 unwind
.fp_reg
= fp_reg
;
3726 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3728 unwind
.fp_offset
-= offset
;
3731 /* Parse an unwind_raw directive. */
3734 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
3737 /* This is an arbitrary limit. */
3738 unsigned char op
[16];
3742 if (exp
.X_op
== O_constant
3743 && skip_past_comma (&input_line_pointer
) != FAIL
)
3745 unwind
.frame_size
+= exp
.X_add_number
;
3749 exp
.X_op
= O_illegal
;
3751 if (exp
.X_op
!= O_constant
)
3753 as_bad (_("expected <offset>, <opcode>"));
3754 ignore_rest_of_line ();
3760 /* Parse the opcode. */
3765 as_bad (_("unwind opcode too long"));
3766 ignore_rest_of_line ();
3768 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
3770 as_bad (_("invalid unwind opcode"));
3771 ignore_rest_of_line ();
3774 op
[count
++] = exp
.X_add_number
;
3776 /* Parse the next byte. */
3777 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3783 /* Add the opcode bytes in reverse order. */
3785 add_unwind_opcode (op
[count
], 1);
3787 demand_empty_rest_of_line ();
3791 /* Parse a .eabi_attribute directive. */
3794 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
3797 bfd_boolean is_string
;
3804 if (exp
.X_op
!= O_constant
)
3807 tag
= exp
.X_add_number
;
3808 if (tag
== 4 || tag
== 5 || tag
== 32 || (tag
> 32 && (tag
& 1) != 0))
3813 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3815 if (tag
== 32 || !is_string
)
3818 if (exp
.X_op
!= O_constant
)
3820 as_bad (_("expected numeric constant"));
3821 ignore_rest_of_line ();
3824 i
= exp
.X_add_number
;
3826 if (tag
== Tag_compatibility
3827 && skip_past_comma (&input_line_pointer
) == FAIL
)
3829 as_bad (_("expected comma"));
3830 ignore_rest_of_line ();
3835 skip_whitespace(input_line_pointer
);
3836 if (*input_line_pointer
!= '"')
3838 input_line_pointer
++;
3839 s
= input_line_pointer
;
3840 while (*input_line_pointer
&& *input_line_pointer
!= '"')
3841 input_line_pointer
++;
3842 if (*input_line_pointer
!= '"')
3844 saved_char
= *input_line_pointer
;
3845 *input_line_pointer
= 0;
3853 if (tag
== Tag_compatibility
)
3854 elf32_arm_add_eabi_attr_compat (stdoutput
, i
, s
);
3856 elf32_arm_add_eabi_attr_string (stdoutput
, tag
, s
);
3858 elf32_arm_add_eabi_attr_int (stdoutput
, tag
, i
);
3862 *input_line_pointer
= saved_char
;
3863 input_line_pointer
++;
3865 demand_empty_rest_of_line ();
3868 as_bad (_("bad string constant"));
3869 ignore_rest_of_line ();
3872 as_bad (_("expected <tag> , <value>"));
3873 ignore_rest_of_line ();
3875 #endif /* OBJ_ELF */
3877 static void s_arm_arch (int);
3878 static void s_arm_cpu (int);
3879 static void s_arm_fpu (int);
3881 /* This table describes all the machine specific pseudo-ops the assembler
3882 has to support. The fields are:
3883 pseudo-op name without dot
3884 function to call to execute this pseudo-op
3885 Integer arg to pass to the function. */
3887 const pseudo_typeS md_pseudo_table
[] =
3889 /* Never called because '.req' does not start a line. */
3890 { "req", s_req
, 0 },
3891 /* Following two are likewise never called. */
3894 { "unreq", s_unreq
, 0 },
3895 { "bss", s_bss
, 0 },
3896 { "align", s_align
, 0 },
3897 { "arm", s_arm
, 0 },
3898 { "thumb", s_thumb
, 0 },
3899 { "code", s_code
, 0 },
3900 { "force_thumb", s_force_thumb
, 0 },
3901 { "thumb_func", s_thumb_func
, 0 },
3902 { "thumb_set", s_thumb_set
, 0 },
3903 { "even", s_even
, 0 },
3904 { "ltorg", s_ltorg
, 0 },
3905 { "pool", s_ltorg
, 0 },
3906 { "syntax", s_syntax
, 0 },
3907 { "cpu", s_arm_cpu
, 0 },
3908 { "arch", s_arm_arch
, 0 },
3909 { "fpu", s_arm_fpu
, 0 },
3911 { "word", s_arm_elf_cons
, 4 },
3912 { "long", s_arm_elf_cons
, 4 },
3913 { "rel31", s_arm_rel31
, 0 },
3914 { "fnstart", s_arm_unwind_fnstart
, 0 },
3915 { "fnend", s_arm_unwind_fnend
, 0 },
3916 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
3917 { "personality", s_arm_unwind_personality
, 0 },
3918 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
3919 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
3920 { "save", s_arm_unwind_save
, 0 },
3921 { "vsave", s_arm_unwind_save
, 1 },
3922 { "movsp", s_arm_unwind_movsp
, 0 },
3923 { "pad", s_arm_unwind_pad
, 0 },
3924 { "setfp", s_arm_unwind_setfp
, 0 },
3925 { "unwind_raw", s_arm_unwind_raw
, 0 },
3926 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
3930 { "extend", float_cons
, 'x' },
3931 { "ldouble", float_cons
, 'x' },
3932 { "packed", float_cons
, 'p' },
3936 /* Parser functions used exclusively in instruction operands. */
3938 /* Generic immediate-value read function for use in insn parsing.
3939 STR points to the beginning of the immediate (the leading #);
3940 VAL receives the value; if the value is outside [MIN, MAX]
3941 issue an error. PREFIX_OPT is true if the immediate prefix is
3945 parse_immediate (char **str
, int *val
, int min
, int max
,
3946 bfd_boolean prefix_opt
)
3949 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
3950 if (exp
.X_op
!= O_constant
)
3952 inst
.error
= _("constant expression required");
3956 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
3958 inst
.error
= _("immediate value out of range");
3962 *val
= exp
.X_add_number
;
3966 /* Less-generic immediate-value read function with the possibility of loading a
3967 big (64-bit) immediate, as required by Neon VMOV and VMVN immediate
3968 instructions. Puts the result directly in inst.operands[i]. */
3971 parse_big_immediate (char **str
, int i
)
3976 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
3978 if (exp
.X_op
== O_constant
)
3979 inst
.operands
[i
].imm
= exp
.X_add_number
;
3980 else if (exp
.X_op
== O_big
3981 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
3982 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
3984 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
3985 /* Bignums have their least significant bits in
3986 generic_bignum[0]. Make sure we put 32 bits in imm and
3987 32 bits in reg, in a (hopefully) portable way. */
3988 assert (parts
!= 0);
3989 inst
.operands
[i
].imm
= 0;
3990 for (j
= 0; j
< parts
; j
++, idx
++)
3991 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
3992 << (LITTLENUM_NUMBER_OF_BITS
* j
);
3993 inst
.operands
[i
].reg
= 0;
3994 for (j
= 0; j
< parts
; j
++, idx
++)
3995 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
3996 << (LITTLENUM_NUMBER_OF_BITS
* j
);
3997 inst
.operands
[i
].regisimm
= 1;
4007 /* Returns the pseudo-register number of an FPA immediate constant,
4008 or FAIL if there isn't a valid constant here. */
4011 parse_fpa_immediate (char ** str
)
4013 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4019 /* First try and match exact strings, this is to guarantee
4020 that some formats will work even for cross assembly. */
4022 for (i
= 0; fp_const
[i
]; i
++)
4024 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4028 *str
+= strlen (fp_const
[i
]);
4029 if (is_end_of_line
[(unsigned char) **str
])
4035 /* Just because we didn't get a match doesn't mean that the constant
4036 isn't valid, just that it is in a format that we don't
4037 automatically recognize. Try parsing it with the standard
4038 expression routines. */
4040 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4042 /* Look for a raw floating point number. */
4043 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4044 && is_end_of_line
[(unsigned char) *save_in
])
4046 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4048 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4050 if (words
[j
] != fp_values
[i
][j
])
4054 if (j
== MAX_LITTLENUMS
)
4062 /* Try and parse a more complex expression, this will probably fail
4063 unless the code uses a floating point prefix (eg "0f"). */
4064 save_in
= input_line_pointer
;
4065 input_line_pointer
= *str
;
4066 if (expression (&exp
) == absolute_section
4067 && exp
.X_op
== O_big
4068 && exp
.X_add_number
< 0)
4070 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4072 if (gen_to_words (words
, 5, (long) 15) == 0)
4074 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4076 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4078 if (words
[j
] != fp_values
[i
][j
])
4082 if (j
== MAX_LITTLENUMS
)
4084 *str
= input_line_pointer
;
4085 input_line_pointer
= save_in
;
4092 *str
= input_line_pointer
;
4093 input_line_pointer
= save_in
;
4094 inst
.error
= _("invalid FPA immediate expression");
4098 /* Returns 1 if a number has "quarter-precision" float format
4099 0baBbbbbbc defgh000 00000000 00000000. */
4102 is_quarter_float (unsigned imm
)
4104 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4105 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4108 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4109 0baBbbbbbc defgh000 00000000 00000000.
4110 The minus-zero case needs special handling, since it can't be encoded in the
4111 "quarter-precision" float format, but can nonetheless be loaded as an integer
4115 parse_qfloat_immediate (char **ccp
, int *immed
)
4118 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4120 skip_past_char (&str
, '#');
4122 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4124 unsigned fpword
= 0;
4127 /* Our FP word must be 32 bits (single-precision FP). */
4128 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4130 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4134 if (is_quarter_float (fpword
) || fpword
== 0x80000000)
4147 /* Shift operands. */
4150 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4153 struct asm_shift_name
4156 enum shift_kind kind
;
4159 /* Third argument to parse_shift. */
4160 enum parse_shift_mode
4162 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4163 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4164 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4165 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4166 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4169 /* Parse a <shift> specifier on an ARM data processing instruction.
4170 This has three forms:
4172 (LSL|LSR|ASL|ASR|ROR) Rs
4173 (LSL|LSR|ASL|ASR|ROR) #imm
4176 Note that ASL is assimilated to LSL in the instruction encoding, and
4177 RRX to ROR #0 (which cannot be written as such). */
4180 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4182 const struct asm_shift_name
*shift_name
;
4183 enum shift_kind shift
;
4188 for (p
= *str
; ISALPHA (*p
); p
++)
4193 inst
.error
= _("shift expression expected");
4197 shift_name
= hash_find_n (arm_shift_hsh
, *str
, p
- *str
);
4199 if (shift_name
== NULL
)
4201 inst
.error
= _("shift expression expected");
4205 shift
= shift_name
->kind
;
4209 case NO_SHIFT_RESTRICT
:
4210 case SHIFT_IMMEDIATE
: break;
4212 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4213 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4215 inst
.error
= _("'LSL' or 'ASR' required");
4220 case SHIFT_LSL_IMMEDIATE
:
4221 if (shift
!= SHIFT_LSL
)
4223 inst
.error
= _("'LSL' required");
4228 case SHIFT_ASR_IMMEDIATE
:
4229 if (shift
!= SHIFT_ASR
)
4231 inst
.error
= _("'ASR' required");
4239 if (shift
!= SHIFT_RRX
)
4241 /* Whitespace can appear here if the next thing is a bare digit. */
4242 skip_whitespace (p
);
4244 if (mode
== NO_SHIFT_RESTRICT
4245 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4247 inst
.operands
[i
].imm
= reg
;
4248 inst
.operands
[i
].immisreg
= 1;
4250 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4253 inst
.operands
[i
].shift_kind
= shift
;
4254 inst
.operands
[i
].shifted
= 1;
4259 /* Parse a <shifter_operand> for an ARM data processing instruction:
4262 #<immediate>, <rotate>
4266 where <shift> is defined by parse_shift above, and <rotate> is a
4267 multiple of 2 between 0 and 30. Validation of immediate operands
4268 is deferred to md_apply_fix. */
4271 parse_shifter_operand (char **str
, int i
)
4276 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4278 inst
.operands
[i
].reg
= value
;
4279 inst
.operands
[i
].isreg
= 1;
4281 /* parse_shift will override this if appropriate */
4282 inst
.reloc
.exp
.X_op
= O_constant
;
4283 inst
.reloc
.exp
.X_add_number
= 0;
4285 if (skip_past_comma (str
) == FAIL
)
4288 /* Shift operation on register. */
4289 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4292 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4295 if (skip_past_comma (str
) == SUCCESS
)
4297 /* #x, y -- ie explicit rotation by Y. */
4298 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
4301 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4303 inst
.error
= _("constant expression expected");
4307 value
= expr
.X_add_number
;
4308 if (value
< 0 || value
> 30 || value
% 2 != 0)
4310 inst
.error
= _("invalid rotation");
4313 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4315 inst
.error
= _("invalid constant");
4319 /* Convert to decoded value. md_apply_fix will put it back. */
4320 inst
.reloc
.exp
.X_add_number
4321 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4322 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4325 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4326 inst
.reloc
.pc_rel
= 0;
4330 /* Group relocation information. Each entry in the table contains the
4331 textual name of the relocation as may appear in assembler source
4332 and must end with a colon.
4333 Along with this textual name are the relocation codes to be used if
4334 the corresponding instruction is an ALU instruction (ADD or SUB only),
4335 an LDR, an LDRS, or an LDC. */
4337 struct group_reloc_table_entry
4348 /* Varieties of non-ALU group relocation. */
4355 static struct group_reloc_table_entry group_reloc_table
[] =
4356 { /* Program counter relative: */
4358 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4363 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4364 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4365 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4366 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4368 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4373 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4374 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4375 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4376 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4378 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4379 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4380 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4381 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4382 /* Section base relative */
4384 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4389 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4390 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4391 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4392 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4394 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4399 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4400 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4401 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4402 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4404 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4405 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4406 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4407 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4409 /* Given the address of a pointer pointing to the textual name of a group
4410 relocation as may appear in assembler source, attempt to find its details
4411 in group_reloc_table. The pointer will be updated to the character after
4412 the trailing colon. On failure, FAIL will be returned; SUCCESS
4413 otherwise. On success, *entry will be updated to point at the relevant
4414 group_reloc_table entry. */
4417 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4420 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4422 int length
= strlen (group_reloc_table
[i
].name
);
4424 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0 &&
4425 (*str
)[length
] == ':')
4427 *out
= &group_reloc_table
[i
];
4428 *str
+= (length
+ 1);
4436 /* Parse a <shifter_operand> for an ARM data processing instruction
4437 (as for parse_shifter_operand) where group relocations are allowed:
4440 #<immediate>, <rotate>
4441 #:<group_reloc>:<expression>
4445 where <group_reloc> is one of the strings defined in group_reloc_table.
4446 The hashes are optional.
4448 Everything else is as for parse_shifter_operand. */
4450 static parse_operand_result
4451 parse_shifter_operand_group_reloc (char **str
, int i
)
4453 /* Determine if we have the sequence of characters #: or just :
4454 coming next. If we do, then we check for a group relocation.
4455 If we don't, punt the whole lot to parse_shifter_operand. */
4457 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4458 || (*str
)[0] == ':')
4460 struct group_reloc_table_entry
*entry
;
4462 if ((*str
)[0] == '#')
4467 /* Try to parse a group relocation. Anything else is an error. */
4468 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4470 inst
.error
= _("unknown group relocation");
4471 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4474 /* We now have the group relocation table entry corresponding to
4475 the name in the assembler source. Next, we parse the expression. */
4476 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4477 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4479 /* Record the relocation type (always the ALU variant here). */
4480 inst
.reloc
.type
= entry
->alu_code
;
4481 assert (inst
.reloc
.type
!= 0);
4483 return PARSE_OPERAND_SUCCESS
;
4486 return parse_shifter_operand (str
, i
) == SUCCESS
4487 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4489 /* Never reached. */
4492 /* Parse all forms of an ARM address expression. Information is written
4493 to inst.operands[i] and/or inst.reloc.
4495 Preindexed addressing (.preind=1):
4497 [Rn, #offset] .reg=Rn .reloc.exp=offset
4498 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4499 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4500 .shift_kind=shift .reloc.exp=shift_imm
4502 These three may have a trailing ! which causes .writeback to be set also.
4504 Postindexed addressing (.postind=1, .writeback=1):
4506 [Rn], #offset .reg=Rn .reloc.exp=offset
4507 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4508 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4509 .shift_kind=shift .reloc.exp=shift_imm
4511 Unindexed addressing (.preind=0, .postind=0):
4513 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4517 [Rn]{!} shorthand for [Rn,#0]{!}
4518 =immediate .isreg=0 .reloc.exp=immediate
4519 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4521 It is the caller's responsibility to check for addressing modes not
4522 supported by the instruction, and to set inst.reloc.type. */
4524 static parse_operand_result
4525 parse_address_main (char **str
, int i
, int group_relocations
,
4526 group_reloc_type group_type
)
4531 if (skip_past_char (&p
, '[') == FAIL
)
4533 if (skip_past_char (&p
, '=') == FAIL
)
4535 /* bare address - translate to PC-relative offset */
4536 inst
.reloc
.pc_rel
= 1;
4537 inst
.operands
[i
].reg
= REG_PC
;
4538 inst
.operands
[i
].isreg
= 1;
4539 inst
.operands
[i
].preind
= 1;
4541 /* else a load-constant pseudo op, no special treatment needed here */
4543 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4544 return PARSE_OPERAND_FAIL
;
4547 return PARSE_OPERAND_SUCCESS
;
4550 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4552 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4553 return PARSE_OPERAND_FAIL
;
4555 inst
.operands
[i
].reg
= reg
;
4556 inst
.operands
[i
].isreg
= 1;
4558 if (skip_past_comma (&p
) == SUCCESS
)
4560 inst
.operands
[i
].preind
= 1;
4563 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4565 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4567 inst
.operands
[i
].imm
= reg
;
4568 inst
.operands
[i
].immisreg
= 1;
4570 if (skip_past_comma (&p
) == SUCCESS
)
4571 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4572 return PARSE_OPERAND_FAIL
;
4574 else if (skip_past_char (&p
, ':') == SUCCESS
)
4576 /* FIXME: '@' should be used here, but it's filtered out by generic
4577 code before we get to see it here. This may be subject to
4580 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4581 if (exp
.X_op
!= O_constant
)
4583 inst
.error
= _("alignment must be constant");
4584 return PARSE_OPERAND_FAIL
;
4586 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4587 inst
.operands
[i
].immisalign
= 1;
4588 /* Alignments are not pre-indexes. */
4589 inst
.operands
[i
].preind
= 0;
4593 if (inst
.operands
[i
].negative
)
4595 inst
.operands
[i
].negative
= 0;
4599 if (group_relocations
&&
4600 ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
4603 struct group_reloc_table_entry
*entry
;
4605 /* Skip over the #: or : sequence. */
4611 /* Try to parse a group relocation. Anything else is an
4613 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
4615 inst
.error
= _("unknown group relocation");
4616 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4619 /* We now have the group relocation table entry corresponding to
4620 the name in the assembler source. Next, we parse the
4622 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4623 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4625 /* Record the relocation type. */
4629 inst
.reloc
.type
= entry
->ldr_code
;
4633 inst
.reloc
.type
= entry
->ldrs_code
;
4637 inst
.reloc
.type
= entry
->ldc_code
;
4644 if (inst
.reloc
.type
== 0)
4646 inst
.error
= _("this group relocation is not allowed on this instruction");
4647 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4651 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4652 return PARSE_OPERAND_FAIL
;
4656 if (skip_past_char (&p
, ']') == FAIL
)
4658 inst
.error
= _("']' expected");
4659 return PARSE_OPERAND_FAIL
;
4662 if (skip_past_char (&p
, '!') == SUCCESS
)
4663 inst
.operands
[i
].writeback
= 1;
4665 else if (skip_past_comma (&p
) == SUCCESS
)
4667 if (skip_past_char (&p
, '{') == SUCCESS
)
4669 /* [Rn], {expr} - unindexed, with option */
4670 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
4671 0, 255, TRUE
) == FAIL
)
4672 return PARSE_OPERAND_FAIL
;
4674 if (skip_past_char (&p
, '}') == FAIL
)
4676 inst
.error
= _("'}' expected at end of 'option' field");
4677 return PARSE_OPERAND_FAIL
;
4679 if (inst
.operands
[i
].preind
)
4681 inst
.error
= _("cannot combine index with option");
4682 return PARSE_OPERAND_FAIL
;
4685 return PARSE_OPERAND_SUCCESS
;
4689 inst
.operands
[i
].postind
= 1;
4690 inst
.operands
[i
].writeback
= 1;
4692 if (inst
.operands
[i
].preind
)
4694 inst
.error
= _("cannot combine pre- and post-indexing");
4695 return PARSE_OPERAND_FAIL
;
4699 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4701 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4703 /* We might be using the immediate for alignment already. If we
4704 are, OR the register number into the low-order bits. */
4705 if (inst
.operands
[i
].immisalign
)
4706 inst
.operands
[i
].imm
|= reg
;
4708 inst
.operands
[i
].imm
= reg
;
4709 inst
.operands
[i
].immisreg
= 1;
4711 if (skip_past_comma (&p
) == SUCCESS
)
4712 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4713 return PARSE_OPERAND_FAIL
;
4717 if (inst
.operands
[i
].negative
)
4719 inst
.operands
[i
].negative
= 0;
4722 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4723 return PARSE_OPERAND_FAIL
;
4728 /* If at this point neither .preind nor .postind is set, we have a
4729 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
4730 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
4732 inst
.operands
[i
].preind
= 1;
4733 inst
.reloc
.exp
.X_op
= O_constant
;
4734 inst
.reloc
.exp
.X_add_number
= 0;
4737 return PARSE_OPERAND_SUCCESS
;
4741 parse_address (char **str
, int i
)
4743 return parse_address_main (str
, i
, 0, 0) == PARSE_OPERAND_SUCCESS
4747 static parse_operand_result
4748 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
4750 return parse_address_main (str
, i
, 1, type
);
4753 /* Parse an operand for a MOVW or MOVT instruction. */
4755 parse_half (char **str
)
4760 skip_past_char (&p
, '#');
4761 if (strncasecmp (p
, ":lower16:", 9) == 0)
4762 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
4763 else if (strncasecmp (p
, ":upper16:", 9) == 0)
4764 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
4766 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4772 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4775 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4777 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4779 inst
.error
= _("constant expression expected");
4782 if (inst
.reloc
.exp
.X_add_number
< 0
4783 || inst
.reloc
.exp
.X_add_number
> 0xffff)
4785 inst
.error
= _("immediate value out of range");
4793 /* Miscellaneous. */
4795 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
4796 or a bitmask suitable to be or-ed into the ARM msr instruction. */
4798 parse_psr (char **str
)
4801 unsigned long psr_field
;
4802 const struct asm_psr
*psr
;
4805 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
4806 feature for ease of use and backwards compatibility. */
4808 if (strncasecmp (p
, "SPSR", 4) == 0)
4809 psr_field
= SPSR_BIT
;
4810 else if (strncasecmp (p
, "CPSR", 4) == 0)
4817 while (ISALNUM (*p
) || *p
== '_');
4819 psr
= hash_find_n (arm_v7m_psr_hsh
, start
, p
- start
);
4830 /* A suffix follows. */
4836 while (ISALNUM (*p
) || *p
== '_');
4838 psr
= hash_find_n (arm_psr_hsh
, start
, p
- start
);
4842 psr_field
|= psr
->field
;
4847 goto error
; /* Garbage after "[CS]PSR". */
4849 psr_field
|= (PSR_c
| PSR_f
);
4855 inst
.error
= _("flag for {c}psr instruction expected");
4859 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
4860 value suitable for splatting into the AIF field of the instruction. */
4863 parse_cps_flags (char **str
)
4872 case '\0': case ',':
4875 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
4876 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
4877 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
4880 inst
.error
= _("unrecognized CPS flag");
4885 if (saw_a_flag
== 0)
4887 inst
.error
= _("missing CPS flags");
4895 /* Parse an endian specifier ("BE" or "LE", case insensitive);
4896 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
4899 parse_endian_specifier (char **str
)
4904 if (strncasecmp (s
, "BE", 2))
4906 else if (strncasecmp (s
, "LE", 2))
4910 inst
.error
= _("valid endian specifiers are be or le");
4914 if (ISALNUM (s
[2]) || s
[2] == '_')
4916 inst
.error
= _("valid endian specifiers are be or le");
4921 return little_endian
;
4924 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
4925 value suitable for poking into the rotate field of an sxt or sxta
4926 instruction, or FAIL on error. */
4929 parse_ror (char **str
)
4934 if (strncasecmp (s
, "ROR", 3) == 0)
4938 inst
.error
= _("missing rotation field after comma");
4942 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
4947 case 0: *str
= s
; return 0x0;
4948 case 8: *str
= s
; return 0x1;
4949 case 16: *str
= s
; return 0x2;
4950 case 24: *str
= s
; return 0x3;
4953 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
4958 /* Parse a conditional code (from conds[] below). The value returned is in the
4959 range 0 .. 14, or FAIL. */
4961 parse_cond (char **str
)
4964 const struct asm_cond
*c
;
4967 while (ISALPHA (*q
))
4970 c
= hash_find_n (arm_cond_hsh
, p
, q
- p
);
4973 inst
.error
= _("condition required");
4981 /* Parse an option for a barrier instruction. Returns the encoding for the
4984 parse_barrier (char **str
)
4987 const struct asm_barrier_opt
*o
;
4990 while (ISALPHA (*q
))
4993 o
= hash_find_n (arm_barrier_opt_hsh
, p
, q
- p
);
5001 /* Parse the operands of a table branch instruction. Similar to a memory
5004 parse_tb (char **str
)
5009 if (skip_past_char (&p
, '[') == FAIL
)
5011 inst
.error
= _("'[' expected");
5015 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5017 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5020 inst
.operands
[0].reg
= reg
;
5022 if (skip_past_comma (&p
) == FAIL
)
5024 inst
.error
= _("',' expected");
5028 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5030 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5033 inst
.operands
[0].imm
= reg
;
5035 if (skip_past_comma (&p
) == SUCCESS
)
5037 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5039 if (inst
.reloc
.exp
.X_add_number
!= 1)
5041 inst
.error
= _("invalid shift");
5044 inst
.operands
[0].shifted
= 1;
5047 if (skip_past_char (&p
, ']') == FAIL
)
5049 inst
.error
= _("']' expected");
5056 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5057 information on the types the operands can take and how they are encoded.
5058 Up to four operands may be read; this function handles setting the
5059 ".present" field for each read operand itself.
5060 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5061 else returns FAIL. */
5064 parse_neon_mov (char **str
, int *which_operand
)
5066 int i
= *which_operand
, val
;
5067 enum arm_reg_type rtype
;
5069 struct neon_type_el optype
;
5071 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5073 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5074 inst
.operands
[i
].reg
= val
;
5075 inst
.operands
[i
].isscalar
= 1;
5076 inst
.operands
[i
].vectype
= optype
;
5077 inst
.operands
[i
++].present
= 1;
5079 if (skip_past_comma (&ptr
) == FAIL
)
5082 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5085 inst
.operands
[i
].reg
= val
;
5086 inst
.operands
[i
].isreg
= 1;
5087 inst
.operands
[i
].present
= 1;
5089 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5092 /* Cases 0, 1, 2, 3, 5 (D only). */
5093 if (skip_past_comma (&ptr
) == FAIL
)
5096 inst
.operands
[i
].reg
= val
;
5097 inst
.operands
[i
].isreg
= 1;
5098 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5099 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5100 inst
.operands
[i
].isvec
= 1;
5101 inst
.operands
[i
].vectype
= optype
;
5102 inst
.operands
[i
++].present
= 1;
5104 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5106 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5107 Case 13: VMOV <Sd>, <Rm> */
5108 inst
.operands
[i
].reg
= val
;
5109 inst
.operands
[i
].isreg
= 1;
5110 inst
.operands
[i
].present
= 1;
5112 if (rtype
== REG_TYPE_NQ
)
5114 first_error (_("can't use Neon quad register here"));
5117 else if (rtype
!= REG_TYPE_VFS
)
5120 if (skip_past_comma (&ptr
) == FAIL
)
5122 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5124 inst
.operands
[i
].reg
= val
;
5125 inst
.operands
[i
].isreg
= 1;
5126 inst
.operands
[i
].present
= 1;
5129 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5130 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5131 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5132 Case 10: VMOV.F32 <Sd>, #<imm>
5133 Case 11: VMOV.F64 <Dd>, #<imm> */
5135 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5136 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5137 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5139 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5142 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5143 Case 1: VMOV<c><q> <Dd>, <Dm>
5144 Case 8: VMOV.F32 <Sd>, <Sm>
5145 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5147 inst
.operands
[i
].reg
= val
;
5148 inst
.operands
[i
].isreg
= 1;
5149 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5150 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5151 inst
.operands
[i
].isvec
= 1;
5152 inst
.operands
[i
].vectype
= optype
;
5153 inst
.operands
[i
].present
= 1;
5155 if (skip_past_comma (&ptr
) == SUCCESS
)
5160 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5163 inst
.operands
[i
].reg
= val
;
5164 inst
.operands
[i
].isreg
= 1;
5165 inst
.operands
[i
++].present
= 1;
5167 if (skip_past_comma (&ptr
) == FAIL
)
5170 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5173 inst
.operands
[i
].reg
= val
;
5174 inst
.operands
[i
].isreg
= 1;
5175 inst
.operands
[i
++].present
= 1;
5180 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5184 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5187 inst
.operands
[i
].reg
= val
;
5188 inst
.operands
[i
].isreg
= 1;
5189 inst
.operands
[i
++].present
= 1;
5191 if (skip_past_comma (&ptr
) == FAIL
)
5194 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5196 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5197 inst
.operands
[i
].reg
= val
;
5198 inst
.operands
[i
].isscalar
= 1;
5199 inst
.operands
[i
].present
= 1;
5200 inst
.operands
[i
].vectype
= optype
;
5202 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5204 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5205 inst
.operands
[i
].reg
= val
;
5206 inst
.operands
[i
].isreg
= 1;
5207 inst
.operands
[i
++].present
= 1;
5209 if (skip_past_comma (&ptr
) == FAIL
)
5212 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5215 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5219 inst
.operands
[i
].reg
= val
;
5220 inst
.operands
[i
].isreg
= 1;
5221 inst
.operands
[i
].isvec
= 1;
5222 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5223 inst
.operands
[i
].vectype
= optype
;
5224 inst
.operands
[i
].present
= 1;
5226 if (rtype
== REG_TYPE_VFS
)
5230 if (skip_past_comma (&ptr
) == FAIL
)
5232 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5235 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5238 inst
.operands
[i
].reg
= val
;
5239 inst
.operands
[i
].isreg
= 1;
5240 inst
.operands
[i
].isvec
= 1;
5241 inst
.operands
[i
].issingle
= 1;
5242 inst
.operands
[i
].vectype
= optype
;
5243 inst
.operands
[i
].present
= 1;
5246 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5250 inst
.operands
[i
].reg
= val
;
5251 inst
.operands
[i
].isreg
= 1;
5252 inst
.operands
[i
].isvec
= 1;
5253 inst
.operands
[i
].issingle
= 1;
5254 inst
.operands
[i
].vectype
= optype
;
5255 inst
.operands
[i
++].present
= 1;
5260 first_error (_("parse error"));
5264 /* Successfully parsed the operands. Update args. */
5270 first_error (_("expected comma"));
5274 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5278 /* Matcher codes for parse_operands. */
5279 enum operand_parse_code
5281 OP_stop
, /* end of line */
5283 OP_RR
, /* ARM register */
5284 OP_RRnpc
, /* ARM register, not r15 */
5285 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5286 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5287 OP_RCP
, /* Coprocessor number */
5288 OP_RCN
, /* Coprocessor register */
5289 OP_RF
, /* FPA register */
5290 OP_RVS
, /* VFP single precision register */
5291 OP_RVD
, /* VFP double precision register (0..15) */
5292 OP_RND
, /* Neon double precision register (0..31) */
5293 OP_RNQ
, /* Neon quad precision register */
5294 OP_RVSD
, /* VFP single or double precision register */
5295 OP_RNDQ
, /* Neon double or quad precision register */
5296 OP_RNSDQ
, /* Neon single, double or quad precision register */
5297 OP_RNSC
, /* Neon scalar D[X] */
5298 OP_RVC
, /* VFP control register */
5299 OP_RMF
, /* Maverick F register */
5300 OP_RMD
, /* Maverick D register */
5301 OP_RMFX
, /* Maverick FX register */
5302 OP_RMDX
, /* Maverick DX register */
5303 OP_RMAX
, /* Maverick AX register */
5304 OP_RMDS
, /* Maverick DSPSC register */
5305 OP_RIWR
, /* iWMMXt wR register */
5306 OP_RIWC
, /* iWMMXt wC register */
5307 OP_RIWG
, /* iWMMXt wCG register */
5308 OP_RXA
, /* XScale accumulator register */
5310 OP_REGLST
, /* ARM register list */
5311 OP_VRSLST
, /* VFP single-precision register list */
5312 OP_VRDLST
, /* VFP double-precision register list */
5313 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5314 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5315 OP_NSTRLST
, /* Neon element/structure list */
5317 OP_NILO
, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5318 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5319 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5320 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5321 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5322 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5323 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5324 OP_VMOV
, /* Neon VMOV operands. */
5325 OP_RNDQ_IMVNb
,/* Neon D or Q reg, or immediate good for VMVN. */
5326 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5328 OP_I0
, /* immediate zero */
5329 OP_I7
, /* immediate value 0 .. 7 */
5330 OP_I15
, /* 0 .. 15 */
5331 OP_I16
, /* 1 .. 16 */
5332 OP_I16z
, /* 0 .. 16 */
5333 OP_I31
, /* 0 .. 31 */
5334 OP_I31w
, /* 0 .. 31, optional trailing ! */
5335 OP_I32
, /* 1 .. 32 */
5336 OP_I32z
, /* 0 .. 32 */
5337 OP_I63
, /* 0 .. 63 */
5338 OP_I63s
, /* -64 .. 63 */
5339 OP_I64
, /* 1 .. 64 */
5340 OP_I64z
, /* 0 .. 64 */
5341 OP_I255
, /* 0 .. 255 */
5343 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5344 OP_I7b
, /* 0 .. 7 */
5345 OP_I15b
, /* 0 .. 15 */
5346 OP_I31b
, /* 0 .. 31 */
5348 OP_SH
, /* shifter operand */
5349 OP_SHG
, /* shifter operand with possible group relocation */
5350 OP_ADDR
, /* Memory address expression (any mode) */
5351 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5352 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5353 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5354 OP_EXP
, /* arbitrary expression */
5355 OP_EXPi
, /* same, with optional immediate prefix */
5356 OP_EXPr
, /* same, with optional relocation suffix */
5357 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5359 OP_CPSF
, /* CPS flags */
5360 OP_ENDI
, /* Endianness specifier */
5361 OP_PSR
, /* CPSR/SPSR mask for msr */
5362 OP_COND
, /* conditional code */
5363 OP_TB
, /* Table branch. */
5365 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5366 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5368 OP_RRnpc_I0
, /* ARM register or literal 0 */
5369 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5370 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5371 OP_RF_IF
, /* FPA register or immediate */
5372 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5373 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5375 /* Optional operands. */
5376 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5377 OP_oI31b
, /* 0 .. 31 */
5378 OP_oI32b
, /* 1 .. 32 */
5379 OP_oIffffb
, /* 0 .. 65535 */
5380 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5382 OP_oRR
, /* ARM register */
5383 OP_oRRnpc
, /* ARM register, not the PC */
5384 OP_oRND
, /* Optional Neon double precision register */
5385 OP_oRNQ
, /* Optional Neon quad precision register */
5386 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5387 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5388 OP_oSHll
, /* LSL immediate */
5389 OP_oSHar
, /* ASR immediate */
5390 OP_oSHllar
, /* LSL or ASR immediate */
5391 OP_oROR
, /* ROR 0/8/16/24 */
5392 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5394 OP_FIRST_OPTIONAL
= OP_oI7b
5397 /* Generic instruction operand parser. This does no encoding and no
5398 semantic validation; it merely squirrels values away in the inst
5399 structure. Returns SUCCESS or FAIL depending on whether the
5400 specified grammar matched. */
5402 parse_operands (char *str
, const unsigned char *pattern
)
5404 unsigned const char *upat
= pattern
;
5405 char *backtrack_pos
= 0;
5406 const char *backtrack_error
= 0;
5407 int i
, val
, backtrack_index
= 0;
5408 enum arm_reg_type rtype
;
5409 parse_operand_result result
;
5411 #define po_char_or_fail(chr) do { \
5412 if (skip_past_char (&str, chr) == FAIL) \
5416 #define po_reg_or_fail(regtype) do { \
5417 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5418 &inst.operands[i].vectype); \
5421 first_error (_(reg_expected_msgs[regtype])); \
5424 inst.operands[i].reg = val; \
5425 inst.operands[i].isreg = 1; \
5426 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5427 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5428 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5429 || rtype == REG_TYPE_VFD \
5430 || rtype == REG_TYPE_NQ); \
5433 #define po_reg_or_goto(regtype, label) do { \
5434 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5435 &inst.operands[i].vectype); \
5439 inst.operands[i].reg = val; \
5440 inst.operands[i].isreg = 1; \
5441 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5442 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5443 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5444 || rtype == REG_TYPE_VFD \
5445 || rtype == REG_TYPE_NQ); \
5448 #define po_imm_or_fail(min, max, popt) do { \
5449 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5451 inst.operands[i].imm = val; \
5454 #define po_scalar_or_goto(elsz, label) do { \
5455 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \
5458 inst.operands[i].reg = val; \
5459 inst.operands[i].isscalar = 1; \
5462 #define po_misc_or_fail(expr) do { \
5467 #define po_misc_or_fail_no_backtrack(expr) do { \
5469 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
5470 backtrack_pos = 0; \
5471 if (result != PARSE_OPERAND_SUCCESS) \
5475 skip_whitespace (str
);
5477 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5479 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5481 /* Remember where we are in case we need to backtrack. */
5482 assert (!backtrack_pos
);
5483 backtrack_pos
= str
;
5484 backtrack_error
= inst
.error
;
5485 backtrack_index
= i
;
5489 po_char_or_fail (',');
5497 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5498 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5499 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5500 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5501 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5502 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5504 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5505 case OP_RVC
: po_reg_or_fail (REG_TYPE_VFC
); break;
5506 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5507 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5508 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5509 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5510 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5511 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5512 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5513 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5514 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5515 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5517 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
5519 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
5520 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
5522 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
5524 /* Neon scalar. Using an element size of 8 means that some invalid
5525 scalars are accepted here, so deal with those in later code. */
5526 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
5528 /* WARNING: We can expand to two operands here. This has the potential
5529 to totally confuse the backtracking mechanism! It will be OK at
5530 least as long as we don't try to use optional args as well,
5534 po_reg_or_goto (REG_TYPE_NDQ
, try_imm
);
5536 skip_past_comma (&str
);
5537 po_reg_or_goto (REG_TYPE_NDQ
, one_reg_only
);
5540 /* Optional register operand was omitted. Unfortunately, it's in
5541 operands[i-1] and we need it to be in inst.operands[i]. Fix that
5542 here (this is a bit grotty). */
5543 inst
.operands
[i
] = inst
.operands
[i
-1];
5544 inst
.operands
[i
-1].present
= 0;
5547 /* Immediate gets verified properly later, so accept any now. */
5548 po_imm_or_fail (INT_MIN
, INT_MAX
, TRUE
);
5554 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
5557 po_imm_or_fail (0, 0, TRUE
);
5562 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
5567 po_scalar_or_goto (8, try_rr
);
5570 po_reg_or_fail (REG_TYPE_RN
);
5576 po_scalar_or_goto (8, try_nsdq
);
5579 po_reg_or_fail (REG_TYPE_NSDQ
);
5585 po_scalar_or_goto (8, try_ndq
);
5588 po_reg_or_fail (REG_TYPE_NDQ
);
5594 po_scalar_or_goto (8, try_vfd
);
5597 po_reg_or_fail (REG_TYPE_VFD
);
5602 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
5603 not careful then bad things might happen. */
5604 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
5609 po_reg_or_goto (REG_TYPE_NDQ
, try_mvnimm
);
5612 /* There's a possibility of getting a 64-bit immediate here, so
5613 we need special handling. */
5614 if (parse_big_immediate (&str
, i
) == FAIL
)
5616 inst
.error
= _("immediate value is out of range");
5624 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
5627 po_imm_or_fail (0, 63, TRUE
);
5632 po_char_or_fail ('[');
5633 po_reg_or_fail (REG_TYPE_RN
);
5634 po_char_or_fail (']');
5638 po_reg_or_fail (REG_TYPE_RN
);
5639 if (skip_past_char (&str
, '!') == SUCCESS
)
5640 inst
.operands
[i
].writeback
= 1;
5644 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
5645 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
5646 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
5647 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
5648 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
5649 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
5650 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
5651 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
5652 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
5653 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
5654 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
5655 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
5657 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
5659 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
5660 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
5662 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
5663 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
5664 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
5666 /* Immediate variants */
5668 po_char_or_fail ('{');
5669 po_imm_or_fail (0, 255, TRUE
);
5670 po_char_or_fail ('}');
5674 /* The expression parser chokes on a trailing !, so we have
5675 to find it first and zap it. */
5678 while (*s
&& *s
!= ',')
5683 inst
.operands
[i
].writeback
= 1;
5685 po_imm_or_fail (0, 31, TRUE
);
5693 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5698 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5703 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5705 if (inst
.reloc
.exp
.X_op
== O_symbol
)
5707 val
= parse_reloc (&str
);
5710 inst
.error
= _("unrecognized relocation suffix");
5713 else if (val
!= BFD_RELOC_UNUSED
)
5715 inst
.operands
[i
].imm
= val
;
5716 inst
.operands
[i
].hasreloc
= 1;
5721 /* Operand for MOVW or MOVT. */
5723 po_misc_or_fail (parse_half (&str
));
5726 /* Register or expression */
5727 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
5728 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
5730 /* Register or immediate */
5731 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
5732 I0
: po_imm_or_fail (0, 0, FALSE
); break;
5734 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
5736 if (!is_immediate_prefix (*str
))
5739 val
= parse_fpa_immediate (&str
);
5742 /* FPA immediates are encoded as registers 8-15.
5743 parse_fpa_immediate has already applied the offset. */
5744 inst
.operands
[i
].reg
= val
;
5745 inst
.operands
[i
].isreg
= 1;
5748 /* Two kinds of register */
5751 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5752 if (rege
->type
!= REG_TYPE_MMXWR
5753 && rege
->type
!= REG_TYPE_MMXWC
5754 && rege
->type
!= REG_TYPE_MMXWCG
)
5756 inst
.error
= _("iWMMXt data or control register expected");
5759 inst
.operands
[i
].reg
= rege
->number
;
5760 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
5766 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5768 || (rege
->type
!= REG_TYPE_MMXWC
5769 && rege
->type
!= REG_TYPE_MMXWCG
))
5771 inst
.error
= _("iWMMXt control register expected");
5774 inst
.operands
[i
].reg
= rege
->number
;
5775 inst
.operands
[i
].isreg
= 1;
5780 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
5781 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
5782 case OP_oROR
: val
= parse_ror (&str
); break;
5783 case OP_PSR
: val
= parse_psr (&str
); break;
5784 case OP_COND
: val
= parse_cond (&str
); break;
5785 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
5788 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
5789 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
5792 val
= parse_psr (&str
);
5796 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
5799 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
5801 if (strncasecmp (str
, "APSR_", 5) == 0)
5808 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
5809 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
5810 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
5811 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
5812 default: found
= 16;
5816 inst
.operands
[i
].isvec
= 1;
5823 po_misc_or_fail (parse_tb (&str
));
5826 /* Register lists */
5828 val
= parse_reg_list (&str
);
5831 inst
.operands
[1].writeback
= 1;
5837 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
5841 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
5845 /* Allow Q registers too. */
5846 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5851 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5853 inst
.operands
[i
].issingle
= 1;
5858 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5863 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
5864 &inst
.operands
[i
].vectype
);
5867 /* Addressing modes */
5869 po_misc_or_fail (parse_address (&str
, i
));
5873 po_misc_or_fail_no_backtrack (
5874 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
5878 po_misc_or_fail_no_backtrack (
5879 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
5883 po_misc_or_fail_no_backtrack (
5884 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
5888 po_misc_or_fail (parse_shifter_operand (&str
, i
));
5892 po_misc_or_fail_no_backtrack (
5893 parse_shifter_operand_group_reloc (&str
, i
));
5897 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
5901 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
5905 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
5909 as_fatal ("unhandled operand code %d", upat
[i
]);
5912 /* Various value-based sanity checks and shared operations. We
5913 do not signal immediate failures for the register constraints;
5914 this allows a syntax error to take precedence. */
5922 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
5923 inst
.error
= BAD_PC
;
5941 inst
.operands
[i
].imm
= val
;
5948 /* If we get here, this operand was successfully parsed. */
5949 inst
.operands
[i
].present
= 1;
5953 inst
.error
= BAD_ARGS
;
5958 /* The parse routine should already have set inst.error, but set a
5959 defaut here just in case. */
5961 inst
.error
= _("syntax error");
5965 /* Do not backtrack over a trailing optional argument that
5966 absorbed some text. We will only fail again, with the
5967 'garbage following instruction' error message, which is
5968 probably less helpful than the current one. */
5969 if (backtrack_index
== i
&& backtrack_pos
!= str
5970 && upat
[i
+1] == OP_stop
)
5973 inst
.error
= _("syntax error");
5977 /* Try again, skipping the optional argument at backtrack_pos. */
5978 str
= backtrack_pos
;
5979 inst
.error
= backtrack_error
;
5980 inst
.operands
[backtrack_index
].present
= 0;
5981 i
= backtrack_index
;
5985 /* Check that we have parsed all the arguments. */
5986 if (*str
!= '\0' && !inst
.error
)
5987 inst
.error
= _("garbage following instruction");
5989 return inst
.error
? FAIL
: SUCCESS
;
5992 #undef po_char_or_fail
5993 #undef po_reg_or_fail
5994 #undef po_reg_or_goto
5995 #undef po_imm_or_fail
5996 #undef po_scalar_or_fail
5998 /* Shorthand macro for instruction encoding functions issuing errors. */
5999 #define constraint(expr, err) do { \
6007 /* Functions for operand encoding. ARM, then Thumb. */
6009 #define rotate_left(v, n) (v << n | v >> (32 - n))
6011 /* If VAL can be encoded in the immediate field of an ARM instruction,
6012 return the encoded form. Otherwise, return FAIL. */
6015 encode_arm_immediate (unsigned int val
)
6019 for (i
= 0; i
< 32; i
+= 2)
6020 if ((a
= rotate_left (val
, i
)) <= 0xff)
6021 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6026 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6027 return the encoded form. Otherwise, return FAIL. */
6029 encode_thumb32_immediate (unsigned int val
)
6036 for (i
= 1; i
<= 24; i
++)
6039 if ((val
& ~(0xff << i
)) == 0)
6040 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6044 if (val
== ((a
<< 16) | a
))
6046 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6050 if (val
== ((a
<< 16) | a
))
6051 return 0x200 | (a
>> 8);
6055 /* Encode a VFP SP or DP register number into inst.instruction. */
6058 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6060 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6063 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
6066 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6069 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6074 first_error (_("D register out of range for selected VFP version"));
6082 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6086 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6090 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6094 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6098 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6102 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6110 /* Encode a <shift> in an ARM-format instruction. The immediate,
6111 if any, is handled by md_apply_fix. */
6113 encode_arm_shift (int i
)
6115 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6116 inst
.instruction
|= SHIFT_ROR
<< 5;
6119 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6120 if (inst
.operands
[i
].immisreg
)
6122 inst
.instruction
|= SHIFT_BY_REG
;
6123 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6126 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6131 encode_arm_shifter_operand (int i
)
6133 if (inst
.operands
[i
].isreg
)
6135 inst
.instruction
|= inst
.operands
[i
].reg
;
6136 encode_arm_shift (i
);
6139 inst
.instruction
|= INST_IMMEDIATE
;
6142 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6144 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6146 assert (inst
.operands
[i
].isreg
);
6147 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6149 if (inst
.operands
[i
].preind
)
6153 inst
.error
= _("instruction does not accept preindexed addressing");
6156 inst
.instruction
|= PRE_INDEX
;
6157 if (inst
.operands
[i
].writeback
)
6158 inst
.instruction
|= WRITE_BACK
;
6161 else if (inst
.operands
[i
].postind
)
6163 assert (inst
.operands
[i
].writeback
);
6165 inst
.instruction
|= WRITE_BACK
;
6167 else /* unindexed - only for coprocessor */
6169 inst
.error
= _("instruction does not accept unindexed addressing");
6173 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6174 && (((inst
.instruction
& 0x000f0000) >> 16)
6175 == ((inst
.instruction
& 0x0000f000) >> 12)))
6176 as_warn ((inst
.instruction
& LOAD_BIT
)
6177 ? _("destination register same as write-back base")
6178 : _("source register same as write-back base"));
6181 /* inst.operands[i] was set up by parse_address. Encode it into an
6182 ARM-format mode 2 load or store instruction. If is_t is true,
6183 reject forms that cannot be used with a T instruction (i.e. not
6186 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6188 encode_arm_addr_mode_common (i
, is_t
);
6190 if (inst
.operands
[i
].immisreg
)
6192 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6193 inst
.instruction
|= inst
.operands
[i
].imm
;
6194 if (!inst
.operands
[i
].negative
)
6195 inst
.instruction
|= INDEX_UP
;
6196 if (inst
.operands
[i
].shifted
)
6198 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6199 inst
.instruction
|= SHIFT_ROR
<< 5;
6202 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6203 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6207 else /* immediate offset in inst.reloc */
6209 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6210 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6214 /* inst.operands[i] was set up by parse_address. Encode it into an
6215 ARM-format mode 3 load or store instruction. Reject forms that
6216 cannot be used with such instructions. If is_t is true, reject
6217 forms that cannot be used with a T instruction (i.e. not
6220 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6222 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6224 inst
.error
= _("instruction does not accept scaled register index");
6228 encode_arm_addr_mode_common (i
, is_t
);
6230 if (inst
.operands
[i
].immisreg
)
6232 inst
.instruction
|= inst
.operands
[i
].imm
;
6233 if (!inst
.operands
[i
].negative
)
6234 inst
.instruction
|= INDEX_UP
;
6236 else /* immediate offset in inst.reloc */
6238 inst
.instruction
|= HWOFFSET_IMM
;
6239 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6240 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6244 /* inst.operands[i] was set up by parse_address. Encode it into an
6245 ARM-format instruction. Reject all forms which cannot be encoded
6246 into a coprocessor load/store instruction. If wb_ok is false,
6247 reject use of writeback; if unind_ok is false, reject use of
6248 unindexed addressing. If reloc_override is not 0, use it instead
6249 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6250 (in which case it is preserved). */
6253 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6255 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6257 assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6259 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6261 assert (!inst
.operands
[i
].writeback
);
6264 inst
.error
= _("instruction does not support unindexed addressing");
6267 inst
.instruction
|= inst
.operands
[i
].imm
;
6268 inst
.instruction
|= INDEX_UP
;
6272 if (inst
.operands
[i
].preind
)
6273 inst
.instruction
|= PRE_INDEX
;
6275 if (inst
.operands
[i
].writeback
)
6277 if (inst
.operands
[i
].reg
== REG_PC
)
6279 inst
.error
= _("pc may not be used with write-back");
6284 inst
.error
= _("instruction does not support writeback");
6287 inst
.instruction
|= WRITE_BACK
;
6291 inst
.reloc
.type
= reloc_override
;
6292 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6293 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6294 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6297 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6299 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6305 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6306 Determine whether it can be performed with a move instruction; if
6307 it can, convert inst.instruction to that move instruction and
6308 return 1; if it can't, convert inst.instruction to a literal-pool
6309 load and return 0. If this is not a valid thing to do in the
6310 current context, set inst.error and return 1.
6312 inst.operands[i] describes the destination register. */
6315 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6320 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6324 if ((inst
.instruction
& tbit
) == 0)
6326 inst
.error
= _("invalid pseudo operation");
6329 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6331 inst
.error
= _("constant expression expected");
6334 if (inst
.reloc
.exp
.X_op
== O_constant
)
6338 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6340 /* This can be done with a mov(1) instruction. */
6341 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6342 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6348 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6351 /* This can be done with a mov instruction. */
6352 inst
.instruction
&= LITERAL_MASK
;
6353 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6354 inst
.instruction
|= value
& 0xfff;
6358 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6361 /* This can be done with a mvn instruction. */
6362 inst
.instruction
&= LITERAL_MASK
;
6363 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6364 inst
.instruction
|= value
& 0xfff;
6370 if (add_to_lit_pool () == FAIL
)
6372 inst
.error
= _("literal pool insertion failed");
6375 inst
.operands
[1].reg
= REG_PC
;
6376 inst
.operands
[1].isreg
= 1;
6377 inst
.operands
[1].preind
= 1;
6378 inst
.reloc
.pc_rel
= 1;
6379 inst
.reloc
.type
= (thumb_p
6380 ? BFD_RELOC_ARM_THUMB_OFFSET
6382 ? BFD_RELOC_ARM_HWLITERAL
6383 : BFD_RELOC_ARM_LITERAL
));
6387 /* Functions for instruction encoding, sorted by subarchitecture.
6388 First some generics; their names are taken from the conventional
6389 bit positions for register arguments in ARM format instructions. */
6399 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6405 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6406 inst
.instruction
|= inst
.operands
[1].reg
;
6412 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6413 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6419 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6420 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6426 unsigned Rn
= inst
.operands
[2].reg
;
6427 /* Enforce restrictions on SWP instruction. */
6428 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6429 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6430 _("Rn must not overlap other operands"));
6431 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6432 inst
.instruction
|= inst
.operands
[1].reg
;
6433 inst
.instruction
|= Rn
<< 16;
6439 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6440 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6441 inst
.instruction
|= inst
.operands
[2].reg
;
6447 inst
.instruction
|= inst
.operands
[0].reg
;
6448 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6449 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6455 inst
.instruction
|= inst
.operands
[0].imm
;
6461 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6462 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6465 /* ARM instructions, in alphabetical order by function name (except
6466 that wrapper functions appear immediately after the function they
6469 /* This is a pseudo-op of the form "adr rd, label" to be converted
6470 into a relative address of the form "add rd, pc, #label-.-8". */
6475 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6477 /* Frag hacking will turn this into a sub instruction if the offset turns
6478 out to be negative. */
6479 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6480 inst
.reloc
.pc_rel
= 1;
6481 inst
.reloc
.exp
.X_add_number
-= 8;
6484 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6485 into a relative address of the form:
6486 add rd, pc, #low(label-.-8)"
6487 add rd, rd, #high(label-.-8)" */
6492 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6494 /* Frag hacking will turn this into a sub instruction if the offset turns
6495 out to be negative. */
6496 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
6497 inst
.reloc
.pc_rel
= 1;
6498 inst
.size
= INSN_SIZE
* 2;
6499 inst
.reloc
.exp
.X_add_number
-= 8;
6505 if (!inst
.operands
[1].present
)
6506 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
6507 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6508 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6509 encode_arm_shifter_operand (2);
6515 if (inst
.operands
[0].present
)
6517 constraint ((inst
.instruction
& 0xf0) != 0x40
6518 && inst
.operands
[0].imm
!= 0xf,
6519 "bad barrier type");
6520 inst
.instruction
|= inst
.operands
[0].imm
;
6523 inst
.instruction
|= 0xf;
6529 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
6530 constraint (msb
> 32, _("bit-field extends past end of register"));
6531 /* The instruction encoding stores the LSB and MSB,
6532 not the LSB and width. */
6533 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6534 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
6535 inst
.instruction
|= (msb
- 1) << 16;
6543 /* #0 in second position is alternative syntax for bfc, which is
6544 the same instruction but with REG_PC in the Rm field. */
6545 if (!inst
.operands
[1].isreg
)
6546 inst
.operands
[1].reg
= REG_PC
;
6548 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
6549 constraint (msb
> 32, _("bit-field extends past end of register"));
6550 /* The instruction encoding stores the LSB and MSB,
6551 not the LSB and width. */
6552 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6553 inst
.instruction
|= inst
.operands
[1].reg
;
6554 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6555 inst
.instruction
|= (msb
- 1) << 16;
6561 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
6562 _("bit-field extends past end of register"));
6563 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6564 inst
.instruction
|= inst
.operands
[1].reg
;
6565 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6566 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
6569 /* ARM V5 breakpoint instruction (argument parse)
6570 BKPT <16 bit unsigned immediate>
6571 Instruction is not conditional.
6572 The bit pattern given in insns[] has the COND_ALWAYS condition,
6573 and it is an error if the caller tried to override that. */
6578 /* Top 12 of 16 bits to bits 19:8. */
6579 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
6581 /* Bottom 4 of 16 bits to bits 3:0. */
6582 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
6586 encode_branch (int default_reloc
)
6588 if (inst
.operands
[0].hasreloc
)
6590 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
6591 _("the only suffix valid here is '(plt)'"));
6592 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
6596 inst
.reloc
.type
= default_reloc
;
6598 inst
.reloc
.pc_rel
= 1;
6605 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6606 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6609 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6616 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6618 if (inst
.cond
== COND_ALWAYS
)
6619 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6621 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6625 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6628 /* ARM V5 branch-link-exchange instruction (argument parse)
6629 BLX <target_addr> ie BLX(1)
6630 BLX{<condition>} <Rm> ie BLX(2)
6631 Unfortunately, there are two different opcodes for this mnemonic.
6632 So, the insns[].value is not used, and the code here zaps values
6633 into inst.instruction.
6634 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
6639 if (inst
.operands
[0].isreg
)
6641 /* Arg is a register; the opcode provided by insns[] is correct.
6642 It is not illegal to do "blx pc", just useless. */
6643 if (inst
.operands
[0].reg
== REG_PC
)
6644 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
6646 inst
.instruction
|= inst
.operands
[0].reg
;
6650 /* Arg is an address; this instruction cannot be executed
6651 conditionally, and the opcode must be adjusted. */
6652 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
6653 inst
.instruction
= 0xfa000000;
6655 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6656 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6659 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
6666 if (inst
.operands
[0].reg
== REG_PC
)
6667 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
6669 inst
.instruction
|= inst
.operands
[0].reg
;
6673 /* ARM v5TEJ. Jump to Jazelle code. */
6678 if (inst
.operands
[0].reg
== REG_PC
)
6679 as_tsktsk (_("use of r15 in bxj is not really useful"));
6681 inst
.instruction
|= inst
.operands
[0].reg
;
6684 /* Co-processor data operation:
6685 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
6686 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
6690 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6691 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
6692 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6693 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6694 inst
.instruction
|= inst
.operands
[4].reg
;
6695 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6701 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6702 encode_arm_shifter_operand (1);
6705 /* Transfer between coprocessor and ARM registers.
6706 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
6711 No special properties. */
6716 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6717 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
6718 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6719 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6720 inst
.instruction
|= inst
.operands
[4].reg
;
6721 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6724 /* Transfer between coprocessor register and pair of ARM registers.
6725 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6730 Two XScale instructions are special cases of these:
6732 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
6733 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
6735 Result unpredicatable if Rd or Rn is R15. */
6740 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6741 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
6742 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6743 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6744 inst
.instruction
|= inst
.operands
[4].reg
;
6750 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
6751 inst
.instruction
|= inst
.operands
[1].imm
;
6757 inst
.instruction
|= inst
.operands
[0].imm
;
6763 /* There is no IT instruction in ARM mode. We
6764 process it but do not generate code for it. */
6771 int base_reg
= inst
.operands
[0].reg
;
6772 int range
= inst
.operands
[1].imm
;
6774 inst
.instruction
|= base_reg
<< 16;
6775 inst
.instruction
|= range
;
6777 if (inst
.operands
[1].writeback
)
6778 inst
.instruction
|= LDM_TYPE_2_OR_3
;
6780 if (inst
.operands
[0].writeback
)
6782 inst
.instruction
|= WRITE_BACK
;
6783 /* Check for unpredictable uses of writeback. */
6784 if (inst
.instruction
& LOAD_BIT
)
6786 /* Not allowed in LDM type 2. */
6787 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
6788 && ((range
& (1 << REG_PC
)) == 0))
6789 as_warn (_("writeback of base register is UNPREDICTABLE"));
6790 /* Only allowed if base reg not in list for other types. */
6791 else if (range
& (1 << base_reg
))
6792 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
6796 /* Not allowed for type 2. */
6797 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
6798 as_warn (_("writeback of base register is UNPREDICTABLE"));
6799 /* Only allowed if base reg not in list, or first in list. */
6800 else if ((range
& (1 << base_reg
))
6801 && (range
& ((1 << base_reg
) - 1)))
6802 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
6807 /* ARMv5TE load-consecutive (argument parse)
6816 constraint (inst
.operands
[0].reg
% 2 != 0,
6817 _("first destination register must be even"));
6818 constraint (inst
.operands
[1].present
6819 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
6820 _("can only load two consecutive registers"));
6821 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
6822 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
6824 if (!inst
.operands
[1].present
)
6825 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
6827 if (inst
.instruction
& LOAD_BIT
)
6829 /* encode_arm_addr_mode_3 will diagnose overlap between the base
6830 register and the first register written; we have to diagnose
6831 overlap between the base and the second register written here. */
6833 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
6834 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
6835 as_warn (_("base register written back, and overlaps "
6836 "second destination register"));
6838 /* For an index-register load, the index register must not overlap the
6839 destination (even if not write-back). */
6840 else if (inst
.operands
[2].immisreg
6841 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
6842 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
6843 as_warn (_("index register overlaps destination register"));
6846 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6847 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
6853 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
6854 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
6855 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
6856 || inst
.operands
[1].negative
6857 /* This can arise if the programmer has written
6859 or if they have mistakenly used a register name as the last
6862 It is very difficult to distinguish between these two cases
6863 because "rX" might actually be a label. ie the register
6864 name has been occluded by a symbol of the same name. So we
6865 just generate a general 'bad addressing mode' type error
6866 message and leave it up to the programmer to discover the
6867 true cause and fix their mistake. */
6868 || (inst
.operands
[1].reg
== REG_PC
),
6871 constraint (inst
.reloc
.exp
.X_op
!= O_constant
6872 || inst
.reloc
.exp
.X_add_number
!= 0,
6873 _("offset must be zero in ARM encoding"));
6875 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6876 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6877 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6883 constraint (inst
.operands
[0].reg
% 2 != 0,
6884 _("even register required"));
6885 constraint (inst
.operands
[1].present
6886 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
6887 _("can only load two consecutive registers"));
6888 /* If op 1 were present and equal to PC, this function wouldn't
6889 have been called in the first place. */
6890 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
6892 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6893 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6899 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6900 if (!inst
.operands
[1].isreg
)
6901 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
6903 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
6909 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
6911 if (inst
.operands
[1].preind
)
6913 constraint (inst
.reloc
.exp
.X_op
!= O_constant
||
6914 inst
.reloc
.exp
.X_add_number
!= 0,
6915 _("this instruction requires a post-indexed address"));
6917 inst
.operands
[1].preind
= 0;
6918 inst
.operands
[1].postind
= 1;
6919 inst
.operands
[1].writeback
= 1;
6921 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6922 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
6925 /* Halfword and signed-byte load/store operations. */
6930 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6931 if (!inst
.operands
[1].isreg
)
6932 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
6934 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
6940 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
6942 if (inst
.operands
[1].preind
)
6944 constraint (inst
.reloc
.exp
.X_op
!= O_constant
||
6945 inst
.reloc
.exp
.X_add_number
!= 0,
6946 _("this instruction requires a post-indexed address"));
6948 inst
.operands
[1].preind
= 0;
6949 inst
.operands
[1].postind
= 1;
6950 inst
.operands
[1].writeback
= 1;
6952 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6953 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
6956 /* Co-processor register load/store.
6957 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
6961 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6962 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6963 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
6969 /* This restriction does not apply to mls (nor to mla in v6, but
6970 that's hard to detect at present). */
6971 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
6972 && !(inst
.instruction
& 0x00400000))
6973 as_tsktsk (_("rd and rm should be different in mla"));
6975 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6976 inst
.instruction
|= inst
.operands
[1].reg
;
6977 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
6978 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
6985 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6986 encode_arm_shifter_operand (1);
6989 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
6996 top
= (inst
.instruction
& 0x00400000) != 0;
6997 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
6998 _(":lower16: not allowed this instruction"));
6999 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7000 _(":upper16: not allowed instruction"));
7001 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7002 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7004 imm
= inst
.reloc
.exp
.X_add_number
;
7005 /* The value is in two pieces: 0:11, 16:19. */
7006 inst
.instruction
|= (imm
& 0x00000fff);
7007 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7011 static void do_vfp_nsyn_opcode (const char *);
7014 do_vfp_nsyn_mrs (void)
7016 if (inst
.operands
[0].isvec
)
7018 if (inst
.operands
[1].reg
!= 1)
7019 first_error (_("operand 1 must be FPSCR"));
7020 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7021 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7022 do_vfp_nsyn_opcode ("fmstat");
7024 else if (inst
.operands
[1].isvec
)
7025 do_vfp_nsyn_opcode ("fmrx");
7033 do_vfp_nsyn_msr (void)
7035 if (inst
.operands
[0].isvec
)
7036 do_vfp_nsyn_opcode ("fmxr");
7046 if (do_vfp_nsyn_mrs () == SUCCESS
)
7049 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7050 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7052 _("'CPSR' or 'SPSR' expected"));
7053 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7054 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7057 /* Two possible forms:
7058 "{C|S}PSR_<field>, Rm",
7059 "{C|S}PSR_f, #expression". */
7064 if (do_vfp_nsyn_msr () == SUCCESS
)
7067 inst
.instruction
|= inst
.operands
[0].imm
;
7068 if (inst
.operands
[1].isreg
)
7069 inst
.instruction
|= inst
.operands
[1].reg
;
7072 inst
.instruction
|= INST_IMMEDIATE
;
7073 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7074 inst
.reloc
.pc_rel
= 0;
7081 if (!inst
.operands
[2].present
)
7082 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7083 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7084 inst
.instruction
|= inst
.operands
[1].reg
;
7085 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7087 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7088 as_tsktsk (_("rd and rm should be different in mul"));
7091 /* Long Multiply Parser
7092 UMULL RdLo, RdHi, Rm, Rs
7093 SMULL RdLo, RdHi, Rm, Rs
7094 UMLAL RdLo, RdHi, Rm, Rs
7095 SMLAL RdLo, RdHi, Rm, Rs. */
7100 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7101 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7102 inst
.instruction
|= inst
.operands
[2].reg
;
7103 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7105 /* rdhi, rdlo and rm must all be different. */
7106 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7107 || inst
.operands
[0].reg
== inst
.operands
[2].reg
7108 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7109 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7115 if (inst
.operands
[0].present
)
7117 /* Architectural NOP hints are CPSR sets with no bits selected. */
7118 inst
.instruction
&= 0xf0000000;
7119 inst
.instruction
|= 0x0320f000 + inst
.operands
[0].imm
;
7123 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7124 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7125 Condition defaults to COND_ALWAYS.
7126 Error if Rd, Rn or Rm are R15. */
7131 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7132 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7133 inst
.instruction
|= inst
.operands
[2].reg
;
7134 if (inst
.operands
[3].present
)
7135 encode_arm_shift (3);
7138 /* ARM V6 PKHTB (Argument Parse). */
7143 if (!inst
.operands
[3].present
)
7145 /* If the shift specifier is omitted, turn the instruction
7146 into pkhbt rd, rm, rn. */
7147 inst
.instruction
&= 0xfff00010;
7148 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7149 inst
.instruction
|= inst
.operands
[1].reg
;
7150 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7154 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7155 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7156 inst
.instruction
|= inst
.operands
[2].reg
;
7157 encode_arm_shift (3);
7161 /* ARMv5TE: Preload-Cache
7165 Syntactically, like LDR with B=1, W=0, L=1. */
7170 constraint (!inst
.operands
[0].isreg
,
7171 _("'[' expected after PLD mnemonic"));
7172 constraint (inst
.operands
[0].postind
,
7173 _("post-indexed expression used in preload instruction"));
7174 constraint (inst
.operands
[0].writeback
,
7175 _("writeback used in preload instruction"));
7176 constraint (!inst
.operands
[0].preind
,
7177 _("unindexed addressing used in preload instruction"));
7178 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7181 /* ARMv7: PLI <addr_mode> */
7185 constraint (!inst
.operands
[0].isreg
,
7186 _("'[' expected after PLI mnemonic"));
7187 constraint (inst
.operands
[0].postind
,
7188 _("post-indexed expression used in preload instruction"));
7189 constraint (inst
.operands
[0].writeback
,
7190 _("writeback used in preload instruction"));
7191 constraint (!inst
.operands
[0].preind
,
7192 _("unindexed addressing used in preload instruction"));
7193 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7194 inst
.instruction
&= ~PRE_INDEX
;
7200 inst
.operands
[1] = inst
.operands
[0];
7201 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7202 inst
.operands
[0].isreg
= 1;
7203 inst
.operands
[0].writeback
= 1;
7204 inst
.operands
[0].reg
= REG_SP
;
7208 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7209 word at the specified address and the following word
7211 Unconditionally executed.
7212 Error if Rn is R15. */
7217 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7218 if (inst
.operands
[0].writeback
)
7219 inst
.instruction
|= WRITE_BACK
;
7222 /* ARM V6 ssat (argument parse). */
7227 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7228 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7229 inst
.instruction
|= inst
.operands
[2].reg
;
7231 if (inst
.operands
[3].present
)
7232 encode_arm_shift (3);
7235 /* ARM V6 usat (argument parse). */
7240 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7241 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7242 inst
.instruction
|= inst
.operands
[2].reg
;
7244 if (inst
.operands
[3].present
)
7245 encode_arm_shift (3);
7248 /* ARM V6 ssat16 (argument parse). */
7253 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7254 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7255 inst
.instruction
|= inst
.operands
[2].reg
;
7261 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7262 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7263 inst
.instruction
|= inst
.operands
[2].reg
;
7266 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7267 preserving the other bits.
7269 setend <endian_specifier>, where <endian_specifier> is either
7275 if (inst
.operands
[0].imm
)
7276 inst
.instruction
|= 0x200;
7282 unsigned int Rm
= (inst
.operands
[1].present
7283 ? inst
.operands
[1].reg
7284 : inst
.operands
[0].reg
);
7286 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7287 inst
.instruction
|= Rm
;
7288 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7290 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7291 inst
.instruction
|= SHIFT_BY_REG
;
7294 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7300 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7301 inst
.reloc
.pc_rel
= 0;
7307 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7308 inst
.reloc
.pc_rel
= 0;
7311 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7312 SMLAxy{cond} Rd,Rm,Rs,Rn
7313 SMLAWy{cond} Rd,Rm,Rs,Rn
7314 Error if any register is R15. */
7319 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7320 inst
.instruction
|= inst
.operands
[1].reg
;
7321 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7322 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7325 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7326 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7327 Error if any register is R15.
7328 Warning if Rdlo == Rdhi. */
7333 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7334 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7335 inst
.instruction
|= inst
.operands
[2].reg
;
7336 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7338 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7339 as_tsktsk (_("rdhi and rdlo must be different"));
7342 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7343 SMULxy{cond} Rd,Rm,Rs
7344 Error if any register is R15. */
7349 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7350 inst
.instruction
|= inst
.operands
[1].reg
;
7351 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7354 /* ARM V6 srs (argument parse). */
7359 inst
.instruction
|= inst
.operands
[0].imm
;
7360 if (inst
.operands
[0].writeback
)
7361 inst
.instruction
|= WRITE_BACK
;
7364 /* ARM V6 strex (argument parse). */
7369 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7370 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7371 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7372 || inst
.operands
[2].negative
7373 /* See comment in do_ldrex(). */
7374 || (inst
.operands
[2].reg
== REG_PC
),
7377 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7378 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
7380 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7381 || inst
.reloc
.exp
.X_add_number
!= 0,
7382 _("offset must be zero in ARM encoding"));
7384 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7385 inst
.instruction
|= inst
.operands
[1].reg
;
7386 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7387 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7393 constraint (inst
.operands
[1].reg
% 2 != 0,
7394 _("even register required"));
7395 constraint (inst
.operands
[2].present
7396 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
7397 _("can only store two consecutive registers"));
7398 /* If op 2 were present and equal to PC, this function wouldn't
7399 have been called in the first place. */
7400 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
7402 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7403 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
7404 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
7407 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7408 inst
.instruction
|= inst
.operands
[1].reg
;
7409 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7412 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7413 extends it to 32-bits, and adds the result to a value in another
7414 register. You can specify a rotation by 0, 8, 16, or 24 bits
7415 before extracting the 16-bit value.
7416 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7417 Condition defaults to COND_ALWAYS.
7418 Error if any register uses R15. */
7423 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7424 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7425 inst
.instruction
|= inst
.operands
[2].reg
;
7426 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
7431 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
7432 Condition defaults to COND_ALWAYS.
7433 Error if any register uses R15. */
7438 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7439 inst
.instruction
|= inst
.operands
[1].reg
;
7440 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
7443 /* VFP instructions. In a logical order: SP variant first, monad
7444 before dyad, arithmetic then move then load/store. */
7447 do_vfp_sp_monadic (void)
7449 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7450 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7454 do_vfp_sp_dyadic (void)
7456 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7457 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7458 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7462 do_vfp_sp_compare_z (void)
7464 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7468 do_vfp_dp_sp_cvt (void)
7470 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7471 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7475 do_vfp_sp_dp_cvt (void)
7477 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7478 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7482 do_vfp_reg_from_sp (void)
7484 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7485 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7489 do_vfp_reg2_from_sp2 (void)
7491 constraint (inst
.operands
[2].imm
!= 2,
7492 _("only two consecutive VFP SP registers allowed here"));
7493 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7494 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7495 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7499 do_vfp_sp_from_reg (void)
7501 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
7502 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7506 do_vfp_sp2_from_reg2 (void)
7508 constraint (inst
.operands
[0].imm
!= 2,
7509 _("only two consecutive VFP SP registers allowed here"));
7510 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
7511 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7512 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7516 do_vfp_sp_ldst (void)
7518 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7519 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7523 do_vfp_dp_ldst (void)
7525 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7526 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7531 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
7533 if (inst
.operands
[0].writeback
)
7534 inst
.instruction
|= WRITE_BACK
;
7536 constraint (ldstm_type
!= VFP_LDSTMIA
,
7537 _("this addressing mode requires base-register writeback"));
7538 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7539 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
7540 inst
.instruction
|= inst
.operands
[1].imm
;
7544 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
7548 if (inst
.operands
[0].writeback
)
7549 inst
.instruction
|= WRITE_BACK
;
7551 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
7552 _("this addressing mode requires base-register writeback"));
7554 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7555 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7557 count
= inst
.operands
[1].imm
<< 1;
7558 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
7561 inst
.instruction
|= count
;
7565 do_vfp_sp_ldstmia (void)
7567 vfp_sp_ldstm (VFP_LDSTMIA
);
7571 do_vfp_sp_ldstmdb (void)
7573 vfp_sp_ldstm (VFP_LDSTMDB
);
7577 do_vfp_dp_ldstmia (void)
7579 vfp_dp_ldstm (VFP_LDSTMIA
);
7583 do_vfp_dp_ldstmdb (void)
7585 vfp_dp_ldstm (VFP_LDSTMDB
);
7589 do_vfp_xp_ldstmia (void)
7591 vfp_dp_ldstm (VFP_LDSTMIAX
);
7595 do_vfp_xp_ldstmdb (void)
7597 vfp_dp_ldstm (VFP_LDSTMDBX
);
7601 do_vfp_dp_rd_rm (void)
7603 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7604 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7608 do_vfp_dp_rn_rd (void)
7610 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
7611 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7615 do_vfp_dp_rd_rn (void)
7617 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7618 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7622 do_vfp_dp_rd_rn_rm (void)
7624 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7625 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7626 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
7632 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7636 do_vfp_dp_rm_rd_rn (void)
7638 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
7639 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7640 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
7643 /* VFPv3 instructions. */
7645 do_vfp_sp_const (void)
7647 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7648 inst
.instruction
|= (inst
.operands
[1].imm
& 15) << 16;
7649 inst
.instruction
|= (inst
.operands
[1].imm
>> 4);
7653 do_vfp_dp_const (void)
7655 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7656 inst
.instruction
|= (inst
.operands
[1].imm
& 15) << 16;
7657 inst
.instruction
|= (inst
.operands
[1].imm
>> 4);
7661 vfp_conv (int srcsize
)
7663 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
7664 inst
.instruction
|= (immbits
& 1) << 5;
7665 inst
.instruction
|= (immbits
>> 1);
7669 do_vfp_sp_conv_16 (void)
7671 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7676 do_vfp_dp_conv_16 (void)
7678 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7683 do_vfp_sp_conv_32 (void)
7685 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7690 do_vfp_dp_conv_32 (void)
7692 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7697 /* FPA instructions. Also in a logical order. */
7702 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7703 inst
.instruction
|= inst
.operands
[1].reg
;
7707 do_fpa_ldmstm (void)
7709 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7710 switch (inst
.operands
[1].imm
)
7712 case 1: inst
.instruction
|= CP_T_X
; break;
7713 case 2: inst
.instruction
|= CP_T_Y
; break;
7714 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
7719 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
7721 /* The instruction specified "ea" or "fd", so we can only accept
7722 [Rn]{!}. The instruction does not really support stacking or
7723 unstacking, so we have to emulate these by setting appropriate
7724 bits and offsets. */
7725 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7726 || inst
.reloc
.exp
.X_add_number
!= 0,
7727 _("this instruction does not support indexing"));
7729 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
7730 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
7732 if (!(inst
.instruction
& INDEX_UP
))
7733 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
7735 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
7737 inst
.operands
[2].preind
= 0;
7738 inst
.operands
[2].postind
= 1;
7742 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7746 /* iWMMXt instructions: strictly in alphabetical order. */
7749 do_iwmmxt_tandorc (void)
7751 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
7755 do_iwmmxt_textrc (void)
7757 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7758 inst
.instruction
|= inst
.operands
[1].imm
;
7762 do_iwmmxt_textrm (void)
7764 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7765 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7766 inst
.instruction
|= inst
.operands
[2].imm
;
7770 do_iwmmxt_tinsr (void)
7772 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7773 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7774 inst
.instruction
|= inst
.operands
[2].imm
;
7778 do_iwmmxt_tmia (void)
7780 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
7781 inst
.instruction
|= inst
.operands
[1].reg
;
7782 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7786 do_iwmmxt_waligni (void)
7788 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7789 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7790 inst
.instruction
|= inst
.operands
[2].reg
;
7791 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
7795 do_iwmmxt_wmov (void)
7797 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
7798 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7799 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7800 inst
.instruction
|= inst
.operands
[1].reg
;
7804 do_iwmmxt_wldstbh (void)
7807 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7809 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
7811 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
7812 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
7816 do_iwmmxt_wldstw (void)
7818 /* RIWR_RIWC clears .isreg for a control register. */
7819 if (!inst
.operands
[0].isreg
)
7821 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7822 inst
.instruction
|= 0xf0000000;
7825 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7826 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7830 do_iwmmxt_wldstd (void)
7832 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7833 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
7837 do_iwmmxt_wshufh (void)
7839 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7840 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7841 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
7842 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
7846 do_iwmmxt_wzero (void)
7848 /* WZERO reg is an alias for WANDN reg, reg, reg. */
7849 inst
.instruction
|= inst
.operands
[0].reg
;
7850 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7851 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7854 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
7855 operations first, then control, shift, and load/store. */
7857 /* Insns like "foo X,Y,Z". */
7860 do_mav_triple (void)
7862 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7863 inst
.instruction
|= inst
.operands
[1].reg
;
7864 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7867 /* Insns like "foo W,X,Y,Z".
7868 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
7873 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
7874 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7875 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7876 inst
.instruction
|= inst
.operands
[3].reg
;
7879 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
7883 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7886 /* Maverick shift immediate instructions.
7887 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
7888 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
7893 int imm
= inst
.operands
[2].imm
;
7895 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7896 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7898 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
7899 Bits 5-7 of the insn should have bits 4-6 of the immediate.
7900 Bit 4 should be 0. */
7901 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
7903 inst
.instruction
|= imm
;
7906 /* XScale instructions. Also sorted arithmetic before move. */
7908 /* Xscale multiply-accumulate (argument parse)
7911 MIAxycc acc0,Rm,Rs. */
7916 inst
.instruction
|= inst
.operands
[1].reg
;
7917 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7920 /* Xscale move-accumulator-register (argument parse)
7922 MARcc acc0,RdLo,RdHi. */
7927 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7928 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7931 /* Xscale move-register-accumulator (argument parse)
7933 MRAcc RdLo,RdHi,acc0. */
7938 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
7939 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7940 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7943 /* Encoding functions relevant only to Thumb. */
7945 /* inst.operands[i] is a shifted-register operand; encode
7946 it into inst.instruction in the format used by Thumb32. */
7949 encode_thumb32_shifted_operand (int i
)
7951 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
7952 unsigned int shift
= inst
.operands
[i
].shift_kind
;
7954 constraint (inst
.operands
[i
].immisreg
,
7955 _("shift by register not allowed in thumb mode"));
7956 inst
.instruction
|= inst
.operands
[i
].reg
;
7957 if (shift
== SHIFT_RRX
)
7958 inst
.instruction
|= SHIFT_ROR
<< 4;
7961 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
7962 _("expression too complex"));
7964 constraint (value
> 32
7965 || (value
== 32 && (shift
== SHIFT_LSL
7966 || shift
== SHIFT_ROR
)),
7967 _("shift expression is too large"));
7971 else if (value
== 32)
7974 inst
.instruction
|= shift
<< 4;
7975 inst
.instruction
|= (value
& 0x1c) << 10;
7976 inst
.instruction
|= (value
& 0x03) << 6;
7981 /* inst.operands[i] was set up by parse_address. Encode it into a
7982 Thumb32 format load or store instruction. Reject forms that cannot
7983 be used with such instructions. If is_t is true, reject forms that
7984 cannot be used with a T instruction; if is_d is true, reject forms
7985 that cannot be used with a D instruction. */
7988 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
7990 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7992 constraint (!inst
.operands
[i
].isreg
,
7993 _("Instruction does not support =N addresses"));
7995 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7996 if (inst
.operands
[i
].immisreg
)
7998 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
7999 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8000 constraint (inst
.operands
[i
].negative
,
8001 _("Thumb does not support negative register indexing"));
8002 constraint (inst
.operands
[i
].postind
,
8003 _("Thumb does not support register post-indexing"));
8004 constraint (inst
.operands
[i
].writeback
,
8005 _("Thumb does not support register indexing with writeback"));
8006 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8007 _("Thumb supports only LSL in shifted register indexing"));
8009 inst
.instruction
|= inst
.operands
[i
].imm
;
8010 if (inst
.operands
[i
].shifted
)
8012 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8013 _("expression too complex"));
8014 constraint (inst
.reloc
.exp
.X_add_number
< 0
8015 || inst
.reloc
.exp
.X_add_number
> 3,
8016 _("shift out of range"));
8017 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8019 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8021 else if (inst
.operands
[i
].preind
)
8023 constraint (is_pc
&& inst
.operands
[i
].writeback
,
8024 _("cannot use writeback with PC-relative addressing"));
8025 constraint (is_t
&& inst
.operands
[i
].writeback
,
8026 _("cannot use writeback with this instruction"));
8030 inst
.instruction
|= 0x01000000;
8031 if (inst
.operands
[i
].writeback
)
8032 inst
.instruction
|= 0x00200000;
8036 inst
.instruction
|= 0x00000c00;
8037 if (inst
.operands
[i
].writeback
)
8038 inst
.instruction
|= 0x00000100;
8040 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8042 else if (inst
.operands
[i
].postind
)
8044 assert (inst
.operands
[i
].writeback
);
8045 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8046 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8049 inst
.instruction
|= 0x00200000;
8051 inst
.instruction
|= 0x00000900;
8052 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8054 else /* unindexed - only for coprocessor */
8055 inst
.error
= _("instruction does not accept unindexed addressing");
8058 /* Table of Thumb instructions which exist in both 16- and 32-bit
8059 encodings (the latter only in post-V6T2 cores). The index is the
8060 value used in the insns table below. When there is more than one
8061 possible 16-bit encoding for the instruction, this table always
8063 Also contains several pseudo-instructions used during relaxation. */
8064 #define T16_32_TAB \
8065 X(adc, 4140, eb400000), \
8066 X(adcs, 4140, eb500000), \
8067 X(add, 1c00, eb000000), \
8068 X(adds, 1c00, eb100000), \
8069 X(addi, 0000, f1000000), \
8070 X(addis, 0000, f1100000), \
8071 X(add_pc,000f, f20f0000), \
8072 X(add_sp,000d, f10d0000), \
8073 X(adr, 000f, f20f0000), \
8074 X(and, 4000, ea000000), \
8075 X(ands, 4000, ea100000), \
8076 X(asr, 1000, fa40f000), \
8077 X(asrs, 1000, fa50f000), \
8078 X(b, e000, f000b000), \
8079 X(bcond, d000, f0008000), \
8080 X(bic, 4380, ea200000), \
8081 X(bics, 4380, ea300000), \
8082 X(cmn, 42c0, eb100f00), \
8083 X(cmp, 2800, ebb00f00), \
8084 X(cpsie, b660, f3af8400), \
8085 X(cpsid, b670, f3af8600), \
8086 X(cpy, 4600, ea4f0000), \
8087 X(dec_sp,80dd, f1bd0d00), \
8088 X(eor, 4040, ea800000), \
8089 X(eors, 4040, ea900000), \
8090 X(inc_sp,00dd, f10d0d00), \
8091 X(ldmia, c800, e8900000), \
8092 X(ldr, 6800, f8500000), \
8093 X(ldrb, 7800, f8100000), \
8094 X(ldrh, 8800, f8300000), \
8095 X(ldrsb, 5600, f9100000), \
8096 X(ldrsh, 5e00, f9300000), \
8097 X(ldr_pc,4800, f85f0000), \
8098 X(ldr_pc2,4800, f85f0000), \
8099 X(ldr_sp,9800, f85d0000), \
8100 X(lsl, 0000, fa00f000), \
8101 X(lsls, 0000, fa10f000), \
8102 X(lsr, 0800, fa20f000), \
8103 X(lsrs, 0800, fa30f000), \
8104 X(mov, 2000, ea4f0000), \
8105 X(movs, 2000, ea5f0000), \
8106 X(mul, 4340, fb00f000), \
8107 X(muls, 4340, ffffffff), /* no 32b muls */ \
8108 X(mvn, 43c0, ea6f0000), \
8109 X(mvns, 43c0, ea7f0000), \
8110 X(neg, 4240, f1c00000), /* rsb #0 */ \
8111 X(negs, 4240, f1d00000), /* rsbs #0 */ \
8112 X(orr, 4300, ea400000), \
8113 X(orrs, 4300, ea500000), \
8114 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8115 X(push, b400, e92d0000), /* stmdb sp!,... */ \
8116 X(rev, ba00, fa90f080), \
8117 X(rev16, ba40, fa90f090), \
8118 X(revsh, bac0, fa90f0b0), \
8119 X(ror, 41c0, fa60f000), \
8120 X(rors, 41c0, fa70f000), \
8121 X(sbc, 4180, eb600000), \
8122 X(sbcs, 4180, eb700000), \
8123 X(stmia, c000, e8800000), \
8124 X(str, 6000, f8400000), \
8125 X(strb, 7000, f8000000), \
8126 X(strh, 8000, f8200000), \
8127 X(str_sp,9000, f84d0000), \
8128 X(sub, 1e00, eba00000), \
8129 X(subs, 1e00, ebb00000), \
8130 X(subi, 8000, f1a00000), \
8131 X(subis, 8000, f1b00000), \
8132 X(sxtb, b240, fa4ff080), \
8133 X(sxth, b200, fa0ff080), \
8134 X(tst, 4200, ea100f00), \
8135 X(uxtb, b2c0, fa5ff080), \
8136 X(uxth, b280, fa1ff080), \
8137 X(nop, bf00, f3af8000), \
8138 X(yield, bf10, f3af8001), \
8139 X(wfe, bf20, f3af8002), \
8140 X(wfi, bf30, f3af8003), \
8141 X(sev, bf40, f3af9004), /* typo, 8004? */
8143 /* To catch errors in encoding functions, the codes are all offset by
8144 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8145 as 16-bit instructions. */
8146 #define X(a,b,c) T_MNEM_##a
8147 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8150 #define X(a,b,c) 0x##b
8151 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8152 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8155 #define X(a,b,c) 0x##c
8156 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8157 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8158 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8162 /* Thumb instruction encoders, in alphabetical order. */
8166 do_t_add_sub_w (void)
8170 Rd
= inst
.operands
[0].reg
;
8171 Rn
= inst
.operands
[1].reg
;
8173 constraint (Rd
== 15, _("PC not allowed as destination"));
8174 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8175 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8178 /* Parse an add or subtract instruction. We get here with inst.instruction
8179 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8186 Rd
= inst
.operands
[0].reg
;
8187 Rs
= (inst
.operands
[1].present
8188 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8189 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8197 flags
= (inst
.instruction
== T_MNEM_adds
8198 || inst
.instruction
== T_MNEM_subs
);
8200 narrow
= (current_it_mask
== 0);
8202 narrow
= (current_it_mask
!= 0);
8203 if (!inst
.operands
[2].isreg
)
8207 add
= (inst
.instruction
== T_MNEM_add
8208 || inst
.instruction
== T_MNEM_adds
);
8210 if (inst
.size_req
!= 4)
8212 /* Attempt to use a narrow opcode, with relaxation if
8214 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8215 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8216 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8217 opcode
= T_MNEM_add_sp
;
8218 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8219 opcode
= T_MNEM_add_pc
;
8220 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8223 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8225 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8229 inst
.instruction
= THUMB_OP16(opcode
);
8230 inst
.instruction
|= (Rd
<< 4) | Rs
;
8231 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8232 if (inst
.size_req
!= 2)
8233 inst
.relax
= opcode
;
8236 constraint (inst
.size_req
== 2, BAD_HIREG
);
8238 if (inst
.size_req
== 4
8239 || (inst
.size_req
!= 2 && !opcode
))
8243 /* Always use addw/subw. */
8244 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
8245 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8249 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8250 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
8253 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8255 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
8257 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8258 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8263 Rn
= inst
.operands
[2].reg
;
8264 /* See if we can do this with a 16-bit instruction. */
8265 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
8267 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8272 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
8273 || inst
.instruction
== T_MNEM_add
)
8276 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8280 if (inst
.instruction
== T_MNEM_add
)
8284 inst
.instruction
= T_OPCODE_ADD_HI
;
8285 inst
.instruction
|= (Rd
& 8) << 4;
8286 inst
.instruction
|= (Rd
& 7);
8287 inst
.instruction
|= Rn
<< 3;
8290 /* ... because addition is commutative! */
8293 inst
.instruction
= T_OPCODE_ADD_HI
;
8294 inst
.instruction
|= (Rd
& 8) << 4;
8295 inst
.instruction
|= (Rd
& 7);
8296 inst
.instruction
|= Rs
<< 3;
8301 /* If we get here, it can't be done in 16 bits. */
8302 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
8303 _("shift must be constant"));
8304 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8305 inst
.instruction
|= Rd
<< 8;
8306 inst
.instruction
|= Rs
<< 16;
8307 encode_thumb32_shifted_operand (2);
8312 constraint (inst
.instruction
== T_MNEM_adds
8313 || inst
.instruction
== T_MNEM_subs
,
8316 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
8318 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
8319 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
8322 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8324 inst
.instruction
|= (Rd
<< 4) | Rs
;
8325 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8329 Rn
= inst
.operands
[2].reg
;
8330 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
8332 /* We now have Rd, Rs, and Rn set to registers. */
8333 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8335 /* Can't do this for SUB. */
8336 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
8337 inst
.instruction
= T_OPCODE_ADD_HI
;
8338 inst
.instruction
|= (Rd
& 8) << 4;
8339 inst
.instruction
|= (Rd
& 7);
8341 inst
.instruction
|= Rn
<< 3;
8343 inst
.instruction
|= Rs
<< 3;
8345 constraint (1, _("dest must overlap one source register"));
8349 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8350 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
8351 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8359 if (unified_syntax
&& inst
.size_req
== 0 && inst
.operands
[0].reg
<= 7)
8361 /* Defer to section relaxation. */
8362 inst
.relax
= inst
.instruction
;
8363 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8364 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8366 else if (unified_syntax
&& inst
.size_req
!= 2)
8368 /* Generate a 32-bit opcode. */
8369 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8370 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8371 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
8372 inst
.reloc
.pc_rel
= 1;
8376 /* Generate a 16-bit opcode. */
8377 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8378 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8379 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
8380 inst
.reloc
.pc_rel
= 1;
8382 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8386 /* Arithmetic instructions for which there is just one 16-bit
8387 instruction encoding, and it allows only two low registers.
8388 For maximal compatibility with ARM syntax, we allow three register
8389 operands even when Thumb-32 instructions are not available, as long
8390 as the first two are identical. For instance, both "sbc r0,r1" and
8391 "sbc r0,r0,r1" are allowed. */
8397 Rd
= inst
.operands
[0].reg
;
8398 Rs
= (inst
.operands
[1].present
8399 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8400 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8401 Rn
= inst
.operands
[2].reg
;
8405 if (!inst
.operands
[2].isreg
)
8407 /* For an immediate, we always generate a 32-bit opcode;
8408 section relaxation will shrink it later if possible. */
8409 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8410 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8411 inst
.instruction
|= Rd
<< 8;
8412 inst
.instruction
|= Rs
<< 16;
8413 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8419 /* See if we can do this with a 16-bit instruction. */
8420 if (THUMB_SETS_FLAGS (inst
.instruction
))
8421 narrow
= current_it_mask
== 0;
8423 narrow
= current_it_mask
!= 0;
8425 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8427 if (inst
.operands
[2].shifted
)
8429 if (inst
.size_req
== 4)
8435 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8436 inst
.instruction
|= Rd
;
8437 inst
.instruction
|= Rn
<< 3;
8441 /* If we get here, it can't be done in 16 bits. */
8442 constraint (inst
.operands
[2].shifted
8443 && inst
.operands
[2].immisreg
,
8444 _("shift must be constant"));
8445 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8446 inst
.instruction
|= Rd
<< 8;
8447 inst
.instruction
|= Rs
<< 16;
8448 encode_thumb32_shifted_operand (2);
8453 /* On its face this is a lie - the instruction does set the
8454 flags. However, the only supported mnemonic in this mode
8456 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8458 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8459 _("unshifted register required"));
8460 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8461 constraint (Rd
!= Rs
,
8462 _("dest and source1 must be the same register"));
8464 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8465 inst
.instruction
|= Rd
;
8466 inst
.instruction
|= Rn
<< 3;
8470 /* Similarly, but for instructions where the arithmetic operation is
8471 commutative, so we can allow either of them to be different from
8472 the destination operand in a 16-bit instruction. For instance, all
8473 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
8480 Rd
= inst
.operands
[0].reg
;
8481 Rs
= (inst
.operands
[1].present
8482 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8483 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8484 Rn
= inst
.operands
[2].reg
;
8488 if (!inst
.operands
[2].isreg
)
8490 /* For an immediate, we always generate a 32-bit opcode;
8491 section relaxation will shrink it later if possible. */
8492 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8493 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8494 inst
.instruction
|= Rd
<< 8;
8495 inst
.instruction
|= Rs
<< 16;
8496 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8502 /* See if we can do this with a 16-bit instruction. */
8503 if (THUMB_SETS_FLAGS (inst
.instruction
))
8504 narrow
= current_it_mask
== 0;
8506 narrow
= current_it_mask
!= 0;
8508 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8510 if (inst
.operands
[2].shifted
)
8512 if (inst
.size_req
== 4)
8519 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8520 inst
.instruction
|= Rd
;
8521 inst
.instruction
|= Rn
<< 3;
8526 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8527 inst
.instruction
|= Rd
;
8528 inst
.instruction
|= Rs
<< 3;
8533 /* If we get here, it can't be done in 16 bits. */
8534 constraint (inst
.operands
[2].shifted
8535 && inst
.operands
[2].immisreg
,
8536 _("shift must be constant"));
8537 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8538 inst
.instruction
|= Rd
<< 8;
8539 inst
.instruction
|= Rs
<< 16;
8540 encode_thumb32_shifted_operand (2);
8545 /* On its face this is a lie - the instruction does set the
8546 flags. However, the only supported mnemonic in this mode
8548 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8550 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8551 _("unshifted register required"));
8552 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8554 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8555 inst
.instruction
|= Rd
;
8558 inst
.instruction
|= Rn
<< 3;
8560 inst
.instruction
|= Rs
<< 3;
8562 constraint (1, _("dest must overlap one source register"));
8569 if (inst
.operands
[0].present
)
8571 constraint ((inst
.instruction
& 0xf0) != 0x40
8572 && inst
.operands
[0].imm
!= 0xf,
8573 "bad barrier type");
8574 inst
.instruction
|= inst
.operands
[0].imm
;
8577 inst
.instruction
|= 0xf;
8583 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8584 constraint (msb
> 32, _("bit-field extends past end of register"));
8585 /* The instruction encoding stores the LSB and MSB,
8586 not the LSB and width. */
8587 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8588 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
8589 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
8590 inst
.instruction
|= msb
- 1;
8598 /* #0 in second position is alternative syntax for bfc, which is
8599 the same instruction but with REG_PC in the Rm field. */
8600 if (!inst
.operands
[1].isreg
)
8601 inst
.operands
[1].reg
= REG_PC
;
8603 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8604 constraint (msb
> 32, _("bit-field extends past end of register"));
8605 /* The instruction encoding stores the LSB and MSB,
8606 not the LSB and width. */
8607 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8608 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8609 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8610 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8611 inst
.instruction
|= msb
- 1;
8617 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8618 _("bit-field extends past end of register"));
8619 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8620 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8621 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8622 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8623 inst
.instruction
|= inst
.operands
[3].imm
- 1;
8626 /* ARM V5 Thumb BLX (argument parse)
8627 BLX <target_addr> which is BLX(1)
8628 BLX <Rm> which is BLX(2)
8629 Unfortunately, there are two different opcodes for this mnemonic.
8630 So, the insns[].value is not used, and the code here zaps values
8631 into inst.instruction.
8633 ??? How to take advantage of the additional two bits of displacement
8634 available in Thumb32 mode? Need new relocation? */
8639 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8640 if (inst
.operands
[0].isreg
)
8641 /* We have a register, so this is BLX(2). */
8642 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8645 /* No register. This must be BLX(1). */
8646 inst
.instruction
= 0xf000e800;
8648 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8649 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8652 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
8653 inst
.reloc
.pc_rel
= 1;
8663 if (current_it_mask
)
8665 /* Conditional branches inside IT blocks are encoded as unconditional
8668 /* A branch must be the last instruction in an IT block. */
8669 constraint (current_it_mask
!= 0x10, BAD_BRANCH
);
8674 if (cond
!= COND_ALWAYS
)
8675 opcode
= T_MNEM_bcond
;
8677 opcode
= inst
.instruction
;
8679 if (unified_syntax
&& inst
.size_req
== 4)
8681 inst
.instruction
= THUMB_OP32(opcode
);
8682 if (cond
== COND_ALWAYS
)
8683 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
8686 assert (cond
!= 0xF);
8687 inst
.instruction
|= cond
<< 22;
8688 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
8693 inst
.instruction
= THUMB_OP16(opcode
);
8694 if (cond
== COND_ALWAYS
)
8695 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
8698 inst
.instruction
|= cond
<< 8;
8699 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
8701 /* Allow section relaxation. */
8702 if (unified_syntax
&& inst
.size_req
!= 2)
8703 inst
.relax
= opcode
;
8706 inst
.reloc
.pc_rel
= 1;
8712 constraint (inst
.cond
!= COND_ALWAYS
,
8713 _("instruction is always unconditional"));
8714 if (inst
.operands
[0].present
)
8716 constraint (inst
.operands
[0].imm
> 255,
8717 _("immediate value out of range"));
8718 inst
.instruction
|= inst
.operands
[0].imm
;
8723 do_t_branch23 (void)
8725 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8726 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8727 inst
.reloc
.pc_rel
= 1;
8729 /* If the destination of the branch is a defined symbol which does not have
8730 the THUMB_FUNC attribute, then we must be calling a function which has
8731 the (interfacearm) attribute. We look for the Thumb entry point to that
8732 function and change the branch to refer to that function instead. */
8733 if ( inst
.reloc
.exp
.X_op
== O_symbol
8734 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8735 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8736 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8737 inst
.reloc
.exp
.X_add_symbol
=
8738 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
8744 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8745 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8746 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
8747 should cause the alignment to be checked once it is known. This is
8748 because BX PC only works if the instruction is word aligned. */
8754 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8755 if (inst
.operands
[0].reg
== REG_PC
)
8756 as_tsktsk (_("use of r15 in bxj is not really useful"));
8758 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8764 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8765 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8766 inst
.instruction
|= inst
.operands
[1].reg
;
8772 constraint (current_it_mask
, BAD_NOT_IT
);
8773 inst
.instruction
|= inst
.operands
[0].imm
;
8779 constraint (current_it_mask
, BAD_NOT_IT
);
8781 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
8782 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
8784 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
8785 inst
.instruction
= 0xf3af8000;
8786 inst
.instruction
|= imod
<< 9;
8787 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
8788 if (inst
.operands
[1].present
)
8789 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
8793 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
8794 && (inst
.operands
[0].imm
& 4),
8795 _("selected processor does not support 'A' form "
8796 "of this instruction"));
8797 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
8798 _("Thumb does not support the 2-argument "
8799 "form of this instruction"));
8800 inst
.instruction
|= inst
.operands
[0].imm
;
8804 /* THUMB CPY instruction (argument parse). */
8809 if (inst
.size_req
== 4)
8811 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
8812 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8813 inst
.instruction
|= inst
.operands
[1].reg
;
8817 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
8818 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
8819 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
8826 constraint (current_it_mask
, BAD_NOT_IT
);
8827 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
8828 inst
.instruction
|= inst
.operands
[0].reg
;
8829 inst
.reloc
.pc_rel
= 1;
8830 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
8836 inst
.instruction
|= inst
.operands
[0].imm
;
8842 if (!inst
.operands
[1].present
)
8843 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8844 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8845 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8846 inst
.instruction
|= inst
.operands
[2].reg
;
8852 if (unified_syntax
&& inst
.size_req
== 4)
8853 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8855 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8861 unsigned int cond
= inst
.operands
[0].imm
;
8863 constraint (current_it_mask
, BAD_NOT_IT
);
8864 current_it_mask
= (inst
.instruction
& 0xf) | 0x10;
8867 /* If the condition is a negative condition, invert the mask. */
8868 if ((cond
& 0x1) == 0x0)
8870 unsigned int mask
= inst
.instruction
& 0x000f;
8872 if ((mask
& 0x7) == 0)
8873 /* no conversion needed */;
8874 else if ((mask
& 0x3) == 0)
8876 else if ((mask
& 0x1) == 0)
8881 inst
.instruction
&= 0xfff0;
8882 inst
.instruction
|= mask
;
8885 inst
.instruction
|= cond
<< 4;
8891 /* This really doesn't seem worth it. */
8892 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
8893 _("expression too complex"));
8894 constraint (inst
.operands
[1].writeback
,
8895 _("Thumb load/store multiple does not support {reglist}^"));
8899 /* See if we can use a 16-bit instruction. */
8900 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
8901 && inst
.size_req
!= 4
8902 && inst
.operands
[0].reg
<= 7
8903 && !(inst
.operands
[1].imm
& ~0xff)
8904 && (inst
.instruction
== T_MNEM_stmia
8905 ? inst
.operands
[0].writeback
8906 : (inst
.operands
[0].writeback
8907 == !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))))
8909 if (inst
.instruction
== T_MNEM_stmia
8910 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
8911 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
8912 as_warn (_("value stored for r%d is UNPREDICTABLE"),
8913 inst
.operands
[0].reg
);
8915 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8916 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8917 inst
.instruction
|= inst
.operands
[1].imm
;
8921 if (inst
.operands
[1].imm
& (1 << 13))
8922 as_warn (_("SP should not be in register list"));
8923 if (inst
.instruction
== T_MNEM_stmia
)
8925 if (inst
.operands
[1].imm
& (1 << 15))
8926 as_warn (_("PC should not be in register list"));
8927 if (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
8928 as_warn (_("value stored for r%d is UNPREDICTABLE"),
8929 inst
.operands
[0].reg
);
8933 if (inst
.operands
[1].imm
& (1 << 14)
8934 && inst
.operands
[1].imm
& (1 << 15))
8935 as_warn (_("LR and PC should not both be in register list"));
8936 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
8937 && inst
.operands
[0].writeback
)
8938 as_warn (_("base register should not be in register list "
8939 "when written back"));
8941 if (inst
.instruction
< 0xffff)
8942 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8943 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8944 inst
.instruction
|= inst
.operands
[1].imm
;
8945 if (inst
.operands
[0].writeback
)
8946 inst
.instruction
|= WRITE_BACK
;
8951 constraint (inst
.operands
[0].reg
> 7
8952 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
8953 if (inst
.instruction
== T_MNEM_stmia
)
8955 if (!inst
.operands
[0].writeback
)
8956 as_warn (_("this instruction will write back the base register"));
8957 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
8958 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
8959 as_warn (_("value stored for r%d is UNPREDICTABLE"),
8960 inst
.operands
[0].reg
);
8964 if (!inst
.operands
[0].writeback
8965 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
8966 as_warn (_("this instruction will write back the base register"));
8967 else if (inst
.operands
[0].writeback
8968 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
8969 as_warn (_("this instruction will not write back the base register"));
8972 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8973 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8974 inst
.instruction
|= inst
.operands
[1].imm
;
8981 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8982 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8983 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8984 || inst
.operands
[1].negative
,
8987 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8988 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8989 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
8995 if (!inst
.operands
[1].present
)
8997 constraint (inst
.operands
[0].reg
== REG_LR
,
8998 _("r14 not allowed as first register "
8999 "when second register is omitted"));
9000 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9002 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9005 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9006 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9007 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9013 unsigned long opcode
;
9016 opcode
= inst
.instruction
;
9019 if (!inst
.operands
[1].isreg
)
9021 if (opcode
<= 0xffff)
9022 inst
.instruction
= THUMB_OP32 (opcode
);
9023 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9026 if (inst
.operands
[1].isreg
9027 && !inst
.operands
[1].writeback
9028 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9029 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9031 && inst
.size_req
!= 4)
9033 /* Insn may have a 16-bit form. */
9034 Rn
= inst
.operands
[1].reg
;
9035 if (inst
.operands
[1].immisreg
)
9037 inst
.instruction
= THUMB_OP16 (opcode
);
9039 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9042 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9043 && opcode
!= T_MNEM_ldrsb
)
9044 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9045 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9052 if (inst
.reloc
.pc_rel
)
9053 opcode
= T_MNEM_ldr_pc2
;
9055 opcode
= T_MNEM_ldr_pc
;
9059 if (opcode
== T_MNEM_ldr
)
9060 opcode
= T_MNEM_ldr_sp
;
9062 opcode
= T_MNEM_str_sp
;
9064 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9068 inst
.instruction
= inst
.operands
[0].reg
;
9069 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9071 inst
.instruction
|= THUMB_OP16 (opcode
);
9072 if (inst
.size_req
== 2)
9073 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9075 inst
.relax
= opcode
;
9079 /* Definitely a 32-bit variant. */
9080 inst
.instruction
= THUMB_OP32 (opcode
);
9081 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9082 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9086 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9088 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9090 /* Only [Rn,Rm] is acceptable. */
9091 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9092 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9093 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9094 || inst
.operands
[1].negative
,
9095 _("Thumb does not support this addressing mode"));
9096 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9100 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9101 if (!inst
.operands
[1].isreg
)
9102 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9105 constraint (!inst
.operands
[1].preind
9106 || inst
.operands
[1].shifted
9107 || inst
.operands
[1].writeback
,
9108 _("Thumb does not support this addressing mode"));
9109 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9111 constraint (inst
.instruction
& 0x0600,
9112 _("byte or halfword not valid for base register"));
9113 constraint (inst
.operands
[1].reg
== REG_PC
9114 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9115 _("r15 based store not allowed"));
9116 constraint (inst
.operands
[1].immisreg
,
9117 _("invalid base register for register offset"));
9119 if (inst
.operands
[1].reg
== REG_PC
)
9120 inst
.instruction
= T_OPCODE_LDR_PC
;
9121 else if (inst
.instruction
& THUMB_LOAD_BIT
)
9122 inst
.instruction
= T_OPCODE_LDR_SP
;
9124 inst
.instruction
= T_OPCODE_STR_SP
;
9126 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9127 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9131 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
9132 if (!inst
.operands
[1].immisreg
)
9134 /* Immediate offset. */
9135 inst
.instruction
|= inst
.operands
[0].reg
;
9136 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9137 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9141 /* Register offset. */
9142 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
9143 constraint (inst
.operands
[1].negative
,
9144 _("Thumb does not support this addressing mode"));
9147 switch (inst
.instruction
)
9149 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
9150 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
9151 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
9152 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
9153 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
9154 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
9155 case 0x5600 /* ldrsb */:
9156 case 0x5e00 /* ldrsh */: break;
9160 inst
.instruction
|= inst
.operands
[0].reg
;
9161 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9162 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
9168 if (!inst
.operands
[1].present
)
9170 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9171 constraint (inst
.operands
[0].reg
== REG_LR
,
9172 _("r14 not allowed here"));
9174 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9175 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9176 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
9183 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9184 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
9190 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9191 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9192 inst
.instruction
|= inst
.operands
[2].reg
;
9193 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9199 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9200 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9201 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9202 inst
.instruction
|= inst
.operands
[3].reg
;
9210 int r0off
= (inst
.instruction
== T_MNEM_mov
9211 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
9212 unsigned long opcode
;
9214 bfd_boolean low_regs
;
9216 low_regs
= (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7);
9217 opcode
= inst
.instruction
;
9218 if (current_it_mask
)
9219 narrow
= opcode
!= T_MNEM_movs
;
9221 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
9222 if (inst
.size_req
== 4
9223 || inst
.operands
[1].shifted
)
9226 if (!inst
.operands
[1].isreg
)
9228 /* Immediate operand. */
9229 if (current_it_mask
== 0 && opcode
== T_MNEM_mov
)
9231 if (low_regs
&& narrow
)
9233 inst
.instruction
= THUMB_OP16 (opcode
);
9234 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9235 if (inst
.size_req
== 2)
9236 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9238 inst
.relax
= opcode
;
9242 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9243 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9244 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9245 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9250 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9251 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9252 encode_thumb32_shifted_operand (1);
9255 switch (inst
.instruction
)
9258 inst
.instruction
= T_OPCODE_MOV_HR
;
9259 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9260 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9261 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9265 /* We know we have low registers at this point.
9266 Generate ADD Rd, Rs, #0. */
9267 inst
.instruction
= T_OPCODE_ADD_I3
;
9268 inst
.instruction
|= inst
.operands
[0].reg
;
9269 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9275 inst
.instruction
= T_OPCODE_CMP_LR
;
9276 inst
.instruction
|= inst
.operands
[0].reg
;
9277 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9281 inst
.instruction
= T_OPCODE_CMP_HR
;
9282 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9283 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9284 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9291 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9292 if (inst
.operands
[1].isreg
)
9294 if (inst
.operands
[0].reg
< 8 && inst
.operands
[1].reg
< 8)
9296 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
9297 since a MOV instruction produces unpredictable results. */
9298 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9299 inst
.instruction
= T_OPCODE_ADD_I3
;
9301 inst
.instruction
= T_OPCODE_CMP_LR
;
9303 inst
.instruction
|= inst
.operands
[0].reg
;
9304 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9308 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9309 inst
.instruction
= T_OPCODE_MOV_HR
;
9311 inst
.instruction
= T_OPCODE_CMP_HR
;
9317 constraint (inst
.operands
[0].reg
> 7,
9318 _("only lo regs allowed with immediate"));
9319 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9320 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9330 top
= (inst
.instruction
& 0x00800000) != 0;
9331 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
9333 constraint (top
, _(":lower16: not allowed this instruction"));
9334 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
9336 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
9338 constraint (!top
, _(":upper16: not allowed this instruction"));
9339 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
9342 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9343 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9345 imm
= inst
.reloc
.exp
.X_add_number
;
9346 inst
.instruction
|= (imm
& 0xf000) << 4;
9347 inst
.instruction
|= (imm
& 0x0800) << 15;
9348 inst
.instruction
|= (imm
& 0x0700) << 4;
9349 inst
.instruction
|= (imm
& 0x00ff);
9358 int r0off
= (inst
.instruction
== T_MNEM_mvn
9359 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
9362 if (inst
.size_req
== 4
9363 || inst
.instruction
> 0xffff
9364 || inst
.operands
[1].shifted
9365 || inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9367 else if (inst
.instruction
== T_MNEM_cmn
)
9369 else if (THUMB_SETS_FLAGS (inst
.instruction
))
9370 narrow
= (current_it_mask
== 0);
9372 narrow
= (current_it_mask
!= 0);
9374 if (!inst
.operands
[1].isreg
)
9376 /* For an immediate, we always generate a 32-bit opcode;
9377 section relaxation will shrink it later if possible. */
9378 if (inst
.instruction
< 0xffff)
9379 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9380 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9381 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9382 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9386 /* See if we can do this with a 16-bit instruction. */
9389 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9390 inst
.instruction
|= inst
.operands
[0].reg
;
9391 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9395 constraint (inst
.operands
[1].shifted
9396 && inst
.operands
[1].immisreg
,
9397 _("shift must be constant"));
9398 if (inst
.instruction
< 0xffff)
9399 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9400 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9401 encode_thumb32_shifted_operand (1);
9407 constraint (inst
.instruction
> 0xffff
9408 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
9409 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
9410 _("unshifted register required"));
9411 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9414 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9415 inst
.instruction
|= inst
.operands
[0].reg
;
9416 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9425 if (do_vfp_nsyn_mrs () == SUCCESS
)
9428 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
9431 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
9432 _("selected processor does not support "
9433 "requested special purpose register"));
9437 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9438 _("selected processor does not support "
9439 "requested special purpose register %x"));
9440 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9441 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
9442 _("'CPSR' or 'SPSR' expected"));
9445 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9446 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9447 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
9455 if (do_vfp_nsyn_msr () == SUCCESS
)
9458 constraint (!inst
.operands
[1].isreg
,
9459 _("Thumb encoding does not support an immediate here"));
9460 flags
= inst
.operands
[0].imm
;
9463 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9464 _("selected processor does not support "
9465 "requested special purpose register"));
9469 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
9470 _("selected processor does not support "
9471 "requested special purpose register"));
9474 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9475 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
9476 inst
.instruction
|= (flags
& 0xff);
9477 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9483 if (!inst
.operands
[2].present
)
9484 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9486 /* There is no 32-bit MULS and no 16-bit MUL. */
9487 if (unified_syntax
&& inst
.instruction
== T_MNEM_mul
)
9489 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9490 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9491 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9492 inst
.instruction
|= inst
.operands
[2].reg
<< 0;
9496 constraint (!unified_syntax
9497 && inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
9498 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9501 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9502 inst
.instruction
|= inst
.operands
[0].reg
;
9504 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9505 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9506 else if (inst
.operands
[0].reg
== inst
.operands
[2].reg
)
9507 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9509 constraint (1, _("dest must overlap one source register"));
9516 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9517 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9518 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9519 inst
.instruction
|= inst
.operands
[3].reg
;
9521 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9522 as_tsktsk (_("rdhi and rdlo must be different"));
9530 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
9532 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9533 inst
.instruction
|= inst
.operands
[0].imm
;
9537 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9538 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
9543 constraint (inst
.operands
[0].present
,
9544 _("Thumb does not support NOP with hints"));
9545 inst
.instruction
= 0x46c0;
9556 if (THUMB_SETS_FLAGS (inst
.instruction
))
9557 narrow
= (current_it_mask
== 0);
9559 narrow
= (current_it_mask
!= 0);
9560 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9562 if (inst
.size_req
== 4)
9567 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9568 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9569 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9573 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9574 inst
.instruction
|= inst
.operands
[0].reg
;
9575 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9580 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9582 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9584 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9585 inst
.instruction
|= inst
.operands
[0].reg
;
9586 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9593 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9594 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9595 inst
.instruction
|= inst
.operands
[2].reg
;
9596 if (inst
.operands
[3].present
)
9598 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
9599 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9600 _("expression too complex"));
9601 inst
.instruction
|= (val
& 0x1c) << 10;
9602 inst
.instruction
|= (val
& 0x03) << 6;
9609 if (!inst
.operands
[3].present
)
9610 inst
.instruction
&= ~0x00000020;
9617 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9621 do_t_push_pop (void)
9625 constraint (inst
.operands
[0].writeback
,
9626 _("push/pop do not support {reglist}^"));
9627 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9628 _("expression too complex"));
9630 mask
= inst
.operands
[0].imm
;
9631 if ((mask
& ~0xff) == 0)
9632 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9633 else if ((inst
.instruction
== T_MNEM_push
9634 && (mask
& ~0xff) == 1 << REG_LR
)
9635 || (inst
.instruction
== T_MNEM_pop
9636 && (mask
& ~0xff) == 1 << REG_PC
))
9638 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9639 inst
.instruction
|= THUMB_PP_PC_LR
;
9642 else if (unified_syntax
)
9644 if (mask
& (1 << 13))
9645 inst
.error
= _("SP not allowed in register list");
9646 if (inst
.instruction
== T_MNEM_push
)
9648 if (mask
& (1 << 15))
9649 inst
.error
= _("PC not allowed in register list");
9653 if (mask
& (1 << 14)
9654 && mask
& (1 << 15))
9655 inst
.error
= _("LR and PC should not both be in register list");
9657 if ((mask
& (mask
- 1)) == 0)
9659 /* Single register push/pop implemented as str/ldr. */
9660 if (inst
.instruction
== T_MNEM_push
)
9661 inst
.instruction
= 0xf84d0d04; /* str reg, [sp, #-4]! */
9663 inst
.instruction
= 0xf85d0b04; /* ldr reg, [sp], #4 */
9664 mask
= ffs(mask
) - 1;
9668 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9672 inst
.error
= _("invalid register list to push/pop instruction");
9676 inst
.instruction
|= mask
;
9682 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9683 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9689 if (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
9690 && inst
.size_req
!= 4)
9692 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9693 inst
.instruction
|= inst
.operands
[0].reg
;
9694 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9696 else if (unified_syntax
)
9698 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9699 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9700 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9701 inst
.instruction
|= inst
.operands
[1].reg
;
9704 inst
.error
= BAD_HIREG
;
9712 Rd
= inst
.operands
[0].reg
;
9713 Rs
= (inst
.operands
[1].present
9714 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9715 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9717 inst
.instruction
|= Rd
<< 8;
9718 inst
.instruction
|= Rs
<< 16;
9719 if (!inst
.operands
[2].isreg
)
9721 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9722 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9725 encode_thumb32_shifted_operand (2);
9731 constraint (current_it_mask
, BAD_NOT_IT
);
9732 if (inst
.operands
[0].imm
)
9733 inst
.instruction
|= 0x8;
9739 if (!inst
.operands
[1].present
)
9740 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9747 switch (inst
.instruction
)
9750 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
9752 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
9754 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
9756 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
9760 if (THUMB_SETS_FLAGS (inst
.instruction
))
9761 narrow
= (current_it_mask
== 0);
9763 narrow
= (current_it_mask
!= 0);
9764 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9766 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
9768 if (inst
.operands
[2].isreg
9769 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
9770 || inst
.operands
[2].reg
> 7))
9772 if (inst
.size_req
== 4)
9777 if (inst
.operands
[2].isreg
)
9779 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9780 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9781 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9782 inst
.instruction
|= inst
.operands
[2].reg
;
9786 inst
.operands
[1].shifted
= 1;
9787 inst
.operands
[1].shift_kind
= shift_kind
;
9788 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
9789 ? T_MNEM_movs
: T_MNEM_mov
);
9790 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9791 encode_thumb32_shifted_operand (1);
9792 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
9793 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9798 if (inst
.operands
[2].isreg
)
9802 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
9803 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
9804 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
9805 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
9809 inst
.instruction
|= inst
.operands
[0].reg
;
9810 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9816 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
9817 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
9818 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
9821 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
9822 inst
.instruction
|= inst
.operands
[0].reg
;
9823 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9829 constraint (inst
.operands
[0].reg
> 7
9830 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
9831 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9833 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
9835 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
9836 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
9837 _("source1 and dest must be same register"));
9839 switch (inst
.instruction
)
9841 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
9842 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
9843 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
9844 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
9848 inst
.instruction
|= inst
.operands
[0].reg
;
9849 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9853 switch (inst
.instruction
)
9855 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
9856 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
9857 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
9858 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
9861 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
9862 inst
.instruction
|= inst
.operands
[0].reg
;
9863 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9871 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9872 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9873 inst
.instruction
|= inst
.operands
[2].reg
;
9879 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9880 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9881 _("expression too complex"));
9882 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9883 inst
.instruction
|= (value
& 0xf000) >> 12;
9884 inst
.instruction
|= (value
& 0x0ff0);
9885 inst
.instruction
|= (value
& 0x000f) << 16;
9891 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9892 inst
.instruction
|= inst
.operands
[1].imm
- 1;
9893 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9895 if (inst
.operands
[3].present
)
9897 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9898 _("expression too complex"));
9900 if (inst
.reloc
.exp
.X_add_number
!= 0)
9902 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
9903 inst
.instruction
|= 0x00200000; /* sh bit */
9904 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
9905 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
9907 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9914 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9915 inst
.instruction
|= inst
.operands
[1].imm
- 1;
9916 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9922 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9923 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9924 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9925 || inst
.operands
[2].negative
,
9928 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9929 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9930 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9931 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9937 if (!inst
.operands
[2].present
)
9938 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
9940 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9941 || inst
.operands
[0].reg
== inst
.operands
[2].reg
9942 || inst
.operands
[0].reg
== inst
.operands
[3].reg
9943 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
9946 inst
.instruction
|= inst
.operands
[0].reg
;
9947 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9948 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9949 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9955 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9956 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9957 inst
.instruction
|= inst
.operands
[2].reg
;
9958 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
9964 if (inst
.instruction
<= 0xffff && inst
.size_req
!= 4
9965 && inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
9966 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
9968 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9969 inst
.instruction
|= inst
.operands
[0].reg
;
9970 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9972 else if (unified_syntax
)
9974 if (inst
.instruction
<= 0xffff)
9975 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9976 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9977 inst
.instruction
|= inst
.operands
[1].reg
;
9978 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
9982 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
9983 _("Thumb encoding does not support rotation"));
9984 constraint (1, BAD_HIREG
);
9991 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9999 half
= (inst
.instruction
& 0x10) != 0;
10000 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
10001 constraint (inst
.operands
[0].immisreg
,
10002 _("instruction requires register index"));
10003 constraint (inst
.operands
[0].imm
== 15,
10004 _("PC is not a valid index register"));
10005 constraint (!half
&& inst
.operands
[0].shifted
,
10006 _("instruction does not allow shifted index"));
10007 inst
.instruction
|= (inst
.operands
[0].reg
<< 16) | inst
.operands
[0].imm
;
10013 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10014 inst
.instruction
|= inst
.operands
[1].imm
;
10015 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10017 if (inst
.operands
[3].present
)
10019 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10020 _("expression too complex"));
10021 if (inst
.reloc
.exp
.X_add_number
!= 0)
10023 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10024 inst
.instruction
|= 0x00200000; /* sh bit */
10026 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10027 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10029 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10036 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10037 inst
.instruction
|= inst
.operands
[1].imm
;
10038 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10041 /* Neon instruction encoder helpers. */
10043 /* Encodings for the different types for various Neon opcodes. */
10045 /* An "invalid" code for the following tables. */
10048 struct neon_tab_entry
10051 unsigned float_or_poly
;
10052 unsigned scalar_or_imm
;
10055 /* Map overloaded Neon opcodes to their respective encodings. */
10056 #define NEON_ENC_TAB \
10057 X(vabd, 0x0000700, 0x1200d00, N_INV), \
10058 X(vmax, 0x0000600, 0x0000f00, N_INV), \
10059 X(vmin, 0x0000610, 0x0200f00, N_INV), \
10060 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
10061 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
10062 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
10063 X(vadd, 0x0000800, 0x0000d00, N_INV), \
10064 X(vsub, 0x1000800, 0x0200d00, N_INV), \
10065 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
10066 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
10067 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
10068 /* Register variants of the following two instructions are encoded as
10069 vcge / vcgt with the operands reversed. */ \
10070 X(vclt, 0x0000310, 0x1000e00, 0x1b10200), \
10071 X(vcle, 0x0000300, 0x1200e00, 0x1b10180), \
10072 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
10073 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
10074 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
10075 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
10076 X(vmlal, 0x0800800, N_INV, 0x0800240), \
10077 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
10078 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
10079 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
10080 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
10081 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
10082 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
10083 X(vshl, 0x0000400, N_INV, 0x0800510), \
10084 X(vqshl, 0x0000410, N_INV, 0x0800710), \
10085 X(vand, 0x0000110, N_INV, 0x0800030), \
10086 X(vbic, 0x0100110, N_INV, 0x0800030), \
10087 X(veor, 0x1000110, N_INV, N_INV), \
10088 X(vorn, 0x0300110, N_INV, 0x0800010), \
10089 X(vorr, 0x0200110, N_INV, 0x0800010), \
10090 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
10091 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
10092 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
10093 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
10094 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
10095 X(vst1, 0x0000000, 0x0800000, N_INV), \
10096 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
10097 X(vst2, 0x0000100, 0x0800100, N_INV), \
10098 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
10099 X(vst3, 0x0000200, 0x0800200, N_INV), \
10100 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
10101 X(vst4, 0x0000300, 0x0800300, N_INV), \
10102 X(vmovn, 0x1b20200, N_INV, N_INV), \
10103 X(vtrn, 0x1b20080, N_INV, N_INV), \
10104 X(vqmovn, 0x1b20200, N_INV, N_INV), \
10105 X(vqmovun, 0x1b20240, N_INV, N_INV), \
10106 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
10107 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \
10108 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \
10109 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
10110 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
10111 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
10112 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
10116 #define X(OPC,I,F,S) N_MNEM_##OPC
10121 static const struct neon_tab_entry neon_enc_tab
[] =
10123 #define X(OPC,I,F,S) { (I), (F), (S) }
10128 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10129 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10130 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10131 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10132 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10133 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10134 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10135 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10136 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10137 #define NEON_ENC_SINGLE(X) \
10138 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
10139 #define NEON_ENC_DOUBLE(X) \
10140 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
10142 /* Define shapes for instruction operands. The following mnemonic characters
10143 are used in this table:
10145 F - VFP S<n> register
10146 D - Neon D<n> register
10147 Q - Neon Q<n> register
10151 L - D<n> register list
10153 This table is used to generate various data:
10154 - enumerations of the form NS_DDR to be used as arguments to
10156 - a table classifying shapes into single, double, quad, mixed.
10157 - a table used to drive neon_select_shape.
10160 #define NEON_SHAPE_DEF \
10161 X(3, (D, D, D), DOUBLE), \
10162 X(3, (Q, Q, Q), QUAD), \
10163 X(3, (D, D, I), DOUBLE), \
10164 X(3, (Q, Q, I), QUAD), \
10165 X(3, (D, D, S), DOUBLE), \
10166 X(3, (Q, Q, S), QUAD), \
10167 X(2, (D, D), DOUBLE), \
10168 X(2, (Q, Q), QUAD), \
10169 X(2, (D, S), DOUBLE), \
10170 X(2, (Q, S), QUAD), \
10171 X(2, (D, R), DOUBLE), \
10172 X(2, (Q, R), QUAD), \
10173 X(2, (D, I), DOUBLE), \
10174 X(2, (Q, I), QUAD), \
10175 X(3, (D, L, D), DOUBLE), \
10176 X(2, (D, Q), MIXED), \
10177 X(2, (Q, D), MIXED), \
10178 X(3, (D, Q, I), MIXED), \
10179 X(3, (Q, D, I), MIXED), \
10180 X(3, (Q, D, D), MIXED), \
10181 X(3, (D, Q, Q), MIXED), \
10182 X(3, (Q, Q, D), MIXED), \
10183 X(3, (Q, D, S), MIXED), \
10184 X(3, (D, Q, S), MIXED), \
10185 X(4, (D, D, D, I), DOUBLE), \
10186 X(4, (Q, Q, Q, I), QUAD), \
10187 X(2, (F, F), SINGLE), \
10188 X(3, (F, F, F), SINGLE), \
10189 X(2, (F, I), SINGLE), \
10190 X(2, (F, D), MIXED), \
10191 X(2, (D, F), MIXED), \
10192 X(3, (F, F, I), MIXED), \
10193 X(4, (R, R, F, F), SINGLE), \
10194 X(4, (F, F, R, R), SINGLE), \
10195 X(3, (D, R, R), DOUBLE), \
10196 X(3, (R, R, D), DOUBLE), \
10197 X(2, (S, R), SINGLE), \
10198 X(2, (R, S), SINGLE), \
10199 X(2, (F, R), SINGLE), \
10200 X(2, (R, F), SINGLE)
10202 #define S2(A,B) NS_##A##B
10203 #define S3(A,B,C) NS_##A##B##C
10204 #define S4(A,B,C,D) NS_##A##B##C##D
10206 #define X(N, L, C) S##N L
10219 enum neon_shape_class
10227 #define X(N, L, C) SC_##C
10229 static enum neon_shape_class neon_shape_class
[] =
10247 /* Register widths of above. */
10248 static unsigned neon_shape_el_size
[] =
10259 struct neon_shape_info
10262 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
10265 #define S2(A,B) { SE_##A, SE_##B }
10266 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
10267 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
10269 #define X(N, L, C) { N, S##N L }
10271 static struct neon_shape_info neon_shape_tab
[] =
10281 /* Bit masks used in type checking given instructions.
10282 'N_EQK' means the type must be the same as (or based on in some way) the key
10283 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
10284 set, various other bits can be set as well in order to modify the meaning of
10285 the type constraint. */
10287 enum neon_type_mask
10309 N_KEY
= 0x100000, /* key element (main type specifier). */
10310 N_EQK
= 0x200000, /* given operand has the same type & size as the key. */
10311 N_VFP
= 0x400000, /* VFP mode: operand size must match register width. */
10312 N_DBL
= 0x000001, /* if N_EQK, this operand is twice the size. */
10313 N_HLF
= 0x000002, /* if N_EQK, this operand is half the size. */
10314 N_SGN
= 0x000004, /* if N_EQK, this operand is forced to be signed. */
10315 N_UNS
= 0x000008, /* if N_EQK, this operand is forced to be unsigned. */
10316 N_INT
= 0x000010, /* if N_EQK, this operand is forced to be integer. */
10317 N_FLT
= 0x000020, /* if N_EQK, this operand is forced to be float. */
10318 N_SIZ
= 0x000040, /* if N_EQK, this operand is forced to be size-only. */
10320 N_MAX_NONSPECIAL
= N_F64
10323 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
10325 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
10326 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
10327 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
10328 #define N_SUF_32 (N_SU_32 | N_F32)
10329 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
10330 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
10332 /* Pass this as the first type argument to neon_check_type to ignore types
10334 #define N_IGNORE_TYPE (N_KEY | N_EQK)
10336 /* Select a "shape" for the current instruction (describing register types or
10337 sizes) from a list of alternatives. Return NS_NULL if the current instruction
10338 doesn't fit. For non-polymorphic shapes, checking is usually done as a
10339 function of operand parsing, so this function doesn't need to be called.
10340 Shapes should be listed in order of decreasing length. */
10342 static enum neon_shape
10343 neon_select_shape (enum neon_shape shape
, ...)
10346 enum neon_shape first_shape
= shape
;
10348 /* Fix missing optional operands. FIXME: we don't know at this point how
10349 many arguments we should have, so this makes the assumption that we have
10350 > 1. This is true of all current Neon opcodes, I think, but may not be
10351 true in the future. */
10352 if (!inst
.operands
[1].present
)
10353 inst
.operands
[1] = inst
.operands
[0];
10355 va_start (ap
, shape
);
10357 for (; shape
!= NS_NULL
; shape
= va_arg (ap
, int))
10362 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
10364 if (!inst
.operands
[j
].present
)
10370 switch (neon_shape_tab
[shape
].el
[j
])
10373 if (!(inst
.operands
[j
].isreg
10374 && inst
.operands
[j
].isvec
10375 && inst
.operands
[j
].issingle
10376 && !inst
.operands
[j
].isquad
))
10381 if (!(inst
.operands
[j
].isreg
10382 && inst
.operands
[j
].isvec
10383 && !inst
.operands
[j
].isquad
10384 && !inst
.operands
[j
].issingle
))
10389 if (!(inst
.operands
[j
].isreg
10390 && !inst
.operands
[j
].isvec
))
10395 if (!(inst
.operands
[j
].isreg
10396 && inst
.operands
[j
].isvec
10397 && inst
.operands
[j
].isquad
10398 && !inst
.operands
[j
].issingle
))
10403 if (!(!inst
.operands
[j
].isreg
10404 && !inst
.operands
[j
].isscalar
))
10409 if (!(!inst
.operands
[j
].isreg
10410 && inst
.operands
[j
].isscalar
))
10424 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
10425 first_error (_("invalid instruction shape"));
10430 /* True if SHAPE is predominantly a quadword operation (most of the time, this
10431 means the Q bit should be set). */
10434 neon_quad (enum neon_shape shape
)
10436 return neon_shape_class
[shape
] == SC_QUAD
;
10440 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
10443 /* Allow modification to be made to types which are constrained to be
10444 based on the key element, based on bits set alongside N_EQK. */
10445 if ((typebits
& N_EQK
) != 0)
10447 if ((typebits
& N_HLF
) != 0)
10449 else if ((typebits
& N_DBL
) != 0)
10451 if ((typebits
& N_SGN
) != 0)
10452 *g_type
= NT_signed
;
10453 else if ((typebits
& N_UNS
) != 0)
10454 *g_type
= NT_unsigned
;
10455 else if ((typebits
& N_INT
) != 0)
10456 *g_type
= NT_integer
;
10457 else if ((typebits
& N_FLT
) != 0)
10458 *g_type
= NT_float
;
10459 else if ((typebits
& N_SIZ
) != 0)
10460 *g_type
= NT_untyped
;
10464 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
10465 operand type, i.e. the single type specified in a Neon instruction when it
10466 is the only one given. */
10468 static struct neon_type_el
10469 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
10471 struct neon_type_el dest
= *key
;
10473 assert ((thisarg
& N_EQK
) != 0);
10475 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
10480 /* Convert Neon type and size into compact bitmask representation. */
10482 static enum neon_type_mask
10483 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
10490 case 8: return N_8
;
10491 case 16: return N_16
;
10492 case 32: return N_32
;
10493 case 64: return N_64
;
10501 case 8: return N_I8
;
10502 case 16: return N_I16
;
10503 case 32: return N_I32
;
10504 case 64: return N_I64
;
10512 case 32: return N_F32
;
10513 case 64: return N_F64
;
10521 case 8: return N_P8
;
10522 case 16: return N_P16
;
10530 case 8: return N_S8
;
10531 case 16: return N_S16
;
10532 case 32: return N_S32
;
10533 case 64: return N_S64
;
10541 case 8: return N_U8
;
10542 case 16: return N_U16
;
10543 case 32: return N_U32
;
10544 case 64: return N_U64
;
10555 /* Convert compact Neon bitmask type representation to a type and size. Only
10556 handles the case where a single bit is set in the mask. */
10559 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
10560 enum neon_type_mask mask
)
10562 if ((mask
& N_EQK
) != 0)
10565 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
10567 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
10569 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
10571 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
10576 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
10578 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
10579 *type
= NT_unsigned
;
10580 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
10581 *type
= NT_integer
;
10582 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
10583 *type
= NT_untyped
;
10584 else if ((mask
& (N_P8
| N_P16
)) != 0)
10586 else if ((mask
& (N_F32
| N_F64
)) != 0)
10594 /* Modify a bitmask of allowed types. This is only needed for type
10598 modify_types_allowed (unsigned allowed
, unsigned mods
)
10601 enum neon_el_type type
;
10607 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
10609 if (el_type_of_type_chk (&type
, &size
, allowed
& i
) == SUCCESS
)
10611 neon_modify_type_size (mods
, &type
, &size
);
10612 destmask
|= type_chk_of_el_type (type
, size
);
10619 /* Check type and return type classification.
10620 The manual states (paraphrase): If one datatype is given, it indicates the
10622 - the second operand, if there is one
10623 - the operand, if there is no second operand
10624 - the result, if there are no operands.
10625 This isn't quite good enough though, so we use a concept of a "key" datatype
10626 which is set on a per-instruction basis, which is the one which matters when
10627 only one data type is written.
10628 Note: this function has side-effects (e.g. filling in missing operands). All
10629 Neon instructions should call it before performing bit encoding. */
10631 static struct neon_type_el
10632 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
10635 unsigned i
, pass
, key_el
= 0;
10636 unsigned types
[NEON_MAX_TYPE_ELS
];
10637 enum neon_el_type k_type
= NT_invtype
;
10638 unsigned k_size
= -1u;
10639 struct neon_type_el badtype
= {NT_invtype
, -1};
10640 unsigned key_allowed
= 0;
10642 /* Optional registers in Neon instructions are always (not) in operand 1.
10643 Fill in the missing operand here, if it was omitted. */
10644 if (els
> 1 && !inst
.operands
[1].present
)
10645 inst
.operands
[1] = inst
.operands
[0];
10647 /* Suck up all the varargs. */
10649 for (i
= 0; i
< els
; i
++)
10651 unsigned thisarg
= va_arg (ap
, unsigned);
10652 if (thisarg
== N_IGNORE_TYPE
)
10657 types
[i
] = thisarg
;
10658 if ((thisarg
& N_KEY
) != 0)
10663 if (inst
.vectype
.elems
> 0)
10664 for (i
= 0; i
< els
; i
++)
10665 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
10667 first_error (_("types specified in both the mnemonic and operands"));
10671 /* Duplicate inst.vectype elements here as necessary.
10672 FIXME: No idea if this is exactly the same as the ARM assembler,
10673 particularly when an insn takes one register and one non-register
10675 if (inst
.vectype
.elems
== 1 && els
> 1)
10678 inst
.vectype
.elems
= els
;
10679 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
10680 for (j
= 0; j
< els
; j
++)
10682 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
10685 else if (inst
.vectype
.elems
== 0 && els
> 0)
10688 /* No types were given after the mnemonic, so look for types specified
10689 after each operand. We allow some flexibility here; as long as the
10690 "key" operand has a type, we can infer the others. */
10691 for (j
= 0; j
< els
; j
++)
10692 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
10693 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
10695 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
10697 for (j
= 0; j
< els
; j
++)
10698 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
10699 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
10704 first_error (_("operand types can't be inferred"));
10708 else if (inst
.vectype
.elems
!= els
)
10710 first_error (_("type specifier has the wrong number of parts"));
10714 for (pass
= 0; pass
< 2; pass
++)
10716 for (i
= 0; i
< els
; i
++)
10718 unsigned thisarg
= types
[i
];
10719 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
10720 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
10721 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
10722 unsigned g_size
= inst
.vectype
.el
[i
].size
;
10724 /* Decay more-specific signed & unsigned types to sign-insensitive
10725 integer types if sign-specific variants are unavailable. */
10726 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
10727 && (types_allowed
& N_SU_ALL
) == 0)
10728 g_type
= NT_integer
;
10730 /* If only untyped args are allowed, decay any more specific types to
10731 them. Some instructions only care about signs for some element
10732 sizes, so handle that properly. */
10733 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
10734 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
10735 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
10736 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
10737 g_type
= NT_untyped
;
10741 if ((thisarg
& N_KEY
) != 0)
10745 key_allowed
= thisarg
& ~N_KEY
;
10750 if ((thisarg
& N_VFP
) != 0)
10752 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
10753 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
10755 /* In VFP mode, operands must match register widths. If we
10756 have a key operand, use its width, else use the width of
10757 the current operand. */
10763 if (regwidth
!= match
)
10765 first_error (_("operand size must match register width"));
10770 if ((thisarg
& N_EQK
) == 0)
10772 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
10774 if ((given_type
& types_allowed
) == 0)
10776 first_error (_("bad type in Neon instruction"));
10782 enum neon_el_type mod_k_type
= k_type
;
10783 unsigned mod_k_size
= k_size
;
10784 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
10785 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
10787 first_error (_("inconsistent types in Neon instruction"));
10795 return inst
.vectype
.el
[key_el
];
10798 /* Neon-style VFP instruction forwarding. */
10800 /* Thumb VFP instructions have 0xE in the condition field. */
10803 do_vfp_cond_or_thumb (void)
10806 inst
.instruction
|= 0xe0000000;
10808 inst
.instruction
|= inst
.cond
<< 28;
10811 /* Look up and encode a simple mnemonic, for use as a helper function for the
10812 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
10813 etc. It is assumed that operand parsing has already been done, and that the
10814 operands are in the form expected by the given opcode (this isn't necessarily
10815 the same as the form in which they were parsed, hence some massaging must
10816 take place before this function is called).
10817 Checks current arch version against that in the looked-up opcode. */
10820 do_vfp_nsyn_opcode (const char *opname
)
10822 const struct asm_opcode
*opcode
;
10824 opcode
= hash_find (arm_ops_hsh
, opname
);
10829 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
10830 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
10835 inst
.instruction
= opcode
->tvalue
;
10836 opcode
->tencode ();
10840 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
10841 opcode
->aencode ();
10846 do_vfp_nsyn_add_sub (enum neon_shape rs
)
10848 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
10853 do_vfp_nsyn_opcode ("fadds");
10855 do_vfp_nsyn_opcode ("fsubs");
10860 do_vfp_nsyn_opcode ("faddd");
10862 do_vfp_nsyn_opcode ("fsubd");
10866 /* Check operand types to see if this is a VFP instruction, and if so call
10870 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
10872 enum neon_shape rs
;
10873 struct neon_type_el et
;
10878 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
10879 et
= neon_check_type (2, rs
,
10880 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
10884 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
10885 et
= neon_check_type (3, rs
,
10886 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
10893 if (et
.type
!= NT_invtype
)
10905 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
10907 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
10912 do_vfp_nsyn_opcode ("fmacs");
10914 do_vfp_nsyn_opcode ("fmscs");
10919 do_vfp_nsyn_opcode ("fmacd");
10921 do_vfp_nsyn_opcode ("fmscd");
10926 do_vfp_nsyn_mul (enum neon_shape rs
)
10929 do_vfp_nsyn_opcode ("fmuls");
10931 do_vfp_nsyn_opcode ("fmuld");
10935 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
10937 int is_neg
= (inst
.instruction
& 0x80) != 0;
10938 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
10943 do_vfp_nsyn_opcode ("fnegs");
10945 do_vfp_nsyn_opcode ("fabss");
10950 do_vfp_nsyn_opcode ("fnegd");
10952 do_vfp_nsyn_opcode ("fabsd");
10956 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
10957 insns belong to Neon, and are handled elsewhere. */
10960 do_vfp_nsyn_ldm_stm (int is_dbmode
)
10962 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
10966 do_vfp_nsyn_opcode ("fldmdbs");
10968 do_vfp_nsyn_opcode ("fldmias");
10973 do_vfp_nsyn_opcode ("fstmdbs");
10975 do_vfp_nsyn_opcode ("fstmias");
10980 do_vfp_nsyn_sqrt (void)
10982 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
10983 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
10986 do_vfp_nsyn_opcode ("fsqrts");
10988 do_vfp_nsyn_opcode ("fsqrtd");
10992 do_vfp_nsyn_div (void)
10994 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
10995 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
10996 N_F32
| N_F64
| N_KEY
| N_VFP
);
10999 do_vfp_nsyn_opcode ("fdivs");
11001 do_vfp_nsyn_opcode ("fdivd");
11005 do_vfp_nsyn_nmul (void)
11007 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11008 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11009 N_F32
| N_F64
| N_KEY
| N_VFP
);
11013 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11014 do_vfp_sp_dyadic ();
11018 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11019 do_vfp_dp_rd_rn_rm ();
11021 do_vfp_cond_or_thumb ();
11025 do_vfp_nsyn_cmp (void)
11027 if (inst
.operands
[1].isreg
)
11029 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11030 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11034 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11035 do_vfp_sp_monadic ();
11039 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11040 do_vfp_dp_rd_rm ();
11045 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
11046 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
11048 switch (inst
.instruction
& 0x0fffffff)
11051 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
11054 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
11062 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11063 do_vfp_sp_compare_z ();
11067 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11071 do_vfp_cond_or_thumb ();
11075 nsyn_insert_sp (void)
11077 inst
.operands
[1] = inst
.operands
[0];
11078 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
11079 inst
.operands
[0].reg
= 13;
11080 inst
.operands
[0].isreg
= 1;
11081 inst
.operands
[0].writeback
= 1;
11082 inst
.operands
[0].present
= 1;
11086 do_vfp_nsyn_push (void)
11089 if (inst
.operands
[1].issingle
)
11090 do_vfp_nsyn_opcode ("fstmdbs");
11092 do_vfp_nsyn_opcode ("fstmdbd");
11096 do_vfp_nsyn_pop (void)
11099 if (inst
.operands
[1].issingle
)
11100 do_vfp_nsyn_opcode ("fldmdbs");
11102 do_vfp_nsyn_opcode ("fldmdbd");
11105 /* Fix up Neon data-processing instructions, ORing in the correct bits for
11106 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
11109 neon_dp_fixup (unsigned i
)
11113 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
11127 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
11131 neon_logbits (unsigned x
)
11133 return ffs (x
) - 4;
11136 #define LOW4(R) ((R) & 0xf)
11137 #define HI1(R) (((R) >> 4) & 1)
11139 /* Encode insns with bit pattern:
11141 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
11142 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
11144 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
11145 different meaning for some instruction. */
11148 neon_three_same (int isquad
, int ubit
, int size
)
11150 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11151 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11152 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
11153 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
11154 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
11155 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
11156 inst
.instruction
|= (isquad
!= 0) << 6;
11157 inst
.instruction
|= (ubit
!= 0) << 24;
11159 inst
.instruction
|= neon_logbits (size
) << 20;
11161 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11164 /* Encode instructions of the form:
11166 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
11167 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
11169 Don't write size if SIZE == -1. */
11172 neon_two_same (int qbit
, int ubit
, int size
)
11174 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11175 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11176 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11177 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11178 inst
.instruction
|= (qbit
!= 0) << 6;
11179 inst
.instruction
|= (ubit
!= 0) << 24;
11182 inst
.instruction
|= neon_logbits (size
) << 18;
11184 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11187 /* Neon instruction encoders, in approximate order of appearance. */
11190 do_neon_dyadic_i_su (void)
11192 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11193 struct neon_type_el et
= neon_check_type (3, rs
,
11194 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
11195 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11199 do_neon_dyadic_i64_su (void)
11201 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11202 struct neon_type_el et
= neon_check_type (3, rs
,
11203 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11204 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11208 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
11211 unsigned size
= et
.size
>> 3;
11212 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11213 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11214 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11215 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11216 inst
.instruction
|= (isquad
!= 0) << 6;
11217 inst
.instruction
|= immbits
<< 16;
11218 inst
.instruction
|= (size
>> 3) << 7;
11219 inst
.instruction
|= (size
& 0x7) << 19;
11221 inst
.instruction
|= (uval
!= 0) << 24;
11223 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11227 do_neon_shl_imm (void)
11229 if (!inst
.operands
[2].isreg
)
11231 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11232 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
11233 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11234 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
11238 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11239 struct neon_type_el et
= neon_check_type (3, rs
,
11240 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11241 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11242 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11247 do_neon_qshl_imm (void)
11249 if (!inst
.operands
[2].isreg
)
11251 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11252 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
11253 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11254 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
11255 inst
.operands
[2].imm
);
11259 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11260 struct neon_type_el et
= neon_check_type (3, rs
,
11261 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11262 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11263 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11268 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
11270 /* Handle .I8 and .I64 as pseudo-instructions. */
11274 /* Unfortunately, this will make everything apart from zero out-of-range.
11275 FIXME is this the intended semantics? There doesn't seem much point in
11276 accepting .I8 if so. */
11277 immediate
|= immediate
<< 8;
11281 /* Similarly, anything other than zero will be replicated in bits [63:32],
11282 which probably isn't want we want if we specified .I64. */
11283 if (immediate
!= 0)
11284 goto bad_immediate
;
11290 if (immediate
== (immediate
& 0x000000ff))
11292 *immbits
= immediate
;
11293 return (size
== 16) ? 0x9 : 0x1;
11295 else if (immediate
== (immediate
& 0x0000ff00))
11297 *immbits
= immediate
>> 8;
11298 return (size
== 16) ? 0xb : 0x3;
11300 else if (immediate
== (immediate
& 0x00ff0000))
11302 *immbits
= immediate
>> 16;
11305 else if (immediate
== (immediate
& 0xff000000))
11307 *immbits
= immediate
>> 24;
11312 first_error (_("immediate value out of range"));
11316 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
11320 neon_bits_same_in_bytes (unsigned imm
)
11322 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
11323 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
11324 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
11325 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
11328 /* For immediate of above form, return 0bABCD. */
11331 neon_squash_bits (unsigned imm
)
11333 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
11334 | ((imm
& 0x01000000) >> 21);
11337 /* Compress quarter-float representation to 0b...000 abcdefgh. */
11340 neon_qfloat_bits (unsigned imm
)
11342 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
11345 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
11346 the instruction. *OP is passed as the initial value of the op field, and
11347 may be set to a different value depending on the constant (i.e.
11348 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
11352 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, unsigned *immbits
,
11353 int *op
, int size
, enum neon_el_type type
)
11355 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
11357 if (size
!= 32 || *op
== 1)
11359 *immbits
= neon_qfloat_bits (immlo
);
11362 else if (size
== 64 && neon_bits_same_in_bytes (immhi
)
11363 && neon_bits_same_in_bytes (immlo
))
11365 /* Check this one first so we don't have to bother with immhi in later
11369 *immbits
= (neon_squash_bits (immhi
) << 4) | neon_squash_bits (immlo
);
11373 else if (immhi
!= 0)
11375 else if (immlo
== (immlo
& 0x000000ff))
11377 /* 64-bit case was already handled. Don't allow MVN with 8-bit
11379 if ((size
!= 8 && size
!= 16 && size
!= 32)
11380 || (size
== 8 && *op
== 1))
11383 return (size
== 8) ? 0xe : (size
== 16) ? 0x8 : 0x0;
11385 else if (immlo
== (immlo
& 0x0000ff00))
11387 if (size
!= 16 && size
!= 32)
11389 *immbits
= immlo
>> 8;
11390 return (size
== 16) ? 0xa : 0x2;
11392 else if (immlo
== (immlo
& 0x00ff0000))
11396 *immbits
= immlo
>> 16;
11399 else if (immlo
== (immlo
& 0xff000000))
11403 *immbits
= immlo
>> 24;
11406 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
11410 *immbits
= (immlo
>> 8) & 0xff;
11413 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
11417 *immbits
= (immlo
>> 16) & 0xff;
11424 /* Write immediate bits [7:0] to the following locations:
11426 |28/24|23 19|18 16|15 4|3 0|
11427 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
11429 This function is used by VMOV/VMVN/VORR/VBIC. */
11432 neon_write_immbits (unsigned immbits
)
11434 inst
.instruction
|= immbits
& 0xf;
11435 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
11436 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
11439 /* Invert low-order SIZE bits of XHI:XLO. */
11442 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
11444 unsigned immlo
= xlo
? *xlo
: 0;
11445 unsigned immhi
= xhi
? *xhi
: 0;
11450 immlo
= (~immlo
) & 0xff;
11454 immlo
= (~immlo
) & 0xffff;
11458 immhi
= (~immhi
) & 0xffffffff;
11459 /* fall through. */
11462 immlo
= (~immlo
) & 0xffffffff;
11477 do_neon_logic (void)
11479 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
11481 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11482 neon_check_type (3, rs
, N_IGNORE_TYPE
);
11483 /* U bit and size field were set as part of the bitmask. */
11484 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11485 neon_three_same (neon_quad (rs
), 0, -1);
11489 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
11490 struct neon_type_el et
= neon_check_type (2, rs
,
11491 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
11492 enum neon_opc opcode
= inst
.instruction
& 0x0fffffff;
11496 if (et
.type
== NT_invtype
)
11499 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11504 cmode
= neon_cmode_for_logic_imm (inst
.operands
[1].imm
, &immbits
,
11509 cmode
= neon_cmode_for_logic_imm (inst
.operands
[1].imm
, &immbits
,
11514 /* Pseudo-instruction for VBIC. */
11515 immbits
= inst
.operands
[1].imm
;
11516 neon_invert_size (&immbits
, 0, et
.size
);
11517 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11521 /* Pseudo-instruction for VORR. */
11522 immbits
= inst
.operands
[1].imm
;
11523 neon_invert_size (&immbits
, 0, et
.size
);
11524 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11534 inst
.instruction
|= neon_quad (rs
) << 6;
11535 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11536 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11537 inst
.instruction
|= cmode
<< 8;
11538 neon_write_immbits (immbits
);
11540 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11545 do_neon_bitfield (void)
11547 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11548 neon_check_type (3, rs
, N_IGNORE_TYPE
);
11549 neon_three_same (neon_quad (rs
), 0, -1);
11553 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
11556 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11557 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
11559 if (et
.type
== NT_float
)
11561 inst
.instruction
= NEON_ENC_FLOAT (inst
.instruction
);
11562 neon_three_same (neon_quad (rs
), 0, -1);
11566 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11567 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
11572 do_neon_dyadic_if_su (void)
11574 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
11578 do_neon_dyadic_if_su_d (void)
11580 /* This version only allow D registers, but that constraint is enforced during
11581 operand parsing so we don't need to do anything extra here. */
11582 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
11586 do_neon_dyadic_if_i (void)
11588 neon_dyadic_misc (NT_unsigned
, N_IF_32
, 0);
11592 do_neon_dyadic_if_i_d (void)
11594 neon_dyadic_misc (NT_unsigned
, N_IF_32
, 0);
11597 enum vfp_or_neon_is_neon_bits
11600 NEON_CHECK_ARCH
= 2
11603 /* Call this function if an instruction which may have belonged to the VFP or
11604 Neon instruction sets, but turned out to be a Neon instruction (due to the
11605 operand types involved, etc.). We have to check and/or fix-up a couple of
11608 - Make sure the user hasn't attempted to make a Neon instruction
11610 - Alter the value in the condition code field if necessary.
11611 - Make sure that the arch supports Neon instructions.
11613 Which of these operations take place depends on bits from enum
11614 vfp_or_neon_is_neon_bits.
11616 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
11617 current instruction's condition is COND_ALWAYS, the condition field is
11618 changed to inst.uncond_value. This is necessary because instructions shared
11619 between VFP and Neon may be conditional for the VFP variants only, and the
11620 unconditional Neon version must have, e.g., 0xF in the condition field. */
11623 vfp_or_neon_is_neon (unsigned check
)
11625 /* Conditions are always legal in Thumb mode (IT blocks). */
11626 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
11628 if (inst
.cond
!= COND_ALWAYS
)
11630 first_error (_(BAD_COND
));
11633 if (inst
.uncond_value
!= -1)
11634 inst
.instruction
|= inst
.uncond_value
<< 28;
11637 if ((check
& NEON_CHECK_ARCH
)
11638 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
11640 first_error (_(BAD_FPU
));
11648 do_neon_addsub_if_i (void)
11650 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
11653 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11656 /* The "untyped" case can't happen. Do this to stop the "U" bit being
11657 affected if we specify unsigned args. */
11658 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
11661 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
11663 V<op> A,B (A is operand 0, B is operand 2)
11668 so handle that case specially. */
11671 neon_exchange_operands (void)
11673 void *scratch
= alloca (sizeof (inst
.operands
[0]));
11674 if (inst
.operands
[1].present
)
11676 /* Swap operands[1] and operands[2]. */
11677 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
11678 inst
.operands
[1] = inst
.operands
[2];
11679 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
11683 inst
.operands
[1] = inst
.operands
[2];
11684 inst
.operands
[2] = inst
.operands
[0];
11689 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
11691 if (inst
.operands
[2].isreg
)
11694 neon_exchange_operands ();
11695 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
11699 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11700 struct neon_type_el et
= neon_check_type (2, rs
,
11701 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
11703 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11704 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11705 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11706 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11707 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11708 inst
.instruction
|= neon_quad (rs
) << 6;
11709 inst
.instruction
|= (et
.type
== NT_float
) << 10;
11710 inst
.instruction
|= neon_logbits (et
.size
) << 18;
11712 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11719 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
11723 do_neon_cmp_inv (void)
11725 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
11731 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
11734 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
11735 scalars, which are encoded in 5 bits, M : Rm.
11736 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
11737 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
11741 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
11743 unsigned regno
= NEON_SCALAR_REG (scalar
);
11744 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
11749 if (regno
> 7 || elno
> 3)
11751 return regno
| (elno
<< 3);
11754 if (regno
> 15 || elno
> 1)
11756 return regno
| (elno
<< 4);
11760 first_error (_("scalar out of range for multiply instruction"));
11766 /* Encode multiply / multiply-accumulate scalar instructions. */
11769 neon_mul_mac (struct neon_type_el et
, int ubit
)
11773 /* Give a more helpful error message if we have an invalid type. */
11774 if (et
.type
== NT_invtype
)
11777 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
11778 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11779 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11780 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
11781 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
11782 inst
.instruction
|= LOW4 (scalar
);
11783 inst
.instruction
|= HI1 (scalar
) << 5;
11784 inst
.instruction
|= (et
.type
== NT_float
) << 8;
11785 inst
.instruction
|= neon_logbits (et
.size
) << 20;
11786 inst
.instruction
|= (ubit
!= 0) << 24;
11788 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11792 do_neon_mac_maybe_scalar (void)
11794 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
11797 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11800 if (inst
.operands
[2].isscalar
)
11802 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
11803 struct neon_type_el et
= neon_check_type (3, rs
,
11804 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
11805 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
11806 neon_mul_mac (et
, neon_quad (rs
));
11809 do_neon_dyadic_if_i ();
11815 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11816 struct neon_type_el et
= neon_check_type (3, rs
,
11817 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
11818 neon_three_same (neon_quad (rs
), 0, et
.size
);
11821 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
11822 same types as the MAC equivalents. The polynomial type for this instruction
11823 is encoded the same as the integer type. */
11828 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
11831 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11834 if (inst
.operands
[2].isscalar
)
11835 do_neon_mac_maybe_scalar ();
11837 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
11841 do_neon_qdmulh (void)
11843 if (inst
.operands
[2].isscalar
)
11845 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
11846 struct neon_type_el et
= neon_check_type (3, rs
,
11847 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
11848 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
11849 neon_mul_mac (et
, neon_quad (rs
));
11853 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11854 struct neon_type_el et
= neon_check_type (3, rs
,
11855 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
11856 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11857 /* The U bit (rounding) comes from bit mask. */
11858 neon_three_same (neon_quad (rs
), 0, et
.size
);
11863 do_neon_fcmp_absolute (void)
11865 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11866 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
11867 /* Size field comes from bit mask. */
11868 neon_three_same (neon_quad (rs
), 1, -1);
11872 do_neon_fcmp_absolute_inv (void)
11874 neon_exchange_operands ();
11875 do_neon_fcmp_absolute ();
11879 do_neon_step (void)
11881 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11882 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
11883 neon_three_same (neon_quad (rs
), 0, -1);
11887 do_neon_abs_neg (void)
11889 enum neon_shape rs
;
11890 struct neon_type_el et
;
11892 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
11895 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11898 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
11899 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
11901 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11902 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11903 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11904 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11905 inst
.instruction
|= neon_quad (rs
) << 6;
11906 inst
.instruction
|= (et
.type
== NT_float
) << 10;
11907 inst
.instruction
|= neon_logbits (et
.size
) << 18;
11909 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11915 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11916 struct neon_type_el et
= neon_check_type (2, rs
,
11917 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
11918 int imm
= inst
.operands
[2].imm
;
11919 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
11920 _("immediate out of range for insert"));
11921 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
11927 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11928 struct neon_type_el et
= neon_check_type (2, rs
,
11929 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
11930 int imm
= inst
.operands
[2].imm
;
11931 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
11932 _("immediate out of range for insert"));
11933 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
11937 do_neon_qshlu_imm (void)
11939 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11940 struct neon_type_el et
= neon_check_type (2, rs
,
11941 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
11942 int imm
= inst
.operands
[2].imm
;
11943 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
11944 _("immediate out of range for shift"));
11945 /* Only encodes the 'U present' variant of the instruction.
11946 In this case, signed types have OP (bit 8) set to 0.
11947 Unsigned types have OP set to 1. */
11948 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
11949 /* The rest of the bits are the same as other immediate shifts. */
11950 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
11954 do_neon_qmovn (void)
11956 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
11957 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
11958 /* Saturating move where operands can be signed or unsigned, and the
11959 destination has the same signedness. */
11960 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11961 if (et
.type
== NT_unsigned
)
11962 inst
.instruction
|= 0xc0;
11964 inst
.instruction
|= 0x80;
11965 neon_two_same (0, 1, et
.size
/ 2);
11969 do_neon_qmovun (void)
11971 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
11972 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
11973 /* Saturating move with unsigned results. Operands must be signed. */
11974 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11975 neon_two_same (0, 1, et
.size
/ 2);
11979 do_neon_rshift_sat_narrow (void)
11981 /* FIXME: Types for narrowing. If operands are signed, results can be signed
11982 or unsigned. If operands are unsigned, results must also be unsigned. */
11983 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
11984 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
11985 int imm
= inst
.operands
[2].imm
;
11986 /* This gets the bounds check, size encoding and immediate bits calculation
11990 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
11991 VQMOVN.I<size> <Dd>, <Qm>. */
11994 inst
.operands
[2].present
= 0;
11995 inst
.instruction
= N_MNEM_vqmovn
;
12000 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12001 _("immediate out of range"));
12002 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
12006 do_neon_rshift_sat_narrow_u (void)
12008 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12009 or unsigned. If operands are unsigned, results must also be unsigned. */
12010 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12011 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12012 int imm
= inst
.operands
[2].imm
;
12013 /* This gets the bounds check, size encoding and immediate bits calculation
12017 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
12018 VQMOVUN.I<size> <Dd>, <Qm>. */
12021 inst
.operands
[2].present
= 0;
12022 inst
.instruction
= N_MNEM_vqmovun
;
12027 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12028 _("immediate out of range"));
12029 /* FIXME: The manual is kind of unclear about what value U should have in
12030 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
12032 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
12036 do_neon_movn (void)
12038 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12039 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12040 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12041 neon_two_same (0, 1, et
.size
/ 2);
12045 do_neon_rshift_narrow (void)
12047 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12048 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12049 int imm
= inst
.operands
[2].imm
;
12050 /* This gets the bounds check, size encoding and immediate bits calculation
12054 /* If immediate is zero then we are a pseudo-instruction for
12055 VMOVN.I<size> <Dd>, <Qm> */
12058 inst
.operands
[2].present
= 0;
12059 inst
.instruction
= N_MNEM_vmovn
;
12064 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12065 _("immediate out of range for narrowing operation"));
12066 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
12070 do_neon_shll (void)
12072 /* FIXME: Type checking when lengthening. */
12073 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
12074 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
12075 unsigned imm
= inst
.operands
[2].imm
;
12077 if (imm
== et
.size
)
12079 /* Maximum shift variant. */
12080 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12081 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12082 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12083 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12084 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12085 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12087 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12091 /* A more-specific type check for non-max versions. */
12092 et
= neon_check_type (2, NS_QDI
,
12093 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12094 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12095 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
12099 /* Check the various types for the VCVT instruction, and return which version
12100 the current instruction is. */
12103 neon_cvt_flavour (enum neon_shape rs
)
12105 #define CVT_VAR(C,X,Y) \
12106 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
12107 if (et.type != NT_invtype) \
12109 inst.error = NULL; \
12112 struct neon_type_el et
;
12113 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
12114 || rs
== NS_FF
) ? N_VFP
: 0;
12115 /* The instruction versions which take an immediate take one register
12116 argument, which is extended to the width of the full register. Thus the
12117 "source" and "destination" registers must have the same width. Hack that
12118 here by making the size equal to the key (wider, in this case) operand. */
12119 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
12121 CVT_VAR (0, N_S32
, N_F32
);
12122 CVT_VAR (1, N_U32
, N_F32
);
12123 CVT_VAR (2, N_F32
, N_S32
);
12124 CVT_VAR (3, N_F32
, N_U32
);
12128 /* VFP instructions. */
12129 CVT_VAR (4, N_F32
, N_F64
);
12130 CVT_VAR (5, N_F64
, N_F32
);
12131 CVT_VAR (6, N_S32
, N_F64
| key
);
12132 CVT_VAR (7, N_U32
, N_F64
| key
);
12133 CVT_VAR (8, N_F64
| key
, N_S32
);
12134 CVT_VAR (9, N_F64
| key
, N_U32
);
12135 /* VFP instructions with bitshift. */
12136 CVT_VAR (10, N_F32
| key
, N_S16
);
12137 CVT_VAR (11, N_F32
| key
, N_U16
);
12138 CVT_VAR (12, N_F64
| key
, N_S16
);
12139 CVT_VAR (13, N_F64
| key
, N_U16
);
12140 CVT_VAR (14, N_S16
, N_F32
| key
);
12141 CVT_VAR (15, N_U16
, N_F32
| key
);
12142 CVT_VAR (16, N_S16
, N_F64
| key
);
12143 CVT_VAR (17, N_U16
, N_F64
| key
);
12149 /* Neon-syntax VFP conversions. */
12152 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
12154 const char *opname
= 0;
12156 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
12158 /* Conversions with immediate bitshift. */
12159 const char *enc
[] =
12181 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12183 opname
= enc
[flavour
];
12184 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12185 _("operands 0 and 1 must be the same register"));
12186 inst
.operands
[1] = inst
.operands
[2];
12187 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
12192 /* Conversions without bitshift. */
12193 const char *enc
[] =
12207 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12208 opname
= enc
[flavour
];
12212 do_vfp_nsyn_opcode (opname
);
12216 do_vfp_nsyn_cvtz (void)
12218 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
12219 int flavour
= neon_cvt_flavour (rs
);
12220 const char *enc
[] =
12232 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
12233 do_vfp_nsyn_opcode (enc
[flavour
]);
12239 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
12240 NS_FD
, NS_DF
, NS_FF
, NS_NULL
);
12241 int flavour
= neon_cvt_flavour (rs
);
12243 /* VFP rather than Neon conversions. */
12246 do_vfp_nsyn_cvt (rs
, flavour
);
12255 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12258 /* Fixed-point conversion with #0 immediate is encoded as an
12259 integer conversion. */
12260 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
12262 unsigned immbits
= 32 - inst
.operands
[2].imm
;
12263 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
12264 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12266 inst
.instruction
|= enctab
[flavour
];
12267 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12268 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12269 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12270 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12271 inst
.instruction
|= neon_quad (rs
) << 6;
12272 inst
.instruction
|= 1 << 21;
12273 inst
.instruction
|= immbits
<< 16;
12275 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12283 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
12285 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12287 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12291 inst
.instruction
|= enctab
[flavour
];
12293 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12294 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12295 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12296 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12297 inst
.instruction
|= neon_quad (rs
) << 6;
12298 inst
.instruction
|= 2 << 18;
12300 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12305 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
12306 do_vfp_nsyn_cvt (rs
, flavour
);
12311 neon_move_immediate (void)
12313 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12314 struct neon_type_el et
= neon_check_type (2, rs
,
12315 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12316 unsigned immlo
, immhi
= 0, immbits
;
12319 constraint (et
.type
== NT_invtype
,
12320 _("operand size must be specified for immediate VMOV"));
12322 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
12323 op
= (inst
.instruction
& (1 << 5)) != 0;
12325 immlo
= inst
.operands
[1].imm
;
12326 if (inst
.operands
[1].regisimm
)
12327 immhi
= inst
.operands
[1].reg
;
12329 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
12330 _("immediate has bits set outside the operand size"));
12332 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, &immbits
, &op
,
12333 et
.size
, et
.type
)) == FAIL
)
12335 /* Invert relevant bits only. */
12336 neon_invert_size (&immlo
, &immhi
, et
.size
);
12337 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
12338 with one or the other; those cases are caught by
12339 neon_cmode_for_move_imm. */
12341 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, &immbits
, &op
,
12342 et
.size
, et
.type
)) == FAIL
)
12344 first_error (_("immediate out of range"));
12349 inst
.instruction
&= ~(1 << 5);
12350 inst
.instruction
|= op
<< 5;
12352 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12353 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12354 inst
.instruction
|= neon_quad (rs
) << 6;
12355 inst
.instruction
|= cmode
<< 8;
12357 neon_write_immbits (immbits
);
12363 if (inst
.operands
[1].isreg
)
12365 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12367 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12368 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12369 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12370 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12371 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12372 inst
.instruction
|= neon_quad (rs
) << 6;
12376 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12377 neon_move_immediate ();
12380 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12383 /* Encode instructions of form:
12385 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12386 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm |
12391 neon_mixed_length (struct neon_type_el et
, unsigned size
)
12393 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12394 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12395 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12396 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12397 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12398 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12399 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
12400 inst
.instruction
|= neon_logbits (size
) << 20;
12402 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12406 do_neon_dyadic_long (void)
12408 /* FIXME: Type checking for lengthening op. */
12409 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12410 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12411 neon_mixed_length (et
, et
.size
);
12415 do_neon_abal (void)
12417 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12418 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12419 neon_mixed_length (et
, et
.size
);
12423 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
12425 if (inst
.operands
[2].isscalar
)
12427 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
12428 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
12429 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12430 neon_mul_mac (et
, et
.type
== NT_unsigned
);
12434 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12435 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
12436 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12437 neon_mixed_length (et
, et
.size
);
12442 do_neon_mac_maybe_scalar_long (void)
12444 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
12448 do_neon_dyadic_wide (void)
12450 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
12451 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12452 neon_mixed_length (et
, et
.size
);
12456 do_neon_dyadic_narrow (void)
12458 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12459 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
12460 neon_mixed_length (et
, et
.size
/ 2);
12464 do_neon_mul_sat_scalar_long (void)
12466 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
12470 do_neon_vmull (void)
12472 if (inst
.operands
[2].isscalar
)
12473 do_neon_mac_maybe_scalar_long ();
12476 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12477 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
12478 if (et
.type
== NT_poly
)
12479 inst
.instruction
= NEON_ENC_POLY (inst
.instruction
);
12481 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12482 /* For polynomial encoding, size field must be 0b00 and the U bit must be
12483 zero. Should be OK as-is. */
12484 neon_mixed_length (et
, et
.size
);
12491 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
12492 struct neon_type_el et
= neon_check_type (3, rs
,
12493 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12494 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
12495 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12496 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12497 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12498 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12499 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12500 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12501 inst
.instruction
|= neon_quad (rs
) << 6;
12502 inst
.instruction
|= imm
<< 8;
12504 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12510 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12511 struct neon_type_el et
= neon_check_type (2, rs
,
12512 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12513 unsigned op
= (inst
.instruction
>> 7) & 3;
12514 /* N (width of reversed regions) is encoded as part of the bitmask. We
12515 extract it here to check the elements to be reversed are smaller.
12516 Otherwise we'd get a reserved instruction. */
12517 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
12518 assert (elsize
!= 0);
12519 constraint (et
.size
>= elsize
,
12520 _("elements must be smaller than reversal region"));
12521 neon_two_same (neon_quad (rs
), 1, et
.size
);
12527 if (inst
.operands
[1].isscalar
)
12529 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
12530 struct neon_type_el et
= neon_check_type (2, rs
,
12531 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12532 unsigned sizebits
= et
.size
>> 3;
12533 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
12534 int logsize
= neon_logbits (et
.size
);
12535 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
12537 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
12540 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12541 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12542 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12543 inst
.instruction
|= LOW4 (dm
);
12544 inst
.instruction
|= HI1 (dm
) << 5;
12545 inst
.instruction
|= neon_quad (rs
) << 6;
12546 inst
.instruction
|= x
<< 17;
12547 inst
.instruction
|= sizebits
<< 16;
12549 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12553 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
12554 struct neon_type_el et
= neon_check_type (2, rs
,
12555 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
12556 /* Duplicate ARM register to lanes of vector. */
12557 inst
.instruction
= NEON_ENC_ARMREG (inst
.instruction
);
12560 case 8: inst
.instruction
|= 0x400000; break;
12561 case 16: inst
.instruction
|= 0x000020; break;
12562 case 32: inst
.instruction
|= 0x000000; break;
12565 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
12566 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
12567 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
12568 inst
.instruction
|= neon_quad (rs
) << 21;
12569 /* The encoding for this instruction is identical for the ARM and Thumb
12570 variants, except for the condition field. */
12571 do_vfp_cond_or_thumb ();
12575 /* VMOV has particularly many variations. It can be one of:
12576 0. VMOV<c><q> <Qd>, <Qm>
12577 1. VMOV<c><q> <Dd>, <Dm>
12578 (Register operations, which are VORR with Rm = Rn.)
12579 2. VMOV<c><q>.<dt> <Qd>, #<imm>
12580 3. VMOV<c><q>.<dt> <Dd>, #<imm>
12582 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
12583 (ARM register to scalar.)
12584 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
12585 (Two ARM registers to vector.)
12586 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
12587 (Scalar to ARM register.)
12588 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
12589 (Vector to two ARM registers.)
12590 8. VMOV.F32 <Sd>, <Sm>
12591 9. VMOV.F64 <Dd>, <Dm>
12592 (VFP register moves.)
12593 10. VMOV.F32 <Sd>, #imm
12594 11. VMOV.F64 <Dd>, #imm
12595 (VFP float immediate load.)
12596 12. VMOV <Rd>, <Sm>
12597 (VFP single to ARM reg.)
12598 13. VMOV <Sd>, <Rm>
12599 (ARM reg to VFP single.)
12600 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
12601 (Two ARM regs to two VFP singles.)
12602 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
12603 (Two VFP singles to two ARM regs.)
12605 These cases can be disambiguated using neon_select_shape, except cases 1/9
12606 and 3/11 which depend on the operand type too.
12608 All the encoded bits are hardcoded by this function.
12610 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
12611 Cases 5, 7 may be used with VFPv2 and above.
12613 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
12614 can specify a type where it doesn't make sense to, and is ignored).
12620 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
12621 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
12623 struct neon_type_el et
;
12624 const char *ldconst
= 0;
12628 case NS_DD
: /* case 1/9. */
12629 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
12630 /* It is not an error here if no type is given. */
12632 if (et
.type
== NT_float
&& et
.size
== 64)
12634 do_vfp_nsyn_opcode ("fcpyd");
12637 /* fall through. */
12639 case NS_QQ
: /* case 0/1. */
12641 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12643 /* The architecture manual I have doesn't explicitly state which
12644 value the U bit should have for register->register moves, but
12645 the equivalent VORR instruction has U = 0, so do that. */
12646 inst
.instruction
= 0x0200110;
12647 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12648 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12649 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12650 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12651 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12652 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12653 inst
.instruction
|= neon_quad (rs
) << 6;
12655 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12659 case NS_DI
: /* case 3/11. */
12660 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
12662 if (et
.type
== NT_float
&& et
.size
== 64)
12664 /* case 11 (fconstd). */
12665 ldconst
= "fconstd";
12666 goto encode_fconstd
;
12668 /* fall through. */
12670 case NS_QI
: /* case 2/3. */
12671 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12673 inst
.instruction
= 0x0800010;
12674 neon_move_immediate ();
12675 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12678 case NS_SR
: /* case 4. */
12680 unsigned bcdebits
= 0;
12681 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
12682 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
12683 int logsize
= neon_logbits (et
.size
);
12684 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
12685 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
12687 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
12689 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
12690 && et
.size
!= 32, _(BAD_FPU
));
12691 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
12692 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
12696 case 8: bcdebits
= 0x8; break;
12697 case 16: bcdebits
= 0x1; break;
12698 case 32: bcdebits
= 0x0; break;
12702 bcdebits
|= x
<< logsize
;
12704 inst
.instruction
= 0xe000b10;
12705 do_vfp_cond_or_thumb ();
12706 inst
.instruction
|= LOW4 (dn
) << 16;
12707 inst
.instruction
|= HI1 (dn
) << 7;
12708 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12709 inst
.instruction
|= (bcdebits
& 3) << 5;
12710 inst
.instruction
|= (bcdebits
>> 2) << 21;
12714 case NS_DRR
: /* case 5 (fmdrr). */
12715 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
12718 inst
.instruction
= 0xc400b10;
12719 do_vfp_cond_or_thumb ();
12720 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
12721 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
12722 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12723 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12726 case NS_RS
: /* case 6. */
12728 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
12729 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
12730 unsigned logsize
= neon_logbits (et
.size
);
12731 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
12732 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
12733 unsigned abcdebits
= 0;
12735 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
12737 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
12738 && et
.size
!= 32, _(BAD_FPU
));
12739 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
12740 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
12744 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
12745 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
12746 case 32: abcdebits
= 0x00; break;
12750 abcdebits
|= x
<< logsize
;
12751 inst
.instruction
= 0xe100b10;
12752 do_vfp_cond_or_thumb ();
12753 inst
.instruction
|= LOW4 (dn
) << 16;
12754 inst
.instruction
|= HI1 (dn
) << 7;
12755 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12756 inst
.instruction
|= (abcdebits
& 3) << 5;
12757 inst
.instruction
|= (abcdebits
>> 2) << 21;
12761 case NS_RRD
: /* case 7 (fmrrd). */
12762 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
12765 inst
.instruction
= 0xc500b10;
12766 do_vfp_cond_or_thumb ();
12767 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12768 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12769 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12770 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12773 case NS_FF
: /* case 8 (fcpys). */
12774 do_vfp_nsyn_opcode ("fcpys");
12777 case NS_FI
: /* case 10 (fconsts). */
12778 ldconst
= "fconsts";
12780 if (is_quarter_float (inst
.operands
[1].imm
))
12782 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
12783 do_vfp_nsyn_opcode (ldconst
);
12786 first_error (_("immediate out of range"));
12789 case NS_RF
: /* case 12 (fmrs). */
12790 do_vfp_nsyn_opcode ("fmrs");
12793 case NS_FR
: /* case 13 (fmsr). */
12794 do_vfp_nsyn_opcode ("fmsr");
12797 /* The encoders for the fmrrs and fmsrr instructions expect three operands
12798 (one of which is a list), but we have parsed four. Do some fiddling to
12799 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
12801 case NS_RRFF
: /* case 14 (fmrrs). */
12802 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
12803 _("VFP registers must be adjacent"));
12804 inst
.operands
[2].imm
= 2;
12805 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
12806 do_vfp_nsyn_opcode ("fmrrs");
12809 case NS_FFRR
: /* case 15 (fmsrr). */
12810 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
12811 _("VFP registers must be adjacent"));
12812 inst
.operands
[1] = inst
.operands
[2];
12813 inst
.operands
[2] = inst
.operands
[3];
12814 inst
.operands
[0].imm
= 2;
12815 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
12816 do_vfp_nsyn_opcode ("fmsrr");
12825 do_neon_rshift_round_imm (void)
12827 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12828 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12829 int imm
= inst
.operands
[2].imm
;
12831 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
12834 inst
.operands
[2].present
= 0;
12839 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12840 _("immediate out of range for shift"));
12841 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12846 do_neon_movl (void)
12848 struct neon_type_el et
= neon_check_type (2, NS_QD
,
12849 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12850 unsigned sizebits
= et
.size
>> 3;
12851 inst
.instruction
|= sizebits
<< 19;
12852 neon_two_same (0, et
.type
== NT_unsigned
, -1);
12858 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12859 struct neon_type_el et
= neon_check_type (2, rs
,
12860 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12861 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12862 neon_two_same (neon_quad (rs
), 1, et
.size
);
12866 do_neon_zip_uzp (void)
12868 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12869 struct neon_type_el et
= neon_check_type (2, rs
,
12870 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12871 if (rs
== NS_DD
&& et
.size
== 32)
12873 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
12874 inst
.instruction
= N_MNEM_vtrn
;
12878 neon_two_same (neon_quad (rs
), 1, et
.size
);
12882 do_neon_sat_abs_neg (void)
12884 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12885 struct neon_type_el et
= neon_check_type (2, rs
,
12886 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
12887 neon_two_same (neon_quad (rs
), 1, et
.size
);
12891 do_neon_pair_long (void)
12893 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12894 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
12895 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
12896 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
12897 neon_two_same (neon_quad (rs
), 1, et
.size
);
12901 do_neon_recip_est (void)
12903 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12904 struct neon_type_el et
= neon_check_type (2, rs
,
12905 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
12906 inst
.instruction
|= (et
.type
== NT_float
) << 8;
12907 neon_two_same (neon_quad (rs
), 1, et
.size
);
12913 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12914 struct neon_type_el et
= neon_check_type (2, rs
,
12915 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
12916 neon_two_same (neon_quad (rs
), 1, et
.size
);
12922 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12923 struct neon_type_el et
= neon_check_type (2, rs
,
12924 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
12925 neon_two_same (neon_quad (rs
), 1, et
.size
);
12931 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12932 struct neon_type_el et
= neon_check_type (2, rs
,
12933 N_EQK
| N_INT
, N_8
| N_KEY
);
12934 neon_two_same (neon_quad (rs
), 1, et
.size
);
12940 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12941 neon_two_same (neon_quad (rs
), 1, -1);
12945 do_neon_tbl_tbx (void)
12947 unsigned listlenbits
;
12948 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
12950 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
12952 first_error (_("bad list length for table lookup"));
12956 listlenbits
= inst
.operands
[1].imm
- 1;
12957 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12958 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12959 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12960 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12961 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12962 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12963 inst
.instruction
|= listlenbits
<< 8;
12965 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12969 do_neon_ldm_stm (void)
12971 /* P, U and L bits are part of bitmask. */
12972 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
12973 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
12975 if (inst
.operands
[1].issingle
)
12977 do_vfp_nsyn_ldm_stm (is_dbmode
);
12981 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
12982 _("writeback (!) must be used for VLDMDB and VSTMDB"));
12984 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
12985 _("register list must contain at least 1 and at most 16 "
12988 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
12989 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
12990 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
12991 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
12993 inst
.instruction
|= offsetbits
;
12995 do_vfp_cond_or_thumb ();
12999 do_neon_ldr_str (void)
13001 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
13003 if (inst
.operands
[0].issingle
)
13006 do_vfp_nsyn_opcode ("flds");
13008 do_vfp_nsyn_opcode ("fsts");
13013 do_vfp_nsyn_opcode ("fldd");
13015 do_vfp_nsyn_opcode ("fstd");
13019 /* "interleave" version also handles non-interleaving register VLD1/VST1
13023 do_neon_ld_st_interleave (void)
13025 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
13026 N_8
| N_16
| N_32
| N_64
);
13027 unsigned alignbits
= 0;
13029 /* The bits in this table go:
13030 0: register stride of one (0) or two (1)
13031 1,2: register list length, minus one (1, 2, 3, 4).
13032 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
13033 We use -1 for invalid entries. */
13034 const int typetable
[] =
13036 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
13037 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
13038 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
13039 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
13043 if (et
.type
== NT_invtype
)
13046 if (inst
.operands
[1].immisalign
)
13047 switch (inst
.operands
[1].imm
>> 8)
13049 case 64: alignbits
= 1; break;
13051 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13052 goto bad_alignment
;
13056 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13057 goto bad_alignment
;
13062 first_error (_("bad alignment"));
13066 inst
.instruction
|= alignbits
<< 4;
13067 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13069 /* Bits [4:6] of the immediate in a list specifier encode register stride
13070 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
13071 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
13072 up the right value for "type" in a table based on this value and the given
13073 list style, then stick it back. */
13074 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
13075 | (((inst
.instruction
>> 8) & 3) << 3);
13077 typebits
= typetable
[idx
];
13079 constraint (typebits
== -1, _("bad list type for instruction"));
13081 inst
.instruction
&= ~0xf00;
13082 inst
.instruction
|= typebits
<< 8;
13085 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
13086 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
13087 otherwise. The variable arguments are a list of pairs of legal (size, align)
13088 values, terminated with -1. */
13091 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
13094 int result
= FAIL
, thissize
, thisalign
;
13096 if (!inst
.operands
[1].immisalign
)
13102 va_start (ap
, do_align
);
13106 thissize
= va_arg (ap
, int);
13107 if (thissize
== -1)
13109 thisalign
= va_arg (ap
, int);
13111 if (size
== thissize
&& align
== thisalign
)
13114 while (result
!= SUCCESS
);
13118 if (result
== SUCCESS
)
13121 first_error (_("unsupported alignment for instruction"));
13127 do_neon_ld_st_lane (void)
13129 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13130 int align_good
, do_align
= 0;
13131 int logsize
= neon_logbits (et
.size
);
13132 int align
= inst
.operands
[1].imm
>> 8;
13133 int n
= (inst
.instruction
>> 8) & 3;
13134 int max_el
= 64 / et
.size
;
13136 if (et
.type
== NT_invtype
)
13139 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
13140 _("bad list length"));
13141 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
13142 _("scalar index out of range"));
13143 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
13145 _("stride of 2 unavailable when element size is 8"));
13149 case 0: /* VLD1 / VST1. */
13150 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
13152 if (align_good
== FAIL
)
13156 unsigned alignbits
= 0;
13159 case 16: alignbits
= 0x1; break;
13160 case 32: alignbits
= 0x3; break;
13163 inst
.instruction
|= alignbits
<< 4;
13167 case 1: /* VLD2 / VST2. */
13168 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
13170 if (align_good
== FAIL
)
13173 inst
.instruction
|= 1 << 4;
13176 case 2: /* VLD3 / VST3. */
13177 constraint (inst
.operands
[1].immisalign
,
13178 _("can't use alignment with this instruction"));
13181 case 3: /* VLD4 / VST4. */
13182 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13183 16, 64, 32, 64, 32, 128, -1);
13184 if (align_good
== FAIL
)
13188 unsigned alignbits
= 0;
13191 case 8: alignbits
= 0x1; break;
13192 case 16: alignbits
= 0x1; break;
13193 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
13196 inst
.instruction
|= alignbits
<< 4;
13203 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
13204 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13205 inst
.instruction
|= 1 << (4 + logsize
);
13207 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
13208 inst
.instruction
|= logsize
<< 10;
13211 /* Encode single n-element structure to all lanes VLD<n> instructions. */
13214 do_neon_ld_dup (void)
13216 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13217 int align_good
, do_align
= 0;
13219 if (et
.type
== NT_invtype
)
13222 switch ((inst
.instruction
>> 8) & 3)
13224 case 0: /* VLD1. */
13225 assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
13226 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13227 &do_align
, 16, 16, 32, 32, -1);
13228 if (align_good
== FAIL
)
13230 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
13233 case 2: inst
.instruction
|= 1 << 5; break;
13234 default: first_error (_("bad list length")); return;
13236 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13239 case 1: /* VLD2. */
13240 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13241 &do_align
, 8, 16, 16, 32, 32, 64, -1);
13242 if (align_good
== FAIL
)
13244 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
13245 _("bad list length"));
13246 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13247 inst
.instruction
|= 1 << 5;
13248 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13251 case 2: /* VLD3. */
13252 constraint (inst
.operands
[1].immisalign
,
13253 _("can't use alignment with this instruction"));
13254 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
13255 _("bad list length"));
13256 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13257 inst
.instruction
|= 1 << 5;
13258 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13261 case 3: /* VLD4. */
13263 int align
= inst
.operands
[1].imm
>> 8;
13264 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13265 16, 64, 32, 64, 32, 128, -1);
13266 if (align_good
== FAIL
)
13268 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
13269 _("bad list length"));
13270 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13271 inst
.instruction
|= 1 << 5;
13272 if (et
.size
== 32 && align
== 128)
13273 inst
.instruction
|= 0x3 << 6;
13275 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13282 inst
.instruction
|= do_align
<< 4;
13285 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
13286 apart from bits [11:4]. */
13289 do_neon_ldx_stx (void)
13291 switch (NEON_LANE (inst
.operands
[0].imm
))
13293 case NEON_INTERLEAVE_LANES
:
13294 inst
.instruction
= NEON_ENC_INTERLV (inst
.instruction
);
13295 do_neon_ld_st_interleave ();
13298 case NEON_ALL_LANES
:
13299 inst
.instruction
= NEON_ENC_DUP (inst
.instruction
);
13304 inst
.instruction
= NEON_ENC_LANE (inst
.instruction
);
13305 do_neon_ld_st_lane ();
13308 /* L bit comes from bit mask. */
13309 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13310 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13311 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13313 if (inst
.operands
[1].postind
)
13315 int postreg
= inst
.operands
[1].imm
& 0xf;
13316 constraint (!inst
.operands
[1].immisreg
,
13317 _("post-index must be a register"));
13318 constraint (postreg
== 0xd || postreg
== 0xf,
13319 _("bad register for post-index"));
13320 inst
.instruction
|= postreg
;
13322 else if (inst
.operands
[1].writeback
)
13324 inst
.instruction
|= 0xd;
13327 inst
.instruction
|= 0xf;
13330 inst
.instruction
|= 0xf9000000;
13332 inst
.instruction
|= 0xf4000000;
13336 /* Overall per-instruction processing. */
13338 /* We need to be able to fix up arbitrary expressions in some statements.
13339 This is so that we can handle symbols that are an arbitrary distance from
13340 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
13341 which returns part of an address in a form which will be valid for
13342 a data instruction. We do this by pushing the expression into a symbol
13343 in the expr_section, and creating a fix for that. */
13346 fix_new_arm (fragS
* frag
,
13361 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
13365 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
13370 /* Mark whether the fix is to a THUMB instruction, or an ARM
13372 new_fix
->tc_fix_data
= thumb_mode
;
13375 /* Create a frg for an instruction requiring relaxation. */
13377 output_relax_insn (void)
13384 /* The size of the instruction is unknown, so tie the debug info to the
13385 start of the instruction. */
13386 dwarf2_emit_insn (0);
13389 switch (inst
.reloc
.exp
.X_op
)
13392 sym
= inst
.reloc
.exp
.X_add_symbol
;
13393 offset
= inst
.reloc
.exp
.X_add_number
;
13397 offset
= inst
.reloc
.exp
.X_add_number
;
13400 sym
= make_expr_symbol (&inst
.reloc
.exp
);
13404 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
13405 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
13406 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
13409 /* Write a 32-bit thumb instruction to buf. */
13411 put_thumb32_insn (char * buf
, unsigned long insn
)
13413 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
13414 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
13418 output_inst (const char * str
)
13424 as_bad ("%s -- `%s'", inst
.error
, str
);
13428 output_relax_insn();
13431 if (inst
.size
== 0)
13434 to
= frag_more (inst
.size
);
13436 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
13438 assert (inst
.size
== (2 * THUMB_SIZE
));
13439 put_thumb32_insn (to
, inst
.instruction
);
13441 else if (inst
.size
> INSN_SIZE
)
13443 assert (inst
.size
== (2 * INSN_SIZE
));
13444 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
13445 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
13448 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
13450 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
13451 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
13452 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
13456 dwarf2_emit_insn (inst
.size
);
13460 /* Tag values used in struct asm_opcode's tag field. */
13463 OT_unconditional
, /* Instruction cannot be conditionalized.
13464 The ARM condition field is still 0xE. */
13465 OT_unconditionalF
, /* Instruction cannot be conditionalized
13466 and carries 0xF in its ARM condition field. */
13467 OT_csuffix
, /* Instruction takes a conditional suffix. */
13468 OT_csuffixF
, /* Some forms of the instruction take a conditional
13469 suffix, others place 0xF where the condition field
13471 OT_cinfix3
, /* Instruction takes a conditional infix,
13472 beginning at character index 3. (In
13473 unified mode, it becomes a suffix.) */
13474 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
13475 tsts, cmps, cmns, and teqs. */
13476 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
13477 character index 3, even in unified mode. Used for
13478 legacy instructions where suffix and infix forms
13479 may be ambiguous. */
13480 OT_csuf_or_in3
, /* Instruction takes either a conditional
13481 suffix or an infix at character index 3. */
13482 OT_odd_infix_unc
, /* This is the unconditional variant of an
13483 instruction that takes a conditional infix
13484 at an unusual position. In unified mode,
13485 this variant will accept a suffix. */
13486 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
13487 are the conditional variants of instructions that
13488 take conditional infixes in unusual positions.
13489 The infix appears at character index
13490 (tag - OT_odd_infix_0). These are not accepted
13491 in unified mode. */
13494 /* Subroutine of md_assemble, responsible for looking up the primary
13495 opcode from the mnemonic the user wrote. STR points to the
13496 beginning of the mnemonic.
13498 This is not simply a hash table lookup, because of conditional
13499 variants. Most instructions have conditional variants, which are
13500 expressed with a _conditional affix_ to the mnemonic. If we were
13501 to encode each conditional variant as a literal string in the opcode
13502 table, it would have approximately 20,000 entries.
13504 Most mnemonics take this affix as a suffix, and in unified syntax,
13505 'most' is upgraded to 'all'. However, in the divided syntax, some
13506 instructions take the affix as an infix, notably the s-variants of
13507 the arithmetic instructions. Of those instructions, all but six
13508 have the infix appear after the third character of the mnemonic.
13510 Accordingly, the algorithm for looking up primary opcodes given
13513 1. Look up the identifier in the opcode table.
13514 If we find a match, go to step U.
13516 2. Look up the last two characters of the identifier in the
13517 conditions table. If we find a match, look up the first N-2
13518 characters of the identifier in the opcode table. If we
13519 find a match, go to step CE.
13521 3. Look up the fourth and fifth characters of the identifier in
13522 the conditions table. If we find a match, extract those
13523 characters from the identifier, and look up the remaining
13524 characters in the opcode table. If we find a match, go
13529 U. Examine the tag field of the opcode structure, in case this is
13530 one of the six instructions with its conditional infix in an
13531 unusual place. If it is, the tag tells us where to find the
13532 infix; look it up in the conditions table and set inst.cond
13533 accordingly. Otherwise, this is an unconditional instruction.
13534 Again set inst.cond accordingly. Return the opcode structure.
13536 CE. Examine the tag field to make sure this is an instruction that
13537 should receive a conditional suffix. If it is not, fail.
13538 Otherwise, set inst.cond from the suffix we already looked up,
13539 and return the opcode structure.
13541 CM. Examine the tag field to make sure this is an instruction that
13542 should receive a conditional infix after the third character.
13543 If it is not, fail. Otherwise, undo the edits to the current
13544 line of input and proceed as for case CE. */
13546 static const struct asm_opcode
*
13547 opcode_lookup (char **str
)
13551 const struct asm_opcode
*opcode
;
13552 const struct asm_cond
*cond
;
13555 /* Scan up to the end of the mnemonic, which must end in white space,
13556 '.' (in unified mode only), or end of string. */
13557 for (base
= end
= *str
; *end
!= '\0'; end
++)
13558 if (*end
== ' ' || (unified_syntax
&& *end
== '.'))
13564 /* Handle a possible width suffix and/or Neon type suffix. */
13571 else if (end
[1] == 'n')
13576 inst
.vectype
.elems
= 0;
13578 *str
= end
+ offset
;
13580 if (end
[offset
] == '.')
13582 /* See if we have a Neon type suffix. */
13583 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
13586 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
13592 /* Look for unaffixed or special-case affixed mnemonic. */
13593 opcode
= hash_find_n (arm_ops_hsh
, base
, end
- base
);
13597 if (opcode
->tag
< OT_odd_infix_0
)
13599 inst
.cond
= COND_ALWAYS
;
13603 if (unified_syntax
)
13604 as_warn (_("conditional infixes are deprecated in unified syntax"));
13605 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
13606 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
13609 inst
.cond
= cond
->value
;
13613 /* Cannot have a conditional suffix on a mnemonic of less than two
13615 if (end
- base
< 3)
13618 /* Look for suffixed mnemonic. */
13620 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
13621 opcode
= hash_find_n (arm_ops_hsh
, base
, affix
- base
);
13622 if (opcode
&& cond
)
13625 switch (opcode
->tag
)
13627 case OT_cinfix3_legacy
:
13628 /* Ignore conditional suffixes matched on infix only mnemonics. */
13632 case OT_cinfix3_deprecated
:
13633 case OT_odd_infix_unc
:
13634 if (!unified_syntax
)
13636 /* else fall through */
13640 case OT_csuf_or_in3
:
13641 inst
.cond
= cond
->value
;
13644 case OT_unconditional
:
13645 case OT_unconditionalF
:
13648 inst
.cond
= cond
->value
;
13652 /* delayed diagnostic */
13653 inst
.error
= BAD_COND
;
13654 inst
.cond
= COND_ALWAYS
;
13663 /* Cannot have a usual-position infix on a mnemonic of less than
13664 six characters (five would be a suffix). */
13665 if (end
- base
< 6)
13668 /* Look for infixed mnemonic in the usual position. */
13670 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
13674 memcpy (save
, affix
, 2);
13675 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
13676 opcode
= hash_find_n (arm_ops_hsh
, base
, (end
- base
) - 2);
13677 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
13678 memcpy (affix
, save
, 2);
13681 && (opcode
->tag
== OT_cinfix3
13682 || opcode
->tag
== OT_cinfix3_deprecated
13683 || opcode
->tag
== OT_csuf_or_in3
13684 || opcode
->tag
== OT_cinfix3_legacy
))
13688 && (opcode
->tag
== OT_cinfix3
13689 || opcode
->tag
== OT_cinfix3_deprecated
))
13690 as_warn (_("conditional infixes are deprecated in unified syntax"));
13692 inst
.cond
= cond
->value
;
13700 md_assemble (char *str
)
13703 const struct asm_opcode
* opcode
;
13705 /* Align the previous label if needed. */
13706 if (last_label_seen
!= NULL
)
13708 symbol_set_frag (last_label_seen
, frag_now
);
13709 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
13710 S_SET_SEGMENT (last_label_seen
, now_seg
);
13713 memset (&inst
, '\0', sizeof (inst
));
13714 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13716 opcode
= opcode_lookup (&p
);
13719 /* It wasn't an instruction, but it might be a register alias of
13720 the form alias .req reg, or a Neon .dn/.qn directive. */
13721 if (!create_register_alias (str
, p
)
13722 && !create_neon_reg_alias (str
, p
))
13723 as_bad (_("bad instruction `%s'"), str
);
13728 if (opcode
->tag
== OT_cinfix3_deprecated
)
13729 as_warn (_("s suffix on comparison instruction is deprecated"));
13731 /* The value which unconditional instructions should have in place of the
13732 condition field. */
13733 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
13737 arm_feature_set variant
;
13739 variant
= cpu_variant
;
13740 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
13741 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
13742 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
13743 /* Check that this instruction is supported for this CPU. */
13744 if (!opcode
->tvariant
13745 || (thumb_mode
== 1
13746 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
13748 as_bad (_("selected processor does not support `%s'"), str
);
13751 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
13752 && opcode
->tencode
!= do_t_branch
)
13754 as_bad (_("Thumb does not support conditional execution"));
13758 /* Check conditional suffixes. */
13759 if (current_it_mask
)
13762 cond
= current_cc
^ ((current_it_mask
>> 4) & 1) ^ 1;
13763 current_it_mask
<<= 1;
13764 current_it_mask
&= 0x1f;
13765 /* The BKPT instruction is unconditional even in an IT block. */
13767 && cond
!= inst
.cond
&& opcode
->tencode
!= do_t_bkpt
)
13769 as_bad (_("incorrect condition in IT block"));
13773 else if (inst
.cond
!= COND_ALWAYS
&& opcode
->tencode
!= do_t_branch
)
13775 as_bad (_("thumb conditional instrunction not in IT block"));
13779 mapping_state (MAP_THUMB
);
13780 inst
.instruction
= opcode
->tvalue
;
13782 if (!parse_operands (p
, opcode
->operands
))
13783 opcode
->tencode ();
13785 /* Clear current_it_mask at the end of an IT block. */
13786 if (current_it_mask
== 0x10)
13787 current_it_mask
= 0;
13789 if (!(inst
.error
|| inst
.relax
))
13791 assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
13792 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
13793 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
13795 as_bad (_("cannot honor width suffix -- `%s'"), str
);
13799 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13800 *opcode
->tvariant
);
13801 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
13802 set those bits when Thumb-2 32-bit instructions are seen. ie.
13803 anything other than bl/blx.
13804 This is overly pessimistic for relaxable instructions. */
13805 if ((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
13807 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13812 /* Check that this instruction is supported for this CPU. */
13813 if (!opcode
->avariant
||
13814 !ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
))
13816 as_bad (_("selected processor does not support `%s'"), str
);
13821 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
13825 mapping_state (MAP_ARM
);
13826 inst
.instruction
= opcode
->avalue
;
13827 if (opcode
->tag
== OT_unconditionalF
)
13828 inst
.instruction
|= 0xF << 28;
13830 inst
.instruction
|= inst
.cond
<< 28;
13831 inst
.size
= INSN_SIZE
;
13832 if (!parse_operands (p
, opcode
->operands
))
13833 opcode
->aencode ();
13834 /* Arm mode bx is marked as both v4T and v5 because it's still required
13835 on a hypothetical non-thumb v5 core. */
13836 if (ARM_CPU_HAS_FEATURE (*opcode
->avariant
, arm_ext_v4t
)
13837 || ARM_CPU_HAS_FEATURE (*opcode
->avariant
, arm_ext_v5
))
13838 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
13840 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
13841 *opcode
->avariant
);
13846 /* Various frobbings of labels and their addresses. */
13849 arm_start_line_hook (void)
13851 last_label_seen
= NULL
;
13855 arm_frob_label (symbolS
* sym
)
13857 last_label_seen
= sym
;
13859 ARM_SET_THUMB (sym
, thumb_mode
);
13861 #if defined OBJ_COFF || defined OBJ_ELF
13862 ARM_SET_INTERWORK (sym
, support_interwork
);
13865 /* Note - do not allow local symbols (.Lxxx) to be labeled
13866 as Thumb functions. This is because these labels, whilst
13867 they exist inside Thumb code, are not the entry points for
13868 possible ARM->Thumb calls. Also, these labels can be used
13869 as part of a computed goto or switch statement. eg gcc
13870 can generate code that looks like this:
13872 ldr r2, [pc, .Laaa]
13882 The first instruction loads the address of the jump table.
13883 The second instruction converts a table index into a byte offset.
13884 The third instruction gets the jump address out of the table.
13885 The fourth instruction performs the jump.
13887 If the address stored at .Laaa is that of a symbol which has the
13888 Thumb_Func bit set, then the linker will arrange for this address
13889 to have the bottom bit set, which in turn would mean that the
13890 address computation performed by the third instruction would end
13891 up with the bottom bit set. Since the ARM is capable of unaligned
13892 word loads, the instruction would then load the incorrect address
13893 out of the jump table, and chaos would ensue. */
13894 if (label_is_thumb_function_name
13895 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
13896 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
13898 /* When the address of a Thumb function is taken the bottom
13899 bit of that address should be set. This will allow
13900 interworking between Arm and Thumb functions to work
13903 THUMB_SET_FUNC (sym
, 1);
13905 label_is_thumb_function_name
= FALSE
;
13909 dwarf2_emit_label (sym
);
13914 arm_data_in_code (void)
13916 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
13918 *input_line_pointer
= '/';
13919 input_line_pointer
+= 5;
13920 *input_line_pointer
= 0;
13928 arm_canonicalize_symbol_name (char * name
)
13932 if (thumb_mode
&& (len
= strlen (name
)) > 5
13933 && streq (name
+ len
- 5, "/data"))
13934 *(name
+ len
- 5) = 0;
13939 /* Table of all register names defined by default. The user can
13940 define additional names with .req. Note that all register names
13941 should appear in both upper and lowercase variants. Some registers
13942 also have mixed-case names. */
13944 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
13945 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
13946 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
13947 #define REGSET(p,t) \
13948 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
13949 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
13950 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
13951 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
13952 #define REGSETH(p,t) \
13953 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
13954 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
13955 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
13956 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
13957 #define REGSET2(p,t) \
13958 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
13959 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
13960 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
13961 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
13963 static const struct reg_entry reg_names
[] =
13965 /* ARM integer registers. */
13966 REGSET(r
, RN
), REGSET(R
, RN
),
13968 /* ATPCS synonyms. */
13969 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
13970 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
13971 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
13973 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
13974 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
13975 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
13977 /* Well-known aliases. */
13978 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
13979 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
13981 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
13982 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
13984 /* Coprocessor numbers. */
13985 REGSET(p
, CP
), REGSET(P
, CP
),
13987 /* Coprocessor register numbers. The "cr" variants are for backward
13989 REGSET(c
, CN
), REGSET(C
, CN
),
13990 REGSET(cr
, CN
), REGSET(CR
, CN
),
13992 /* FPA registers. */
13993 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
13994 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
13996 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
13997 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
13999 /* VFP SP registers. */
14000 REGSET(s
,VFS
), REGSET(S
,VFS
),
14001 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
14003 /* VFP DP Registers. */
14004 REGSET(d
,VFD
), REGSET(D
,VFD
),
14005 /* Extra Neon DP registers. */
14006 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
14008 /* Neon QP registers. */
14009 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
14011 /* VFP control registers. */
14012 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
14013 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
14015 /* Maverick DSP coprocessor registers. */
14016 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
14017 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
14019 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
14020 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
14021 REGDEF(dspsc
,0,DSPSC
),
14023 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
14024 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
14025 REGDEF(DSPSC
,0,DSPSC
),
14027 /* iWMMXt data registers - p0, c0-15. */
14028 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
14030 /* iWMMXt control registers - p1, c0-3. */
14031 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
14032 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
14033 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
14034 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
14036 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
14037 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
14038 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
14039 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
14040 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
14042 /* XScale accumulator registers. */
14043 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
14049 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
14050 within psr_required_here. */
14051 static const struct asm_psr psrs
[] =
14053 /* Backward compatibility notation. Note that "all" is no longer
14054 truly all possible PSR bits. */
14055 {"all", PSR_c
| PSR_f
},
14059 /* Individual flags. */
14064 /* Combinations of flags. */
14065 {"fs", PSR_f
| PSR_s
},
14066 {"fx", PSR_f
| PSR_x
},
14067 {"fc", PSR_f
| PSR_c
},
14068 {"sf", PSR_s
| PSR_f
},
14069 {"sx", PSR_s
| PSR_x
},
14070 {"sc", PSR_s
| PSR_c
},
14071 {"xf", PSR_x
| PSR_f
},
14072 {"xs", PSR_x
| PSR_s
},
14073 {"xc", PSR_x
| PSR_c
},
14074 {"cf", PSR_c
| PSR_f
},
14075 {"cs", PSR_c
| PSR_s
},
14076 {"cx", PSR_c
| PSR_x
},
14077 {"fsx", PSR_f
| PSR_s
| PSR_x
},
14078 {"fsc", PSR_f
| PSR_s
| PSR_c
},
14079 {"fxs", PSR_f
| PSR_x
| PSR_s
},
14080 {"fxc", PSR_f
| PSR_x
| PSR_c
},
14081 {"fcs", PSR_f
| PSR_c
| PSR_s
},
14082 {"fcx", PSR_f
| PSR_c
| PSR_x
},
14083 {"sfx", PSR_s
| PSR_f
| PSR_x
},
14084 {"sfc", PSR_s
| PSR_f
| PSR_c
},
14085 {"sxf", PSR_s
| PSR_x
| PSR_f
},
14086 {"sxc", PSR_s
| PSR_x
| PSR_c
},
14087 {"scf", PSR_s
| PSR_c
| PSR_f
},
14088 {"scx", PSR_s
| PSR_c
| PSR_x
},
14089 {"xfs", PSR_x
| PSR_f
| PSR_s
},
14090 {"xfc", PSR_x
| PSR_f
| PSR_c
},
14091 {"xsf", PSR_x
| PSR_s
| PSR_f
},
14092 {"xsc", PSR_x
| PSR_s
| PSR_c
},
14093 {"xcf", PSR_x
| PSR_c
| PSR_f
},
14094 {"xcs", PSR_x
| PSR_c
| PSR_s
},
14095 {"cfs", PSR_c
| PSR_f
| PSR_s
},
14096 {"cfx", PSR_c
| PSR_f
| PSR_x
},
14097 {"csf", PSR_c
| PSR_s
| PSR_f
},
14098 {"csx", PSR_c
| PSR_s
| PSR_x
},
14099 {"cxf", PSR_c
| PSR_x
| PSR_f
},
14100 {"cxs", PSR_c
| PSR_x
| PSR_s
},
14101 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
14102 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
14103 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
14104 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
14105 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
14106 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
14107 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
14108 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
14109 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
14110 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
14111 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
14112 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
14113 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
14114 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
14115 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
14116 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
14117 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
14118 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
14119 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
14120 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
14121 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
14122 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
14123 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
14124 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
14127 /* Table of V7M psr names. */
14128 static const struct asm_psr v7m_psrs
[] =
14141 {"basepri_max", 18},
14146 /* Table of all shift-in-operand names. */
14147 static const struct asm_shift_name shift_names
[] =
14149 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
14150 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
14151 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
14152 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
14153 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
14154 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
14157 /* Table of all explicit relocation names. */
14159 static struct reloc_entry reloc_names
[] =
14161 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
14162 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
14163 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
14164 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
14165 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
14166 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
14167 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
14168 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
14169 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
14170 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
14171 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
14175 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
14176 static const struct asm_cond conds
[] =
14180 {"cs", 0x2}, {"hs", 0x2},
14181 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
14195 static struct asm_barrier_opt barrier_opt_names
[] =
14203 /* Table of ARM-format instructions. */
14205 /* Macros for gluing together operand strings. N.B. In all cases
14206 other than OPS0, the trailing OP_stop comes from default
14207 zero-initialization of the unspecified elements of the array. */
14208 #define OPS0() { OP_stop, }
14209 #define OPS1(a) { OP_##a, }
14210 #define OPS2(a,b) { OP_##a,OP_##b, }
14211 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
14212 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
14213 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
14214 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
14216 /* These macros abstract out the exact format of the mnemonic table and
14217 save some repeated characters. */
14219 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
14220 #define TxCE(mnem, op, top, nops, ops, ae, te) \
14221 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
14222 THUMB_VARIANT, do_##ae, do_##te }
14224 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
14225 a T_MNEM_xyz enumerator. */
14226 #define TCE(mnem, aop, top, nops, ops, ae, te) \
14227 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
14228 #define tCE(mnem, aop, top, nops, ops, ae, te) \
14229 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14231 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
14232 infix after the third character. */
14233 #define TxC3(mnem, op, top, nops, ops, ae, te) \
14234 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
14235 THUMB_VARIANT, do_##ae, do_##te }
14236 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
14237 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
14238 THUMB_VARIANT, do_##ae, do_##te }
14239 #define TC3(mnem, aop, top, nops, ops, ae, te) \
14240 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
14241 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
14242 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
14243 #define tC3(mnem, aop, top, nops, ops, ae, te) \
14244 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14245 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
14246 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14248 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
14249 appear in the condition table. */
14250 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
14251 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14252 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
14254 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
14255 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
14256 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
14257 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
14258 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
14259 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
14260 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
14261 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
14262 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
14263 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
14264 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
14265 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
14266 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
14267 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
14268 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
14269 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
14270 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
14271 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
14272 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
14273 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
14275 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
14276 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
14277 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
14278 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
14280 /* Mnemonic that cannot be conditionalized. The ARM condition-code
14281 field is still 0xE. Many of the Thumb variants can be executed
14282 conditionally, so this is checked separately. */
14283 #define TUE(mnem, op, top, nops, ops, ae, te) \
14284 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
14285 THUMB_VARIANT, do_##ae, do_##te }
14287 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
14288 condition code field. */
14289 #define TUF(mnem, op, top, nops, ops, ae, te) \
14290 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
14291 THUMB_VARIANT, do_##ae, do_##te }
14293 /* ARM-only variants of all the above. */
14294 #define CE(mnem, op, nops, ops, ae) \
14295 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14297 #define C3(mnem, op, nops, ops, ae) \
14298 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14300 /* Legacy mnemonics that always have conditional infix after the third
14302 #define CL(mnem, op, nops, ops, ae) \
14303 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14304 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14306 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
14307 #define cCE(mnem, op, nops, ops, ae) \
14308 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14310 /* Legacy coprocessor instructions where conditional infix and conditional
14311 suffix are ambiguous. For consistency this includes all FPA instructions,
14312 not just the potentially ambiguous ones. */
14313 #define cCL(mnem, op, nops, ops, ae) \
14314 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14315 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14317 /* Coprocessor, takes either a suffix or a position-3 infix
14318 (for an FPA corner case). */
14319 #define C3E(mnem, op, nops, ops, ae) \
14320 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
14321 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14323 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
14324 { #m1 #m2 #m3, OPS##nops ops, \
14325 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14326 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14328 #define CM(m1, m2, op, nops, ops, ae) \
14329 xCM_(m1, , m2, op, nops, ops, ae), \
14330 xCM_(m1, eq, m2, op, nops, ops, ae), \
14331 xCM_(m1, ne, m2, op, nops, ops, ae), \
14332 xCM_(m1, cs, m2, op, nops, ops, ae), \
14333 xCM_(m1, hs, m2, op, nops, ops, ae), \
14334 xCM_(m1, cc, m2, op, nops, ops, ae), \
14335 xCM_(m1, ul, m2, op, nops, ops, ae), \
14336 xCM_(m1, lo, m2, op, nops, ops, ae), \
14337 xCM_(m1, mi, m2, op, nops, ops, ae), \
14338 xCM_(m1, pl, m2, op, nops, ops, ae), \
14339 xCM_(m1, vs, m2, op, nops, ops, ae), \
14340 xCM_(m1, vc, m2, op, nops, ops, ae), \
14341 xCM_(m1, hi, m2, op, nops, ops, ae), \
14342 xCM_(m1, ls, m2, op, nops, ops, ae), \
14343 xCM_(m1, ge, m2, op, nops, ops, ae), \
14344 xCM_(m1, lt, m2, op, nops, ops, ae), \
14345 xCM_(m1, gt, m2, op, nops, ops, ae), \
14346 xCM_(m1, le, m2, op, nops, ops, ae), \
14347 xCM_(m1, al, m2, op, nops, ops, ae)
14349 #define UE(mnem, op, nops, ops, ae) \
14350 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14352 #define UF(mnem, op, nops, ops, ae) \
14353 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14355 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
14356 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
14357 use the same encoding function for each. */
14358 #define NUF(mnem, op, nops, ops, enc) \
14359 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
14360 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14362 /* Neon data processing, version which indirects through neon_enc_tab for
14363 the various overloaded versions of opcodes. */
14364 #define nUF(mnem, op, nops, ops, enc) \
14365 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \
14366 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14368 /* Neon insn with conditional suffix for the ARM version, non-overloaded
14370 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
14371 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
14372 THUMB_VARIANT, do_##enc, do_##enc }
14374 #define NCE(mnem, op, nops, ops, enc) \
14375 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14377 #define NCEF(mnem, op, nops, ops, enc) \
14378 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14380 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
14381 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
14382 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \
14383 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14385 #define nCE(mnem, op, nops, ops, enc) \
14386 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14388 #define nCEF(mnem, op, nops, ops, enc) \
14389 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14393 /* Thumb-only, unconditional. */
14394 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
14396 static const struct asm_opcode insns
[] =
14398 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
14399 #define THUMB_VARIANT &arm_ext_v4t
14400 tCE(and, 0000000, and, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14401 tC3(ands
, 0100000, ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14402 tCE(eor
, 0200000, eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14403 tC3(eors
, 0300000, eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14404 tCE(sub
, 0400000, sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14405 tC3(subs
, 0500000, subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14406 tCE(add
, 0800000, add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14407 tC3(adds
, 0900000, adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14408 tCE(adc
, 0a00000
, adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14409 tC3(adcs
, 0b00000, adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14410 tCE(sbc
, 0c00000
, sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14411 tC3(sbcs
, 0d00000
, sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14412 tCE(orr
, 1800000, orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14413 tC3(orrs
, 1900000, orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14414 tCE(bic
, 1c00000
, bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14415 tC3(bics
, 1d00000
, bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14417 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
14418 for setting PSR flag bits. They are obsolete in V6 and do not
14419 have Thumb equivalents. */
14420 tCE(tst
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14421 tC3w(tsts
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14422 CL(tstp
, 110f000
, 2, (RR
, SH
), cmp
),
14423 tCE(cmp
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14424 tC3w(cmps
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14425 CL(cmpp
, 150f000
, 2, (RR
, SH
), cmp
),
14426 tCE(cmn
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14427 tC3w(cmns
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14428 CL(cmnp
, 170f000
, 2, (RR
, SH
), cmp
),
14430 tCE(mov
, 1a00000
, mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14431 tC3(movs
, 1b00000
, movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14432 tCE(mvn
, 1e00000
, mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14433 tC3(mvns
, 1f00000
, mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14435 tCE(ldr
, 4100000, ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14436 tC3(ldrb
, 4500000, ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14437 tCE(str
, 4000000, str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14438 tC3(strb
, 4400000, strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14440 tCE(stm
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14441 tC3(stmia
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14442 tC3(stmea
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14443 tCE(ldm
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14444 tC3(ldmia
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14445 tC3(ldmfd
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14447 TCE(swi
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14448 TCE(svc
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14449 tCE(b
, a000000
, b
, 1, (EXPr
), branch
, t_branch
),
14450 TCE(bl
, b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
14453 tCE(adr
, 28f0000
, adr
, 2, (RR
, EXP
), adr
, t_adr
),
14454 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
14455 tCE(nop
, 1a00000
, nop
, 1, (oI255c
), nop
, t_nop
),
14457 /* Thumb-compatibility pseudo ops. */
14458 tCE(lsl
, 1a00000
, lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14459 tC3(lsls
, 1b00000
, lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14460 tCE(lsr
, 1a00020
, lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14461 tC3(lsrs
, 1b00020
, lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14462 tCE(asr
, 1a00040
, asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14463 tC3(asrs
, 1b00040
, asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14464 tCE(ror
, 1a00060
, ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14465 tC3(rors
, 1b00060
, rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14466 tCE(neg
, 2600000, neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
14467 tC3(negs
, 2700000, negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
14468 tCE(push
, 92d0000
, push
, 1, (REGLST
), push_pop
, t_push_pop
),
14469 tCE(pop
, 8bd0000
, pop
, 1, (REGLST
), push_pop
, t_push_pop
),
14471 #undef THUMB_VARIANT
14472 #define THUMB_VARIANT &arm_ext_v6
14473 TCE(cpy
, 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
14475 /* V1 instructions with no Thumb analogue prior to V6T2. */
14476 #undef THUMB_VARIANT
14477 #define THUMB_VARIANT &arm_ext_v6t2
14478 TCE(rsb
, 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14479 TC3(rsbs
, 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14480 TCE(teq
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14481 TC3w(teqs
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14482 CL(teqp
, 130f000
, 2, (RR
, SH
), cmp
),
14484 TC3(ldrt
, 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14485 TC3(ldrbt
, 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14486 TC3(strt
, 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14487 TC3(strbt
, 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14489 TC3(stmdb
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14490 TC3(stmfd
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14492 TC3(ldmdb
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14493 TC3(ldmea
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14495 /* V1 instructions with no Thumb analogue at all. */
14496 CE(rsc
, 0e00000
, 3, (RR
, oRR
, SH
), arit
),
14497 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
14499 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
14500 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
14501 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
14502 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
14503 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
14504 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
14505 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
14506 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
14509 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
14510 #undef THUMB_VARIANT
14511 #define THUMB_VARIANT &arm_ext_v4t
14512 tCE(mul
, 0000090, mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
14513 tC3(muls
, 0100090, muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
14515 #undef THUMB_VARIANT
14516 #define THUMB_VARIANT &arm_ext_v6t2
14517 TCE(mla
, 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
14518 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
14520 /* Generic coprocessor instructions. */
14521 TCE(cdp
, e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
14522 TCE(ldc
, c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14523 TC3(ldcl
, c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14524 TCE(stc
, c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14525 TC3(stcl
, c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14526 TCE(mcr
, e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14527 TCE(mrc
, e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14530 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
14531 CE(swp
, 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
14532 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
14535 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
14536 TCE(mrs
, 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
14537 TCE(msr
, 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
14540 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
14541 TCE(smull
, 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14542 CM(smull
,s
, 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14543 TCE(umull
, 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14544 CM(umull
,s
, 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14545 TCE(smlal
, 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14546 CM(smlal
,s
, 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14547 TCE(umlal
, 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14548 CM(umlal
,s
, 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14551 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
14552 #undef THUMB_VARIANT
14553 #define THUMB_VARIANT &arm_ext_v4t
14554 tC3(ldrh
, 01000b0
, ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14555 tC3(strh
, 00000b0
, strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14556 tC3(ldrsh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14557 tC3(ldrsb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14558 tCM(ld
,sh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14559 tCM(ld
,sb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14562 #define ARM_VARIANT &arm_ext_v4t_5
14563 /* ARM Architecture 4T. */
14564 /* Note: bx (and blx) are required on V5, even if the processor does
14565 not support Thumb. */
14566 TCE(bx
, 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
14569 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
14570 #undef THUMB_VARIANT
14571 #define THUMB_VARIANT &arm_ext_v5t
14572 /* Note: blx has 2 variants; the .value coded here is for
14573 BLX(2). Only this variant has conditional execution. */
14574 TCE(blx
, 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
14575 TUE(bkpt
, 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
14577 #undef THUMB_VARIANT
14578 #define THUMB_VARIANT &arm_ext_v6t2
14579 TCE(clz
, 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
14580 TUF(ldc2
, c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14581 TUF(ldc2l
, c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14582 TUF(stc2
, c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14583 TUF(stc2l
, c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14584 TUF(cdp2
, e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
14585 TUF(mcr2
, e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14586 TUF(mrc2
, e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14589 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
14590 TCE(smlabb
, 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14591 TCE(smlatb
, 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14592 TCE(smlabt
, 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14593 TCE(smlatt
, 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14595 TCE(smlawb
, 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14596 TCE(smlawt
, 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14598 TCE(smlalbb
, 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14599 TCE(smlaltb
, 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14600 TCE(smlalbt
, 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14601 TCE(smlaltt
, 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14603 TCE(smulbb
, 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14604 TCE(smultb
, 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14605 TCE(smulbt
, 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14606 TCE(smultt
, 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14608 TCE(smulwb
, 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14609 TCE(smulwt
, 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14611 TCE(qadd
, 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14612 TCE(qdadd
, 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14613 TCE(qsub
, 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14614 TCE(qdsub
, 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14617 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
14618 TUF(pld
, 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
14619 TC3(ldrd
, 00000d0
, e9500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
14620 TC3(strd
, 00000f0
, e9400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
14622 TCE(mcrr
, c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14623 TCE(mrrc
, c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14626 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
14627 TCE(bxj
, 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
14630 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
14631 #undef THUMB_VARIANT
14632 #define THUMB_VARIANT &arm_ext_v6
14633 TUF(cpsie
, 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
14634 TUF(cpsid
, 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
14635 tCE(rev
, 6bf0f30
, rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
14636 tCE(rev16
, 6bf0fb0
, rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
14637 tCE(revsh
, 6ff0fb0
, revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
14638 tCE(sxth
, 6bf0070
, sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14639 tCE(uxth
, 6ff0070
, uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14640 tCE(sxtb
, 6af0070
, sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14641 tCE(uxtb
, 6ef0070
, uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14642 TUF(setend
, 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
14644 #undef THUMB_VARIANT
14645 #define THUMB_VARIANT &arm_ext_v6t2
14646 TCE(ldrex
, 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
14647 TUF(mcrr2
, c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14648 TUF(mrrc2
, c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14650 TCE(ssat
, 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
14651 TCE(usat
, 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
14653 /* ARM V6 not included in V7M (eg. integer SIMD). */
14654 #undef THUMB_VARIANT
14655 #define THUMB_VARIANT &arm_ext_v6_notm
14656 TUF(cps
, 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
14657 TCE(pkhbt
, 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
14658 TCE(pkhtb
, 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
14659 TCE(qadd16
, 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14660 TCE(qadd8
, 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14661 TCE(qaddsubx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14662 TCE(qsub16
, 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14663 TCE(qsub8
, 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14664 TCE(qsubaddx
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14665 TCE(sadd16
, 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14666 TCE(sadd8
, 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14667 TCE(saddsubx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14668 TCE(shadd16
, 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14669 TCE(shadd8
, 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14670 TCE(shaddsubx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14671 TCE(shsub16
, 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14672 TCE(shsub8
, 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14673 TCE(shsubaddx
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14674 TCE(ssub16
, 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14675 TCE(ssub8
, 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14676 TCE(ssubaddx
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14677 TCE(uadd16
, 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14678 TCE(uadd8
, 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14679 TCE(uaddsubx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14680 TCE(uhadd16
, 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14681 TCE(uhadd8
, 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14682 TCE(uhaddsubx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14683 TCE(uhsub16
, 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14684 TCE(uhsub8
, 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14685 TCE(uhsubaddx
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14686 TCE(uqadd16
, 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14687 TCE(uqadd8
, 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14688 TCE(uqaddsubx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14689 TCE(uqsub16
, 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14690 TCE(uqsub8
, 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14691 TCE(uqsubaddx
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14692 TCE(usub16
, 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14693 TCE(usub8
, 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14694 TCE(usubaddx
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14695 TUF(rfeia
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
14696 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
14697 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
14698 TUF(rfedb
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
14699 TUF(rfefd
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
14700 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
14701 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
14702 TUF(rfeed
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
14703 TCE(sxtah
, 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14704 TCE(sxtab16
, 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14705 TCE(sxtab
, 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14706 TCE(sxtb16
, 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14707 TCE(uxtah
, 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14708 TCE(uxtab16
, 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14709 TCE(uxtab
, 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14710 TCE(uxtb16
, 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14711 TCE(sel
, 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14712 TCE(smlad
, 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14713 TCE(smladx
, 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14714 TCE(smlald
, 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14715 TCE(smlaldx
, 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14716 TCE(smlsd
, 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14717 TCE(smlsdx
, 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14718 TCE(smlsld
, 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14719 TCE(smlsldx
, 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14720 TCE(smmla
, 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14721 TCE(smmlar
, 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14722 TCE(smmls
, 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14723 TCE(smmlsr
, 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14724 TCE(smmul
, 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14725 TCE(smmulr
, 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14726 TCE(smuad
, 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14727 TCE(smuadx
, 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14728 TCE(smusd
, 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14729 TCE(smusdx
, 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14730 TUF(srsia
, 8cd0500
, e980c000
, 1, (I31w
), srs
, srs
),
14731 UF(srsib
, 9cd0500
, 1, (I31w
), srs
),
14732 UF(srsda
, 84d0500
, 1, (I31w
), srs
),
14733 TUF(srsdb
, 94d0500
, e800c000
, 1, (I31w
), srs
, srs
),
14734 TCE(ssat16
, 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
14735 TCE(strex
, 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
14736 TCE(umaal
, 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
14737 TCE(usad8
, 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14738 TCE(usada8
, 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14739 TCE(usat16
, 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
14742 #define ARM_VARIANT &arm_ext_v6k
14743 #undef THUMB_VARIANT
14744 #define THUMB_VARIANT &arm_ext_v6k
14745 tCE(yield
, 320f001
, yield
, 0, (), noargs
, t_hint
),
14746 tCE(wfe
, 320f002
, wfe
, 0, (), noargs
, t_hint
),
14747 tCE(wfi
, 320f003
, wfi
, 0, (), noargs
, t_hint
),
14748 tCE(sev
, 320f004
, sev
, 0, (), noargs
, t_hint
),
14750 #undef THUMB_VARIANT
14751 #define THUMB_VARIANT &arm_ext_v6_notm
14752 TCE(ldrexd
, 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
14753 TCE(strexd
, 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
14755 #undef THUMB_VARIANT
14756 #define THUMB_VARIANT &arm_ext_v6t2
14757 TCE(ldrexb
, 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
14758 TCE(ldrexh
, 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
14759 TCE(strexb
, 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
14760 TCE(strexh
, 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
14761 TUF(clrex
, 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
14764 #define ARM_VARIANT &arm_ext_v6z
14765 TCE(smc
, 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
14768 #define ARM_VARIANT &arm_ext_v6t2
14769 TCE(bfc
, 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
14770 TCE(bfi
, 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
14771 TCE(sbfx
, 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
14772 TCE(ubfx
, 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
14774 TCE(mls
, 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
14775 TCE(movw
, 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
14776 TCE(movt
, 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
14777 TCE(rbit
, 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
14779 TC3(ldrht
, 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
14780 TC3(ldrsht
, 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
14781 TC3(ldrsbt
, 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
14782 TC3(strht
, 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
14784 UT(cbnz
, b900
, 2, (RR
, EXP
), t_czb
),
14785 UT(cbz
, b100
, 2, (RR
, EXP
), t_czb
),
14786 /* ARM does not really have an IT instruction. */
14787 TUE(it
, 0, bf08
, 1, (COND
), it
, t_it
),
14788 TUE(itt
, 0, bf0c
, 1, (COND
), it
, t_it
),
14789 TUE(ite
, 0, bf04
, 1, (COND
), it
, t_it
),
14790 TUE(ittt
, 0, bf0e
, 1, (COND
), it
, t_it
),
14791 TUE(itet
, 0, bf06
, 1, (COND
), it
, t_it
),
14792 TUE(itte
, 0, bf0a
, 1, (COND
), it
, t_it
),
14793 TUE(itee
, 0, bf02
, 1, (COND
), it
, t_it
),
14794 TUE(itttt
, 0, bf0f
, 1, (COND
), it
, t_it
),
14795 TUE(itett
, 0, bf07
, 1, (COND
), it
, t_it
),
14796 TUE(ittet
, 0, bf0b
, 1, (COND
), it
, t_it
),
14797 TUE(iteet
, 0, bf03
, 1, (COND
), it
, t_it
),
14798 TUE(ittte
, 0, bf0d
, 1, (COND
), it
, t_it
),
14799 TUE(itete
, 0, bf05
, 1, (COND
), it
, t_it
),
14800 TUE(ittee
, 0, bf09
, 1, (COND
), it
, t_it
),
14801 TUE(iteee
, 0, bf01
, 1, (COND
), it
, t_it
),
14803 /* Thumb2 only instructions. */
14805 #define ARM_VARIANT NULL
14807 TCE(addw
, 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
14808 TCE(subw
, 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
14809 TCE(tbb
, 0, e8d0f000
, 1, (TB
), 0, t_tb
),
14810 TCE(tbh
, 0, e8d0f010
, 1, (TB
), 0, t_tb
),
14812 /* Thumb-2 hardware division instructions (R and M profiles only). */
14813 #undef THUMB_VARIANT
14814 #define THUMB_VARIANT &arm_ext_div
14815 TCE(sdiv
, 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
14816 TCE(udiv
, 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
14818 /* ARM V7 instructions. */
14820 #define ARM_VARIANT &arm_ext_v7
14821 #undef THUMB_VARIANT
14822 #define THUMB_VARIANT &arm_ext_v7
14823 TUF(pli
, 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
14824 TCE(dbg
, 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
14825 TUF(dmb
, 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
14826 TUF(dsb
, 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
14827 TUF(isb
, 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
14830 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
14831 cCE(wfs
, e200110
, 1, (RR
), rd
),
14832 cCE(rfs
, e300110
, 1, (RR
), rd
),
14833 cCE(wfc
, e400110
, 1, (RR
), rd
),
14834 cCE(rfc
, e500110
, 1, (RR
), rd
),
14836 cCL(ldfs
, c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14837 cCL(ldfd
, c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14838 cCL(ldfe
, c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14839 cCL(ldfp
, c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14841 cCL(stfs
, c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14842 cCL(stfd
, c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14843 cCL(stfe
, c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14844 cCL(stfp
, c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14846 cCL(mvfs
, e008100
, 2, (RF
, RF_IF
), rd_rm
),
14847 cCL(mvfsp
, e008120
, 2, (RF
, RF_IF
), rd_rm
),
14848 cCL(mvfsm
, e008140
, 2, (RF
, RF_IF
), rd_rm
),
14849 cCL(mvfsz
, e008160
, 2, (RF
, RF_IF
), rd_rm
),
14850 cCL(mvfd
, e008180
, 2, (RF
, RF_IF
), rd_rm
),
14851 cCL(mvfdp
, e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
14852 cCL(mvfdm
, e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
14853 cCL(mvfdz
, e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
14854 cCL(mvfe
, e088100
, 2, (RF
, RF_IF
), rd_rm
),
14855 cCL(mvfep
, e088120
, 2, (RF
, RF_IF
), rd_rm
),
14856 cCL(mvfem
, e088140
, 2, (RF
, RF_IF
), rd_rm
),
14857 cCL(mvfez
, e088160
, 2, (RF
, RF_IF
), rd_rm
),
14859 cCL(mnfs
, e108100
, 2, (RF
, RF_IF
), rd_rm
),
14860 cCL(mnfsp
, e108120
, 2, (RF
, RF_IF
), rd_rm
),
14861 cCL(mnfsm
, e108140
, 2, (RF
, RF_IF
), rd_rm
),
14862 cCL(mnfsz
, e108160
, 2, (RF
, RF_IF
), rd_rm
),
14863 cCL(mnfd
, e108180
, 2, (RF
, RF_IF
), rd_rm
),
14864 cCL(mnfdp
, e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
14865 cCL(mnfdm
, e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
14866 cCL(mnfdz
, e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
14867 cCL(mnfe
, e188100
, 2, (RF
, RF_IF
), rd_rm
),
14868 cCL(mnfep
, e188120
, 2, (RF
, RF_IF
), rd_rm
),
14869 cCL(mnfem
, e188140
, 2, (RF
, RF_IF
), rd_rm
),
14870 cCL(mnfez
, e188160
, 2, (RF
, RF_IF
), rd_rm
),
14872 cCL(abss
, e208100
, 2, (RF
, RF_IF
), rd_rm
),
14873 cCL(abssp
, e208120
, 2, (RF
, RF_IF
), rd_rm
),
14874 cCL(abssm
, e208140
, 2, (RF
, RF_IF
), rd_rm
),
14875 cCL(abssz
, e208160
, 2, (RF
, RF_IF
), rd_rm
),
14876 cCL(absd
, e208180
, 2, (RF
, RF_IF
), rd_rm
),
14877 cCL(absdp
, e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
14878 cCL(absdm
, e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
14879 cCL(absdz
, e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
14880 cCL(abse
, e288100
, 2, (RF
, RF_IF
), rd_rm
),
14881 cCL(absep
, e288120
, 2, (RF
, RF_IF
), rd_rm
),
14882 cCL(absem
, e288140
, 2, (RF
, RF_IF
), rd_rm
),
14883 cCL(absez
, e288160
, 2, (RF
, RF_IF
), rd_rm
),
14885 cCL(rnds
, e308100
, 2, (RF
, RF_IF
), rd_rm
),
14886 cCL(rndsp
, e308120
, 2, (RF
, RF_IF
), rd_rm
),
14887 cCL(rndsm
, e308140
, 2, (RF
, RF_IF
), rd_rm
),
14888 cCL(rndsz
, e308160
, 2, (RF
, RF_IF
), rd_rm
),
14889 cCL(rndd
, e308180
, 2, (RF
, RF_IF
), rd_rm
),
14890 cCL(rnddp
, e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
14891 cCL(rnddm
, e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
14892 cCL(rnddz
, e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
14893 cCL(rnde
, e388100
, 2, (RF
, RF_IF
), rd_rm
),
14894 cCL(rndep
, e388120
, 2, (RF
, RF_IF
), rd_rm
),
14895 cCL(rndem
, e388140
, 2, (RF
, RF_IF
), rd_rm
),
14896 cCL(rndez
, e388160
, 2, (RF
, RF_IF
), rd_rm
),
14898 cCL(sqts
, e408100
, 2, (RF
, RF_IF
), rd_rm
),
14899 cCL(sqtsp
, e408120
, 2, (RF
, RF_IF
), rd_rm
),
14900 cCL(sqtsm
, e408140
, 2, (RF
, RF_IF
), rd_rm
),
14901 cCL(sqtsz
, e408160
, 2, (RF
, RF_IF
), rd_rm
),
14902 cCL(sqtd
, e408180
, 2, (RF
, RF_IF
), rd_rm
),
14903 cCL(sqtdp
, e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
14904 cCL(sqtdm
, e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
14905 cCL(sqtdz
, e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
14906 cCL(sqte
, e488100
, 2, (RF
, RF_IF
), rd_rm
),
14907 cCL(sqtep
, e488120
, 2, (RF
, RF_IF
), rd_rm
),
14908 cCL(sqtem
, e488140
, 2, (RF
, RF_IF
), rd_rm
),
14909 cCL(sqtez
, e488160
, 2, (RF
, RF_IF
), rd_rm
),
14911 cCL(logs
, e508100
, 2, (RF
, RF_IF
), rd_rm
),
14912 cCL(logsp
, e508120
, 2, (RF
, RF_IF
), rd_rm
),
14913 cCL(logsm
, e508140
, 2, (RF
, RF_IF
), rd_rm
),
14914 cCL(logsz
, e508160
, 2, (RF
, RF_IF
), rd_rm
),
14915 cCL(logd
, e508180
, 2, (RF
, RF_IF
), rd_rm
),
14916 cCL(logdp
, e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
14917 cCL(logdm
, e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
14918 cCL(logdz
, e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
14919 cCL(loge
, e588100
, 2, (RF
, RF_IF
), rd_rm
),
14920 cCL(logep
, e588120
, 2, (RF
, RF_IF
), rd_rm
),
14921 cCL(logem
, e588140
, 2, (RF
, RF_IF
), rd_rm
),
14922 cCL(logez
, e588160
, 2, (RF
, RF_IF
), rd_rm
),
14924 cCL(lgns
, e608100
, 2, (RF
, RF_IF
), rd_rm
),
14925 cCL(lgnsp
, e608120
, 2, (RF
, RF_IF
), rd_rm
),
14926 cCL(lgnsm
, e608140
, 2, (RF
, RF_IF
), rd_rm
),
14927 cCL(lgnsz
, e608160
, 2, (RF
, RF_IF
), rd_rm
),
14928 cCL(lgnd
, e608180
, 2, (RF
, RF_IF
), rd_rm
),
14929 cCL(lgndp
, e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
14930 cCL(lgndm
, e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
14931 cCL(lgndz
, e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
14932 cCL(lgne
, e688100
, 2, (RF
, RF_IF
), rd_rm
),
14933 cCL(lgnep
, e688120
, 2, (RF
, RF_IF
), rd_rm
),
14934 cCL(lgnem
, e688140
, 2, (RF
, RF_IF
), rd_rm
),
14935 cCL(lgnez
, e688160
, 2, (RF
, RF_IF
), rd_rm
),
14937 cCL(exps
, e708100
, 2, (RF
, RF_IF
), rd_rm
),
14938 cCL(expsp
, e708120
, 2, (RF
, RF_IF
), rd_rm
),
14939 cCL(expsm
, e708140
, 2, (RF
, RF_IF
), rd_rm
),
14940 cCL(expsz
, e708160
, 2, (RF
, RF_IF
), rd_rm
),
14941 cCL(expd
, e708180
, 2, (RF
, RF_IF
), rd_rm
),
14942 cCL(expdp
, e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
14943 cCL(expdm
, e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
14944 cCL(expdz
, e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
14945 cCL(expe
, e788100
, 2, (RF
, RF_IF
), rd_rm
),
14946 cCL(expep
, e788120
, 2, (RF
, RF_IF
), rd_rm
),
14947 cCL(expem
, e788140
, 2, (RF
, RF_IF
), rd_rm
),
14948 cCL(expdz
, e788160
, 2, (RF
, RF_IF
), rd_rm
),
14950 cCL(sins
, e808100
, 2, (RF
, RF_IF
), rd_rm
),
14951 cCL(sinsp
, e808120
, 2, (RF
, RF_IF
), rd_rm
),
14952 cCL(sinsm
, e808140
, 2, (RF
, RF_IF
), rd_rm
),
14953 cCL(sinsz
, e808160
, 2, (RF
, RF_IF
), rd_rm
),
14954 cCL(sind
, e808180
, 2, (RF
, RF_IF
), rd_rm
),
14955 cCL(sindp
, e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
14956 cCL(sindm
, e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
14957 cCL(sindz
, e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
14958 cCL(sine
, e888100
, 2, (RF
, RF_IF
), rd_rm
),
14959 cCL(sinep
, e888120
, 2, (RF
, RF_IF
), rd_rm
),
14960 cCL(sinem
, e888140
, 2, (RF
, RF_IF
), rd_rm
),
14961 cCL(sinez
, e888160
, 2, (RF
, RF_IF
), rd_rm
),
14963 cCL(coss
, e908100
, 2, (RF
, RF_IF
), rd_rm
),
14964 cCL(cossp
, e908120
, 2, (RF
, RF_IF
), rd_rm
),
14965 cCL(cossm
, e908140
, 2, (RF
, RF_IF
), rd_rm
),
14966 cCL(cossz
, e908160
, 2, (RF
, RF_IF
), rd_rm
),
14967 cCL(cosd
, e908180
, 2, (RF
, RF_IF
), rd_rm
),
14968 cCL(cosdp
, e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
14969 cCL(cosdm
, e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
14970 cCL(cosdz
, e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
14971 cCL(cose
, e988100
, 2, (RF
, RF_IF
), rd_rm
),
14972 cCL(cosep
, e988120
, 2, (RF
, RF_IF
), rd_rm
),
14973 cCL(cosem
, e988140
, 2, (RF
, RF_IF
), rd_rm
),
14974 cCL(cosez
, e988160
, 2, (RF
, RF_IF
), rd_rm
),
14976 cCL(tans
, ea08100
, 2, (RF
, RF_IF
), rd_rm
),
14977 cCL(tansp
, ea08120
, 2, (RF
, RF_IF
), rd_rm
),
14978 cCL(tansm
, ea08140
, 2, (RF
, RF_IF
), rd_rm
),
14979 cCL(tansz
, ea08160
, 2, (RF
, RF_IF
), rd_rm
),
14980 cCL(tand
, ea08180
, 2, (RF
, RF_IF
), rd_rm
),
14981 cCL(tandp
, ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
14982 cCL(tandm
, ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
14983 cCL(tandz
, ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
14984 cCL(tane
, ea88100
, 2, (RF
, RF_IF
), rd_rm
),
14985 cCL(tanep
, ea88120
, 2, (RF
, RF_IF
), rd_rm
),
14986 cCL(tanem
, ea88140
, 2, (RF
, RF_IF
), rd_rm
),
14987 cCL(tanez
, ea88160
, 2, (RF
, RF_IF
), rd_rm
),
14989 cCL(asns
, eb08100
, 2, (RF
, RF_IF
), rd_rm
),
14990 cCL(asnsp
, eb08120
, 2, (RF
, RF_IF
), rd_rm
),
14991 cCL(asnsm
, eb08140
, 2, (RF
, RF_IF
), rd_rm
),
14992 cCL(asnsz
, eb08160
, 2, (RF
, RF_IF
), rd_rm
),
14993 cCL(asnd
, eb08180
, 2, (RF
, RF_IF
), rd_rm
),
14994 cCL(asndp
, eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
14995 cCL(asndm
, eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
14996 cCL(asndz
, eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
14997 cCL(asne
, eb88100
, 2, (RF
, RF_IF
), rd_rm
),
14998 cCL(asnep
, eb88120
, 2, (RF
, RF_IF
), rd_rm
),
14999 cCL(asnem
, eb88140
, 2, (RF
, RF_IF
), rd_rm
),
15000 cCL(asnez
, eb88160
, 2, (RF
, RF_IF
), rd_rm
),
15002 cCL(acss
, ec08100
, 2, (RF
, RF_IF
), rd_rm
),
15003 cCL(acssp
, ec08120
, 2, (RF
, RF_IF
), rd_rm
),
15004 cCL(acssm
, ec08140
, 2, (RF
, RF_IF
), rd_rm
),
15005 cCL(acssz
, ec08160
, 2, (RF
, RF_IF
), rd_rm
),
15006 cCL(acsd
, ec08180
, 2, (RF
, RF_IF
), rd_rm
),
15007 cCL(acsdp
, ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
15008 cCL(acsdm
, ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
15009 cCL(acsdz
, ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
15010 cCL(acse
, ec88100
, 2, (RF
, RF_IF
), rd_rm
),
15011 cCL(acsep
, ec88120
, 2, (RF
, RF_IF
), rd_rm
),
15012 cCL(acsem
, ec88140
, 2, (RF
, RF_IF
), rd_rm
),
15013 cCL(acsez
, ec88160
, 2, (RF
, RF_IF
), rd_rm
),
15015 cCL(atns
, ed08100
, 2, (RF
, RF_IF
), rd_rm
),
15016 cCL(atnsp
, ed08120
, 2, (RF
, RF_IF
), rd_rm
),
15017 cCL(atnsm
, ed08140
, 2, (RF
, RF_IF
), rd_rm
),
15018 cCL(atnsz
, ed08160
, 2, (RF
, RF_IF
), rd_rm
),
15019 cCL(atnd
, ed08180
, 2, (RF
, RF_IF
), rd_rm
),
15020 cCL(atndp
, ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
15021 cCL(atndm
, ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
15022 cCL(atndz
, ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
15023 cCL(atne
, ed88100
, 2, (RF
, RF_IF
), rd_rm
),
15024 cCL(atnep
, ed88120
, 2, (RF
, RF_IF
), rd_rm
),
15025 cCL(atnem
, ed88140
, 2, (RF
, RF_IF
), rd_rm
),
15026 cCL(atnez
, ed88160
, 2, (RF
, RF_IF
), rd_rm
),
15028 cCL(urds
, ee08100
, 2, (RF
, RF_IF
), rd_rm
),
15029 cCL(urdsp
, ee08120
, 2, (RF
, RF_IF
), rd_rm
),
15030 cCL(urdsm
, ee08140
, 2, (RF
, RF_IF
), rd_rm
),
15031 cCL(urdsz
, ee08160
, 2, (RF
, RF_IF
), rd_rm
),
15032 cCL(urdd
, ee08180
, 2, (RF
, RF_IF
), rd_rm
),
15033 cCL(urddp
, ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
15034 cCL(urddm
, ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
15035 cCL(urddz
, ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
15036 cCL(urde
, ee88100
, 2, (RF
, RF_IF
), rd_rm
),
15037 cCL(urdep
, ee88120
, 2, (RF
, RF_IF
), rd_rm
),
15038 cCL(urdem
, ee88140
, 2, (RF
, RF_IF
), rd_rm
),
15039 cCL(urdez
, ee88160
, 2, (RF
, RF_IF
), rd_rm
),
15041 cCL(nrms
, ef08100
, 2, (RF
, RF_IF
), rd_rm
),
15042 cCL(nrmsp
, ef08120
, 2, (RF
, RF_IF
), rd_rm
),
15043 cCL(nrmsm
, ef08140
, 2, (RF
, RF_IF
), rd_rm
),
15044 cCL(nrmsz
, ef08160
, 2, (RF
, RF_IF
), rd_rm
),
15045 cCL(nrmd
, ef08180
, 2, (RF
, RF_IF
), rd_rm
),
15046 cCL(nrmdp
, ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
15047 cCL(nrmdm
, ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
15048 cCL(nrmdz
, ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
15049 cCL(nrme
, ef88100
, 2, (RF
, RF_IF
), rd_rm
),
15050 cCL(nrmep
, ef88120
, 2, (RF
, RF_IF
), rd_rm
),
15051 cCL(nrmem
, ef88140
, 2, (RF
, RF_IF
), rd_rm
),
15052 cCL(nrmez
, ef88160
, 2, (RF
, RF_IF
), rd_rm
),
15054 cCL(adfs
, e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15055 cCL(adfsp
, e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15056 cCL(adfsm
, e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15057 cCL(adfsz
, e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15058 cCL(adfd
, e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15059 cCL(adfdp
, e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15060 cCL(adfdm
, e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15061 cCL(adfdz
, e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15062 cCL(adfe
, e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15063 cCL(adfep
, e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15064 cCL(adfem
, e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15065 cCL(adfez
, e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15067 cCL(sufs
, e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15068 cCL(sufsp
, e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15069 cCL(sufsm
, e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15070 cCL(sufsz
, e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15071 cCL(sufd
, e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15072 cCL(sufdp
, e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15073 cCL(sufdm
, e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15074 cCL(sufdz
, e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15075 cCL(sufe
, e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15076 cCL(sufep
, e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15077 cCL(sufem
, e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15078 cCL(sufez
, e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15080 cCL(rsfs
, e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15081 cCL(rsfsp
, e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15082 cCL(rsfsm
, e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15083 cCL(rsfsz
, e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15084 cCL(rsfd
, e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15085 cCL(rsfdp
, e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15086 cCL(rsfdm
, e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15087 cCL(rsfdz
, e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15088 cCL(rsfe
, e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15089 cCL(rsfep
, e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15090 cCL(rsfem
, e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15091 cCL(rsfez
, e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15093 cCL(mufs
, e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15094 cCL(mufsp
, e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15095 cCL(mufsm
, e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15096 cCL(mufsz
, e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15097 cCL(mufd
, e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15098 cCL(mufdp
, e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15099 cCL(mufdm
, e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15100 cCL(mufdz
, e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15101 cCL(mufe
, e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15102 cCL(mufep
, e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15103 cCL(mufem
, e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15104 cCL(mufez
, e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15106 cCL(dvfs
, e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15107 cCL(dvfsp
, e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15108 cCL(dvfsm
, e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15109 cCL(dvfsz
, e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15110 cCL(dvfd
, e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15111 cCL(dvfdp
, e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15112 cCL(dvfdm
, e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15113 cCL(dvfdz
, e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15114 cCL(dvfe
, e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15115 cCL(dvfep
, e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15116 cCL(dvfem
, e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15117 cCL(dvfez
, e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15119 cCL(rdfs
, e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15120 cCL(rdfsp
, e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15121 cCL(rdfsm
, e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15122 cCL(rdfsz
, e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15123 cCL(rdfd
, e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15124 cCL(rdfdp
, e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15125 cCL(rdfdm
, e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15126 cCL(rdfdz
, e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15127 cCL(rdfe
, e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15128 cCL(rdfep
, e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15129 cCL(rdfem
, e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15130 cCL(rdfez
, e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15132 cCL(pows
, e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15133 cCL(powsp
, e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15134 cCL(powsm
, e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15135 cCL(powsz
, e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15136 cCL(powd
, e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15137 cCL(powdp
, e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15138 cCL(powdm
, e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15139 cCL(powdz
, e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15140 cCL(powe
, e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15141 cCL(powep
, e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15142 cCL(powem
, e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15143 cCL(powez
, e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15145 cCL(rpws
, e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15146 cCL(rpwsp
, e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15147 cCL(rpwsm
, e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15148 cCL(rpwsz
, e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15149 cCL(rpwd
, e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15150 cCL(rpwdp
, e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15151 cCL(rpwdm
, e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15152 cCL(rpwdz
, e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15153 cCL(rpwe
, e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15154 cCL(rpwep
, e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15155 cCL(rpwem
, e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15156 cCL(rpwez
, e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15158 cCL(rmfs
, e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15159 cCL(rmfsp
, e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15160 cCL(rmfsm
, e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15161 cCL(rmfsz
, e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15162 cCL(rmfd
, e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15163 cCL(rmfdp
, e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15164 cCL(rmfdm
, e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15165 cCL(rmfdz
, e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15166 cCL(rmfe
, e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15167 cCL(rmfep
, e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15168 cCL(rmfem
, e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15169 cCL(rmfez
, e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15171 cCL(fmls
, e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15172 cCL(fmlsp
, e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15173 cCL(fmlsm
, e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15174 cCL(fmlsz
, e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15175 cCL(fmld
, e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15176 cCL(fmldp
, e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15177 cCL(fmldm
, e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15178 cCL(fmldz
, e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15179 cCL(fmle
, e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15180 cCL(fmlep
, e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15181 cCL(fmlem
, e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15182 cCL(fmlez
, e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15184 cCL(fdvs
, ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15185 cCL(fdvsp
, ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15186 cCL(fdvsm
, ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15187 cCL(fdvsz
, ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15188 cCL(fdvd
, ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15189 cCL(fdvdp
, ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15190 cCL(fdvdm
, ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15191 cCL(fdvdz
, ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15192 cCL(fdve
, ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15193 cCL(fdvep
, ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15194 cCL(fdvem
, ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15195 cCL(fdvez
, ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15197 cCL(frds
, eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15198 cCL(frdsp
, eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15199 cCL(frdsm
, eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15200 cCL(frdsz
, eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15201 cCL(frdd
, eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15202 cCL(frddp
, eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15203 cCL(frddm
, eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15204 cCL(frddz
, eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15205 cCL(frde
, eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15206 cCL(frdep
, eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15207 cCL(frdem
, eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15208 cCL(frdez
, eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15210 cCL(pols
, ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15211 cCL(polsp
, ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15212 cCL(polsm
, ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15213 cCL(polsz
, ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15214 cCL(pold
, ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15215 cCL(poldp
, ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15216 cCL(poldm
, ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15217 cCL(poldz
, ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15218 cCL(pole
, ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15219 cCL(polep
, ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15220 cCL(polem
, ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15221 cCL(polez
, ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15223 cCE(cmf
, e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15224 C3E(cmfe
, ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15225 cCE(cnf
, eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15226 C3E(cnfe
, ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15228 cCL(flts
, e000110
, 2, (RF
, RR
), rn_rd
),
15229 cCL(fltsp
, e000130
, 2, (RF
, RR
), rn_rd
),
15230 cCL(fltsm
, e000150
, 2, (RF
, RR
), rn_rd
),
15231 cCL(fltsz
, e000170
, 2, (RF
, RR
), rn_rd
),
15232 cCL(fltd
, e000190
, 2, (RF
, RR
), rn_rd
),
15233 cCL(fltdp
, e0001b0
, 2, (RF
, RR
), rn_rd
),
15234 cCL(fltdm
, e0001d0
, 2, (RF
, RR
), rn_rd
),
15235 cCL(fltdz
, e0001f0
, 2, (RF
, RR
), rn_rd
),
15236 cCL(flte
, e080110
, 2, (RF
, RR
), rn_rd
),
15237 cCL(fltep
, e080130
, 2, (RF
, RR
), rn_rd
),
15238 cCL(fltem
, e080150
, 2, (RF
, RR
), rn_rd
),
15239 cCL(fltez
, e080170
, 2, (RF
, RR
), rn_rd
),
15241 /* The implementation of the FIX instruction is broken on some
15242 assemblers, in that it accepts a precision specifier as well as a
15243 rounding specifier, despite the fact that this is meaningless.
15244 To be more compatible, we accept it as well, though of course it
15245 does not set any bits. */
15246 cCE(fix
, e100110
, 2, (RR
, RF
), rd_rm
),
15247 cCL(fixp
, e100130
, 2, (RR
, RF
), rd_rm
),
15248 cCL(fixm
, e100150
, 2, (RR
, RF
), rd_rm
),
15249 cCL(fixz
, e100170
, 2, (RR
, RF
), rd_rm
),
15250 cCL(fixsp
, e100130
, 2, (RR
, RF
), rd_rm
),
15251 cCL(fixsm
, e100150
, 2, (RR
, RF
), rd_rm
),
15252 cCL(fixsz
, e100170
, 2, (RR
, RF
), rd_rm
),
15253 cCL(fixdp
, e100130
, 2, (RR
, RF
), rd_rm
),
15254 cCL(fixdm
, e100150
, 2, (RR
, RF
), rd_rm
),
15255 cCL(fixdz
, e100170
, 2, (RR
, RF
), rd_rm
),
15256 cCL(fixep
, e100130
, 2, (RR
, RF
), rd_rm
),
15257 cCL(fixem
, e100150
, 2, (RR
, RF
), rd_rm
),
15258 cCL(fixez
, e100170
, 2, (RR
, RF
), rd_rm
),
15260 /* Instructions that were new with the real FPA, call them V2. */
15262 #define ARM_VARIANT &fpu_fpa_ext_v2
15263 cCE(lfm
, c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15264 cCL(lfmfd
, c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15265 cCL(lfmea
, d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15266 cCE(sfm
, c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15267 cCL(sfmfd
, d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15268 cCL(sfmea
, c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15271 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
15272 /* Moves and type conversions. */
15273 cCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15274 cCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
15275 cCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
15276 cCE(fmstat
, ef1fa10
, 0, (), noargs
),
15277 cCE(fsitos
, eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15278 cCE(fuitos
, eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15279 cCE(ftosis
, ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15280 cCE(ftosizs
, ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15281 cCE(ftouis
, ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15282 cCE(ftouizs
, ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15283 cCE(fmrx
, ef00a10
, 2, (RR
, RVC
), rd_rn
),
15284 cCE(fmxr
, ee00a10
, 2, (RVC
, RR
), rn_rd
),
15286 /* Memory operations. */
15287 cCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15288 cCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15289 cCE(fldmias
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15290 cCE(fldmfds
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15291 cCE(fldmdbs
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15292 cCE(fldmeas
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15293 cCE(fldmiax
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15294 cCE(fldmfdx
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15295 cCE(fldmdbx
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15296 cCE(fldmeax
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15297 cCE(fstmias
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15298 cCE(fstmeas
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15299 cCE(fstmdbs
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15300 cCE(fstmfds
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15301 cCE(fstmiax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15302 cCE(fstmeax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15303 cCE(fstmdbx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15304 cCE(fstmfdx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15306 /* Monadic operations. */
15307 cCE(fabss
, eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15308 cCE(fnegs
, eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15309 cCE(fsqrts
, eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15311 /* Dyadic operations. */
15312 cCE(fadds
, e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15313 cCE(fsubs
, e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15314 cCE(fmuls
, e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15315 cCE(fdivs
, e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15316 cCE(fmacs
, e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15317 cCE(fmscs
, e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15318 cCE(fnmuls
, e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15319 cCE(fnmacs
, e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15320 cCE(fnmscs
, e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15323 cCE(fcmps
, eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15324 cCE(fcmpzs
, eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
15325 cCE(fcmpes
, eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15326 cCE(fcmpezs
, eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
15329 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
15330 /* Moves and type conversions. */
15331 cCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15332 cCE(fcvtds
, eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15333 cCE(fcvtsd
, eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15334 cCE(fmdhr
, e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15335 cCE(fmdlr
, e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15336 cCE(fmrdh
, e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15337 cCE(fmrdl
, e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15338 cCE(fsitod
, eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15339 cCE(fuitod
, eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15340 cCE(ftosid
, ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15341 cCE(ftosizd
, ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15342 cCE(ftouid
, ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15343 cCE(ftouizd
, ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15345 /* Memory operations. */
15346 cCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15347 cCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15348 cCE(fldmiad
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15349 cCE(fldmfdd
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15350 cCE(fldmdbd
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15351 cCE(fldmead
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15352 cCE(fstmiad
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15353 cCE(fstmead
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15354 cCE(fstmdbd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15355 cCE(fstmfdd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15357 /* Monadic operations. */
15358 cCE(fabsd
, eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15359 cCE(fnegd
, eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15360 cCE(fsqrtd
, eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15362 /* Dyadic operations. */
15363 cCE(faddd
, e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15364 cCE(fsubd
, e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15365 cCE(fmuld
, e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15366 cCE(fdivd
, e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15367 cCE(fmacd
, e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15368 cCE(fmscd
, e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15369 cCE(fnmuld
, e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15370 cCE(fnmacd
, e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15371 cCE(fnmscd
, e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15374 cCE(fcmpd
, eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15375 cCE(fcmpzd
, eb50b40
, 1, (RVD
), vfp_dp_rd
),
15376 cCE(fcmped
, eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15377 cCE(fcmpezd
, eb50bc0
, 1, (RVD
), vfp_dp_rd
),
15380 #define ARM_VARIANT &fpu_vfp_ext_v2
15381 cCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
15382 cCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
15383 cCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
15384 cCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
15386 /* Instructions which may belong to either the Neon or VFP instruction sets.
15387 Individual encoder functions perform additional architecture checks. */
15389 #define ARM_VARIANT &fpu_vfp_ext_v1xd
15390 #undef THUMB_VARIANT
15391 #define THUMB_VARIANT &fpu_vfp_ext_v1xd
15392 /* These mnemonics are unique to VFP. */
15393 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
15394 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
15395 nCE(vnmul
, vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15396 nCE(vnmla
, vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15397 nCE(vnmls
, vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15398 nCE(vcmp
, vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15399 nCE(vcmpe
, vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15400 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
15401 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
15402 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
15404 /* Mnemonics shared by Neon and VFP. */
15405 nCEF(vmul
, vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
15406 nCEF(vmla
, vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15407 nCEF(vmls
, vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15409 nCEF(vadd
, vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15410 nCEF(vsub
, vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15412 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15413 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15415 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15416 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15417 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15418 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15419 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15420 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15421 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15422 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15424 nCEF(vcvt
, vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
15426 /* NOTE: All VMOV encoding is special-cased! */
15427 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
15428 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
15430 #undef THUMB_VARIANT
15431 #define THUMB_VARIANT &fpu_neon_ext_v1
15433 #define ARM_VARIANT &fpu_neon_ext_v1
15434 /* Data processing with three registers of the same length. */
15435 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
15436 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
15437 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
15438 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15439 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15440 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15441 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15442 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15443 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15444 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
15445 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15446 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15447 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15448 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15449 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15450 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15451 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15452 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15453 /* If not immediate, fall back to neon_dyadic_i64_su.
15454 shl_imm should accept I8 I16 I32 I64,
15455 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
15456 nUF(vshl
, vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
15457 nUF(vshlq
, vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
15458 nUF(vqshl
, vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
15459 nUF(vqshlq
, vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
15460 /* Logic ops, types optional & ignored. */
15461 nUF(vand
, vand
, 2, (RNDQ
, NILO
), neon_logic
),
15462 nUF(vandq
, vand
, 2, (RNQ
, NILO
), neon_logic
),
15463 nUF(vbic
, vbic
, 2, (RNDQ
, NILO
), neon_logic
),
15464 nUF(vbicq
, vbic
, 2, (RNQ
, NILO
), neon_logic
),
15465 nUF(vorr
, vorr
, 2, (RNDQ
, NILO
), neon_logic
),
15466 nUF(vorrq
, vorr
, 2, (RNQ
, NILO
), neon_logic
),
15467 nUF(vorn
, vorn
, 2, (RNDQ
, NILO
), neon_logic
),
15468 nUF(vornq
, vorn
, 2, (RNQ
, NILO
), neon_logic
),
15469 nUF(veor
, veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
15470 nUF(veorq
, veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
15471 /* Bitfield ops, untyped. */
15472 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15473 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15474 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15475 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15476 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15477 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15478 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
15479 nUF(vabd
, vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15480 nUF(vabdq
, vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15481 nUF(vmax
, vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15482 nUF(vmaxq
, vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15483 nUF(vmin
, vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15484 nUF(vminq
, vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15485 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
15486 back to neon_dyadic_if_su. */
15487 nUF(vcge
, vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
15488 nUF(vcgeq
, vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
15489 nUF(vcgt
, vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
15490 nUF(vcgtq
, vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
15491 nUF(vclt
, vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
15492 nUF(vcltq
, vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
15493 nUF(vcle
, vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
15494 nUF(vcleq
, vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
15495 /* Comparison. Type I8 I16 I32 F32. Non-immediate -> neon_dyadic_if_i. */
15496 nUF(vceq
, vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
15497 nUF(vceqq
, vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
15498 /* As above, D registers only. */
15499 nUF(vpmax
, vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
15500 nUF(vpmin
, vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
15501 /* Int and float variants, signedness unimportant. */
15502 /* If not scalar, fall back to neon_dyadic_if_i. */
15503 nUF(vmlaq
, vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
15504 nUF(vmlsq
, vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
15505 nUF(vpadd
, vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
15506 /* Add/sub take types I8 I16 I32 I64 F32. */
15507 nUF(vaddq
, vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
15508 nUF(vsubq
, vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
15509 /* vtst takes sizes 8, 16, 32. */
15510 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
15511 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
15512 /* VMUL takes I8 I16 I32 F32 P8. */
15513 nUF(vmulq
, vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
15514 /* VQD{R}MULH takes S16 S32. */
15515 nUF(vqdmulh
, vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
15516 nUF(vqdmulhq
, vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
15517 nUF(vqrdmulh
, vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
15518 nUF(vqrdmulhq
, vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
15519 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
15520 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
15521 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
15522 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
15523 NUF(vaclt
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
15524 NUF(vacltq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
15525 NUF(vacle
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
15526 NUF(vacleq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
15527 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
15528 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
15529 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
15530 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
15532 /* Two address, int/float. Types S8 S16 S32 F32. */
15533 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
15534 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
15536 /* Data processing with two registers and a shift amount. */
15537 /* Right shifts, and variants with rounding.
15538 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
15539 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
15540 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
15541 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
15542 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
15543 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
15544 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
15545 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
15546 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
15547 /* Shift and insert. Sizes accepted 8 16 32 64. */
15548 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
15549 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
15550 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
15551 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
15552 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
15553 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
15554 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
15555 /* Right shift immediate, saturating & narrowing, with rounding variants.
15556 Types accepted S16 S32 S64 U16 U32 U64. */
15557 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
15558 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
15559 /* As above, unsigned. Types accepted S16 S32 S64. */
15560 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
15561 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
15562 /* Right shift narrowing. Types accepted I16 I32 I64. */
15563 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
15564 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
15565 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
15566 nUF(vshll
, vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
15567 /* CVT with optional immediate for fixed-point variant. */
15568 nUF(vcvtq
, vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
15570 nUF(vmvn
, vmvn
, 2, (RNDQ
, RNDQ_IMVNb
), neon_mvn
),
15571 nUF(vmvnq
, vmvn
, 2, (RNQ
, RNDQ_IMVNb
), neon_mvn
),
15573 /* Data processing, three registers of different lengths. */
15574 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
15575 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
15576 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
15577 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
15578 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
15579 /* If not scalar, fall back to neon_dyadic_long.
15580 Vector types as above, scalar types S16 S32 U16 U32. */
15581 nUF(vmlal
, vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
15582 nUF(vmlsl
, vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
15583 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
15584 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
15585 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
15586 /* Dyadic, narrowing insns. Types I16 I32 I64. */
15587 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15588 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15589 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15590 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15591 /* Saturating doubling multiplies. Types S16 S32. */
15592 nUF(vqdmlal
, vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
15593 nUF(vqdmlsl
, vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
15594 nUF(vqdmull
, vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
15595 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
15596 S16 S32 U16 U32. */
15597 nUF(vmull
, vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
15599 /* Extract. Size 8. */
15600 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I7
), neon_ext
),
15601 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I7
), neon_ext
),
15603 /* Two registers, miscellaneous. */
15604 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
15605 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
15606 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
15607 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
15608 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
15609 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
15610 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
15611 /* Vector replicate. Sizes 8 16 32. */
15612 nCE(vdup
, vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
15613 nCE(vdupq
, vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
15614 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
15615 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
15616 /* VMOVN. Types I16 I32 I64. */
15617 nUF(vmovn
, vmovn
, 2, (RND
, RNQ
), neon_movn
),
15618 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
15619 nUF(vqmovn
, vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
15620 /* VQMOVUN. Types S16 S32 S64. */
15621 nUF(vqmovun
, vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
15622 /* VZIP / VUZP. Sizes 8 16 32. */
15623 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
15624 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
15625 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
15626 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
15627 /* VQABS / VQNEG. Types S8 S16 S32. */
15628 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
15629 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
15630 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
15631 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
15632 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
15633 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
15634 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
15635 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
15636 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
15637 /* Reciprocal estimates. Types U32 F32. */
15638 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
15639 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
15640 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
15641 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
15642 /* VCLS. Types S8 S16 S32. */
15643 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
15644 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
15645 /* VCLZ. Types I8 I16 I32. */
15646 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
15647 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
15648 /* VCNT. Size 8. */
15649 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
15650 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
15651 /* Two address, untyped. */
15652 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
15653 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
15654 /* VTRN. Sizes 8 16 32. */
15655 nUF(vtrn
, vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
15656 nUF(vtrnq
, vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
15658 /* Table lookup. Size 8. */
15659 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
15660 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
15662 #undef THUMB_VARIANT
15663 #define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
15665 #define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
15666 /* Neon element/structure load/store. */
15667 nUF(vld1
, vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15668 nUF(vst1
, vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15669 nUF(vld2
, vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15670 nUF(vst2
, vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15671 nUF(vld3
, vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15672 nUF(vst3
, vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15673 nUF(vld4
, vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15674 nUF(vst4
, vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15676 #undef THUMB_VARIANT
15677 #define THUMB_VARIANT &fpu_vfp_ext_v3
15679 #define ARM_VARIANT &fpu_vfp_ext_v3
15680 cCE(fconsts
, eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
15681 cCE(fconstd
, eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
15682 cCE(fshtos
, eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15683 cCE(fshtod
, eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15684 cCE(fsltos
, eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15685 cCE(fsltod
, eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15686 cCE(fuhtos
, ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15687 cCE(fuhtod
, ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15688 cCE(fultos
, ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15689 cCE(fultod
, ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15690 cCE(ftoshs
, ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15691 cCE(ftoshd
, ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15692 cCE(ftosls
, ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15693 cCE(ftosld
, ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15694 cCE(ftouhs
, ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15695 cCE(ftouhd
, ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15696 cCE(ftouls
, ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15697 cCE(ftould
, ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15699 #undef THUMB_VARIANT
15701 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
15702 cCE(mia
, e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15703 cCE(miaph
, e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15704 cCE(miabb
, e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15705 cCE(miabt
, e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15706 cCE(miatb
, e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15707 cCE(miatt
, e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15708 cCE(mar
, c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
15709 cCE(mra
, c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
15712 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
15713 cCE(tandcb
, e13f130
, 1, (RR
), iwmmxt_tandorc
),
15714 cCE(tandch
, e53f130
, 1, (RR
), iwmmxt_tandorc
),
15715 cCE(tandcw
, e93f130
, 1, (RR
), iwmmxt_tandorc
),
15716 cCE(tbcstb
, e400010
, 2, (RIWR
, RR
), rn_rd
),
15717 cCE(tbcsth
, e400050
, 2, (RIWR
, RR
), rn_rd
),
15718 cCE(tbcstw
, e400090
, 2, (RIWR
, RR
), rn_rd
),
15719 cCE(textrcb
, e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
15720 cCE(textrch
, e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
15721 cCE(textrcw
, e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
15722 cCE(textrmub
, e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15723 cCE(textrmuh
, e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15724 cCE(textrmuw
, e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15725 cCE(textrmsb
, e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15726 cCE(textrmsh
, e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15727 cCE(textrmsw
, e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15728 cCE(tinsrb
, e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
15729 cCE(tinsrh
, e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
15730 cCE(tinsrw
, e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
15731 cCE(tmcr
, e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
15732 cCE(tmcrr
, c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
15733 cCE(tmia
, e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15734 cCE(tmiaph
, e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15735 cCE(tmiabb
, e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15736 cCE(tmiabt
, e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15737 cCE(tmiatb
, e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15738 cCE(tmiatt
, e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15739 cCE(tmovmskb
, e100030
, 2, (RR
, RIWR
), rd_rn
),
15740 cCE(tmovmskh
, e500030
, 2, (RR
, RIWR
), rd_rn
),
15741 cCE(tmovmskw
, e900030
, 2, (RR
, RIWR
), rd_rn
),
15742 cCE(tmrc
, e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
15743 cCE(tmrrc
, c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
15744 cCE(torcb
, e13f150
, 1, (RR
), iwmmxt_tandorc
),
15745 cCE(torch
, e53f150
, 1, (RR
), iwmmxt_tandorc
),
15746 cCE(torcw
, e93f150
, 1, (RR
), iwmmxt_tandorc
),
15747 cCE(waccb
, e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
15748 cCE(wacch
, e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
15749 cCE(waccw
, e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
15750 cCE(waddbss
, e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15751 cCE(waddb
, e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15752 cCE(waddbus
, e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15753 cCE(waddhss
, e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15754 cCE(waddh
, e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15755 cCE(waddhus
, e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15756 cCE(waddwss
, eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15757 cCE(waddw
, e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15758 cCE(waddwus
, e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15759 cCE(waligni
, e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
15760 cCE(walignr0
, e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15761 cCE(walignr1
, e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15762 cCE(walignr2
, ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15763 cCE(walignr3
, eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15764 cCE(wand
, e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15765 cCE(wandn
, e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15766 cCE(wavg2b
, e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15767 cCE(wavg2br
, e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15768 cCE(wavg2h
, ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15769 cCE(wavg2hr
, ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15770 cCE(wcmpeqb
, e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15771 cCE(wcmpeqh
, e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15772 cCE(wcmpeqw
, e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15773 cCE(wcmpgtub
, e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15774 cCE(wcmpgtuh
, e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15775 cCE(wcmpgtuw
, e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15776 cCE(wcmpgtsb
, e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15777 cCE(wcmpgtsh
, e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15778 cCE(wcmpgtsw
, eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15779 cCE(wldrb
, c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
15780 cCE(wldrh
, c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
15781 cCE(wldrw
, c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
15782 cCE(wldrd
, c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
15783 cCE(wmacs
, e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15784 cCE(wmacsz
, e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15785 cCE(wmacu
, e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15786 cCE(wmacuz
, e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15787 cCE(wmadds
, ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15788 cCE(wmaddu
, e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15789 cCE(wmaxsb
, e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15790 cCE(wmaxsh
, e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15791 cCE(wmaxsw
, ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15792 cCE(wmaxub
, e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15793 cCE(wmaxuh
, e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15794 cCE(wmaxuw
, e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15795 cCE(wminsb
, e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15796 cCE(wminsh
, e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15797 cCE(wminsw
, eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15798 cCE(wminub
, e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15799 cCE(wminuh
, e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15800 cCE(wminuw
, e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15801 cCE(wmov
, e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
15802 cCE(wmulsm
, e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15803 cCE(wmulsl
, e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15804 cCE(wmulum
, e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15805 cCE(wmulul
, e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15806 cCE(wor
, e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15807 cCE(wpackhss
, e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15808 cCE(wpackhus
, e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15809 cCE(wpackwss
, eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15810 cCE(wpackwus
, e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15811 cCE(wpackdss
, ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15812 cCE(wpackdus
, ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15813 cCE(wrorh
, e700040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15814 cCE(wrorhg
, e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15815 cCE(wrorw
, eb00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15816 cCE(wrorwg
, eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15817 cCE(wrord
, ef00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15818 cCE(wrordg
, ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15819 cCE(wsadb
, e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15820 cCE(wsadbz
, e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15821 cCE(wsadh
, e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15822 cCE(wsadhz
, e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15823 cCE(wshufh
, e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
15824 cCE(wsllh
, e500040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15825 cCE(wsllhg
, e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15826 cCE(wsllw
, e900040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15827 cCE(wsllwg
, e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15828 cCE(wslld
, ed00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15829 cCE(wslldg
, ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15830 cCE(wsrah
, e400040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15831 cCE(wsrahg
, e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15832 cCE(wsraw
, e800040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15833 cCE(wsrawg
, e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15834 cCE(wsrad
, ec00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15835 cCE(wsradg
, ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15836 cCE(wsrlh
, e600040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15837 cCE(wsrlhg
, e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15838 cCE(wsrlw
, ea00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15839 cCE(wsrlwg
, ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15840 cCE(wsrld
, ee00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15841 cCE(wsrldg
, ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15842 cCE(wstrb
, c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
15843 cCE(wstrh
, c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
15844 cCE(wstrw
, c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
15845 cCE(wstrd
, c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
15846 cCE(wsubbss
, e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15847 cCE(wsubb
, e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15848 cCE(wsubbus
, e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15849 cCE(wsubhss
, e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15850 cCE(wsubh
, e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15851 cCE(wsubhus
, e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15852 cCE(wsubwss
, eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15853 cCE(wsubw
, e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15854 cCE(wsubwus
, e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15855 cCE(wunpckehub
,e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15856 cCE(wunpckehuh
,e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15857 cCE(wunpckehuw
,e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15858 cCE(wunpckehsb
,e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15859 cCE(wunpckehsh
,e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15860 cCE(wunpckehsw
,ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15861 cCE(wunpckihb
, e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15862 cCE(wunpckihh
, e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15863 cCE(wunpckihw
, e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15864 cCE(wunpckelub
,e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15865 cCE(wunpckeluh
,e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15866 cCE(wunpckeluw
,e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15867 cCE(wunpckelsb
,e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15868 cCE(wunpckelsh
,e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15869 cCE(wunpckelsw
,ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15870 cCE(wunpckilb
, e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15871 cCE(wunpckilh
, e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15872 cCE(wunpckilw
, e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15873 cCE(wxor
, e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15874 cCE(wzero
, e300000
, 1, (RIWR
), iwmmxt_wzero
),
15877 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
15878 cCE(cfldrs
, c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
15879 cCE(cfldrd
, c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
15880 cCE(cfldr32
, c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
15881 cCE(cfldr64
, c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
15882 cCE(cfstrs
, c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
15883 cCE(cfstrd
, c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
15884 cCE(cfstr32
, c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
15885 cCE(cfstr64
, c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
15886 cCE(cfmvsr
, e000450
, 2, (RMF
, RR
), rn_rd
),
15887 cCE(cfmvrs
, e100450
, 2, (RR
, RMF
), rd_rn
),
15888 cCE(cfmvdlr
, e000410
, 2, (RMD
, RR
), rn_rd
),
15889 cCE(cfmvrdl
, e100410
, 2, (RR
, RMD
), rd_rn
),
15890 cCE(cfmvdhr
, e000430
, 2, (RMD
, RR
), rn_rd
),
15891 cCE(cfmvrdh
, e100430
, 2, (RR
, RMD
), rd_rn
),
15892 cCE(cfmv64lr
, e000510
, 2, (RMDX
, RR
), rn_rd
),
15893 cCE(cfmvr64l
, e100510
, 2, (RR
, RMDX
), rd_rn
),
15894 cCE(cfmv64hr
, e000530
, 2, (RMDX
, RR
), rn_rd
),
15895 cCE(cfmvr64h
, e100530
, 2, (RR
, RMDX
), rd_rn
),
15896 cCE(cfmval32
, e200440
, 2, (RMAX
, RMFX
), rd_rn
),
15897 cCE(cfmv32al
, e100440
, 2, (RMFX
, RMAX
), rd_rn
),
15898 cCE(cfmvam32
, e200460
, 2, (RMAX
, RMFX
), rd_rn
),
15899 cCE(cfmv32am
, e100460
, 2, (RMFX
, RMAX
), rd_rn
),
15900 cCE(cfmvah32
, e200480
, 2, (RMAX
, RMFX
), rd_rn
),
15901 cCE(cfmv32ah
, e100480
, 2, (RMFX
, RMAX
), rd_rn
),
15902 cCE(cfmva32
, e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
15903 cCE(cfmv32a
, e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
15904 cCE(cfmva64
, e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
15905 cCE(cfmv64a
, e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
15906 cCE(cfmvsc32
, e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
15907 cCE(cfmv32sc
, e1004e0
, 2, (RMDX
, RMDS
), rd
),
15908 cCE(cfcpys
, e000400
, 2, (RMF
, RMF
), rd_rn
),
15909 cCE(cfcpyd
, e000420
, 2, (RMD
, RMD
), rd_rn
),
15910 cCE(cfcvtsd
, e000460
, 2, (RMD
, RMF
), rd_rn
),
15911 cCE(cfcvtds
, e000440
, 2, (RMF
, RMD
), rd_rn
),
15912 cCE(cfcvt32s
, e000480
, 2, (RMF
, RMFX
), rd_rn
),
15913 cCE(cfcvt32d
, e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
15914 cCE(cfcvt64s
, e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
15915 cCE(cfcvt64d
, e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
15916 cCE(cfcvts32
, e100580
, 2, (RMFX
, RMF
), rd_rn
),
15917 cCE(cfcvtd32
, e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
15918 cCE(cftruncs32
,e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
15919 cCE(cftruncd32
,e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
15920 cCE(cfrshl32
, e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
15921 cCE(cfrshl64
, e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
15922 cCE(cfsh32
, e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
15923 cCE(cfsh64
, e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
15924 cCE(cfcmps
, e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
15925 cCE(cfcmpd
, e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
15926 cCE(cfcmp32
, e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
15927 cCE(cfcmp64
, e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
15928 cCE(cfabss
, e300400
, 2, (RMF
, RMF
), rd_rn
),
15929 cCE(cfabsd
, e300420
, 2, (RMD
, RMD
), rd_rn
),
15930 cCE(cfnegs
, e300440
, 2, (RMF
, RMF
), rd_rn
),
15931 cCE(cfnegd
, e300460
, 2, (RMD
, RMD
), rd_rn
),
15932 cCE(cfadds
, e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
15933 cCE(cfaddd
, e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
15934 cCE(cfsubs
, e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
15935 cCE(cfsubd
, e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
15936 cCE(cfmuls
, e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
15937 cCE(cfmuld
, e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
15938 cCE(cfabs32
, e300500
, 2, (RMFX
, RMFX
), rd_rn
),
15939 cCE(cfabs64
, e300520
, 2, (RMDX
, RMDX
), rd_rn
),
15940 cCE(cfneg32
, e300540
, 2, (RMFX
, RMFX
), rd_rn
),
15941 cCE(cfneg64
, e300560
, 2, (RMDX
, RMDX
), rd_rn
),
15942 cCE(cfadd32
, e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15943 cCE(cfadd64
, e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
15944 cCE(cfsub32
, e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15945 cCE(cfsub64
, e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
15946 cCE(cfmul32
, e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15947 cCE(cfmul64
, e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
15948 cCE(cfmac32
, e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15949 cCE(cfmsc32
, e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15950 cCE(cfmadd32
, e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
15951 cCE(cfmsub32
, e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
15952 cCE(cfmadda32
, e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
15953 cCE(cfmsuba32
, e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
15956 #undef THUMB_VARIANT
15983 /* MD interface: bits in the object file. */
15985 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
15986 for use in the a.out file, and stores them in the array pointed to by buf.
15987 This knows about the endian-ness of the target machine and does
15988 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
15989 2 (short) and 4 (long) Floating numbers are put out as a series of
15990 LITTLENUMS (shorts, here at least). */
15993 md_number_to_chars (char * buf
, valueT val
, int n
)
15995 if (target_big_endian
)
15996 number_to_chars_bigendian (buf
, val
, n
);
15998 number_to_chars_littleendian (buf
, val
, n
);
16002 md_chars_to_number (char * buf
, int n
)
16005 unsigned char * where
= (unsigned char *) buf
;
16007 if (target_big_endian
)
16012 result
|= (*where
++ & 255);
16020 result
|= (where
[n
] & 255);
16027 /* MD interface: Sections. */
16029 /* Estimate the size of a frag before relaxing. Assume everything fits in
16033 md_estimate_size_before_relax (fragS
* fragp
,
16034 segT segtype ATTRIBUTE_UNUSED
)
16040 /* Convert a machine dependent frag. */
16043 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
16045 unsigned long insn
;
16046 unsigned long old_op
;
16054 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16056 old_op
= bfd_get_16(abfd
, buf
);
16057 if (fragp
->fr_symbol
) {
16058 exp
.X_op
= O_symbol
;
16059 exp
.X_add_symbol
= fragp
->fr_symbol
;
16061 exp
.X_op
= O_constant
;
16063 exp
.X_add_number
= fragp
->fr_offset
;
16064 opcode
= fragp
->fr_subtype
;
16067 case T_MNEM_ldr_pc
:
16068 case T_MNEM_ldr_pc2
:
16069 case T_MNEM_ldr_sp
:
16070 case T_MNEM_str_sp
:
16077 if (fragp
->fr_var
== 4)
16079 insn
= THUMB_OP32(opcode
);
16080 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
16082 insn
|= (old_op
& 0x700) << 4;
16086 insn
|= (old_op
& 7) << 12;
16087 insn
|= (old_op
& 0x38) << 13;
16089 insn
|= 0x00000c00;
16090 put_thumb32_insn (buf
, insn
);
16091 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
16095 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
16097 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
16100 if (fragp
->fr_var
== 4)
16102 insn
= THUMB_OP32 (opcode
);
16103 insn
|= (old_op
& 0xf0) << 4;
16104 put_thumb32_insn (buf
, insn
);
16105 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
16109 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16110 exp
.X_add_number
-= 4;
16118 if (fragp
->fr_var
== 4)
16120 int r0off
= (opcode
== T_MNEM_mov
16121 || opcode
== T_MNEM_movs
) ? 0 : 8;
16122 insn
= THUMB_OP32 (opcode
);
16123 insn
= (insn
& 0xe1ffffff) | 0x10000000;
16124 insn
|= (old_op
& 0x700) << r0off
;
16125 put_thumb32_insn (buf
, insn
);
16126 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16130 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
16135 if (fragp
->fr_var
== 4)
16137 insn
= THUMB_OP32(opcode
);
16138 put_thumb32_insn (buf
, insn
);
16139 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
16142 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
16146 if (fragp
->fr_var
== 4)
16148 insn
= THUMB_OP32(opcode
);
16149 insn
|= (old_op
& 0xf00) << 14;
16150 put_thumb32_insn (buf
, insn
);
16151 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
16154 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
16157 case T_MNEM_add_sp
:
16158 case T_MNEM_add_pc
:
16159 case T_MNEM_inc_sp
:
16160 case T_MNEM_dec_sp
:
16161 if (fragp
->fr_var
== 4)
16163 /* ??? Choose between add and addw. */
16164 insn
= THUMB_OP32 (opcode
);
16165 insn
|= (old_op
& 0xf0) << 4;
16166 put_thumb32_insn (buf
, insn
);
16167 if (opcode
== T_MNEM_add_pc
)
16168 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
16170 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16173 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16181 if (fragp
->fr_var
== 4)
16183 insn
= THUMB_OP32 (opcode
);
16184 insn
|= (old_op
& 0xf0) << 4;
16185 insn
|= (old_op
& 0xf) << 16;
16186 put_thumb32_insn (buf
, insn
);
16187 if (insn
& (1 << 20))
16188 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16190 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16193 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16199 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
16201 fixp
->fx_file
= fragp
->fr_file
;
16202 fixp
->fx_line
= fragp
->fr_line
;
16203 fragp
->fr_fix
+= fragp
->fr_var
;
16206 /* Return the size of a relaxable immediate operand instruction.
16207 SHIFT and SIZE specify the form of the allowable immediate. */
16209 relax_immediate (fragS
*fragp
, int size
, int shift
)
16215 /* ??? Should be able to do better than this. */
16216 if (fragp
->fr_symbol
)
16219 low
= (1 << shift
) - 1;
16220 mask
= (1 << (shift
+ size
)) - (1 << shift
);
16221 offset
= fragp
->fr_offset
;
16222 /* Force misaligned offsets to 32-bit variant. */
16225 if (offset
& ~mask
)
16230 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
16233 relax_adr (fragS
*fragp
, asection
*sec
)
16238 /* Assume worst case for symbols not known to be in the same section. */
16239 if (!S_IS_DEFINED(fragp
->fr_symbol
)
16240 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16243 val
= S_GET_VALUE(fragp
->fr_symbol
) + fragp
->fr_offset
;
16244 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16245 addr
= (addr
+ 4) & ~3;
16246 /* Fix the insn as the 4-byte version if the target address is not
16247 sufficiently aligned. This is prevents an infinite loop when two
16248 instructions have contradictory range/alignment requirements. */
16252 if (val
< 0 || val
> 1020)
16257 /* Return the size of a relaxable add/sub immediate instruction. */
16259 relax_addsub (fragS
*fragp
, asection
*sec
)
16264 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16265 op
= bfd_get_16(sec
->owner
, buf
);
16266 if ((op
& 0xf) == ((op
>> 4) & 0xf))
16267 return relax_immediate (fragp
, 8, 0);
16269 return relax_immediate (fragp
, 3, 0);
16273 /* Return the size of a relaxable branch instruction. BITS is the
16274 size of the offset field in the narrow instruction. */
16277 relax_branch (fragS
*fragp
, asection
*sec
, int bits
)
16283 /* Assume worst case for symbols not known to be in the same section. */
16284 if (!S_IS_DEFINED(fragp
->fr_symbol
)
16285 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16288 val
= S_GET_VALUE(fragp
->fr_symbol
) + fragp
->fr_offset
;
16289 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16292 /* Offset is a signed value *2 */
16294 if (val
>= limit
|| val
< -limit
)
16300 /* Relax a machine dependent frag. This returns the amount by which
16301 the current size of the frag should change. */
16304 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
16309 oldsize
= fragp
->fr_var
;
16310 switch (fragp
->fr_subtype
)
16312 case T_MNEM_ldr_pc2
:
16313 newsize
= relax_adr(fragp
, sec
);
16315 case T_MNEM_ldr_pc
:
16316 case T_MNEM_ldr_sp
:
16317 case T_MNEM_str_sp
:
16318 newsize
= relax_immediate(fragp
, 8, 2);
16322 newsize
= relax_immediate(fragp
, 5, 2);
16326 newsize
= relax_immediate(fragp
, 5, 1);
16330 newsize
= relax_immediate(fragp
, 5, 0);
16333 newsize
= relax_adr(fragp
, sec
);
16339 newsize
= relax_immediate(fragp
, 8, 0);
16342 newsize
= relax_branch(fragp
, sec
, 11);
16345 newsize
= relax_branch(fragp
, sec
, 8);
16347 case T_MNEM_add_sp
:
16348 case T_MNEM_add_pc
:
16349 newsize
= relax_immediate (fragp
, 8, 2);
16351 case T_MNEM_inc_sp
:
16352 case T_MNEM_dec_sp
:
16353 newsize
= relax_immediate (fragp
, 7, 2);
16359 newsize
= relax_addsub (fragp
, sec
);
16366 fragp
->fr_var
= -newsize
;
16367 md_convert_frag (sec
->owner
, sec
, fragp
);
16369 return -(newsize
+ oldsize
);
16371 fragp
->fr_var
= newsize
;
16372 return newsize
- oldsize
;
16375 /* Round up a section size to the appropriate boundary. */
16378 md_section_align (segT segment ATTRIBUTE_UNUSED
,
16384 /* Round all sects to multiple of 4. */
16385 return (size
+ 3) & ~3;
16389 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
16390 of an rs_align_code fragment. */
16393 arm_handle_align (fragS
* fragP
)
16395 static char const arm_noop
[4] = { 0x00, 0x00, 0xa0, 0xe1 };
16396 static char const thumb_noop
[2] = { 0xc0, 0x46 };
16397 static char const arm_bigend_noop
[4] = { 0xe1, 0xa0, 0x00, 0x00 };
16398 static char const thumb_bigend_noop
[2] = { 0x46, 0xc0 };
16400 int bytes
, fix
, noop_size
;
16404 if (fragP
->fr_type
!= rs_align_code
)
16407 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
16408 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
16411 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
16412 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
16414 if (fragP
->tc_frag_data
)
16416 if (target_big_endian
)
16417 noop
= thumb_bigend_noop
;
16420 noop_size
= sizeof (thumb_noop
);
16424 if (target_big_endian
)
16425 noop
= arm_bigend_noop
;
16428 noop_size
= sizeof (arm_noop
);
16431 if (bytes
& (noop_size
- 1))
16433 fix
= bytes
& (noop_size
- 1);
16434 memset (p
, 0, fix
);
16439 while (bytes
>= noop_size
)
16441 memcpy (p
, noop
, noop_size
);
16443 bytes
-= noop_size
;
16447 fragP
->fr_fix
+= fix
;
16448 fragP
->fr_var
= noop_size
;
16451 /* Called from md_do_align. Used to create an alignment
16452 frag in a code section. */
16455 arm_frag_align_code (int n
, int max
)
16459 /* We assume that there will never be a requirement
16460 to support alignments greater than 32 bytes. */
16461 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
16462 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
16464 p
= frag_var (rs_align_code
,
16465 MAX_MEM_FOR_RS_ALIGN_CODE
,
16467 (relax_substateT
) max
,
16474 /* Perform target specific initialisation of a frag. */
16477 arm_init_frag (fragS
* fragP
)
16479 /* Record whether this frag is in an ARM or a THUMB area. */
16480 fragP
->tc_frag_data
= thumb_mode
;
16484 /* When we change sections we need to issue a new mapping symbol. */
16487 arm_elf_change_section (void)
16490 segment_info_type
*seginfo
;
16492 /* Link an unlinked unwind index table section to the .text section. */
16493 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
16494 && elf_linked_to_section (now_seg
) == NULL
)
16495 elf_linked_to_section (now_seg
) = text_section
;
16497 if (!SEG_NORMAL (now_seg
))
16500 flags
= bfd_get_section_flags (stdoutput
, now_seg
);
16502 /* We can ignore sections that only contain debug info. */
16503 if ((flags
& SEC_ALLOC
) == 0)
16506 seginfo
= seg_info (now_seg
);
16507 mapstate
= seginfo
->tc_segment_info_data
.mapstate
;
16508 marked_pr_dependency
= seginfo
->tc_segment_info_data
.marked_pr_dependency
;
16512 arm_elf_section_type (const char * str
, size_t len
)
16514 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
16515 return SHT_ARM_EXIDX
;
16520 /* Code to deal with unwinding tables. */
16522 static void add_unwind_adjustsp (offsetT
);
16524 /* Cenerate and deferred unwind frame offset. */
16527 flush_pending_unwind (void)
16531 offset
= unwind
.pending_offset
;
16532 unwind
.pending_offset
= 0;
16534 add_unwind_adjustsp (offset
);
16537 /* Add an opcode to this list for this function. Two-byte opcodes should
16538 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
16542 add_unwind_opcode (valueT op
, int length
)
16544 /* Add any deferred stack adjustment. */
16545 if (unwind
.pending_offset
)
16546 flush_pending_unwind ();
16548 unwind
.sp_restored
= 0;
16550 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
16552 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
16553 if (unwind
.opcodes
)
16554 unwind
.opcodes
= xrealloc (unwind
.opcodes
,
16555 unwind
.opcode_alloc
);
16557 unwind
.opcodes
= xmalloc (unwind
.opcode_alloc
);
16562 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
16564 unwind
.opcode_count
++;
16568 /* Add unwind opcodes to adjust the stack pointer. */
16571 add_unwind_adjustsp (offsetT offset
)
16575 if (offset
> 0x200)
16577 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
16582 /* Long form: 0xb2, uleb128. */
16583 /* This might not fit in a word so add the individual bytes,
16584 remembering the list is built in reverse order. */
16585 o
= (valueT
) ((offset
- 0x204) >> 2);
16587 add_unwind_opcode (0, 1);
16589 /* Calculate the uleb128 encoding of the offset. */
16593 bytes
[n
] = o
& 0x7f;
16599 /* Add the insn. */
16601 add_unwind_opcode (bytes
[n
- 1], 1);
16602 add_unwind_opcode (0xb2, 1);
16604 else if (offset
> 0x100)
16606 /* Two short opcodes. */
16607 add_unwind_opcode (0x3f, 1);
16608 op
= (offset
- 0x104) >> 2;
16609 add_unwind_opcode (op
, 1);
16611 else if (offset
> 0)
16613 /* Short opcode. */
16614 op
= (offset
- 4) >> 2;
16615 add_unwind_opcode (op
, 1);
16617 else if (offset
< 0)
16620 while (offset
> 0x100)
16622 add_unwind_opcode (0x7f, 1);
16625 op
= ((offset
- 4) >> 2) | 0x40;
16626 add_unwind_opcode (op
, 1);
16630 /* Finish the list of unwind opcodes for this function. */
16632 finish_unwind_opcodes (void)
16636 if (unwind
.fp_used
)
16638 /* Adjust sp as necessary. */
16639 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
16640 flush_pending_unwind ();
16642 /* After restoring sp from the frame pointer. */
16643 op
= 0x90 | unwind
.fp_reg
;
16644 add_unwind_opcode (op
, 1);
16647 flush_pending_unwind ();
16651 /* Start an exception table entry. If idx is nonzero this is an index table
16655 start_unwind_section (const segT text_seg
, int idx
)
16657 const char * text_name
;
16658 const char * prefix
;
16659 const char * prefix_once
;
16660 const char * group_name
;
16664 size_t sec_name_len
;
16671 prefix
= ELF_STRING_ARM_unwind
;
16672 prefix_once
= ELF_STRING_ARM_unwind_once
;
16673 type
= SHT_ARM_EXIDX
;
16677 prefix
= ELF_STRING_ARM_unwind_info
;
16678 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
16679 type
= SHT_PROGBITS
;
16682 text_name
= segment_name (text_seg
);
16683 if (streq (text_name
, ".text"))
16686 if (strncmp (text_name
, ".gnu.linkonce.t.",
16687 strlen (".gnu.linkonce.t.")) == 0)
16689 prefix
= prefix_once
;
16690 text_name
+= strlen (".gnu.linkonce.t.");
16693 prefix_len
= strlen (prefix
);
16694 text_len
= strlen (text_name
);
16695 sec_name_len
= prefix_len
+ text_len
;
16696 sec_name
= xmalloc (sec_name_len
+ 1);
16697 memcpy (sec_name
, prefix
, prefix_len
);
16698 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
16699 sec_name
[prefix_len
+ text_len
] = '\0';
16705 /* Handle COMDAT group. */
16706 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
16708 group_name
= elf_group_name (text_seg
);
16709 if (group_name
== NULL
)
16711 as_bad ("Group section `%s' has no group signature",
16712 segment_name (text_seg
));
16713 ignore_rest_of_line ();
16716 flags
|= SHF_GROUP
;
16720 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
16722 /* Set the setion link for index tables. */
16724 elf_linked_to_section (now_seg
) = text_seg
;
16728 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
16729 personality routine data. Returns zero, or the index table value for
16730 and inline entry. */
16733 create_unwind_entry (int have_data
)
16738 /* The current word of data. */
16740 /* The number of bytes left in this word. */
16743 finish_unwind_opcodes ();
16745 /* Remember the current text section. */
16746 unwind
.saved_seg
= now_seg
;
16747 unwind
.saved_subseg
= now_subseg
;
16749 start_unwind_section (now_seg
, 0);
16751 if (unwind
.personality_routine
== NULL
)
16753 if (unwind
.personality_index
== -2)
16756 as_bad (_("handerdata in cantunwind frame"));
16757 return 1; /* EXIDX_CANTUNWIND. */
16760 /* Use a default personality routine if none is specified. */
16761 if (unwind
.personality_index
== -1)
16763 if (unwind
.opcode_count
> 3)
16764 unwind
.personality_index
= 1;
16766 unwind
.personality_index
= 0;
16769 /* Space for the personality routine entry. */
16770 if (unwind
.personality_index
== 0)
16772 if (unwind
.opcode_count
> 3)
16773 as_bad (_("too many unwind opcodes for personality routine 0"));
16777 /* All the data is inline in the index table. */
16780 while (unwind
.opcode_count
> 0)
16782 unwind
.opcode_count
--;
16783 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
16787 /* Pad with "finish" opcodes. */
16789 data
= (data
<< 8) | 0xb0;
16796 /* We get two opcodes "free" in the first word. */
16797 size
= unwind
.opcode_count
- 2;
16800 /* An extra byte is required for the opcode count. */
16801 size
= unwind
.opcode_count
+ 1;
16803 size
= (size
+ 3) >> 2;
16805 as_bad (_("too many unwind opcodes"));
16807 frag_align (2, 0, 0);
16808 record_alignment (now_seg
, 2);
16809 unwind
.table_entry
= expr_build_dot ();
16811 /* Allocate the table entry. */
16812 ptr
= frag_more ((size
<< 2) + 4);
16813 where
= frag_now_fix () - ((size
<< 2) + 4);
16815 switch (unwind
.personality_index
)
16818 /* ??? Should this be a PLT generating relocation? */
16819 /* Custom personality routine. */
16820 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
16821 BFD_RELOC_ARM_PREL31
);
16826 /* Set the first byte to the number of additional words. */
16831 /* ABI defined personality routines. */
16833 /* Three opcodes bytes are packed into the first word. */
16840 /* The size and first two opcode bytes go in the first word. */
16841 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
16846 /* Should never happen. */
16850 /* Pack the opcodes into words (MSB first), reversing the list at the same
16852 while (unwind
.opcode_count
> 0)
16856 md_number_to_chars (ptr
, data
, 4);
16861 unwind
.opcode_count
--;
16863 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
16866 /* Finish off the last word. */
16869 /* Pad with "finish" opcodes. */
16871 data
= (data
<< 8) | 0xb0;
16873 md_number_to_chars (ptr
, data
, 4);
16878 /* Add an empty descriptor if there is no user-specified data. */
16879 ptr
= frag_more (4);
16880 md_number_to_chars (ptr
, 0, 4);
16886 /* Convert REGNAME to a DWARF-2 register number. */
16889 tc_arm_regname_to_dw2regnum (char *regname
)
16891 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
16899 /* Initialize the DWARF-2 unwind information for this procedure. */
16902 tc_arm_frame_initial_instructions (void)
16904 cfi_add_CFA_def_cfa (REG_SP
, 0);
16906 #endif /* OBJ_ELF */
16909 /* MD interface: Symbol and relocation handling. */
16911 /* Return the address within the segment that a PC-relative fixup is
16912 relative to. For ARM, PC-relative fixups applied to instructions
16913 are generally relative to the location of the fixup plus 8 bytes.
16914 Thumb branches are offset by 4, and Thumb loads relative to PC
16915 require special handling. */
16918 md_pcrel_from_section (fixS
* fixP
, segT seg
)
16920 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
16922 /* If this is pc-relative and we are going to emit a relocation
16923 then we just want to put out any pipeline compensation that the linker
16924 will need. Otherwise we want to use the calculated base.
16925 For WinCE we skip the bias for externals as well, since this
16926 is how the MS ARM-CE assembler behaves and we want to be compatible. */
16928 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
16929 || (arm_force_relocation (fixP
)
16931 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
16936 switch (fixP
->fx_r_type
)
16938 /* PC relative addressing on the Thumb is slightly odd as the
16939 bottom two bits of the PC are forced to zero for the
16940 calculation. This happens *after* application of the
16941 pipeline offset. However, Thumb adrl already adjusts for
16942 this, so we need not do it again. */
16943 case BFD_RELOC_ARM_THUMB_ADD
:
16946 case BFD_RELOC_ARM_THUMB_OFFSET
:
16947 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
16948 case BFD_RELOC_ARM_T32_ADD_PC12
:
16949 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
16950 return (base
+ 4) & ~3;
16952 /* Thumb branches are simply offset by +4. */
16953 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
16954 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
16955 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
16956 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
16957 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
16958 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
16959 case BFD_RELOC_THUMB_PCREL_BLX
:
16962 /* ARM mode branches are offset by +8. However, the Windows CE
16963 loader expects the relocation not to take this into account. */
16964 case BFD_RELOC_ARM_PCREL_BRANCH
:
16965 case BFD_RELOC_ARM_PCREL_CALL
:
16966 case BFD_RELOC_ARM_PCREL_JUMP
:
16967 case BFD_RELOC_ARM_PCREL_BLX
:
16968 case BFD_RELOC_ARM_PLT32
:
16970 /* When handling fixups immediately, because we have already
16971 discovered the value of a symbol, or the address of the frag involved
16972 we must account for the offset by +8, as the OS loader will never see the reloc.
16973 see fixup_segment() in write.c
16974 The S_IS_EXTERNAL test handles the case of global symbols.
16975 Those need the calculated base, not just the pipe compensation the linker will need. */
16977 && fixP
->fx_addsy
!= NULL
16978 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
16979 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
16986 /* ARM mode loads relative to PC are also offset by +8. Unlike
16987 branches, the Windows CE loader *does* expect the relocation
16988 to take this into account. */
16989 case BFD_RELOC_ARM_OFFSET_IMM
:
16990 case BFD_RELOC_ARM_OFFSET_IMM8
:
16991 case BFD_RELOC_ARM_HWLITERAL
:
16992 case BFD_RELOC_ARM_LITERAL
:
16993 case BFD_RELOC_ARM_CP_OFF_IMM
:
16997 /* Other PC-relative relocations are un-offset. */
17003 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
17004 Otherwise we have no need to default values of symbols. */
17007 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
17010 if (name
[0] == '_' && name
[1] == 'G'
17011 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
17015 if (symbol_find (name
))
17016 as_bad ("GOT already in the symbol table");
17018 GOT_symbol
= symbol_new (name
, undefined_section
,
17019 (valueT
) 0, & zero_address_frag
);
17029 /* Subroutine of md_apply_fix. Check to see if an immediate can be
17030 computed as two separate immediate values, added together. We
17031 already know that this value cannot be computed by just one ARM
17034 static unsigned int
17035 validate_immediate_twopart (unsigned int val
,
17036 unsigned int * highpart
)
17041 for (i
= 0; i
< 32; i
+= 2)
17042 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
17048 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
17050 else if (a
& 0xff0000)
17052 if (a
& 0xff000000)
17054 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
17058 assert (a
& 0xff000000);
17059 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
17062 return (a
& 0xff) | (i
<< 7);
17069 validate_offset_imm (unsigned int val
, int hwse
)
17071 if ((hwse
&& val
> 255) || val
> 4095)
17076 /* Subroutine of md_apply_fix. Do those data_ops which can take a
17077 negative immediate constant by altering the instruction. A bit of
17082 by inverting the second operand, and
17085 by negating the second operand. */
17088 negate_data_op (unsigned long * instruction
,
17089 unsigned long value
)
17092 unsigned long negated
, inverted
;
17094 negated
= encode_arm_immediate (-value
);
17095 inverted
= encode_arm_immediate (~value
);
17097 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
17100 /* First negates. */
17101 case OPCODE_SUB
: /* ADD <-> SUB */
17102 new_inst
= OPCODE_ADD
;
17107 new_inst
= OPCODE_SUB
;
17111 case OPCODE_CMP
: /* CMP <-> CMN */
17112 new_inst
= OPCODE_CMN
;
17117 new_inst
= OPCODE_CMP
;
17121 /* Now Inverted ops. */
17122 case OPCODE_MOV
: /* MOV <-> MVN */
17123 new_inst
= OPCODE_MVN
;
17128 new_inst
= OPCODE_MOV
;
17132 case OPCODE_AND
: /* AND <-> BIC */
17133 new_inst
= OPCODE_BIC
;
17138 new_inst
= OPCODE_AND
;
17142 case OPCODE_ADC
: /* ADC <-> SBC */
17143 new_inst
= OPCODE_SBC
;
17148 new_inst
= OPCODE_ADC
;
17152 /* We cannot do anything. */
17157 if (value
== (unsigned) FAIL
)
17160 *instruction
&= OPCODE_MASK
;
17161 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
17165 /* Like negate_data_op, but for Thumb-2. */
17167 static unsigned int
17168 thumb32_negate_data_op (offsetT
*instruction
, offsetT value
)
17172 offsetT negated
, inverted
;
17174 negated
= encode_thumb32_immediate (-value
);
17175 inverted
= encode_thumb32_immediate (~value
);
17177 rd
= (*instruction
>> 8) & 0xf;
17178 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
17181 /* ADD <-> SUB. Includes CMP <-> CMN. */
17182 case T2_OPCODE_SUB
:
17183 new_inst
= T2_OPCODE_ADD
;
17187 case T2_OPCODE_ADD
:
17188 new_inst
= T2_OPCODE_SUB
;
17192 /* ORR <-> ORN. Includes MOV <-> MVN. */
17193 case T2_OPCODE_ORR
:
17194 new_inst
= T2_OPCODE_ORN
;
17198 case T2_OPCODE_ORN
:
17199 new_inst
= T2_OPCODE_ORR
;
17203 /* AND <-> BIC. TST has no inverted equivalent. */
17204 case T2_OPCODE_AND
:
17205 new_inst
= T2_OPCODE_BIC
;
17212 case T2_OPCODE_BIC
:
17213 new_inst
= T2_OPCODE_AND
;
17218 case T2_OPCODE_ADC
:
17219 new_inst
= T2_OPCODE_SBC
;
17223 case T2_OPCODE_SBC
:
17224 new_inst
= T2_OPCODE_ADC
;
17228 /* We cannot do anything. */
17236 *instruction
&= T2_OPCODE_MASK
;
17237 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
17241 /* Read a 32-bit thumb instruction from buf. */
17242 static unsigned long
17243 get_thumb32_insn (char * buf
)
17245 unsigned long insn
;
17246 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
17247 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17253 /* We usually want to set the low bit on the address of thumb function
17254 symbols. In particular .word foo - . should have the low bit set.
17255 Generic code tries to fold the difference of two symbols to
17256 a constant. Prevent this and force a relocation when the first symbols
17257 is a thumb function. */
17259 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
17261 if (op
== O_subtract
17262 && l
->X_op
== O_symbol
17263 && r
->X_op
== O_symbol
17264 && THUMB_IS_FUNC (l
->X_add_symbol
))
17266 l
->X_op
= O_subtract
;
17267 l
->X_op_symbol
= r
->X_add_symbol
;
17268 l
->X_add_number
-= r
->X_add_number
;
17271 /* Process as normal. */
17276 md_apply_fix (fixS
* fixP
,
17280 offsetT value
= * valP
;
17282 unsigned int newimm
;
17283 unsigned long temp
;
17285 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
17287 assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
17289 /* Note whether this will delete the relocation. */
17291 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
17294 /* On a 64-bit host, silently truncate 'value' to 32 bits for
17295 consistency with the behavior on 32-bit hosts. Remember value
17297 value
&= 0xffffffff;
17298 value
^= 0x80000000;
17299 value
-= 0x80000000;
17302 fixP
->fx_addnumber
= value
;
17304 /* Same treatment for fixP->fx_offset. */
17305 fixP
->fx_offset
&= 0xffffffff;
17306 fixP
->fx_offset
^= 0x80000000;
17307 fixP
->fx_offset
-= 0x80000000;
17309 switch (fixP
->fx_r_type
)
17311 case BFD_RELOC_NONE
:
17312 /* This will need to go in the object file. */
17316 case BFD_RELOC_ARM_IMMEDIATE
:
17317 /* We claim that this fixup has been processed here,
17318 even if in fact we generate an error because we do
17319 not have a reloc for it, so tc_gen_reloc will reject it. */
17323 && ! S_IS_DEFINED (fixP
->fx_addsy
))
17325 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17326 _("undefined symbol %s used as an immediate value"),
17327 S_GET_NAME (fixP
->fx_addsy
));
17331 newimm
= encode_arm_immediate (value
);
17332 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17334 /* If the instruction will fail, see if we can fix things up by
17335 changing the opcode. */
17336 if (newimm
== (unsigned int) FAIL
17337 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
17339 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17340 _("invalid constant (%lx) after fixup"),
17341 (unsigned long) value
);
17345 newimm
|= (temp
& 0xfffff000);
17346 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
17349 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
17351 unsigned int highpart
= 0;
17352 unsigned int newinsn
= 0xe1a00000; /* nop. */
17354 newimm
= encode_arm_immediate (value
);
17355 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17357 /* If the instruction will fail, see if we can fix things up by
17358 changing the opcode. */
17359 if (newimm
== (unsigned int) FAIL
17360 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
17362 /* No ? OK - try using two ADD instructions to generate
17364 newimm
= validate_immediate_twopart (value
, & highpart
);
17366 /* Yes - then make sure that the second instruction is
17368 if (newimm
!= (unsigned int) FAIL
)
17370 /* Still No ? Try using a negated value. */
17371 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
17372 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
17373 /* Otherwise - give up. */
17376 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17377 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
17382 /* Replace the first operand in the 2nd instruction (which
17383 is the PC) with the destination register. We have
17384 already added in the PC in the first instruction and we
17385 do not want to do it again. */
17386 newinsn
&= ~ 0xf0000;
17387 newinsn
|= ((newinsn
& 0x0f000) << 4);
17390 newimm
|= (temp
& 0xfffff000);
17391 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
17393 highpart
|= (newinsn
& 0xfffff000);
17394 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
17398 case BFD_RELOC_ARM_OFFSET_IMM
:
17399 if (!fixP
->fx_done
&& seg
->use_rela_p
)
17402 case BFD_RELOC_ARM_LITERAL
:
17408 if (validate_offset_imm (value
, 0) == FAIL
)
17410 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
17411 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17412 _("invalid literal constant: pool needs to be closer"));
17414 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17415 _("bad immediate value for offset (%ld)"),
17420 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17421 newval
&= 0xff7ff000;
17422 newval
|= value
| (sign
? INDEX_UP
: 0);
17423 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17426 case BFD_RELOC_ARM_OFFSET_IMM8
:
17427 case BFD_RELOC_ARM_HWLITERAL
:
17433 if (validate_offset_imm (value
, 1) == FAIL
)
17435 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
17436 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17437 _("invalid literal constant: pool needs to be closer"));
17439 as_bad (_("bad immediate value for half-word offset (%ld)"),
17444 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17445 newval
&= 0xff7ff0f0;
17446 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
17447 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17450 case BFD_RELOC_ARM_T32_OFFSET_U8
:
17451 if (value
< 0 || value
> 1020 || value
% 4 != 0)
17452 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17453 _("bad immediate value for offset (%ld)"), (long) value
);
17456 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
17458 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
17461 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
17462 /* This is a complicated relocation used for all varieties of Thumb32
17463 load/store instruction with immediate offset:
17465 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
17466 *4, optional writeback(W)
17467 (doubleword load/store)
17469 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
17470 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
17471 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
17472 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
17473 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
17475 Uppercase letters indicate bits that are already encoded at
17476 this point. Lowercase letters are our problem. For the
17477 second block of instructions, the secondary opcode nybble
17478 (bits 8..11) is present, and bit 23 is zero, even if this is
17479 a PC-relative operation. */
17480 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17482 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
17484 if ((newval
& 0xf0000000) == 0xe0000000)
17486 /* Doubleword load/store: 8-bit offset, scaled by 4. */
17488 newval
|= (1 << 23);
17491 if (value
% 4 != 0)
17493 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17494 _("offset not a multiple of 4"));
17500 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17501 _("offset out of range"));
17506 else if ((newval
& 0x000f0000) == 0x000f0000)
17508 /* PC-relative, 12-bit offset. */
17510 newval
|= (1 << 23);
17515 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17516 _("offset out of range"));
17521 else if ((newval
& 0x00000100) == 0x00000100)
17523 /* Writeback: 8-bit, +/- offset. */
17525 newval
|= (1 << 9);
17530 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17531 _("offset out of range"));
17536 else if ((newval
& 0x00000f00) == 0x00000e00)
17538 /* T-instruction: positive 8-bit offset. */
17539 if (value
< 0 || value
> 0xff)
17541 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17542 _("offset out of range"));
17550 /* Positive 12-bit or negative 8-bit offset. */
17554 newval
|= (1 << 23);
17564 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17565 _("offset out of range"));
17572 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
17573 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
17576 case BFD_RELOC_ARM_SHIFT_IMM
:
17577 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17578 if (((unsigned long) value
) > 32
17580 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
17582 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17583 _("shift expression is too large"));
17588 /* Shifts of zero must be done as lsl. */
17590 else if (value
== 32)
17592 newval
&= 0xfffff07f;
17593 newval
|= (value
& 0x1f) << 7;
17594 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17597 case BFD_RELOC_ARM_T32_IMMEDIATE
:
17598 case BFD_RELOC_ARM_T32_ADD_IMM
:
17599 case BFD_RELOC_ARM_T32_IMM12
:
17600 case BFD_RELOC_ARM_T32_ADD_PC12
:
17601 /* We claim that this fixup has been processed here,
17602 even if in fact we generate an error because we do
17603 not have a reloc for it, so tc_gen_reloc will reject it. */
17607 && ! S_IS_DEFINED (fixP
->fx_addsy
))
17609 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17610 _("undefined symbol %s used as an immediate value"),
17611 S_GET_NAME (fixP
->fx_addsy
));
17615 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17617 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
17620 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
17621 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
17623 newimm
= encode_thumb32_immediate (value
);
17624 if (newimm
== (unsigned int) FAIL
)
17625 newimm
= thumb32_negate_data_op (&newval
, value
);
17627 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
17628 && newimm
== (unsigned int) FAIL
)
17630 /* Turn add/sum into addw/subw. */
17631 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
17632 newval
= (newval
& 0xfeffffff) | 0x02000000;
17634 /* 12 bit immediate for addw/subw. */
17638 newval
^= 0x00a00000;
17641 newimm
= (unsigned int) FAIL
;
17646 if (newimm
== (unsigned int)FAIL
)
17648 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17649 _("invalid constant (%lx) after fixup"),
17650 (unsigned long) value
);
17654 newval
|= (newimm
& 0x800) << 15;
17655 newval
|= (newimm
& 0x700) << 4;
17656 newval
|= (newimm
& 0x0ff);
17658 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
17659 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
17662 case BFD_RELOC_ARM_SMC
:
17663 if (((unsigned long) value
) > 0xffff)
17664 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17665 _("invalid smc expression"));
17666 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17667 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
17668 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17671 case BFD_RELOC_ARM_SWI
:
17672 if (fixP
->tc_fix_data
!= 0)
17674 if (((unsigned long) value
) > 0xff)
17675 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17676 _("invalid swi expression"));
17677 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17679 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17683 if (((unsigned long) value
) > 0x00ffffff)
17684 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17685 _("invalid swi expression"));
17686 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17688 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17692 case BFD_RELOC_ARM_MULTI
:
17693 if (((unsigned long) value
) > 0xffff)
17694 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17695 _("invalid expression in load/store multiple"));
17696 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
17697 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17701 case BFD_RELOC_ARM_PCREL_CALL
:
17702 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17703 if ((newval
& 0xf0000000) == 0xf0000000)
17707 goto arm_branch_common
;
17709 case BFD_RELOC_ARM_PCREL_JUMP
:
17710 case BFD_RELOC_ARM_PLT32
:
17712 case BFD_RELOC_ARM_PCREL_BRANCH
:
17714 goto arm_branch_common
;
17716 case BFD_RELOC_ARM_PCREL_BLX
:
17719 /* We are going to store value (shifted right by two) in the
17720 instruction, in a 24 bit, signed field. Bits 26 through 32 either
17721 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
17722 also be be clear. */
17724 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17725 _("misaligned branch destination"));
17726 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
17727 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
17728 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17729 _("branch out of range"));
17731 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17733 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17734 newval
|= (value
>> 2) & 0x00ffffff;
17735 /* Set the H bit on BLX instructions. */
17739 newval
|= 0x01000000;
17741 newval
&= ~0x01000000;
17743 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17747 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CZB */
17748 /* CZB can only branch forward. */
17750 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17751 _("branch out of range"));
17753 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17755 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17756 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
17757 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17761 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
17762 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
17763 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17764 _("branch out of range"));
17766 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17768 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17769 newval
|= (value
& 0x1ff) >> 1;
17770 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17774 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
17775 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
17776 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17777 _("branch out of range"));
17779 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17781 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17782 newval
|= (value
& 0xfff) >> 1;
17783 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17787 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
17788 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
17789 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17790 _("conditional branch out of range"));
17792 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17795 addressT S
, J1
, J2
, lo
, hi
;
17797 S
= (value
& 0x00100000) >> 20;
17798 J2
= (value
& 0x00080000) >> 19;
17799 J1
= (value
& 0x00040000) >> 18;
17800 hi
= (value
& 0x0003f000) >> 12;
17801 lo
= (value
& 0x00000ffe) >> 1;
17803 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17804 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17805 newval
|= (S
<< 10) | hi
;
17806 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
17807 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17808 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
17812 case BFD_RELOC_THUMB_PCREL_BLX
:
17813 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
17814 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
17815 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17816 _("branch out of range"));
17818 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
17819 /* For a BLX instruction, make sure that the relocation is rounded up
17820 to a word boundary. This follows the semantics of the instruction
17821 which specifies that bit 1 of the target address will come from bit
17822 1 of the base address. */
17823 value
= (value
+ 1) & ~ 1;
17825 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17829 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17830 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17831 newval
|= (value
& 0x7fffff) >> 12;
17832 newval2
|= (value
& 0xfff) >> 1;
17833 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17834 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
17838 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
17839 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
17840 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17841 _("branch out of range"));
17843 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17846 addressT S
, I1
, I2
, lo
, hi
;
17848 S
= (value
& 0x01000000) >> 24;
17849 I1
= (value
& 0x00800000) >> 23;
17850 I2
= (value
& 0x00400000) >> 22;
17851 hi
= (value
& 0x003ff000) >> 12;
17852 lo
= (value
& 0x00000ffe) >> 1;
17857 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17858 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17859 newval
|= (S
<< 10) | hi
;
17860 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
17861 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17862 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
17867 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17868 md_number_to_chars (buf
, value
, 1);
17872 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17873 md_number_to_chars (buf
, value
, 2);
17877 case BFD_RELOC_ARM_TLS_GD32
:
17878 case BFD_RELOC_ARM_TLS_LE32
:
17879 case BFD_RELOC_ARM_TLS_IE32
:
17880 case BFD_RELOC_ARM_TLS_LDM32
:
17881 case BFD_RELOC_ARM_TLS_LDO32
:
17882 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
17885 case BFD_RELOC_ARM_GOT32
:
17886 case BFD_RELOC_ARM_GOTOFF
:
17887 case BFD_RELOC_ARM_TARGET2
:
17888 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17889 md_number_to_chars (buf
, 0, 4);
17893 case BFD_RELOC_RVA
:
17895 case BFD_RELOC_ARM_TARGET1
:
17896 case BFD_RELOC_ARM_ROSEGREL32
:
17897 case BFD_RELOC_ARM_SBREL32
:
17898 case BFD_RELOC_32_PCREL
:
17899 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17901 /* For WinCE we only do this for pcrel fixups. */
17902 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
17904 md_number_to_chars (buf
, value
, 4);
17908 case BFD_RELOC_ARM_PREL31
:
17909 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17911 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
17912 if ((value
^ (value
>> 1)) & 0x40000000)
17914 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17915 _("rel31 relocation overflow"));
17917 newval
|= value
& 0x7fffffff;
17918 md_number_to_chars (buf
, newval
, 4);
17923 case BFD_RELOC_ARM_CP_OFF_IMM
:
17924 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
17925 if (value
< -1023 || value
> 1023 || (value
& 3))
17926 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17927 _("co-processor offset out of range"));
17932 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
17933 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
17934 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17936 newval
= get_thumb32_insn (buf
);
17937 newval
&= 0xff7fff00;
17938 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
17940 newval
&= ~WRITE_BACK
;
17941 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
17942 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
17943 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17945 put_thumb32_insn (buf
, newval
);
17948 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
17949 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
17950 if (value
< -255 || value
> 255)
17951 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17952 _("co-processor offset out of range"));
17954 goto cp_off_common
;
17956 case BFD_RELOC_ARM_THUMB_OFFSET
:
17957 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17958 /* Exactly what ranges, and where the offset is inserted depends
17959 on the type of instruction, we can establish this from the
17961 switch (newval
>> 12)
17963 case 4: /* PC load. */
17964 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
17965 forced to zero for these loads; md_pcrel_from has already
17966 compensated for this. */
17968 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17969 _("invalid offset, target not word aligned (0x%08lX)"),
17970 (((unsigned long) fixP
->fx_frag
->fr_address
17971 + (unsigned long) fixP
->fx_where
) & ~3)
17972 + (unsigned long) value
);
17974 if (value
& ~0x3fc)
17975 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17976 _("invalid offset, value too big (0x%08lX)"),
17979 newval
|= value
>> 2;
17982 case 9: /* SP load/store. */
17983 if (value
& ~0x3fc)
17984 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17985 _("invalid offset, value too big (0x%08lX)"),
17987 newval
|= value
>> 2;
17990 case 6: /* Word load/store. */
17992 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17993 _("invalid offset, value too big (0x%08lX)"),
17995 newval
|= value
<< 4; /* 6 - 2. */
17998 case 7: /* Byte load/store. */
18000 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18001 _("invalid offset, value too big (0x%08lX)"),
18003 newval
|= value
<< 6;
18006 case 8: /* Halfword load/store. */
18008 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18009 _("invalid offset, value too big (0x%08lX)"),
18011 newval
|= value
<< 5; /* 6 - 1. */
18015 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18016 "Unable to process relocation for thumb opcode: %lx",
18017 (unsigned long) newval
);
18020 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18023 case BFD_RELOC_ARM_THUMB_ADD
:
18024 /* This is a complicated relocation, since we use it for all of
18025 the following immediate relocations:
18029 9bit ADD/SUB SP word-aligned
18030 10bit ADD PC/SP word-aligned
18032 The type of instruction being processed is encoded in the
18039 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18041 int rd
= (newval
>> 4) & 0xf;
18042 int rs
= newval
& 0xf;
18043 int subtract
= !!(newval
& 0x8000);
18045 /* Check for HI regs, only very restricted cases allowed:
18046 Adjusting SP, and using PC or SP to get an address. */
18047 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
18048 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
18049 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18050 _("invalid Hi register with immediate"));
18052 /* If value is negative, choose the opposite instruction. */
18056 subtract
= !subtract
;
18058 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18059 _("immediate value out of range"));
18064 if (value
& ~0x1fc)
18065 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18066 _("invalid immediate for stack address calculation"));
18067 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
18068 newval
|= value
>> 2;
18070 else if (rs
== REG_PC
|| rs
== REG_SP
)
18072 if (subtract
|| value
& ~0x3fc)
18073 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18074 _("invalid immediate for address calculation (value = 0x%08lX)"),
18075 (unsigned long) value
);
18076 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
18078 newval
|= value
>> 2;
18083 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18084 _("immediate value out of range"));
18085 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
18086 newval
|= (rd
<< 8) | value
;
18091 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18092 _("immediate value out of range"));
18093 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
18094 newval
|= rd
| (rs
<< 3) | (value
<< 6);
18097 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18100 case BFD_RELOC_ARM_THUMB_IMM
:
18101 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18102 if (value
< 0 || value
> 255)
18103 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18104 _("invalid immediate: %ld is too large"),
18107 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18110 case BFD_RELOC_ARM_THUMB_SHIFT
:
18111 /* 5bit shift value (0..32). LSL cannot take 32. */
18112 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
18113 temp
= newval
& 0xf800;
18114 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
18115 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18116 _("invalid shift value: %ld"), (long) value
);
18117 /* Shifts of zero must be encoded as LSL. */
18119 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
18120 /* Shifts of 32 are encoded as zero. */
18121 else if (value
== 32)
18123 newval
|= value
<< 6;
18124 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18127 case BFD_RELOC_VTABLE_INHERIT
:
18128 case BFD_RELOC_VTABLE_ENTRY
:
18132 case BFD_RELOC_ARM_MOVW
:
18133 case BFD_RELOC_ARM_MOVT
:
18134 case BFD_RELOC_ARM_THUMB_MOVW
:
18135 case BFD_RELOC_ARM_THUMB_MOVT
:
18136 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18138 /* REL format relocations are limited to a 16-bit addend. */
18139 if (!fixP
->fx_done
)
18141 if (value
< -0x1000 || value
> 0xffff)
18142 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18143 _("offset too big"));
18145 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
18146 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18151 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
18152 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18154 newval
= get_thumb32_insn (buf
);
18155 newval
&= 0xfbf08f00;
18156 newval
|= (value
& 0xf000) << 4;
18157 newval
|= (value
& 0x0800) << 15;
18158 newval
|= (value
& 0x0700) << 4;
18159 newval
|= (value
& 0x00ff);
18160 put_thumb32_insn (buf
, newval
);
18164 newval
= md_chars_to_number (buf
, 4);
18165 newval
&= 0xfff0f000;
18166 newval
|= value
& 0x0fff;
18167 newval
|= (value
& 0xf000) << 4;
18168 md_number_to_chars (buf
, newval
, 4);
18173 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
18174 case BFD_RELOC_ARM_ALU_PC_G0
:
18175 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
18176 case BFD_RELOC_ARM_ALU_PC_G1
:
18177 case BFD_RELOC_ARM_ALU_PC_G2
:
18178 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
18179 case BFD_RELOC_ARM_ALU_SB_G0
:
18180 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
18181 case BFD_RELOC_ARM_ALU_SB_G1
:
18182 case BFD_RELOC_ARM_ALU_SB_G2
:
18183 assert (!fixP
->fx_done
);
18184 if (!seg
->use_rela_p
)
18187 bfd_vma encoded_addend
;
18188 bfd_vma addend_abs
= abs (value
);
18190 /* Check that the absolute value of the addend can be
18191 expressed as an 8-bit constant plus a rotation. */
18192 encoded_addend
= encode_arm_immediate (addend_abs
);
18193 if (encoded_addend
== (unsigned int) FAIL
)
18194 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18195 _("the offset 0x%08lX is not representable"),
18198 /* Extract the instruction. */
18199 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18201 /* If the addend is positive, use an ADD instruction.
18202 Otherwise use a SUB. Take care not to destroy the S bit. */
18203 insn
&= 0xff1fffff;
18209 /* Place the encoded addend into the first 12 bits of the
18211 insn
&= 0xfffff000;
18212 insn
|= encoded_addend
;
18214 /* Update the instruction. */
18215 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18219 case BFD_RELOC_ARM_LDR_PC_G0
:
18220 case BFD_RELOC_ARM_LDR_PC_G1
:
18221 case BFD_RELOC_ARM_LDR_PC_G2
:
18222 case BFD_RELOC_ARM_LDR_SB_G0
:
18223 case BFD_RELOC_ARM_LDR_SB_G1
:
18224 case BFD_RELOC_ARM_LDR_SB_G2
:
18225 assert (!fixP
->fx_done
);
18226 if (!seg
->use_rela_p
)
18229 bfd_vma addend_abs
= abs (value
);
18231 /* Check that the absolute value of the addend can be
18232 encoded in 12 bits. */
18233 if (addend_abs
>= 0x1000)
18234 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18235 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
18238 /* Extract the instruction. */
18239 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18241 /* If the addend is negative, clear bit 23 of the instruction.
18242 Otherwise set it. */
18244 insn
&= ~(1 << 23);
18248 /* Place the absolute value of the addend into the first 12 bits
18249 of the instruction. */
18250 insn
&= 0xfffff000;
18251 insn
|= addend_abs
;
18253 /* Update the instruction. */
18254 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18258 case BFD_RELOC_ARM_LDRS_PC_G0
:
18259 case BFD_RELOC_ARM_LDRS_PC_G1
:
18260 case BFD_RELOC_ARM_LDRS_PC_G2
:
18261 case BFD_RELOC_ARM_LDRS_SB_G0
:
18262 case BFD_RELOC_ARM_LDRS_SB_G1
:
18263 case BFD_RELOC_ARM_LDRS_SB_G2
:
18264 assert (!fixP
->fx_done
);
18265 if (!seg
->use_rela_p
)
18268 bfd_vma addend_abs
= abs (value
);
18270 /* Check that the absolute value of the addend can be
18271 encoded in 8 bits. */
18272 if (addend_abs
>= 0x100)
18273 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18274 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
18277 /* Extract the instruction. */
18278 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18280 /* If the addend is negative, clear bit 23 of the instruction.
18281 Otherwise set it. */
18283 insn
&= ~(1 << 23);
18287 /* Place the first four bits of the absolute value of the addend
18288 into the first 4 bits of the instruction, and the remaining
18289 four into bits 8 .. 11. */
18290 insn
&= 0xfffff0f0;
18291 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
18293 /* Update the instruction. */
18294 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18298 case BFD_RELOC_ARM_LDC_PC_G0
:
18299 case BFD_RELOC_ARM_LDC_PC_G1
:
18300 case BFD_RELOC_ARM_LDC_PC_G2
:
18301 case BFD_RELOC_ARM_LDC_SB_G0
:
18302 case BFD_RELOC_ARM_LDC_SB_G1
:
18303 case BFD_RELOC_ARM_LDC_SB_G2
:
18304 assert (!fixP
->fx_done
);
18305 if (!seg
->use_rela_p
)
18308 bfd_vma addend_abs
= abs (value
);
18310 /* Check that the absolute value of the addend is a multiple of
18311 four and, when divided by four, fits in 8 bits. */
18312 if (addend_abs
& 0x3)
18313 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18314 _("bad offset 0x%08lX (must be word-aligned)"),
18317 if ((addend_abs
>> 2) > 0xff)
18318 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18319 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
18322 /* Extract the instruction. */
18323 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18325 /* If the addend is negative, clear bit 23 of the instruction.
18326 Otherwise set it. */
18328 insn
&= ~(1 << 23);
18332 /* Place the addend (divided by four) into the first eight
18333 bits of the instruction. */
18334 insn
&= 0xfffffff0;
18335 insn
|= addend_abs
>> 2;
18337 /* Update the instruction. */
18338 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18342 case BFD_RELOC_UNUSED
:
18344 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18345 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
18349 /* Translate internal representation of relocation info to BFD target
18353 tc_gen_reloc (asection
*section
, fixS
*fixp
)
18356 bfd_reloc_code_real_type code
;
18358 reloc
= xmalloc (sizeof (arelent
));
18360 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
18361 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18362 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18364 if (fixp
->fx_pcrel
)
18366 if (section
->use_rela_p
)
18367 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
18369 fixp
->fx_offset
= reloc
->address
;
18371 reloc
->addend
= fixp
->fx_offset
;
18373 switch (fixp
->fx_r_type
)
18376 if (fixp
->fx_pcrel
)
18378 code
= BFD_RELOC_8_PCREL
;
18383 if (fixp
->fx_pcrel
)
18385 code
= BFD_RELOC_16_PCREL
;
18390 if (fixp
->fx_pcrel
)
18392 code
= BFD_RELOC_32_PCREL
;
18396 case BFD_RELOC_ARM_MOVW
:
18397 if (fixp
->fx_pcrel
)
18399 code
= BFD_RELOC_ARM_MOVW_PCREL
;
18403 case BFD_RELOC_ARM_MOVT
:
18404 if (fixp
->fx_pcrel
)
18406 code
= BFD_RELOC_ARM_MOVT_PCREL
;
18410 case BFD_RELOC_ARM_THUMB_MOVW
:
18411 if (fixp
->fx_pcrel
)
18413 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
18417 case BFD_RELOC_ARM_THUMB_MOVT
:
18418 if (fixp
->fx_pcrel
)
18420 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
18424 case BFD_RELOC_NONE
:
18425 case BFD_RELOC_ARM_PCREL_BRANCH
:
18426 case BFD_RELOC_ARM_PCREL_BLX
:
18427 case BFD_RELOC_RVA
:
18428 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
18429 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
18430 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
18431 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
18432 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
18433 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
18434 case BFD_RELOC_THUMB_PCREL_BLX
:
18435 case BFD_RELOC_VTABLE_ENTRY
:
18436 case BFD_RELOC_VTABLE_INHERIT
:
18437 code
= fixp
->fx_r_type
;
18440 case BFD_RELOC_ARM_LITERAL
:
18441 case BFD_RELOC_ARM_HWLITERAL
:
18442 /* If this is called then the a literal has
18443 been referenced across a section boundary. */
18444 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18445 _("literal referenced across section boundary"));
18449 case BFD_RELOC_ARM_GOT32
:
18450 case BFD_RELOC_ARM_GOTOFF
:
18451 case BFD_RELOC_ARM_PLT32
:
18452 case BFD_RELOC_ARM_TARGET1
:
18453 case BFD_RELOC_ARM_ROSEGREL32
:
18454 case BFD_RELOC_ARM_SBREL32
:
18455 case BFD_RELOC_ARM_PREL31
:
18456 case BFD_RELOC_ARM_TARGET2
:
18457 case BFD_RELOC_ARM_TLS_LE32
:
18458 case BFD_RELOC_ARM_TLS_LDO32
:
18459 case BFD_RELOC_ARM_PCREL_CALL
:
18460 case BFD_RELOC_ARM_PCREL_JUMP
:
18461 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
18462 case BFD_RELOC_ARM_ALU_PC_G0
:
18463 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
18464 case BFD_RELOC_ARM_ALU_PC_G1
:
18465 case BFD_RELOC_ARM_ALU_PC_G2
:
18466 case BFD_RELOC_ARM_LDR_PC_G0
:
18467 case BFD_RELOC_ARM_LDR_PC_G1
:
18468 case BFD_RELOC_ARM_LDR_PC_G2
:
18469 case BFD_RELOC_ARM_LDRS_PC_G0
:
18470 case BFD_RELOC_ARM_LDRS_PC_G1
:
18471 case BFD_RELOC_ARM_LDRS_PC_G2
:
18472 case BFD_RELOC_ARM_LDC_PC_G0
:
18473 case BFD_RELOC_ARM_LDC_PC_G1
:
18474 case BFD_RELOC_ARM_LDC_PC_G2
:
18475 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
18476 case BFD_RELOC_ARM_ALU_SB_G0
:
18477 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
18478 case BFD_RELOC_ARM_ALU_SB_G1
:
18479 case BFD_RELOC_ARM_ALU_SB_G2
:
18480 case BFD_RELOC_ARM_LDR_SB_G0
:
18481 case BFD_RELOC_ARM_LDR_SB_G1
:
18482 case BFD_RELOC_ARM_LDR_SB_G2
:
18483 case BFD_RELOC_ARM_LDRS_SB_G0
:
18484 case BFD_RELOC_ARM_LDRS_SB_G1
:
18485 case BFD_RELOC_ARM_LDRS_SB_G2
:
18486 case BFD_RELOC_ARM_LDC_SB_G0
:
18487 case BFD_RELOC_ARM_LDC_SB_G1
:
18488 case BFD_RELOC_ARM_LDC_SB_G2
:
18489 code
= fixp
->fx_r_type
;
18492 case BFD_RELOC_ARM_TLS_GD32
:
18493 case BFD_RELOC_ARM_TLS_IE32
:
18494 case BFD_RELOC_ARM_TLS_LDM32
:
18495 /* BFD will include the symbol's address in the addend.
18496 But we don't want that, so subtract it out again here. */
18497 if (!S_IS_COMMON (fixp
->fx_addsy
))
18498 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
18499 code
= fixp
->fx_r_type
;
18503 case BFD_RELOC_ARM_IMMEDIATE
:
18504 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18505 _("internal relocation (type: IMMEDIATE) not fixed up"));
18508 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
18509 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18510 _("ADRL used for a symbol not defined in the same file"));
18513 case BFD_RELOC_ARM_OFFSET_IMM
:
18514 if (section
->use_rela_p
)
18516 code
= fixp
->fx_r_type
;
18520 if (fixp
->fx_addsy
!= NULL
18521 && !S_IS_DEFINED (fixp
->fx_addsy
)
18522 && S_IS_LOCAL (fixp
->fx_addsy
))
18524 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18525 _("undefined local label `%s'"),
18526 S_GET_NAME (fixp
->fx_addsy
));
18530 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18531 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
18538 switch (fixp
->fx_r_type
)
18540 case BFD_RELOC_NONE
: type
= "NONE"; break;
18541 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
18542 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
18543 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
18544 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
18545 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
18546 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
18547 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
18548 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
18549 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
18550 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
18551 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
18552 default: type
= _("<unknown>"); break;
18554 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18555 _("cannot represent %s relocation in this object file format"),
18562 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
18564 && fixp
->fx_addsy
== GOT_symbol
)
18566 code
= BFD_RELOC_ARM_GOTPC
;
18567 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
18571 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18573 if (reloc
->howto
== NULL
)
18575 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18576 _("cannot represent %s relocation in this object file format"),
18577 bfd_get_reloc_code_name (code
));
18581 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
18582 vtable entry to be used in the relocation's section offset. */
18583 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18584 reloc
->address
= fixp
->fx_offset
;
18589 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
18592 cons_fix_new_arm (fragS
* frag
,
18597 bfd_reloc_code_real_type type
;
18601 FIXME: @@ Should look at CPU word size. */
18605 type
= BFD_RELOC_8
;
18608 type
= BFD_RELOC_16
;
18612 type
= BFD_RELOC_32
;
18615 type
= BFD_RELOC_64
;
18619 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
18622 #if defined OBJ_COFF || defined OBJ_ELF
18624 arm_validate_fix (fixS
* fixP
)
18626 /* If the destination of the branch is a defined symbol which does not have
18627 the THUMB_FUNC attribute, then we must be calling a function which has
18628 the (interfacearm) attribute. We look for the Thumb entry point to that
18629 function and change the branch to refer to that function instead. */
18630 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
18631 && fixP
->fx_addsy
!= NULL
18632 && S_IS_DEFINED (fixP
->fx_addsy
)
18633 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
18635 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
18641 arm_force_relocation (struct fix
* fixp
)
18643 #if defined (OBJ_COFF) && defined (TE_PE)
18644 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
18648 /* Resolve these relocations even if the symbol is extern or weak. */
18649 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
18650 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
18651 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
18652 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
18653 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
18654 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
18655 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
18658 /* Always leave these relocations for the linker. */
18659 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
18660 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
18661 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
18664 return generic_force_reloc (fixp
);
18669 arm_fix_adjustable (fixS
* fixP
)
18671 /* This is a little hack to help the gas/arm/adrl.s test. It prevents
18672 local labels from being added to the output symbol table when they
18673 are used with the ADRL pseudo op. The ADRL relocation should always
18674 be resolved before the binbary is emitted, so it is safe to say that
18675 it is adjustable. */
18676 if (fixP
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
)
18679 /* This is a hack for the gas/all/redef2.s test. This test causes symbols
18680 to be cloned, and without this test relocs would still be generated
18681 against the original, pre-cloned symbol. Such symbols would not appear
18682 in the symbol table however, and so a valid reloc could not be
18683 generated. So check to see if the fixup is against a symbol which has
18684 been removed from the symbol chain, and if it is, then allow it to be
18685 adjusted into a reloc against a section symbol. */
18686 if (fixP
->fx_addsy
!= NULL
18687 && ! S_IS_LOCAL (fixP
->fx_addsy
)
18688 && symbol_next (fixP
->fx_addsy
) == NULL
18689 && symbol_next (fixP
->fx_addsy
) == symbol_previous (fixP
->fx_addsy
))
18697 /* Relocations against function names must be left unadjusted,
18698 so that the linker can use this information to generate interworking
18699 stubs. The MIPS version of this function
18700 also prevents relocations that are mips-16 specific, but I do not
18701 know why it does this.
18704 There is one other problem that ought to be addressed here, but
18705 which currently is not: Taking the address of a label (rather
18706 than a function) and then later jumping to that address. Such
18707 addresses also ought to have their bottom bit set (assuming that
18708 they reside in Thumb code), but at the moment they will not. */
18711 arm_fix_adjustable (fixS
* fixP
)
18713 if (fixP
->fx_addsy
== NULL
)
18716 /* Preserve relocations against symbols with function type. */
18717 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
18720 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
18721 && fixP
->fx_subsy
== NULL
)
18724 /* We need the symbol name for the VTABLE entries. */
18725 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
18726 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18729 /* Don't allow symbols to be discarded on GOT related relocs. */
18730 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
18731 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
18732 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
18733 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
18734 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
18735 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
18736 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
18737 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
18738 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
18741 /* Similarly for group relocations. */
18742 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
18743 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
18744 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
18751 elf32_arm_target_format (void)
18754 return (target_big_endian
18755 ? "elf32-bigarm-symbian"
18756 : "elf32-littlearm-symbian");
18757 #elif defined (TE_VXWORKS)
18758 return (target_big_endian
18759 ? "elf32-bigarm-vxworks"
18760 : "elf32-littlearm-vxworks");
18762 if (target_big_endian
)
18763 return "elf32-bigarm";
18765 return "elf32-littlearm";
18770 armelf_frob_symbol (symbolS
* symp
,
18773 elf_frob_symbol (symp
, puntp
);
18777 /* MD interface: Finalization. */
18779 /* A good place to do this, although this was probably not intended
18780 for this kind of use. We need to dump the literal pool before
18781 references are made to a null symbol pointer. */
18786 literal_pool
* pool
;
18788 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
18790 /* Put it at the end of the relevent section. */
18791 subseg_set (pool
->section
, pool
->sub_section
);
18793 arm_elf_change_section ();
18799 /* Adjust the symbol table. This marks Thumb symbols as distinct from
18803 arm_adjust_symtab (void)
18808 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
18810 if (ARM_IS_THUMB (sym
))
18812 if (THUMB_IS_FUNC (sym
))
18814 /* Mark the symbol as a Thumb function. */
18815 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
18816 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
18817 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
18819 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
18820 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
18822 as_bad (_("%s: unexpected function type: %d"),
18823 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
18825 else switch (S_GET_STORAGE_CLASS (sym
))
18828 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
18831 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
18834 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
18842 if (ARM_IS_INTERWORK (sym
))
18843 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
18850 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
18852 if (ARM_IS_THUMB (sym
))
18854 elf_symbol_type
* elf_sym
;
18856 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
18857 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
18859 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
18860 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
18862 /* If it's a .thumb_func, declare it as so,
18863 otherwise tag label as .code 16. */
18864 if (THUMB_IS_FUNC (sym
))
18865 elf_sym
->internal_elf_sym
.st_info
=
18866 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
18868 elf_sym
->internal_elf_sym
.st_info
=
18869 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
18876 /* MD interface: Initialization. */
18879 set_constant_flonums (void)
18883 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
18884 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
18894 if ( (arm_ops_hsh
= hash_new ()) == NULL
18895 || (arm_cond_hsh
= hash_new ()) == NULL
18896 || (arm_shift_hsh
= hash_new ()) == NULL
18897 || (arm_psr_hsh
= hash_new ()) == NULL
18898 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
18899 || (arm_reg_hsh
= hash_new ()) == NULL
18900 || (arm_reloc_hsh
= hash_new ()) == NULL
18901 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
18902 as_fatal (_("virtual memory exhausted"));
18904 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
18905 hash_insert (arm_ops_hsh
, insns
[i
].template, (PTR
) (insns
+ i
));
18906 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
18907 hash_insert (arm_cond_hsh
, conds
[i
].template, (PTR
) (conds
+ i
));
18908 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
18909 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (PTR
) (shift_names
+ i
));
18910 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
18911 hash_insert (arm_psr_hsh
, psrs
[i
].template, (PTR
) (psrs
+ i
));
18912 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
18913 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template, (PTR
) (v7m_psrs
+ i
));
18914 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
18915 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (PTR
) (reg_names
+ i
));
18917 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
18919 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template,
18920 (PTR
) (barrier_opt_names
+ i
));
18922 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
18923 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (PTR
) (reloc_names
+ i
));
18926 set_constant_flonums ();
18928 /* Set the cpu variant based on the command-line options. We prefer
18929 -mcpu= over -march= if both are set (as for GCC); and we prefer
18930 -mfpu= over any other way of setting the floating point unit.
18931 Use of legacy options with new options are faulted. */
18934 if (mcpu_cpu_opt
|| march_cpu_opt
)
18935 as_bad (_("use of old and new-style options to set CPU type"));
18937 mcpu_cpu_opt
= legacy_cpu
;
18939 else if (!mcpu_cpu_opt
)
18940 mcpu_cpu_opt
= march_cpu_opt
;
18945 as_bad (_("use of old and new-style options to set FPU type"));
18947 mfpu_opt
= legacy_fpu
;
18949 else if (!mfpu_opt
)
18951 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
18952 /* Some environments specify a default FPU. If they don't, infer it
18953 from the processor. */
18955 mfpu_opt
= mcpu_fpu_opt
;
18957 mfpu_opt
= march_fpu_opt
;
18959 mfpu_opt
= &fpu_default
;
18966 mfpu_opt
= &fpu_default
;
18967 else if (ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
18968 mfpu_opt
= &fpu_arch_vfp_v2
;
18970 mfpu_opt
= &fpu_arch_fpa
;
18976 mcpu_cpu_opt
= &cpu_default
;
18977 selected_cpu
= cpu_default
;
18981 selected_cpu
= *mcpu_cpu_opt
;
18983 mcpu_cpu_opt
= &arm_arch_any
;
18986 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
18988 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
18990 #if defined OBJ_COFF || defined OBJ_ELF
18992 unsigned int flags
= 0;
18994 #if defined OBJ_ELF
18995 flags
= meabi_flags
;
18997 switch (meabi_flags
)
18999 case EF_ARM_EABI_UNKNOWN
:
19001 /* Set the flags in the private structure. */
19002 if (uses_apcs_26
) flags
|= F_APCS26
;
19003 if (support_interwork
) flags
|= F_INTERWORK
;
19004 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
19005 if (pic_code
) flags
|= F_PIC
;
19006 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
19007 flags
|= F_SOFT_FLOAT
;
19009 switch (mfloat_abi_opt
)
19011 case ARM_FLOAT_ABI_SOFT
:
19012 case ARM_FLOAT_ABI_SOFTFP
:
19013 flags
|= F_SOFT_FLOAT
;
19016 case ARM_FLOAT_ABI_HARD
:
19017 if (flags
& F_SOFT_FLOAT
)
19018 as_bad (_("hard-float conflicts with specified fpu"));
19022 /* Using pure-endian doubles (even if soft-float). */
19023 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
19024 flags
|= F_VFP_FLOAT
;
19026 #if defined OBJ_ELF
19027 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
19028 flags
|= EF_ARM_MAVERICK_FLOAT
;
19031 case EF_ARM_EABI_VER4
:
19032 case EF_ARM_EABI_VER5
:
19033 /* No additional flags to set. */
19040 bfd_set_private_flags (stdoutput
, flags
);
19042 /* We have run out flags in the COFF header to encode the
19043 status of ATPCS support, so instead we create a dummy,
19044 empty, debug section called .arm.atpcs. */
19049 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
19053 bfd_set_section_flags
19054 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
19055 bfd_set_section_size (stdoutput
, sec
, 0);
19056 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
19062 /* Record the CPU type as well. */
19063 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
19064 mach
= bfd_mach_arm_iWMMXt
;
19065 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
19066 mach
= bfd_mach_arm_XScale
;
19067 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
19068 mach
= bfd_mach_arm_ep9312
;
19069 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
19070 mach
= bfd_mach_arm_5TE
;
19071 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
19073 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19074 mach
= bfd_mach_arm_5T
;
19076 mach
= bfd_mach_arm_5
;
19078 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
19080 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19081 mach
= bfd_mach_arm_4T
;
19083 mach
= bfd_mach_arm_4
;
19085 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
19086 mach
= bfd_mach_arm_3M
;
19087 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
19088 mach
= bfd_mach_arm_3
;
19089 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
19090 mach
= bfd_mach_arm_2a
;
19091 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
19092 mach
= bfd_mach_arm_2
;
19094 mach
= bfd_mach_arm_unknown
;
19096 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
19099 /* Command line processing. */
19102 Invocation line includes a switch not recognized by the base assembler.
19103 See if it's a processor-specific option.
19105 This routine is somewhat complicated by the need for backwards
19106 compatibility (since older releases of gcc can't be changed).
19107 The new options try to make the interface as compatible as
19110 New options (supported) are:
19112 -mcpu=<cpu name> Assemble for selected processor
19113 -march=<architecture name> Assemble for selected architecture
19114 -mfpu=<fpu architecture> Assemble for selected FPU.
19115 -EB/-mbig-endian Big-endian
19116 -EL/-mlittle-endian Little-endian
19117 -k Generate PIC code
19118 -mthumb Start in Thumb mode
19119 -mthumb-interwork Code supports ARM/Thumb interworking
19121 For now we will also provide support for:
19123 -mapcs-32 32-bit Program counter
19124 -mapcs-26 26-bit Program counter
19125 -macps-float Floats passed in FP registers
19126 -mapcs-reentrant Reentrant code
19128 (sometime these will probably be replaced with -mapcs=<list of options>
19129 and -matpcs=<list of options>)
19131 The remaining options are only supported for back-wards compatibility.
19132 Cpu variants, the arm part is optional:
19133 -m[arm]1 Currently not supported.
19134 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
19135 -m[arm]3 Arm 3 processor
19136 -m[arm]6[xx], Arm 6 processors
19137 -m[arm]7[xx][t][[d]m] Arm 7 processors
19138 -m[arm]8[10] Arm 8 processors
19139 -m[arm]9[20][tdmi] Arm 9 processors
19140 -mstrongarm[110[0]] StrongARM processors
19141 -mxscale XScale processors
19142 -m[arm]v[2345[t[e]]] Arm architectures
19143 -mall All (except the ARM1)
19145 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
19146 -mfpe-old (No float load/store multiples)
19147 -mvfpxd VFP Single precision
19149 -mno-fpu Disable all floating point instructions
19151 The following CPU names are recognized:
19152 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
19153 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
19154 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
19155 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
19156 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
19157 arm10t arm10e, arm1020t, arm1020e, arm10200e,
19158 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
19162 const char * md_shortopts
= "m:k";
19164 #ifdef ARM_BI_ENDIAN
19165 #define OPTION_EB (OPTION_MD_BASE + 0)
19166 #define OPTION_EL (OPTION_MD_BASE + 1)
19168 #if TARGET_BYTES_BIG_ENDIAN
19169 #define OPTION_EB (OPTION_MD_BASE + 0)
19171 #define OPTION_EL (OPTION_MD_BASE + 1)
19175 struct option md_longopts
[] =
19178 {"EB", no_argument
, NULL
, OPTION_EB
},
19181 {"EL", no_argument
, NULL
, OPTION_EL
},
19183 {NULL
, no_argument
, NULL
, 0}
19186 size_t md_longopts_size
= sizeof (md_longopts
);
19188 struct arm_option_table
19190 char *option
; /* Option name to match. */
19191 char *help
; /* Help information. */
19192 int *var
; /* Variable to change. */
19193 int value
; /* What to change it to. */
19194 char *deprecated
; /* If non-null, print this message. */
19197 struct arm_option_table arm_opts
[] =
19199 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
19200 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
19201 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
19202 &support_interwork
, 1, NULL
},
19203 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
19204 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
19205 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
19207 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
19208 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
19209 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
19210 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
19213 /* These are recognized by the assembler, but have no affect on code. */
19214 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
19215 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
19216 {NULL
, NULL
, NULL
, 0, NULL
}
19219 struct arm_legacy_option_table
19221 char *option
; /* Option name to match. */
19222 const arm_feature_set
**var
; /* Variable to change. */
19223 const arm_feature_set value
; /* What to change it to. */
19224 char *deprecated
; /* If non-null, print this message. */
19227 const struct arm_legacy_option_table arm_legacy_opts
[] =
19229 /* DON'T add any new processors to this list -- we want the whole list
19230 to go away... Add them to the processors table instead. */
19231 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19232 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19233 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19234 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19235 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19236 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19237 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19238 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19239 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19240 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19241 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19242 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19243 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19244 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19245 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19246 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19247 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19248 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19249 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19250 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19251 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19252 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19253 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19254 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19255 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19256 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19257 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19258 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19259 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19260 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19261 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19262 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19263 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19264 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19265 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19266 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19267 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19268 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19269 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19270 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19271 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19272 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19273 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19274 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19275 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19276 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19277 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19278 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19279 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19280 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19281 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19282 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19283 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19284 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19285 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19286 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19287 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19288 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19289 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19290 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19291 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19292 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19293 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19294 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19295 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19296 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19297 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19298 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19299 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
19300 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
19301 N_("use -mcpu=strongarm110")},
19302 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
19303 N_("use -mcpu=strongarm1100")},
19304 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
19305 N_("use -mcpu=strongarm1110")},
19306 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
19307 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
19308 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
19310 /* Architecture variants -- don't add any more to this list either. */
19311 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19312 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19313 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19314 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19315 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19316 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19317 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19318 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19319 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19320 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19321 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
19322 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
19323 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
19324 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
19325 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
19326 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
19327 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
19328 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
19330 /* Floating point variants -- don't add any more to this list either. */
19331 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
19332 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
19333 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
19334 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
19335 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
19337 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
19340 struct arm_cpu_option_table
19343 const arm_feature_set value
;
19344 /* For some CPUs we assume an FPU unless the user explicitly sets
19346 const arm_feature_set default_fpu
;
19347 /* The canonical name of the CPU, or NULL to use NAME converted to upper
19349 const char *canonical_name
;
19352 /* This list should, at a minimum, contain all the cpu names
19353 recognized by GCC. */
19354 static const struct arm_cpu_option_table arm_cpus
[] =
19356 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
19357 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
19358 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
19359 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
19360 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
19361 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19362 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19363 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19364 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19365 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19366 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19367 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
19368 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19369 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
19370 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19371 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
19372 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19373 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19374 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19375 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19376 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19377 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19378 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19379 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19380 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19381 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19382 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19383 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19384 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19385 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19386 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19387 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19388 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19389 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19390 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19391 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19392 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19393 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19394 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19395 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
19396 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19397 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19398 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19399 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19400 /* For V5 or later processors we default to using VFP; but the user
19401 should really set the FPU type explicitly. */
19402 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
19403 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19404 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
19405 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
19406 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
19407 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
19408 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
19409 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19410 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
19411 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
19412 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19413 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19414 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
19415 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
19416 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19417 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
19418 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
19419 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19420 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19421 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
19422 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
19423 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
19424 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
19425 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
19426 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
19427 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
19428 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
19429 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
19430 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
19431 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
19432 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
19433 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE(0, FPU_VFP_V3
19434 | FPU_NEON_EXT_V1
),
19436 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
19437 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
19438 /* ??? XSCALE is really an architecture. */
19439 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
19440 /* ??? iwmmxt is not a processor. */
19441 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
19442 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
19444 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
19445 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
19448 struct arm_arch_option_table
19451 const arm_feature_set value
;
19452 const arm_feature_set default_fpu
;
19455 /* This list should, at a minimum, contain all the architecture names
19456 recognized by GCC. */
19457 static const struct arm_arch_option_table arm_archs
[] =
19459 {"all", ARM_ANY
, FPU_ARCH_FPA
},
19460 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
19461 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
19462 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
19463 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
19464 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
19465 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
19466 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
19467 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
19468 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
19469 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
19470 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
19471 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
19472 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
19473 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
19474 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
19475 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
19476 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
19477 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
19478 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
19479 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
19480 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
19481 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
19482 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
19483 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
19484 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
19485 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
19486 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
19487 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
19488 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
19489 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
19490 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
19491 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
19494 /* ISA extensions in the co-processor space. */
19495 struct arm_option_cpu_value_table
19498 const arm_feature_set value
;
19501 static const struct arm_option_cpu_value_table arm_extensions
[] =
19503 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
19504 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
19505 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
19506 {NULL
, ARM_ARCH_NONE
}
19509 /* This list should, at a minimum, contain all the fpu names
19510 recognized by GCC. */
19511 static const struct arm_option_cpu_value_table arm_fpus
[] =
19513 {"softfpa", FPU_NONE
},
19514 {"fpe", FPU_ARCH_FPE
},
19515 {"fpe2", FPU_ARCH_FPE
},
19516 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
19517 {"fpa", FPU_ARCH_FPA
},
19518 {"fpa10", FPU_ARCH_FPA
},
19519 {"fpa11", FPU_ARCH_FPA
},
19520 {"arm7500fe", FPU_ARCH_FPA
},
19521 {"softvfp", FPU_ARCH_VFP
},
19522 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
19523 {"vfp", FPU_ARCH_VFP_V2
},
19524 {"vfp9", FPU_ARCH_VFP_V2
},
19525 {"vfp3", FPU_ARCH_VFP_V3
},
19526 {"vfp10", FPU_ARCH_VFP_V2
},
19527 {"vfp10-r0", FPU_ARCH_VFP_V1
},
19528 {"vfpxd", FPU_ARCH_VFP_V1xD
},
19529 {"arm1020t", FPU_ARCH_VFP_V1
},
19530 {"arm1020e", FPU_ARCH_VFP_V2
},
19531 {"arm1136jfs", FPU_ARCH_VFP_V2
},
19532 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
19533 {"maverick", FPU_ARCH_MAVERICK
},
19534 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
19535 {NULL
, ARM_ARCH_NONE
}
19538 struct arm_option_value_table
19544 static const struct arm_option_value_table arm_float_abis
[] =
19546 {"hard", ARM_FLOAT_ABI_HARD
},
19547 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
19548 {"soft", ARM_FLOAT_ABI_SOFT
},
19553 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
19554 static const struct arm_option_value_table arm_eabis
[] =
19556 {"gnu", EF_ARM_EABI_UNKNOWN
},
19557 {"4", EF_ARM_EABI_VER4
},
19558 {"5", EF_ARM_EABI_VER5
},
19563 struct arm_long_option_table
19565 char * option
; /* Substring to match. */
19566 char * help
; /* Help information. */
19567 int (* func
) (char * subopt
); /* Function to decode sub-option. */
19568 char * deprecated
; /* If non-null, print this message. */
19572 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
19574 arm_feature_set
*ext_set
= xmalloc (sizeof (arm_feature_set
));
19576 /* Copy the feature set, so that we can modify it. */
19577 *ext_set
= **opt_p
;
19580 while (str
!= NULL
&& *str
!= 0)
19582 const struct arm_option_cpu_value_table
* opt
;
19588 as_bad (_("invalid architectural extension"));
19593 ext
= strchr (str
, '+');
19596 optlen
= ext
- str
;
19598 optlen
= strlen (str
);
19602 as_bad (_("missing architectural extension"));
19606 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
19607 if (strncmp (opt
->name
, str
, optlen
) == 0)
19609 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
19613 if (opt
->name
== NULL
)
19615 as_bad (_("unknown architectural extnsion `%s'"), str
);
19626 arm_parse_cpu (char * str
)
19628 const struct arm_cpu_option_table
* opt
;
19629 char * ext
= strchr (str
, '+');
19633 optlen
= ext
- str
;
19635 optlen
= strlen (str
);
19639 as_bad (_("missing cpu name `%s'"), str
);
19643 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
19644 if (strncmp (opt
->name
, str
, optlen
) == 0)
19646 mcpu_cpu_opt
= &opt
->value
;
19647 mcpu_fpu_opt
= &opt
->default_fpu
;
19648 if (opt
->canonical_name
)
19649 strcpy(selected_cpu_name
, opt
->canonical_name
);
19653 for (i
= 0; i
< optlen
; i
++)
19654 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
19655 selected_cpu_name
[i
] = 0;
19659 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
19664 as_bad (_("unknown cpu `%s'"), str
);
19669 arm_parse_arch (char * str
)
19671 const struct arm_arch_option_table
*opt
;
19672 char *ext
= strchr (str
, '+');
19676 optlen
= ext
- str
;
19678 optlen
= strlen (str
);
19682 as_bad (_("missing architecture name `%s'"), str
);
19686 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
19687 if (streq (opt
->name
, str
))
19689 march_cpu_opt
= &opt
->value
;
19690 march_fpu_opt
= &opt
->default_fpu
;
19691 strcpy(selected_cpu_name
, opt
->name
);
19694 return arm_parse_extension (ext
, &march_cpu_opt
);
19699 as_bad (_("unknown architecture `%s'\n"), str
);
19704 arm_parse_fpu (char * str
)
19706 const struct arm_option_cpu_value_table
* opt
;
19708 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
19709 if (streq (opt
->name
, str
))
19711 mfpu_opt
= &opt
->value
;
19715 as_bad (_("unknown floating point format `%s'\n"), str
);
19720 arm_parse_float_abi (char * str
)
19722 const struct arm_option_value_table
* opt
;
19724 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
19725 if (streq (opt
->name
, str
))
19727 mfloat_abi_opt
= opt
->value
;
19731 as_bad (_("unknown floating point abi `%s'\n"), str
);
19737 arm_parse_eabi (char * str
)
19739 const struct arm_option_value_table
*opt
;
19741 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
19742 if (streq (opt
->name
, str
))
19744 meabi_flags
= opt
->value
;
19747 as_bad (_("unknown EABI `%s'\n"), str
);
19752 struct arm_long_option_table arm_long_opts
[] =
19754 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
19755 arm_parse_cpu
, NULL
},
19756 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
19757 arm_parse_arch
, NULL
},
19758 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
19759 arm_parse_fpu
, NULL
},
19760 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
19761 arm_parse_float_abi
, NULL
},
19763 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
19764 arm_parse_eabi
, NULL
},
19766 {NULL
, NULL
, 0, NULL
}
19770 md_parse_option (int c
, char * arg
)
19772 struct arm_option_table
*opt
;
19773 const struct arm_legacy_option_table
*fopt
;
19774 struct arm_long_option_table
*lopt
;
19780 target_big_endian
= 1;
19786 target_big_endian
= 0;
19791 /* Listing option. Just ignore these, we don't support additional
19796 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
19798 if (c
== opt
->option
[0]
19799 && ((arg
== NULL
&& opt
->option
[1] == 0)
19800 || streq (arg
, opt
->option
+ 1)))
19802 #if WARN_DEPRECATED
19803 /* If the option is deprecated, tell the user. */
19804 if (opt
->deprecated
!= NULL
)
19805 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
19806 arg
? arg
: "", _(opt
->deprecated
));
19809 if (opt
->var
!= NULL
)
19810 *opt
->var
= opt
->value
;
19816 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
19818 if (c
== fopt
->option
[0]
19819 && ((arg
== NULL
&& fopt
->option
[1] == 0)
19820 || streq (arg
, fopt
->option
+ 1)))
19822 #if WARN_DEPRECATED
19823 /* If the option is deprecated, tell the user. */
19824 if (fopt
->deprecated
!= NULL
)
19825 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
19826 arg
? arg
: "", _(fopt
->deprecated
));
19829 if (fopt
->var
!= NULL
)
19830 *fopt
->var
= &fopt
->value
;
19836 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
19838 /* These options are expected to have an argument. */
19839 if (c
== lopt
->option
[0]
19841 && strncmp (arg
, lopt
->option
+ 1,
19842 strlen (lopt
->option
+ 1)) == 0)
19844 #if WARN_DEPRECATED
19845 /* If the option is deprecated, tell the user. */
19846 if (lopt
->deprecated
!= NULL
)
19847 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
19848 _(lopt
->deprecated
));
19851 /* Call the sup-option parser. */
19852 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
19863 md_show_usage (FILE * fp
)
19865 struct arm_option_table
*opt
;
19866 struct arm_long_option_table
*lopt
;
19868 fprintf (fp
, _(" ARM-specific assembler options:\n"));
19870 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
19871 if (opt
->help
!= NULL
)
19872 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
19874 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
19875 if (lopt
->help
!= NULL
)
19876 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
19880 -EB assemble code for a big-endian cpu\n"));
19885 -EL assemble code for a little-endian cpu\n"));
19894 arm_feature_set flags
;
19895 } cpu_arch_ver_table
;
19897 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
19898 least features first. */
19899 static const cpu_arch_ver_table cpu_arch_ver
[] =
19904 {4, ARM_ARCH_V5TE
},
19905 {5, ARM_ARCH_V5TEJ
},
19909 {9, ARM_ARCH_V6T2
},
19910 {10, ARM_ARCH_V7A
},
19911 {10, ARM_ARCH_V7R
},
19912 {10, ARM_ARCH_V7M
},
19916 /* Set the public EABI object attributes. */
19918 aeabi_set_public_attributes (void)
19921 arm_feature_set flags
;
19922 arm_feature_set tmp
;
19923 const cpu_arch_ver_table
*p
;
19925 /* Choose the architecture based on the capabilities of the requested cpu
19926 (if any) and/or the instructions actually used. */
19927 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
19928 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
19929 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
19933 for (p
= cpu_arch_ver
; p
->val
; p
++)
19935 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
19938 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
19942 /* Tag_CPU_name. */
19943 if (selected_cpu_name
[0])
19947 p
= selected_cpu_name
;
19948 if (strncmp(p
, "armv", 4) == 0)
19953 for (i
= 0; p
[i
]; i
++)
19954 p
[i
] = TOUPPER (p
[i
]);
19956 elf32_arm_add_eabi_attr_string (stdoutput
, 5, p
);
19958 /* Tag_CPU_arch. */
19959 elf32_arm_add_eabi_attr_int (stdoutput
, 6, arch
);
19960 /* Tag_CPU_arch_profile. */
19961 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
19962 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'A');
19963 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
19964 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'R');
19965 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
))
19966 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'M');
19967 /* Tag_ARM_ISA_use. */
19968 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_full
))
19969 elf32_arm_add_eabi_attr_int (stdoutput
, 8, 1);
19970 /* Tag_THUMB_ISA_use. */
19971 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_full
))
19972 elf32_arm_add_eabi_attr_int (stdoutput
, 9,
19973 ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
) ? 2 : 1);
19974 /* Tag_VFP_arch. */
19975 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v3
)
19976 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v3
))
19977 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 3);
19978 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v2
)
19979 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v2
))
19980 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 2);
19981 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1
)
19982 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1
)
19983 || ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1xd
)
19984 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1xd
))
19985 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 1);
19986 /* Tag_WMMX_arch. */
19987 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_cext_iwmmxt
)
19988 || ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_cext_iwmmxt
))
19989 elf32_arm_add_eabi_attr_int (stdoutput
, 11, 1);
19990 /* Tag_NEON_arch. */
19991 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_neon_ext_v1
)
19992 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_neon_ext_v1
))
19993 elf32_arm_add_eabi_attr_int (stdoutput
, 12, 1);
19996 /* Add the .ARM.attributes section. */
20005 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
20008 aeabi_set_public_attributes ();
20009 size
= elf32_arm_eabi_attr_size (stdoutput
);
20010 s
= subseg_new (".ARM.attributes", 0);
20011 bfd_set_section_flags (stdoutput
, s
, SEC_READONLY
| SEC_DATA
);
20012 addr
= frag_now_fix ();
20013 p
= frag_more (size
);
20014 elf32_arm_set_eabi_attr_contents (stdoutput
, (bfd_byte
*)p
, size
);
20016 #endif /* OBJ_ELF */
20019 /* Parse a .cpu directive. */
20022 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
20024 const struct arm_cpu_option_table
*opt
;
20028 name
= input_line_pointer
;
20029 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20030 input_line_pointer
++;
20031 saved_char
= *input_line_pointer
;
20032 *input_line_pointer
= 0;
20034 /* Skip the first "all" entry. */
20035 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
20036 if (streq (opt
->name
, name
))
20038 mcpu_cpu_opt
= &opt
->value
;
20039 selected_cpu
= opt
->value
;
20040 if (opt
->canonical_name
)
20041 strcpy(selected_cpu_name
, opt
->canonical_name
);
20045 for (i
= 0; opt
->name
[i
]; i
++)
20046 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20047 selected_cpu_name
[i
] = 0;
20049 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20050 *input_line_pointer
= saved_char
;
20051 demand_empty_rest_of_line ();
20054 as_bad (_("unknown cpu `%s'"), name
);
20055 *input_line_pointer
= saved_char
;
20056 ignore_rest_of_line ();
20060 /* Parse a .arch directive. */
20063 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
20065 const struct arm_arch_option_table
*opt
;
20069 name
= input_line_pointer
;
20070 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20071 input_line_pointer
++;
20072 saved_char
= *input_line_pointer
;
20073 *input_line_pointer
= 0;
20075 /* Skip the first "all" entry. */
20076 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
20077 if (streq (opt
->name
, name
))
20079 mcpu_cpu_opt
= &opt
->value
;
20080 selected_cpu
= opt
->value
;
20081 strcpy(selected_cpu_name
, opt
->name
);
20082 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20083 *input_line_pointer
= saved_char
;
20084 demand_empty_rest_of_line ();
20088 as_bad (_("unknown architecture `%s'\n"), name
);
20089 *input_line_pointer
= saved_char
;
20090 ignore_rest_of_line ();
20094 /* Parse a .fpu directive. */
20097 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
20099 const struct arm_option_cpu_value_table
*opt
;
20103 name
= input_line_pointer
;
20104 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20105 input_line_pointer
++;
20106 saved_char
= *input_line_pointer
;
20107 *input_line_pointer
= 0;
20109 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
20110 if (streq (opt
->name
, name
))
20112 mfpu_opt
= &opt
->value
;
20113 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20114 *input_line_pointer
= saved_char
;
20115 demand_empty_rest_of_line ();
20119 as_bad (_("unknown floating point format `%s'\n"), name
);
20120 *input_line_pointer
= saved_char
;
20121 ignore_rest_of_line ();