1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 #if defined __XSCALE__
101 #define CPU_DEFAULT ARM_ARCH_XSCALE
103 #if defined __thumb__
104 #define CPU_DEFAULT ARM_ARCH_V5T
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 static arm_feature_set cpu_variant
;
130 static arm_feature_set arm_arch_used
;
131 static arm_feature_set thumb_arch_used
;
133 /* Flags stored in private area of BFD structure. */
134 static int uses_apcs_26
= FALSE
;
135 static int atpcs
= FALSE
;
136 static int support_interwork
= FALSE
;
137 static int uses_apcs_float
= FALSE
;
138 static int pic_code
= FALSE
;
139 static int fix_v4bx
= FALSE
;
140 /* Warn on using deprecated features. */
141 static int warn_on_deprecated
= TRUE
;
144 /* Variables that we set while parsing command-line options. Once all
145 options have been read we re-process these values to set the real
147 static const arm_feature_set
*legacy_cpu
= NULL
;
148 static const arm_feature_set
*legacy_fpu
= NULL
;
150 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
151 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
152 static const arm_feature_set
*march_cpu_opt
= NULL
;
153 static const arm_feature_set
*march_fpu_opt
= NULL
;
154 static const arm_feature_set
*mfpu_opt
= NULL
;
155 static const arm_feature_set
*object_arch
= NULL
;
157 /* Constants for known architecture features. */
158 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
159 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
160 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
161 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
162 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
163 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
164 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
165 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
166 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
169 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
172 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
174 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
175 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
176 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
177 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
178 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
179 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
180 static const arm_feature_set arm_ext_v4t_5
=
181 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
182 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
183 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
184 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
185 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
186 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
187 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
188 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
189 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
190 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
191 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
192 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
193 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
194 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
195 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
196 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
197 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
198 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
199 static const arm_feature_set arm_ext_m
=
200 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_V7M
, 0);
202 static const arm_feature_set arm_arch_any
= ARM_ANY
;
203 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
204 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
205 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
207 static const arm_feature_set arm_cext_iwmmxt2
=
208 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
209 static const arm_feature_set arm_cext_iwmmxt
=
210 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
211 static const arm_feature_set arm_cext_xscale
=
212 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
213 static const arm_feature_set arm_cext_maverick
=
214 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
215 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
216 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
217 static const arm_feature_set fpu_vfp_ext_v1xd
=
218 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
219 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
220 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
221 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
222 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
223 static const arm_feature_set fpu_vfp_ext_d32
=
224 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
225 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
226 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
227 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
228 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
229 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
230 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
232 static int mfloat_abi_opt
= -1;
233 /* Record user cpu selection for object attributes. */
234 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
235 /* Must be long enough to hold any of the names in arm_cpus. */
236 static char selected_cpu_name
[16];
239 static int meabi_flags
= EABI_DEFAULT
;
241 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
244 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
249 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
254 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
255 symbolS
* GOT_symbol
;
258 /* 0: assemble for ARM,
259 1: assemble for Thumb,
260 2: assemble for Thumb even though target CPU does not support thumb
262 static int thumb_mode
= 0;
263 /* A value distinct from the possible values for thumb_mode that we
264 can use to record whether thumb_mode has been copied into the
265 tc_frag_data field of a frag. */
266 #define MODE_RECORDED (1 << 4)
268 /* Specifies the intrinsic IT insn behavior mode. */
269 enum implicit_it_mode
271 IMPLICIT_IT_MODE_NEVER
= 0x00,
272 IMPLICIT_IT_MODE_ARM
= 0x01,
273 IMPLICIT_IT_MODE_THUMB
= 0x02,
274 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
276 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
278 /* If unified_syntax is true, we are processing the new unified
279 ARM/Thumb syntax. Important differences from the old ARM mode:
281 - Immediate operands do not require a # prefix.
282 - Conditional affixes always appear at the end of the
283 instruction. (For backward compatibility, those instructions
284 that formerly had them in the middle, continue to accept them
286 - The IT instruction may appear, and if it does is validated
287 against subsequent conditional affixes. It does not generate
290 Important differences from the old Thumb mode:
292 - Immediate operands do not require a # prefix.
293 - Most of the V6T2 instructions are only available in unified mode.
294 - The .N and .W suffixes are recognized and honored (it is an error
295 if they cannot be honored).
296 - All instructions set the flags if and only if they have an 's' affix.
297 - Conditional affixes may be used. They are validated against
298 preceding IT instructions. Unlike ARM mode, you cannot use a
299 conditional affix except in the scope of an IT instruction. */
301 static bfd_boolean unified_syntax
= FALSE
;
316 enum neon_el_type type
;
320 #define NEON_MAX_TYPE_ELS 4
324 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
328 enum it_instruction_type
333 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
334 if inside, should be the last one. */
335 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
336 i.e. BKPT and NOP. */
337 IT_INSN
/* The IT insn has been parsed. */
343 unsigned long instruction
;
347 /* "uncond_value" is set to the value in place of the conditional field in
348 unconditional versions of the instruction, or -1 if nothing is
351 struct neon_type vectype
;
352 /* Set to the opcode if the instruction needs relaxation.
353 Zero if the instruction is not relaxed. */
357 bfd_reloc_code_real_type type
;
362 enum it_instruction_type it_insn_type
;
368 struct neon_type_el vectype
;
369 unsigned present
: 1; /* Operand present. */
370 unsigned isreg
: 1; /* Operand was a register. */
371 unsigned immisreg
: 1; /* .imm field is a second register. */
372 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
373 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
374 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
375 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
376 instructions. This allows us to disambiguate ARM <-> vector insns. */
377 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
378 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
379 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
380 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
381 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
382 unsigned writeback
: 1; /* Operand has trailing ! */
383 unsigned preind
: 1; /* Preindexed address. */
384 unsigned postind
: 1; /* Postindexed address. */
385 unsigned negative
: 1; /* Index register was negated. */
386 unsigned shifted
: 1; /* Shift applied to operation. */
387 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
391 static struct arm_it inst
;
393 #define NUM_FLOAT_VALS 8
395 const char * fp_const
[] =
397 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
400 /* Number of littlenums required to hold an extended precision number. */
401 #define MAX_LITTLENUMS 6
403 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
413 #define CP_T_X 0x00008000
414 #define CP_T_Y 0x00400000
416 #define CONDS_BIT 0x00100000
417 #define LOAD_BIT 0x00100000
419 #define DOUBLE_LOAD_FLAG 0x00000001
423 const char * template_name
;
427 #define COND_ALWAYS 0xE
431 const char * template_name
;
435 struct asm_barrier_opt
437 const char * template_name
;
441 /* The bit that distinguishes CPSR and SPSR. */
442 #define SPSR_BIT (1 << 22)
444 /* The individual PSR flag bits. */
445 #define PSR_c (1 << 16)
446 #define PSR_x (1 << 17)
447 #define PSR_s (1 << 18)
448 #define PSR_f (1 << 19)
453 bfd_reloc_code_real_type reloc
;
458 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
459 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
464 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
467 /* Bits for DEFINED field in neon_typed_alias. */
468 #define NTA_HASTYPE 1
469 #define NTA_HASINDEX 2
471 struct neon_typed_alias
473 unsigned char defined
;
475 struct neon_type_el eltype
;
478 /* ARM register categories. This includes coprocessor numbers and various
479 architecture extensions' registers. */
505 /* Structure for a hash table entry for a register.
506 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
507 information which states whether a vector type or index is specified (for a
508 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
512 unsigned char number
;
514 unsigned char builtin
;
515 struct neon_typed_alias
* neon
;
518 /* Diagnostics used when we don't get a register of the expected type. */
519 const char * const reg_expected_msgs
[] =
521 N_("ARM register expected"),
522 N_("bad or missing co-processor number"),
523 N_("co-processor register expected"),
524 N_("FPA register expected"),
525 N_("VFP single precision register expected"),
526 N_("VFP/Neon double precision register expected"),
527 N_("Neon quad precision register expected"),
528 N_("VFP single or double precision register expected"),
529 N_("Neon double or quad precision register expected"),
530 N_("VFP single, double or Neon quad precision register expected"),
531 N_("VFP system register expected"),
532 N_("Maverick MVF register expected"),
533 N_("Maverick MVD register expected"),
534 N_("Maverick MVFX register expected"),
535 N_("Maverick MVDX register expected"),
536 N_("Maverick MVAX register expected"),
537 N_("Maverick DSPSC register expected"),
538 N_("iWMMXt data register expected"),
539 N_("iWMMXt control register expected"),
540 N_("iWMMXt scalar register expected"),
541 N_("XScale accumulator register expected"),
544 /* Some well known registers that we refer to directly elsewhere. */
549 /* ARM instructions take 4bytes in the object file, Thumb instructions
555 /* Basic string to match. */
556 const char * template_name
;
558 /* Parameters to instruction. */
559 unsigned char operands
[8];
561 /* Conditional tag - see opcode_lookup. */
562 unsigned int tag
: 4;
564 /* Basic instruction code. */
565 unsigned int avalue
: 28;
567 /* Thumb-format instruction code. */
570 /* Which architecture variant provides this instruction. */
571 const arm_feature_set
* avariant
;
572 const arm_feature_set
* tvariant
;
574 /* Function to call to encode instruction in ARM format. */
575 void (* aencode
) (void);
577 /* Function to call to encode instruction in Thumb format. */
578 void (* tencode
) (void);
581 /* Defines for various bits that we will want to toggle. */
582 #define INST_IMMEDIATE 0x02000000
583 #define OFFSET_REG 0x02000000
584 #define HWOFFSET_IMM 0x00400000
585 #define SHIFT_BY_REG 0x00000010
586 #define PRE_INDEX 0x01000000
587 #define INDEX_UP 0x00800000
588 #define WRITE_BACK 0x00200000
589 #define LDM_TYPE_2_OR_3 0x00400000
590 #define CPSI_MMOD 0x00020000
592 #define LITERAL_MASK 0xf000f000
593 #define OPCODE_MASK 0xfe1fffff
594 #define V4_STR_BIT 0x00000020
596 #define T2_SUBS_PC_LR 0xf3de8f00
598 #define DATA_OP_SHIFT 21
600 #define T2_OPCODE_MASK 0xfe1fffff
601 #define T2_DATA_OP_SHIFT 21
603 /* Codes to distinguish the arithmetic instructions. */
614 #define OPCODE_CMP 10
615 #define OPCODE_CMN 11
616 #define OPCODE_ORR 12
617 #define OPCODE_MOV 13
618 #define OPCODE_BIC 14
619 #define OPCODE_MVN 15
621 #define T2_OPCODE_AND 0
622 #define T2_OPCODE_BIC 1
623 #define T2_OPCODE_ORR 2
624 #define T2_OPCODE_ORN 3
625 #define T2_OPCODE_EOR 4
626 #define T2_OPCODE_ADD 8
627 #define T2_OPCODE_ADC 10
628 #define T2_OPCODE_SBC 11
629 #define T2_OPCODE_SUB 13
630 #define T2_OPCODE_RSB 14
632 #define T_OPCODE_MUL 0x4340
633 #define T_OPCODE_TST 0x4200
634 #define T_OPCODE_CMN 0x42c0
635 #define T_OPCODE_NEG 0x4240
636 #define T_OPCODE_MVN 0x43c0
638 #define T_OPCODE_ADD_R3 0x1800
639 #define T_OPCODE_SUB_R3 0x1a00
640 #define T_OPCODE_ADD_HI 0x4400
641 #define T_OPCODE_ADD_ST 0xb000
642 #define T_OPCODE_SUB_ST 0xb080
643 #define T_OPCODE_ADD_SP 0xa800
644 #define T_OPCODE_ADD_PC 0xa000
645 #define T_OPCODE_ADD_I8 0x3000
646 #define T_OPCODE_SUB_I8 0x3800
647 #define T_OPCODE_ADD_I3 0x1c00
648 #define T_OPCODE_SUB_I3 0x1e00
650 #define T_OPCODE_ASR_R 0x4100
651 #define T_OPCODE_LSL_R 0x4080
652 #define T_OPCODE_LSR_R 0x40c0
653 #define T_OPCODE_ROR_R 0x41c0
654 #define T_OPCODE_ASR_I 0x1000
655 #define T_OPCODE_LSL_I 0x0000
656 #define T_OPCODE_LSR_I 0x0800
658 #define T_OPCODE_MOV_I8 0x2000
659 #define T_OPCODE_CMP_I8 0x2800
660 #define T_OPCODE_CMP_LR 0x4280
661 #define T_OPCODE_MOV_HR 0x4600
662 #define T_OPCODE_CMP_HR 0x4500
664 #define T_OPCODE_LDR_PC 0x4800
665 #define T_OPCODE_LDR_SP 0x9800
666 #define T_OPCODE_STR_SP 0x9000
667 #define T_OPCODE_LDR_IW 0x6800
668 #define T_OPCODE_STR_IW 0x6000
669 #define T_OPCODE_LDR_IH 0x8800
670 #define T_OPCODE_STR_IH 0x8000
671 #define T_OPCODE_LDR_IB 0x7800
672 #define T_OPCODE_STR_IB 0x7000
673 #define T_OPCODE_LDR_RW 0x5800
674 #define T_OPCODE_STR_RW 0x5000
675 #define T_OPCODE_LDR_RH 0x5a00
676 #define T_OPCODE_STR_RH 0x5200
677 #define T_OPCODE_LDR_RB 0x5c00
678 #define T_OPCODE_STR_RB 0x5400
680 #define T_OPCODE_PUSH 0xb400
681 #define T_OPCODE_POP 0xbc00
683 #define T_OPCODE_BRANCH 0xe000
685 #define THUMB_SIZE 2 /* Size of thumb instruction. */
686 #define THUMB_PP_PC_LR 0x0100
687 #define THUMB_LOAD_BIT 0x0800
688 #define THUMB2_LOAD_BIT 0x00100000
690 #define BAD_ARGS _("bad arguments to instruction")
691 #define BAD_SP _("r13 not allowed here")
692 #define BAD_PC _("r15 not allowed here")
693 #define BAD_COND _("instruction cannot be conditional")
694 #define BAD_OVERLAP _("registers may not be the same")
695 #define BAD_HIREG _("lo register required")
696 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
697 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
698 #define BAD_BRANCH _("branch must be last instruction in IT block")
699 #define BAD_NOT_IT _("instruction not allowed in IT block")
700 #define BAD_FPU _("selected FPU does not support instruction")
701 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
702 #define BAD_IT_COND _("incorrect condition in IT block")
703 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
704 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
706 static struct hash_control
* arm_ops_hsh
;
707 static struct hash_control
* arm_cond_hsh
;
708 static struct hash_control
* arm_shift_hsh
;
709 static struct hash_control
* arm_psr_hsh
;
710 static struct hash_control
* arm_v7m_psr_hsh
;
711 static struct hash_control
* arm_reg_hsh
;
712 static struct hash_control
* arm_reloc_hsh
;
713 static struct hash_control
* arm_barrier_opt_hsh
;
715 /* Stuff needed to resolve the label ambiguity
724 symbolS
* last_label_seen
;
725 static int label_is_thumb_function_name
= FALSE
;
727 /* Literal pool structure. Held on a per-section
728 and per-sub-section basis. */
730 #define MAX_LITERAL_POOL_SIZE 1024
731 typedef struct literal_pool
733 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
734 unsigned int next_free_entry
;
739 struct literal_pool
* next
;
742 /* Pointer to a linked list of literal pools. */
743 literal_pool
* list_of_pools
= NULL
;
746 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
748 static struct current_it now_it
;
752 now_it_compatible (int cond
)
754 return (cond
& ~1) == (now_it
.cc
& ~1);
758 conditional_insn (void)
760 return inst
.cond
!= COND_ALWAYS
;
763 static int in_it_block (void);
765 static int handle_it_state (void);
767 static void force_automatic_it_block_close (void);
769 static void it_fsm_post_encode (void);
771 #define set_it_insn_type(type) \
774 inst.it_insn_type = type; \
775 if (handle_it_state () == FAIL) \
780 #define set_it_insn_type_nonvoid(type, failret) \
783 inst.it_insn_type = type; \
784 if (handle_it_state () == FAIL) \
789 #define set_it_insn_type_last() \
792 if (inst.cond == COND_ALWAYS) \
793 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
795 set_it_insn_type (INSIDE_IT_LAST_INSN); \
801 /* This array holds the chars that always start a comment. If the
802 pre-processor is disabled, these aren't very useful. */
803 const char comment_chars
[] = "@";
805 /* This array holds the chars that only start a comment at the beginning of
806 a line. If the line seems to have the form '# 123 filename'
807 .line and .file directives will appear in the pre-processed output. */
808 /* Note that input_file.c hand checks for '#' at the beginning of the
809 first line of the input file. This is because the compiler outputs
810 #NO_APP at the beginning of its output. */
811 /* Also note that comments like this one will always work. */
812 const char line_comment_chars
[] = "#";
814 const char line_separator_chars
[] = ";";
816 /* Chars that can be used to separate mant
817 from exp in floating point numbers. */
818 const char EXP_CHARS
[] = "eE";
820 /* Chars that mean this number is a floating point constant. */
824 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
826 /* Prefix characters that indicate the start of an immediate
828 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
830 /* Separator character handling. */
832 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
835 skip_past_char (char ** str
, char c
)
846 #define skip_past_comma(str) skip_past_char (str, ',')
848 /* Arithmetic expressions (possibly involving symbols). */
850 /* Return TRUE if anything in the expression is a bignum. */
853 walk_no_bignums (symbolS
* sp
)
855 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
858 if (symbol_get_value_expression (sp
)->X_add_symbol
)
860 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
861 || (symbol_get_value_expression (sp
)->X_op_symbol
862 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
868 static int in_my_get_expression
= 0;
870 /* Third argument to my_get_expression. */
871 #define GE_NO_PREFIX 0
872 #define GE_IMM_PREFIX 1
873 #define GE_OPT_PREFIX 2
874 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
875 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
876 #define GE_OPT_PREFIX_BIG 3
879 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
884 /* In unified syntax, all prefixes are optional. */
886 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
891 case GE_NO_PREFIX
: break;
893 if (!is_immediate_prefix (**str
))
895 inst
.error
= _("immediate expression requires a # prefix");
901 case GE_OPT_PREFIX_BIG
:
902 if (is_immediate_prefix (**str
))
908 memset (ep
, 0, sizeof (expressionS
));
910 save_in
= input_line_pointer
;
911 input_line_pointer
= *str
;
912 in_my_get_expression
= 1;
913 seg
= expression (ep
);
914 in_my_get_expression
= 0;
916 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
918 /* We found a bad or missing expression in md_operand(). */
919 *str
= input_line_pointer
;
920 input_line_pointer
= save_in
;
921 if (inst
.error
== NULL
)
922 inst
.error
= (ep
->X_op
== O_absent
923 ? _("missing expression") :_("bad expression"));
928 if (seg
!= absolute_section
929 && seg
!= text_section
930 && seg
!= data_section
931 && seg
!= bss_section
932 && seg
!= undefined_section
)
934 inst
.error
= _("bad segment");
935 *str
= input_line_pointer
;
936 input_line_pointer
= save_in
;
941 /* Get rid of any bignums now, so that we don't generate an error for which
942 we can't establish a line number later on. Big numbers are never valid
943 in instructions, which is where this routine is always called. */
944 if (prefix_mode
!= GE_OPT_PREFIX_BIG
945 && (ep
->X_op
== O_big
947 && (walk_no_bignums (ep
->X_add_symbol
)
949 && walk_no_bignums (ep
->X_op_symbol
))))))
951 inst
.error
= _("invalid constant");
952 *str
= input_line_pointer
;
953 input_line_pointer
= save_in
;
957 *str
= input_line_pointer
;
958 input_line_pointer
= save_in
;
962 /* Turn a string in input_line_pointer into a floating point constant
963 of type TYPE, and store the appropriate bytes in *LITP. The number
964 of LITTLENUMS emitted is stored in *SIZEP. An error message is
965 returned, or NULL on OK.
967 Note that fp constants aren't represent in the normal way on the ARM.
968 In big endian mode, things are as expected. However, in little endian
969 mode fp constants are big-endian word-wise, and little-endian byte-wise
970 within the words. For example, (double) 1.1 in big endian mode is
971 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
972 the byte sequence 99 99 f1 3f 9a 99 99 99.
974 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
977 md_atof (int type
, char * litP
, int * sizeP
)
980 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1012 return _("Unrecognized or unsupported floating point constant");
1015 t
= atof_ieee (input_line_pointer
, type
, words
);
1017 input_line_pointer
= t
;
1018 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1020 if (target_big_endian
)
1022 for (i
= 0; i
< prec
; i
++)
1024 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1025 litP
+= sizeof (LITTLENUM_TYPE
);
1030 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1031 for (i
= prec
- 1; i
>= 0; i
--)
1033 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1034 litP
+= sizeof (LITTLENUM_TYPE
);
1037 /* For a 4 byte float the order of elements in `words' is 1 0.
1038 For an 8 byte float the order is 1 0 3 2. */
1039 for (i
= 0; i
< prec
; i
+= 2)
1041 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1042 sizeof (LITTLENUM_TYPE
));
1043 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1044 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1045 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1052 /* We handle all bad expressions here, so that we can report the faulty
1053 instruction in the error message. */
1055 md_operand (expressionS
* exp
)
1057 if (in_my_get_expression
)
1058 exp
->X_op
= O_illegal
;
1061 /* Immediate values. */
1063 /* Generic immediate-value read function for use in directives.
1064 Accepts anything that 'expression' can fold to a constant.
1065 *val receives the number. */
1068 immediate_for_directive (int *val
)
1071 exp
.X_op
= O_illegal
;
1073 if (is_immediate_prefix (*input_line_pointer
))
1075 input_line_pointer
++;
1079 if (exp
.X_op
!= O_constant
)
1081 as_bad (_("expected #constant"));
1082 ignore_rest_of_line ();
1085 *val
= exp
.X_add_number
;
1090 /* Register parsing. */
1092 /* Generic register parser. CCP points to what should be the
1093 beginning of a register name. If it is indeed a valid register
1094 name, advance CCP over it and return the reg_entry structure;
1095 otherwise return NULL. Does not issue diagnostics. */
1097 static struct reg_entry
*
1098 arm_reg_parse_multi (char **ccp
)
1102 struct reg_entry
*reg
;
1104 #ifdef REGISTER_PREFIX
1105 if (*start
!= REGISTER_PREFIX
)
1109 #ifdef OPTIONAL_REGISTER_PREFIX
1110 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1115 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1120 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1122 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1132 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1133 enum arm_reg_type type
)
1135 /* Alternative syntaxes are accepted for a few register classes. */
1142 /* Generic coprocessor register names are allowed for these. */
1143 if (reg
&& reg
->type
== REG_TYPE_CN
)
1148 /* For backward compatibility, a bare number is valid here. */
1150 unsigned long processor
= strtoul (start
, ccp
, 10);
1151 if (*ccp
!= start
&& processor
<= 15)
1155 case REG_TYPE_MMXWC
:
1156 /* WC includes WCG. ??? I'm not sure this is true for all
1157 instructions that take WC registers. */
1158 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1169 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1170 return value is the register number or FAIL. */
1173 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1176 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1179 /* Do not allow a scalar (reg+index) to parse as a register. */
1180 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1183 if (reg
&& reg
->type
== type
)
1186 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1193 /* Parse a Neon type specifier. *STR should point at the leading '.'
1194 character. Does no verification at this stage that the type fits the opcode
1201 Can all be legally parsed by this function.
1203 Fills in neon_type struct pointer with parsed information, and updates STR
1204 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1205 type, FAIL if not. */
1208 parse_neon_type (struct neon_type
*type
, char **str
)
1215 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1217 enum neon_el_type thistype
= NT_untyped
;
1218 unsigned thissize
= -1u;
1225 /* Just a size without an explicit type. */
1229 switch (TOLOWER (*ptr
))
1231 case 'i': thistype
= NT_integer
; break;
1232 case 'f': thistype
= NT_float
; break;
1233 case 'p': thistype
= NT_poly
; break;
1234 case 's': thistype
= NT_signed
; break;
1235 case 'u': thistype
= NT_unsigned
; break;
1237 thistype
= NT_float
;
1242 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1248 /* .f is an abbreviation for .f32. */
1249 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1254 thissize
= strtoul (ptr
, &ptr
, 10);
1256 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1259 as_bad (_("bad size %d in type specifier"), thissize
);
1267 type
->el
[type
->elems
].type
= thistype
;
1268 type
->el
[type
->elems
].size
= thissize
;
1273 /* Empty/missing type is not a successful parse. */
1274 if (type
->elems
== 0)
1282 /* Errors may be set multiple times during parsing or bit encoding
1283 (particularly in the Neon bits), but usually the earliest error which is set
1284 will be the most meaningful. Avoid overwriting it with later (cascading)
1285 errors by calling this function. */
1288 first_error (const char *err
)
1294 /* Parse a single type, e.g. ".s32", leading period included. */
1296 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1299 struct neon_type optype
;
1303 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1305 if (optype
.elems
== 1)
1306 *vectype
= optype
.el
[0];
1309 first_error (_("only one type should be specified for operand"));
1315 first_error (_("vector type expected"));
1327 /* Special meanings for indices (which have a range of 0-7), which will fit into
1330 #define NEON_ALL_LANES 15
1331 #define NEON_INTERLEAVE_LANES 14
1333 /* Parse either a register or a scalar, with an optional type. Return the
1334 register number, and optionally fill in the actual type of the register
1335 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1336 type/index information in *TYPEINFO. */
1339 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1340 enum arm_reg_type
*rtype
,
1341 struct neon_typed_alias
*typeinfo
)
1344 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1345 struct neon_typed_alias atype
;
1346 struct neon_type_el parsetype
;
1350 atype
.eltype
.type
= NT_invtype
;
1351 atype
.eltype
.size
= -1;
1353 /* Try alternate syntax for some types of register. Note these are mutually
1354 exclusive with the Neon syntax extensions. */
1357 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1365 /* Undo polymorphism when a set of register types may be accepted. */
1366 if ((type
== REG_TYPE_NDQ
1367 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1368 || (type
== REG_TYPE_VFSD
1369 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1370 || (type
== REG_TYPE_NSDQ
1371 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1372 || reg
->type
== REG_TYPE_NQ
))
1373 || (type
== REG_TYPE_MMXWC
1374 && (reg
->type
== REG_TYPE_MMXWCG
)))
1375 type
= (enum arm_reg_type
) reg
->type
;
1377 if (type
!= reg
->type
)
1383 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1385 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1387 first_error (_("can't redefine type for operand"));
1390 atype
.defined
|= NTA_HASTYPE
;
1391 atype
.eltype
= parsetype
;
1394 if (skip_past_char (&str
, '[') == SUCCESS
)
1396 if (type
!= REG_TYPE_VFD
)
1398 first_error (_("only D registers may be indexed"));
1402 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1404 first_error (_("can't change index for operand"));
1408 atype
.defined
|= NTA_HASINDEX
;
1410 if (skip_past_char (&str
, ']') == SUCCESS
)
1411 atype
.index
= NEON_ALL_LANES
;
1416 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1418 if (exp
.X_op
!= O_constant
)
1420 first_error (_("constant expression required"));
1424 if (skip_past_char (&str
, ']') == FAIL
)
1427 atype
.index
= exp
.X_add_number
;
1442 /* Like arm_reg_parse, but allow allow the following extra features:
1443 - If RTYPE is non-zero, return the (possibly restricted) type of the
1444 register (e.g. Neon double or quad reg when either has been requested).
1445 - If this is a Neon vector type with additional type information, fill
1446 in the struct pointed to by VECTYPE (if non-NULL).
1447 This function will fault on encountering a scalar. */
1450 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1451 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1453 struct neon_typed_alias atype
;
1455 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1460 /* Do not allow a scalar (reg+index) to parse as a register. */
1461 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1463 first_error (_("register operand expected, but got scalar"));
1468 *vectype
= atype
.eltype
;
1475 #define NEON_SCALAR_REG(X) ((X) >> 4)
1476 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1478 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1479 have enough information to be able to do a good job bounds-checking. So, we
1480 just do easy checks here, and do further checks later. */
1483 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1487 struct neon_typed_alias atype
;
1489 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1491 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1494 if (atype
.index
== NEON_ALL_LANES
)
1496 first_error (_("scalar must have an index"));
1499 else if (atype
.index
>= 64 / elsize
)
1501 first_error (_("scalar index out of range"));
1506 *type
= atype
.eltype
;
1510 return reg
* 16 + atype
.index
;
1513 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1516 parse_reg_list (char ** strp
)
1518 char * str
= * strp
;
1522 /* We come back here if we get ranges concatenated by '+' or '|'. */
1537 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1539 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1549 first_error (_("bad range in register list"));
1553 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1555 if (range
& (1 << i
))
1557 (_("Warning: duplicated register (r%d) in register list"),
1565 if (range
& (1 << reg
))
1566 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1568 else if (reg
<= cur_reg
)
1569 as_tsktsk (_("Warning: register range not in ascending order"));
1574 while (skip_past_comma (&str
) != FAIL
1575 || (in_range
= 1, *str
++ == '-'));
1580 first_error (_("missing `}'"));
1588 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1591 if (exp
.X_op
== O_constant
)
1593 if (exp
.X_add_number
1594 != (exp
.X_add_number
& 0x0000ffff))
1596 inst
.error
= _("invalid register mask");
1600 if ((range
& exp
.X_add_number
) != 0)
1602 int regno
= range
& exp
.X_add_number
;
1605 regno
= (1 << regno
) - 1;
1607 (_("Warning: duplicated register (r%d) in register list"),
1611 range
|= exp
.X_add_number
;
1615 if (inst
.reloc
.type
!= 0)
1617 inst
.error
= _("expression too complex");
1621 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1622 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1623 inst
.reloc
.pc_rel
= 0;
1627 if (*str
== '|' || *str
== '+')
1633 while (another_range
);
1639 /* Types of registers in a list. */
1648 /* Parse a VFP register list. If the string is invalid return FAIL.
1649 Otherwise return the number of registers, and set PBASE to the first
1650 register. Parses registers of type ETYPE.
1651 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1652 - Q registers can be used to specify pairs of D registers
1653 - { } can be omitted from around a singleton register list
1654 FIXME: This is not implemented, as it would require backtracking in
1657 This could be done (the meaning isn't really ambiguous), but doesn't
1658 fit in well with the current parsing framework.
1659 - 32 D registers may be used (also true for VFPv3).
1660 FIXME: Types are ignored in these register lists, which is probably a
1664 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1669 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1673 unsigned long mask
= 0;
1678 inst
.error
= _("expecting {");
1687 regtype
= REG_TYPE_VFS
;
1692 regtype
= REG_TYPE_VFD
;
1695 case REGLIST_NEON_D
:
1696 regtype
= REG_TYPE_NDQ
;
1700 if (etype
!= REGLIST_VFP_S
)
1702 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1703 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1707 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1710 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1717 base_reg
= max_regs
;
1721 int setmask
= 1, addregs
= 1;
1723 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1725 if (new_base
== FAIL
)
1727 first_error (_(reg_expected_msgs
[regtype
]));
1731 if (new_base
>= max_regs
)
1733 first_error (_("register out of range in list"));
1737 /* Note: a value of 2 * n is returned for the register Q<n>. */
1738 if (regtype
== REG_TYPE_NQ
)
1744 if (new_base
< base_reg
)
1745 base_reg
= new_base
;
1747 if (mask
& (setmask
<< new_base
))
1749 first_error (_("invalid register list"));
1753 if ((mask
>> new_base
) != 0 && ! warned
)
1755 as_tsktsk (_("register list not in ascending order"));
1759 mask
|= setmask
<< new_base
;
1762 if (*str
== '-') /* We have the start of a range expression */
1768 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1771 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1775 if (high_range
>= max_regs
)
1777 first_error (_("register out of range in list"));
1781 if (regtype
== REG_TYPE_NQ
)
1782 high_range
= high_range
+ 1;
1784 if (high_range
<= new_base
)
1786 inst
.error
= _("register range not in ascending order");
1790 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1792 if (mask
& (setmask
<< new_base
))
1794 inst
.error
= _("invalid register list");
1798 mask
|= setmask
<< new_base
;
1803 while (skip_past_comma (&str
) != FAIL
);
1807 /* Sanity check -- should have raised a parse error above. */
1808 if (count
== 0 || count
> max_regs
)
1813 /* Final test -- the registers must be consecutive. */
1815 for (i
= 0; i
< count
; i
++)
1817 if ((mask
& (1u << i
)) == 0)
1819 inst
.error
= _("non-contiguous register range");
1829 /* True if two alias types are the same. */
1832 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1840 if (a
->defined
!= b
->defined
)
1843 if ((a
->defined
& NTA_HASTYPE
) != 0
1844 && (a
->eltype
.type
!= b
->eltype
.type
1845 || a
->eltype
.size
!= b
->eltype
.size
))
1848 if ((a
->defined
& NTA_HASINDEX
) != 0
1849 && (a
->index
!= b
->index
))
1855 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1856 The base register is put in *PBASE.
1857 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1859 The register stride (minus one) is put in bit 4 of the return value.
1860 Bits [6:5] encode the list length (minus one).
1861 The type of the list elements is put in *ELTYPE, if non-NULL. */
1863 #define NEON_LANE(X) ((X) & 0xf)
1864 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1865 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1868 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1869 struct neon_type_el
*eltype
)
1876 int leading_brace
= 0;
1877 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1879 const char *const incr_error
= _("register stride must be 1 or 2");
1880 const char *const type_error
= _("mismatched element/structure types in list");
1881 struct neon_typed_alias firsttype
;
1883 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1888 struct neon_typed_alias atype
;
1889 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1893 first_error (_(reg_expected_msgs
[rtype
]));
1900 if (rtype
== REG_TYPE_NQ
)
1907 else if (reg_incr
== -1)
1909 reg_incr
= getreg
- base_reg
;
1910 if (reg_incr
< 1 || reg_incr
> 2)
1912 first_error (_(incr_error
));
1916 else if (getreg
!= base_reg
+ reg_incr
* count
)
1918 first_error (_(incr_error
));
1922 if (! neon_alias_types_same (&atype
, &firsttype
))
1924 first_error (_(type_error
));
1928 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1932 struct neon_typed_alias htype
;
1933 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1935 lane
= NEON_INTERLEAVE_LANES
;
1936 else if (lane
!= NEON_INTERLEAVE_LANES
)
1938 first_error (_(type_error
));
1943 else if (reg_incr
!= 1)
1945 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1949 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1952 first_error (_(reg_expected_msgs
[rtype
]));
1955 if (! neon_alias_types_same (&htype
, &firsttype
))
1957 first_error (_(type_error
));
1960 count
+= hireg
+ dregs
- getreg
;
1964 /* If we're using Q registers, we can't use [] or [n] syntax. */
1965 if (rtype
== REG_TYPE_NQ
)
1971 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1975 else if (lane
!= atype
.index
)
1977 first_error (_(type_error
));
1981 else if (lane
== -1)
1982 lane
= NEON_INTERLEAVE_LANES
;
1983 else if (lane
!= NEON_INTERLEAVE_LANES
)
1985 first_error (_(type_error
));
1990 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1992 /* No lane set by [x]. We must be interleaving structures. */
1994 lane
= NEON_INTERLEAVE_LANES
;
1997 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
1998 || (count
> 1 && reg_incr
== -1))
2000 first_error (_("error parsing element/structure list"));
2004 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2006 first_error (_("expected }"));
2014 *eltype
= firsttype
.eltype
;
2019 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2022 /* Parse an explicit relocation suffix on an expression. This is
2023 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2024 arm_reloc_hsh contains no entries, so this function can only
2025 succeed if there is no () after the word. Returns -1 on error,
2026 BFD_RELOC_UNUSED if there wasn't any suffix. */
2028 parse_reloc (char **str
)
2030 struct reloc_entry
*r
;
2034 return BFD_RELOC_UNUSED
;
2039 while (*q
&& *q
!= ')' && *q
!= ',')
2044 if ((r
= (struct reloc_entry
*)
2045 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2052 /* Directives: register aliases. */
2054 static struct reg_entry
*
2055 insert_reg_alias (char *str
, int number
, int type
)
2057 struct reg_entry
*new_reg
;
2060 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2062 if (new_reg
->builtin
)
2063 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2065 /* Only warn about a redefinition if it's not defined as the
2067 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2068 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2073 name
= xstrdup (str
);
2074 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2076 new_reg
->name
= name
;
2077 new_reg
->number
= number
;
2078 new_reg
->type
= type
;
2079 new_reg
->builtin
= FALSE
;
2080 new_reg
->neon
= NULL
;
2082 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2089 insert_neon_reg_alias (char *str
, int number
, int type
,
2090 struct neon_typed_alias
*atype
)
2092 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2096 first_error (_("attempt to redefine typed alias"));
2102 reg
->neon
= (struct neon_typed_alias
*)
2103 xmalloc (sizeof (struct neon_typed_alias
));
2104 *reg
->neon
= *atype
;
2108 /* Look for the .req directive. This is of the form:
2110 new_register_name .req existing_register_name
2112 If we find one, or if it looks sufficiently like one that we want to
2113 handle any error here, return TRUE. Otherwise return FALSE. */
2116 create_register_alias (char * newname
, char *p
)
2118 struct reg_entry
*old
;
2119 char *oldname
, *nbuf
;
2122 /* The input scrubber ensures that whitespace after the mnemonic is
2123 collapsed to single spaces. */
2125 if (strncmp (oldname
, " .req ", 6) != 0)
2129 if (*oldname
== '\0')
2132 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2135 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2139 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2140 the desired alias name, and p points to its end. If not, then
2141 the desired alias name is in the global original_case_string. */
2142 #ifdef TC_CASE_SENSITIVE
2145 newname
= original_case_string
;
2146 nlen
= strlen (newname
);
2149 nbuf
= (char *) alloca (nlen
+ 1);
2150 memcpy (nbuf
, newname
, nlen
);
2153 /* Create aliases under the new name as stated; an all-lowercase
2154 version of the new name; and an all-uppercase version of the new
2156 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2158 for (p
= nbuf
; *p
; p
++)
2161 if (strncmp (nbuf
, newname
, nlen
))
2163 /* If this attempt to create an additional alias fails, do not bother
2164 trying to create the all-lower case alias. We will fail and issue
2165 a second, duplicate error message. This situation arises when the
2166 programmer does something like:
2169 The second .req creates the "Foo" alias but then fails to create
2170 the artificial FOO alias because it has already been created by the
2172 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2176 for (p
= nbuf
; *p
; p
++)
2179 if (strncmp (nbuf
, newname
, nlen
))
2180 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2186 /* Create a Neon typed/indexed register alias using directives, e.g.:
2191 These typed registers can be used instead of the types specified after the
2192 Neon mnemonic, so long as all operands given have types. Types can also be
2193 specified directly, e.g.:
2194 vadd d0.s32, d1.s32, d2.s32 */
2197 create_neon_reg_alias (char *newname
, char *p
)
2199 enum arm_reg_type basetype
;
2200 struct reg_entry
*basereg
;
2201 struct reg_entry mybasereg
;
2202 struct neon_type ntype
;
2203 struct neon_typed_alias typeinfo
;
2204 char *namebuf
, *nameend
;
2207 typeinfo
.defined
= 0;
2208 typeinfo
.eltype
.type
= NT_invtype
;
2209 typeinfo
.eltype
.size
= -1;
2210 typeinfo
.index
= -1;
2214 if (strncmp (p
, " .dn ", 5) == 0)
2215 basetype
= REG_TYPE_VFD
;
2216 else if (strncmp (p
, " .qn ", 5) == 0)
2217 basetype
= REG_TYPE_NQ
;
2226 basereg
= arm_reg_parse_multi (&p
);
2228 if (basereg
&& basereg
->type
!= basetype
)
2230 as_bad (_("bad type for register"));
2234 if (basereg
== NULL
)
2237 /* Try parsing as an integer. */
2238 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2239 if (exp
.X_op
!= O_constant
)
2241 as_bad (_("expression must be constant"));
2244 basereg
= &mybasereg
;
2245 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2251 typeinfo
= *basereg
->neon
;
2253 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2255 /* We got a type. */
2256 if (typeinfo
.defined
& NTA_HASTYPE
)
2258 as_bad (_("can't redefine the type of a register alias"));
2262 typeinfo
.defined
|= NTA_HASTYPE
;
2263 if (ntype
.elems
!= 1)
2265 as_bad (_("you must specify a single type only"));
2268 typeinfo
.eltype
= ntype
.el
[0];
2271 if (skip_past_char (&p
, '[') == SUCCESS
)
2274 /* We got a scalar index. */
2276 if (typeinfo
.defined
& NTA_HASINDEX
)
2278 as_bad (_("can't redefine the index of a scalar alias"));
2282 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2284 if (exp
.X_op
!= O_constant
)
2286 as_bad (_("scalar index must be constant"));
2290 typeinfo
.defined
|= NTA_HASINDEX
;
2291 typeinfo
.index
= exp
.X_add_number
;
2293 if (skip_past_char (&p
, ']') == FAIL
)
2295 as_bad (_("expecting ]"));
2300 namelen
= nameend
- newname
;
2301 namebuf
= (char *) alloca (namelen
+ 1);
2302 strncpy (namebuf
, newname
, namelen
);
2303 namebuf
[namelen
] = '\0';
2305 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2306 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2308 /* Insert name in all uppercase. */
2309 for (p
= namebuf
; *p
; p
++)
2312 if (strncmp (namebuf
, newname
, namelen
))
2313 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2314 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2316 /* Insert name in all lowercase. */
2317 for (p
= namebuf
; *p
; p
++)
2320 if (strncmp (namebuf
, newname
, namelen
))
2321 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2322 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2327 /* Should never be called, as .req goes between the alias and the
2328 register name, not at the beginning of the line. */
2331 s_req (int a ATTRIBUTE_UNUSED
)
2333 as_bad (_("invalid syntax for .req directive"));
2337 s_dn (int a ATTRIBUTE_UNUSED
)
2339 as_bad (_("invalid syntax for .dn directive"));
2343 s_qn (int a ATTRIBUTE_UNUSED
)
2345 as_bad (_("invalid syntax for .qn directive"));
2348 /* The .unreq directive deletes an alias which was previously defined
2349 by .req. For example:
2355 s_unreq (int a ATTRIBUTE_UNUSED
)
2360 name
= input_line_pointer
;
2362 while (*input_line_pointer
!= 0
2363 && *input_line_pointer
!= ' '
2364 && *input_line_pointer
!= '\n')
2365 ++input_line_pointer
;
2367 saved_char
= *input_line_pointer
;
2368 *input_line_pointer
= 0;
2371 as_bad (_("invalid syntax for .unreq directive"));
2374 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2378 as_bad (_("unknown register alias '%s'"), name
);
2379 else if (reg
->builtin
)
2380 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2387 hash_delete (arm_reg_hsh
, name
, FALSE
);
2388 free ((char *) reg
->name
);
2393 /* Also locate the all upper case and all lower case versions.
2394 Do not complain if we cannot find one or the other as it
2395 was probably deleted above. */
2397 nbuf
= strdup (name
);
2398 for (p
= nbuf
; *p
; p
++)
2400 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2403 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2404 free ((char *) reg
->name
);
2410 for (p
= nbuf
; *p
; p
++)
2412 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2415 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2416 free ((char *) reg
->name
);
2426 *input_line_pointer
= saved_char
;
2427 demand_empty_rest_of_line ();
2430 /* Directives: Instruction set selection. */
2433 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2434 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2435 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2436 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2438 /* Create a new mapping symbol for the transition to STATE. */
2441 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2444 const char * symname
;
2451 type
= BSF_NO_FLAGS
;
2455 type
= BSF_NO_FLAGS
;
2459 type
= BSF_NO_FLAGS
;
2465 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2466 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2471 THUMB_SET_FUNC (symbolP
, 0);
2472 ARM_SET_THUMB (symbolP
, 0);
2473 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2477 THUMB_SET_FUNC (symbolP
, 1);
2478 ARM_SET_THUMB (symbolP
, 1);
2479 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2487 /* Save the mapping symbols for future reference. Also check that
2488 we do not place two mapping symbols at the same offset within a
2489 frag. We'll handle overlap between frags in
2490 check_mapping_symbols. */
2493 know (frag
->tc_frag_data
.first_map
== NULL
);
2494 frag
->tc_frag_data
.first_map
= symbolP
;
2496 if (frag
->tc_frag_data
.last_map
!= NULL
)
2497 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) < S_GET_VALUE (symbolP
));
2498 frag
->tc_frag_data
.last_map
= symbolP
;
2501 /* We must sometimes convert a region marked as code to data during
2502 code alignment, if an odd number of bytes have to be padded. The
2503 code mapping symbol is pushed to an aligned address. */
2506 insert_data_mapping_symbol (enum mstate state
,
2507 valueT value
, fragS
*frag
, offsetT bytes
)
2509 /* If there was already a mapping symbol, remove it. */
2510 if (frag
->tc_frag_data
.last_map
!= NULL
2511 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2513 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2517 know (frag
->tc_frag_data
.first_map
== symp
);
2518 frag
->tc_frag_data
.first_map
= NULL
;
2520 frag
->tc_frag_data
.last_map
= NULL
;
2521 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2524 make_mapping_symbol (MAP_DATA
, value
, frag
);
2525 make_mapping_symbol (state
, value
+ bytes
, frag
);
2528 static void mapping_state_2 (enum mstate state
, int max_chars
);
2530 /* Set the mapping state to STATE. Only call this when about to
2531 emit some STATE bytes to the file. */
2534 mapping_state (enum mstate state
)
2536 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2538 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2540 if (mapstate
== state
)
2541 /* The mapping symbol has already been emitted.
2542 There is nothing else to do. */
2544 else if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2545 /* This case will be evaluated later in the next else. */
2547 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2548 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2550 /* Only add the symbol if the offset is > 0:
2551 if we're at the first frag, check it's size > 0;
2552 if we're not at the first frag, then for sure
2553 the offset is > 0. */
2554 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2555 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2558 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2561 mapping_state_2 (state
, 0);
2565 /* Same as mapping_state, but MAX_CHARS bytes have already been
2566 allocated. Put the mapping symbol that far back. */
2569 mapping_state_2 (enum mstate state
, int max_chars
)
2571 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2573 if (!SEG_NORMAL (now_seg
))
2576 if (mapstate
== state
)
2577 /* The mapping symbol has already been emitted.
2578 There is nothing else to do. */
2581 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2582 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2585 #define mapping_state(x) ((void)0)
2586 #define mapping_state_2(x, y) ((void)0)
2589 /* Find the real, Thumb encoded start of a Thumb function. */
2593 find_real_start (symbolS
* symbolP
)
2596 const char * name
= S_GET_NAME (symbolP
);
2597 symbolS
* new_target
;
2599 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2600 #define STUB_NAME ".real_start_of"
2605 /* The compiler may generate BL instructions to local labels because
2606 it needs to perform a branch to a far away location. These labels
2607 do not have a corresponding ".real_start_of" label. We check
2608 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2609 the ".real_start_of" convention for nonlocal branches. */
2610 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2613 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2614 new_target
= symbol_find (real_start
);
2616 if (new_target
== NULL
)
2618 as_warn (_("Failed to find real start of function: %s\n"), name
);
2619 new_target
= symbolP
;
2627 opcode_select (int width
)
2634 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2635 as_bad (_("selected processor does not support THUMB opcodes"));
2638 /* No need to force the alignment, since we will have been
2639 coming from ARM mode, which is word-aligned. */
2640 record_alignment (now_seg
, 1);
2647 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2648 as_bad (_("selected processor does not support ARM opcodes"));
2653 frag_align (2, 0, 0);
2655 record_alignment (now_seg
, 1);
2660 as_bad (_("invalid instruction size selected (%d)"), width
);
2665 s_arm (int ignore ATTRIBUTE_UNUSED
)
2668 demand_empty_rest_of_line ();
2672 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2675 demand_empty_rest_of_line ();
2679 s_code (int unused ATTRIBUTE_UNUSED
)
2683 temp
= get_absolute_expression ();
2688 opcode_select (temp
);
2692 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2697 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2699 /* If we are not already in thumb mode go into it, EVEN if
2700 the target processor does not support thumb instructions.
2701 This is used by gcc/config/arm/lib1funcs.asm for example
2702 to compile interworking support functions even if the
2703 target processor should not support interworking. */
2707 record_alignment (now_seg
, 1);
2710 demand_empty_rest_of_line ();
2714 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2718 /* The following label is the name/address of the start of a Thumb function.
2719 We need to know this for the interworking support. */
2720 label_is_thumb_function_name
= TRUE
;
2723 /* Perform a .set directive, but also mark the alias as
2724 being a thumb function. */
2727 s_thumb_set (int equiv
)
2729 /* XXX the following is a duplicate of the code for s_set() in read.c
2730 We cannot just call that code as we need to get at the symbol that
2737 /* Especial apologies for the random logic:
2738 This just grew, and could be parsed much more simply!
2740 name
= input_line_pointer
;
2741 delim
= get_symbol_end ();
2742 end_name
= input_line_pointer
;
2745 if (*input_line_pointer
!= ',')
2748 as_bad (_("expected comma after name \"%s\""), name
);
2750 ignore_rest_of_line ();
2754 input_line_pointer
++;
2757 if (name
[0] == '.' && name
[1] == '\0')
2759 /* XXX - this should not happen to .thumb_set. */
2763 if ((symbolP
= symbol_find (name
)) == NULL
2764 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2767 /* When doing symbol listings, play games with dummy fragments living
2768 outside the normal fragment chain to record the file and line info
2770 if (listing
& LISTING_SYMBOLS
)
2772 extern struct list_info_struct
* listing_tail
;
2773 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2775 memset (dummy_frag
, 0, sizeof (fragS
));
2776 dummy_frag
->fr_type
= rs_fill
;
2777 dummy_frag
->line
= listing_tail
;
2778 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2779 dummy_frag
->fr_symbol
= symbolP
;
2783 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2786 /* "set" symbols are local unless otherwise specified. */
2787 SF_SET_LOCAL (symbolP
);
2788 #endif /* OBJ_COFF */
2789 } /* Make a new symbol. */
2791 symbol_table_insert (symbolP
);
2796 && S_IS_DEFINED (symbolP
)
2797 && S_GET_SEGMENT (symbolP
) != reg_section
)
2798 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2800 pseudo_set (symbolP
);
2802 demand_empty_rest_of_line ();
2804 /* XXX Now we come to the Thumb specific bit of code. */
2806 THUMB_SET_FUNC (symbolP
, 1);
2807 ARM_SET_THUMB (symbolP
, 1);
2808 #if defined OBJ_ELF || defined OBJ_COFF
2809 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2813 /* Directives: Mode selection. */
2815 /* .syntax [unified|divided] - choose the new unified syntax
2816 (same for Arm and Thumb encoding, modulo slight differences in what
2817 can be represented) or the old divergent syntax for each mode. */
2819 s_syntax (int unused ATTRIBUTE_UNUSED
)
2823 name
= input_line_pointer
;
2824 delim
= get_symbol_end ();
2826 if (!strcasecmp (name
, "unified"))
2827 unified_syntax
= TRUE
;
2828 else if (!strcasecmp (name
, "divided"))
2829 unified_syntax
= FALSE
;
2832 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2835 *input_line_pointer
= delim
;
2836 demand_empty_rest_of_line ();
2839 /* Directives: sectioning and alignment. */
2841 /* Same as s_align_ptwo but align 0 => align 2. */
2844 s_align (int unused ATTRIBUTE_UNUSED
)
2849 long max_alignment
= 15;
2851 temp
= get_absolute_expression ();
2852 if (temp
> max_alignment
)
2853 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2856 as_bad (_("alignment negative. 0 assumed."));
2860 if (*input_line_pointer
== ',')
2862 input_line_pointer
++;
2863 temp_fill
= get_absolute_expression ();
2875 /* Only make a frag if we HAVE to. */
2876 if (temp
&& !need_pass_2
)
2878 if (!fill_p
&& subseg_text_p (now_seg
))
2879 frag_align_code (temp
, 0);
2881 frag_align (temp
, (int) temp_fill
, 0);
2883 demand_empty_rest_of_line ();
2885 record_alignment (now_seg
, temp
);
2889 s_bss (int ignore ATTRIBUTE_UNUSED
)
2891 /* We don't support putting frags in the BSS segment, we fake it by
2892 marking in_bss, then looking at s_skip for clues. */
2893 subseg_set (bss_section
, 0);
2894 demand_empty_rest_of_line ();
2896 #ifdef md_elf_section_change_hook
2897 md_elf_section_change_hook ();
2902 s_even (int ignore ATTRIBUTE_UNUSED
)
2904 /* Never make frag if expect extra pass. */
2906 frag_align (1, 0, 0);
2908 record_alignment (now_seg
, 1);
2910 demand_empty_rest_of_line ();
2913 /* Directives: Literal pools. */
2915 static literal_pool
*
2916 find_literal_pool (void)
2918 literal_pool
* pool
;
2920 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2922 if (pool
->section
== now_seg
2923 && pool
->sub_section
== now_subseg
)
2930 static literal_pool
*
2931 find_or_make_literal_pool (void)
2933 /* Next literal pool ID number. */
2934 static unsigned int latest_pool_num
= 1;
2935 literal_pool
* pool
;
2937 pool
= find_literal_pool ();
2941 /* Create a new pool. */
2942 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
2946 pool
->next_free_entry
= 0;
2947 pool
->section
= now_seg
;
2948 pool
->sub_section
= now_subseg
;
2949 pool
->next
= list_of_pools
;
2950 pool
->symbol
= NULL
;
2952 /* Add it to the list. */
2953 list_of_pools
= pool
;
2956 /* New pools, and emptied pools, will have a NULL symbol. */
2957 if (pool
->symbol
== NULL
)
2959 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2960 (valueT
) 0, &zero_address_frag
);
2961 pool
->id
= latest_pool_num
++;
2968 /* Add the literal in the global 'inst'
2969 structure to the relevant literal pool. */
2972 add_to_lit_pool (void)
2974 literal_pool
* pool
;
2977 pool
= find_or_make_literal_pool ();
2979 /* Check if this literal value is already in the pool. */
2980 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2982 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2983 && (inst
.reloc
.exp
.X_op
== O_constant
)
2984 && (pool
->literals
[entry
].X_add_number
2985 == inst
.reloc
.exp
.X_add_number
)
2986 && (pool
->literals
[entry
].X_unsigned
2987 == inst
.reloc
.exp
.X_unsigned
))
2990 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2991 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2992 && (pool
->literals
[entry
].X_add_number
2993 == inst
.reloc
.exp
.X_add_number
)
2994 && (pool
->literals
[entry
].X_add_symbol
2995 == inst
.reloc
.exp
.X_add_symbol
)
2996 && (pool
->literals
[entry
].X_op_symbol
2997 == inst
.reloc
.exp
.X_op_symbol
))
3001 /* Do we need to create a new entry? */
3002 if (entry
== pool
->next_free_entry
)
3004 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3006 inst
.error
= _("literal pool overflow");
3010 pool
->literals
[entry
] = inst
.reloc
.exp
;
3011 pool
->next_free_entry
+= 1;
3014 inst
.reloc
.exp
.X_op
= O_symbol
;
3015 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3016 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3021 /* Can't use symbol_new here, so have to create a symbol and then at
3022 a later date assign it a value. Thats what these functions do. */
3025 symbol_locate (symbolS
* symbolP
,
3026 const char * name
, /* It is copied, the caller can modify. */
3027 segT segment
, /* Segment identifier (SEG_<something>). */
3028 valueT valu
, /* Symbol value. */
3029 fragS
* frag
) /* Associated fragment. */
3031 unsigned int name_length
;
3032 char * preserved_copy_of_name
;
3034 name_length
= strlen (name
) + 1; /* +1 for \0. */
3035 obstack_grow (¬es
, name
, name_length
);
3036 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3038 #ifdef tc_canonicalize_symbol_name
3039 preserved_copy_of_name
=
3040 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3043 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3045 S_SET_SEGMENT (symbolP
, segment
);
3046 S_SET_VALUE (symbolP
, valu
);
3047 symbol_clear_list_pointers (symbolP
);
3049 symbol_set_frag (symbolP
, frag
);
3051 /* Link to end of symbol chain. */
3053 extern int symbol_table_frozen
;
3055 if (symbol_table_frozen
)
3059 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3061 obj_symbol_new_hook (symbolP
);
3063 #ifdef tc_symbol_new_hook
3064 tc_symbol_new_hook (symbolP
);
3068 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3069 #endif /* DEBUG_SYMS */
3074 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3077 literal_pool
* pool
;
3080 pool
= find_literal_pool ();
3082 || pool
->symbol
== NULL
3083 || pool
->next_free_entry
== 0)
3086 mapping_state (MAP_DATA
);
3088 /* Align pool as you have word accesses.
3089 Only make a frag if we have to. */
3091 frag_align (2, 0, 0);
3093 record_alignment (now_seg
, 2);
3095 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3097 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3098 (valueT
) frag_now_fix (), frag_now
);
3099 symbol_table_insert (pool
->symbol
);
3101 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3103 #if defined OBJ_COFF || defined OBJ_ELF
3104 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3107 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3108 /* First output the expression in the instruction to the pool. */
3109 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3111 /* Mark the pool as empty. */
3112 pool
->next_free_entry
= 0;
3113 pool
->symbol
= NULL
;
3117 /* Forward declarations for functions below, in the MD interface
3119 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3120 static valueT
create_unwind_entry (int);
3121 static void start_unwind_section (const segT
, int);
3122 static void add_unwind_opcode (valueT
, int);
3123 static void flush_pending_unwind (void);
3125 /* Directives: Data. */
3128 s_arm_elf_cons (int nbytes
)
3132 #ifdef md_flush_pending_output
3133 md_flush_pending_output ();
3136 if (is_it_end_of_statement ())
3138 demand_empty_rest_of_line ();
3142 #ifdef md_cons_align
3143 md_cons_align (nbytes
);
3146 mapping_state (MAP_DATA
);
3150 char *base
= input_line_pointer
;
3154 if (exp
.X_op
!= O_symbol
)
3155 emit_expr (&exp
, (unsigned int) nbytes
);
3158 char *before_reloc
= input_line_pointer
;
3159 reloc
= parse_reloc (&input_line_pointer
);
3162 as_bad (_("unrecognized relocation suffix"));
3163 ignore_rest_of_line ();
3166 else if (reloc
== BFD_RELOC_UNUSED
)
3167 emit_expr (&exp
, (unsigned int) nbytes
);
3170 reloc_howto_type
*howto
= (reloc_howto_type
*)
3171 bfd_reloc_type_lookup (stdoutput
,
3172 (bfd_reloc_code_real_type
) reloc
);
3173 int size
= bfd_get_reloc_size (howto
);
3175 if (reloc
== BFD_RELOC_ARM_PLT32
)
3177 as_bad (_("(plt) is only valid on branch targets"));
3178 reloc
= BFD_RELOC_UNUSED
;
3183 as_bad (_("%s relocations do not fit in %d bytes"),
3184 howto
->name
, nbytes
);
3187 /* We've parsed an expression stopping at O_symbol.
3188 But there may be more expression left now that we
3189 have parsed the relocation marker. Parse it again.
3190 XXX Surely there is a cleaner way to do this. */
3191 char *p
= input_line_pointer
;
3193 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3194 memcpy (save_buf
, base
, input_line_pointer
- base
);
3195 memmove (base
+ (input_line_pointer
- before_reloc
),
3196 base
, before_reloc
- base
);
3198 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3200 memcpy (base
, save_buf
, p
- base
);
3202 offset
= nbytes
- size
;
3203 p
= frag_more ((int) nbytes
);
3204 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3205 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3210 while (*input_line_pointer
++ == ',');
3212 /* Put terminator back into stream. */
3213 input_line_pointer
--;
3214 demand_empty_rest_of_line ();
3217 /* Emit an expression containing a 32-bit thumb instruction.
3218 Implementation based on put_thumb32_insn. */
3221 emit_thumb32_expr (expressionS
* exp
)
3223 expressionS exp_high
= *exp
;
3225 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3226 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3227 exp
->X_add_number
&= 0xffff;
3228 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3231 /* Guess the instruction size based on the opcode. */
3234 thumb_insn_size (int opcode
)
3236 if ((unsigned int) opcode
< 0xe800u
)
3238 else if ((unsigned int) opcode
>= 0xe8000000u
)
3245 emit_insn (expressionS
*exp
, int nbytes
)
3249 if (exp
->X_op
== O_constant
)
3254 size
= thumb_insn_size (exp
->X_add_number
);
3258 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3260 as_bad (_(".inst.n operand too big. "\
3261 "Use .inst.w instead"));
3266 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3267 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3269 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3271 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3272 emit_thumb32_expr (exp
);
3274 emit_expr (exp
, (unsigned int) size
);
3276 it_fsm_post_encode ();
3280 as_bad (_("cannot determine Thumb instruction size. " \
3281 "Use .inst.n/.inst.w instead"));
3284 as_bad (_("constant expression required"));
3289 /* Like s_arm_elf_cons but do not use md_cons_align and
3290 set the mapping state to MAP_ARM/MAP_THUMB. */
3293 s_arm_elf_inst (int nbytes
)
3295 if (is_it_end_of_statement ())
3297 demand_empty_rest_of_line ();
3301 /* Calling mapping_state () here will not change ARM/THUMB,
3302 but will ensure not to be in DATA state. */
3305 mapping_state (MAP_THUMB
);
3310 as_bad (_("width suffixes are invalid in ARM mode"));
3311 ignore_rest_of_line ();
3317 mapping_state (MAP_ARM
);
3326 if (! emit_insn (& exp
, nbytes
))
3328 ignore_rest_of_line ();
3332 while (*input_line_pointer
++ == ',');
3334 /* Put terminator back into stream. */
3335 input_line_pointer
--;
3336 demand_empty_rest_of_line ();
3339 /* Parse a .rel31 directive. */
3342 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3349 if (*input_line_pointer
== '1')
3350 highbit
= 0x80000000;
3351 else if (*input_line_pointer
!= '0')
3352 as_bad (_("expected 0 or 1"));
3354 input_line_pointer
++;
3355 if (*input_line_pointer
!= ',')
3356 as_bad (_("missing comma"));
3357 input_line_pointer
++;
3359 #ifdef md_flush_pending_output
3360 md_flush_pending_output ();
3363 #ifdef md_cons_align
3367 mapping_state (MAP_DATA
);
3372 md_number_to_chars (p
, highbit
, 4);
3373 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3374 BFD_RELOC_ARM_PREL31
);
3376 demand_empty_rest_of_line ();
3379 /* Directives: AEABI stack-unwind tables. */
3381 /* Parse an unwind_fnstart directive. Simply records the current location. */
3384 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3386 demand_empty_rest_of_line ();
3387 if (unwind
.proc_start
)
3389 as_bad (_("duplicate .fnstart directive"));
3393 /* Mark the start of the function. */
3394 unwind
.proc_start
= expr_build_dot ();
3396 /* Reset the rest of the unwind info. */
3397 unwind
.opcode_count
= 0;
3398 unwind
.table_entry
= NULL
;
3399 unwind
.personality_routine
= NULL
;
3400 unwind
.personality_index
= -1;
3401 unwind
.frame_size
= 0;
3402 unwind
.fp_offset
= 0;
3403 unwind
.fp_reg
= REG_SP
;
3405 unwind
.sp_restored
= 0;
3409 /* Parse a handlerdata directive. Creates the exception handling table entry
3410 for the function. */
3413 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3415 demand_empty_rest_of_line ();
3416 if (!unwind
.proc_start
)
3417 as_bad (MISSING_FNSTART
);
3419 if (unwind
.table_entry
)
3420 as_bad (_("duplicate .handlerdata directive"));
3422 create_unwind_entry (1);
3425 /* Parse an unwind_fnend directive. Generates the index table entry. */
3428 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3433 unsigned int marked_pr_dependency
;
3435 demand_empty_rest_of_line ();
3437 if (!unwind
.proc_start
)
3439 as_bad (_(".fnend directive without .fnstart"));
3443 /* Add eh table entry. */
3444 if (unwind
.table_entry
== NULL
)
3445 val
= create_unwind_entry (0);
3449 /* Add index table entry. This is two words. */
3450 start_unwind_section (unwind
.saved_seg
, 1);
3451 frag_align (2, 0, 0);
3452 record_alignment (now_seg
, 2);
3454 ptr
= frag_more (8);
3455 where
= frag_now_fix () - 8;
3457 /* Self relative offset of the function start. */
3458 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3459 BFD_RELOC_ARM_PREL31
);
3461 /* Indicate dependency on EHABI-defined personality routines to the
3462 linker, if it hasn't been done already. */
3463 marked_pr_dependency
3464 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3465 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3466 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3468 static const char *const name
[] =
3470 "__aeabi_unwind_cpp_pr0",
3471 "__aeabi_unwind_cpp_pr1",
3472 "__aeabi_unwind_cpp_pr2"
3474 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3475 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3476 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3477 |= 1 << unwind
.personality_index
;
3481 /* Inline exception table entry. */
3482 md_number_to_chars (ptr
+ 4, val
, 4);
3484 /* Self relative offset of the table entry. */
3485 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3486 BFD_RELOC_ARM_PREL31
);
3488 /* Restore the original section. */
3489 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3491 unwind
.proc_start
= NULL
;
3495 /* Parse an unwind_cantunwind directive. */
3498 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3500 demand_empty_rest_of_line ();
3501 if (!unwind
.proc_start
)
3502 as_bad (MISSING_FNSTART
);
3504 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3505 as_bad (_("personality routine specified for cantunwind frame"));
3507 unwind
.personality_index
= -2;
3511 /* Parse a personalityindex directive. */
3514 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3518 if (!unwind
.proc_start
)
3519 as_bad (MISSING_FNSTART
);
3521 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3522 as_bad (_("duplicate .personalityindex directive"));
3526 if (exp
.X_op
!= O_constant
3527 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3529 as_bad (_("bad personality routine number"));
3530 ignore_rest_of_line ();
3534 unwind
.personality_index
= exp
.X_add_number
;
3536 demand_empty_rest_of_line ();
3540 /* Parse a personality directive. */
3543 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3547 if (!unwind
.proc_start
)
3548 as_bad (MISSING_FNSTART
);
3550 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3551 as_bad (_("duplicate .personality directive"));
3553 name
= input_line_pointer
;
3554 c
= get_symbol_end ();
3555 p
= input_line_pointer
;
3556 unwind
.personality_routine
= symbol_find_or_make (name
);
3558 demand_empty_rest_of_line ();
3562 /* Parse a directive saving core registers. */
3565 s_arm_unwind_save_core (void)
3571 range
= parse_reg_list (&input_line_pointer
);
3574 as_bad (_("expected register list"));
3575 ignore_rest_of_line ();
3579 demand_empty_rest_of_line ();
3581 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3582 into .unwind_save {..., sp...}. We aren't bothered about the value of
3583 ip because it is clobbered by calls. */
3584 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3585 && (range
& 0x3000) == 0x1000)
3587 unwind
.opcode_count
--;
3588 unwind
.sp_restored
= 0;
3589 range
= (range
| 0x2000) & ~0x1000;
3590 unwind
.pending_offset
= 0;
3596 /* See if we can use the short opcodes. These pop a block of up to 8
3597 registers starting with r4, plus maybe r14. */
3598 for (n
= 0; n
< 8; n
++)
3600 /* Break at the first non-saved register. */
3601 if ((range
& (1 << (n
+ 4))) == 0)
3604 /* See if there are any other bits set. */
3605 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3607 /* Use the long form. */
3608 op
= 0x8000 | ((range
>> 4) & 0xfff);
3609 add_unwind_opcode (op
, 2);
3613 /* Use the short form. */
3615 op
= 0xa8; /* Pop r14. */
3617 op
= 0xa0; /* Do not pop r14. */
3619 add_unwind_opcode (op
, 1);
3626 op
= 0xb100 | (range
& 0xf);
3627 add_unwind_opcode (op
, 2);
3630 /* Record the number of bytes pushed. */
3631 for (n
= 0; n
< 16; n
++)
3633 if (range
& (1 << n
))
3634 unwind
.frame_size
+= 4;
3639 /* Parse a directive saving FPA registers. */
3642 s_arm_unwind_save_fpa (int reg
)
3648 /* Get Number of registers to transfer. */
3649 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3652 exp
.X_op
= O_illegal
;
3654 if (exp
.X_op
!= O_constant
)
3656 as_bad (_("expected , <constant>"));
3657 ignore_rest_of_line ();
3661 num_regs
= exp
.X_add_number
;
3663 if (num_regs
< 1 || num_regs
> 4)
3665 as_bad (_("number of registers must be in the range [1:4]"));
3666 ignore_rest_of_line ();
3670 demand_empty_rest_of_line ();
3675 op
= 0xb4 | (num_regs
- 1);
3676 add_unwind_opcode (op
, 1);
3681 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3682 add_unwind_opcode (op
, 2);
3684 unwind
.frame_size
+= num_regs
* 12;
3688 /* Parse a directive saving VFP registers for ARMv6 and above. */
3691 s_arm_unwind_save_vfp_armv6 (void)
3696 int num_vfpv3_regs
= 0;
3697 int num_regs_below_16
;
3699 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3702 as_bad (_("expected register list"));
3703 ignore_rest_of_line ();
3707 demand_empty_rest_of_line ();
3709 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3710 than FSTMX/FLDMX-style ones). */
3712 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3714 num_vfpv3_regs
= count
;
3715 else if (start
+ count
> 16)
3716 num_vfpv3_regs
= start
+ count
- 16;
3718 if (num_vfpv3_regs
> 0)
3720 int start_offset
= start
> 16 ? start
- 16 : 0;
3721 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3722 add_unwind_opcode (op
, 2);
3725 /* Generate opcode for registers numbered in the range 0 .. 15. */
3726 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3727 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3728 if (num_regs_below_16
> 0)
3730 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3731 add_unwind_opcode (op
, 2);
3734 unwind
.frame_size
+= count
* 8;
3738 /* Parse a directive saving VFP registers for pre-ARMv6. */
3741 s_arm_unwind_save_vfp (void)
3747 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3750 as_bad (_("expected register list"));
3751 ignore_rest_of_line ();
3755 demand_empty_rest_of_line ();
3760 op
= 0xb8 | (count
- 1);
3761 add_unwind_opcode (op
, 1);
3766 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3767 add_unwind_opcode (op
, 2);
3769 unwind
.frame_size
+= count
* 8 + 4;
3773 /* Parse a directive saving iWMMXt data registers. */
3776 s_arm_unwind_save_mmxwr (void)
3784 if (*input_line_pointer
== '{')
3785 input_line_pointer
++;
3789 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3793 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3798 as_tsktsk (_("register list not in ascending order"));
3801 if (*input_line_pointer
== '-')
3803 input_line_pointer
++;
3804 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3807 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3810 else if (reg
>= hi_reg
)
3812 as_bad (_("bad register range"));
3815 for (; reg
< hi_reg
; reg
++)
3819 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3821 if (*input_line_pointer
== '}')
3822 input_line_pointer
++;
3824 demand_empty_rest_of_line ();
3826 /* Generate any deferred opcodes because we're going to be looking at
3828 flush_pending_unwind ();
3830 for (i
= 0; i
< 16; i
++)
3832 if (mask
& (1 << i
))
3833 unwind
.frame_size
+= 8;
3836 /* Attempt to combine with a previous opcode. We do this because gcc
3837 likes to output separate unwind directives for a single block of
3839 if (unwind
.opcode_count
> 0)
3841 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3842 if ((i
& 0xf8) == 0xc0)
3845 /* Only merge if the blocks are contiguous. */
3848 if ((mask
& 0xfe00) == (1 << 9))
3850 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3851 unwind
.opcode_count
--;
3854 else if (i
== 6 && unwind
.opcode_count
>= 2)
3856 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3860 op
= 0xffff << (reg
- 1);
3862 && ((mask
& op
) == (1u << (reg
- 1))))
3864 op
= (1 << (reg
+ i
+ 1)) - 1;
3865 op
&= ~((1 << reg
) - 1);
3867 unwind
.opcode_count
-= 2;
3874 /* We want to generate opcodes in the order the registers have been
3875 saved, ie. descending order. */
3876 for (reg
= 15; reg
>= -1; reg
--)
3878 /* Save registers in blocks. */
3880 || !(mask
& (1 << reg
)))
3882 /* We found an unsaved reg. Generate opcodes to save the
3889 op
= 0xc0 | (hi_reg
- 10);
3890 add_unwind_opcode (op
, 1);
3895 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3896 add_unwind_opcode (op
, 2);
3905 ignore_rest_of_line ();
3909 s_arm_unwind_save_mmxwcg (void)
3916 if (*input_line_pointer
== '{')
3917 input_line_pointer
++;
3921 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3925 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3931 as_tsktsk (_("register list not in ascending order"));
3934 if (*input_line_pointer
== '-')
3936 input_line_pointer
++;
3937 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3940 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3943 else if (reg
>= hi_reg
)
3945 as_bad (_("bad register range"));
3948 for (; reg
< hi_reg
; reg
++)
3952 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3954 if (*input_line_pointer
== '}')
3955 input_line_pointer
++;
3957 demand_empty_rest_of_line ();
3959 /* Generate any deferred opcodes because we're going to be looking at
3961 flush_pending_unwind ();
3963 for (reg
= 0; reg
< 16; reg
++)
3965 if (mask
& (1 << reg
))
3966 unwind
.frame_size
+= 4;
3969 add_unwind_opcode (op
, 2);
3972 ignore_rest_of_line ();
3976 /* Parse an unwind_save directive.
3977 If the argument is non-zero, this is a .vsave directive. */
3980 s_arm_unwind_save (int arch_v6
)
3983 struct reg_entry
*reg
;
3984 bfd_boolean had_brace
= FALSE
;
3986 if (!unwind
.proc_start
)
3987 as_bad (MISSING_FNSTART
);
3989 /* Figure out what sort of save we have. */
3990 peek
= input_line_pointer
;
3998 reg
= arm_reg_parse_multi (&peek
);
4002 as_bad (_("register expected"));
4003 ignore_rest_of_line ();
4012 as_bad (_("FPA .unwind_save does not take a register list"));
4013 ignore_rest_of_line ();
4016 input_line_pointer
= peek
;
4017 s_arm_unwind_save_fpa (reg
->number
);
4020 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4023 s_arm_unwind_save_vfp_armv6 ();
4025 s_arm_unwind_save_vfp ();
4027 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4028 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4031 as_bad (_(".unwind_save does not support this kind of register"));
4032 ignore_rest_of_line ();
4037 /* Parse an unwind_movsp directive. */
4040 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4046 if (!unwind
.proc_start
)
4047 as_bad (MISSING_FNSTART
);
4049 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4052 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4053 ignore_rest_of_line ();
4057 /* Optional constant. */
4058 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4060 if (immediate_for_directive (&offset
) == FAIL
)
4066 demand_empty_rest_of_line ();
4068 if (reg
== REG_SP
|| reg
== REG_PC
)
4070 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4074 if (unwind
.fp_reg
!= REG_SP
)
4075 as_bad (_("unexpected .unwind_movsp directive"));
4077 /* Generate opcode to restore the value. */
4079 add_unwind_opcode (op
, 1);
4081 /* Record the information for later. */
4082 unwind
.fp_reg
= reg
;
4083 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4084 unwind
.sp_restored
= 1;
4087 /* Parse an unwind_pad directive. */
4090 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4094 if (!unwind
.proc_start
)
4095 as_bad (MISSING_FNSTART
);
4097 if (immediate_for_directive (&offset
) == FAIL
)
4102 as_bad (_("stack increment must be multiple of 4"));
4103 ignore_rest_of_line ();
4107 /* Don't generate any opcodes, just record the details for later. */
4108 unwind
.frame_size
+= offset
;
4109 unwind
.pending_offset
+= offset
;
4111 demand_empty_rest_of_line ();
4114 /* Parse an unwind_setfp directive. */
4117 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4123 if (!unwind
.proc_start
)
4124 as_bad (MISSING_FNSTART
);
4126 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4127 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4130 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4132 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4134 as_bad (_("expected <reg>, <reg>"));
4135 ignore_rest_of_line ();
4139 /* Optional constant. */
4140 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4142 if (immediate_for_directive (&offset
) == FAIL
)
4148 demand_empty_rest_of_line ();
4150 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4152 as_bad (_("register must be either sp or set by a previous"
4153 "unwind_movsp directive"));
4157 /* Don't generate any opcodes, just record the information for later. */
4158 unwind
.fp_reg
= fp_reg
;
4160 if (sp_reg
== REG_SP
)
4161 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4163 unwind
.fp_offset
-= offset
;
4166 /* Parse an unwind_raw directive. */
4169 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4172 /* This is an arbitrary limit. */
4173 unsigned char op
[16];
4176 if (!unwind
.proc_start
)
4177 as_bad (MISSING_FNSTART
);
4180 if (exp
.X_op
== O_constant
4181 && skip_past_comma (&input_line_pointer
) != FAIL
)
4183 unwind
.frame_size
+= exp
.X_add_number
;
4187 exp
.X_op
= O_illegal
;
4189 if (exp
.X_op
!= O_constant
)
4191 as_bad (_("expected <offset>, <opcode>"));
4192 ignore_rest_of_line ();
4198 /* Parse the opcode. */
4203 as_bad (_("unwind opcode too long"));
4204 ignore_rest_of_line ();
4206 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4208 as_bad (_("invalid unwind opcode"));
4209 ignore_rest_of_line ();
4212 op
[count
++] = exp
.X_add_number
;
4214 /* Parse the next byte. */
4215 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4221 /* Add the opcode bytes in reverse order. */
4223 add_unwind_opcode (op
[count
], 1);
4225 demand_empty_rest_of_line ();
4229 /* Parse a .eabi_attribute directive. */
4232 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4234 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4236 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4237 attributes_set_explicitly
[tag
] = 1;
4239 #endif /* OBJ_ELF */
4241 static void s_arm_arch (int);
4242 static void s_arm_object_arch (int);
4243 static void s_arm_cpu (int);
4244 static void s_arm_fpu (int);
4249 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4256 if (exp
.X_op
== O_symbol
)
4257 exp
.X_op
= O_secrel
;
4259 emit_expr (&exp
, 4);
4261 while (*input_line_pointer
++ == ',');
4263 input_line_pointer
--;
4264 demand_empty_rest_of_line ();
4268 /* This table describes all the machine specific pseudo-ops the assembler
4269 has to support. The fields are:
4270 pseudo-op name without dot
4271 function to call to execute this pseudo-op
4272 Integer arg to pass to the function. */
4274 const pseudo_typeS md_pseudo_table
[] =
4276 /* Never called because '.req' does not start a line. */
4277 { "req", s_req
, 0 },
4278 /* Following two are likewise never called. */
4281 { "unreq", s_unreq
, 0 },
4282 { "bss", s_bss
, 0 },
4283 { "align", s_align
, 0 },
4284 { "arm", s_arm
, 0 },
4285 { "thumb", s_thumb
, 0 },
4286 { "code", s_code
, 0 },
4287 { "force_thumb", s_force_thumb
, 0 },
4288 { "thumb_func", s_thumb_func
, 0 },
4289 { "thumb_set", s_thumb_set
, 0 },
4290 { "even", s_even
, 0 },
4291 { "ltorg", s_ltorg
, 0 },
4292 { "pool", s_ltorg
, 0 },
4293 { "syntax", s_syntax
, 0 },
4294 { "cpu", s_arm_cpu
, 0 },
4295 { "arch", s_arm_arch
, 0 },
4296 { "object_arch", s_arm_object_arch
, 0 },
4297 { "fpu", s_arm_fpu
, 0 },
4299 { "word", s_arm_elf_cons
, 4 },
4300 { "long", s_arm_elf_cons
, 4 },
4301 { "inst.n", s_arm_elf_inst
, 2 },
4302 { "inst.w", s_arm_elf_inst
, 4 },
4303 { "inst", s_arm_elf_inst
, 0 },
4304 { "rel31", s_arm_rel31
, 0 },
4305 { "fnstart", s_arm_unwind_fnstart
, 0 },
4306 { "fnend", s_arm_unwind_fnend
, 0 },
4307 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4308 { "personality", s_arm_unwind_personality
, 0 },
4309 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4310 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4311 { "save", s_arm_unwind_save
, 0 },
4312 { "vsave", s_arm_unwind_save
, 1 },
4313 { "movsp", s_arm_unwind_movsp
, 0 },
4314 { "pad", s_arm_unwind_pad
, 0 },
4315 { "setfp", s_arm_unwind_setfp
, 0 },
4316 { "unwind_raw", s_arm_unwind_raw
, 0 },
4317 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4321 /* These are used for dwarf. */
4325 /* These are used for dwarf2. */
4326 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4327 { "loc", dwarf2_directive_loc
, 0 },
4328 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4330 { "extend", float_cons
, 'x' },
4331 { "ldouble", float_cons
, 'x' },
4332 { "packed", float_cons
, 'p' },
4334 {"secrel32", pe_directive_secrel
, 0},
4339 /* Parser functions used exclusively in instruction operands. */
4341 /* Generic immediate-value read function for use in insn parsing.
4342 STR points to the beginning of the immediate (the leading #);
4343 VAL receives the value; if the value is outside [MIN, MAX]
4344 issue an error. PREFIX_OPT is true if the immediate prefix is
4348 parse_immediate (char **str
, int *val
, int min
, int max
,
4349 bfd_boolean prefix_opt
)
4352 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4353 if (exp
.X_op
!= O_constant
)
4355 inst
.error
= _("constant expression required");
4359 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4361 inst
.error
= _("immediate value out of range");
4365 *val
= exp
.X_add_number
;
4369 /* Less-generic immediate-value read function with the possibility of loading a
4370 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4371 instructions. Puts the result directly in inst.operands[i]. */
4374 parse_big_immediate (char **str
, int i
)
4379 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4381 if (exp
.X_op
== O_constant
)
4383 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4384 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4385 O_constant. We have to be careful not to break compilation for
4386 32-bit X_add_number, though. */
4387 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4389 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4390 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4391 inst
.operands
[i
].regisimm
= 1;
4394 else if (exp
.X_op
== O_big
4395 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4396 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4398 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4399 /* Bignums have their least significant bits in
4400 generic_bignum[0]. Make sure we put 32 bits in imm and
4401 32 bits in reg, in a (hopefully) portable way. */
4402 gas_assert (parts
!= 0);
4403 inst
.operands
[i
].imm
= 0;
4404 for (j
= 0; j
< parts
; j
++, idx
++)
4405 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4406 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4407 inst
.operands
[i
].reg
= 0;
4408 for (j
= 0; j
< parts
; j
++, idx
++)
4409 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4410 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4411 inst
.operands
[i
].regisimm
= 1;
4421 /* Returns the pseudo-register number of an FPA immediate constant,
4422 or FAIL if there isn't a valid constant here. */
4425 parse_fpa_immediate (char ** str
)
4427 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4433 /* First try and match exact strings, this is to guarantee
4434 that some formats will work even for cross assembly. */
4436 for (i
= 0; fp_const
[i
]; i
++)
4438 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4442 *str
+= strlen (fp_const
[i
]);
4443 if (is_end_of_line
[(unsigned char) **str
])
4449 /* Just because we didn't get a match doesn't mean that the constant
4450 isn't valid, just that it is in a format that we don't
4451 automatically recognize. Try parsing it with the standard
4452 expression routines. */
4454 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4456 /* Look for a raw floating point number. */
4457 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4458 && is_end_of_line
[(unsigned char) *save_in
])
4460 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4462 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4464 if (words
[j
] != fp_values
[i
][j
])
4468 if (j
== MAX_LITTLENUMS
)
4476 /* Try and parse a more complex expression, this will probably fail
4477 unless the code uses a floating point prefix (eg "0f"). */
4478 save_in
= input_line_pointer
;
4479 input_line_pointer
= *str
;
4480 if (expression (&exp
) == absolute_section
4481 && exp
.X_op
== O_big
4482 && exp
.X_add_number
< 0)
4484 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4486 if (gen_to_words (words
, 5, (long) 15) == 0)
4488 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4490 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4492 if (words
[j
] != fp_values
[i
][j
])
4496 if (j
== MAX_LITTLENUMS
)
4498 *str
= input_line_pointer
;
4499 input_line_pointer
= save_in
;
4506 *str
= input_line_pointer
;
4507 input_line_pointer
= save_in
;
4508 inst
.error
= _("invalid FPA immediate expression");
4512 /* Returns 1 if a number has "quarter-precision" float format
4513 0baBbbbbbc defgh000 00000000 00000000. */
4516 is_quarter_float (unsigned imm
)
4518 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4519 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4522 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4523 0baBbbbbbc defgh000 00000000 00000000.
4524 The zero and minus-zero cases need special handling, since they can't be
4525 encoded in the "quarter-precision" float format, but can nonetheless be
4526 loaded as integer constants. */
4529 parse_qfloat_immediate (char **ccp
, int *immed
)
4533 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4534 int found_fpchar
= 0;
4536 skip_past_char (&str
, '#');
4538 /* We must not accidentally parse an integer as a floating-point number. Make
4539 sure that the value we parse is not an integer by checking for special
4540 characters '.' or 'e'.
4541 FIXME: This is a horrible hack, but doing better is tricky because type
4542 information isn't in a very usable state at parse time. */
4544 skip_whitespace (fpnum
);
4546 if (strncmp (fpnum
, "0x", 2) == 0)
4550 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4551 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4561 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4563 unsigned fpword
= 0;
4566 /* Our FP word must be 32 bits (single-precision FP). */
4567 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4569 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4573 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4586 /* Shift operands. */
4589 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4592 struct asm_shift_name
4595 enum shift_kind kind
;
4598 /* Third argument to parse_shift. */
4599 enum parse_shift_mode
4601 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4602 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4603 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4604 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4605 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4608 /* Parse a <shift> specifier on an ARM data processing instruction.
4609 This has three forms:
4611 (LSL|LSR|ASL|ASR|ROR) Rs
4612 (LSL|LSR|ASL|ASR|ROR) #imm
4615 Note that ASL is assimilated to LSL in the instruction encoding, and
4616 RRX to ROR #0 (which cannot be written as such). */
4619 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4621 const struct asm_shift_name
*shift_name
;
4622 enum shift_kind shift
;
4627 for (p
= *str
; ISALPHA (*p
); p
++)
4632 inst
.error
= _("shift expression expected");
4636 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4639 if (shift_name
== NULL
)
4641 inst
.error
= _("shift expression expected");
4645 shift
= shift_name
->kind
;
4649 case NO_SHIFT_RESTRICT
:
4650 case SHIFT_IMMEDIATE
: break;
4652 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4653 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4655 inst
.error
= _("'LSL' or 'ASR' required");
4660 case SHIFT_LSL_IMMEDIATE
:
4661 if (shift
!= SHIFT_LSL
)
4663 inst
.error
= _("'LSL' required");
4668 case SHIFT_ASR_IMMEDIATE
:
4669 if (shift
!= SHIFT_ASR
)
4671 inst
.error
= _("'ASR' required");
4679 if (shift
!= SHIFT_RRX
)
4681 /* Whitespace can appear here if the next thing is a bare digit. */
4682 skip_whitespace (p
);
4684 if (mode
== NO_SHIFT_RESTRICT
4685 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4687 inst
.operands
[i
].imm
= reg
;
4688 inst
.operands
[i
].immisreg
= 1;
4690 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4693 inst
.operands
[i
].shift_kind
= shift
;
4694 inst
.operands
[i
].shifted
= 1;
4699 /* Parse a <shifter_operand> for an ARM data processing instruction:
4702 #<immediate>, <rotate>
4706 where <shift> is defined by parse_shift above, and <rotate> is a
4707 multiple of 2 between 0 and 30. Validation of immediate operands
4708 is deferred to md_apply_fix. */
4711 parse_shifter_operand (char **str
, int i
)
4716 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4718 inst
.operands
[i
].reg
= value
;
4719 inst
.operands
[i
].isreg
= 1;
4721 /* parse_shift will override this if appropriate */
4722 inst
.reloc
.exp
.X_op
= O_constant
;
4723 inst
.reloc
.exp
.X_add_number
= 0;
4725 if (skip_past_comma (str
) == FAIL
)
4728 /* Shift operation on register. */
4729 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4732 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4735 if (skip_past_comma (str
) == SUCCESS
)
4737 /* #x, y -- ie explicit rotation by Y. */
4738 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
4741 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4743 inst
.error
= _("constant expression expected");
4747 value
= exp
.X_add_number
;
4748 if (value
< 0 || value
> 30 || value
% 2 != 0)
4750 inst
.error
= _("invalid rotation");
4753 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4755 inst
.error
= _("invalid constant");
4759 /* Convert to decoded value. md_apply_fix will put it back. */
4760 inst
.reloc
.exp
.X_add_number
4761 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4762 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4765 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4766 inst
.reloc
.pc_rel
= 0;
4770 /* Group relocation information. Each entry in the table contains the
4771 textual name of the relocation as may appear in assembler source
4772 and must end with a colon.
4773 Along with this textual name are the relocation codes to be used if
4774 the corresponding instruction is an ALU instruction (ADD or SUB only),
4775 an LDR, an LDRS, or an LDC. */
4777 struct group_reloc_table_entry
4788 /* Varieties of non-ALU group relocation. */
4795 static struct group_reloc_table_entry group_reloc_table
[] =
4796 { /* Program counter relative: */
4798 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4803 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4804 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4805 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4806 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4808 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4813 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4814 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4815 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4816 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4818 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4819 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4820 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4821 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4822 /* Section base relative */
4824 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4829 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4830 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4831 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4832 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4834 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4839 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4840 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4841 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4842 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4844 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4845 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4846 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4847 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4849 /* Given the address of a pointer pointing to the textual name of a group
4850 relocation as may appear in assembler source, attempt to find its details
4851 in group_reloc_table. The pointer will be updated to the character after
4852 the trailing colon. On failure, FAIL will be returned; SUCCESS
4853 otherwise. On success, *entry will be updated to point at the relevant
4854 group_reloc_table entry. */
4857 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4860 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4862 int length
= strlen (group_reloc_table
[i
].name
);
4864 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4865 && (*str
)[length
] == ':')
4867 *out
= &group_reloc_table
[i
];
4868 *str
+= (length
+ 1);
4876 /* Parse a <shifter_operand> for an ARM data processing instruction
4877 (as for parse_shifter_operand) where group relocations are allowed:
4880 #<immediate>, <rotate>
4881 #:<group_reloc>:<expression>
4885 where <group_reloc> is one of the strings defined in group_reloc_table.
4886 The hashes are optional.
4888 Everything else is as for parse_shifter_operand. */
4890 static parse_operand_result
4891 parse_shifter_operand_group_reloc (char **str
, int i
)
4893 /* Determine if we have the sequence of characters #: or just :
4894 coming next. If we do, then we check for a group relocation.
4895 If we don't, punt the whole lot to parse_shifter_operand. */
4897 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4898 || (*str
)[0] == ':')
4900 struct group_reloc_table_entry
*entry
;
4902 if ((*str
)[0] == '#')
4907 /* Try to parse a group relocation. Anything else is an error. */
4908 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4910 inst
.error
= _("unknown group relocation");
4911 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4914 /* We now have the group relocation table entry corresponding to
4915 the name in the assembler source. Next, we parse the expression. */
4916 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4917 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4919 /* Record the relocation type (always the ALU variant here). */
4920 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
4921 gas_assert (inst
.reloc
.type
!= 0);
4923 return PARSE_OPERAND_SUCCESS
;
4926 return parse_shifter_operand (str
, i
) == SUCCESS
4927 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4929 /* Never reached. */
4932 /* Parse all forms of an ARM address expression. Information is written
4933 to inst.operands[i] and/or inst.reloc.
4935 Preindexed addressing (.preind=1):
4937 [Rn, #offset] .reg=Rn .reloc.exp=offset
4938 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4939 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4940 .shift_kind=shift .reloc.exp=shift_imm
4942 These three may have a trailing ! which causes .writeback to be set also.
4944 Postindexed addressing (.postind=1, .writeback=1):
4946 [Rn], #offset .reg=Rn .reloc.exp=offset
4947 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4948 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4949 .shift_kind=shift .reloc.exp=shift_imm
4951 Unindexed addressing (.preind=0, .postind=0):
4953 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4957 [Rn]{!} shorthand for [Rn,#0]{!}
4958 =immediate .isreg=0 .reloc.exp=immediate
4959 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4961 It is the caller's responsibility to check for addressing modes not
4962 supported by the instruction, and to set inst.reloc.type. */
4964 static parse_operand_result
4965 parse_address_main (char **str
, int i
, int group_relocations
,
4966 group_reloc_type group_type
)
4971 if (skip_past_char (&p
, '[') == FAIL
)
4973 if (skip_past_char (&p
, '=') == FAIL
)
4975 /* Bare address - translate to PC-relative offset. */
4976 inst
.reloc
.pc_rel
= 1;
4977 inst
.operands
[i
].reg
= REG_PC
;
4978 inst
.operands
[i
].isreg
= 1;
4979 inst
.operands
[i
].preind
= 1;
4981 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
4983 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4984 return PARSE_OPERAND_FAIL
;
4987 return PARSE_OPERAND_SUCCESS
;
4990 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4992 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4993 return PARSE_OPERAND_FAIL
;
4995 inst
.operands
[i
].reg
= reg
;
4996 inst
.operands
[i
].isreg
= 1;
4998 if (skip_past_comma (&p
) == SUCCESS
)
5000 inst
.operands
[i
].preind
= 1;
5003 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5005 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5007 inst
.operands
[i
].imm
= reg
;
5008 inst
.operands
[i
].immisreg
= 1;
5010 if (skip_past_comma (&p
) == SUCCESS
)
5011 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5012 return PARSE_OPERAND_FAIL
;
5014 else if (skip_past_char (&p
, ':') == SUCCESS
)
5016 /* FIXME: '@' should be used here, but it's filtered out by generic
5017 code before we get to see it here. This may be subject to
5020 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5021 if (exp
.X_op
!= O_constant
)
5023 inst
.error
= _("alignment must be constant");
5024 return PARSE_OPERAND_FAIL
;
5026 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5027 inst
.operands
[i
].immisalign
= 1;
5028 /* Alignments are not pre-indexes. */
5029 inst
.operands
[i
].preind
= 0;
5033 if (inst
.operands
[i
].negative
)
5035 inst
.operands
[i
].negative
= 0;
5039 if (group_relocations
5040 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5042 struct group_reloc_table_entry
*entry
;
5044 /* Skip over the #: or : sequence. */
5050 /* Try to parse a group relocation. Anything else is an
5052 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5054 inst
.error
= _("unknown group relocation");
5055 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5058 /* We now have the group relocation table entry corresponding to
5059 the name in the assembler source. Next, we parse the
5061 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5062 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5064 /* Record the relocation type. */
5068 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5072 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5076 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5083 if (inst
.reloc
.type
== 0)
5085 inst
.error
= _("this group relocation is not allowed on this instruction");
5086 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5090 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5091 return PARSE_OPERAND_FAIL
;
5095 if (skip_past_char (&p
, ']') == FAIL
)
5097 inst
.error
= _("']' expected");
5098 return PARSE_OPERAND_FAIL
;
5101 if (skip_past_char (&p
, '!') == SUCCESS
)
5102 inst
.operands
[i
].writeback
= 1;
5104 else if (skip_past_comma (&p
) == SUCCESS
)
5106 if (skip_past_char (&p
, '{') == SUCCESS
)
5108 /* [Rn], {expr} - unindexed, with option */
5109 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5110 0, 255, TRUE
) == FAIL
)
5111 return PARSE_OPERAND_FAIL
;
5113 if (skip_past_char (&p
, '}') == FAIL
)
5115 inst
.error
= _("'}' expected at end of 'option' field");
5116 return PARSE_OPERAND_FAIL
;
5118 if (inst
.operands
[i
].preind
)
5120 inst
.error
= _("cannot combine index with option");
5121 return PARSE_OPERAND_FAIL
;
5124 return PARSE_OPERAND_SUCCESS
;
5128 inst
.operands
[i
].postind
= 1;
5129 inst
.operands
[i
].writeback
= 1;
5131 if (inst
.operands
[i
].preind
)
5133 inst
.error
= _("cannot combine pre- and post-indexing");
5134 return PARSE_OPERAND_FAIL
;
5138 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5140 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5142 /* We might be using the immediate for alignment already. If we
5143 are, OR the register number into the low-order bits. */
5144 if (inst
.operands
[i
].immisalign
)
5145 inst
.operands
[i
].imm
|= reg
;
5147 inst
.operands
[i
].imm
= reg
;
5148 inst
.operands
[i
].immisreg
= 1;
5150 if (skip_past_comma (&p
) == SUCCESS
)
5151 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5152 return PARSE_OPERAND_FAIL
;
5156 if (inst
.operands
[i
].negative
)
5158 inst
.operands
[i
].negative
= 0;
5161 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5162 return PARSE_OPERAND_FAIL
;
5167 /* If at this point neither .preind nor .postind is set, we have a
5168 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5169 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5171 inst
.operands
[i
].preind
= 1;
5172 inst
.reloc
.exp
.X_op
= O_constant
;
5173 inst
.reloc
.exp
.X_add_number
= 0;
5176 return PARSE_OPERAND_SUCCESS
;
5180 parse_address (char **str
, int i
)
5182 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5186 static parse_operand_result
5187 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5189 return parse_address_main (str
, i
, 1, type
);
5192 /* Parse an operand for a MOVW or MOVT instruction. */
5194 parse_half (char **str
)
5199 skip_past_char (&p
, '#');
5200 if (strncasecmp (p
, ":lower16:", 9) == 0)
5201 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5202 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5203 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5205 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5208 skip_whitespace (p
);
5211 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5214 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5216 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5218 inst
.error
= _("constant expression expected");
5221 if (inst
.reloc
.exp
.X_add_number
< 0
5222 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5224 inst
.error
= _("immediate value out of range");
5232 /* Miscellaneous. */
5234 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5235 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5237 parse_psr (char **str
)
5240 unsigned long psr_field
;
5241 const struct asm_psr
*psr
;
5244 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5245 feature for ease of use and backwards compatibility. */
5247 if (strncasecmp (p
, "SPSR", 4) == 0)
5248 psr_field
= SPSR_BIT
;
5249 else if (strncasecmp (p
, "CPSR", 4) == 0)
5256 while (ISALNUM (*p
) || *p
== '_');
5258 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5270 /* A suffix follows. */
5276 while (ISALNUM (*p
) || *p
== '_');
5278 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5283 psr_field
|= psr
->field
;
5288 goto error
; /* Garbage after "[CS]PSR". */
5290 psr_field
|= (PSR_c
| PSR_f
);
5296 inst
.error
= _("flag for {c}psr instruction expected");
5300 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5301 value suitable for splatting into the AIF field of the instruction. */
5304 parse_cps_flags (char **str
)
5313 case '\0': case ',':
5316 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5317 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5318 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5321 inst
.error
= _("unrecognized CPS flag");
5326 if (saw_a_flag
== 0)
5328 inst
.error
= _("missing CPS flags");
5336 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5337 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5340 parse_endian_specifier (char **str
)
5345 if (strncasecmp (s
, "BE", 2))
5347 else if (strncasecmp (s
, "LE", 2))
5351 inst
.error
= _("valid endian specifiers are be or le");
5355 if (ISALNUM (s
[2]) || s
[2] == '_')
5357 inst
.error
= _("valid endian specifiers are be or le");
5362 return little_endian
;
5365 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5366 value suitable for poking into the rotate field of an sxt or sxta
5367 instruction, or FAIL on error. */
5370 parse_ror (char **str
)
5375 if (strncasecmp (s
, "ROR", 3) == 0)
5379 inst
.error
= _("missing rotation field after comma");
5383 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5388 case 0: *str
= s
; return 0x0;
5389 case 8: *str
= s
; return 0x1;
5390 case 16: *str
= s
; return 0x2;
5391 case 24: *str
= s
; return 0x3;
5394 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5399 /* Parse a conditional code (from conds[] below). The value returned is in the
5400 range 0 .. 14, or FAIL. */
5402 parse_cond (char **str
)
5405 const struct asm_cond
*c
;
5407 /* Condition codes are always 2 characters, so matching up to
5408 3 characters is sufficient. */
5413 while (ISALPHA (*q
) && n
< 3)
5415 cond
[n
] = TOLOWER (*q
);
5420 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5423 inst
.error
= _("condition required");
5431 /* Parse an option for a barrier instruction. Returns the encoding for the
5434 parse_barrier (char **str
)
5437 const struct asm_barrier_opt
*o
;
5440 while (ISALPHA (*q
))
5443 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5452 /* Parse the operands of a table branch instruction. Similar to a memory
5455 parse_tb (char **str
)
5460 if (skip_past_char (&p
, '[') == FAIL
)
5462 inst
.error
= _("'[' expected");
5466 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5468 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5471 inst
.operands
[0].reg
= reg
;
5473 if (skip_past_comma (&p
) == FAIL
)
5475 inst
.error
= _("',' expected");
5479 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5481 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5484 inst
.operands
[0].imm
= reg
;
5486 if (skip_past_comma (&p
) == SUCCESS
)
5488 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5490 if (inst
.reloc
.exp
.X_add_number
!= 1)
5492 inst
.error
= _("invalid shift");
5495 inst
.operands
[0].shifted
= 1;
5498 if (skip_past_char (&p
, ']') == FAIL
)
5500 inst
.error
= _("']' expected");
5507 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5508 information on the types the operands can take and how they are encoded.
5509 Up to four operands may be read; this function handles setting the
5510 ".present" field for each read operand itself.
5511 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5512 else returns FAIL. */
5515 parse_neon_mov (char **str
, int *which_operand
)
5517 int i
= *which_operand
, val
;
5518 enum arm_reg_type rtype
;
5520 struct neon_type_el optype
;
5522 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5524 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5525 inst
.operands
[i
].reg
= val
;
5526 inst
.operands
[i
].isscalar
= 1;
5527 inst
.operands
[i
].vectype
= optype
;
5528 inst
.operands
[i
++].present
= 1;
5530 if (skip_past_comma (&ptr
) == FAIL
)
5533 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5536 inst
.operands
[i
].reg
= val
;
5537 inst
.operands
[i
].isreg
= 1;
5538 inst
.operands
[i
].present
= 1;
5540 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5543 /* Cases 0, 1, 2, 3, 5 (D only). */
5544 if (skip_past_comma (&ptr
) == FAIL
)
5547 inst
.operands
[i
].reg
= val
;
5548 inst
.operands
[i
].isreg
= 1;
5549 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5550 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5551 inst
.operands
[i
].isvec
= 1;
5552 inst
.operands
[i
].vectype
= optype
;
5553 inst
.operands
[i
++].present
= 1;
5555 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5557 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5558 Case 13: VMOV <Sd>, <Rm> */
5559 inst
.operands
[i
].reg
= val
;
5560 inst
.operands
[i
].isreg
= 1;
5561 inst
.operands
[i
].present
= 1;
5563 if (rtype
== REG_TYPE_NQ
)
5565 first_error (_("can't use Neon quad register here"));
5568 else if (rtype
!= REG_TYPE_VFS
)
5571 if (skip_past_comma (&ptr
) == FAIL
)
5573 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5575 inst
.operands
[i
].reg
= val
;
5576 inst
.operands
[i
].isreg
= 1;
5577 inst
.operands
[i
].present
= 1;
5580 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5583 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5584 Case 1: VMOV<c><q> <Dd>, <Dm>
5585 Case 8: VMOV.F32 <Sd>, <Sm>
5586 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5588 inst
.operands
[i
].reg
= val
;
5589 inst
.operands
[i
].isreg
= 1;
5590 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5591 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5592 inst
.operands
[i
].isvec
= 1;
5593 inst
.operands
[i
].vectype
= optype
;
5594 inst
.operands
[i
].present
= 1;
5596 if (skip_past_comma (&ptr
) == SUCCESS
)
5601 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5604 inst
.operands
[i
].reg
= val
;
5605 inst
.operands
[i
].isreg
= 1;
5606 inst
.operands
[i
++].present
= 1;
5608 if (skip_past_comma (&ptr
) == FAIL
)
5611 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5614 inst
.operands
[i
].reg
= val
;
5615 inst
.operands
[i
].isreg
= 1;
5616 inst
.operands
[i
++].present
= 1;
5619 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5620 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5621 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5622 Case 10: VMOV.F32 <Sd>, #<imm>
5623 Case 11: VMOV.F64 <Dd>, #<imm> */
5624 inst
.operands
[i
].immisfloat
= 1;
5625 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5626 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5627 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5631 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5635 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5638 inst
.operands
[i
].reg
= val
;
5639 inst
.operands
[i
].isreg
= 1;
5640 inst
.operands
[i
++].present
= 1;
5642 if (skip_past_comma (&ptr
) == FAIL
)
5645 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5647 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5648 inst
.operands
[i
].reg
= val
;
5649 inst
.operands
[i
].isscalar
= 1;
5650 inst
.operands
[i
].present
= 1;
5651 inst
.operands
[i
].vectype
= optype
;
5653 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5655 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5656 inst
.operands
[i
].reg
= val
;
5657 inst
.operands
[i
].isreg
= 1;
5658 inst
.operands
[i
++].present
= 1;
5660 if (skip_past_comma (&ptr
) == FAIL
)
5663 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5666 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5670 inst
.operands
[i
].reg
= val
;
5671 inst
.operands
[i
].isreg
= 1;
5672 inst
.operands
[i
].isvec
= 1;
5673 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5674 inst
.operands
[i
].vectype
= optype
;
5675 inst
.operands
[i
].present
= 1;
5677 if (rtype
== REG_TYPE_VFS
)
5681 if (skip_past_comma (&ptr
) == FAIL
)
5683 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5686 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5689 inst
.operands
[i
].reg
= val
;
5690 inst
.operands
[i
].isreg
= 1;
5691 inst
.operands
[i
].isvec
= 1;
5692 inst
.operands
[i
].issingle
= 1;
5693 inst
.operands
[i
].vectype
= optype
;
5694 inst
.operands
[i
].present
= 1;
5697 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5701 inst
.operands
[i
].reg
= val
;
5702 inst
.operands
[i
].isreg
= 1;
5703 inst
.operands
[i
].isvec
= 1;
5704 inst
.operands
[i
].issingle
= 1;
5705 inst
.operands
[i
].vectype
= optype
;
5706 inst
.operands
[i
++].present
= 1;
5711 first_error (_("parse error"));
5715 /* Successfully parsed the operands. Update args. */
5721 first_error (_("expected comma"));
5725 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5729 /* Matcher codes for parse_operands. */
5730 enum operand_parse_code
5732 OP_stop
, /* end of line */
5734 OP_RR
, /* ARM register */
5735 OP_RRnpc
, /* ARM register, not r15 */
5736 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5737 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5738 OP_RCP
, /* Coprocessor number */
5739 OP_RCN
, /* Coprocessor register */
5740 OP_RF
, /* FPA register */
5741 OP_RVS
, /* VFP single precision register */
5742 OP_RVD
, /* VFP double precision register (0..15) */
5743 OP_RND
, /* Neon double precision register (0..31) */
5744 OP_RNQ
, /* Neon quad precision register */
5745 OP_RVSD
, /* VFP single or double precision register */
5746 OP_RNDQ
, /* Neon double or quad precision register */
5747 OP_RNSDQ
, /* Neon single, double or quad precision register */
5748 OP_RNSC
, /* Neon scalar D[X] */
5749 OP_RVC
, /* VFP control register */
5750 OP_RMF
, /* Maverick F register */
5751 OP_RMD
, /* Maverick D register */
5752 OP_RMFX
, /* Maverick FX register */
5753 OP_RMDX
, /* Maverick DX register */
5754 OP_RMAX
, /* Maverick AX register */
5755 OP_RMDS
, /* Maverick DSPSC register */
5756 OP_RIWR
, /* iWMMXt wR register */
5757 OP_RIWC
, /* iWMMXt wC register */
5758 OP_RIWG
, /* iWMMXt wCG register */
5759 OP_RXA
, /* XScale accumulator register */
5761 OP_REGLST
, /* ARM register list */
5762 OP_VRSLST
, /* VFP single-precision register list */
5763 OP_VRDLST
, /* VFP double-precision register list */
5764 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5765 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5766 OP_NSTRLST
, /* Neon element/structure list */
5768 OP_NILO
, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5769 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5770 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5771 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5772 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5773 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5774 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5775 OP_VMOV
, /* Neon VMOV operands. */
5776 OP_RNDQ_IMVNb
,/* Neon D or Q reg, or immediate good for VMVN. */
5777 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5778 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5780 OP_I0
, /* immediate zero */
5781 OP_I7
, /* immediate value 0 .. 7 */
5782 OP_I15
, /* 0 .. 15 */
5783 OP_I16
, /* 1 .. 16 */
5784 OP_I16z
, /* 0 .. 16 */
5785 OP_I31
, /* 0 .. 31 */
5786 OP_I31w
, /* 0 .. 31, optional trailing ! */
5787 OP_I32
, /* 1 .. 32 */
5788 OP_I32z
, /* 0 .. 32 */
5789 OP_I63
, /* 0 .. 63 */
5790 OP_I63s
, /* -64 .. 63 */
5791 OP_I64
, /* 1 .. 64 */
5792 OP_I64z
, /* 0 .. 64 */
5793 OP_I255
, /* 0 .. 255 */
5795 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5796 OP_I7b
, /* 0 .. 7 */
5797 OP_I15b
, /* 0 .. 15 */
5798 OP_I31b
, /* 0 .. 31 */
5800 OP_SH
, /* shifter operand */
5801 OP_SHG
, /* shifter operand with possible group relocation */
5802 OP_ADDR
, /* Memory address expression (any mode) */
5803 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5804 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5805 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5806 OP_EXP
, /* arbitrary expression */
5807 OP_EXPi
, /* same, with optional immediate prefix */
5808 OP_EXPr
, /* same, with optional relocation suffix */
5809 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5811 OP_CPSF
, /* CPS flags */
5812 OP_ENDI
, /* Endianness specifier */
5813 OP_PSR
, /* CPSR/SPSR mask for msr */
5814 OP_COND
, /* conditional code */
5815 OP_TB
, /* Table branch. */
5817 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5818 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5820 OP_RRnpc_I0
, /* ARM register or literal 0 */
5821 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5822 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5823 OP_RF_IF
, /* FPA register or immediate */
5824 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5825 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5827 /* Optional operands. */
5828 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5829 OP_oI31b
, /* 0 .. 31 */
5830 OP_oI32b
, /* 1 .. 32 */
5831 OP_oIffffb
, /* 0 .. 65535 */
5832 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5834 OP_oRR
, /* ARM register */
5835 OP_oRRnpc
, /* ARM register, not the PC */
5836 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5837 OP_oRND
, /* Optional Neon double precision register */
5838 OP_oRNQ
, /* Optional Neon quad precision register */
5839 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5840 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5841 OP_oSHll
, /* LSL immediate */
5842 OP_oSHar
, /* ASR immediate */
5843 OP_oSHllar
, /* LSL or ASR immediate */
5844 OP_oROR
, /* ROR 0/8/16/24 */
5845 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5847 OP_FIRST_OPTIONAL
= OP_oI7b
5850 /* Generic instruction operand parser. This does no encoding and no
5851 semantic validation; it merely squirrels values away in the inst
5852 structure. Returns SUCCESS or FAIL depending on whether the
5853 specified grammar matched. */
5855 parse_operands (char *str
, const unsigned char *pattern
)
5857 unsigned const char *upat
= pattern
;
5858 char *backtrack_pos
= 0;
5859 const char *backtrack_error
= 0;
5860 int i
, val
, backtrack_index
= 0;
5861 enum arm_reg_type rtype
;
5862 parse_operand_result result
;
5864 #define po_char_or_fail(chr) \
5867 if (skip_past_char (&str, chr) == FAIL) \
5872 #define po_reg_or_fail(regtype) \
5875 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5876 & inst.operands[i].vectype); \
5879 first_error (_(reg_expected_msgs[regtype])); \
5882 inst.operands[i].reg = val; \
5883 inst.operands[i].isreg = 1; \
5884 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5885 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5886 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5887 || rtype == REG_TYPE_VFD \
5888 || rtype == REG_TYPE_NQ); \
5892 #define po_reg_or_goto(regtype, label) \
5895 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5896 & inst.operands[i].vectype); \
5900 inst.operands[i].reg = val; \
5901 inst.operands[i].isreg = 1; \
5902 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5903 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5904 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5905 || rtype == REG_TYPE_VFD \
5906 || rtype == REG_TYPE_NQ); \
5910 #define po_imm_or_fail(min, max, popt) \
5913 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5915 inst.operands[i].imm = val; \
5919 #define po_scalar_or_goto(elsz, label) \
5922 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
5925 inst.operands[i].reg = val; \
5926 inst.operands[i].isscalar = 1; \
5930 #define po_misc_or_fail(expr) \
5938 #define po_misc_or_fail_no_backtrack(expr) \
5942 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
5943 backtrack_pos = 0; \
5944 if (result != PARSE_OPERAND_SUCCESS) \
5949 skip_whitespace (str
);
5951 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5953 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5955 /* Remember where we are in case we need to backtrack. */
5956 gas_assert (!backtrack_pos
);
5957 backtrack_pos
= str
;
5958 backtrack_error
= inst
.error
;
5959 backtrack_index
= i
;
5962 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
5963 po_char_or_fail (',');
5971 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5972 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5973 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5974 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5975 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5976 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5978 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5980 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
5982 /* Also accept generic coprocessor regs for unknown registers. */
5984 po_reg_or_fail (REG_TYPE_CN
);
5986 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5987 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5988 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5989 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5990 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5991 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5992 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5993 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5994 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5995 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5997 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
5999 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6000 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6002 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6004 /* Neon scalar. Using an element size of 8 means that some invalid
6005 scalars are accepted here, so deal with those in later code. */
6006 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6008 /* WARNING: We can expand to two operands here. This has the potential
6009 to totally confuse the backtracking mechanism! It will be OK at
6010 least as long as we don't try to use optional args as well,
6014 po_reg_or_goto (REG_TYPE_NDQ
, try_imm
);
6015 inst
.operands
[i
].present
= 1;
6017 skip_past_comma (&str
);
6018 po_reg_or_goto (REG_TYPE_NDQ
, one_reg_only
);
6021 /* Optional register operand was omitted. Unfortunately, it's in
6022 operands[i-1] and we need it to be in inst.operands[i]. Fix that
6023 here (this is a bit grotty). */
6024 inst
.operands
[i
] = inst
.operands
[i
-1];
6025 inst
.operands
[i
-1].present
= 0;
6028 /* There's a possibility of getting a 64-bit immediate here, so
6029 we need special handling. */
6030 if (parse_big_immediate (&str
, i
) == FAIL
)
6032 inst
.error
= _("immediate value is out of range");
6040 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6043 po_imm_or_fail (0, 0, TRUE
);
6048 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6053 po_scalar_or_goto (8, try_rr
);
6056 po_reg_or_fail (REG_TYPE_RN
);
6062 po_scalar_or_goto (8, try_nsdq
);
6065 po_reg_or_fail (REG_TYPE_NSDQ
);
6071 po_scalar_or_goto (8, try_ndq
);
6074 po_reg_or_fail (REG_TYPE_NDQ
);
6080 po_scalar_or_goto (8, try_vfd
);
6083 po_reg_or_fail (REG_TYPE_VFD
);
6088 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6089 not careful then bad things might happen. */
6090 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6095 po_reg_or_goto (REG_TYPE_NDQ
, try_mvnimm
);
6098 /* There's a possibility of getting a 64-bit immediate here, so
6099 we need special handling. */
6100 if (parse_big_immediate (&str
, i
) == FAIL
)
6102 inst
.error
= _("immediate value is out of range");
6110 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6113 po_imm_or_fail (0, 63, TRUE
);
6118 po_char_or_fail ('[');
6119 po_reg_or_fail (REG_TYPE_RN
);
6120 po_char_or_fail (']');
6125 po_reg_or_fail (REG_TYPE_RN
);
6126 if (skip_past_char (&str
, '!') == SUCCESS
)
6127 inst
.operands
[i
].writeback
= 1;
6131 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6132 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6133 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6134 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6135 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6136 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6137 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6138 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6139 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6140 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6141 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6142 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6144 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6146 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6147 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6149 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6150 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6151 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6153 /* Immediate variants */
6155 po_char_or_fail ('{');
6156 po_imm_or_fail (0, 255, TRUE
);
6157 po_char_or_fail ('}');
6161 /* The expression parser chokes on a trailing !, so we have
6162 to find it first and zap it. */
6165 while (*s
&& *s
!= ',')
6170 inst
.operands
[i
].writeback
= 1;
6172 po_imm_or_fail (0, 31, TRUE
);
6180 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6185 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6190 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6192 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6194 val
= parse_reloc (&str
);
6197 inst
.error
= _("unrecognized relocation suffix");
6200 else if (val
!= BFD_RELOC_UNUSED
)
6202 inst
.operands
[i
].imm
= val
;
6203 inst
.operands
[i
].hasreloc
= 1;
6208 /* Operand for MOVW or MOVT. */
6210 po_misc_or_fail (parse_half (&str
));
6213 /* Register or expression. */
6214 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6215 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6217 /* Register or immediate. */
6218 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6219 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6221 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6223 if (!is_immediate_prefix (*str
))
6226 val
= parse_fpa_immediate (&str
);
6229 /* FPA immediates are encoded as registers 8-15.
6230 parse_fpa_immediate has already applied the offset. */
6231 inst
.operands
[i
].reg
= val
;
6232 inst
.operands
[i
].isreg
= 1;
6235 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6236 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6238 /* Two kinds of register. */
6241 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6243 || (rege
->type
!= REG_TYPE_MMXWR
6244 && rege
->type
!= REG_TYPE_MMXWC
6245 && rege
->type
!= REG_TYPE_MMXWCG
))
6247 inst
.error
= _("iWMMXt data or control register expected");
6250 inst
.operands
[i
].reg
= rege
->number
;
6251 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6257 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6259 || (rege
->type
!= REG_TYPE_MMXWC
6260 && rege
->type
!= REG_TYPE_MMXWCG
))
6262 inst
.error
= _("iWMMXt control register expected");
6265 inst
.operands
[i
].reg
= rege
->number
;
6266 inst
.operands
[i
].isreg
= 1;
6271 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6272 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6273 case OP_oROR
: val
= parse_ror (&str
); break;
6274 case OP_PSR
: val
= parse_psr (&str
); break;
6275 case OP_COND
: val
= parse_cond (&str
); break;
6276 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
6279 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
6280 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
6283 val
= parse_psr (&str
);
6287 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6290 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6292 if (strncasecmp (str
, "APSR_", 5) == 0)
6299 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6300 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6301 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6302 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6303 default: found
= 16;
6307 inst
.operands
[i
].isvec
= 1;
6308 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6309 inst
.operands
[i
].reg
= REG_PC
;
6316 po_misc_or_fail (parse_tb (&str
));
6319 /* Register lists. */
6321 val
= parse_reg_list (&str
);
6324 inst
.operands
[1].writeback
= 1;
6330 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6334 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6338 /* Allow Q registers too. */
6339 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6344 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6346 inst
.operands
[i
].issingle
= 1;
6351 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6356 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6357 &inst
.operands
[i
].vectype
);
6360 /* Addressing modes */
6362 po_misc_or_fail (parse_address (&str
, i
));
6366 po_misc_or_fail_no_backtrack (
6367 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6371 po_misc_or_fail_no_backtrack (
6372 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6376 po_misc_or_fail_no_backtrack (
6377 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6381 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6385 po_misc_or_fail_no_backtrack (
6386 parse_shifter_operand_group_reloc (&str
, i
));
6390 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6394 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6398 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6402 as_fatal (_("unhandled operand code %d"), upat
[i
]);
6405 /* Various value-based sanity checks and shared operations. We
6406 do not signal immediate failures for the register constraints;
6407 this allows a syntax error to take precedence. */
6416 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6417 inst
.error
= BAD_PC
;
6435 inst
.operands
[i
].imm
= val
;
6442 /* If we get here, this operand was successfully parsed. */
6443 inst
.operands
[i
].present
= 1;
6447 inst
.error
= BAD_ARGS
;
6452 /* The parse routine should already have set inst.error, but set a
6453 default here just in case. */
6455 inst
.error
= _("syntax error");
6459 /* Do not backtrack over a trailing optional argument that
6460 absorbed some text. We will only fail again, with the
6461 'garbage following instruction' error message, which is
6462 probably less helpful than the current one. */
6463 if (backtrack_index
== i
&& backtrack_pos
!= str
6464 && upat
[i
+1] == OP_stop
)
6467 inst
.error
= _("syntax error");
6471 /* Try again, skipping the optional argument at backtrack_pos. */
6472 str
= backtrack_pos
;
6473 inst
.error
= backtrack_error
;
6474 inst
.operands
[backtrack_index
].present
= 0;
6475 i
= backtrack_index
;
6479 /* Check that we have parsed all the arguments. */
6480 if (*str
!= '\0' && !inst
.error
)
6481 inst
.error
= _("garbage following instruction");
6483 return inst
.error
? FAIL
: SUCCESS
;
6486 #undef po_char_or_fail
6487 #undef po_reg_or_fail
6488 #undef po_reg_or_goto
6489 #undef po_imm_or_fail
6490 #undef po_scalar_or_fail
6492 /* Shorthand macro for instruction encoding functions issuing errors. */
6493 #define constraint(expr, err) \
6504 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6505 instructions are unpredictable if these registers are used. This
6506 is the BadReg predicate in ARM's Thumb-2 documentation. */
6507 #define reject_bad_reg(reg) \
6509 if (reg == REG_SP || reg == REG_PC) \
6511 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6516 /* If REG is R13 (the stack pointer), warn that its use is
6518 #define warn_deprecated_sp(reg) \
6520 if (warn_on_deprecated && reg == REG_SP) \
6521 as_warn (_("use of r13 is deprecated")); \
6524 /* Functions for operand encoding. ARM, then Thumb. */
6526 #define rotate_left(v, n) (v << n | v >> (32 - n))
6528 /* If VAL can be encoded in the immediate field of an ARM instruction,
6529 return the encoded form. Otherwise, return FAIL. */
6532 encode_arm_immediate (unsigned int val
)
6536 for (i
= 0; i
< 32; i
+= 2)
6537 if ((a
= rotate_left (val
, i
)) <= 0xff)
6538 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6543 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6544 return the encoded form. Otherwise, return FAIL. */
6546 encode_thumb32_immediate (unsigned int val
)
6553 for (i
= 1; i
<= 24; i
++)
6556 if ((val
& ~(0xff << i
)) == 0)
6557 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6561 if (val
== ((a
<< 16) | a
))
6563 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6567 if (val
== ((a
<< 16) | a
))
6568 return 0x200 | (a
>> 8);
6572 /* Encode a VFP SP or DP register number into inst.instruction. */
6575 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6577 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6580 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6583 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6586 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6591 first_error (_("D register out of range for selected VFP version"));
6599 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6603 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6607 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6611 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6615 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6619 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6627 /* Encode a <shift> in an ARM-format instruction. The immediate,
6628 if any, is handled by md_apply_fix. */
6630 encode_arm_shift (int i
)
6632 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6633 inst
.instruction
|= SHIFT_ROR
<< 5;
6636 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6637 if (inst
.operands
[i
].immisreg
)
6639 inst
.instruction
|= SHIFT_BY_REG
;
6640 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6643 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6648 encode_arm_shifter_operand (int i
)
6650 if (inst
.operands
[i
].isreg
)
6652 inst
.instruction
|= inst
.operands
[i
].reg
;
6653 encode_arm_shift (i
);
6656 inst
.instruction
|= INST_IMMEDIATE
;
6659 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6661 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6663 gas_assert (inst
.operands
[i
].isreg
);
6664 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6666 if (inst
.operands
[i
].preind
)
6670 inst
.error
= _("instruction does not accept preindexed addressing");
6673 inst
.instruction
|= PRE_INDEX
;
6674 if (inst
.operands
[i
].writeback
)
6675 inst
.instruction
|= WRITE_BACK
;
6678 else if (inst
.operands
[i
].postind
)
6680 gas_assert (inst
.operands
[i
].writeback
);
6682 inst
.instruction
|= WRITE_BACK
;
6684 else /* unindexed - only for coprocessor */
6686 inst
.error
= _("instruction does not accept unindexed addressing");
6690 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6691 && (((inst
.instruction
& 0x000f0000) >> 16)
6692 == ((inst
.instruction
& 0x0000f000) >> 12)))
6693 as_warn ((inst
.instruction
& LOAD_BIT
)
6694 ? _("destination register same as write-back base")
6695 : _("source register same as write-back base"));
6698 /* inst.operands[i] was set up by parse_address. Encode it into an
6699 ARM-format mode 2 load or store instruction. If is_t is true,
6700 reject forms that cannot be used with a T instruction (i.e. not
6703 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6705 encode_arm_addr_mode_common (i
, is_t
);
6707 if (inst
.operands
[i
].immisreg
)
6709 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6710 inst
.instruction
|= inst
.operands
[i
].imm
;
6711 if (!inst
.operands
[i
].negative
)
6712 inst
.instruction
|= INDEX_UP
;
6713 if (inst
.operands
[i
].shifted
)
6715 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6716 inst
.instruction
|= SHIFT_ROR
<< 5;
6719 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6720 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6724 else /* immediate offset in inst.reloc */
6726 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6727 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6731 /* inst.operands[i] was set up by parse_address. Encode it into an
6732 ARM-format mode 3 load or store instruction. Reject forms that
6733 cannot be used with such instructions. If is_t is true, reject
6734 forms that cannot be used with a T instruction (i.e. not
6737 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6739 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6741 inst
.error
= _("instruction does not accept scaled register index");
6745 encode_arm_addr_mode_common (i
, is_t
);
6747 if (inst
.operands
[i
].immisreg
)
6749 inst
.instruction
|= inst
.operands
[i
].imm
;
6750 if (!inst
.operands
[i
].negative
)
6751 inst
.instruction
|= INDEX_UP
;
6753 else /* immediate offset in inst.reloc */
6755 inst
.instruction
|= HWOFFSET_IMM
;
6756 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6757 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6761 /* inst.operands[i] was set up by parse_address. Encode it into an
6762 ARM-format instruction. Reject all forms which cannot be encoded
6763 into a coprocessor load/store instruction. If wb_ok is false,
6764 reject use of writeback; if unind_ok is false, reject use of
6765 unindexed addressing. If reloc_override is not 0, use it instead
6766 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6767 (in which case it is preserved). */
6770 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6772 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6774 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6776 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6778 gas_assert (!inst
.operands
[i
].writeback
);
6781 inst
.error
= _("instruction does not support unindexed addressing");
6784 inst
.instruction
|= inst
.operands
[i
].imm
;
6785 inst
.instruction
|= INDEX_UP
;
6789 if (inst
.operands
[i
].preind
)
6790 inst
.instruction
|= PRE_INDEX
;
6792 if (inst
.operands
[i
].writeback
)
6794 if (inst
.operands
[i
].reg
== REG_PC
)
6796 inst
.error
= _("pc may not be used with write-back");
6801 inst
.error
= _("instruction does not support writeback");
6804 inst
.instruction
|= WRITE_BACK
;
6808 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
6809 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6810 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6811 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6814 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6816 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6822 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6823 Determine whether it can be performed with a move instruction; if
6824 it can, convert inst.instruction to that move instruction and
6825 return TRUE; if it can't, convert inst.instruction to a literal-pool
6826 load and return FALSE. If this is not a valid thing to do in the
6827 current context, set inst.error and return TRUE.
6829 inst.operands[i] describes the destination register. */
6832 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6837 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6841 if ((inst
.instruction
& tbit
) == 0)
6843 inst
.error
= _("invalid pseudo operation");
6846 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6848 inst
.error
= _("constant expression expected");
6851 if (inst
.reloc
.exp
.X_op
== O_constant
)
6855 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6857 /* This can be done with a mov(1) instruction. */
6858 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6859 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6865 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6868 /* This can be done with a mov instruction. */
6869 inst
.instruction
&= LITERAL_MASK
;
6870 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6871 inst
.instruction
|= value
& 0xfff;
6875 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6878 /* This can be done with a mvn instruction. */
6879 inst
.instruction
&= LITERAL_MASK
;
6880 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6881 inst
.instruction
|= value
& 0xfff;
6887 if (add_to_lit_pool () == FAIL
)
6889 inst
.error
= _("literal pool insertion failed");
6892 inst
.operands
[1].reg
= REG_PC
;
6893 inst
.operands
[1].isreg
= 1;
6894 inst
.operands
[1].preind
= 1;
6895 inst
.reloc
.pc_rel
= 1;
6896 inst
.reloc
.type
= (thumb_p
6897 ? BFD_RELOC_ARM_THUMB_OFFSET
6899 ? BFD_RELOC_ARM_HWLITERAL
6900 : BFD_RELOC_ARM_LITERAL
));
6904 /* Functions for instruction encoding, sorted by sub-architecture.
6905 First some generics; their names are taken from the conventional
6906 bit positions for register arguments in ARM format instructions. */
6916 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6922 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6923 inst
.instruction
|= inst
.operands
[1].reg
;
6929 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6930 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6936 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6937 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6943 unsigned Rn
= inst
.operands
[2].reg
;
6944 /* Enforce restrictions on SWP instruction. */
6945 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6946 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6947 _("Rn must not overlap other operands"));
6948 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6949 inst
.instruction
|= inst
.operands
[1].reg
;
6950 inst
.instruction
|= Rn
<< 16;
6956 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6957 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6958 inst
.instruction
|= inst
.operands
[2].reg
;
6964 inst
.instruction
|= inst
.operands
[0].reg
;
6965 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6966 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6972 inst
.instruction
|= inst
.operands
[0].imm
;
6978 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6979 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6982 /* ARM instructions, in alphabetical order by function name (except
6983 that wrapper functions appear immediately after the function they
6986 /* This is a pseudo-op of the form "adr rd, label" to be converted
6987 into a relative address of the form "add rd, pc, #label-.-8". */
6992 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6994 /* Frag hacking will turn this into a sub instruction if the offset turns
6995 out to be negative. */
6996 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6997 inst
.reloc
.pc_rel
= 1;
6998 inst
.reloc
.exp
.X_add_number
-= 8;
7001 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7002 into a relative address of the form:
7003 add rd, pc, #low(label-.-8)"
7004 add rd, rd, #high(label-.-8)" */
7009 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7011 /* Frag hacking will turn this into a sub instruction if the offset turns
7012 out to be negative. */
7013 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7014 inst
.reloc
.pc_rel
= 1;
7015 inst
.size
= INSN_SIZE
* 2;
7016 inst
.reloc
.exp
.X_add_number
-= 8;
7022 if (!inst
.operands
[1].present
)
7023 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7024 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7025 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7026 encode_arm_shifter_operand (2);
7032 if (inst
.operands
[0].present
)
7034 constraint ((inst
.instruction
& 0xf0) != 0x40
7035 && inst
.operands
[0].imm
!= 0xf,
7036 _("bad barrier type"));
7037 inst
.instruction
|= inst
.operands
[0].imm
;
7040 inst
.instruction
|= 0xf;
7046 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7047 constraint (msb
> 32, _("bit-field extends past end of register"));
7048 /* The instruction encoding stores the LSB and MSB,
7049 not the LSB and width. */
7050 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7051 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7052 inst
.instruction
|= (msb
- 1) << 16;
7060 /* #0 in second position is alternative syntax for bfc, which is
7061 the same instruction but with REG_PC in the Rm field. */
7062 if (!inst
.operands
[1].isreg
)
7063 inst
.operands
[1].reg
= REG_PC
;
7065 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7066 constraint (msb
> 32, _("bit-field extends past end of register"));
7067 /* The instruction encoding stores the LSB and MSB,
7068 not the LSB and width. */
7069 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7070 inst
.instruction
|= inst
.operands
[1].reg
;
7071 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7072 inst
.instruction
|= (msb
- 1) << 16;
7078 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7079 _("bit-field extends past end of register"));
7080 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7081 inst
.instruction
|= inst
.operands
[1].reg
;
7082 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7083 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7086 /* ARM V5 breakpoint instruction (argument parse)
7087 BKPT <16 bit unsigned immediate>
7088 Instruction is not conditional.
7089 The bit pattern given in insns[] has the COND_ALWAYS condition,
7090 and it is an error if the caller tried to override that. */
7095 /* Top 12 of 16 bits to bits 19:8. */
7096 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7098 /* Bottom 4 of 16 bits to bits 3:0. */
7099 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7103 encode_branch (int default_reloc
)
7105 if (inst
.operands
[0].hasreloc
)
7107 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
7108 _("the only suffix valid here is '(plt)'"));
7109 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
7113 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7115 inst
.reloc
.pc_rel
= 1;
7122 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7123 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7126 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7133 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7135 if (inst
.cond
== COND_ALWAYS
)
7136 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7138 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7142 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7145 /* ARM V5 branch-link-exchange instruction (argument parse)
7146 BLX <target_addr> ie BLX(1)
7147 BLX{<condition>} <Rm> ie BLX(2)
7148 Unfortunately, there are two different opcodes for this mnemonic.
7149 So, the insns[].value is not used, and the code here zaps values
7150 into inst.instruction.
7151 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7156 if (inst
.operands
[0].isreg
)
7158 /* Arg is a register; the opcode provided by insns[] is correct.
7159 It is not illegal to do "blx pc", just useless. */
7160 if (inst
.operands
[0].reg
== REG_PC
)
7161 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7163 inst
.instruction
|= inst
.operands
[0].reg
;
7167 /* Arg is an address; this instruction cannot be executed
7168 conditionally, and the opcode must be adjusted.
7169 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7170 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7171 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7172 inst
.instruction
= 0xfa000000;
7173 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7180 bfd_boolean want_reloc
;
7182 if (inst
.operands
[0].reg
== REG_PC
)
7183 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7185 inst
.instruction
|= inst
.operands
[0].reg
;
7186 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7187 it is for ARMv4t or earlier. */
7188 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7189 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7193 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7198 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7202 /* ARM v5TEJ. Jump to Jazelle code. */
7207 if (inst
.operands
[0].reg
== REG_PC
)
7208 as_tsktsk (_("use of r15 in bxj is not really useful"));
7210 inst
.instruction
|= inst
.operands
[0].reg
;
7213 /* Co-processor data operation:
7214 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7215 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7219 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7220 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7221 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7222 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7223 inst
.instruction
|= inst
.operands
[4].reg
;
7224 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7230 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7231 encode_arm_shifter_operand (1);
7234 /* Transfer between coprocessor and ARM registers.
7235 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7240 No special properties. */
7247 Rd
= inst
.operands
[2].reg
;
7250 if (inst
.instruction
== 0xee000010
7251 || inst
.instruction
== 0xfe000010)
7253 reject_bad_reg (Rd
);
7256 constraint (Rd
== REG_SP
, BAD_SP
);
7261 if (inst
.instruction
== 0xe000010)
7262 constraint (Rd
== REG_PC
, BAD_PC
);
7266 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7267 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7268 inst
.instruction
|= Rd
<< 12;
7269 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7270 inst
.instruction
|= inst
.operands
[4].reg
;
7271 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7274 /* Transfer between coprocessor register and pair of ARM registers.
7275 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7280 Two XScale instructions are special cases of these:
7282 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7283 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7285 Result unpredictable if Rd or Rn is R15. */
7292 Rd
= inst
.operands
[2].reg
;
7293 Rn
= inst
.operands
[3].reg
;
7297 reject_bad_reg (Rd
);
7298 reject_bad_reg (Rn
);
7302 constraint (Rd
== REG_PC
, BAD_PC
);
7303 constraint (Rn
== REG_PC
, BAD_PC
);
7306 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7307 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7308 inst
.instruction
|= Rd
<< 12;
7309 inst
.instruction
|= Rn
<< 16;
7310 inst
.instruction
|= inst
.operands
[4].reg
;
7316 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7317 if (inst
.operands
[1].present
)
7319 inst
.instruction
|= CPSI_MMOD
;
7320 inst
.instruction
|= inst
.operands
[1].imm
;
7327 inst
.instruction
|= inst
.operands
[0].imm
;
7333 /* There is no IT instruction in ARM mode. We
7334 process it to do the validation as if in
7335 thumb mode, just in case the code gets
7336 assembled for thumb using the unified syntax. */
7341 set_it_insn_type (IT_INSN
);
7342 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7343 now_it
.cc
= inst
.operands
[0].imm
;
7350 int base_reg
= inst
.operands
[0].reg
;
7351 int range
= inst
.operands
[1].imm
;
7353 inst
.instruction
|= base_reg
<< 16;
7354 inst
.instruction
|= range
;
7356 if (inst
.operands
[1].writeback
)
7357 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7359 if (inst
.operands
[0].writeback
)
7361 inst
.instruction
|= WRITE_BACK
;
7362 /* Check for unpredictable uses of writeback. */
7363 if (inst
.instruction
& LOAD_BIT
)
7365 /* Not allowed in LDM type 2. */
7366 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7367 && ((range
& (1 << REG_PC
)) == 0))
7368 as_warn (_("writeback of base register is UNPREDICTABLE"));
7369 /* Only allowed if base reg not in list for other types. */
7370 else if (range
& (1 << base_reg
))
7371 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7375 /* Not allowed for type 2. */
7376 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7377 as_warn (_("writeback of base register is UNPREDICTABLE"));
7378 /* Only allowed if base reg not in list, or first in list. */
7379 else if ((range
& (1 << base_reg
))
7380 && (range
& ((1 << base_reg
) - 1)))
7381 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7386 /* ARMv5TE load-consecutive (argument parse)
7395 constraint (inst
.operands
[0].reg
% 2 != 0,
7396 _("first destination register must be even"));
7397 constraint (inst
.operands
[1].present
7398 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7399 _("can only load two consecutive registers"));
7400 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7401 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7403 if (!inst
.operands
[1].present
)
7404 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7406 if (inst
.instruction
& LOAD_BIT
)
7408 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7409 register and the first register written; we have to diagnose
7410 overlap between the base and the second register written here. */
7412 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7413 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7414 as_warn (_("base register written back, and overlaps "
7415 "second destination register"));
7417 /* For an index-register load, the index register must not overlap the
7418 destination (even if not write-back). */
7419 else if (inst
.operands
[2].immisreg
7420 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7421 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7422 as_warn (_("index register overlaps destination register"));
7425 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7426 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7432 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7433 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7434 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7435 || inst
.operands
[1].negative
7436 /* This can arise if the programmer has written
7438 or if they have mistakenly used a register name as the last
7441 It is very difficult to distinguish between these two cases
7442 because "rX" might actually be a label. ie the register
7443 name has been occluded by a symbol of the same name. So we
7444 just generate a general 'bad addressing mode' type error
7445 message and leave it up to the programmer to discover the
7446 true cause and fix their mistake. */
7447 || (inst
.operands
[1].reg
== REG_PC
),
7450 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7451 || inst
.reloc
.exp
.X_add_number
!= 0,
7452 _("offset must be zero in ARM encoding"));
7454 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7455 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7456 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7462 constraint (inst
.operands
[0].reg
% 2 != 0,
7463 _("even register required"));
7464 constraint (inst
.operands
[1].present
7465 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7466 _("can only load two consecutive registers"));
7467 /* If op 1 were present and equal to PC, this function wouldn't
7468 have been called in the first place. */
7469 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7471 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7472 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7478 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7479 if (!inst
.operands
[1].isreg
)
7480 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7482 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7488 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7490 if (inst
.operands
[1].preind
)
7492 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7493 || inst
.reloc
.exp
.X_add_number
!= 0,
7494 _("this instruction requires a post-indexed address"));
7496 inst
.operands
[1].preind
= 0;
7497 inst
.operands
[1].postind
= 1;
7498 inst
.operands
[1].writeback
= 1;
7500 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7501 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7504 /* Halfword and signed-byte load/store operations. */
7509 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7510 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7511 if (!inst
.operands
[1].isreg
)
7512 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7514 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7520 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7522 if (inst
.operands
[1].preind
)
7524 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7525 || inst
.reloc
.exp
.X_add_number
!= 0,
7526 _("this instruction requires a post-indexed address"));
7528 inst
.operands
[1].preind
= 0;
7529 inst
.operands
[1].postind
= 1;
7530 inst
.operands
[1].writeback
= 1;
7532 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7533 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7536 /* Co-processor register load/store.
7537 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7541 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7542 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7543 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7549 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7550 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7551 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7552 && !(inst
.instruction
& 0x00400000))
7553 as_tsktsk (_("Rd and Rm should be different in mla"));
7555 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7556 inst
.instruction
|= inst
.operands
[1].reg
;
7557 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7558 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7564 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7565 encode_arm_shifter_operand (1);
7568 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7575 top
= (inst
.instruction
& 0x00400000) != 0;
7576 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7577 _(":lower16: not allowed this instruction"));
7578 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7579 _(":upper16: not allowed instruction"));
7580 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7581 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7583 imm
= inst
.reloc
.exp
.X_add_number
;
7584 /* The value is in two pieces: 0:11, 16:19. */
7585 inst
.instruction
|= (imm
& 0x00000fff);
7586 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7590 static void do_vfp_nsyn_opcode (const char *);
7593 do_vfp_nsyn_mrs (void)
7595 if (inst
.operands
[0].isvec
)
7597 if (inst
.operands
[1].reg
!= 1)
7598 first_error (_("operand 1 must be FPSCR"));
7599 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7600 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7601 do_vfp_nsyn_opcode ("fmstat");
7603 else if (inst
.operands
[1].isvec
)
7604 do_vfp_nsyn_opcode ("fmrx");
7612 do_vfp_nsyn_msr (void)
7614 if (inst
.operands
[0].isvec
)
7615 do_vfp_nsyn_opcode ("fmxr");
7625 unsigned Rt
= inst
.operands
[0].reg
;
7627 if (thumb_mode
&& inst
.operands
[0].reg
== REG_SP
)
7629 inst
.error
= BAD_SP
;
7633 /* APSR_ sets isvec. All other refs to PC are illegal. */
7634 if (!inst
.operands
[0].isvec
&& inst
.operands
[0].reg
== REG_PC
)
7636 inst
.error
= BAD_PC
;
7640 if (inst
.operands
[1].reg
!= 1)
7641 first_error (_("operand 1 must be FPSCR"));
7643 inst
.instruction
|= (Rt
<< 12);
7649 unsigned Rt
= inst
.operands
[1].reg
;
7652 reject_bad_reg (Rt
);
7653 else if (Rt
== REG_PC
)
7655 inst
.error
= BAD_PC
;
7659 if (inst
.operands
[0].reg
!= 1)
7660 first_error (_("operand 0 must be FPSCR"));
7662 inst
.instruction
|= (Rt
<< 12);
7668 if (do_vfp_nsyn_mrs () == SUCCESS
)
7671 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7672 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7674 _("'CPSR' or 'SPSR' expected"));
7675 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7676 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7677 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7680 /* Two possible forms:
7681 "{C|S}PSR_<field>, Rm",
7682 "{C|S}PSR_f, #expression". */
7687 if (do_vfp_nsyn_msr () == SUCCESS
)
7690 inst
.instruction
|= inst
.operands
[0].imm
;
7691 if (inst
.operands
[1].isreg
)
7692 inst
.instruction
|= inst
.operands
[1].reg
;
7695 inst
.instruction
|= INST_IMMEDIATE
;
7696 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7697 inst
.reloc
.pc_rel
= 0;
7704 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
7706 if (!inst
.operands
[2].present
)
7707 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7708 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7709 inst
.instruction
|= inst
.operands
[1].reg
;
7710 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7712 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7713 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7714 as_tsktsk (_("Rd and Rm should be different in mul"));
7717 /* Long Multiply Parser
7718 UMULL RdLo, RdHi, Rm, Rs
7719 SMULL RdLo, RdHi, Rm, Rs
7720 UMLAL RdLo, RdHi, Rm, Rs
7721 SMLAL RdLo, RdHi, Rm, Rs. */
7726 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7727 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7728 inst
.instruction
|= inst
.operands
[2].reg
;
7729 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7731 /* rdhi and rdlo must be different. */
7732 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7733 as_tsktsk (_("rdhi and rdlo must be different"));
7735 /* rdhi, rdlo and rm must all be different before armv6. */
7736 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7737 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7738 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7739 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7745 if (inst
.operands
[0].present
7746 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
7748 /* Architectural NOP hints are CPSR sets with no bits selected. */
7749 inst
.instruction
&= 0xf0000000;
7750 inst
.instruction
|= 0x0320f000;
7751 if (inst
.operands
[0].present
)
7752 inst
.instruction
|= inst
.operands
[0].imm
;
7756 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7757 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7758 Condition defaults to COND_ALWAYS.
7759 Error if Rd, Rn or Rm are R15. */
7764 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7765 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7766 inst
.instruction
|= inst
.operands
[2].reg
;
7767 if (inst
.operands
[3].present
)
7768 encode_arm_shift (3);
7771 /* ARM V6 PKHTB (Argument Parse). */
7776 if (!inst
.operands
[3].present
)
7778 /* If the shift specifier is omitted, turn the instruction
7779 into pkhbt rd, rm, rn. */
7780 inst
.instruction
&= 0xfff00010;
7781 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7782 inst
.instruction
|= inst
.operands
[1].reg
;
7783 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7787 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7788 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7789 inst
.instruction
|= inst
.operands
[2].reg
;
7790 encode_arm_shift (3);
7794 /* ARMv5TE: Preload-Cache
7798 Syntactically, like LDR with B=1, W=0, L=1. */
7803 constraint (!inst
.operands
[0].isreg
,
7804 _("'[' expected after PLD mnemonic"));
7805 constraint (inst
.operands
[0].postind
,
7806 _("post-indexed expression used in preload instruction"));
7807 constraint (inst
.operands
[0].writeback
,
7808 _("writeback used in preload instruction"));
7809 constraint (!inst
.operands
[0].preind
,
7810 _("unindexed addressing used in preload instruction"));
7811 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7814 /* ARMv7: PLI <addr_mode> */
7818 constraint (!inst
.operands
[0].isreg
,
7819 _("'[' expected after PLI mnemonic"));
7820 constraint (inst
.operands
[0].postind
,
7821 _("post-indexed expression used in preload instruction"));
7822 constraint (inst
.operands
[0].writeback
,
7823 _("writeback used in preload instruction"));
7824 constraint (!inst
.operands
[0].preind
,
7825 _("unindexed addressing used in preload instruction"));
7826 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7827 inst
.instruction
&= ~PRE_INDEX
;
7833 inst
.operands
[1] = inst
.operands
[0];
7834 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7835 inst
.operands
[0].isreg
= 1;
7836 inst
.operands
[0].writeback
= 1;
7837 inst
.operands
[0].reg
= REG_SP
;
7841 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7842 word at the specified address and the following word
7844 Unconditionally executed.
7845 Error if Rn is R15. */
7850 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7851 if (inst
.operands
[0].writeback
)
7852 inst
.instruction
|= WRITE_BACK
;
7855 /* ARM V6 ssat (argument parse). */
7860 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7861 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7862 inst
.instruction
|= inst
.operands
[2].reg
;
7864 if (inst
.operands
[3].present
)
7865 encode_arm_shift (3);
7868 /* ARM V6 usat (argument parse). */
7873 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7874 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7875 inst
.instruction
|= inst
.operands
[2].reg
;
7877 if (inst
.operands
[3].present
)
7878 encode_arm_shift (3);
7881 /* ARM V6 ssat16 (argument parse). */
7886 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7887 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7888 inst
.instruction
|= inst
.operands
[2].reg
;
7894 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7895 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7896 inst
.instruction
|= inst
.operands
[2].reg
;
7899 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7900 preserving the other bits.
7902 setend <endian_specifier>, where <endian_specifier> is either
7908 if (inst
.operands
[0].imm
)
7909 inst
.instruction
|= 0x200;
7915 unsigned int Rm
= (inst
.operands
[1].present
7916 ? inst
.operands
[1].reg
7917 : inst
.operands
[0].reg
);
7919 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7920 inst
.instruction
|= Rm
;
7921 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7923 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7924 inst
.instruction
|= SHIFT_BY_REG
;
7927 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7933 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7934 inst
.reloc
.pc_rel
= 0;
7940 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7941 inst
.reloc
.pc_rel
= 0;
7944 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7945 SMLAxy{cond} Rd,Rm,Rs,Rn
7946 SMLAWy{cond} Rd,Rm,Rs,Rn
7947 Error if any register is R15. */
7952 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7953 inst
.instruction
|= inst
.operands
[1].reg
;
7954 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7955 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7958 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7959 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7960 Error if any register is R15.
7961 Warning if Rdlo == Rdhi. */
7966 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7967 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7968 inst
.instruction
|= inst
.operands
[2].reg
;
7969 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7971 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7972 as_tsktsk (_("rdhi and rdlo must be different"));
7975 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7976 SMULxy{cond} Rd,Rm,Rs
7977 Error if any register is R15. */
7982 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7983 inst
.instruction
|= inst
.operands
[1].reg
;
7984 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7987 /* ARM V6 srs (argument parse). The variable fields in the encoding are
7988 the same for both ARM and Thumb-2. */
7995 if (inst
.operands
[0].present
)
7997 reg
= inst
.operands
[0].reg
;
7998 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
8003 inst
.instruction
|= reg
<< 16;
8004 inst
.instruction
|= inst
.operands
[1].imm
;
8005 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8006 inst
.instruction
|= WRITE_BACK
;
8009 /* ARM V6 strex (argument parse). */
8014 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8015 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8016 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8017 || inst
.operands
[2].negative
8018 /* See comment in do_ldrex(). */
8019 || (inst
.operands
[2].reg
== REG_PC
),
8022 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8023 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8025 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8026 || inst
.reloc
.exp
.X_add_number
!= 0,
8027 _("offset must be zero in ARM encoding"));
8029 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8030 inst
.instruction
|= inst
.operands
[1].reg
;
8031 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8032 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8038 constraint (inst
.operands
[1].reg
% 2 != 0,
8039 _("even register required"));
8040 constraint (inst
.operands
[2].present
8041 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8042 _("can only store two consecutive registers"));
8043 /* If op 2 were present and equal to PC, this function wouldn't
8044 have been called in the first place. */
8045 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8047 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8048 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8049 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8052 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8053 inst
.instruction
|= inst
.operands
[1].reg
;
8054 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8057 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8058 extends it to 32-bits, and adds the result to a value in another
8059 register. You can specify a rotation by 0, 8, 16, or 24 bits
8060 before extracting the 16-bit value.
8061 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8062 Condition defaults to COND_ALWAYS.
8063 Error if any register uses R15. */
8068 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8069 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8070 inst
.instruction
|= inst
.operands
[2].reg
;
8071 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8076 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8077 Condition defaults to COND_ALWAYS.
8078 Error if any register uses R15. */
8083 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8084 inst
.instruction
|= inst
.operands
[1].reg
;
8085 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8088 /* VFP instructions. In a logical order: SP variant first, monad
8089 before dyad, arithmetic then move then load/store. */
8092 do_vfp_sp_monadic (void)
8094 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8095 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8099 do_vfp_sp_dyadic (void)
8101 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8102 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8103 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8107 do_vfp_sp_compare_z (void)
8109 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8113 do_vfp_dp_sp_cvt (void)
8115 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8116 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8120 do_vfp_sp_dp_cvt (void)
8122 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8123 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8127 do_vfp_reg_from_sp (void)
8129 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8130 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8134 do_vfp_reg2_from_sp2 (void)
8136 constraint (inst
.operands
[2].imm
!= 2,
8137 _("only two consecutive VFP SP registers allowed here"));
8138 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8139 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8140 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8144 do_vfp_sp_from_reg (void)
8146 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8147 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8151 do_vfp_sp2_from_reg2 (void)
8153 constraint (inst
.operands
[0].imm
!= 2,
8154 _("only two consecutive VFP SP registers allowed here"));
8155 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8156 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8157 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8161 do_vfp_sp_ldst (void)
8163 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8164 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8168 do_vfp_dp_ldst (void)
8170 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8171 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8176 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8178 if (inst
.operands
[0].writeback
)
8179 inst
.instruction
|= WRITE_BACK
;
8181 constraint (ldstm_type
!= VFP_LDSTMIA
,
8182 _("this addressing mode requires base-register writeback"));
8183 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8184 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8185 inst
.instruction
|= inst
.operands
[1].imm
;
8189 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8193 if (inst
.operands
[0].writeback
)
8194 inst
.instruction
|= WRITE_BACK
;
8196 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8197 _("this addressing mode requires base-register writeback"));
8199 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8200 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8202 count
= inst
.operands
[1].imm
<< 1;
8203 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8206 inst
.instruction
|= count
;
8210 do_vfp_sp_ldstmia (void)
8212 vfp_sp_ldstm (VFP_LDSTMIA
);
8216 do_vfp_sp_ldstmdb (void)
8218 vfp_sp_ldstm (VFP_LDSTMDB
);
8222 do_vfp_dp_ldstmia (void)
8224 vfp_dp_ldstm (VFP_LDSTMIA
);
8228 do_vfp_dp_ldstmdb (void)
8230 vfp_dp_ldstm (VFP_LDSTMDB
);
8234 do_vfp_xp_ldstmia (void)
8236 vfp_dp_ldstm (VFP_LDSTMIAX
);
8240 do_vfp_xp_ldstmdb (void)
8242 vfp_dp_ldstm (VFP_LDSTMDBX
);
8246 do_vfp_dp_rd_rm (void)
8248 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8249 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8253 do_vfp_dp_rn_rd (void)
8255 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8256 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8260 do_vfp_dp_rd_rn (void)
8262 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8263 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8267 do_vfp_dp_rd_rn_rm (void)
8269 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8270 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8271 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8277 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8281 do_vfp_dp_rm_rd_rn (void)
8283 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8284 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8285 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8288 /* VFPv3 instructions. */
8290 do_vfp_sp_const (void)
8292 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8293 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8294 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8298 do_vfp_dp_const (void)
8300 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8301 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8302 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8306 vfp_conv (int srcsize
)
8308 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
8309 inst
.instruction
|= (immbits
& 1) << 5;
8310 inst
.instruction
|= (immbits
>> 1);
8314 do_vfp_sp_conv_16 (void)
8316 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8321 do_vfp_dp_conv_16 (void)
8323 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8328 do_vfp_sp_conv_32 (void)
8330 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8335 do_vfp_dp_conv_32 (void)
8337 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8341 /* FPA instructions. Also in a logical order. */
8346 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8347 inst
.instruction
|= inst
.operands
[1].reg
;
8351 do_fpa_ldmstm (void)
8353 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8354 switch (inst
.operands
[1].imm
)
8356 case 1: inst
.instruction
|= CP_T_X
; break;
8357 case 2: inst
.instruction
|= CP_T_Y
; break;
8358 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8363 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8365 /* The instruction specified "ea" or "fd", so we can only accept
8366 [Rn]{!}. The instruction does not really support stacking or
8367 unstacking, so we have to emulate these by setting appropriate
8368 bits and offsets. */
8369 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8370 || inst
.reloc
.exp
.X_add_number
!= 0,
8371 _("this instruction does not support indexing"));
8373 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8374 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8376 if (!(inst
.instruction
& INDEX_UP
))
8377 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8379 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8381 inst
.operands
[2].preind
= 0;
8382 inst
.operands
[2].postind
= 1;
8386 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8389 /* iWMMXt instructions: strictly in alphabetical order. */
8392 do_iwmmxt_tandorc (void)
8394 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8398 do_iwmmxt_textrc (void)
8400 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8401 inst
.instruction
|= inst
.operands
[1].imm
;
8405 do_iwmmxt_textrm (void)
8407 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8408 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8409 inst
.instruction
|= inst
.operands
[2].imm
;
8413 do_iwmmxt_tinsr (void)
8415 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8416 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8417 inst
.instruction
|= inst
.operands
[2].imm
;
8421 do_iwmmxt_tmia (void)
8423 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8424 inst
.instruction
|= inst
.operands
[1].reg
;
8425 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8429 do_iwmmxt_waligni (void)
8431 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8432 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8433 inst
.instruction
|= inst
.operands
[2].reg
;
8434 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8438 do_iwmmxt_wmerge (void)
8440 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8441 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8442 inst
.instruction
|= inst
.operands
[2].reg
;
8443 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8447 do_iwmmxt_wmov (void)
8449 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8450 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8451 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8452 inst
.instruction
|= inst
.operands
[1].reg
;
8456 do_iwmmxt_wldstbh (void)
8459 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8461 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8463 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8464 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8468 do_iwmmxt_wldstw (void)
8470 /* RIWR_RIWC clears .isreg for a control register. */
8471 if (!inst
.operands
[0].isreg
)
8473 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8474 inst
.instruction
|= 0xf0000000;
8477 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8478 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8482 do_iwmmxt_wldstd (void)
8484 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8485 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8486 && inst
.operands
[1].immisreg
)
8488 inst
.instruction
&= ~0x1a000ff;
8489 inst
.instruction
|= (0xf << 28);
8490 if (inst
.operands
[1].preind
)
8491 inst
.instruction
|= PRE_INDEX
;
8492 if (!inst
.operands
[1].negative
)
8493 inst
.instruction
|= INDEX_UP
;
8494 if (inst
.operands
[1].writeback
)
8495 inst
.instruction
|= WRITE_BACK
;
8496 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8497 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8498 inst
.instruction
|= inst
.operands
[1].imm
;
8501 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8505 do_iwmmxt_wshufh (void)
8507 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8508 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8509 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8510 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8514 do_iwmmxt_wzero (void)
8516 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8517 inst
.instruction
|= inst
.operands
[0].reg
;
8518 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8519 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8523 do_iwmmxt_wrwrwr_or_imm5 (void)
8525 if (inst
.operands
[2].isreg
)
8528 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8529 _("immediate operand requires iWMMXt2"));
8531 if (inst
.operands
[2].imm
== 0)
8533 switch ((inst
.instruction
>> 20) & 0xf)
8539 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8540 inst
.operands
[2].imm
= 16;
8541 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8547 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8548 inst
.operands
[2].imm
= 32;
8549 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8556 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8558 wrn
= (inst
.instruction
>> 16) & 0xf;
8559 inst
.instruction
&= 0xff0fff0f;
8560 inst
.instruction
|= wrn
;
8561 /* Bail out here; the instruction is now assembled. */
8566 /* Map 32 -> 0, etc. */
8567 inst
.operands
[2].imm
&= 0x1f;
8568 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8572 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8573 operations first, then control, shift, and load/store. */
8575 /* Insns like "foo X,Y,Z". */
8578 do_mav_triple (void)
8580 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8581 inst
.instruction
|= inst
.operands
[1].reg
;
8582 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8585 /* Insns like "foo W,X,Y,Z".
8586 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8591 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8592 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8593 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8594 inst
.instruction
|= inst
.operands
[3].reg
;
8597 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8601 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8604 /* Maverick shift immediate instructions.
8605 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8606 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8611 int imm
= inst
.operands
[2].imm
;
8613 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8614 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8616 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8617 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8618 Bit 4 should be 0. */
8619 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8621 inst
.instruction
|= imm
;
8624 /* XScale instructions. Also sorted arithmetic before move. */
8626 /* Xscale multiply-accumulate (argument parse)
8629 MIAxycc acc0,Rm,Rs. */
8634 inst
.instruction
|= inst
.operands
[1].reg
;
8635 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8638 /* Xscale move-accumulator-register (argument parse)
8640 MARcc acc0,RdLo,RdHi. */
8645 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8646 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8649 /* Xscale move-register-accumulator (argument parse)
8651 MRAcc RdLo,RdHi,acc0. */
8656 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8657 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8658 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8661 /* Encoding functions relevant only to Thumb. */
8663 /* inst.operands[i] is a shifted-register operand; encode
8664 it into inst.instruction in the format used by Thumb32. */
8667 encode_thumb32_shifted_operand (int i
)
8669 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8670 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8672 constraint (inst
.operands
[i
].immisreg
,
8673 _("shift by register not allowed in thumb mode"));
8674 inst
.instruction
|= inst
.operands
[i
].reg
;
8675 if (shift
== SHIFT_RRX
)
8676 inst
.instruction
|= SHIFT_ROR
<< 4;
8679 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8680 _("expression too complex"));
8682 constraint (value
> 32
8683 || (value
== 32 && (shift
== SHIFT_LSL
8684 || shift
== SHIFT_ROR
)),
8685 _("shift expression is too large"));
8689 else if (value
== 32)
8692 inst
.instruction
|= shift
<< 4;
8693 inst
.instruction
|= (value
& 0x1c) << 10;
8694 inst
.instruction
|= (value
& 0x03) << 6;
8699 /* inst.operands[i] was set up by parse_address. Encode it into a
8700 Thumb32 format load or store instruction. Reject forms that cannot
8701 be used with such instructions. If is_t is true, reject forms that
8702 cannot be used with a T instruction; if is_d is true, reject forms
8703 that cannot be used with a D instruction. */
8706 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8708 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8710 constraint (!inst
.operands
[i
].isreg
,
8711 _("Instruction does not support =N addresses"));
8713 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8714 if (inst
.operands
[i
].immisreg
)
8716 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
8717 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8718 constraint (inst
.operands
[i
].negative
,
8719 _("Thumb does not support negative register indexing"));
8720 constraint (inst
.operands
[i
].postind
,
8721 _("Thumb does not support register post-indexing"));
8722 constraint (inst
.operands
[i
].writeback
,
8723 _("Thumb does not support register indexing with writeback"));
8724 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8725 _("Thumb supports only LSL in shifted register indexing"));
8727 inst
.instruction
|= inst
.operands
[i
].imm
;
8728 if (inst
.operands
[i
].shifted
)
8730 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8731 _("expression too complex"));
8732 constraint (inst
.reloc
.exp
.X_add_number
< 0
8733 || inst
.reloc
.exp
.X_add_number
> 3,
8734 _("shift out of range"));
8735 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8737 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8739 else if (inst
.operands
[i
].preind
)
8741 constraint (is_pc
&& inst
.operands
[i
].writeback
,
8742 _("cannot use writeback with PC-relative addressing"));
8743 constraint (is_t
&& inst
.operands
[i
].writeback
,
8744 _("cannot use writeback with this instruction"));
8748 inst
.instruction
|= 0x01000000;
8749 if (inst
.operands
[i
].writeback
)
8750 inst
.instruction
|= 0x00200000;
8754 inst
.instruction
|= 0x00000c00;
8755 if (inst
.operands
[i
].writeback
)
8756 inst
.instruction
|= 0x00000100;
8758 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8760 else if (inst
.operands
[i
].postind
)
8762 gas_assert (inst
.operands
[i
].writeback
);
8763 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8764 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8767 inst
.instruction
|= 0x00200000;
8769 inst
.instruction
|= 0x00000900;
8770 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8772 else /* unindexed - only for coprocessor */
8773 inst
.error
= _("instruction does not accept unindexed addressing");
8776 /* Table of Thumb instructions which exist in both 16- and 32-bit
8777 encodings (the latter only in post-V6T2 cores). The index is the
8778 value used in the insns table below. When there is more than one
8779 possible 16-bit encoding for the instruction, this table always
8781 Also contains several pseudo-instructions used during relaxation. */
8782 #define T16_32_TAB \
8783 X(_adc, 4140, eb400000), \
8784 X(_adcs, 4140, eb500000), \
8785 X(_add, 1c00, eb000000), \
8786 X(_adds, 1c00, eb100000), \
8787 X(_addi, 0000, f1000000), \
8788 X(_addis, 0000, f1100000), \
8789 X(_add_pc,000f, f20f0000), \
8790 X(_add_sp,000d, f10d0000), \
8791 X(_adr, 000f, f20f0000), \
8792 X(_and, 4000, ea000000), \
8793 X(_ands, 4000, ea100000), \
8794 X(_asr, 1000, fa40f000), \
8795 X(_asrs, 1000, fa50f000), \
8796 X(_b, e000, f000b000), \
8797 X(_bcond, d000, f0008000), \
8798 X(_bic, 4380, ea200000), \
8799 X(_bics, 4380, ea300000), \
8800 X(_cmn, 42c0, eb100f00), \
8801 X(_cmp, 2800, ebb00f00), \
8802 X(_cpsie, b660, f3af8400), \
8803 X(_cpsid, b670, f3af8600), \
8804 X(_cpy, 4600, ea4f0000), \
8805 X(_dec_sp,80dd, f1ad0d00), \
8806 X(_eor, 4040, ea800000), \
8807 X(_eors, 4040, ea900000), \
8808 X(_inc_sp,00dd, f10d0d00), \
8809 X(_ldmia, c800, e8900000), \
8810 X(_ldr, 6800, f8500000), \
8811 X(_ldrb, 7800, f8100000), \
8812 X(_ldrh, 8800, f8300000), \
8813 X(_ldrsb, 5600, f9100000), \
8814 X(_ldrsh, 5e00, f9300000), \
8815 X(_ldr_pc,4800, f85f0000), \
8816 X(_ldr_pc2,4800, f85f0000), \
8817 X(_ldr_sp,9800, f85d0000), \
8818 X(_lsl, 0000, fa00f000), \
8819 X(_lsls, 0000, fa10f000), \
8820 X(_lsr, 0800, fa20f000), \
8821 X(_lsrs, 0800, fa30f000), \
8822 X(_mov, 2000, ea4f0000), \
8823 X(_movs, 2000, ea5f0000), \
8824 X(_mul, 4340, fb00f000), \
8825 X(_muls, 4340, ffffffff), /* no 32b muls */ \
8826 X(_mvn, 43c0, ea6f0000), \
8827 X(_mvns, 43c0, ea7f0000), \
8828 X(_neg, 4240, f1c00000), /* rsb #0 */ \
8829 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
8830 X(_orr, 4300, ea400000), \
8831 X(_orrs, 4300, ea500000), \
8832 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8833 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
8834 X(_rev, ba00, fa90f080), \
8835 X(_rev16, ba40, fa90f090), \
8836 X(_revsh, bac0, fa90f0b0), \
8837 X(_ror, 41c0, fa60f000), \
8838 X(_rors, 41c0, fa70f000), \
8839 X(_sbc, 4180, eb600000), \
8840 X(_sbcs, 4180, eb700000), \
8841 X(_stmia, c000, e8800000), \
8842 X(_str, 6000, f8400000), \
8843 X(_strb, 7000, f8000000), \
8844 X(_strh, 8000, f8200000), \
8845 X(_str_sp,9000, f84d0000), \
8846 X(_sub, 1e00, eba00000), \
8847 X(_subs, 1e00, ebb00000), \
8848 X(_subi, 8000, f1a00000), \
8849 X(_subis, 8000, f1b00000), \
8850 X(_sxtb, b240, fa4ff080), \
8851 X(_sxth, b200, fa0ff080), \
8852 X(_tst, 4200, ea100f00), \
8853 X(_uxtb, b2c0, fa5ff080), \
8854 X(_uxth, b280, fa1ff080), \
8855 X(_nop, bf00, f3af8000), \
8856 X(_yield, bf10, f3af8001), \
8857 X(_wfe, bf20, f3af8002), \
8858 X(_wfi, bf30, f3af8003), \
8859 X(_sev, bf40, f3af8004),
8861 /* To catch errors in encoding functions, the codes are all offset by
8862 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8863 as 16-bit instructions. */
8864 #define X(a,b,c) T_MNEM##a
8865 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8868 #define X(a,b,c) 0x##b
8869 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8870 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8873 #define X(a,b,c) 0x##c
8874 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8875 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8876 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8880 /* Thumb instruction encoders, in alphabetical order. */
8885 do_t_add_sub_w (void)
8889 Rd
= inst
.operands
[0].reg
;
8890 Rn
= inst
.operands
[1].reg
;
8892 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
8893 is the SP-{plus,minus}-immediate form of the instruction. */
8895 constraint (Rd
== REG_PC
, BAD_PC
);
8897 reject_bad_reg (Rd
);
8899 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8900 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8903 /* Parse an add or subtract instruction. We get here with inst.instruction
8904 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8911 Rd
= inst
.operands
[0].reg
;
8912 Rs
= (inst
.operands
[1].present
8913 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8914 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8917 set_it_insn_type_last ();
8925 flags
= (inst
.instruction
== T_MNEM_adds
8926 || inst
.instruction
== T_MNEM_subs
);
8928 narrow
= !in_it_block ();
8930 narrow
= in_it_block ();
8931 if (!inst
.operands
[2].isreg
)
8935 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
8937 add
= (inst
.instruction
== T_MNEM_add
8938 || inst
.instruction
== T_MNEM_adds
);
8940 if (inst
.size_req
!= 4)
8942 /* Attempt to use a narrow opcode, with relaxation if
8944 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8945 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8946 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8947 opcode
= T_MNEM_add_sp
;
8948 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8949 opcode
= T_MNEM_add_pc
;
8950 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8953 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8955 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8959 inst
.instruction
= THUMB_OP16(opcode
);
8960 inst
.instruction
|= (Rd
<< 4) | Rs
;
8961 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8962 if (inst
.size_req
!= 2)
8963 inst
.relax
= opcode
;
8966 constraint (inst
.size_req
== 2, BAD_HIREG
);
8968 if (inst
.size_req
== 4
8969 || (inst
.size_req
!= 2 && !opcode
))
8973 constraint (add
, BAD_PC
);
8974 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
8975 _("only SUBS PC, LR, #const allowed"));
8976 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8977 _("expression too complex"));
8978 constraint (inst
.reloc
.exp
.X_add_number
< 0
8979 || inst
.reloc
.exp
.X_add_number
> 0xff,
8980 _("immediate value out of range"));
8981 inst
.instruction
= T2_SUBS_PC_LR
8982 | inst
.reloc
.exp
.X_add_number
;
8983 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8986 else if (Rs
== REG_PC
)
8988 /* Always use addw/subw. */
8989 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
8990 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8994 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8995 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
8998 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9000 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
9002 inst
.instruction
|= Rd
<< 8;
9003 inst
.instruction
|= Rs
<< 16;
9008 Rn
= inst
.operands
[2].reg
;
9009 /* See if we can do this with a 16-bit instruction. */
9010 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9012 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9017 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9018 || inst
.instruction
== T_MNEM_add
)
9021 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9025 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9027 /* Thumb-1 cores (except v6-M) require at least one high
9028 register in a narrow non flag setting add. */
9029 if (Rd
> 7 || Rn
> 7
9030 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9031 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9038 inst
.instruction
= T_OPCODE_ADD_HI
;
9039 inst
.instruction
|= (Rd
& 8) << 4;
9040 inst
.instruction
|= (Rd
& 7);
9041 inst
.instruction
|= Rn
<< 3;
9047 constraint (Rd
== REG_PC
, BAD_PC
);
9048 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9049 constraint (Rs
== REG_PC
, BAD_PC
);
9050 reject_bad_reg (Rn
);
9052 /* If we get here, it can't be done in 16 bits. */
9053 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9054 _("shift must be constant"));
9055 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9056 inst
.instruction
|= Rd
<< 8;
9057 inst
.instruction
|= Rs
<< 16;
9058 encode_thumb32_shifted_operand (2);
9063 constraint (inst
.instruction
== T_MNEM_adds
9064 || inst
.instruction
== T_MNEM_subs
,
9067 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9069 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9070 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9073 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9075 inst
.instruction
|= (Rd
<< 4) | Rs
;
9076 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9080 Rn
= inst
.operands
[2].reg
;
9081 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9083 /* We now have Rd, Rs, and Rn set to registers. */
9084 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9086 /* Can't do this for SUB. */
9087 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9088 inst
.instruction
= T_OPCODE_ADD_HI
;
9089 inst
.instruction
|= (Rd
& 8) << 4;
9090 inst
.instruction
|= (Rd
& 7);
9092 inst
.instruction
|= Rn
<< 3;
9094 inst
.instruction
|= Rs
<< 3;
9096 constraint (1, _("dest must overlap one source register"));
9100 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9101 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9102 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9112 Rd
= inst
.operands
[0].reg
;
9113 reject_bad_reg (Rd
);
9115 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9117 /* Defer to section relaxation. */
9118 inst
.relax
= inst
.instruction
;
9119 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9120 inst
.instruction
|= Rd
<< 4;
9122 else if (unified_syntax
&& inst
.size_req
!= 2)
9124 /* Generate a 32-bit opcode. */
9125 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9126 inst
.instruction
|= Rd
<< 8;
9127 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9128 inst
.reloc
.pc_rel
= 1;
9132 /* Generate a 16-bit opcode. */
9133 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9134 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9135 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9136 inst
.reloc
.pc_rel
= 1;
9138 inst
.instruction
|= Rd
<< 4;
9142 /* Arithmetic instructions for which there is just one 16-bit
9143 instruction encoding, and it allows only two low registers.
9144 For maximal compatibility with ARM syntax, we allow three register
9145 operands even when Thumb-32 instructions are not available, as long
9146 as the first two are identical. For instance, both "sbc r0,r1" and
9147 "sbc r0,r0,r1" are allowed. */
9153 Rd
= inst
.operands
[0].reg
;
9154 Rs
= (inst
.operands
[1].present
9155 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9156 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9157 Rn
= inst
.operands
[2].reg
;
9159 reject_bad_reg (Rd
);
9160 reject_bad_reg (Rs
);
9161 if (inst
.operands
[2].isreg
)
9162 reject_bad_reg (Rn
);
9166 if (!inst
.operands
[2].isreg
)
9168 /* For an immediate, we always generate a 32-bit opcode;
9169 section relaxation will shrink it later if possible. */
9170 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9171 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9172 inst
.instruction
|= Rd
<< 8;
9173 inst
.instruction
|= Rs
<< 16;
9174 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9180 /* See if we can do this with a 16-bit instruction. */
9181 if (THUMB_SETS_FLAGS (inst
.instruction
))
9182 narrow
= !in_it_block ();
9184 narrow
= in_it_block ();
9186 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9188 if (inst
.operands
[2].shifted
)
9190 if (inst
.size_req
== 4)
9196 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9197 inst
.instruction
|= Rd
;
9198 inst
.instruction
|= Rn
<< 3;
9202 /* If we get here, it can't be done in 16 bits. */
9203 constraint (inst
.operands
[2].shifted
9204 && inst
.operands
[2].immisreg
,
9205 _("shift must be constant"));
9206 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9207 inst
.instruction
|= Rd
<< 8;
9208 inst
.instruction
|= Rs
<< 16;
9209 encode_thumb32_shifted_operand (2);
9214 /* On its face this is a lie - the instruction does set the
9215 flags. However, the only supported mnemonic in this mode
9217 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9219 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9220 _("unshifted register required"));
9221 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9222 constraint (Rd
!= Rs
,
9223 _("dest and source1 must be the same register"));
9225 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9226 inst
.instruction
|= Rd
;
9227 inst
.instruction
|= Rn
<< 3;
9231 /* Similarly, but for instructions where the arithmetic operation is
9232 commutative, so we can allow either of them to be different from
9233 the destination operand in a 16-bit instruction. For instance, all
9234 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9241 Rd
= inst
.operands
[0].reg
;
9242 Rs
= (inst
.operands
[1].present
9243 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9244 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9245 Rn
= inst
.operands
[2].reg
;
9247 reject_bad_reg (Rd
);
9248 reject_bad_reg (Rs
);
9249 if (inst
.operands
[2].isreg
)
9250 reject_bad_reg (Rn
);
9254 if (!inst
.operands
[2].isreg
)
9256 /* For an immediate, we always generate a 32-bit opcode;
9257 section relaxation will shrink it later if possible. */
9258 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9259 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9260 inst
.instruction
|= Rd
<< 8;
9261 inst
.instruction
|= Rs
<< 16;
9262 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9268 /* See if we can do this with a 16-bit instruction. */
9269 if (THUMB_SETS_FLAGS (inst
.instruction
))
9270 narrow
= !in_it_block ();
9272 narrow
= in_it_block ();
9274 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9276 if (inst
.operands
[2].shifted
)
9278 if (inst
.size_req
== 4)
9285 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9286 inst
.instruction
|= Rd
;
9287 inst
.instruction
|= Rn
<< 3;
9292 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9293 inst
.instruction
|= Rd
;
9294 inst
.instruction
|= Rs
<< 3;
9299 /* If we get here, it can't be done in 16 bits. */
9300 constraint (inst
.operands
[2].shifted
9301 && inst
.operands
[2].immisreg
,
9302 _("shift must be constant"));
9303 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9304 inst
.instruction
|= Rd
<< 8;
9305 inst
.instruction
|= Rs
<< 16;
9306 encode_thumb32_shifted_operand (2);
9311 /* On its face this is a lie - the instruction does set the
9312 flags. However, the only supported mnemonic in this mode
9314 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9316 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9317 _("unshifted register required"));
9318 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9320 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9321 inst
.instruction
|= Rd
;
9324 inst
.instruction
|= Rn
<< 3;
9326 inst
.instruction
|= Rs
<< 3;
9328 constraint (1, _("dest must overlap one source register"));
9335 if (inst
.operands
[0].present
)
9337 constraint ((inst
.instruction
& 0xf0) != 0x40
9338 && inst
.operands
[0].imm
!= 0xf,
9339 _("bad barrier type"));
9340 inst
.instruction
|= inst
.operands
[0].imm
;
9343 inst
.instruction
|= 0xf;
9350 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9351 constraint (msb
> 32, _("bit-field extends past end of register"));
9352 /* The instruction encoding stores the LSB and MSB,
9353 not the LSB and width. */
9354 Rd
= inst
.operands
[0].reg
;
9355 reject_bad_reg (Rd
);
9356 inst
.instruction
|= Rd
<< 8;
9357 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9358 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9359 inst
.instruction
|= msb
- 1;
9368 Rd
= inst
.operands
[0].reg
;
9369 reject_bad_reg (Rd
);
9371 /* #0 in second position is alternative syntax for bfc, which is
9372 the same instruction but with REG_PC in the Rm field. */
9373 if (!inst
.operands
[1].isreg
)
9377 Rn
= inst
.operands
[1].reg
;
9378 reject_bad_reg (Rn
);
9381 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9382 constraint (msb
> 32, _("bit-field extends past end of register"));
9383 /* The instruction encoding stores the LSB and MSB,
9384 not the LSB and width. */
9385 inst
.instruction
|= Rd
<< 8;
9386 inst
.instruction
|= Rn
<< 16;
9387 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9388 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9389 inst
.instruction
|= msb
- 1;
9397 Rd
= inst
.operands
[0].reg
;
9398 Rn
= inst
.operands
[1].reg
;
9400 reject_bad_reg (Rd
);
9401 reject_bad_reg (Rn
);
9403 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9404 _("bit-field extends past end of register"));
9405 inst
.instruction
|= Rd
<< 8;
9406 inst
.instruction
|= Rn
<< 16;
9407 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9408 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9409 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9412 /* ARM V5 Thumb BLX (argument parse)
9413 BLX <target_addr> which is BLX(1)
9414 BLX <Rm> which is BLX(2)
9415 Unfortunately, there are two different opcodes for this mnemonic.
9416 So, the insns[].value is not used, and the code here zaps values
9417 into inst.instruction.
9419 ??? How to take advantage of the additional two bits of displacement
9420 available in Thumb32 mode? Need new relocation? */
9425 set_it_insn_type_last ();
9427 if (inst
.operands
[0].isreg
)
9429 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9430 /* We have a register, so this is BLX(2). */
9431 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9435 /* No register. This must be BLX(1). */
9436 inst
.instruction
= 0xf000e800;
9437 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
9438 inst
.reloc
.pc_rel
= 1;
9449 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9453 /* Conditional branches inside IT blocks are encoded as unconditional
9460 if (cond
!= COND_ALWAYS
)
9461 opcode
= T_MNEM_bcond
;
9463 opcode
= inst
.instruction
;
9465 if (unified_syntax
&& inst
.size_req
== 4)
9467 inst
.instruction
= THUMB_OP32(opcode
);
9468 if (cond
== COND_ALWAYS
)
9469 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9472 gas_assert (cond
!= 0xF);
9473 inst
.instruction
|= cond
<< 22;
9474 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9479 inst
.instruction
= THUMB_OP16(opcode
);
9480 if (cond
== COND_ALWAYS
)
9481 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9484 inst
.instruction
|= cond
<< 8;
9485 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9487 /* Allow section relaxation. */
9488 if (unified_syntax
&& inst
.size_req
!= 2)
9489 inst
.relax
= opcode
;
9492 inst
.reloc
.pc_rel
= 1;
9498 constraint (inst
.cond
!= COND_ALWAYS
,
9499 _("instruction is always unconditional"));
9500 if (inst
.operands
[0].present
)
9502 constraint (inst
.operands
[0].imm
> 255,
9503 _("immediate value out of range"));
9504 inst
.instruction
|= inst
.operands
[0].imm
;
9505 set_it_insn_type (NEUTRAL_IT_INSN
);
9510 do_t_branch23 (void)
9512 set_it_insn_type_last ();
9513 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9514 inst
.reloc
.pc_rel
= 1;
9516 #if defined(OBJ_COFF)
9517 /* If the destination of the branch is a defined symbol which does not have
9518 the THUMB_FUNC attribute, then we must be calling a function which has
9519 the (interfacearm) attribute. We look for the Thumb entry point to that
9520 function and change the branch to refer to that function instead. */
9521 if ( inst
.reloc
.exp
.X_op
== O_symbol
9522 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9523 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9524 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9525 inst
.reloc
.exp
.X_add_symbol
=
9526 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9533 set_it_insn_type_last ();
9534 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9535 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9536 should cause the alignment to be checked once it is known. This is
9537 because BX PC only works if the instruction is word aligned. */
9545 set_it_insn_type_last ();
9546 Rm
= inst
.operands
[0].reg
;
9547 reject_bad_reg (Rm
);
9548 inst
.instruction
|= Rm
<< 16;
9557 Rd
= inst
.operands
[0].reg
;
9558 Rm
= inst
.operands
[1].reg
;
9560 reject_bad_reg (Rd
);
9561 reject_bad_reg (Rm
);
9563 inst
.instruction
|= Rd
<< 8;
9564 inst
.instruction
|= Rm
<< 16;
9565 inst
.instruction
|= Rm
;
9571 set_it_insn_type (OUTSIDE_IT_INSN
);
9572 inst
.instruction
|= inst
.operands
[0].imm
;
9578 set_it_insn_type (OUTSIDE_IT_INSN
);
9580 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9581 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9583 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9584 inst
.instruction
= 0xf3af8000;
9585 inst
.instruction
|= imod
<< 9;
9586 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9587 if (inst
.operands
[1].present
)
9588 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9592 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9593 && (inst
.operands
[0].imm
& 4),
9594 _("selected processor does not support 'A' form "
9595 "of this instruction"));
9596 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9597 _("Thumb does not support the 2-argument "
9598 "form of this instruction"));
9599 inst
.instruction
|= inst
.operands
[0].imm
;
9603 /* THUMB CPY instruction (argument parse). */
9608 if (inst
.size_req
== 4)
9610 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9611 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9612 inst
.instruction
|= inst
.operands
[1].reg
;
9616 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9617 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9618 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9625 set_it_insn_type (OUTSIDE_IT_INSN
);
9626 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9627 inst
.instruction
|= inst
.operands
[0].reg
;
9628 inst
.reloc
.pc_rel
= 1;
9629 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9635 inst
.instruction
|= inst
.operands
[0].imm
;
9641 unsigned Rd
, Rn
, Rm
;
9643 Rd
= inst
.operands
[0].reg
;
9644 Rn
= (inst
.operands
[1].present
9645 ? inst
.operands
[1].reg
: Rd
);
9646 Rm
= inst
.operands
[2].reg
;
9648 reject_bad_reg (Rd
);
9649 reject_bad_reg (Rn
);
9650 reject_bad_reg (Rm
);
9652 inst
.instruction
|= Rd
<< 8;
9653 inst
.instruction
|= Rn
<< 16;
9654 inst
.instruction
|= Rm
;
9660 if (unified_syntax
&& inst
.size_req
== 4)
9661 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9663 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9669 unsigned int cond
= inst
.operands
[0].imm
;
9671 set_it_insn_type (IT_INSN
);
9672 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
9675 /* If the condition is a negative condition, invert the mask. */
9676 if ((cond
& 0x1) == 0x0)
9678 unsigned int mask
= inst
.instruction
& 0x000f;
9680 if ((mask
& 0x7) == 0)
9681 /* no conversion needed */;
9682 else if ((mask
& 0x3) == 0)
9684 else if ((mask
& 0x1) == 0)
9689 inst
.instruction
&= 0xfff0;
9690 inst
.instruction
|= mask
;
9693 inst
.instruction
|= cond
<< 4;
9696 /* Helper function used for both push/pop and ldm/stm. */
9698 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9702 load
= (inst
.instruction
& (1 << 20)) != 0;
9704 if (mask
& (1 << 13))
9705 inst
.error
= _("SP not allowed in register list");
9708 if (mask
& (1 << 15))
9710 if (mask
& (1 << 14))
9711 inst
.error
= _("LR and PC should not both be in register list");
9713 set_it_insn_type_last ();
9716 if ((mask
& (1 << base
)) != 0
9718 as_warn (_("base register should not be in register list "
9719 "when written back"));
9723 if (mask
& (1 << 15))
9724 inst
.error
= _("PC not allowed in register list");
9726 if (mask
& (1 << base
))
9727 as_warn (_("value stored for r%d is UNPREDICTABLE"), base
);
9730 if ((mask
& (mask
- 1)) == 0)
9732 /* Single register transfers implemented as str/ldr. */
9735 if (inst
.instruction
& (1 << 23))
9736 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9738 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9742 if (inst
.instruction
& (1 << 23))
9743 inst
.instruction
= 0x00800000; /* ia -> [base] */
9745 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9748 inst
.instruction
|= 0xf8400000;
9750 inst
.instruction
|= 0x00100000;
9752 mask
= ffs (mask
) - 1;
9756 inst
.instruction
|= WRITE_BACK
;
9758 inst
.instruction
|= mask
;
9759 inst
.instruction
|= base
<< 16;
9765 /* This really doesn't seem worth it. */
9766 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9767 _("expression too complex"));
9768 constraint (inst
.operands
[1].writeback
,
9769 _("Thumb load/store multiple does not support {reglist}^"));
9777 /* See if we can use a 16-bit instruction. */
9778 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9779 && inst
.size_req
!= 4
9780 && !(inst
.operands
[1].imm
& ~0xff))
9782 mask
= 1 << inst
.operands
[0].reg
;
9784 if (inst
.operands
[0].reg
<= 7
9785 && (inst
.instruction
== T_MNEM_stmia
9786 ? inst
.operands
[0].writeback
9787 : (inst
.operands
[0].writeback
9788 == !(inst
.operands
[1].imm
& mask
))))
9790 if (inst
.instruction
== T_MNEM_stmia
9791 && (inst
.operands
[1].imm
& mask
)
9792 && (inst
.operands
[1].imm
& (mask
- 1)))
9793 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9794 inst
.operands
[0].reg
);
9796 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9797 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9798 inst
.instruction
|= inst
.operands
[1].imm
;
9801 else if (inst
.operands
[0] .reg
== REG_SP
9802 && inst
.operands
[0].writeback
)
9804 inst
.instruction
= THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9805 ? T_MNEM_push
: T_MNEM_pop
);
9806 inst
.instruction
|= inst
.operands
[1].imm
;
9813 if (inst
.instruction
< 0xffff)
9814 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9816 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
9817 inst
.operands
[0].writeback
);
9822 constraint (inst
.operands
[0].reg
> 7
9823 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9824 constraint (inst
.instruction
!= T_MNEM_ldmia
9825 && inst
.instruction
!= T_MNEM_stmia
,
9826 _("Thumb-2 instruction only valid in unified syntax"));
9827 if (inst
.instruction
== T_MNEM_stmia
)
9829 if (!inst
.operands
[0].writeback
)
9830 as_warn (_("this instruction will write back the base register"));
9831 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9832 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9833 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9834 inst
.operands
[0].reg
);
9838 if (!inst
.operands
[0].writeback
9839 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9840 as_warn (_("this instruction will write back the base register"));
9841 else if (inst
.operands
[0].writeback
9842 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9843 as_warn (_("this instruction will not write back the base register"));
9846 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9847 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9848 inst
.instruction
|= inst
.operands
[1].imm
;
9855 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9856 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9857 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9858 || inst
.operands
[1].negative
,
9861 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9862 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9863 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9869 if (!inst
.operands
[1].present
)
9871 constraint (inst
.operands
[0].reg
== REG_LR
,
9872 _("r14 not allowed as first register "
9873 "when second register is omitted"));
9874 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9876 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9879 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9880 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9881 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9887 unsigned long opcode
;
9890 if (inst
.operands
[0].isreg
9891 && !inst
.operands
[0].preind
9892 && inst
.operands
[0].reg
== REG_PC
)
9893 set_it_insn_type_last ();
9895 opcode
= inst
.instruction
;
9898 if (!inst
.operands
[1].isreg
)
9900 if (opcode
<= 0xffff)
9901 inst
.instruction
= THUMB_OP32 (opcode
);
9902 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9905 if (inst
.operands
[1].isreg
9906 && !inst
.operands
[1].writeback
9907 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9908 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9910 && inst
.size_req
!= 4)
9912 /* Insn may have a 16-bit form. */
9913 Rn
= inst
.operands
[1].reg
;
9914 if (inst
.operands
[1].immisreg
)
9916 inst
.instruction
= THUMB_OP16 (opcode
);
9918 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9921 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9922 && opcode
!= T_MNEM_ldrsb
)
9923 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9924 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9931 if (inst
.reloc
.pc_rel
)
9932 opcode
= T_MNEM_ldr_pc2
;
9934 opcode
= T_MNEM_ldr_pc
;
9938 if (opcode
== T_MNEM_ldr
)
9939 opcode
= T_MNEM_ldr_sp
;
9941 opcode
= T_MNEM_str_sp
;
9943 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9947 inst
.instruction
= inst
.operands
[0].reg
;
9948 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9950 inst
.instruction
|= THUMB_OP16 (opcode
);
9951 if (inst
.size_req
== 2)
9952 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9954 inst
.relax
= opcode
;
9958 /* Definitely a 32-bit variant. */
9959 inst
.instruction
= THUMB_OP32 (opcode
);
9960 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9961 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9965 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9967 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9969 /* Only [Rn,Rm] is acceptable. */
9970 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9971 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9972 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9973 || inst
.operands
[1].negative
,
9974 _("Thumb does not support this addressing mode"));
9975 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9979 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9980 if (!inst
.operands
[1].isreg
)
9981 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9984 constraint (!inst
.operands
[1].preind
9985 || inst
.operands
[1].shifted
9986 || inst
.operands
[1].writeback
,
9987 _("Thumb does not support this addressing mode"));
9988 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9990 constraint (inst
.instruction
& 0x0600,
9991 _("byte or halfword not valid for base register"));
9992 constraint (inst
.operands
[1].reg
== REG_PC
9993 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9994 _("r15 based store not allowed"));
9995 constraint (inst
.operands
[1].immisreg
,
9996 _("invalid base register for register offset"));
9998 if (inst
.operands
[1].reg
== REG_PC
)
9999 inst
.instruction
= T_OPCODE_LDR_PC
;
10000 else if (inst
.instruction
& THUMB_LOAD_BIT
)
10001 inst
.instruction
= T_OPCODE_LDR_SP
;
10003 inst
.instruction
= T_OPCODE_STR_SP
;
10005 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10006 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10010 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10011 if (!inst
.operands
[1].immisreg
)
10013 /* Immediate offset. */
10014 inst
.instruction
|= inst
.operands
[0].reg
;
10015 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10016 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10020 /* Register offset. */
10021 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10022 constraint (inst
.operands
[1].negative
,
10023 _("Thumb does not support this addressing mode"));
10026 switch (inst
.instruction
)
10028 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10029 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10030 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10031 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10032 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10033 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10034 case 0x5600 /* ldrsb */:
10035 case 0x5e00 /* ldrsh */: break;
10039 inst
.instruction
|= inst
.operands
[0].reg
;
10040 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10041 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
10047 if (!inst
.operands
[1].present
)
10049 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10050 constraint (inst
.operands
[0].reg
== REG_LR
,
10051 _("r14 not allowed here"));
10053 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10054 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10055 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10061 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10062 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10068 unsigned Rd
, Rn
, Rm
, Ra
;
10070 Rd
= inst
.operands
[0].reg
;
10071 Rn
= inst
.operands
[1].reg
;
10072 Rm
= inst
.operands
[2].reg
;
10073 Ra
= inst
.operands
[3].reg
;
10075 reject_bad_reg (Rd
);
10076 reject_bad_reg (Rn
);
10077 reject_bad_reg (Rm
);
10078 reject_bad_reg (Ra
);
10080 inst
.instruction
|= Rd
<< 8;
10081 inst
.instruction
|= Rn
<< 16;
10082 inst
.instruction
|= Rm
;
10083 inst
.instruction
|= Ra
<< 12;
10089 unsigned RdLo
, RdHi
, Rn
, Rm
;
10091 RdLo
= inst
.operands
[0].reg
;
10092 RdHi
= inst
.operands
[1].reg
;
10093 Rn
= inst
.operands
[2].reg
;
10094 Rm
= inst
.operands
[3].reg
;
10096 reject_bad_reg (RdLo
);
10097 reject_bad_reg (RdHi
);
10098 reject_bad_reg (Rn
);
10099 reject_bad_reg (Rm
);
10101 inst
.instruction
|= RdLo
<< 12;
10102 inst
.instruction
|= RdHi
<< 8;
10103 inst
.instruction
|= Rn
<< 16;
10104 inst
.instruction
|= Rm
;
10108 do_t_mov_cmp (void)
10112 Rn
= inst
.operands
[0].reg
;
10113 Rm
= inst
.operands
[1].reg
;
10116 set_it_insn_type_last ();
10118 if (unified_syntax
)
10120 int r0off
= (inst
.instruction
== T_MNEM_mov
10121 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10122 unsigned long opcode
;
10123 bfd_boolean narrow
;
10124 bfd_boolean low_regs
;
10126 low_regs
= (Rn
<= 7 && Rm
<= 7);
10127 opcode
= inst
.instruction
;
10128 if (in_it_block ())
10129 narrow
= opcode
!= T_MNEM_movs
;
10131 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10132 if (inst
.size_req
== 4
10133 || inst
.operands
[1].shifted
)
10136 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10137 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10138 && !inst
.operands
[1].shifted
10142 inst
.instruction
= T2_SUBS_PC_LR
;
10146 if (opcode
== T_MNEM_cmp
)
10148 constraint (Rn
== REG_PC
, BAD_PC
);
10151 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10153 warn_deprecated_sp (Rm
);
10154 /* R15 was documented as a valid choice for Rm in ARMv6,
10155 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10156 tools reject R15, so we do too. */
10157 constraint (Rm
== REG_PC
, BAD_PC
);
10160 reject_bad_reg (Rm
);
10162 else if (opcode
== T_MNEM_mov
10163 || opcode
== T_MNEM_movs
)
10165 if (inst
.operands
[1].isreg
)
10167 if (opcode
== T_MNEM_movs
)
10169 reject_bad_reg (Rn
);
10170 reject_bad_reg (Rm
);
10172 else if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10173 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10174 reject_bad_reg (Rm
);
10177 reject_bad_reg (Rn
);
10180 if (!inst
.operands
[1].isreg
)
10182 /* Immediate operand. */
10183 if (!in_it_block () && opcode
== T_MNEM_mov
)
10185 if (low_regs
&& narrow
)
10187 inst
.instruction
= THUMB_OP16 (opcode
);
10188 inst
.instruction
|= Rn
<< 8;
10189 if (inst
.size_req
== 2)
10190 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10192 inst
.relax
= opcode
;
10196 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10197 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10198 inst
.instruction
|= Rn
<< r0off
;
10199 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10202 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10203 && (inst
.instruction
== T_MNEM_mov
10204 || inst
.instruction
== T_MNEM_movs
))
10206 /* Register shifts are encoded as separate shift instructions. */
10207 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10209 if (in_it_block ())
10214 if (inst
.size_req
== 4)
10217 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10223 switch (inst
.operands
[1].shift_kind
)
10226 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10229 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10232 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10235 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10241 inst
.instruction
= opcode
;
10244 inst
.instruction
|= Rn
;
10245 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10250 inst
.instruction
|= CONDS_BIT
;
10252 inst
.instruction
|= Rn
<< 8;
10253 inst
.instruction
|= Rm
<< 16;
10254 inst
.instruction
|= inst
.operands
[1].imm
;
10259 /* Some mov with immediate shift have narrow variants.
10260 Register shifts are handled above. */
10261 if (low_regs
&& inst
.operands
[1].shifted
10262 && (inst
.instruction
== T_MNEM_mov
10263 || inst
.instruction
== T_MNEM_movs
))
10265 if (in_it_block ())
10266 narrow
= (inst
.instruction
== T_MNEM_mov
);
10268 narrow
= (inst
.instruction
== T_MNEM_movs
);
10273 switch (inst
.operands
[1].shift_kind
)
10275 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10276 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10277 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10278 default: narrow
= FALSE
; break;
10284 inst
.instruction
|= Rn
;
10285 inst
.instruction
|= Rm
<< 3;
10286 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10290 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10291 inst
.instruction
|= Rn
<< r0off
;
10292 encode_thumb32_shifted_operand (1);
10296 switch (inst
.instruction
)
10299 inst
.instruction
= T_OPCODE_MOV_HR
;
10300 inst
.instruction
|= (Rn
& 0x8) << 4;
10301 inst
.instruction
|= (Rn
& 0x7);
10302 inst
.instruction
|= Rm
<< 3;
10306 /* We know we have low registers at this point.
10307 Generate ADD Rd, Rs, #0. */
10308 inst
.instruction
= T_OPCODE_ADD_I3
;
10309 inst
.instruction
|= Rn
;
10310 inst
.instruction
|= Rm
<< 3;
10316 inst
.instruction
= T_OPCODE_CMP_LR
;
10317 inst
.instruction
|= Rn
;
10318 inst
.instruction
|= Rm
<< 3;
10322 inst
.instruction
= T_OPCODE_CMP_HR
;
10323 inst
.instruction
|= (Rn
& 0x8) << 4;
10324 inst
.instruction
|= (Rn
& 0x7);
10325 inst
.instruction
|= Rm
<< 3;
10332 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10334 /* PR 10443: Do not silently ignore shifted operands. */
10335 constraint (inst
.operands
[1].shifted
,
10336 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10338 if (inst
.operands
[1].isreg
)
10340 if (Rn
< 8 && Rm
< 8)
10342 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10343 since a MOV instruction produces unpredictable results. */
10344 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10345 inst
.instruction
= T_OPCODE_ADD_I3
;
10347 inst
.instruction
= T_OPCODE_CMP_LR
;
10349 inst
.instruction
|= Rn
;
10350 inst
.instruction
|= Rm
<< 3;
10354 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10355 inst
.instruction
= T_OPCODE_MOV_HR
;
10357 inst
.instruction
= T_OPCODE_CMP_HR
;
10363 constraint (Rn
> 7,
10364 _("only lo regs allowed with immediate"));
10365 inst
.instruction
|= Rn
<< 8;
10366 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10377 top
= (inst
.instruction
& 0x00800000) != 0;
10378 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
10380 constraint (top
, _(":lower16: not allowed this instruction"));
10381 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
10383 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
10385 constraint (!top
, _(":upper16: not allowed this instruction"));
10386 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
10389 Rd
= inst
.operands
[0].reg
;
10390 reject_bad_reg (Rd
);
10392 inst
.instruction
|= Rd
<< 8;
10393 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
10395 imm
= inst
.reloc
.exp
.X_add_number
;
10396 inst
.instruction
|= (imm
& 0xf000) << 4;
10397 inst
.instruction
|= (imm
& 0x0800) << 15;
10398 inst
.instruction
|= (imm
& 0x0700) << 4;
10399 inst
.instruction
|= (imm
& 0x00ff);
10404 do_t_mvn_tst (void)
10408 Rn
= inst
.operands
[0].reg
;
10409 Rm
= inst
.operands
[1].reg
;
10411 if (inst
.instruction
== T_MNEM_cmp
10412 || inst
.instruction
== T_MNEM_cmn
)
10413 constraint (Rn
== REG_PC
, BAD_PC
);
10415 reject_bad_reg (Rn
);
10416 reject_bad_reg (Rm
);
10418 if (unified_syntax
)
10420 int r0off
= (inst
.instruction
== T_MNEM_mvn
10421 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
10422 bfd_boolean narrow
;
10424 if (inst
.size_req
== 4
10425 || inst
.instruction
> 0xffff
10426 || inst
.operands
[1].shifted
10427 || Rn
> 7 || Rm
> 7)
10429 else if (inst
.instruction
== T_MNEM_cmn
)
10431 else if (THUMB_SETS_FLAGS (inst
.instruction
))
10432 narrow
= !in_it_block ();
10434 narrow
= in_it_block ();
10436 if (!inst
.operands
[1].isreg
)
10438 /* For an immediate, we always generate a 32-bit opcode;
10439 section relaxation will shrink it later if possible. */
10440 if (inst
.instruction
< 0xffff)
10441 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10442 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10443 inst
.instruction
|= Rn
<< r0off
;
10444 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10448 /* See if we can do this with a 16-bit instruction. */
10451 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10452 inst
.instruction
|= Rn
;
10453 inst
.instruction
|= Rm
<< 3;
10457 constraint (inst
.operands
[1].shifted
10458 && inst
.operands
[1].immisreg
,
10459 _("shift must be constant"));
10460 if (inst
.instruction
< 0xffff)
10461 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10462 inst
.instruction
|= Rn
<< r0off
;
10463 encode_thumb32_shifted_operand (1);
10469 constraint (inst
.instruction
> 0xffff
10470 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
10471 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
10472 _("unshifted register required"));
10473 constraint (Rn
> 7 || Rm
> 7,
10476 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10477 inst
.instruction
|= Rn
;
10478 inst
.instruction
|= Rm
<< 3;
10488 if (do_vfp_nsyn_mrs () == SUCCESS
)
10491 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
10494 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10495 _("selected processor does not support "
10496 "requested special purpose register"));
10500 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10501 _("selected processor does not support "
10502 "requested special purpose register"));
10503 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10504 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
10505 _("'CPSR' or 'SPSR' expected"));
10508 Rd
= inst
.operands
[0].reg
;
10509 reject_bad_reg (Rd
);
10511 inst
.instruction
|= Rd
<< 8;
10512 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10513 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
10522 if (do_vfp_nsyn_msr () == SUCCESS
)
10525 constraint (!inst
.operands
[1].isreg
,
10526 _("Thumb encoding does not support an immediate here"));
10527 flags
= inst
.operands
[0].imm
;
10530 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10531 _("selected processor does not support "
10532 "requested special purpose register"));
10536 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10537 _("selected processor does not support "
10538 "requested special purpose register"));
10542 Rn
= inst
.operands
[1].reg
;
10543 reject_bad_reg (Rn
);
10545 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10546 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
10547 inst
.instruction
|= (flags
& 0xff);
10548 inst
.instruction
|= Rn
<< 16;
10554 bfd_boolean narrow
;
10555 unsigned Rd
, Rn
, Rm
;
10557 if (!inst
.operands
[2].present
)
10558 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10560 Rd
= inst
.operands
[0].reg
;
10561 Rn
= inst
.operands
[1].reg
;
10562 Rm
= inst
.operands
[2].reg
;
10564 if (unified_syntax
)
10566 if (inst
.size_req
== 4
10572 else if (inst
.instruction
== T_MNEM_muls
)
10573 narrow
= !in_it_block ();
10575 narrow
= in_it_block ();
10579 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
10580 constraint (Rn
> 7 || Rm
> 7,
10587 /* 16-bit MULS/Conditional MUL. */
10588 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10589 inst
.instruction
|= Rd
;
10592 inst
.instruction
|= Rm
<< 3;
10594 inst
.instruction
|= Rn
<< 3;
10596 constraint (1, _("dest must overlap one source register"));
10600 constraint (inst
.instruction
!= T_MNEM_mul
,
10601 _("Thumb-2 MUL must not set flags"));
10603 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10604 inst
.instruction
|= Rd
<< 8;
10605 inst
.instruction
|= Rn
<< 16;
10606 inst
.instruction
|= Rm
<< 0;
10608 reject_bad_reg (Rd
);
10609 reject_bad_reg (Rn
);
10610 reject_bad_reg (Rm
);
10617 unsigned RdLo
, RdHi
, Rn
, Rm
;
10619 RdLo
= inst
.operands
[0].reg
;
10620 RdHi
= inst
.operands
[1].reg
;
10621 Rn
= inst
.operands
[2].reg
;
10622 Rm
= inst
.operands
[3].reg
;
10624 reject_bad_reg (RdLo
);
10625 reject_bad_reg (RdHi
);
10626 reject_bad_reg (Rn
);
10627 reject_bad_reg (Rm
);
10629 inst
.instruction
|= RdLo
<< 12;
10630 inst
.instruction
|= RdHi
<< 8;
10631 inst
.instruction
|= Rn
<< 16;
10632 inst
.instruction
|= Rm
;
10635 as_tsktsk (_("rdhi and rdlo must be different"));
10641 set_it_insn_type (NEUTRAL_IT_INSN
);
10643 if (unified_syntax
)
10645 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
10647 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10648 inst
.instruction
|= inst
.operands
[0].imm
;
10652 /* PR9722: Check for Thumb2 availability before
10653 generating a thumb2 nop instruction. */
10654 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
10656 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10657 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
10660 inst
.instruction
= 0x46c0;
10665 constraint (inst
.operands
[0].present
,
10666 _("Thumb does not support NOP with hints"));
10667 inst
.instruction
= 0x46c0;
10674 if (unified_syntax
)
10676 bfd_boolean narrow
;
10678 if (THUMB_SETS_FLAGS (inst
.instruction
))
10679 narrow
= !in_it_block ();
10681 narrow
= in_it_block ();
10682 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10684 if (inst
.size_req
== 4)
10689 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10690 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10691 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10695 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10696 inst
.instruction
|= inst
.operands
[0].reg
;
10697 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10702 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
10704 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10706 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10707 inst
.instruction
|= inst
.operands
[0].reg
;
10708 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10717 Rd
= inst
.operands
[0].reg
;
10718 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
10720 reject_bad_reg (Rd
);
10721 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
10722 reject_bad_reg (Rn
);
10724 inst
.instruction
|= Rd
<< 8;
10725 inst
.instruction
|= Rn
<< 16;
10727 if (!inst
.operands
[2].isreg
)
10729 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10730 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10736 Rm
= inst
.operands
[2].reg
;
10737 reject_bad_reg (Rm
);
10739 constraint (inst
.operands
[2].shifted
10740 && inst
.operands
[2].immisreg
,
10741 _("shift must be constant"));
10742 encode_thumb32_shifted_operand (2);
10749 unsigned Rd
, Rn
, Rm
;
10751 Rd
= inst
.operands
[0].reg
;
10752 Rn
= inst
.operands
[1].reg
;
10753 Rm
= inst
.operands
[2].reg
;
10755 reject_bad_reg (Rd
);
10756 reject_bad_reg (Rn
);
10757 reject_bad_reg (Rm
);
10759 inst
.instruction
|= Rd
<< 8;
10760 inst
.instruction
|= Rn
<< 16;
10761 inst
.instruction
|= Rm
;
10762 if (inst
.operands
[3].present
)
10764 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
10765 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10766 _("expression too complex"));
10767 inst
.instruction
|= (val
& 0x1c) << 10;
10768 inst
.instruction
|= (val
& 0x03) << 6;
10775 if (!inst
.operands
[3].present
)
10779 inst
.instruction
&= ~0x00000020;
10781 /* PR 10168. Swap the Rm and Rn registers. */
10782 Rtmp
= inst
.operands
[1].reg
;
10783 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
10784 inst
.operands
[2].reg
= Rtmp
;
10792 if (inst
.operands
[0].immisreg
)
10793 reject_bad_reg (inst
.operands
[0].imm
);
10795 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10799 do_t_push_pop (void)
10803 constraint (inst
.operands
[0].writeback
,
10804 _("push/pop do not support {reglist}^"));
10805 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10806 _("expression too complex"));
10808 mask
= inst
.operands
[0].imm
;
10809 if ((mask
& ~0xff) == 0)
10810 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
10811 else if ((inst
.instruction
== T_MNEM_push
10812 && (mask
& ~0xff) == 1 << REG_LR
)
10813 || (inst
.instruction
== T_MNEM_pop
10814 && (mask
& ~0xff) == 1 << REG_PC
))
10816 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10817 inst
.instruction
|= THUMB_PP_PC_LR
;
10818 inst
.instruction
|= mask
& 0xff;
10820 else if (unified_syntax
)
10822 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10823 encode_thumb2_ldmstm (13, mask
, TRUE
);
10827 inst
.error
= _("invalid register list to push/pop instruction");
10837 Rd
= inst
.operands
[0].reg
;
10838 Rm
= inst
.operands
[1].reg
;
10840 reject_bad_reg (Rd
);
10841 reject_bad_reg (Rm
);
10843 inst
.instruction
|= Rd
<< 8;
10844 inst
.instruction
|= Rm
<< 16;
10845 inst
.instruction
|= Rm
;
10853 Rd
= inst
.operands
[0].reg
;
10854 Rm
= inst
.operands
[1].reg
;
10856 reject_bad_reg (Rd
);
10857 reject_bad_reg (Rm
);
10859 if (Rd
<= 7 && Rm
<= 7
10860 && inst
.size_req
!= 4)
10862 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10863 inst
.instruction
|= Rd
;
10864 inst
.instruction
|= Rm
<< 3;
10866 else if (unified_syntax
)
10868 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10869 inst
.instruction
|= Rd
<< 8;
10870 inst
.instruction
|= Rm
<< 16;
10871 inst
.instruction
|= Rm
;
10874 inst
.error
= BAD_HIREG
;
10882 Rd
= inst
.operands
[0].reg
;
10883 Rm
= inst
.operands
[1].reg
;
10885 reject_bad_reg (Rd
);
10886 reject_bad_reg (Rm
);
10888 inst
.instruction
|= Rd
<< 8;
10889 inst
.instruction
|= Rm
;
10897 Rd
= inst
.operands
[0].reg
;
10898 Rs
= (inst
.operands
[1].present
10899 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10900 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10902 reject_bad_reg (Rd
);
10903 reject_bad_reg (Rs
);
10904 if (inst
.operands
[2].isreg
)
10905 reject_bad_reg (inst
.operands
[2].reg
);
10907 inst
.instruction
|= Rd
<< 8;
10908 inst
.instruction
|= Rs
<< 16;
10909 if (!inst
.operands
[2].isreg
)
10911 bfd_boolean narrow
;
10913 if ((inst
.instruction
& 0x00100000) != 0)
10914 narrow
= !in_it_block ();
10916 narrow
= in_it_block ();
10918 if (Rd
> 7 || Rs
> 7)
10921 if (inst
.size_req
== 4 || !unified_syntax
)
10924 if (inst
.reloc
.exp
.X_op
!= O_constant
10925 || inst
.reloc
.exp
.X_add_number
!= 0)
10928 /* Turn rsb #0 into 16-bit neg. We should probably do this via
10929 relaxation, but it doesn't seem worth the hassle. */
10932 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10933 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
10934 inst
.instruction
|= Rs
<< 3;
10935 inst
.instruction
|= Rd
;
10939 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10940 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10944 encode_thumb32_shifted_operand (2);
10950 set_it_insn_type (OUTSIDE_IT_INSN
);
10951 if (inst
.operands
[0].imm
)
10952 inst
.instruction
|= 0x8;
10958 if (!inst
.operands
[1].present
)
10959 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
10961 if (unified_syntax
)
10963 bfd_boolean narrow
;
10966 switch (inst
.instruction
)
10969 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
10971 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
10973 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
10975 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
10979 if (THUMB_SETS_FLAGS (inst
.instruction
))
10980 narrow
= !in_it_block ();
10982 narrow
= in_it_block ();
10983 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10985 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
10987 if (inst
.operands
[2].isreg
10988 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
10989 || inst
.operands
[2].reg
> 7))
10991 if (inst
.size_req
== 4)
10994 reject_bad_reg (inst
.operands
[0].reg
);
10995 reject_bad_reg (inst
.operands
[1].reg
);
10999 if (inst
.operands
[2].isreg
)
11001 reject_bad_reg (inst
.operands
[2].reg
);
11002 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11003 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11004 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11005 inst
.instruction
|= inst
.operands
[2].reg
;
11009 inst
.operands
[1].shifted
= 1;
11010 inst
.operands
[1].shift_kind
= shift_kind
;
11011 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
11012 ? T_MNEM_movs
: T_MNEM_mov
);
11013 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11014 encode_thumb32_shifted_operand (1);
11015 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11016 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11021 if (inst
.operands
[2].isreg
)
11023 switch (shift_kind
)
11025 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11026 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11027 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11028 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11032 inst
.instruction
|= inst
.operands
[0].reg
;
11033 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11037 switch (shift_kind
)
11039 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11040 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11041 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11044 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11045 inst
.instruction
|= inst
.operands
[0].reg
;
11046 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11052 constraint (inst
.operands
[0].reg
> 7
11053 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11054 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11056 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11058 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11059 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11060 _("source1 and dest must be same register"));
11062 switch (inst
.instruction
)
11064 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11065 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11066 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11067 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11071 inst
.instruction
|= inst
.operands
[0].reg
;
11072 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11076 switch (inst
.instruction
)
11078 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11079 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11080 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11081 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11084 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11085 inst
.instruction
|= inst
.operands
[0].reg
;
11086 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11094 unsigned Rd
, Rn
, Rm
;
11096 Rd
= inst
.operands
[0].reg
;
11097 Rn
= inst
.operands
[1].reg
;
11098 Rm
= inst
.operands
[2].reg
;
11100 reject_bad_reg (Rd
);
11101 reject_bad_reg (Rn
);
11102 reject_bad_reg (Rm
);
11104 inst
.instruction
|= Rd
<< 8;
11105 inst
.instruction
|= Rn
<< 16;
11106 inst
.instruction
|= Rm
;
11112 unsigned Rd
, Rn
, Rm
;
11114 Rd
= inst
.operands
[0].reg
;
11115 Rm
= inst
.operands
[1].reg
;
11116 Rn
= inst
.operands
[2].reg
;
11118 reject_bad_reg (Rd
);
11119 reject_bad_reg (Rn
);
11120 reject_bad_reg (Rm
);
11122 inst
.instruction
|= Rd
<< 8;
11123 inst
.instruction
|= Rn
<< 16;
11124 inst
.instruction
|= Rm
;
11130 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11131 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11132 _("expression too complex"));
11133 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11134 inst
.instruction
|= (value
& 0xf000) >> 12;
11135 inst
.instruction
|= (value
& 0x0ff0);
11136 inst
.instruction
|= (value
& 0x000f) << 16;
11140 do_t_ssat_usat (int bias
)
11144 Rd
= inst
.operands
[0].reg
;
11145 Rn
= inst
.operands
[2].reg
;
11147 reject_bad_reg (Rd
);
11148 reject_bad_reg (Rn
);
11150 inst
.instruction
|= Rd
<< 8;
11151 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
11152 inst
.instruction
|= Rn
<< 16;
11154 if (inst
.operands
[3].present
)
11156 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
11158 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11160 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11161 _("expression too complex"));
11163 if (shift_amount
!= 0)
11165 constraint (shift_amount
> 31,
11166 _("shift expression is too large"));
11168 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
11169 inst
.instruction
|= 0x00200000; /* sh bit. */
11171 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
11172 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11180 do_t_ssat_usat (1);
11188 Rd
= inst
.operands
[0].reg
;
11189 Rn
= inst
.operands
[2].reg
;
11191 reject_bad_reg (Rd
);
11192 reject_bad_reg (Rn
);
11194 inst
.instruction
|= Rd
<< 8;
11195 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11196 inst
.instruction
|= Rn
<< 16;
11202 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11203 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11204 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11205 || inst
.operands
[2].negative
,
11208 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11209 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11210 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11211 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11217 if (!inst
.operands
[2].present
)
11218 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11220 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11221 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11222 || inst
.operands
[0].reg
== inst
.operands
[3].reg
11223 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
11226 inst
.instruction
|= inst
.operands
[0].reg
;
11227 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11228 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11229 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11235 unsigned Rd
, Rn
, Rm
;
11237 Rd
= inst
.operands
[0].reg
;
11238 Rn
= inst
.operands
[1].reg
;
11239 Rm
= inst
.operands
[2].reg
;
11241 reject_bad_reg (Rd
);
11242 reject_bad_reg (Rn
);
11243 reject_bad_reg (Rm
);
11245 inst
.instruction
|= Rd
<< 8;
11246 inst
.instruction
|= Rn
<< 16;
11247 inst
.instruction
|= Rm
;
11248 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11256 Rd
= inst
.operands
[0].reg
;
11257 Rm
= inst
.operands
[1].reg
;
11259 reject_bad_reg (Rd
);
11260 reject_bad_reg (Rm
);
11262 if (inst
.instruction
<= 0xffff
11263 && inst
.size_req
!= 4
11264 && Rd
<= 7 && Rm
<= 7
11265 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11267 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11268 inst
.instruction
|= Rd
;
11269 inst
.instruction
|= Rm
<< 3;
11271 else if (unified_syntax
)
11273 if (inst
.instruction
<= 0xffff)
11274 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11275 inst
.instruction
|= Rd
<< 8;
11276 inst
.instruction
|= Rm
;
11277 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11281 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11282 _("Thumb encoding does not support rotation"));
11283 constraint (1, BAD_HIREG
);
11290 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11299 half
= (inst
.instruction
& 0x10) != 0;
11300 set_it_insn_type_last ();
11301 constraint (inst
.operands
[0].immisreg
,
11302 _("instruction requires register index"));
11304 Rn
= inst
.operands
[0].reg
;
11305 Rm
= inst
.operands
[0].imm
;
11307 constraint (Rn
== REG_SP
, BAD_SP
);
11308 reject_bad_reg (Rm
);
11310 constraint (!half
&& inst
.operands
[0].shifted
,
11311 _("instruction does not allow shifted index"));
11312 inst
.instruction
|= (Rn
<< 16) | Rm
;
11318 do_t_ssat_usat (0);
11326 Rd
= inst
.operands
[0].reg
;
11327 Rn
= inst
.operands
[2].reg
;
11329 reject_bad_reg (Rd
);
11330 reject_bad_reg (Rn
);
11332 inst
.instruction
|= Rd
<< 8;
11333 inst
.instruction
|= inst
.operands
[1].imm
;
11334 inst
.instruction
|= Rn
<< 16;
11337 /* Neon instruction encoder helpers. */
11339 /* Encodings for the different types for various Neon opcodes. */
11341 /* An "invalid" code for the following tables. */
11344 struct neon_tab_entry
11347 unsigned float_or_poly
;
11348 unsigned scalar_or_imm
;
11351 /* Map overloaded Neon opcodes to their respective encodings. */
11352 #define NEON_ENC_TAB \
11353 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11354 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11355 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11356 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11357 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11358 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11359 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11360 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11361 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11362 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11363 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11364 /* Register variants of the following two instructions are encoded as
11365 vcge / vcgt with the operands reversed. */ \
11366 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11367 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11368 X(vfma, N_INV, 0x0000c10, N_INV), \
11369 X(vfms, N_INV, 0x0200c10, N_INV), \
11370 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11371 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11372 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11373 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11374 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11375 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11376 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11377 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11378 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11379 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11380 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11381 X(vshl, 0x0000400, N_INV, 0x0800510), \
11382 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11383 X(vand, 0x0000110, N_INV, 0x0800030), \
11384 X(vbic, 0x0100110, N_INV, 0x0800030), \
11385 X(veor, 0x1000110, N_INV, N_INV), \
11386 X(vorn, 0x0300110, N_INV, 0x0800010), \
11387 X(vorr, 0x0200110, N_INV, 0x0800010), \
11388 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11389 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11390 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11391 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11392 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11393 X(vst1, 0x0000000, 0x0800000, N_INV), \
11394 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11395 X(vst2, 0x0000100, 0x0800100, N_INV), \
11396 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11397 X(vst3, 0x0000200, 0x0800200, N_INV), \
11398 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11399 X(vst4, 0x0000300, 0x0800300, N_INV), \
11400 X(vmovn, 0x1b20200, N_INV, N_INV), \
11401 X(vtrn, 0x1b20080, N_INV, N_INV), \
11402 X(vqmovn, 0x1b20200, N_INV, N_INV), \
11403 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11404 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
11405 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
11406 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
11407 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
11408 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
11409 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11410 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
11411 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
11412 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
11416 #define X(OPC,I,F,S) N_MNEM_##OPC
11421 static const struct neon_tab_entry neon_enc_tab
[] =
11423 #define X(OPC,I,F,S) { (I), (F), (S) }
11428 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11429 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11430 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11431 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11432 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11433 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11434 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11435 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11436 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11437 #define NEON_ENC_SINGLE(X) \
11438 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
11439 #define NEON_ENC_DOUBLE(X) \
11440 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
11442 /* Define shapes for instruction operands. The following mnemonic characters
11443 are used in this table:
11445 F - VFP S<n> register
11446 D - Neon D<n> register
11447 Q - Neon Q<n> register
11451 L - D<n> register list
11453 This table is used to generate various data:
11454 - enumerations of the form NS_DDR to be used as arguments to
11456 - a table classifying shapes into single, double, quad, mixed.
11457 - a table used to drive neon_select_shape. */
11459 #define NEON_SHAPE_DEF \
11460 X(3, (D, D, D), DOUBLE), \
11461 X(3, (Q, Q, Q), QUAD), \
11462 X(3, (D, D, I), DOUBLE), \
11463 X(3, (Q, Q, I), QUAD), \
11464 X(3, (D, D, S), DOUBLE), \
11465 X(3, (Q, Q, S), QUAD), \
11466 X(2, (D, D), DOUBLE), \
11467 X(2, (Q, Q), QUAD), \
11468 X(2, (D, S), DOUBLE), \
11469 X(2, (Q, S), QUAD), \
11470 X(2, (D, R), DOUBLE), \
11471 X(2, (Q, R), QUAD), \
11472 X(2, (D, I), DOUBLE), \
11473 X(2, (Q, I), QUAD), \
11474 X(3, (D, L, D), DOUBLE), \
11475 X(2, (D, Q), MIXED), \
11476 X(2, (Q, D), MIXED), \
11477 X(3, (D, Q, I), MIXED), \
11478 X(3, (Q, D, I), MIXED), \
11479 X(3, (Q, D, D), MIXED), \
11480 X(3, (D, Q, Q), MIXED), \
11481 X(3, (Q, Q, D), MIXED), \
11482 X(3, (Q, D, S), MIXED), \
11483 X(3, (D, Q, S), MIXED), \
11484 X(4, (D, D, D, I), DOUBLE), \
11485 X(4, (Q, Q, Q, I), QUAD), \
11486 X(2, (F, F), SINGLE), \
11487 X(3, (F, F, F), SINGLE), \
11488 X(2, (F, I), SINGLE), \
11489 X(2, (F, D), MIXED), \
11490 X(2, (D, F), MIXED), \
11491 X(3, (F, F, I), MIXED), \
11492 X(4, (R, R, F, F), SINGLE), \
11493 X(4, (F, F, R, R), SINGLE), \
11494 X(3, (D, R, R), DOUBLE), \
11495 X(3, (R, R, D), DOUBLE), \
11496 X(2, (S, R), SINGLE), \
11497 X(2, (R, S), SINGLE), \
11498 X(2, (F, R), SINGLE), \
11499 X(2, (R, F), SINGLE)
11501 #define S2(A,B) NS_##A##B
11502 #define S3(A,B,C) NS_##A##B##C
11503 #define S4(A,B,C,D) NS_##A##B##C##D
11505 #define X(N, L, C) S##N L
11518 enum neon_shape_class
11526 #define X(N, L, C) SC_##C
11528 static enum neon_shape_class neon_shape_class
[] =
11546 /* Register widths of above. */
11547 static unsigned neon_shape_el_size
[] =
11558 struct neon_shape_info
11561 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
11564 #define S2(A,B) { SE_##A, SE_##B }
11565 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
11566 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
11568 #define X(N, L, C) { N, S##N L }
11570 static struct neon_shape_info neon_shape_tab
[] =
11580 /* Bit masks used in type checking given instructions.
11581 'N_EQK' means the type must be the same as (or based on in some way) the key
11582 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
11583 set, various other bits can be set as well in order to modify the meaning of
11584 the type constraint. */
11586 enum neon_type_mask
11609 N_KEY
= 0x1000000, /* Key element (main type specifier). */
11610 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
11611 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
11612 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
11613 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
11614 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
11615 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
11616 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
11617 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
11618 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
11620 N_MAX_NONSPECIAL
= N_F64
11623 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
11625 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
11626 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
11627 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
11628 #define N_SUF_32 (N_SU_32 | N_F32)
11629 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
11630 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
11632 /* Pass this as the first type argument to neon_check_type to ignore types
11634 #define N_IGNORE_TYPE (N_KEY | N_EQK)
11636 /* Select a "shape" for the current instruction (describing register types or
11637 sizes) from a list of alternatives. Return NS_NULL if the current instruction
11638 doesn't fit. For non-polymorphic shapes, checking is usually done as a
11639 function of operand parsing, so this function doesn't need to be called.
11640 Shapes should be listed in order of decreasing length. */
11642 static enum neon_shape
11643 neon_select_shape (enum neon_shape shape
, ...)
11646 enum neon_shape first_shape
= shape
;
11648 /* Fix missing optional operands. FIXME: we don't know at this point how
11649 many arguments we should have, so this makes the assumption that we have
11650 > 1. This is true of all current Neon opcodes, I think, but may not be
11651 true in the future. */
11652 if (!inst
.operands
[1].present
)
11653 inst
.operands
[1] = inst
.operands
[0];
11655 va_start (ap
, shape
);
11657 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
11662 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
11664 if (!inst
.operands
[j
].present
)
11670 switch (neon_shape_tab
[shape
].el
[j
])
11673 if (!(inst
.operands
[j
].isreg
11674 && inst
.operands
[j
].isvec
11675 && inst
.operands
[j
].issingle
11676 && !inst
.operands
[j
].isquad
))
11681 if (!(inst
.operands
[j
].isreg
11682 && inst
.operands
[j
].isvec
11683 && !inst
.operands
[j
].isquad
11684 && !inst
.operands
[j
].issingle
))
11689 if (!(inst
.operands
[j
].isreg
11690 && !inst
.operands
[j
].isvec
))
11695 if (!(inst
.operands
[j
].isreg
11696 && inst
.operands
[j
].isvec
11697 && inst
.operands
[j
].isquad
11698 && !inst
.operands
[j
].issingle
))
11703 if (!(!inst
.operands
[j
].isreg
11704 && !inst
.operands
[j
].isscalar
))
11709 if (!(!inst
.operands
[j
].isreg
11710 && inst
.operands
[j
].isscalar
))
11724 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
11725 first_error (_("invalid instruction shape"));
11730 /* True if SHAPE is predominantly a quadword operation (most of the time, this
11731 means the Q bit should be set). */
11734 neon_quad (enum neon_shape shape
)
11736 return neon_shape_class
[shape
] == SC_QUAD
;
11740 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
11743 /* Allow modification to be made to types which are constrained to be
11744 based on the key element, based on bits set alongside N_EQK. */
11745 if ((typebits
& N_EQK
) != 0)
11747 if ((typebits
& N_HLF
) != 0)
11749 else if ((typebits
& N_DBL
) != 0)
11751 if ((typebits
& N_SGN
) != 0)
11752 *g_type
= NT_signed
;
11753 else if ((typebits
& N_UNS
) != 0)
11754 *g_type
= NT_unsigned
;
11755 else if ((typebits
& N_INT
) != 0)
11756 *g_type
= NT_integer
;
11757 else if ((typebits
& N_FLT
) != 0)
11758 *g_type
= NT_float
;
11759 else if ((typebits
& N_SIZ
) != 0)
11760 *g_type
= NT_untyped
;
11764 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
11765 operand type, i.e. the single type specified in a Neon instruction when it
11766 is the only one given. */
11768 static struct neon_type_el
11769 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
11771 struct neon_type_el dest
= *key
;
11773 gas_assert ((thisarg
& N_EQK
) != 0);
11775 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
11780 /* Convert Neon type and size into compact bitmask representation. */
11782 static enum neon_type_mask
11783 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
11790 case 8: return N_8
;
11791 case 16: return N_16
;
11792 case 32: return N_32
;
11793 case 64: return N_64
;
11801 case 8: return N_I8
;
11802 case 16: return N_I16
;
11803 case 32: return N_I32
;
11804 case 64: return N_I64
;
11812 case 16: return N_F16
;
11813 case 32: return N_F32
;
11814 case 64: return N_F64
;
11822 case 8: return N_P8
;
11823 case 16: return N_P16
;
11831 case 8: return N_S8
;
11832 case 16: return N_S16
;
11833 case 32: return N_S32
;
11834 case 64: return N_S64
;
11842 case 8: return N_U8
;
11843 case 16: return N_U16
;
11844 case 32: return N_U32
;
11845 case 64: return N_U64
;
11856 /* Convert compact Neon bitmask type representation to a type and size. Only
11857 handles the case where a single bit is set in the mask. */
11860 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
11861 enum neon_type_mask mask
)
11863 if ((mask
& N_EQK
) != 0)
11866 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
11868 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
11870 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
11872 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
11877 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
11879 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
11880 *type
= NT_unsigned
;
11881 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
11882 *type
= NT_integer
;
11883 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
11884 *type
= NT_untyped
;
11885 else if ((mask
& (N_P8
| N_P16
)) != 0)
11887 else if ((mask
& (N_F32
| N_F64
)) != 0)
11895 /* Modify a bitmask of allowed types. This is only needed for type
11899 modify_types_allowed (unsigned allowed
, unsigned mods
)
11902 enum neon_el_type type
;
11908 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
11910 if (el_type_of_type_chk (&type
, &size
,
11911 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
11913 neon_modify_type_size (mods
, &type
, &size
);
11914 destmask
|= type_chk_of_el_type (type
, size
);
11921 /* Check type and return type classification.
11922 The manual states (paraphrase): If one datatype is given, it indicates the
11924 - the second operand, if there is one
11925 - the operand, if there is no second operand
11926 - the result, if there are no operands.
11927 This isn't quite good enough though, so we use a concept of a "key" datatype
11928 which is set on a per-instruction basis, which is the one which matters when
11929 only one data type is written.
11930 Note: this function has side-effects (e.g. filling in missing operands). All
11931 Neon instructions should call it before performing bit encoding. */
11933 static struct neon_type_el
11934 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
11937 unsigned i
, pass
, key_el
= 0;
11938 unsigned types
[NEON_MAX_TYPE_ELS
];
11939 enum neon_el_type k_type
= NT_invtype
;
11940 unsigned k_size
= -1u;
11941 struct neon_type_el badtype
= {NT_invtype
, -1};
11942 unsigned key_allowed
= 0;
11944 /* Optional registers in Neon instructions are always (not) in operand 1.
11945 Fill in the missing operand here, if it was omitted. */
11946 if (els
> 1 && !inst
.operands
[1].present
)
11947 inst
.operands
[1] = inst
.operands
[0];
11949 /* Suck up all the varargs. */
11951 for (i
= 0; i
< els
; i
++)
11953 unsigned thisarg
= va_arg (ap
, unsigned);
11954 if (thisarg
== N_IGNORE_TYPE
)
11959 types
[i
] = thisarg
;
11960 if ((thisarg
& N_KEY
) != 0)
11965 if (inst
.vectype
.elems
> 0)
11966 for (i
= 0; i
< els
; i
++)
11967 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
11969 first_error (_("types specified in both the mnemonic and operands"));
11973 /* Duplicate inst.vectype elements here as necessary.
11974 FIXME: No idea if this is exactly the same as the ARM assembler,
11975 particularly when an insn takes one register and one non-register
11977 if (inst
.vectype
.elems
== 1 && els
> 1)
11980 inst
.vectype
.elems
= els
;
11981 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
11982 for (j
= 0; j
< els
; j
++)
11984 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11987 else if (inst
.vectype
.elems
== 0 && els
> 0)
11990 /* No types were given after the mnemonic, so look for types specified
11991 after each operand. We allow some flexibility here; as long as the
11992 "key" operand has a type, we can infer the others. */
11993 for (j
= 0; j
< els
; j
++)
11994 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
11995 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
11997 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
11999 for (j
= 0; j
< els
; j
++)
12000 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
12001 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12006 first_error (_("operand types can't be inferred"));
12010 else if (inst
.vectype
.elems
!= els
)
12012 first_error (_("type specifier has the wrong number of parts"));
12016 for (pass
= 0; pass
< 2; pass
++)
12018 for (i
= 0; i
< els
; i
++)
12020 unsigned thisarg
= types
[i
];
12021 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
12022 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
12023 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
12024 unsigned g_size
= inst
.vectype
.el
[i
].size
;
12026 /* Decay more-specific signed & unsigned types to sign-insensitive
12027 integer types if sign-specific variants are unavailable. */
12028 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
12029 && (types_allowed
& N_SU_ALL
) == 0)
12030 g_type
= NT_integer
;
12032 /* If only untyped args are allowed, decay any more specific types to
12033 them. Some instructions only care about signs for some element
12034 sizes, so handle that properly. */
12035 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
12036 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
12037 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
12038 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
12039 g_type
= NT_untyped
;
12043 if ((thisarg
& N_KEY
) != 0)
12047 key_allowed
= thisarg
& ~N_KEY
;
12052 if ((thisarg
& N_VFP
) != 0)
12054 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
12055 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
12057 /* In VFP mode, operands must match register widths. If we
12058 have a key operand, use its width, else use the width of
12059 the current operand. */
12065 if (regwidth
!= match
)
12067 first_error (_("operand size must match register width"));
12072 if ((thisarg
& N_EQK
) == 0)
12074 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
12076 if ((given_type
& types_allowed
) == 0)
12078 first_error (_("bad type in Neon instruction"));
12084 enum neon_el_type mod_k_type
= k_type
;
12085 unsigned mod_k_size
= k_size
;
12086 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
12087 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
12089 first_error (_("inconsistent types in Neon instruction"));
12097 return inst
.vectype
.el
[key_el
];
12100 /* Neon-style VFP instruction forwarding. */
12102 /* Thumb VFP instructions have 0xE in the condition field. */
12105 do_vfp_cond_or_thumb (void)
12108 inst
.instruction
|= 0xe0000000;
12110 inst
.instruction
|= inst
.cond
<< 28;
12113 /* Look up and encode a simple mnemonic, for use as a helper function for the
12114 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12115 etc. It is assumed that operand parsing has already been done, and that the
12116 operands are in the form expected by the given opcode (this isn't necessarily
12117 the same as the form in which they were parsed, hence some massaging must
12118 take place before this function is called).
12119 Checks current arch version against that in the looked-up opcode. */
12122 do_vfp_nsyn_opcode (const char *opname
)
12124 const struct asm_opcode
*opcode
;
12126 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
12131 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
12132 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
12137 inst
.instruction
= opcode
->tvalue
;
12138 opcode
->tencode ();
12142 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
12143 opcode
->aencode ();
12148 do_vfp_nsyn_add_sub (enum neon_shape rs
)
12150 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
12155 do_vfp_nsyn_opcode ("fadds");
12157 do_vfp_nsyn_opcode ("fsubs");
12162 do_vfp_nsyn_opcode ("faddd");
12164 do_vfp_nsyn_opcode ("fsubd");
12168 /* Check operand types to see if this is a VFP instruction, and if so call
12172 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
12174 enum neon_shape rs
;
12175 struct neon_type_el et
;
12180 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12181 et
= neon_check_type (2, rs
,
12182 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12186 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12187 et
= neon_check_type (3, rs
,
12188 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12195 if (et
.type
!= NT_invtype
)
12207 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12209 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12214 do_vfp_nsyn_opcode ("fmacs");
12216 do_vfp_nsyn_opcode ("fnmacs");
12221 do_vfp_nsyn_opcode ("fmacd");
12223 do_vfp_nsyn_opcode ("fnmacd");
12228 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
12230 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
12235 do_vfp_nsyn_opcode ("ffmas");
12237 do_vfp_nsyn_opcode ("ffnmas");
12242 do_vfp_nsyn_opcode ("ffmad");
12244 do_vfp_nsyn_opcode ("ffnmad");
12249 do_vfp_nsyn_mul (enum neon_shape rs
)
12252 do_vfp_nsyn_opcode ("fmuls");
12254 do_vfp_nsyn_opcode ("fmuld");
12258 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12260 int is_neg
= (inst
.instruction
& 0x80) != 0;
12261 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12266 do_vfp_nsyn_opcode ("fnegs");
12268 do_vfp_nsyn_opcode ("fabss");
12273 do_vfp_nsyn_opcode ("fnegd");
12275 do_vfp_nsyn_opcode ("fabsd");
12279 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12280 insns belong to Neon, and are handled elsewhere. */
12283 do_vfp_nsyn_ldm_stm (int is_dbmode
)
12285 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
12289 do_vfp_nsyn_opcode ("fldmdbs");
12291 do_vfp_nsyn_opcode ("fldmias");
12296 do_vfp_nsyn_opcode ("fstmdbs");
12298 do_vfp_nsyn_opcode ("fstmias");
12303 do_vfp_nsyn_sqrt (void)
12305 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12306 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12309 do_vfp_nsyn_opcode ("fsqrts");
12311 do_vfp_nsyn_opcode ("fsqrtd");
12315 do_vfp_nsyn_div (void)
12317 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12318 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12319 N_F32
| N_F64
| N_KEY
| N_VFP
);
12322 do_vfp_nsyn_opcode ("fdivs");
12324 do_vfp_nsyn_opcode ("fdivd");
12328 do_vfp_nsyn_nmul (void)
12330 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12331 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12332 N_F32
| N_F64
| N_KEY
| N_VFP
);
12336 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
12337 do_vfp_sp_dyadic ();
12341 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
12342 do_vfp_dp_rd_rn_rm ();
12344 do_vfp_cond_or_thumb ();
12348 do_vfp_nsyn_cmp (void)
12350 if (inst
.operands
[1].isreg
)
12352 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12353 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12357 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
12358 do_vfp_sp_monadic ();
12362 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
12363 do_vfp_dp_rd_rm ();
12368 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
12369 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
12371 switch (inst
.instruction
& 0x0fffffff)
12374 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
12377 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
12385 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
12386 do_vfp_sp_compare_z ();
12390 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
12394 do_vfp_cond_or_thumb ();
12398 nsyn_insert_sp (void)
12400 inst
.operands
[1] = inst
.operands
[0];
12401 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
12402 inst
.operands
[0].reg
= REG_SP
;
12403 inst
.operands
[0].isreg
= 1;
12404 inst
.operands
[0].writeback
= 1;
12405 inst
.operands
[0].present
= 1;
12409 do_vfp_nsyn_push (void)
12412 if (inst
.operands
[1].issingle
)
12413 do_vfp_nsyn_opcode ("fstmdbs");
12415 do_vfp_nsyn_opcode ("fstmdbd");
12419 do_vfp_nsyn_pop (void)
12422 if (inst
.operands
[1].issingle
)
12423 do_vfp_nsyn_opcode ("fldmias");
12425 do_vfp_nsyn_opcode ("fldmiad");
12428 /* Fix up Neon data-processing instructions, ORing in the correct bits for
12429 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
12432 neon_dp_fixup (unsigned i
)
12436 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
12450 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
12454 neon_logbits (unsigned x
)
12456 return ffs (x
) - 4;
12459 #define LOW4(R) ((R) & 0xf)
12460 #define HI1(R) (((R) >> 4) & 1)
12462 /* Encode insns with bit pattern:
12464 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12465 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
12467 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
12468 different meaning for some instruction. */
12471 neon_three_same (int isquad
, int ubit
, int size
)
12473 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12474 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12475 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12476 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12477 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12478 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12479 inst
.instruction
|= (isquad
!= 0) << 6;
12480 inst
.instruction
|= (ubit
!= 0) << 24;
12482 inst
.instruction
|= neon_logbits (size
) << 20;
12484 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12487 /* Encode instructions of the form:
12489 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
12490 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
12492 Don't write size if SIZE == -1. */
12495 neon_two_same (int qbit
, int ubit
, int size
)
12497 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12498 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12499 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12500 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12501 inst
.instruction
|= (qbit
!= 0) << 6;
12502 inst
.instruction
|= (ubit
!= 0) << 24;
12505 inst
.instruction
|= neon_logbits (size
) << 18;
12507 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12510 /* Neon instruction encoders, in approximate order of appearance. */
12513 do_neon_dyadic_i_su (void)
12515 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12516 struct neon_type_el et
= neon_check_type (3, rs
,
12517 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
12518 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12522 do_neon_dyadic_i64_su (void)
12524 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12525 struct neon_type_el et
= neon_check_type (3, rs
,
12526 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12527 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12531 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
12534 unsigned size
= et
.size
>> 3;
12535 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12536 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12537 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12538 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12539 inst
.instruction
|= (isquad
!= 0) << 6;
12540 inst
.instruction
|= immbits
<< 16;
12541 inst
.instruction
|= (size
>> 3) << 7;
12542 inst
.instruction
|= (size
& 0x7) << 19;
12544 inst
.instruction
|= (uval
!= 0) << 24;
12546 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12550 do_neon_shl_imm (void)
12552 if (!inst
.operands
[2].isreg
)
12554 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12555 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
12556 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12557 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
12561 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12562 struct neon_type_el et
= neon_check_type (3, rs
,
12563 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12566 /* VSHL/VQSHL 3-register variants have syntax such as:
12568 whereas other 3-register operations encoded by neon_three_same have
12571 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
12573 tmp
= inst
.operands
[2].reg
;
12574 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12575 inst
.operands
[1].reg
= tmp
;
12576 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12577 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12582 do_neon_qshl_imm (void)
12584 if (!inst
.operands
[2].isreg
)
12586 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12587 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12589 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12590 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12591 inst
.operands
[2].imm
);
12595 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12596 struct neon_type_el et
= neon_check_type (3, rs
,
12597 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12600 /* See note in do_neon_shl_imm. */
12601 tmp
= inst
.operands
[2].reg
;
12602 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12603 inst
.operands
[1].reg
= tmp
;
12604 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12605 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12610 do_neon_rshl (void)
12612 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12613 struct neon_type_el et
= neon_check_type (3, rs
,
12614 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12617 tmp
= inst
.operands
[2].reg
;
12618 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12619 inst
.operands
[1].reg
= tmp
;
12620 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12624 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
12626 /* Handle .I8 pseudo-instructions. */
12629 /* Unfortunately, this will make everything apart from zero out-of-range.
12630 FIXME is this the intended semantics? There doesn't seem much point in
12631 accepting .I8 if so. */
12632 immediate
|= immediate
<< 8;
12638 if (immediate
== (immediate
& 0x000000ff))
12640 *immbits
= immediate
;
12643 else if (immediate
== (immediate
& 0x0000ff00))
12645 *immbits
= immediate
>> 8;
12648 else if (immediate
== (immediate
& 0x00ff0000))
12650 *immbits
= immediate
>> 16;
12653 else if (immediate
== (immediate
& 0xff000000))
12655 *immbits
= immediate
>> 24;
12658 if ((immediate
& 0xffff) != (immediate
>> 16))
12659 goto bad_immediate
;
12660 immediate
&= 0xffff;
12663 if (immediate
== (immediate
& 0x000000ff))
12665 *immbits
= immediate
;
12668 else if (immediate
== (immediate
& 0x0000ff00))
12670 *immbits
= immediate
>> 8;
12675 first_error (_("immediate value out of range"));
12679 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
12683 neon_bits_same_in_bytes (unsigned imm
)
12685 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
12686 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
12687 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
12688 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
12691 /* For immediate of above form, return 0bABCD. */
12694 neon_squash_bits (unsigned imm
)
12696 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
12697 | ((imm
& 0x01000000) >> 21);
12700 /* Compress quarter-float representation to 0b...000 abcdefgh. */
12703 neon_qfloat_bits (unsigned imm
)
12705 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
12708 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
12709 the instruction. *OP is passed as the initial value of the op field, and
12710 may be set to a different value depending on the constant (i.e.
12711 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
12712 MVN). If the immediate looks like a repeated pattern then also
12713 try smaller element sizes. */
12716 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
12717 unsigned *immbits
, int *op
, int size
,
12718 enum neon_el_type type
)
12720 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
12722 if (type
== NT_float
&& !float_p
)
12725 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
12727 if (size
!= 32 || *op
== 1)
12729 *immbits
= neon_qfloat_bits (immlo
);
12735 if (neon_bits_same_in_bytes (immhi
)
12736 && neon_bits_same_in_bytes (immlo
))
12740 *immbits
= (neon_squash_bits (immhi
) << 4)
12741 | neon_squash_bits (immlo
);
12746 if (immhi
!= immlo
)
12752 if (immlo
== (immlo
& 0x000000ff))
12757 else if (immlo
== (immlo
& 0x0000ff00))
12759 *immbits
= immlo
>> 8;
12762 else if (immlo
== (immlo
& 0x00ff0000))
12764 *immbits
= immlo
>> 16;
12767 else if (immlo
== (immlo
& 0xff000000))
12769 *immbits
= immlo
>> 24;
12772 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
12774 *immbits
= (immlo
>> 8) & 0xff;
12777 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
12779 *immbits
= (immlo
>> 16) & 0xff;
12783 if ((immlo
& 0xffff) != (immlo
>> 16))
12790 if (immlo
== (immlo
& 0x000000ff))
12795 else if (immlo
== (immlo
& 0x0000ff00))
12797 *immbits
= immlo
>> 8;
12801 if ((immlo
& 0xff) != (immlo
>> 8))
12806 if (immlo
== (immlo
& 0x000000ff))
12808 /* Don't allow MVN with 8-bit immediate. */
12818 /* Write immediate bits [7:0] to the following locations:
12820 |28/24|23 19|18 16|15 4|3 0|
12821 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
12823 This function is used by VMOV/VMVN/VORR/VBIC. */
12826 neon_write_immbits (unsigned immbits
)
12828 inst
.instruction
|= immbits
& 0xf;
12829 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
12830 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
12833 /* Invert low-order SIZE bits of XHI:XLO. */
12836 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
12838 unsigned immlo
= xlo
? *xlo
: 0;
12839 unsigned immhi
= xhi
? *xhi
: 0;
12844 immlo
= (~immlo
) & 0xff;
12848 immlo
= (~immlo
) & 0xffff;
12852 immhi
= (~immhi
) & 0xffffffff;
12853 /* fall through. */
12856 immlo
= (~immlo
) & 0xffffffff;
12871 do_neon_logic (void)
12873 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
12875 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12876 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12877 /* U bit and size field were set as part of the bitmask. */
12878 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12879 neon_three_same (neon_quad (rs
), 0, -1);
12883 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12884 struct neon_type_el et
= neon_check_type (2, rs
,
12885 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12886 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
12890 if (et
.type
== NT_invtype
)
12893 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12895 immbits
= inst
.operands
[1].imm
;
12898 /* .i64 is a pseudo-op, so the immediate must be a repeating
12900 if (immbits
!= (inst
.operands
[1].regisimm
?
12901 inst
.operands
[1].reg
: 0))
12903 /* Set immbits to an invalid constant. */
12904 immbits
= 0xdeadbeef;
12911 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12915 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12919 /* Pseudo-instruction for VBIC. */
12920 neon_invert_size (&immbits
, 0, et
.size
);
12921 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12925 /* Pseudo-instruction for VORR. */
12926 neon_invert_size (&immbits
, 0, et
.size
);
12927 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12937 inst
.instruction
|= neon_quad (rs
) << 6;
12938 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12939 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12940 inst
.instruction
|= cmode
<< 8;
12941 neon_write_immbits (immbits
);
12943 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12948 do_neon_bitfield (void)
12950 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12951 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12952 neon_three_same (neon_quad (rs
), 0, -1);
12956 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
12959 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12960 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
12962 if (et
.type
== NT_float
)
12964 inst
.instruction
= NEON_ENC_FLOAT (inst
.instruction
);
12965 neon_three_same (neon_quad (rs
), 0, -1);
12969 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12970 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
12975 do_neon_dyadic_if_su (void)
12977 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12981 do_neon_dyadic_if_su_d (void)
12983 /* This version only allow D registers, but that constraint is enforced during
12984 operand parsing so we don't need to do anything extra here. */
12985 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12989 do_neon_dyadic_if_i_d (void)
12991 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12992 affected if we specify unsigned args. */
12993 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12996 enum vfp_or_neon_is_neon_bits
12999 NEON_CHECK_ARCH
= 2
13002 /* Call this function if an instruction which may have belonged to the VFP or
13003 Neon instruction sets, but turned out to be a Neon instruction (due to the
13004 operand types involved, etc.). We have to check and/or fix-up a couple of
13007 - Make sure the user hasn't attempted to make a Neon instruction
13009 - Alter the value in the condition code field if necessary.
13010 - Make sure that the arch supports Neon instructions.
13012 Which of these operations take place depends on bits from enum
13013 vfp_or_neon_is_neon_bits.
13015 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13016 current instruction's condition is COND_ALWAYS, the condition field is
13017 changed to inst.uncond_value. This is necessary because instructions shared
13018 between VFP and Neon may be conditional for the VFP variants only, and the
13019 unconditional Neon version must have, e.g., 0xF in the condition field. */
13022 vfp_or_neon_is_neon (unsigned check
)
13024 /* Conditions are always legal in Thumb mode (IT blocks). */
13025 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
13027 if (inst
.cond
!= COND_ALWAYS
)
13029 first_error (_(BAD_COND
));
13032 if (inst
.uncond_value
!= -1)
13033 inst
.instruction
|= inst
.uncond_value
<< 28;
13036 if ((check
& NEON_CHECK_ARCH
)
13037 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
13039 first_error (_(BAD_FPU
));
13047 do_neon_addsub_if_i (void)
13049 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
13052 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13055 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13056 affected if we specify unsigned args. */
13057 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
13060 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13062 V<op> A,B (A is operand 0, B is operand 2)
13067 so handle that case specially. */
13070 neon_exchange_operands (void)
13072 void *scratch
= alloca (sizeof (inst
.operands
[0]));
13073 if (inst
.operands
[1].present
)
13075 /* Swap operands[1] and operands[2]. */
13076 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
13077 inst
.operands
[1] = inst
.operands
[2];
13078 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
13082 inst
.operands
[1] = inst
.operands
[2];
13083 inst
.operands
[2] = inst
.operands
[0];
13088 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
13090 if (inst
.operands
[2].isreg
)
13093 neon_exchange_operands ();
13094 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
13098 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13099 struct neon_type_el et
= neon_check_type (2, rs
,
13100 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
13102 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13103 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13104 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13105 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13106 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13107 inst
.instruction
|= neon_quad (rs
) << 6;
13108 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13109 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13111 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13118 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
13122 do_neon_cmp_inv (void)
13124 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
13130 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
13133 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13134 scalars, which are encoded in 5 bits, M : Rm.
13135 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13136 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13140 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
13142 unsigned regno
= NEON_SCALAR_REG (scalar
);
13143 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
13148 if (regno
> 7 || elno
> 3)
13150 return regno
| (elno
<< 3);
13153 if (regno
> 15 || elno
> 1)
13155 return regno
| (elno
<< 4);
13159 first_error (_("scalar out of range for multiply instruction"));
13165 /* Encode multiply / multiply-accumulate scalar instructions. */
13168 neon_mul_mac (struct neon_type_el et
, int ubit
)
13172 /* Give a more helpful error message if we have an invalid type. */
13173 if (et
.type
== NT_invtype
)
13176 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
13177 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13178 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13179 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13180 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13181 inst
.instruction
|= LOW4 (scalar
);
13182 inst
.instruction
|= HI1 (scalar
) << 5;
13183 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13184 inst
.instruction
|= neon_logbits (et
.size
) << 20;
13185 inst
.instruction
|= (ubit
!= 0) << 24;
13187 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13191 do_neon_mac_maybe_scalar (void)
13193 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
13196 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13199 if (inst
.operands
[2].isscalar
)
13201 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13202 struct neon_type_el et
= neon_check_type (3, rs
,
13203 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13204 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13205 neon_mul_mac (et
, neon_quad (rs
));
13209 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13210 affected if we specify unsigned args. */
13211 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13216 do_neon_fmac (void)
13218 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
13221 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13224 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13230 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13231 struct neon_type_el et
= neon_check_type (3, rs
,
13232 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13233 neon_three_same (neon_quad (rs
), 0, et
.size
);
13236 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13237 same types as the MAC equivalents. The polynomial type for this instruction
13238 is encoded the same as the integer type. */
13243 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13246 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13249 if (inst
.operands
[2].isscalar
)
13250 do_neon_mac_maybe_scalar ();
13252 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13256 do_neon_qdmulh (void)
13258 if (inst
.operands
[2].isscalar
)
13260 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13261 struct neon_type_el et
= neon_check_type (3, rs
,
13262 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13263 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13264 neon_mul_mac (et
, neon_quad (rs
));
13268 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13269 struct neon_type_el et
= neon_check_type (3, rs
,
13270 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13271 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13272 /* The U bit (rounding) comes from bit mask. */
13273 neon_three_same (neon_quad (rs
), 0, et
.size
);
13278 do_neon_fcmp_absolute (void)
13280 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13281 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13282 /* Size field comes from bit mask. */
13283 neon_three_same (neon_quad (rs
), 1, -1);
13287 do_neon_fcmp_absolute_inv (void)
13289 neon_exchange_operands ();
13290 do_neon_fcmp_absolute ();
13294 do_neon_step (void)
13296 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13297 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13298 neon_three_same (neon_quad (rs
), 0, -1);
13302 do_neon_abs_neg (void)
13304 enum neon_shape rs
;
13305 struct neon_type_el et
;
13307 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
13310 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13313 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13314 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
13316 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13317 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13318 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13319 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13320 inst
.instruction
|= neon_quad (rs
) << 6;
13321 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13322 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13324 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13330 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13331 struct neon_type_el et
= neon_check_type (2, rs
,
13332 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13333 int imm
= inst
.operands
[2].imm
;
13334 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13335 _("immediate out of range for insert"));
13336 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13342 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13343 struct neon_type_el et
= neon_check_type (2, rs
,
13344 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13345 int imm
= inst
.operands
[2].imm
;
13346 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13347 _("immediate out of range for insert"));
13348 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
13352 do_neon_qshlu_imm (void)
13354 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13355 struct neon_type_el et
= neon_check_type (2, rs
,
13356 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
13357 int imm
= inst
.operands
[2].imm
;
13358 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13359 _("immediate out of range for shift"));
13360 /* Only encodes the 'U present' variant of the instruction.
13361 In this case, signed types have OP (bit 8) set to 0.
13362 Unsigned types have OP set to 1. */
13363 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
13364 /* The rest of the bits are the same as other immediate shifts. */
13365 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13369 do_neon_qmovn (void)
13371 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13372 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13373 /* Saturating move where operands can be signed or unsigned, and the
13374 destination has the same signedness. */
13375 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13376 if (et
.type
== NT_unsigned
)
13377 inst
.instruction
|= 0xc0;
13379 inst
.instruction
|= 0x80;
13380 neon_two_same (0, 1, et
.size
/ 2);
13384 do_neon_qmovun (void)
13386 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13387 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13388 /* Saturating move with unsigned results. Operands must be signed. */
13389 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13390 neon_two_same (0, 1, et
.size
/ 2);
13394 do_neon_rshift_sat_narrow (void)
13396 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13397 or unsigned. If operands are unsigned, results must also be unsigned. */
13398 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13399 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13400 int imm
= inst
.operands
[2].imm
;
13401 /* This gets the bounds check, size encoding and immediate bits calculation
13405 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
13406 VQMOVN.I<size> <Dd>, <Qm>. */
13409 inst
.operands
[2].present
= 0;
13410 inst
.instruction
= N_MNEM_vqmovn
;
13415 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13416 _("immediate out of range"));
13417 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
13421 do_neon_rshift_sat_narrow_u (void)
13423 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13424 or unsigned. If operands are unsigned, results must also be unsigned. */
13425 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13426 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13427 int imm
= inst
.operands
[2].imm
;
13428 /* This gets the bounds check, size encoding and immediate bits calculation
13432 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
13433 VQMOVUN.I<size> <Dd>, <Qm>. */
13436 inst
.operands
[2].present
= 0;
13437 inst
.instruction
= N_MNEM_vqmovun
;
13442 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13443 _("immediate out of range"));
13444 /* FIXME: The manual is kind of unclear about what value U should have in
13445 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
13447 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
13451 do_neon_movn (void)
13453 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13454 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13455 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13456 neon_two_same (0, 1, et
.size
/ 2);
13460 do_neon_rshift_narrow (void)
13462 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13463 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13464 int imm
= inst
.operands
[2].imm
;
13465 /* This gets the bounds check, size encoding and immediate bits calculation
13469 /* If immediate is zero then we are a pseudo-instruction for
13470 VMOVN.I<size> <Dd>, <Qm> */
13473 inst
.operands
[2].present
= 0;
13474 inst
.instruction
= N_MNEM_vmovn
;
13479 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13480 _("immediate out of range for narrowing operation"));
13481 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
13485 do_neon_shll (void)
13487 /* FIXME: Type checking when lengthening. */
13488 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
13489 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
13490 unsigned imm
= inst
.operands
[2].imm
;
13492 if (imm
== et
.size
)
13494 /* Maximum shift variant. */
13495 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13496 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13497 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13498 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13499 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13500 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13502 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13506 /* A more-specific type check for non-max versions. */
13507 et
= neon_check_type (2, NS_QDI
,
13508 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13509 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13510 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
13514 /* Check the various types for the VCVT instruction, and return which version
13515 the current instruction is. */
13518 neon_cvt_flavour (enum neon_shape rs
)
13520 #define CVT_VAR(C,X,Y) \
13521 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
13522 if (et.type != NT_invtype) \
13524 inst.error = NULL; \
13527 struct neon_type_el et
;
13528 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
13529 || rs
== NS_FF
) ? N_VFP
: 0;
13530 /* The instruction versions which take an immediate take one register
13531 argument, which is extended to the width of the full register. Thus the
13532 "source" and "destination" registers must have the same width. Hack that
13533 here by making the size equal to the key (wider, in this case) operand. */
13534 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
13536 CVT_VAR (0, N_S32
, N_F32
);
13537 CVT_VAR (1, N_U32
, N_F32
);
13538 CVT_VAR (2, N_F32
, N_S32
);
13539 CVT_VAR (3, N_F32
, N_U32
);
13540 /* Half-precision conversions. */
13541 CVT_VAR (4, N_F32
, N_F16
);
13542 CVT_VAR (5, N_F16
, N_F32
);
13546 /* VFP instructions. */
13547 CVT_VAR (6, N_F32
, N_F64
);
13548 CVT_VAR (7, N_F64
, N_F32
);
13549 CVT_VAR (8, N_S32
, N_F64
| key
);
13550 CVT_VAR (9, N_U32
, N_F64
| key
);
13551 CVT_VAR (10, N_F64
| key
, N_S32
);
13552 CVT_VAR (11, N_F64
| key
, N_U32
);
13553 /* VFP instructions with bitshift. */
13554 CVT_VAR (12, N_F32
| key
, N_S16
);
13555 CVT_VAR (13, N_F32
| key
, N_U16
);
13556 CVT_VAR (14, N_F64
| key
, N_S16
);
13557 CVT_VAR (15, N_F64
| key
, N_U16
);
13558 CVT_VAR (16, N_S16
, N_F32
| key
);
13559 CVT_VAR (17, N_U16
, N_F32
| key
);
13560 CVT_VAR (18, N_S16
, N_F64
| key
);
13561 CVT_VAR (19, N_U16
, N_F64
| key
);
13567 /* Neon-syntax VFP conversions. */
13570 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
13572 const char *opname
= 0;
13574 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
13576 /* Conversions with immediate bitshift. */
13577 const char *enc
[] =
13601 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13603 opname
= enc
[flavour
];
13604 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13605 _("operands 0 and 1 must be the same register"));
13606 inst
.operands
[1] = inst
.operands
[2];
13607 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
13612 /* Conversions without bitshift. */
13613 const char *enc
[] =
13629 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13630 opname
= enc
[flavour
];
13634 do_vfp_nsyn_opcode (opname
);
13638 do_vfp_nsyn_cvtz (void)
13640 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
13641 int flavour
= neon_cvt_flavour (rs
);
13642 const char *enc
[] =
13656 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
13657 do_vfp_nsyn_opcode (enc
[flavour
]);
13663 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
13664 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
13665 int flavour
= neon_cvt_flavour (rs
);
13667 /* VFP rather than Neon conversions. */
13670 do_vfp_nsyn_cvt (rs
, flavour
);
13680 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
13682 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13685 /* Fixed-point conversion with #0 immediate is encoded as an
13686 integer conversion. */
13687 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
13689 immbits
= 32 - inst
.operands
[2].imm
;
13690 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13692 inst
.instruction
|= enctab
[flavour
];
13693 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13694 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13695 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13696 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13697 inst
.instruction
|= neon_quad (rs
) << 6;
13698 inst
.instruction
|= 1 << 21;
13699 inst
.instruction
|= immbits
<< 16;
13701 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13709 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
13711 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13713 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13717 inst
.instruction
|= enctab
[flavour
];
13719 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13720 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13721 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13722 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13723 inst
.instruction
|= neon_quad (rs
) << 6;
13724 inst
.instruction
|= 2 << 18;
13726 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13730 /* Half-precision conversions for Advanced SIMD -- neon. */
13735 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
13737 as_bad (_("operand size must match register width"));
13742 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
13744 as_bad (_("operand size must match register width"));
13749 inst
.instruction
= 0x3b60600;
13751 inst
.instruction
= 0x3b60700;
13753 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13754 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13755 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13756 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13757 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13761 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
13762 do_vfp_nsyn_cvt (rs
, flavour
);
13767 do_neon_cvtb (void)
13769 inst
.instruction
= 0xeb20a40;
13771 /* The sizes are attached to the mnemonic. */
13772 if (inst
.vectype
.el
[0].type
!= NT_invtype
13773 && inst
.vectype
.el
[0].size
== 16)
13774 inst
.instruction
|= 0x00010000;
13776 /* Programmer's syntax: the sizes are attached to the operands. */
13777 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
13778 && inst
.operands
[0].vectype
.size
== 16)
13779 inst
.instruction
|= 0x00010000;
13781 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
13782 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
13783 do_vfp_cond_or_thumb ();
13788 do_neon_cvtt (void)
13791 inst
.instruction
|= 0x80;
13795 neon_move_immediate (void)
13797 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
13798 struct neon_type_el et
= neon_check_type (2, rs
,
13799 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13800 unsigned immlo
, immhi
= 0, immbits
;
13801 int op
, cmode
, float_p
;
13803 constraint (et
.type
== NT_invtype
,
13804 _("operand size must be specified for immediate VMOV"));
13806 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
13807 op
= (inst
.instruction
& (1 << 5)) != 0;
13809 immlo
= inst
.operands
[1].imm
;
13810 if (inst
.operands
[1].regisimm
)
13811 immhi
= inst
.operands
[1].reg
;
13813 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
13814 _("immediate has bits set outside the operand size"));
13816 float_p
= inst
.operands
[1].immisfloat
;
13818 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
13819 et
.size
, et
.type
)) == FAIL
)
13821 /* Invert relevant bits only. */
13822 neon_invert_size (&immlo
, &immhi
, et
.size
);
13823 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
13824 with one or the other; those cases are caught by
13825 neon_cmode_for_move_imm. */
13827 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
13828 &op
, et
.size
, et
.type
)) == FAIL
)
13830 first_error (_("immediate out of range"));
13835 inst
.instruction
&= ~(1 << 5);
13836 inst
.instruction
|= op
<< 5;
13838 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13839 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13840 inst
.instruction
|= neon_quad (rs
) << 6;
13841 inst
.instruction
|= cmode
<< 8;
13843 neon_write_immbits (immbits
);
13849 if (inst
.operands
[1].isreg
)
13851 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13853 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13854 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13855 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13856 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13857 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13858 inst
.instruction
|= neon_quad (rs
) << 6;
13862 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13863 neon_move_immediate ();
13866 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13869 /* Encode instructions of form:
13871 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13872 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
13875 neon_mixed_length (struct neon_type_el et
, unsigned size
)
13877 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13878 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13879 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13880 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13881 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13882 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13883 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
13884 inst
.instruction
|= neon_logbits (size
) << 20;
13886 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13890 do_neon_dyadic_long (void)
13892 /* FIXME: Type checking for lengthening op. */
13893 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13894 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
13895 neon_mixed_length (et
, et
.size
);
13899 do_neon_abal (void)
13901 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13902 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
13903 neon_mixed_length (et
, et
.size
);
13907 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
13909 if (inst
.operands
[2].isscalar
)
13911 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
13912 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
13913 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13914 neon_mul_mac (et
, et
.type
== NT_unsigned
);
13918 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13919 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
13920 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13921 neon_mixed_length (et
, et
.size
);
13926 do_neon_mac_maybe_scalar_long (void)
13928 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
13932 do_neon_dyadic_wide (void)
13934 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
13935 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13936 neon_mixed_length (et
, et
.size
);
13940 do_neon_dyadic_narrow (void)
13942 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13943 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
13944 /* Operand sign is unimportant, and the U bit is part of the opcode,
13945 so force the operand type to integer. */
13946 et
.type
= NT_integer
;
13947 neon_mixed_length (et
, et
.size
/ 2);
13951 do_neon_mul_sat_scalar_long (void)
13953 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
13957 do_neon_vmull (void)
13959 if (inst
.operands
[2].isscalar
)
13960 do_neon_mac_maybe_scalar_long ();
13963 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13964 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
13965 if (et
.type
== NT_poly
)
13966 inst
.instruction
= NEON_ENC_POLY (inst
.instruction
);
13968 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13969 /* For polynomial encoding, size field must be 0b00 and the U bit must be
13970 zero. Should be OK as-is. */
13971 neon_mixed_length (et
, et
.size
);
13978 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
13979 struct neon_type_el et
= neon_check_type (3, rs
,
13980 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13981 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
13983 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
13984 _("shift out of range"));
13985 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13986 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13987 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13988 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13989 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13990 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13991 inst
.instruction
|= neon_quad (rs
) << 6;
13992 inst
.instruction
|= imm
<< 8;
13994 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
14000 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14001 struct neon_type_el et
= neon_check_type (2, rs
,
14002 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14003 unsigned op
= (inst
.instruction
>> 7) & 3;
14004 /* N (width of reversed regions) is encoded as part of the bitmask. We
14005 extract it here to check the elements to be reversed are smaller.
14006 Otherwise we'd get a reserved instruction. */
14007 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
14008 gas_assert (elsize
!= 0);
14009 constraint (et
.size
>= elsize
,
14010 _("elements must be smaller than reversal region"));
14011 neon_two_same (neon_quad (rs
), 1, et
.size
);
14017 if (inst
.operands
[1].isscalar
)
14019 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
14020 struct neon_type_el et
= neon_check_type (2, rs
,
14021 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14022 unsigned sizebits
= et
.size
>> 3;
14023 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14024 int logsize
= neon_logbits (et
.size
);
14025 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
14027 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
14030 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
14031 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14032 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14033 inst
.instruction
|= LOW4 (dm
);
14034 inst
.instruction
|= HI1 (dm
) << 5;
14035 inst
.instruction
|= neon_quad (rs
) << 6;
14036 inst
.instruction
|= x
<< 17;
14037 inst
.instruction
|= sizebits
<< 16;
14039 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
14043 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
14044 struct neon_type_el et
= neon_check_type (2, rs
,
14045 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14046 /* Duplicate ARM register to lanes of vector. */
14047 inst
.instruction
= NEON_ENC_ARMREG (inst
.instruction
);
14050 case 8: inst
.instruction
|= 0x400000; break;
14051 case 16: inst
.instruction
|= 0x000020; break;
14052 case 32: inst
.instruction
|= 0x000000; break;
14055 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14056 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
14057 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
14058 inst
.instruction
|= neon_quad (rs
) << 21;
14059 /* The encoding for this instruction is identical for the ARM and Thumb
14060 variants, except for the condition field. */
14061 do_vfp_cond_or_thumb ();
14065 /* VMOV has particularly many variations. It can be one of:
14066 0. VMOV<c><q> <Qd>, <Qm>
14067 1. VMOV<c><q> <Dd>, <Dm>
14068 (Register operations, which are VORR with Rm = Rn.)
14069 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14070 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14072 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14073 (ARM register to scalar.)
14074 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14075 (Two ARM registers to vector.)
14076 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14077 (Scalar to ARM register.)
14078 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14079 (Vector to two ARM registers.)
14080 8. VMOV.F32 <Sd>, <Sm>
14081 9. VMOV.F64 <Dd>, <Dm>
14082 (VFP register moves.)
14083 10. VMOV.F32 <Sd>, #imm
14084 11. VMOV.F64 <Dd>, #imm
14085 (VFP float immediate load.)
14086 12. VMOV <Rd>, <Sm>
14087 (VFP single to ARM reg.)
14088 13. VMOV <Sd>, <Rm>
14089 (ARM reg to VFP single.)
14090 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14091 (Two ARM regs to two VFP singles.)
14092 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14093 (Two VFP singles to two ARM regs.)
14095 These cases can be disambiguated using neon_select_shape, except cases 1/9
14096 and 3/11 which depend on the operand type too.
14098 All the encoded bits are hardcoded by this function.
14100 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14101 Cases 5, 7 may be used with VFPv2 and above.
14103 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14104 can specify a type where it doesn't make sense to, and is ignored). */
14109 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
14110 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
14112 struct neon_type_el et
;
14113 const char *ldconst
= 0;
14117 case NS_DD
: /* case 1/9. */
14118 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14119 /* It is not an error here if no type is given. */
14121 if (et
.type
== NT_float
&& et
.size
== 64)
14123 do_vfp_nsyn_opcode ("fcpyd");
14126 /* fall through. */
14128 case NS_QQ
: /* case 0/1. */
14130 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14132 /* The architecture manual I have doesn't explicitly state which
14133 value the U bit should have for register->register moves, but
14134 the equivalent VORR instruction has U = 0, so do that. */
14135 inst
.instruction
= 0x0200110;
14136 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14137 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14138 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14139 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14140 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14141 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14142 inst
.instruction
|= neon_quad (rs
) << 6;
14144 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
14148 case NS_DI
: /* case 3/11. */
14149 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14151 if (et
.type
== NT_float
&& et
.size
== 64)
14153 /* case 11 (fconstd). */
14154 ldconst
= "fconstd";
14155 goto encode_fconstd
;
14157 /* fall through. */
14159 case NS_QI
: /* case 2/3. */
14160 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14162 inst
.instruction
= 0x0800010;
14163 neon_move_immediate ();
14164 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
14167 case NS_SR
: /* case 4. */
14169 unsigned bcdebits
= 0;
14171 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
14172 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
14174 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14175 logsize
= neon_logbits (et
.size
);
14177 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14179 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14180 && et
.size
!= 32, _(BAD_FPU
));
14181 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14182 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14186 case 8: bcdebits
= 0x8; break;
14187 case 16: bcdebits
= 0x1; break;
14188 case 32: bcdebits
= 0x0; break;
14192 bcdebits
|= x
<< logsize
;
14194 inst
.instruction
= 0xe000b10;
14195 do_vfp_cond_or_thumb ();
14196 inst
.instruction
|= LOW4 (dn
) << 16;
14197 inst
.instruction
|= HI1 (dn
) << 7;
14198 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14199 inst
.instruction
|= (bcdebits
& 3) << 5;
14200 inst
.instruction
|= (bcdebits
>> 2) << 21;
14204 case NS_DRR
: /* case 5 (fmdrr). */
14205 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14208 inst
.instruction
= 0xc400b10;
14209 do_vfp_cond_or_thumb ();
14210 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
14211 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
14212 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14213 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14216 case NS_RS
: /* case 6. */
14219 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14220 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14221 unsigned abcdebits
= 0;
14223 et
= neon_check_type (2, NS_NULL
,
14224 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14225 logsize
= neon_logbits (et
.size
);
14227 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14229 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14230 && et
.size
!= 32, _(BAD_FPU
));
14231 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14232 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14236 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14237 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14238 case 32: abcdebits
= 0x00; break;
14242 abcdebits
|= x
<< logsize
;
14243 inst
.instruction
= 0xe100b10;
14244 do_vfp_cond_or_thumb ();
14245 inst
.instruction
|= LOW4 (dn
) << 16;
14246 inst
.instruction
|= HI1 (dn
) << 7;
14247 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14248 inst
.instruction
|= (abcdebits
& 3) << 5;
14249 inst
.instruction
|= (abcdebits
>> 2) << 21;
14253 case NS_RRD
: /* case 7 (fmrrd). */
14254 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14257 inst
.instruction
= 0xc500b10;
14258 do_vfp_cond_or_thumb ();
14259 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14260 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14261 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14262 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14265 case NS_FF
: /* case 8 (fcpys). */
14266 do_vfp_nsyn_opcode ("fcpys");
14269 case NS_FI
: /* case 10 (fconsts). */
14270 ldconst
= "fconsts";
14272 if (is_quarter_float (inst
.operands
[1].imm
))
14274 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
14275 do_vfp_nsyn_opcode (ldconst
);
14278 first_error (_("immediate out of range"));
14281 case NS_RF
: /* case 12 (fmrs). */
14282 do_vfp_nsyn_opcode ("fmrs");
14285 case NS_FR
: /* case 13 (fmsr). */
14286 do_vfp_nsyn_opcode ("fmsr");
14289 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14290 (one of which is a list), but we have parsed four. Do some fiddling to
14291 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14293 case NS_RRFF
: /* case 14 (fmrrs). */
14294 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
14295 _("VFP registers must be adjacent"));
14296 inst
.operands
[2].imm
= 2;
14297 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14298 do_vfp_nsyn_opcode ("fmrrs");
14301 case NS_FFRR
: /* case 15 (fmsrr). */
14302 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
14303 _("VFP registers must be adjacent"));
14304 inst
.operands
[1] = inst
.operands
[2];
14305 inst
.operands
[2] = inst
.operands
[3];
14306 inst
.operands
[0].imm
= 2;
14307 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14308 do_vfp_nsyn_opcode ("fmsrr");
14317 do_neon_rshift_round_imm (void)
14319 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14320 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14321 int imm
= inst
.operands
[2].imm
;
14323 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14326 inst
.operands
[2].present
= 0;
14331 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14332 _("immediate out of range for shift"));
14333 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
14338 do_neon_movl (void)
14340 struct neon_type_el et
= neon_check_type (2, NS_QD
,
14341 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14342 unsigned sizebits
= et
.size
>> 3;
14343 inst
.instruction
|= sizebits
<< 19;
14344 neon_two_same (0, et
.type
== NT_unsigned
, -1);
14350 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14351 struct neon_type_el et
= neon_check_type (2, rs
,
14352 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14353 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
14354 neon_two_same (neon_quad (rs
), 1, et
.size
);
14358 do_neon_zip_uzp (void)
14360 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14361 struct neon_type_el et
= neon_check_type (2, rs
,
14362 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14363 if (rs
== NS_DD
&& et
.size
== 32)
14365 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
14366 inst
.instruction
= N_MNEM_vtrn
;
14370 neon_two_same (neon_quad (rs
), 1, et
.size
);
14374 do_neon_sat_abs_neg (void)
14376 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14377 struct neon_type_el et
= neon_check_type (2, rs
,
14378 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14379 neon_two_same (neon_quad (rs
), 1, et
.size
);
14383 do_neon_pair_long (void)
14385 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14386 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
14387 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
14388 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
14389 neon_two_same (neon_quad (rs
), 1, et
.size
);
14393 do_neon_recip_est (void)
14395 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14396 struct neon_type_el et
= neon_check_type (2, rs
,
14397 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
14398 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14399 neon_two_same (neon_quad (rs
), 1, et
.size
);
14405 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14406 struct neon_type_el et
= neon_check_type (2, rs
,
14407 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14408 neon_two_same (neon_quad (rs
), 1, et
.size
);
14414 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14415 struct neon_type_el et
= neon_check_type (2, rs
,
14416 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
14417 neon_two_same (neon_quad (rs
), 1, et
.size
);
14423 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14424 struct neon_type_el et
= neon_check_type (2, rs
,
14425 N_EQK
| N_INT
, N_8
| N_KEY
);
14426 neon_two_same (neon_quad (rs
), 1, et
.size
);
14432 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14433 neon_two_same (neon_quad (rs
), 1, -1);
14437 do_neon_tbl_tbx (void)
14439 unsigned listlenbits
;
14440 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
14442 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
14444 first_error (_("bad list length for table lookup"));
14448 listlenbits
= inst
.operands
[1].imm
- 1;
14449 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14450 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14451 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14452 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14453 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14454 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14455 inst
.instruction
|= listlenbits
<< 8;
14457 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
14461 do_neon_ldm_stm (void)
14463 /* P, U and L bits are part of bitmask. */
14464 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
14465 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
14467 if (inst
.operands
[1].issingle
)
14469 do_vfp_nsyn_ldm_stm (is_dbmode
);
14473 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
14474 _("writeback (!) must be used for VLDMDB and VSTMDB"));
14476 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14477 _("register list must contain at least 1 and at most 16 "
14480 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14481 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
14482 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14483 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
14485 inst
.instruction
|= offsetbits
;
14487 do_vfp_cond_or_thumb ();
14491 do_neon_ldr_str (void)
14493 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
14495 if (inst
.operands
[0].issingle
)
14498 do_vfp_nsyn_opcode ("flds");
14500 do_vfp_nsyn_opcode ("fsts");
14505 do_vfp_nsyn_opcode ("fldd");
14507 do_vfp_nsyn_opcode ("fstd");
14511 /* "interleave" version also handles non-interleaving register VLD1/VST1
14515 do_neon_ld_st_interleave (void)
14517 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
14518 N_8
| N_16
| N_32
| N_64
);
14519 unsigned alignbits
= 0;
14521 /* The bits in this table go:
14522 0: register stride of one (0) or two (1)
14523 1,2: register list length, minus one (1, 2, 3, 4).
14524 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
14525 We use -1 for invalid entries. */
14526 const int typetable
[] =
14528 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
14529 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
14530 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
14531 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
14535 if (et
.type
== NT_invtype
)
14538 if (inst
.operands
[1].immisalign
)
14539 switch (inst
.operands
[1].imm
>> 8)
14541 case 64: alignbits
= 1; break;
14543 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
14544 goto bad_alignment
;
14548 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
14549 goto bad_alignment
;
14554 first_error (_("bad alignment"));
14558 inst
.instruction
|= alignbits
<< 4;
14559 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14561 /* Bits [4:6] of the immediate in a list specifier encode register stride
14562 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
14563 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
14564 up the right value for "type" in a table based on this value and the given
14565 list style, then stick it back. */
14566 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
14567 | (((inst
.instruction
>> 8) & 3) << 3);
14569 typebits
= typetable
[idx
];
14571 constraint (typebits
== -1, _("bad list type for instruction"));
14573 inst
.instruction
&= ~0xf00;
14574 inst
.instruction
|= typebits
<< 8;
14577 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
14578 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
14579 otherwise. The variable arguments are a list of pairs of legal (size, align)
14580 values, terminated with -1. */
14583 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
14586 int result
= FAIL
, thissize
, thisalign
;
14588 if (!inst
.operands
[1].immisalign
)
14594 va_start (ap
, do_align
);
14598 thissize
= va_arg (ap
, int);
14599 if (thissize
== -1)
14601 thisalign
= va_arg (ap
, int);
14603 if (size
== thissize
&& align
== thisalign
)
14606 while (result
!= SUCCESS
);
14610 if (result
== SUCCESS
)
14613 first_error (_("unsupported alignment for instruction"));
14619 do_neon_ld_st_lane (void)
14621 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14622 int align_good
, do_align
= 0;
14623 int logsize
= neon_logbits (et
.size
);
14624 int align
= inst
.operands
[1].imm
>> 8;
14625 int n
= (inst
.instruction
>> 8) & 3;
14626 int max_el
= 64 / et
.size
;
14628 if (et
.type
== NT_invtype
)
14631 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
14632 _("bad list length"));
14633 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
14634 _("scalar index out of range"));
14635 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
14637 _("stride of 2 unavailable when element size is 8"));
14641 case 0: /* VLD1 / VST1. */
14642 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
14644 if (align_good
== FAIL
)
14648 unsigned alignbits
= 0;
14651 case 16: alignbits
= 0x1; break;
14652 case 32: alignbits
= 0x3; break;
14655 inst
.instruction
|= alignbits
<< 4;
14659 case 1: /* VLD2 / VST2. */
14660 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
14662 if (align_good
== FAIL
)
14665 inst
.instruction
|= 1 << 4;
14668 case 2: /* VLD3 / VST3. */
14669 constraint (inst
.operands
[1].immisalign
,
14670 _("can't use alignment with this instruction"));
14673 case 3: /* VLD4 / VST4. */
14674 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14675 16, 64, 32, 64, 32, 128, -1);
14676 if (align_good
== FAIL
)
14680 unsigned alignbits
= 0;
14683 case 8: alignbits
= 0x1; break;
14684 case 16: alignbits
= 0x1; break;
14685 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
14688 inst
.instruction
|= alignbits
<< 4;
14695 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
14696 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14697 inst
.instruction
|= 1 << (4 + logsize
);
14699 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
14700 inst
.instruction
|= logsize
<< 10;
14703 /* Encode single n-element structure to all lanes VLD<n> instructions. */
14706 do_neon_ld_dup (void)
14708 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14709 int align_good
, do_align
= 0;
14711 if (et
.type
== NT_invtype
)
14714 switch ((inst
.instruction
>> 8) & 3)
14716 case 0: /* VLD1. */
14717 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
14718 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14719 &do_align
, 16, 16, 32, 32, -1);
14720 if (align_good
== FAIL
)
14722 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
14725 case 2: inst
.instruction
|= 1 << 5; break;
14726 default: first_error (_("bad list length")); return;
14728 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14731 case 1: /* VLD2. */
14732 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14733 &do_align
, 8, 16, 16, 32, 32, 64, -1);
14734 if (align_good
== FAIL
)
14736 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
14737 _("bad list length"));
14738 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14739 inst
.instruction
|= 1 << 5;
14740 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14743 case 2: /* VLD3. */
14744 constraint (inst
.operands
[1].immisalign
,
14745 _("can't use alignment with this instruction"));
14746 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
14747 _("bad list length"));
14748 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14749 inst
.instruction
|= 1 << 5;
14750 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14753 case 3: /* VLD4. */
14755 int align
= inst
.operands
[1].imm
>> 8;
14756 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14757 16, 64, 32, 64, 32, 128, -1);
14758 if (align_good
== FAIL
)
14760 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
14761 _("bad list length"));
14762 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14763 inst
.instruction
|= 1 << 5;
14764 if (et
.size
== 32 && align
== 128)
14765 inst
.instruction
|= 0x3 << 6;
14767 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14774 inst
.instruction
|= do_align
<< 4;
14777 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
14778 apart from bits [11:4]. */
14781 do_neon_ldx_stx (void)
14783 switch (NEON_LANE (inst
.operands
[0].imm
))
14785 case NEON_INTERLEAVE_LANES
:
14786 inst
.instruction
= NEON_ENC_INTERLV (inst
.instruction
);
14787 do_neon_ld_st_interleave ();
14790 case NEON_ALL_LANES
:
14791 inst
.instruction
= NEON_ENC_DUP (inst
.instruction
);
14796 inst
.instruction
= NEON_ENC_LANE (inst
.instruction
);
14797 do_neon_ld_st_lane ();
14800 /* L bit comes from bit mask. */
14801 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14802 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14803 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14805 if (inst
.operands
[1].postind
)
14807 int postreg
= inst
.operands
[1].imm
& 0xf;
14808 constraint (!inst
.operands
[1].immisreg
,
14809 _("post-index must be a register"));
14810 constraint (postreg
== 0xd || postreg
== 0xf,
14811 _("bad register for post-index"));
14812 inst
.instruction
|= postreg
;
14814 else if (inst
.operands
[1].writeback
)
14816 inst
.instruction
|= 0xd;
14819 inst
.instruction
|= 0xf;
14822 inst
.instruction
|= 0xf9000000;
14824 inst
.instruction
|= 0xf4000000;
14827 /* Overall per-instruction processing. */
14829 /* We need to be able to fix up arbitrary expressions in some statements.
14830 This is so that we can handle symbols that are an arbitrary distance from
14831 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
14832 which returns part of an address in a form which will be valid for
14833 a data instruction. We do this by pushing the expression into a symbol
14834 in the expr_section, and creating a fix for that. */
14837 fix_new_arm (fragS
* frag
,
14852 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
14853 (enum bfd_reloc_code_real
) reloc
);
14857 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
14858 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
14862 /* Mark whether the fix is to a THUMB instruction, or an ARM
14864 new_fix
->tc_fix_data
= thumb_mode
;
14867 /* Create a frg for an instruction requiring relaxation. */
14869 output_relax_insn (void)
14875 /* The size of the instruction is unknown, so tie the debug info to the
14876 start of the instruction. */
14877 dwarf2_emit_insn (0);
14879 switch (inst
.reloc
.exp
.X_op
)
14882 sym
= inst
.reloc
.exp
.X_add_symbol
;
14883 offset
= inst
.reloc
.exp
.X_add_number
;
14887 offset
= inst
.reloc
.exp
.X_add_number
;
14890 sym
= make_expr_symbol (&inst
.reloc
.exp
);
14894 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
14895 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
14896 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
14899 /* Write a 32-bit thumb instruction to buf. */
14901 put_thumb32_insn (char * buf
, unsigned long insn
)
14903 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
14904 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
14908 output_inst (const char * str
)
14914 as_bad ("%s -- `%s'", inst
.error
, str
);
14919 output_relax_insn ();
14922 if (inst
.size
== 0)
14925 to
= frag_more (inst
.size
);
14926 /* PR 9814: Record the thumb mode into the current frag so that we know
14927 what type of NOP padding to use, if necessary. We override any previous
14928 setting so that if the mode has changed then the NOPS that we use will
14929 match the encoding of the last instruction in the frag. */
14930 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
14932 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
14934 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
14935 put_thumb32_insn (to
, inst
.instruction
);
14937 else if (inst
.size
> INSN_SIZE
)
14939 gas_assert (inst
.size
== (2 * INSN_SIZE
));
14940 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
14941 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
14944 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
14946 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
14947 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
14948 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
14951 dwarf2_emit_insn (inst
.size
);
14955 output_it_inst (int cond
, int mask
, char * to
)
14957 unsigned long instruction
= 0xbf00;
14960 instruction
|= mask
;
14961 instruction
|= cond
<< 4;
14965 to
= frag_more (2);
14967 dwarf2_emit_insn (2);
14971 md_number_to_chars (to
, instruction
, 2);
14976 /* Tag values used in struct asm_opcode's tag field. */
14979 OT_unconditional
, /* Instruction cannot be conditionalized.
14980 The ARM condition field is still 0xE. */
14981 OT_unconditionalF
, /* Instruction cannot be conditionalized
14982 and carries 0xF in its ARM condition field. */
14983 OT_csuffix
, /* Instruction takes a conditional suffix. */
14984 OT_csuffixF
, /* Some forms of the instruction take a conditional
14985 suffix, others place 0xF where the condition field
14987 OT_cinfix3
, /* Instruction takes a conditional infix,
14988 beginning at character index 3. (In
14989 unified mode, it becomes a suffix.) */
14990 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
14991 tsts, cmps, cmns, and teqs. */
14992 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
14993 character index 3, even in unified mode. Used for
14994 legacy instructions where suffix and infix forms
14995 may be ambiguous. */
14996 OT_csuf_or_in3
, /* Instruction takes either a conditional
14997 suffix or an infix at character index 3. */
14998 OT_odd_infix_unc
, /* This is the unconditional variant of an
14999 instruction that takes a conditional infix
15000 at an unusual position. In unified mode,
15001 this variant will accept a suffix. */
15002 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
15003 are the conditional variants of instructions that
15004 take conditional infixes in unusual positions.
15005 The infix appears at character index
15006 (tag - OT_odd_infix_0). These are not accepted
15007 in unified mode. */
15010 /* Subroutine of md_assemble, responsible for looking up the primary
15011 opcode from the mnemonic the user wrote. STR points to the
15012 beginning of the mnemonic.
15014 This is not simply a hash table lookup, because of conditional
15015 variants. Most instructions have conditional variants, which are
15016 expressed with a _conditional affix_ to the mnemonic. If we were
15017 to encode each conditional variant as a literal string in the opcode
15018 table, it would have approximately 20,000 entries.
15020 Most mnemonics take this affix as a suffix, and in unified syntax,
15021 'most' is upgraded to 'all'. However, in the divided syntax, some
15022 instructions take the affix as an infix, notably the s-variants of
15023 the arithmetic instructions. Of those instructions, all but six
15024 have the infix appear after the third character of the mnemonic.
15026 Accordingly, the algorithm for looking up primary opcodes given
15029 1. Look up the identifier in the opcode table.
15030 If we find a match, go to step U.
15032 2. Look up the last two characters of the identifier in the
15033 conditions table. If we find a match, look up the first N-2
15034 characters of the identifier in the opcode table. If we
15035 find a match, go to step CE.
15037 3. Look up the fourth and fifth characters of the identifier in
15038 the conditions table. If we find a match, extract those
15039 characters from the identifier, and look up the remaining
15040 characters in the opcode table. If we find a match, go
15045 U. Examine the tag field of the opcode structure, in case this is
15046 one of the six instructions with its conditional infix in an
15047 unusual place. If it is, the tag tells us where to find the
15048 infix; look it up in the conditions table and set inst.cond
15049 accordingly. Otherwise, this is an unconditional instruction.
15050 Again set inst.cond accordingly. Return the opcode structure.
15052 CE. Examine the tag field to make sure this is an instruction that
15053 should receive a conditional suffix. If it is not, fail.
15054 Otherwise, set inst.cond from the suffix we already looked up,
15055 and return the opcode structure.
15057 CM. Examine the tag field to make sure this is an instruction that
15058 should receive a conditional infix after the third character.
15059 If it is not, fail. Otherwise, undo the edits to the current
15060 line of input and proceed as for case CE. */
15062 static const struct asm_opcode
*
15063 opcode_lookup (char **str
)
15067 const struct asm_opcode
*opcode
;
15068 const struct asm_cond
*cond
;
15071 /* Scan up to the end of the mnemonic, which must end in white space,
15072 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15073 for (base
= end
= *str
; *end
!= '\0'; end
++)
15074 if (*end
== ' ' || *end
== '.')
15080 /* Handle a possible width suffix and/or Neon type suffix. */
15085 /* The .w and .n suffixes are only valid if the unified syntax is in
15087 if (unified_syntax
&& end
[1] == 'w')
15089 else if (unified_syntax
&& end
[1] == 'n')
15094 inst
.vectype
.elems
= 0;
15096 *str
= end
+ offset
;
15098 if (end
[offset
] == '.')
15100 /* See if we have a Neon type suffix (possible in either unified or
15101 non-unified ARM syntax mode). */
15102 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
15105 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
15111 /* Look for unaffixed or special-case affixed mnemonic. */
15112 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15117 if (opcode
->tag
< OT_odd_infix_0
)
15119 inst
.cond
= COND_ALWAYS
;
15123 if (warn_on_deprecated
&& unified_syntax
)
15124 as_warn (_("conditional infixes are deprecated in unified syntax"));
15125 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
15126 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15129 inst
.cond
= cond
->value
;
15133 /* Cannot have a conditional suffix on a mnemonic of less than two
15135 if (end
- base
< 3)
15138 /* Look for suffixed mnemonic. */
15140 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15141 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15143 if (opcode
&& cond
)
15146 switch (opcode
->tag
)
15148 case OT_cinfix3_legacy
:
15149 /* Ignore conditional suffixes matched on infix only mnemonics. */
15153 case OT_cinfix3_deprecated
:
15154 case OT_odd_infix_unc
:
15155 if (!unified_syntax
)
15157 /* else fall through */
15161 case OT_csuf_or_in3
:
15162 inst
.cond
= cond
->value
;
15165 case OT_unconditional
:
15166 case OT_unconditionalF
:
15168 inst
.cond
= cond
->value
;
15171 /* Delayed diagnostic. */
15172 inst
.error
= BAD_COND
;
15173 inst
.cond
= COND_ALWAYS
;
15182 /* Cannot have a usual-position infix on a mnemonic of less than
15183 six characters (five would be a suffix). */
15184 if (end
- base
< 6)
15187 /* Look for infixed mnemonic in the usual position. */
15189 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15193 memcpy (save
, affix
, 2);
15194 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
15195 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15197 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
15198 memcpy (affix
, save
, 2);
15201 && (opcode
->tag
== OT_cinfix3
15202 || opcode
->tag
== OT_cinfix3_deprecated
15203 || opcode
->tag
== OT_csuf_or_in3
15204 || opcode
->tag
== OT_cinfix3_legacy
))
15207 if (warn_on_deprecated
&& unified_syntax
15208 && (opcode
->tag
== OT_cinfix3
15209 || opcode
->tag
== OT_cinfix3_deprecated
))
15210 as_warn (_("conditional infixes are deprecated in unified syntax"));
15212 inst
.cond
= cond
->value
;
15219 /* This function generates an initial IT instruction, leaving its block
15220 virtually open for the new instructions. Eventually,
15221 the mask will be updated by now_it_add_mask () each time
15222 a new instruction needs to be included in the IT block.
15223 Finally, the block is closed with close_automatic_it_block ().
15224 The block closure can be requested either from md_assemble (),
15225 a tencode (), or due to a label hook. */
15228 new_automatic_it_block (int cond
)
15230 now_it
.state
= AUTOMATIC_IT_BLOCK
;
15231 now_it
.mask
= 0x18;
15233 now_it
.block_length
= 1;
15234 mapping_state (MAP_THUMB
);
15235 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
15238 /* Close an automatic IT block.
15239 See comments in new_automatic_it_block (). */
15242 close_automatic_it_block (void)
15244 now_it
.mask
= 0x10;
15245 now_it
.block_length
= 0;
15248 /* Update the mask of the current automatically-generated IT
15249 instruction. See comments in new_automatic_it_block (). */
15252 now_it_add_mask (int cond
)
15254 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15255 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15256 | ((bitvalue) << (nbit)))
15257 const int resulting_bit
= (cond
& 1);
15259 now_it
.mask
&= 0xf;
15260 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15262 (5 - now_it
.block_length
));
15263 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15265 ((5 - now_it
.block_length
) - 1) );
15266 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
15269 #undef SET_BIT_VALUE
15272 /* The IT blocks handling machinery is accessed through the these functions:
15273 it_fsm_pre_encode () from md_assemble ()
15274 set_it_insn_type () optional, from the tencode functions
15275 set_it_insn_type_last () ditto
15276 in_it_block () ditto
15277 it_fsm_post_encode () from md_assemble ()
15278 force_automatic_it_block_close () from label habdling functions
15281 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15282 initializing the IT insn type with a generic initial value depending
15283 on the inst.condition.
15284 2) During the tencode function, two things may happen:
15285 a) The tencode function overrides the IT insn type by
15286 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15287 b) The tencode function queries the IT block state by
15288 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15290 Both set_it_insn_type and in_it_block run the internal FSM state
15291 handling function (handle_it_state), because: a) setting the IT insn
15292 type may incur in an invalid state (exiting the function),
15293 and b) querying the state requires the FSM to be updated.
15294 Specifically we want to avoid creating an IT block for conditional
15295 branches, so it_fsm_pre_encode is actually a guess and we can't
15296 determine whether an IT block is required until the tencode () routine
15297 has decided what type of instruction this actually it.
15298 Because of this, if set_it_insn_type and in_it_block have to be used,
15299 set_it_insn_type has to be called first.
15301 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15302 determines the insn IT type depending on the inst.cond code.
15303 When a tencode () routine encodes an instruction that can be
15304 either outside an IT block, or, in the case of being inside, has to be
15305 the last one, set_it_insn_type_last () will determine the proper
15306 IT instruction type based on the inst.cond code. Otherwise,
15307 set_it_insn_type can be called for overriding that logic or
15308 for covering other cases.
15310 Calling handle_it_state () may not transition the IT block state to
15311 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
15312 still queried. Instead, if the FSM determines that the state should
15313 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
15314 after the tencode () function: that's what it_fsm_post_encode () does.
15316 Since in_it_block () calls the state handling function to get an
15317 updated state, an error may occur (due to invalid insns combination).
15318 In that case, inst.error is set.
15319 Therefore, inst.error has to be checked after the execution of
15320 the tencode () routine.
15322 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
15323 any pending state change (if any) that didn't take place in
15324 handle_it_state () as explained above. */
15327 it_fsm_pre_encode (void)
15329 if (inst
.cond
!= COND_ALWAYS
)
15330 inst
.it_insn_type
= INSIDE_IT_INSN
;
15332 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
15334 now_it
.state_handled
= 0;
15337 /* IT state FSM handling function. */
15340 handle_it_state (void)
15342 now_it
.state_handled
= 1;
15344 switch (now_it
.state
)
15346 case OUTSIDE_IT_BLOCK
:
15347 switch (inst
.it_insn_type
)
15349 case OUTSIDE_IT_INSN
:
15352 case INSIDE_IT_INSN
:
15353 case INSIDE_IT_LAST_INSN
:
15354 if (thumb_mode
== 0)
15357 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
15358 as_tsktsk (_("Warning: conditional outside an IT block"\
15363 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
15364 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
15366 /* Automatically generate the IT instruction. */
15367 new_automatic_it_block (inst
.cond
);
15368 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
15369 close_automatic_it_block ();
15373 inst
.error
= BAD_OUT_IT
;
15379 case IF_INSIDE_IT_LAST_INSN
:
15380 case NEUTRAL_IT_INSN
:
15384 now_it
.state
= MANUAL_IT_BLOCK
;
15385 now_it
.block_length
= 0;
15390 case AUTOMATIC_IT_BLOCK
:
15391 /* Three things may happen now:
15392 a) We should increment current it block size;
15393 b) We should close current it block (closing insn or 4 insns);
15394 c) We should close current it block and start a new one (due
15395 to incompatible conditions or
15396 4 insns-length block reached). */
15398 switch (inst
.it_insn_type
)
15400 case OUTSIDE_IT_INSN
:
15401 /* The closure of the block shall happen immediatelly,
15402 so any in_it_block () call reports the block as closed. */
15403 force_automatic_it_block_close ();
15406 case INSIDE_IT_INSN
:
15407 case INSIDE_IT_LAST_INSN
:
15408 case IF_INSIDE_IT_LAST_INSN
:
15409 now_it
.block_length
++;
15411 if (now_it
.block_length
> 4
15412 || !now_it_compatible (inst
.cond
))
15414 force_automatic_it_block_close ();
15415 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
15416 new_automatic_it_block (inst
.cond
);
15420 now_it_add_mask (inst
.cond
);
15423 if (now_it
.state
== AUTOMATIC_IT_BLOCK
15424 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
15425 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
15426 close_automatic_it_block ();
15429 case NEUTRAL_IT_INSN
:
15430 now_it
.block_length
++;
15432 if (now_it
.block_length
> 4)
15433 force_automatic_it_block_close ();
15435 now_it_add_mask (now_it
.cc
& 1);
15439 close_automatic_it_block ();
15440 now_it
.state
= MANUAL_IT_BLOCK
;
15445 case MANUAL_IT_BLOCK
:
15447 /* Check conditional suffixes. */
15448 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
15451 now_it
.mask
&= 0x1f;
15452 is_last
= (now_it
.mask
== 0x10);
15454 switch (inst
.it_insn_type
)
15456 case OUTSIDE_IT_INSN
:
15457 inst
.error
= BAD_NOT_IT
;
15460 case INSIDE_IT_INSN
:
15461 if (cond
!= inst
.cond
)
15463 inst
.error
= BAD_IT_COND
;
15468 case INSIDE_IT_LAST_INSN
:
15469 case IF_INSIDE_IT_LAST_INSN
:
15470 if (cond
!= inst
.cond
)
15472 inst
.error
= BAD_IT_COND
;
15477 inst
.error
= BAD_BRANCH
;
15482 case NEUTRAL_IT_INSN
:
15483 /* The BKPT instruction is unconditional even in an IT block. */
15487 inst
.error
= BAD_IT_IT
;
15498 it_fsm_post_encode (void)
15502 if (!now_it
.state_handled
)
15503 handle_it_state ();
15505 is_last
= (now_it
.mask
== 0x10);
15508 now_it
.state
= OUTSIDE_IT_BLOCK
;
15514 force_automatic_it_block_close (void)
15516 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
15518 close_automatic_it_block ();
15519 now_it
.state
= OUTSIDE_IT_BLOCK
;
15527 if (!now_it
.state_handled
)
15528 handle_it_state ();
15530 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
15534 md_assemble (char *str
)
15537 const struct asm_opcode
* opcode
;
15539 /* Align the previous label if needed. */
15540 if (last_label_seen
!= NULL
)
15542 symbol_set_frag (last_label_seen
, frag_now
);
15543 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
15544 S_SET_SEGMENT (last_label_seen
, now_seg
);
15547 memset (&inst
, '\0', sizeof (inst
));
15548 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
15550 opcode
= opcode_lookup (&p
);
15553 /* It wasn't an instruction, but it might be a register alias of
15554 the form alias .req reg, or a Neon .dn/.qn directive. */
15555 if (! create_register_alias (str
, p
)
15556 && ! create_neon_reg_alias (str
, p
))
15557 as_bad (_("bad instruction `%s'"), str
);
15562 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
15563 as_warn (_("s suffix on comparison instruction is deprecated"));
15565 /* The value which unconditional instructions should have in place of the
15566 condition field. */
15567 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
15571 arm_feature_set variant
;
15573 variant
= cpu_variant
;
15574 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
15575 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
15576 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
15577 /* Check that this instruction is supported for this CPU. */
15578 if (!opcode
->tvariant
15579 || (thumb_mode
== 1
15580 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
15582 as_bad (_("selected processor does not support `%s'"), str
);
15585 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
15586 && opcode
->tencode
!= do_t_branch
)
15588 as_bad (_("Thumb does not support conditional execution"));
15592 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
15594 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
15595 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
15596 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
15598 /* Two things are addressed here.
15599 1) Implicit require narrow instructions on Thumb-1.
15600 This avoids relaxation accidentally introducing Thumb-2
15602 2) Reject wide instructions in non Thumb-2 cores. */
15603 if (inst
.size_req
== 0)
15605 else if (inst
.size_req
== 4)
15607 as_bad (_("selected processor does not support `%s'"), str
);
15613 inst
.instruction
= opcode
->tvalue
;
15615 if (!parse_operands (p
, opcode
->operands
))
15617 /* Prepare the it_insn_type for those encodings that don't set
15619 it_fsm_pre_encode ();
15621 opcode
->tencode ();
15623 it_fsm_post_encode ();
15626 if (!(inst
.error
|| inst
.relax
))
15628 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
15629 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
15630 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
15632 as_bad (_("cannot honor width suffix -- `%s'"), str
);
15637 /* Something has gone badly wrong if we try to relax a fixed size
15639 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
15641 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15642 *opcode
->tvariant
);
15643 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
15644 set those bits when Thumb-2 32-bit instructions are seen. ie.
15645 anything other than bl/blx and v6-M instructions.
15646 This is overly pessimistic for relaxable instructions. */
15647 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
15649 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
15650 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
15651 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15656 mapping_state (MAP_THUMB
);
15659 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
15663 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
15664 is_bx
= (opcode
->aencode
== do_bx
);
15666 /* Check that this instruction is supported for this CPU. */
15667 if (!(is_bx
&& fix_v4bx
)
15668 && !(opcode
->avariant
&&
15669 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
15671 as_bad (_("selected processor does not support `%s'"), str
);
15676 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
15680 inst
.instruction
= opcode
->avalue
;
15681 if (opcode
->tag
== OT_unconditionalF
)
15682 inst
.instruction
|= 0xF << 28;
15684 inst
.instruction
|= inst
.cond
<< 28;
15685 inst
.size
= INSN_SIZE
;
15686 if (!parse_operands (p
, opcode
->operands
))
15688 it_fsm_pre_encode ();
15689 opcode
->aencode ();
15690 it_fsm_post_encode ();
15692 /* Arm mode bx is marked as both v4T and v5 because it's still required
15693 on a hypothetical non-thumb v5 core. */
15695 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
15697 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
15698 *opcode
->avariant
);
15701 mapping_state (MAP_ARM
);
15706 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
15714 check_it_blocks_finished (void)
15719 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
15720 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
15721 == MANUAL_IT_BLOCK
)
15723 as_warn (_("section '%s' finished with an open IT block."),
15727 if (now_it
.state
== MANUAL_IT_BLOCK
)
15728 as_warn (_("file finished with an open IT block."));
15732 /* Various frobbings of labels and their addresses. */
15735 arm_start_line_hook (void)
15737 last_label_seen
= NULL
;
15741 arm_frob_label (symbolS
* sym
)
15743 last_label_seen
= sym
;
15745 ARM_SET_THUMB (sym
, thumb_mode
);
15747 #if defined OBJ_COFF || defined OBJ_ELF
15748 ARM_SET_INTERWORK (sym
, support_interwork
);
15751 force_automatic_it_block_close ();
15753 /* Note - do not allow local symbols (.Lxxx) to be labelled
15754 as Thumb functions. This is because these labels, whilst
15755 they exist inside Thumb code, are not the entry points for
15756 possible ARM->Thumb calls. Also, these labels can be used
15757 as part of a computed goto or switch statement. eg gcc
15758 can generate code that looks like this:
15760 ldr r2, [pc, .Laaa]
15770 The first instruction loads the address of the jump table.
15771 The second instruction converts a table index into a byte offset.
15772 The third instruction gets the jump address out of the table.
15773 The fourth instruction performs the jump.
15775 If the address stored at .Laaa is that of a symbol which has the
15776 Thumb_Func bit set, then the linker will arrange for this address
15777 to have the bottom bit set, which in turn would mean that the
15778 address computation performed by the third instruction would end
15779 up with the bottom bit set. Since the ARM is capable of unaligned
15780 word loads, the instruction would then load the incorrect address
15781 out of the jump table, and chaos would ensue. */
15782 if (label_is_thumb_function_name
15783 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
15784 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
15786 /* When the address of a Thumb function is taken the bottom
15787 bit of that address should be set. This will allow
15788 interworking between Arm and Thumb functions to work
15791 THUMB_SET_FUNC (sym
, 1);
15793 label_is_thumb_function_name
= FALSE
;
15796 dwarf2_emit_label (sym
);
15800 arm_data_in_code (void)
15802 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
15804 *input_line_pointer
= '/';
15805 input_line_pointer
+= 5;
15806 *input_line_pointer
= 0;
15814 arm_canonicalize_symbol_name (char * name
)
15818 if (thumb_mode
&& (len
= strlen (name
)) > 5
15819 && streq (name
+ len
- 5, "/data"))
15820 *(name
+ len
- 5) = 0;
15825 /* Table of all register names defined by default. The user can
15826 define additional names with .req. Note that all register names
15827 should appear in both upper and lowercase variants. Some registers
15828 also have mixed-case names. */
15830 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
15831 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
15832 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
15833 #define REGSET(p,t) \
15834 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
15835 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
15836 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
15837 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
15838 #define REGSETH(p,t) \
15839 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
15840 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
15841 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
15842 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
15843 #define REGSET2(p,t) \
15844 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
15845 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
15846 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
15847 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
15849 static const struct reg_entry reg_names
[] =
15851 /* ARM integer registers. */
15852 REGSET(r
, RN
), REGSET(R
, RN
),
15854 /* ATPCS synonyms. */
15855 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
15856 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
15857 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
15859 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
15860 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
15861 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
15863 /* Well-known aliases. */
15864 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
15865 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
15867 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
15868 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
15870 /* Coprocessor numbers. */
15871 REGSET(p
, CP
), REGSET(P
, CP
),
15873 /* Coprocessor register numbers. The "cr" variants are for backward
15875 REGSET(c
, CN
), REGSET(C
, CN
),
15876 REGSET(cr
, CN
), REGSET(CR
, CN
),
15878 /* FPA registers. */
15879 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
15880 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
15882 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
15883 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
15885 /* VFP SP registers. */
15886 REGSET(s
,VFS
), REGSET(S
,VFS
),
15887 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
15889 /* VFP DP Registers. */
15890 REGSET(d
,VFD
), REGSET(D
,VFD
),
15891 /* Extra Neon DP registers. */
15892 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
15894 /* Neon QP registers. */
15895 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
15897 /* VFP control registers. */
15898 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
15899 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
15900 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
15901 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
15902 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
15903 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
15905 /* Maverick DSP coprocessor registers. */
15906 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
15907 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
15909 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
15910 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
15911 REGDEF(dspsc
,0,DSPSC
),
15913 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
15914 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
15915 REGDEF(DSPSC
,0,DSPSC
),
15917 /* iWMMXt data registers - p0, c0-15. */
15918 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
15920 /* iWMMXt control registers - p1, c0-3. */
15921 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
15922 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
15923 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
15924 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
15926 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
15927 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
15928 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
15929 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
15930 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
15932 /* XScale accumulator registers. */
15933 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
15939 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
15940 within psr_required_here. */
15941 static const struct asm_psr psrs
[] =
15943 /* Backward compatibility notation. Note that "all" is no longer
15944 truly all possible PSR bits. */
15945 {"all", PSR_c
| PSR_f
},
15949 /* Individual flags. */
15954 /* Combinations of flags. */
15955 {"fs", PSR_f
| PSR_s
},
15956 {"fx", PSR_f
| PSR_x
},
15957 {"fc", PSR_f
| PSR_c
},
15958 {"sf", PSR_s
| PSR_f
},
15959 {"sx", PSR_s
| PSR_x
},
15960 {"sc", PSR_s
| PSR_c
},
15961 {"xf", PSR_x
| PSR_f
},
15962 {"xs", PSR_x
| PSR_s
},
15963 {"xc", PSR_x
| PSR_c
},
15964 {"cf", PSR_c
| PSR_f
},
15965 {"cs", PSR_c
| PSR_s
},
15966 {"cx", PSR_c
| PSR_x
},
15967 {"fsx", PSR_f
| PSR_s
| PSR_x
},
15968 {"fsc", PSR_f
| PSR_s
| PSR_c
},
15969 {"fxs", PSR_f
| PSR_x
| PSR_s
},
15970 {"fxc", PSR_f
| PSR_x
| PSR_c
},
15971 {"fcs", PSR_f
| PSR_c
| PSR_s
},
15972 {"fcx", PSR_f
| PSR_c
| PSR_x
},
15973 {"sfx", PSR_s
| PSR_f
| PSR_x
},
15974 {"sfc", PSR_s
| PSR_f
| PSR_c
},
15975 {"sxf", PSR_s
| PSR_x
| PSR_f
},
15976 {"sxc", PSR_s
| PSR_x
| PSR_c
},
15977 {"scf", PSR_s
| PSR_c
| PSR_f
},
15978 {"scx", PSR_s
| PSR_c
| PSR_x
},
15979 {"xfs", PSR_x
| PSR_f
| PSR_s
},
15980 {"xfc", PSR_x
| PSR_f
| PSR_c
},
15981 {"xsf", PSR_x
| PSR_s
| PSR_f
},
15982 {"xsc", PSR_x
| PSR_s
| PSR_c
},
15983 {"xcf", PSR_x
| PSR_c
| PSR_f
},
15984 {"xcs", PSR_x
| PSR_c
| PSR_s
},
15985 {"cfs", PSR_c
| PSR_f
| PSR_s
},
15986 {"cfx", PSR_c
| PSR_f
| PSR_x
},
15987 {"csf", PSR_c
| PSR_s
| PSR_f
},
15988 {"csx", PSR_c
| PSR_s
| PSR_x
},
15989 {"cxf", PSR_c
| PSR_x
| PSR_f
},
15990 {"cxs", PSR_c
| PSR_x
| PSR_s
},
15991 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
15992 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
15993 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
15994 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
15995 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
15996 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
15997 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
15998 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
15999 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
16000 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
16001 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
16002 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
16003 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
16004 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
16005 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
16006 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
16007 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
16008 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
16009 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
16010 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
16011 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
16012 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
16013 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
16014 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
16017 /* Table of V7M psr names. */
16018 static const struct asm_psr v7m_psrs
[] =
16020 {"apsr", 0 }, {"APSR", 0 },
16021 {"iapsr", 1 }, {"IAPSR", 1 },
16022 {"eapsr", 2 }, {"EAPSR", 2 },
16023 {"psr", 3 }, {"PSR", 3 },
16024 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16025 {"ipsr", 5 }, {"IPSR", 5 },
16026 {"epsr", 6 }, {"EPSR", 6 },
16027 {"iepsr", 7 }, {"IEPSR", 7 },
16028 {"msp", 8 }, {"MSP", 8 },
16029 {"psp", 9 }, {"PSP", 9 },
16030 {"primask", 16}, {"PRIMASK", 16},
16031 {"basepri", 17}, {"BASEPRI", 17},
16032 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16033 {"faultmask", 19}, {"FAULTMASK", 19},
16034 {"control", 20}, {"CONTROL", 20}
16037 /* Table of all shift-in-operand names. */
16038 static const struct asm_shift_name shift_names
[] =
16040 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
16041 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
16042 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
16043 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
16044 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
16045 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
16048 /* Table of all explicit relocation names. */
16050 static struct reloc_entry reloc_names
[] =
16052 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
16053 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
16054 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
16055 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
16056 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
16057 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
16058 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
16059 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
16060 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
16061 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
16062 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
16066 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16067 static const struct asm_cond conds
[] =
16071 {"cs", 0x2}, {"hs", 0x2},
16072 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16086 static struct asm_barrier_opt barrier_opt_names
[] =
16094 /* Table of ARM-format instructions. */
16096 /* Macros for gluing together operand strings. N.B. In all cases
16097 other than OPS0, the trailing OP_stop comes from default
16098 zero-initialization of the unspecified elements of the array. */
16099 #define OPS0() { OP_stop, }
16100 #define OPS1(a) { OP_##a, }
16101 #define OPS2(a,b) { OP_##a,OP_##b, }
16102 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16103 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16104 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16105 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16107 /* These macros abstract out the exact format of the mnemonic table and
16108 save some repeated characters. */
16110 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16111 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16112 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16113 THUMB_VARIANT, do_##ae, do_##te }
16115 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16116 a T_MNEM_xyz enumerator. */
16117 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16118 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16119 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16120 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16122 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16123 infix after the third character. */
16124 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16125 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16126 THUMB_VARIANT, do_##ae, do_##te }
16127 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16128 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16129 THUMB_VARIANT, do_##ae, do_##te }
16130 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16131 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16132 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16133 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16134 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16135 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16136 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16137 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16139 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16140 appear in the condition table. */
16141 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16142 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16143 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16145 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16146 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16147 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16148 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16149 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16150 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16151 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16152 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16153 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16154 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16155 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16156 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16157 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16158 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16159 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16160 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16161 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16162 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16163 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16164 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16166 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16167 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16168 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16169 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16171 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16172 field is still 0xE. Many of the Thumb variants can be executed
16173 conditionally, so this is checked separately. */
16174 #define TUE(mnem, op, top, nops, ops, ae, te) \
16175 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16176 THUMB_VARIANT, do_##ae, do_##te }
16178 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16179 condition code field. */
16180 #define TUF(mnem, op, top, nops, ops, ae, te) \
16181 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16182 THUMB_VARIANT, do_##ae, do_##te }
16184 /* ARM-only variants of all the above. */
16185 #define CE(mnem, op, nops, ops, ae) \
16186 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16188 #define C3(mnem, op, nops, ops, ae) \
16189 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16191 /* Legacy mnemonics that always have conditional infix after the third
16193 #define CL(mnem, op, nops, ops, ae) \
16194 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16195 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16197 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16198 #define cCE(mnem, op, nops, ops, ae) \
16199 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16201 /* Legacy coprocessor instructions where conditional infix and conditional
16202 suffix are ambiguous. For consistency this includes all FPA instructions,
16203 not just the potentially ambiguous ones. */
16204 #define cCL(mnem, op, nops, ops, ae) \
16205 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16206 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16208 /* Coprocessor, takes either a suffix or a position-3 infix
16209 (for an FPA corner case). */
16210 #define C3E(mnem, op, nops, ops, ae) \
16211 { mnem, OPS##nops ops, OT_csuf_or_in3, \
16212 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16214 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
16215 { m1 #m2 m3, OPS##nops ops, \
16216 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16217 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16219 #define CM(m1, m2, op, nops, ops, ae) \
16220 xCM_ (m1, , m2, op, nops, ops, ae), \
16221 xCM_ (m1, eq, m2, op, nops, ops, ae), \
16222 xCM_ (m1, ne, m2, op, nops, ops, ae), \
16223 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16224 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16225 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16226 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16227 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16228 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16229 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16230 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16231 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16232 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16233 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16234 xCM_ (m1, ge, m2, op, nops, ops, ae), \
16235 xCM_ (m1, lt, m2, op, nops, ops, ae), \
16236 xCM_ (m1, gt, m2, op, nops, ops, ae), \
16237 xCM_ (m1, le, m2, op, nops, ops, ae), \
16238 xCM_ (m1, al, m2, op, nops, ops, ae)
16240 #define UE(mnem, op, nops, ops, ae) \
16241 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16243 #define UF(mnem, op, nops, ops, ae) \
16244 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16246 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
16247 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
16248 use the same encoding function for each. */
16249 #define NUF(mnem, op, nops, ops, enc) \
16250 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
16251 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16253 /* Neon data processing, version which indirects through neon_enc_tab for
16254 the various overloaded versions of opcodes. */
16255 #define nUF(mnem, op, nops, ops, enc) \
16256 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
16257 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16259 /* Neon insn with conditional suffix for the ARM version, non-overloaded
16261 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
16262 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
16263 THUMB_VARIANT, do_##enc, do_##enc }
16265 #define NCE(mnem, op, nops, ops, enc) \
16266 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16268 #define NCEF(mnem, op, nops, ops, enc) \
16269 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16271 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
16272 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
16273 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
16274 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16276 #define nCE(mnem, op, nops, ops, enc) \
16277 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16279 #define nCEF(mnem, op, nops, ops, enc) \
16280 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16284 /* Thumb-only, unconditional. */
16285 #define UT(mnem, op, nops, ops, te) TUE (mnem, 0, op, nops, ops, 0, te)
16287 static const struct asm_opcode insns
[] =
16289 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
16290 #define THUMB_VARIANT &arm_ext_v4t
16291 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16292 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16293 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16294 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16295 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16296 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16297 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16298 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16299 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16300 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16301 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16302 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16303 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16304 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16305 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16306 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16308 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
16309 for setting PSR flag bits. They are obsolete in V6 and do not
16310 have Thumb equivalents. */
16311 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16312 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16313 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
16314 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16315 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16316 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
16317 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16318 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16319 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
16321 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16322 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16323 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16324 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16326 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16327 tC3("ldrb", 4500000, _ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16328 tCE("str", 4000000, _str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16329 tC3("strb", 4400000, _strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16331 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16332 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16333 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16334 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16335 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16336 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16338 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16339 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16340 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
16341 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
16344 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
16345 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
16346 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
16348 /* Thumb-compatibility pseudo ops. */
16349 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16350 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16351 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16352 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16353 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16354 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16355 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16356 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16357 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
16358 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
16359 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
16360 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
16362 /* These may simplify to neg. */
16363 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16364 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16366 #undef THUMB_VARIANT
16367 #define THUMB_VARIANT & arm_ext_v6
16369 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
16371 /* V1 instructions with no Thumb analogue prior to V6T2. */
16372 #undef THUMB_VARIANT
16373 #define THUMB_VARIANT & arm_ext_v6t2
16375 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16376 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16377 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
16379 TC3("ldrt", 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16380 TC3("ldrbt", 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16381 TC3("strt", 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16382 TC3("strbt", 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16384 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16385 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16387 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16388 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16390 /* V1 instructions with no Thumb analogue at all. */
16391 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
16392 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
16394 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16395 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16396 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16397 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16398 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16399 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16400 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16401 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16404 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
16405 #undef THUMB_VARIANT
16406 #define THUMB_VARIANT & arm_ext_v4t
16408 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16409 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16411 #undef THUMB_VARIANT
16412 #define THUMB_VARIANT & arm_ext_v6t2
16414 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16415 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
16417 /* Generic coprocessor instructions. */
16418 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16419 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16420 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16421 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16422 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16423 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16424 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16427 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
16429 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16430 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16433 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
16434 #undef THUMB_VARIANT
16435 #define THUMB_VARIANT & arm_ext_msr
16437 TCE("mrs", 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
16438 TCE("msr", 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
16441 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
16442 #undef THUMB_VARIANT
16443 #define THUMB_VARIANT & arm_ext_v6t2
16445 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16446 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16447 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16448 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16449 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16450 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16451 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16452 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16455 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
16456 #undef THUMB_VARIANT
16457 #define THUMB_VARIANT & arm_ext_v4t
16459 tC3("ldrh", 01000b0
, _ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16460 tC3("strh", 00000b0
, _strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16461 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16462 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16463 tCM("ld","sh", 01000f0
, _ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16464 tCM("ld","sb", 01000d0
, _ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16467 #define ARM_VARIANT & arm_ext_v4t_5
16469 /* ARM Architecture 4T. */
16470 /* Note: bx (and blx) are required on V5, even if the processor does
16471 not support Thumb. */
16472 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
16475 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
16476 #undef THUMB_VARIANT
16477 #define THUMB_VARIANT & arm_ext_v5t
16479 /* Note: blx has 2 variants; the .value coded here is for
16480 BLX(2). Only this variant has conditional execution. */
16481 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
16482 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
16484 #undef THUMB_VARIANT
16485 #define THUMB_VARIANT & arm_ext_v6t2
16487 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
16488 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16489 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16490 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16491 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16492 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16493 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16494 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16497 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
16498 #undef THUMB_VARIANT
16499 #define THUMB_VARIANT &arm_ext_v5exp
16501 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16502 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16503 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16504 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16506 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16507 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16509 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16510 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16511 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16512 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16514 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16515 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16516 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16517 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16519 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16520 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16522 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16523 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16524 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16525 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16528 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
16529 #undef THUMB_VARIANT
16530 #define THUMB_VARIANT &arm_ext_v6t2
16532 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
16533 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
16534 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
16536 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16537 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16540 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
16542 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
16545 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
16546 #undef THUMB_VARIANT
16547 #define THUMB_VARIANT & arm_ext_v6
16549 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16550 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16551 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16552 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16553 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16554 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16555 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16556 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16557 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16558 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
16560 #undef THUMB_VARIANT
16561 #define THUMB_VARIANT & arm_ext_v6t2
16563 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
16564 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
16565 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16566 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16568 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
16569 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
16571 /* ARM V6 not included in V7M. */
16572 #undef THUMB_VARIANT
16573 #define THUMB_VARIANT & arm_ext_v6_notm
16574 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16575 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
16576 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
16577 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16578 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16579 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
16580 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
16581 TUF("rfeed", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16582 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
16583 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
16584 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
16585 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
16587 /* ARM V6 not included in V7M (eg. integer SIMD). */
16588 #undef THUMB_VARIANT
16589 #define THUMB_VARIANT & arm_ext_v6_dsp
16590 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
16591 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
16592 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
16593 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16594 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16595 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16596 /* Old name for QASX. */
16597 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16598 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16599 /* Old name for QSAX. */
16600 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16601 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16602 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16603 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16604 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16605 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16606 /* Old name for SASX. */
16607 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16608 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16609 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16610 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16611 /* Old name for SHASX. */
16612 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16613 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16614 /* Old name for SHSAX. */
16615 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16616 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16617 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16618 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16619 /* Old name for SSAX. */
16620 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16621 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16622 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16623 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16624 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16625 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16626 /* Old name for UASX. */
16627 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16628 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16629 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16630 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16631 /* Old name for UHASX. */
16632 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16633 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16634 /* Old name for UHSAX. */
16635 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16636 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16637 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16638 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16639 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16640 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16641 /* Old name for UQASX. */
16642 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16643 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16644 /* Old name for UQSAX. */
16645 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16646 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16647 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16648 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16649 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16650 /* Old name for USAX. */
16651 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16652 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16653 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16654 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16655 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16656 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16657 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16658 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16659 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16660 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16661 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16662 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16663 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16664 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16665 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16666 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16667 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16668 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16669 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16670 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16671 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16672 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16673 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16674 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16675 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16676 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16677 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16678 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16679 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16680 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
16681 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
16682 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16683 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16684 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
16687 #define ARM_VARIANT & arm_ext_v6k
16688 #undef THUMB_VARIANT
16689 #define THUMB_VARIANT & arm_ext_v6k
16691 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
16692 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
16693 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
16694 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
16696 #undef THUMB_VARIANT
16697 #define THUMB_VARIANT & arm_ext_v6_notm
16699 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
16700 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
16702 #undef THUMB_VARIANT
16703 #define THUMB_VARIANT & arm_ext_v6t2
16705 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
16706 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
16707 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
16708 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
16709 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
16712 #define ARM_VARIANT & arm_ext_v6z
16714 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
16717 #define ARM_VARIANT & arm_ext_v6t2
16719 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
16720 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
16721 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
16722 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
16724 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16725 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
16726 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
16727 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
16729 TC3("ldrht", 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16730 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16731 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16732 TC3("strht", 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16734 UT("cbnz", b900
, 2, (RR
, EXP
), t_cbz
),
16735 UT("cbz", b100
, 2, (RR
, EXP
), t_cbz
),
16737 /* ARM does not really have an IT instruction, so always allow it.
16738 The opcode is copied from Thumb in order to allow warnings in
16739 -mimplicit-it=[never | arm] modes. */
16741 #define ARM_VARIANT & arm_ext_v1
16743 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
16744 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
16745 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
16746 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
16747 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
16748 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
16749 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
16750 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
16751 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
16752 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
16753 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
16754 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
16755 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
16756 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
16757 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
16758 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
16759 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
16760 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
16762 /* Thumb2 only instructions. */
16764 #define ARM_VARIANT NULL
16766 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
16767 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
16768 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
16769 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
16770 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
16771 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
16773 /* Thumb-2 hardware division instructions (R and M profiles only). */
16774 #undef THUMB_VARIANT
16775 #define THUMB_VARIANT & arm_ext_div
16777 TCE("sdiv", 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
16778 TCE("udiv", 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
16780 /* ARM V6M/V7 instructions. */
16782 #define ARM_VARIANT & arm_ext_barrier
16783 #undef THUMB_VARIANT
16784 #define THUMB_VARIANT & arm_ext_barrier
16786 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
16787 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
16788 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
16790 /* ARM V7 instructions. */
16792 #define ARM_VARIANT & arm_ext_v7
16793 #undef THUMB_VARIANT
16794 #define THUMB_VARIANT & arm_ext_v7
16796 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
16797 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
16800 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
16802 cCE("wfs", e200110
, 1, (RR
), rd
),
16803 cCE("rfs", e300110
, 1, (RR
), rd
),
16804 cCE("wfc", e400110
, 1, (RR
), rd
),
16805 cCE("rfc", e500110
, 1, (RR
), rd
),
16807 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16808 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16809 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16810 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16812 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16813 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16814 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16815 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16817 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
16818 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
16819 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
16820 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
16821 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
16822 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
16823 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
16824 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
16825 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
16826 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
16827 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
16828 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
16830 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
16831 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
16832 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
16833 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
16834 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
16835 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
16836 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
16837 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
16838 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
16839 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
16840 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
16841 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
16843 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
16844 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
16845 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
16846 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
16847 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
16848 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
16849 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
16850 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
16851 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
16852 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
16853 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
16854 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
16856 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
16857 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
16858 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
16859 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
16860 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
16861 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
16862 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
16863 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
16864 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
16865 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
16866 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
16867 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
16869 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
16870 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
16871 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
16872 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
16873 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
16874 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
16875 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
16876 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
16877 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
16878 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
16879 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
16880 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
16882 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
16883 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
16884 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
16885 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
16886 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
16887 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
16888 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
16889 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
16890 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
16891 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
16892 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
16893 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
16895 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
16896 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
16897 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
16898 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
16899 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
16900 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
16901 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
16902 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
16903 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
16904 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
16905 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
16906 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
16908 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
16909 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
16910 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
16911 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
16912 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
16913 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
16914 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
16915 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
16916 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
16917 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
16918 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
16919 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
16921 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
16922 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
16923 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
16924 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
16925 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
16926 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
16927 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
16928 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
16929 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
16930 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
16931 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
16932 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
16934 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
16935 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
16936 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
16937 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
16938 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
16939 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
16940 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
16941 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
16942 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
16943 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
16944 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
16945 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
16947 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
16948 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
16949 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
16950 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
16951 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
16952 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
16953 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
16954 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
16955 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
16956 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
16957 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
16958 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
16960 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
16961 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
16962 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
16963 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
16964 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
16965 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
16966 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
16967 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
16968 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
16969 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
16970 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
16971 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
16973 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
16974 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
16975 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
16976 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
16977 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
16978 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
16979 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
16980 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
16981 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
16982 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
16983 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
16984 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
16986 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
16987 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
16988 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
16989 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
16990 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
16991 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
16992 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
16993 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
16994 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
16995 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
16996 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
16997 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
16999 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
17000 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
17001 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
17002 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
17003 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
17004 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
17005 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
17006 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
17007 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
17008 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
17009 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
17010 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
17012 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
17013 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
17014 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
17015 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
17016 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
17017 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
17018 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
17019 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
17020 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
17021 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
17022 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
17023 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
17025 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17026 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17027 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17028 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17029 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17030 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17031 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17032 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17033 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17034 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17035 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17036 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17038 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17039 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17040 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17041 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17042 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17043 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17044 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17045 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17046 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17047 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17048 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17049 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17051 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17052 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17053 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17054 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17055 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17056 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17057 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17058 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17059 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17060 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17061 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17062 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17064 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17065 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17066 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17067 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17068 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17069 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17070 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17071 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17072 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17073 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17074 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17075 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17077 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17078 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17079 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17080 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17081 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17082 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17083 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17084 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17085 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17086 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17087 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17088 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17090 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17091 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17092 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17093 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17094 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17095 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17096 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17097 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17098 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17099 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17100 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17101 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17103 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17104 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17105 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17106 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17107 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17108 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17109 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17110 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17111 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17112 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17113 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17114 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17116 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17117 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17118 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17119 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17120 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17121 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17122 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17123 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17124 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17125 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17126 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17127 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17129 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17130 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17131 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17132 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17133 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17134 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17135 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17136 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17137 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17138 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17139 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17140 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17142 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17143 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17144 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17145 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17146 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17147 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17148 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17149 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17150 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17151 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17152 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17153 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17155 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17156 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17157 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17158 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17159 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17160 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17161 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17162 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17163 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17164 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17165 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17166 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17168 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17169 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17170 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17171 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17172 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17173 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17174 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17175 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17176 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17177 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17178 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17179 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17181 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17182 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17183 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17184 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17185 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17186 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17187 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17188 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17189 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17190 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17191 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17192 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17194 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17195 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17196 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17197 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17199 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
17200 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
17201 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
17202 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
17203 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
17204 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
17205 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
17206 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
17207 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
17208 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
17209 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
17210 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
17212 /* The implementation of the FIX instruction is broken on some
17213 assemblers, in that it accepts a precision specifier as well as a
17214 rounding specifier, despite the fact that this is meaningless.
17215 To be more compatible, we accept it as well, though of course it
17216 does not set any bits. */
17217 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
17218 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
17219 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
17220 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
17221 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
17222 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
17223 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
17224 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
17225 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
17226 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
17227 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
17228 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
17229 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
17231 /* Instructions that were new with the real FPA, call them V2. */
17233 #define ARM_VARIANT & fpu_fpa_ext_v2
17235 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17236 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17237 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17238 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17239 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17240 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17243 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
17245 /* Moves and type conversions. */
17246 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17247 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
17248 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
17249 cCE("fmstat", ef1fa10
, 0, (), noargs
),
17250 cCE("vmrs", ef10a10
, 2, (APSR_RR
, RVC
), vmrs
),
17251 cCE("vmsr", ee10a10
, 2, (RVC
, RR
), vmsr
),
17252 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17253 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17254 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17255 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17256 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17257 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17258 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
17259 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
17261 /* Memory operations. */
17262 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17263 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17264 cCE("fldmias", c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17265 cCE("fldmfds", c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17266 cCE("fldmdbs", d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17267 cCE("fldmeas", d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17268 cCE("fldmiax", c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17269 cCE("fldmfdx", c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17270 cCE("fldmdbx", d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17271 cCE("fldmeax", d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17272 cCE("fstmias", c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17273 cCE("fstmeas", c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17274 cCE("fstmdbs", d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17275 cCE("fstmfds", d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17276 cCE("fstmiax", c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17277 cCE("fstmeax", c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17278 cCE("fstmdbx", d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17279 cCE("fstmfdx", d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17281 /* Monadic operations. */
17282 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17283 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17284 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17286 /* Dyadic operations. */
17287 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17288 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17289 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17290 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17291 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17292 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17293 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17294 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17295 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17298 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17299 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
17300 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17301 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
17303 /* Double precision load/store are still present on single precision
17304 implementations. */
17305 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17306 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17307 cCE("fldmiad", c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17308 cCE("fldmfdd", c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17309 cCE("fldmdbd", d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17310 cCE("fldmead", d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17311 cCE("fstmiad", c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17312 cCE("fstmead", c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17313 cCE("fstmdbd", d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17314 cCE("fstmfdd", d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17317 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
17319 /* Moves and type conversions. */
17320 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17321 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17322 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17323 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17324 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17325 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17326 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17327 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17328 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17329 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17330 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17331 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17332 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17334 /* Monadic operations. */
17335 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17336 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17337 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17339 /* Dyadic operations. */
17340 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17341 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17342 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17343 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17344 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17345 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17346 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17347 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17348 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17351 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17352 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
17353 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17354 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
17357 #define ARM_VARIANT & fpu_vfp_ext_v2
17359 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
17360 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
17361 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
17362 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
17364 /* Instructions which may belong to either the Neon or VFP instruction sets.
17365 Individual encoder functions perform additional architecture checks. */
17367 #define ARM_VARIANT & fpu_vfp_ext_v1xd
17368 #undef THUMB_VARIANT
17369 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
17371 /* These mnemonics are unique to VFP. */
17372 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
17373 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
17374 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17375 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17376 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17377 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17378 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17379 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
17380 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
17381 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
17383 /* Mnemonics shared by Neon and VFP. */
17384 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
17385 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17386 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17388 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17389 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17391 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17392 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17394 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17395 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17396 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17397 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17398 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17399 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17400 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17401 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17403 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
17404 nCEF(vcvtb
, _vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
17405 nCEF(vcvtt
, _vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
17408 /* NOTE: All VMOV encoding is special-cased! */
17409 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
17410 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
17412 #undef THUMB_VARIANT
17413 #define THUMB_VARIANT & fpu_neon_ext_v1
17415 #define ARM_VARIANT & fpu_neon_ext_v1
17417 /* Data processing with three registers of the same length. */
17418 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
17419 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
17420 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
17421 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17422 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17423 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17424 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17425 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17426 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17427 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
17428 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17429 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17430 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17431 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17432 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17433 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17434 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17435 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17436 /* If not immediate, fall back to neon_dyadic_i64_su.
17437 shl_imm should accept I8 I16 I32 I64,
17438 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
17439 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
17440 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
17441 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
17442 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
17443 /* Logic ops, types optional & ignored. */
17444 nUF(vand
, _vand
, 2, (RNDQ
, NILO
), neon_logic
),
17445 nUF(vandq
, _vand
, 2, (RNQ
, NILO
), neon_logic
),
17446 nUF(vbic
, _vbic
, 2, (RNDQ
, NILO
), neon_logic
),
17447 nUF(vbicq
, _vbic
, 2, (RNQ
, NILO
), neon_logic
),
17448 nUF(vorr
, _vorr
, 2, (RNDQ
, NILO
), neon_logic
),
17449 nUF(vorrq
, _vorr
, 2, (RNQ
, NILO
), neon_logic
),
17450 nUF(vorn
, _vorn
, 2, (RNDQ
, NILO
), neon_logic
),
17451 nUF(vornq
, _vorn
, 2, (RNQ
, NILO
), neon_logic
),
17452 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
17453 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
17454 /* Bitfield ops, untyped. */
17455 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17456 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17457 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17458 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17459 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17460 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17461 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
17462 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17463 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17464 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17465 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17466 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17467 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17468 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
17469 back to neon_dyadic_if_su. */
17470 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17471 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17472 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17473 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17474 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17475 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17476 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17477 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17478 /* Comparison. Type I8 I16 I32 F32. */
17479 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
17480 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
17481 /* As above, D registers only. */
17482 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17483 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17484 /* Int and float variants, signedness unimportant. */
17485 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17486 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17487 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
17488 /* Add/sub take types I8 I16 I32 I64 F32. */
17489 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17490 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17491 /* vtst takes sizes 8, 16, 32. */
17492 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
17493 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
17494 /* VMUL takes I8 I16 I32 F32 P8. */
17495 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
17496 /* VQD{R}MULH takes S16 S32. */
17497 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17498 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17499 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17500 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17501 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17502 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17503 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17504 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17505 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17506 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17507 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17508 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17509 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17510 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17511 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17512 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17514 /* Two address, int/float. Types S8 S16 S32 F32. */
17515 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17516 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17518 /* Data processing with two registers and a shift amount. */
17519 /* Right shifts, and variants with rounding.
17520 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
17521 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17522 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17523 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17524 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17525 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17526 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17527 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17528 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17529 /* Shift and insert. Sizes accepted 8 16 32 64. */
17530 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
17531 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
17532 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
17533 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
17534 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
17535 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
17536 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
17537 /* Right shift immediate, saturating & narrowing, with rounding variants.
17538 Types accepted S16 S32 S64 U16 U32 U64. */
17539 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17540 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17541 /* As above, unsigned. Types accepted S16 S32 S64. */
17542 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17543 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17544 /* Right shift narrowing. Types accepted I16 I32 I64. */
17545 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17546 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17547 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
17548 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
17549 /* CVT with optional immediate for fixed-point variant. */
17550 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
17552 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_IMVNb
), neon_mvn
),
17553 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_IMVNb
), neon_mvn
),
17555 /* Data processing, three registers of different lengths. */
17556 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
17557 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
17558 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17559 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17560 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17561 /* If not scalar, fall back to neon_dyadic_long.
17562 Vector types as above, scalar types S16 S32 U16 U32. */
17563 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17564 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17565 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
17566 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17567 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17568 /* Dyadic, narrowing insns. Types I16 I32 I64. */
17569 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17570 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17571 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17572 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17573 /* Saturating doubling multiplies. Types S16 S32. */
17574 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17575 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17576 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17577 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
17578 S16 S32 U16 U32. */
17579 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
17581 /* Extract. Size 8. */
17582 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
17583 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
17585 /* Two registers, miscellaneous. */
17586 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
17587 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
17588 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
17589 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
17590 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
17591 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
17592 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
17593 /* Vector replicate. Sizes 8 16 32. */
17594 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
17595 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
17596 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
17597 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
17598 /* VMOVN. Types I16 I32 I64. */
17599 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
17600 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
17601 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
17602 /* VQMOVUN. Types S16 S32 S64. */
17603 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
17604 /* VZIP / VUZP. Sizes 8 16 32. */
17605 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17606 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17607 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17608 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17609 /* VQABS / VQNEG. Types S8 S16 S32. */
17610 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17611 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17612 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17613 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17614 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
17615 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17616 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
17617 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17618 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
17619 /* Reciprocal estimates. Types U32 F32. */
17620 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17621 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
17622 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17623 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
17624 /* VCLS. Types S8 S16 S32. */
17625 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
17626 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
17627 /* VCLZ. Types I8 I16 I32. */
17628 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
17629 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
17630 /* VCNT. Size 8. */
17631 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
17632 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
17633 /* Two address, untyped. */
17634 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
17635 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
17636 /* VTRN. Sizes 8 16 32. */
17637 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
17638 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
17640 /* Table lookup. Size 8. */
17641 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17642 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17644 #undef THUMB_VARIANT
17645 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
17647 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
17649 /* Neon element/structure load/store. */
17650 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17651 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17652 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17653 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17654 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17655 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17656 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17657 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17659 #undef THUMB_VARIANT
17660 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
17662 #define ARM_VARIANT &fpu_vfp_ext_v3xd
17663 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
17664 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17665 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17666 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17667 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17668 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17669 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17670 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17671 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17673 #undef THUMB_VARIANT
17674 #define THUMB_VARIANT & fpu_vfp_ext_v3
17676 #define ARM_VARIANT & fpu_vfp_ext_v3
17678 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
17679 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17680 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17681 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17682 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17683 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17684 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17685 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17686 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17689 #define ARM_VARIANT &fpu_vfp_ext_fma
17690 #undef THUMB_VARIANT
17691 #define THUMB_VARIANT &fpu_vfp_ext_fma
17692 /* Mnemonics shared by Neon and VFP. These are included in the
17693 VFP FMA variant; NEON and VFP FMA always includes the NEON
17694 FMA instructions. */
17695 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
17696 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
17697 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
17698 the v form should always be used. */
17699 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17700 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17701 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17702 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17703 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17704 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17706 #undef THUMB_VARIANT
17708 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
17710 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17711 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17712 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17713 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17714 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17715 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17716 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
17717 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
17720 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
17722 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
17723 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
17724 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
17725 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
17726 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
17727 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
17728 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
17729 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
17730 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
17731 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17732 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17733 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17734 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17735 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17736 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17737 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17738 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17739 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17740 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
17741 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
17742 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17743 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17744 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17745 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17746 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17747 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17748 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
17749 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
17750 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
17751 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
17752 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
17753 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
17754 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
17755 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
17756 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17757 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17758 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17759 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17760 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17761 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17762 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17763 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17764 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17765 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17766 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17767 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17768 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
17769 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17770 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17771 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17772 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17773 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17774 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17775 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17776 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17777 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17778 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17779 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17780 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17781 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17782 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17783 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17784 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17785 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17786 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17787 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17788 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17789 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17790 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
17791 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
17792 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17793 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17794 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17795 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17796 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17797 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17798 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17799 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17800 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17801 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17802 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17803 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17804 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17805 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17806 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17807 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17808 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17809 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17810 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
17811 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17812 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17813 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17814 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17815 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17816 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17817 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17818 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17819 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17820 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17821 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17822 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17823 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17824 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17825 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17826 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17827 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17828 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17829 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17830 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17831 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17832 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
17833 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17834 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17835 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17836 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17837 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17838 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17839 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17840 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17841 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17842 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17843 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17844 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17845 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17846 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17847 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17848 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17849 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17850 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17851 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17852 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17853 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
17854 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
17855 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17856 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17857 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17858 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17859 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17860 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17861 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17862 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17863 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17864 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17865 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17866 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17867 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17868 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17869 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17870 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17871 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17872 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17873 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17874 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17875 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17876 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17877 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17878 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17879 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17880 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17881 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17882 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17883 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
17886 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
17888 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
17889 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
17890 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
17891 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17892 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17893 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17894 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17895 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17896 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17897 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17898 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17899 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17900 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17901 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17902 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17903 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17904 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17905 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17906 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17907 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17908 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
17909 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17910 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17911 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17912 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17913 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17914 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17915 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17916 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17917 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17918 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17919 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17920 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17921 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17922 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17923 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17924 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17925 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17926 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17927 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17928 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17929 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17930 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17931 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17932 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17933 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17934 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17935 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17936 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17937 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17938 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17939 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17940 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17941 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17942 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17943 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17944 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17947 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
17949 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
17950 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
17951 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
17952 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
17953 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
17954 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
17955 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
17956 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
17957 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
17958 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
17959 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
17960 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
17961 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
17962 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
17963 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
17964 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
17965 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
17966 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
17967 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
17968 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
17969 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
17970 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
17971 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
17972 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
17973 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
17974 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
17975 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
17976 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
17977 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
17978 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
17979 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
17980 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
17981 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
17982 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
17983 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
17984 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
17985 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
17986 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
17987 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
17988 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
17989 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
17990 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
17991 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
17992 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
17993 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
17994 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
17995 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
17996 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
17997 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
17998 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
17999 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
18000 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
18001 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
18002 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
18003 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18004 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18005 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18006 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18007 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18008 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18009 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
18010 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
18011 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
18012 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
18013 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18014 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18015 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18016 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18017 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18018 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18019 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18020 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18021 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18022 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18023 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18024 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18027 #undef THUMB_VARIANT
18054 /* MD interface: bits in the object file. */
18056 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18057 for use in the a.out file, and stores them in the array pointed to by buf.
18058 This knows about the endian-ness of the target machine and does
18059 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18060 2 (short) and 4 (long) Floating numbers are put out as a series of
18061 LITTLENUMS (shorts, here at least). */
18064 md_number_to_chars (char * buf
, valueT val
, int n
)
18066 if (target_big_endian
)
18067 number_to_chars_bigendian (buf
, val
, n
);
18069 number_to_chars_littleendian (buf
, val
, n
);
18073 md_chars_to_number (char * buf
, int n
)
18076 unsigned char * where
= (unsigned char *) buf
;
18078 if (target_big_endian
)
18083 result
|= (*where
++ & 255);
18091 result
|= (where
[n
] & 255);
18098 /* MD interface: Sections. */
18100 /* Estimate the size of a frag before relaxing. Assume everything fits in
18104 md_estimate_size_before_relax (fragS
* fragp
,
18105 segT segtype ATTRIBUTE_UNUSED
)
18111 /* Convert a machine dependent frag. */
18114 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
18116 unsigned long insn
;
18117 unsigned long old_op
;
18125 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18127 old_op
= bfd_get_16(abfd
, buf
);
18128 if (fragp
->fr_symbol
)
18130 exp
.X_op
= O_symbol
;
18131 exp
.X_add_symbol
= fragp
->fr_symbol
;
18135 exp
.X_op
= O_constant
;
18137 exp
.X_add_number
= fragp
->fr_offset
;
18138 opcode
= fragp
->fr_subtype
;
18141 case T_MNEM_ldr_pc
:
18142 case T_MNEM_ldr_pc2
:
18143 case T_MNEM_ldr_sp
:
18144 case T_MNEM_str_sp
:
18151 if (fragp
->fr_var
== 4)
18153 insn
= THUMB_OP32 (opcode
);
18154 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
18156 insn
|= (old_op
& 0x700) << 4;
18160 insn
|= (old_op
& 7) << 12;
18161 insn
|= (old_op
& 0x38) << 13;
18163 insn
|= 0x00000c00;
18164 put_thumb32_insn (buf
, insn
);
18165 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
18169 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
18171 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
18174 if (fragp
->fr_var
== 4)
18176 insn
= THUMB_OP32 (opcode
);
18177 insn
|= (old_op
& 0xf0) << 4;
18178 put_thumb32_insn (buf
, insn
);
18179 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
18183 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18184 exp
.X_add_number
-= 4;
18192 if (fragp
->fr_var
== 4)
18194 int r0off
= (opcode
== T_MNEM_mov
18195 || opcode
== T_MNEM_movs
) ? 0 : 8;
18196 insn
= THUMB_OP32 (opcode
);
18197 insn
= (insn
& 0xe1ffffff) | 0x10000000;
18198 insn
|= (old_op
& 0x700) << r0off
;
18199 put_thumb32_insn (buf
, insn
);
18200 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18204 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
18209 if (fragp
->fr_var
== 4)
18211 insn
= THUMB_OP32(opcode
);
18212 put_thumb32_insn (buf
, insn
);
18213 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
18216 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
18220 if (fragp
->fr_var
== 4)
18222 insn
= THUMB_OP32(opcode
);
18223 insn
|= (old_op
& 0xf00) << 14;
18224 put_thumb32_insn (buf
, insn
);
18225 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
18228 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
18231 case T_MNEM_add_sp
:
18232 case T_MNEM_add_pc
:
18233 case T_MNEM_inc_sp
:
18234 case T_MNEM_dec_sp
:
18235 if (fragp
->fr_var
== 4)
18237 /* ??? Choose between add and addw. */
18238 insn
= THUMB_OP32 (opcode
);
18239 insn
|= (old_op
& 0xf0) << 4;
18240 put_thumb32_insn (buf
, insn
);
18241 if (opcode
== T_MNEM_add_pc
)
18242 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
18244 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18247 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18255 if (fragp
->fr_var
== 4)
18257 insn
= THUMB_OP32 (opcode
);
18258 insn
|= (old_op
& 0xf0) << 4;
18259 insn
|= (old_op
& 0xf) << 16;
18260 put_thumb32_insn (buf
, insn
);
18261 if (insn
& (1 << 20))
18262 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18264 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18267 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18273 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
18274 (enum bfd_reloc_code_real
) reloc_type
);
18275 fixp
->fx_file
= fragp
->fr_file
;
18276 fixp
->fx_line
= fragp
->fr_line
;
18277 fragp
->fr_fix
+= fragp
->fr_var
;
18280 /* Return the size of a relaxable immediate operand instruction.
18281 SHIFT and SIZE specify the form of the allowable immediate. */
18283 relax_immediate (fragS
*fragp
, int size
, int shift
)
18289 /* ??? Should be able to do better than this. */
18290 if (fragp
->fr_symbol
)
18293 low
= (1 << shift
) - 1;
18294 mask
= (1 << (shift
+ size
)) - (1 << shift
);
18295 offset
= fragp
->fr_offset
;
18296 /* Force misaligned offsets to 32-bit variant. */
18299 if (offset
& ~mask
)
18304 /* Get the address of a symbol during relaxation. */
18306 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
18312 sym
= fragp
->fr_symbol
;
18313 sym_frag
= symbol_get_frag (sym
);
18314 know (S_GET_SEGMENT (sym
) != absolute_section
18315 || sym_frag
== &zero_address_frag
);
18316 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
18318 /* If frag has yet to be reached on this pass, assume it will
18319 move by STRETCH just as we did. If this is not so, it will
18320 be because some frag between grows, and that will force
18324 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
18328 /* Adjust stretch for any alignment frag. Note that if have
18329 been expanding the earlier code, the symbol may be
18330 defined in what appears to be an earlier frag. FIXME:
18331 This doesn't handle the fr_subtype field, which specifies
18332 a maximum number of bytes to skip when doing an
18334 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
18336 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
18339 stretch
= - ((- stretch
)
18340 & ~ ((1 << (int) f
->fr_offset
) - 1));
18342 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
18354 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
18357 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
18362 /* Assume worst case for symbols not known to be in the same section. */
18363 if (fragp
->fr_symbol
== NULL
18364 || !S_IS_DEFINED (fragp
->fr_symbol
)
18365 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
18368 val
= relaxed_symbol_addr (fragp
, stretch
);
18369 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18370 addr
= (addr
+ 4) & ~3;
18371 /* Force misaligned targets to 32-bit variant. */
18375 if (val
< 0 || val
> 1020)
18380 /* Return the size of a relaxable add/sub immediate instruction. */
18382 relax_addsub (fragS
*fragp
, asection
*sec
)
18387 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18388 op
= bfd_get_16(sec
->owner
, buf
);
18389 if ((op
& 0xf) == ((op
>> 4) & 0xf))
18390 return relax_immediate (fragp
, 8, 0);
18392 return relax_immediate (fragp
, 3, 0);
18396 /* Return the size of a relaxable branch instruction. BITS is the
18397 size of the offset field in the narrow instruction. */
18400 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
18406 /* Assume worst case for symbols not known to be in the same section. */
18407 if (!S_IS_DEFINED (fragp
->fr_symbol
)
18408 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
18412 if (S_IS_DEFINED (fragp
->fr_symbol
)
18413 && ARM_IS_FUNC (fragp
->fr_symbol
))
18417 val
= relaxed_symbol_addr (fragp
, stretch
);
18418 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18421 /* Offset is a signed value *2 */
18423 if (val
>= limit
|| val
< -limit
)
18429 /* Relax a machine dependent frag. This returns the amount by which
18430 the current size of the frag should change. */
18433 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18438 oldsize
= fragp
->fr_var
;
18439 switch (fragp
->fr_subtype
)
18441 case T_MNEM_ldr_pc2
:
18442 newsize
= relax_adr (fragp
, sec
, stretch
);
18444 case T_MNEM_ldr_pc
:
18445 case T_MNEM_ldr_sp
:
18446 case T_MNEM_str_sp
:
18447 newsize
= relax_immediate (fragp
, 8, 2);
18451 newsize
= relax_immediate (fragp
, 5, 2);
18455 newsize
= relax_immediate (fragp
, 5, 1);
18459 newsize
= relax_immediate (fragp
, 5, 0);
18462 newsize
= relax_adr (fragp
, sec
, stretch
);
18468 newsize
= relax_immediate (fragp
, 8, 0);
18471 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
18474 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
18476 case T_MNEM_add_sp
:
18477 case T_MNEM_add_pc
:
18478 newsize
= relax_immediate (fragp
, 8, 2);
18480 case T_MNEM_inc_sp
:
18481 case T_MNEM_dec_sp
:
18482 newsize
= relax_immediate (fragp
, 7, 2);
18488 newsize
= relax_addsub (fragp
, sec
);
18494 fragp
->fr_var
= newsize
;
18495 /* Freeze wide instructions that are at or before the same location as
18496 in the previous pass. This avoids infinite loops.
18497 Don't freeze them unconditionally because targets may be artificially
18498 misaligned by the expansion of preceding frags. */
18499 if (stretch
<= 0 && newsize
> 2)
18501 md_convert_frag (sec
->owner
, sec
, fragp
);
18505 return newsize
- oldsize
;
18508 /* Round up a section size to the appropriate boundary. */
18511 md_section_align (segT segment ATTRIBUTE_UNUSED
,
18514 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
18515 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
18517 /* For a.out, force the section size to be aligned. If we don't do
18518 this, BFD will align it for us, but it will not write out the
18519 final bytes of the section. This may be a bug in BFD, but it is
18520 easier to fix it here since that is how the other a.out targets
18524 align
= bfd_get_section_alignment (stdoutput
, segment
);
18525 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
18532 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
18533 of an rs_align_code fragment. */
18536 arm_handle_align (fragS
* fragP
)
18538 static char const arm_noop
[2][2][4] =
18541 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
18542 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
18545 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
18546 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
18549 static char const thumb_noop
[2][2][2] =
18552 {0xc0, 0x46}, /* LE */
18553 {0x46, 0xc0}, /* BE */
18556 {0x00, 0xbf}, /* LE */
18557 {0xbf, 0x00} /* BE */
18560 static char const wide_thumb_noop
[2][4] =
18561 { /* Wide Thumb-2 */
18562 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
18563 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
18566 unsigned bytes
, fix
, noop_size
;
18569 const char *narrow_noop
= NULL
;
18574 if (fragP
->fr_type
!= rs_align_code
)
18577 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
18578 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
18581 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18582 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
18584 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
18586 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
18588 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
18590 narrow_noop
= thumb_noop
[1][target_big_endian
];
18591 noop
= wide_thumb_noop
[target_big_endian
];
18594 noop
= thumb_noop
[0][target_big_endian
];
18602 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
18603 [target_big_endian
];
18610 fragP
->fr_var
= noop_size
;
18612 if (bytes
& (noop_size
- 1))
18614 fix
= bytes
& (noop_size
- 1);
18616 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
18618 memset (p
, 0, fix
);
18625 if (bytes
& noop_size
)
18627 /* Insert a narrow noop. */
18628 memcpy (p
, narrow_noop
, noop_size
);
18630 bytes
-= noop_size
;
18634 /* Use wide noops for the remainder */
18638 while (bytes
>= noop_size
)
18640 memcpy (p
, noop
, noop_size
);
18642 bytes
-= noop_size
;
18646 fragP
->fr_fix
+= fix
;
18649 /* Called from md_do_align. Used to create an alignment
18650 frag in a code section. */
18653 arm_frag_align_code (int n
, int max
)
18657 /* We assume that there will never be a requirement
18658 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
18659 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18664 _("alignments greater than %d bytes not supported in .text sections."),
18665 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
18666 as_fatal ("%s", err_msg
);
18669 p
= frag_var (rs_align_code
,
18670 MAX_MEM_FOR_RS_ALIGN_CODE
,
18672 (relax_substateT
) max
,
18679 /* Perform target specific initialisation of a frag.
18680 Note - despite the name this initialisation is not done when the frag
18681 is created, but only when its type is assigned. A frag can be created
18682 and used a long time before its type is set, so beware of assuming that
18683 this initialisationis performed first. */
18687 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
18689 /* Record whether this frag is in an ARM or a THUMB area. */
18690 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18693 #else /* OBJ_ELF is defined. */
18695 arm_init_frag (fragS
* fragP
, int max_chars
)
18697 /* If the current ARM vs THUMB mode has not already
18698 been recorded into this frag then do so now. */
18699 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
18701 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18703 /* Record a mapping symbol for alignment frags. We will delete this
18704 later if the alignment ends up empty. */
18705 switch (fragP
->fr_type
)
18708 case rs_align_test
:
18710 mapping_state_2 (MAP_DATA
, max_chars
);
18712 case rs_align_code
:
18713 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
18721 /* When we change sections we need to issue a new mapping symbol. */
18724 arm_elf_change_section (void)
18726 /* Link an unlinked unwind index table section to the .text section. */
18727 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
18728 && elf_linked_to_section (now_seg
) == NULL
)
18729 elf_linked_to_section (now_seg
) = text_section
;
18733 arm_elf_section_type (const char * str
, size_t len
)
18735 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
18736 return SHT_ARM_EXIDX
;
18741 /* Code to deal with unwinding tables. */
18743 static void add_unwind_adjustsp (offsetT
);
18745 /* Generate any deferred unwind frame offset. */
18748 flush_pending_unwind (void)
18752 offset
= unwind
.pending_offset
;
18753 unwind
.pending_offset
= 0;
18755 add_unwind_adjustsp (offset
);
18758 /* Add an opcode to this list for this function. Two-byte opcodes should
18759 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
18763 add_unwind_opcode (valueT op
, int length
)
18765 /* Add any deferred stack adjustment. */
18766 if (unwind
.pending_offset
)
18767 flush_pending_unwind ();
18769 unwind
.sp_restored
= 0;
18771 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
18773 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
18774 if (unwind
.opcodes
)
18775 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
18776 unwind
.opcode_alloc
);
18778 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
18783 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
18785 unwind
.opcode_count
++;
18789 /* Add unwind opcodes to adjust the stack pointer. */
18792 add_unwind_adjustsp (offsetT offset
)
18796 if (offset
> 0x200)
18798 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
18803 /* Long form: 0xb2, uleb128. */
18804 /* This might not fit in a word so add the individual bytes,
18805 remembering the list is built in reverse order. */
18806 o
= (valueT
) ((offset
- 0x204) >> 2);
18808 add_unwind_opcode (0, 1);
18810 /* Calculate the uleb128 encoding of the offset. */
18814 bytes
[n
] = o
& 0x7f;
18820 /* Add the insn. */
18822 add_unwind_opcode (bytes
[n
- 1], 1);
18823 add_unwind_opcode (0xb2, 1);
18825 else if (offset
> 0x100)
18827 /* Two short opcodes. */
18828 add_unwind_opcode (0x3f, 1);
18829 op
= (offset
- 0x104) >> 2;
18830 add_unwind_opcode (op
, 1);
18832 else if (offset
> 0)
18834 /* Short opcode. */
18835 op
= (offset
- 4) >> 2;
18836 add_unwind_opcode (op
, 1);
18838 else if (offset
< 0)
18841 while (offset
> 0x100)
18843 add_unwind_opcode (0x7f, 1);
18846 op
= ((offset
- 4) >> 2) | 0x40;
18847 add_unwind_opcode (op
, 1);
18851 /* Finish the list of unwind opcodes for this function. */
18853 finish_unwind_opcodes (void)
18857 if (unwind
.fp_used
)
18859 /* Adjust sp as necessary. */
18860 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
18861 flush_pending_unwind ();
18863 /* After restoring sp from the frame pointer. */
18864 op
= 0x90 | unwind
.fp_reg
;
18865 add_unwind_opcode (op
, 1);
18868 flush_pending_unwind ();
18872 /* Start an exception table entry. If idx is nonzero this is an index table
18876 start_unwind_section (const segT text_seg
, int idx
)
18878 const char * text_name
;
18879 const char * prefix
;
18880 const char * prefix_once
;
18881 const char * group_name
;
18885 size_t sec_name_len
;
18892 prefix
= ELF_STRING_ARM_unwind
;
18893 prefix_once
= ELF_STRING_ARM_unwind_once
;
18894 type
= SHT_ARM_EXIDX
;
18898 prefix
= ELF_STRING_ARM_unwind_info
;
18899 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
18900 type
= SHT_PROGBITS
;
18903 text_name
= segment_name (text_seg
);
18904 if (streq (text_name
, ".text"))
18907 if (strncmp (text_name
, ".gnu.linkonce.t.",
18908 strlen (".gnu.linkonce.t.")) == 0)
18910 prefix
= prefix_once
;
18911 text_name
+= strlen (".gnu.linkonce.t.");
18914 prefix_len
= strlen (prefix
);
18915 text_len
= strlen (text_name
);
18916 sec_name_len
= prefix_len
+ text_len
;
18917 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
18918 memcpy (sec_name
, prefix
, prefix_len
);
18919 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
18920 sec_name
[prefix_len
+ text_len
] = '\0';
18926 /* Handle COMDAT group. */
18927 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
18929 group_name
= elf_group_name (text_seg
);
18930 if (group_name
== NULL
)
18932 as_bad (_("Group section `%s' has no group signature"),
18933 segment_name (text_seg
));
18934 ignore_rest_of_line ();
18937 flags
|= SHF_GROUP
;
18941 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
18943 /* Set the section link for index tables. */
18945 elf_linked_to_section (now_seg
) = text_seg
;
18949 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
18950 personality routine data. Returns zero, or the index table value for
18951 and inline entry. */
18954 create_unwind_entry (int have_data
)
18959 /* The current word of data. */
18961 /* The number of bytes left in this word. */
18964 finish_unwind_opcodes ();
18966 /* Remember the current text section. */
18967 unwind
.saved_seg
= now_seg
;
18968 unwind
.saved_subseg
= now_subseg
;
18970 start_unwind_section (now_seg
, 0);
18972 if (unwind
.personality_routine
== NULL
)
18974 if (unwind
.personality_index
== -2)
18977 as_bad (_("handlerdata in cantunwind frame"));
18978 return 1; /* EXIDX_CANTUNWIND. */
18981 /* Use a default personality routine if none is specified. */
18982 if (unwind
.personality_index
== -1)
18984 if (unwind
.opcode_count
> 3)
18985 unwind
.personality_index
= 1;
18987 unwind
.personality_index
= 0;
18990 /* Space for the personality routine entry. */
18991 if (unwind
.personality_index
== 0)
18993 if (unwind
.opcode_count
> 3)
18994 as_bad (_("too many unwind opcodes for personality routine 0"));
18998 /* All the data is inline in the index table. */
19001 while (unwind
.opcode_count
> 0)
19003 unwind
.opcode_count
--;
19004 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19008 /* Pad with "finish" opcodes. */
19010 data
= (data
<< 8) | 0xb0;
19017 /* We get two opcodes "free" in the first word. */
19018 size
= unwind
.opcode_count
- 2;
19021 /* An extra byte is required for the opcode count. */
19022 size
= unwind
.opcode_count
+ 1;
19024 size
= (size
+ 3) >> 2;
19026 as_bad (_("too many unwind opcodes"));
19028 frag_align (2, 0, 0);
19029 record_alignment (now_seg
, 2);
19030 unwind
.table_entry
= expr_build_dot ();
19032 /* Allocate the table entry. */
19033 ptr
= frag_more ((size
<< 2) + 4);
19034 where
= frag_now_fix () - ((size
<< 2) + 4);
19036 switch (unwind
.personality_index
)
19039 /* ??? Should this be a PLT generating relocation? */
19040 /* Custom personality routine. */
19041 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
19042 BFD_RELOC_ARM_PREL31
);
19047 /* Set the first byte to the number of additional words. */
19052 /* ABI defined personality routines. */
19054 /* Three opcodes bytes are packed into the first word. */
19061 /* The size and first two opcode bytes go in the first word. */
19062 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
19067 /* Should never happen. */
19071 /* Pack the opcodes into words (MSB first), reversing the list at the same
19073 while (unwind
.opcode_count
> 0)
19077 md_number_to_chars (ptr
, data
, 4);
19082 unwind
.opcode_count
--;
19084 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19087 /* Finish off the last word. */
19090 /* Pad with "finish" opcodes. */
19092 data
= (data
<< 8) | 0xb0;
19094 md_number_to_chars (ptr
, data
, 4);
19099 /* Add an empty descriptor if there is no user-specified data. */
19100 ptr
= frag_more (4);
19101 md_number_to_chars (ptr
, 0, 4);
19108 /* Initialize the DWARF-2 unwind information for this procedure. */
19111 tc_arm_frame_initial_instructions (void)
19113 cfi_add_CFA_def_cfa (REG_SP
, 0);
19115 #endif /* OBJ_ELF */
19117 /* Convert REGNAME to a DWARF-2 register number. */
19120 tc_arm_regname_to_dw2regnum (char *regname
)
19122 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
19132 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
19136 exp
.X_op
= O_secrel
;
19137 exp
.X_add_symbol
= symbol
;
19138 exp
.X_add_number
= 0;
19139 emit_expr (&exp
, size
);
19143 /* MD interface: Symbol and relocation handling. */
19145 /* Return the address within the segment that a PC-relative fixup is
19146 relative to. For ARM, PC-relative fixups applied to instructions
19147 are generally relative to the location of the fixup plus 8 bytes.
19148 Thumb branches are offset by 4, and Thumb loads relative to PC
19149 require special handling. */
19152 md_pcrel_from_section (fixS
* fixP
, segT seg
)
19154 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19156 /* If this is pc-relative and we are going to emit a relocation
19157 then we just want to put out any pipeline compensation that the linker
19158 will need. Otherwise we want to use the calculated base.
19159 For WinCE we skip the bias for externals as well, since this
19160 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19162 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19163 || (arm_force_relocation (fixP
)
19165 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19171 switch (fixP
->fx_r_type
)
19173 /* PC relative addressing on the Thumb is slightly odd as the
19174 bottom two bits of the PC are forced to zero for the
19175 calculation. This happens *after* application of the
19176 pipeline offset. However, Thumb adrl already adjusts for
19177 this, so we need not do it again. */
19178 case BFD_RELOC_ARM_THUMB_ADD
:
19181 case BFD_RELOC_ARM_THUMB_OFFSET
:
19182 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19183 case BFD_RELOC_ARM_T32_ADD_PC12
:
19184 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
19185 return (base
+ 4) & ~3;
19187 /* Thumb branches are simply offset by +4. */
19188 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19189 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19190 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19191 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19192 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19195 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19197 && ARM_IS_FUNC (fixP
->fx_addsy
)
19198 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19199 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19202 /* BLX is like branches above, but forces the low two bits of PC to
19204 case BFD_RELOC_THUMB_PCREL_BLX
:
19206 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19207 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19208 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19209 return (base
+ 4) & ~3;
19211 /* ARM mode branches are offset by +8. However, the Windows CE
19212 loader expects the relocation not to take this into account. */
19213 case BFD_RELOC_ARM_PCREL_BLX
:
19215 && ARM_IS_FUNC (fixP
->fx_addsy
)
19216 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19217 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19220 case BFD_RELOC_ARM_PCREL_CALL
:
19222 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19223 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19224 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19227 case BFD_RELOC_ARM_PCREL_BRANCH
:
19228 case BFD_RELOC_ARM_PCREL_JUMP
:
19229 case BFD_RELOC_ARM_PLT32
:
19231 /* When handling fixups immediately, because we have already
19232 discovered the value of a symbol, or the address of the frag involved
19233 we must account for the offset by +8, as the OS loader will never see the reloc.
19234 see fixup_segment() in write.c
19235 The S_IS_EXTERNAL test handles the case of global symbols.
19236 Those need the calculated base, not just the pipe compensation the linker will need. */
19238 && fixP
->fx_addsy
!= NULL
19239 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19240 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
19248 /* ARM mode loads relative to PC are also offset by +8. Unlike
19249 branches, the Windows CE loader *does* expect the relocation
19250 to take this into account. */
19251 case BFD_RELOC_ARM_OFFSET_IMM
:
19252 case BFD_RELOC_ARM_OFFSET_IMM8
:
19253 case BFD_RELOC_ARM_HWLITERAL
:
19254 case BFD_RELOC_ARM_LITERAL
:
19255 case BFD_RELOC_ARM_CP_OFF_IMM
:
19259 /* Other PC-relative relocations are un-offset. */
19265 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
19266 Otherwise we have no need to default values of symbols. */
19269 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
19272 if (name
[0] == '_' && name
[1] == 'G'
19273 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
19277 if (symbol_find (name
))
19278 as_bad (_("GOT already in the symbol table"));
19280 GOT_symbol
= symbol_new (name
, undefined_section
,
19281 (valueT
) 0, & zero_address_frag
);
19291 /* Subroutine of md_apply_fix. Check to see if an immediate can be
19292 computed as two separate immediate values, added together. We
19293 already know that this value cannot be computed by just one ARM
19296 static unsigned int
19297 validate_immediate_twopart (unsigned int val
,
19298 unsigned int * highpart
)
19303 for (i
= 0; i
< 32; i
+= 2)
19304 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
19310 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
19312 else if (a
& 0xff0000)
19314 if (a
& 0xff000000)
19316 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
19320 gas_assert (a
& 0xff000000);
19321 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
19324 return (a
& 0xff) | (i
<< 7);
19331 validate_offset_imm (unsigned int val
, int hwse
)
19333 if ((hwse
&& val
> 255) || val
> 4095)
19338 /* Subroutine of md_apply_fix. Do those data_ops which can take a
19339 negative immediate constant by altering the instruction. A bit of
19344 by inverting the second operand, and
19347 by negating the second operand. */
19350 negate_data_op (unsigned long * instruction
,
19351 unsigned long value
)
19354 unsigned long negated
, inverted
;
19356 negated
= encode_arm_immediate (-value
);
19357 inverted
= encode_arm_immediate (~value
);
19359 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
19362 /* First negates. */
19363 case OPCODE_SUB
: /* ADD <-> SUB */
19364 new_inst
= OPCODE_ADD
;
19369 new_inst
= OPCODE_SUB
;
19373 case OPCODE_CMP
: /* CMP <-> CMN */
19374 new_inst
= OPCODE_CMN
;
19379 new_inst
= OPCODE_CMP
;
19383 /* Now Inverted ops. */
19384 case OPCODE_MOV
: /* MOV <-> MVN */
19385 new_inst
= OPCODE_MVN
;
19390 new_inst
= OPCODE_MOV
;
19394 case OPCODE_AND
: /* AND <-> BIC */
19395 new_inst
= OPCODE_BIC
;
19400 new_inst
= OPCODE_AND
;
19404 case OPCODE_ADC
: /* ADC <-> SBC */
19405 new_inst
= OPCODE_SBC
;
19410 new_inst
= OPCODE_ADC
;
19414 /* We cannot do anything. */
19419 if (value
== (unsigned) FAIL
)
19422 *instruction
&= OPCODE_MASK
;
19423 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
19427 /* Like negate_data_op, but for Thumb-2. */
19429 static unsigned int
19430 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
19434 unsigned int negated
, inverted
;
19436 negated
= encode_thumb32_immediate (-value
);
19437 inverted
= encode_thumb32_immediate (~value
);
19439 rd
= (*instruction
>> 8) & 0xf;
19440 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
19443 /* ADD <-> SUB. Includes CMP <-> CMN. */
19444 case T2_OPCODE_SUB
:
19445 new_inst
= T2_OPCODE_ADD
;
19449 case T2_OPCODE_ADD
:
19450 new_inst
= T2_OPCODE_SUB
;
19454 /* ORR <-> ORN. Includes MOV <-> MVN. */
19455 case T2_OPCODE_ORR
:
19456 new_inst
= T2_OPCODE_ORN
;
19460 case T2_OPCODE_ORN
:
19461 new_inst
= T2_OPCODE_ORR
;
19465 /* AND <-> BIC. TST has no inverted equivalent. */
19466 case T2_OPCODE_AND
:
19467 new_inst
= T2_OPCODE_BIC
;
19474 case T2_OPCODE_BIC
:
19475 new_inst
= T2_OPCODE_AND
;
19480 case T2_OPCODE_ADC
:
19481 new_inst
= T2_OPCODE_SBC
;
19485 case T2_OPCODE_SBC
:
19486 new_inst
= T2_OPCODE_ADC
;
19490 /* We cannot do anything. */
19495 if (value
== (unsigned int)FAIL
)
19498 *instruction
&= T2_OPCODE_MASK
;
19499 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
19503 /* Read a 32-bit thumb instruction from buf. */
19504 static unsigned long
19505 get_thumb32_insn (char * buf
)
19507 unsigned long insn
;
19508 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
19509 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19515 /* We usually want to set the low bit on the address of thumb function
19516 symbols. In particular .word foo - . should have the low bit set.
19517 Generic code tries to fold the difference of two symbols to
19518 a constant. Prevent this and force a relocation when the first symbols
19519 is a thumb function. */
19522 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
19524 if (op
== O_subtract
19525 && l
->X_op
== O_symbol
19526 && r
->X_op
== O_symbol
19527 && THUMB_IS_FUNC (l
->X_add_symbol
))
19529 l
->X_op
= O_subtract
;
19530 l
->X_op_symbol
= r
->X_add_symbol
;
19531 l
->X_add_number
-= r
->X_add_number
;
19535 /* Process as normal. */
19539 /* Encode Thumb2 unconditional branches and calls. The encoding
19540 for the 2 are identical for the immediate values. */
19543 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
19545 #define T2I1I2MASK ((1 << 13) | (1 << 11))
19548 addressT S
, I1
, I2
, lo
, hi
;
19550 S
= (value
>> 24) & 0x01;
19551 I1
= (value
>> 23) & 0x01;
19552 I2
= (value
>> 22) & 0x01;
19553 hi
= (value
>> 12) & 0x3ff;
19554 lo
= (value
>> 1) & 0x7ff;
19555 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19556 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19557 newval
|= (S
<< 10) | hi
;
19558 newval2
&= ~T2I1I2MASK
;
19559 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
19560 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19561 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
19565 md_apply_fix (fixS
* fixP
,
19569 offsetT value
= * valP
;
19571 unsigned int newimm
;
19572 unsigned long temp
;
19574 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
19576 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
19578 /* Note whether this will delete the relocation. */
19580 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
19583 /* On a 64-bit host, silently truncate 'value' to 32 bits for
19584 consistency with the behaviour on 32-bit hosts. Remember value
19586 value
&= 0xffffffff;
19587 value
^= 0x80000000;
19588 value
-= 0x80000000;
19591 fixP
->fx_addnumber
= value
;
19593 /* Same treatment for fixP->fx_offset. */
19594 fixP
->fx_offset
&= 0xffffffff;
19595 fixP
->fx_offset
^= 0x80000000;
19596 fixP
->fx_offset
-= 0x80000000;
19598 switch (fixP
->fx_r_type
)
19600 case BFD_RELOC_NONE
:
19601 /* This will need to go in the object file. */
19605 case BFD_RELOC_ARM_IMMEDIATE
:
19606 /* We claim that this fixup has been processed here,
19607 even if in fact we generate an error because we do
19608 not have a reloc for it, so tc_gen_reloc will reject it. */
19612 && ! S_IS_DEFINED (fixP
->fx_addsy
))
19614 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19615 _("undefined symbol %s used as an immediate value"),
19616 S_GET_NAME (fixP
->fx_addsy
));
19621 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19623 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19624 _("symbol %s is in a different section"),
19625 S_GET_NAME (fixP
->fx_addsy
));
19629 newimm
= encode_arm_immediate (value
);
19630 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19632 /* If the instruction will fail, see if we can fix things up by
19633 changing the opcode. */
19634 if (newimm
== (unsigned int) FAIL
19635 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
19637 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19638 _("invalid constant (%lx) after fixup"),
19639 (unsigned long) value
);
19643 newimm
|= (temp
& 0xfffff000);
19644 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19647 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
19649 unsigned int highpart
= 0;
19650 unsigned int newinsn
= 0xe1a00000; /* nop. */
19653 && ! S_IS_DEFINED (fixP
->fx_addsy
))
19655 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19656 _("undefined symbol %s used as an immediate value"),
19657 S_GET_NAME (fixP
->fx_addsy
));
19662 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19664 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19665 _("symbol %s is in a different section"),
19666 S_GET_NAME (fixP
->fx_addsy
));
19670 newimm
= encode_arm_immediate (value
);
19671 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19673 /* If the instruction will fail, see if we can fix things up by
19674 changing the opcode. */
19675 if (newimm
== (unsigned int) FAIL
19676 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
19678 /* No ? OK - try using two ADD instructions to generate
19680 newimm
= validate_immediate_twopart (value
, & highpart
);
19682 /* Yes - then make sure that the second instruction is
19684 if (newimm
!= (unsigned int) FAIL
)
19686 /* Still No ? Try using a negated value. */
19687 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
19688 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
19689 /* Otherwise - give up. */
19692 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19693 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
19698 /* Replace the first operand in the 2nd instruction (which
19699 is the PC) with the destination register. We have
19700 already added in the PC in the first instruction and we
19701 do not want to do it again. */
19702 newinsn
&= ~ 0xf0000;
19703 newinsn
|= ((newinsn
& 0x0f000) << 4);
19706 newimm
|= (temp
& 0xfffff000);
19707 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19709 highpart
|= (newinsn
& 0xfffff000);
19710 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
19714 case BFD_RELOC_ARM_OFFSET_IMM
:
19715 if (!fixP
->fx_done
&& seg
->use_rela_p
)
19718 case BFD_RELOC_ARM_LITERAL
:
19724 if (validate_offset_imm (value
, 0) == FAIL
)
19726 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
19727 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19728 _("invalid literal constant: pool needs to be closer"));
19730 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19731 _("bad immediate value for offset (%ld)"),
19736 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19737 newval
&= 0xff7ff000;
19738 newval
|= value
| (sign
? INDEX_UP
: 0);
19739 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19742 case BFD_RELOC_ARM_OFFSET_IMM8
:
19743 case BFD_RELOC_ARM_HWLITERAL
:
19749 if (validate_offset_imm (value
, 1) == FAIL
)
19751 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
19752 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19753 _("invalid literal constant: pool needs to be closer"));
19755 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
19760 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19761 newval
&= 0xff7ff0f0;
19762 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
19763 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19766 case BFD_RELOC_ARM_T32_OFFSET_U8
:
19767 if (value
< 0 || value
> 1020 || value
% 4 != 0)
19768 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19769 _("bad immediate value for offset (%ld)"), (long) value
);
19772 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
19774 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
19777 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19778 /* This is a complicated relocation used for all varieties of Thumb32
19779 load/store instruction with immediate offset:
19781 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
19782 *4, optional writeback(W)
19783 (doubleword load/store)
19785 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
19786 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
19787 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
19788 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
19789 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
19791 Uppercase letters indicate bits that are already encoded at
19792 this point. Lowercase letters are our problem. For the
19793 second block of instructions, the secondary opcode nybble
19794 (bits 8..11) is present, and bit 23 is zero, even if this is
19795 a PC-relative operation. */
19796 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19798 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
19800 if ((newval
& 0xf0000000) == 0xe0000000)
19802 /* Doubleword load/store: 8-bit offset, scaled by 4. */
19804 newval
|= (1 << 23);
19807 if (value
% 4 != 0)
19809 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19810 _("offset not a multiple of 4"));
19816 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19817 _("offset out of range"));
19822 else if ((newval
& 0x000f0000) == 0x000f0000)
19824 /* PC-relative, 12-bit offset. */
19826 newval
|= (1 << 23);
19831 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19832 _("offset out of range"));
19837 else if ((newval
& 0x00000100) == 0x00000100)
19839 /* Writeback: 8-bit, +/- offset. */
19841 newval
|= (1 << 9);
19846 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19847 _("offset out of range"));
19852 else if ((newval
& 0x00000f00) == 0x00000e00)
19854 /* T-instruction: positive 8-bit offset. */
19855 if (value
< 0 || value
> 0xff)
19857 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19858 _("offset out of range"));
19866 /* Positive 12-bit or negative 8-bit offset. */
19870 newval
|= (1 << 23);
19880 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19881 _("offset out of range"));
19888 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
19889 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
19892 case BFD_RELOC_ARM_SHIFT_IMM
:
19893 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19894 if (((unsigned long) value
) > 32
19896 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
19898 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19899 _("shift expression is too large"));
19904 /* Shifts of zero must be done as lsl. */
19906 else if (value
== 32)
19908 newval
&= 0xfffff07f;
19909 newval
|= (value
& 0x1f) << 7;
19910 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19913 case BFD_RELOC_ARM_T32_IMMEDIATE
:
19914 case BFD_RELOC_ARM_T32_ADD_IMM
:
19915 case BFD_RELOC_ARM_T32_IMM12
:
19916 case BFD_RELOC_ARM_T32_ADD_PC12
:
19917 /* We claim that this fixup has been processed here,
19918 even if in fact we generate an error because we do
19919 not have a reloc for it, so tc_gen_reloc will reject it. */
19923 && ! S_IS_DEFINED (fixP
->fx_addsy
))
19925 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19926 _("undefined symbol %s used as an immediate value"),
19927 S_GET_NAME (fixP
->fx_addsy
));
19931 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19933 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
19936 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
19937 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
19939 newimm
= encode_thumb32_immediate (value
);
19940 if (newimm
== (unsigned int) FAIL
)
19941 newimm
= thumb32_negate_data_op (&newval
, value
);
19943 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
19944 && newimm
== (unsigned int) FAIL
)
19946 /* Turn add/sum into addw/subw. */
19947 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
19948 newval
= (newval
& 0xfeffffff) | 0x02000000;
19950 /* 12 bit immediate for addw/subw. */
19954 newval
^= 0x00a00000;
19957 newimm
= (unsigned int) FAIL
;
19962 if (newimm
== (unsigned int)FAIL
)
19964 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19965 _("invalid constant (%lx) after fixup"),
19966 (unsigned long) value
);
19970 newval
|= (newimm
& 0x800) << 15;
19971 newval
|= (newimm
& 0x700) << 4;
19972 newval
|= (newimm
& 0x0ff);
19974 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
19975 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
19978 case BFD_RELOC_ARM_SMC
:
19979 if (((unsigned long) value
) > 0xffff)
19980 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19981 _("invalid smc expression"));
19982 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19983 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
19984 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19987 case BFD_RELOC_ARM_SWI
:
19988 if (fixP
->tc_fix_data
!= 0)
19990 if (((unsigned long) value
) > 0xff)
19991 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19992 _("invalid swi expression"));
19993 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19995 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19999 if (((unsigned long) value
) > 0x00ffffff)
20000 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20001 _("invalid swi expression"));
20002 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20004 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20008 case BFD_RELOC_ARM_MULTI
:
20009 if (((unsigned long) value
) > 0xffff)
20010 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20011 _("invalid expression in load/store multiple"));
20012 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
20013 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20017 case BFD_RELOC_ARM_PCREL_CALL
:
20019 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20021 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20022 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20023 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20024 /* Flip the bl to blx. This is a simple flip
20025 bit here because we generate PCREL_CALL for
20026 unconditional bls. */
20028 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20029 newval
= newval
| 0x10000000;
20030 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20036 goto arm_branch_common
;
20038 case BFD_RELOC_ARM_PCREL_JUMP
:
20039 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20041 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20042 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20043 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20045 /* This would map to a bl<cond>, b<cond>,
20046 b<always> to a Thumb function. We
20047 need to force a relocation for this particular
20049 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20053 case BFD_RELOC_ARM_PLT32
:
20055 case BFD_RELOC_ARM_PCREL_BRANCH
:
20057 goto arm_branch_common
;
20059 case BFD_RELOC_ARM_PCREL_BLX
:
20062 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20064 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20065 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20066 && ARM_IS_FUNC (fixP
->fx_addsy
))
20068 /* Flip the blx to a bl and warn. */
20069 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20070 newval
= 0xeb000000;
20071 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20072 _("blx to '%s' an ARM ISA state function changed to bl"),
20074 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20080 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20081 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
20085 /* We are going to store value (shifted right by two) in the
20086 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20087 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20088 also be be clear. */
20090 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20091 _("misaligned branch destination"));
20092 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
20093 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
20094 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20095 _("branch out of range"));
20097 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20099 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20100 newval
|= (value
>> 2) & 0x00ffffff;
20101 /* Set the H bit on BLX instructions. */
20105 newval
|= 0x01000000;
20107 newval
&= ~0x01000000;
20109 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20113 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
20114 /* CBZ can only branch forward. */
20116 /* Attempts to use CBZ to branch to the next instruction
20117 (which, strictly speaking, are prohibited) will be turned into
20120 FIXME: It may be better to remove the instruction completely and
20121 perform relaxation. */
20124 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20125 newval
= 0xbf00; /* NOP encoding T1 */
20126 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20131 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20132 _("branch out of range"));
20134 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20136 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20137 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
20138 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20143 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
20144 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
20145 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20146 _("branch out of range"));
20148 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20150 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20151 newval
|= (value
& 0x1ff) >> 1;
20152 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20156 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
20157 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
20158 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20159 _("branch out of range"));
20161 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20163 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20164 newval
|= (value
& 0xfff) >> 1;
20165 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20169 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20171 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20172 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20173 && S_IS_DEFINED (fixP
->fx_addsy
)
20174 && ARM_IS_FUNC (fixP
->fx_addsy
)
20175 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20177 /* Force a relocation for a branch 20 bits wide. */
20180 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
20181 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20182 _("conditional branch out of range"));
20184 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20187 addressT S
, J1
, J2
, lo
, hi
;
20189 S
= (value
& 0x00100000) >> 20;
20190 J2
= (value
& 0x00080000) >> 19;
20191 J1
= (value
& 0x00040000) >> 18;
20192 hi
= (value
& 0x0003f000) >> 12;
20193 lo
= (value
& 0x00000ffe) >> 1;
20195 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20196 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20197 newval
|= (S
<< 10) | hi
;
20198 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
20199 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20200 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20204 case BFD_RELOC_THUMB_PCREL_BLX
:
20206 /* If there is a blx from a thumb state function to
20207 another thumb function flip this to a bl and warn
20211 && S_IS_DEFINED (fixP
->fx_addsy
)
20212 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20213 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20214 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20216 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20217 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20218 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
20220 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20221 newval
= newval
| 0x1000;
20222 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20223 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20228 goto thumb_bl_common
;
20230 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20232 /* A bl from Thumb state ISA to an internal ARM state function
20233 is converted to a blx. */
20235 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20236 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20237 && S_IS_DEFINED (fixP
->fx_addsy
)
20238 && ARM_IS_FUNC (fixP
->fx_addsy
)
20239 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20241 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20242 newval
= newval
& ~0x1000;
20243 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20244 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
20251 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
20252 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20253 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20256 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20257 /* For a BLX instruction, make sure that the relocation is rounded up
20258 to a word boundary. This follows the semantics of the instruction
20259 which specifies that bit 1 of the target address will come from bit
20260 1 of the base address. */
20261 value
= (value
+ 1) & ~ 1;
20264 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
20266 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
20268 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20269 _("branch out of range"));
20271 else if ((value
& ~0x1ffffff)
20272 && ((value
& ~0x1ffffff) != ~0x1ffffff))
20274 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20275 _("Thumb2 branch out of range"));
20279 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20280 encode_thumb2_b_bl_offset (buf
, value
);
20284 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20285 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
20286 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20287 _("branch out of range"));
20289 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20290 encode_thumb2_b_bl_offset (buf
, value
);
20295 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20296 md_number_to_chars (buf
, value
, 1);
20300 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20301 md_number_to_chars (buf
, value
, 2);
20305 case BFD_RELOC_ARM_TLS_GD32
:
20306 case BFD_RELOC_ARM_TLS_LE32
:
20307 case BFD_RELOC_ARM_TLS_IE32
:
20308 case BFD_RELOC_ARM_TLS_LDM32
:
20309 case BFD_RELOC_ARM_TLS_LDO32
:
20310 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
20313 case BFD_RELOC_ARM_GOT32
:
20314 case BFD_RELOC_ARM_GOTOFF
:
20315 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20316 md_number_to_chars (buf
, 0, 4);
20319 case BFD_RELOC_ARM_TARGET2
:
20320 /* TARGET2 is not partial-inplace, so we need to write the
20321 addend here for REL targets, because it won't be written out
20322 during reloc processing later. */
20323 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20324 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
20328 case BFD_RELOC_RVA
:
20330 case BFD_RELOC_ARM_TARGET1
:
20331 case BFD_RELOC_ARM_ROSEGREL32
:
20332 case BFD_RELOC_ARM_SBREL32
:
20333 case BFD_RELOC_32_PCREL
:
20335 case BFD_RELOC_32_SECREL
:
20337 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20339 /* For WinCE we only do this for pcrel fixups. */
20340 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
20342 md_number_to_chars (buf
, value
, 4);
20346 case BFD_RELOC_ARM_PREL31
:
20347 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20349 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
20350 if ((value
^ (value
>> 1)) & 0x40000000)
20352 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20353 _("rel31 relocation overflow"));
20355 newval
|= value
& 0x7fffffff;
20356 md_number_to_chars (buf
, newval
, 4);
20361 case BFD_RELOC_ARM_CP_OFF_IMM
:
20362 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
20363 if (value
< -1023 || value
> 1023 || (value
& 3))
20364 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20365 _("co-processor offset out of range"));
20370 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20371 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20372 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20374 newval
= get_thumb32_insn (buf
);
20375 newval
&= 0xff7fff00;
20376 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
20377 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20378 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20379 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20381 put_thumb32_insn (buf
, newval
);
20384 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
20385 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
20386 if (value
< -255 || value
> 255)
20387 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20388 _("co-processor offset out of range"));
20390 goto cp_off_common
;
20392 case BFD_RELOC_ARM_THUMB_OFFSET
:
20393 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20394 /* Exactly what ranges, and where the offset is inserted depends
20395 on the type of instruction, we can establish this from the
20397 switch (newval
>> 12)
20399 case 4: /* PC load. */
20400 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
20401 forced to zero for these loads; md_pcrel_from has already
20402 compensated for this. */
20404 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20405 _("invalid offset, target not word aligned (0x%08lX)"),
20406 (((unsigned long) fixP
->fx_frag
->fr_address
20407 + (unsigned long) fixP
->fx_where
) & ~3)
20408 + (unsigned long) value
);
20410 if (value
& ~0x3fc)
20411 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20412 _("invalid offset, value too big (0x%08lX)"),
20415 newval
|= value
>> 2;
20418 case 9: /* SP load/store. */
20419 if (value
& ~0x3fc)
20420 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20421 _("invalid offset, value too big (0x%08lX)"),
20423 newval
|= value
>> 2;
20426 case 6: /* Word load/store. */
20428 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20429 _("invalid offset, value too big (0x%08lX)"),
20431 newval
|= value
<< 4; /* 6 - 2. */
20434 case 7: /* Byte load/store. */
20436 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20437 _("invalid offset, value too big (0x%08lX)"),
20439 newval
|= value
<< 6;
20442 case 8: /* Halfword load/store. */
20444 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20445 _("invalid offset, value too big (0x%08lX)"),
20447 newval
|= value
<< 5; /* 6 - 1. */
20451 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20452 "Unable to process relocation for thumb opcode: %lx",
20453 (unsigned long) newval
);
20456 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20459 case BFD_RELOC_ARM_THUMB_ADD
:
20460 /* This is a complicated relocation, since we use it for all of
20461 the following immediate relocations:
20465 9bit ADD/SUB SP word-aligned
20466 10bit ADD PC/SP word-aligned
20468 The type of instruction being processed is encoded in the
20475 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20477 int rd
= (newval
>> 4) & 0xf;
20478 int rs
= newval
& 0xf;
20479 int subtract
= !!(newval
& 0x8000);
20481 /* Check for HI regs, only very restricted cases allowed:
20482 Adjusting SP, and using PC or SP to get an address. */
20483 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
20484 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
20485 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20486 _("invalid Hi register with immediate"));
20488 /* If value is negative, choose the opposite instruction. */
20492 subtract
= !subtract
;
20494 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20495 _("immediate value out of range"));
20500 if (value
& ~0x1fc)
20501 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20502 _("invalid immediate for stack address calculation"));
20503 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
20504 newval
|= value
>> 2;
20506 else if (rs
== REG_PC
|| rs
== REG_SP
)
20508 if (subtract
|| value
& ~0x3fc)
20509 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20510 _("invalid immediate for address calculation (value = 0x%08lX)"),
20511 (unsigned long) value
);
20512 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
20514 newval
|= value
>> 2;
20519 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20520 _("immediate value out of range"));
20521 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
20522 newval
|= (rd
<< 8) | value
;
20527 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20528 _("immediate value out of range"));
20529 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
20530 newval
|= rd
| (rs
<< 3) | (value
<< 6);
20533 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20536 case BFD_RELOC_ARM_THUMB_IMM
:
20537 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20538 if (value
< 0 || value
> 255)
20539 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20540 _("invalid immediate: %ld is out of range"),
20543 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20546 case BFD_RELOC_ARM_THUMB_SHIFT
:
20547 /* 5bit shift value (0..32). LSL cannot take 32. */
20548 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
20549 temp
= newval
& 0xf800;
20550 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
20551 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20552 _("invalid shift value: %ld"), (long) value
);
20553 /* Shifts of zero must be encoded as LSL. */
20555 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
20556 /* Shifts of 32 are encoded as zero. */
20557 else if (value
== 32)
20559 newval
|= value
<< 6;
20560 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20563 case BFD_RELOC_VTABLE_INHERIT
:
20564 case BFD_RELOC_VTABLE_ENTRY
:
20568 case BFD_RELOC_ARM_MOVW
:
20569 case BFD_RELOC_ARM_MOVT
:
20570 case BFD_RELOC_ARM_THUMB_MOVW
:
20571 case BFD_RELOC_ARM_THUMB_MOVT
:
20572 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20574 /* REL format relocations are limited to a 16-bit addend. */
20575 if (!fixP
->fx_done
)
20577 if (value
< -0x8000 || value
> 0x7fff)
20578 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20579 _("offset out of range"));
20581 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
20582 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20587 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
20588 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20590 newval
= get_thumb32_insn (buf
);
20591 newval
&= 0xfbf08f00;
20592 newval
|= (value
& 0xf000) << 4;
20593 newval
|= (value
& 0x0800) << 15;
20594 newval
|= (value
& 0x0700) << 4;
20595 newval
|= (value
& 0x00ff);
20596 put_thumb32_insn (buf
, newval
);
20600 newval
= md_chars_to_number (buf
, 4);
20601 newval
&= 0xfff0f000;
20602 newval
|= value
& 0x0fff;
20603 newval
|= (value
& 0xf000) << 4;
20604 md_number_to_chars (buf
, newval
, 4);
20609 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
20610 case BFD_RELOC_ARM_ALU_PC_G0
:
20611 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
20612 case BFD_RELOC_ARM_ALU_PC_G1
:
20613 case BFD_RELOC_ARM_ALU_PC_G2
:
20614 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
20615 case BFD_RELOC_ARM_ALU_SB_G0
:
20616 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
20617 case BFD_RELOC_ARM_ALU_SB_G1
:
20618 case BFD_RELOC_ARM_ALU_SB_G2
:
20619 gas_assert (!fixP
->fx_done
);
20620 if (!seg
->use_rela_p
)
20623 bfd_vma encoded_addend
;
20624 bfd_vma addend_abs
= abs (value
);
20626 /* Check that the absolute value of the addend can be
20627 expressed as an 8-bit constant plus a rotation. */
20628 encoded_addend
= encode_arm_immediate (addend_abs
);
20629 if (encoded_addend
== (unsigned int) FAIL
)
20630 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20631 _("the offset 0x%08lX is not representable"),
20632 (unsigned long) addend_abs
);
20634 /* Extract the instruction. */
20635 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20637 /* If the addend is positive, use an ADD instruction.
20638 Otherwise use a SUB. Take care not to destroy the S bit. */
20639 insn
&= 0xff1fffff;
20645 /* Place the encoded addend into the first 12 bits of the
20647 insn
&= 0xfffff000;
20648 insn
|= encoded_addend
;
20650 /* Update the instruction. */
20651 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20655 case BFD_RELOC_ARM_LDR_PC_G0
:
20656 case BFD_RELOC_ARM_LDR_PC_G1
:
20657 case BFD_RELOC_ARM_LDR_PC_G2
:
20658 case BFD_RELOC_ARM_LDR_SB_G0
:
20659 case BFD_RELOC_ARM_LDR_SB_G1
:
20660 case BFD_RELOC_ARM_LDR_SB_G2
:
20661 gas_assert (!fixP
->fx_done
);
20662 if (!seg
->use_rela_p
)
20665 bfd_vma addend_abs
= abs (value
);
20667 /* Check that the absolute value of the addend can be
20668 encoded in 12 bits. */
20669 if (addend_abs
>= 0x1000)
20670 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20671 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
20672 (unsigned long) addend_abs
);
20674 /* Extract the instruction. */
20675 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20677 /* If the addend is negative, clear bit 23 of the instruction.
20678 Otherwise set it. */
20680 insn
&= ~(1 << 23);
20684 /* Place the absolute value of the addend into the first 12 bits
20685 of the instruction. */
20686 insn
&= 0xfffff000;
20687 insn
|= addend_abs
;
20689 /* Update the instruction. */
20690 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20694 case BFD_RELOC_ARM_LDRS_PC_G0
:
20695 case BFD_RELOC_ARM_LDRS_PC_G1
:
20696 case BFD_RELOC_ARM_LDRS_PC_G2
:
20697 case BFD_RELOC_ARM_LDRS_SB_G0
:
20698 case BFD_RELOC_ARM_LDRS_SB_G1
:
20699 case BFD_RELOC_ARM_LDRS_SB_G2
:
20700 gas_assert (!fixP
->fx_done
);
20701 if (!seg
->use_rela_p
)
20704 bfd_vma addend_abs
= abs (value
);
20706 /* Check that the absolute value of the addend can be
20707 encoded in 8 bits. */
20708 if (addend_abs
>= 0x100)
20709 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20710 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
20711 (unsigned long) addend_abs
);
20713 /* Extract the instruction. */
20714 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20716 /* If the addend is negative, clear bit 23 of the instruction.
20717 Otherwise set it. */
20719 insn
&= ~(1 << 23);
20723 /* Place the first four bits of the absolute value of the addend
20724 into the first 4 bits of the instruction, and the remaining
20725 four into bits 8 .. 11. */
20726 insn
&= 0xfffff0f0;
20727 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
20729 /* Update the instruction. */
20730 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20734 case BFD_RELOC_ARM_LDC_PC_G0
:
20735 case BFD_RELOC_ARM_LDC_PC_G1
:
20736 case BFD_RELOC_ARM_LDC_PC_G2
:
20737 case BFD_RELOC_ARM_LDC_SB_G0
:
20738 case BFD_RELOC_ARM_LDC_SB_G1
:
20739 case BFD_RELOC_ARM_LDC_SB_G2
:
20740 gas_assert (!fixP
->fx_done
);
20741 if (!seg
->use_rela_p
)
20744 bfd_vma addend_abs
= abs (value
);
20746 /* Check that the absolute value of the addend is a multiple of
20747 four and, when divided by four, fits in 8 bits. */
20748 if (addend_abs
& 0x3)
20749 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20750 _("bad offset 0x%08lX (must be word-aligned)"),
20751 (unsigned long) addend_abs
);
20753 if ((addend_abs
>> 2) > 0xff)
20754 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20755 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
20756 (unsigned long) addend_abs
);
20758 /* Extract the instruction. */
20759 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20761 /* If the addend is negative, clear bit 23 of the instruction.
20762 Otherwise set it. */
20764 insn
&= ~(1 << 23);
20768 /* Place the addend (divided by four) into the first eight
20769 bits of the instruction. */
20770 insn
&= 0xfffffff0;
20771 insn
|= addend_abs
>> 2;
20773 /* Update the instruction. */
20774 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20778 case BFD_RELOC_ARM_V4BX
:
20779 /* This will need to go in the object file. */
20783 case BFD_RELOC_UNUSED
:
20785 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20786 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
20790 /* Translate internal representation of relocation info to BFD target
20794 tc_gen_reloc (asection
*section
, fixS
*fixp
)
20797 bfd_reloc_code_real_type code
;
20799 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
20801 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
20802 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
20803 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
20805 if (fixp
->fx_pcrel
)
20807 if (section
->use_rela_p
)
20808 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
20810 fixp
->fx_offset
= reloc
->address
;
20812 reloc
->addend
= fixp
->fx_offset
;
20814 switch (fixp
->fx_r_type
)
20817 if (fixp
->fx_pcrel
)
20819 code
= BFD_RELOC_8_PCREL
;
20824 if (fixp
->fx_pcrel
)
20826 code
= BFD_RELOC_16_PCREL
;
20831 if (fixp
->fx_pcrel
)
20833 code
= BFD_RELOC_32_PCREL
;
20837 case BFD_RELOC_ARM_MOVW
:
20838 if (fixp
->fx_pcrel
)
20840 code
= BFD_RELOC_ARM_MOVW_PCREL
;
20844 case BFD_RELOC_ARM_MOVT
:
20845 if (fixp
->fx_pcrel
)
20847 code
= BFD_RELOC_ARM_MOVT_PCREL
;
20851 case BFD_RELOC_ARM_THUMB_MOVW
:
20852 if (fixp
->fx_pcrel
)
20854 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
20858 case BFD_RELOC_ARM_THUMB_MOVT
:
20859 if (fixp
->fx_pcrel
)
20861 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
20865 case BFD_RELOC_NONE
:
20866 case BFD_RELOC_ARM_PCREL_BRANCH
:
20867 case BFD_RELOC_ARM_PCREL_BLX
:
20868 case BFD_RELOC_RVA
:
20869 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
20870 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
20871 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
20872 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20873 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20874 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20875 case BFD_RELOC_VTABLE_ENTRY
:
20876 case BFD_RELOC_VTABLE_INHERIT
:
20878 case BFD_RELOC_32_SECREL
:
20880 code
= fixp
->fx_r_type
;
20883 case BFD_RELOC_THUMB_PCREL_BLX
:
20885 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20886 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20889 code
= BFD_RELOC_THUMB_PCREL_BLX
;
20892 case BFD_RELOC_ARM_LITERAL
:
20893 case BFD_RELOC_ARM_HWLITERAL
:
20894 /* If this is called then the a literal has
20895 been referenced across a section boundary. */
20896 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20897 _("literal referenced across section boundary"));
20901 case BFD_RELOC_ARM_GOT32
:
20902 case BFD_RELOC_ARM_GOTOFF
:
20903 case BFD_RELOC_ARM_PLT32
:
20904 case BFD_RELOC_ARM_TARGET1
:
20905 case BFD_RELOC_ARM_ROSEGREL32
:
20906 case BFD_RELOC_ARM_SBREL32
:
20907 case BFD_RELOC_ARM_PREL31
:
20908 case BFD_RELOC_ARM_TARGET2
:
20909 case BFD_RELOC_ARM_TLS_LE32
:
20910 case BFD_RELOC_ARM_TLS_LDO32
:
20911 case BFD_RELOC_ARM_PCREL_CALL
:
20912 case BFD_RELOC_ARM_PCREL_JUMP
:
20913 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
20914 case BFD_RELOC_ARM_ALU_PC_G0
:
20915 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
20916 case BFD_RELOC_ARM_ALU_PC_G1
:
20917 case BFD_RELOC_ARM_ALU_PC_G2
:
20918 case BFD_RELOC_ARM_LDR_PC_G0
:
20919 case BFD_RELOC_ARM_LDR_PC_G1
:
20920 case BFD_RELOC_ARM_LDR_PC_G2
:
20921 case BFD_RELOC_ARM_LDRS_PC_G0
:
20922 case BFD_RELOC_ARM_LDRS_PC_G1
:
20923 case BFD_RELOC_ARM_LDRS_PC_G2
:
20924 case BFD_RELOC_ARM_LDC_PC_G0
:
20925 case BFD_RELOC_ARM_LDC_PC_G1
:
20926 case BFD_RELOC_ARM_LDC_PC_G2
:
20927 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
20928 case BFD_RELOC_ARM_ALU_SB_G0
:
20929 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
20930 case BFD_RELOC_ARM_ALU_SB_G1
:
20931 case BFD_RELOC_ARM_ALU_SB_G2
:
20932 case BFD_RELOC_ARM_LDR_SB_G0
:
20933 case BFD_RELOC_ARM_LDR_SB_G1
:
20934 case BFD_RELOC_ARM_LDR_SB_G2
:
20935 case BFD_RELOC_ARM_LDRS_SB_G0
:
20936 case BFD_RELOC_ARM_LDRS_SB_G1
:
20937 case BFD_RELOC_ARM_LDRS_SB_G2
:
20938 case BFD_RELOC_ARM_LDC_SB_G0
:
20939 case BFD_RELOC_ARM_LDC_SB_G1
:
20940 case BFD_RELOC_ARM_LDC_SB_G2
:
20941 case BFD_RELOC_ARM_V4BX
:
20942 code
= fixp
->fx_r_type
;
20945 case BFD_RELOC_ARM_TLS_GD32
:
20946 case BFD_RELOC_ARM_TLS_IE32
:
20947 case BFD_RELOC_ARM_TLS_LDM32
:
20948 /* BFD will include the symbol's address in the addend.
20949 But we don't want that, so subtract it out again here. */
20950 if (!S_IS_COMMON (fixp
->fx_addsy
))
20951 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
20952 code
= fixp
->fx_r_type
;
20956 case BFD_RELOC_ARM_IMMEDIATE
:
20957 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20958 _("internal relocation (type: IMMEDIATE) not fixed up"));
20961 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
20962 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20963 _("ADRL used for a symbol not defined in the same file"));
20966 case BFD_RELOC_ARM_OFFSET_IMM
:
20967 if (section
->use_rela_p
)
20969 code
= fixp
->fx_r_type
;
20973 if (fixp
->fx_addsy
!= NULL
20974 && !S_IS_DEFINED (fixp
->fx_addsy
)
20975 && S_IS_LOCAL (fixp
->fx_addsy
))
20977 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20978 _("undefined local label `%s'"),
20979 S_GET_NAME (fixp
->fx_addsy
));
20983 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20984 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
20991 switch (fixp
->fx_r_type
)
20993 case BFD_RELOC_NONE
: type
= "NONE"; break;
20994 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
20995 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
20996 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
20997 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
20998 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
20999 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
21000 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
21001 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
21002 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
21003 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
21004 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
21005 default: type
= _("<unknown>"); break;
21007 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21008 _("cannot represent %s relocation in this object file format"),
21015 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
21017 && fixp
->fx_addsy
== GOT_symbol
)
21019 code
= BFD_RELOC_ARM_GOTPC
;
21020 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
21024 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
21026 if (reloc
->howto
== NULL
)
21028 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21029 _("cannot represent %s relocation in this object file format"),
21030 bfd_get_reloc_code_name (code
));
21034 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21035 vtable entry to be used in the relocation's section offset. */
21036 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21037 reloc
->address
= fixp
->fx_offset
;
21042 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21045 cons_fix_new_arm (fragS
* frag
,
21050 bfd_reloc_code_real_type type
;
21054 FIXME: @@ Should look at CPU word size. */
21058 type
= BFD_RELOC_8
;
21061 type
= BFD_RELOC_16
;
21065 type
= BFD_RELOC_32
;
21068 type
= BFD_RELOC_64
;
21073 if (exp
->X_op
== O_secrel
)
21075 exp
->X_op
= O_symbol
;
21076 type
= BFD_RELOC_32_SECREL
;
21080 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
21083 #if defined (OBJ_COFF)
21085 arm_validate_fix (fixS
* fixP
)
21087 /* If the destination of the branch is a defined symbol which does not have
21088 the THUMB_FUNC attribute, then we must be calling a function which has
21089 the (interfacearm) attribute. We look for the Thumb entry point to that
21090 function and change the branch to refer to that function instead. */
21091 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
21092 && fixP
->fx_addsy
!= NULL
21093 && S_IS_DEFINED (fixP
->fx_addsy
)
21094 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
21096 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
21103 arm_force_relocation (struct fix
* fixp
)
21105 #if defined (OBJ_COFF) && defined (TE_PE)
21106 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
21110 /* In case we have a call or a branch to a function in ARM ISA mode from
21111 a thumb function or vice-versa force the relocation. These relocations
21112 are cleared off for some cores that might have blx and simple transformations
21116 switch (fixp
->fx_r_type
)
21118 case BFD_RELOC_ARM_PCREL_JUMP
:
21119 case BFD_RELOC_ARM_PCREL_CALL
:
21120 case BFD_RELOC_THUMB_PCREL_BLX
:
21121 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
21125 case BFD_RELOC_ARM_PCREL_BLX
:
21126 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21127 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21128 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21129 if (ARM_IS_FUNC (fixp
->fx_addsy
))
21138 /* Resolve these relocations even if the symbol is extern or weak. */
21139 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
21140 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
21141 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
21142 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
21143 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
21144 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
21145 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
21148 /* Always leave these relocations for the linker. */
21149 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21150 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21151 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21154 /* Always generate relocations against function symbols. */
21155 if (fixp
->fx_r_type
== BFD_RELOC_32
21157 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
21160 return generic_force_reloc (fixp
);
21163 #if defined (OBJ_ELF) || defined (OBJ_COFF)
21164 /* Relocations against function names must be left unadjusted,
21165 so that the linker can use this information to generate interworking
21166 stubs. The MIPS version of this function
21167 also prevents relocations that are mips-16 specific, but I do not
21168 know why it does this.
21171 There is one other problem that ought to be addressed here, but
21172 which currently is not: Taking the address of a label (rather
21173 than a function) and then later jumping to that address. Such
21174 addresses also ought to have their bottom bit set (assuming that
21175 they reside in Thumb code), but at the moment they will not. */
21178 arm_fix_adjustable (fixS
* fixP
)
21180 if (fixP
->fx_addsy
== NULL
)
21183 /* Preserve relocations against symbols with function type. */
21184 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
21187 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
21188 && fixP
->fx_subsy
== NULL
)
21191 /* We need the symbol name for the VTABLE entries. */
21192 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
21193 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21196 /* Don't allow symbols to be discarded on GOT related relocs. */
21197 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
21198 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
21199 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
21200 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
21201 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
21202 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
21203 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
21204 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
21205 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
21208 /* Similarly for group relocations. */
21209 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21210 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21211 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21214 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
21215 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
21216 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21217 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
21218 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
21219 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21220 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
21221 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
21222 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
21227 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
21232 elf32_arm_target_format (void)
21235 return (target_big_endian
21236 ? "elf32-bigarm-symbian"
21237 : "elf32-littlearm-symbian");
21238 #elif defined (TE_VXWORKS)
21239 return (target_big_endian
21240 ? "elf32-bigarm-vxworks"
21241 : "elf32-littlearm-vxworks");
21243 if (target_big_endian
)
21244 return "elf32-bigarm";
21246 return "elf32-littlearm";
21251 armelf_frob_symbol (symbolS
* symp
,
21254 elf_frob_symbol (symp
, puntp
);
21258 /* MD interface: Finalization. */
21263 literal_pool
* pool
;
21265 /* Ensure that all the IT blocks are properly closed. */
21266 check_it_blocks_finished ();
21268 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
21270 /* Put it at the end of the relevant section. */
21271 subseg_set (pool
->section
, pool
->sub_section
);
21273 arm_elf_change_section ();
21280 /* Remove any excess mapping symbols generated for alignment frags in
21281 SEC. We may have created a mapping symbol before a zero byte
21282 alignment; remove it if there's a mapping symbol after the
21285 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
21286 void *dummy ATTRIBUTE_UNUSED
)
21288 segment_info_type
*seginfo
= seg_info (sec
);
21291 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
21294 for (fragp
= seginfo
->frchainP
->frch_root
;
21296 fragp
= fragp
->fr_next
)
21298 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
21299 fragS
*next
= fragp
->fr_next
;
21301 /* Variable-sized frags have been converted to fixed size by
21302 this point. But if this was variable-sized to start with,
21303 there will be a fixed-size frag after it. So don't handle
21305 if (sym
== NULL
|| next
== NULL
)
21308 if (S_GET_VALUE (sym
) < next
->fr_address
)
21309 /* Not at the end of this frag. */
21311 know (S_GET_VALUE (sym
) == next
->fr_address
);
21315 if (next
->tc_frag_data
.first_map
!= NULL
)
21317 /* Next frag starts with a mapping symbol. Discard this
21319 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21323 if (next
->fr_next
== NULL
)
21325 /* This mapping symbol is at the end of the section. Discard
21327 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
21328 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21332 /* As long as we have empty frags without any mapping symbols,
21334 /* If the next frag is non-empty and does not start with a
21335 mapping symbol, then this mapping symbol is required. */
21336 if (next
->fr_address
!= next
->fr_next
->fr_address
)
21339 next
= next
->fr_next
;
21341 while (next
!= NULL
);
21346 /* Adjust the symbol table. This marks Thumb symbols as distinct from
21350 arm_adjust_symtab (void)
21355 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21357 if (ARM_IS_THUMB (sym
))
21359 if (THUMB_IS_FUNC (sym
))
21361 /* Mark the symbol as a Thumb function. */
21362 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
21363 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
21364 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
21366 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
21367 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
21369 as_bad (_("%s: unexpected function type: %d"),
21370 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
21372 else switch (S_GET_STORAGE_CLASS (sym
))
21375 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
21378 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
21381 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
21389 if (ARM_IS_INTERWORK (sym
))
21390 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
21397 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21399 if (ARM_IS_THUMB (sym
))
21401 elf_symbol_type
* elf_sym
;
21403 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
21404 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
21406 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
21407 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
21409 /* If it's a .thumb_func, declare it as so,
21410 otherwise tag label as .code 16. */
21411 if (THUMB_IS_FUNC (sym
))
21412 elf_sym
->internal_elf_sym
.st_info
=
21413 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
21414 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
21415 elf_sym
->internal_elf_sym
.st_info
=
21416 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
21421 /* Remove any overlapping mapping symbols generated by alignment frags. */
21422 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
21426 /* MD interface: Initialization. */
21429 set_constant_flonums (void)
21433 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
21434 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
21438 /* Auto-select Thumb mode if it's the only available instruction set for the
21439 given architecture. */
21442 autoselect_thumb_from_cpu_variant (void)
21444 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
21445 opcode_select (16);
21454 if ( (arm_ops_hsh
= hash_new ()) == NULL
21455 || (arm_cond_hsh
= hash_new ()) == NULL
21456 || (arm_shift_hsh
= hash_new ()) == NULL
21457 || (arm_psr_hsh
= hash_new ()) == NULL
21458 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
21459 || (arm_reg_hsh
= hash_new ()) == NULL
21460 || (arm_reloc_hsh
= hash_new ()) == NULL
21461 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
21462 as_fatal (_("virtual memory exhausted"));
21464 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
21465 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
21466 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
21467 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
21468 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
21469 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
21470 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
21471 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
21472 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
21473 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
21474 (void *) (v7m_psrs
+ i
));
21475 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
21476 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
21478 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
21480 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
21481 (void *) (barrier_opt_names
+ i
));
21483 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
21484 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
21487 set_constant_flonums ();
21489 /* Set the cpu variant based on the command-line options. We prefer
21490 -mcpu= over -march= if both are set (as for GCC); and we prefer
21491 -mfpu= over any other way of setting the floating point unit.
21492 Use of legacy options with new options are faulted. */
21495 if (mcpu_cpu_opt
|| march_cpu_opt
)
21496 as_bad (_("use of old and new-style options to set CPU type"));
21498 mcpu_cpu_opt
= legacy_cpu
;
21500 else if (!mcpu_cpu_opt
)
21501 mcpu_cpu_opt
= march_cpu_opt
;
21506 as_bad (_("use of old and new-style options to set FPU type"));
21508 mfpu_opt
= legacy_fpu
;
21510 else if (!mfpu_opt
)
21512 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
21513 || defined (TE_NetBSD) || defined (TE_VXWORKS))
21514 /* Some environments specify a default FPU. If they don't, infer it
21515 from the processor. */
21517 mfpu_opt
= mcpu_fpu_opt
;
21519 mfpu_opt
= march_fpu_opt
;
21521 mfpu_opt
= &fpu_default
;
21527 if (mcpu_cpu_opt
!= NULL
)
21528 mfpu_opt
= &fpu_default
;
21529 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
21530 mfpu_opt
= &fpu_arch_vfp_v2
;
21532 mfpu_opt
= &fpu_arch_fpa
;
21538 mcpu_cpu_opt
= &cpu_default
;
21539 selected_cpu
= cpu_default
;
21543 selected_cpu
= *mcpu_cpu_opt
;
21545 mcpu_cpu_opt
= &arm_arch_any
;
21548 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21550 autoselect_thumb_from_cpu_variant ();
21552 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
21554 #if defined OBJ_COFF || defined OBJ_ELF
21556 unsigned int flags
= 0;
21558 #if defined OBJ_ELF
21559 flags
= meabi_flags
;
21561 switch (meabi_flags
)
21563 case EF_ARM_EABI_UNKNOWN
:
21565 /* Set the flags in the private structure. */
21566 if (uses_apcs_26
) flags
|= F_APCS26
;
21567 if (support_interwork
) flags
|= F_INTERWORK
;
21568 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
21569 if (pic_code
) flags
|= F_PIC
;
21570 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
21571 flags
|= F_SOFT_FLOAT
;
21573 switch (mfloat_abi_opt
)
21575 case ARM_FLOAT_ABI_SOFT
:
21576 case ARM_FLOAT_ABI_SOFTFP
:
21577 flags
|= F_SOFT_FLOAT
;
21580 case ARM_FLOAT_ABI_HARD
:
21581 if (flags
& F_SOFT_FLOAT
)
21582 as_bad (_("hard-float conflicts with specified fpu"));
21586 /* Using pure-endian doubles (even if soft-float). */
21587 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
21588 flags
|= F_VFP_FLOAT
;
21590 #if defined OBJ_ELF
21591 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
21592 flags
|= EF_ARM_MAVERICK_FLOAT
;
21595 case EF_ARM_EABI_VER4
:
21596 case EF_ARM_EABI_VER5
:
21597 /* No additional flags to set. */
21604 bfd_set_private_flags (stdoutput
, flags
);
21606 /* We have run out flags in the COFF header to encode the
21607 status of ATPCS support, so instead we create a dummy,
21608 empty, debug section called .arm.atpcs. */
21613 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
21617 bfd_set_section_flags
21618 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
21619 bfd_set_section_size (stdoutput
, sec
, 0);
21620 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
21626 /* Record the CPU type as well. */
21627 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
21628 mach
= bfd_mach_arm_iWMMXt2
;
21629 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
21630 mach
= bfd_mach_arm_iWMMXt
;
21631 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
21632 mach
= bfd_mach_arm_XScale
;
21633 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
21634 mach
= bfd_mach_arm_ep9312
;
21635 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
21636 mach
= bfd_mach_arm_5TE
;
21637 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
21639 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21640 mach
= bfd_mach_arm_5T
;
21642 mach
= bfd_mach_arm_5
;
21644 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
21646 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21647 mach
= bfd_mach_arm_4T
;
21649 mach
= bfd_mach_arm_4
;
21651 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
21652 mach
= bfd_mach_arm_3M
;
21653 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
21654 mach
= bfd_mach_arm_3
;
21655 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
21656 mach
= bfd_mach_arm_2a
;
21657 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
21658 mach
= bfd_mach_arm_2
;
21660 mach
= bfd_mach_arm_unknown
;
21662 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
21665 /* Command line processing. */
21668 Invocation line includes a switch not recognized by the base assembler.
21669 See if it's a processor-specific option.
21671 This routine is somewhat complicated by the need for backwards
21672 compatibility (since older releases of gcc can't be changed).
21673 The new options try to make the interface as compatible as
21676 New options (supported) are:
21678 -mcpu=<cpu name> Assemble for selected processor
21679 -march=<architecture name> Assemble for selected architecture
21680 -mfpu=<fpu architecture> Assemble for selected FPU.
21681 -EB/-mbig-endian Big-endian
21682 -EL/-mlittle-endian Little-endian
21683 -k Generate PIC code
21684 -mthumb Start in Thumb mode
21685 -mthumb-interwork Code supports ARM/Thumb interworking
21687 -m[no-]warn-deprecated Warn about deprecated features
21689 For now we will also provide support for:
21691 -mapcs-32 32-bit Program counter
21692 -mapcs-26 26-bit Program counter
21693 -macps-float Floats passed in FP registers
21694 -mapcs-reentrant Reentrant code
21696 (sometime these will probably be replaced with -mapcs=<list of options>
21697 and -matpcs=<list of options>)
21699 The remaining options are only supported for back-wards compatibility.
21700 Cpu variants, the arm part is optional:
21701 -m[arm]1 Currently not supported.
21702 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
21703 -m[arm]3 Arm 3 processor
21704 -m[arm]6[xx], Arm 6 processors
21705 -m[arm]7[xx][t][[d]m] Arm 7 processors
21706 -m[arm]8[10] Arm 8 processors
21707 -m[arm]9[20][tdmi] Arm 9 processors
21708 -mstrongarm[110[0]] StrongARM processors
21709 -mxscale XScale processors
21710 -m[arm]v[2345[t[e]]] Arm architectures
21711 -mall All (except the ARM1)
21713 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
21714 -mfpe-old (No float load/store multiples)
21715 -mvfpxd VFP Single precision
21717 -mno-fpu Disable all floating point instructions
21719 The following CPU names are recognized:
21720 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
21721 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
21722 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
21723 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
21724 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
21725 arm10t arm10e, arm1020t, arm1020e, arm10200e,
21726 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
21730 const char * md_shortopts
= "m:k";
21732 #ifdef ARM_BI_ENDIAN
21733 #define OPTION_EB (OPTION_MD_BASE + 0)
21734 #define OPTION_EL (OPTION_MD_BASE + 1)
21736 #if TARGET_BYTES_BIG_ENDIAN
21737 #define OPTION_EB (OPTION_MD_BASE + 0)
21739 #define OPTION_EL (OPTION_MD_BASE + 1)
21742 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
21744 struct option md_longopts
[] =
21747 {"EB", no_argument
, NULL
, OPTION_EB
},
21750 {"EL", no_argument
, NULL
, OPTION_EL
},
21752 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
21753 {NULL
, no_argument
, NULL
, 0}
21756 size_t md_longopts_size
= sizeof (md_longopts
);
21758 struct arm_option_table
21760 char *option
; /* Option name to match. */
21761 char *help
; /* Help information. */
21762 int *var
; /* Variable to change. */
21763 int value
; /* What to change it to. */
21764 char *deprecated
; /* If non-null, print this message. */
21767 struct arm_option_table arm_opts
[] =
21769 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
21770 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
21771 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
21772 &support_interwork
, 1, NULL
},
21773 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
21774 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
21775 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
21777 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
21778 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
21779 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
21780 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
21783 /* These are recognized by the assembler, but have no affect on code. */
21784 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
21785 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
21787 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
21788 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
21789 &warn_on_deprecated
, 0, NULL
},
21790 {NULL
, NULL
, NULL
, 0, NULL
}
21793 struct arm_legacy_option_table
21795 char *option
; /* Option name to match. */
21796 const arm_feature_set
**var
; /* Variable to change. */
21797 const arm_feature_set value
; /* What to change it to. */
21798 char *deprecated
; /* If non-null, print this message. */
21801 const struct arm_legacy_option_table arm_legacy_opts
[] =
21803 /* DON'T add any new processors to this list -- we want the whole list
21804 to go away... Add them to the processors table instead. */
21805 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
21806 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
21807 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
21808 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
21809 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
21810 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
21811 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
21812 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
21813 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
21814 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
21815 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
21816 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
21817 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
21818 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
21819 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
21820 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
21821 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
21822 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
21823 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
21824 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
21825 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
21826 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
21827 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
21828 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
21829 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
21830 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
21831 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
21832 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
21833 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
21834 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
21835 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
21836 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
21837 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
21838 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
21839 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
21840 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
21841 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
21842 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
21843 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
21844 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
21845 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
21846 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
21847 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
21848 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
21849 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
21850 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
21851 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21852 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21853 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21854 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21855 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
21856 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
21857 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
21858 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
21859 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
21860 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
21861 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
21862 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
21863 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
21864 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
21865 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
21866 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
21867 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
21868 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
21869 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
21870 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
21871 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
21872 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
21873 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
21874 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
21875 N_("use -mcpu=strongarm110")},
21876 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
21877 N_("use -mcpu=strongarm1100")},
21878 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
21879 N_("use -mcpu=strongarm1110")},
21880 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
21881 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
21882 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
21884 /* Architecture variants -- don't add any more to this list either. */
21885 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
21886 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
21887 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
21888 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
21889 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
21890 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
21891 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
21892 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
21893 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
21894 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
21895 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
21896 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
21897 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
21898 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
21899 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
21900 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
21901 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
21902 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
21904 /* Floating point variants -- don't add any more to this list either. */
21905 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
21906 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
21907 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
21908 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
21909 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
21911 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
21914 struct arm_cpu_option_table
21917 const arm_feature_set value
;
21918 /* For some CPUs we assume an FPU unless the user explicitly sets
21920 const arm_feature_set default_fpu
;
21921 /* The canonical name of the CPU, or NULL to use NAME converted to upper
21923 const char *canonical_name
;
21926 /* This list should, at a minimum, contain all the cpu names
21927 recognized by GCC. */
21928 static const struct arm_cpu_option_table arm_cpus
[] =
21930 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
21931 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
21932 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
21933 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
21934 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
21935 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21936 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21937 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21938 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21939 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21940 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21941 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
21942 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21943 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
21944 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21945 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
21946 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21947 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21948 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21949 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21950 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21951 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21952 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21953 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21954 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21955 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21956 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21957 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21958 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21959 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21960 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21961 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21962 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21963 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21964 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21965 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21966 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21967 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21968 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21969 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
21970 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21971 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21972 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21973 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21974 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21975 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21976 /* For V5 or later processors we default to using VFP; but the user
21977 should really set the FPU type explicitly. */
21978 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
21979 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21980 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
21981 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
21982 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
21983 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
21984 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
21985 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21986 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
21987 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
21988 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21989 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21990 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
21991 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
21992 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21993 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
21994 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
21995 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21996 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21997 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
21998 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
21999 {"fa626te", ARM_ARCH_V5TE
, FPU_NONE
, NULL
},
22000 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22001 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
22002 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
22003 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
22004 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
22005 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
22006 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
22007 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
22008 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
22009 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
22010 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
22011 {"cortex-a5", ARM_ARCH_V7A
, FPU_NONE
, NULL
},
22012 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
22013 | FPU_NEON_EXT_V1
),
22015 {"cortex-a9", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
22016 | FPU_NEON_EXT_V1
),
22018 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
22019 {"cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
, NULL
},
22020 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
22021 {"cortex-m1", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
22022 {"cortex-m0", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
22023 /* ??? XSCALE is really an architecture. */
22024 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22025 /* ??? iwmmxt is not a processor. */
22026 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
22027 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
22028 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22030 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
22031 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
22034 struct arm_arch_option_table
22037 const arm_feature_set value
;
22038 const arm_feature_set default_fpu
;
22041 /* This list should, at a minimum, contain all the architecture names
22042 recognized by GCC. */
22043 static const struct arm_arch_option_table arm_archs
[] =
22045 {"all", ARM_ANY
, FPU_ARCH_FPA
},
22046 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
22047 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
22048 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22049 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22050 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
22051 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
22052 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
22053 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
22054 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
22055 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
22056 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
22057 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
22058 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
22059 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
22060 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
22061 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
22062 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22063 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22064 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
22065 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
22066 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
22067 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
22068 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
22069 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
22070 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
22071 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
22072 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
22073 /* The official spelling of the ARMv7 profile variants is the dashed form.
22074 Accept the non-dashed form for compatibility with old toolchains. */
22075 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22076 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22077 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22078 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22079 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22080 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22081 {"armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
},
22082 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
22083 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
22084 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
22085 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22088 /* ISA extensions in the co-processor space. */
22089 struct arm_option_cpu_value_table
22092 const arm_feature_set value
;
22095 static const struct arm_option_cpu_value_table arm_extensions
[] =
22097 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
22098 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
22099 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
22100 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
22101 {NULL
, ARM_ARCH_NONE
}
22104 /* This list should, at a minimum, contain all the fpu names
22105 recognized by GCC. */
22106 static const struct arm_option_cpu_value_table arm_fpus
[] =
22108 {"softfpa", FPU_NONE
},
22109 {"fpe", FPU_ARCH_FPE
},
22110 {"fpe2", FPU_ARCH_FPE
},
22111 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
22112 {"fpa", FPU_ARCH_FPA
},
22113 {"fpa10", FPU_ARCH_FPA
},
22114 {"fpa11", FPU_ARCH_FPA
},
22115 {"arm7500fe", FPU_ARCH_FPA
},
22116 {"softvfp", FPU_ARCH_VFP
},
22117 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
22118 {"vfp", FPU_ARCH_VFP_V2
},
22119 {"vfp9", FPU_ARCH_VFP_V2
},
22120 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
22121 {"vfp10", FPU_ARCH_VFP_V2
},
22122 {"vfp10-r0", FPU_ARCH_VFP_V1
},
22123 {"vfpxd", FPU_ARCH_VFP_V1xD
},
22124 {"vfpv2", FPU_ARCH_VFP_V2
},
22125 {"vfpv3", FPU_ARCH_VFP_V3
},
22126 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
22127 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
22128 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
22129 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
22130 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
22131 {"arm1020t", FPU_ARCH_VFP_V1
},
22132 {"arm1020e", FPU_ARCH_VFP_V2
},
22133 {"arm1136jfs", FPU_ARCH_VFP_V2
},
22134 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
22135 {"maverick", FPU_ARCH_MAVERICK
},
22136 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
22137 {"neon-fp16", FPU_ARCH_NEON_FP16
},
22138 {"vfpv4", FPU_ARCH_VFP_V4
},
22139 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
22140 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
22141 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
22142 {NULL
, ARM_ARCH_NONE
}
22145 struct arm_option_value_table
22151 static const struct arm_option_value_table arm_float_abis
[] =
22153 {"hard", ARM_FLOAT_ABI_HARD
},
22154 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
22155 {"soft", ARM_FLOAT_ABI_SOFT
},
22160 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
22161 static const struct arm_option_value_table arm_eabis
[] =
22163 {"gnu", EF_ARM_EABI_UNKNOWN
},
22164 {"4", EF_ARM_EABI_VER4
},
22165 {"5", EF_ARM_EABI_VER5
},
22170 struct arm_long_option_table
22172 char * option
; /* Substring to match. */
22173 char * help
; /* Help information. */
22174 int (* func
) (char * subopt
); /* Function to decode sub-option. */
22175 char * deprecated
; /* If non-null, print this message. */
22179 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
22181 arm_feature_set
*ext_set
= (arm_feature_set
*)
22182 xmalloc (sizeof (arm_feature_set
));
22184 /* Copy the feature set, so that we can modify it. */
22185 *ext_set
= **opt_p
;
22188 while (str
!= NULL
&& *str
!= 0)
22190 const struct arm_option_cpu_value_table
* opt
;
22196 as_bad (_("invalid architectural extension"));
22201 ext
= strchr (str
, '+');
22204 optlen
= ext
- str
;
22206 optlen
= strlen (str
);
22210 as_bad (_("missing architectural extension"));
22214 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
22215 if (strncmp (opt
->name
, str
, optlen
) == 0)
22217 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
22221 if (opt
->name
== NULL
)
22223 as_bad (_("unknown architectural extension `%s'"), str
);
22234 arm_parse_cpu (char * str
)
22236 const struct arm_cpu_option_table
* opt
;
22237 char * ext
= strchr (str
, '+');
22241 optlen
= ext
- str
;
22243 optlen
= strlen (str
);
22247 as_bad (_("missing cpu name `%s'"), str
);
22251 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
22252 if (strncmp (opt
->name
, str
, optlen
) == 0)
22254 mcpu_cpu_opt
= &opt
->value
;
22255 mcpu_fpu_opt
= &opt
->default_fpu
;
22256 if (opt
->canonical_name
)
22257 strcpy (selected_cpu_name
, opt
->canonical_name
);
22262 for (i
= 0; i
< optlen
; i
++)
22263 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22264 selected_cpu_name
[i
] = 0;
22268 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
22273 as_bad (_("unknown cpu `%s'"), str
);
22278 arm_parse_arch (char * str
)
22280 const struct arm_arch_option_table
*opt
;
22281 char *ext
= strchr (str
, '+');
22285 optlen
= ext
- str
;
22287 optlen
= strlen (str
);
22291 as_bad (_("missing architecture name `%s'"), str
);
22295 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
22296 if (streq (opt
->name
, str
))
22298 march_cpu_opt
= &opt
->value
;
22299 march_fpu_opt
= &opt
->default_fpu
;
22300 strcpy (selected_cpu_name
, opt
->name
);
22303 return arm_parse_extension (ext
, &march_cpu_opt
);
22308 as_bad (_("unknown architecture `%s'\n"), str
);
22313 arm_parse_fpu (char * str
)
22315 const struct arm_option_cpu_value_table
* opt
;
22317 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22318 if (streq (opt
->name
, str
))
22320 mfpu_opt
= &opt
->value
;
22324 as_bad (_("unknown floating point format `%s'\n"), str
);
22329 arm_parse_float_abi (char * str
)
22331 const struct arm_option_value_table
* opt
;
22333 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
22334 if (streq (opt
->name
, str
))
22336 mfloat_abi_opt
= opt
->value
;
22340 as_bad (_("unknown floating point abi `%s'\n"), str
);
22346 arm_parse_eabi (char * str
)
22348 const struct arm_option_value_table
*opt
;
22350 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
22351 if (streq (opt
->name
, str
))
22353 meabi_flags
= opt
->value
;
22356 as_bad (_("unknown EABI `%s'\n"), str
);
22362 arm_parse_it_mode (char * str
)
22364 bfd_boolean ret
= TRUE
;
22366 if (streq ("arm", str
))
22367 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
22368 else if (streq ("thumb", str
))
22369 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
22370 else if (streq ("always", str
))
22371 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
22372 else if (streq ("never", str
))
22373 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
22376 as_bad (_("unknown implicit IT mode `%s', should be "\
22377 "arm, thumb, always, or never."), str
);
22384 struct arm_long_option_table arm_long_opts
[] =
22386 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
22387 arm_parse_cpu
, NULL
},
22388 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
22389 arm_parse_arch
, NULL
},
22390 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
22391 arm_parse_fpu
, NULL
},
22392 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
22393 arm_parse_float_abi
, NULL
},
22395 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
22396 arm_parse_eabi
, NULL
},
22398 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
22399 arm_parse_it_mode
, NULL
},
22400 {NULL
, NULL
, 0, NULL
}
22404 md_parse_option (int c
, char * arg
)
22406 struct arm_option_table
*opt
;
22407 const struct arm_legacy_option_table
*fopt
;
22408 struct arm_long_option_table
*lopt
;
22414 target_big_endian
= 1;
22420 target_big_endian
= 0;
22424 case OPTION_FIX_V4BX
:
22429 /* Listing option. Just ignore these, we don't support additional
22434 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22436 if (c
== opt
->option
[0]
22437 && ((arg
== NULL
&& opt
->option
[1] == 0)
22438 || streq (arg
, opt
->option
+ 1)))
22440 /* If the option is deprecated, tell the user. */
22441 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
22442 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22443 arg
? arg
: "", _(opt
->deprecated
));
22445 if (opt
->var
!= NULL
)
22446 *opt
->var
= opt
->value
;
22452 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
22454 if (c
== fopt
->option
[0]
22455 && ((arg
== NULL
&& fopt
->option
[1] == 0)
22456 || streq (arg
, fopt
->option
+ 1)))
22458 /* If the option is deprecated, tell the user. */
22459 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
22460 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22461 arg
? arg
: "", _(fopt
->deprecated
));
22463 if (fopt
->var
!= NULL
)
22464 *fopt
->var
= &fopt
->value
;
22470 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22472 /* These options are expected to have an argument. */
22473 if (c
== lopt
->option
[0]
22475 && strncmp (arg
, lopt
->option
+ 1,
22476 strlen (lopt
->option
+ 1)) == 0)
22478 /* If the option is deprecated, tell the user. */
22479 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
22480 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
22481 _(lopt
->deprecated
));
22483 /* Call the sup-option parser. */
22484 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
22495 md_show_usage (FILE * fp
)
22497 struct arm_option_table
*opt
;
22498 struct arm_long_option_table
*lopt
;
22500 fprintf (fp
, _(" ARM-specific assembler options:\n"));
22502 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22503 if (opt
->help
!= NULL
)
22504 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
22506 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22507 if (lopt
->help
!= NULL
)
22508 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
22512 -EB assemble code for a big-endian cpu\n"));
22517 -EL assemble code for a little-endian cpu\n"));
22521 --fix-v4bx Allow BX in ARMv4 code\n"));
22529 arm_feature_set flags
;
22530 } cpu_arch_ver_table
;
22532 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
22533 least features first. */
22534 static const cpu_arch_ver_table cpu_arch_ver
[] =
22540 {4, ARM_ARCH_V5TE
},
22541 {5, ARM_ARCH_V5TEJ
},
22545 {11, ARM_ARCH_V6M
},
22546 {8, ARM_ARCH_V6T2
},
22547 {10, ARM_ARCH_V7A
},
22548 {10, ARM_ARCH_V7R
},
22549 {10, ARM_ARCH_V7M
},
22553 /* Set an attribute if it has not already been set by the user. */
22555 aeabi_set_attribute_int (int tag
, int value
)
22558 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22559 || !attributes_set_explicitly
[tag
])
22560 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
22564 aeabi_set_attribute_string (int tag
, const char *value
)
22567 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22568 || !attributes_set_explicitly
[tag
])
22569 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
22572 /* Set the public EABI object attributes. */
22574 aeabi_set_public_attributes (void)
22577 arm_feature_set flags
;
22578 arm_feature_set tmp
;
22579 const cpu_arch_ver_table
*p
;
22581 /* Choose the architecture based on the capabilities of the requested cpu
22582 (if any) and/or the instructions actually used. */
22583 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
22584 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
22585 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
22586 /*Allow the user to override the reported architecture. */
22589 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
22590 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
22595 for (p
= cpu_arch_ver
; p
->val
; p
++)
22597 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
22600 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
22604 /* The table lookup above finds the last architecture to contribute
22605 a new feature. Unfortunately, Tag13 is a subset of the union of
22606 v6T2 and v7-M, so it is never seen as contributing a new feature.
22607 We can not search for the last entry which is entirely used,
22608 because if no CPU is specified we build up only those flags
22609 actually used. Perhaps we should separate out the specified
22610 and implicit cases. Avoid taking this path for -march=all by
22611 checking for contradictory v7-A / v7-M features. */
22613 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
22614 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
22615 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
22618 /* Tag_CPU_name. */
22619 if (selected_cpu_name
[0])
22623 q
= selected_cpu_name
;
22624 if (strncmp (q
, "armv", 4) == 0)
22629 for (i
= 0; q
[i
]; i
++)
22630 q
[i
] = TOUPPER (q
[i
]);
22632 aeabi_set_attribute_string (Tag_CPU_name
, q
);
22635 /* Tag_CPU_arch. */
22636 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
22638 /* Tag_CPU_arch_profile. */
22639 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
22640 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
22641 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
22642 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
22643 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
22644 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
22646 /* Tag_ARM_ISA_use. */
22647 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
22649 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
22651 /* Tag_THUMB_ISA_use. */
22652 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
22654 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
22655 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
22657 /* Tag_VFP_arch. */
22658 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
22659 aeabi_set_attribute_int (Tag_VFP_arch
,
22660 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
22662 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
22663 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
22664 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
22665 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
22666 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
22667 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
22668 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
22669 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
22670 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
22672 /* Tag_WMMX_arch. */
22673 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
22674 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
22675 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
22676 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
22678 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
22679 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
22680 aeabi_set_attribute_int
22681 (Tag_Advanced_SIMD_arch
, (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
)
22684 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
22685 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
))
22686 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
22689 /* Add the default contents for the .ARM.attributes section. */
22693 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
22696 aeabi_set_public_attributes ();
22698 #endif /* OBJ_ELF */
22701 /* Parse a .cpu directive. */
22704 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
22706 const struct arm_cpu_option_table
*opt
;
22710 name
= input_line_pointer
;
22711 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22712 input_line_pointer
++;
22713 saved_char
= *input_line_pointer
;
22714 *input_line_pointer
= 0;
22716 /* Skip the first "all" entry. */
22717 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
22718 if (streq (opt
->name
, name
))
22720 mcpu_cpu_opt
= &opt
->value
;
22721 selected_cpu
= opt
->value
;
22722 if (opt
->canonical_name
)
22723 strcpy (selected_cpu_name
, opt
->canonical_name
);
22727 for (i
= 0; opt
->name
[i
]; i
++)
22728 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22729 selected_cpu_name
[i
] = 0;
22731 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22732 *input_line_pointer
= saved_char
;
22733 demand_empty_rest_of_line ();
22736 as_bad (_("unknown cpu `%s'"), name
);
22737 *input_line_pointer
= saved_char
;
22738 ignore_rest_of_line ();
22742 /* Parse a .arch directive. */
22745 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
22747 const struct arm_arch_option_table
*opt
;
22751 name
= input_line_pointer
;
22752 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22753 input_line_pointer
++;
22754 saved_char
= *input_line_pointer
;
22755 *input_line_pointer
= 0;
22757 /* Skip the first "all" entry. */
22758 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
22759 if (streq (opt
->name
, name
))
22761 mcpu_cpu_opt
= &opt
->value
;
22762 selected_cpu
= opt
->value
;
22763 strcpy (selected_cpu_name
, opt
->name
);
22764 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22765 *input_line_pointer
= saved_char
;
22766 demand_empty_rest_of_line ();
22770 as_bad (_("unknown architecture `%s'\n"), name
);
22771 *input_line_pointer
= saved_char
;
22772 ignore_rest_of_line ();
22776 /* Parse a .object_arch directive. */
22779 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
22781 const struct arm_arch_option_table
*opt
;
22785 name
= input_line_pointer
;
22786 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22787 input_line_pointer
++;
22788 saved_char
= *input_line_pointer
;
22789 *input_line_pointer
= 0;
22791 /* Skip the first "all" entry. */
22792 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
22793 if (streq (opt
->name
, name
))
22795 object_arch
= &opt
->value
;
22796 *input_line_pointer
= saved_char
;
22797 demand_empty_rest_of_line ();
22801 as_bad (_("unknown architecture `%s'\n"), name
);
22802 *input_line_pointer
= saved_char
;
22803 ignore_rest_of_line ();
22806 /* Parse a .fpu directive. */
22809 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
22811 const struct arm_option_cpu_value_table
*opt
;
22815 name
= input_line_pointer
;
22816 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22817 input_line_pointer
++;
22818 saved_char
= *input_line_pointer
;
22819 *input_line_pointer
= 0;
22821 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22822 if (streq (opt
->name
, name
))
22824 mfpu_opt
= &opt
->value
;
22825 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22826 *input_line_pointer
= saved_char
;
22827 demand_empty_rest_of_line ();
22831 as_bad (_("unknown floating point format `%s'\n"), name
);
22832 *input_line_pointer
= saved_char
;
22833 ignore_rest_of_line ();
22836 /* Copy symbol information. */
22839 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
22841 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
22845 /* Given a symbolic attribute NAME, return the proper integer value.
22846 Returns -1 if the attribute is not known. */
22849 arm_convert_symbolic_attribute (const char *name
)
22851 static const struct
22856 attribute_table
[] =
22858 /* When you modify this table you should
22859 also modify the list in doc/c-arm.texi. */
22860 #define T(tag) {#tag, tag}
22861 T (Tag_CPU_raw_name
),
22864 T (Tag_CPU_arch_profile
),
22865 T (Tag_ARM_ISA_use
),
22866 T (Tag_THUMB_ISA_use
),
22869 T (Tag_Advanced_SIMD_arch
),
22870 T (Tag_PCS_config
),
22871 T (Tag_ABI_PCS_R9_use
),
22872 T (Tag_ABI_PCS_RW_data
),
22873 T (Tag_ABI_PCS_RO_data
),
22874 T (Tag_ABI_PCS_GOT_use
),
22875 T (Tag_ABI_PCS_wchar_t
),
22876 T (Tag_ABI_FP_rounding
),
22877 T (Tag_ABI_FP_denormal
),
22878 T (Tag_ABI_FP_exceptions
),
22879 T (Tag_ABI_FP_user_exceptions
),
22880 T (Tag_ABI_FP_number_model
),
22881 T (Tag_ABI_align8_needed
),
22882 T (Tag_ABI_align8_preserved
),
22883 T (Tag_ABI_enum_size
),
22884 T (Tag_ABI_HardFP_use
),
22885 T (Tag_ABI_VFP_args
),
22886 T (Tag_ABI_WMMX_args
),
22887 T (Tag_ABI_optimization_goals
),
22888 T (Tag_ABI_FP_optimization_goals
),
22889 T (Tag_compatibility
),
22890 T (Tag_CPU_unaligned_access
),
22891 T (Tag_VFP_HP_extension
),
22892 T (Tag_ABI_FP_16bit_format
),
22893 T (Tag_nodefaults
),
22894 T (Tag_also_compatible_with
),
22895 T (Tag_conformance
),
22897 T (Tag_Virtualization_use
),
22898 T (Tag_MPextension_use
)
22906 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
22907 if (streq (name
, attribute_table
[i
].name
))
22908 return attribute_table
[i
].tag
;
22914 /* Apply sym value for relocations only in the case that
22915 they are for local symbols and you have the respective
22916 architectural feature for blx and simple switches. */
22918 arm_apply_sym_value (struct fix
* fixP
)
22921 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22922 && !S_IS_EXTERNAL (fixP
->fx_addsy
))
22924 switch (fixP
->fx_r_type
)
22926 case BFD_RELOC_ARM_PCREL_BLX
:
22927 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22928 if (ARM_IS_FUNC (fixP
->fx_addsy
))
22932 case BFD_RELOC_ARM_PCREL_CALL
:
22933 case BFD_RELOC_THUMB_PCREL_BLX
:
22934 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
22945 #endif /* OBJ_ELF */