1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant
;
129 static arm_feature_set arm_arch_used
;
130 static arm_feature_set thumb_arch_used
;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26
= FALSE
;
134 static int atpcs
= FALSE
;
135 static int support_interwork
= FALSE
;
136 static int uses_apcs_float
= FALSE
;
137 static int pic_code
= FALSE
;
138 static int fix_v4bx
= FALSE
;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated
= TRUE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
187 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
188 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
189 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
190 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
198 static const arm_feature_set arm_ext_m
=
199 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_V7M
, 0);
201 static const arm_feature_set arm_arch_any
= ARM_ANY
;
202 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
203 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
204 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
206 static const arm_feature_set arm_cext_iwmmxt2
=
207 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
208 static const arm_feature_set arm_cext_iwmmxt
=
209 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
210 static const arm_feature_set arm_cext_xscale
=
211 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
212 static const arm_feature_set arm_cext_maverick
=
213 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
214 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
215 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
216 static const arm_feature_set fpu_vfp_ext_v1xd
=
217 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
218 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
219 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
220 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
221 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
222 static const arm_feature_set fpu_vfp_ext_d32
=
223 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
224 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
225 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
226 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
227 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
228 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
229 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
231 static int mfloat_abi_opt
= -1;
232 /* Record user cpu selection for object attributes. */
233 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
234 /* Must be long enough to hold any of the names in arm_cpus. */
235 static char selected_cpu_name
[16];
238 static int meabi_flags
= EABI_DEFAULT
;
240 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
243 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
248 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
253 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
254 symbolS
* GOT_symbol
;
257 /* 0: assemble for ARM,
258 1: assemble for Thumb,
259 2: assemble for Thumb even though target CPU does not support thumb
261 static int thumb_mode
= 0;
262 /* A value distinct from the possible values for thumb_mode that we
263 can use to record whether thumb_mode has been copied into the
264 tc_frag_data field of a frag. */
265 #define MODE_RECORDED (1 << 4)
267 /* Specifies the intrinsic IT insn behavior mode. */
268 enum implicit_it_mode
270 IMPLICIT_IT_MODE_NEVER
= 0x00,
271 IMPLICIT_IT_MODE_ARM
= 0x01,
272 IMPLICIT_IT_MODE_THUMB
= 0x02,
273 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
275 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
277 /* If unified_syntax is true, we are processing the new unified
278 ARM/Thumb syntax. Important differences from the old ARM mode:
280 - Immediate operands do not require a # prefix.
281 - Conditional affixes always appear at the end of the
282 instruction. (For backward compatibility, those instructions
283 that formerly had them in the middle, continue to accept them
285 - The IT instruction may appear, and if it does is validated
286 against subsequent conditional affixes. It does not generate
289 Important differences from the old Thumb mode:
291 - Immediate operands do not require a # prefix.
292 - Most of the V6T2 instructions are only available in unified mode.
293 - The .N and .W suffixes are recognized and honored (it is an error
294 if they cannot be honored).
295 - All instructions set the flags if and only if they have an 's' affix.
296 - Conditional affixes may be used. They are validated against
297 preceding IT instructions. Unlike ARM mode, you cannot use a
298 conditional affix except in the scope of an IT instruction. */
300 static bfd_boolean unified_syntax
= FALSE
;
315 enum neon_el_type type
;
319 #define NEON_MAX_TYPE_ELS 4
323 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
327 enum it_instruction_type
332 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
333 if inside, should be the last one. */
334 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
335 i.e. BKPT and NOP. */
336 IT_INSN
/* The IT insn has been parsed. */
342 unsigned long instruction
;
346 /* "uncond_value" is set to the value in place of the conditional field in
347 unconditional versions of the instruction, or -1 if nothing is
350 struct neon_type vectype
;
351 /* This does not indicate an actual NEON instruction, only that
352 the mnemonic accepts neon-style type suffixes. */
354 /* Set to the opcode if the instruction needs relaxation.
355 Zero if the instruction is not relaxed. */
359 bfd_reloc_code_real_type type
;
364 enum it_instruction_type it_insn_type
;
370 struct neon_type_el vectype
;
371 unsigned present
: 1; /* Operand present. */
372 unsigned isreg
: 1; /* Operand was a register. */
373 unsigned immisreg
: 1; /* .imm field is a second register. */
374 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
375 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
376 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
377 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
378 instructions. This allows us to disambiguate ARM <-> vector insns. */
379 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
380 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
381 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
382 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
383 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
384 unsigned writeback
: 1; /* Operand has trailing ! */
385 unsigned preind
: 1; /* Preindexed address. */
386 unsigned postind
: 1; /* Postindexed address. */
387 unsigned negative
: 1; /* Index register was negated. */
388 unsigned shifted
: 1; /* Shift applied to operation. */
389 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
393 static struct arm_it inst
;
395 #define NUM_FLOAT_VALS 8
397 const char * fp_const
[] =
399 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
402 /* Number of littlenums required to hold an extended precision number. */
403 #define MAX_LITTLENUMS 6
405 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
415 #define CP_T_X 0x00008000
416 #define CP_T_Y 0x00400000
418 #define CONDS_BIT 0x00100000
419 #define LOAD_BIT 0x00100000
421 #define DOUBLE_LOAD_FLAG 0x00000001
425 const char * template_name
;
429 #define COND_ALWAYS 0xE
433 const char * template_name
;
437 struct asm_barrier_opt
439 const char * template_name
;
443 /* The bit that distinguishes CPSR and SPSR. */
444 #define SPSR_BIT (1 << 22)
446 /* The individual PSR flag bits. */
447 #define PSR_c (1 << 16)
448 #define PSR_x (1 << 17)
449 #define PSR_s (1 << 18)
450 #define PSR_f (1 << 19)
455 bfd_reloc_code_real_type reloc
;
460 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
461 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
466 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
469 /* Bits for DEFINED field in neon_typed_alias. */
470 #define NTA_HASTYPE 1
471 #define NTA_HASINDEX 2
473 struct neon_typed_alias
475 unsigned char defined
;
477 struct neon_type_el eltype
;
480 /* ARM register categories. This includes coprocessor numbers and various
481 architecture extensions' registers. */
507 /* Structure for a hash table entry for a register.
508 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
509 information which states whether a vector type or index is specified (for a
510 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
514 unsigned char number
;
516 unsigned char builtin
;
517 struct neon_typed_alias
* neon
;
520 /* Diagnostics used when we don't get a register of the expected type. */
521 const char * const reg_expected_msgs
[] =
523 N_("ARM register expected"),
524 N_("bad or missing co-processor number"),
525 N_("co-processor register expected"),
526 N_("FPA register expected"),
527 N_("VFP single precision register expected"),
528 N_("VFP/Neon double precision register expected"),
529 N_("Neon quad precision register expected"),
530 N_("VFP single or double precision register expected"),
531 N_("Neon double or quad precision register expected"),
532 N_("VFP single, double or Neon quad precision register expected"),
533 N_("VFP system register expected"),
534 N_("Maverick MVF register expected"),
535 N_("Maverick MVD register expected"),
536 N_("Maverick MVFX register expected"),
537 N_("Maverick MVDX register expected"),
538 N_("Maverick MVAX register expected"),
539 N_("Maverick DSPSC register expected"),
540 N_("iWMMXt data register expected"),
541 N_("iWMMXt control register expected"),
542 N_("iWMMXt scalar register expected"),
543 N_("XScale accumulator register expected"),
546 /* Some well known registers that we refer to directly elsewhere. */
551 /* ARM instructions take 4bytes in the object file, Thumb instructions
557 /* Basic string to match. */
558 const char * template_name
;
560 /* Parameters to instruction. */
561 unsigned int operands
[8];
563 /* Conditional tag - see opcode_lookup. */
564 unsigned int tag
: 4;
566 /* Basic instruction code. */
567 unsigned int avalue
: 28;
569 /* Thumb-format instruction code. */
572 /* Which architecture variant provides this instruction. */
573 const arm_feature_set
* avariant
;
574 const arm_feature_set
* tvariant
;
576 /* Function to call to encode instruction in ARM format. */
577 void (* aencode
) (void);
579 /* Function to call to encode instruction in Thumb format. */
580 void (* tencode
) (void);
583 /* Defines for various bits that we will want to toggle. */
584 #define INST_IMMEDIATE 0x02000000
585 #define OFFSET_REG 0x02000000
586 #define HWOFFSET_IMM 0x00400000
587 #define SHIFT_BY_REG 0x00000010
588 #define PRE_INDEX 0x01000000
589 #define INDEX_UP 0x00800000
590 #define WRITE_BACK 0x00200000
591 #define LDM_TYPE_2_OR_3 0x00400000
592 #define CPSI_MMOD 0x00020000
594 #define LITERAL_MASK 0xf000f000
595 #define OPCODE_MASK 0xfe1fffff
596 #define V4_STR_BIT 0x00000020
598 #define T2_SUBS_PC_LR 0xf3de8f00
600 #define DATA_OP_SHIFT 21
602 #define T2_OPCODE_MASK 0xfe1fffff
603 #define T2_DATA_OP_SHIFT 21
605 /* Codes to distinguish the arithmetic instructions. */
616 #define OPCODE_CMP 10
617 #define OPCODE_CMN 11
618 #define OPCODE_ORR 12
619 #define OPCODE_MOV 13
620 #define OPCODE_BIC 14
621 #define OPCODE_MVN 15
623 #define T2_OPCODE_AND 0
624 #define T2_OPCODE_BIC 1
625 #define T2_OPCODE_ORR 2
626 #define T2_OPCODE_ORN 3
627 #define T2_OPCODE_EOR 4
628 #define T2_OPCODE_ADD 8
629 #define T2_OPCODE_ADC 10
630 #define T2_OPCODE_SBC 11
631 #define T2_OPCODE_SUB 13
632 #define T2_OPCODE_RSB 14
634 #define T_OPCODE_MUL 0x4340
635 #define T_OPCODE_TST 0x4200
636 #define T_OPCODE_CMN 0x42c0
637 #define T_OPCODE_NEG 0x4240
638 #define T_OPCODE_MVN 0x43c0
640 #define T_OPCODE_ADD_R3 0x1800
641 #define T_OPCODE_SUB_R3 0x1a00
642 #define T_OPCODE_ADD_HI 0x4400
643 #define T_OPCODE_ADD_ST 0xb000
644 #define T_OPCODE_SUB_ST 0xb080
645 #define T_OPCODE_ADD_SP 0xa800
646 #define T_OPCODE_ADD_PC 0xa000
647 #define T_OPCODE_ADD_I8 0x3000
648 #define T_OPCODE_SUB_I8 0x3800
649 #define T_OPCODE_ADD_I3 0x1c00
650 #define T_OPCODE_SUB_I3 0x1e00
652 #define T_OPCODE_ASR_R 0x4100
653 #define T_OPCODE_LSL_R 0x4080
654 #define T_OPCODE_LSR_R 0x40c0
655 #define T_OPCODE_ROR_R 0x41c0
656 #define T_OPCODE_ASR_I 0x1000
657 #define T_OPCODE_LSL_I 0x0000
658 #define T_OPCODE_LSR_I 0x0800
660 #define T_OPCODE_MOV_I8 0x2000
661 #define T_OPCODE_CMP_I8 0x2800
662 #define T_OPCODE_CMP_LR 0x4280
663 #define T_OPCODE_MOV_HR 0x4600
664 #define T_OPCODE_CMP_HR 0x4500
666 #define T_OPCODE_LDR_PC 0x4800
667 #define T_OPCODE_LDR_SP 0x9800
668 #define T_OPCODE_STR_SP 0x9000
669 #define T_OPCODE_LDR_IW 0x6800
670 #define T_OPCODE_STR_IW 0x6000
671 #define T_OPCODE_LDR_IH 0x8800
672 #define T_OPCODE_STR_IH 0x8000
673 #define T_OPCODE_LDR_IB 0x7800
674 #define T_OPCODE_STR_IB 0x7000
675 #define T_OPCODE_LDR_RW 0x5800
676 #define T_OPCODE_STR_RW 0x5000
677 #define T_OPCODE_LDR_RH 0x5a00
678 #define T_OPCODE_STR_RH 0x5200
679 #define T_OPCODE_LDR_RB 0x5c00
680 #define T_OPCODE_STR_RB 0x5400
682 #define T_OPCODE_PUSH 0xb400
683 #define T_OPCODE_POP 0xbc00
685 #define T_OPCODE_BRANCH 0xe000
687 #define THUMB_SIZE 2 /* Size of thumb instruction. */
688 #define THUMB_PP_PC_LR 0x0100
689 #define THUMB_LOAD_BIT 0x0800
690 #define THUMB2_LOAD_BIT 0x00100000
692 #define BAD_ARGS _("bad arguments to instruction")
693 #define BAD_SP _("r13 not allowed here")
694 #define BAD_PC _("r15 not allowed here")
695 #define BAD_COND _("instruction cannot be conditional")
696 #define BAD_OVERLAP _("registers may not be the same")
697 #define BAD_HIREG _("lo register required")
698 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
699 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
700 #define BAD_BRANCH _("branch must be last instruction in IT block")
701 #define BAD_NOT_IT _("instruction not allowed in IT block")
702 #define BAD_FPU _("selected FPU does not support instruction")
703 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
704 #define BAD_IT_COND _("incorrect condition in IT block")
705 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
706 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
707 #define BAD_PC_ADDRESSING \
708 _("cannot use register index with PC-relative addressing")
709 #define BAD_PC_WRITEBACK \
710 _("cannot use writeback with PC-relative addressing")
712 static struct hash_control
* arm_ops_hsh
;
713 static struct hash_control
* arm_cond_hsh
;
714 static struct hash_control
* arm_shift_hsh
;
715 static struct hash_control
* arm_psr_hsh
;
716 static struct hash_control
* arm_v7m_psr_hsh
;
717 static struct hash_control
* arm_reg_hsh
;
718 static struct hash_control
* arm_reloc_hsh
;
719 static struct hash_control
* arm_barrier_opt_hsh
;
721 /* Stuff needed to resolve the label ambiguity
730 symbolS
* last_label_seen
;
731 static int label_is_thumb_function_name
= FALSE
;
733 /* Literal pool structure. Held on a per-section
734 and per-sub-section basis. */
736 #define MAX_LITERAL_POOL_SIZE 1024
737 typedef struct literal_pool
739 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
740 unsigned int next_free_entry
;
745 struct literal_pool
* next
;
748 /* Pointer to a linked list of literal pools. */
749 literal_pool
* list_of_pools
= NULL
;
752 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
754 static struct current_it now_it
;
758 now_it_compatible (int cond
)
760 return (cond
& ~1) == (now_it
.cc
& ~1);
764 conditional_insn (void)
766 return inst
.cond
!= COND_ALWAYS
;
769 static int in_it_block (void);
771 static int handle_it_state (void);
773 static void force_automatic_it_block_close (void);
775 static void it_fsm_post_encode (void);
777 #define set_it_insn_type(type) \
780 inst.it_insn_type = type; \
781 if (handle_it_state () == FAIL) \
786 #define set_it_insn_type_nonvoid(type, failret) \
789 inst.it_insn_type = type; \
790 if (handle_it_state () == FAIL) \
795 #define set_it_insn_type_last() \
798 if (inst.cond == COND_ALWAYS) \
799 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
801 set_it_insn_type (INSIDE_IT_LAST_INSN); \
807 /* This array holds the chars that always start a comment. If the
808 pre-processor is disabled, these aren't very useful. */
809 const char comment_chars
[] = "@";
811 /* This array holds the chars that only start a comment at the beginning of
812 a line. If the line seems to have the form '# 123 filename'
813 .line and .file directives will appear in the pre-processed output. */
814 /* Note that input_file.c hand checks for '#' at the beginning of the
815 first line of the input file. This is because the compiler outputs
816 #NO_APP at the beginning of its output. */
817 /* Also note that comments like this one will always work. */
818 const char line_comment_chars
[] = "#";
820 const char line_separator_chars
[] = ";";
822 /* Chars that can be used to separate mant
823 from exp in floating point numbers. */
824 const char EXP_CHARS
[] = "eE";
826 /* Chars that mean this number is a floating point constant. */
830 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
832 /* Prefix characters that indicate the start of an immediate
834 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
836 /* Separator character handling. */
838 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
841 skip_past_char (char ** str
, char c
)
852 #define skip_past_comma(str) skip_past_char (str, ',')
854 /* Arithmetic expressions (possibly involving symbols). */
856 /* Return TRUE if anything in the expression is a bignum. */
859 walk_no_bignums (symbolS
* sp
)
861 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
864 if (symbol_get_value_expression (sp
)->X_add_symbol
)
866 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
867 || (symbol_get_value_expression (sp
)->X_op_symbol
868 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
874 static int in_my_get_expression
= 0;
876 /* Third argument to my_get_expression. */
877 #define GE_NO_PREFIX 0
878 #define GE_IMM_PREFIX 1
879 #define GE_OPT_PREFIX 2
880 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
881 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
882 #define GE_OPT_PREFIX_BIG 3
885 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
890 /* In unified syntax, all prefixes are optional. */
892 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
897 case GE_NO_PREFIX
: break;
899 if (!is_immediate_prefix (**str
))
901 inst
.error
= _("immediate expression requires a # prefix");
907 case GE_OPT_PREFIX_BIG
:
908 if (is_immediate_prefix (**str
))
914 memset (ep
, 0, sizeof (expressionS
));
916 save_in
= input_line_pointer
;
917 input_line_pointer
= *str
;
918 in_my_get_expression
= 1;
919 seg
= expression (ep
);
920 in_my_get_expression
= 0;
922 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
924 /* We found a bad or missing expression in md_operand(). */
925 *str
= input_line_pointer
;
926 input_line_pointer
= save_in
;
927 if (inst
.error
== NULL
)
928 inst
.error
= (ep
->X_op
== O_absent
929 ? _("missing expression") :_("bad expression"));
934 if (seg
!= absolute_section
935 && seg
!= text_section
936 && seg
!= data_section
937 && seg
!= bss_section
938 && seg
!= undefined_section
)
940 inst
.error
= _("bad segment");
941 *str
= input_line_pointer
;
942 input_line_pointer
= save_in
;
947 /* Get rid of any bignums now, so that we don't generate an error for which
948 we can't establish a line number later on. Big numbers are never valid
949 in instructions, which is where this routine is always called. */
950 if (prefix_mode
!= GE_OPT_PREFIX_BIG
951 && (ep
->X_op
== O_big
953 && (walk_no_bignums (ep
->X_add_symbol
)
955 && walk_no_bignums (ep
->X_op_symbol
))))))
957 inst
.error
= _("invalid constant");
958 *str
= input_line_pointer
;
959 input_line_pointer
= save_in
;
963 *str
= input_line_pointer
;
964 input_line_pointer
= save_in
;
968 /* Turn a string in input_line_pointer into a floating point constant
969 of type TYPE, and store the appropriate bytes in *LITP. The number
970 of LITTLENUMS emitted is stored in *SIZEP. An error message is
971 returned, or NULL on OK.
973 Note that fp constants aren't represent in the normal way on the ARM.
974 In big endian mode, things are as expected. However, in little endian
975 mode fp constants are big-endian word-wise, and little-endian byte-wise
976 within the words. For example, (double) 1.1 in big endian mode is
977 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
978 the byte sequence 99 99 f1 3f 9a 99 99 99.
980 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
983 md_atof (int type
, char * litP
, int * sizeP
)
986 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1018 return _("Unrecognized or unsupported floating point constant");
1021 t
= atof_ieee (input_line_pointer
, type
, words
);
1023 input_line_pointer
= t
;
1024 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1026 if (target_big_endian
)
1028 for (i
= 0; i
< prec
; i
++)
1030 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1031 litP
+= sizeof (LITTLENUM_TYPE
);
1036 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1037 for (i
= prec
- 1; i
>= 0; i
--)
1039 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1040 litP
+= sizeof (LITTLENUM_TYPE
);
1043 /* For a 4 byte float the order of elements in `words' is 1 0.
1044 For an 8 byte float the order is 1 0 3 2. */
1045 for (i
= 0; i
< prec
; i
+= 2)
1047 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1048 sizeof (LITTLENUM_TYPE
));
1049 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1050 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1051 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1058 /* We handle all bad expressions here, so that we can report the faulty
1059 instruction in the error message. */
1061 md_operand (expressionS
* exp
)
1063 if (in_my_get_expression
)
1064 exp
->X_op
= O_illegal
;
1067 /* Immediate values. */
1069 /* Generic immediate-value read function for use in directives.
1070 Accepts anything that 'expression' can fold to a constant.
1071 *val receives the number. */
1074 immediate_for_directive (int *val
)
1077 exp
.X_op
= O_illegal
;
1079 if (is_immediate_prefix (*input_line_pointer
))
1081 input_line_pointer
++;
1085 if (exp
.X_op
!= O_constant
)
1087 as_bad (_("expected #constant"));
1088 ignore_rest_of_line ();
1091 *val
= exp
.X_add_number
;
1096 /* Register parsing. */
1098 /* Generic register parser. CCP points to what should be the
1099 beginning of a register name. If it is indeed a valid register
1100 name, advance CCP over it and return the reg_entry structure;
1101 otherwise return NULL. Does not issue diagnostics. */
1103 static struct reg_entry
*
1104 arm_reg_parse_multi (char **ccp
)
1108 struct reg_entry
*reg
;
1110 #ifdef REGISTER_PREFIX
1111 if (*start
!= REGISTER_PREFIX
)
1115 #ifdef OPTIONAL_REGISTER_PREFIX
1116 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1121 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1126 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1128 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1138 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1139 enum arm_reg_type type
)
1141 /* Alternative syntaxes are accepted for a few register classes. */
1148 /* Generic coprocessor register names are allowed for these. */
1149 if (reg
&& reg
->type
== REG_TYPE_CN
)
1154 /* For backward compatibility, a bare number is valid here. */
1156 unsigned long processor
= strtoul (start
, ccp
, 10);
1157 if (*ccp
!= start
&& processor
<= 15)
1161 case REG_TYPE_MMXWC
:
1162 /* WC includes WCG. ??? I'm not sure this is true for all
1163 instructions that take WC registers. */
1164 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1175 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1176 return value is the register number or FAIL. */
1179 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1182 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1185 /* Do not allow a scalar (reg+index) to parse as a register. */
1186 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1189 if (reg
&& reg
->type
== type
)
1192 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1199 /* Parse a Neon type specifier. *STR should point at the leading '.'
1200 character. Does no verification at this stage that the type fits the opcode
1207 Can all be legally parsed by this function.
1209 Fills in neon_type struct pointer with parsed information, and updates STR
1210 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1211 type, FAIL if not. */
1214 parse_neon_type (struct neon_type
*type
, char **str
)
1221 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1223 enum neon_el_type thistype
= NT_untyped
;
1224 unsigned thissize
= -1u;
1231 /* Just a size without an explicit type. */
1235 switch (TOLOWER (*ptr
))
1237 case 'i': thistype
= NT_integer
; break;
1238 case 'f': thistype
= NT_float
; break;
1239 case 'p': thistype
= NT_poly
; break;
1240 case 's': thistype
= NT_signed
; break;
1241 case 'u': thistype
= NT_unsigned
; break;
1243 thistype
= NT_float
;
1248 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1254 /* .f is an abbreviation for .f32. */
1255 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1260 thissize
= strtoul (ptr
, &ptr
, 10);
1262 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1265 as_bad (_("bad size %d in type specifier"), thissize
);
1273 type
->el
[type
->elems
].type
= thistype
;
1274 type
->el
[type
->elems
].size
= thissize
;
1279 /* Empty/missing type is not a successful parse. */
1280 if (type
->elems
== 0)
1288 /* Errors may be set multiple times during parsing or bit encoding
1289 (particularly in the Neon bits), but usually the earliest error which is set
1290 will be the most meaningful. Avoid overwriting it with later (cascading)
1291 errors by calling this function. */
1294 first_error (const char *err
)
1300 /* Parse a single type, e.g. ".s32", leading period included. */
1302 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1305 struct neon_type optype
;
1309 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1311 if (optype
.elems
== 1)
1312 *vectype
= optype
.el
[0];
1315 first_error (_("only one type should be specified for operand"));
1321 first_error (_("vector type expected"));
1333 /* Special meanings for indices (which have a range of 0-7), which will fit into
1336 #define NEON_ALL_LANES 15
1337 #define NEON_INTERLEAVE_LANES 14
1339 /* Parse either a register or a scalar, with an optional type. Return the
1340 register number, and optionally fill in the actual type of the register
1341 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1342 type/index information in *TYPEINFO. */
1345 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1346 enum arm_reg_type
*rtype
,
1347 struct neon_typed_alias
*typeinfo
)
1350 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1351 struct neon_typed_alias atype
;
1352 struct neon_type_el parsetype
;
1356 atype
.eltype
.type
= NT_invtype
;
1357 atype
.eltype
.size
= -1;
1359 /* Try alternate syntax for some types of register. Note these are mutually
1360 exclusive with the Neon syntax extensions. */
1363 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1371 /* Undo polymorphism when a set of register types may be accepted. */
1372 if ((type
== REG_TYPE_NDQ
1373 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1374 || (type
== REG_TYPE_VFSD
1375 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1376 || (type
== REG_TYPE_NSDQ
1377 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1378 || reg
->type
== REG_TYPE_NQ
))
1379 || (type
== REG_TYPE_MMXWC
1380 && (reg
->type
== REG_TYPE_MMXWCG
)))
1381 type
= (enum arm_reg_type
) reg
->type
;
1383 if (type
!= reg
->type
)
1389 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1391 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1393 first_error (_("can't redefine type for operand"));
1396 atype
.defined
|= NTA_HASTYPE
;
1397 atype
.eltype
= parsetype
;
1400 if (skip_past_char (&str
, '[') == SUCCESS
)
1402 if (type
!= REG_TYPE_VFD
)
1404 first_error (_("only D registers may be indexed"));
1408 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1410 first_error (_("can't change index for operand"));
1414 atype
.defined
|= NTA_HASINDEX
;
1416 if (skip_past_char (&str
, ']') == SUCCESS
)
1417 atype
.index
= NEON_ALL_LANES
;
1422 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1424 if (exp
.X_op
!= O_constant
)
1426 first_error (_("constant expression required"));
1430 if (skip_past_char (&str
, ']') == FAIL
)
1433 atype
.index
= exp
.X_add_number
;
1448 /* Like arm_reg_parse, but allow allow the following extra features:
1449 - If RTYPE is non-zero, return the (possibly restricted) type of the
1450 register (e.g. Neon double or quad reg when either has been requested).
1451 - If this is a Neon vector type with additional type information, fill
1452 in the struct pointed to by VECTYPE (if non-NULL).
1453 This function will fault on encountering a scalar. */
1456 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1457 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1459 struct neon_typed_alias atype
;
1461 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1466 /* Do not allow a scalar (reg+index) to parse as a register. */
1467 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1469 first_error (_("register operand expected, but got scalar"));
1474 *vectype
= atype
.eltype
;
1481 #define NEON_SCALAR_REG(X) ((X) >> 4)
1482 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1484 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1485 have enough information to be able to do a good job bounds-checking. So, we
1486 just do easy checks here, and do further checks later. */
1489 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1493 struct neon_typed_alias atype
;
1495 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1497 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1500 if (atype
.index
== NEON_ALL_LANES
)
1502 first_error (_("scalar must have an index"));
1505 else if (atype
.index
>= 64 / elsize
)
1507 first_error (_("scalar index out of range"));
1512 *type
= atype
.eltype
;
1516 return reg
* 16 + atype
.index
;
1519 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1522 parse_reg_list (char ** strp
)
1524 char * str
= * strp
;
1528 /* We come back here if we get ranges concatenated by '+' or '|'. */
1543 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1545 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1555 first_error (_("bad range in register list"));
1559 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1561 if (range
& (1 << i
))
1563 (_("Warning: duplicated register (r%d) in register list"),
1571 if (range
& (1 << reg
))
1572 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1574 else if (reg
<= cur_reg
)
1575 as_tsktsk (_("Warning: register range not in ascending order"));
1580 while (skip_past_comma (&str
) != FAIL
1581 || (in_range
= 1, *str
++ == '-'));
1586 first_error (_("missing `}'"));
1594 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1597 if (exp
.X_op
== O_constant
)
1599 if (exp
.X_add_number
1600 != (exp
.X_add_number
& 0x0000ffff))
1602 inst
.error
= _("invalid register mask");
1606 if ((range
& exp
.X_add_number
) != 0)
1608 int regno
= range
& exp
.X_add_number
;
1611 regno
= (1 << regno
) - 1;
1613 (_("Warning: duplicated register (r%d) in register list"),
1617 range
|= exp
.X_add_number
;
1621 if (inst
.reloc
.type
!= 0)
1623 inst
.error
= _("expression too complex");
1627 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1628 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1629 inst
.reloc
.pc_rel
= 0;
1633 if (*str
== '|' || *str
== '+')
1639 while (another_range
);
1645 /* Types of registers in a list. */
1654 /* Parse a VFP register list. If the string is invalid return FAIL.
1655 Otherwise return the number of registers, and set PBASE to the first
1656 register. Parses registers of type ETYPE.
1657 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1658 - Q registers can be used to specify pairs of D registers
1659 - { } can be omitted from around a singleton register list
1660 FIXME: This is not implemented, as it would require backtracking in
1663 This could be done (the meaning isn't really ambiguous), but doesn't
1664 fit in well with the current parsing framework.
1665 - 32 D registers may be used (also true for VFPv3).
1666 FIXME: Types are ignored in these register lists, which is probably a
1670 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1675 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1679 unsigned long mask
= 0;
1684 inst
.error
= _("expecting {");
1693 regtype
= REG_TYPE_VFS
;
1698 regtype
= REG_TYPE_VFD
;
1701 case REGLIST_NEON_D
:
1702 regtype
= REG_TYPE_NDQ
;
1706 if (etype
!= REGLIST_VFP_S
)
1708 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1709 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1713 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1716 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1723 base_reg
= max_regs
;
1727 int setmask
= 1, addregs
= 1;
1729 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1731 if (new_base
== FAIL
)
1733 first_error (_(reg_expected_msgs
[regtype
]));
1737 if (new_base
>= max_regs
)
1739 first_error (_("register out of range in list"));
1743 /* Note: a value of 2 * n is returned for the register Q<n>. */
1744 if (regtype
== REG_TYPE_NQ
)
1750 if (new_base
< base_reg
)
1751 base_reg
= new_base
;
1753 if (mask
& (setmask
<< new_base
))
1755 first_error (_("invalid register list"));
1759 if ((mask
>> new_base
) != 0 && ! warned
)
1761 as_tsktsk (_("register list not in ascending order"));
1765 mask
|= setmask
<< new_base
;
1768 if (*str
== '-') /* We have the start of a range expression */
1774 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1777 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1781 if (high_range
>= max_regs
)
1783 first_error (_("register out of range in list"));
1787 if (regtype
== REG_TYPE_NQ
)
1788 high_range
= high_range
+ 1;
1790 if (high_range
<= new_base
)
1792 inst
.error
= _("register range not in ascending order");
1796 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1798 if (mask
& (setmask
<< new_base
))
1800 inst
.error
= _("invalid register list");
1804 mask
|= setmask
<< new_base
;
1809 while (skip_past_comma (&str
) != FAIL
);
1813 /* Sanity check -- should have raised a parse error above. */
1814 if (count
== 0 || count
> max_regs
)
1819 /* Final test -- the registers must be consecutive. */
1821 for (i
= 0; i
< count
; i
++)
1823 if ((mask
& (1u << i
)) == 0)
1825 inst
.error
= _("non-contiguous register range");
1835 /* True if two alias types are the same. */
1838 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1846 if (a
->defined
!= b
->defined
)
1849 if ((a
->defined
& NTA_HASTYPE
) != 0
1850 && (a
->eltype
.type
!= b
->eltype
.type
1851 || a
->eltype
.size
!= b
->eltype
.size
))
1854 if ((a
->defined
& NTA_HASINDEX
) != 0
1855 && (a
->index
!= b
->index
))
1861 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1862 The base register is put in *PBASE.
1863 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1865 The register stride (minus one) is put in bit 4 of the return value.
1866 Bits [6:5] encode the list length (minus one).
1867 The type of the list elements is put in *ELTYPE, if non-NULL. */
1869 #define NEON_LANE(X) ((X) & 0xf)
1870 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1871 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1874 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1875 struct neon_type_el
*eltype
)
1882 int leading_brace
= 0;
1883 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1885 const char *const incr_error
= _("register stride must be 1 or 2");
1886 const char *const type_error
= _("mismatched element/structure types in list");
1887 struct neon_typed_alias firsttype
;
1889 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1894 struct neon_typed_alias atype
;
1895 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1899 first_error (_(reg_expected_msgs
[rtype
]));
1906 if (rtype
== REG_TYPE_NQ
)
1913 else if (reg_incr
== -1)
1915 reg_incr
= getreg
- base_reg
;
1916 if (reg_incr
< 1 || reg_incr
> 2)
1918 first_error (_(incr_error
));
1922 else if (getreg
!= base_reg
+ reg_incr
* count
)
1924 first_error (_(incr_error
));
1928 if (! neon_alias_types_same (&atype
, &firsttype
))
1930 first_error (_(type_error
));
1934 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1938 struct neon_typed_alias htype
;
1939 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1941 lane
= NEON_INTERLEAVE_LANES
;
1942 else if (lane
!= NEON_INTERLEAVE_LANES
)
1944 first_error (_(type_error
));
1949 else if (reg_incr
!= 1)
1951 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1955 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1958 first_error (_(reg_expected_msgs
[rtype
]));
1961 if (! neon_alias_types_same (&htype
, &firsttype
))
1963 first_error (_(type_error
));
1966 count
+= hireg
+ dregs
- getreg
;
1970 /* If we're using Q registers, we can't use [] or [n] syntax. */
1971 if (rtype
== REG_TYPE_NQ
)
1977 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1981 else if (lane
!= atype
.index
)
1983 first_error (_(type_error
));
1987 else if (lane
== -1)
1988 lane
= NEON_INTERLEAVE_LANES
;
1989 else if (lane
!= NEON_INTERLEAVE_LANES
)
1991 first_error (_(type_error
));
1996 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1998 /* No lane set by [x]. We must be interleaving structures. */
2000 lane
= NEON_INTERLEAVE_LANES
;
2003 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2004 || (count
> 1 && reg_incr
== -1))
2006 first_error (_("error parsing element/structure list"));
2010 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2012 first_error (_("expected }"));
2020 *eltype
= firsttype
.eltype
;
2025 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2028 /* Parse an explicit relocation suffix on an expression. This is
2029 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2030 arm_reloc_hsh contains no entries, so this function can only
2031 succeed if there is no () after the word. Returns -1 on error,
2032 BFD_RELOC_UNUSED if there wasn't any suffix. */
2034 parse_reloc (char **str
)
2036 struct reloc_entry
*r
;
2040 return BFD_RELOC_UNUSED
;
2045 while (*q
&& *q
!= ')' && *q
!= ',')
2050 if ((r
= (struct reloc_entry
*)
2051 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2058 /* Directives: register aliases. */
2060 static struct reg_entry
*
2061 insert_reg_alias (char *str
, int number
, int type
)
2063 struct reg_entry
*new_reg
;
2066 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2068 if (new_reg
->builtin
)
2069 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2071 /* Only warn about a redefinition if it's not defined as the
2073 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2074 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2079 name
= xstrdup (str
);
2080 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2082 new_reg
->name
= name
;
2083 new_reg
->number
= number
;
2084 new_reg
->type
= type
;
2085 new_reg
->builtin
= FALSE
;
2086 new_reg
->neon
= NULL
;
2088 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2095 insert_neon_reg_alias (char *str
, int number
, int type
,
2096 struct neon_typed_alias
*atype
)
2098 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2102 first_error (_("attempt to redefine typed alias"));
2108 reg
->neon
= (struct neon_typed_alias
*)
2109 xmalloc (sizeof (struct neon_typed_alias
));
2110 *reg
->neon
= *atype
;
2114 /* Look for the .req directive. This is of the form:
2116 new_register_name .req existing_register_name
2118 If we find one, or if it looks sufficiently like one that we want to
2119 handle any error here, return TRUE. Otherwise return FALSE. */
2122 create_register_alias (char * newname
, char *p
)
2124 struct reg_entry
*old
;
2125 char *oldname
, *nbuf
;
2128 /* The input scrubber ensures that whitespace after the mnemonic is
2129 collapsed to single spaces. */
2131 if (strncmp (oldname
, " .req ", 6) != 0)
2135 if (*oldname
== '\0')
2138 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2141 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2145 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2146 the desired alias name, and p points to its end. If not, then
2147 the desired alias name is in the global original_case_string. */
2148 #ifdef TC_CASE_SENSITIVE
2151 newname
= original_case_string
;
2152 nlen
= strlen (newname
);
2155 nbuf
= (char *) alloca (nlen
+ 1);
2156 memcpy (nbuf
, newname
, nlen
);
2159 /* Create aliases under the new name as stated; an all-lowercase
2160 version of the new name; and an all-uppercase version of the new
2162 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2164 for (p
= nbuf
; *p
; p
++)
2167 if (strncmp (nbuf
, newname
, nlen
))
2169 /* If this attempt to create an additional alias fails, do not bother
2170 trying to create the all-lower case alias. We will fail and issue
2171 a second, duplicate error message. This situation arises when the
2172 programmer does something like:
2175 The second .req creates the "Foo" alias but then fails to create
2176 the artificial FOO alias because it has already been created by the
2178 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2182 for (p
= nbuf
; *p
; p
++)
2185 if (strncmp (nbuf
, newname
, nlen
))
2186 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2192 /* Create a Neon typed/indexed register alias using directives, e.g.:
2197 These typed registers can be used instead of the types specified after the
2198 Neon mnemonic, so long as all operands given have types. Types can also be
2199 specified directly, e.g.:
2200 vadd d0.s32, d1.s32, d2.s32 */
2203 create_neon_reg_alias (char *newname
, char *p
)
2205 enum arm_reg_type basetype
;
2206 struct reg_entry
*basereg
;
2207 struct reg_entry mybasereg
;
2208 struct neon_type ntype
;
2209 struct neon_typed_alias typeinfo
;
2210 char *namebuf
, *nameend
;
2213 typeinfo
.defined
= 0;
2214 typeinfo
.eltype
.type
= NT_invtype
;
2215 typeinfo
.eltype
.size
= -1;
2216 typeinfo
.index
= -1;
2220 if (strncmp (p
, " .dn ", 5) == 0)
2221 basetype
= REG_TYPE_VFD
;
2222 else if (strncmp (p
, " .qn ", 5) == 0)
2223 basetype
= REG_TYPE_NQ
;
2232 basereg
= arm_reg_parse_multi (&p
);
2234 if (basereg
&& basereg
->type
!= basetype
)
2236 as_bad (_("bad type for register"));
2240 if (basereg
== NULL
)
2243 /* Try parsing as an integer. */
2244 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2245 if (exp
.X_op
!= O_constant
)
2247 as_bad (_("expression must be constant"));
2250 basereg
= &mybasereg
;
2251 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2257 typeinfo
= *basereg
->neon
;
2259 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2261 /* We got a type. */
2262 if (typeinfo
.defined
& NTA_HASTYPE
)
2264 as_bad (_("can't redefine the type of a register alias"));
2268 typeinfo
.defined
|= NTA_HASTYPE
;
2269 if (ntype
.elems
!= 1)
2271 as_bad (_("you must specify a single type only"));
2274 typeinfo
.eltype
= ntype
.el
[0];
2277 if (skip_past_char (&p
, '[') == SUCCESS
)
2280 /* We got a scalar index. */
2282 if (typeinfo
.defined
& NTA_HASINDEX
)
2284 as_bad (_("can't redefine the index of a scalar alias"));
2288 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2290 if (exp
.X_op
!= O_constant
)
2292 as_bad (_("scalar index must be constant"));
2296 typeinfo
.defined
|= NTA_HASINDEX
;
2297 typeinfo
.index
= exp
.X_add_number
;
2299 if (skip_past_char (&p
, ']') == FAIL
)
2301 as_bad (_("expecting ]"));
2306 namelen
= nameend
- newname
;
2307 namebuf
= (char *) alloca (namelen
+ 1);
2308 strncpy (namebuf
, newname
, namelen
);
2309 namebuf
[namelen
] = '\0';
2311 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2312 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2314 /* Insert name in all uppercase. */
2315 for (p
= namebuf
; *p
; p
++)
2318 if (strncmp (namebuf
, newname
, namelen
))
2319 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2320 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2322 /* Insert name in all lowercase. */
2323 for (p
= namebuf
; *p
; p
++)
2326 if (strncmp (namebuf
, newname
, namelen
))
2327 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2328 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2333 /* Should never be called, as .req goes between the alias and the
2334 register name, not at the beginning of the line. */
2337 s_req (int a ATTRIBUTE_UNUSED
)
2339 as_bad (_("invalid syntax for .req directive"));
2343 s_dn (int a ATTRIBUTE_UNUSED
)
2345 as_bad (_("invalid syntax for .dn directive"));
2349 s_qn (int a ATTRIBUTE_UNUSED
)
2351 as_bad (_("invalid syntax for .qn directive"));
2354 /* The .unreq directive deletes an alias which was previously defined
2355 by .req. For example:
2361 s_unreq (int a ATTRIBUTE_UNUSED
)
2366 name
= input_line_pointer
;
2368 while (*input_line_pointer
!= 0
2369 && *input_line_pointer
!= ' '
2370 && *input_line_pointer
!= '\n')
2371 ++input_line_pointer
;
2373 saved_char
= *input_line_pointer
;
2374 *input_line_pointer
= 0;
2377 as_bad (_("invalid syntax for .unreq directive"));
2380 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2384 as_bad (_("unknown register alias '%s'"), name
);
2385 else if (reg
->builtin
)
2386 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2393 hash_delete (arm_reg_hsh
, name
, FALSE
);
2394 free ((char *) reg
->name
);
2399 /* Also locate the all upper case and all lower case versions.
2400 Do not complain if we cannot find one or the other as it
2401 was probably deleted above. */
2403 nbuf
= strdup (name
);
2404 for (p
= nbuf
; *p
; p
++)
2406 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2409 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2410 free ((char *) reg
->name
);
2416 for (p
= nbuf
; *p
; p
++)
2418 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2421 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2422 free ((char *) reg
->name
);
2432 *input_line_pointer
= saved_char
;
2433 demand_empty_rest_of_line ();
2436 /* Directives: Instruction set selection. */
2439 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2440 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2441 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2442 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2444 /* Create a new mapping symbol for the transition to STATE. */
2447 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2450 const char * symname
;
2457 type
= BSF_NO_FLAGS
;
2461 type
= BSF_NO_FLAGS
;
2465 type
= BSF_NO_FLAGS
;
2471 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2472 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2477 THUMB_SET_FUNC (symbolP
, 0);
2478 ARM_SET_THUMB (symbolP
, 0);
2479 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2483 THUMB_SET_FUNC (symbolP
, 1);
2484 ARM_SET_THUMB (symbolP
, 1);
2485 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2493 /* Save the mapping symbols for future reference. Also check that
2494 we do not place two mapping symbols at the same offset within a
2495 frag. We'll handle overlap between frags in
2496 check_mapping_symbols.
2498 If .fill or other data filling directive generates zero sized data,
2499 the mapping symbol for the following code will have the same value
2500 as the one generated for the data filling directive. In this case,
2501 we replace the old symbol with the new one at the same address. */
2504 if (frag
->tc_frag_data
.first_map
!= NULL
)
2506 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2507 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2509 frag
->tc_frag_data
.first_map
= symbolP
;
2511 if (frag
->tc_frag_data
.last_map
!= NULL
)
2513 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2514 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2515 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2517 frag
->tc_frag_data
.last_map
= symbolP
;
2520 /* We must sometimes convert a region marked as code to data during
2521 code alignment, if an odd number of bytes have to be padded. The
2522 code mapping symbol is pushed to an aligned address. */
2525 insert_data_mapping_symbol (enum mstate state
,
2526 valueT value
, fragS
*frag
, offsetT bytes
)
2528 /* If there was already a mapping symbol, remove it. */
2529 if (frag
->tc_frag_data
.last_map
!= NULL
2530 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2532 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2536 know (frag
->tc_frag_data
.first_map
== symp
);
2537 frag
->tc_frag_data
.first_map
= NULL
;
2539 frag
->tc_frag_data
.last_map
= NULL
;
2540 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2543 make_mapping_symbol (MAP_DATA
, value
, frag
);
2544 make_mapping_symbol (state
, value
+ bytes
, frag
);
2547 static void mapping_state_2 (enum mstate state
, int max_chars
);
2549 /* Set the mapping state to STATE. Only call this when about to
2550 emit some STATE bytes to the file. */
2553 mapping_state (enum mstate state
)
2555 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2557 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2559 if (mapstate
== state
)
2560 /* The mapping symbol has already been emitted.
2561 There is nothing else to do. */
2563 else if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2564 /* This case will be evaluated later in the next else. */
2566 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2567 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2569 /* Only add the symbol if the offset is > 0:
2570 if we're at the first frag, check it's size > 0;
2571 if we're not at the first frag, then for sure
2572 the offset is > 0. */
2573 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2574 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2577 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2580 mapping_state_2 (state
, 0);
2584 /* Same as mapping_state, but MAX_CHARS bytes have already been
2585 allocated. Put the mapping symbol that far back. */
2588 mapping_state_2 (enum mstate state
, int max_chars
)
2590 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2592 if (!SEG_NORMAL (now_seg
))
2595 if (mapstate
== state
)
2596 /* The mapping symbol has already been emitted.
2597 There is nothing else to do. */
2600 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2601 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2604 #define mapping_state(x) ((void)0)
2605 #define mapping_state_2(x, y) ((void)0)
2608 /* Find the real, Thumb encoded start of a Thumb function. */
2612 find_real_start (symbolS
* symbolP
)
2615 const char * name
= S_GET_NAME (symbolP
);
2616 symbolS
* new_target
;
2618 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2619 #define STUB_NAME ".real_start_of"
2624 /* The compiler may generate BL instructions to local labels because
2625 it needs to perform a branch to a far away location. These labels
2626 do not have a corresponding ".real_start_of" label. We check
2627 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2628 the ".real_start_of" convention for nonlocal branches. */
2629 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2632 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2633 new_target
= symbol_find (real_start
);
2635 if (new_target
== NULL
)
2637 as_warn (_("Failed to find real start of function: %s\n"), name
);
2638 new_target
= symbolP
;
2646 opcode_select (int width
)
2653 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2654 as_bad (_("selected processor does not support THUMB opcodes"));
2657 /* No need to force the alignment, since we will have been
2658 coming from ARM mode, which is word-aligned. */
2659 record_alignment (now_seg
, 1);
2666 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2667 as_bad (_("selected processor does not support ARM opcodes"));
2672 frag_align (2, 0, 0);
2674 record_alignment (now_seg
, 1);
2679 as_bad (_("invalid instruction size selected (%d)"), width
);
2684 s_arm (int ignore ATTRIBUTE_UNUSED
)
2687 demand_empty_rest_of_line ();
2691 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2694 demand_empty_rest_of_line ();
2698 s_code (int unused ATTRIBUTE_UNUSED
)
2702 temp
= get_absolute_expression ();
2707 opcode_select (temp
);
2711 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2716 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2718 /* If we are not already in thumb mode go into it, EVEN if
2719 the target processor does not support thumb instructions.
2720 This is used by gcc/config/arm/lib1funcs.asm for example
2721 to compile interworking support functions even if the
2722 target processor should not support interworking. */
2726 record_alignment (now_seg
, 1);
2729 demand_empty_rest_of_line ();
2733 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2737 /* The following label is the name/address of the start of a Thumb function.
2738 We need to know this for the interworking support. */
2739 label_is_thumb_function_name
= TRUE
;
2742 /* Perform a .set directive, but also mark the alias as
2743 being a thumb function. */
2746 s_thumb_set (int equiv
)
2748 /* XXX the following is a duplicate of the code for s_set() in read.c
2749 We cannot just call that code as we need to get at the symbol that
2756 /* Especial apologies for the random logic:
2757 This just grew, and could be parsed much more simply!
2759 name
= input_line_pointer
;
2760 delim
= get_symbol_end ();
2761 end_name
= input_line_pointer
;
2764 if (*input_line_pointer
!= ',')
2767 as_bad (_("expected comma after name \"%s\""), name
);
2769 ignore_rest_of_line ();
2773 input_line_pointer
++;
2776 if (name
[0] == '.' && name
[1] == '\0')
2778 /* XXX - this should not happen to .thumb_set. */
2782 if ((symbolP
= symbol_find (name
)) == NULL
2783 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2786 /* When doing symbol listings, play games with dummy fragments living
2787 outside the normal fragment chain to record the file and line info
2789 if (listing
& LISTING_SYMBOLS
)
2791 extern struct list_info_struct
* listing_tail
;
2792 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2794 memset (dummy_frag
, 0, sizeof (fragS
));
2795 dummy_frag
->fr_type
= rs_fill
;
2796 dummy_frag
->line
= listing_tail
;
2797 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2798 dummy_frag
->fr_symbol
= symbolP
;
2802 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2805 /* "set" symbols are local unless otherwise specified. */
2806 SF_SET_LOCAL (symbolP
);
2807 #endif /* OBJ_COFF */
2808 } /* Make a new symbol. */
2810 symbol_table_insert (symbolP
);
2815 && S_IS_DEFINED (symbolP
)
2816 && S_GET_SEGMENT (symbolP
) != reg_section
)
2817 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2819 pseudo_set (symbolP
);
2821 demand_empty_rest_of_line ();
2823 /* XXX Now we come to the Thumb specific bit of code. */
2825 THUMB_SET_FUNC (symbolP
, 1);
2826 ARM_SET_THUMB (symbolP
, 1);
2827 #if defined OBJ_ELF || defined OBJ_COFF
2828 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2832 /* Directives: Mode selection. */
2834 /* .syntax [unified|divided] - choose the new unified syntax
2835 (same for Arm and Thumb encoding, modulo slight differences in what
2836 can be represented) or the old divergent syntax for each mode. */
2838 s_syntax (int unused ATTRIBUTE_UNUSED
)
2842 name
= input_line_pointer
;
2843 delim
= get_symbol_end ();
2845 if (!strcasecmp (name
, "unified"))
2846 unified_syntax
= TRUE
;
2847 else if (!strcasecmp (name
, "divided"))
2848 unified_syntax
= FALSE
;
2851 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2854 *input_line_pointer
= delim
;
2855 demand_empty_rest_of_line ();
2858 /* Directives: sectioning and alignment. */
2860 /* Same as s_align_ptwo but align 0 => align 2. */
2863 s_align (int unused ATTRIBUTE_UNUSED
)
2868 long max_alignment
= 15;
2870 temp
= get_absolute_expression ();
2871 if (temp
> max_alignment
)
2872 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2875 as_bad (_("alignment negative. 0 assumed."));
2879 if (*input_line_pointer
== ',')
2881 input_line_pointer
++;
2882 temp_fill
= get_absolute_expression ();
2894 /* Only make a frag if we HAVE to. */
2895 if (temp
&& !need_pass_2
)
2897 if (!fill_p
&& subseg_text_p (now_seg
))
2898 frag_align_code (temp
, 0);
2900 frag_align (temp
, (int) temp_fill
, 0);
2902 demand_empty_rest_of_line ();
2904 record_alignment (now_seg
, temp
);
2908 s_bss (int ignore ATTRIBUTE_UNUSED
)
2910 /* We don't support putting frags in the BSS segment, we fake it by
2911 marking in_bss, then looking at s_skip for clues. */
2912 subseg_set (bss_section
, 0);
2913 demand_empty_rest_of_line ();
2915 #ifdef md_elf_section_change_hook
2916 md_elf_section_change_hook ();
2921 s_even (int ignore ATTRIBUTE_UNUSED
)
2923 /* Never make frag if expect extra pass. */
2925 frag_align (1, 0, 0);
2927 record_alignment (now_seg
, 1);
2929 demand_empty_rest_of_line ();
2932 /* Directives: Literal pools. */
2934 static literal_pool
*
2935 find_literal_pool (void)
2937 literal_pool
* pool
;
2939 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2941 if (pool
->section
== now_seg
2942 && pool
->sub_section
== now_subseg
)
2949 static literal_pool
*
2950 find_or_make_literal_pool (void)
2952 /* Next literal pool ID number. */
2953 static unsigned int latest_pool_num
= 1;
2954 literal_pool
* pool
;
2956 pool
= find_literal_pool ();
2960 /* Create a new pool. */
2961 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
2965 pool
->next_free_entry
= 0;
2966 pool
->section
= now_seg
;
2967 pool
->sub_section
= now_subseg
;
2968 pool
->next
= list_of_pools
;
2969 pool
->symbol
= NULL
;
2971 /* Add it to the list. */
2972 list_of_pools
= pool
;
2975 /* New pools, and emptied pools, will have a NULL symbol. */
2976 if (pool
->symbol
== NULL
)
2978 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2979 (valueT
) 0, &zero_address_frag
);
2980 pool
->id
= latest_pool_num
++;
2987 /* Add the literal in the global 'inst'
2988 structure to the relevant literal pool. */
2991 add_to_lit_pool (void)
2993 literal_pool
* pool
;
2996 pool
= find_or_make_literal_pool ();
2998 /* Check if this literal value is already in the pool. */
2999 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3001 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3002 && (inst
.reloc
.exp
.X_op
== O_constant
)
3003 && (pool
->literals
[entry
].X_add_number
3004 == inst
.reloc
.exp
.X_add_number
)
3005 && (pool
->literals
[entry
].X_unsigned
3006 == inst
.reloc
.exp
.X_unsigned
))
3009 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3010 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3011 && (pool
->literals
[entry
].X_add_number
3012 == inst
.reloc
.exp
.X_add_number
)
3013 && (pool
->literals
[entry
].X_add_symbol
3014 == inst
.reloc
.exp
.X_add_symbol
)
3015 && (pool
->literals
[entry
].X_op_symbol
3016 == inst
.reloc
.exp
.X_op_symbol
))
3020 /* Do we need to create a new entry? */
3021 if (entry
== pool
->next_free_entry
)
3023 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3025 inst
.error
= _("literal pool overflow");
3029 pool
->literals
[entry
] = inst
.reloc
.exp
;
3030 pool
->next_free_entry
+= 1;
3033 inst
.reloc
.exp
.X_op
= O_symbol
;
3034 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3035 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3040 /* Can't use symbol_new here, so have to create a symbol and then at
3041 a later date assign it a value. Thats what these functions do. */
3044 symbol_locate (symbolS
* symbolP
,
3045 const char * name
, /* It is copied, the caller can modify. */
3046 segT segment
, /* Segment identifier (SEG_<something>). */
3047 valueT valu
, /* Symbol value. */
3048 fragS
* frag
) /* Associated fragment. */
3050 unsigned int name_length
;
3051 char * preserved_copy_of_name
;
3053 name_length
= strlen (name
) + 1; /* +1 for \0. */
3054 obstack_grow (¬es
, name
, name_length
);
3055 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3057 #ifdef tc_canonicalize_symbol_name
3058 preserved_copy_of_name
=
3059 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3062 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3064 S_SET_SEGMENT (symbolP
, segment
);
3065 S_SET_VALUE (symbolP
, valu
);
3066 symbol_clear_list_pointers (symbolP
);
3068 symbol_set_frag (symbolP
, frag
);
3070 /* Link to end of symbol chain. */
3072 extern int symbol_table_frozen
;
3074 if (symbol_table_frozen
)
3078 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3080 obj_symbol_new_hook (symbolP
);
3082 #ifdef tc_symbol_new_hook
3083 tc_symbol_new_hook (symbolP
);
3087 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3088 #endif /* DEBUG_SYMS */
3093 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3096 literal_pool
* pool
;
3099 pool
= find_literal_pool ();
3101 || pool
->symbol
== NULL
3102 || pool
->next_free_entry
== 0)
3105 mapping_state (MAP_DATA
);
3107 /* Align pool as you have word accesses.
3108 Only make a frag if we have to. */
3110 frag_align (2, 0, 0);
3112 record_alignment (now_seg
, 2);
3114 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3116 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3117 (valueT
) frag_now_fix (), frag_now
);
3118 symbol_table_insert (pool
->symbol
);
3120 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3122 #if defined OBJ_COFF || defined OBJ_ELF
3123 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3126 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3127 /* First output the expression in the instruction to the pool. */
3128 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3130 /* Mark the pool as empty. */
3131 pool
->next_free_entry
= 0;
3132 pool
->symbol
= NULL
;
3136 /* Forward declarations for functions below, in the MD interface
3138 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3139 static valueT
create_unwind_entry (int);
3140 static void start_unwind_section (const segT
, int);
3141 static void add_unwind_opcode (valueT
, int);
3142 static void flush_pending_unwind (void);
3144 /* Directives: Data. */
3147 s_arm_elf_cons (int nbytes
)
3151 #ifdef md_flush_pending_output
3152 md_flush_pending_output ();
3155 if (is_it_end_of_statement ())
3157 demand_empty_rest_of_line ();
3161 #ifdef md_cons_align
3162 md_cons_align (nbytes
);
3165 mapping_state (MAP_DATA
);
3169 char *base
= input_line_pointer
;
3173 if (exp
.X_op
!= O_symbol
)
3174 emit_expr (&exp
, (unsigned int) nbytes
);
3177 char *before_reloc
= input_line_pointer
;
3178 reloc
= parse_reloc (&input_line_pointer
);
3181 as_bad (_("unrecognized relocation suffix"));
3182 ignore_rest_of_line ();
3185 else if (reloc
== BFD_RELOC_UNUSED
)
3186 emit_expr (&exp
, (unsigned int) nbytes
);
3189 reloc_howto_type
*howto
= (reloc_howto_type
*)
3190 bfd_reloc_type_lookup (stdoutput
,
3191 (bfd_reloc_code_real_type
) reloc
);
3192 int size
= bfd_get_reloc_size (howto
);
3194 if (reloc
== BFD_RELOC_ARM_PLT32
)
3196 as_bad (_("(plt) is only valid on branch targets"));
3197 reloc
= BFD_RELOC_UNUSED
;
3202 as_bad (_("%s relocations do not fit in %d bytes"),
3203 howto
->name
, nbytes
);
3206 /* We've parsed an expression stopping at O_symbol.
3207 But there may be more expression left now that we
3208 have parsed the relocation marker. Parse it again.
3209 XXX Surely there is a cleaner way to do this. */
3210 char *p
= input_line_pointer
;
3212 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3213 memcpy (save_buf
, base
, input_line_pointer
- base
);
3214 memmove (base
+ (input_line_pointer
- before_reloc
),
3215 base
, before_reloc
- base
);
3217 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3219 memcpy (base
, save_buf
, p
- base
);
3221 offset
= nbytes
- size
;
3222 p
= frag_more ((int) nbytes
);
3223 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3224 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3229 while (*input_line_pointer
++ == ',');
3231 /* Put terminator back into stream. */
3232 input_line_pointer
--;
3233 demand_empty_rest_of_line ();
3236 /* Emit an expression containing a 32-bit thumb instruction.
3237 Implementation based on put_thumb32_insn. */
3240 emit_thumb32_expr (expressionS
* exp
)
3242 expressionS exp_high
= *exp
;
3244 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3245 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3246 exp
->X_add_number
&= 0xffff;
3247 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3250 /* Guess the instruction size based on the opcode. */
3253 thumb_insn_size (int opcode
)
3255 if ((unsigned int) opcode
< 0xe800u
)
3257 else if ((unsigned int) opcode
>= 0xe8000000u
)
3264 emit_insn (expressionS
*exp
, int nbytes
)
3268 if (exp
->X_op
== O_constant
)
3273 size
= thumb_insn_size (exp
->X_add_number
);
3277 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3279 as_bad (_(".inst.n operand too big. "\
3280 "Use .inst.w instead"));
3285 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3286 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3288 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3290 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3291 emit_thumb32_expr (exp
);
3293 emit_expr (exp
, (unsigned int) size
);
3295 it_fsm_post_encode ();
3299 as_bad (_("cannot determine Thumb instruction size. " \
3300 "Use .inst.n/.inst.w instead"));
3303 as_bad (_("constant expression required"));
3308 /* Like s_arm_elf_cons but do not use md_cons_align and
3309 set the mapping state to MAP_ARM/MAP_THUMB. */
3312 s_arm_elf_inst (int nbytes
)
3314 if (is_it_end_of_statement ())
3316 demand_empty_rest_of_line ();
3320 /* Calling mapping_state () here will not change ARM/THUMB,
3321 but will ensure not to be in DATA state. */
3324 mapping_state (MAP_THUMB
);
3329 as_bad (_("width suffixes are invalid in ARM mode"));
3330 ignore_rest_of_line ();
3336 mapping_state (MAP_ARM
);
3345 if (! emit_insn (& exp
, nbytes
))
3347 ignore_rest_of_line ();
3351 while (*input_line_pointer
++ == ',');
3353 /* Put terminator back into stream. */
3354 input_line_pointer
--;
3355 demand_empty_rest_of_line ();
3358 /* Parse a .rel31 directive. */
3361 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3368 if (*input_line_pointer
== '1')
3369 highbit
= 0x80000000;
3370 else if (*input_line_pointer
!= '0')
3371 as_bad (_("expected 0 or 1"));
3373 input_line_pointer
++;
3374 if (*input_line_pointer
!= ',')
3375 as_bad (_("missing comma"));
3376 input_line_pointer
++;
3378 #ifdef md_flush_pending_output
3379 md_flush_pending_output ();
3382 #ifdef md_cons_align
3386 mapping_state (MAP_DATA
);
3391 md_number_to_chars (p
, highbit
, 4);
3392 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3393 BFD_RELOC_ARM_PREL31
);
3395 demand_empty_rest_of_line ();
3398 /* Directives: AEABI stack-unwind tables. */
3400 /* Parse an unwind_fnstart directive. Simply records the current location. */
3403 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3405 demand_empty_rest_of_line ();
3406 if (unwind
.proc_start
)
3408 as_bad (_("duplicate .fnstart directive"));
3412 /* Mark the start of the function. */
3413 unwind
.proc_start
= expr_build_dot ();
3415 /* Reset the rest of the unwind info. */
3416 unwind
.opcode_count
= 0;
3417 unwind
.table_entry
= NULL
;
3418 unwind
.personality_routine
= NULL
;
3419 unwind
.personality_index
= -1;
3420 unwind
.frame_size
= 0;
3421 unwind
.fp_offset
= 0;
3422 unwind
.fp_reg
= REG_SP
;
3424 unwind
.sp_restored
= 0;
3428 /* Parse a handlerdata directive. Creates the exception handling table entry
3429 for the function. */
3432 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3434 demand_empty_rest_of_line ();
3435 if (!unwind
.proc_start
)
3436 as_bad (MISSING_FNSTART
);
3438 if (unwind
.table_entry
)
3439 as_bad (_("duplicate .handlerdata directive"));
3441 create_unwind_entry (1);
3444 /* Parse an unwind_fnend directive. Generates the index table entry. */
3447 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3452 unsigned int marked_pr_dependency
;
3454 demand_empty_rest_of_line ();
3456 if (!unwind
.proc_start
)
3458 as_bad (_(".fnend directive without .fnstart"));
3462 /* Add eh table entry. */
3463 if (unwind
.table_entry
== NULL
)
3464 val
= create_unwind_entry (0);
3468 /* Add index table entry. This is two words. */
3469 start_unwind_section (unwind
.saved_seg
, 1);
3470 frag_align (2, 0, 0);
3471 record_alignment (now_seg
, 2);
3473 ptr
= frag_more (8);
3474 where
= frag_now_fix () - 8;
3476 /* Self relative offset of the function start. */
3477 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3478 BFD_RELOC_ARM_PREL31
);
3480 /* Indicate dependency on EHABI-defined personality routines to the
3481 linker, if it hasn't been done already. */
3482 marked_pr_dependency
3483 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3484 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3485 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3487 static const char *const name
[] =
3489 "__aeabi_unwind_cpp_pr0",
3490 "__aeabi_unwind_cpp_pr1",
3491 "__aeabi_unwind_cpp_pr2"
3493 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3494 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3495 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3496 |= 1 << unwind
.personality_index
;
3500 /* Inline exception table entry. */
3501 md_number_to_chars (ptr
+ 4, val
, 4);
3503 /* Self relative offset of the table entry. */
3504 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3505 BFD_RELOC_ARM_PREL31
);
3507 /* Restore the original section. */
3508 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3510 unwind
.proc_start
= NULL
;
3514 /* Parse an unwind_cantunwind directive. */
3517 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3519 demand_empty_rest_of_line ();
3520 if (!unwind
.proc_start
)
3521 as_bad (MISSING_FNSTART
);
3523 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3524 as_bad (_("personality routine specified for cantunwind frame"));
3526 unwind
.personality_index
= -2;
3530 /* Parse a personalityindex directive. */
3533 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3537 if (!unwind
.proc_start
)
3538 as_bad (MISSING_FNSTART
);
3540 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3541 as_bad (_("duplicate .personalityindex directive"));
3545 if (exp
.X_op
!= O_constant
3546 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3548 as_bad (_("bad personality routine number"));
3549 ignore_rest_of_line ();
3553 unwind
.personality_index
= exp
.X_add_number
;
3555 demand_empty_rest_of_line ();
3559 /* Parse a personality directive. */
3562 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3566 if (!unwind
.proc_start
)
3567 as_bad (MISSING_FNSTART
);
3569 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3570 as_bad (_("duplicate .personality directive"));
3572 name
= input_line_pointer
;
3573 c
= get_symbol_end ();
3574 p
= input_line_pointer
;
3575 unwind
.personality_routine
= symbol_find_or_make (name
);
3577 demand_empty_rest_of_line ();
3581 /* Parse a directive saving core registers. */
3584 s_arm_unwind_save_core (void)
3590 range
= parse_reg_list (&input_line_pointer
);
3593 as_bad (_("expected register list"));
3594 ignore_rest_of_line ();
3598 demand_empty_rest_of_line ();
3600 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3601 into .unwind_save {..., sp...}. We aren't bothered about the value of
3602 ip because it is clobbered by calls. */
3603 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3604 && (range
& 0x3000) == 0x1000)
3606 unwind
.opcode_count
--;
3607 unwind
.sp_restored
= 0;
3608 range
= (range
| 0x2000) & ~0x1000;
3609 unwind
.pending_offset
= 0;
3615 /* See if we can use the short opcodes. These pop a block of up to 8
3616 registers starting with r4, plus maybe r14. */
3617 for (n
= 0; n
< 8; n
++)
3619 /* Break at the first non-saved register. */
3620 if ((range
& (1 << (n
+ 4))) == 0)
3623 /* See if there are any other bits set. */
3624 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3626 /* Use the long form. */
3627 op
= 0x8000 | ((range
>> 4) & 0xfff);
3628 add_unwind_opcode (op
, 2);
3632 /* Use the short form. */
3634 op
= 0xa8; /* Pop r14. */
3636 op
= 0xa0; /* Do not pop r14. */
3638 add_unwind_opcode (op
, 1);
3645 op
= 0xb100 | (range
& 0xf);
3646 add_unwind_opcode (op
, 2);
3649 /* Record the number of bytes pushed. */
3650 for (n
= 0; n
< 16; n
++)
3652 if (range
& (1 << n
))
3653 unwind
.frame_size
+= 4;
3658 /* Parse a directive saving FPA registers. */
3661 s_arm_unwind_save_fpa (int reg
)
3667 /* Get Number of registers to transfer. */
3668 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3671 exp
.X_op
= O_illegal
;
3673 if (exp
.X_op
!= O_constant
)
3675 as_bad (_("expected , <constant>"));
3676 ignore_rest_of_line ();
3680 num_regs
= exp
.X_add_number
;
3682 if (num_regs
< 1 || num_regs
> 4)
3684 as_bad (_("number of registers must be in the range [1:4]"));
3685 ignore_rest_of_line ();
3689 demand_empty_rest_of_line ();
3694 op
= 0xb4 | (num_regs
- 1);
3695 add_unwind_opcode (op
, 1);
3700 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3701 add_unwind_opcode (op
, 2);
3703 unwind
.frame_size
+= num_regs
* 12;
3707 /* Parse a directive saving VFP registers for ARMv6 and above. */
3710 s_arm_unwind_save_vfp_armv6 (void)
3715 int num_vfpv3_regs
= 0;
3716 int num_regs_below_16
;
3718 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3721 as_bad (_("expected register list"));
3722 ignore_rest_of_line ();
3726 demand_empty_rest_of_line ();
3728 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3729 than FSTMX/FLDMX-style ones). */
3731 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3733 num_vfpv3_regs
= count
;
3734 else if (start
+ count
> 16)
3735 num_vfpv3_regs
= start
+ count
- 16;
3737 if (num_vfpv3_regs
> 0)
3739 int start_offset
= start
> 16 ? start
- 16 : 0;
3740 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3741 add_unwind_opcode (op
, 2);
3744 /* Generate opcode for registers numbered in the range 0 .. 15. */
3745 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3746 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3747 if (num_regs_below_16
> 0)
3749 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3750 add_unwind_opcode (op
, 2);
3753 unwind
.frame_size
+= count
* 8;
3757 /* Parse a directive saving VFP registers for pre-ARMv6. */
3760 s_arm_unwind_save_vfp (void)
3766 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3769 as_bad (_("expected register list"));
3770 ignore_rest_of_line ();
3774 demand_empty_rest_of_line ();
3779 op
= 0xb8 | (count
- 1);
3780 add_unwind_opcode (op
, 1);
3785 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3786 add_unwind_opcode (op
, 2);
3788 unwind
.frame_size
+= count
* 8 + 4;
3792 /* Parse a directive saving iWMMXt data registers. */
3795 s_arm_unwind_save_mmxwr (void)
3803 if (*input_line_pointer
== '{')
3804 input_line_pointer
++;
3808 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3812 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3817 as_tsktsk (_("register list not in ascending order"));
3820 if (*input_line_pointer
== '-')
3822 input_line_pointer
++;
3823 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3826 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3829 else if (reg
>= hi_reg
)
3831 as_bad (_("bad register range"));
3834 for (; reg
< hi_reg
; reg
++)
3838 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3840 if (*input_line_pointer
== '}')
3841 input_line_pointer
++;
3843 demand_empty_rest_of_line ();
3845 /* Generate any deferred opcodes because we're going to be looking at
3847 flush_pending_unwind ();
3849 for (i
= 0; i
< 16; i
++)
3851 if (mask
& (1 << i
))
3852 unwind
.frame_size
+= 8;
3855 /* Attempt to combine with a previous opcode. We do this because gcc
3856 likes to output separate unwind directives for a single block of
3858 if (unwind
.opcode_count
> 0)
3860 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3861 if ((i
& 0xf8) == 0xc0)
3864 /* Only merge if the blocks are contiguous. */
3867 if ((mask
& 0xfe00) == (1 << 9))
3869 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3870 unwind
.opcode_count
--;
3873 else if (i
== 6 && unwind
.opcode_count
>= 2)
3875 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3879 op
= 0xffff << (reg
- 1);
3881 && ((mask
& op
) == (1u << (reg
- 1))))
3883 op
= (1 << (reg
+ i
+ 1)) - 1;
3884 op
&= ~((1 << reg
) - 1);
3886 unwind
.opcode_count
-= 2;
3893 /* We want to generate opcodes in the order the registers have been
3894 saved, ie. descending order. */
3895 for (reg
= 15; reg
>= -1; reg
--)
3897 /* Save registers in blocks. */
3899 || !(mask
& (1 << reg
)))
3901 /* We found an unsaved reg. Generate opcodes to save the
3908 op
= 0xc0 | (hi_reg
- 10);
3909 add_unwind_opcode (op
, 1);
3914 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3915 add_unwind_opcode (op
, 2);
3924 ignore_rest_of_line ();
3928 s_arm_unwind_save_mmxwcg (void)
3935 if (*input_line_pointer
== '{')
3936 input_line_pointer
++;
3940 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3944 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3950 as_tsktsk (_("register list not in ascending order"));
3953 if (*input_line_pointer
== '-')
3955 input_line_pointer
++;
3956 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3959 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3962 else if (reg
>= hi_reg
)
3964 as_bad (_("bad register range"));
3967 for (; reg
< hi_reg
; reg
++)
3971 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3973 if (*input_line_pointer
== '}')
3974 input_line_pointer
++;
3976 demand_empty_rest_of_line ();
3978 /* Generate any deferred opcodes because we're going to be looking at
3980 flush_pending_unwind ();
3982 for (reg
= 0; reg
< 16; reg
++)
3984 if (mask
& (1 << reg
))
3985 unwind
.frame_size
+= 4;
3988 add_unwind_opcode (op
, 2);
3991 ignore_rest_of_line ();
3995 /* Parse an unwind_save directive.
3996 If the argument is non-zero, this is a .vsave directive. */
3999 s_arm_unwind_save (int arch_v6
)
4002 struct reg_entry
*reg
;
4003 bfd_boolean had_brace
= FALSE
;
4005 if (!unwind
.proc_start
)
4006 as_bad (MISSING_FNSTART
);
4008 /* Figure out what sort of save we have. */
4009 peek
= input_line_pointer
;
4017 reg
= arm_reg_parse_multi (&peek
);
4021 as_bad (_("register expected"));
4022 ignore_rest_of_line ();
4031 as_bad (_("FPA .unwind_save does not take a register list"));
4032 ignore_rest_of_line ();
4035 input_line_pointer
= peek
;
4036 s_arm_unwind_save_fpa (reg
->number
);
4039 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4042 s_arm_unwind_save_vfp_armv6 ();
4044 s_arm_unwind_save_vfp ();
4046 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4047 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4050 as_bad (_(".unwind_save does not support this kind of register"));
4051 ignore_rest_of_line ();
4056 /* Parse an unwind_movsp directive. */
4059 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4065 if (!unwind
.proc_start
)
4066 as_bad (MISSING_FNSTART
);
4068 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4071 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4072 ignore_rest_of_line ();
4076 /* Optional constant. */
4077 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4079 if (immediate_for_directive (&offset
) == FAIL
)
4085 demand_empty_rest_of_line ();
4087 if (reg
== REG_SP
|| reg
== REG_PC
)
4089 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4093 if (unwind
.fp_reg
!= REG_SP
)
4094 as_bad (_("unexpected .unwind_movsp directive"));
4096 /* Generate opcode to restore the value. */
4098 add_unwind_opcode (op
, 1);
4100 /* Record the information for later. */
4101 unwind
.fp_reg
= reg
;
4102 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4103 unwind
.sp_restored
= 1;
4106 /* Parse an unwind_pad directive. */
4109 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4113 if (!unwind
.proc_start
)
4114 as_bad (MISSING_FNSTART
);
4116 if (immediate_for_directive (&offset
) == FAIL
)
4121 as_bad (_("stack increment must be multiple of 4"));
4122 ignore_rest_of_line ();
4126 /* Don't generate any opcodes, just record the details for later. */
4127 unwind
.frame_size
+= offset
;
4128 unwind
.pending_offset
+= offset
;
4130 demand_empty_rest_of_line ();
4133 /* Parse an unwind_setfp directive. */
4136 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4142 if (!unwind
.proc_start
)
4143 as_bad (MISSING_FNSTART
);
4145 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4146 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4149 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4151 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4153 as_bad (_("expected <reg>, <reg>"));
4154 ignore_rest_of_line ();
4158 /* Optional constant. */
4159 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4161 if (immediate_for_directive (&offset
) == FAIL
)
4167 demand_empty_rest_of_line ();
4169 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4171 as_bad (_("register must be either sp or set by a previous"
4172 "unwind_movsp directive"));
4176 /* Don't generate any opcodes, just record the information for later. */
4177 unwind
.fp_reg
= fp_reg
;
4179 if (sp_reg
== REG_SP
)
4180 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4182 unwind
.fp_offset
-= offset
;
4185 /* Parse an unwind_raw directive. */
4188 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4191 /* This is an arbitrary limit. */
4192 unsigned char op
[16];
4195 if (!unwind
.proc_start
)
4196 as_bad (MISSING_FNSTART
);
4199 if (exp
.X_op
== O_constant
4200 && skip_past_comma (&input_line_pointer
) != FAIL
)
4202 unwind
.frame_size
+= exp
.X_add_number
;
4206 exp
.X_op
= O_illegal
;
4208 if (exp
.X_op
!= O_constant
)
4210 as_bad (_("expected <offset>, <opcode>"));
4211 ignore_rest_of_line ();
4217 /* Parse the opcode. */
4222 as_bad (_("unwind opcode too long"));
4223 ignore_rest_of_line ();
4225 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4227 as_bad (_("invalid unwind opcode"));
4228 ignore_rest_of_line ();
4231 op
[count
++] = exp
.X_add_number
;
4233 /* Parse the next byte. */
4234 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4240 /* Add the opcode bytes in reverse order. */
4242 add_unwind_opcode (op
[count
], 1);
4244 demand_empty_rest_of_line ();
4248 /* Parse a .eabi_attribute directive. */
4251 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4253 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4255 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4256 attributes_set_explicitly
[tag
] = 1;
4258 #endif /* OBJ_ELF */
4260 static void s_arm_arch (int);
4261 static void s_arm_object_arch (int);
4262 static void s_arm_cpu (int);
4263 static void s_arm_fpu (int);
4268 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4275 if (exp
.X_op
== O_symbol
)
4276 exp
.X_op
= O_secrel
;
4278 emit_expr (&exp
, 4);
4280 while (*input_line_pointer
++ == ',');
4282 input_line_pointer
--;
4283 demand_empty_rest_of_line ();
4287 /* This table describes all the machine specific pseudo-ops the assembler
4288 has to support. The fields are:
4289 pseudo-op name without dot
4290 function to call to execute this pseudo-op
4291 Integer arg to pass to the function. */
4293 const pseudo_typeS md_pseudo_table
[] =
4295 /* Never called because '.req' does not start a line. */
4296 { "req", s_req
, 0 },
4297 /* Following two are likewise never called. */
4300 { "unreq", s_unreq
, 0 },
4301 { "bss", s_bss
, 0 },
4302 { "align", s_align
, 0 },
4303 { "arm", s_arm
, 0 },
4304 { "thumb", s_thumb
, 0 },
4305 { "code", s_code
, 0 },
4306 { "force_thumb", s_force_thumb
, 0 },
4307 { "thumb_func", s_thumb_func
, 0 },
4308 { "thumb_set", s_thumb_set
, 0 },
4309 { "even", s_even
, 0 },
4310 { "ltorg", s_ltorg
, 0 },
4311 { "pool", s_ltorg
, 0 },
4312 { "syntax", s_syntax
, 0 },
4313 { "cpu", s_arm_cpu
, 0 },
4314 { "arch", s_arm_arch
, 0 },
4315 { "object_arch", s_arm_object_arch
, 0 },
4316 { "fpu", s_arm_fpu
, 0 },
4318 { "word", s_arm_elf_cons
, 4 },
4319 { "long", s_arm_elf_cons
, 4 },
4320 { "inst.n", s_arm_elf_inst
, 2 },
4321 { "inst.w", s_arm_elf_inst
, 4 },
4322 { "inst", s_arm_elf_inst
, 0 },
4323 { "rel31", s_arm_rel31
, 0 },
4324 { "fnstart", s_arm_unwind_fnstart
, 0 },
4325 { "fnend", s_arm_unwind_fnend
, 0 },
4326 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4327 { "personality", s_arm_unwind_personality
, 0 },
4328 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4329 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4330 { "save", s_arm_unwind_save
, 0 },
4331 { "vsave", s_arm_unwind_save
, 1 },
4332 { "movsp", s_arm_unwind_movsp
, 0 },
4333 { "pad", s_arm_unwind_pad
, 0 },
4334 { "setfp", s_arm_unwind_setfp
, 0 },
4335 { "unwind_raw", s_arm_unwind_raw
, 0 },
4336 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4340 /* These are used for dwarf. */
4344 /* These are used for dwarf2. */
4345 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4346 { "loc", dwarf2_directive_loc
, 0 },
4347 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4349 { "extend", float_cons
, 'x' },
4350 { "ldouble", float_cons
, 'x' },
4351 { "packed", float_cons
, 'p' },
4353 {"secrel32", pe_directive_secrel
, 0},
4358 /* Parser functions used exclusively in instruction operands. */
4360 /* Generic immediate-value read function for use in insn parsing.
4361 STR points to the beginning of the immediate (the leading #);
4362 VAL receives the value; if the value is outside [MIN, MAX]
4363 issue an error. PREFIX_OPT is true if the immediate prefix is
4367 parse_immediate (char **str
, int *val
, int min
, int max
,
4368 bfd_boolean prefix_opt
)
4371 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4372 if (exp
.X_op
!= O_constant
)
4374 inst
.error
= _("constant expression required");
4378 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4380 inst
.error
= _("immediate value out of range");
4384 *val
= exp
.X_add_number
;
4388 /* Less-generic immediate-value read function with the possibility of loading a
4389 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4390 instructions. Puts the result directly in inst.operands[i]. */
4393 parse_big_immediate (char **str
, int i
)
4398 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4400 if (exp
.X_op
== O_constant
)
4402 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4403 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4404 O_constant. We have to be careful not to break compilation for
4405 32-bit X_add_number, though. */
4406 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4408 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4409 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4410 inst
.operands
[i
].regisimm
= 1;
4413 else if (exp
.X_op
== O_big
4414 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4415 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4417 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4418 /* Bignums have their least significant bits in
4419 generic_bignum[0]. Make sure we put 32 bits in imm and
4420 32 bits in reg, in a (hopefully) portable way. */
4421 gas_assert (parts
!= 0);
4422 inst
.operands
[i
].imm
= 0;
4423 for (j
= 0; j
< parts
; j
++, idx
++)
4424 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4425 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4426 inst
.operands
[i
].reg
= 0;
4427 for (j
= 0; j
< parts
; j
++, idx
++)
4428 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4429 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4430 inst
.operands
[i
].regisimm
= 1;
4440 /* Returns the pseudo-register number of an FPA immediate constant,
4441 or FAIL if there isn't a valid constant here. */
4444 parse_fpa_immediate (char ** str
)
4446 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4452 /* First try and match exact strings, this is to guarantee
4453 that some formats will work even for cross assembly. */
4455 for (i
= 0; fp_const
[i
]; i
++)
4457 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4461 *str
+= strlen (fp_const
[i
]);
4462 if (is_end_of_line
[(unsigned char) **str
])
4468 /* Just because we didn't get a match doesn't mean that the constant
4469 isn't valid, just that it is in a format that we don't
4470 automatically recognize. Try parsing it with the standard
4471 expression routines. */
4473 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4475 /* Look for a raw floating point number. */
4476 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4477 && is_end_of_line
[(unsigned char) *save_in
])
4479 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4481 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4483 if (words
[j
] != fp_values
[i
][j
])
4487 if (j
== MAX_LITTLENUMS
)
4495 /* Try and parse a more complex expression, this will probably fail
4496 unless the code uses a floating point prefix (eg "0f"). */
4497 save_in
= input_line_pointer
;
4498 input_line_pointer
= *str
;
4499 if (expression (&exp
) == absolute_section
4500 && exp
.X_op
== O_big
4501 && exp
.X_add_number
< 0)
4503 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4505 if (gen_to_words (words
, 5, (long) 15) == 0)
4507 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4509 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4511 if (words
[j
] != fp_values
[i
][j
])
4515 if (j
== MAX_LITTLENUMS
)
4517 *str
= input_line_pointer
;
4518 input_line_pointer
= save_in
;
4525 *str
= input_line_pointer
;
4526 input_line_pointer
= save_in
;
4527 inst
.error
= _("invalid FPA immediate expression");
4531 /* Returns 1 if a number has "quarter-precision" float format
4532 0baBbbbbbc defgh000 00000000 00000000. */
4535 is_quarter_float (unsigned imm
)
4537 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4538 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4541 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4542 0baBbbbbbc defgh000 00000000 00000000.
4543 The zero and minus-zero cases need special handling, since they can't be
4544 encoded in the "quarter-precision" float format, but can nonetheless be
4545 loaded as integer constants. */
4548 parse_qfloat_immediate (char **ccp
, int *immed
)
4552 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4553 int found_fpchar
= 0;
4555 skip_past_char (&str
, '#');
4557 /* We must not accidentally parse an integer as a floating-point number. Make
4558 sure that the value we parse is not an integer by checking for special
4559 characters '.' or 'e'.
4560 FIXME: This is a horrible hack, but doing better is tricky because type
4561 information isn't in a very usable state at parse time. */
4563 skip_whitespace (fpnum
);
4565 if (strncmp (fpnum
, "0x", 2) == 0)
4569 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4570 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4580 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4582 unsigned fpword
= 0;
4585 /* Our FP word must be 32 bits (single-precision FP). */
4586 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4588 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4592 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4605 /* Shift operands. */
4608 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4611 struct asm_shift_name
4614 enum shift_kind kind
;
4617 /* Third argument to parse_shift. */
4618 enum parse_shift_mode
4620 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4621 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4622 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4623 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4624 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4627 /* Parse a <shift> specifier on an ARM data processing instruction.
4628 This has three forms:
4630 (LSL|LSR|ASL|ASR|ROR) Rs
4631 (LSL|LSR|ASL|ASR|ROR) #imm
4634 Note that ASL is assimilated to LSL in the instruction encoding, and
4635 RRX to ROR #0 (which cannot be written as such). */
4638 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4640 const struct asm_shift_name
*shift_name
;
4641 enum shift_kind shift
;
4646 for (p
= *str
; ISALPHA (*p
); p
++)
4651 inst
.error
= _("shift expression expected");
4655 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4658 if (shift_name
== NULL
)
4660 inst
.error
= _("shift expression expected");
4664 shift
= shift_name
->kind
;
4668 case NO_SHIFT_RESTRICT
:
4669 case SHIFT_IMMEDIATE
: break;
4671 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4672 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4674 inst
.error
= _("'LSL' or 'ASR' required");
4679 case SHIFT_LSL_IMMEDIATE
:
4680 if (shift
!= SHIFT_LSL
)
4682 inst
.error
= _("'LSL' required");
4687 case SHIFT_ASR_IMMEDIATE
:
4688 if (shift
!= SHIFT_ASR
)
4690 inst
.error
= _("'ASR' required");
4698 if (shift
!= SHIFT_RRX
)
4700 /* Whitespace can appear here if the next thing is a bare digit. */
4701 skip_whitespace (p
);
4703 if (mode
== NO_SHIFT_RESTRICT
4704 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4706 inst
.operands
[i
].imm
= reg
;
4707 inst
.operands
[i
].immisreg
= 1;
4709 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4712 inst
.operands
[i
].shift_kind
= shift
;
4713 inst
.operands
[i
].shifted
= 1;
4718 /* Parse a <shifter_operand> for an ARM data processing instruction:
4721 #<immediate>, <rotate>
4725 where <shift> is defined by parse_shift above, and <rotate> is a
4726 multiple of 2 between 0 and 30. Validation of immediate operands
4727 is deferred to md_apply_fix. */
4730 parse_shifter_operand (char **str
, int i
)
4735 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4737 inst
.operands
[i
].reg
= value
;
4738 inst
.operands
[i
].isreg
= 1;
4740 /* parse_shift will override this if appropriate */
4741 inst
.reloc
.exp
.X_op
= O_constant
;
4742 inst
.reloc
.exp
.X_add_number
= 0;
4744 if (skip_past_comma (str
) == FAIL
)
4747 /* Shift operation on register. */
4748 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4751 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4754 if (skip_past_comma (str
) == SUCCESS
)
4756 /* #x, y -- ie explicit rotation by Y. */
4757 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
4760 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4762 inst
.error
= _("constant expression expected");
4766 value
= exp
.X_add_number
;
4767 if (value
< 0 || value
> 30 || value
% 2 != 0)
4769 inst
.error
= _("invalid rotation");
4772 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4774 inst
.error
= _("invalid constant");
4778 /* Convert to decoded value. md_apply_fix will put it back. */
4779 inst
.reloc
.exp
.X_add_number
4780 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4781 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4784 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4785 inst
.reloc
.pc_rel
= 0;
4789 /* Group relocation information. Each entry in the table contains the
4790 textual name of the relocation as may appear in assembler source
4791 and must end with a colon.
4792 Along with this textual name are the relocation codes to be used if
4793 the corresponding instruction is an ALU instruction (ADD or SUB only),
4794 an LDR, an LDRS, or an LDC. */
4796 struct group_reloc_table_entry
4807 /* Varieties of non-ALU group relocation. */
4814 static struct group_reloc_table_entry group_reloc_table
[] =
4815 { /* Program counter relative: */
4817 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4822 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4823 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4824 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4825 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4827 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4832 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4833 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4834 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4835 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4837 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4838 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4839 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4840 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4841 /* Section base relative */
4843 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4848 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4849 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4850 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4851 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4853 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4858 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4859 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4860 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4861 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4863 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4864 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4865 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4866 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4868 /* Given the address of a pointer pointing to the textual name of a group
4869 relocation as may appear in assembler source, attempt to find its details
4870 in group_reloc_table. The pointer will be updated to the character after
4871 the trailing colon. On failure, FAIL will be returned; SUCCESS
4872 otherwise. On success, *entry will be updated to point at the relevant
4873 group_reloc_table entry. */
4876 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4879 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4881 int length
= strlen (group_reloc_table
[i
].name
);
4883 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4884 && (*str
)[length
] == ':')
4886 *out
= &group_reloc_table
[i
];
4887 *str
+= (length
+ 1);
4895 /* Parse a <shifter_operand> for an ARM data processing instruction
4896 (as for parse_shifter_operand) where group relocations are allowed:
4899 #<immediate>, <rotate>
4900 #:<group_reloc>:<expression>
4904 where <group_reloc> is one of the strings defined in group_reloc_table.
4905 The hashes are optional.
4907 Everything else is as for parse_shifter_operand. */
4909 static parse_operand_result
4910 parse_shifter_operand_group_reloc (char **str
, int i
)
4912 /* Determine if we have the sequence of characters #: or just :
4913 coming next. If we do, then we check for a group relocation.
4914 If we don't, punt the whole lot to parse_shifter_operand. */
4916 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4917 || (*str
)[0] == ':')
4919 struct group_reloc_table_entry
*entry
;
4921 if ((*str
)[0] == '#')
4926 /* Try to parse a group relocation. Anything else is an error. */
4927 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4929 inst
.error
= _("unknown group relocation");
4930 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4933 /* We now have the group relocation table entry corresponding to
4934 the name in the assembler source. Next, we parse the expression. */
4935 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4936 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4938 /* Record the relocation type (always the ALU variant here). */
4939 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
4940 gas_assert (inst
.reloc
.type
!= 0);
4942 return PARSE_OPERAND_SUCCESS
;
4945 return parse_shifter_operand (str
, i
) == SUCCESS
4946 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4948 /* Never reached. */
4951 /* Parse all forms of an ARM address expression. Information is written
4952 to inst.operands[i] and/or inst.reloc.
4954 Preindexed addressing (.preind=1):
4956 [Rn, #offset] .reg=Rn .reloc.exp=offset
4957 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4958 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4959 .shift_kind=shift .reloc.exp=shift_imm
4961 These three may have a trailing ! which causes .writeback to be set also.
4963 Postindexed addressing (.postind=1, .writeback=1):
4965 [Rn], #offset .reg=Rn .reloc.exp=offset
4966 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4967 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4968 .shift_kind=shift .reloc.exp=shift_imm
4970 Unindexed addressing (.preind=0, .postind=0):
4972 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4976 [Rn]{!} shorthand for [Rn,#0]{!}
4977 =immediate .isreg=0 .reloc.exp=immediate
4978 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4980 It is the caller's responsibility to check for addressing modes not
4981 supported by the instruction, and to set inst.reloc.type. */
4983 static parse_operand_result
4984 parse_address_main (char **str
, int i
, int group_relocations
,
4985 group_reloc_type group_type
)
4990 if (skip_past_char (&p
, '[') == FAIL
)
4992 if (skip_past_char (&p
, '=') == FAIL
)
4994 /* Bare address - translate to PC-relative offset. */
4995 inst
.reloc
.pc_rel
= 1;
4996 inst
.operands
[i
].reg
= REG_PC
;
4997 inst
.operands
[i
].isreg
= 1;
4998 inst
.operands
[i
].preind
= 1;
5000 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5002 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5003 return PARSE_OPERAND_FAIL
;
5006 return PARSE_OPERAND_SUCCESS
;
5009 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5011 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5012 return PARSE_OPERAND_FAIL
;
5014 inst
.operands
[i
].reg
= reg
;
5015 inst
.operands
[i
].isreg
= 1;
5017 if (skip_past_comma (&p
) == SUCCESS
)
5019 inst
.operands
[i
].preind
= 1;
5022 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5024 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5026 inst
.operands
[i
].imm
= reg
;
5027 inst
.operands
[i
].immisreg
= 1;
5029 if (skip_past_comma (&p
) == SUCCESS
)
5030 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5031 return PARSE_OPERAND_FAIL
;
5033 else if (skip_past_char (&p
, ':') == SUCCESS
)
5035 /* FIXME: '@' should be used here, but it's filtered out by generic
5036 code before we get to see it here. This may be subject to
5039 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5040 if (exp
.X_op
!= O_constant
)
5042 inst
.error
= _("alignment must be constant");
5043 return PARSE_OPERAND_FAIL
;
5045 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5046 inst
.operands
[i
].immisalign
= 1;
5047 /* Alignments are not pre-indexes. */
5048 inst
.operands
[i
].preind
= 0;
5052 if (inst
.operands
[i
].negative
)
5054 inst
.operands
[i
].negative
= 0;
5058 if (group_relocations
5059 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5061 struct group_reloc_table_entry
*entry
;
5063 /* Skip over the #: or : sequence. */
5069 /* Try to parse a group relocation. Anything else is an
5071 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5073 inst
.error
= _("unknown group relocation");
5074 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5077 /* We now have the group relocation table entry corresponding to
5078 the name in the assembler source. Next, we parse the
5080 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5081 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5083 /* Record the relocation type. */
5087 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5091 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5095 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5102 if (inst
.reloc
.type
== 0)
5104 inst
.error
= _("this group relocation is not allowed on this instruction");
5105 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5109 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5110 return PARSE_OPERAND_FAIL
;
5114 if (skip_past_char (&p
, ']') == FAIL
)
5116 inst
.error
= _("']' expected");
5117 return PARSE_OPERAND_FAIL
;
5120 if (skip_past_char (&p
, '!') == SUCCESS
)
5121 inst
.operands
[i
].writeback
= 1;
5123 else if (skip_past_comma (&p
) == SUCCESS
)
5125 if (skip_past_char (&p
, '{') == SUCCESS
)
5127 /* [Rn], {expr} - unindexed, with option */
5128 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5129 0, 255, TRUE
) == FAIL
)
5130 return PARSE_OPERAND_FAIL
;
5132 if (skip_past_char (&p
, '}') == FAIL
)
5134 inst
.error
= _("'}' expected at end of 'option' field");
5135 return PARSE_OPERAND_FAIL
;
5137 if (inst
.operands
[i
].preind
)
5139 inst
.error
= _("cannot combine index with option");
5140 return PARSE_OPERAND_FAIL
;
5143 return PARSE_OPERAND_SUCCESS
;
5147 inst
.operands
[i
].postind
= 1;
5148 inst
.operands
[i
].writeback
= 1;
5150 if (inst
.operands
[i
].preind
)
5152 inst
.error
= _("cannot combine pre- and post-indexing");
5153 return PARSE_OPERAND_FAIL
;
5157 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5159 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5161 /* We might be using the immediate for alignment already. If we
5162 are, OR the register number into the low-order bits. */
5163 if (inst
.operands
[i
].immisalign
)
5164 inst
.operands
[i
].imm
|= reg
;
5166 inst
.operands
[i
].imm
= reg
;
5167 inst
.operands
[i
].immisreg
= 1;
5169 if (skip_past_comma (&p
) == SUCCESS
)
5170 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5171 return PARSE_OPERAND_FAIL
;
5175 if (inst
.operands
[i
].negative
)
5177 inst
.operands
[i
].negative
= 0;
5180 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5181 return PARSE_OPERAND_FAIL
;
5186 /* If at this point neither .preind nor .postind is set, we have a
5187 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5188 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5190 inst
.operands
[i
].preind
= 1;
5191 inst
.reloc
.exp
.X_op
= O_constant
;
5192 inst
.reloc
.exp
.X_add_number
= 0;
5195 return PARSE_OPERAND_SUCCESS
;
5199 parse_address (char **str
, int i
)
5201 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5205 static parse_operand_result
5206 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5208 return parse_address_main (str
, i
, 1, type
);
5211 /* Parse an operand for a MOVW or MOVT instruction. */
5213 parse_half (char **str
)
5218 skip_past_char (&p
, '#');
5219 if (strncasecmp (p
, ":lower16:", 9) == 0)
5220 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5221 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5222 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5224 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5227 skip_whitespace (p
);
5230 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5233 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5235 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5237 inst
.error
= _("constant expression expected");
5240 if (inst
.reloc
.exp
.X_add_number
< 0
5241 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5243 inst
.error
= _("immediate value out of range");
5251 /* Miscellaneous. */
5253 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5254 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5256 parse_psr (char **str
)
5259 unsigned long psr_field
;
5260 const struct asm_psr
*psr
;
5263 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5264 feature for ease of use and backwards compatibility. */
5266 if (strncasecmp (p
, "SPSR", 4) == 0)
5267 psr_field
= SPSR_BIT
;
5268 else if (strncasecmp (p
, "CPSR", 4) == 0)
5275 while (ISALNUM (*p
) || *p
== '_');
5277 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5289 /* A suffix follows. */
5295 while (ISALNUM (*p
) || *p
== '_');
5297 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5302 psr_field
|= psr
->field
;
5307 goto error
; /* Garbage after "[CS]PSR". */
5309 psr_field
|= (PSR_c
| PSR_f
);
5315 inst
.error
= _("flag for {c}psr instruction expected");
5319 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5320 value suitable for splatting into the AIF field of the instruction. */
5323 parse_cps_flags (char **str
)
5332 case '\0': case ',':
5335 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5336 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5337 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5340 inst
.error
= _("unrecognized CPS flag");
5345 if (saw_a_flag
== 0)
5347 inst
.error
= _("missing CPS flags");
5355 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5356 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5359 parse_endian_specifier (char **str
)
5364 if (strncasecmp (s
, "BE", 2))
5366 else if (strncasecmp (s
, "LE", 2))
5370 inst
.error
= _("valid endian specifiers are be or le");
5374 if (ISALNUM (s
[2]) || s
[2] == '_')
5376 inst
.error
= _("valid endian specifiers are be or le");
5381 return little_endian
;
5384 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5385 value suitable for poking into the rotate field of an sxt or sxta
5386 instruction, or FAIL on error. */
5389 parse_ror (char **str
)
5394 if (strncasecmp (s
, "ROR", 3) == 0)
5398 inst
.error
= _("missing rotation field after comma");
5402 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5407 case 0: *str
= s
; return 0x0;
5408 case 8: *str
= s
; return 0x1;
5409 case 16: *str
= s
; return 0x2;
5410 case 24: *str
= s
; return 0x3;
5413 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5418 /* Parse a conditional code (from conds[] below). The value returned is in the
5419 range 0 .. 14, or FAIL. */
5421 parse_cond (char **str
)
5424 const struct asm_cond
*c
;
5426 /* Condition codes are always 2 characters, so matching up to
5427 3 characters is sufficient. */
5432 while (ISALPHA (*q
) && n
< 3)
5434 cond
[n
] = TOLOWER (*q
);
5439 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5442 inst
.error
= _("condition required");
5450 /* Parse an option for a barrier instruction. Returns the encoding for the
5453 parse_barrier (char **str
)
5456 const struct asm_barrier_opt
*o
;
5459 while (ISALPHA (*q
))
5462 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5471 /* Parse the operands of a table branch instruction. Similar to a memory
5474 parse_tb (char **str
)
5479 if (skip_past_char (&p
, '[') == FAIL
)
5481 inst
.error
= _("'[' expected");
5485 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5487 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5490 inst
.operands
[0].reg
= reg
;
5492 if (skip_past_comma (&p
) == FAIL
)
5494 inst
.error
= _("',' expected");
5498 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5500 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5503 inst
.operands
[0].imm
= reg
;
5505 if (skip_past_comma (&p
) == SUCCESS
)
5507 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5509 if (inst
.reloc
.exp
.X_add_number
!= 1)
5511 inst
.error
= _("invalid shift");
5514 inst
.operands
[0].shifted
= 1;
5517 if (skip_past_char (&p
, ']') == FAIL
)
5519 inst
.error
= _("']' expected");
5526 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5527 information on the types the operands can take and how they are encoded.
5528 Up to four operands may be read; this function handles setting the
5529 ".present" field for each read operand itself.
5530 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5531 else returns FAIL. */
5534 parse_neon_mov (char **str
, int *which_operand
)
5536 int i
= *which_operand
, val
;
5537 enum arm_reg_type rtype
;
5539 struct neon_type_el optype
;
5541 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5543 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5544 inst
.operands
[i
].reg
= val
;
5545 inst
.operands
[i
].isscalar
= 1;
5546 inst
.operands
[i
].vectype
= optype
;
5547 inst
.operands
[i
++].present
= 1;
5549 if (skip_past_comma (&ptr
) == FAIL
)
5552 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5555 inst
.operands
[i
].reg
= val
;
5556 inst
.operands
[i
].isreg
= 1;
5557 inst
.operands
[i
].present
= 1;
5559 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5562 /* Cases 0, 1, 2, 3, 5 (D only). */
5563 if (skip_past_comma (&ptr
) == FAIL
)
5566 inst
.operands
[i
].reg
= val
;
5567 inst
.operands
[i
].isreg
= 1;
5568 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5569 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5570 inst
.operands
[i
].isvec
= 1;
5571 inst
.operands
[i
].vectype
= optype
;
5572 inst
.operands
[i
++].present
= 1;
5574 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5576 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5577 Case 13: VMOV <Sd>, <Rm> */
5578 inst
.operands
[i
].reg
= val
;
5579 inst
.operands
[i
].isreg
= 1;
5580 inst
.operands
[i
].present
= 1;
5582 if (rtype
== REG_TYPE_NQ
)
5584 first_error (_("can't use Neon quad register here"));
5587 else if (rtype
!= REG_TYPE_VFS
)
5590 if (skip_past_comma (&ptr
) == FAIL
)
5592 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5594 inst
.operands
[i
].reg
= val
;
5595 inst
.operands
[i
].isreg
= 1;
5596 inst
.operands
[i
].present
= 1;
5599 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5602 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5603 Case 1: VMOV<c><q> <Dd>, <Dm>
5604 Case 8: VMOV.F32 <Sd>, <Sm>
5605 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5607 inst
.operands
[i
].reg
= val
;
5608 inst
.operands
[i
].isreg
= 1;
5609 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5610 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5611 inst
.operands
[i
].isvec
= 1;
5612 inst
.operands
[i
].vectype
= optype
;
5613 inst
.operands
[i
].present
= 1;
5615 if (skip_past_comma (&ptr
) == SUCCESS
)
5620 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5623 inst
.operands
[i
].reg
= val
;
5624 inst
.operands
[i
].isreg
= 1;
5625 inst
.operands
[i
++].present
= 1;
5627 if (skip_past_comma (&ptr
) == FAIL
)
5630 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5633 inst
.operands
[i
].reg
= val
;
5634 inst
.operands
[i
].isreg
= 1;
5635 inst
.operands
[i
++].present
= 1;
5638 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5639 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5640 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5641 Case 10: VMOV.F32 <Sd>, #<imm>
5642 Case 11: VMOV.F64 <Dd>, #<imm> */
5643 inst
.operands
[i
].immisfloat
= 1;
5644 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5645 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5646 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5650 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5654 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5657 inst
.operands
[i
].reg
= val
;
5658 inst
.operands
[i
].isreg
= 1;
5659 inst
.operands
[i
++].present
= 1;
5661 if (skip_past_comma (&ptr
) == FAIL
)
5664 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5666 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5667 inst
.operands
[i
].reg
= val
;
5668 inst
.operands
[i
].isscalar
= 1;
5669 inst
.operands
[i
].present
= 1;
5670 inst
.operands
[i
].vectype
= optype
;
5672 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5674 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5675 inst
.operands
[i
].reg
= val
;
5676 inst
.operands
[i
].isreg
= 1;
5677 inst
.operands
[i
++].present
= 1;
5679 if (skip_past_comma (&ptr
) == FAIL
)
5682 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5685 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5689 inst
.operands
[i
].reg
= val
;
5690 inst
.operands
[i
].isreg
= 1;
5691 inst
.operands
[i
].isvec
= 1;
5692 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5693 inst
.operands
[i
].vectype
= optype
;
5694 inst
.operands
[i
].present
= 1;
5696 if (rtype
== REG_TYPE_VFS
)
5700 if (skip_past_comma (&ptr
) == FAIL
)
5702 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5705 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5708 inst
.operands
[i
].reg
= val
;
5709 inst
.operands
[i
].isreg
= 1;
5710 inst
.operands
[i
].isvec
= 1;
5711 inst
.operands
[i
].issingle
= 1;
5712 inst
.operands
[i
].vectype
= optype
;
5713 inst
.operands
[i
].present
= 1;
5716 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5720 inst
.operands
[i
].reg
= val
;
5721 inst
.operands
[i
].isreg
= 1;
5722 inst
.operands
[i
].isvec
= 1;
5723 inst
.operands
[i
].issingle
= 1;
5724 inst
.operands
[i
].vectype
= optype
;
5725 inst
.operands
[i
++].present
= 1;
5730 first_error (_("parse error"));
5734 /* Successfully parsed the operands. Update args. */
5740 first_error (_("expected comma"));
5744 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5748 /* Use this macro when the operand constraints are different
5749 for ARM and THUMB (e.g. ldrd). */
5750 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
5751 ((arm_operand) | ((thumb_operand) << 16))
5753 /* Matcher codes for parse_operands. */
5754 enum operand_parse_code
5756 OP_stop
, /* end of line */
5758 OP_RR
, /* ARM register */
5759 OP_RRnpc
, /* ARM register, not r15 */
5760 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
5761 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5762 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
5763 optional trailing ! */
5764 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5765 OP_RCP
, /* Coprocessor number */
5766 OP_RCN
, /* Coprocessor register */
5767 OP_RF
, /* FPA register */
5768 OP_RVS
, /* VFP single precision register */
5769 OP_RVD
, /* VFP double precision register (0..15) */
5770 OP_RND
, /* Neon double precision register (0..31) */
5771 OP_RNQ
, /* Neon quad precision register */
5772 OP_RVSD
, /* VFP single or double precision register */
5773 OP_RNDQ
, /* Neon double or quad precision register */
5774 OP_RNSDQ
, /* Neon single, double or quad precision register */
5775 OP_RNSC
, /* Neon scalar D[X] */
5776 OP_RVC
, /* VFP control register */
5777 OP_RMF
, /* Maverick F register */
5778 OP_RMD
, /* Maverick D register */
5779 OP_RMFX
, /* Maverick FX register */
5780 OP_RMDX
, /* Maverick DX register */
5781 OP_RMAX
, /* Maverick AX register */
5782 OP_RMDS
, /* Maverick DSPSC register */
5783 OP_RIWR
, /* iWMMXt wR register */
5784 OP_RIWC
, /* iWMMXt wC register */
5785 OP_RIWG
, /* iWMMXt wCG register */
5786 OP_RXA
, /* XScale accumulator register */
5788 OP_REGLST
, /* ARM register list */
5789 OP_VRSLST
, /* VFP single-precision register list */
5790 OP_VRDLST
, /* VFP double-precision register list */
5791 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5792 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5793 OP_NSTRLST
, /* Neon element/structure list */
5795 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5796 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5797 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5798 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5799 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5800 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5801 OP_VMOV
, /* Neon VMOV operands. */
5802 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
5803 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5804 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5806 OP_I0
, /* immediate zero */
5807 OP_I7
, /* immediate value 0 .. 7 */
5808 OP_I15
, /* 0 .. 15 */
5809 OP_I16
, /* 1 .. 16 */
5810 OP_I16z
, /* 0 .. 16 */
5811 OP_I31
, /* 0 .. 31 */
5812 OP_I31w
, /* 0 .. 31, optional trailing ! */
5813 OP_I32
, /* 1 .. 32 */
5814 OP_I32z
, /* 0 .. 32 */
5815 OP_I63
, /* 0 .. 63 */
5816 OP_I63s
, /* -64 .. 63 */
5817 OP_I64
, /* 1 .. 64 */
5818 OP_I64z
, /* 0 .. 64 */
5819 OP_I255
, /* 0 .. 255 */
5821 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5822 OP_I7b
, /* 0 .. 7 */
5823 OP_I15b
, /* 0 .. 15 */
5824 OP_I31b
, /* 0 .. 31 */
5826 OP_SH
, /* shifter operand */
5827 OP_SHG
, /* shifter operand with possible group relocation */
5828 OP_ADDR
, /* Memory address expression (any mode) */
5829 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5830 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5831 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5832 OP_EXP
, /* arbitrary expression */
5833 OP_EXPi
, /* same, with optional immediate prefix */
5834 OP_EXPr
, /* same, with optional relocation suffix */
5835 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5837 OP_CPSF
, /* CPS flags */
5838 OP_ENDI
, /* Endianness specifier */
5839 OP_PSR
, /* CPSR/SPSR mask for msr */
5840 OP_COND
, /* conditional code */
5841 OP_TB
, /* Table branch. */
5843 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5844 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5846 OP_RRnpc_I0
, /* ARM register or literal 0 */
5847 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5848 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5849 OP_RF_IF
, /* FPA register or immediate */
5850 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5851 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5853 /* Optional operands. */
5854 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5855 OP_oI31b
, /* 0 .. 31 */
5856 OP_oI32b
, /* 1 .. 32 */
5857 OP_oIffffb
, /* 0 .. 65535 */
5858 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5860 OP_oRR
, /* ARM register */
5861 OP_oRRnpc
, /* ARM register, not the PC */
5862 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
5863 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5864 OP_oRND
, /* Optional Neon double precision register */
5865 OP_oRNQ
, /* Optional Neon quad precision register */
5866 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5867 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5868 OP_oSHll
, /* LSL immediate */
5869 OP_oSHar
, /* ASR immediate */
5870 OP_oSHllar
, /* LSL or ASR immediate */
5871 OP_oROR
, /* ROR 0/8/16/24 */
5872 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5874 /* Some pre-defined mixed (ARM/THUMB) operands. */
5875 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
5876 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
5877 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
5879 OP_FIRST_OPTIONAL
= OP_oI7b
5882 /* Generic instruction operand parser. This does no encoding and no
5883 semantic validation; it merely squirrels values away in the inst
5884 structure. Returns SUCCESS or FAIL depending on whether the
5885 specified grammar matched. */
5887 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
5889 unsigned const int *upat
= pattern
;
5890 char *backtrack_pos
= 0;
5891 const char *backtrack_error
= 0;
5892 int i
, val
, backtrack_index
= 0;
5893 enum arm_reg_type rtype
;
5894 parse_operand_result result
;
5895 unsigned int op_parse_code
;
5897 #define po_char_or_fail(chr) \
5900 if (skip_past_char (&str, chr) == FAIL) \
5905 #define po_reg_or_fail(regtype) \
5908 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5909 & inst.operands[i].vectype); \
5912 first_error (_(reg_expected_msgs[regtype])); \
5915 inst.operands[i].reg = val; \
5916 inst.operands[i].isreg = 1; \
5917 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5918 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5919 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5920 || rtype == REG_TYPE_VFD \
5921 || rtype == REG_TYPE_NQ); \
5925 #define po_reg_or_goto(regtype, label) \
5928 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5929 & inst.operands[i].vectype); \
5933 inst.operands[i].reg = val; \
5934 inst.operands[i].isreg = 1; \
5935 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5936 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5937 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5938 || rtype == REG_TYPE_VFD \
5939 || rtype == REG_TYPE_NQ); \
5943 #define po_imm_or_fail(min, max, popt) \
5946 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5948 inst.operands[i].imm = val; \
5952 #define po_scalar_or_goto(elsz, label) \
5955 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
5958 inst.operands[i].reg = val; \
5959 inst.operands[i].isscalar = 1; \
5963 #define po_misc_or_fail(expr) \
5971 #define po_misc_or_fail_no_backtrack(expr) \
5975 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
5976 backtrack_pos = 0; \
5977 if (result != PARSE_OPERAND_SUCCESS) \
5982 skip_whitespace (str
);
5984 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5986 op_parse_code
= upat
[i
];
5987 if (op_parse_code
>= 1<<16)
5988 op_parse_code
= thumb
? (op_parse_code
>> 16)
5989 : (op_parse_code
& ((1<<16)-1));
5991 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
5993 /* Remember where we are in case we need to backtrack. */
5994 gas_assert (!backtrack_pos
);
5995 backtrack_pos
= str
;
5996 backtrack_error
= inst
.error
;
5997 backtrack_index
= i
;
6000 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6001 po_char_or_fail (',');
6003 switch (op_parse_code
)
6011 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6012 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6013 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6014 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6015 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6016 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6018 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6020 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6022 /* Also accept generic coprocessor regs for unknown registers. */
6024 po_reg_or_fail (REG_TYPE_CN
);
6026 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6027 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6028 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6029 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6030 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6031 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6032 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6033 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6034 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6035 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6037 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6039 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6040 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6042 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6044 /* Neon scalar. Using an element size of 8 means that some invalid
6045 scalars are accepted here, so deal with those in later code. */
6046 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6050 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6053 po_imm_or_fail (0, 0, TRUE
);
6058 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6063 po_scalar_or_goto (8, try_rr
);
6066 po_reg_or_fail (REG_TYPE_RN
);
6072 po_scalar_or_goto (8, try_nsdq
);
6075 po_reg_or_fail (REG_TYPE_NSDQ
);
6081 po_scalar_or_goto (8, try_ndq
);
6084 po_reg_or_fail (REG_TYPE_NDQ
);
6090 po_scalar_or_goto (8, try_vfd
);
6093 po_reg_or_fail (REG_TYPE_VFD
);
6098 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6099 not careful then bad things might happen. */
6100 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6105 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6108 /* There's a possibility of getting a 64-bit immediate here, so
6109 we need special handling. */
6110 if (parse_big_immediate (&str
, i
) == FAIL
)
6112 inst
.error
= _("immediate value is out of range");
6120 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6123 po_imm_or_fail (0, 63, TRUE
);
6128 po_char_or_fail ('[');
6129 po_reg_or_fail (REG_TYPE_RN
);
6130 po_char_or_fail (']');
6136 po_reg_or_fail (REG_TYPE_RN
);
6137 if (skip_past_char (&str
, '!') == SUCCESS
)
6138 inst
.operands
[i
].writeback
= 1;
6142 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6143 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6144 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6145 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6146 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6147 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6148 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6149 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6150 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6151 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6152 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6153 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6155 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6157 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6158 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6160 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6161 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6162 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6164 /* Immediate variants */
6166 po_char_or_fail ('{');
6167 po_imm_or_fail (0, 255, TRUE
);
6168 po_char_or_fail ('}');
6172 /* The expression parser chokes on a trailing !, so we have
6173 to find it first and zap it. */
6176 while (*s
&& *s
!= ',')
6181 inst
.operands
[i
].writeback
= 1;
6183 po_imm_or_fail (0, 31, TRUE
);
6191 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6196 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6201 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6203 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6205 val
= parse_reloc (&str
);
6208 inst
.error
= _("unrecognized relocation suffix");
6211 else if (val
!= BFD_RELOC_UNUSED
)
6213 inst
.operands
[i
].imm
= val
;
6214 inst
.operands
[i
].hasreloc
= 1;
6219 /* Operand for MOVW or MOVT. */
6221 po_misc_or_fail (parse_half (&str
));
6224 /* Register or expression. */
6225 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6226 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6228 /* Register or immediate. */
6229 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6230 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6232 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6234 if (!is_immediate_prefix (*str
))
6237 val
= parse_fpa_immediate (&str
);
6240 /* FPA immediates are encoded as registers 8-15.
6241 parse_fpa_immediate has already applied the offset. */
6242 inst
.operands
[i
].reg
= val
;
6243 inst
.operands
[i
].isreg
= 1;
6246 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6247 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6249 /* Two kinds of register. */
6252 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6254 || (rege
->type
!= REG_TYPE_MMXWR
6255 && rege
->type
!= REG_TYPE_MMXWC
6256 && rege
->type
!= REG_TYPE_MMXWCG
))
6258 inst
.error
= _("iWMMXt data or control register expected");
6261 inst
.operands
[i
].reg
= rege
->number
;
6262 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6268 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6270 || (rege
->type
!= REG_TYPE_MMXWC
6271 && rege
->type
!= REG_TYPE_MMXWCG
))
6273 inst
.error
= _("iWMMXt control register expected");
6276 inst
.operands
[i
].reg
= rege
->number
;
6277 inst
.operands
[i
].isreg
= 1;
6282 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6283 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6284 case OP_oROR
: val
= parse_ror (&str
); break;
6285 case OP_PSR
: val
= parse_psr (&str
); break;
6286 case OP_COND
: val
= parse_cond (&str
); break;
6287 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
6290 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
6291 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
6294 val
= parse_psr (&str
);
6298 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6301 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6303 if (strncasecmp (str
, "APSR_", 5) == 0)
6310 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6311 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6312 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6313 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6314 default: found
= 16;
6318 inst
.operands
[i
].isvec
= 1;
6319 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6320 inst
.operands
[i
].reg
= REG_PC
;
6327 po_misc_or_fail (parse_tb (&str
));
6330 /* Register lists. */
6332 val
= parse_reg_list (&str
);
6335 inst
.operands
[1].writeback
= 1;
6341 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6345 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6349 /* Allow Q registers too. */
6350 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6355 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6357 inst
.operands
[i
].issingle
= 1;
6362 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6367 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6368 &inst
.operands
[i
].vectype
);
6371 /* Addressing modes */
6373 po_misc_or_fail (parse_address (&str
, i
));
6377 po_misc_or_fail_no_backtrack (
6378 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6382 po_misc_or_fail_no_backtrack (
6383 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6387 po_misc_or_fail_no_backtrack (
6388 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6392 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6396 po_misc_or_fail_no_backtrack (
6397 parse_shifter_operand_group_reloc (&str
, i
));
6401 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6405 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6409 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6413 as_fatal (_("unhandled operand code %d"), op_parse_code
);
6416 /* Various value-based sanity checks and shared operations. We
6417 do not signal immediate failures for the register constraints;
6418 this allows a syntax error to take precedence. */
6419 switch (op_parse_code
)
6427 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6428 inst
.error
= BAD_PC
;
6433 if (inst
.operands
[i
].isreg
)
6435 if (inst
.operands
[i
].reg
== REG_PC
)
6436 inst
.error
= BAD_PC
;
6437 else if (inst
.operands
[i
].reg
== REG_SP
)
6438 inst
.error
= BAD_SP
;
6443 if (inst
.operands
[i
].isreg
6444 && inst
.operands
[i
].reg
== REG_PC
6445 && (inst
.operands
[i
].writeback
|| thumb
))
6446 inst
.error
= BAD_PC
;
6464 inst
.operands
[i
].imm
= val
;
6471 /* If we get here, this operand was successfully parsed. */
6472 inst
.operands
[i
].present
= 1;
6476 inst
.error
= BAD_ARGS
;
6481 /* The parse routine should already have set inst.error, but set a
6482 default here just in case. */
6484 inst
.error
= _("syntax error");
6488 /* Do not backtrack over a trailing optional argument that
6489 absorbed some text. We will only fail again, with the
6490 'garbage following instruction' error message, which is
6491 probably less helpful than the current one. */
6492 if (backtrack_index
== i
&& backtrack_pos
!= str
6493 && upat
[i
+1] == OP_stop
)
6496 inst
.error
= _("syntax error");
6500 /* Try again, skipping the optional argument at backtrack_pos. */
6501 str
= backtrack_pos
;
6502 inst
.error
= backtrack_error
;
6503 inst
.operands
[backtrack_index
].present
= 0;
6504 i
= backtrack_index
;
6508 /* Check that we have parsed all the arguments. */
6509 if (*str
!= '\0' && !inst
.error
)
6510 inst
.error
= _("garbage following instruction");
6512 return inst
.error
? FAIL
: SUCCESS
;
6515 #undef po_char_or_fail
6516 #undef po_reg_or_fail
6517 #undef po_reg_or_goto
6518 #undef po_imm_or_fail
6519 #undef po_scalar_or_fail
6521 /* Shorthand macro for instruction encoding functions issuing errors. */
6522 #define constraint(expr, err) \
6533 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6534 instructions are unpredictable if these registers are used. This
6535 is the BadReg predicate in ARM's Thumb-2 documentation. */
6536 #define reject_bad_reg(reg) \
6538 if (reg == REG_SP || reg == REG_PC) \
6540 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6545 /* If REG is R13 (the stack pointer), warn that its use is
6547 #define warn_deprecated_sp(reg) \
6549 if (warn_on_deprecated && reg == REG_SP) \
6550 as_warn (_("use of r13 is deprecated")); \
6553 /* Functions for operand encoding. ARM, then Thumb. */
6555 #define rotate_left(v, n) (v << n | v >> (32 - n))
6557 /* If VAL can be encoded in the immediate field of an ARM instruction,
6558 return the encoded form. Otherwise, return FAIL. */
6561 encode_arm_immediate (unsigned int val
)
6565 for (i
= 0; i
< 32; i
+= 2)
6566 if ((a
= rotate_left (val
, i
)) <= 0xff)
6567 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6572 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6573 return the encoded form. Otherwise, return FAIL. */
6575 encode_thumb32_immediate (unsigned int val
)
6582 for (i
= 1; i
<= 24; i
++)
6585 if ((val
& ~(0xff << i
)) == 0)
6586 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6590 if (val
== ((a
<< 16) | a
))
6592 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6596 if (val
== ((a
<< 16) | a
))
6597 return 0x200 | (a
>> 8);
6601 /* Encode a VFP SP or DP register number into inst.instruction. */
6604 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6606 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6609 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6612 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6615 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6620 first_error (_("D register out of range for selected VFP version"));
6628 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6632 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6636 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6640 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6644 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6648 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6656 /* Encode a <shift> in an ARM-format instruction. The immediate,
6657 if any, is handled by md_apply_fix. */
6659 encode_arm_shift (int i
)
6661 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6662 inst
.instruction
|= SHIFT_ROR
<< 5;
6665 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6666 if (inst
.operands
[i
].immisreg
)
6668 inst
.instruction
|= SHIFT_BY_REG
;
6669 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6672 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6677 encode_arm_shifter_operand (int i
)
6679 if (inst
.operands
[i
].isreg
)
6681 inst
.instruction
|= inst
.operands
[i
].reg
;
6682 encode_arm_shift (i
);
6685 inst
.instruction
|= INST_IMMEDIATE
;
6688 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6690 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6692 gas_assert (inst
.operands
[i
].isreg
);
6693 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6695 if (inst
.operands
[i
].preind
)
6699 inst
.error
= _("instruction does not accept preindexed addressing");
6702 inst
.instruction
|= PRE_INDEX
;
6703 if (inst
.operands
[i
].writeback
)
6704 inst
.instruction
|= WRITE_BACK
;
6707 else if (inst
.operands
[i
].postind
)
6709 gas_assert (inst
.operands
[i
].writeback
);
6711 inst
.instruction
|= WRITE_BACK
;
6713 else /* unindexed - only for coprocessor */
6715 inst
.error
= _("instruction does not accept unindexed addressing");
6719 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6720 && (((inst
.instruction
& 0x000f0000) >> 16)
6721 == ((inst
.instruction
& 0x0000f000) >> 12)))
6722 as_warn ((inst
.instruction
& LOAD_BIT
)
6723 ? _("destination register same as write-back base")
6724 : _("source register same as write-back base"));
6727 /* inst.operands[i] was set up by parse_address. Encode it into an
6728 ARM-format mode 2 load or store instruction. If is_t is true,
6729 reject forms that cannot be used with a T instruction (i.e. not
6732 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6734 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
6736 encode_arm_addr_mode_common (i
, is_t
);
6738 if (inst
.operands
[i
].immisreg
)
6740 constraint ((inst
.operands
[i
].imm
== REG_PC
6741 || (is_pc
&& inst
.operands
[i
].writeback
)),
6743 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6744 inst
.instruction
|= inst
.operands
[i
].imm
;
6745 if (!inst
.operands
[i
].negative
)
6746 inst
.instruction
|= INDEX_UP
;
6747 if (inst
.operands
[i
].shifted
)
6749 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6750 inst
.instruction
|= SHIFT_ROR
<< 5;
6753 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6754 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6758 else /* immediate offset in inst.reloc */
6760 if (is_pc
&& !inst
.reloc
.pc_rel
)
6762 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
6763 /* BAD_PC_ADDRESSING Condition =
6765 which becomes !is_load || is_t. */
6766 constraint ((!is_load
|| is_t
),
6770 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6771 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6775 /* inst.operands[i] was set up by parse_address. Encode it into an
6776 ARM-format mode 3 load or store instruction. Reject forms that
6777 cannot be used with such instructions. If is_t is true, reject
6778 forms that cannot be used with a T instruction (i.e. not
6781 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6783 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6785 inst
.error
= _("instruction does not accept scaled register index");
6789 encode_arm_addr_mode_common (i
, is_t
);
6791 if (inst
.operands
[i
].immisreg
)
6793 constraint ((inst
.operands
[i
].imm
== REG_PC
6794 || inst
.operands
[i
].reg
== REG_PC
),
6796 inst
.instruction
|= inst
.operands
[i
].imm
;
6797 if (!inst
.operands
[i
].negative
)
6798 inst
.instruction
|= INDEX_UP
;
6800 else /* immediate offset in inst.reloc */
6802 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
6803 && inst
.operands
[i
].writeback
),
6805 inst
.instruction
|= HWOFFSET_IMM
;
6806 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6807 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6811 /* inst.operands[i] was set up by parse_address. Encode it into an
6812 ARM-format instruction. Reject all forms which cannot be encoded
6813 into a coprocessor load/store instruction. If wb_ok is false,
6814 reject use of writeback; if unind_ok is false, reject use of
6815 unindexed addressing. If reloc_override is not 0, use it instead
6816 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6817 (in which case it is preserved). */
6820 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6822 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6824 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6826 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6828 gas_assert (!inst
.operands
[i
].writeback
);
6831 inst
.error
= _("instruction does not support unindexed addressing");
6834 inst
.instruction
|= inst
.operands
[i
].imm
;
6835 inst
.instruction
|= INDEX_UP
;
6839 if (inst
.operands
[i
].preind
)
6840 inst
.instruction
|= PRE_INDEX
;
6842 if (inst
.operands
[i
].writeback
)
6844 if (inst
.operands
[i
].reg
== REG_PC
)
6846 inst
.error
= _("pc may not be used with write-back");
6851 inst
.error
= _("instruction does not support writeback");
6854 inst
.instruction
|= WRITE_BACK
;
6858 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
6859 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6860 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6861 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6864 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6866 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6872 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6873 Determine whether it can be performed with a move instruction; if
6874 it can, convert inst.instruction to that move instruction and
6875 return TRUE; if it can't, convert inst.instruction to a literal-pool
6876 load and return FALSE. If this is not a valid thing to do in the
6877 current context, set inst.error and return TRUE.
6879 inst.operands[i] describes the destination register. */
6882 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6887 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6891 if ((inst
.instruction
& tbit
) == 0)
6893 inst
.error
= _("invalid pseudo operation");
6896 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6898 inst
.error
= _("constant expression expected");
6901 if (inst
.reloc
.exp
.X_op
== O_constant
)
6905 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6907 /* This can be done with a mov(1) instruction. */
6908 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6909 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6915 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6918 /* This can be done with a mov instruction. */
6919 inst
.instruction
&= LITERAL_MASK
;
6920 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6921 inst
.instruction
|= value
& 0xfff;
6925 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6928 /* This can be done with a mvn instruction. */
6929 inst
.instruction
&= LITERAL_MASK
;
6930 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6931 inst
.instruction
|= value
& 0xfff;
6937 if (add_to_lit_pool () == FAIL
)
6939 inst
.error
= _("literal pool insertion failed");
6942 inst
.operands
[1].reg
= REG_PC
;
6943 inst
.operands
[1].isreg
= 1;
6944 inst
.operands
[1].preind
= 1;
6945 inst
.reloc
.pc_rel
= 1;
6946 inst
.reloc
.type
= (thumb_p
6947 ? BFD_RELOC_ARM_THUMB_OFFSET
6949 ? BFD_RELOC_ARM_HWLITERAL
6950 : BFD_RELOC_ARM_LITERAL
));
6954 /* Functions for instruction encoding, sorted by sub-architecture.
6955 First some generics; their names are taken from the conventional
6956 bit positions for register arguments in ARM format instructions. */
6966 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6972 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6973 inst
.instruction
|= inst
.operands
[1].reg
;
6979 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6980 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6986 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6987 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6993 unsigned Rn
= inst
.operands
[2].reg
;
6994 /* Enforce restrictions on SWP instruction. */
6995 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6997 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6998 _("Rn must not overlap other operands"));
7000 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7001 if (warn_on_deprecated
7002 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7003 as_warn (_("swp{b} use is deprecated for this architecture"));
7006 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7007 inst
.instruction
|= inst
.operands
[1].reg
;
7008 inst
.instruction
|= Rn
<< 16;
7014 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7015 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7016 inst
.instruction
|= inst
.operands
[2].reg
;
7022 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
7023 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
7024 && inst
.reloc
.exp
.X_op
!= O_illegal
)
7025 || inst
.reloc
.exp
.X_add_number
!= 0),
7027 inst
.instruction
|= inst
.operands
[0].reg
;
7028 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7029 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7035 inst
.instruction
|= inst
.operands
[0].imm
;
7041 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7042 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7045 /* ARM instructions, in alphabetical order by function name (except
7046 that wrapper functions appear immediately after the function they
7049 /* This is a pseudo-op of the form "adr rd, label" to be converted
7050 into a relative address of the form "add rd, pc, #label-.-8". */
7055 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7057 /* Frag hacking will turn this into a sub instruction if the offset turns
7058 out to be negative. */
7059 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7060 inst
.reloc
.pc_rel
= 1;
7061 inst
.reloc
.exp
.X_add_number
-= 8;
7064 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7065 into a relative address of the form:
7066 add rd, pc, #low(label-.-8)"
7067 add rd, rd, #high(label-.-8)" */
7072 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7074 /* Frag hacking will turn this into a sub instruction if the offset turns
7075 out to be negative. */
7076 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7077 inst
.reloc
.pc_rel
= 1;
7078 inst
.size
= INSN_SIZE
* 2;
7079 inst
.reloc
.exp
.X_add_number
-= 8;
7085 if (!inst
.operands
[1].present
)
7086 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7087 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7088 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7089 encode_arm_shifter_operand (2);
7095 if (inst
.operands
[0].present
)
7097 constraint ((inst
.instruction
& 0xf0) != 0x40
7098 && inst
.operands
[0].imm
!= 0xf,
7099 _("bad barrier type"));
7100 inst
.instruction
|= inst
.operands
[0].imm
;
7103 inst
.instruction
|= 0xf;
7109 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7110 constraint (msb
> 32, _("bit-field extends past end of register"));
7111 /* The instruction encoding stores the LSB and MSB,
7112 not the LSB and width. */
7113 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7114 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7115 inst
.instruction
|= (msb
- 1) << 16;
7123 /* #0 in second position is alternative syntax for bfc, which is
7124 the same instruction but with REG_PC in the Rm field. */
7125 if (!inst
.operands
[1].isreg
)
7126 inst
.operands
[1].reg
= REG_PC
;
7128 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7129 constraint (msb
> 32, _("bit-field extends past end of register"));
7130 /* The instruction encoding stores the LSB and MSB,
7131 not the LSB and width. */
7132 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7133 inst
.instruction
|= inst
.operands
[1].reg
;
7134 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7135 inst
.instruction
|= (msb
- 1) << 16;
7141 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7142 _("bit-field extends past end of register"));
7143 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7144 inst
.instruction
|= inst
.operands
[1].reg
;
7145 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7146 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7149 /* ARM V5 breakpoint instruction (argument parse)
7150 BKPT <16 bit unsigned immediate>
7151 Instruction is not conditional.
7152 The bit pattern given in insns[] has the COND_ALWAYS condition,
7153 and it is an error if the caller tried to override that. */
7158 /* Top 12 of 16 bits to bits 19:8. */
7159 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7161 /* Bottom 4 of 16 bits to bits 3:0. */
7162 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7166 encode_branch (int default_reloc
)
7168 if (inst
.operands
[0].hasreloc
)
7170 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
7171 _("the only suffix valid here is '(plt)'"));
7172 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
7176 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7178 inst
.reloc
.pc_rel
= 1;
7185 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7186 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7189 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7196 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7198 if (inst
.cond
== COND_ALWAYS
)
7199 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7201 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7205 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7208 /* ARM V5 branch-link-exchange instruction (argument parse)
7209 BLX <target_addr> ie BLX(1)
7210 BLX{<condition>} <Rm> ie BLX(2)
7211 Unfortunately, there are two different opcodes for this mnemonic.
7212 So, the insns[].value is not used, and the code here zaps values
7213 into inst.instruction.
7214 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7219 if (inst
.operands
[0].isreg
)
7221 /* Arg is a register; the opcode provided by insns[] is correct.
7222 It is not illegal to do "blx pc", just useless. */
7223 if (inst
.operands
[0].reg
== REG_PC
)
7224 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7226 inst
.instruction
|= inst
.operands
[0].reg
;
7230 /* Arg is an address; this instruction cannot be executed
7231 conditionally, and the opcode must be adjusted.
7232 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7233 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7234 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7235 inst
.instruction
= 0xfa000000;
7236 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7243 bfd_boolean want_reloc
;
7245 if (inst
.operands
[0].reg
== REG_PC
)
7246 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7248 inst
.instruction
|= inst
.operands
[0].reg
;
7249 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7250 it is for ARMv4t or earlier. */
7251 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7252 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7256 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7261 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7265 /* ARM v5TEJ. Jump to Jazelle code. */
7270 if (inst
.operands
[0].reg
== REG_PC
)
7271 as_tsktsk (_("use of r15 in bxj is not really useful"));
7273 inst
.instruction
|= inst
.operands
[0].reg
;
7276 /* Co-processor data operation:
7277 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7278 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7282 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7283 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7284 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7285 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7286 inst
.instruction
|= inst
.operands
[4].reg
;
7287 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7293 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7294 encode_arm_shifter_operand (1);
7297 /* Transfer between coprocessor and ARM registers.
7298 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7303 No special properties. */
7310 Rd
= inst
.operands
[2].reg
;
7313 if (inst
.instruction
== 0xee000010
7314 || inst
.instruction
== 0xfe000010)
7316 reject_bad_reg (Rd
);
7319 constraint (Rd
== REG_SP
, BAD_SP
);
7324 if (inst
.instruction
== 0xe000010)
7325 constraint (Rd
== REG_PC
, BAD_PC
);
7329 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7330 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7331 inst
.instruction
|= Rd
<< 12;
7332 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7333 inst
.instruction
|= inst
.operands
[4].reg
;
7334 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7337 /* Transfer between coprocessor register and pair of ARM registers.
7338 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7343 Two XScale instructions are special cases of these:
7345 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7346 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7348 Result unpredictable if Rd or Rn is R15. */
7355 Rd
= inst
.operands
[2].reg
;
7356 Rn
= inst
.operands
[3].reg
;
7360 reject_bad_reg (Rd
);
7361 reject_bad_reg (Rn
);
7365 constraint (Rd
== REG_PC
, BAD_PC
);
7366 constraint (Rn
== REG_PC
, BAD_PC
);
7369 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7370 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7371 inst
.instruction
|= Rd
<< 12;
7372 inst
.instruction
|= Rn
<< 16;
7373 inst
.instruction
|= inst
.operands
[4].reg
;
7379 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7380 if (inst
.operands
[1].present
)
7382 inst
.instruction
|= CPSI_MMOD
;
7383 inst
.instruction
|= inst
.operands
[1].imm
;
7390 inst
.instruction
|= inst
.operands
[0].imm
;
7396 /* There is no IT instruction in ARM mode. We
7397 process it to do the validation as if in
7398 thumb mode, just in case the code gets
7399 assembled for thumb using the unified syntax. */
7404 set_it_insn_type (IT_INSN
);
7405 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7406 now_it
.cc
= inst
.operands
[0].imm
;
7413 int base_reg
= inst
.operands
[0].reg
;
7414 int range
= inst
.operands
[1].imm
;
7416 inst
.instruction
|= base_reg
<< 16;
7417 inst
.instruction
|= range
;
7419 if (inst
.operands
[1].writeback
)
7420 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7422 if (inst
.operands
[0].writeback
)
7424 inst
.instruction
|= WRITE_BACK
;
7425 /* Check for unpredictable uses of writeback. */
7426 if (inst
.instruction
& LOAD_BIT
)
7428 /* Not allowed in LDM type 2. */
7429 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7430 && ((range
& (1 << REG_PC
)) == 0))
7431 as_warn (_("writeback of base register is UNPREDICTABLE"));
7432 /* Only allowed if base reg not in list for other types. */
7433 else if (range
& (1 << base_reg
))
7434 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7438 /* Not allowed for type 2. */
7439 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7440 as_warn (_("writeback of base register is UNPREDICTABLE"));
7441 /* Only allowed if base reg not in list, or first in list. */
7442 else if ((range
& (1 << base_reg
))
7443 && (range
& ((1 << base_reg
) - 1)))
7444 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7449 /* ARMv5TE load-consecutive (argument parse)
7458 constraint (inst
.operands
[0].reg
% 2 != 0,
7459 _("first destination register must be even"));
7460 constraint (inst
.operands
[1].present
7461 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7462 _("can only load two consecutive registers"));
7463 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7464 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7466 if (!inst
.operands
[1].present
)
7467 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7469 if (inst
.instruction
& LOAD_BIT
)
7471 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7472 register and the first register written; we have to diagnose
7473 overlap between the base and the second register written here. */
7475 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7476 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7477 as_warn (_("base register written back, and overlaps "
7478 "second destination register"));
7480 /* For an index-register load, the index register must not overlap the
7481 destination (even if not write-back). */
7482 else if (inst
.operands
[2].immisreg
7483 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7484 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7485 as_warn (_("index register overlaps destination register"));
7488 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7489 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7495 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7496 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7497 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7498 || inst
.operands
[1].negative
7499 /* This can arise if the programmer has written
7501 or if they have mistakenly used a register name as the last
7504 It is very difficult to distinguish between these two cases
7505 because "rX" might actually be a label. ie the register
7506 name has been occluded by a symbol of the same name. So we
7507 just generate a general 'bad addressing mode' type error
7508 message and leave it up to the programmer to discover the
7509 true cause and fix their mistake. */
7510 || (inst
.operands
[1].reg
== REG_PC
),
7513 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7514 || inst
.reloc
.exp
.X_add_number
!= 0,
7515 _("offset must be zero in ARM encoding"));
7517 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
7519 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7520 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7521 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7527 constraint (inst
.operands
[0].reg
% 2 != 0,
7528 _("even register required"));
7529 constraint (inst
.operands
[1].present
7530 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7531 _("can only load two consecutive registers"));
7532 /* If op 1 were present and equal to PC, this function wouldn't
7533 have been called in the first place. */
7534 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7536 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7537 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7543 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7544 if (!inst
.operands
[1].isreg
)
7545 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7547 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7553 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7555 if (inst
.operands
[1].preind
)
7557 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7558 || inst
.reloc
.exp
.X_add_number
!= 0,
7559 _("this instruction requires a post-indexed address"));
7561 inst
.operands
[1].preind
= 0;
7562 inst
.operands
[1].postind
= 1;
7563 inst
.operands
[1].writeback
= 1;
7565 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7566 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7569 /* Halfword and signed-byte load/store operations. */
7574 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7575 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7576 if (!inst
.operands
[1].isreg
)
7577 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7579 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7585 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7587 if (inst
.operands
[1].preind
)
7589 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7590 || inst
.reloc
.exp
.X_add_number
!= 0,
7591 _("this instruction requires a post-indexed address"));
7593 inst
.operands
[1].preind
= 0;
7594 inst
.operands
[1].postind
= 1;
7595 inst
.operands
[1].writeback
= 1;
7597 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7598 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7601 /* Co-processor register load/store.
7602 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7606 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7607 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7608 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7614 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7615 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7616 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7617 && !(inst
.instruction
& 0x00400000))
7618 as_tsktsk (_("Rd and Rm should be different in mla"));
7620 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7621 inst
.instruction
|= inst
.operands
[1].reg
;
7622 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7623 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7629 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7630 encode_arm_shifter_operand (1);
7633 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7640 top
= (inst
.instruction
& 0x00400000) != 0;
7641 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7642 _(":lower16: not allowed this instruction"));
7643 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7644 _(":upper16: not allowed instruction"));
7645 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7646 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7648 imm
= inst
.reloc
.exp
.X_add_number
;
7649 /* The value is in two pieces: 0:11, 16:19. */
7650 inst
.instruction
|= (imm
& 0x00000fff);
7651 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7655 static void do_vfp_nsyn_opcode (const char *);
7658 do_vfp_nsyn_mrs (void)
7660 if (inst
.operands
[0].isvec
)
7662 if (inst
.operands
[1].reg
!= 1)
7663 first_error (_("operand 1 must be FPSCR"));
7664 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7665 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7666 do_vfp_nsyn_opcode ("fmstat");
7668 else if (inst
.operands
[1].isvec
)
7669 do_vfp_nsyn_opcode ("fmrx");
7677 do_vfp_nsyn_msr (void)
7679 if (inst
.operands
[0].isvec
)
7680 do_vfp_nsyn_opcode ("fmxr");
7690 unsigned Rt
= inst
.operands
[0].reg
;
7692 if (thumb_mode
&& inst
.operands
[0].reg
== REG_SP
)
7694 inst
.error
= BAD_SP
;
7698 /* APSR_ sets isvec. All other refs to PC are illegal. */
7699 if (!inst
.operands
[0].isvec
&& inst
.operands
[0].reg
== REG_PC
)
7701 inst
.error
= BAD_PC
;
7705 if (inst
.operands
[1].reg
!= 1)
7706 first_error (_("operand 1 must be FPSCR"));
7708 inst
.instruction
|= (Rt
<< 12);
7714 unsigned Rt
= inst
.operands
[1].reg
;
7717 reject_bad_reg (Rt
);
7718 else if (Rt
== REG_PC
)
7720 inst
.error
= BAD_PC
;
7724 if (inst
.operands
[0].reg
!= 1)
7725 first_error (_("operand 0 must be FPSCR"));
7727 inst
.instruction
|= (Rt
<< 12);
7733 if (do_vfp_nsyn_mrs () == SUCCESS
)
7736 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7737 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7739 _("'CPSR' or 'SPSR' expected"));
7740 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7741 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7742 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7745 /* Two possible forms:
7746 "{C|S}PSR_<field>, Rm",
7747 "{C|S}PSR_f, #expression". */
7752 if (do_vfp_nsyn_msr () == SUCCESS
)
7755 inst
.instruction
|= inst
.operands
[0].imm
;
7756 if (inst
.operands
[1].isreg
)
7757 inst
.instruction
|= inst
.operands
[1].reg
;
7760 inst
.instruction
|= INST_IMMEDIATE
;
7761 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7762 inst
.reloc
.pc_rel
= 0;
7769 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
7771 if (!inst
.operands
[2].present
)
7772 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7773 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7774 inst
.instruction
|= inst
.operands
[1].reg
;
7775 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7777 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7778 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7779 as_tsktsk (_("Rd and Rm should be different in mul"));
7782 /* Long Multiply Parser
7783 UMULL RdLo, RdHi, Rm, Rs
7784 SMULL RdLo, RdHi, Rm, Rs
7785 UMLAL RdLo, RdHi, Rm, Rs
7786 SMLAL RdLo, RdHi, Rm, Rs. */
7791 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7792 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7793 inst
.instruction
|= inst
.operands
[2].reg
;
7794 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7796 /* rdhi and rdlo must be different. */
7797 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7798 as_tsktsk (_("rdhi and rdlo must be different"));
7800 /* rdhi, rdlo and rm must all be different before armv6. */
7801 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7802 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7803 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7804 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7810 if (inst
.operands
[0].present
7811 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
7813 /* Architectural NOP hints are CPSR sets with no bits selected. */
7814 inst
.instruction
&= 0xf0000000;
7815 inst
.instruction
|= 0x0320f000;
7816 if (inst
.operands
[0].present
)
7817 inst
.instruction
|= inst
.operands
[0].imm
;
7821 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7822 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7823 Condition defaults to COND_ALWAYS.
7824 Error if Rd, Rn or Rm are R15. */
7829 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7830 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7831 inst
.instruction
|= inst
.operands
[2].reg
;
7832 if (inst
.operands
[3].present
)
7833 encode_arm_shift (3);
7836 /* ARM V6 PKHTB (Argument Parse). */
7841 if (!inst
.operands
[3].present
)
7843 /* If the shift specifier is omitted, turn the instruction
7844 into pkhbt rd, rm, rn. */
7845 inst
.instruction
&= 0xfff00010;
7846 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7847 inst
.instruction
|= inst
.operands
[1].reg
;
7848 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7852 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7853 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7854 inst
.instruction
|= inst
.operands
[2].reg
;
7855 encode_arm_shift (3);
7859 /* ARMv5TE: Preload-Cache
7863 Syntactically, like LDR with B=1, W=0, L=1. */
7868 constraint (!inst
.operands
[0].isreg
,
7869 _("'[' expected after PLD mnemonic"));
7870 constraint (inst
.operands
[0].postind
,
7871 _("post-indexed expression used in preload instruction"));
7872 constraint (inst
.operands
[0].writeback
,
7873 _("writeback used in preload instruction"));
7874 constraint (!inst
.operands
[0].preind
,
7875 _("unindexed addressing used in preload instruction"));
7876 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7879 /* ARMv7: PLI <addr_mode> */
7883 constraint (!inst
.operands
[0].isreg
,
7884 _("'[' expected after PLI mnemonic"));
7885 constraint (inst
.operands
[0].postind
,
7886 _("post-indexed expression used in preload instruction"));
7887 constraint (inst
.operands
[0].writeback
,
7888 _("writeback used in preload instruction"));
7889 constraint (!inst
.operands
[0].preind
,
7890 _("unindexed addressing used in preload instruction"));
7891 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7892 inst
.instruction
&= ~PRE_INDEX
;
7898 inst
.operands
[1] = inst
.operands
[0];
7899 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7900 inst
.operands
[0].isreg
= 1;
7901 inst
.operands
[0].writeback
= 1;
7902 inst
.operands
[0].reg
= REG_SP
;
7906 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7907 word at the specified address and the following word
7909 Unconditionally executed.
7910 Error if Rn is R15. */
7915 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7916 if (inst
.operands
[0].writeback
)
7917 inst
.instruction
|= WRITE_BACK
;
7920 /* ARM V6 ssat (argument parse). */
7925 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7926 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7927 inst
.instruction
|= inst
.operands
[2].reg
;
7929 if (inst
.operands
[3].present
)
7930 encode_arm_shift (3);
7933 /* ARM V6 usat (argument parse). */
7938 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7939 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7940 inst
.instruction
|= inst
.operands
[2].reg
;
7942 if (inst
.operands
[3].present
)
7943 encode_arm_shift (3);
7946 /* ARM V6 ssat16 (argument parse). */
7951 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7952 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7953 inst
.instruction
|= inst
.operands
[2].reg
;
7959 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7960 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7961 inst
.instruction
|= inst
.operands
[2].reg
;
7964 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7965 preserving the other bits.
7967 setend <endian_specifier>, where <endian_specifier> is either
7973 if (inst
.operands
[0].imm
)
7974 inst
.instruction
|= 0x200;
7980 unsigned int Rm
= (inst
.operands
[1].present
7981 ? inst
.operands
[1].reg
7982 : inst
.operands
[0].reg
);
7984 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7985 inst
.instruction
|= Rm
;
7986 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7988 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7989 inst
.instruction
|= SHIFT_BY_REG
;
7992 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7998 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7999 inst
.reloc
.pc_rel
= 0;
8005 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
8006 inst
.reloc
.pc_rel
= 0;
8009 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8010 SMLAxy{cond} Rd,Rm,Rs,Rn
8011 SMLAWy{cond} Rd,Rm,Rs,Rn
8012 Error if any register is R15. */
8017 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8018 inst
.instruction
|= inst
.operands
[1].reg
;
8019 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8020 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8023 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8024 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8025 Error if any register is R15.
8026 Warning if Rdlo == Rdhi. */
8031 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8032 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8033 inst
.instruction
|= inst
.operands
[2].reg
;
8034 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8036 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8037 as_tsktsk (_("rdhi and rdlo must be different"));
8040 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8041 SMULxy{cond} Rd,Rm,Rs
8042 Error if any register is R15. */
8047 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8048 inst
.instruction
|= inst
.operands
[1].reg
;
8049 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8052 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8053 the same for both ARM and Thumb-2. */
8060 if (inst
.operands
[0].present
)
8062 reg
= inst
.operands
[0].reg
;
8063 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
8068 inst
.instruction
|= reg
<< 16;
8069 inst
.instruction
|= inst
.operands
[1].imm
;
8070 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8071 inst
.instruction
|= WRITE_BACK
;
8074 /* ARM V6 strex (argument parse). */
8079 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8080 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8081 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8082 || inst
.operands
[2].negative
8083 /* See comment in do_ldrex(). */
8084 || (inst
.operands
[2].reg
== REG_PC
),
8087 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8088 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8090 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8091 || inst
.reloc
.exp
.X_add_number
!= 0,
8092 _("offset must be zero in ARM encoding"));
8094 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8095 inst
.instruction
|= inst
.operands
[1].reg
;
8096 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8097 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8103 constraint (inst
.operands
[1].reg
% 2 != 0,
8104 _("even register required"));
8105 constraint (inst
.operands
[2].present
8106 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8107 _("can only store two consecutive registers"));
8108 /* If op 2 were present and equal to PC, this function wouldn't
8109 have been called in the first place. */
8110 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8112 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8113 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8114 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8117 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8118 inst
.instruction
|= inst
.operands
[1].reg
;
8119 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8122 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8123 extends it to 32-bits, and adds the result to a value in another
8124 register. You can specify a rotation by 0, 8, 16, or 24 bits
8125 before extracting the 16-bit value.
8126 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8127 Condition defaults to COND_ALWAYS.
8128 Error if any register uses R15. */
8133 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8134 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8135 inst
.instruction
|= inst
.operands
[2].reg
;
8136 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8141 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8142 Condition defaults to COND_ALWAYS.
8143 Error if any register uses R15. */
8148 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8149 inst
.instruction
|= inst
.operands
[1].reg
;
8150 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8153 /* VFP instructions. In a logical order: SP variant first, monad
8154 before dyad, arithmetic then move then load/store. */
8157 do_vfp_sp_monadic (void)
8159 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8160 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8164 do_vfp_sp_dyadic (void)
8166 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8167 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8168 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8172 do_vfp_sp_compare_z (void)
8174 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8178 do_vfp_dp_sp_cvt (void)
8180 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8181 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8185 do_vfp_sp_dp_cvt (void)
8187 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8188 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8192 do_vfp_reg_from_sp (void)
8194 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8195 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8199 do_vfp_reg2_from_sp2 (void)
8201 constraint (inst
.operands
[2].imm
!= 2,
8202 _("only two consecutive VFP SP registers allowed here"));
8203 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8204 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8205 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8209 do_vfp_sp_from_reg (void)
8211 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8212 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8216 do_vfp_sp2_from_reg2 (void)
8218 constraint (inst
.operands
[0].imm
!= 2,
8219 _("only two consecutive VFP SP registers allowed here"));
8220 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8221 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8222 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8226 do_vfp_sp_ldst (void)
8228 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8229 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8233 do_vfp_dp_ldst (void)
8235 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8236 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8241 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8243 if (inst
.operands
[0].writeback
)
8244 inst
.instruction
|= WRITE_BACK
;
8246 constraint (ldstm_type
!= VFP_LDSTMIA
,
8247 _("this addressing mode requires base-register writeback"));
8248 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8249 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8250 inst
.instruction
|= inst
.operands
[1].imm
;
8254 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8258 if (inst
.operands
[0].writeback
)
8259 inst
.instruction
|= WRITE_BACK
;
8261 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8262 _("this addressing mode requires base-register writeback"));
8264 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8265 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8267 count
= inst
.operands
[1].imm
<< 1;
8268 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8271 inst
.instruction
|= count
;
8275 do_vfp_sp_ldstmia (void)
8277 vfp_sp_ldstm (VFP_LDSTMIA
);
8281 do_vfp_sp_ldstmdb (void)
8283 vfp_sp_ldstm (VFP_LDSTMDB
);
8287 do_vfp_dp_ldstmia (void)
8289 vfp_dp_ldstm (VFP_LDSTMIA
);
8293 do_vfp_dp_ldstmdb (void)
8295 vfp_dp_ldstm (VFP_LDSTMDB
);
8299 do_vfp_xp_ldstmia (void)
8301 vfp_dp_ldstm (VFP_LDSTMIAX
);
8305 do_vfp_xp_ldstmdb (void)
8307 vfp_dp_ldstm (VFP_LDSTMDBX
);
8311 do_vfp_dp_rd_rm (void)
8313 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8314 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8318 do_vfp_dp_rn_rd (void)
8320 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8321 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8325 do_vfp_dp_rd_rn (void)
8327 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8328 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8332 do_vfp_dp_rd_rn_rm (void)
8334 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8335 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8336 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8342 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8346 do_vfp_dp_rm_rd_rn (void)
8348 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8349 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8350 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8353 /* VFPv3 instructions. */
8355 do_vfp_sp_const (void)
8357 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8358 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8359 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8363 do_vfp_dp_const (void)
8365 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8366 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8367 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8371 vfp_conv (int srcsize
)
8373 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
8374 inst
.instruction
|= (immbits
& 1) << 5;
8375 inst
.instruction
|= (immbits
>> 1);
8379 do_vfp_sp_conv_16 (void)
8381 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8386 do_vfp_dp_conv_16 (void)
8388 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8393 do_vfp_sp_conv_32 (void)
8395 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8400 do_vfp_dp_conv_32 (void)
8402 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8406 /* FPA instructions. Also in a logical order. */
8411 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8412 inst
.instruction
|= inst
.operands
[1].reg
;
8416 do_fpa_ldmstm (void)
8418 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8419 switch (inst
.operands
[1].imm
)
8421 case 1: inst
.instruction
|= CP_T_X
; break;
8422 case 2: inst
.instruction
|= CP_T_Y
; break;
8423 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8428 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8430 /* The instruction specified "ea" or "fd", so we can only accept
8431 [Rn]{!}. The instruction does not really support stacking or
8432 unstacking, so we have to emulate these by setting appropriate
8433 bits and offsets. */
8434 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8435 || inst
.reloc
.exp
.X_add_number
!= 0,
8436 _("this instruction does not support indexing"));
8438 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8439 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8441 if (!(inst
.instruction
& INDEX_UP
))
8442 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8444 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8446 inst
.operands
[2].preind
= 0;
8447 inst
.operands
[2].postind
= 1;
8451 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8454 /* iWMMXt instructions: strictly in alphabetical order. */
8457 do_iwmmxt_tandorc (void)
8459 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8463 do_iwmmxt_textrc (void)
8465 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8466 inst
.instruction
|= inst
.operands
[1].imm
;
8470 do_iwmmxt_textrm (void)
8472 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8473 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8474 inst
.instruction
|= inst
.operands
[2].imm
;
8478 do_iwmmxt_tinsr (void)
8480 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8481 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8482 inst
.instruction
|= inst
.operands
[2].imm
;
8486 do_iwmmxt_tmia (void)
8488 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8489 inst
.instruction
|= inst
.operands
[1].reg
;
8490 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8494 do_iwmmxt_waligni (void)
8496 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8497 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8498 inst
.instruction
|= inst
.operands
[2].reg
;
8499 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8503 do_iwmmxt_wmerge (void)
8505 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8506 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8507 inst
.instruction
|= inst
.operands
[2].reg
;
8508 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8512 do_iwmmxt_wmov (void)
8514 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8515 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8516 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8517 inst
.instruction
|= inst
.operands
[1].reg
;
8521 do_iwmmxt_wldstbh (void)
8524 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8526 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8528 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8529 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8533 do_iwmmxt_wldstw (void)
8535 /* RIWR_RIWC clears .isreg for a control register. */
8536 if (!inst
.operands
[0].isreg
)
8538 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8539 inst
.instruction
|= 0xf0000000;
8542 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8543 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8547 do_iwmmxt_wldstd (void)
8549 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8550 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8551 && inst
.operands
[1].immisreg
)
8553 inst
.instruction
&= ~0x1a000ff;
8554 inst
.instruction
|= (0xf << 28);
8555 if (inst
.operands
[1].preind
)
8556 inst
.instruction
|= PRE_INDEX
;
8557 if (!inst
.operands
[1].negative
)
8558 inst
.instruction
|= INDEX_UP
;
8559 if (inst
.operands
[1].writeback
)
8560 inst
.instruction
|= WRITE_BACK
;
8561 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8562 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8563 inst
.instruction
|= inst
.operands
[1].imm
;
8566 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8570 do_iwmmxt_wshufh (void)
8572 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8573 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8574 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8575 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8579 do_iwmmxt_wzero (void)
8581 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8582 inst
.instruction
|= inst
.operands
[0].reg
;
8583 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8584 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8588 do_iwmmxt_wrwrwr_or_imm5 (void)
8590 if (inst
.operands
[2].isreg
)
8593 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8594 _("immediate operand requires iWMMXt2"));
8596 if (inst
.operands
[2].imm
== 0)
8598 switch ((inst
.instruction
>> 20) & 0xf)
8604 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8605 inst
.operands
[2].imm
= 16;
8606 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8612 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8613 inst
.operands
[2].imm
= 32;
8614 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8621 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8623 wrn
= (inst
.instruction
>> 16) & 0xf;
8624 inst
.instruction
&= 0xff0fff0f;
8625 inst
.instruction
|= wrn
;
8626 /* Bail out here; the instruction is now assembled. */
8631 /* Map 32 -> 0, etc. */
8632 inst
.operands
[2].imm
&= 0x1f;
8633 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8637 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8638 operations first, then control, shift, and load/store. */
8640 /* Insns like "foo X,Y,Z". */
8643 do_mav_triple (void)
8645 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8646 inst
.instruction
|= inst
.operands
[1].reg
;
8647 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8650 /* Insns like "foo W,X,Y,Z".
8651 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8656 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8657 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8658 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8659 inst
.instruction
|= inst
.operands
[3].reg
;
8662 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8666 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8669 /* Maverick shift immediate instructions.
8670 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8671 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8676 int imm
= inst
.operands
[2].imm
;
8678 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8679 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8681 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8682 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8683 Bit 4 should be 0. */
8684 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8686 inst
.instruction
|= imm
;
8689 /* XScale instructions. Also sorted arithmetic before move. */
8691 /* Xscale multiply-accumulate (argument parse)
8694 MIAxycc acc0,Rm,Rs. */
8699 inst
.instruction
|= inst
.operands
[1].reg
;
8700 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8703 /* Xscale move-accumulator-register (argument parse)
8705 MARcc acc0,RdLo,RdHi. */
8710 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8711 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8714 /* Xscale move-register-accumulator (argument parse)
8716 MRAcc RdLo,RdHi,acc0. */
8721 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8722 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8723 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8726 /* Encoding functions relevant only to Thumb. */
8728 /* inst.operands[i] is a shifted-register operand; encode
8729 it into inst.instruction in the format used by Thumb32. */
8732 encode_thumb32_shifted_operand (int i
)
8734 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8735 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8737 constraint (inst
.operands
[i
].immisreg
,
8738 _("shift by register not allowed in thumb mode"));
8739 inst
.instruction
|= inst
.operands
[i
].reg
;
8740 if (shift
== SHIFT_RRX
)
8741 inst
.instruction
|= SHIFT_ROR
<< 4;
8744 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8745 _("expression too complex"));
8747 constraint (value
> 32
8748 || (value
== 32 && (shift
== SHIFT_LSL
8749 || shift
== SHIFT_ROR
)),
8750 _("shift expression is too large"));
8754 else if (value
== 32)
8757 inst
.instruction
|= shift
<< 4;
8758 inst
.instruction
|= (value
& 0x1c) << 10;
8759 inst
.instruction
|= (value
& 0x03) << 6;
8764 /* inst.operands[i] was set up by parse_address. Encode it into a
8765 Thumb32 format load or store instruction. Reject forms that cannot
8766 be used with such instructions. If is_t is true, reject forms that
8767 cannot be used with a T instruction; if is_d is true, reject forms
8768 that cannot be used with a D instruction. If it is a store insn,
8772 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8774 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8776 constraint (!inst
.operands
[i
].isreg
,
8777 _("Instruction does not support =N addresses"));
8779 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8780 if (inst
.operands
[i
].immisreg
)
8782 constraint (is_pc
, BAD_PC_ADDRESSING
);
8783 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8784 constraint (inst
.operands
[i
].negative
,
8785 _("Thumb does not support negative register indexing"));
8786 constraint (inst
.operands
[i
].postind
,
8787 _("Thumb does not support register post-indexing"));
8788 constraint (inst
.operands
[i
].writeback
,
8789 _("Thumb does not support register indexing with writeback"));
8790 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8791 _("Thumb supports only LSL in shifted register indexing"));
8793 inst
.instruction
|= inst
.operands
[i
].imm
;
8794 if (inst
.operands
[i
].shifted
)
8796 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8797 _("expression too complex"));
8798 constraint (inst
.reloc
.exp
.X_add_number
< 0
8799 || inst
.reloc
.exp
.X_add_number
> 3,
8800 _("shift out of range"));
8801 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8803 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8805 else if (inst
.operands
[i
].preind
)
8807 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
8808 constraint (is_t
&& inst
.operands
[i
].writeback
,
8809 _("cannot use writeback with this instruction"));
8810 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0)
8811 && !inst
.reloc
.pc_rel
, BAD_PC_ADDRESSING
);
8815 inst
.instruction
|= 0x01000000;
8816 if (inst
.operands
[i
].writeback
)
8817 inst
.instruction
|= 0x00200000;
8821 inst
.instruction
|= 0x00000c00;
8822 if (inst
.operands
[i
].writeback
)
8823 inst
.instruction
|= 0x00000100;
8825 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8827 else if (inst
.operands
[i
].postind
)
8829 gas_assert (inst
.operands
[i
].writeback
);
8830 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8831 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8834 inst
.instruction
|= 0x00200000;
8836 inst
.instruction
|= 0x00000900;
8837 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8839 else /* unindexed - only for coprocessor */
8840 inst
.error
= _("instruction does not accept unindexed addressing");
8843 /* Table of Thumb instructions which exist in both 16- and 32-bit
8844 encodings (the latter only in post-V6T2 cores). The index is the
8845 value used in the insns table below. When there is more than one
8846 possible 16-bit encoding for the instruction, this table always
8848 Also contains several pseudo-instructions used during relaxation. */
8849 #define T16_32_TAB \
8850 X(_adc, 4140, eb400000), \
8851 X(_adcs, 4140, eb500000), \
8852 X(_add, 1c00, eb000000), \
8853 X(_adds, 1c00, eb100000), \
8854 X(_addi, 0000, f1000000), \
8855 X(_addis, 0000, f1100000), \
8856 X(_add_pc,000f, f20f0000), \
8857 X(_add_sp,000d, f10d0000), \
8858 X(_adr, 000f, f20f0000), \
8859 X(_and, 4000, ea000000), \
8860 X(_ands, 4000, ea100000), \
8861 X(_asr, 1000, fa40f000), \
8862 X(_asrs, 1000, fa50f000), \
8863 X(_b, e000, f000b000), \
8864 X(_bcond, d000, f0008000), \
8865 X(_bic, 4380, ea200000), \
8866 X(_bics, 4380, ea300000), \
8867 X(_cmn, 42c0, eb100f00), \
8868 X(_cmp, 2800, ebb00f00), \
8869 X(_cpsie, b660, f3af8400), \
8870 X(_cpsid, b670, f3af8600), \
8871 X(_cpy, 4600, ea4f0000), \
8872 X(_dec_sp,80dd, f1ad0d00), \
8873 X(_eor, 4040, ea800000), \
8874 X(_eors, 4040, ea900000), \
8875 X(_inc_sp,00dd, f10d0d00), \
8876 X(_ldmia, c800, e8900000), \
8877 X(_ldr, 6800, f8500000), \
8878 X(_ldrb, 7800, f8100000), \
8879 X(_ldrh, 8800, f8300000), \
8880 X(_ldrsb, 5600, f9100000), \
8881 X(_ldrsh, 5e00, f9300000), \
8882 X(_ldr_pc,4800, f85f0000), \
8883 X(_ldr_pc2,4800, f85f0000), \
8884 X(_ldr_sp,9800, f85d0000), \
8885 X(_lsl, 0000, fa00f000), \
8886 X(_lsls, 0000, fa10f000), \
8887 X(_lsr, 0800, fa20f000), \
8888 X(_lsrs, 0800, fa30f000), \
8889 X(_mov, 2000, ea4f0000), \
8890 X(_movs, 2000, ea5f0000), \
8891 X(_mul, 4340, fb00f000), \
8892 X(_muls, 4340, ffffffff), /* no 32b muls */ \
8893 X(_mvn, 43c0, ea6f0000), \
8894 X(_mvns, 43c0, ea7f0000), \
8895 X(_neg, 4240, f1c00000), /* rsb #0 */ \
8896 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
8897 X(_orr, 4300, ea400000), \
8898 X(_orrs, 4300, ea500000), \
8899 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8900 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
8901 X(_rev, ba00, fa90f080), \
8902 X(_rev16, ba40, fa90f090), \
8903 X(_revsh, bac0, fa90f0b0), \
8904 X(_ror, 41c0, fa60f000), \
8905 X(_rors, 41c0, fa70f000), \
8906 X(_sbc, 4180, eb600000), \
8907 X(_sbcs, 4180, eb700000), \
8908 X(_stmia, c000, e8800000), \
8909 X(_str, 6000, f8400000), \
8910 X(_strb, 7000, f8000000), \
8911 X(_strh, 8000, f8200000), \
8912 X(_str_sp,9000, f84d0000), \
8913 X(_sub, 1e00, eba00000), \
8914 X(_subs, 1e00, ebb00000), \
8915 X(_subi, 8000, f1a00000), \
8916 X(_subis, 8000, f1b00000), \
8917 X(_sxtb, b240, fa4ff080), \
8918 X(_sxth, b200, fa0ff080), \
8919 X(_tst, 4200, ea100f00), \
8920 X(_uxtb, b2c0, fa5ff080), \
8921 X(_uxth, b280, fa1ff080), \
8922 X(_nop, bf00, f3af8000), \
8923 X(_yield, bf10, f3af8001), \
8924 X(_wfe, bf20, f3af8002), \
8925 X(_wfi, bf30, f3af8003), \
8926 X(_sev, bf40, f3af8004),
8928 /* To catch errors in encoding functions, the codes are all offset by
8929 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8930 as 16-bit instructions. */
8931 #define X(a,b,c) T_MNEM##a
8932 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8935 #define X(a,b,c) 0x##b
8936 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8937 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8940 #define X(a,b,c) 0x##c
8941 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8942 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8943 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8947 /* Thumb instruction encoders, in alphabetical order. */
8952 do_t_add_sub_w (void)
8956 Rd
= inst
.operands
[0].reg
;
8957 Rn
= inst
.operands
[1].reg
;
8959 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
8960 is the SP-{plus,minus}-immediate form of the instruction. */
8962 constraint (Rd
== REG_PC
, BAD_PC
);
8964 reject_bad_reg (Rd
);
8966 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8967 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8970 /* Parse an add or subtract instruction. We get here with inst.instruction
8971 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8978 Rd
= inst
.operands
[0].reg
;
8979 Rs
= (inst
.operands
[1].present
8980 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8981 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8984 set_it_insn_type_last ();
8992 flags
= (inst
.instruction
== T_MNEM_adds
8993 || inst
.instruction
== T_MNEM_subs
);
8995 narrow
= !in_it_block ();
8997 narrow
= in_it_block ();
8998 if (!inst
.operands
[2].isreg
)
9002 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9004 add
= (inst
.instruction
== T_MNEM_add
9005 || inst
.instruction
== T_MNEM_adds
);
9007 if (inst
.size_req
!= 4)
9009 /* Attempt to use a narrow opcode, with relaxation if
9011 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
9012 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
9013 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
9014 opcode
= T_MNEM_add_sp
;
9015 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
9016 opcode
= T_MNEM_add_pc
;
9017 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
9020 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
9022 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
9026 inst
.instruction
= THUMB_OP16(opcode
);
9027 inst
.instruction
|= (Rd
<< 4) | Rs
;
9028 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9029 if (inst
.size_req
!= 2)
9030 inst
.relax
= opcode
;
9033 constraint (inst
.size_req
== 2, BAD_HIREG
);
9035 if (inst
.size_req
== 4
9036 || (inst
.size_req
!= 2 && !opcode
))
9040 constraint (add
, BAD_PC
);
9041 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
9042 _("only SUBS PC, LR, #const allowed"));
9043 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9044 _("expression too complex"));
9045 constraint (inst
.reloc
.exp
.X_add_number
< 0
9046 || inst
.reloc
.exp
.X_add_number
> 0xff,
9047 _("immediate value out of range"));
9048 inst
.instruction
= T2_SUBS_PC_LR
9049 | inst
.reloc
.exp
.X_add_number
;
9050 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9053 else if (Rs
== REG_PC
)
9055 /* Always use addw/subw. */
9056 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
9057 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9061 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9062 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
9065 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9067 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
9069 inst
.instruction
|= Rd
<< 8;
9070 inst
.instruction
|= Rs
<< 16;
9075 Rn
= inst
.operands
[2].reg
;
9076 /* See if we can do this with a 16-bit instruction. */
9077 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9079 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9084 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9085 || inst
.instruction
== T_MNEM_add
)
9088 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9092 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9094 /* Thumb-1 cores (except v6-M) require at least one high
9095 register in a narrow non flag setting add. */
9096 if (Rd
> 7 || Rn
> 7
9097 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9098 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9105 inst
.instruction
= T_OPCODE_ADD_HI
;
9106 inst
.instruction
|= (Rd
& 8) << 4;
9107 inst
.instruction
|= (Rd
& 7);
9108 inst
.instruction
|= Rn
<< 3;
9114 constraint (Rd
== REG_PC
, BAD_PC
);
9115 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9116 constraint (Rs
== REG_PC
, BAD_PC
);
9117 reject_bad_reg (Rn
);
9119 /* If we get here, it can't be done in 16 bits. */
9120 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9121 _("shift must be constant"));
9122 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9123 inst
.instruction
|= Rd
<< 8;
9124 inst
.instruction
|= Rs
<< 16;
9125 encode_thumb32_shifted_operand (2);
9130 constraint (inst
.instruction
== T_MNEM_adds
9131 || inst
.instruction
== T_MNEM_subs
,
9134 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9136 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9137 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9140 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9142 inst
.instruction
|= (Rd
<< 4) | Rs
;
9143 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9147 Rn
= inst
.operands
[2].reg
;
9148 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9150 /* We now have Rd, Rs, and Rn set to registers. */
9151 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9153 /* Can't do this for SUB. */
9154 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9155 inst
.instruction
= T_OPCODE_ADD_HI
;
9156 inst
.instruction
|= (Rd
& 8) << 4;
9157 inst
.instruction
|= (Rd
& 7);
9159 inst
.instruction
|= Rn
<< 3;
9161 inst
.instruction
|= Rs
<< 3;
9163 constraint (1, _("dest must overlap one source register"));
9167 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9168 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9169 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9179 Rd
= inst
.operands
[0].reg
;
9180 reject_bad_reg (Rd
);
9182 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9184 /* Defer to section relaxation. */
9185 inst
.relax
= inst
.instruction
;
9186 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9187 inst
.instruction
|= Rd
<< 4;
9189 else if (unified_syntax
&& inst
.size_req
!= 2)
9191 /* Generate a 32-bit opcode. */
9192 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9193 inst
.instruction
|= Rd
<< 8;
9194 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9195 inst
.reloc
.pc_rel
= 1;
9199 /* Generate a 16-bit opcode. */
9200 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9201 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9202 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9203 inst
.reloc
.pc_rel
= 1;
9205 inst
.instruction
|= Rd
<< 4;
9209 /* Arithmetic instructions for which there is just one 16-bit
9210 instruction encoding, and it allows only two low registers.
9211 For maximal compatibility with ARM syntax, we allow three register
9212 operands even when Thumb-32 instructions are not available, as long
9213 as the first two are identical. For instance, both "sbc r0,r1" and
9214 "sbc r0,r0,r1" are allowed. */
9220 Rd
= inst
.operands
[0].reg
;
9221 Rs
= (inst
.operands
[1].present
9222 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9223 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9224 Rn
= inst
.operands
[2].reg
;
9226 reject_bad_reg (Rd
);
9227 reject_bad_reg (Rs
);
9228 if (inst
.operands
[2].isreg
)
9229 reject_bad_reg (Rn
);
9233 if (!inst
.operands
[2].isreg
)
9235 /* For an immediate, we always generate a 32-bit opcode;
9236 section relaxation will shrink it later if possible. */
9237 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9238 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9239 inst
.instruction
|= Rd
<< 8;
9240 inst
.instruction
|= Rs
<< 16;
9241 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9247 /* See if we can do this with a 16-bit instruction. */
9248 if (THUMB_SETS_FLAGS (inst
.instruction
))
9249 narrow
= !in_it_block ();
9251 narrow
= in_it_block ();
9253 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9255 if (inst
.operands
[2].shifted
)
9257 if (inst
.size_req
== 4)
9263 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9264 inst
.instruction
|= Rd
;
9265 inst
.instruction
|= Rn
<< 3;
9269 /* If we get here, it can't be done in 16 bits. */
9270 constraint (inst
.operands
[2].shifted
9271 && inst
.operands
[2].immisreg
,
9272 _("shift must be constant"));
9273 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9274 inst
.instruction
|= Rd
<< 8;
9275 inst
.instruction
|= Rs
<< 16;
9276 encode_thumb32_shifted_operand (2);
9281 /* On its face this is a lie - the instruction does set the
9282 flags. However, the only supported mnemonic in this mode
9284 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9286 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9287 _("unshifted register required"));
9288 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9289 constraint (Rd
!= Rs
,
9290 _("dest and source1 must be the same register"));
9292 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9293 inst
.instruction
|= Rd
;
9294 inst
.instruction
|= Rn
<< 3;
9298 /* Similarly, but for instructions where the arithmetic operation is
9299 commutative, so we can allow either of them to be different from
9300 the destination operand in a 16-bit instruction. For instance, all
9301 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9308 Rd
= inst
.operands
[0].reg
;
9309 Rs
= (inst
.operands
[1].present
9310 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9311 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9312 Rn
= inst
.operands
[2].reg
;
9314 reject_bad_reg (Rd
);
9315 reject_bad_reg (Rs
);
9316 if (inst
.operands
[2].isreg
)
9317 reject_bad_reg (Rn
);
9321 if (!inst
.operands
[2].isreg
)
9323 /* For an immediate, we always generate a 32-bit opcode;
9324 section relaxation will shrink it later if possible. */
9325 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9326 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9327 inst
.instruction
|= Rd
<< 8;
9328 inst
.instruction
|= Rs
<< 16;
9329 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9335 /* See if we can do this with a 16-bit instruction. */
9336 if (THUMB_SETS_FLAGS (inst
.instruction
))
9337 narrow
= !in_it_block ();
9339 narrow
= in_it_block ();
9341 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9343 if (inst
.operands
[2].shifted
)
9345 if (inst
.size_req
== 4)
9352 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9353 inst
.instruction
|= Rd
;
9354 inst
.instruction
|= Rn
<< 3;
9359 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9360 inst
.instruction
|= Rd
;
9361 inst
.instruction
|= Rs
<< 3;
9366 /* If we get here, it can't be done in 16 bits. */
9367 constraint (inst
.operands
[2].shifted
9368 && inst
.operands
[2].immisreg
,
9369 _("shift must be constant"));
9370 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9371 inst
.instruction
|= Rd
<< 8;
9372 inst
.instruction
|= Rs
<< 16;
9373 encode_thumb32_shifted_operand (2);
9378 /* On its face this is a lie - the instruction does set the
9379 flags. However, the only supported mnemonic in this mode
9381 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9383 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9384 _("unshifted register required"));
9385 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9387 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9388 inst
.instruction
|= Rd
;
9391 inst
.instruction
|= Rn
<< 3;
9393 inst
.instruction
|= Rs
<< 3;
9395 constraint (1, _("dest must overlap one source register"));
9402 if (inst
.operands
[0].present
)
9404 constraint ((inst
.instruction
& 0xf0) != 0x40
9405 && inst
.operands
[0].imm
!= 0xf,
9406 _("bad barrier type"));
9407 inst
.instruction
|= inst
.operands
[0].imm
;
9410 inst
.instruction
|= 0xf;
9417 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9418 constraint (msb
> 32, _("bit-field extends past end of register"));
9419 /* The instruction encoding stores the LSB and MSB,
9420 not the LSB and width. */
9421 Rd
= inst
.operands
[0].reg
;
9422 reject_bad_reg (Rd
);
9423 inst
.instruction
|= Rd
<< 8;
9424 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9425 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9426 inst
.instruction
|= msb
- 1;
9435 Rd
= inst
.operands
[0].reg
;
9436 reject_bad_reg (Rd
);
9438 /* #0 in second position is alternative syntax for bfc, which is
9439 the same instruction but with REG_PC in the Rm field. */
9440 if (!inst
.operands
[1].isreg
)
9444 Rn
= inst
.operands
[1].reg
;
9445 reject_bad_reg (Rn
);
9448 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9449 constraint (msb
> 32, _("bit-field extends past end of register"));
9450 /* The instruction encoding stores the LSB and MSB,
9451 not the LSB and width. */
9452 inst
.instruction
|= Rd
<< 8;
9453 inst
.instruction
|= Rn
<< 16;
9454 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9455 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9456 inst
.instruction
|= msb
- 1;
9464 Rd
= inst
.operands
[0].reg
;
9465 Rn
= inst
.operands
[1].reg
;
9467 reject_bad_reg (Rd
);
9468 reject_bad_reg (Rn
);
9470 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9471 _("bit-field extends past end of register"));
9472 inst
.instruction
|= Rd
<< 8;
9473 inst
.instruction
|= Rn
<< 16;
9474 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9475 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9476 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9479 /* ARM V5 Thumb BLX (argument parse)
9480 BLX <target_addr> which is BLX(1)
9481 BLX <Rm> which is BLX(2)
9482 Unfortunately, there are two different opcodes for this mnemonic.
9483 So, the insns[].value is not used, and the code here zaps values
9484 into inst.instruction.
9486 ??? How to take advantage of the additional two bits of displacement
9487 available in Thumb32 mode? Need new relocation? */
9492 set_it_insn_type_last ();
9494 if (inst
.operands
[0].isreg
)
9496 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9497 /* We have a register, so this is BLX(2). */
9498 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9502 /* No register. This must be BLX(1). */
9503 inst
.instruction
= 0xf000e800;
9504 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
9505 inst
.reloc
.pc_rel
= 1;
9516 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9520 /* Conditional branches inside IT blocks are encoded as unconditional
9527 if (cond
!= COND_ALWAYS
)
9528 opcode
= T_MNEM_bcond
;
9530 opcode
= inst
.instruction
;
9532 if (unified_syntax
&& inst
.size_req
== 4)
9534 inst
.instruction
= THUMB_OP32(opcode
);
9535 if (cond
== COND_ALWAYS
)
9536 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9539 gas_assert (cond
!= 0xF);
9540 inst
.instruction
|= cond
<< 22;
9541 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9546 inst
.instruction
= THUMB_OP16(opcode
);
9547 if (cond
== COND_ALWAYS
)
9548 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9551 inst
.instruction
|= cond
<< 8;
9552 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9554 /* Allow section relaxation. */
9555 if (unified_syntax
&& inst
.size_req
!= 2)
9556 inst
.relax
= opcode
;
9559 inst
.reloc
.pc_rel
= 1;
9565 constraint (inst
.cond
!= COND_ALWAYS
,
9566 _("instruction is always unconditional"));
9567 if (inst
.operands
[0].present
)
9569 constraint (inst
.operands
[0].imm
> 255,
9570 _("immediate value out of range"));
9571 inst
.instruction
|= inst
.operands
[0].imm
;
9572 set_it_insn_type (NEUTRAL_IT_INSN
);
9577 do_t_branch23 (void)
9579 set_it_insn_type_last ();
9580 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9581 inst
.reloc
.pc_rel
= 1;
9583 #if defined(OBJ_COFF)
9584 /* If the destination of the branch is a defined symbol which does not have
9585 the THUMB_FUNC attribute, then we must be calling a function which has
9586 the (interfacearm) attribute. We look for the Thumb entry point to that
9587 function and change the branch to refer to that function instead. */
9588 if ( inst
.reloc
.exp
.X_op
== O_symbol
9589 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9590 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9591 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9592 inst
.reloc
.exp
.X_add_symbol
=
9593 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9600 set_it_insn_type_last ();
9601 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9602 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9603 should cause the alignment to be checked once it is known. This is
9604 because BX PC only works if the instruction is word aligned. */
9612 set_it_insn_type_last ();
9613 Rm
= inst
.operands
[0].reg
;
9614 reject_bad_reg (Rm
);
9615 inst
.instruction
|= Rm
<< 16;
9624 Rd
= inst
.operands
[0].reg
;
9625 Rm
= inst
.operands
[1].reg
;
9627 reject_bad_reg (Rd
);
9628 reject_bad_reg (Rm
);
9630 inst
.instruction
|= Rd
<< 8;
9631 inst
.instruction
|= Rm
<< 16;
9632 inst
.instruction
|= Rm
;
9638 set_it_insn_type (OUTSIDE_IT_INSN
);
9639 inst
.instruction
|= inst
.operands
[0].imm
;
9645 set_it_insn_type (OUTSIDE_IT_INSN
);
9647 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9648 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9650 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9651 inst
.instruction
= 0xf3af8000;
9652 inst
.instruction
|= imod
<< 9;
9653 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9654 if (inst
.operands
[1].present
)
9655 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9659 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9660 && (inst
.operands
[0].imm
& 4),
9661 _("selected processor does not support 'A' form "
9662 "of this instruction"));
9663 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9664 _("Thumb does not support the 2-argument "
9665 "form of this instruction"));
9666 inst
.instruction
|= inst
.operands
[0].imm
;
9670 /* THUMB CPY instruction (argument parse). */
9675 if (inst
.size_req
== 4)
9677 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9678 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9679 inst
.instruction
|= inst
.operands
[1].reg
;
9683 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9684 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9685 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9692 set_it_insn_type (OUTSIDE_IT_INSN
);
9693 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9694 inst
.instruction
|= inst
.operands
[0].reg
;
9695 inst
.reloc
.pc_rel
= 1;
9696 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9702 inst
.instruction
|= inst
.operands
[0].imm
;
9708 unsigned Rd
, Rn
, Rm
;
9710 Rd
= inst
.operands
[0].reg
;
9711 Rn
= (inst
.operands
[1].present
9712 ? inst
.operands
[1].reg
: Rd
);
9713 Rm
= inst
.operands
[2].reg
;
9715 reject_bad_reg (Rd
);
9716 reject_bad_reg (Rn
);
9717 reject_bad_reg (Rm
);
9719 inst
.instruction
|= Rd
<< 8;
9720 inst
.instruction
|= Rn
<< 16;
9721 inst
.instruction
|= Rm
;
9727 if (unified_syntax
&& inst
.size_req
== 4)
9728 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9730 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9736 unsigned int cond
= inst
.operands
[0].imm
;
9738 set_it_insn_type (IT_INSN
);
9739 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
9742 /* If the condition is a negative condition, invert the mask. */
9743 if ((cond
& 0x1) == 0x0)
9745 unsigned int mask
= inst
.instruction
& 0x000f;
9747 if ((mask
& 0x7) == 0)
9748 /* no conversion needed */;
9749 else if ((mask
& 0x3) == 0)
9751 else if ((mask
& 0x1) == 0)
9756 inst
.instruction
&= 0xfff0;
9757 inst
.instruction
|= mask
;
9760 inst
.instruction
|= cond
<< 4;
9763 /* Helper function used for both push/pop and ldm/stm. */
9765 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9769 load
= (inst
.instruction
& (1 << 20)) != 0;
9771 if (mask
& (1 << 13))
9772 inst
.error
= _("SP not allowed in register list");
9774 if ((mask
& (1 << base
)) != 0
9776 inst
.error
= _("having the base register in the register list when "
9777 "using write back is UNPREDICTABLE");
9781 if (mask
& (1 << 15))
9783 if (mask
& (1 << 14))
9784 inst
.error
= _("LR and PC should not both be in register list");
9786 set_it_insn_type_last ();
9791 if (mask
& (1 << 15))
9792 inst
.error
= _("PC not allowed in register list");
9795 if ((mask
& (mask
- 1)) == 0)
9797 /* Single register transfers implemented as str/ldr. */
9800 if (inst
.instruction
& (1 << 23))
9801 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9803 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9807 if (inst
.instruction
& (1 << 23))
9808 inst
.instruction
= 0x00800000; /* ia -> [base] */
9810 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9813 inst
.instruction
|= 0xf8400000;
9815 inst
.instruction
|= 0x00100000;
9817 mask
= ffs (mask
) - 1;
9821 inst
.instruction
|= WRITE_BACK
;
9823 inst
.instruction
|= mask
;
9824 inst
.instruction
|= base
<< 16;
9830 /* This really doesn't seem worth it. */
9831 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9832 _("expression too complex"));
9833 constraint (inst
.operands
[1].writeback
,
9834 _("Thumb load/store multiple does not support {reglist}^"));
9842 /* See if we can use a 16-bit instruction. */
9843 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9844 && inst
.size_req
!= 4
9845 && !(inst
.operands
[1].imm
& ~0xff))
9847 mask
= 1 << inst
.operands
[0].reg
;
9849 if (inst
.operands
[0].reg
<= 7
9850 && (inst
.instruction
== T_MNEM_stmia
9851 ? inst
.operands
[0].writeback
9852 : (inst
.operands
[0].writeback
9853 == !(inst
.operands
[1].imm
& mask
))))
9855 if (inst
.instruction
== T_MNEM_stmia
9856 && (inst
.operands
[1].imm
& mask
)
9857 && (inst
.operands
[1].imm
& (mask
- 1)))
9858 as_warn (_("value stored for r%d is UNKNOWN"),
9859 inst
.operands
[0].reg
);
9861 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9862 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9863 inst
.instruction
|= inst
.operands
[1].imm
;
9866 else if (inst
.operands
[0] .reg
== REG_SP
9867 && inst
.operands
[0].writeback
)
9869 inst
.instruction
= THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9870 ? T_MNEM_push
: T_MNEM_pop
);
9871 inst
.instruction
|= inst
.operands
[1].imm
;
9878 if (inst
.instruction
< 0xffff)
9879 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9881 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
9882 inst
.operands
[0].writeback
);
9887 constraint (inst
.operands
[0].reg
> 7
9888 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9889 constraint (inst
.instruction
!= T_MNEM_ldmia
9890 && inst
.instruction
!= T_MNEM_stmia
,
9891 _("Thumb-2 instruction only valid in unified syntax"));
9892 if (inst
.instruction
== T_MNEM_stmia
)
9894 if (!inst
.operands
[0].writeback
)
9895 as_warn (_("this instruction will write back the base register"));
9896 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9897 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9898 as_warn (_("value stored for r%d is UNKNOWN"),
9899 inst
.operands
[0].reg
);
9903 if (!inst
.operands
[0].writeback
9904 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9905 as_warn (_("this instruction will write back the base register"));
9906 else if (inst
.operands
[0].writeback
9907 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9908 as_warn (_("this instruction will not write back the base register"));
9911 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9912 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9913 inst
.instruction
|= inst
.operands
[1].imm
;
9920 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9921 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9922 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9923 || inst
.operands
[1].negative
,
9926 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9928 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9929 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9930 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9936 if (!inst
.operands
[1].present
)
9938 constraint (inst
.operands
[0].reg
== REG_LR
,
9939 _("r14 not allowed as first register "
9940 "when second register is omitted"));
9941 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9943 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9946 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9947 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9948 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9954 unsigned long opcode
;
9957 if (inst
.operands
[0].isreg
9958 && !inst
.operands
[0].preind
9959 && inst
.operands
[0].reg
== REG_PC
)
9960 set_it_insn_type_last ();
9962 opcode
= inst
.instruction
;
9965 if (!inst
.operands
[1].isreg
)
9967 if (opcode
<= 0xffff)
9968 inst
.instruction
= THUMB_OP32 (opcode
);
9969 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9972 if (inst
.operands
[1].isreg
9973 && !inst
.operands
[1].writeback
9974 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9975 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9977 && inst
.size_req
!= 4)
9979 /* Insn may have a 16-bit form. */
9980 Rn
= inst
.operands
[1].reg
;
9981 if (inst
.operands
[1].immisreg
)
9983 inst
.instruction
= THUMB_OP16 (opcode
);
9985 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9987 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
9988 reject_bad_reg (inst
.operands
[1].imm
);
9990 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9991 && opcode
!= T_MNEM_ldrsb
)
9992 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9993 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
10000 if (inst
.reloc
.pc_rel
)
10001 opcode
= T_MNEM_ldr_pc2
;
10003 opcode
= T_MNEM_ldr_pc
;
10007 if (opcode
== T_MNEM_ldr
)
10008 opcode
= T_MNEM_ldr_sp
;
10010 opcode
= T_MNEM_str_sp
;
10012 inst
.instruction
= inst
.operands
[0].reg
<< 8;
10016 inst
.instruction
= inst
.operands
[0].reg
;
10017 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10019 inst
.instruction
|= THUMB_OP16 (opcode
);
10020 if (inst
.size_req
== 2)
10021 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10023 inst
.relax
= opcode
;
10027 /* Definitely a 32-bit variant. */
10029 /* Do some validations regarding addressing modes. */
10030 if (inst
.operands
[1].immisreg
&& opcode
!= T_MNEM_ldr
10031 && opcode
!= T_MNEM_str
)
10032 reject_bad_reg (inst
.operands
[1].imm
);
10034 inst
.instruction
= THUMB_OP32 (opcode
);
10035 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10036 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10040 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10042 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
10044 /* Only [Rn,Rm] is acceptable. */
10045 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
10046 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
10047 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
10048 || inst
.operands
[1].negative
,
10049 _("Thumb does not support this addressing mode"));
10050 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10054 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10055 if (!inst
.operands
[1].isreg
)
10056 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10059 constraint (!inst
.operands
[1].preind
10060 || inst
.operands
[1].shifted
10061 || inst
.operands
[1].writeback
,
10062 _("Thumb does not support this addressing mode"));
10063 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
10065 constraint (inst
.instruction
& 0x0600,
10066 _("byte or halfword not valid for base register"));
10067 constraint (inst
.operands
[1].reg
== REG_PC
10068 && !(inst
.instruction
& THUMB_LOAD_BIT
),
10069 _("r15 based store not allowed"));
10070 constraint (inst
.operands
[1].immisreg
,
10071 _("invalid base register for register offset"));
10073 if (inst
.operands
[1].reg
== REG_PC
)
10074 inst
.instruction
= T_OPCODE_LDR_PC
;
10075 else if (inst
.instruction
& THUMB_LOAD_BIT
)
10076 inst
.instruction
= T_OPCODE_LDR_SP
;
10078 inst
.instruction
= T_OPCODE_STR_SP
;
10080 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10081 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10085 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10086 if (!inst
.operands
[1].immisreg
)
10088 /* Immediate offset. */
10089 inst
.instruction
|= inst
.operands
[0].reg
;
10090 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10091 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10095 /* Register offset. */
10096 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10097 constraint (inst
.operands
[1].negative
,
10098 _("Thumb does not support this addressing mode"));
10101 switch (inst
.instruction
)
10103 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10104 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10105 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10106 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10107 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10108 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10109 case 0x5600 /* ldrsb */:
10110 case 0x5e00 /* ldrsh */: break;
10114 inst
.instruction
|= inst
.operands
[0].reg
;
10115 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10116 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
10122 if (!inst
.operands
[1].present
)
10124 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10125 constraint (inst
.operands
[0].reg
== REG_LR
,
10126 _("r14 not allowed here"));
10128 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10129 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10130 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10136 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10137 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10143 unsigned Rd
, Rn
, Rm
, Ra
;
10145 Rd
= inst
.operands
[0].reg
;
10146 Rn
= inst
.operands
[1].reg
;
10147 Rm
= inst
.operands
[2].reg
;
10148 Ra
= inst
.operands
[3].reg
;
10150 reject_bad_reg (Rd
);
10151 reject_bad_reg (Rn
);
10152 reject_bad_reg (Rm
);
10153 reject_bad_reg (Ra
);
10155 inst
.instruction
|= Rd
<< 8;
10156 inst
.instruction
|= Rn
<< 16;
10157 inst
.instruction
|= Rm
;
10158 inst
.instruction
|= Ra
<< 12;
10164 unsigned RdLo
, RdHi
, Rn
, Rm
;
10166 RdLo
= inst
.operands
[0].reg
;
10167 RdHi
= inst
.operands
[1].reg
;
10168 Rn
= inst
.operands
[2].reg
;
10169 Rm
= inst
.operands
[3].reg
;
10171 reject_bad_reg (RdLo
);
10172 reject_bad_reg (RdHi
);
10173 reject_bad_reg (Rn
);
10174 reject_bad_reg (Rm
);
10176 inst
.instruction
|= RdLo
<< 12;
10177 inst
.instruction
|= RdHi
<< 8;
10178 inst
.instruction
|= Rn
<< 16;
10179 inst
.instruction
|= Rm
;
10183 do_t_mov_cmp (void)
10187 Rn
= inst
.operands
[0].reg
;
10188 Rm
= inst
.operands
[1].reg
;
10191 set_it_insn_type_last ();
10193 if (unified_syntax
)
10195 int r0off
= (inst
.instruction
== T_MNEM_mov
10196 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10197 unsigned long opcode
;
10198 bfd_boolean narrow
;
10199 bfd_boolean low_regs
;
10201 low_regs
= (Rn
<= 7 && Rm
<= 7);
10202 opcode
= inst
.instruction
;
10203 if (in_it_block ())
10204 narrow
= opcode
!= T_MNEM_movs
;
10206 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10207 if (inst
.size_req
== 4
10208 || inst
.operands
[1].shifted
)
10211 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10212 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10213 && !inst
.operands
[1].shifted
10217 inst
.instruction
= T2_SUBS_PC_LR
;
10221 if (opcode
== T_MNEM_cmp
)
10223 constraint (Rn
== REG_PC
, BAD_PC
);
10226 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10228 warn_deprecated_sp (Rm
);
10229 /* R15 was documented as a valid choice for Rm in ARMv6,
10230 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10231 tools reject R15, so we do too. */
10232 constraint (Rm
== REG_PC
, BAD_PC
);
10235 reject_bad_reg (Rm
);
10237 else if (opcode
== T_MNEM_mov
10238 || opcode
== T_MNEM_movs
)
10240 if (inst
.operands
[1].isreg
)
10242 if (opcode
== T_MNEM_movs
)
10244 reject_bad_reg (Rn
);
10245 reject_bad_reg (Rm
);
10247 else if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10248 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10249 reject_bad_reg (Rm
);
10252 reject_bad_reg (Rn
);
10255 if (!inst
.operands
[1].isreg
)
10257 /* Immediate operand. */
10258 if (!in_it_block () && opcode
== T_MNEM_mov
)
10260 if (low_regs
&& narrow
)
10262 inst
.instruction
= THUMB_OP16 (opcode
);
10263 inst
.instruction
|= Rn
<< 8;
10264 if (inst
.size_req
== 2)
10265 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10267 inst
.relax
= opcode
;
10271 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10272 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10273 inst
.instruction
|= Rn
<< r0off
;
10274 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10277 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10278 && (inst
.instruction
== T_MNEM_mov
10279 || inst
.instruction
== T_MNEM_movs
))
10281 /* Register shifts are encoded as separate shift instructions. */
10282 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10284 if (in_it_block ())
10289 if (inst
.size_req
== 4)
10292 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10298 switch (inst
.operands
[1].shift_kind
)
10301 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10304 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10307 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10310 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10316 inst
.instruction
= opcode
;
10319 inst
.instruction
|= Rn
;
10320 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10325 inst
.instruction
|= CONDS_BIT
;
10327 inst
.instruction
|= Rn
<< 8;
10328 inst
.instruction
|= Rm
<< 16;
10329 inst
.instruction
|= inst
.operands
[1].imm
;
10334 /* Some mov with immediate shift have narrow variants.
10335 Register shifts are handled above. */
10336 if (low_regs
&& inst
.operands
[1].shifted
10337 && (inst
.instruction
== T_MNEM_mov
10338 || inst
.instruction
== T_MNEM_movs
))
10340 if (in_it_block ())
10341 narrow
= (inst
.instruction
== T_MNEM_mov
);
10343 narrow
= (inst
.instruction
== T_MNEM_movs
);
10348 switch (inst
.operands
[1].shift_kind
)
10350 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10351 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10352 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10353 default: narrow
= FALSE
; break;
10359 inst
.instruction
|= Rn
;
10360 inst
.instruction
|= Rm
<< 3;
10361 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10365 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10366 inst
.instruction
|= Rn
<< r0off
;
10367 encode_thumb32_shifted_operand (1);
10371 switch (inst
.instruction
)
10374 inst
.instruction
= T_OPCODE_MOV_HR
;
10375 inst
.instruction
|= (Rn
& 0x8) << 4;
10376 inst
.instruction
|= (Rn
& 0x7);
10377 inst
.instruction
|= Rm
<< 3;
10381 /* We know we have low registers at this point.
10382 Generate LSLS Rd, Rs, #0. */
10383 inst
.instruction
= T_OPCODE_LSL_I
;
10384 inst
.instruction
|= Rn
;
10385 inst
.instruction
|= Rm
<< 3;
10391 inst
.instruction
= T_OPCODE_CMP_LR
;
10392 inst
.instruction
|= Rn
;
10393 inst
.instruction
|= Rm
<< 3;
10397 inst
.instruction
= T_OPCODE_CMP_HR
;
10398 inst
.instruction
|= (Rn
& 0x8) << 4;
10399 inst
.instruction
|= (Rn
& 0x7);
10400 inst
.instruction
|= Rm
<< 3;
10407 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10409 /* PR 10443: Do not silently ignore shifted operands. */
10410 constraint (inst
.operands
[1].shifted
,
10411 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10413 if (inst
.operands
[1].isreg
)
10415 if (Rn
< 8 && Rm
< 8)
10417 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10418 since a MOV instruction produces unpredictable results. */
10419 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10420 inst
.instruction
= T_OPCODE_ADD_I3
;
10422 inst
.instruction
= T_OPCODE_CMP_LR
;
10424 inst
.instruction
|= Rn
;
10425 inst
.instruction
|= Rm
<< 3;
10429 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10430 inst
.instruction
= T_OPCODE_MOV_HR
;
10432 inst
.instruction
= T_OPCODE_CMP_HR
;
10438 constraint (Rn
> 7,
10439 _("only lo regs allowed with immediate"));
10440 inst
.instruction
|= Rn
<< 8;
10441 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10452 top
= (inst
.instruction
& 0x00800000) != 0;
10453 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
10455 constraint (top
, _(":lower16: not allowed this instruction"));
10456 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
10458 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
10460 constraint (!top
, _(":upper16: not allowed this instruction"));
10461 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
10464 Rd
= inst
.operands
[0].reg
;
10465 reject_bad_reg (Rd
);
10467 inst
.instruction
|= Rd
<< 8;
10468 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
10470 imm
= inst
.reloc
.exp
.X_add_number
;
10471 inst
.instruction
|= (imm
& 0xf000) << 4;
10472 inst
.instruction
|= (imm
& 0x0800) << 15;
10473 inst
.instruction
|= (imm
& 0x0700) << 4;
10474 inst
.instruction
|= (imm
& 0x00ff);
10479 do_t_mvn_tst (void)
10483 Rn
= inst
.operands
[0].reg
;
10484 Rm
= inst
.operands
[1].reg
;
10486 if (inst
.instruction
== T_MNEM_cmp
10487 || inst
.instruction
== T_MNEM_cmn
)
10488 constraint (Rn
== REG_PC
, BAD_PC
);
10490 reject_bad_reg (Rn
);
10491 reject_bad_reg (Rm
);
10493 if (unified_syntax
)
10495 int r0off
= (inst
.instruction
== T_MNEM_mvn
10496 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
10497 bfd_boolean narrow
;
10499 if (inst
.size_req
== 4
10500 || inst
.instruction
> 0xffff
10501 || inst
.operands
[1].shifted
10502 || Rn
> 7 || Rm
> 7)
10504 else if (inst
.instruction
== T_MNEM_cmn
)
10506 else if (THUMB_SETS_FLAGS (inst
.instruction
))
10507 narrow
= !in_it_block ();
10509 narrow
= in_it_block ();
10511 if (!inst
.operands
[1].isreg
)
10513 /* For an immediate, we always generate a 32-bit opcode;
10514 section relaxation will shrink it later if possible. */
10515 if (inst
.instruction
< 0xffff)
10516 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10517 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10518 inst
.instruction
|= Rn
<< r0off
;
10519 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10523 /* See if we can do this with a 16-bit instruction. */
10526 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10527 inst
.instruction
|= Rn
;
10528 inst
.instruction
|= Rm
<< 3;
10532 constraint (inst
.operands
[1].shifted
10533 && inst
.operands
[1].immisreg
,
10534 _("shift must be constant"));
10535 if (inst
.instruction
< 0xffff)
10536 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10537 inst
.instruction
|= Rn
<< r0off
;
10538 encode_thumb32_shifted_operand (1);
10544 constraint (inst
.instruction
> 0xffff
10545 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
10546 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
10547 _("unshifted register required"));
10548 constraint (Rn
> 7 || Rm
> 7,
10551 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10552 inst
.instruction
|= Rn
;
10553 inst
.instruction
|= Rm
<< 3;
10563 if (do_vfp_nsyn_mrs () == SUCCESS
)
10566 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
10569 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10570 _("selected processor does not support "
10571 "requested special purpose register"));
10575 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10576 _("selected processor does not support "
10577 "requested special purpose register"));
10578 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10579 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
10580 _("'CPSR' or 'SPSR' expected"));
10583 Rd
= inst
.operands
[0].reg
;
10584 reject_bad_reg (Rd
);
10586 inst
.instruction
|= Rd
<< 8;
10587 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10588 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
10597 if (do_vfp_nsyn_msr () == SUCCESS
)
10600 constraint (!inst
.operands
[1].isreg
,
10601 _("Thumb encoding does not support an immediate here"));
10602 flags
= inst
.operands
[0].imm
;
10605 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10606 _("selected processor does not support "
10607 "requested special purpose register"));
10611 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10612 _("selected processor does not support "
10613 "requested special purpose register"));
10617 Rn
= inst
.operands
[1].reg
;
10618 reject_bad_reg (Rn
);
10620 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10621 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
10622 inst
.instruction
|= (flags
& 0xff);
10623 inst
.instruction
|= Rn
<< 16;
10629 bfd_boolean narrow
;
10630 unsigned Rd
, Rn
, Rm
;
10632 if (!inst
.operands
[2].present
)
10633 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10635 Rd
= inst
.operands
[0].reg
;
10636 Rn
= inst
.operands
[1].reg
;
10637 Rm
= inst
.operands
[2].reg
;
10639 if (unified_syntax
)
10641 if (inst
.size_req
== 4
10647 else if (inst
.instruction
== T_MNEM_muls
)
10648 narrow
= !in_it_block ();
10650 narrow
= in_it_block ();
10654 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
10655 constraint (Rn
> 7 || Rm
> 7,
10662 /* 16-bit MULS/Conditional MUL. */
10663 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10664 inst
.instruction
|= Rd
;
10667 inst
.instruction
|= Rm
<< 3;
10669 inst
.instruction
|= Rn
<< 3;
10671 constraint (1, _("dest must overlap one source register"));
10675 constraint (inst
.instruction
!= T_MNEM_mul
,
10676 _("Thumb-2 MUL must not set flags"));
10678 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10679 inst
.instruction
|= Rd
<< 8;
10680 inst
.instruction
|= Rn
<< 16;
10681 inst
.instruction
|= Rm
<< 0;
10683 reject_bad_reg (Rd
);
10684 reject_bad_reg (Rn
);
10685 reject_bad_reg (Rm
);
10692 unsigned RdLo
, RdHi
, Rn
, Rm
;
10694 RdLo
= inst
.operands
[0].reg
;
10695 RdHi
= inst
.operands
[1].reg
;
10696 Rn
= inst
.operands
[2].reg
;
10697 Rm
= inst
.operands
[3].reg
;
10699 reject_bad_reg (RdLo
);
10700 reject_bad_reg (RdHi
);
10701 reject_bad_reg (Rn
);
10702 reject_bad_reg (Rm
);
10704 inst
.instruction
|= RdLo
<< 12;
10705 inst
.instruction
|= RdHi
<< 8;
10706 inst
.instruction
|= Rn
<< 16;
10707 inst
.instruction
|= Rm
;
10710 as_tsktsk (_("rdhi and rdlo must be different"));
10716 set_it_insn_type (NEUTRAL_IT_INSN
);
10718 if (unified_syntax
)
10720 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
10722 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10723 inst
.instruction
|= inst
.operands
[0].imm
;
10727 /* PR9722: Check for Thumb2 availability before
10728 generating a thumb2 nop instruction. */
10729 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
10731 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10732 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
10735 inst
.instruction
= 0x46c0;
10740 constraint (inst
.operands
[0].present
,
10741 _("Thumb does not support NOP with hints"));
10742 inst
.instruction
= 0x46c0;
10749 if (unified_syntax
)
10751 bfd_boolean narrow
;
10753 if (THUMB_SETS_FLAGS (inst
.instruction
))
10754 narrow
= !in_it_block ();
10756 narrow
= in_it_block ();
10757 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10759 if (inst
.size_req
== 4)
10764 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10765 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10766 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10770 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10771 inst
.instruction
|= inst
.operands
[0].reg
;
10772 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10777 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
10779 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10781 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10782 inst
.instruction
|= inst
.operands
[0].reg
;
10783 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10792 Rd
= inst
.operands
[0].reg
;
10793 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
10795 reject_bad_reg (Rd
);
10796 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
10797 reject_bad_reg (Rn
);
10799 inst
.instruction
|= Rd
<< 8;
10800 inst
.instruction
|= Rn
<< 16;
10802 if (!inst
.operands
[2].isreg
)
10804 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10805 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10811 Rm
= inst
.operands
[2].reg
;
10812 reject_bad_reg (Rm
);
10814 constraint (inst
.operands
[2].shifted
10815 && inst
.operands
[2].immisreg
,
10816 _("shift must be constant"));
10817 encode_thumb32_shifted_operand (2);
10824 unsigned Rd
, Rn
, Rm
;
10826 Rd
= inst
.operands
[0].reg
;
10827 Rn
= inst
.operands
[1].reg
;
10828 Rm
= inst
.operands
[2].reg
;
10830 reject_bad_reg (Rd
);
10831 reject_bad_reg (Rn
);
10832 reject_bad_reg (Rm
);
10834 inst
.instruction
|= Rd
<< 8;
10835 inst
.instruction
|= Rn
<< 16;
10836 inst
.instruction
|= Rm
;
10837 if (inst
.operands
[3].present
)
10839 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
10840 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10841 _("expression too complex"));
10842 inst
.instruction
|= (val
& 0x1c) << 10;
10843 inst
.instruction
|= (val
& 0x03) << 6;
10850 if (!inst
.operands
[3].present
)
10854 inst
.instruction
&= ~0x00000020;
10856 /* PR 10168. Swap the Rm and Rn registers. */
10857 Rtmp
= inst
.operands
[1].reg
;
10858 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
10859 inst
.operands
[2].reg
= Rtmp
;
10867 if (inst
.operands
[0].immisreg
)
10868 reject_bad_reg (inst
.operands
[0].imm
);
10870 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10874 do_t_push_pop (void)
10878 constraint (inst
.operands
[0].writeback
,
10879 _("push/pop do not support {reglist}^"));
10880 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10881 _("expression too complex"));
10883 mask
= inst
.operands
[0].imm
;
10884 if ((mask
& ~0xff) == 0)
10885 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
10886 else if ((inst
.instruction
== T_MNEM_push
10887 && (mask
& ~0xff) == 1 << REG_LR
)
10888 || (inst
.instruction
== T_MNEM_pop
10889 && (mask
& ~0xff) == 1 << REG_PC
))
10891 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10892 inst
.instruction
|= THUMB_PP_PC_LR
;
10893 inst
.instruction
|= mask
& 0xff;
10895 else if (unified_syntax
)
10897 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10898 encode_thumb2_ldmstm (13, mask
, TRUE
);
10902 inst
.error
= _("invalid register list to push/pop instruction");
10912 Rd
= inst
.operands
[0].reg
;
10913 Rm
= inst
.operands
[1].reg
;
10915 reject_bad_reg (Rd
);
10916 reject_bad_reg (Rm
);
10918 inst
.instruction
|= Rd
<< 8;
10919 inst
.instruction
|= Rm
<< 16;
10920 inst
.instruction
|= Rm
;
10928 Rd
= inst
.operands
[0].reg
;
10929 Rm
= inst
.operands
[1].reg
;
10931 reject_bad_reg (Rd
);
10932 reject_bad_reg (Rm
);
10934 if (Rd
<= 7 && Rm
<= 7
10935 && inst
.size_req
!= 4)
10937 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10938 inst
.instruction
|= Rd
;
10939 inst
.instruction
|= Rm
<< 3;
10941 else if (unified_syntax
)
10943 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10944 inst
.instruction
|= Rd
<< 8;
10945 inst
.instruction
|= Rm
<< 16;
10946 inst
.instruction
|= Rm
;
10949 inst
.error
= BAD_HIREG
;
10957 Rd
= inst
.operands
[0].reg
;
10958 Rm
= inst
.operands
[1].reg
;
10960 reject_bad_reg (Rd
);
10961 reject_bad_reg (Rm
);
10963 inst
.instruction
|= Rd
<< 8;
10964 inst
.instruction
|= Rm
;
10972 Rd
= inst
.operands
[0].reg
;
10973 Rs
= (inst
.operands
[1].present
10974 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10975 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10977 reject_bad_reg (Rd
);
10978 reject_bad_reg (Rs
);
10979 if (inst
.operands
[2].isreg
)
10980 reject_bad_reg (inst
.operands
[2].reg
);
10982 inst
.instruction
|= Rd
<< 8;
10983 inst
.instruction
|= Rs
<< 16;
10984 if (!inst
.operands
[2].isreg
)
10986 bfd_boolean narrow
;
10988 if ((inst
.instruction
& 0x00100000) != 0)
10989 narrow
= !in_it_block ();
10991 narrow
= in_it_block ();
10993 if (Rd
> 7 || Rs
> 7)
10996 if (inst
.size_req
== 4 || !unified_syntax
)
10999 if (inst
.reloc
.exp
.X_op
!= O_constant
11000 || inst
.reloc
.exp
.X_add_number
!= 0)
11003 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11004 relaxation, but it doesn't seem worth the hassle. */
11007 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11008 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
11009 inst
.instruction
|= Rs
<< 3;
11010 inst
.instruction
|= Rd
;
11014 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11015 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11019 encode_thumb32_shifted_operand (2);
11025 set_it_insn_type (OUTSIDE_IT_INSN
);
11026 if (inst
.operands
[0].imm
)
11027 inst
.instruction
|= 0x8;
11033 if (!inst
.operands
[1].present
)
11034 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
11036 if (unified_syntax
)
11038 bfd_boolean narrow
;
11041 switch (inst
.instruction
)
11044 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
11046 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
11048 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
11050 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
11054 if (THUMB_SETS_FLAGS (inst
.instruction
))
11055 narrow
= !in_it_block ();
11057 narrow
= in_it_block ();
11058 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11060 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
11062 if (inst
.operands
[2].isreg
11063 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
11064 || inst
.operands
[2].reg
> 7))
11066 if (inst
.size_req
== 4)
11069 reject_bad_reg (inst
.operands
[0].reg
);
11070 reject_bad_reg (inst
.operands
[1].reg
);
11074 if (inst
.operands
[2].isreg
)
11076 reject_bad_reg (inst
.operands
[2].reg
);
11077 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11078 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11079 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11080 inst
.instruction
|= inst
.operands
[2].reg
;
11084 inst
.operands
[1].shifted
= 1;
11085 inst
.operands
[1].shift_kind
= shift_kind
;
11086 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
11087 ? T_MNEM_movs
: T_MNEM_mov
);
11088 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11089 encode_thumb32_shifted_operand (1);
11090 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11091 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11096 if (inst
.operands
[2].isreg
)
11098 switch (shift_kind
)
11100 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11101 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11102 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11103 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11107 inst
.instruction
|= inst
.operands
[0].reg
;
11108 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11112 switch (shift_kind
)
11114 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11115 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11116 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11119 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11120 inst
.instruction
|= inst
.operands
[0].reg
;
11121 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11127 constraint (inst
.operands
[0].reg
> 7
11128 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11129 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11131 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11133 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11134 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11135 _("source1 and dest must be same register"));
11137 switch (inst
.instruction
)
11139 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11140 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11141 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11142 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11146 inst
.instruction
|= inst
.operands
[0].reg
;
11147 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11151 switch (inst
.instruction
)
11153 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11154 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11155 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11156 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11159 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11160 inst
.instruction
|= inst
.operands
[0].reg
;
11161 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11169 unsigned Rd
, Rn
, Rm
;
11171 Rd
= inst
.operands
[0].reg
;
11172 Rn
= inst
.operands
[1].reg
;
11173 Rm
= inst
.operands
[2].reg
;
11175 reject_bad_reg (Rd
);
11176 reject_bad_reg (Rn
);
11177 reject_bad_reg (Rm
);
11179 inst
.instruction
|= Rd
<< 8;
11180 inst
.instruction
|= Rn
<< 16;
11181 inst
.instruction
|= Rm
;
11187 unsigned Rd
, Rn
, Rm
;
11189 Rd
= inst
.operands
[0].reg
;
11190 Rm
= inst
.operands
[1].reg
;
11191 Rn
= inst
.operands
[2].reg
;
11193 reject_bad_reg (Rd
);
11194 reject_bad_reg (Rn
);
11195 reject_bad_reg (Rm
);
11197 inst
.instruction
|= Rd
<< 8;
11198 inst
.instruction
|= Rn
<< 16;
11199 inst
.instruction
|= Rm
;
11205 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11206 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11207 _("expression too complex"));
11208 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11209 inst
.instruction
|= (value
& 0xf000) >> 12;
11210 inst
.instruction
|= (value
& 0x0ff0);
11211 inst
.instruction
|= (value
& 0x000f) << 16;
11215 do_t_ssat_usat (int bias
)
11219 Rd
= inst
.operands
[0].reg
;
11220 Rn
= inst
.operands
[2].reg
;
11222 reject_bad_reg (Rd
);
11223 reject_bad_reg (Rn
);
11225 inst
.instruction
|= Rd
<< 8;
11226 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
11227 inst
.instruction
|= Rn
<< 16;
11229 if (inst
.operands
[3].present
)
11231 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
11233 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11235 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11236 _("expression too complex"));
11238 if (shift_amount
!= 0)
11240 constraint (shift_amount
> 31,
11241 _("shift expression is too large"));
11243 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
11244 inst
.instruction
|= 0x00200000; /* sh bit. */
11246 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
11247 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11255 do_t_ssat_usat (1);
11263 Rd
= inst
.operands
[0].reg
;
11264 Rn
= inst
.operands
[2].reg
;
11266 reject_bad_reg (Rd
);
11267 reject_bad_reg (Rn
);
11269 inst
.instruction
|= Rd
<< 8;
11270 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11271 inst
.instruction
|= Rn
<< 16;
11277 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11278 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11279 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11280 || inst
.operands
[2].negative
,
11283 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
11285 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11286 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11287 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11288 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11294 if (!inst
.operands
[2].present
)
11295 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11297 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11298 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11299 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
11302 inst
.instruction
|= inst
.operands
[0].reg
;
11303 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11304 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11305 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11311 unsigned Rd
, Rn
, Rm
;
11313 Rd
= inst
.operands
[0].reg
;
11314 Rn
= inst
.operands
[1].reg
;
11315 Rm
= inst
.operands
[2].reg
;
11317 reject_bad_reg (Rd
);
11318 reject_bad_reg (Rn
);
11319 reject_bad_reg (Rm
);
11321 inst
.instruction
|= Rd
<< 8;
11322 inst
.instruction
|= Rn
<< 16;
11323 inst
.instruction
|= Rm
;
11324 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11332 Rd
= inst
.operands
[0].reg
;
11333 Rm
= inst
.operands
[1].reg
;
11335 reject_bad_reg (Rd
);
11336 reject_bad_reg (Rm
);
11338 if (inst
.instruction
<= 0xffff
11339 && inst
.size_req
!= 4
11340 && Rd
<= 7 && Rm
<= 7
11341 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11343 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11344 inst
.instruction
|= Rd
;
11345 inst
.instruction
|= Rm
<< 3;
11347 else if (unified_syntax
)
11349 if (inst
.instruction
<= 0xffff)
11350 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11351 inst
.instruction
|= Rd
<< 8;
11352 inst
.instruction
|= Rm
;
11353 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11357 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11358 _("Thumb encoding does not support rotation"));
11359 constraint (1, BAD_HIREG
);
11366 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11375 half
= (inst
.instruction
& 0x10) != 0;
11376 set_it_insn_type_last ();
11377 constraint (inst
.operands
[0].immisreg
,
11378 _("instruction requires register index"));
11380 Rn
= inst
.operands
[0].reg
;
11381 Rm
= inst
.operands
[0].imm
;
11383 constraint (Rn
== REG_SP
, BAD_SP
);
11384 reject_bad_reg (Rm
);
11386 constraint (!half
&& inst
.operands
[0].shifted
,
11387 _("instruction does not allow shifted index"));
11388 inst
.instruction
|= (Rn
<< 16) | Rm
;
11394 do_t_ssat_usat (0);
11402 Rd
= inst
.operands
[0].reg
;
11403 Rn
= inst
.operands
[2].reg
;
11405 reject_bad_reg (Rd
);
11406 reject_bad_reg (Rn
);
11408 inst
.instruction
|= Rd
<< 8;
11409 inst
.instruction
|= inst
.operands
[1].imm
;
11410 inst
.instruction
|= Rn
<< 16;
11413 /* Neon instruction encoder helpers. */
11415 /* Encodings for the different types for various Neon opcodes. */
11417 /* An "invalid" code for the following tables. */
11420 struct neon_tab_entry
11423 unsigned float_or_poly
;
11424 unsigned scalar_or_imm
;
11427 /* Map overloaded Neon opcodes to their respective encodings. */
11428 #define NEON_ENC_TAB \
11429 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11430 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11431 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11432 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11433 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11434 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11435 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11436 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11437 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11438 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11439 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11440 /* Register variants of the following two instructions are encoded as
11441 vcge / vcgt with the operands reversed. */ \
11442 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11443 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11444 X(vfma, N_INV, 0x0000c10, N_INV), \
11445 X(vfms, N_INV, 0x0200c10, N_INV), \
11446 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11447 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11448 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11449 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11450 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11451 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11452 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11453 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11454 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11455 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11456 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11457 X(vshl, 0x0000400, N_INV, 0x0800510), \
11458 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11459 X(vand, 0x0000110, N_INV, 0x0800030), \
11460 X(vbic, 0x0100110, N_INV, 0x0800030), \
11461 X(veor, 0x1000110, N_INV, N_INV), \
11462 X(vorn, 0x0300110, N_INV, 0x0800010), \
11463 X(vorr, 0x0200110, N_INV, 0x0800010), \
11464 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11465 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11466 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11467 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11468 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11469 X(vst1, 0x0000000, 0x0800000, N_INV), \
11470 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11471 X(vst2, 0x0000100, 0x0800100, N_INV), \
11472 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11473 X(vst3, 0x0000200, 0x0800200, N_INV), \
11474 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11475 X(vst4, 0x0000300, 0x0800300, N_INV), \
11476 X(vmovn, 0x1b20200, N_INV, N_INV), \
11477 X(vtrn, 0x1b20080, N_INV, N_INV), \
11478 X(vqmovn, 0x1b20200, N_INV, N_INV), \
11479 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11480 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
11481 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
11482 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
11483 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
11484 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
11485 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11486 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
11487 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
11488 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
11492 #define X(OPC,I,F,S) N_MNEM_##OPC
11497 static const struct neon_tab_entry neon_enc_tab
[] =
11499 #define X(OPC,I,F,S) { (I), (F), (S) }
11504 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
11505 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11506 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11507 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11508 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11509 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11510 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11511 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11512 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11513 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11514 #define NEON_ENC_SINGLE_(X) \
11515 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
11516 #define NEON_ENC_DOUBLE_(X) \
11517 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
11519 #define NEON_ENCODE(type, inst) \
11522 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
11523 inst.is_neon = 1; \
11527 #define check_neon_suffixes \
11530 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
11532 as_bad (_("invalid neon suffix for non neon instruction")); \
11538 /* Define shapes for instruction operands. The following mnemonic characters
11539 are used in this table:
11541 F - VFP S<n> register
11542 D - Neon D<n> register
11543 Q - Neon Q<n> register
11547 L - D<n> register list
11549 This table is used to generate various data:
11550 - enumerations of the form NS_DDR to be used as arguments to
11552 - a table classifying shapes into single, double, quad, mixed.
11553 - a table used to drive neon_select_shape. */
11555 #define NEON_SHAPE_DEF \
11556 X(3, (D, D, D), DOUBLE), \
11557 X(3, (Q, Q, Q), QUAD), \
11558 X(3, (D, D, I), DOUBLE), \
11559 X(3, (Q, Q, I), QUAD), \
11560 X(3, (D, D, S), DOUBLE), \
11561 X(3, (Q, Q, S), QUAD), \
11562 X(2, (D, D), DOUBLE), \
11563 X(2, (Q, Q), QUAD), \
11564 X(2, (D, S), DOUBLE), \
11565 X(2, (Q, S), QUAD), \
11566 X(2, (D, R), DOUBLE), \
11567 X(2, (Q, R), QUAD), \
11568 X(2, (D, I), DOUBLE), \
11569 X(2, (Q, I), QUAD), \
11570 X(3, (D, L, D), DOUBLE), \
11571 X(2, (D, Q), MIXED), \
11572 X(2, (Q, D), MIXED), \
11573 X(3, (D, Q, I), MIXED), \
11574 X(3, (Q, D, I), MIXED), \
11575 X(3, (Q, D, D), MIXED), \
11576 X(3, (D, Q, Q), MIXED), \
11577 X(3, (Q, Q, D), MIXED), \
11578 X(3, (Q, D, S), MIXED), \
11579 X(3, (D, Q, S), MIXED), \
11580 X(4, (D, D, D, I), DOUBLE), \
11581 X(4, (Q, Q, Q, I), QUAD), \
11582 X(2, (F, F), SINGLE), \
11583 X(3, (F, F, F), SINGLE), \
11584 X(2, (F, I), SINGLE), \
11585 X(2, (F, D), MIXED), \
11586 X(2, (D, F), MIXED), \
11587 X(3, (F, F, I), MIXED), \
11588 X(4, (R, R, F, F), SINGLE), \
11589 X(4, (F, F, R, R), SINGLE), \
11590 X(3, (D, R, R), DOUBLE), \
11591 X(3, (R, R, D), DOUBLE), \
11592 X(2, (S, R), SINGLE), \
11593 X(2, (R, S), SINGLE), \
11594 X(2, (F, R), SINGLE), \
11595 X(2, (R, F), SINGLE)
11597 #define S2(A,B) NS_##A##B
11598 #define S3(A,B,C) NS_##A##B##C
11599 #define S4(A,B,C,D) NS_##A##B##C##D
11601 #define X(N, L, C) S##N L
11614 enum neon_shape_class
11622 #define X(N, L, C) SC_##C
11624 static enum neon_shape_class neon_shape_class
[] =
11642 /* Register widths of above. */
11643 static unsigned neon_shape_el_size
[] =
11654 struct neon_shape_info
11657 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
11660 #define S2(A,B) { SE_##A, SE_##B }
11661 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
11662 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
11664 #define X(N, L, C) { N, S##N L }
11666 static struct neon_shape_info neon_shape_tab
[] =
11676 /* Bit masks used in type checking given instructions.
11677 'N_EQK' means the type must be the same as (or based on in some way) the key
11678 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
11679 set, various other bits can be set as well in order to modify the meaning of
11680 the type constraint. */
11682 enum neon_type_mask
11705 N_KEY
= 0x1000000, /* Key element (main type specifier). */
11706 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
11707 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
11708 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
11709 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
11710 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
11711 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
11712 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
11713 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
11714 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
11716 N_MAX_NONSPECIAL
= N_F64
11719 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
11721 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
11722 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
11723 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
11724 #define N_SUF_32 (N_SU_32 | N_F32)
11725 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
11726 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
11728 /* Pass this as the first type argument to neon_check_type to ignore types
11730 #define N_IGNORE_TYPE (N_KEY | N_EQK)
11732 /* Select a "shape" for the current instruction (describing register types or
11733 sizes) from a list of alternatives. Return NS_NULL if the current instruction
11734 doesn't fit. For non-polymorphic shapes, checking is usually done as a
11735 function of operand parsing, so this function doesn't need to be called.
11736 Shapes should be listed in order of decreasing length. */
11738 static enum neon_shape
11739 neon_select_shape (enum neon_shape shape
, ...)
11742 enum neon_shape first_shape
= shape
;
11744 /* Fix missing optional operands. FIXME: we don't know at this point how
11745 many arguments we should have, so this makes the assumption that we have
11746 > 1. This is true of all current Neon opcodes, I think, but may not be
11747 true in the future. */
11748 if (!inst
.operands
[1].present
)
11749 inst
.operands
[1] = inst
.operands
[0];
11751 va_start (ap
, shape
);
11753 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
11758 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
11760 if (!inst
.operands
[j
].present
)
11766 switch (neon_shape_tab
[shape
].el
[j
])
11769 if (!(inst
.operands
[j
].isreg
11770 && inst
.operands
[j
].isvec
11771 && inst
.operands
[j
].issingle
11772 && !inst
.operands
[j
].isquad
))
11777 if (!(inst
.operands
[j
].isreg
11778 && inst
.operands
[j
].isvec
11779 && !inst
.operands
[j
].isquad
11780 && !inst
.operands
[j
].issingle
))
11785 if (!(inst
.operands
[j
].isreg
11786 && !inst
.operands
[j
].isvec
))
11791 if (!(inst
.operands
[j
].isreg
11792 && inst
.operands
[j
].isvec
11793 && inst
.operands
[j
].isquad
11794 && !inst
.operands
[j
].issingle
))
11799 if (!(!inst
.operands
[j
].isreg
11800 && !inst
.operands
[j
].isscalar
))
11805 if (!(!inst
.operands
[j
].isreg
11806 && inst
.operands
[j
].isscalar
))
11822 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
11823 first_error (_("invalid instruction shape"));
11828 /* True if SHAPE is predominantly a quadword operation (most of the time, this
11829 means the Q bit should be set). */
11832 neon_quad (enum neon_shape shape
)
11834 return neon_shape_class
[shape
] == SC_QUAD
;
11838 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
11841 /* Allow modification to be made to types which are constrained to be
11842 based on the key element, based on bits set alongside N_EQK. */
11843 if ((typebits
& N_EQK
) != 0)
11845 if ((typebits
& N_HLF
) != 0)
11847 else if ((typebits
& N_DBL
) != 0)
11849 if ((typebits
& N_SGN
) != 0)
11850 *g_type
= NT_signed
;
11851 else if ((typebits
& N_UNS
) != 0)
11852 *g_type
= NT_unsigned
;
11853 else if ((typebits
& N_INT
) != 0)
11854 *g_type
= NT_integer
;
11855 else if ((typebits
& N_FLT
) != 0)
11856 *g_type
= NT_float
;
11857 else if ((typebits
& N_SIZ
) != 0)
11858 *g_type
= NT_untyped
;
11862 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
11863 operand type, i.e. the single type specified in a Neon instruction when it
11864 is the only one given. */
11866 static struct neon_type_el
11867 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
11869 struct neon_type_el dest
= *key
;
11871 gas_assert ((thisarg
& N_EQK
) != 0);
11873 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
11878 /* Convert Neon type and size into compact bitmask representation. */
11880 static enum neon_type_mask
11881 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
11888 case 8: return N_8
;
11889 case 16: return N_16
;
11890 case 32: return N_32
;
11891 case 64: return N_64
;
11899 case 8: return N_I8
;
11900 case 16: return N_I16
;
11901 case 32: return N_I32
;
11902 case 64: return N_I64
;
11910 case 16: return N_F16
;
11911 case 32: return N_F32
;
11912 case 64: return N_F64
;
11920 case 8: return N_P8
;
11921 case 16: return N_P16
;
11929 case 8: return N_S8
;
11930 case 16: return N_S16
;
11931 case 32: return N_S32
;
11932 case 64: return N_S64
;
11940 case 8: return N_U8
;
11941 case 16: return N_U16
;
11942 case 32: return N_U32
;
11943 case 64: return N_U64
;
11954 /* Convert compact Neon bitmask type representation to a type and size. Only
11955 handles the case where a single bit is set in the mask. */
11958 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
11959 enum neon_type_mask mask
)
11961 if ((mask
& N_EQK
) != 0)
11964 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
11966 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
11968 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
11970 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
11975 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
11977 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
11978 *type
= NT_unsigned
;
11979 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
11980 *type
= NT_integer
;
11981 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
11982 *type
= NT_untyped
;
11983 else if ((mask
& (N_P8
| N_P16
)) != 0)
11985 else if ((mask
& (N_F32
| N_F64
)) != 0)
11993 /* Modify a bitmask of allowed types. This is only needed for type
11997 modify_types_allowed (unsigned allowed
, unsigned mods
)
12000 enum neon_el_type type
;
12006 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
12008 if (el_type_of_type_chk (&type
, &size
,
12009 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
12011 neon_modify_type_size (mods
, &type
, &size
);
12012 destmask
|= type_chk_of_el_type (type
, size
);
12019 /* Check type and return type classification.
12020 The manual states (paraphrase): If one datatype is given, it indicates the
12022 - the second operand, if there is one
12023 - the operand, if there is no second operand
12024 - the result, if there are no operands.
12025 This isn't quite good enough though, so we use a concept of a "key" datatype
12026 which is set on a per-instruction basis, which is the one which matters when
12027 only one data type is written.
12028 Note: this function has side-effects (e.g. filling in missing operands). All
12029 Neon instructions should call it before performing bit encoding. */
12031 static struct neon_type_el
12032 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
12035 unsigned i
, pass
, key_el
= 0;
12036 unsigned types
[NEON_MAX_TYPE_ELS
];
12037 enum neon_el_type k_type
= NT_invtype
;
12038 unsigned k_size
= -1u;
12039 struct neon_type_el badtype
= {NT_invtype
, -1};
12040 unsigned key_allowed
= 0;
12042 /* Optional registers in Neon instructions are always (not) in operand 1.
12043 Fill in the missing operand here, if it was omitted. */
12044 if (els
> 1 && !inst
.operands
[1].present
)
12045 inst
.operands
[1] = inst
.operands
[0];
12047 /* Suck up all the varargs. */
12049 for (i
= 0; i
< els
; i
++)
12051 unsigned thisarg
= va_arg (ap
, unsigned);
12052 if (thisarg
== N_IGNORE_TYPE
)
12057 types
[i
] = thisarg
;
12058 if ((thisarg
& N_KEY
) != 0)
12063 if (inst
.vectype
.elems
> 0)
12064 for (i
= 0; i
< els
; i
++)
12065 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
12067 first_error (_("types specified in both the mnemonic and operands"));
12071 /* Duplicate inst.vectype elements here as necessary.
12072 FIXME: No idea if this is exactly the same as the ARM assembler,
12073 particularly when an insn takes one register and one non-register
12075 if (inst
.vectype
.elems
== 1 && els
> 1)
12078 inst
.vectype
.elems
= els
;
12079 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
12080 for (j
= 0; j
< els
; j
++)
12082 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12085 else if (inst
.vectype
.elems
== 0 && els
> 0)
12088 /* No types were given after the mnemonic, so look for types specified
12089 after each operand. We allow some flexibility here; as long as the
12090 "key" operand has a type, we can infer the others. */
12091 for (j
= 0; j
< els
; j
++)
12092 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
12093 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
12095 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
12097 for (j
= 0; j
< els
; j
++)
12098 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
12099 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12104 first_error (_("operand types can't be inferred"));
12108 else if (inst
.vectype
.elems
!= els
)
12110 first_error (_("type specifier has the wrong number of parts"));
12114 for (pass
= 0; pass
< 2; pass
++)
12116 for (i
= 0; i
< els
; i
++)
12118 unsigned thisarg
= types
[i
];
12119 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
12120 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
12121 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
12122 unsigned g_size
= inst
.vectype
.el
[i
].size
;
12124 /* Decay more-specific signed & unsigned types to sign-insensitive
12125 integer types if sign-specific variants are unavailable. */
12126 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
12127 && (types_allowed
& N_SU_ALL
) == 0)
12128 g_type
= NT_integer
;
12130 /* If only untyped args are allowed, decay any more specific types to
12131 them. Some instructions only care about signs for some element
12132 sizes, so handle that properly. */
12133 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
12134 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
12135 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
12136 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
12137 g_type
= NT_untyped
;
12141 if ((thisarg
& N_KEY
) != 0)
12145 key_allowed
= thisarg
& ~N_KEY
;
12150 if ((thisarg
& N_VFP
) != 0)
12152 enum neon_shape_el regshape
;
12153 unsigned regwidth
, match
;
12155 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12158 first_error (_("invalid instruction shape"));
12161 regshape
= neon_shape_tab
[ns
].el
[i
];
12162 regwidth
= neon_shape_el_size
[regshape
];
12164 /* In VFP mode, operands must match register widths. If we
12165 have a key operand, use its width, else use the width of
12166 the current operand. */
12172 if (regwidth
!= match
)
12174 first_error (_("operand size must match register width"));
12179 if ((thisarg
& N_EQK
) == 0)
12181 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
12183 if ((given_type
& types_allowed
) == 0)
12185 first_error (_("bad type in Neon instruction"));
12191 enum neon_el_type mod_k_type
= k_type
;
12192 unsigned mod_k_size
= k_size
;
12193 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
12194 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
12196 first_error (_("inconsistent types in Neon instruction"));
12204 return inst
.vectype
.el
[key_el
];
12207 /* Neon-style VFP instruction forwarding. */
12209 /* Thumb VFP instructions have 0xE in the condition field. */
12212 do_vfp_cond_or_thumb (void)
12217 inst
.instruction
|= 0xe0000000;
12219 inst
.instruction
|= inst
.cond
<< 28;
12222 /* Look up and encode a simple mnemonic, for use as a helper function for the
12223 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12224 etc. It is assumed that operand parsing has already been done, and that the
12225 operands are in the form expected by the given opcode (this isn't necessarily
12226 the same as the form in which they were parsed, hence some massaging must
12227 take place before this function is called).
12228 Checks current arch version against that in the looked-up opcode. */
12231 do_vfp_nsyn_opcode (const char *opname
)
12233 const struct asm_opcode
*opcode
;
12235 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
12240 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
12241 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
12248 inst
.instruction
= opcode
->tvalue
;
12249 opcode
->tencode ();
12253 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
12254 opcode
->aencode ();
12259 do_vfp_nsyn_add_sub (enum neon_shape rs
)
12261 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
12266 do_vfp_nsyn_opcode ("fadds");
12268 do_vfp_nsyn_opcode ("fsubs");
12273 do_vfp_nsyn_opcode ("faddd");
12275 do_vfp_nsyn_opcode ("fsubd");
12279 /* Check operand types to see if this is a VFP instruction, and if so call
12283 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
12285 enum neon_shape rs
;
12286 struct neon_type_el et
;
12291 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12292 et
= neon_check_type (2, rs
,
12293 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12297 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12298 et
= neon_check_type (3, rs
,
12299 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12306 if (et
.type
!= NT_invtype
)
12317 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12319 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12324 do_vfp_nsyn_opcode ("fmacs");
12326 do_vfp_nsyn_opcode ("fnmacs");
12331 do_vfp_nsyn_opcode ("fmacd");
12333 do_vfp_nsyn_opcode ("fnmacd");
12338 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
12340 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
12345 do_vfp_nsyn_opcode ("ffmas");
12347 do_vfp_nsyn_opcode ("ffnmas");
12352 do_vfp_nsyn_opcode ("ffmad");
12354 do_vfp_nsyn_opcode ("ffnmad");
12359 do_vfp_nsyn_mul (enum neon_shape rs
)
12362 do_vfp_nsyn_opcode ("fmuls");
12364 do_vfp_nsyn_opcode ("fmuld");
12368 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12370 int is_neg
= (inst
.instruction
& 0x80) != 0;
12371 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12376 do_vfp_nsyn_opcode ("fnegs");
12378 do_vfp_nsyn_opcode ("fabss");
12383 do_vfp_nsyn_opcode ("fnegd");
12385 do_vfp_nsyn_opcode ("fabsd");
12389 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12390 insns belong to Neon, and are handled elsewhere. */
12393 do_vfp_nsyn_ldm_stm (int is_dbmode
)
12395 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
12399 do_vfp_nsyn_opcode ("fldmdbs");
12401 do_vfp_nsyn_opcode ("fldmias");
12406 do_vfp_nsyn_opcode ("fstmdbs");
12408 do_vfp_nsyn_opcode ("fstmias");
12413 do_vfp_nsyn_sqrt (void)
12415 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12416 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12419 do_vfp_nsyn_opcode ("fsqrts");
12421 do_vfp_nsyn_opcode ("fsqrtd");
12425 do_vfp_nsyn_div (void)
12427 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12428 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12429 N_F32
| N_F64
| N_KEY
| N_VFP
);
12432 do_vfp_nsyn_opcode ("fdivs");
12434 do_vfp_nsyn_opcode ("fdivd");
12438 do_vfp_nsyn_nmul (void)
12440 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12441 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12442 N_F32
| N_F64
| N_KEY
| N_VFP
);
12446 NEON_ENCODE (SINGLE
, inst
);
12447 do_vfp_sp_dyadic ();
12451 NEON_ENCODE (DOUBLE
, inst
);
12452 do_vfp_dp_rd_rn_rm ();
12454 do_vfp_cond_or_thumb ();
12458 do_vfp_nsyn_cmp (void)
12460 if (inst
.operands
[1].isreg
)
12462 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12463 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12467 NEON_ENCODE (SINGLE
, inst
);
12468 do_vfp_sp_monadic ();
12472 NEON_ENCODE (DOUBLE
, inst
);
12473 do_vfp_dp_rd_rm ();
12478 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
12479 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
12481 switch (inst
.instruction
& 0x0fffffff)
12484 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
12487 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
12495 NEON_ENCODE (SINGLE
, inst
);
12496 do_vfp_sp_compare_z ();
12500 NEON_ENCODE (DOUBLE
, inst
);
12504 do_vfp_cond_or_thumb ();
12508 nsyn_insert_sp (void)
12510 inst
.operands
[1] = inst
.operands
[0];
12511 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
12512 inst
.operands
[0].reg
= REG_SP
;
12513 inst
.operands
[0].isreg
= 1;
12514 inst
.operands
[0].writeback
= 1;
12515 inst
.operands
[0].present
= 1;
12519 do_vfp_nsyn_push (void)
12522 if (inst
.operands
[1].issingle
)
12523 do_vfp_nsyn_opcode ("fstmdbs");
12525 do_vfp_nsyn_opcode ("fstmdbd");
12529 do_vfp_nsyn_pop (void)
12532 if (inst
.operands
[1].issingle
)
12533 do_vfp_nsyn_opcode ("fldmias");
12535 do_vfp_nsyn_opcode ("fldmiad");
12538 /* Fix up Neon data-processing instructions, ORing in the correct bits for
12539 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
12542 neon_dp_fixup (struct arm_it
* insn
)
12544 unsigned int i
= insn
->instruction
;
12549 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
12560 insn
->instruction
= i
;
12563 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
12567 neon_logbits (unsigned x
)
12569 return ffs (x
) - 4;
12572 #define LOW4(R) ((R) & 0xf)
12573 #define HI1(R) (((R) >> 4) & 1)
12575 /* Encode insns with bit pattern:
12577 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12578 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
12580 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
12581 different meaning for some instruction. */
12584 neon_three_same (int isquad
, int ubit
, int size
)
12586 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12587 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12588 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12589 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12590 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12591 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12592 inst
.instruction
|= (isquad
!= 0) << 6;
12593 inst
.instruction
|= (ubit
!= 0) << 24;
12595 inst
.instruction
|= neon_logbits (size
) << 20;
12597 neon_dp_fixup (&inst
);
12600 /* Encode instructions of the form:
12602 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
12603 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
12605 Don't write size if SIZE == -1. */
12608 neon_two_same (int qbit
, int ubit
, int size
)
12610 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12611 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12612 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12613 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12614 inst
.instruction
|= (qbit
!= 0) << 6;
12615 inst
.instruction
|= (ubit
!= 0) << 24;
12618 inst
.instruction
|= neon_logbits (size
) << 18;
12620 neon_dp_fixup (&inst
);
12623 /* Neon instruction encoders, in approximate order of appearance. */
12626 do_neon_dyadic_i_su (void)
12628 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12629 struct neon_type_el et
= neon_check_type (3, rs
,
12630 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
12631 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12635 do_neon_dyadic_i64_su (void)
12637 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12638 struct neon_type_el et
= neon_check_type (3, rs
,
12639 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12640 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12644 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
12647 unsigned size
= et
.size
>> 3;
12648 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12649 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12650 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12651 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12652 inst
.instruction
|= (isquad
!= 0) << 6;
12653 inst
.instruction
|= immbits
<< 16;
12654 inst
.instruction
|= (size
>> 3) << 7;
12655 inst
.instruction
|= (size
& 0x7) << 19;
12657 inst
.instruction
|= (uval
!= 0) << 24;
12659 neon_dp_fixup (&inst
);
12663 do_neon_shl_imm (void)
12665 if (!inst
.operands
[2].isreg
)
12667 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12668 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
12669 NEON_ENCODE (IMMED
, inst
);
12670 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
12674 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12675 struct neon_type_el et
= neon_check_type (3, rs
,
12676 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12679 /* VSHL/VQSHL 3-register variants have syntax such as:
12681 whereas other 3-register operations encoded by neon_three_same have
12684 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
12686 tmp
= inst
.operands
[2].reg
;
12687 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12688 inst
.operands
[1].reg
= tmp
;
12689 NEON_ENCODE (INTEGER
, inst
);
12690 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12695 do_neon_qshl_imm (void)
12697 if (!inst
.operands
[2].isreg
)
12699 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12700 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12702 NEON_ENCODE (IMMED
, inst
);
12703 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12704 inst
.operands
[2].imm
);
12708 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12709 struct neon_type_el et
= neon_check_type (3, rs
,
12710 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12713 /* See note in do_neon_shl_imm. */
12714 tmp
= inst
.operands
[2].reg
;
12715 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12716 inst
.operands
[1].reg
= tmp
;
12717 NEON_ENCODE (INTEGER
, inst
);
12718 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12723 do_neon_rshl (void)
12725 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12726 struct neon_type_el et
= neon_check_type (3, rs
,
12727 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12730 tmp
= inst
.operands
[2].reg
;
12731 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12732 inst
.operands
[1].reg
= tmp
;
12733 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12737 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
12739 /* Handle .I8 pseudo-instructions. */
12742 /* Unfortunately, this will make everything apart from zero out-of-range.
12743 FIXME is this the intended semantics? There doesn't seem much point in
12744 accepting .I8 if so. */
12745 immediate
|= immediate
<< 8;
12751 if (immediate
== (immediate
& 0x000000ff))
12753 *immbits
= immediate
;
12756 else if (immediate
== (immediate
& 0x0000ff00))
12758 *immbits
= immediate
>> 8;
12761 else if (immediate
== (immediate
& 0x00ff0000))
12763 *immbits
= immediate
>> 16;
12766 else if (immediate
== (immediate
& 0xff000000))
12768 *immbits
= immediate
>> 24;
12771 if ((immediate
& 0xffff) != (immediate
>> 16))
12772 goto bad_immediate
;
12773 immediate
&= 0xffff;
12776 if (immediate
== (immediate
& 0x000000ff))
12778 *immbits
= immediate
;
12781 else if (immediate
== (immediate
& 0x0000ff00))
12783 *immbits
= immediate
>> 8;
12788 first_error (_("immediate value out of range"));
12792 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
12796 neon_bits_same_in_bytes (unsigned imm
)
12798 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
12799 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
12800 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
12801 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
12804 /* For immediate of above form, return 0bABCD. */
12807 neon_squash_bits (unsigned imm
)
12809 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
12810 | ((imm
& 0x01000000) >> 21);
12813 /* Compress quarter-float representation to 0b...000 abcdefgh. */
12816 neon_qfloat_bits (unsigned imm
)
12818 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
12821 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
12822 the instruction. *OP is passed as the initial value of the op field, and
12823 may be set to a different value depending on the constant (i.e.
12824 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
12825 MVN). If the immediate looks like a repeated pattern then also
12826 try smaller element sizes. */
12829 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
12830 unsigned *immbits
, int *op
, int size
,
12831 enum neon_el_type type
)
12833 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
12835 if (type
== NT_float
&& !float_p
)
12838 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
12840 if (size
!= 32 || *op
== 1)
12842 *immbits
= neon_qfloat_bits (immlo
);
12848 if (neon_bits_same_in_bytes (immhi
)
12849 && neon_bits_same_in_bytes (immlo
))
12853 *immbits
= (neon_squash_bits (immhi
) << 4)
12854 | neon_squash_bits (immlo
);
12859 if (immhi
!= immlo
)
12865 if (immlo
== (immlo
& 0x000000ff))
12870 else if (immlo
== (immlo
& 0x0000ff00))
12872 *immbits
= immlo
>> 8;
12875 else if (immlo
== (immlo
& 0x00ff0000))
12877 *immbits
= immlo
>> 16;
12880 else if (immlo
== (immlo
& 0xff000000))
12882 *immbits
= immlo
>> 24;
12885 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
12887 *immbits
= (immlo
>> 8) & 0xff;
12890 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
12892 *immbits
= (immlo
>> 16) & 0xff;
12896 if ((immlo
& 0xffff) != (immlo
>> 16))
12903 if (immlo
== (immlo
& 0x000000ff))
12908 else if (immlo
== (immlo
& 0x0000ff00))
12910 *immbits
= immlo
>> 8;
12914 if ((immlo
& 0xff) != (immlo
>> 8))
12919 if (immlo
== (immlo
& 0x000000ff))
12921 /* Don't allow MVN with 8-bit immediate. */
12931 /* Write immediate bits [7:0] to the following locations:
12933 |28/24|23 19|18 16|15 4|3 0|
12934 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
12936 This function is used by VMOV/VMVN/VORR/VBIC. */
12939 neon_write_immbits (unsigned immbits
)
12941 inst
.instruction
|= immbits
& 0xf;
12942 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
12943 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
12946 /* Invert low-order SIZE bits of XHI:XLO. */
12949 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
12951 unsigned immlo
= xlo
? *xlo
: 0;
12952 unsigned immhi
= xhi
? *xhi
: 0;
12957 immlo
= (~immlo
) & 0xff;
12961 immlo
= (~immlo
) & 0xffff;
12965 immhi
= (~immhi
) & 0xffffffff;
12966 /* fall through. */
12969 immlo
= (~immlo
) & 0xffffffff;
12984 do_neon_logic (void)
12986 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
12988 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12989 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12990 /* U bit and size field were set as part of the bitmask. */
12991 NEON_ENCODE (INTEGER
, inst
);
12992 neon_three_same (neon_quad (rs
), 0, -1);
12996 const int three_ops_form
= (inst
.operands
[2].present
12997 && !inst
.operands
[2].isreg
);
12998 const int immoperand
= (three_ops_form
? 2 : 1);
12999 enum neon_shape rs
= (three_ops_form
13000 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
13001 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
13002 struct neon_type_el et
= neon_check_type (2, rs
,
13003 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13004 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
13008 if (et
.type
== NT_invtype
)
13011 if (three_ops_form
)
13012 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13013 _("first and second operands shall be the same register"));
13015 NEON_ENCODE (IMMED
, inst
);
13017 immbits
= inst
.operands
[immoperand
].imm
;
13020 /* .i64 is a pseudo-op, so the immediate must be a repeating
13022 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
13023 inst
.operands
[immoperand
].reg
: 0))
13025 /* Set immbits to an invalid constant. */
13026 immbits
= 0xdeadbeef;
13033 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13037 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13041 /* Pseudo-instruction for VBIC. */
13042 neon_invert_size (&immbits
, 0, et
.size
);
13043 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13047 /* Pseudo-instruction for VORR. */
13048 neon_invert_size (&immbits
, 0, et
.size
);
13049 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13059 inst
.instruction
|= neon_quad (rs
) << 6;
13060 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13061 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13062 inst
.instruction
|= cmode
<< 8;
13063 neon_write_immbits (immbits
);
13065 neon_dp_fixup (&inst
);
13070 do_neon_bitfield (void)
13072 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13073 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13074 neon_three_same (neon_quad (rs
), 0, -1);
13078 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
13081 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13082 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
13084 if (et
.type
== NT_float
)
13086 NEON_ENCODE (FLOAT
, inst
);
13087 neon_three_same (neon_quad (rs
), 0, -1);
13091 NEON_ENCODE (INTEGER
, inst
);
13092 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
13097 do_neon_dyadic_if_su (void)
13099 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13103 do_neon_dyadic_if_su_d (void)
13105 /* This version only allow D registers, but that constraint is enforced during
13106 operand parsing so we don't need to do anything extra here. */
13107 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13111 do_neon_dyadic_if_i_d (void)
13113 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13114 affected if we specify unsigned args. */
13115 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13118 enum vfp_or_neon_is_neon_bits
13121 NEON_CHECK_ARCH
= 2
13124 /* Call this function if an instruction which may have belonged to the VFP or
13125 Neon instruction sets, but turned out to be a Neon instruction (due to the
13126 operand types involved, etc.). We have to check and/or fix-up a couple of
13129 - Make sure the user hasn't attempted to make a Neon instruction
13131 - Alter the value in the condition code field if necessary.
13132 - Make sure that the arch supports Neon instructions.
13134 Which of these operations take place depends on bits from enum
13135 vfp_or_neon_is_neon_bits.
13137 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13138 current instruction's condition is COND_ALWAYS, the condition field is
13139 changed to inst.uncond_value. This is necessary because instructions shared
13140 between VFP and Neon may be conditional for the VFP variants only, and the
13141 unconditional Neon version must have, e.g., 0xF in the condition field. */
13144 vfp_or_neon_is_neon (unsigned check
)
13146 /* Conditions are always legal in Thumb mode (IT blocks). */
13147 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
13149 if (inst
.cond
!= COND_ALWAYS
)
13151 first_error (_(BAD_COND
));
13154 if (inst
.uncond_value
!= -1)
13155 inst
.instruction
|= inst
.uncond_value
<< 28;
13158 if ((check
& NEON_CHECK_ARCH
)
13159 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
13161 first_error (_(BAD_FPU
));
13169 do_neon_addsub_if_i (void)
13171 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
13174 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13177 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13178 affected if we specify unsigned args. */
13179 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
13182 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13184 V<op> A,B (A is operand 0, B is operand 2)
13189 so handle that case specially. */
13192 neon_exchange_operands (void)
13194 void *scratch
= alloca (sizeof (inst
.operands
[0]));
13195 if (inst
.operands
[1].present
)
13197 /* Swap operands[1] and operands[2]. */
13198 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
13199 inst
.operands
[1] = inst
.operands
[2];
13200 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
13204 inst
.operands
[1] = inst
.operands
[2];
13205 inst
.operands
[2] = inst
.operands
[0];
13210 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
13212 if (inst
.operands
[2].isreg
)
13215 neon_exchange_operands ();
13216 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
13220 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13221 struct neon_type_el et
= neon_check_type (2, rs
,
13222 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
13224 NEON_ENCODE (IMMED
, inst
);
13225 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13226 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13227 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13228 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13229 inst
.instruction
|= neon_quad (rs
) << 6;
13230 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13231 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13233 neon_dp_fixup (&inst
);
13240 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
13244 do_neon_cmp_inv (void)
13246 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
13252 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
13255 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13256 scalars, which are encoded in 5 bits, M : Rm.
13257 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13258 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13262 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
13264 unsigned regno
= NEON_SCALAR_REG (scalar
);
13265 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
13270 if (regno
> 7 || elno
> 3)
13272 return regno
| (elno
<< 3);
13275 if (regno
> 15 || elno
> 1)
13277 return regno
| (elno
<< 4);
13281 first_error (_("scalar out of range for multiply instruction"));
13287 /* Encode multiply / multiply-accumulate scalar instructions. */
13290 neon_mul_mac (struct neon_type_el et
, int ubit
)
13294 /* Give a more helpful error message if we have an invalid type. */
13295 if (et
.type
== NT_invtype
)
13298 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
13299 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13300 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13301 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13302 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13303 inst
.instruction
|= LOW4 (scalar
);
13304 inst
.instruction
|= HI1 (scalar
) << 5;
13305 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13306 inst
.instruction
|= neon_logbits (et
.size
) << 20;
13307 inst
.instruction
|= (ubit
!= 0) << 24;
13309 neon_dp_fixup (&inst
);
13313 do_neon_mac_maybe_scalar (void)
13315 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
13318 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13321 if (inst
.operands
[2].isscalar
)
13323 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13324 struct neon_type_el et
= neon_check_type (3, rs
,
13325 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13326 NEON_ENCODE (SCALAR
, inst
);
13327 neon_mul_mac (et
, neon_quad (rs
));
13331 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13332 affected if we specify unsigned args. */
13333 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13338 do_neon_fmac (void)
13340 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
13343 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13346 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13352 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13353 struct neon_type_el et
= neon_check_type (3, rs
,
13354 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13355 neon_three_same (neon_quad (rs
), 0, et
.size
);
13358 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13359 same types as the MAC equivalents. The polynomial type for this instruction
13360 is encoded the same as the integer type. */
13365 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13368 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13371 if (inst
.operands
[2].isscalar
)
13372 do_neon_mac_maybe_scalar ();
13374 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13378 do_neon_qdmulh (void)
13380 if (inst
.operands
[2].isscalar
)
13382 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13383 struct neon_type_el et
= neon_check_type (3, rs
,
13384 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13385 NEON_ENCODE (SCALAR
, inst
);
13386 neon_mul_mac (et
, neon_quad (rs
));
13390 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13391 struct neon_type_el et
= neon_check_type (3, rs
,
13392 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13393 NEON_ENCODE (INTEGER
, inst
);
13394 /* The U bit (rounding) comes from bit mask. */
13395 neon_three_same (neon_quad (rs
), 0, et
.size
);
13400 do_neon_fcmp_absolute (void)
13402 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13403 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13404 /* Size field comes from bit mask. */
13405 neon_three_same (neon_quad (rs
), 1, -1);
13409 do_neon_fcmp_absolute_inv (void)
13411 neon_exchange_operands ();
13412 do_neon_fcmp_absolute ();
13416 do_neon_step (void)
13418 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13419 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13420 neon_three_same (neon_quad (rs
), 0, -1);
13424 do_neon_abs_neg (void)
13426 enum neon_shape rs
;
13427 struct neon_type_el et
;
13429 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
13432 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13435 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13436 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
13438 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13439 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13440 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13441 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13442 inst
.instruction
|= neon_quad (rs
) << 6;
13443 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13444 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13446 neon_dp_fixup (&inst
);
13452 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13453 struct neon_type_el et
= neon_check_type (2, rs
,
13454 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13455 int imm
= inst
.operands
[2].imm
;
13456 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13457 _("immediate out of range for insert"));
13458 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13464 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13465 struct neon_type_el et
= neon_check_type (2, rs
,
13466 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13467 int imm
= inst
.operands
[2].imm
;
13468 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13469 _("immediate out of range for insert"));
13470 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
13474 do_neon_qshlu_imm (void)
13476 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13477 struct neon_type_el et
= neon_check_type (2, rs
,
13478 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
13479 int imm
= inst
.operands
[2].imm
;
13480 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13481 _("immediate out of range for shift"));
13482 /* Only encodes the 'U present' variant of the instruction.
13483 In this case, signed types have OP (bit 8) set to 0.
13484 Unsigned types have OP set to 1. */
13485 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
13486 /* The rest of the bits are the same as other immediate shifts. */
13487 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13491 do_neon_qmovn (void)
13493 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13494 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13495 /* Saturating move where operands can be signed or unsigned, and the
13496 destination has the same signedness. */
13497 NEON_ENCODE (INTEGER
, inst
);
13498 if (et
.type
== NT_unsigned
)
13499 inst
.instruction
|= 0xc0;
13501 inst
.instruction
|= 0x80;
13502 neon_two_same (0, 1, et
.size
/ 2);
13506 do_neon_qmovun (void)
13508 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13509 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13510 /* Saturating move with unsigned results. Operands must be signed. */
13511 NEON_ENCODE (INTEGER
, inst
);
13512 neon_two_same (0, 1, et
.size
/ 2);
13516 do_neon_rshift_sat_narrow (void)
13518 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13519 or unsigned. If operands are unsigned, results must also be unsigned. */
13520 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13521 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13522 int imm
= inst
.operands
[2].imm
;
13523 /* This gets the bounds check, size encoding and immediate bits calculation
13527 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
13528 VQMOVN.I<size> <Dd>, <Qm>. */
13531 inst
.operands
[2].present
= 0;
13532 inst
.instruction
= N_MNEM_vqmovn
;
13537 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13538 _("immediate out of range"));
13539 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
13543 do_neon_rshift_sat_narrow_u (void)
13545 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13546 or unsigned. If operands are unsigned, results must also be unsigned. */
13547 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13548 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13549 int imm
= inst
.operands
[2].imm
;
13550 /* This gets the bounds check, size encoding and immediate bits calculation
13554 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
13555 VQMOVUN.I<size> <Dd>, <Qm>. */
13558 inst
.operands
[2].present
= 0;
13559 inst
.instruction
= N_MNEM_vqmovun
;
13564 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13565 _("immediate out of range"));
13566 /* FIXME: The manual is kind of unclear about what value U should have in
13567 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
13569 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
13573 do_neon_movn (void)
13575 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13576 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13577 NEON_ENCODE (INTEGER
, inst
);
13578 neon_two_same (0, 1, et
.size
/ 2);
13582 do_neon_rshift_narrow (void)
13584 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13585 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13586 int imm
= inst
.operands
[2].imm
;
13587 /* This gets the bounds check, size encoding and immediate bits calculation
13591 /* If immediate is zero then we are a pseudo-instruction for
13592 VMOVN.I<size> <Dd>, <Qm> */
13595 inst
.operands
[2].present
= 0;
13596 inst
.instruction
= N_MNEM_vmovn
;
13601 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13602 _("immediate out of range for narrowing operation"));
13603 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
13607 do_neon_shll (void)
13609 /* FIXME: Type checking when lengthening. */
13610 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
13611 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
13612 unsigned imm
= inst
.operands
[2].imm
;
13614 if (imm
== et
.size
)
13616 /* Maximum shift variant. */
13617 NEON_ENCODE (INTEGER
, inst
);
13618 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13619 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13620 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13621 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13622 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13624 neon_dp_fixup (&inst
);
13628 /* A more-specific type check for non-max versions. */
13629 et
= neon_check_type (2, NS_QDI
,
13630 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13631 NEON_ENCODE (IMMED
, inst
);
13632 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
13636 /* Check the various types for the VCVT instruction, and return which version
13637 the current instruction is. */
13640 neon_cvt_flavour (enum neon_shape rs
)
13642 #define CVT_VAR(C,X,Y) \
13643 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
13644 if (et.type != NT_invtype) \
13646 inst.error = NULL; \
13649 struct neon_type_el et
;
13650 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
13651 || rs
== NS_FF
) ? N_VFP
: 0;
13652 /* The instruction versions which take an immediate take one register
13653 argument, which is extended to the width of the full register. Thus the
13654 "source" and "destination" registers must have the same width. Hack that
13655 here by making the size equal to the key (wider, in this case) operand. */
13656 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
13658 CVT_VAR (0, N_S32
, N_F32
);
13659 CVT_VAR (1, N_U32
, N_F32
);
13660 CVT_VAR (2, N_F32
, N_S32
);
13661 CVT_VAR (3, N_F32
, N_U32
);
13662 /* Half-precision conversions. */
13663 CVT_VAR (4, N_F32
, N_F16
);
13664 CVT_VAR (5, N_F16
, N_F32
);
13668 /* VFP instructions. */
13669 CVT_VAR (6, N_F32
, N_F64
);
13670 CVT_VAR (7, N_F64
, N_F32
);
13671 CVT_VAR (8, N_S32
, N_F64
| key
);
13672 CVT_VAR (9, N_U32
, N_F64
| key
);
13673 CVT_VAR (10, N_F64
| key
, N_S32
);
13674 CVT_VAR (11, N_F64
| key
, N_U32
);
13675 /* VFP instructions with bitshift. */
13676 CVT_VAR (12, N_F32
| key
, N_S16
);
13677 CVT_VAR (13, N_F32
| key
, N_U16
);
13678 CVT_VAR (14, N_F64
| key
, N_S16
);
13679 CVT_VAR (15, N_F64
| key
, N_U16
);
13680 CVT_VAR (16, N_S16
, N_F32
| key
);
13681 CVT_VAR (17, N_U16
, N_F32
| key
);
13682 CVT_VAR (18, N_S16
, N_F64
| key
);
13683 CVT_VAR (19, N_U16
, N_F64
| key
);
13689 /* Neon-syntax VFP conversions. */
13692 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
13694 const char *opname
= 0;
13696 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
13698 /* Conversions with immediate bitshift. */
13699 const char *enc
[] =
13723 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13725 opname
= enc
[flavour
];
13726 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13727 _("operands 0 and 1 must be the same register"));
13728 inst
.operands
[1] = inst
.operands
[2];
13729 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
13734 /* Conversions without bitshift. */
13735 const char *enc
[] =
13751 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13752 opname
= enc
[flavour
];
13756 do_vfp_nsyn_opcode (opname
);
13760 do_vfp_nsyn_cvtz (void)
13762 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
13763 int flavour
= neon_cvt_flavour (rs
);
13764 const char *enc
[] =
13778 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
13779 do_vfp_nsyn_opcode (enc
[flavour
]);
13783 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED
)
13785 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
13786 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
13787 int flavour
= neon_cvt_flavour (rs
);
13789 /* PR11109: Handle round-to-zero for VCVT conversions. */
13791 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
13792 && (flavour
== 0 || flavour
== 1 || flavour
== 8 || flavour
== 9)
13793 && (rs
== NS_FD
|| rs
== NS_FF
))
13795 do_vfp_nsyn_cvtz ();
13799 /* VFP rather than Neon conversions. */
13802 do_vfp_nsyn_cvt (rs
, flavour
);
13812 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
13814 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13817 /* Fixed-point conversion with #0 immediate is encoded as an
13818 integer conversion. */
13819 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
13821 immbits
= 32 - inst
.operands
[2].imm
;
13822 NEON_ENCODE (IMMED
, inst
);
13824 inst
.instruction
|= enctab
[flavour
];
13825 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13826 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13827 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13828 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13829 inst
.instruction
|= neon_quad (rs
) << 6;
13830 inst
.instruction
|= 1 << 21;
13831 inst
.instruction
|= immbits
<< 16;
13833 neon_dp_fixup (&inst
);
13841 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
13843 NEON_ENCODE (INTEGER
, inst
);
13845 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13849 inst
.instruction
|= enctab
[flavour
];
13851 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13852 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13853 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13854 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13855 inst
.instruction
|= neon_quad (rs
) << 6;
13856 inst
.instruction
|= 2 << 18;
13858 neon_dp_fixup (&inst
);
13862 /* Half-precision conversions for Advanced SIMD -- neon. */
13867 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
13869 as_bad (_("operand size must match register width"));
13874 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
13876 as_bad (_("operand size must match register width"));
13881 inst
.instruction
= 0x3b60600;
13883 inst
.instruction
= 0x3b60700;
13885 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13886 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13887 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13888 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13889 neon_dp_fixup (&inst
);
13893 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
13894 do_vfp_nsyn_cvt (rs
, flavour
);
13899 do_neon_cvtr (void)
13901 do_neon_cvt_1 (FALSE
);
13907 do_neon_cvt_1 (TRUE
);
13911 do_neon_cvtb (void)
13913 inst
.instruction
= 0xeb20a40;
13915 /* The sizes are attached to the mnemonic. */
13916 if (inst
.vectype
.el
[0].type
!= NT_invtype
13917 && inst
.vectype
.el
[0].size
== 16)
13918 inst
.instruction
|= 0x00010000;
13920 /* Programmer's syntax: the sizes are attached to the operands. */
13921 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
13922 && inst
.operands
[0].vectype
.size
== 16)
13923 inst
.instruction
|= 0x00010000;
13925 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
13926 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
13927 do_vfp_cond_or_thumb ();
13932 do_neon_cvtt (void)
13935 inst
.instruction
|= 0x80;
13939 neon_move_immediate (void)
13941 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
13942 struct neon_type_el et
= neon_check_type (2, rs
,
13943 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13944 unsigned immlo
, immhi
= 0, immbits
;
13945 int op
, cmode
, float_p
;
13947 constraint (et
.type
== NT_invtype
,
13948 _("operand size must be specified for immediate VMOV"));
13950 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
13951 op
= (inst
.instruction
& (1 << 5)) != 0;
13953 immlo
= inst
.operands
[1].imm
;
13954 if (inst
.operands
[1].regisimm
)
13955 immhi
= inst
.operands
[1].reg
;
13957 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
13958 _("immediate has bits set outside the operand size"));
13960 float_p
= inst
.operands
[1].immisfloat
;
13962 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
13963 et
.size
, et
.type
)) == FAIL
)
13965 /* Invert relevant bits only. */
13966 neon_invert_size (&immlo
, &immhi
, et
.size
);
13967 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
13968 with one or the other; those cases are caught by
13969 neon_cmode_for_move_imm. */
13971 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
13972 &op
, et
.size
, et
.type
)) == FAIL
)
13974 first_error (_("immediate out of range"));
13979 inst
.instruction
&= ~(1 << 5);
13980 inst
.instruction
|= op
<< 5;
13982 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13983 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13984 inst
.instruction
|= neon_quad (rs
) << 6;
13985 inst
.instruction
|= cmode
<< 8;
13987 neon_write_immbits (immbits
);
13993 if (inst
.operands
[1].isreg
)
13995 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13997 NEON_ENCODE (INTEGER
, inst
);
13998 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13999 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14000 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14001 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14002 inst
.instruction
|= neon_quad (rs
) << 6;
14006 NEON_ENCODE (IMMED
, inst
);
14007 neon_move_immediate ();
14010 neon_dp_fixup (&inst
);
14013 /* Encode instructions of form:
14015 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14016 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14019 neon_mixed_length (struct neon_type_el et
, unsigned size
)
14021 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14022 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14023 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14024 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14025 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14026 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14027 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
14028 inst
.instruction
|= neon_logbits (size
) << 20;
14030 neon_dp_fixup (&inst
);
14034 do_neon_dyadic_long (void)
14036 /* FIXME: Type checking for lengthening op. */
14037 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14038 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14039 neon_mixed_length (et
, et
.size
);
14043 do_neon_abal (void)
14045 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14046 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14047 neon_mixed_length (et
, et
.size
);
14051 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
14053 if (inst
.operands
[2].isscalar
)
14055 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
14056 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
14057 NEON_ENCODE (SCALAR
, inst
);
14058 neon_mul_mac (et
, et
.type
== NT_unsigned
);
14062 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14063 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
14064 NEON_ENCODE (INTEGER
, inst
);
14065 neon_mixed_length (et
, et
.size
);
14070 do_neon_mac_maybe_scalar_long (void)
14072 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
14076 do_neon_dyadic_wide (void)
14078 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
14079 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14080 neon_mixed_length (et
, et
.size
);
14084 do_neon_dyadic_narrow (void)
14086 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14087 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
14088 /* Operand sign is unimportant, and the U bit is part of the opcode,
14089 so force the operand type to integer. */
14090 et
.type
= NT_integer
;
14091 neon_mixed_length (et
, et
.size
/ 2);
14095 do_neon_mul_sat_scalar_long (void)
14097 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
14101 do_neon_vmull (void)
14103 if (inst
.operands
[2].isscalar
)
14104 do_neon_mac_maybe_scalar_long ();
14107 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14108 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
14109 if (et
.type
== NT_poly
)
14110 NEON_ENCODE (POLY
, inst
);
14112 NEON_ENCODE (INTEGER
, inst
);
14113 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14114 zero. Should be OK as-is. */
14115 neon_mixed_length (et
, et
.size
);
14122 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
14123 struct neon_type_el et
= neon_check_type (3, rs
,
14124 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14125 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
14127 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
14128 _("shift out of range"));
14129 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14130 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14131 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14132 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14133 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14134 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14135 inst
.instruction
|= neon_quad (rs
) << 6;
14136 inst
.instruction
|= imm
<< 8;
14138 neon_dp_fixup (&inst
);
14144 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14145 struct neon_type_el et
= neon_check_type (2, rs
,
14146 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14147 unsigned op
= (inst
.instruction
>> 7) & 3;
14148 /* N (width of reversed regions) is encoded as part of the bitmask. We
14149 extract it here to check the elements to be reversed are smaller.
14150 Otherwise we'd get a reserved instruction. */
14151 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
14152 gas_assert (elsize
!= 0);
14153 constraint (et
.size
>= elsize
,
14154 _("elements must be smaller than reversal region"));
14155 neon_two_same (neon_quad (rs
), 1, et
.size
);
14161 if (inst
.operands
[1].isscalar
)
14163 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
14164 struct neon_type_el et
= neon_check_type (2, rs
,
14165 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14166 unsigned sizebits
= et
.size
>> 3;
14167 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14168 int logsize
= neon_logbits (et
.size
);
14169 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
14171 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
14174 NEON_ENCODE (SCALAR
, inst
);
14175 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14176 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14177 inst
.instruction
|= LOW4 (dm
);
14178 inst
.instruction
|= HI1 (dm
) << 5;
14179 inst
.instruction
|= neon_quad (rs
) << 6;
14180 inst
.instruction
|= x
<< 17;
14181 inst
.instruction
|= sizebits
<< 16;
14183 neon_dp_fixup (&inst
);
14187 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
14188 struct neon_type_el et
= neon_check_type (2, rs
,
14189 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14190 /* Duplicate ARM register to lanes of vector. */
14191 NEON_ENCODE (ARMREG
, inst
);
14194 case 8: inst
.instruction
|= 0x400000; break;
14195 case 16: inst
.instruction
|= 0x000020; break;
14196 case 32: inst
.instruction
|= 0x000000; break;
14199 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14200 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
14201 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
14202 inst
.instruction
|= neon_quad (rs
) << 21;
14203 /* The encoding for this instruction is identical for the ARM and Thumb
14204 variants, except for the condition field. */
14205 do_vfp_cond_or_thumb ();
14209 /* VMOV has particularly many variations. It can be one of:
14210 0. VMOV<c><q> <Qd>, <Qm>
14211 1. VMOV<c><q> <Dd>, <Dm>
14212 (Register operations, which are VORR with Rm = Rn.)
14213 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14214 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14216 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14217 (ARM register to scalar.)
14218 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14219 (Two ARM registers to vector.)
14220 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14221 (Scalar to ARM register.)
14222 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14223 (Vector to two ARM registers.)
14224 8. VMOV.F32 <Sd>, <Sm>
14225 9. VMOV.F64 <Dd>, <Dm>
14226 (VFP register moves.)
14227 10. VMOV.F32 <Sd>, #imm
14228 11. VMOV.F64 <Dd>, #imm
14229 (VFP float immediate load.)
14230 12. VMOV <Rd>, <Sm>
14231 (VFP single to ARM reg.)
14232 13. VMOV <Sd>, <Rm>
14233 (ARM reg to VFP single.)
14234 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14235 (Two ARM regs to two VFP singles.)
14236 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14237 (Two VFP singles to two ARM regs.)
14239 These cases can be disambiguated using neon_select_shape, except cases 1/9
14240 and 3/11 which depend on the operand type too.
14242 All the encoded bits are hardcoded by this function.
14244 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14245 Cases 5, 7 may be used with VFPv2 and above.
14247 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14248 can specify a type where it doesn't make sense to, and is ignored). */
14253 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
14254 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
14256 struct neon_type_el et
;
14257 const char *ldconst
= 0;
14261 case NS_DD
: /* case 1/9. */
14262 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14263 /* It is not an error here if no type is given. */
14265 if (et
.type
== NT_float
&& et
.size
== 64)
14267 do_vfp_nsyn_opcode ("fcpyd");
14270 /* fall through. */
14272 case NS_QQ
: /* case 0/1. */
14274 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14276 /* The architecture manual I have doesn't explicitly state which
14277 value the U bit should have for register->register moves, but
14278 the equivalent VORR instruction has U = 0, so do that. */
14279 inst
.instruction
= 0x0200110;
14280 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14281 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14282 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14283 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14284 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14285 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14286 inst
.instruction
|= neon_quad (rs
) << 6;
14288 neon_dp_fixup (&inst
);
14292 case NS_DI
: /* case 3/11. */
14293 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14295 if (et
.type
== NT_float
&& et
.size
== 64)
14297 /* case 11 (fconstd). */
14298 ldconst
= "fconstd";
14299 goto encode_fconstd
;
14301 /* fall through. */
14303 case NS_QI
: /* case 2/3. */
14304 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14306 inst
.instruction
= 0x0800010;
14307 neon_move_immediate ();
14308 neon_dp_fixup (&inst
);
14311 case NS_SR
: /* case 4. */
14313 unsigned bcdebits
= 0;
14315 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
14316 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
14318 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14319 logsize
= neon_logbits (et
.size
);
14321 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14323 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14324 && et
.size
!= 32, _(BAD_FPU
));
14325 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14326 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14330 case 8: bcdebits
= 0x8; break;
14331 case 16: bcdebits
= 0x1; break;
14332 case 32: bcdebits
= 0x0; break;
14336 bcdebits
|= x
<< logsize
;
14338 inst
.instruction
= 0xe000b10;
14339 do_vfp_cond_or_thumb ();
14340 inst
.instruction
|= LOW4 (dn
) << 16;
14341 inst
.instruction
|= HI1 (dn
) << 7;
14342 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14343 inst
.instruction
|= (bcdebits
& 3) << 5;
14344 inst
.instruction
|= (bcdebits
>> 2) << 21;
14348 case NS_DRR
: /* case 5 (fmdrr). */
14349 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14352 inst
.instruction
= 0xc400b10;
14353 do_vfp_cond_or_thumb ();
14354 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
14355 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
14356 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14357 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14360 case NS_RS
: /* case 6. */
14363 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14364 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14365 unsigned abcdebits
= 0;
14367 et
= neon_check_type (2, NS_NULL
,
14368 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14369 logsize
= neon_logbits (et
.size
);
14371 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14373 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14374 && et
.size
!= 32, _(BAD_FPU
));
14375 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14376 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14380 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14381 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14382 case 32: abcdebits
= 0x00; break;
14386 abcdebits
|= x
<< logsize
;
14387 inst
.instruction
= 0xe100b10;
14388 do_vfp_cond_or_thumb ();
14389 inst
.instruction
|= LOW4 (dn
) << 16;
14390 inst
.instruction
|= HI1 (dn
) << 7;
14391 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14392 inst
.instruction
|= (abcdebits
& 3) << 5;
14393 inst
.instruction
|= (abcdebits
>> 2) << 21;
14397 case NS_RRD
: /* case 7 (fmrrd). */
14398 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14401 inst
.instruction
= 0xc500b10;
14402 do_vfp_cond_or_thumb ();
14403 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14404 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14405 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14406 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14409 case NS_FF
: /* case 8 (fcpys). */
14410 do_vfp_nsyn_opcode ("fcpys");
14413 case NS_FI
: /* case 10 (fconsts). */
14414 ldconst
= "fconsts";
14416 if (is_quarter_float (inst
.operands
[1].imm
))
14418 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
14419 do_vfp_nsyn_opcode (ldconst
);
14422 first_error (_("immediate out of range"));
14425 case NS_RF
: /* case 12 (fmrs). */
14426 do_vfp_nsyn_opcode ("fmrs");
14429 case NS_FR
: /* case 13 (fmsr). */
14430 do_vfp_nsyn_opcode ("fmsr");
14433 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14434 (one of which is a list), but we have parsed four. Do some fiddling to
14435 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14437 case NS_RRFF
: /* case 14 (fmrrs). */
14438 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
14439 _("VFP registers must be adjacent"));
14440 inst
.operands
[2].imm
= 2;
14441 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14442 do_vfp_nsyn_opcode ("fmrrs");
14445 case NS_FFRR
: /* case 15 (fmsrr). */
14446 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
14447 _("VFP registers must be adjacent"));
14448 inst
.operands
[1] = inst
.operands
[2];
14449 inst
.operands
[2] = inst
.operands
[3];
14450 inst
.operands
[0].imm
= 2;
14451 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14452 do_vfp_nsyn_opcode ("fmsrr");
14461 do_neon_rshift_round_imm (void)
14463 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14464 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14465 int imm
= inst
.operands
[2].imm
;
14467 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14470 inst
.operands
[2].present
= 0;
14475 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14476 _("immediate out of range for shift"));
14477 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
14482 do_neon_movl (void)
14484 struct neon_type_el et
= neon_check_type (2, NS_QD
,
14485 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14486 unsigned sizebits
= et
.size
>> 3;
14487 inst
.instruction
|= sizebits
<< 19;
14488 neon_two_same (0, et
.type
== NT_unsigned
, -1);
14494 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14495 struct neon_type_el et
= neon_check_type (2, rs
,
14496 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14497 NEON_ENCODE (INTEGER
, inst
);
14498 neon_two_same (neon_quad (rs
), 1, et
.size
);
14502 do_neon_zip_uzp (void)
14504 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14505 struct neon_type_el et
= neon_check_type (2, rs
,
14506 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14507 if (rs
== NS_DD
&& et
.size
== 32)
14509 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
14510 inst
.instruction
= N_MNEM_vtrn
;
14514 neon_two_same (neon_quad (rs
), 1, et
.size
);
14518 do_neon_sat_abs_neg (void)
14520 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14521 struct neon_type_el et
= neon_check_type (2, rs
,
14522 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14523 neon_two_same (neon_quad (rs
), 1, et
.size
);
14527 do_neon_pair_long (void)
14529 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14530 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
14531 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
14532 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
14533 neon_two_same (neon_quad (rs
), 1, et
.size
);
14537 do_neon_recip_est (void)
14539 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14540 struct neon_type_el et
= neon_check_type (2, rs
,
14541 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
14542 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14543 neon_two_same (neon_quad (rs
), 1, et
.size
);
14549 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14550 struct neon_type_el et
= neon_check_type (2, rs
,
14551 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14552 neon_two_same (neon_quad (rs
), 1, et
.size
);
14558 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14559 struct neon_type_el et
= neon_check_type (2, rs
,
14560 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
14561 neon_two_same (neon_quad (rs
), 1, et
.size
);
14567 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14568 struct neon_type_el et
= neon_check_type (2, rs
,
14569 N_EQK
| N_INT
, N_8
| N_KEY
);
14570 neon_two_same (neon_quad (rs
), 1, et
.size
);
14576 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14577 neon_two_same (neon_quad (rs
), 1, -1);
14581 do_neon_tbl_tbx (void)
14583 unsigned listlenbits
;
14584 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
14586 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
14588 first_error (_("bad list length for table lookup"));
14592 listlenbits
= inst
.operands
[1].imm
- 1;
14593 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14594 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14595 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14596 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14597 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14598 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14599 inst
.instruction
|= listlenbits
<< 8;
14601 neon_dp_fixup (&inst
);
14605 do_neon_ldm_stm (void)
14607 /* P, U and L bits are part of bitmask. */
14608 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
14609 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
14611 if (inst
.operands
[1].issingle
)
14613 do_vfp_nsyn_ldm_stm (is_dbmode
);
14617 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
14618 _("writeback (!) must be used for VLDMDB and VSTMDB"));
14620 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14621 _("register list must contain at least 1 and at most 16 "
14624 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14625 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
14626 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14627 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
14629 inst
.instruction
|= offsetbits
;
14631 do_vfp_cond_or_thumb ();
14635 do_neon_ldr_str (void)
14637 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
14639 if (inst
.operands
[0].issingle
)
14642 do_vfp_nsyn_opcode ("flds");
14644 do_vfp_nsyn_opcode ("fsts");
14649 do_vfp_nsyn_opcode ("fldd");
14651 do_vfp_nsyn_opcode ("fstd");
14655 /* "interleave" version also handles non-interleaving register VLD1/VST1
14659 do_neon_ld_st_interleave (void)
14661 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
14662 N_8
| N_16
| N_32
| N_64
);
14663 unsigned alignbits
= 0;
14665 /* The bits in this table go:
14666 0: register stride of one (0) or two (1)
14667 1,2: register list length, minus one (1, 2, 3, 4).
14668 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
14669 We use -1 for invalid entries. */
14670 const int typetable
[] =
14672 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
14673 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
14674 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
14675 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
14679 if (et
.type
== NT_invtype
)
14682 if (inst
.operands
[1].immisalign
)
14683 switch (inst
.operands
[1].imm
>> 8)
14685 case 64: alignbits
= 1; break;
14687 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
14688 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
14689 goto bad_alignment
;
14693 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
14694 goto bad_alignment
;
14699 first_error (_("bad alignment"));
14703 inst
.instruction
|= alignbits
<< 4;
14704 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14706 /* Bits [4:6] of the immediate in a list specifier encode register stride
14707 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
14708 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
14709 up the right value for "type" in a table based on this value and the given
14710 list style, then stick it back. */
14711 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
14712 | (((inst
.instruction
>> 8) & 3) << 3);
14714 typebits
= typetable
[idx
];
14716 constraint (typebits
== -1, _("bad list type for instruction"));
14718 inst
.instruction
&= ~0xf00;
14719 inst
.instruction
|= typebits
<< 8;
14722 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
14723 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
14724 otherwise. The variable arguments are a list of pairs of legal (size, align)
14725 values, terminated with -1. */
14728 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
14731 int result
= FAIL
, thissize
, thisalign
;
14733 if (!inst
.operands
[1].immisalign
)
14739 va_start (ap
, do_align
);
14743 thissize
= va_arg (ap
, int);
14744 if (thissize
== -1)
14746 thisalign
= va_arg (ap
, int);
14748 if (size
== thissize
&& align
== thisalign
)
14751 while (result
!= SUCCESS
);
14755 if (result
== SUCCESS
)
14758 first_error (_("unsupported alignment for instruction"));
14764 do_neon_ld_st_lane (void)
14766 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14767 int align_good
, do_align
= 0;
14768 int logsize
= neon_logbits (et
.size
);
14769 int align
= inst
.operands
[1].imm
>> 8;
14770 int n
= (inst
.instruction
>> 8) & 3;
14771 int max_el
= 64 / et
.size
;
14773 if (et
.type
== NT_invtype
)
14776 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
14777 _("bad list length"));
14778 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
14779 _("scalar index out of range"));
14780 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
14782 _("stride of 2 unavailable when element size is 8"));
14786 case 0: /* VLD1 / VST1. */
14787 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
14789 if (align_good
== FAIL
)
14793 unsigned alignbits
= 0;
14796 case 16: alignbits
= 0x1; break;
14797 case 32: alignbits
= 0x3; break;
14800 inst
.instruction
|= alignbits
<< 4;
14804 case 1: /* VLD2 / VST2. */
14805 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
14807 if (align_good
== FAIL
)
14810 inst
.instruction
|= 1 << 4;
14813 case 2: /* VLD3 / VST3. */
14814 constraint (inst
.operands
[1].immisalign
,
14815 _("can't use alignment with this instruction"));
14818 case 3: /* VLD4 / VST4. */
14819 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14820 16, 64, 32, 64, 32, 128, -1);
14821 if (align_good
== FAIL
)
14825 unsigned alignbits
= 0;
14828 case 8: alignbits
= 0x1; break;
14829 case 16: alignbits
= 0x1; break;
14830 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
14833 inst
.instruction
|= alignbits
<< 4;
14840 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
14841 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14842 inst
.instruction
|= 1 << (4 + logsize
);
14844 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
14845 inst
.instruction
|= logsize
<< 10;
14848 /* Encode single n-element structure to all lanes VLD<n> instructions. */
14851 do_neon_ld_dup (void)
14853 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14854 int align_good
, do_align
= 0;
14856 if (et
.type
== NT_invtype
)
14859 switch ((inst
.instruction
>> 8) & 3)
14861 case 0: /* VLD1. */
14862 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
14863 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14864 &do_align
, 16, 16, 32, 32, -1);
14865 if (align_good
== FAIL
)
14867 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
14870 case 2: inst
.instruction
|= 1 << 5; break;
14871 default: first_error (_("bad list length")); return;
14873 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14876 case 1: /* VLD2. */
14877 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14878 &do_align
, 8, 16, 16, 32, 32, 64, -1);
14879 if (align_good
== FAIL
)
14881 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
14882 _("bad list length"));
14883 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14884 inst
.instruction
|= 1 << 5;
14885 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14888 case 2: /* VLD3. */
14889 constraint (inst
.operands
[1].immisalign
,
14890 _("can't use alignment with this instruction"));
14891 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
14892 _("bad list length"));
14893 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14894 inst
.instruction
|= 1 << 5;
14895 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14898 case 3: /* VLD4. */
14900 int align
= inst
.operands
[1].imm
>> 8;
14901 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14902 16, 64, 32, 64, 32, 128, -1);
14903 if (align_good
== FAIL
)
14905 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
14906 _("bad list length"));
14907 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14908 inst
.instruction
|= 1 << 5;
14909 if (et
.size
== 32 && align
== 128)
14910 inst
.instruction
|= 0x3 << 6;
14912 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14919 inst
.instruction
|= do_align
<< 4;
14922 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
14923 apart from bits [11:4]. */
14926 do_neon_ldx_stx (void)
14928 if (inst
.operands
[1].isreg
)
14929 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
14931 switch (NEON_LANE (inst
.operands
[0].imm
))
14933 case NEON_INTERLEAVE_LANES
:
14934 NEON_ENCODE (INTERLV
, inst
);
14935 do_neon_ld_st_interleave ();
14938 case NEON_ALL_LANES
:
14939 NEON_ENCODE (DUP
, inst
);
14944 NEON_ENCODE (LANE
, inst
);
14945 do_neon_ld_st_lane ();
14948 /* L bit comes from bit mask. */
14949 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14950 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14951 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14953 if (inst
.operands
[1].postind
)
14955 int postreg
= inst
.operands
[1].imm
& 0xf;
14956 constraint (!inst
.operands
[1].immisreg
,
14957 _("post-index must be a register"));
14958 constraint (postreg
== 0xd || postreg
== 0xf,
14959 _("bad register for post-index"));
14960 inst
.instruction
|= postreg
;
14962 else if (inst
.operands
[1].writeback
)
14964 inst
.instruction
|= 0xd;
14967 inst
.instruction
|= 0xf;
14970 inst
.instruction
|= 0xf9000000;
14972 inst
.instruction
|= 0xf4000000;
14975 /* Overall per-instruction processing. */
14977 /* We need to be able to fix up arbitrary expressions in some statements.
14978 This is so that we can handle symbols that are an arbitrary distance from
14979 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
14980 which returns part of an address in a form which will be valid for
14981 a data instruction. We do this by pushing the expression into a symbol
14982 in the expr_section, and creating a fix for that. */
14985 fix_new_arm (fragS
* frag
,
15000 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
15001 (enum bfd_reloc_code_real
) reloc
);
15005 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
15006 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
15010 /* Mark whether the fix is to a THUMB instruction, or an ARM
15012 new_fix
->tc_fix_data
= thumb_mode
;
15015 /* Create a frg for an instruction requiring relaxation. */
15017 output_relax_insn (void)
15023 /* The size of the instruction is unknown, so tie the debug info to the
15024 start of the instruction. */
15025 dwarf2_emit_insn (0);
15027 switch (inst
.reloc
.exp
.X_op
)
15030 sym
= inst
.reloc
.exp
.X_add_symbol
;
15031 offset
= inst
.reloc
.exp
.X_add_number
;
15035 offset
= inst
.reloc
.exp
.X_add_number
;
15038 sym
= make_expr_symbol (&inst
.reloc
.exp
);
15042 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
15043 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
15044 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
15047 /* Write a 32-bit thumb instruction to buf. */
15049 put_thumb32_insn (char * buf
, unsigned long insn
)
15051 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
15052 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
15056 output_inst (const char * str
)
15062 as_bad ("%s -- `%s'", inst
.error
, str
);
15067 output_relax_insn ();
15070 if (inst
.size
== 0)
15073 to
= frag_more (inst
.size
);
15074 /* PR 9814: Record the thumb mode into the current frag so that we know
15075 what type of NOP padding to use, if necessary. We override any previous
15076 setting so that if the mode has changed then the NOPS that we use will
15077 match the encoding of the last instruction in the frag. */
15078 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
15080 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
15082 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
15083 put_thumb32_insn (to
, inst
.instruction
);
15085 else if (inst
.size
> INSN_SIZE
)
15087 gas_assert (inst
.size
== (2 * INSN_SIZE
));
15088 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
15089 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
15092 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
15094 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
15095 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
15096 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
15099 dwarf2_emit_insn (inst
.size
);
15103 output_it_inst (int cond
, int mask
, char * to
)
15105 unsigned long instruction
= 0xbf00;
15108 instruction
|= mask
;
15109 instruction
|= cond
<< 4;
15113 to
= frag_more (2);
15115 dwarf2_emit_insn (2);
15119 md_number_to_chars (to
, instruction
, 2);
15124 /* Tag values used in struct asm_opcode's tag field. */
15127 OT_unconditional
, /* Instruction cannot be conditionalized.
15128 The ARM condition field is still 0xE. */
15129 OT_unconditionalF
, /* Instruction cannot be conditionalized
15130 and carries 0xF in its ARM condition field. */
15131 OT_csuffix
, /* Instruction takes a conditional suffix. */
15132 OT_csuffixF
, /* Some forms of the instruction take a conditional
15133 suffix, others place 0xF where the condition field
15135 OT_cinfix3
, /* Instruction takes a conditional infix,
15136 beginning at character index 3. (In
15137 unified mode, it becomes a suffix.) */
15138 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
15139 tsts, cmps, cmns, and teqs. */
15140 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
15141 character index 3, even in unified mode. Used for
15142 legacy instructions where suffix and infix forms
15143 may be ambiguous. */
15144 OT_csuf_or_in3
, /* Instruction takes either a conditional
15145 suffix or an infix at character index 3. */
15146 OT_odd_infix_unc
, /* This is the unconditional variant of an
15147 instruction that takes a conditional infix
15148 at an unusual position. In unified mode,
15149 this variant will accept a suffix. */
15150 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
15151 are the conditional variants of instructions that
15152 take conditional infixes in unusual positions.
15153 The infix appears at character index
15154 (tag - OT_odd_infix_0). These are not accepted
15155 in unified mode. */
15158 /* Subroutine of md_assemble, responsible for looking up the primary
15159 opcode from the mnemonic the user wrote. STR points to the
15160 beginning of the mnemonic.
15162 This is not simply a hash table lookup, because of conditional
15163 variants. Most instructions have conditional variants, which are
15164 expressed with a _conditional affix_ to the mnemonic. If we were
15165 to encode each conditional variant as a literal string in the opcode
15166 table, it would have approximately 20,000 entries.
15168 Most mnemonics take this affix as a suffix, and in unified syntax,
15169 'most' is upgraded to 'all'. However, in the divided syntax, some
15170 instructions take the affix as an infix, notably the s-variants of
15171 the arithmetic instructions. Of those instructions, all but six
15172 have the infix appear after the third character of the mnemonic.
15174 Accordingly, the algorithm for looking up primary opcodes given
15177 1. Look up the identifier in the opcode table.
15178 If we find a match, go to step U.
15180 2. Look up the last two characters of the identifier in the
15181 conditions table. If we find a match, look up the first N-2
15182 characters of the identifier in the opcode table. If we
15183 find a match, go to step CE.
15185 3. Look up the fourth and fifth characters of the identifier in
15186 the conditions table. If we find a match, extract those
15187 characters from the identifier, and look up the remaining
15188 characters in the opcode table. If we find a match, go
15193 U. Examine the tag field of the opcode structure, in case this is
15194 one of the six instructions with its conditional infix in an
15195 unusual place. If it is, the tag tells us where to find the
15196 infix; look it up in the conditions table and set inst.cond
15197 accordingly. Otherwise, this is an unconditional instruction.
15198 Again set inst.cond accordingly. Return the opcode structure.
15200 CE. Examine the tag field to make sure this is an instruction that
15201 should receive a conditional suffix. If it is not, fail.
15202 Otherwise, set inst.cond from the suffix we already looked up,
15203 and return the opcode structure.
15205 CM. Examine the tag field to make sure this is an instruction that
15206 should receive a conditional infix after the third character.
15207 If it is not, fail. Otherwise, undo the edits to the current
15208 line of input and proceed as for case CE. */
15210 static const struct asm_opcode
*
15211 opcode_lookup (char **str
)
15215 const struct asm_opcode
*opcode
;
15216 const struct asm_cond
*cond
;
15219 /* Scan up to the end of the mnemonic, which must end in white space,
15220 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15221 for (base
= end
= *str
; *end
!= '\0'; end
++)
15222 if (*end
== ' ' || *end
== '.')
15228 /* Handle a possible width suffix and/or Neon type suffix. */
15233 /* The .w and .n suffixes are only valid if the unified syntax is in
15235 if (unified_syntax
&& end
[1] == 'w')
15237 else if (unified_syntax
&& end
[1] == 'n')
15242 inst
.vectype
.elems
= 0;
15244 *str
= end
+ offset
;
15246 if (end
[offset
] == '.')
15248 /* See if we have a Neon type suffix (possible in either unified or
15249 non-unified ARM syntax mode). */
15250 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
15253 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
15259 /* Look for unaffixed or special-case affixed mnemonic. */
15260 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15265 if (opcode
->tag
< OT_odd_infix_0
)
15267 inst
.cond
= COND_ALWAYS
;
15271 if (warn_on_deprecated
&& unified_syntax
)
15272 as_warn (_("conditional infixes are deprecated in unified syntax"));
15273 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
15274 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15277 inst
.cond
= cond
->value
;
15281 /* Cannot have a conditional suffix on a mnemonic of less than two
15283 if (end
- base
< 3)
15286 /* Look for suffixed mnemonic. */
15288 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15289 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15291 if (opcode
&& cond
)
15294 switch (opcode
->tag
)
15296 case OT_cinfix3_legacy
:
15297 /* Ignore conditional suffixes matched on infix only mnemonics. */
15301 case OT_cinfix3_deprecated
:
15302 case OT_odd_infix_unc
:
15303 if (!unified_syntax
)
15305 /* else fall through */
15309 case OT_csuf_or_in3
:
15310 inst
.cond
= cond
->value
;
15313 case OT_unconditional
:
15314 case OT_unconditionalF
:
15316 inst
.cond
= cond
->value
;
15319 /* Delayed diagnostic. */
15320 inst
.error
= BAD_COND
;
15321 inst
.cond
= COND_ALWAYS
;
15330 /* Cannot have a usual-position infix on a mnemonic of less than
15331 six characters (five would be a suffix). */
15332 if (end
- base
< 6)
15335 /* Look for infixed mnemonic in the usual position. */
15337 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15341 memcpy (save
, affix
, 2);
15342 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
15343 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15345 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
15346 memcpy (affix
, save
, 2);
15349 && (opcode
->tag
== OT_cinfix3
15350 || opcode
->tag
== OT_cinfix3_deprecated
15351 || opcode
->tag
== OT_csuf_or_in3
15352 || opcode
->tag
== OT_cinfix3_legacy
))
15355 if (warn_on_deprecated
&& unified_syntax
15356 && (opcode
->tag
== OT_cinfix3
15357 || opcode
->tag
== OT_cinfix3_deprecated
))
15358 as_warn (_("conditional infixes are deprecated in unified syntax"));
15360 inst
.cond
= cond
->value
;
15367 /* This function generates an initial IT instruction, leaving its block
15368 virtually open for the new instructions. Eventually,
15369 the mask will be updated by now_it_add_mask () each time
15370 a new instruction needs to be included in the IT block.
15371 Finally, the block is closed with close_automatic_it_block ().
15372 The block closure can be requested either from md_assemble (),
15373 a tencode (), or due to a label hook. */
15376 new_automatic_it_block (int cond
)
15378 now_it
.state
= AUTOMATIC_IT_BLOCK
;
15379 now_it
.mask
= 0x18;
15381 now_it
.block_length
= 1;
15382 mapping_state (MAP_THUMB
);
15383 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
15386 /* Close an automatic IT block.
15387 See comments in new_automatic_it_block (). */
15390 close_automatic_it_block (void)
15392 now_it
.mask
= 0x10;
15393 now_it
.block_length
= 0;
15396 /* Update the mask of the current automatically-generated IT
15397 instruction. See comments in new_automatic_it_block (). */
15400 now_it_add_mask (int cond
)
15402 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15403 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15404 | ((bitvalue) << (nbit)))
15405 const int resulting_bit
= (cond
& 1);
15407 now_it
.mask
&= 0xf;
15408 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15410 (5 - now_it
.block_length
));
15411 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15413 ((5 - now_it
.block_length
) - 1) );
15414 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
15417 #undef SET_BIT_VALUE
15420 /* The IT blocks handling machinery is accessed through the these functions:
15421 it_fsm_pre_encode () from md_assemble ()
15422 set_it_insn_type () optional, from the tencode functions
15423 set_it_insn_type_last () ditto
15424 in_it_block () ditto
15425 it_fsm_post_encode () from md_assemble ()
15426 force_automatic_it_block_close () from label habdling functions
15429 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15430 initializing the IT insn type with a generic initial value depending
15431 on the inst.condition.
15432 2) During the tencode function, two things may happen:
15433 a) The tencode function overrides the IT insn type by
15434 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15435 b) The tencode function queries the IT block state by
15436 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15438 Both set_it_insn_type and in_it_block run the internal FSM state
15439 handling function (handle_it_state), because: a) setting the IT insn
15440 type may incur in an invalid state (exiting the function),
15441 and b) querying the state requires the FSM to be updated.
15442 Specifically we want to avoid creating an IT block for conditional
15443 branches, so it_fsm_pre_encode is actually a guess and we can't
15444 determine whether an IT block is required until the tencode () routine
15445 has decided what type of instruction this actually it.
15446 Because of this, if set_it_insn_type and in_it_block have to be used,
15447 set_it_insn_type has to be called first.
15449 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15450 determines the insn IT type depending on the inst.cond code.
15451 When a tencode () routine encodes an instruction that can be
15452 either outside an IT block, or, in the case of being inside, has to be
15453 the last one, set_it_insn_type_last () will determine the proper
15454 IT instruction type based on the inst.cond code. Otherwise,
15455 set_it_insn_type can be called for overriding that logic or
15456 for covering other cases.
15458 Calling handle_it_state () may not transition the IT block state to
15459 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
15460 still queried. Instead, if the FSM determines that the state should
15461 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
15462 after the tencode () function: that's what it_fsm_post_encode () does.
15464 Since in_it_block () calls the state handling function to get an
15465 updated state, an error may occur (due to invalid insns combination).
15466 In that case, inst.error is set.
15467 Therefore, inst.error has to be checked after the execution of
15468 the tencode () routine.
15470 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
15471 any pending state change (if any) that didn't take place in
15472 handle_it_state () as explained above. */
15475 it_fsm_pre_encode (void)
15477 if (inst
.cond
!= COND_ALWAYS
)
15478 inst
.it_insn_type
= INSIDE_IT_INSN
;
15480 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
15482 now_it
.state_handled
= 0;
15485 /* IT state FSM handling function. */
15488 handle_it_state (void)
15490 now_it
.state_handled
= 1;
15492 switch (now_it
.state
)
15494 case OUTSIDE_IT_BLOCK
:
15495 switch (inst
.it_insn_type
)
15497 case OUTSIDE_IT_INSN
:
15500 case INSIDE_IT_INSN
:
15501 case INSIDE_IT_LAST_INSN
:
15502 if (thumb_mode
== 0)
15505 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
15506 as_tsktsk (_("Warning: conditional outside an IT block"\
15511 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
15512 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
15514 /* Automatically generate the IT instruction. */
15515 new_automatic_it_block (inst
.cond
);
15516 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
15517 close_automatic_it_block ();
15521 inst
.error
= BAD_OUT_IT
;
15527 case IF_INSIDE_IT_LAST_INSN
:
15528 case NEUTRAL_IT_INSN
:
15532 now_it
.state
= MANUAL_IT_BLOCK
;
15533 now_it
.block_length
= 0;
15538 case AUTOMATIC_IT_BLOCK
:
15539 /* Three things may happen now:
15540 a) We should increment current it block size;
15541 b) We should close current it block (closing insn or 4 insns);
15542 c) We should close current it block and start a new one (due
15543 to incompatible conditions or
15544 4 insns-length block reached). */
15546 switch (inst
.it_insn_type
)
15548 case OUTSIDE_IT_INSN
:
15549 /* The closure of the block shall happen immediatelly,
15550 so any in_it_block () call reports the block as closed. */
15551 force_automatic_it_block_close ();
15554 case INSIDE_IT_INSN
:
15555 case INSIDE_IT_LAST_INSN
:
15556 case IF_INSIDE_IT_LAST_INSN
:
15557 now_it
.block_length
++;
15559 if (now_it
.block_length
> 4
15560 || !now_it_compatible (inst
.cond
))
15562 force_automatic_it_block_close ();
15563 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
15564 new_automatic_it_block (inst
.cond
);
15568 now_it_add_mask (inst
.cond
);
15571 if (now_it
.state
== AUTOMATIC_IT_BLOCK
15572 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
15573 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
15574 close_automatic_it_block ();
15577 case NEUTRAL_IT_INSN
:
15578 now_it
.block_length
++;
15580 if (now_it
.block_length
> 4)
15581 force_automatic_it_block_close ();
15583 now_it_add_mask (now_it
.cc
& 1);
15587 close_automatic_it_block ();
15588 now_it
.state
= MANUAL_IT_BLOCK
;
15593 case MANUAL_IT_BLOCK
:
15595 /* Check conditional suffixes. */
15596 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
15599 now_it
.mask
&= 0x1f;
15600 is_last
= (now_it
.mask
== 0x10);
15602 switch (inst
.it_insn_type
)
15604 case OUTSIDE_IT_INSN
:
15605 inst
.error
= BAD_NOT_IT
;
15608 case INSIDE_IT_INSN
:
15609 if (cond
!= inst
.cond
)
15611 inst
.error
= BAD_IT_COND
;
15616 case INSIDE_IT_LAST_INSN
:
15617 case IF_INSIDE_IT_LAST_INSN
:
15618 if (cond
!= inst
.cond
)
15620 inst
.error
= BAD_IT_COND
;
15625 inst
.error
= BAD_BRANCH
;
15630 case NEUTRAL_IT_INSN
:
15631 /* The BKPT instruction is unconditional even in an IT block. */
15635 inst
.error
= BAD_IT_IT
;
15646 it_fsm_post_encode (void)
15650 if (!now_it
.state_handled
)
15651 handle_it_state ();
15653 is_last
= (now_it
.mask
== 0x10);
15656 now_it
.state
= OUTSIDE_IT_BLOCK
;
15662 force_automatic_it_block_close (void)
15664 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
15666 close_automatic_it_block ();
15667 now_it
.state
= OUTSIDE_IT_BLOCK
;
15675 if (!now_it
.state_handled
)
15676 handle_it_state ();
15678 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
15682 md_assemble (char *str
)
15685 const struct asm_opcode
* opcode
;
15687 /* Align the previous label if needed. */
15688 if (last_label_seen
!= NULL
)
15690 symbol_set_frag (last_label_seen
, frag_now
);
15691 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
15692 S_SET_SEGMENT (last_label_seen
, now_seg
);
15695 memset (&inst
, '\0', sizeof (inst
));
15696 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
15698 opcode
= opcode_lookup (&p
);
15701 /* It wasn't an instruction, but it might be a register alias of
15702 the form alias .req reg, or a Neon .dn/.qn directive. */
15703 if (! create_register_alias (str
, p
)
15704 && ! create_neon_reg_alias (str
, p
))
15705 as_bad (_("bad instruction `%s'"), str
);
15710 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
15711 as_warn (_("s suffix on comparison instruction is deprecated"));
15713 /* The value which unconditional instructions should have in place of the
15714 condition field. */
15715 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
15719 arm_feature_set variant
;
15721 variant
= cpu_variant
;
15722 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
15723 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
15724 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
15725 /* Check that this instruction is supported for this CPU. */
15726 if (!opcode
->tvariant
15727 || (thumb_mode
== 1
15728 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
15730 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
15733 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
15734 && opcode
->tencode
!= do_t_branch
)
15736 as_bad (_("Thumb does not support conditional execution"));
15740 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
15742 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
15743 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
15744 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
15746 /* Two things are addressed here.
15747 1) Implicit require narrow instructions on Thumb-1.
15748 This avoids relaxation accidentally introducing Thumb-2
15750 2) Reject wide instructions in non Thumb-2 cores. */
15751 if (inst
.size_req
== 0)
15753 else if (inst
.size_req
== 4)
15755 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
15761 inst
.instruction
= opcode
->tvalue
;
15763 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
15765 /* Prepare the it_insn_type for those encodings that don't set
15767 it_fsm_pre_encode ();
15769 opcode
->tencode ();
15771 it_fsm_post_encode ();
15774 if (!(inst
.error
|| inst
.relax
))
15776 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
15777 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
15778 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
15780 as_bad (_("cannot honor width suffix -- `%s'"), str
);
15785 /* Something has gone badly wrong if we try to relax a fixed size
15787 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
15789 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15790 *opcode
->tvariant
);
15791 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
15792 set those bits when Thumb-2 32-bit instructions are seen. ie.
15793 anything other than bl/blx and v6-M instructions.
15794 This is overly pessimistic for relaxable instructions. */
15795 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
15797 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
15798 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
15799 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15802 check_neon_suffixes
;
15806 mapping_state (MAP_THUMB
);
15809 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
15813 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
15814 is_bx
= (opcode
->aencode
== do_bx
);
15816 /* Check that this instruction is supported for this CPU. */
15817 if (!(is_bx
&& fix_v4bx
)
15818 && !(opcode
->avariant
&&
15819 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
15821 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
15826 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
15830 inst
.instruction
= opcode
->avalue
;
15831 if (opcode
->tag
== OT_unconditionalF
)
15832 inst
.instruction
|= 0xF << 28;
15834 inst
.instruction
|= inst
.cond
<< 28;
15835 inst
.size
= INSN_SIZE
;
15836 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
15838 it_fsm_pre_encode ();
15839 opcode
->aencode ();
15840 it_fsm_post_encode ();
15842 /* Arm mode bx is marked as both v4T and v5 because it's still required
15843 on a hypothetical non-thumb v5 core. */
15845 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
15847 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
15848 *opcode
->avariant
);
15850 check_neon_suffixes
;
15854 mapping_state (MAP_ARM
);
15859 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
15867 check_it_blocks_finished (void)
15872 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
15873 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
15874 == MANUAL_IT_BLOCK
)
15876 as_warn (_("section '%s' finished with an open IT block."),
15880 if (now_it
.state
== MANUAL_IT_BLOCK
)
15881 as_warn (_("file finished with an open IT block."));
15885 /* Various frobbings of labels and their addresses. */
15888 arm_start_line_hook (void)
15890 last_label_seen
= NULL
;
15894 arm_frob_label (symbolS
* sym
)
15896 last_label_seen
= sym
;
15898 ARM_SET_THUMB (sym
, thumb_mode
);
15900 #if defined OBJ_COFF || defined OBJ_ELF
15901 ARM_SET_INTERWORK (sym
, support_interwork
);
15904 force_automatic_it_block_close ();
15906 /* Note - do not allow local symbols (.Lxxx) to be labelled
15907 as Thumb functions. This is because these labels, whilst
15908 they exist inside Thumb code, are not the entry points for
15909 possible ARM->Thumb calls. Also, these labels can be used
15910 as part of a computed goto or switch statement. eg gcc
15911 can generate code that looks like this:
15913 ldr r2, [pc, .Laaa]
15923 The first instruction loads the address of the jump table.
15924 The second instruction converts a table index into a byte offset.
15925 The third instruction gets the jump address out of the table.
15926 The fourth instruction performs the jump.
15928 If the address stored at .Laaa is that of a symbol which has the
15929 Thumb_Func bit set, then the linker will arrange for this address
15930 to have the bottom bit set, which in turn would mean that the
15931 address computation performed by the third instruction would end
15932 up with the bottom bit set. Since the ARM is capable of unaligned
15933 word loads, the instruction would then load the incorrect address
15934 out of the jump table, and chaos would ensue. */
15935 if (label_is_thumb_function_name
15936 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
15937 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
15939 /* When the address of a Thumb function is taken the bottom
15940 bit of that address should be set. This will allow
15941 interworking between Arm and Thumb functions to work
15944 THUMB_SET_FUNC (sym
, 1);
15946 label_is_thumb_function_name
= FALSE
;
15949 dwarf2_emit_label (sym
);
15953 arm_data_in_code (void)
15955 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
15957 *input_line_pointer
= '/';
15958 input_line_pointer
+= 5;
15959 *input_line_pointer
= 0;
15967 arm_canonicalize_symbol_name (char * name
)
15971 if (thumb_mode
&& (len
= strlen (name
)) > 5
15972 && streq (name
+ len
- 5, "/data"))
15973 *(name
+ len
- 5) = 0;
15978 /* Table of all register names defined by default. The user can
15979 define additional names with .req. Note that all register names
15980 should appear in both upper and lowercase variants. Some registers
15981 also have mixed-case names. */
15983 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
15984 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
15985 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
15986 #define REGSET(p,t) \
15987 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
15988 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
15989 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
15990 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
15991 #define REGSETH(p,t) \
15992 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
15993 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
15994 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
15995 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
15996 #define REGSET2(p,t) \
15997 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
15998 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
15999 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16000 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16002 static const struct reg_entry reg_names
[] =
16004 /* ARM integer registers. */
16005 REGSET(r
, RN
), REGSET(R
, RN
),
16007 /* ATPCS synonyms. */
16008 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
16009 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
16010 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
16012 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
16013 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
16014 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
16016 /* Well-known aliases. */
16017 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
16018 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
16020 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
16021 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
16023 /* Coprocessor numbers. */
16024 REGSET(p
, CP
), REGSET(P
, CP
),
16026 /* Coprocessor register numbers. The "cr" variants are for backward
16028 REGSET(c
, CN
), REGSET(C
, CN
),
16029 REGSET(cr
, CN
), REGSET(CR
, CN
),
16031 /* FPA registers. */
16032 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
16033 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
16035 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
16036 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
16038 /* VFP SP registers. */
16039 REGSET(s
,VFS
), REGSET(S
,VFS
),
16040 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
16042 /* VFP DP Registers. */
16043 REGSET(d
,VFD
), REGSET(D
,VFD
),
16044 /* Extra Neon DP registers. */
16045 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
16047 /* Neon QP registers. */
16048 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
16050 /* VFP control registers. */
16051 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
16052 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
16053 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
16054 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
16055 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
16056 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
16058 /* Maverick DSP coprocessor registers. */
16059 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
16060 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
16062 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
16063 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
16064 REGDEF(dspsc
,0,DSPSC
),
16066 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
16067 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
16068 REGDEF(DSPSC
,0,DSPSC
),
16070 /* iWMMXt data registers - p0, c0-15. */
16071 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
16073 /* iWMMXt control registers - p1, c0-3. */
16074 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
16075 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
16076 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
16077 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
16079 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16080 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
16081 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
16082 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
16083 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
16085 /* XScale accumulator registers. */
16086 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
16092 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16093 within psr_required_here. */
16094 static const struct asm_psr psrs
[] =
16096 /* Backward compatibility notation. Note that "all" is no longer
16097 truly all possible PSR bits. */
16098 {"all", PSR_c
| PSR_f
},
16102 /* Individual flags. */
16107 /* Combinations of flags. */
16108 {"fs", PSR_f
| PSR_s
},
16109 {"fx", PSR_f
| PSR_x
},
16110 {"fc", PSR_f
| PSR_c
},
16111 {"sf", PSR_s
| PSR_f
},
16112 {"sx", PSR_s
| PSR_x
},
16113 {"sc", PSR_s
| PSR_c
},
16114 {"xf", PSR_x
| PSR_f
},
16115 {"xs", PSR_x
| PSR_s
},
16116 {"xc", PSR_x
| PSR_c
},
16117 {"cf", PSR_c
| PSR_f
},
16118 {"cs", PSR_c
| PSR_s
},
16119 {"cx", PSR_c
| PSR_x
},
16120 {"fsx", PSR_f
| PSR_s
| PSR_x
},
16121 {"fsc", PSR_f
| PSR_s
| PSR_c
},
16122 {"fxs", PSR_f
| PSR_x
| PSR_s
},
16123 {"fxc", PSR_f
| PSR_x
| PSR_c
},
16124 {"fcs", PSR_f
| PSR_c
| PSR_s
},
16125 {"fcx", PSR_f
| PSR_c
| PSR_x
},
16126 {"sfx", PSR_s
| PSR_f
| PSR_x
},
16127 {"sfc", PSR_s
| PSR_f
| PSR_c
},
16128 {"sxf", PSR_s
| PSR_x
| PSR_f
},
16129 {"sxc", PSR_s
| PSR_x
| PSR_c
},
16130 {"scf", PSR_s
| PSR_c
| PSR_f
},
16131 {"scx", PSR_s
| PSR_c
| PSR_x
},
16132 {"xfs", PSR_x
| PSR_f
| PSR_s
},
16133 {"xfc", PSR_x
| PSR_f
| PSR_c
},
16134 {"xsf", PSR_x
| PSR_s
| PSR_f
},
16135 {"xsc", PSR_x
| PSR_s
| PSR_c
},
16136 {"xcf", PSR_x
| PSR_c
| PSR_f
},
16137 {"xcs", PSR_x
| PSR_c
| PSR_s
},
16138 {"cfs", PSR_c
| PSR_f
| PSR_s
},
16139 {"cfx", PSR_c
| PSR_f
| PSR_x
},
16140 {"csf", PSR_c
| PSR_s
| PSR_f
},
16141 {"csx", PSR_c
| PSR_s
| PSR_x
},
16142 {"cxf", PSR_c
| PSR_x
| PSR_f
},
16143 {"cxs", PSR_c
| PSR_x
| PSR_s
},
16144 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
16145 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
16146 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
16147 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
16148 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
16149 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
16150 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
16151 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
16152 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
16153 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
16154 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
16155 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
16156 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
16157 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
16158 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
16159 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
16160 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
16161 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
16162 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
16163 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
16164 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
16165 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
16166 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
16167 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
16170 /* Table of V7M psr names. */
16171 static const struct asm_psr v7m_psrs
[] =
16173 {"apsr", 0 }, {"APSR", 0 },
16174 {"iapsr", 1 }, {"IAPSR", 1 },
16175 {"eapsr", 2 }, {"EAPSR", 2 },
16176 {"psr", 3 }, {"PSR", 3 },
16177 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16178 {"ipsr", 5 }, {"IPSR", 5 },
16179 {"epsr", 6 }, {"EPSR", 6 },
16180 {"iepsr", 7 }, {"IEPSR", 7 },
16181 {"msp", 8 }, {"MSP", 8 },
16182 {"psp", 9 }, {"PSP", 9 },
16183 {"primask", 16}, {"PRIMASK", 16},
16184 {"basepri", 17}, {"BASEPRI", 17},
16185 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16186 {"faultmask", 19}, {"FAULTMASK", 19},
16187 {"control", 20}, {"CONTROL", 20}
16190 /* Table of all shift-in-operand names. */
16191 static const struct asm_shift_name shift_names
[] =
16193 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
16194 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
16195 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
16196 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
16197 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
16198 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
16201 /* Table of all explicit relocation names. */
16203 static struct reloc_entry reloc_names
[] =
16205 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
16206 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
16207 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
16208 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
16209 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
16210 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
16211 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
16212 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
16213 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
16214 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
16215 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
16216 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
}
16220 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16221 static const struct asm_cond conds
[] =
16225 {"cs", 0x2}, {"hs", 0x2},
16226 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16240 static struct asm_barrier_opt barrier_opt_names
[] =
16248 /* Table of ARM-format instructions. */
16250 /* Macros for gluing together operand strings. N.B. In all cases
16251 other than OPS0, the trailing OP_stop comes from default
16252 zero-initialization of the unspecified elements of the array. */
16253 #define OPS0() { OP_stop, }
16254 #define OPS1(a) { OP_##a, }
16255 #define OPS2(a,b) { OP_##a,OP_##b, }
16256 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16257 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16258 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16259 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16261 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16262 This is useful when mixing operands for ARM and THUMB, i.e. using the
16263 MIX_ARM_THUMB_OPERANDS macro.
16264 In order to use these macros, prefix the number of operands with _
16266 #define OPS_1(a) { a, }
16267 #define OPS_2(a,b) { a,b, }
16268 #define OPS_3(a,b,c) { a,b,c, }
16269 #define OPS_4(a,b,c,d) { a,b,c,d, }
16270 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16271 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16273 /* These macros abstract out the exact format of the mnemonic table and
16274 save some repeated characters. */
16276 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16277 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16278 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16279 THUMB_VARIANT, do_##ae, do_##te }
16281 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16282 a T_MNEM_xyz enumerator. */
16283 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16284 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16285 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16286 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16288 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16289 infix after the third character. */
16290 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16291 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16292 THUMB_VARIANT, do_##ae, do_##te }
16293 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16294 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16295 THUMB_VARIANT, do_##ae, do_##te }
16296 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16297 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16298 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16299 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16300 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16301 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16302 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16303 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16305 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16306 appear in the condition table. */
16307 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16308 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16309 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16311 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16312 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16313 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16314 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16315 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16316 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16317 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16318 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16319 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16320 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16321 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16322 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16323 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16324 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16325 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16326 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16327 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16328 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16329 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16330 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16332 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16333 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16334 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16335 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16337 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16338 field is still 0xE. Many of the Thumb variants can be executed
16339 conditionally, so this is checked separately. */
16340 #define TUE(mnem, op, top, nops, ops, ae, te) \
16341 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16342 THUMB_VARIANT, do_##ae, do_##te }
16344 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16345 condition code field. */
16346 #define TUF(mnem, op, top, nops, ops, ae, te) \
16347 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16348 THUMB_VARIANT, do_##ae, do_##te }
16350 /* ARM-only variants of all the above. */
16351 #define CE(mnem, op, nops, ops, ae) \
16352 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16354 #define C3(mnem, op, nops, ops, ae) \
16355 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16357 /* Legacy mnemonics that always have conditional infix after the third
16359 #define CL(mnem, op, nops, ops, ae) \
16360 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16361 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16363 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16364 #define cCE(mnem, op, nops, ops, ae) \
16365 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16367 /* Legacy coprocessor instructions where conditional infix and conditional
16368 suffix are ambiguous. For consistency this includes all FPA instructions,
16369 not just the potentially ambiguous ones. */
16370 #define cCL(mnem, op, nops, ops, ae) \
16371 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16372 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16374 /* Coprocessor, takes either a suffix or a position-3 infix
16375 (for an FPA corner case). */
16376 #define C3E(mnem, op, nops, ops, ae) \
16377 { mnem, OPS##nops ops, OT_csuf_or_in3, \
16378 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16380 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
16381 { m1 #m2 m3, OPS##nops ops, \
16382 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16383 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16385 #define CM(m1, m2, op, nops, ops, ae) \
16386 xCM_ (m1, , m2, op, nops, ops, ae), \
16387 xCM_ (m1, eq, m2, op, nops, ops, ae), \
16388 xCM_ (m1, ne, m2, op, nops, ops, ae), \
16389 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16390 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16391 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16392 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16393 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16394 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16395 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16396 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16397 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16398 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16399 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16400 xCM_ (m1, ge, m2, op, nops, ops, ae), \
16401 xCM_ (m1, lt, m2, op, nops, ops, ae), \
16402 xCM_ (m1, gt, m2, op, nops, ops, ae), \
16403 xCM_ (m1, le, m2, op, nops, ops, ae), \
16404 xCM_ (m1, al, m2, op, nops, ops, ae)
16406 #define UE(mnem, op, nops, ops, ae) \
16407 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16409 #define UF(mnem, op, nops, ops, ae) \
16410 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16412 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
16413 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
16414 use the same encoding function for each. */
16415 #define NUF(mnem, op, nops, ops, enc) \
16416 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
16417 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16419 /* Neon data processing, version which indirects through neon_enc_tab for
16420 the various overloaded versions of opcodes. */
16421 #define nUF(mnem, op, nops, ops, enc) \
16422 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
16423 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16425 /* Neon insn with conditional suffix for the ARM version, non-overloaded
16427 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
16428 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
16429 THUMB_VARIANT, do_##enc, do_##enc }
16431 #define NCE(mnem, op, nops, ops, enc) \
16432 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16434 #define NCEF(mnem, op, nops, ops, enc) \
16435 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16437 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
16438 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
16439 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
16440 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16442 #define nCE(mnem, op, nops, ops, enc) \
16443 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16445 #define nCEF(mnem, op, nops, ops, enc) \
16446 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16450 static const struct asm_opcode insns
[] =
16452 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
16453 #define THUMB_VARIANT &arm_ext_v4t
16454 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16455 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16456 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16457 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16458 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16459 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16460 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16461 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16462 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16463 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16464 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16465 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16466 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16467 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16468 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16469 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16471 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
16472 for setting PSR flag bits. They are obsolete in V6 and do not
16473 have Thumb equivalents. */
16474 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16475 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16476 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
16477 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16478 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16479 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
16480 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16481 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16482 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
16484 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16485 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16486 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16487 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16489 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16490 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16491 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
16493 OP_ADDRGLDR
),ldst
, t_ldst
),
16494 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16496 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16497 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16498 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16499 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16500 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16501 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16503 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16504 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16505 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
16506 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
16509 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
16510 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
16511 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
16513 /* Thumb-compatibility pseudo ops. */
16514 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16515 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16516 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16517 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16518 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16519 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16520 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16521 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16522 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
16523 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
16524 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
16525 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
16527 /* These may simplify to neg. */
16528 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16529 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16531 #undef THUMB_VARIANT
16532 #define THUMB_VARIANT & arm_ext_v6
16534 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
16536 /* V1 instructions with no Thumb analogue prior to V6T2. */
16537 #undef THUMB_VARIANT
16538 #define THUMB_VARIANT & arm_ext_v6t2
16540 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16541 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16542 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
16544 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16545 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16546 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
16547 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16549 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16550 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16552 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16553 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16555 /* V1 instructions with no Thumb analogue at all. */
16556 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
16557 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
16559 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16560 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16561 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16562 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16563 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16564 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16565 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16566 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16569 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
16570 #undef THUMB_VARIANT
16571 #define THUMB_VARIANT & arm_ext_v4t
16573 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16574 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16576 #undef THUMB_VARIANT
16577 #define THUMB_VARIANT & arm_ext_v6t2
16579 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16580 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
16582 /* Generic coprocessor instructions. */
16583 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16584 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16585 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16586 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16587 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16588 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16589 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16592 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
16594 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16595 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16598 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
16599 #undef THUMB_VARIANT
16600 #define THUMB_VARIANT & arm_ext_msr
16602 TCE("mrs", 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
16603 TCE("msr", 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
16606 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
16607 #undef THUMB_VARIANT
16608 #define THUMB_VARIANT & arm_ext_v6t2
16610 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16611 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16612 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16613 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16614 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16615 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16616 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16617 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16620 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
16621 #undef THUMB_VARIANT
16622 #define THUMB_VARIANT & arm_ext_v4t
16624 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16625 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16626 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16627 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16628 tCM("ld","sh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16629 tCM("ld","sb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16632 #define ARM_VARIANT & arm_ext_v4t_5
16634 /* ARM Architecture 4T. */
16635 /* Note: bx (and blx) are required on V5, even if the processor does
16636 not support Thumb. */
16637 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
16640 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
16641 #undef THUMB_VARIANT
16642 #define THUMB_VARIANT & arm_ext_v5t
16644 /* Note: blx has 2 variants; the .value coded here is for
16645 BLX(2). Only this variant has conditional execution. */
16646 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
16647 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
16649 #undef THUMB_VARIANT
16650 #define THUMB_VARIANT & arm_ext_v6t2
16652 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
16653 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16654 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16655 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16656 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16657 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16658 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16659 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16662 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
16663 #undef THUMB_VARIANT
16664 #define THUMB_VARIANT &arm_ext_v5exp
16666 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16667 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16668 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16669 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16671 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16672 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16674 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16675 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16676 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16677 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16679 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16680 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16681 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16682 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16684 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16685 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16687 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16688 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16689 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16690 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16693 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
16694 #undef THUMB_VARIANT
16695 #define THUMB_VARIANT &arm_ext_v6t2
16697 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
16698 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
16700 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
16701 ADDRGLDRS
), ldrd
, t_ldstd
),
16703 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16704 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16707 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
16709 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
16712 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
16713 #undef THUMB_VARIANT
16714 #define THUMB_VARIANT & arm_ext_v6
16716 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16717 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16718 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16719 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16720 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16721 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16722 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16723 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16724 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16725 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
16727 #undef THUMB_VARIANT
16728 #define THUMB_VARIANT & arm_ext_v6t2
16730 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
16731 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
16733 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16734 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16736 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
16737 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
16739 /* ARM V6 not included in V7M. */
16740 #undef THUMB_VARIANT
16741 #define THUMB_VARIANT & arm_ext_v6_notm
16742 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16743 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
16744 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
16745 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16746 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16747 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
16748 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
16749 TUF("rfeed", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16750 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
16751 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
16752 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
16753 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
16755 /* ARM V6 not included in V7M (eg. integer SIMD). */
16756 #undef THUMB_VARIANT
16757 #define THUMB_VARIANT & arm_ext_v6_dsp
16758 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
16759 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
16760 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
16761 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16762 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16763 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16764 /* Old name for QASX. */
16765 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16766 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16767 /* Old name for QSAX. */
16768 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16769 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16770 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16771 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16772 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16773 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16774 /* Old name for SASX. */
16775 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16776 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16777 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16778 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16779 /* Old name for SHASX. */
16780 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16781 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16782 /* Old name for SHSAX. */
16783 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16784 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16785 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16786 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16787 /* Old name for SSAX. */
16788 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16789 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16790 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16791 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16792 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16793 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16794 /* Old name for UASX. */
16795 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16796 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16797 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16798 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16799 /* Old name for UHASX. */
16800 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16801 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16802 /* Old name for UHSAX. */
16803 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16804 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16805 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16806 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16807 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16808 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16809 /* Old name for UQASX. */
16810 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16811 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16812 /* Old name for UQSAX. */
16813 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16814 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16815 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16816 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16817 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16818 /* Old name for USAX. */
16819 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16820 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16821 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16822 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16823 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16824 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16825 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16826 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16827 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16828 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16829 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16830 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16831 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16832 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16833 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16834 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16835 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16836 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16837 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16838 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16839 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16840 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16841 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16842 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16843 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16844 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16845 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16846 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16847 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16848 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
16849 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
16850 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16851 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16852 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
16855 #define ARM_VARIANT & arm_ext_v6k
16856 #undef THUMB_VARIANT
16857 #define THUMB_VARIANT & arm_ext_v6k
16859 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
16860 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
16861 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
16862 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
16864 #undef THUMB_VARIANT
16865 #define THUMB_VARIANT & arm_ext_v6_notm
16866 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
16868 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
16869 RRnpcb
), strexd
, t_strexd
),
16871 #undef THUMB_VARIANT
16872 #define THUMB_VARIANT & arm_ext_v6t2
16873 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
16875 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
16877 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
16879 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
16881 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
16884 #define ARM_VARIANT & arm_ext_v6z
16886 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
16889 #define ARM_VARIANT & arm_ext_v6t2
16891 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
16892 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
16893 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
16894 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
16896 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16897 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
16898 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
16899 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
16901 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
16902 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
16903 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
16904 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
16906 /* Thumb-only instructions. */
16908 #define ARM_VARIANT NULL
16909 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
16910 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
16912 /* ARM does not really have an IT instruction, so always allow it.
16913 The opcode is copied from Thumb in order to allow warnings in
16914 -mimplicit-it=[never | arm] modes. */
16916 #define ARM_VARIANT & arm_ext_v1
16918 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
16919 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
16920 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
16921 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
16922 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
16923 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
16924 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
16925 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
16926 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
16927 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
16928 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
16929 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
16930 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
16931 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
16932 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
16933 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
16934 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
16935 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
16937 /* Thumb2 only instructions. */
16939 #define ARM_VARIANT NULL
16941 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
16942 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
16943 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
16944 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
16945 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
16946 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
16948 /* Thumb-2 hardware division instructions (R and M profiles only). */
16949 #undef THUMB_VARIANT
16950 #define THUMB_VARIANT & arm_ext_div
16952 TCE("sdiv", 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
16953 TCE("udiv", 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
16955 /* ARM V6M/V7 instructions. */
16957 #define ARM_VARIANT & arm_ext_barrier
16958 #undef THUMB_VARIANT
16959 #define THUMB_VARIANT & arm_ext_barrier
16961 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
16962 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
16963 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
16965 /* ARM V7 instructions. */
16967 #define ARM_VARIANT & arm_ext_v7
16968 #undef THUMB_VARIANT
16969 #define THUMB_VARIANT & arm_ext_v7
16971 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
16972 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
16975 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
16977 cCE("wfs", e200110
, 1, (RR
), rd
),
16978 cCE("rfs", e300110
, 1, (RR
), rd
),
16979 cCE("wfc", e400110
, 1, (RR
), rd
),
16980 cCE("rfc", e500110
, 1, (RR
), rd
),
16982 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16983 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16984 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16985 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16987 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16988 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16989 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16990 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16992 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
16993 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
16994 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
16995 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
16996 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
16997 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
16998 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
16999 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
17000 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
17001 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
17002 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
17003 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
17005 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
17006 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
17007 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
17008 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
17009 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
17010 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
17011 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
17012 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
17013 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
17014 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
17015 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
17016 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
17018 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
17019 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
17020 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
17021 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
17022 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
17023 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
17024 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
17025 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
17026 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
17027 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
17028 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
17029 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
17031 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
17032 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
17033 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
17034 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
17035 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
17036 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
17037 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
17038 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
17039 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
17040 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
17041 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
17042 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
17044 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
17045 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
17046 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
17047 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
17048 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
17049 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
17050 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
17051 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
17052 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
17053 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
17054 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
17055 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
17057 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
17058 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
17059 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
17060 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
17061 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
17062 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
17063 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
17064 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
17065 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
17066 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
17067 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
17068 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
17070 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
17071 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
17072 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
17073 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
17074 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
17075 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
17076 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
17077 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
17078 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
17079 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
17080 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
17081 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
17083 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
17084 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
17085 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
17086 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
17087 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
17088 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
17089 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
17090 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
17091 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
17092 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
17093 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
17094 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
17096 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
17097 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
17098 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
17099 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
17100 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
17101 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
17102 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
17103 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
17104 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
17105 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
17106 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
17107 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
17109 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
17110 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
17111 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
17112 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
17113 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
17114 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
17115 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
17116 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
17117 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
17118 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
17119 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
17120 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
17122 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
17123 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
17124 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
17125 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
17126 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
17127 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
17128 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
17129 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
17130 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
17131 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
17132 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
17133 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
17135 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
17136 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
17137 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
17138 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
17139 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
17140 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
17141 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
17142 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
17143 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
17144 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
17145 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
17146 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
17148 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
17149 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
17150 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
17151 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
17152 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
17153 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
17154 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
17155 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
17156 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
17157 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
17158 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
17159 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
17161 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
17162 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
17163 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
17164 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
17165 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
17166 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
17167 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
17168 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
17169 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
17170 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
17171 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
17172 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
17174 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
17175 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
17176 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
17177 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
17178 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
17179 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
17180 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
17181 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
17182 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
17183 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
17184 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
17185 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
17187 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
17188 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
17189 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
17190 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
17191 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
17192 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
17193 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
17194 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
17195 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
17196 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
17197 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
17198 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
17200 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17201 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17202 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17203 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17204 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17205 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17206 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17207 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17208 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17209 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17210 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17211 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17213 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17214 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17215 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17216 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17217 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17218 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17219 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17220 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17221 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17222 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17223 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17224 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17226 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17227 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17228 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17229 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17230 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17231 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17232 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17233 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17234 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17235 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17236 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17237 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17239 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17240 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17241 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17242 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17243 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17244 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17245 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17246 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17247 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17248 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17249 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17250 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17252 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17253 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17254 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17255 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17256 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17257 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17258 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17259 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17260 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17261 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17262 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17263 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17265 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17266 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17267 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17268 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17269 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17270 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17271 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17272 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17273 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17274 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17275 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17276 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17278 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17279 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17280 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17281 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17282 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17283 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17284 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17285 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17286 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17287 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17288 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17289 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17291 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17292 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17293 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17294 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17295 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17296 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17297 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17298 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17299 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17300 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17301 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17302 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17304 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17305 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17306 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17307 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17308 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17309 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17310 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17311 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17312 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17313 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17314 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17315 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17317 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17318 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17319 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17320 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17321 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17322 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17323 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17324 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17325 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17326 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17327 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17328 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17330 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17331 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17332 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17333 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17334 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17335 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17336 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17337 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17338 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17339 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17340 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17341 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17343 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17344 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17345 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17346 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17347 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17348 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17349 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17350 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17351 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17352 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17353 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17354 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17356 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17357 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17358 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17359 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17360 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17361 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17362 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17363 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17364 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17365 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17366 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17367 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17369 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17370 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17371 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17372 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17374 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
17375 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
17376 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
17377 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
17378 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
17379 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
17380 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
17381 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
17382 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
17383 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
17384 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
17385 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
17387 /* The implementation of the FIX instruction is broken on some
17388 assemblers, in that it accepts a precision specifier as well as a
17389 rounding specifier, despite the fact that this is meaningless.
17390 To be more compatible, we accept it as well, though of course it
17391 does not set any bits. */
17392 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
17393 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
17394 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
17395 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
17396 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
17397 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
17398 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
17399 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
17400 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
17401 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
17402 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
17403 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
17404 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
17406 /* Instructions that were new with the real FPA, call them V2. */
17408 #define ARM_VARIANT & fpu_fpa_ext_v2
17410 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17411 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17412 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17413 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17414 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17415 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17418 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
17420 /* Moves and type conversions. */
17421 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17422 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
17423 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
17424 cCE("fmstat", ef1fa10
, 0, (), noargs
),
17425 cCE("vmrs", ef10a10
, 2, (APSR_RR
, RVC
), vmrs
),
17426 cCE("vmsr", ee10a10
, 2, (RVC
, RR
), vmsr
),
17427 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17428 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17429 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17430 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17431 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17432 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17433 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
17434 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
17436 /* Memory operations. */
17437 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17438 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17439 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17440 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17441 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17442 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17443 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17444 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17445 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17446 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17447 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17448 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17449 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17450 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17451 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17452 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17453 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17454 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17456 /* Monadic operations. */
17457 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17458 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17459 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17461 /* Dyadic operations. */
17462 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17463 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17464 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17465 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17466 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17467 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17468 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17469 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17470 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17473 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17474 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
17475 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17476 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
17478 /* Double precision load/store are still present on single precision
17479 implementations. */
17480 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17481 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17482 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17483 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17484 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17485 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17486 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17487 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17488 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17489 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17492 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
17494 /* Moves and type conversions. */
17495 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17496 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17497 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17498 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17499 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17500 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17501 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17502 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17503 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17504 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17505 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17506 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17507 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17509 /* Monadic operations. */
17510 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17511 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17512 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17514 /* Dyadic operations. */
17515 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17516 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17517 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17518 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17519 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17520 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17521 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17522 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17523 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17526 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17527 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
17528 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17529 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
17532 #define ARM_VARIANT & fpu_vfp_ext_v2
17534 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
17535 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
17536 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
17537 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
17539 /* Instructions which may belong to either the Neon or VFP instruction sets.
17540 Individual encoder functions perform additional architecture checks. */
17542 #define ARM_VARIANT & fpu_vfp_ext_v1xd
17543 #undef THUMB_VARIANT
17544 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
17546 /* These mnemonics are unique to VFP. */
17547 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
17548 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
17549 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17550 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17551 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17552 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17553 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17554 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
17555 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
17556 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
17558 /* Mnemonics shared by Neon and VFP. */
17559 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
17560 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17561 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17563 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17564 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17566 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17567 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17569 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17570 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17571 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17572 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17573 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17574 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17575 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17576 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17578 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
17579 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
17580 nCEF(vcvtb
, _vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
17581 nCEF(vcvtt
, _vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
17584 /* NOTE: All VMOV encoding is special-cased! */
17585 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
17586 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
17588 #undef THUMB_VARIANT
17589 #define THUMB_VARIANT & fpu_neon_ext_v1
17591 #define ARM_VARIANT & fpu_neon_ext_v1
17593 /* Data processing with three registers of the same length. */
17594 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
17595 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
17596 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
17597 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17598 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17599 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17600 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17601 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17602 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17603 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
17604 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17605 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17606 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17607 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17608 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17609 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17610 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17611 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17612 /* If not immediate, fall back to neon_dyadic_i64_su.
17613 shl_imm should accept I8 I16 I32 I64,
17614 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
17615 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
17616 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
17617 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
17618 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
17619 /* Logic ops, types optional & ignored. */
17620 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17621 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17622 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17623 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17624 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17625 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17626 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17627 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17628 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
17629 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
17630 /* Bitfield ops, untyped. */
17631 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17632 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17633 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17634 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17635 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17636 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17637 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
17638 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17639 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17640 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17641 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17642 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17643 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17644 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
17645 back to neon_dyadic_if_su. */
17646 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17647 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17648 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17649 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17650 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17651 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17652 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17653 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17654 /* Comparison. Type I8 I16 I32 F32. */
17655 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
17656 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
17657 /* As above, D registers only. */
17658 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17659 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17660 /* Int and float variants, signedness unimportant. */
17661 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17662 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17663 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
17664 /* Add/sub take types I8 I16 I32 I64 F32. */
17665 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17666 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17667 /* vtst takes sizes 8, 16, 32. */
17668 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
17669 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
17670 /* VMUL takes I8 I16 I32 F32 P8. */
17671 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
17672 /* VQD{R}MULH takes S16 S32. */
17673 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17674 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17675 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17676 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17677 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17678 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17679 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17680 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17681 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17682 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17683 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17684 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17685 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17686 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17687 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17688 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17690 /* Two address, int/float. Types S8 S16 S32 F32. */
17691 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17692 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17694 /* Data processing with two registers and a shift amount. */
17695 /* Right shifts, and variants with rounding.
17696 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
17697 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17698 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17699 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17700 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17701 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17702 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17703 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17704 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17705 /* Shift and insert. Sizes accepted 8 16 32 64. */
17706 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
17707 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
17708 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
17709 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
17710 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
17711 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
17712 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
17713 /* Right shift immediate, saturating & narrowing, with rounding variants.
17714 Types accepted S16 S32 S64 U16 U32 U64. */
17715 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17716 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17717 /* As above, unsigned. Types accepted S16 S32 S64. */
17718 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17719 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17720 /* Right shift narrowing. Types accepted I16 I32 I64. */
17721 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17722 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17723 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
17724 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
17725 /* CVT with optional immediate for fixed-point variant. */
17726 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
17728 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
17729 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
17731 /* Data processing, three registers of different lengths. */
17732 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
17733 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
17734 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17735 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17736 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17737 /* If not scalar, fall back to neon_dyadic_long.
17738 Vector types as above, scalar types S16 S32 U16 U32. */
17739 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17740 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17741 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
17742 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17743 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17744 /* Dyadic, narrowing insns. Types I16 I32 I64. */
17745 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17746 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17747 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17748 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17749 /* Saturating doubling multiplies. Types S16 S32. */
17750 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17751 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17752 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17753 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
17754 S16 S32 U16 U32. */
17755 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
17757 /* Extract. Size 8. */
17758 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
17759 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
17761 /* Two registers, miscellaneous. */
17762 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
17763 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
17764 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
17765 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
17766 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
17767 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
17768 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
17769 /* Vector replicate. Sizes 8 16 32. */
17770 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
17771 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
17772 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
17773 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
17774 /* VMOVN. Types I16 I32 I64. */
17775 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
17776 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
17777 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
17778 /* VQMOVUN. Types S16 S32 S64. */
17779 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
17780 /* VZIP / VUZP. Sizes 8 16 32. */
17781 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17782 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17783 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17784 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17785 /* VQABS / VQNEG. Types S8 S16 S32. */
17786 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17787 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17788 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17789 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17790 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
17791 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17792 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
17793 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17794 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
17795 /* Reciprocal estimates. Types U32 F32. */
17796 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17797 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
17798 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17799 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
17800 /* VCLS. Types S8 S16 S32. */
17801 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
17802 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
17803 /* VCLZ. Types I8 I16 I32. */
17804 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
17805 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
17806 /* VCNT. Size 8. */
17807 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
17808 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
17809 /* Two address, untyped. */
17810 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
17811 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
17812 /* VTRN. Sizes 8 16 32. */
17813 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
17814 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
17816 /* Table lookup. Size 8. */
17817 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17818 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17820 #undef THUMB_VARIANT
17821 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
17823 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
17825 /* Neon element/structure load/store. */
17826 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17827 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17828 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17829 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17830 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17831 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17832 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17833 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17835 #undef THUMB_VARIANT
17836 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
17838 #define ARM_VARIANT &fpu_vfp_ext_v3xd
17839 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
17840 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17841 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17842 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17843 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17844 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17845 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17846 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17847 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17849 #undef THUMB_VARIANT
17850 #define THUMB_VARIANT & fpu_vfp_ext_v3
17852 #define ARM_VARIANT & fpu_vfp_ext_v3
17854 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
17855 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17856 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17857 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17858 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17859 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17860 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17861 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17862 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17865 #define ARM_VARIANT &fpu_vfp_ext_fma
17866 #undef THUMB_VARIANT
17867 #define THUMB_VARIANT &fpu_vfp_ext_fma
17868 /* Mnemonics shared by Neon and VFP. These are included in the
17869 VFP FMA variant; NEON and VFP FMA always includes the NEON
17870 FMA instructions. */
17871 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
17872 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
17873 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
17874 the v form should always be used. */
17875 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17876 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17877 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17878 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17879 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17880 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17882 #undef THUMB_VARIANT
17884 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
17886 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17887 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17888 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17889 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17890 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17891 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17892 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
17893 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
17896 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
17898 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
17899 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
17900 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
17901 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
17902 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
17903 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
17904 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
17905 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
17906 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
17907 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17908 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17909 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17910 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17911 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17912 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17913 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17914 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17915 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17916 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
17917 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
17918 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17919 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17920 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17921 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17922 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17923 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17924 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
17925 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
17926 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
17927 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
17928 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
17929 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
17930 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
17931 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
17932 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17933 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17934 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17935 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17936 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17937 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17938 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17939 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17940 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17941 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17942 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17943 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17944 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
17945 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17946 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17947 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17948 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17949 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17950 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17951 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17952 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17953 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17954 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17955 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17956 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17957 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17958 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17959 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17960 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17961 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17962 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17963 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17964 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17965 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17966 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
17967 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
17968 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17969 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17970 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17971 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17972 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17973 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17974 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17975 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17976 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17977 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17978 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17979 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17980 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17981 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17982 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17983 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17984 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17985 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17986 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
17987 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17988 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17989 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17990 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17991 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17992 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17993 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17994 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17995 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17996 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17997 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17998 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17999 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18000 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18001 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18002 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18003 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18004 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18005 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18006 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18007 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18008 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
18009 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18010 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18011 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18012 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18013 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18014 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18015 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18016 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18017 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18018 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18019 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18020 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18021 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18022 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18023 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18024 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18025 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18026 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18027 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18028 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18029 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18030 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18031 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18032 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18033 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18034 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18035 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18036 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18037 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18038 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18039 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18040 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18041 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18042 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18043 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18044 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18045 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18046 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18047 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18048 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18049 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18050 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18051 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18052 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18053 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18054 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18055 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18056 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18057 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18058 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18059 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
18062 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18064 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
18065 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
18066 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
18067 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18068 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18069 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18070 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18071 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18072 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18073 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18074 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18075 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18076 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18077 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18078 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18079 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18080 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18081 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18082 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18083 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18084 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
18085 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18086 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18087 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18088 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18089 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18090 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18091 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18092 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18093 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18094 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18095 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18096 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18097 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18098 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18099 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18100 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18101 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18102 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18103 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18104 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18105 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18106 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18107 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18108 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18109 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18110 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18111 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18112 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18113 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18114 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18115 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18116 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18117 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18118 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18119 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18120 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18123 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18125 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18126 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18127 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18128 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18129 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18130 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18131 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18132 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18133 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
18134 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
18135 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
18136 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
18137 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
18138 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
18139 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
18140 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
18141 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
18142 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
18143 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
18144 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
18145 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
18146 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
18147 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
18148 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
18149 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
18150 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
18151 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
18152 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
18153 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
18154 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
18155 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
18156 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
18157 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
18158 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
18159 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
18160 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
18161 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
18162 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
18163 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
18164 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
18165 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
18166 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
18167 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
18168 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
18169 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
18170 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
18171 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
18172 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
18173 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
18174 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
18175 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
18176 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
18177 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
18178 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
18179 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18180 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18181 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18182 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18183 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18184 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18185 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
18186 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
18187 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
18188 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
18189 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18190 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18191 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18192 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18193 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18194 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18195 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18196 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18197 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18198 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18199 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18200 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18203 #undef THUMB_VARIANT
18230 /* MD interface: bits in the object file. */
18232 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18233 for use in the a.out file, and stores them in the array pointed to by buf.
18234 This knows about the endian-ness of the target machine and does
18235 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18236 2 (short) and 4 (long) Floating numbers are put out as a series of
18237 LITTLENUMS (shorts, here at least). */
18240 md_number_to_chars (char * buf
, valueT val
, int n
)
18242 if (target_big_endian
)
18243 number_to_chars_bigendian (buf
, val
, n
);
18245 number_to_chars_littleendian (buf
, val
, n
);
18249 md_chars_to_number (char * buf
, int n
)
18252 unsigned char * where
= (unsigned char *) buf
;
18254 if (target_big_endian
)
18259 result
|= (*where
++ & 255);
18267 result
|= (where
[n
] & 255);
18274 /* MD interface: Sections. */
18276 /* Estimate the size of a frag before relaxing. Assume everything fits in
18280 md_estimate_size_before_relax (fragS
* fragp
,
18281 segT segtype ATTRIBUTE_UNUSED
)
18287 /* Convert a machine dependent frag. */
18290 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
18292 unsigned long insn
;
18293 unsigned long old_op
;
18301 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18303 old_op
= bfd_get_16(abfd
, buf
);
18304 if (fragp
->fr_symbol
)
18306 exp
.X_op
= O_symbol
;
18307 exp
.X_add_symbol
= fragp
->fr_symbol
;
18311 exp
.X_op
= O_constant
;
18313 exp
.X_add_number
= fragp
->fr_offset
;
18314 opcode
= fragp
->fr_subtype
;
18317 case T_MNEM_ldr_pc
:
18318 case T_MNEM_ldr_pc2
:
18319 case T_MNEM_ldr_sp
:
18320 case T_MNEM_str_sp
:
18327 if (fragp
->fr_var
== 4)
18329 insn
= THUMB_OP32 (opcode
);
18330 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
18332 insn
|= (old_op
& 0x700) << 4;
18336 insn
|= (old_op
& 7) << 12;
18337 insn
|= (old_op
& 0x38) << 13;
18339 insn
|= 0x00000c00;
18340 put_thumb32_insn (buf
, insn
);
18341 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
18345 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
18347 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
18350 if (fragp
->fr_var
== 4)
18352 insn
= THUMB_OP32 (opcode
);
18353 insn
|= (old_op
& 0xf0) << 4;
18354 put_thumb32_insn (buf
, insn
);
18355 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
18359 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18360 exp
.X_add_number
-= 4;
18368 if (fragp
->fr_var
== 4)
18370 int r0off
= (opcode
== T_MNEM_mov
18371 || opcode
== T_MNEM_movs
) ? 0 : 8;
18372 insn
= THUMB_OP32 (opcode
);
18373 insn
= (insn
& 0xe1ffffff) | 0x10000000;
18374 insn
|= (old_op
& 0x700) << r0off
;
18375 put_thumb32_insn (buf
, insn
);
18376 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18380 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
18385 if (fragp
->fr_var
== 4)
18387 insn
= THUMB_OP32(opcode
);
18388 put_thumb32_insn (buf
, insn
);
18389 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
18392 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
18396 if (fragp
->fr_var
== 4)
18398 insn
= THUMB_OP32(opcode
);
18399 insn
|= (old_op
& 0xf00) << 14;
18400 put_thumb32_insn (buf
, insn
);
18401 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
18404 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
18407 case T_MNEM_add_sp
:
18408 case T_MNEM_add_pc
:
18409 case T_MNEM_inc_sp
:
18410 case T_MNEM_dec_sp
:
18411 if (fragp
->fr_var
== 4)
18413 /* ??? Choose between add and addw. */
18414 insn
= THUMB_OP32 (opcode
);
18415 insn
|= (old_op
& 0xf0) << 4;
18416 put_thumb32_insn (buf
, insn
);
18417 if (opcode
== T_MNEM_add_pc
)
18418 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
18420 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18423 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18431 if (fragp
->fr_var
== 4)
18433 insn
= THUMB_OP32 (opcode
);
18434 insn
|= (old_op
& 0xf0) << 4;
18435 insn
|= (old_op
& 0xf) << 16;
18436 put_thumb32_insn (buf
, insn
);
18437 if (insn
& (1 << 20))
18438 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18440 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18443 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18449 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
18450 (enum bfd_reloc_code_real
) reloc_type
);
18451 fixp
->fx_file
= fragp
->fr_file
;
18452 fixp
->fx_line
= fragp
->fr_line
;
18453 fragp
->fr_fix
+= fragp
->fr_var
;
18456 /* Return the size of a relaxable immediate operand instruction.
18457 SHIFT and SIZE specify the form of the allowable immediate. */
18459 relax_immediate (fragS
*fragp
, int size
, int shift
)
18465 /* ??? Should be able to do better than this. */
18466 if (fragp
->fr_symbol
)
18469 low
= (1 << shift
) - 1;
18470 mask
= (1 << (shift
+ size
)) - (1 << shift
);
18471 offset
= fragp
->fr_offset
;
18472 /* Force misaligned offsets to 32-bit variant. */
18475 if (offset
& ~mask
)
18480 /* Get the address of a symbol during relaxation. */
18482 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
18488 sym
= fragp
->fr_symbol
;
18489 sym_frag
= symbol_get_frag (sym
);
18490 know (S_GET_SEGMENT (sym
) != absolute_section
18491 || sym_frag
== &zero_address_frag
);
18492 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
18494 /* If frag has yet to be reached on this pass, assume it will
18495 move by STRETCH just as we did. If this is not so, it will
18496 be because some frag between grows, and that will force
18500 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
18504 /* Adjust stretch for any alignment frag. Note that if have
18505 been expanding the earlier code, the symbol may be
18506 defined in what appears to be an earlier frag. FIXME:
18507 This doesn't handle the fr_subtype field, which specifies
18508 a maximum number of bytes to skip when doing an
18510 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
18512 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
18515 stretch
= - ((- stretch
)
18516 & ~ ((1 << (int) f
->fr_offset
) - 1));
18518 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
18530 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
18533 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
18538 /* Assume worst case for symbols not known to be in the same section. */
18539 if (fragp
->fr_symbol
== NULL
18540 || !S_IS_DEFINED (fragp
->fr_symbol
)
18541 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
18542 || S_IS_WEAK (fragp
->fr_symbol
))
18545 val
= relaxed_symbol_addr (fragp
, stretch
);
18546 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18547 addr
= (addr
+ 4) & ~3;
18548 /* Force misaligned targets to 32-bit variant. */
18552 if (val
< 0 || val
> 1020)
18557 /* Return the size of a relaxable add/sub immediate instruction. */
18559 relax_addsub (fragS
*fragp
, asection
*sec
)
18564 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18565 op
= bfd_get_16(sec
->owner
, buf
);
18566 if ((op
& 0xf) == ((op
>> 4) & 0xf))
18567 return relax_immediate (fragp
, 8, 0);
18569 return relax_immediate (fragp
, 3, 0);
18573 /* Return the size of a relaxable branch instruction. BITS is the
18574 size of the offset field in the narrow instruction. */
18577 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
18583 /* Assume worst case for symbols not known to be in the same section. */
18584 if (!S_IS_DEFINED (fragp
->fr_symbol
)
18585 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
18586 || S_IS_WEAK (fragp
->fr_symbol
))
18590 if (S_IS_DEFINED (fragp
->fr_symbol
)
18591 && ARM_IS_FUNC (fragp
->fr_symbol
))
18595 val
= relaxed_symbol_addr (fragp
, stretch
);
18596 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18599 /* Offset is a signed value *2 */
18601 if (val
>= limit
|| val
< -limit
)
18607 /* Relax a machine dependent frag. This returns the amount by which
18608 the current size of the frag should change. */
18611 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18616 oldsize
= fragp
->fr_var
;
18617 switch (fragp
->fr_subtype
)
18619 case T_MNEM_ldr_pc2
:
18620 newsize
= relax_adr (fragp
, sec
, stretch
);
18622 case T_MNEM_ldr_pc
:
18623 case T_MNEM_ldr_sp
:
18624 case T_MNEM_str_sp
:
18625 newsize
= relax_immediate (fragp
, 8, 2);
18629 newsize
= relax_immediate (fragp
, 5, 2);
18633 newsize
= relax_immediate (fragp
, 5, 1);
18637 newsize
= relax_immediate (fragp
, 5, 0);
18640 newsize
= relax_adr (fragp
, sec
, stretch
);
18646 newsize
= relax_immediate (fragp
, 8, 0);
18649 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
18652 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
18654 case T_MNEM_add_sp
:
18655 case T_MNEM_add_pc
:
18656 newsize
= relax_immediate (fragp
, 8, 2);
18658 case T_MNEM_inc_sp
:
18659 case T_MNEM_dec_sp
:
18660 newsize
= relax_immediate (fragp
, 7, 2);
18666 newsize
= relax_addsub (fragp
, sec
);
18672 fragp
->fr_var
= newsize
;
18673 /* Freeze wide instructions that are at or before the same location as
18674 in the previous pass. This avoids infinite loops.
18675 Don't freeze them unconditionally because targets may be artificially
18676 misaligned by the expansion of preceding frags. */
18677 if (stretch
<= 0 && newsize
> 2)
18679 md_convert_frag (sec
->owner
, sec
, fragp
);
18683 return newsize
- oldsize
;
18686 /* Round up a section size to the appropriate boundary. */
18689 md_section_align (segT segment ATTRIBUTE_UNUSED
,
18692 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
18693 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
18695 /* For a.out, force the section size to be aligned. If we don't do
18696 this, BFD will align it for us, but it will not write out the
18697 final bytes of the section. This may be a bug in BFD, but it is
18698 easier to fix it here since that is how the other a.out targets
18702 align
= bfd_get_section_alignment (stdoutput
, segment
);
18703 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
18710 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
18711 of an rs_align_code fragment. */
18714 arm_handle_align (fragS
* fragP
)
18716 static char const arm_noop
[2][2][4] =
18719 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
18720 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
18723 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
18724 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
18727 static char const thumb_noop
[2][2][2] =
18730 {0xc0, 0x46}, /* LE */
18731 {0x46, 0xc0}, /* BE */
18734 {0x00, 0xbf}, /* LE */
18735 {0xbf, 0x00} /* BE */
18738 static char const wide_thumb_noop
[2][4] =
18739 { /* Wide Thumb-2 */
18740 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
18741 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
18744 unsigned bytes
, fix
, noop_size
;
18747 const char *narrow_noop
= NULL
;
18752 if (fragP
->fr_type
!= rs_align_code
)
18755 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
18756 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
18759 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18760 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
18762 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
18764 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
18766 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
18768 narrow_noop
= thumb_noop
[1][target_big_endian
];
18769 noop
= wide_thumb_noop
[target_big_endian
];
18772 noop
= thumb_noop
[0][target_big_endian
];
18780 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
18781 [target_big_endian
];
18788 fragP
->fr_var
= noop_size
;
18790 if (bytes
& (noop_size
- 1))
18792 fix
= bytes
& (noop_size
- 1);
18794 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
18796 memset (p
, 0, fix
);
18803 if (bytes
& noop_size
)
18805 /* Insert a narrow noop. */
18806 memcpy (p
, narrow_noop
, noop_size
);
18808 bytes
-= noop_size
;
18812 /* Use wide noops for the remainder */
18816 while (bytes
>= noop_size
)
18818 memcpy (p
, noop
, noop_size
);
18820 bytes
-= noop_size
;
18824 fragP
->fr_fix
+= fix
;
18827 /* Called from md_do_align. Used to create an alignment
18828 frag in a code section. */
18831 arm_frag_align_code (int n
, int max
)
18835 /* We assume that there will never be a requirement
18836 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
18837 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18842 _("alignments greater than %d bytes not supported in .text sections."),
18843 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
18844 as_fatal ("%s", err_msg
);
18847 p
= frag_var (rs_align_code
,
18848 MAX_MEM_FOR_RS_ALIGN_CODE
,
18850 (relax_substateT
) max
,
18857 /* Perform target specific initialisation of a frag.
18858 Note - despite the name this initialisation is not done when the frag
18859 is created, but only when its type is assigned. A frag can be created
18860 and used a long time before its type is set, so beware of assuming that
18861 this initialisationis performed first. */
18865 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
18867 /* Record whether this frag is in an ARM or a THUMB area. */
18868 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18871 #else /* OBJ_ELF is defined. */
18873 arm_init_frag (fragS
* fragP
, int max_chars
)
18875 /* If the current ARM vs THUMB mode has not already
18876 been recorded into this frag then do so now. */
18877 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
18879 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18881 /* Record a mapping symbol for alignment frags. We will delete this
18882 later if the alignment ends up empty. */
18883 switch (fragP
->fr_type
)
18886 case rs_align_test
:
18888 mapping_state_2 (MAP_DATA
, max_chars
);
18890 case rs_align_code
:
18891 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
18899 /* When we change sections we need to issue a new mapping symbol. */
18902 arm_elf_change_section (void)
18904 /* Link an unlinked unwind index table section to the .text section. */
18905 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
18906 && elf_linked_to_section (now_seg
) == NULL
)
18907 elf_linked_to_section (now_seg
) = text_section
;
18911 arm_elf_section_type (const char * str
, size_t len
)
18913 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
18914 return SHT_ARM_EXIDX
;
18919 /* Code to deal with unwinding tables. */
18921 static void add_unwind_adjustsp (offsetT
);
18923 /* Generate any deferred unwind frame offset. */
18926 flush_pending_unwind (void)
18930 offset
= unwind
.pending_offset
;
18931 unwind
.pending_offset
= 0;
18933 add_unwind_adjustsp (offset
);
18936 /* Add an opcode to this list for this function. Two-byte opcodes should
18937 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
18941 add_unwind_opcode (valueT op
, int length
)
18943 /* Add any deferred stack adjustment. */
18944 if (unwind
.pending_offset
)
18945 flush_pending_unwind ();
18947 unwind
.sp_restored
= 0;
18949 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
18951 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
18952 if (unwind
.opcodes
)
18953 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
18954 unwind
.opcode_alloc
);
18956 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
18961 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
18963 unwind
.opcode_count
++;
18967 /* Add unwind opcodes to adjust the stack pointer. */
18970 add_unwind_adjustsp (offsetT offset
)
18974 if (offset
> 0x200)
18976 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
18981 /* Long form: 0xb2, uleb128. */
18982 /* This might not fit in a word so add the individual bytes,
18983 remembering the list is built in reverse order. */
18984 o
= (valueT
) ((offset
- 0x204) >> 2);
18986 add_unwind_opcode (0, 1);
18988 /* Calculate the uleb128 encoding of the offset. */
18992 bytes
[n
] = o
& 0x7f;
18998 /* Add the insn. */
19000 add_unwind_opcode (bytes
[n
- 1], 1);
19001 add_unwind_opcode (0xb2, 1);
19003 else if (offset
> 0x100)
19005 /* Two short opcodes. */
19006 add_unwind_opcode (0x3f, 1);
19007 op
= (offset
- 0x104) >> 2;
19008 add_unwind_opcode (op
, 1);
19010 else if (offset
> 0)
19012 /* Short opcode. */
19013 op
= (offset
- 4) >> 2;
19014 add_unwind_opcode (op
, 1);
19016 else if (offset
< 0)
19019 while (offset
> 0x100)
19021 add_unwind_opcode (0x7f, 1);
19024 op
= ((offset
- 4) >> 2) | 0x40;
19025 add_unwind_opcode (op
, 1);
19029 /* Finish the list of unwind opcodes for this function. */
19031 finish_unwind_opcodes (void)
19035 if (unwind
.fp_used
)
19037 /* Adjust sp as necessary. */
19038 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
19039 flush_pending_unwind ();
19041 /* After restoring sp from the frame pointer. */
19042 op
= 0x90 | unwind
.fp_reg
;
19043 add_unwind_opcode (op
, 1);
19046 flush_pending_unwind ();
19050 /* Start an exception table entry. If idx is nonzero this is an index table
19054 start_unwind_section (const segT text_seg
, int idx
)
19056 const char * text_name
;
19057 const char * prefix
;
19058 const char * prefix_once
;
19059 const char * group_name
;
19063 size_t sec_name_len
;
19070 prefix
= ELF_STRING_ARM_unwind
;
19071 prefix_once
= ELF_STRING_ARM_unwind_once
;
19072 type
= SHT_ARM_EXIDX
;
19076 prefix
= ELF_STRING_ARM_unwind_info
;
19077 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
19078 type
= SHT_PROGBITS
;
19081 text_name
= segment_name (text_seg
);
19082 if (streq (text_name
, ".text"))
19085 if (strncmp (text_name
, ".gnu.linkonce.t.",
19086 strlen (".gnu.linkonce.t.")) == 0)
19088 prefix
= prefix_once
;
19089 text_name
+= strlen (".gnu.linkonce.t.");
19092 prefix_len
= strlen (prefix
);
19093 text_len
= strlen (text_name
);
19094 sec_name_len
= prefix_len
+ text_len
;
19095 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
19096 memcpy (sec_name
, prefix
, prefix_len
);
19097 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
19098 sec_name
[prefix_len
+ text_len
] = '\0';
19104 /* Handle COMDAT group. */
19105 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
19107 group_name
= elf_group_name (text_seg
);
19108 if (group_name
== NULL
)
19110 as_bad (_("Group section `%s' has no group signature"),
19111 segment_name (text_seg
));
19112 ignore_rest_of_line ();
19115 flags
|= SHF_GROUP
;
19119 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
19121 /* Set the section link for index tables. */
19123 elf_linked_to_section (now_seg
) = text_seg
;
19127 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19128 personality routine data. Returns zero, or the index table value for
19129 and inline entry. */
19132 create_unwind_entry (int have_data
)
19137 /* The current word of data. */
19139 /* The number of bytes left in this word. */
19142 finish_unwind_opcodes ();
19144 /* Remember the current text section. */
19145 unwind
.saved_seg
= now_seg
;
19146 unwind
.saved_subseg
= now_subseg
;
19148 start_unwind_section (now_seg
, 0);
19150 if (unwind
.personality_routine
== NULL
)
19152 if (unwind
.personality_index
== -2)
19155 as_bad (_("handlerdata in cantunwind frame"));
19156 return 1; /* EXIDX_CANTUNWIND. */
19159 /* Use a default personality routine if none is specified. */
19160 if (unwind
.personality_index
== -1)
19162 if (unwind
.opcode_count
> 3)
19163 unwind
.personality_index
= 1;
19165 unwind
.personality_index
= 0;
19168 /* Space for the personality routine entry. */
19169 if (unwind
.personality_index
== 0)
19171 if (unwind
.opcode_count
> 3)
19172 as_bad (_("too many unwind opcodes for personality routine 0"));
19176 /* All the data is inline in the index table. */
19179 while (unwind
.opcode_count
> 0)
19181 unwind
.opcode_count
--;
19182 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19186 /* Pad with "finish" opcodes. */
19188 data
= (data
<< 8) | 0xb0;
19195 /* We get two opcodes "free" in the first word. */
19196 size
= unwind
.opcode_count
- 2;
19199 /* An extra byte is required for the opcode count. */
19200 size
= unwind
.opcode_count
+ 1;
19202 size
= (size
+ 3) >> 2;
19204 as_bad (_("too many unwind opcodes"));
19206 frag_align (2, 0, 0);
19207 record_alignment (now_seg
, 2);
19208 unwind
.table_entry
= expr_build_dot ();
19210 /* Allocate the table entry. */
19211 ptr
= frag_more ((size
<< 2) + 4);
19212 where
= frag_now_fix () - ((size
<< 2) + 4);
19214 switch (unwind
.personality_index
)
19217 /* ??? Should this be a PLT generating relocation? */
19218 /* Custom personality routine. */
19219 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
19220 BFD_RELOC_ARM_PREL31
);
19225 /* Set the first byte to the number of additional words. */
19230 /* ABI defined personality routines. */
19232 /* Three opcodes bytes are packed into the first word. */
19239 /* The size and first two opcode bytes go in the first word. */
19240 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
19245 /* Should never happen. */
19249 /* Pack the opcodes into words (MSB first), reversing the list at the same
19251 while (unwind
.opcode_count
> 0)
19255 md_number_to_chars (ptr
, data
, 4);
19260 unwind
.opcode_count
--;
19262 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19265 /* Finish off the last word. */
19268 /* Pad with "finish" opcodes. */
19270 data
= (data
<< 8) | 0xb0;
19272 md_number_to_chars (ptr
, data
, 4);
19277 /* Add an empty descriptor if there is no user-specified data. */
19278 ptr
= frag_more (4);
19279 md_number_to_chars (ptr
, 0, 4);
19286 /* Initialize the DWARF-2 unwind information for this procedure. */
19289 tc_arm_frame_initial_instructions (void)
19291 cfi_add_CFA_def_cfa (REG_SP
, 0);
19293 #endif /* OBJ_ELF */
19295 /* Convert REGNAME to a DWARF-2 register number. */
19298 tc_arm_regname_to_dw2regnum (char *regname
)
19300 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
19310 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
19314 exp
.X_op
= O_secrel
;
19315 exp
.X_add_symbol
= symbol
;
19316 exp
.X_add_number
= 0;
19317 emit_expr (&exp
, size
);
19321 /* MD interface: Symbol and relocation handling. */
19323 /* Return the address within the segment that a PC-relative fixup is
19324 relative to. For ARM, PC-relative fixups applied to instructions
19325 are generally relative to the location of the fixup plus 8 bytes.
19326 Thumb branches are offset by 4, and Thumb loads relative to PC
19327 require special handling. */
19330 md_pcrel_from_section (fixS
* fixP
, segT seg
)
19332 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19334 /* If this is pc-relative and we are going to emit a relocation
19335 then we just want to put out any pipeline compensation that the linker
19336 will need. Otherwise we want to use the calculated base.
19337 For WinCE we skip the bias for externals as well, since this
19338 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19340 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19341 || (arm_force_relocation (fixP
)
19343 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19349 switch (fixP
->fx_r_type
)
19351 /* PC relative addressing on the Thumb is slightly odd as the
19352 bottom two bits of the PC are forced to zero for the
19353 calculation. This happens *after* application of the
19354 pipeline offset. However, Thumb adrl already adjusts for
19355 this, so we need not do it again. */
19356 case BFD_RELOC_ARM_THUMB_ADD
:
19359 case BFD_RELOC_ARM_THUMB_OFFSET
:
19360 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19361 case BFD_RELOC_ARM_T32_ADD_PC12
:
19362 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
19363 return (base
+ 4) & ~3;
19365 /* Thumb branches are simply offset by +4. */
19366 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19367 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19368 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19369 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19370 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19373 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19375 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19376 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19377 && ARM_IS_FUNC (fixP
->fx_addsy
)
19378 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19379 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19382 /* BLX is like branches above, but forces the low two bits of PC to
19384 case BFD_RELOC_THUMB_PCREL_BLX
:
19386 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19387 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19388 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19389 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19390 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19391 return (base
+ 4) & ~3;
19393 /* ARM mode branches are offset by +8. However, the Windows CE
19394 loader expects the relocation not to take this into account. */
19395 case BFD_RELOC_ARM_PCREL_BLX
:
19397 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19398 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19399 && ARM_IS_FUNC (fixP
->fx_addsy
)
19400 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19401 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19404 case BFD_RELOC_ARM_PCREL_CALL
:
19406 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19407 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19408 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19409 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19410 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19413 case BFD_RELOC_ARM_PCREL_BRANCH
:
19414 case BFD_RELOC_ARM_PCREL_JUMP
:
19415 case BFD_RELOC_ARM_PLT32
:
19417 /* When handling fixups immediately, because we have already
19418 discovered the value of a symbol, or the address of the frag involved
19419 we must account for the offset by +8, as the OS loader will never see the reloc.
19420 see fixup_segment() in write.c
19421 The S_IS_EXTERNAL test handles the case of global symbols.
19422 Those need the calculated base, not just the pipe compensation the linker will need. */
19424 && fixP
->fx_addsy
!= NULL
19425 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19426 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
19434 /* ARM mode loads relative to PC are also offset by +8. Unlike
19435 branches, the Windows CE loader *does* expect the relocation
19436 to take this into account. */
19437 case BFD_RELOC_ARM_OFFSET_IMM
:
19438 case BFD_RELOC_ARM_OFFSET_IMM8
:
19439 case BFD_RELOC_ARM_HWLITERAL
:
19440 case BFD_RELOC_ARM_LITERAL
:
19441 case BFD_RELOC_ARM_CP_OFF_IMM
:
19445 /* Other PC-relative relocations are un-offset. */
19451 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
19452 Otherwise we have no need to default values of symbols. */
19455 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
19458 if (name
[0] == '_' && name
[1] == 'G'
19459 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
19463 if (symbol_find (name
))
19464 as_bad (_("GOT already in the symbol table"));
19466 GOT_symbol
= symbol_new (name
, undefined_section
,
19467 (valueT
) 0, & zero_address_frag
);
19477 /* Subroutine of md_apply_fix. Check to see if an immediate can be
19478 computed as two separate immediate values, added together. We
19479 already know that this value cannot be computed by just one ARM
19482 static unsigned int
19483 validate_immediate_twopart (unsigned int val
,
19484 unsigned int * highpart
)
19489 for (i
= 0; i
< 32; i
+= 2)
19490 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
19496 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
19498 else if (a
& 0xff0000)
19500 if (a
& 0xff000000)
19502 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
19506 gas_assert (a
& 0xff000000);
19507 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
19510 return (a
& 0xff) | (i
<< 7);
19517 validate_offset_imm (unsigned int val
, int hwse
)
19519 if ((hwse
&& val
> 255) || val
> 4095)
19524 /* Subroutine of md_apply_fix. Do those data_ops which can take a
19525 negative immediate constant by altering the instruction. A bit of
19530 by inverting the second operand, and
19533 by negating the second operand. */
19536 negate_data_op (unsigned long * instruction
,
19537 unsigned long value
)
19540 unsigned long negated
, inverted
;
19542 negated
= encode_arm_immediate (-value
);
19543 inverted
= encode_arm_immediate (~value
);
19545 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
19548 /* First negates. */
19549 case OPCODE_SUB
: /* ADD <-> SUB */
19550 new_inst
= OPCODE_ADD
;
19555 new_inst
= OPCODE_SUB
;
19559 case OPCODE_CMP
: /* CMP <-> CMN */
19560 new_inst
= OPCODE_CMN
;
19565 new_inst
= OPCODE_CMP
;
19569 /* Now Inverted ops. */
19570 case OPCODE_MOV
: /* MOV <-> MVN */
19571 new_inst
= OPCODE_MVN
;
19576 new_inst
= OPCODE_MOV
;
19580 case OPCODE_AND
: /* AND <-> BIC */
19581 new_inst
= OPCODE_BIC
;
19586 new_inst
= OPCODE_AND
;
19590 case OPCODE_ADC
: /* ADC <-> SBC */
19591 new_inst
= OPCODE_SBC
;
19596 new_inst
= OPCODE_ADC
;
19600 /* We cannot do anything. */
19605 if (value
== (unsigned) FAIL
)
19608 *instruction
&= OPCODE_MASK
;
19609 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
19613 /* Like negate_data_op, but for Thumb-2. */
19615 static unsigned int
19616 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
19620 unsigned int negated
, inverted
;
19622 negated
= encode_thumb32_immediate (-value
);
19623 inverted
= encode_thumb32_immediate (~value
);
19625 rd
= (*instruction
>> 8) & 0xf;
19626 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
19629 /* ADD <-> SUB. Includes CMP <-> CMN. */
19630 case T2_OPCODE_SUB
:
19631 new_inst
= T2_OPCODE_ADD
;
19635 case T2_OPCODE_ADD
:
19636 new_inst
= T2_OPCODE_SUB
;
19640 /* ORR <-> ORN. Includes MOV <-> MVN. */
19641 case T2_OPCODE_ORR
:
19642 new_inst
= T2_OPCODE_ORN
;
19646 case T2_OPCODE_ORN
:
19647 new_inst
= T2_OPCODE_ORR
;
19651 /* AND <-> BIC. TST has no inverted equivalent. */
19652 case T2_OPCODE_AND
:
19653 new_inst
= T2_OPCODE_BIC
;
19660 case T2_OPCODE_BIC
:
19661 new_inst
= T2_OPCODE_AND
;
19666 case T2_OPCODE_ADC
:
19667 new_inst
= T2_OPCODE_SBC
;
19671 case T2_OPCODE_SBC
:
19672 new_inst
= T2_OPCODE_ADC
;
19676 /* We cannot do anything. */
19681 if (value
== (unsigned int)FAIL
)
19684 *instruction
&= T2_OPCODE_MASK
;
19685 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
19689 /* Read a 32-bit thumb instruction from buf. */
19690 static unsigned long
19691 get_thumb32_insn (char * buf
)
19693 unsigned long insn
;
19694 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
19695 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19701 /* We usually want to set the low bit on the address of thumb function
19702 symbols. In particular .word foo - . should have the low bit set.
19703 Generic code tries to fold the difference of two symbols to
19704 a constant. Prevent this and force a relocation when the first symbols
19705 is a thumb function. */
19708 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
19710 if (op
== O_subtract
19711 && l
->X_op
== O_symbol
19712 && r
->X_op
== O_symbol
19713 && THUMB_IS_FUNC (l
->X_add_symbol
))
19715 l
->X_op
= O_subtract
;
19716 l
->X_op_symbol
= r
->X_add_symbol
;
19717 l
->X_add_number
-= r
->X_add_number
;
19721 /* Process as normal. */
19725 /* Encode Thumb2 unconditional branches and calls. The encoding
19726 for the 2 are identical for the immediate values. */
19729 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
19731 #define T2I1I2MASK ((1 << 13) | (1 << 11))
19734 addressT S
, I1
, I2
, lo
, hi
;
19736 S
= (value
>> 24) & 0x01;
19737 I1
= (value
>> 23) & 0x01;
19738 I2
= (value
>> 22) & 0x01;
19739 hi
= (value
>> 12) & 0x3ff;
19740 lo
= (value
>> 1) & 0x7ff;
19741 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19742 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19743 newval
|= (S
<< 10) | hi
;
19744 newval2
&= ~T2I1I2MASK
;
19745 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
19746 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19747 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
19751 md_apply_fix (fixS
* fixP
,
19755 offsetT value
= * valP
;
19757 unsigned int newimm
;
19758 unsigned long temp
;
19760 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
19762 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
19764 /* Note whether this will delete the relocation. */
19766 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
19769 /* On a 64-bit host, silently truncate 'value' to 32 bits for
19770 consistency with the behaviour on 32-bit hosts. Remember value
19772 value
&= 0xffffffff;
19773 value
^= 0x80000000;
19774 value
-= 0x80000000;
19777 fixP
->fx_addnumber
= value
;
19779 /* Same treatment for fixP->fx_offset. */
19780 fixP
->fx_offset
&= 0xffffffff;
19781 fixP
->fx_offset
^= 0x80000000;
19782 fixP
->fx_offset
-= 0x80000000;
19784 switch (fixP
->fx_r_type
)
19786 case BFD_RELOC_NONE
:
19787 /* This will need to go in the object file. */
19791 case BFD_RELOC_ARM_IMMEDIATE
:
19792 /* We claim that this fixup has been processed here,
19793 even if in fact we generate an error because we do
19794 not have a reloc for it, so tc_gen_reloc will reject it. */
19797 if (fixP
->fx_addsy
)
19799 const char *msg
= 0;
19801 if (! S_IS_DEFINED (fixP
->fx_addsy
))
19802 msg
= _("undefined symbol %s used as an immediate value");
19803 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19804 msg
= _("symbol %s is in a different section");
19805 else if (S_IS_WEAK (fixP
->fx_addsy
))
19806 msg
= _("symbol %s is weak and may be overridden later");
19810 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19811 msg
, S_GET_NAME (fixP
->fx_addsy
));
19816 newimm
= encode_arm_immediate (value
);
19817 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19819 /* If the instruction will fail, see if we can fix things up by
19820 changing the opcode. */
19821 if (newimm
== (unsigned int) FAIL
19822 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
19824 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19825 _("invalid constant (%lx) after fixup"),
19826 (unsigned long) value
);
19830 newimm
|= (temp
& 0xfffff000);
19831 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19834 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
19836 unsigned int highpart
= 0;
19837 unsigned int newinsn
= 0xe1a00000; /* nop. */
19839 if (fixP
->fx_addsy
)
19841 const char *msg
= 0;
19843 if (! S_IS_DEFINED (fixP
->fx_addsy
))
19844 msg
= _("undefined symbol %s used as an immediate value");
19845 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19846 msg
= _("symbol %s is in a different section");
19847 else if (S_IS_WEAK (fixP
->fx_addsy
))
19848 msg
= _("symbol %s is weak and may be overridden later");
19852 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19853 msg
, S_GET_NAME (fixP
->fx_addsy
));
19858 newimm
= encode_arm_immediate (value
);
19859 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19861 /* If the instruction will fail, see if we can fix things up by
19862 changing the opcode. */
19863 if (newimm
== (unsigned int) FAIL
19864 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
19866 /* No ? OK - try using two ADD instructions to generate
19868 newimm
= validate_immediate_twopart (value
, & highpart
);
19870 /* Yes - then make sure that the second instruction is
19872 if (newimm
!= (unsigned int) FAIL
)
19874 /* Still No ? Try using a negated value. */
19875 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
19876 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
19877 /* Otherwise - give up. */
19880 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19881 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
19886 /* Replace the first operand in the 2nd instruction (which
19887 is the PC) with the destination register. We have
19888 already added in the PC in the first instruction and we
19889 do not want to do it again. */
19890 newinsn
&= ~ 0xf0000;
19891 newinsn
|= ((newinsn
& 0x0f000) << 4);
19894 newimm
|= (temp
& 0xfffff000);
19895 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19897 highpart
|= (newinsn
& 0xfffff000);
19898 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
19902 case BFD_RELOC_ARM_OFFSET_IMM
:
19903 if (!fixP
->fx_done
&& seg
->use_rela_p
)
19906 case BFD_RELOC_ARM_LITERAL
:
19912 if (validate_offset_imm (value
, 0) == FAIL
)
19914 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
19915 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19916 _("invalid literal constant: pool needs to be closer"));
19918 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19919 _("bad immediate value for offset (%ld)"),
19924 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19925 newval
&= 0xff7ff000;
19926 newval
|= value
| (sign
? INDEX_UP
: 0);
19927 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19930 case BFD_RELOC_ARM_OFFSET_IMM8
:
19931 case BFD_RELOC_ARM_HWLITERAL
:
19937 if (validate_offset_imm (value
, 1) == FAIL
)
19939 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
19940 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19941 _("invalid literal constant: pool needs to be closer"));
19943 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
19948 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19949 newval
&= 0xff7ff0f0;
19950 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
19951 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19954 case BFD_RELOC_ARM_T32_OFFSET_U8
:
19955 if (value
< 0 || value
> 1020 || value
% 4 != 0)
19956 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19957 _("bad immediate value for offset (%ld)"), (long) value
);
19960 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
19962 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
19965 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19966 /* This is a complicated relocation used for all varieties of Thumb32
19967 load/store instruction with immediate offset:
19969 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
19970 *4, optional writeback(W)
19971 (doubleword load/store)
19973 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
19974 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
19975 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
19976 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
19977 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
19979 Uppercase letters indicate bits that are already encoded at
19980 this point. Lowercase letters are our problem. For the
19981 second block of instructions, the secondary opcode nybble
19982 (bits 8..11) is present, and bit 23 is zero, even if this is
19983 a PC-relative operation. */
19984 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19986 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
19988 if ((newval
& 0xf0000000) == 0xe0000000)
19990 /* Doubleword load/store: 8-bit offset, scaled by 4. */
19992 newval
|= (1 << 23);
19995 if (value
% 4 != 0)
19997 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19998 _("offset not a multiple of 4"));
20004 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20005 _("offset out of range"));
20010 else if ((newval
& 0x000f0000) == 0x000f0000)
20012 /* PC-relative, 12-bit offset. */
20014 newval
|= (1 << 23);
20019 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20020 _("offset out of range"));
20025 else if ((newval
& 0x00000100) == 0x00000100)
20027 /* Writeback: 8-bit, +/- offset. */
20029 newval
|= (1 << 9);
20034 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20035 _("offset out of range"));
20040 else if ((newval
& 0x00000f00) == 0x00000e00)
20042 /* T-instruction: positive 8-bit offset. */
20043 if (value
< 0 || value
> 0xff)
20045 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20046 _("offset out of range"));
20054 /* Positive 12-bit or negative 8-bit offset. */
20058 newval
|= (1 << 23);
20068 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20069 _("offset out of range"));
20076 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
20077 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
20080 case BFD_RELOC_ARM_SHIFT_IMM
:
20081 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20082 if (((unsigned long) value
) > 32
20084 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
20086 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20087 _("shift expression is too large"));
20092 /* Shifts of zero must be done as lsl. */
20094 else if (value
== 32)
20096 newval
&= 0xfffff07f;
20097 newval
|= (value
& 0x1f) << 7;
20098 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20101 case BFD_RELOC_ARM_T32_IMMEDIATE
:
20102 case BFD_RELOC_ARM_T32_ADD_IMM
:
20103 case BFD_RELOC_ARM_T32_IMM12
:
20104 case BFD_RELOC_ARM_T32_ADD_PC12
:
20105 /* We claim that this fixup has been processed here,
20106 even if in fact we generate an error because we do
20107 not have a reloc for it, so tc_gen_reloc will reject it. */
20111 && ! S_IS_DEFINED (fixP
->fx_addsy
))
20113 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20114 _("undefined symbol %s used as an immediate value"),
20115 S_GET_NAME (fixP
->fx_addsy
));
20119 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20121 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
20124 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
20125 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20127 newimm
= encode_thumb32_immediate (value
);
20128 if (newimm
== (unsigned int) FAIL
)
20129 newimm
= thumb32_negate_data_op (&newval
, value
);
20131 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
20132 && newimm
== (unsigned int) FAIL
)
20134 /* Turn add/sum into addw/subw. */
20135 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20136 newval
= (newval
& 0xfeffffff) | 0x02000000;
20138 /* 12 bit immediate for addw/subw. */
20142 newval
^= 0x00a00000;
20145 newimm
= (unsigned int) FAIL
;
20150 if (newimm
== (unsigned int)FAIL
)
20152 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20153 _("invalid constant (%lx) after fixup"),
20154 (unsigned long) value
);
20158 newval
|= (newimm
& 0x800) << 15;
20159 newval
|= (newimm
& 0x700) << 4;
20160 newval
|= (newimm
& 0x0ff);
20162 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
20163 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
20166 case BFD_RELOC_ARM_SMC
:
20167 if (((unsigned long) value
) > 0xffff)
20168 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20169 _("invalid smc expression"));
20170 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20171 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20172 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20175 case BFD_RELOC_ARM_SWI
:
20176 if (fixP
->tc_fix_data
!= 0)
20178 if (((unsigned long) value
) > 0xff)
20179 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20180 _("invalid swi expression"));
20181 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20183 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20187 if (((unsigned long) value
) > 0x00ffffff)
20188 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20189 _("invalid swi expression"));
20190 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20192 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20196 case BFD_RELOC_ARM_MULTI
:
20197 if (((unsigned long) value
) > 0xffff)
20198 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20199 _("invalid expression in load/store multiple"));
20200 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
20201 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20205 case BFD_RELOC_ARM_PCREL_CALL
:
20207 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20209 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20210 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20211 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20212 /* Flip the bl to blx. This is a simple flip
20213 bit here because we generate PCREL_CALL for
20214 unconditional bls. */
20216 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20217 newval
= newval
| 0x10000000;
20218 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20224 goto arm_branch_common
;
20226 case BFD_RELOC_ARM_PCREL_JUMP
:
20227 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20229 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20230 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20231 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20233 /* This would map to a bl<cond>, b<cond>,
20234 b<always> to a Thumb function. We
20235 need to force a relocation for this particular
20237 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20241 case BFD_RELOC_ARM_PLT32
:
20243 case BFD_RELOC_ARM_PCREL_BRANCH
:
20245 goto arm_branch_common
;
20247 case BFD_RELOC_ARM_PCREL_BLX
:
20250 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20252 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20253 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20254 && ARM_IS_FUNC (fixP
->fx_addsy
))
20256 /* Flip the blx to a bl and warn. */
20257 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20258 newval
= 0xeb000000;
20259 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20260 _("blx to '%s' an ARM ISA state function changed to bl"),
20262 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20268 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20269 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
20273 /* We are going to store value (shifted right by two) in the
20274 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20275 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20276 also be be clear. */
20278 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20279 _("misaligned branch destination"));
20280 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
20281 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
20282 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20283 _("branch out of range"));
20285 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20287 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20288 newval
|= (value
>> 2) & 0x00ffffff;
20289 /* Set the H bit on BLX instructions. */
20293 newval
|= 0x01000000;
20295 newval
&= ~0x01000000;
20297 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20301 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
20302 /* CBZ can only branch forward. */
20304 /* Attempts to use CBZ to branch to the next instruction
20305 (which, strictly speaking, are prohibited) will be turned into
20308 FIXME: It may be better to remove the instruction completely and
20309 perform relaxation. */
20312 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20313 newval
= 0xbf00; /* NOP encoding T1 */
20314 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20319 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20320 _("branch out of range"));
20322 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20324 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20325 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
20326 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20331 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
20332 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
20333 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20334 _("branch out of range"));
20336 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20338 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20339 newval
|= (value
& 0x1ff) >> 1;
20340 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20344 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
20345 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
20346 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20347 _("branch out of range"));
20349 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20351 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20352 newval
|= (value
& 0xfff) >> 1;
20353 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20357 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20359 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20360 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20361 && S_IS_DEFINED (fixP
->fx_addsy
)
20362 && ARM_IS_FUNC (fixP
->fx_addsy
)
20363 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20365 /* Force a relocation for a branch 20 bits wide. */
20368 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
20369 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20370 _("conditional branch out of range"));
20372 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20375 addressT S
, J1
, J2
, lo
, hi
;
20377 S
= (value
& 0x00100000) >> 20;
20378 J2
= (value
& 0x00080000) >> 19;
20379 J1
= (value
& 0x00040000) >> 18;
20380 hi
= (value
& 0x0003f000) >> 12;
20381 lo
= (value
& 0x00000ffe) >> 1;
20383 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20384 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20385 newval
|= (S
<< 10) | hi
;
20386 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
20387 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20388 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20392 case BFD_RELOC_THUMB_PCREL_BLX
:
20394 /* If there is a blx from a thumb state function to
20395 another thumb function flip this to a bl and warn
20399 && S_IS_DEFINED (fixP
->fx_addsy
)
20400 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20401 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20402 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20404 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20405 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20406 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
20408 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20409 newval
= newval
| 0x1000;
20410 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20411 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20416 goto thumb_bl_common
;
20418 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20420 /* A bl from Thumb state ISA to an internal ARM state function
20421 is converted to a blx. */
20423 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20424 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20425 && S_IS_DEFINED (fixP
->fx_addsy
)
20426 && ARM_IS_FUNC (fixP
->fx_addsy
)
20427 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20429 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20430 newval
= newval
& ~0x1000;
20431 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20432 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
20439 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
20440 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20441 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20444 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20445 /* For a BLX instruction, make sure that the relocation is rounded up
20446 to a word boundary. This follows the semantics of the instruction
20447 which specifies that bit 1 of the target address will come from bit
20448 1 of the base address. */
20449 value
= (value
+ 1) & ~ 1;
20452 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
20454 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
20456 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20457 _("branch out of range"));
20459 else if ((value
& ~0x1ffffff)
20460 && ((value
& ~0x1ffffff) != ~0x1ffffff))
20462 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20463 _("Thumb2 branch out of range"));
20467 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20468 encode_thumb2_b_bl_offset (buf
, value
);
20472 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20473 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
20474 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20475 _("branch out of range"));
20477 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20478 encode_thumb2_b_bl_offset (buf
, value
);
20483 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20484 md_number_to_chars (buf
, value
, 1);
20488 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20489 md_number_to_chars (buf
, value
, 2);
20493 case BFD_RELOC_ARM_TLS_GD32
:
20494 case BFD_RELOC_ARM_TLS_LE32
:
20495 case BFD_RELOC_ARM_TLS_IE32
:
20496 case BFD_RELOC_ARM_TLS_LDM32
:
20497 case BFD_RELOC_ARM_TLS_LDO32
:
20498 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
20501 case BFD_RELOC_ARM_GOT32
:
20502 case BFD_RELOC_ARM_GOTOFF
:
20503 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20504 md_number_to_chars (buf
, 0, 4);
20507 case BFD_RELOC_ARM_GOT_PREL
:
20508 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20509 md_number_to_chars (buf
, value
, 4);
20512 case BFD_RELOC_ARM_TARGET2
:
20513 /* TARGET2 is not partial-inplace, so we need to write the
20514 addend here for REL targets, because it won't be written out
20515 during reloc processing later. */
20516 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20517 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
20521 case BFD_RELOC_RVA
:
20523 case BFD_RELOC_ARM_TARGET1
:
20524 case BFD_RELOC_ARM_ROSEGREL32
:
20525 case BFD_RELOC_ARM_SBREL32
:
20526 case BFD_RELOC_32_PCREL
:
20528 case BFD_RELOC_32_SECREL
:
20530 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20532 /* For WinCE we only do this for pcrel fixups. */
20533 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
20535 md_number_to_chars (buf
, value
, 4);
20539 case BFD_RELOC_ARM_PREL31
:
20540 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20542 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
20543 if ((value
^ (value
>> 1)) & 0x40000000)
20545 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20546 _("rel31 relocation overflow"));
20548 newval
|= value
& 0x7fffffff;
20549 md_number_to_chars (buf
, newval
, 4);
20554 case BFD_RELOC_ARM_CP_OFF_IMM
:
20555 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
20556 if (value
< -1023 || value
> 1023 || (value
& 3))
20557 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20558 _("co-processor offset out of range"));
20563 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20564 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20565 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20567 newval
= get_thumb32_insn (buf
);
20568 newval
&= 0xff7fff00;
20569 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
20570 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20571 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20572 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20574 put_thumb32_insn (buf
, newval
);
20577 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
20578 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
20579 if (value
< -255 || value
> 255)
20580 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20581 _("co-processor offset out of range"));
20583 goto cp_off_common
;
20585 case BFD_RELOC_ARM_THUMB_OFFSET
:
20586 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20587 /* Exactly what ranges, and where the offset is inserted depends
20588 on the type of instruction, we can establish this from the
20590 switch (newval
>> 12)
20592 case 4: /* PC load. */
20593 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
20594 forced to zero for these loads; md_pcrel_from has already
20595 compensated for this. */
20597 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20598 _("invalid offset, target not word aligned (0x%08lX)"),
20599 (((unsigned long) fixP
->fx_frag
->fr_address
20600 + (unsigned long) fixP
->fx_where
) & ~3)
20601 + (unsigned long) value
);
20603 if (value
& ~0x3fc)
20604 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20605 _("invalid offset, value too big (0x%08lX)"),
20608 newval
|= value
>> 2;
20611 case 9: /* SP load/store. */
20612 if (value
& ~0x3fc)
20613 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20614 _("invalid offset, value too big (0x%08lX)"),
20616 newval
|= value
>> 2;
20619 case 6: /* Word load/store. */
20621 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20622 _("invalid offset, value too big (0x%08lX)"),
20624 newval
|= value
<< 4; /* 6 - 2. */
20627 case 7: /* Byte load/store. */
20629 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20630 _("invalid offset, value too big (0x%08lX)"),
20632 newval
|= value
<< 6;
20635 case 8: /* Halfword load/store. */
20637 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20638 _("invalid offset, value too big (0x%08lX)"),
20640 newval
|= value
<< 5; /* 6 - 1. */
20644 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20645 "Unable to process relocation for thumb opcode: %lx",
20646 (unsigned long) newval
);
20649 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20652 case BFD_RELOC_ARM_THUMB_ADD
:
20653 /* This is a complicated relocation, since we use it for all of
20654 the following immediate relocations:
20658 9bit ADD/SUB SP word-aligned
20659 10bit ADD PC/SP word-aligned
20661 The type of instruction being processed is encoded in the
20668 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20670 int rd
= (newval
>> 4) & 0xf;
20671 int rs
= newval
& 0xf;
20672 int subtract
= !!(newval
& 0x8000);
20674 /* Check for HI regs, only very restricted cases allowed:
20675 Adjusting SP, and using PC or SP to get an address. */
20676 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
20677 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
20678 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20679 _("invalid Hi register with immediate"));
20681 /* If value is negative, choose the opposite instruction. */
20685 subtract
= !subtract
;
20687 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20688 _("immediate value out of range"));
20693 if (value
& ~0x1fc)
20694 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20695 _("invalid immediate for stack address calculation"));
20696 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
20697 newval
|= value
>> 2;
20699 else if (rs
== REG_PC
|| rs
== REG_SP
)
20701 if (subtract
|| value
& ~0x3fc)
20702 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20703 _("invalid immediate for address calculation (value = 0x%08lX)"),
20704 (unsigned long) value
);
20705 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
20707 newval
|= value
>> 2;
20712 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20713 _("immediate value out of range"));
20714 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
20715 newval
|= (rd
<< 8) | value
;
20720 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20721 _("immediate value out of range"));
20722 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
20723 newval
|= rd
| (rs
<< 3) | (value
<< 6);
20726 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20729 case BFD_RELOC_ARM_THUMB_IMM
:
20730 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20731 if (value
< 0 || value
> 255)
20732 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20733 _("invalid immediate: %ld is out of range"),
20736 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20739 case BFD_RELOC_ARM_THUMB_SHIFT
:
20740 /* 5bit shift value (0..32). LSL cannot take 32. */
20741 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
20742 temp
= newval
& 0xf800;
20743 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
20744 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20745 _("invalid shift value: %ld"), (long) value
);
20746 /* Shifts of zero must be encoded as LSL. */
20748 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
20749 /* Shifts of 32 are encoded as zero. */
20750 else if (value
== 32)
20752 newval
|= value
<< 6;
20753 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20756 case BFD_RELOC_VTABLE_INHERIT
:
20757 case BFD_RELOC_VTABLE_ENTRY
:
20761 case BFD_RELOC_ARM_MOVW
:
20762 case BFD_RELOC_ARM_MOVT
:
20763 case BFD_RELOC_ARM_THUMB_MOVW
:
20764 case BFD_RELOC_ARM_THUMB_MOVT
:
20765 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20767 /* REL format relocations are limited to a 16-bit addend. */
20768 if (!fixP
->fx_done
)
20770 if (value
< -0x8000 || value
> 0x7fff)
20771 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20772 _("offset out of range"));
20774 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
20775 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20780 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
20781 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20783 newval
= get_thumb32_insn (buf
);
20784 newval
&= 0xfbf08f00;
20785 newval
|= (value
& 0xf000) << 4;
20786 newval
|= (value
& 0x0800) << 15;
20787 newval
|= (value
& 0x0700) << 4;
20788 newval
|= (value
& 0x00ff);
20789 put_thumb32_insn (buf
, newval
);
20793 newval
= md_chars_to_number (buf
, 4);
20794 newval
&= 0xfff0f000;
20795 newval
|= value
& 0x0fff;
20796 newval
|= (value
& 0xf000) << 4;
20797 md_number_to_chars (buf
, newval
, 4);
20802 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
20803 case BFD_RELOC_ARM_ALU_PC_G0
:
20804 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
20805 case BFD_RELOC_ARM_ALU_PC_G1
:
20806 case BFD_RELOC_ARM_ALU_PC_G2
:
20807 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
20808 case BFD_RELOC_ARM_ALU_SB_G0
:
20809 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
20810 case BFD_RELOC_ARM_ALU_SB_G1
:
20811 case BFD_RELOC_ARM_ALU_SB_G2
:
20812 gas_assert (!fixP
->fx_done
);
20813 if (!seg
->use_rela_p
)
20816 bfd_vma encoded_addend
;
20817 bfd_vma addend_abs
= abs (value
);
20819 /* Check that the absolute value of the addend can be
20820 expressed as an 8-bit constant plus a rotation. */
20821 encoded_addend
= encode_arm_immediate (addend_abs
);
20822 if (encoded_addend
== (unsigned int) FAIL
)
20823 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20824 _("the offset 0x%08lX is not representable"),
20825 (unsigned long) addend_abs
);
20827 /* Extract the instruction. */
20828 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20830 /* If the addend is positive, use an ADD instruction.
20831 Otherwise use a SUB. Take care not to destroy the S bit. */
20832 insn
&= 0xff1fffff;
20838 /* Place the encoded addend into the first 12 bits of the
20840 insn
&= 0xfffff000;
20841 insn
|= encoded_addend
;
20843 /* Update the instruction. */
20844 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20848 case BFD_RELOC_ARM_LDR_PC_G0
:
20849 case BFD_RELOC_ARM_LDR_PC_G1
:
20850 case BFD_RELOC_ARM_LDR_PC_G2
:
20851 case BFD_RELOC_ARM_LDR_SB_G0
:
20852 case BFD_RELOC_ARM_LDR_SB_G1
:
20853 case BFD_RELOC_ARM_LDR_SB_G2
:
20854 gas_assert (!fixP
->fx_done
);
20855 if (!seg
->use_rela_p
)
20858 bfd_vma addend_abs
= abs (value
);
20860 /* Check that the absolute value of the addend can be
20861 encoded in 12 bits. */
20862 if (addend_abs
>= 0x1000)
20863 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20864 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
20865 (unsigned long) addend_abs
);
20867 /* Extract the instruction. */
20868 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20870 /* If the addend is negative, clear bit 23 of the instruction.
20871 Otherwise set it. */
20873 insn
&= ~(1 << 23);
20877 /* Place the absolute value of the addend into the first 12 bits
20878 of the instruction. */
20879 insn
&= 0xfffff000;
20880 insn
|= addend_abs
;
20882 /* Update the instruction. */
20883 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20887 case BFD_RELOC_ARM_LDRS_PC_G0
:
20888 case BFD_RELOC_ARM_LDRS_PC_G1
:
20889 case BFD_RELOC_ARM_LDRS_PC_G2
:
20890 case BFD_RELOC_ARM_LDRS_SB_G0
:
20891 case BFD_RELOC_ARM_LDRS_SB_G1
:
20892 case BFD_RELOC_ARM_LDRS_SB_G2
:
20893 gas_assert (!fixP
->fx_done
);
20894 if (!seg
->use_rela_p
)
20897 bfd_vma addend_abs
= abs (value
);
20899 /* Check that the absolute value of the addend can be
20900 encoded in 8 bits. */
20901 if (addend_abs
>= 0x100)
20902 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20903 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
20904 (unsigned long) addend_abs
);
20906 /* Extract the instruction. */
20907 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20909 /* If the addend is negative, clear bit 23 of the instruction.
20910 Otherwise set it. */
20912 insn
&= ~(1 << 23);
20916 /* Place the first four bits of the absolute value of the addend
20917 into the first 4 bits of the instruction, and the remaining
20918 four into bits 8 .. 11. */
20919 insn
&= 0xfffff0f0;
20920 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
20922 /* Update the instruction. */
20923 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20927 case BFD_RELOC_ARM_LDC_PC_G0
:
20928 case BFD_RELOC_ARM_LDC_PC_G1
:
20929 case BFD_RELOC_ARM_LDC_PC_G2
:
20930 case BFD_RELOC_ARM_LDC_SB_G0
:
20931 case BFD_RELOC_ARM_LDC_SB_G1
:
20932 case BFD_RELOC_ARM_LDC_SB_G2
:
20933 gas_assert (!fixP
->fx_done
);
20934 if (!seg
->use_rela_p
)
20937 bfd_vma addend_abs
= abs (value
);
20939 /* Check that the absolute value of the addend is a multiple of
20940 four and, when divided by four, fits in 8 bits. */
20941 if (addend_abs
& 0x3)
20942 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20943 _("bad offset 0x%08lX (must be word-aligned)"),
20944 (unsigned long) addend_abs
);
20946 if ((addend_abs
>> 2) > 0xff)
20947 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20948 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
20949 (unsigned long) addend_abs
);
20951 /* Extract the instruction. */
20952 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20954 /* If the addend is negative, clear bit 23 of the instruction.
20955 Otherwise set it. */
20957 insn
&= ~(1 << 23);
20961 /* Place the addend (divided by four) into the first eight
20962 bits of the instruction. */
20963 insn
&= 0xfffffff0;
20964 insn
|= addend_abs
>> 2;
20966 /* Update the instruction. */
20967 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20971 case BFD_RELOC_ARM_V4BX
:
20972 /* This will need to go in the object file. */
20976 case BFD_RELOC_UNUSED
:
20978 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20979 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
20983 /* Translate internal representation of relocation info to BFD target
20987 tc_gen_reloc (asection
*section
, fixS
*fixp
)
20990 bfd_reloc_code_real_type code
;
20992 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
20994 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
20995 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
20996 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
20998 if (fixp
->fx_pcrel
)
21000 if (section
->use_rela_p
)
21001 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
21003 fixp
->fx_offset
= reloc
->address
;
21005 reloc
->addend
= fixp
->fx_offset
;
21007 switch (fixp
->fx_r_type
)
21010 if (fixp
->fx_pcrel
)
21012 code
= BFD_RELOC_8_PCREL
;
21017 if (fixp
->fx_pcrel
)
21019 code
= BFD_RELOC_16_PCREL
;
21024 if (fixp
->fx_pcrel
)
21026 code
= BFD_RELOC_32_PCREL
;
21030 case BFD_RELOC_ARM_MOVW
:
21031 if (fixp
->fx_pcrel
)
21033 code
= BFD_RELOC_ARM_MOVW_PCREL
;
21037 case BFD_RELOC_ARM_MOVT
:
21038 if (fixp
->fx_pcrel
)
21040 code
= BFD_RELOC_ARM_MOVT_PCREL
;
21044 case BFD_RELOC_ARM_THUMB_MOVW
:
21045 if (fixp
->fx_pcrel
)
21047 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
21051 case BFD_RELOC_ARM_THUMB_MOVT
:
21052 if (fixp
->fx_pcrel
)
21054 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
21058 case BFD_RELOC_NONE
:
21059 case BFD_RELOC_ARM_PCREL_BRANCH
:
21060 case BFD_RELOC_ARM_PCREL_BLX
:
21061 case BFD_RELOC_RVA
:
21062 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21063 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21064 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21065 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21066 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21067 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21068 case BFD_RELOC_VTABLE_ENTRY
:
21069 case BFD_RELOC_VTABLE_INHERIT
:
21071 case BFD_RELOC_32_SECREL
:
21073 code
= fixp
->fx_r_type
;
21076 case BFD_RELOC_THUMB_PCREL_BLX
:
21078 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
21079 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21082 code
= BFD_RELOC_THUMB_PCREL_BLX
;
21085 case BFD_RELOC_ARM_LITERAL
:
21086 case BFD_RELOC_ARM_HWLITERAL
:
21087 /* If this is called then the a literal has
21088 been referenced across a section boundary. */
21089 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21090 _("literal referenced across section boundary"));
21094 case BFD_RELOC_ARM_GOT32
:
21095 case BFD_RELOC_ARM_GOTOFF
:
21096 case BFD_RELOC_ARM_GOT_PREL
:
21097 case BFD_RELOC_ARM_PLT32
:
21098 case BFD_RELOC_ARM_TARGET1
:
21099 case BFD_RELOC_ARM_ROSEGREL32
:
21100 case BFD_RELOC_ARM_SBREL32
:
21101 case BFD_RELOC_ARM_PREL31
:
21102 case BFD_RELOC_ARM_TARGET2
:
21103 case BFD_RELOC_ARM_TLS_LE32
:
21104 case BFD_RELOC_ARM_TLS_LDO32
:
21105 case BFD_RELOC_ARM_PCREL_CALL
:
21106 case BFD_RELOC_ARM_PCREL_JUMP
:
21107 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21108 case BFD_RELOC_ARM_ALU_PC_G0
:
21109 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21110 case BFD_RELOC_ARM_ALU_PC_G1
:
21111 case BFD_RELOC_ARM_ALU_PC_G2
:
21112 case BFD_RELOC_ARM_LDR_PC_G0
:
21113 case BFD_RELOC_ARM_LDR_PC_G1
:
21114 case BFD_RELOC_ARM_LDR_PC_G2
:
21115 case BFD_RELOC_ARM_LDRS_PC_G0
:
21116 case BFD_RELOC_ARM_LDRS_PC_G1
:
21117 case BFD_RELOC_ARM_LDRS_PC_G2
:
21118 case BFD_RELOC_ARM_LDC_PC_G0
:
21119 case BFD_RELOC_ARM_LDC_PC_G1
:
21120 case BFD_RELOC_ARM_LDC_PC_G2
:
21121 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21122 case BFD_RELOC_ARM_ALU_SB_G0
:
21123 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21124 case BFD_RELOC_ARM_ALU_SB_G1
:
21125 case BFD_RELOC_ARM_ALU_SB_G2
:
21126 case BFD_RELOC_ARM_LDR_SB_G0
:
21127 case BFD_RELOC_ARM_LDR_SB_G1
:
21128 case BFD_RELOC_ARM_LDR_SB_G2
:
21129 case BFD_RELOC_ARM_LDRS_SB_G0
:
21130 case BFD_RELOC_ARM_LDRS_SB_G1
:
21131 case BFD_RELOC_ARM_LDRS_SB_G2
:
21132 case BFD_RELOC_ARM_LDC_SB_G0
:
21133 case BFD_RELOC_ARM_LDC_SB_G1
:
21134 case BFD_RELOC_ARM_LDC_SB_G2
:
21135 case BFD_RELOC_ARM_V4BX
:
21136 code
= fixp
->fx_r_type
;
21139 case BFD_RELOC_ARM_TLS_GD32
:
21140 case BFD_RELOC_ARM_TLS_IE32
:
21141 case BFD_RELOC_ARM_TLS_LDM32
:
21142 /* BFD will include the symbol's address in the addend.
21143 But we don't want that, so subtract it out again here. */
21144 if (!S_IS_COMMON (fixp
->fx_addsy
))
21145 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
21146 code
= fixp
->fx_r_type
;
21150 case BFD_RELOC_ARM_IMMEDIATE
:
21151 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21152 _("internal relocation (type: IMMEDIATE) not fixed up"));
21155 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
21156 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21157 _("ADRL used for a symbol not defined in the same file"));
21160 case BFD_RELOC_ARM_OFFSET_IMM
:
21161 if (section
->use_rela_p
)
21163 code
= fixp
->fx_r_type
;
21167 if (fixp
->fx_addsy
!= NULL
21168 && !S_IS_DEFINED (fixp
->fx_addsy
)
21169 && S_IS_LOCAL (fixp
->fx_addsy
))
21171 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21172 _("undefined local label `%s'"),
21173 S_GET_NAME (fixp
->fx_addsy
));
21177 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21178 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21185 switch (fixp
->fx_r_type
)
21187 case BFD_RELOC_NONE
: type
= "NONE"; break;
21188 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
21189 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
21190 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
21191 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
21192 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
21193 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
21194 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
21195 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
21196 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
21197 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
21198 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
21199 default: type
= _("<unknown>"); break;
21201 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21202 _("cannot represent %s relocation in this object file format"),
21209 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
21211 && fixp
->fx_addsy
== GOT_symbol
)
21213 code
= BFD_RELOC_ARM_GOTPC
;
21214 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
21218 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
21220 if (reloc
->howto
== NULL
)
21222 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21223 _("cannot represent %s relocation in this object file format"),
21224 bfd_get_reloc_code_name (code
));
21228 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21229 vtable entry to be used in the relocation's section offset. */
21230 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21231 reloc
->address
= fixp
->fx_offset
;
21236 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21239 cons_fix_new_arm (fragS
* frag
,
21244 bfd_reloc_code_real_type type
;
21248 FIXME: @@ Should look at CPU word size. */
21252 type
= BFD_RELOC_8
;
21255 type
= BFD_RELOC_16
;
21259 type
= BFD_RELOC_32
;
21262 type
= BFD_RELOC_64
;
21267 if (exp
->X_op
== O_secrel
)
21269 exp
->X_op
= O_symbol
;
21270 type
= BFD_RELOC_32_SECREL
;
21274 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
21277 #if defined (OBJ_COFF)
21279 arm_validate_fix (fixS
* fixP
)
21281 /* If the destination of the branch is a defined symbol which does not have
21282 the THUMB_FUNC attribute, then we must be calling a function which has
21283 the (interfacearm) attribute. We look for the Thumb entry point to that
21284 function and change the branch to refer to that function instead. */
21285 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
21286 && fixP
->fx_addsy
!= NULL
21287 && S_IS_DEFINED (fixP
->fx_addsy
)
21288 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
21290 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
21297 arm_force_relocation (struct fix
* fixp
)
21299 #if defined (OBJ_COFF) && defined (TE_PE)
21300 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
21304 /* In case we have a call or a branch to a function in ARM ISA mode from
21305 a thumb function or vice-versa force the relocation. These relocations
21306 are cleared off for some cores that might have blx and simple transformations
21310 switch (fixp
->fx_r_type
)
21312 case BFD_RELOC_ARM_PCREL_JUMP
:
21313 case BFD_RELOC_ARM_PCREL_CALL
:
21314 case BFD_RELOC_THUMB_PCREL_BLX
:
21315 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
21319 case BFD_RELOC_ARM_PCREL_BLX
:
21320 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21321 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21322 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21323 if (ARM_IS_FUNC (fixp
->fx_addsy
))
21332 /* Resolve these relocations even if the symbol is extern or weak. */
21333 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
21334 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
21335 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
21336 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
21337 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
21338 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
21339 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
21342 /* Always leave these relocations for the linker. */
21343 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21344 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21345 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21348 /* Always generate relocations against function symbols. */
21349 if (fixp
->fx_r_type
== BFD_RELOC_32
21351 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
21354 return generic_force_reloc (fixp
);
21357 #if defined (OBJ_ELF) || defined (OBJ_COFF)
21358 /* Relocations against function names must be left unadjusted,
21359 so that the linker can use this information to generate interworking
21360 stubs. The MIPS version of this function
21361 also prevents relocations that are mips-16 specific, but I do not
21362 know why it does this.
21365 There is one other problem that ought to be addressed here, but
21366 which currently is not: Taking the address of a label (rather
21367 than a function) and then later jumping to that address. Such
21368 addresses also ought to have their bottom bit set (assuming that
21369 they reside in Thumb code), but at the moment they will not. */
21372 arm_fix_adjustable (fixS
* fixP
)
21374 if (fixP
->fx_addsy
== NULL
)
21377 /* Preserve relocations against symbols with function type. */
21378 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
21381 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
21382 && fixP
->fx_subsy
== NULL
)
21385 /* We need the symbol name for the VTABLE entries. */
21386 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
21387 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21390 /* Don't allow symbols to be discarded on GOT related relocs. */
21391 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
21392 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
21393 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
21394 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
21395 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
21396 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
21397 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
21398 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
21399 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
21402 /* Similarly for group relocations. */
21403 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21404 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21405 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21408 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
21409 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
21410 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21411 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
21412 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
21413 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21414 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
21415 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
21416 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
21421 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
21426 elf32_arm_target_format (void)
21429 return (target_big_endian
21430 ? "elf32-bigarm-symbian"
21431 : "elf32-littlearm-symbian");
21432 #elif defined (TE_VXWORKS)
21433 return (target_big_endian
21434 ? "elf32-bigarm-vxworks"
21435 : "elf32-littlearm-vxworks");
21437 if (target_big_endian
)
21438 return "elf32-bigarm";
21440 return "elf32-littlearm";
21445 armelf_frob_symbol (symbolS
* symp
,
21448 elf_frob_symbol (symp
, puntp
);
21452 /* MD interface: Finalization. */
21457 literal_pool
* pool
;
21459 /* Ensure that all the IT blocks are properly closed. */
21460 check_it_blocks_finished ();
21462 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
21464 /* Put it at the end of the relevant section. */
21465 subseg_set (pool
->section
, pool
->sub_section
);
21467 arm_elf_change_section ();
21474 /* Remove any excess mapping symbols generated for alignment frags in
21475 SEC. We may have created a mapping symbol before a zero byte
21476 alignment; remove it if there's a mapping symbol after the
21479 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
21480 void *dummy ATTRIBUTE_UNUSED
)
21482 segment_info_type
*seginfo
= seg_info (sec
);
21485 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
21488 for (fragp
= seginfo
->frchainP
->frch_root
;
21490 fragp
= fragp
->fr_next
)
21492 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
21493 fragS
*next
= fragp
->fr_next
;
21495 /* Variable-sized frags have been converted to fixed size by
21496 this point. But if this was variable-sized to start with,
21497 there will be a fixed-size frag after it. So don't handle
21499 if (sym
== NULL
|| next
== NULL
)
21502 if (S_GET_VALUE (sym
) < next
->fr_address
)
21503 /* Not at the end of this frag. */
21505 know (S_GET_VALUE (sym
) == next
->fr_address
);
21509 if (next
->tc_frag_data
.first_map
!= NULL
)
21511 /* Next frag starts with a mapping symbol. Discard this
21513 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21517 if (next
->fr_next
== NULL
)
21519 /* This mapping symbol is at the end of the section. Discard
21521 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
21522 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21526 /* As long as we have empty frags without any mapping symbols,
21528 /* If the next frag is non-empty and does not start with a
21529 mapping symbol, then this mapping symbol is required. */
21530 if (next
->fr_address
!= next
->fr_next
->fr_address
)
21533 next
= next
->fr_next
;
21535 while (next
!= NULL
);
21540 /* Adjust the symbol table. This marks Thumb symbols as distinct from
21544 arm_adjust_symtab (void)
21549 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21551 if (ARM_IS_THUMB (sym
))
21553 if (THUMB_IS_FUNC (sym
))
21555 /* Mark the symbol as a Thumb function. */
21556 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
21557 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
21558 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
21560 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
21561 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
21563 as_bad (_("%s: unexpected function type: %d"),
21564 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
21566 else switch (S_GET_STORAGE_CLASS (sym
))
21569 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
21572 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
21575 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
21583 if (ARM_IS_INTERWORK (sym
))
21584 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
21591 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21593 if (ARM_IS_THUMB (sym
))
21595 elf_symbol_type
* elf_sym
;
21597 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
21598 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
21600 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
21601 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
21603 /* If it's a .thumb_func, declare it as so,
21604 otherwise tag label as .code 16. */
21605 if (THUMB_IS_FUNC (sym
))
21606 elf_sym
->internal_elf_sym
.st_info
=
21607 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
21608 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
21609 elf_sym
->internal_elf_sym
.st_info
=
21610 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
21615 /* Remove any overlapping mapping symbols generated by alignment frags. */
21616 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
21620 /* MD interface: Initialization. */
21623 set_constant_flonums (void)
21627 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
21628 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
21632 /* Auto-select Thumb mode if it's the only available instruction set for the
21633 given architecture. */
21636 autoselect_thumb_from_cpu_variant (void)
21638 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
21639 opcode_select (16);
21648 if ( (arm_ops_hsh
= hash_new ()) == NULL
21649 || (arm_cond_hsh
= hash_new ()) == NULL
21650 || (arm_shift_hsh
= hash_new ()) == NULL
21651 || (arm_psr_hsh
= hash_new ()) == NULL
21652 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
21653 || (arm_reg_hsh
= hash_new ()) == NULL
21654 || (arm_reloc_hsh
= hash_new ()) == NULL
21655 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
21656 as_fatal (_("virtual memory exhausted"));
21658 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
21659 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
21660 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
21661 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
21662 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
21663 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
21664 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
21665 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
21666 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
21667 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
21668 (void *) (v7m_psrs
+ i
));
21669 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
21670 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
21672 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
21674 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
21675 (void *) (barrier_opt_names
+ i
));
21677 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
21678 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
21681 set_constant_flonums ();
21683 /* Set the cpu variant based on the command-line options. We prefer
21684 -mcpu= over -march= if both are set (as for GCC); and we prefer
21685 -mfpu= over any other way of setting the floating point unit.
21686 Use of legacy options with new options are faulted. */
21689 if (mcpu_cpu_opt
|| march_cpu_opt
)
21690 as_bad (_("use of old and new-style options to set CPU type"));
21692 mcpu_cpu_opt
= legacy_cpu
;
21694 else if (!mcpu_cpu_opt
)
21695 mcpu_cpu_opt
= march_cpu_opt
;
21700 as_bad (_("use of old and new-style options to set FPU type"));
21702 mfpu_opt
= legacy_fpu
;
21704 else if (!mfpu_opt
)
21706 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
21707 || defined (TE_NetBSD) || defined (TE_VXWORKS))
21708 /* Some environments specify a default FPU. If they don't, infer it
21709 from the processor. */
21711 mfpu_opt
= mcpu_fpu_opt
;
21713 mfpu_opt
= march_fpu_opt
;
21715 mfpu_opt
= &fpu_default
;
21721 if (mcpu_cpu_opt
!= NULL
)
21722 mfpu_opt
= &fpu_default
;
21723 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
21724 mfpu_opt
= &fpu_arch_vfp_v2
;
21726 mfpu_opt
= &fpu_arch_fpa
;
21732 mcpu_cpu_opt
= &cpu_default
;
21733 selected_cpu
= cpu_default
;
21737 selected_cpu
= *mcpu_cpu_opt
;
21739 mcpu_cpu_opt
= &arm_arch_any
;
21742 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21744 autoselect_thumb_from_cpu_variant ();
21746 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
21748 #if defined OBJ_COFF || defined OBJ_ELF
21750 unsigned int flags
= 0;
21752 #if defined OBJ_ELF
21753 flags
= meabi_flags
;
21755 switch (meabi_flags
)
21757 case EF_ARM_EABI_UNKNOWN
:
21759 /* Set the flags in the private structure. */
21760 if (uses_apcs_26
) flags
|= F_APCS26
;
21761 if (support_interwork
) flags
|= F_INTERWORK
;
21762 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
21763 if (pic_code
) flags
|= F_PIC
;
21764 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
21765 flags
|= F_SOFT_FLOAT
;
21767 switch (mfloat_abi_opt
)
21769 case ARM_FLOAT_ABI_SOFT
:
21770 case ARM_FLOAT_ABI_SOFTFP
:
21771 flags
|= F_SOFT_FLOAT
;
21774 case ARM_FLOAT_ABI_HARD
:
21775 if (flags
& F_SOFT_FLOAT
)
21776 as_bad (_("hard-float conflicts with specified fpu"));
21780 /* Using pure-endian doubles (even if soft-float). */
21781 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
21782 flags
|= F_VFP_FLOAT
;
21784 #if defined OBJ_ELF
21785 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
21786 flags
|= EF_ARM_MAVERICK_FLOAT
;
21789 case EF_ARM_EABI_VER4
:
21790 case EF_ARM_EABI_VER5
:
21791 /* No additional flags to set. */
21798 bfd_set_private_flags (stdoutput
, flags
);
21800 /* We have run out flags in the COFF header to encode the
21801 status of ATPCS support, so instead we create a dummy,
21802 empty, debug section called .arm.atpcs. */
21807 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
21811 bfd_set_section_flags
21812 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
21813 bfd_set_section_size (stdoutput
, sec
, 0);
21814 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
21820 /* Record the CPU type as well. */
21821 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
21822 mach
= bfd_mach_arm_iWMMXt2
;
21823 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
21824 mach
= bfd_mach_arm_iWMMXt
;
21825 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
21826 mach
= bfd_mach_arm_XScale
;
21827 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
21828 mach
= bfd_mach_arm_ep9312
;
21829 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
21830 mach
= bfd_mach_arm_5TE
;
21831 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
21833 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21834 mach
= bfd_mach_arm_5T
;
21836 mach
= bfd_mach_arm_5
;
21838 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
21840 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21841 mach
= bfd_mach_arm_4T
;
21843 mach
= bfd_mach_arm_4
;
21845 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
21846 mach
= bfd_mach_arm_3M
;
21847 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
21848 mach
= bfd_mach_arm_3
;
21849 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
21850 mach
= bfd_mach_arm_2a
;
21851 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
21852 mach
= bfd_mach_arm_2
;
21854 mach
= bfd_mach_arm_unknown
;
21856 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
21859 /* Command line processing. */
21862 Invocation line includes a switch not recognized by the base assembler.
21863 See if it's a processor-specific option.
21865 This routine is somewhat complicated by the need for backwards
21866 compatibility (since older releases of gcc can't be changed).
21867 The new options try to make the interface as compatible as
21870 New options (supported) are:
21872 -mcpu=<cpu name> Assemble for selected processor
21873 -march=<architecture name> Assemble for selected architecture
21874 -mfpu=<fpu architecture> Assemble for selected FPU.
21875 -EB/-mbig-endian Big-endian
21876 -EL/-mlittle-endian Little-endian
21877 -k Generate PIC code
21878 -mthumb Start in Thumb mode
21879 -mthumb-interwork Code supports ARM/Thumb interworking
21881 -m[no-]warn-deprecated Warn about deprecated features
21883 For now we will also provide support for:
21885 -mapcs-32 32-bit Program counter
21886 -mapcs-26 26-bit Program counter
21887 -macps-float Floats passed in FP registers
21888 -mapcs-reentrant Reentrant code
21890 (sometime these will probably be replaced with -mapcs=<list of options>
21891 and -matpcs=<list of options>)
21893 The remaining options are only supported for back-wards compatibility.
21894 Cpu variants, the arm part is optional:
21895 -m[arm]1 Currently not supported.
21896 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
21897 -m[arm]3 Arm 3 processor
21898 -m[arm]6[xx], Arm 6 processors
21899 -m[arm]7[xx][t][[d]m] Arm 7 processors
21900 -m[arm]8[10] Arm 8 processors
21901 -m[arm]9[20][tdmi] Arm 9 processors
21902 -mstrongarm[110[0]] StrongARM processors
21903 -mxscale XScale processors
21904 -m[arm]v[2345[t[e]]] Arm architectures
21905 -mall All (except the ARM1)
21907 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
21908 -mfpe-old (No float load/store multiples)
21909 -mvfpxd VFP Single precision
21911 -mno-fpu Disable all floating point instructions
21913 The following CPU names are recognized:
21914 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
21915 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
21916 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
21917 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
21918 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
21919 arm10t arm10e, arm1020t, arm1020e, arm10200e,
21920 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
21924 const char * md_shortopts
= "m:k";
21926 #ifdef ARM_BI_ENDIAN
21927 #define OPTION_EB (OPTION_MD_BASE + 0)
21928 #define OPTION_EL (OPTION_MD_BASE + 1)
21930 #if TARGET_BYTES_BIG_ENDIAN
21931 #define OPTION_EB (OPTION_MD_BASE + 0)
21933 #define OPTION_EL (OPTION_MD_BASE + 1)
21936 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
21938 struct option md_longopts
[] =
21941 {"EB", no_argument
, NULL
, OPTION_EB
},
21944 {"EL", no_argument
, NULL
, OPTION_EL
},
21946 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
21947 {NULL
, no_argument
, NULL
, 0}
21950 size_t md_longopts_size
= sizeof (md_longopts
);
21952 struct arm_option_table
21954 char *option
; /* Option name to match. */
21955 char *help
; /* Help information. */
21956 int *var
; /* Variable to change. */
21957 int value
; /* What to change it to. */
21958 char *deprecated
; /* If non-null, print this message. */
21961 struct arm_option_table arm_opts
[] =
21963 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
21964 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
21965 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
21966 &support_interwork
, 1, NULL
},
21967 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
21968 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
21969 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
21971 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
21972 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
21973 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
21974 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
21977 /* These are recognized by the assembler, but have no affect on code. */
21978 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
21979 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
21981 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
21982 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
21983 &warn_on_deprecated
, 0, NULL
},
21984 {NULL
, NULL
, NULL
, 0, NULL
}
21987 struct arm_legacy_option_table
21989 char *option
; /* Option name to match. */
21990 const arm_feature_set
**var
; /* Variable to change. */
21991 const arm_feature_set value
; /* What to change it to. */
21992 char *deprecated
; /* If non-null, print this message. */
21995 const struct arm_legacy_option_table arm_legacy_opts
[] =
21997 /* DON'T add any new processors to this list -- we want the whole list
21998 to go away... Add them to the processors table instead. */
21999 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22000 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22001 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22002 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22003 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22004 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22005 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22006 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22007 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22008 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22009 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22010 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22011 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22012 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22013 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22014 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22015 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22016 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22017 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22018 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22019 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22020 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22021 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22022 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22023 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22024 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22025 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22026 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22027 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22028 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22029 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22030 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22031 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22032 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22033 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22034 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22035 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22036 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22037 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22038 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22039 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22040 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22041 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22042 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22043 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22044 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22045 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22046 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22047 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22048 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22049 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22050 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22051 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22052 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22053 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22054 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22055 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22056 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22057 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22058 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22059 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22060 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22061 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22062 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22063 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22064 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22065 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22066 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22067 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
22068 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
22069 N_("use -mcpu=strongarm110")},
22070 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
22071 N_("use -mcpu=strongarm1100")},
22072 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
22073 N_("use -mcpu=strongarm1110")},
22074 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
22075 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
22076 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
22078 /* Architecture variants -- don't add any more to this list either. */
22079 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22080 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22081 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22082 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22083 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22084 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22085 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22086 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22087 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22088 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22089 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22090 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22091 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22092 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22093 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22094 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22095 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22096 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22098 /* Floating point variants -- don't add any more to this list either. */
22099 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
22100 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
22101 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
22102 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
22103 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22105 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
22108 struct arm_cpu_option_table
22111 const arm_feature_set value
;
22112 /* For some CPUs we assume an FPU unless the user explicitly sets
22114 const arm_feature_set default_fpu
;
22115 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22117 const char *canonical_name
;
22120 /* This list should, at a minimum, contain all the cpu names
22121 recognized by GCC. */
22122 static const struct arm_cpu_option_table arm_cpus
[] =
22124 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
22125 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
22126 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
22127 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22128 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22129 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22130 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22131 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22132 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22133 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22134 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22135 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22136 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22137 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22138 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22139 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22140 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22141 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22142 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22143 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22144 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22145 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22146 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22147 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22148 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22149 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22150 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22151 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22152 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22153 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22154 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22155 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22156 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22157 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22158 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22159 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22160 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22161 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22162 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22163 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
22164 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22165 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22166 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22167 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22168 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22169 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22170 /* For V5 or later processors we default to using VFP; but the user
22171 should really set the FPU type explicitly. */
22172 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22173 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22174 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22175 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22176 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22177 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22178 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
22179 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22180 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22181 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
22182 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22183 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22184 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22185 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22186 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22187 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
22188 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22189 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22190 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22191 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
22192 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22193 {"fa626te", ARM_ARCH_V5TE
, FPU_NONE
, NULL
},
22194 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22195 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
22196 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
22197 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
22198 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
22199 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
22200 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
22201 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
22202 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
22203 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
22204 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
22205 {"cortex-a5", ARM_ARCH_V7A
, FPU_NONE
, NULL
},
22206 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
22207 | FPU_NEON_EXT_V1
),
22209 {"cortex-a9", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
22210 | FPU_NEON_EXT_V1
),
22212 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
22213 {"cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
, NULL
},
22214 {"cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, NULL
},
22215 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
22216 {"cortex-m1", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
22217 {"cortex-m0", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
22218 /* ??? XSCALE is really an architecture. */
22219 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22220 /* ??? iwmmxt is not a processor. */
22221 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
22222 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
22223 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22225 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
22226 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
22229 struct arm_arch_option_table
22232 const arm_feature_set value
;
22233 const arm_feature_set default_fpu
;
22236 /* This list should, at a minimum, contain all the architecture names
22237 recognized by GCC. */
22238 static const struct arm_arch_option_table arm_archs
[] =
22240 {"all", ARM_ANY
, FPU_ARCH_FPA
},
22241 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
22242 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
22243 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22244 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22245 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
22246 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
22247 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
22248 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
22249 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
22250 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
22251 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
22252 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
22253 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
22254 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
22255 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
22256 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
22257 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22258 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22259 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
22260 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
22261 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
22262 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
22263 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
22264 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
22265 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
22266 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
22267 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
22268 /* The official spelling of the ARMv7 profile variants is the dashed form.
22269 Accept the non-dashed form for compatibility with old toolchains. */
22270 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22271 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22272 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22273 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22274 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22275 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22276 {"armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
},
22277 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
22278 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
22279 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
22280 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22283 /* ISA extensions in the co-processor space. */
22284 struct arm_option_cpu_value_table
22287 const arm_feature_set value
;
22290 static const struct arm_option_cpu_value_table arm_extensions
[] =
22292 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
22293 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
22294 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
22295 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
22296 {NULL
, ARM_ARCH_NONE
}
22299 /* This list should, at a minimum, contain all the fpu names
22300 recognized by GCC. */
22301 static const struct arm_option_cpu_value_table arm_fpus
[] =
22303 {"softfpa", FPU_NONE
},
22304 {"fpe", FPU_ARCH_FPE
},
22305 {"fpe2", FPU_ARCH_FPE
},
22306 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
22307 {"fpa", FPU_ARCH_FPA
},
22308 {"fpa10", FPU_ARCH_FPA
},
22309 {"fpa11", FPU_ARCH_FPA
},
22310 {"arm7500fe", FPU_ARCH_FPA
},
22311 {"softvfp", FPU_ARCH_VFP
},
22312 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
22313 {"vfp", FPU_ARCH_VFP_V2
},
22314 {"vfp9", FPU_ARCH_VFP_V2
},
22315 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
22316 {"vfp10", FPU_ARCH_VFP_V2
},
22317 {"vfp10-r0", FPU_ARCH_VFP_V1
},
22318 {"vfpxd", FPU_ARCH_VFP_V1xD
},
22319 {"vfpv2", FPU_ARCH_VFP_V2
},
22320 {"vfpv3", FPU_ARCH_VFP_V3
},
22321 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
22322 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
22323 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
22324 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
22325 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
22326 {"arm1020t", FPU_ARCH_VFP_V1
},
22327 {"arm1020e", FPU_ARCH_VFP_V2
},
22328 {"arm1136jfs", FPU_ARCH_VFP_V2
},
22329 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
22330 {"maverick", FPU_ARCH_MAVERICK
},
22331 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
22332 {"neon-fp16", FPU_ARCH_NEON_FP16
},
22333 {"vfpv4", FPU_ARCH_VFP_V4
},
22334 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
22335 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
22336 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
22337 {NULL
, ARM_ARCH_NONE
}
22340 struct arm_option_value_table
22346 static const struct arm_option_value_table arm_float_abis
[] =
22348 {"hard", ARM_FLOAT_ABI_HARD
},
22349 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
22350 {"soft", ARM_FLOAT_ABI_SOFT
},
22355 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
22356 static const struct arm_option_value_table arm_eabis
[] =
22358 {"gnu", EF_ARM_EABI_UNKNOWN
},
22359 {"4", EF_ARM_EABI_VER4
},
22360 {"5", EF_ARM_EABI_VER5
},
22365 struct arm_long_option_table
22367 char * option
; /* Substring to match. */
22368 char * help
; /* Help information. */
22369 int (* func
) (char * subopt
); /* Function to decode sub-option. */
22370 char * deprecated
; /* If non-null, print this message. */
22374 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
22376 arm_feature_set
*ext_set
= (arm_feature_set
*)
22377 xmalloc (sizeof (arm_feature_set
));
22379 /* Copy the feature set, so that we can modify it. */
22380 *ext_set
= **opt_p
;
22383 while (str
!= NULL
&& *str
!= 0)
22385 const struct arm_option_cpu_value_table
* opt
;
22391 as_bad (_("invalid architectural extension"));
22396 ext
= strchr (str
, '+');
22399 optlen
= ext
- str
;
22401 optlen
= strlen (str
);
22405 as_bad (_("missing architectural extension"));
22409 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
22410 if (strncmp (opt
->name
, str
, optlen
) == 0)
22412 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
22416 if (opt
->name
== NULL
)
22418 as_bad (_("unknown architectural extension `%s'"), str
);
22429 arm_parse_cpu (char * str
)
22431 const struct arm_cpu_option_table
* opt
;
22432 char * ext
= strchr (str
, '+');
22436 optlen
= ext
- str
;
22438 optlen
= strlen (str
);
22442 as_bad (_("missing cpu name `%s'"), str
);
22446 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
22447 if (strncmp (opt
->name
, str
, optlen
) == 0)
22449 mcpu_cpu_opt
= &opt
->value
;
22450 mcpu_fpu_opt
= &opt
->default_fpu
;
22451 if (opt
->canonical_name
)
22452 strcpy (selected_cpu_name
, opt
->canonical_name
);
22457 for (i
= 0; i
< optlen
; i
++)
22458 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22459 selected_cpu_name
[i
] = 0;
22463 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
22468 as_bad (_("unknown cpu `%s'"), str
);
22473 arm_parse_arch (char * str
)
22475 const struct arm_arch_option_table
*opt
;
22476 char *ext
= strchr (str
, '+');
22480 optlen
= ext
- str
;
22482 optlen
= strlen (str
);
22486 as_bad (_("missing architecture name `%s'"), str
);
22490 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
22491 if (streq (opt
->name
, str
))
22493 march_cpu_opt
= &opt
->value
;
22494 march_fpu_opt
= &opt
->default_fpu
;
22495 strcpy (selected_cpu_name
, opt
->name
);
22498 return arm_parse_extension (ext
, &march_cpu_opt
);
22503 as_bad (_("unknown architecture `%s'\n"), str
);
22508 arm_parse_fpu (char * str
)
22510 const struct arm_option_cpu_value_table
* opt
;
22512 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22513 if (streq (opt
->name
, str
))
22515 mfpu_opt
= &opt
->value
;
22519 as_bad (_("unknown floating point format `%s'\n"), str
);
22524 arm_parse_float_abi (char * str
)
22526 const struct arm_option_value_table
* opt
;
22528 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
22529 if (streq (opt
->name
, str
))
22531 mfloat_abi_opt
= opt
->value
;
22535 as_bad (_("unknown floating point abi `%s'\n"), str
);
22541 arm_parse_eabi (char * str
)
22543 const struct arm_option_value_table
*opt
;
22545 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
22546 if (streq (opt
->name
, str
))
22548 meabi_flags
= opt
->value
;
22551 as_bad (_("unknown EABI `%s'\n"), str
);
22557 arm_parse_it_mode (char * str
)
22559 bfd_boolean ret
= TRUE
;
22561 if (streq ("arm", str
))
22562 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
22563 else if (streq ("thumb", str
))
22564 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
22565 else if (streq ("always", str
))
22566 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
22567 else if (streq ("never", str
))
22568 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
22571 as_bad (_("unknown implicit IT mode `%s', should be "\
22572 "arm, thumb, always, or never."), str
);
22579 struct arm_long_option_table arm_long_opts
[] =
22581 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
22582 arm_parse_cpu
, NULL
},
22583 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
22584 arm_parse_arch
, NULL
},
22585 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
22586 arm_parse_fpu
, NULL
},
22587 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
22588 arm_parse_float_abi
, NULL
},
22590 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
22591 arm_parse_eabi
, NULL
},
22593 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
22594 arm_parse_it_mode
, NULL
},
22595 {NULL
, NULL
, 0, NULL
}
22599 md_parse_option (int c
, char * arg
)
22601 struct arm_option_table
*opt
;
22602 const struct arm_legacy_option_table
*fopt
;
22603 struct arm_long_option_table
*lopt
;
22609 target_big_endian
= 1;
22615 target_big_endian
= 0;
22619 case OPTION_FIX_V4BX
:
22624 /* Listing option. Just ignore these, we don't support additional
22629 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22631 if (c
== opt
->option
[0]
22632 && ((arg
== NULL
&& opt
->option
[1] == 0)
22633 || streq (arg
, opt
->option
+ 1)))
22635 /* If the option is deprecated, tell the user. */
22636 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
22637 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22638 arg
? arg
: "", _(opt
->deprecated
));
22640 if (opt
->var
!= NULL
)
22641 *opt
->var
= opt
->value
;
22647 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
22649 if (c
== fopt
->option
[0]
22650 && ((arg
== NULL
&& fopt
->option
[1] == 0)
22651 || streq (arg
, fopt
->option
+ 1)))
22653 /* If the option is deprecated, tell the user. */
22654 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
22655 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22656 arg
? arg
: "", _(fopt
->deprecated
));
22658 if (fopt
->var
!= NULL
)
22659 *fopt
->var
= &fopt
->value
;
22665 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22667 /* These options are expected to have an argument. */
22668 if (c
== lopt
->option
[0]
22670 && strncmp (arg
, lopt
->option
+ 1,
22671 strlen (lopt
->option
+ 1)) == 0)
22673 /* If the option is deprecated, tell the user. */
22674 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
22675 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
22676 _(lopt
->deprecated
));
22678 /* Call the sup-option parser. */
22679 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
22690 md_show_usage (FILE * fp
)
22692 struct arm_option_table
*opt
;
22693 struct arm_long_option_table
*lopt
;
22695 fprintf (fp
, _(" ARM-specific assembler options:\n"));
22697 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22698 if (opt
->help
!= NULL
)
22699 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
22701 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22702 if (lopt
->help
!= NULL
)
22703 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
22707 -EB assemble code for a big-endian cpu\n"));
22712 -EL assemble code for a little-endian cpu\n"));
22716 --fix-v4bx Allow BX in ARMv4 code\n"));
22724 arm_feature_set flags
;
22725 } cpu_arch_ver_table
;
22727 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
22728 least features first. */
22729 static const cpu_arch_ver_table cpu_arch_ver
[] =
22735 {4, ARM_ARCH_V5TE
},
22736 {5, ARM_ARCH_V5TEJ
},
22740 {11, ARM_ARCH_V6M
},
22741 {8, ARM_ARCH_V6T2
},
22742 {10, ARM_ARCH_V7A
},
22743 {10, ARM_ARCH_V7R
},
22744 {10, ARM_ARCH_V7M
},
22748 /* Set an attribute if it has not already been set by the user. */
22750 aeabi_set_attribute_int (int tag
, int value
)
22753 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22754 || !attributes_set_explicitly
[tag
])
22755 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
22759 aeabi_set_attribute_string (int tag
, const char *value
)
22762 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22763 || !attributes_set_explicitly
[tag
])
22764 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
22767 /* Set the public EABI object attributes. */
22769 aeabi_set_public_attributes (void)
22772 arm_feature_set flags
;
22773 arm_feature_set tmp
;
22774 const cpu_arch_ver_table
*p
;
22776 /* Choose the architecture based on the capabilities of the requested cpu
22777 (if any) and/or the instructions actually used. */
22778 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
22779 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
22780 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
22781 /*Allow the user to override the reported architecture. */
22784 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
22785 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
22790 for (p
= cpu_arch_ver
; p
->val
; p
++)
22792 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
22795 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
22799 /* The table lookup above finds the last architecture to contribute
22800 a new feature. Unfortunately, Tag13 is a subset of the union of
22801 v6T2 and v7-M, so it is never seen as contributing a new feature.
22802 We can not search for the last entry which is entirely used,
22803 because if no CPU is specified we build up only those flags
22804 actually used. Perhaps we should separate out the specified
22805 and implicit cases. Avoid taking this path for -march=all by
22806 checking for contradictory v7-A / v7-M features. */
22808 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
22809 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
22810 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
22813 /* Tag_CPU_name. */
22814 if (selected_cpu_name
[0])
22818 q
= selected_cpu_name
;
22819 if (strncmp (q
, "armv", 4) == 0)
22824 for (i
= 0; q
[i
]; i
++)
22825 q
[i
] = TOUPPER (q
[i
]);
22827 aeabi_set_attribute_string (Tag_CPU_name
, q
);
22830 /* Tag_CPU_arch. */
22831 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
22833 /* Tag_CPU_arch_profile. */
22834 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
22835 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
22836 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
22837 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
22838 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
22839 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
22841 /* Tag_ARM_ISA_use. */
22842 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
22844 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
22846 /* Tag_THUMB_ISA_use. */
22847 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
22849 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
22850 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
22852 /* Tag_VFP_arch. */
22853 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
22854 aeabi_set_attribute_int (Tag_VFP_arch
,
22855 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
22857 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
22858 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
22859 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
22860 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
22861 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
22862 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
22863 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
22864 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
22865 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
22867 /* Tag_ABI_HardFP_use. */
22868 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
22869 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
22870 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
22872 /* Tag_WMMX_arch. */
22873 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
22874 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
22875 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
22876 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
22878 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
22879 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
22880 aeabi_set_attribute_int
22881 (Tag_Advanced_SIMD_arch
, (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
)
22884 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
22885 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
))
22886 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
22889 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
))
22890 aeabi_set_attribute_int (Tag_DIV_use
, 0);
22891 /* Fill this in when gas supports v7a sdiv/udiv.
22892 else if (... v7a with div extension used ...)
22893 aeabi_set_attribute_int (Tag_DIV_use, 2); */
22895 aeabi_set_attribute_int (Tag_DIV_use
, 1);
22898 /* Add the default contents for the .ARM.attributes section. */
22902 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
22905 aeabi_set_public_attributes ();
22907 #endif /* OBJ_ELF */
22910 /* Parse a .cpu directive. */
22913 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
22915 const struct arm_cpu_option_table
*opt
;
22919 name
= input_line_pointer
;
22920 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22921 input_line_pointer
++;
22922 saved_char
= *input_line_pointer
;
22923 *input_line_pointer
= 0;
22925 /* Skip the first "all" entry. */
22926 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
22927 if (streq (opt
->name
, name
))
22929 mcpu_cpu_opt
= &opt
->value
;
22930 selected_cpu
= opt
->value
;
22931 if (opt
->canonical_name
)
22932 strcpy (selected_cpu_name
, opt
->canonical_name
);
22936 for (i
= 0; opt
->name
[i
]; i
++)
22937 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22938 selected_cpu_name
[i
] = 0;
22940 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22941 *input_line_pointer
= saved_char
;
22942 demand_empty_rest_of_line ();
22945 as_bad (_("unknown cpu `%s'"), name
);
22946 *input_line_pointer
= saved_char
;
22947 ignore_rest_of_line ();
22951 /* Parse a .arch directive. */
22954 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
22956 const struct arm_arch_option_table
*opt
;
22960 name
= input_line_pointer
;
22961 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22962 input_line_pointer
++;
22963 saved_char
= *input_line_pointer
;
22964 *input_line_pointer
= 0;
22966 /* Skip the first "all" entry. */
22967 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
22968 if (streq (opt
->name
, name
))
22970 mcpu_cpu_opt
= &opt
->value
;
22971 selected_cpu
= opt
->value
;
22972 strcpy (selected_cpu_name
, opt
->name
);
22973 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22974 *input_line_pointer
= saved_char
;
22975 demand_empty_rest_of_line ();
22979 as_bad (_("unknown architecture `%s'\n"), name
);
22980 *input_line_pointer
= saved_char
;
22981 ignore_rest_of_line ();
22985 /* Parse a .object_arch directive. */
22988 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
22990 const struct arm_arch_option_table
*opt
;
22994 name
= input_line_pointer
;
22995 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22996 input_line_pointer
++;
22997 saved_char
= *input_line_pointer
;
22998 *input_line_pointer
= 0;
23000 /* Skip the first "all" entry. */
23001 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23002 if (streq (opt
->name
, name
))
23004 object_arch
= &opt
->value
;
23005 *input_line_pointer
= saved_char
;
23006 demand_empty_rest_of_line ();
23010 as_bad (_("unknown architecture `%s'\n"), name
);
23011 *input_line_pointer
= saved_char
;
23012 ignore_rest_of_line ();
23015 /* Parse a .fpu directive. */
23018 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
23020 const struct arm_option_cpu_value_table
*opt
;
23024 name
= input_line_pointer
;
23025 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23026 input_line_pointer
++;
23027 saved_char
= *input_line_pointer
;
23028 *input_line_pointer
= 0;
23030 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
23031 if (streq (opt
->name
, name
))
23033 mfpu_opt
= &opt
->value
;
23034 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23035 *input_line_pointer
= saved_char
;
23036 demand_empty_rest_of_line ();
23040 as_bad (_("unknown floating point format `%s'\n"), name
);
23041 *input_line_pointer
= saved_char
;
23042 ignore_rest_of_line ();
23045 /* Copy symbol information. */
23048 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
23050 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
23054 /* Given a symbolic attribute NAME, return the proper integer value.
23055 Returns -1 if the attribute is not known. */
23058 arm_convert_symbolic_attribute (const char *name
)
23060 static const struct
23065 attribute_table
[] =
23067 /* When you modify this table you should
23068 also modify the list in doc/c-arm.texi. */
23069 #define T(tag) {#tag, tag}
23070 T (Tag_CPU_raw_name
),
23073 T (Tag_CPU_arch_profile
),
23074 T (Tag_ARM_ISA_use
),
23075 T (Tag_THUMB_ISA_use
),
23079 T (Tag_Advanced_SIMD_arch
),
23080 T (Tag_PCS_config
),
23081 T (Tag_ABI_PCS_R9_use
),
23082 T (Tag_ABI_PCS_RW_data
),
23083 T (Tag_ABI_PCS_RO_data
),
23084 T (Tag_ABI_PCS_GOT_use
),
23085 T (Tag_ABI_PCS_wchar_t
),
23086 T (Tag_ABI_FP_rounding
),
23087 T (Tag_ABI_FP_denormal
),
23088 T (Tag_ABI_FP_exceptions
),
23089 T (Tag_ABI_FP_user_exceptions
),
23090 T (Tag_ABI_FP_number_model
),
23091 T (Tag_ABI_align_needed
),
23092 T (Tag_ABI_align8_needed
),
23093 T (Tag_ABI_align_preserved
),
23094 T (Tag_ABI_align8_preserved
),
23095 T (Tag_ABI_enum_size
),
23096 T (Tag_ABI_HardFP_use
),
23097 T (Tag_ABI_VFP_args
),
23098 T (Tag_ABI_WMMX_args
),
23099 T (Tag_ABI_optimization_goals
),
23100 T (Tag_ABI_FP_optimization_goals
),
23101 T (Tag_compatibility
),
23102 T (Tag_CPU_unaligned_access
),
23103 T (Tag_FP_HP_extension
),
23104 T (Tag_VFP_HP_extension
),
23105 T (Tag_ABI_FP_16bit_format
),
23106 T (Tag_MPextension_use
),
23108 T (Tag_nodefaults
),
23109 T (Tag_also_compatible_with
),
23110 T (Tag_conformance
),
23112 T (Tag_Virtualization_use
),
23113 /* We deliberately do not include Tag_MPextension_use_legacy. */
23121 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
23122 if (streq (name
, attribute_table
[i
].name
))
23123 return attribute_table
[i
].tag
;
23129 /* Apply sym value for relocations only in the case that
23130 they are for local symbols and you have the respective
23131 architectural feature for blx and simple switches. */
23133 arm_apply_sym_value (struct fix
* fixP
)
23136 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23137 && !S_IS_EXTERNAL (fixP
->fx_addsy
))
23139 switch (fixP
->fx_r_type
)
23141 case BFD_RELOC_ARM_PCREL_BLX
:
23142 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23143 if (ARM_IS_FUNC (fixP
->fx_addsy
))
23147 case BFD_RELOC_ARM_PCREL_CALL
:
23148 case BFD_RELOC_THUMB_PCREL_BLX
:
23149 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
23160 #endif /* OBJ_ELF */