1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
45 #define WARN_DEPRECATED 1
48 /* Must be at least the size of the largest unwind opcode (currently two). */
49 #define ARM_OPCODE_CHUNK_SIZE 8
51 /* This structure holds the unwinding state. */
56 symbolS
* table_entry
;
57 symbolS
* personality_routine
;
58 int personality_index
;
59 /* The segment containing the function. */
62 /* Opcodes generated from this function. */
63 unsigned char * opcodes
;
66 /* The number of bytes pushed to the stack. */
68 /* We don't add stack adjustment opcodes immediately so that we can merge
69 multiple adjustments. We can also omit the final adjustment
70 when using a frame pointer. */
71 offsetT pending_offset
;
72 /* These two fields are set by both unwind_movsp and unwind_setfp. They
73 hold the reg+offset to use when restoring sp from a frame pointer. */
76 /* Nonzero if an unwind_setfp directive has been seen. */
78 /* Nonzero if the last opcode restores sp from fp_reg. */
79 unsigned sp_restored
:1;
82 /* Bit N indicates that an R_ARM_NONE relocation has been output for
83 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
84 emitted only once per section, to save unnecessary bloat. */
85 static unsigned int marked_pr_dependency
= 0;
89 /* Results from operand parsing worker functions. */
93 PARSE_OPERAND_SUCCESS
,
95 PARSE_OPERAND_FAIL_NO_BACKTRACK
96 } parse_operand_result
;
101 ARM_FLOAT_ABI_SOFTFP
,
105 /* Types of processor to assemble for. */
107 #if defined __XSCALE__
108 #define CPU_DEFAULT ARM_ARCH_XSCALE
110 #if defined __thumb__
111 #define CPU_DEFAULT ARM_ARCH_V5T
118 # define FPU_DEFAULT FPU_ARCH_FPA
119 # elif defined (TE_NetBSD)
121 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
123 /* Legacy a.out format. */
124 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
126 # elif defined (TE_VXWORKS)
127 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
129 /* For backwards compatibility, default to FPA. */
130 # define FPU_DEFAULT FPU_ARCH_FPA
132 #endif /* ifndef FPU_DEFAULT */
134 #define streq(a, b) (strcmp (a, b) == 0)
136 static arm_feature_set cpu_variant
;
137 static arm_feature_set arm_arch_used
;
138 static arm_feature_set thumb_arch_used
;
140 /* Flags stored in private area of BFD structure. */
141 static int uses_apcs_26
= FALSE
;
142 static int atpcs
= FALSE
;
143 static int support_interwork
= FALSE
;
144 static int uses_apcs_float
= FALSE
;
145 static int pic_code
= FALSE
;
146 static int fix_v4bx
= FALSE
;
148 /* Variables that we set while parsing command-line options. Once all
149 options have been read we re-process these values to set the real
151 static const arm_feature_set
*legacy_cpu
= NULL
;
152 static const arm_feature_set
*legacy_fpu
= NULL
;
154 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
155 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
156 static const arm_feature_set
*march_cpu_opt
= NULL
;
157 static const arm_feature_set
*march_fpu_opt
= NULL
;
158 static const arm_feature_set
*mfpu_opt
= NULL
;
159 static const arm_feature_set
*object_arch
= NULL
;
161 /* Constants for known architecture features. */
162 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
163 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
164 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
165 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
166 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
167 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
168 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
169 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
170 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
173 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
176 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
177 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
178 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
179 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
180 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
181 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
182 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
183 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
184 static const arm_feature_set arm_ext_v4t_5
=
185 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
186 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
187 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
188 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
189 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
190 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
191 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
192 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
193 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
194 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
195 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
196 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
197 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
198 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
199 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
201 static const arm_feature_set arm_arch_any
= ARM_ANY
;
202 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
203 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
204 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
206 static const arm_feature_set arm_cext_iwmmxt2
=
207 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
208 static const arm_feature_set arm_cext_iwmmxt
=
209 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
210 static const arm_feature_set arm_cext_xscale
=
211 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
212 static const arm_feature_set arm_cext_maverick
=
213 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
214 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
215 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
216 static const arm_feature_set fpu_vfp_ext_v1xd
=
217 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
218 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
219 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
220 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
221 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
222 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
223 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
225 static int mfloat_abi_opt
= -1;
226 /* Record user cpu selection for object attributes. */
227 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
228 /* Must be long enough to hold any of the names in arm_cpus. */
229 static char selected_cpu_name
[16];
232 static int meabi_flags
= EABI_DEFAULT
;
234 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
240 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
245 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
246 symbolS
* GOT_symbol
;
249 /* 0: assemble for ARM,
250 1: assemble for Thumb,
251 2: assemble for Thumb even though target CPU does not support thumb
253 static int thumb_mode
= 0;
255 /* If unified_syntax is true, we are processing the new unified
256 ARM/Thumb syntax. Important differences from the old ARM mode:
258 - Immediate operands do not require a # prefix.
259 - Conditional affixes always appear at the end of the
260 instruction. (For backward compatibility, those instructions
261 that formerly had them in the middle, continue to accept them
263 - The IT instruction may appear, and if it does is validated
264 against subsequent conditional affixes. It does not generate
267 Important differences from the old Thumb mode:
269 - Immediate operands do not require a # prefix.
270 - Most of the V6T2 instructions are only available in unified mode.
271 - The .N and .W suffixes are recognized and honored (it is an error
272 if they cannot be honored).
273 - All instructions set the flags if and only if they have an 's' affix.
274 - Conditional affixes may be used. They are validated against
275 preceding IT instructions. Unlike ARM mode, you cannot use a
276 conditional affix except in the scope of an IT instruction. */
278 static bfd_boolean unified_syntax
= FALSE
;
293 enum neon_el_type type
;
297 #define NEON_MAX_TYPE_ELS 4
301 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
308 unsigned long instruction
;
312 /* "uncond_value" is set to the value in place of the conditional field in
313 unconditional versions of the instruction, or -1 if nothing is
316 struct neon_type vectype
;
317 /* Set to the opcode if the instruction needs relaxation.
318 Zero if the instruction is not relaxed. */
322 bfd_reloc_code_real_type type
;
331 struct neon_type_el vectype
;
332 unsigned present
: 1; /* Operand present. */
333 unsigned isreg
: 1; /* Operand was a register. */
334 unsigned immisreg
: 1; /* .imm field is a second register. */
335 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
336 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
337 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
338 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
339 instructions. This allows us to disambiguate ARM <-> vector insns. */
340 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
341 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
342 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
343 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
344 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
345 unsigned writeback
: 1; /* Operand has trailing ! */
346 unsigned preind
: 1; /* Preindexed address. */
347 unsigned postind
: 1; /* Postindexed address. */
348 unsigned negative
: 1; /* Index register was negated. */
349 unsigned shifted
: 1; /* Shift applied to operation. */
350 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
354 static struct arm_it inst
;
356 #define NUM_FLOAT_VALS 8
358 const char * fp_const
[] =
360 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
363 /* Number of littlenums required to hold an extended precision number. */
364 #define MAX_LITTLENUMS 6
366 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
376 #define CP_T_X 0x00008000
377 #define CP_T_Y 0x00400000
379 #define CONDS_BIT 0x00100000
380 #define LOAD_BIT 0x00100000
382 #define DOUBLE_LOAD_FLAG 0x00000001
386 const char * template;
390 #define COND_ALWAYS 0xE
394 const char *template;
398 struct asm_barrier_opt
400 const char *template;
404 /* The bit that distinguishes CPSR and SPSR. */
405 #define SPSR_BIT (1 << 22)
407 /* The individual PSR flag bits. */
408 #define PSR_c (1 << 16)
409 #define PSR_x (1 << 17)
410 #define PSR_s (1 << 18)
411 #define PSR_f (1 << 19)
416 bfd_reloc_code_real_type reloc
;
421 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
422 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
427 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
430 /* Bits for DEFINED field in neon_typed_alias. */
431 #define NTA_HASTYPE 1
432 #define NTA_HASINDEX 2
434 struct neon_typed_alias
436 unsigned char defined
;
438 struct neon_type_el eltype
;
441 /* ARM register categories. This includes coprocessor numbers and various
442 architecture extensions' registers. */
468 /* Structure for a hash table entry for a register.
469 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
470 information which states whether a vector type or index is specified (for a
471 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
475 unsigned char number
;
477 unsigned char builtin
;
478 struct neon_typed_alias
*neon
;
481 /* Diagnostics used when we don't get a register of the expected type. */
482 const char *const reg_expected_msgs
[] =
484 N_("ARM register expected"),
485 N_("bad or missing co-processor number"),
486 N_("co-processor register expected"),
487 N_("FPA register expected"),
488 N_("VFP single precision register expected"),
489 N_("VFP/Neon double precision register expected"),
490 N_("Neon quad precision register expected"),
491 N_("VFP single or double precision register expected"),
492 N_("Neon double or quad precision register expected"),
493 N_("VFP single, double or Neon quad precision register expected"),
494 N_("VFP system register expected"),
495 N_("Maverick MVF register expected"),
496 N_("Maverick MVD register expected"),
497 N_("Maverick MVFX register expected"),
498 N_("Maverick MVDX register expected"),
499 N_("Maverick MVAX register expected"),
500 N_("Maverick DSPSC register expected"),
501 N_("iWMMXt data register expected"),
502 N_("iWMMXt control register expected"),
503 N_("iWMMXt scalar register expected"),
504 N_("XScale accumulator register expected"),
507 /* Some well known registers that we refer to directly elsewhere. */
512 /* ARM instructions take 4bytes in the object file, Thumb instructions
518 /* Basic string to match. */
519 const char *template;
521 /* Parameters to instruction. */
522 unsigned char operands
[8];
524 /* Conditional tag - see opcode_lookup. */
525 unsigned int tag
: 4;
527 /* Basic instruction code. */
528 unsigned int avalue
: 28;
530 /* Thumb-format instruction code. */
533 /* Which architecture variant provides this instruction. */
534 const arm_feature_set
*avariant
;
535 const arm_feature_set
*tvariant
;
537 /* Function to call to encode instruction in ARM format. */
538 void (* aencode
) (void);
540 /* Function to call to encode instruction in Thumb format. */
541 void (* tencode
) (void);
544 /* Defines for various bits that we will want to toggle. */
545 #define INST_IMMEDIATE 0x02000000
546 #define OFFSET_REG 0x02000000
547 #define HWOFFSET_IMM 0x00400000
548 #define SHIFT_BY_REG 0x00000010
549 #define PRE_INDEX 0x01000000
550 #define INDEX_UP 0x00800000
551 #define WRITE_BACK 0x00200000
552 #define LDM_TYPE_2_OR_3 0x00400000
553 #define CPSI_MMOD 0x00020000
555 #define LITERAL_MASK 0xf000f000
556 #define OPCODE_MASK 0xfe1fffff
557 #define V4_STR_BIT 0x00000020
559 #define T2_SUBS_PC_LR 0xf3de8f00
561 #define DATA_OP_SHIFT 21
563 #define T2_OPCODE_MASK 0xfe1fffff
564 #define T2_DATA_OP_SHIFT 21
566 /* Codes to distinguish the arithmetic instructions. */
577 #define OPCODE_CMP 10
578 #define OPCODE_CMN 11
579 #define OPCODE_ORR 12
580 #define OPCODE_MOV 13
581 #define OPCODE_BIC 14
582 #define OPCODE_MVN 15
584 #define T2_OPCODE_AND 0
585 #define T2_OPCODE_BIC 1
586 #define T2_OPCODE_ORR 2
587 #define T2_OPCODE_ORN 3
588 #define T2_OPCODE_EOR 4
589 #define T2_OPCODE_ADD 8
590 #define T2_OPCODE_ADC 10
591 #define T2_OPCODE_SBC 11
592 #define T2_OPCODE_SUB 13
593 #define T2_OPCODE_RSB 14
595 #define T_OPCODE_MUL 0x4340
596 #define T_OPCODE_TST 0x4200
597 #define T_OPCODE_CMN 0x42c0
598 #define T_OPCODE_NEG 0x4240
599 #define T_OPCODE_MVN 0x43c0
601 #define T_OPCODE_ADD_R3 0x1800
602 #define T_OPCODE_SUB_R3 0x1a00
603 #define T_OPCODE_ADD_HI 0x4400
604 #define T_OPCODE_ADD_ST 0xb000
605 #define T_OPCODE_SUB_ST 0xb080
606 #define T_OPCODE_ADD_SP 0xa800
607 #define T_OPCODE_ADD_PC 0xa000
608 #define T_OPCODE_ADD_I8 0x3000
609 #define T_OPCODE_SUB_I8 0x3800
610 #define T_OPCODE_ADD_I3 0x1c00
611 #define T_OPCODE_SUB_I3 0x1e00
613 #define T_OPCODE_ASR_R 0x4100
614 #define T_OPCODE_LSL_R 0x4080
615 #define T_OPCODE_LSR_R 0x40c0
616 #define T_OPCODE_ROR_R 0x41c0
617 #define T_OPCODE_ASR_I 0x1000
618 #define T_OPCODE_LSL_I 0x0000
619 #define T_OPCODE_LSR_I 0x0800
621 #define T_OPCODE_MOV_I8 0x2000
622 #define T_OPCODE_CMP_I8 0x2800
623 #define T_OPCODE_CMP_LR 0x4280
624 #define T_OPCODE_MOV_HR 0x4600
625 #define T_OPCODE_CMP_HR 0x4500
627 #define T_OPCODE_LDR_PC 0x4800
628 #define T_OPCODE_LDR_SP 0x9800
629 #define T_OPCODE_STR_SP 0x9000
630 #define T_OPCODE_LDR_IW 0x6800
631 #define T_OPCODE_STR_IW 0x6000
632 #define T_OPCODE_LDR_IH 0x8800
633 #define T_OPCODE_STR_IH 0x8000
634 #define T_OPCODE_LDR_IB 0x7800
635 #define T_OPCODE_STR_IB 0x7000
636 #define T_OPCODE_LDR_RW 0x5800
637 #define T_OPCODE_STR_RW 0x5000
638 #define T_OPCODE_LDR_RH 0x5a00
639 #define T_OPCODE_STR_RH 0x5200
640 #define T_OPCODE_LDR_RB 0x5c00
641 #define T_OPCODE_STR_RB 0x5400
643 #define T_OPCODE_PUSH 0xb400
644 #define T_OPCODE_POP 0xbc00
646 #define T_OPCODE_BRANCH 0xe000
648 #define THUMB_SIZE 2 /* Size of thumb instruction. */
649 #define THUMB_PP_PC_LR 0x0100
650 #define THUMB_LOAD_BIT 0x0800
651 #define THUMB2_LOAD_BIT 0x00100000
653 #define BAD_ARGS _("bad arguments to instruction")
654 #define BAD_PC _("r15 not allowed here")
655 #define BAD_COND _("instruction cannot be conditional")
656 #define BAD_OVERLAP _("registers may not be the same")
657 #define BAD_HIREG _("lo register required")
658 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
659 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
660 #define BAD_BRANCH _("branch must be last instruction in IT block")
661 #define BAD_NOT_IT _("instruction not allowed in IT block")
662 #define BAD_FPU _("selected FPU does not support instruction")
664 static struct hash_control
*arm_ops_hsh
;
665 static struct hash_control
*arm_cond_hsh
;
666 static struct hash_control
*arm_shift_hsh
;
667 static struct hash_control
*arm_psr_hsh
;
668 static struct hash_control
*arm_v7m_psr_hsh
;
669 static struct hash_control
*arm_reg_hsh
;
670 static struct hash_control
*arm_reloc_hsh
;
671 static struct hash_control
*arm_barrier_opt_hsh
;
673 /* Stuff needed to resolve the label ambiguity
682 symbolS
* last_label_seen
;
683 static int label_is_thumb_function_name
= FALSE
;
685 /* Literal pool structure. Held on a per-section
686 and per-sub-section basis. */
688 #define MAX_LITERAL_POOL_SIZE 1024
689 typedef struct literal_pool
691 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
692 unsigned int next_free_entry
;
697 struct literal_pool
* next
;
700 /* Pointer to a linked list of literal pools. */
701 literal_pool
* list_of_pools
= NULL
;
703 /* State variables for IT block handling. */
704 static bfd_boolean current_it_mask
= 0;
705 static int current_cc
;
709 /* This array holds the chars that always start a comment. If the
710 pre-processor is disabled, these aren't very useful. */
711 const char comment_chars
[] = "@";
713 /* This array holds the chars that only start a comment at the beginning of
714 a line. If the line seems to have the form '# 123 filename'
715 .line and .file directives will appear in the pre-processed output. */
716 /* Note that input_file.c hand checks for '#' at the beginning of the
717 first line of the input file. This is because the compiler outputs
718 #NO_APP at the beginning of its output. */
719 /* Also note that comments like this one will always work. */
720 const char line_comment_chars
[] = "#";
722 const char line_separator_chars
[] = ";";
724 /* Chars that can be used to separate mant
725 from exp in floating point numbers. */
726 const char EXP_CHARS
[] = "eE";
728 /* Chars that mean this number is a floating point constant. */
732 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
734 /* Prefix characters that indicate the start of an immediate
736 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
738 /* Separator character handling. */
740 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
743 skip_past_char (char ** str
, char c
)
753 #define skip_past_comma(str) skip_past_char (str, ',')
755 /* Arithmetic expressions (possibly involving symbols). */
757 /* Return TRUE if anything in the expression is a bignum. */
760 walk_no_bignums (symbolS
* sp
)
762 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
765 if (symbol_get_value_expression (sp
)->X_add_symbol
)
767 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
768 || (symbol_get_value_expression (sp
)->X_op_symbol
769 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
775 static int in_my_get_expression
= 0;
777 /* Third argument to my_get_expression. */
778 #define GE_NO_PREFIX 0
779 #define GE_IMM_PREFIX 1
780 #define GE_OPT_PREFIX 2
781 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
782 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
783 #define GE_OPT_PREFIX_BIG 3
786 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
791 /* In unified syntax, all prefixes are optional. */
793 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
798 case GE_NO_PREFIX
: break;
800 if (!is_immediate_prefix (**str
))
802 inst
.error
= _("immediate expression requires a # prefix");
808 case GE_OPT_PREFIX_BIG
:
809 if (is_immediate_prefix (**str
))
815 memset (ep
, 0, sizeof (expressionS
));
817 save_in
= input_line_pointer
;
818 input_line_pointer
= *str
;
819 in_my_get_expression
= 1;
820 seg
= expression (ep
);
821 in_my_get_expression
= 0;
823 if (ep
->X_op
== O_illegal
)
825 /* We found a bad expression in md_operand(). */
826 *str
= input_line_pointer
;
827 input_line_pointer
= save_in
;
828 if (inst
.error
== NULL
)
829 inst
.error
= _("bad expression");
834 if (seg
!= absolute_section
835 && seg
!= text_section
836 && seg
!= data_section
837 && seg
!= bss_section
838 && seg
!= undefined_section
)
840 inst
.error
= _("bad segment");
841 *str
= input_line_pointer
;
842 input_line_pointer
= save_in
;
847 /* Get rid of any bignums now, so that we don't generate an error for which
848 we can't establish a line number later on. Big numbers are never valid
849 in instructions, which is where this routine is always called. */
850 if (prefix_mode
!= GE_OPT_PREFIX_BIG
851 && (ep
->X_op
== O_big
853 && (walk_no_bignums (ep
->X_add_symbol
)
855 && walk_no_bignums (ep
->X_op_symbol
))))))
857 inst
.error
= _("invalid constant");
858 *str
= input_line_pointer
;
859 input_line_pointer
= save_in
;
863 *str
= input_line_pointer
;
864 input_line_pointer
= save_in
;
868 /* Turn a string in input_line_pointer into a floating point constant
869 of type TYPE, and store the appropriate bytes in *LITP. The number
870 of LITTLENUMS emitted is stored in *SIZEP. An error message is
871 returned, or NULL on OK.
873 Note that fp constants aren't represent in the normal way on the ARM.
874 In big endian mode, things are as expected. However, in little endian
875 mode fp constants are big-endian word-wise, and little-endian byte-wise
876 within the words. For example, (double) 1.1 in big endian mode is
877 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
878 the byte sequence 99 99 f1 3f 9a 99 99 99.
880 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
883 md_atof (int type
, char * litP
, int * sizeP
)
886 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
918 return _("Unrecognized or unsupported floating point constant");
921 t
= atof_ieee (input_line_pointer
, type
, words
);
923 input_line_pointer
= t
;
924 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
926 if (target_big_endian
)
928 for (i
= 0; i
< prec
; i
++)
930 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
931 litP
+= sizeof (LITTLENUM_TYPE
);
936 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
937 for (i
= prec
- 1; i
>= 0; i
--)
939 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
940 litP
+= sizeof (LITTLENUM_TYPE
);
943 /* For a 4 byte float the order of elements in `words' is 1 0.
944 For an 8 byte float the order is 1 0 3 2. */
945 for (i
= 0; i
< prec
; i
+= 2)
947 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
948 sizeof (LITTLENUM_TYPE
));
949 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
950 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
951 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
958 /* We handle all bad expressions here, so that we can report the faulty
959 instruction in the error message. */
961 md_operand (expressionS
* expr
)
963 if (in_my_get_expression
)
964 expr
->X_op
= O_illegal
;
967 /* Immediate values. */
969 /* Generic immediate-value read function for use in directives.
970 Accepts anything that 'expression' can fold to a constant.
971 *val receives the number. */
974 immediate_for_directive (int *val
)
977 exp
.X_op
= O_illegal
;
979 if (is_immediate_prefix (*input_line_pointer
))
981 input_line_pointer
++;
985 if (exp
.X_op
!= O_constant
)
987 as_bad (_("expected #constant"));
988 ignore_rest_of_line ();
991 *val
= exp
.X_add_number
;
996 /* Register parsing. */
998 /* Generic register parser. CCP points to what should be the
999 beginning of a register name. If it is indeed a valid register
1000 name, advance CCP over it and return the reg_entry structure;
1001 otherwise return NULL. Does not issue diagnostics. */
1003 static struct reg_entry
*
1004 arm_reg_parse_multi (char **ccp
)
1008 struct reg_entry
*reg
;
1010 #ifdef REGISTER_PREFIX
1011 if (*start
!= REGISTER_PREFIX
)
1015 #ifdef OPTIONAL_REGISTER_PREFIX
1016 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1021 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1026 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1028 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1038 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1039 enum arm_reg_type type
)
1041 /* Alternative syntaxes are accepted for a few register classes. */
1048 /* Generic coprocessor register names are allowed for these. */
1049 if (reg
&& reg
->type
== REG_TYPE_CN
)
1054 /* For backward compatibility, a bare number is valid here. */
1056 unsigned long processor
= strtoul (start
, ccp
, 10);
1057 if (*ccp
!= start
&& processor
<= 15)
1061 case REG_TYPE_MMXWC
:
1062 /* WC includes WCG. ??? I'm not sure this is true for all
1063 instructions that take WC registers. */
1064 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1075 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1076 return value is the register number or FAIL. */
1079 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1082 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1085 /* Do not allow a scalar (reg+index) to parse as a register. */
1086 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1089 if (reg
&& reg
->type
== type
)
1092 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1099 /* Parse a Neon type specifier. *STR should point at the leading '.'
1100 character. Does no verification at this stage that the type fits the opcode
1107 Can all be legally parsed by this function.
1109 Fills in neon_type struct pointer with parsed information, and updates STR
1110 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1111 type, FAIL if not. */
1114 parse_neon_type (struct neon_type
*type
, char **str
)
1121 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1123 enum neon_el_type thistype
= NT_untyped
;
1124 unsigned thissize
= -1u;
1131 /* Just a size without an explicit type. */
1135 switch (TOLOWER (*ptr
))
1137 case 'i': thistype
= NT_integer
; break;
1138 case 'f': thistype
= NT_float
; break;
1139 case 'p': thistype
= NT_poly
; break;
1140 case 's': thistype
= NT_signed
; break;
1141 case 'u': thistype
= NT_unsigned
; break;
1143 thistype
= NT_float
;
1148 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1154 /* .f is an abbreviation for .f32. */
1155 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1160 thissize
= strtoul (ptr
, &ptr
, 10);
1162 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1165 as_bad (_("bad size %d in type specifier"), thissize
);
1173 type
->el
[type
->elems
].type
= thistype
;
1174 type
->el
[type
->elems
].size
= thissize
;
1179 /* Empty/missing type is not a successful parse. */
1180 if (type
->elems
== 0)
1188 /* Errors may be set multiple times during parsing or bit encoding
1189 (particularly in the Neon bits), but usually the earliest error which is set
1190 will be the most meaningful. Avoid overwriting it with later (cascading)
1191 errors by calling this function. */
1194 first_error (const char *err
)
1200 /* Parse a single type, e.g. ".s32", leading period included. */
1202 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1205 struct neon_type optype
;
1209 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1211 if (optype
.elems
== 1)
1212 *vectype
= optype
.el
[0];
1215 first_error (_("only one type should be specified for operand"));
1221 first_error (_("vector type expected"));
1233 /* Special meanings for indices (which have a range of 0-7), which will fit into
1236 #define NEON_ALL_LANES 15
1237 #define NEON_INTERLEAVE_LANES 14
1239 /* Parse either a register or a scalar, with an optional type. Return the
1240 register number, and optionally fill in the actual type of the register
1241 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1242 type/index information in *TYPEINFO. */
1245 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1246 enum arm_reg_type
*rtype
,
1247 struct neon_typed_alias
*typeinfo
)
1250 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1251 struct neon_typed_alias atype
;
1252 struct neon_type_el parsetype
;
1256 atype
.eltype
.type
= NT_invtype
;
1257 atype
.eltype
.size
= -1;
1259 /* Try alternate syntax for some types of register. Note these are mutually
1260 exclusive with the Neon syntax extensions. */
1263 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1271 /* Undo polymorphism when a set of register types may be accepted. */
1272 if ((type
== REG_TYPE_NDQ
1273 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1274 || (type
== REG_TYPE_VFSD
1275 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1276 || (type
== REG_TYPE_NSDQ
1277 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1278 || reg
->type
== REG_TYPE_NQ
))
1279 || (type
== REG_TYPE_MMXWC
1280 && (reg
->type
== REG_TYPE_MMXWCG
)))
1283 if (type
!= reg
->type
)
1289 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1291 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1293 first_error (_("can't redefine type for operand"));
1296 atype
.defined
|= NTA_HASTYPE
;
1297 atype
.eltype
= parsetype
;
1300 if (skip_past_char (&str
, '[') == SUCCESS
)
1302 if (type
!= REG_TYPE_VFD
)
1304 first_error (_("only D registers may be indexed"));
1308 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1310 first_error (_("can't change index for operand"));
1314 atype
.defined
|= NTA_HASINDEX
;
1316 if (skip_past_char (&str
, ']') == SUCCESS
)
1317 atype
.index
= NEON_ALL_LANES
;
1322 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1324 if (exp
.X_op
!= O_constant
)
1326 first_error (_("constant expression required"));
1330 if (skip_past_char (&str
, ']') == FAIL
)
1333 atype
.index
= exp
.X_add_number
;
1348 /* Like arm_reg_parse, but allow allow the following extra features:
1349 - If RTYPE is non-zero, return the (possibly restricted) type of the
1350 register (e.g. Neon double or quad reg when either has been requested).
1351 - If this is a Neon vector type with additional type information, fill
1352 in the struct pointed to by VECTYPE (if non-NULL).
1353 This function will fault on encountering a scalar. */
1356 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1357 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1359 struct neon_typed_alias atype
;
1361 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1366 /* Do not allow a scalar (reg+index) to parse as a register. */
1367 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1369 first_error (_("register operand expected, but got scalar"));
1374 *vectype
= atype
.eltype
;
1381 #define NEON_SCALAR_REG(X) ((X) >> 4)
1382 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1384 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1385 have enough information to be able to do a good job bounds-checking. So, we
1386 just do easy checks here, and do further checks later. */
1389 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1393 struct neon_typed_alias atype
;
1395 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1397 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1400 if (atype
.index
== NEON_ALL_LANES
)
1402 first_error (_("scalar must have an index"));
1405 else if (atype
.index
>= 64 / elsize
)
1407 first_error (_("scalar index out of range"));
1412 *type
= atype
.eltype
;
1416 return reg
* 16 + atype
.index
;
1419 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1421 parse_reg_list (char ** strp
)
1423 char * str
= * strp
;
1427 /* We come back here if we get ranges concatenated by '+' or '|'. */
1442 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1444 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1454 first_error (_("bad range in register list"));
1458 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1460 if (range
& (1 << i
))
1462 (_("Warning: duplicated register (r%d) in register list"),
1470 if (range
& (1 << reg
))
1471 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1473 else if (reg
<= cur_reg
)
1474 as_tsktsk (_("Warning: register range not in ascending order"));
1479 while (skip_past_comma (&str
) != FAIL
1480 || (in_range
= 1, *str
++ == '-'));
1485 first_error (_("missing `}'"));
1493 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1496 if (expr
.X_op
== O_constant
)
1498 if (expr
.X_add_number
1499 != (expr
.X_add_number
& 0x0000ffff))
1501 inst
.error
= _("invalid register mask");
1505 if ((range
& expr
.X_add_number
) != 0)
1507 int regno
= range
& expr
.X_add_number
;
1510 regno
= (1 << regno
) - 1;
1512 (_("Warning: duplicated register (r%d) in register list"),
1516 range
|= expr
.X_add_number
;
1520 if (inst
.reloc
.type
!= 0)
1522 inst
.error
= _("expression too complex");
1526 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1527 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1528 inst
.reloc
.pc_rel
= 0;
1532 if (*str
== '|' || *str
== '+')
1538 while (another_range
);
1544 /* Types of registers in a list. */
1553 /* Parse a VFP register list. If the string is invalid return FAIL.
1554 Otherwise return the number of registers, and set PBASE to the first
1555 register. Parses registers of type ETYPE.
1556 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1557 - Q registers can be used to specify pairs of D registers
1558 - { } can be omitted from around a singleton register list
1559 FIXME: This is not implemented, as it would require backtracking in
1562 This could be done (the meaning isn't really ambiguous), but doesn't
1563 fit in well with the current parsing framework.
1564 - 32 D registers may be used (also true for VFPv3).
1565 FIXME: Types are ignored in these register lists, which is probably a
1569 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1574 enum arm_reg_type regtype
= 0;
1578 unsigned long mask
= 0;
1583 inst
.error
= _("expecting {");
1592 regtype
= REG_TYPE_VFS
;
1597 regtype
= REG_TYPE_VFD
;
1600 case REGLIST_NEON_D
:
1601 regtype
= REG_TYPE_NDQ
;
1605 if (etype
!= REGLIST_VFP_S
)
1607 /* VFPv3 allows 32 D registers. */
1608 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
1612 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1615 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1622 base_reg
= max_regs
;
1626 int setmask
= 1, addregs
= 1;
1628 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1630 if (new_base
== FAIL
)
1632 first_error (_(reg_expected_msgs
[regtype
]));
1636 if (new_base
>= max_regs
)
1638 first_error (_("register out of range in list"));
1642 /* Note: a value of 2 * n is returned for the register Q<n>. */
1643 if (regtype
== REG_TYPE_NQ
)
1649 if (new_base
< base_reg
)
1650 base_reg
= new_base
;
1652 if (mask
& (setmask
<< new_base
))
1654 first_error (_("invalid register list"));
1658 if ((mask
>> new_base
) != 0 && ! warned
)
1660 as_tsktsk (_("register list not in ascending order"));
1664 mask
|= setmask
<< new_base
;
1667 if (*str
== '-') /* We have the start of a range expression */
1673 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1676 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1680 if (high_range
>= max_regs
)
1682 first_error (_("register out of range in list"));
1686 if (regtype
== REG_TYPE_NQ
)
1687 high_range
= high_range
+ 1;
1689 if (high_range
<= new_base
)
1691 inst
.error
= _("register range not in ascending order");
1695 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1697 if (mask
& (setmask
<< new_base
))
1699 inst
.error
= _("invalid register list");
1703 mask
|= setmask
<< new_base
;
1708 while (skip_past_comma (&str
) != FAIL
);
1712 /* Sanity check -- should have raised a parse error above. */
1713 if (count
== 0 || count
> max_regs
)
1718 /* Final test -- the registers must be consecutive. */
1720 for (i
= 0; i
< count
; i
++)
1722 if ((mask
& (1u << i
)) == 0)
1724 inst
.error
= _("non-contiguous register range");
1734 /* True if two alias types are the same. */
1737 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1745 if (a
->defined
!= b
->defined
)
1748 if ((a
->defined
& NTA_HASTYPE
) != 0
1749 && (a
->eltype
.type
!= b
->eltype
.type
1750 || a
->eltype
.size
!= b
->eltype
.size
))
1753 if ((a
->defined
& NTA_HASINDEX
) != 0
1754 && (a
->index
!= b
->index
))
1760 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1761 The base register is put in *PBASE.
1762 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1764 The register stride (minus one) is put in bit 4 of the return value.
1765 Bits [6:5] encode the list length (minus one).
1766 The type of the list elements is put in *ELTYPE, if non-NULL. */
1768 #define NEON_LANE(X) ((X) & 0xf)
1769 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1770 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1773 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1774 struct neon_type_el
*eltype
)
1781 int leading_brace
= 0;
1782 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1784 const char *const incr_error
= "register stride must be 1 or 2";
1785 const char *const type_error
= "mismatched element/structure types in list";
1786 struct neon_typed_alias firsttype
;
1788 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1793 struct neon_typed_alias atype
;
1794 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1798 first_error (_(reg_expected_msgs
[rtype
]));
1805 if (rtype
== REG_TYPE_NQ
)
1812 else if (reg_incr
== -1)
1814 reg_incr
= getreg
- base_reg
;
1815 if (reg_incr
< 1 || reg_incr
> 2)
1817 first_error (_(incr_error
));
1821 else if (getreg
!= base_reg
+ reg_incr
* count
)
1823 first_error (_(incr_error
));
1827 if (!neon_alias_types_same (&atype
, &firsttype
))
1829 first_error (_(type_error
));
1833 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1837 struct neon_typed_alias htype
;
1838 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1840 lane
= NEON_INTERLEAVE_LANES
;
1841 else if (lane
!= NEON_INTERLEAVE_LANES
)
1843 first_error (_(type_error
));
1848 else if (reg_incr
!= 1)
1850 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1854 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1857 first_error (_(reg_expected_msgs
[rtype
]));
1860 if (!neon_alias_types_same (&htype
, &firsttype
))
1862 first_error (_(type_error
));
1865 count
+= hireg
+ dregs
- getreg
;
1869 /* If we're using Q registers, we can't use [] or [n] syntax. */
1870 if (rtype
== REG_TYPE_NQ
)
1876 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1880 else if (lane
!= atype
.index
)
1882 first_error (_(type_error
));
1886 else if (lane
== -1)
1887 lane
= NEON_INTERLEAVE_LANES
;
1888 else if (lane
!= NEON_INTERLEAVE_LANES
)
1890 first_error (_(type_error
));
1895 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1897 /* No lane set by [x]. We must be interleaving structures. */
1899 lane
= NEON_INTERLEAVE_LANES
;
1902 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
1903 || (count
> 1 && reg_incr
== -1))
1905 first_error (_("error parsing element/structure list"));
1909 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
1911 first_error (_("expected }"));
1919 *eltype
= firsttype
.eltype
;
1924 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
1927 /* Parse an explicit relocation suffix on an expression. This is
1928 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1929 arm_reloc_hsh contains no entries, so this function can only
1930 succeed if there is no () after the word. Returns -1 on error,
1931 BFD_RELOC_UNUSED if there wasn't any suffix. */
1933 parse_reloc (char **str
)
1935 struct reloc_entry
*r
;
1939 return BFD_RELOC_UNUSED
;
1944 while (*q
&& *q
!= ')' && *q
!= ',')
1949 if ((r
= hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
1956 /* Directives: register aliases. */
1958 static struct reg_entry
*
1959 insert_reg_alias (char *str
, int number
, int type
)
1961 struct reg_entry
*new;
1964 if ((new = hash_find (arm_reg_hsh
, str
)) != 0)
1967 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
1969 /* Only warn about a redefinition if it's not defined as the
1971 else if (new->number
!= number
|| new->type
!= type
)
1972 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1977 name
= xstrdup (str
);
1978 new = xmalloc (sizeof (struct reg_entry
));
1981 new->number
= number
;
1983 new->builtin
= FALSE
;
1986 if (hash_insert (arm_reg_hsh
, name
, (PTR
) new))
1993 insert_neon_reg_alias (char *str
, int number
, int type
,
1994 struct neon_typed_alias
*atype
)
1996 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2000 first_error (_("attempt to redefine typed alias"));
2006 reg
->neon
= xmalloc (sizeof (struct neon_typed_alias
));
2007 *reg
->neon
= *atype
;
2011 /* Look for the .req directive. This is of the form:
2013 new_register_name .req existing_register_name
2015 If we find one, or if it looks sufficiently like one that we want to
2016 handle any error here, return TRUE. Otherwise return FALSE. */
2019 create_register_alias (char * newname
, char *p
)
2021 struct reg_entry
*old
;
2022 char *oldname
, *nbuf
;
2025 /* The input scrubber ensures that whitespace after the mnemonic is
2026 collapsed to single spaces. */
2028 if (strncmp (oldname
, " .req ", 6) != 0)
2032 if (*oldname
== '\0')
2035 old
= hash_find (arm_reg_hsh
, oldname
);
2038 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2042 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2043 the desired alias name, and p points to its end. If not, then
2044 the desired alias name is in the global original_case_string. */
2045 #ifdef TC_CASE_SENSITIVE
2048 newname
= original_case_string
;
2049 nlen
= strlen (newname
);
2052 nbuf
= alloca (nlen
+ 1);
2053 memcpy (nbuf
, newname
, nlen
);
2056 /* Create aliases under the new name as stated; an all-lowercase
2057 version of the new name; and an all-uppercase version of the new
2059 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2061 for (p
= nbuf
; *p
; p
++)
2064 if (strncmp (nbuf
, newname
, nlen
))
2066 /* If this attempt to create an additional alias fails, do not bother
2067 trying to create the all-lower case alias. We will fail and issue
2068 a second, duplicate error message. This situation arises when the
2069 programmer does something like:
2072 The second .req creates the "Foo" alias but then fails to create
2073 the artificial FOO alias because it has already been created by the
2075 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2079 for (p
= nbuf
; *p
; p
++)
2082 if (strncmp (nbuf
, newname
, nlen
))
2083 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2089 /* Create a Neon typed/indexed register alias using directives, e.g.:
2094 These typed registers can be used instead of the types specified after the
2095 Neon mnemonic, so long as all operands given have types. Types can also be
2096 specified directly, e.g.:
2097 vadd d0.s32, d1.s32, d2.s32 */
2100 create_neon_reg_alias (char *newname
, char *p
)
2102 enum arm_reg_type basetype
;
2103 struct reg_entry
*basereg
;
2104 struct reg_entry mybasereg
;
2105 struct neon_type ntype
;
2106 struct neon_typed_alias typeinfo
;
2107 char *namebuf
, *nameend
;
2110 typeinfo
.defined
= 0;
2111 typeinfo
.eltype
.type
= NT_invtype
;
2112 typeinfo
.eltype
.size
= -1;
2113 typeinfo
.index
= -1;
2117 if (strncmp (p
, " .dn ", 5) == 0)
2118 basetype
= REG_TYPE_VFD
;
2119 else if (strncmp (p
, " .qn ", 5) == 0)
2120 basetype
= REG_TYPE_NQ
;
2129 basereg
= arm_reg_parse_multi (&p
);
2131 if (basereg
&& basereg
->type
!= basetype
)
2133 as_bad (_("bad type for register"));
2137 if (basereg
== NULL
)
2140 /* Try parsing as an integer. */
2141 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2142 if (exp
.X_op
!= O_constant
)
2144 as_bad (_("expression must be constant"));
2147 basereg
= &mybasereg
;
2148 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2154 typeinfo
= *basereg
->neon
;
2156 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2158 /* We got a type. */
2159 if (typeinfo
.defined
& NTA_HASTYPE
)
2161 as_bad (_("can't redefine the type of a register alias"));
2165 typeinfo
.defined
|= NTA_HASTYPE
;
2166 if (ntype
.elems
!= 1)
2168 as_bad (_("you must specify a single type only"));
2171 typeinfo
.eltype
= ntype
.el
[0];
2174 if (skip_past_char (&p
, '[') == SUCCESS
)
2177 /* We got a scalar index. */
2179 if (typeinfo
.defined
& NTA_HASINDEX
)
2181 as_bad (_("can't redefine the index of a scalar alias"));
2185 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2187 if (exp
.X_op
!= O_constant
)
2189 as_bad (_("scalar index must be constant"));
2193 typeinfo
.defined
|= NTA_HASINDEX
;
2194 typeinfo
.index
= exp
.X_add_number
;
2196 if (skip_past_char (&p
, ']') == FAIL
)
2198 as_bad (_("expecting ]"));
2203 namelen
= nameend
- newname
;
2204 namebuf
= alloca (namelen
+ 1);
2205 strncpy (namebuf
, newname
, namelen
);
2206 namebuf
[namelen
] = '\0';
2208 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2209 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2211 /* Insert name in all uppercase. */
2212 for (p
= namebuf
; *p
; p
++)
2215 if (strncmp (namebuf
, newname
, namelen
))
2216 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2217 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2219 /* Insert name in all lowercase. */
2220 for (p
= namebuf
; *p
; p
++)
2223 if (strncmp (namebuf
, newname
, namelen
))
2224 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2225 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2230 /* Should never be called, as .req goes between the alias and the
2231 register name, not at the beginning of the line. */
2233 s_req (int a ATTRIBUTE_UNUSED
)
2235 as_bad (_("invalid syntax for .req directive"));
2239 s_dn (int a ATTRIBUTE_UNUSED
)
2241 as_bad (_("invalid syntax for .dn directive"));
2245 s_qn (int a ATTRIBUTE_UNUSED
)
2247 as_bad (_("invalid syntax for .qn directive"));
2250 /* The .unreq directive deletes an alias which was previously defined
2251 by .req. For example:
2257 s_unreq (int a ATTRIBUTE_UNUSED
)
2262 name
= input_line_pointer
;
2264 while (*input_line_pointer
!= 0
2265 && *input_line_pointer
!= ' '
2266 && *input_line_pointer
!= '\n')
2267 ++input_line_pointer
;
2269 saved_char
= *input_line_pointer
;
2270 *input_line_pointer
= 0;
2273 as_bad (_("invalid syntax for .unreq directive"));
2276 struct reg_entry
*reg
= hash_find (arm_reg_hsh
, name
);
2279 as_bad (_("unknown register alias '%s'"), name
);
2280 else if (reg
->builtin
)
2281 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2288 hash_delete (arm_reg_hsh
, name
);
2289 free ((char *) reg
->name
);
2294 /* Also locate the all upper case and all lower case versions.
2295 Do not complain if we cannot find one or the other as it
2296 was probably deleted above. */
2298 nbuf
= strdup (name
);
2299 for (p
= nbuf
; *p
; p
++)
2301 reg
= hash_find (arm_reg_hsh
, nbuf
);
2304 hash_delete (arm_reg_hsh
, nbuf
);
2305 free ((char *) reg
->name
);
2311 for (p
= nbuf
; *p
; p
++)
2313 reg
= hash_find (arm_reg_hsh
, nbuf
);
2316 hash_delete (arm_reg_hsh
, nbuf
);
2317 free ((char *) reg
->name
);
2327 *input_line_pointer
= saved_char
;
2328 demand_empty_rest_of_line ();
2331 /* Directives: Instruction set selection. */
2334 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2335 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2336 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2337 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2339 static enum mstate mapstate
= MAP_UNDEFINED
;
2342 mapping_state (enum mstate state
)
2345 const char * symname
;
2348 if (mapstate
== state
)
2349 /* The mapping symbol has already been emitted.
2350 There is nothing else to do. */
2359 type
= BSF_NO_FLAGS
;
2363 type
= BSF_NO_FLAGS
;
2367 type
= BSF_NO_FLAGS
;
2375 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2377 symbolP
= symbol_new (symname
, now_seg
, (valueT
) frag_now_fix (), frag_now
);
2378 symbol_table_insert (symbolP
);
2379 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2384 THUMB_SET_FUNC (symbolP
, 0);
2385 ARM_SET_THUMB (symbolP
, 0);
2386 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2390 THUMB_SET_FUNC (symbolP
, 1);
2391 ARM_SET_THUMB (symbolP
, 1);
2392 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2401 #define mapping_state(x) /* nothing */
2404 /* Find the real, Thumb encoded start of a Thumb function. */
2407 find_real_start (symbolS
* symbolP
)
2410 const char * name
= S_GET_NAME (symbolP
);
2411 symbolS
* new_target
;
2413 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2414 #define STUB_NAME ".real_start_of"
2419 /* The compiler may generate BL instructions to local labels because
2420 it needs to perform a branch to a far away location. These labels
2421 do not have a corresponding ".real_start_of" label. We check
2422 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2423 the ".real_start_of" convention for nonlocal branches. */
2424 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2427 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2428 new_target
= symbol_find (real_start
);
2430 if (new_target
== NULL
)
2432 as_warn (_("Failed to find real start of function: %s\n"), name
);
2433 new_target
= symbolP
;
2440 opcode_select (int width
)
2447 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2448 as_bad (_("selected processor does not support THUMB opcodes"));
2451 /* No need to force the alignment, since we will have been
2452 coming from ARM mode, which is word-aligned. */
2453 record_alignment (now_seg
, 1);
2455 mapping_state (MAP_THUMB
);
2461 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2462 as_bad (_("selected processor does not support ARM opcodes"));
2467 frag_align (2, 0, 0);
2469 record_alignment (now_seg
, 1);
2471 mapping_state (MAP_ARM
);
2475 as_bad (_("invalid instruction size selected (%d)"), width
);
2480 s_arm (int ignore ATTRIBUTE_UNUSED
)
2483 demand_empty_rest_of_line ();
2487 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2490 demand_empty_rest_of_line ();
2494 s_code (int unused ATTRIBUTE_UNUSED
)
2498 temp
= get_absolute_expression ();
2503 opcode_select (temp
);
2507 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2512 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2514 /* If we are not already in thumb mode go into it, EVEN if
2515 the target processor does not support thumb instructions.
2516 This is used by gcc/config/arm/lib1funcs.asm for example
2517 to compile interworking support functions even if the
2518 target processor should not support interworking. */
2522 record_alignment (now_seg
, 1);
2525 demand_empty_rest_of_line ();
2529 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2533 /* The following label is the name/address of the start of a Thumb function.
2534 We need to know this for the interworking support. */
2535 label_is_thumb_function_name
= TRUE
;
2538 /* Perform a .set directive, but also mark the alias as
2539 being a thumb function. */
2542 s_thumb_set (int equiv
)
2544 /* XXX the following is a duplicate of the code for s_set() in read.c
2545 We cannot just call that code as we need to get at the symbol that
2552 /* Especial apologies for the random logic:
2553 This just grew, and could be parsed much more simply!
2555 name
= input_line_pointer
;
2556 delim
= get_symbol_end ();
2557 end_name
= input_line_pointer
;
2560 if (*input_line_pointer
!= ',')
2563 as_bad (_("expected comma after name \"%s\""), name
);
2565 ignore_rest_of_line ();
2569 input_line_pointer
++;
2572 if (name
[0] == '.' && name
[1] == '\0')
2574 /* XXX - this should not happen to .thumb_set. */
2578 if ((symbolP
= symbol_find (name
)) == NULL
2579 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2582 /* When doing symbol listings, play games with dummy fragments living
2583 outside the normal fragment chain to record the file and line info
2585 if (listing
& LISTING_SYMBOLS
)
2587 extern struct list_info_struct
* listing_tail
;
2588 fragS
* dummy_frag
= xmalloc (sizeof (fragS
));
2590 memset (dummy_frag
, 0, sizeof (fragS
));
2591 dummy_frag
->fr_type
= rs_fill
;
2592 dummy_frag
->line
= listing_tail
;
2593 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2594 dummy_frag
->fr_symbol
= symbolP
;
2598 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2601 /* "set" symbols are local unless otherwise specified. */
2602 SF_SET_LOCAL (symbolP
);
2603 #endif /* OBJ_COFF */
2604 } /* Make a new symbol. */
2606 symbol_table_insert (symbolP
);
2611 && S_IS_DEFINED (symbolP
)
2612 && S_GET_SEGMENT (symbolP
) != reg_section
)
2613 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2615 pseudo_set (symbolP
);
2617 demand_empty_rest_of_line ();
2619 /* XXX Now we come to the Thumb specific bit of code. */
2621 THUMB_SET_FUNC (symbolP
, 1);
2622 ARM_SET_THUMB (symbolP
, 1);
2623 #if defined OBJ_ELF || defined OBJ_COFF
2624 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2628 /* Directives: Mode selection. */
2630 /* .syntax [unified|divided] - choose the new unified syntax
2631 (same for Arm and Thumb encoding, modulo slight differences in what
2632 can be represented) or the old divergent syntax for each mode. */
2634 s_syntax (int unused ATTRIBUTE_UNUSED
)
2638 name
= input_line_pointer
;
2639 delim
= get_symbol_end ();
2641 if (!strcasecmp (name
, "unified"))
2642 unified_syntax
= TRUE
;
2643 else if (!strcasecmp (name
, "divided"))
2644 unified_syntax
= FALSE
;
2647 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2650 *input_line_pointer
= delim
;
2651 demand_empty_rest_of_line ();
2654 /* Directives: sectioning and alignment. */
2656 /* Same as s_align_ptwo but align 0 => align 2. */
2659 s_align (int unused ATTRIBUTE_UNUSED
)
2664 long max_alignment
= 15;
2666 temp
= get_absolute_expression ();
2667 if (temp
> max_alignment
)
2668 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2671 as_bad (_("alignment negative. 0 assumed."));
2675 if (*input_line_pointer
== ',')
2677 input_line_pointer
++;
2678 temp_fill
= get_absolute_expression ();
2690 /* Only make a frag if we HAVE to. */
2691 if (temp
&& !need_pass_2
)
2693 if (!fill_p
&& subseg_text_p (now_seg
))
2694 frag_align_code (temp
, 0);
2696 frag_align (temp
, (int) temp_fill
, 0);
2698 demand_empty_rest_of_line ();
2700 record_alignment (now_seg
, temp
);
2704 s_bss (int ignore ATTRIBUTE_UNUSED
)
2706 /* We don't support putting frags in the BSS segment, we fake it by
2707 marking in_bss, then looking at s_skip for clues. */
2708 subseg_set (bss_section
, 0);
2709 demand_empty_rest_of_line ();
2710 mapping_state (MAP_DATA
);
2714 s_even (int ignore ATTRIBUTE_UNUSED
)
2716 /* Never make frag if expect extra pass. */
2718 frag_align (1, 0, 0);
2720 record_alignment (now_seg
, 1);
2722 demand_empty_rest_of_line ();
2725 /* Directives: Literal pools. */
2727 static literal_pool
*
2728 find_literal_pool (void)
2730 literal_pool
* pool
;
2732 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2734 if (pool
->section
== now_seg
2735 && pool
->sub_section
== now_subseg
)
2742 static literal_pool
*
2743 find_or_make_literal_pool (void)
2745 /* Next literal pool ID number. */
2746 static unsigned int latest_pool_num
= 1;
2747 literal_pool
* pool
;
2749 pool
= find_literal_pool ();
2753 /* Create a new pool. */
2754 pool
= xmalloc (sizeof (* pool
));
2758 pool
->next_free_entry
= 0;
2759 pool
->section
= now_seg
;
2760 pool
->sub_section
= now_subseg
;
2761 pool
->next
= list_of_pools
;
2762 pool
->symbol
= NULL
;
2764 /* Add it to the list. */
2765 list_of_pools
= pool
;
2768 /* New pools, and emptied pools, will have a NULL symbol. */
2769 if (pool
->symbol
== NULL
)
2771 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2772 (valueT
) 0, &zero_address_frag
);
2773 pool
->id
= latest_pool_num
++;
2780 /* Add the literal in the global 'inst'
2781 structure to the relevant literal pool. */
2784 add_to_lit_pool (void)
2786 literal_pool
* pool
;
2789 pool
= find_or_make_literal_pool ();
2791 /* Check if this literal value is already in the pool. */
2792 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2794 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2795 && (inst
.reloc
.exp
.X_op
== O_constant
)
2796 && (pool
->literals
[entry
].X_add_number
2797 == inst
.reloc
.exp
.X_add_number
)
2798 && (pool
->literals
[entry
].X_unsigned
2799 == inst
.reloc
.exp
.X_unsigned
))
2802 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2803 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2804 && (pool
->literals
[entry
].X_add_number
2805 == inst
.reloc
.exp
.X_add_number
)
2806 && (pool
->literals
[entry
].X_add_symbol
2807 == inst
.reloc
.exp
.X_add_symbol
)
2808 && (pool
->literals
[entry
].X_op_symbol
2809 == inst
.reloc
.exp
.X_op_symbol
))
2813 /* Do we need to create a new entry? */
2814 if (entry
== pool
->next_free_entry
)
2816 if (entry
>= MAX_LITERAL_POOL_SIZE
)
2818 inst
.error
= _("literal pool overflow");
2822 pool
->literals
[entry
] = inst
.reloc
.exp
;
2823 pool
->next_free_entry
+= 1;
2826 inst
.reloc
.exp
.X_op
= O_symbol
;
2827 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
2828 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
2833 /* Can't use symbol_new here, so have to create a symbol and then at
2834 a later date assign it a value. Thats what these functions do. */
2837 symbol_locate (symbolS
* symbolP
,
2838 const char * name
, /* It is copied, the caller can modify. */
2839 segT segment
, /* Segment identifier (SEG_<something>). */
2840 valueT valu
, /* Symbol value. */
2841 fragS
* frag
) /* Associated fragment. */
2843 unsigned int name_length
;
2844 char * preserved_copy_of_name
;
2846 name_length
= strlen (name
) + 1; /* +1 for \0. */
2847 obstack_grow (¬es
, name
, name_length
);
2848 preserved_copy_of_name
= obstack_finish (¬es
);
2850 #ifdef tc_canonicalize_symbol_name
2851 preserved_copy_of_name
=
2852 tc_canonicalize_symbol_name (preserved_copy_of_name
);
2855 S_SET_NAME (symbolP
, preserved_copy_of_name
);
2857 S_SET_SEGMENT (symbolP
, segment
);
2858 S_SET_VALUE (symbolP
, valu
);
2859 symbol_clear_list_pointers (symbolP
);
2861 symbol_set_frag (symbolP
, frag
);
2863 /* Link to end of symbol chain. */
2865 extern int symbol_table_frozen
;
2867 if (symbol_table_frozen
)
2871 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
2873 obj_symbol_new_hook (symbolP
);
2875 #ifdef tc_symbol_new_hook
2876 tc_symbol_new_hook (symbolP
);
2880 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
2881 #endif /* DEBUG_SYMS */
2886 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
2889 literal_pool
* pool
;
2892 pool
= find_literal_pool ();
2894 || pool
->symbol
== NULL
2895 || pool
->next_free_entry
== 0)
2898 mapping_state (MAP_DATA
);
2900 /* Align pool as you have word accesses.
2901 Only make a frag if we have to. */
2903 frag_align (2, 0, 0);
2905 record_alignment (now_seg
, 2);
2907 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
2909 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
2910 (valueT
) frag_now_fix (), frag_now
);
2911 symbol_table_insert (pool
->symbol
);
2913 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
2915 #if defined OBJ_COFF || defined OBJ_ELF
2916 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
2919 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2920 /* First output the expression in the instruction to the pool. */
2921 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
2923 /* Mark the pool as empty. */
2924 pool
->next_free_entry
= 0;
2925 pool
->symbol
= NULL
;
2929 /* Forward declarations for functions below, in the MD interface
2931 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
2932 static valueT
create_unwind_entry (int);
2933 static void start_unwind_section (const segT
, int);
2934 static void add_unwind_opcode (valueT
, int);
2935 static void flush_pending_unwind (void);
2937 /* Directives: Data. */
2940 s_arm_elf_cons (int nbytes
)
2944 #ifdef md_flush_pending_output
2945 md_flush_pending_output ();
2948 if (is_it_end_of_statement ())
2950 demand_empty_rest_of_line ();
2954 #ifdef md_cons_align
2955 md_cons_align (nbytes
);
2958 mapping_state (MAP_DATA
);
2962 char *base
= input_line_pointer
;
2966 if (exp
.X_op
!= O_symbol
)
2967 emit_expr (&exp
, (unsigned int) nbytes
);
2970 char *before_reloc
= input_line_pointer
;
2971 reloc
= parse_reloc (&input_line_pointer
);
2974 as_bad (_("unrecognized relocation suffix"));
2975 ignore_rest_of_line ();
2978 else if (reloc
== BFD_RELOC_UNUSED
)
2979 emit_expr (&exp
, (unsigned int) nbytes
);
2982 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
2983 int size
= bfd_get_reloc_size (howto
);
2985 if (reloc
== BFD_RELOC_ARM_PLT32
)
2987 as_bad (_("(plt) is only valid on branch targets"));
2988 reloc
= BFD_RELOC_UNUSED
;
2993 as_bad (_("%s relocations do not fit in %d bytes"),
2994 howto
->name
, nbytes
);
2997 /* We've parsed an expression stopping at O_symbol.
2998 But there may be more expression left now that we
2999 have parsed the relocation marker. Parse it again.
3000 XXX Surely there is a cleaner way to do this. */
3001 char *p
= input_line_pointer
;
3003 char *save_buf
= alloca (input_line_pointer
- base
);
3004 memcpy (save_buf
, base
, input_line_pointer
- base
);
3005 memmove (base
+ (input_line_pointer
- before_reloc
),
3006 base
, before_reloc
- base
);
3008 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3010 memcpy (base
, save_buf
, p
- base
);
3012 offset
= nbytes
- size
;
3013 p
= frag_more ((int) nbytes
);
3014 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3015 size
, &exp
, 0, reloc
);
3020 while (*input_line_pointer
++ == ',');
3022 /* Put terminator back into stream. */
3023 input_line_pointer
--;
3024 demand_empty_rest_of_line ();
3028 /* Parse a .rel31 directive. */
3031 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3038 if (*input_line_pointer
== '1')
3039 highbit
= 0x80000000;
3040 else if (*input_line_pointer
!= '0')
3041 as_bad (_("expected 0 or 1"));
3043 input_line_pointer
++;
3044 if (*input_line_pointer
!= ',')
3045 as_bad (_("missing comma"));
3046 input_line_pointer
++;
3048 #ifdef md_flush_pending_output
3049 md_flush_pending_output ();
3052 #ifdef md_cons_align
3056 mapping_state (MAP_DATA
);
3061 md_number_to_chars (p
, highbit
, 4);
3062 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3063 BFD_RELOC_ARM_PREL31
);
3065 demand_empty_rest_of_line ();
3068 /* Directives: AEABI stack-unwind tables. */
3070 /* Parse an unwind_fnstart directive. Simply records the current location. */
3073 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3075 demand_empty_rest_of_line ();
3076 /* Mark the start of the function. */
3077 unwind
.proc_start
= expr_build_dot ();
3079 /* Reset the rest of the unwind info. */
3080 unwind
.opcode_count
= 0;
3081 unwind
.table_entry
= NULL
;
3082 unwind
.personality_routine
= NULL
;
3083 unwind
.personality_index
= -1;
3084 unwind
.frame_size
= 0;
3085 unwind
.fp_offset
= 0;
3088 unwind
.sp_restored
= 0;
3092 /* Parse a handlerdata directive. Creates the exception handling table entry
3093 for the function. */
3096 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3098 demand_empty_rest_of_line ();
3099 if (unwind
.table_entry
)
3100 as_bad (_("duplicate .handlerdata directive"));
3102 create_unwind_entry (1);
3105 /* Parse an unwind_fnend directive. Generates the index table entry. */
3108 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3114 demand_empty_rest_of_line ();
3116 /* Add eh table entry. */
3117 if (unwind
.table_entry
== NULL
)
3118 val
= create_unwind_entry (0);
3122 /* Add index table entry. This is two words. */
3123 start_unwind_section (unwind
.saved_seg
, 1);
3124 frag_align (2, 0, 0);
3125 record_alignment (now_seg
, 2);
3127 ptr
= frag_more (8);
3128 where
= frag_now_fix () - 8;
3130 /* Self relative offset of the function start. */
3131 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3132 BFD_RELOC_ARM_PREL31
);
3134 /* Indicate dependency on EHABI-defined personality routines to the
3135 linker, if it hasn't been done already. */
3136 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3137 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3139 static const char *const name
[] =
3141 "__aeabi_unwind_cpp_pr0",
3142 "__aeabi_unwind_cpp_pr1",
3143 "__aeabi_unwind_cpp_pr2"
3145 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3146 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3147 marked_pr_dependency
|= 1 << unwind
.personality_index
;
3148 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3149 = marked_pr_dependency
;
3153 /* Inline exception table entry. */
3154 md_number_to_chars (ptr
+ 4, val
, 4);
3156 /* Self relative offset of the table entry. */
3157 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3158 BFD_RELOC_ARM_PREL31
);
3160 /* Restore the original section. */
3161 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3165 /* Parse an unwind_cantunwind directive. */
3168 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3170 demand_empty_rest_of_line ();
3171 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3172 as_bad (_("personality routine specified for cantunwind frame"));
3174 unwind
.personality_index
= -2;
3178 /* Parse a personalityindex directive. */
3181 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3185 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3186 as_bad (_("duplicate .personalityindex directive"));
3190 if (exp
.X_op
!= O_constant
3191 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3193 as_bad (_("bad personality routine number"));
3194 ignore_rest_of_line ();
3198 unwind
.personality_index
= exp
.X_add_number
;
3200 demand_empty_rest_of_line ();
3204 /* Parse a personality directive. */
3207 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3211 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3212 as_bad (_("duplicate .personality directive"));
3214 name
= input_line_pointer
;
3215 c
= get_symbol_end ();
3216 p
= input_line_pointer
;
3217 unwind
.personality_routine
= symbol_find_or_make (name
);
3219 demand_empty_rest_of_line ();
3223 /* Parse a directive saving core registers. */
3226 s_arm_unwind_save_core (void)
3232 range
= parse_reg_list (&input_line_pointer
);
3235 as_bad (_("expected register list"));
3236 ignore_rest_of_line ();
3240 demand_empty_rest_of_line ();
3242 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3243 into .unwind_save {..., sp...}. We aren't bothered about the value of
3244 ip because it is clobbered by calls. */
3245 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3246 && (range
& 0x3000) == 0x1000)
3248 unwind
.opcode_count
--;
3249 unwind
.sp_restored
= 0;
3250 range
= (range
| 0x2000) & ~0x1000;
3251 unwind
.pending_offset
= 0;
3257 /* See if we can use the short opcodes. These pop a block of up to 8
3258 registers starting with r4, plus maybe r14. */
3259 for (n
= 0; n
< 8; n
++)
3261 /* Break at the first non-saved register. */
3262 if ((range
& (1 << (n
+ 4))) == 0)
3265 /* See if there are any other bits set. */
3266 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3268 /* Use the long form. */
3269 op
= 0x8000 | ((range
>> 4) & 0xfff);
3270 add_unwind_opcode (op
, 2);
3274 /* Use the short form. */
3276 op
= 0xa8; /* Pop r14. */
3278 op
= 0xa0; /* Do not pop r14. */
3280 add_unwind_opcode (op
, 1);
3287 op
= 0xb100 | (range
& 0xf);
3288 add_unwind_opcode (op
, 2);
3291 /* Record the number of bytes pushed. */
3292 for (n
= 0; n
< 16; n
++)
3294 if (range
& (1 << n
))
3295 unwind
.frame_size
+= 4;
3300 /* Parse a directive saving FPA registers. */
3303 s_arm_unwind_save_fpa (int reg
)
3309 /* Get Number of registers to transfer. */
3310 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3313 exp
.X_op
= O_illegal
;
3315 if (exp
.X_op
!= O_constant
)
3317 as_bad (_("expected , <constant>"));
3318 ignore_rest_of_line ();
3322 num_regs
= exp
.X_add_number
;
3324 if (num_regs
< 1 || num_regs
> 4)
3326 as_bad (_("number of registers must be in the range [1:4]"));
3327 ignore_rest_of_line ();
3331 demand_empty_rest_of_line ();
3336 op
= 0xb4 | (num_regs
- 1);
3337 add_unwind_opcode (op
, 1);
3342 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3343 add_unwind_opcode (op
, 2);
3345 unwind
.frame_size
+= num_regs
* 12;
3349 /* Parse a directive saving VFP registers for ARMv6 and above. */
3352 s_arm_unwind_save_vfp_armv6 (void)
3357 int num_vfpv3_regs
= 0;
3358 int num_regs_below_16
;
3360 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3363 as_bad (_("expected register list"));
3364 ignore_rest_of_line ();
3368 demand_empty_rest_of_line ();
3370 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3371 than FSTMX/FLDMX-style ones). */
3373 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3375 num_vfpv3_regs
= count
;
3376 else if (start
+ count
> 16)
3377 num_vfpv3_regs
= start
+ count
- 16;
3379 if (num_vfpv3_regs
> 0)
3381 int start_offset
= start
> 16 ? start
- 16 : 0;
3382 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3383 add_unwind_opcode (op
, 2);
3386 /* Generate opcode for registers numbered in the range 0 .. 15. */
3387 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3388 assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3389 if (num_regs_below_16
> 0)
3391 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3392 add_unwind_opcode (op
, 2);
3395 unwind
.frame_size
+= count
* 8;
3399 /* Parse a directive saving VFP registers for pre-ARMv6. */
3402 s_arm_unwind_save_vfp (void)
3408 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3411 as_bad (_("expected register list"));
3412 ignore_rest_of_line ();
3416 demand_empty_rest_of_line ();
3421 op
= 0xb8 | (count
- 1);
3422 add_unwind_opcode (op
, 1);
3427 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3428 add_unwind_opcode (op
, 2);
3430 unwind
.frame_size
+= count
* 8 + 4;
3434 /* Parse a directive saving iWMMXt data registers. */
3437 s_arm_unwind_save_mmxwr (void)
3445 if (*input_line_pointer
== '{')
3446 input_line_pointer
++;
3450 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3454 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3459 as_tsktsk (_("register list not in ascending order"));
3462 if (*input_line_pointer
== '-')
3464 input_line_pointer
++;
3465 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3468 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3471 else if (reg
>= hi_reg
)
3473 as_bad (_("bad register range"));
3476 for (; reg
< hi_reg
; reg
++)
3480 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3482 if (*input_line_pointer
== '}')
3483 input_line_pointer
++;
3485 demand_empty_rest_of_line ();
3487 /* Generate any deferred opcodes because we're going to be looking at
3489 flush_pending_unwind ();
3491 for (i
= 0; i
< 16; i
++)
3493 if (mask
& (1 << i
))
3494 unwind
.frame_size
+= 8;
3497 /* Attempt to combine with a previous opcode. We do this because gcc
3498 likes to output separate unwind directives for a single block of
3500 if (unwind
.opcode_count
> 0)
3502 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3503 if ((i
& 0xf8) == 0xc0)
3506 /* Only merge if the blocks are contiguous. */
3509 if ((mask
& 0xfe00) == (1 << 9))
3511 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3512 unwind
.opcode_count
--;
3515 else if (i
== 6 && unwind
.opcode_count
>= 2)
3517 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3521 op
= 0xffff << (reg
- 1);
3523 && ((mask
& op
) == (1u << (reg
- 1))))
3525 op
= (1 << (reg
+ i
+ 1)) - 1;
3526 op
&= ~((1 << reg
) - 1);
3528 unwind
.opcode_count
-= 2;
3535 /* We want to generate opcodes in the order the registers have been
3536 saved, ie. descending order. */
3537 for (reg
= 15; reg
>= -1; reg
--)
3539 /* Save registers in blocks. */
3541 || !(mask
& (1 << reg
)))
3543 /* We found an unsaved reg. Generate opcodes to save the
3550 op
= 0xc0 | (hi_reg
- 10);
3551 add_unwind_opcode (op
, 1);
3556 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3557 add_unwind_opcode (op
, 2);
3566 ignore_rest_of_line ();
3570 s_arm_unwind_save_mmxwcg (void)
3577 if (*input_line_pointer
== '{')
3578 input_line_pointer
++;
3582 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3586 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3592 as_tsktsk (_("register list not in ascending order"));
3595 if (*input_line_pointer
== '-')
3597 input_line_pointer
++;
3598 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3601 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3604 else if (reg
>= hi_reg
)
3606 as_bad (_("bad register range"));
3609 for (; reg
< hi_reg
; reg
++)
3613 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3615 if (*input_line_pointer
== '}')
3616 input_line_pointer
++;
3618 demand_empty_rest_of_line ();
3620 /* Generate any deferred opcodes because we're going to be looking at
3622 flush_pending_unwind ();
3624 for (reg
= 0; reg
< 16; reg
++)
3626 if (mask
& (1 << reg
))
3627 unwind
.frame_size
+= 4;
3630 add_unwind_opcode (op
, 2);
3633 ignore_rest_of_line ();
3637 /* Parse an unwind_save directive.
3638 If the argument is non-zero, this is a .vsave directive. */
3641 s_arm_unwind_save (int arch_v6
)
3644 struct reg_entry
*reg
;
3645 bfd_boolean had_brace
= FALSE
;
3647 /* Figure out what sort of save we have. */
3648 peek
= input_line_pointer
;
3656 reg
= arm_reg_parse_multi (&peek
);
3660 as_bad (_("register expected"));
3661 ignore_rest_of_line ();
3670 as_bad (_("FPA .unwind_save does not take a register list"));
3671 ignore_rest_of_line ();
3674 input_line_pointer
= peek
;
3675 s_arm_unwind_save_fpa (reg
->number
);
3678 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
3681 s_arm_unwind_save_vfp_armv6 ();
3683 s_arm_unwind_save_vfp ();
3685 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
3686 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
3689 as_bad (_(".unwind_save does not support this kind of register"));
3690 ignore_rest_of_line ();
3695 /* Parse an unwind_movsp directive. */
3698 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
3704 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3707 as_bad (_(reg_expected_msgs
[REG_TYPE_RN
]));
3708 ignore_rest_of_line ();
3712 /* Optional constant. */
3713 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3715 if (immediate_for_directive (&offset
) == FAIL
)
3721 demand_empty_rest_of_line ();
3723 if (reg
== REG_SP
|| reg
== REG_PC
)
3725 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
3729 if (unwind
.fp_reg
!= REG_SP
)
3730 as_bad (_("unexpected .unwind_movsp directive"));
3732 /* Generate opcode to restore the value. */
3734 add_unwind_opcode (op
, 1);
3736 /* Record the information for later. */
3737 unwind
.fp_reg
= reg
;
3738 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3739 unwind
.sp_restored
= 1;
3742 /* Parse an unwind_pad directive. */
3745 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
3749 if (immediate_for_directive (&offset
) == FAIL
)
3754 as_bad (_("stack increment must be multiple of 4"));
3755 ignore_rest_of_line ();
3759 /* Don't generate any opcodes, just record the details for later. */
3760 unwind
.frame_size
+= offset
;
3761 unwind
.pending_offset
+= offset
;
3763 demand_empty_rest_of_line ();
3766 /* Parse an unwind_setfp directive. */
3769 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
3775 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3776 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3779 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3781 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
3783 as_bad (_("expected <reg>, <reg>"));
3784 ignore_rest_of_line ();
3788 /* Optional constant. */
3789 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3791 if (immediate_for_directive (&offset
) == FAIL
)
3797 demand_empty_rest_of_line ();
3799 if (sp_reg
!= 13 && sp_reg
!= unwind
.fp_reg
)
3801 as_bad (_("register must be either sp or set by a previous"
3802 "unwind_movsp directive"));
3806 /* Don't generate any opcodes, just record the information for later. */
3807 unwind
.fp_reg
= fp_reg
;
3810 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3812 unwind
.fp_offset
-= offset
;
3815 /* Parse an unwind_raw directive. */
3818 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
3821 /* This is an arbitrary limit. */
3822 unsigned char op
[16];
3826 if (exp
.X_op
== O_constant
3827 && skip_past_comma (&input_line_pointer
) != FAIL
)
3829 unwind
.frame_size
+= exp
.X_add_number
;
3833 exp
.X_op
= O_illegal
;
3835 if (exp
.X_op
!= O_constant
)
3837 as_bad (_("expected <offset>, <opcode>"));
3838 ignore_rest_of_line ();
3844 /* Parse the opcode. */
3849 as_bad (_("unwind opcode too long"));
3850 ignore_rest_of_line ();
3852 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
3854 as_bad (_("invalid unwind opcode"));
3855 ignore_rest_of_line ();
3858 op
[count
++] = exp
.X_add_number
;
3860 /* Parse the next byte. */
3861 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3867 /* Add the opcode bytes in reverse order. */
3869 add_unwind_opcode (op
[count
], 1);
3871 demand_empty_rest_of_line ();
3875 /* Parse a .eabi_attribute directive. */
3878 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
3880 s_vendor_attribute (OBJ_ATTR_PROC
);
3882 #endif /* OBJ_ELF */
3884 static void s_arm_arch (int);
3885 static void s_arm_object_arch (int);
3886 static void s_arm_cpu (int);
3887 static void s_arm_fpu (int);
3892 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
3899 if (exp
.X_op
== O_symbol
)
3900 exp
.X_op
= O_secrel
;
3902 emit_expr (&exp
, 4);
3904 while (*input_line_pointer
++ == ',');
3906 input_line_pointer
--;
3907 demand_empty_rest_of_line ();
3911 /* This table describes all the machine specific pseudo-ops the assembler
3912 has to support. The fields are:
3913 pseudo-op name without dot
3914 function to call to execute this pseudo-op
3915 Integer arg to pass to the function. */
3917 const pseudo_typeS md_pseudo_table
[] =
3919 /* Never called because '.req' does not start a line. */
3920 { "req", s_req
, 0 },
3921 /* Following two are likewise never called. */
3924 { "unreq", s_unreq
, 0 },
3925 { "bss", s_bss
, 0 },
3926 { "align", s_align
, 0 },
3927 { "arm", s_arm
, 0 },
3928 { "thumb", s_thumb
, 0 },
3929 { "code", s_code
, 0 },
3930 { "force_thumb", s_force_thumb
, 0 },
3931 { "thumb_func", s_thumb_func
, 0 },
3932 { "thumb_set", s_thumb_set
, 0 },
3933 { "even", s_even
, 0 },
3934 { "ltorg", s_ltorg
, 0 },
3935 { "pool", s_ltorg
, 0 },
3936 { "syntax", s_syntax
, 0 },
3937 { "cpu", s_arm_cpu
, 0 },
3938 { "arch", s_arm_arch
, 0 },
3939 { "object_arch", s_arm_object_arch
, 0 },
3940 { "fpu", s_arm_fpu
, 0 },
3942 { "word", s_arm_elf_cons
, 4 },
3943 { "long", s_arm_elf_cons
, 4 },
3944 { "rel31", s_arm_rel31
, 0 },
3945 { "fnstart", s_arm_unwind_fnstart
, 0 },
3946 { "fnend", s_arm_unwind_fnend
, 0 },
3947 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
3948 { "personality", s_arm_unwind_personality
, 0 },
3949 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
3950 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
3951 { "save", s_arm_unwind_save
, 0 },
3952 { "vsave", s_arm_unwind_save
, 1 },
3953 { "movsp", s_arm_unwind_movsp
, 0 },
3954 { "pad", s_arm_unwind_pad
, 0 },
3955 { "setfp", s_arm_unwind_setfp
, 0 },
3956 { "unwind_raw", s_arm_unwind_raw
, 0 },
3957 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
3961 /* These are used for dwarf. */
3965 /* These are used for dwarf2. */
3966 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
3967 { "loc", dwarf2_directive_loc
, 0 },
3968 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
3970 { "extend", float_cons
, 'x' },
3971 { "ldouble", float_cons
, 'x' },
3972 { "packed", float_cons
, 'p' },
3974 {"secrel32", pe_directive_secrel
, 0},
3979 /* Parser functions used exclusively in instruction operands. */
3981 /* Generic immediate-value read function for use in insn parsing.
3982 STR points to the beginning of the immediate (the leading #);
3983 VAL receives the value; if the value is outside [MIN, MAX]
3984 issue an error. PREFIX_OPT is true if the immediate prefix is
3988 parse_immediate (char **str
, int *val
, int min
, int max
,
3989 bfd_boolean prefix_opt
)
3992 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
3993 if (exp
.X_op
!= O_constant
)
3995 inst
.error
= _("constant expression required");
3999 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4001 inst
.error
= _("immediate value out of range");
4005 *val
= exp
.X_add_number
;
4009 /* Less-generic immediate-value read function with the possibility of loading a
4010 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4011 instructions. Puts the result directly in inst.operands[i]. */
4014 parse_big_immediate (char **str
, int i
)
4019 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4021 if (exp
.X_op
== O_constant
)
4023 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4024 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4025 O_constant. We have to be careful not to break compilation for
4026 32-bit X_add_number, though. */
4027 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4029 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4030 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4031 inst
.operands
[i
].regisimm
= 1;
4034 else if (exp
.X_op
== O_big
4035 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4036 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4038 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4039 /* Bignums have their least significant bits in
4040 generic_bignum[0]. Make sure we put 32 bits in imm and
4041 32 bits in reg, in a (hopefully) portable way. */
4042 assert (parts
!= 0);
4043 inst
.operands
[i
].imm
= 0;
4044 for (j
= 0; j
< parts
; j
++, idx
++)
4045 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4046 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4047 inst
.operands
[i
].reg
= 0;
4048 for (j
= 0; j
< parts
; j
++, idx
++)
4049 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4050 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4051 inst
.operands
[i
].regisimm
= 1;
4061 /* Returns the pseudo-register number of an FPA immediate constant,
4062 or FAIL if there isn't a valid constant here. */
4065 parse_fpa_immediate (char ** str
)
4067 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4073 /* First try and match exact strings, this is to guarantee
4074 that some formats will work even for cross assembly. */
4076 for (i
= 0; fp_const
[i
]; i
++)
4078 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4082 *str
+= strlen (fp_const
[i
]);
4083 if (is_end_of_line
[(unsigned char) **str
])
4089 /* Just because we didn't get a match doesn't mean that the constant
4090 isn't valid, just that it is in a format that we don't
4091 automatically recognize. Try parsing it with the standard
4092 expression routines. */
4094 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4096 /* Look for a raw floating point number. */
4097 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4098 && is_end_of_line
[(unsigned char) *save_in
])
4100 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4102 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4104 if (words
[j
] != fp_values
[i
][j
])
4108 if (j
== MAX_LITTLENUMS
)
4116 /* Try and parse a more complex expression, this will probably fail
4117 unless the code uses a floating point prefix (eg "0f"). */
4118 save_in
= input_line_pointer
;
4119 input_line_pointer
= *str
;
4120 if (expression (&exp
) == absolute_section
4121 && exp
.X_op
== O_big
4122 && exp
.X_add_number
< 0)
4124 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4126 if (gen_to_words (words
, 5, (long) 15) == 0)
4128 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4130 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4132 if (words
[j
] != fp_values
[i
][j
])
4136 if (j
== MAX_LITTLENUMS
)
4138 *str
= input_line_pointer
;
4139 input_line_pointer
= save_in
;
4146 *str
= input_line_pointer
;
4147 input_line_pointer
= save_in
;
4148 inst
.error
= _("invalid FPA immediate expression");
4152 /* Returns 1 if a number has "quarter-precision" float format
4153 0baBbbbbbc defgh000 00000000 00000000. */
4156 is_quarter_float (unsigned imm
)
4158 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4159 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4162 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4163 0baBbbbbbc defgh000 00000000 00000000.
4164 The zero and minus-zero cases need special handling, since they can't be
4165 encoded in the "quarter-precision" float format, but can nonetheless be
4166 loaded as integer constants. */
4169 parse_qfloat_immediate (char **ccp
, int *immed
)
4173 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4174 int found_fpchar
= 0;
4176 skip_past_char (&str
, '#');
4178 /* We must not accidentally parse an integer as a floating-point number. Make
4179 sure that the value we parse is not an integer by checking for special
4180 characters '.' or 'e'.
4181 FIXME: This is a horrible hack, but doing better is tricky because type
4182 information isn't in a very usable state at parse time. */
4184 skip_whitespace (fpnum
);
4186 if (strncmp (fpnum
, "0x", 2) == 0)
4190 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4191 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4201 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4203 unsigned fpword
= 0;
4206 /* Our FP word must be 32 bits (single-precision FP). */
4207 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4209 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4213 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4226 /* Shift operands. */
4229 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4232 struct asm_shift_name
4235 enum shift_kind kind
;
4238 /* Third argument to parse_shift. */
4239 enum parse_shift_mode
4241 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4242 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4243 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4244 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4245 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4248 /* Parse a <shift> specifier on an ARM data processing instruction.
4249 This has three forms:
4251 (LSL|LSR|ASL|ASR|ROR) Rs
4252 (LSL|LSR|ASL|ASR|ROR) #imm
4255 Note that ASL is assimilated to LSL in the instruction encoding, and
4256 RRX to ROR #0 (which cannot be written as such). */
4259 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4261 const struct asm_shift_name
*shift_name
;
4262 enum shift_kind shift
;
4267 for (p
= *str
; ISALPHA (*p
); p
++)
4272 inst
.error
= _("shift expression expected");
4276 shift_name
= hash_find_n (arm_shift_hsh
, *str
, p
- *str
);
4278 if (shift_name
== NULL
)
4280 inst
.error
= _("shift expression expected");
4284 shift
= shift_name
->kind
;
4288 case NO_SHIFT_RESTRICT
:
4289 case SHIFT_IMMEDIATE
: break;
4291 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4292 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4294 inst
.error
= _("'LSL' or 'ASR' required");
4299 case SHIFT_LSL_IMMEDIATE
:
4300 if (shift
!= SHIFT_LSL
)
4302 inst
.error
= _("'LSL' required");
4307 case SHIFT_ASR_IMMEDIATE
:
4308 if (shift
!= SHIFT_ASR
)
4310 inst
.error
= _("'ASR' required");
4318 if (shift
!= SHIFT_RRX
)
4320 /* Whitespace can appear here if the next thing is a bare digit. */
4321 skip_whitespace (p
);
4323 if (mode
== NO_SHIFT_RESTRICT
4324 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4326 inst
.operands
[i
].imm
= reg
;
4327 inst
.operands
[i
].immisreg
= 1;
4329 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4332 inst
.operands
[i
].shift_kind
= shift
;
4333 inst
.operands
[i
].shifted
= 1;
4338 /* Parse a <shifter_operand> for an ARM data processing instruction:
4341 #<immediate>, <rotate>
4345 where <shift> is defined by parse_shift above, and <rotate> is a
4346 multiple of 2 between 0 and 30. Validation of immediate operands
4347 is deferred to md_apply_fix. */
4350 parse_shifter_operand (char **str
, int i
)
4355 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4357 inst
.operands
[i
].reg
= value
;
4358 inst
.operands
[i
].isreg
= 1;
4360 /* parse_shift will override this if appropriate */
4361 inst
.reloc
.exp
.X_op
= O_constant
;
4362 inst
.reloc
.exp
.X_add_number
= 0;
4364 if (skip_past_comma (str
) == FAIL
)
4367 /* Shift operation on register. */
4368 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4371 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4374 if (skip_past_comma (str
) == SUCCESS
)
4376 /* #x, y -- ie explicit rotation by Y. */
4377 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
4380 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4382 inst
.error
= _("constant expression expected");
4386 value
= expr
.X_add_number
;
4387 if (value
< 0 || value
> 30 || value
% 2 != 0)
4389 inst
.error
= _("invalid rotation");
4392 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4394 inst
.error
= _("invalid constant");
4398 /* Convert to decoded value. md_apply_fix will put it back. */
4399 inst
.reloc
.exp
.X_add_number
4400 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4401 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4404 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4405 inst
.reloc
.pc_rel
= 0;
4409 /* Group relocation information. Each entry in the table contains the
4410 textual name of the relocation as may appear in assembler source
4411 and must end with a colon.
4412 Along with this textual name are the relocation codes to be used if
4413 the corresponding instruction is an ALU instruction (ADD or SUB only),
4414 an LDR, an LDRS, or an LDC. */
4416 struct group_reloc_table_entry
4427 /* Varieties of non-ALU group relocation. */
4434 static struct group_reloc_table_entry group_reloc_table
[] =
4435 { /* Program counter relative: */
4437 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4442 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4443 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4444 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4445 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4447 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4452 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4453 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4454 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4455 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4457 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4458 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4459 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4460 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4461 /* Section base relative */
4463 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4468 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4469 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4470 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4471 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4473 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4478 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4479 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4480 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4481 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4483 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4484 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4485 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4486 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4488 /* Given the address of a pointer pointing to the textual name of a group
4489 relocation as may appear in assembler source, attempt to find its details
4490 in group_reloc_table. The pointer will be updated to the character after
4491 the trailing colon. On failure, FAIL will be returned; SUCCESS
4492 otherwise. On success, *entry will be updated to point at the relevant
4493 group_reloc_table entry. */
4496 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4499 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4501 int length
= strlen (group_reloc_table
[i
].name
);
4503 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4504 && (*str
)[length
] == ':')
4506 *out
= &group_reloc_table
[i
];
4507 *str
+= (length
+ 1);
4515 /* Parse a <shifter_operand> for an ARM data processing instruction
4516 (as for parse_shifter_operand) where group relocations are allowed:
4519 #<immediate>, <rotate>
4520 #:<group_reloc>:<expression>
4524 where <group_reloc> is one of the strings defined in group_reloc_table.
4525 The hashes are optional.
4527 Everything else is as for parse_shifter_operand. */
4529 static parse_operand_result
4530 parse_shifter_operand_group_reloc (char **str
, int i
)
4532 /* Determine if we have the sequence of characters #: or just :
4533 coming next. If we do, then we check for a group relocation.
4534 If we don't, punt the whole lot to parse_shifter_operand. */
4536 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4537 || (*str
)[0] == ':')
4539 struct group_reloc_table_entry
*entry
;
4541 if ((*str
)[0] == '#')
4546 /* Try to parse a group relocation. Anything else is an error. */
4547 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4549 inst
.error
= _("unknown group relocation");
4550 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4553 /* We now have the group relocation table entry corresponding to
4554 the name in the assembler source. Next, we parse the expression. */
4555 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4556 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4558 /* Record the relocation type (always the ALU variant here). */
4559 inst
.reloc
.type
= entry
->alu_code
;
4560 assert (inst
.reloc
.type
!= 0);
4562 return PARSE_OPERAND_SUCCESS
;
4565 return parse_shifter_operand (str
, i
) == SUCCESS
4566 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4568 /* Never reached. */
4571 /* Parse all forms of an ARM address expression. Information is written
4572 to inst.operands[i] and/or inst.reloc.
4574 Preindexed addressing (.preind=1):
4576 [Rn, #offset] .reg=Rn .reloc.exp=offset
4577 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4578 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4579 .shift_kind=shift .reloc.exp=shift_imm
4581 These three may have a trailing ! which causes .writeback to be set also.
4583 Postindexed addressing (.postind=1, .writeback=1):
4585 [Rn], #offset .reg=Rn .reloc.exp=offset
4586 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4587 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4588 .shift_kind=shift .reloc.exp=shift_imm
4590 Unindexed addressing (.preind=0, .postind=0):
4592 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4596 [Rn]{!} shorthand for [Rn,#0]{!}
4597 =immediate .isreg=0 .reloc.exp=immediate
4598 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4600 It is the caller's responsibility to check for addressing modes not
4601 supported by the instruction, and to set inst.reloc.type. */
4603 static parse_operand_result
4604 parse_address_main (char **str
, int i
, int group_relocations
,
4605 group_reloc_type group_type
)
4610 if (skip_past_char (&p
, '[') == FAIL
)
4612 if (skip_past_char (&p
, '=') == FAIL
)
4614 /* bare address - translate to PC-relative offset */
4615 inst
.reloc
.pc_rel
= 1;
4616 inst
.operands
[i
].reg
= REG_PC
;
4617 inst
.operands
[i
].isreg
= 1;
4618 inst
.operands
[i
].preind
= 1;
4620 /* else a load-constant pseudo op, no special treatment needed here */
4622 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4623 return PARSE_OPERAND_FAIL
;
4626 return PARSE_OPERAND_SUCCESS
;
4629 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4631 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4632 return PARSE_OPERAND_FAIL
;
4634 inst
.operands
[i
].reg
= reg
;
4635 inst
.operands
[i
].isreg
= 1;
4637 if (skip_past_comma (&p
) == SUCCESS
)
4639 inst
.operands
[i
].preind
= 1;
4642 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4644 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4646 inst
.operands
[i
].imm
= reg
;
4647 inst
.operands
[i
].immisreg
= 1;
4649 if (skip_past_comma (&p
) == SUCCESS
)
4650 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4651 return PARSE_OPERAND_FAIL
;
4653 else if (skip_past_char (&p
, ':') == SUCCESS
)
4655 /* FIXME: '@' should be used here, but it's filtered out by generic
4656 code before we get to see it here. This may be subject to
4659 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4660 if (exp
.X_op
!= O_constant
)
4662 inst
.error
= _("alignment must be constant");
4663 return PARSE_OPERAND_FAIL
;
4665 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4666 inst
.operands
[i
].immisalign
= 1;
4667 /* Alignments are not pre-indexes. */
4668 inst
.operands
[i
].preind
= 0;
4672 if (inst
.operands
[i
].negative
)
4674 inst
.operands
[i
].negative
= 0;
4678 if (group_relocations
4679 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
4681 struct group_reloc_table_entry
*entry
;
4683 /* Skip over the #: or : sequence. */
4689 /* Try to parse a group relocation. Anything else is an
4691 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
4693 inst
.error
= _("unknown group relocation");
4694 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4697 /* We now have the group relocation table entry corresponding to
4698 the name in the assembler source. Next, we parse the
4700 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4701 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4703 /* Record the relocation type. */
4707 inst
.reloc
.type
= entry
->ldr_code
;
4711 inst
.reloc
.type
= entry
->ldrs_code
;
4715 inst
.reloc
.type
= entry
->ldc_code
;
4722 if (inst
.reloc
.type
== 0)
4724 inst
.error
= _("this group relocation is not allowed on this instruction");
4725 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4729 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4730 return PARSE_OPERAND_FAIL
;
4734 if (skip_past_char (&p
, ']') == FAIL
)
4736 inst
.error
= _("']' expected");
4737 return PARSE_OPERAND_FAIL
;
4740 if (skip_past_char (&p
, '!') == SUCCESS
)
4741 inst
.operands
[i
].writeback
= 1;
4743 else if (skip_past_comma (&p
) == SUCCESS
)
4745 if (skip_past_char (&p
, '{') == SUCCESS
)
4747 /* [Rn], {expr} - unindexed, with option */
4748 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
4749 0, 255, TRUE
) == FAIL
)
4750 return PARSE_OPERAND_FAIL
;
4752 if (skip_past_char (&p
, '}') == FAIL
)
4754 inst
.error
= _("'}' expected at end of 'option' field");
4755 return PARSE_OPERAND_FAIL
;
4757 if (inst
.operands
[i
].preind
)
4759 inst
.error
= _("cannot combine index with option");
4760 return PARSE_OPERAND_FAIL
;
4763 return PARSE_OPERAND_SUCCESS
;
4767 inst
.operands
[i
].postind
= 1;
4768 inst
.operands
[i
].writeback
= 1;
4770 if (inst
.operands
[i
].preind
)
4772 inst
.error
= _("cannot combine pre- and post-indexing");
4773 return PARSE_OPERAND_FAIL
;
4777 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4779 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4781 /* We might be using the immediate for alignment already. If we
4782 are, OR the register number into the low-order bits. */
4783 if (inst
.operands
[i
].immisalign
)
4784 inst
.operands
[i
].imm
|= reg
;
4786 inst
.operands
[i
].imm
= reg
;
4787 inst
.operands
[i
].immisreg
= 1;
4789 if (skip_past_comma (&p
) == SUCCESS
)
4790 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4791 return PARSE_OPERAND_FAIL
;
4795 if (inst
.operands
[i
].negative
)
4797 inst
.operands
[i
].negative
= 0;
4800 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4801 return PARSE_OPERAND_FAIL
;
4806 /* If at this point neither .preind nor .postind is set, we have a
4807 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
4808 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
4810 inst
.operands
[i
].preind
= 1;
4811 inst
.reloc
.exp
.X_op
= O_constant
;
4812 inst
.reloc
.exp
.X_add_number
= 0;
4815 return PARSE_OPERAND_SUCCESS
;
4819 parse_address (char **str
, int i
)
4821 return parse_address_main (str
, i
, 0, 0) == PARSE_OPERAND_SUCCESS
4825 static parse_operand_result
4826 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
4828 return parse_address_main (str
, i
, 1, type
);
4831 /* Parse an operand for a MOVW or MOVT instruction. */
4833 parse_half (char **str
)
4838 skip_past_char (&p
, '#');
4839 if (strncasecmp (p
, ":lower16:", 9) == 0)
4840 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
4841 else if (strncasecmp (p
, ":upper16:", 9) == 0)
4842 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
4844 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4847 skip_whitespace (p
);
4850 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4853 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4855 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4857 inst
.error
= _("constant expression expected");
4860 if (inst
.reloc
.exp
.X_add_number
< 0
4861 || inst
.reloc
.exp
.X_add_number
> 0xffff)
4863 inst
.error
= _("immediate value out of range");
4871 /* Miscellaneous. */
4873 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
4874 or a bitmask suitable to be or-ed into the ARM msr instruction. */
4876 parse_psr (char **str
)
4879 unsigned long psr_field
;
4880 const struct asm_psr
*psr
;
4883 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
4884 feature for ease of use and backwards compatibility. */
4886 if (strncasecmp (p
, "SPSR", 4) == 0)
4887 psr_field
= SPSR_BIT
;
4888 else if (strncasecmp (p
, "CPSR", 4) == 0)
4895 while (ISALNUM (*p
) || *p
== '_');
4897 psr
= hash_find_n (arm_v7m_psr_hsh
, start
, p
- start
);
4908 /* A suffix follows. */
4914 while (ISALNUM (*p
) || *p
== '_');
4916 psr
= hash_find_n (arm_psr_hsh
, start
, p
- start
);
4920 psr_field
|= psr
->field
;
4925 goto error
; /* Garbage after "[CS]PSR". */
4927 psr_field
|= (PSR_c
| PSR_f
);
4933 inst
.error
= _("flag for {c}psr instruction expected");
4937 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
4938 value suitable for splatting into the AIF field of the instruction. */
4941 parse_cps_flags (char **str
)
4950 case '\0': case ',':
4953 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
4954 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
4955 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
4958 inst
.error
= _("unrecognized CPS flag");
4963 if (saw_a_flag
== 0)
4965 inst
.error
= _("missing CPS flags");
4973 /* Parse an endian specifier ("BE" or "LE", case insensitive);
4974 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
4977 parse_endian_specifier (char **str
)
4982 if (strncasecmp (s
, "BE", 2))
4984 else if (strncasecmp (s
, "LE", 2))
4988 inst
.error
= _("valid endian specifiers are be or le");
4992 if (ISALNUM (s
[2]) || s
[2] == '_')
4994 inst
.error
= _("valid endian specifiers are be or le");
4999 return little_endian
;
5002 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5003 value suitable for poking into the rotate field of an sxt or sxta
5004 instruction, or FAIL on error. */
5007 parse_ror (char **str
)
5012 if (strncasecmp (s
, "ROR", 3) == 0)
5016 inst
.error
= _("missing rotation field after comma");
5020 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5025 case 0: *str
= s
; return 0x0;
5026 case 8: *str
= s
; return 0x1;
5027 case 16: *str
= s
; return 0x2;
5028 case 24: *str
= s
; return 0x3;
5031 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5036 /* Parse a conditional code (from conds[] below). The value returned is in the
5037 range 0 .. 14, or FAIL. */
5039 parse_cond (char **str
)
5042 const struct asm_cond
*c
;
5045 while (ISALPHA (*q
))
5048 c
= hash_find_n (arm_cond_hsh
, p
, q
- p
);
5051 inst
.error
= _("condition required");
5059 /* Parse an option for a barrier instruction. Returns the encoding for the
5062 parse_barrier (char **str
)
5065 const struct asm_barrier_opt
*o
;
5068 while (ISALPHA (*q
))
5071 o
= hash_find_n (arm_barrier_opt_hsh
, p
, q
- p
);
5079 /* Parse the operands of a table branch instruction. Similar to a memory
5082 parse_tb (char **str
)
5087 if (skip_past_char (&p
, '[') == FAIL
)
5089 inst
.error
= _("'[' expected");
5093 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5095 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5098 inst
.operands
[0].reg
= reg
;
5100 if (skip_past_comma (&p
) == FAIL
)
5102 inst
.error
= _("',' expected");
5106 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5108 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5111 inst
.operands
[0].imm
= reg
;
5113 if (skip_past_comma (&p
) == SUCCESS
)
5115 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5117 if (inst
.reloc
.exp
.X_add_number
!= 1)
5119 inst
.error
= _("invalid shift");
5122 inst
.operands
[0].shifted
= 1;
5125 if (skip_past_char (&p
, ']') == FAIL
)
5127 inst
.error
= _("']' expected");
5134 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5135 information on the types the operands can take and how they are encoded.
5136 Up to four operands may be read; this function handles setting the
5137 ".present" field for each read operand itself.
5138 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5139 else returns FAIL. */
5142 parse_neon_mov (char **str
, int *which_operand
)
5144 int i
= *which_operand
, val
;
5145 enum arm_reg_type rtype
;
5147 struct neon_type_el optype
;
5149 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5151 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5152 inst
.operands
[i
].reg
= val
;
5153 inst
.operands
[i
].isscalar
= 1;
5154 inst
.operands
[i
].vectype
= optype
;
5155 inst
.operands
[i
++].present
= 1;
5157 if (skip_past_comma (&ptr
) == FAIL
)
5160 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5163 inst
.operands
[i
].reg
= val
;
5164 inst
.operands
[i
].isreg
= 1;
5165 inst
.operands
[i
].present
= 1;
5167 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5170 /* Cases 0, 1, 2, 3, 5 (D only). */
5171 if (skip_past_comma (&ptr
) == FAIL
)
5174 inst
.operands
[i
].reg
= val
;
5175 inst
.operands
[i
].isreg
= 1;
5176 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5177 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5178 inst
.operands
[i
].isvec
= 1;
5179 inst
.operands
[i
].vectype
= optype
;
5180 inst
.operands
[i
++].present
= 1;
5182 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5184 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5185 Case 13: VMOV <Sd>, <Rm> */
5186 inst
.operands
[i
].reg
= val
;
5187 inst
.operands
[i
].isreg
= 1;
5188 inst
.operands
[i
].present
= 1;
5190 if (rtype
== REG_TYPE_NQ
)
5192 first_error (_("can't use Neon quad register here"));
5195 else if (rtype
!= REG_TYPE_VFS
)
5198 if (skip_past_comma (&ptr
) == FAIL
)
5200 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5202 inst
.operands
[i
].reg
= val
;
5203 inst
.operands
[i
].isreg
= 1;
5204 inst
.operands
[i
].present
= 1;
5207 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5208 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5209 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5210 Case 10: VMOV.F32 <Sd>, #<imm>
5211 Case 11: VMOV.F64 <Dd>, #<imm> */
5212 inst
.operands
[i
].immisfloat
= 1;
5213 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5214 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5215 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5217 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5220 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5221 Case 1: VMOV<c><q> <Dd>, <Dm>
5222 Case 8: VMOV.F32 <Sd>, <Sm>
5223 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5225 inst
.operands
[i
].reg
= val
;
5226 inst
.operands
[i
].isreg
= 1;
5227 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5228 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5229 inst
.operands
[i
].isvec
= 1;
5230 inst
.operands
[i
].vectype
= optype
;
5231 inst
.operands
[i
].present
= 1;
5233 if (skip_past_comma (&ptr
) == SUCCESS
)
5238 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5241 inst
.operands
[i
].reg
= val
;
5242 inst
.operands
[i
].isreg
= 1;
5243 inst
.operands
[i
++].present
= 1;
5245 if (skip_past_comma (&ptr
) == FAIL
)
5248 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5251 inst
.operands
[i
].reg
= val
;
5252 inst
.operands
[i
].isreg
= 1;
5253 inst
.operands
[i
++].present
= 1;
5258 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5262 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5265 inst
.operands
[i
].reg
= val
;
5266 inst
.operands
[i
].isreg
= 1;
5267 inst
.operands
[i
++].present
= 1;
5269 if (skip_past_comma (&ptr
) == FAIL
)
5272 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5274 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5275 inst
.operands
[i
].reg
= val
;
5276 inst
.operands
[i
].isscalar
= 1;
5277 inst
.operands
[i
].present
= 1;
5278 inst
.operands
[i
].vectype
= optype
;
5280 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5282 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5283 inst
.operands
[i
].reg
= val
;
5284 inst
.operands
[i
].isreg
= 1;
5285 inst
.operands
[i
++].present
= 1;
5287 if (skip_past_comma (&ptr
) == FAIL
)
5290 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5293 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5297 inst
.operands
[i
].reg
= val
;
5298 inst
.operands
[i
].isreg
= 1;
5299 inst
.operands
[i
].isvec
= 1;
5300 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5301 inst
.operands
[i
].vectype
= optype
;
5302 inst
.operands
[i
].present
= 1;
5304 if (rtype
== REG_TYPE_VFS
)
5308 if (skip_past_comma (&ptr
) == FAIL
)
5310 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5313 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5316 inst
.operands
[i
].reg
= val
;
5317 inst
.operands
[i
].isreg
= 1;
5318 inst
.operands
[i
].isvec
= 1;
5319 inst
.operands
[i
].issingle
= 1;
5320 inst
.operands
[i
].vectype
= optype
;
5321 inst
.operands
[i
].present
= 1;
5324 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5328 inst
.operands
[i
].reg
= val
;
5329 inst
.operands
[i
].isreg
= 1;
5330 inst
.operands
[i
].isvec
= 1;
5331 inst
.operands
[i
].issingle
= 1;
5332 inst
.operands
[i
].vectype
= optype
;
5333 inst
.operands
[i
++].present
= 1;
5338 first_error (_("parse error"));
5342 /* Successfully parsed the operands. Update args. */
5348 first_error (_("expected comma"));
5352 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5356 /* Matcher codes for parse_operands. */
5357 enum operand_parse_code
5359 OP_stop
, /* end of line */
5361 OP_RR
, /* ARM register */
5362 OP_RRnpc
, /* ARM register, not r15 */
5363 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5364 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5365 OP_RCP
, /* Coprocessor number */
5366 OP_RCN
, /* Coprocessor register */
5367 OP_RF
, /* FPA register */
5368 OP_RVS
, /* VFP single precision register */
5369 OP_RVD
, /* VFP double precision register (0..15) */
5370 OP_RND
, /* Neon double precision register (0..31) */
5371 OP_RNQ
, /* Neon quad precision register */
5372 OP_RVSD
, /* VFP single or double precision register */
5373 OP_RNDQ
, /* Neon double or quad precision register */
5374 OP_RNSDQ
, /* Neon single, double or quad precision register */
5375 OP_RNSC
, /* Neon scalar D[X] */
5376 OP_RVC
, /* VFP control register */
5377 OP_RMF
, /* Maverick F register */
5378 OP_RMD
, /* Maverick D register */
5379 OP_RMFX
, /* Maverick FX register */
5380 OP_RMDX
, /* Maverick DX register */
5381 OP_RMAX
, /* Maverick AX register */
5382 OP_RMDS
, /* Maverick DSPSC register */
5383 OP_RIWR
, /* iWMMXt wR register */
5384 OP_RIWC
, /* iWMMXt wC register */
5385 OP_RIWG
, /* iWMMXt wCG register */
5386 OP_RXA
, /* XScale accumulator register */
5388 OP_REGLST
, /* ARM register list */
5389 OP_VRSLST
, /* VFP single-precision register list */
5390 OP_VRDLST
, /* VFP double-precision register list */
5391 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5392 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5393 OP_NSTRLST
, /* Neon element/structure list */
5395 OP_NILO
, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5396 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5397 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5398 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5399 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5400 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5401 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5402 OP_VMOV
, /* Neon VMOV operands. */
5403 OP_RNDQ_IMVNb
,/* Neon D or Q reg, or immediate good for VMVN. */
5404 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5405 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5407 OP_I0
, /* immediate zero */
5408 OP_I7
, /* immediate value 0 .. 7 */
5409 OP_I15
, /* 0 .. 15 */
5410 OP_I16
, /* 1 .. 16 */
5411 OP_I16z
, /* 0 .. 16 */
5412 OP_I31
, /* 0 .. 31 */
5413 OP_I31w
, /* 0 .. 31, optional trailing ! */
5414 OP_I32
, /* 1 .. 32 */
5415 OP_I32z
, /* 0 .. 32 */
5416 OP_I63
, /* 0 .. 63 */
5417 OP_I63s
, /* -64 .. 63 */
5418 OP_I64
, /* 1 .. 64 */
5419 OP_I64z
, /* 0 .. 64 */
5420 OP_I255
, /* 0 .. 255 */
5422 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5423 OP_I7b
, /* 0 .. 7 */
5424 OP_I15b
, /* 0 .. 15 */
5425 OP_I31b
, /* 0 .. 31 */
5427 OP_SH
, /* shifter operand */
5428 OP_SHG
, /* shifter operand with possible group relocation */
5429 OP_ADDR
, /* Memory address expression (any mode) */
5430 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5431 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5432 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5433 OP_EXP
, /* arbitrary expression */
5434 OP_EXPi
, /* same, with optional immediate prefix */
5435 OP_EXPr
, /* same, with optional relocation suffix */
5436 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5438 OP_CPSF
, /* CPS flags */
5439 OP_ENDI
, /* Endianness specifier */
5440 OP_PSR
, /* CPSR/SPSR mask for msr */
5441 OP_COND
, /* conditional code */
5442 OP_TB
, /* Table branch. */
5444 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5445 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5447 OP_RRnpc_I0
, /* ARM register or literal 0 */
5448 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5449 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5450 OP_RF_IF
, /* FPA register or immediate */
5451 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5452 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5454 /* Optional operands. */
5455 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5456 OP_oI31b
, /* 0 .. 31 */
5457 OP_oI32b
, /* 1 .. 32 */
5458 OP_oIffffb
, /* 0 .. 65535 */
5459 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5461 OP_oRR
, /* ARM register */
5462 OP_oRRnpc
, /* ARM register, not the PC */
5463 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5464 OP_oRND
, /* Optional Neon double precision register */
5465 OP_oRNQ
, /* Optional Neon quad precision register */
5466 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5467 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5468 OP_oSHll
, /* LSL immediate */
5469 OP_oSHar
, /* ASR immediate */
5470 OP_oSHllar
, /* LSL or ASR immediate */
5471 OP_oROR
, /* ROR 0/8/16/24 */
5472 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5474 OP_FIRST_OPTIONAL
= OP_oI7b
5477 /* Generic instruction operand parser. This does no encoding and no
5478 semantic validation; it merely squirrels values away in the inst
5479 structure. Returns SUCCESS or FAIL depending on whether the
5480 specified grammar matched. */
5482 parse_operands (char *str
, const unsigned char *pattern
)
5484 unsigned const char *upat
= pattern
;
5485 char *backtrack_pos
= 0;
5486 const char *backtrack_error
= 0;
5487 int i
, val
, backtrack_index
= 0;
5488 enum arm_reg_type rtype
;
5489 parse_operand_result result
;
5491 #define po_char_or_fail(chr) do { \
5492 if (skip_past_char (&str, chr) == FAIL) \
5496 #define po_reg_or_fail(regtype) do { \
5497 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5498 &inst.operands[i].vectype); \
5501 first_error (_(reg_expected_msgs[regtype])); \
5504 inst.operands[i].reg = val; \
5505 inst.operands[i].isreg = 1; \
5506 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5507 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5508 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5509 || rtype == REG_TYPE_VFD \
5510 || rtype == REG_TYPE_NQ); \
5513 #define po_reg_or_goto(regtype, label) do { \
5514 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5515 &inst.operands[i].vectype); \
5519 inst.operands[i].reg = val; \
5520 inst.operands[i].isreg = 1; \
5521 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5522 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5523 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5524 || rtype == REG_TYPE_VFD \
5525 || rtype == REG_TYPE_NQ); \
5528 #define po_imm_or_fail(min, max, popt) do { \
5529 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5531 inst.operands[i].imm = val; \
5534 #define po_scalar_or_goto(elsz, label) do { \
5535 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \
5538 inst.operands[i].reg = val; \
5539 inst.operands[i].isscalar = 1; \
5542 #define po_misc_or_fail(expr) do { \
5547 #define po_misc_or_fail_no_backtrack(expr) do { \
5549 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
5550 backtrack_pos = 0; \
5551 if (result != PARSE_OPERAND_SUCCESS) \
5555 skip_whitespace (str
);
5557 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5559 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5561 /* Remember where we are in case we need to backtrack. */
5562 assert (!backtrack_pos
);
5563 backtrack_pos
= str
;
5564 backtrack_error
= inst
.error
;
5565 backtrack_index
= i
;
5568 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
5569 po_char_or_fail (',');
5577 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5578 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5579 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5580 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5581 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5582 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5584 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5586 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
5588 /* Also accept generic coprocessor regs for unknown registers. */
5590 po_reg_or_fail (REG_TYPE_CN
);
5592 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5593 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5594 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5595 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5596 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5597 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5598 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5599 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5600 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5601 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5603 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
5605 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
5606 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
5608 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
5610 /* Neon scalar. Using an element size of 8 means that some invalid
5611 scalars are accepted here, so deal with those in later code. */
5612 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
5614 /* WARNING: We can expand to two operands here. This has the potential
5615 to totally confuse the backtracking mechanism! It will be OK at
5616 least as long as we don't try to use optional args as well,
5620 po_reg_or_goto (REG_TYPE_NDQ
, try_imm
);
5621 inst
.operands
[i
].present
= 1;
5623 skip_past_comma (&str
);
5624 po_reg_or_goto (REG_TYPE_NDQ
, one_reg_only
);
5627 /* Optional register operand was omitted. Unfortunately, it's in
5628 operands[i-1] and we need it to be in inst.operands[i]. Fix that
5629 here (this is a bit grotty). */
5630 inst
.operands
[i
] = inst
.operands
[i
-1];
5631 inst
.operands
[i
-1].present
= 0;
5634 /* There's a possibility of getting a 64-bit immediate here, so
5635 we need special handling. */
5636 if (parse_big_immediate (&str
, i
) == FAIL
)
5638 inst
.error
= _("immediate value is out of range");
5646 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
5649 po_imm_or_fail (0, 0, TRUE
);
5654 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
5659 po_scalar_or_goto (8, try_rr
);
5662 po_reg_or_fail (REG_TYPE_RN
);
5668 po_scalar_or_goto (8, try_nsdq
);
5671 po_reg_or_fail (REG_TYPE_NSDQ
);
5677 po_scalar_or_goto (8, try_ndq
);
5680 po_reg_or_fail (REG_TYPE_NDQ
);
5686 po_scalar_or_goto (8, try_vfd
);
5689 po_reg_or_fail (REG_TYPE_VFD
);
5694 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
5695 not careful then bad things might happen. */
5696 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
5701 po_reg_or_goto (REG_TYPE_NDQ
, try_mvnimm
);
5704 /* There's a possibility of getting a 64-bit immediate here, so
5705 we need special handling. */
5706 if (parse_big_immediate (&str
, i
) == FAIL
)
5708 inst
.error
= _("immediate value is out of range");
5716 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
5719 po_imm_or_fail (0, 63, TRUE
);
5724 po_char_or_fail ('[');
5725 po_reg_or_fail (REG_TYPE_RN
);
5726 po_char_or_fail (']');
5731 po_reg_or_fail (REG_TYPE_RN
);
5732 if (skip_past_char (&str
, '!') == SUCCESS
)
5733 inst
.operands
[i
].writeback
= 1;
5737 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
5738 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
5739 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
5740 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
5741 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
5742 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
5743 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
5744 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
5745 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
5746 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
5747 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
5748 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
5750 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
5752 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
5753 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
5755 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
5756 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
5757 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
5759 /* Immediate variants */
5761 po_char_or_fail ('{');
5762 po_imm_or_fail (0, 255, TRUE
);
5763 po_char_or_fail ('}');
5767 /* The expression parser chokes on a trailing !, so we have
5768 to find it first and zap it. */
5771 while (*s
&& *s
!= ',')
5776 inst
.operands
[i
].writeback
= 1;
5778 po_imm_or_fail (0, 31, TRUE
);
5786 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5791 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5796 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5798 if (inst
.reloc
.exp
.X_op
== O_symbol
)
5800 val
= parse_reloc (&str
);
5803 inst
.error
= _("unrecognized relocation suffix");
5806 else if (val
!= BFD_RELOC_UNUSED
)
5808 inst
.operands
[i
].imm
= val
;
5809 inst
.operands
[i
].hasreloc
= 1;
5814 /* Operand for MOVW or MOVT. */
5816 po_misc_or_fail (parse_half (&str
));
5819 /* Register or expression */
5820 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
5821 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
5823 /* Register or immediate */
5824 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
5825 I0
: po_imm_or_fail (0, 0, FALSE
); break;
5827 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
5829 if (!is_immediate_prefix (*str
))
5832 val
= parse_fpa_immediate (&str
);
5835 /* FPA immediates are encoded as registers 8-15.
5836 parse_fpa_immediate has already applied the offset. */
5837 inst
.operands
[i
].reg
= val
;
5838 inst
.operands
[i
].isreg
= 1;
5841 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
5842 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
5844 /* Two kinds of register */
5847 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5849 || (rege
->type
!= REG_TYPE_MMXWR
5850 && rege
->type
!= REG_TYPE_MMXWC
5851 && rege
->type
!= REG_TYPE_MMXWCG
))
5853 inst
.error
= _("iWMMXt data or control register expected");
5856 inst
.operands
[i
].reg
= rege
->number
;
5857 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
5863 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5865 || (rege
->type
!= REG_TYPE_MMXWC
5866 && rege
->type
!= REG_TYPE_MMXWCG
))
5868 inst
.error
= _("iWMMXt control register expected");
5871 inst
.operands
[i
].reg
= rege
->number
;
5872 inst
.operands
[i
].isreg
= 1;
5877 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
5878 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
5879 case OP_oROR
: val
= parse_ror (&str
); break;
5880 case OP_PSR
: val
= parse_psr (&str
); break;
5881 case OP_COND
: val
= parse_cond (&str
); break;
5882 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
5885 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
5886 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
5889 val
= parse_psr (&str
);
5893 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
5896 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
5898 if (strncasecmp (str
, "APSR_", 5) == 0)
5905 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
5906 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
5907 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
5908 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
5909 default: found
= 16;
5913 inst
.operands
[i
].isvec
= 1;
5920 po_misc_or_fail (parse_tb (&str
));
5923 /* Register lists */
5925 val
= parse_reg_list (&str
);
5928 inst
.operands
[1].writeback
= 1;
5934 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
5938 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
5942 /* Allow Q registers too. */
5943 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5948 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5950 inst
.operands
[i
].issingle
= 1;
5955 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5960 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
5961 &inst
.operands
[i
].vectype
);
5964 /* Addressing modes */
5966 po_misc_or_fail (parse_address (&str
, i
));
5970 po_misc_or_fail_no_backtrack (
5971 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
5975 po_misc_or_fail_no_backtrack (
5976 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
5980 po_misc_or_fail_no_backtrack (
5981 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
5985 po_misc_or_fail (parse_shifter_operand (&str
, i
));
5989 po_misc_or_fail_no_backtrack (
5990 parse_shifter_operand_group_reloc (&str
, i
));
5994 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
5998 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6002 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6006 as_fatal (_("unhandled operand code %d"), upat
[i
]);
6009 /* Various value-based sanity checks and shared operations. We
6010 do not signal immediate failures for the register constraints;
6011 this allows a syntax error to take precedence. */
6020 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6021 inst
.error
= BAD_PC
;
6039 inst
.operands
[i
].imm
= val
;
6046 /* If we get here, this operand was successfully parsed. */
6047 inst
.operands
[i
].present
= 1;
6051 inst
.error
= BAD_ARGS
;
6056 /* The parse routine should already have set inst.error, but set a
6057 default here just in case. */
6059 inst
.error
= _("syntax error");
6063 /* Do not backtrack over a trailing optional argument that
6064 absorbed some text. We will only fail again, with the
6065 'garbage following instruction' error message, which is
6066 probably less helpful than the current one. */
6067 if (backtrack_index
== i
&& backtrack_pos
!= str
6068 && upat
[i
+1] == OP_stop
)
6071 inst
.error
= _("syntax error");
6075 /* Try again, skipping the optional argument at backtrack_pos. */
6076 str
= backtrack_pos
;
6077 inst
.error
= backtrack_error
;
6078 inst
.operands
[backtrack_index
].present
= 0;
6079 i
= backtrack_index
;
6083 /* Check that we have parsed all the arguments. */
6084 if (*str
!= '\0' && !inst
.error
)
6085 inst
.error
= _("garbage following instruction");
6087 return inst
.error
? FAIL
: SUCCESS
;
6090 #undef po_char_or_fail
6091 #undef po_reg_or_fail
6092 #undef po_reg_or_goto
6093 #undef po_imm_or_fail
6094 #undef po_scalar_or_fail
6096 /* Shorthand macro for instruction encoding functions issuing errors. */
6097 #define constraint(expr, err) do { \
6105 /* Functions for operand encoding. ARM, then Thumb. */
6107 #define rotate_left(v, n) (v << n | v >> (32 - n))
6109 /* If VAL can be encoded in the immediate field of an ARM instruction,
6110 return the encoded form. Otherwise, return FAIL. */
6113 encode_arm_immediate (unsigned int val
)
6117 for (i
= 0; i
< 32; i
+= 2)
6118 if ((a
= rotate_left (val
, i
)) <= 0xff)
6119 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6124 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6125 return the encoded form. Otherwise, return FAIL. */
6127 encode_thumb32_immediate (unsigned int val
)
6134 for (i
= 1; i
<= 24; i
++)
6137 if ((val
& ~(0xff << i
)) == 0)
6138 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6142 if (val
== ((a
<< 16) | a
))
6144 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6148 if (val
== ((a
<< 16) | a
))
6149 return 0x200 | (a
>> 8);
6153 /* Encode a VFP SP or DP register number into inst.instruction. */
6156 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6158 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6161 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
6164 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6167 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6172 first_error (_("D register out of range for selected VFP version"));
6180 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6184 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6188 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6192 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6196 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6200 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6208 /* Encode a <shift> in an ARM-format instruction. The immediate,
6209 if any, is handled by md_apply_fix. */
6211 encode_arm_shift (int i
)
6213 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6214 inst
.instruction
|= SHIFT_ROR
<< 5;
6217 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6218 if (inst
.operands
[i
].immisreg
)
6220 inst
.instruction
|= SHIFT_BY_REG
;
6221 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6224 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6229 encode_arm_shifter_operand (int i
)
6231 if (inst
.operands
[i
].isreg
)
6233 inst
.instruction
|= inst
.operands
[i
].reg
;
6234 encode_arm_shift (i
);
6237 inst
.instruction
|= INST_IMMEDIATE
;
6240 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6242 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6244 assert (inst
.operands
[i
].isreg
);
6245 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6247 if (inst
.operands
[i
].preind
)
6251 inst
.error
= _("instruction does not accept preindexed addressing");
6254 inst
.instruction
|= PRE_INDEX
;
6255 if (inst
.operands
[i
].writeback
)
6256 inst
.instruction
|= WRITE_BACK
;
6259 else if (inst
.operands
[i
].postind
)
6261 assert (inst
.operands
[i
].writeback
);
6263 inst
.instruction
|= WRITE_BACK
;
6265 else /* unindexed - only for coprocessor */
6267 inst
.error
= _("instruction does not accept unindexed addressing");
6271 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6272 && (((inst
.instruction
& 0x000f0000) >> 16)
6273 == ((inst
.instruction
& 0x0000f000) >> 12)))
6274 as_warn ((inst
.instruction
& LOAD_BIT
)
6275 ? _("destination register same as write-back base")
6276 : _("source register same as write-back base"));
6279 /* inst.operands[i] was set up by parse_address. Encode it into an
6280 ARM-format mode 2 load or store instruction. If is_t is true,
6281 reject forms that cannot be used with a T instruction (i.e. not
6284 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6286 encode_arm_addr_mode_common (i
, is_t
);
6288 if (inst
.operands
[i
].immisreg
)
6290 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6291 inst
.instruction
|= inst
.operands
[i
].imm
;
6292 if (!inst
.operands
[i
].negative
)
6293 inst
.instruction
|= INDEX_UP
;
6294 if (inst
.operands
[i
].shifted
)
6296 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6297 inst
.instruction
|= SHIFT_ROR
<< 5;
6300 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6301 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6305 else /* immediate offset in inst.reloc */
6307 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6308 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6312 /* inst.operands[i] was set up by parse_address. Encode it into an
6313 ARM-format mode 3 load or store instruction. Reject forms that
6314 cannot be used with such instructions. If is_t is true, reject
6315 forms that cannot be used with a T instruction (i.e. not
6318 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6320 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6322 inst
.error
= _("instruction does not accept scaled register index");
6326 encode_arm_addr_mode_common (i
, is_t
);
6328 if (inst
.operands
[i
].immisreg
)
6330 inst
.instruction
|= inst
.operands
[i
].imm
;
6331 if (!inst
.operands
[i
].negative
)
6332 inst
.instruction
|= INDEX_UP
;
6334 else /* immediate offset in inst.reloc */
6336 inst
.instruction
|= HWOFFSET_IMM
;
6337 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6338 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6342 /* inst.operands[i] was set up by parse_address. Encode it into an
6343 ARM-format instruction. Reject all forms which cannot be encoded
6344 into a coprocessor load/store instruction. If wb_ok is false,
6345 reject use of writeback; if unind_ok is false, reject use of
6346 unindexed addressing. If reloc_override is not 0, use it instead
6347 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6348 (in which case it is preserved). */
6351 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6353 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6355 assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6357 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6359 assert (!inst
.operands
[i
].writeback
);
6362 inst
.error
= _("instruction does not support unindexed addressing");
6365 inst
.instruction
|= inst
.operands
[i
].imm
;
6366 inst
.instruction
|= INDEX_UP
;
6370 if (inst
.operands
[i
].preind
)
6371 inst
.instruction
|= PRE_INDEX
;
6373 if (inst
.operands
[i
].writeback
)
6375 if (inst
.operands
[i
].reg
== REG_PC
)
6377 inst
.error
= _("pc may not be used with write-back");
6382 inst
.error
= _("instruction does not support writeback");
6385 inst
.instruction
|= WRITE_BACK
;
6389 inst
.reloc
.type
= reloc_override
;
6390 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6391 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6392 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6395 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6397 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6403 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6404 Determine whether it can be performed with a move instruction; if
6405 it can, convert inst.instruction to that move instruction and
6406 return 1; if it can't, convert inst.instruction to a literal-pool
6407 load and return 0. If this is not a valid thing to do in the
6408 current context, set inst.error and return 1.
6410 inst.operands[i] describes the destination register. */
6413 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6418 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6422 if ((inst
.instruction
& tbit
) == 0)
6424 inst
.error
= _("invalid pseudo operation");
6427 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6429 inst
.error
= _("constant expression expected");
6432 if (inst
.reloc
.exp
.X_op
== O_constant
)
6436 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6438 /* This can be done with a mov(1) instruction. */
6439 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6440 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6446 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6449 /* This can be done with a mov instruction. */
6450 inst
.instruction
&= LITERAL_MASK
;
6451 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6452 inst
.instruction
|= value
& 0xfff;
6456 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6459 /* This can be done with a mvn instruction. */
6460 inst
.instruction
&= LITERAL_MASK
;
6461 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6462 inst
.instruction
|= value
& 0xfff;
6468 if (add_to_lit_pool () == FAIL
)
6470 inst
.error
= _("literal pool insertion failed");
6473 inst
.operands
[1].reg
= REG_PC
;
6474 inst
.operands
[1].isreg
= 1;
6475 inst
.operands
[1].preind
= 1;
6476 inst
.reloc
.pc_rel
= 1;
6477 inst
.reloc
.type
= (thumb_p
6478 ? BFD_RELOC_ARM_THUMB_OFFSET
6480 ? BFD_RELOC_ARM_HWLITERAL
6481 : BFD_RELOC_ARM_LITERAL
));
6485 /* Functions for instruction encoding, sorted by sub-architecture.
6486 First some generics; their names are taken from the conventional
6487 bit positions for register arguments in ARM format instructions. */
6497 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6503 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6504 inst
.instruction
|= inst
.operands
[1].reg
;
6510 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6511 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6517 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6518 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6524 unsigned Rn
= inst
.operands
[2].reg
;
6525 /* Enforce restrictions on SWP instruction. */
6526 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6527 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6528 _("Rn must not overlap other operands"));
6529 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6530 inst
.instruction
|= inst
.operands
[1].reg
;
6531 inst
.instruction
|= Rn
<< 16;
6537 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6538 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6539 inst
.instruction
|= inst
.operands
[2].reg
;
6545 inst
.instruction
|= inst
.operands
[0].reg
;
6546 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6547 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6553 inst
.instruction
|= inst
.operands
[0].imm
;
6559 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6560 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6563 /* ARM instructions, in alphabetical order by function name (except
6564 that wrapper functions appear immediately after the function they
6567 /* This is a pseudo-op of the form "adr rd, label" to be converted
6568 into a relative address of the form "add rd, pc, #label-.-8". */
6573 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6575 /* Frag hacking will turn this into a sub instruction if the offset turns
6576 out to be negative. */
6577 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6578 inst
.reloc
.pc_rel
= 1;
6579 inst
.reloc
.exp
.X_add_number
-= 8;
6582 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6583 into a relative address of the form:
6584 add rd, pc, #low(label-.-8)"
6585 add rd, rd, #high(label-.-8)" */
6590 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6592 /* Frag hacking will turn this into a sub instruction if the offset turns
6593 out to be negative. */
6594 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
6595 inst
.reloc
.pc_rel
= 1;
6596 inst
.size
= INSN_SIZE
* 2;
6597 inst
.reloc
.exp
.X_add_number
-= 8;
6603 if (!inst
.operands
[1].present
)
6604 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
6605 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6606 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6607 encode_arm_shifter_operand (2);
6613 if (inst
.operands
[0].present
)
6615 constraint ((inst
.instruction
& 0xf0) != 0x40
6616 && inst
.operands
[0].imm
!= 0xf,
6617 _("bad barrier type"));
6618 inst
.instruction
|= inst
.operands
[0].imm
;
6621 inst
.instruction
|= 0xf;
6627 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
6628 constraint (msb
> 32, _("bit-field extends past end of register"));
6629 /* The instruction encoding stores the LSB and MSB,
6630 not the LSB and width. */
6631 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6632 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
6633 inst
.instruction
|= (msb
- 1) << 16;
6641 /* #0 in second position is alternative syntax for bfc, which is
6642 the same instruction but with REG_PC in the Rm field. */
6643 if (!inst
.operands
[1].isreg
)
6644 inst
.operands
[1].reg
= REG_PC
;
6646 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
6647 constraint (msb
> 32, _("bit-field extends past end of register"));
6648 /* The instruction encoding stores the LSB and MSB,
6649 not the LSB and width. */
6650 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6651 inst
.instruction
|= inst
.operands
[1].reg
;
6652 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6653 inst
.instruction
|= (msb
- 1) << 16;
6659 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
6660 _("bit-field extends past end of register"));
6661 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6662 inst
.instruction
|= inst
.operands
[1].reg
;
6663 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6664 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
6667 /* ARM V5 breakpoint instruction (argument parse)
6668 BKPT <16 bit unsigned immediate>
6669 Instruction is not conditional.
6670 The bit pattern given in insns[] has the COND_ALWAYS condition,
6671 and it is an error if the caller tried to override that. */
6676 /* Top 12 of 16 bits to bits 19:8. */
6677 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
6679 /* Bottom 4 of 16 bits to bits 3:0. */
6680 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
6684 encode_branch (int default_reloc
)
6686 if (inst
.operands
[0].hasreloc
)
6688 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
6689 _("the only suffix valid here is '(plt)'"));
6690 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
6694 inst
.reloc
.type
= default_reloc
;
6696 inst
.reloc
.pc_rel
= 1;
6703 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6704 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6707 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6714 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6716 if (inst
.cond
== COND_ALWAYS
)
6717 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6719 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6723 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6726 /* ARM V5 branch-link-exchange instruction (argument parse)
6727 BLX <target_addr> ie BLX(1)
6728 BLX{<condition>} <Rm> ie BLX(2)
6729 Unfortunately, there are two different opcodes for this mnemonic.
6730 So, the insns[].value is not used, and the code here zaps values
6731 into inst.instruction.
6732 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
6737 if (inst
.operands
[0].isreg
)
6739 /* Arg is a register; the opcode provided by insns[] is correct.
6740 It is not illegal to do "blx pc", just useless. */
6741 if (inst
.operands
[0].reg
== REG_PC
)
6742 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
6744 inst
.instruction
|= inst
.operands
[0].reg
;
6748 /* Arg is an address; this instruction cannot be executed
6749 conditionally, and the opcode must be adjusted. */
6750 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
6751 inst
.instruction
= 0xfa000000;
6753 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6754 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6757 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
6764 bfd_boolean want_reloc
;
6766 if (inst
.operands
[0].reg
== REG_PC
)
6767 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
6769 inst
.instruction
|= inst
.operands
[0].reg
;
6770 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
6771 it is for ARMv4t or earlier. */
6772 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
6773 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
6777 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
6782 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
6786 /* ARM v5TEJ. Jump to Jazelle code. */
6791 if (inst
.operands
[0].reg
== REG_PC
)
6792 as_tsktsk (_("use of r15 in bxj is not really useful"));
6794 inst
.instruction
|= inst
.operands
[0].reg
;
6797 /* Co-processor data operation:
6798 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
6799 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
6803 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6804 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
6805 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6806 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6807 inst
.instruction
|= inst
.operands
[4].reg
;
6808 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6814 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6815 encode_arm_shifter_operand (1);
6818 /* Transfer between coprocessor and ARM registers.
6819 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
6824 No special properties. */
6829 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6830 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
6831 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6832 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6833 inst
.instruction
|= inst
.operands
[4].reg
;
6834 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6837 /* Transfer between coprocessor register and pair of ARM registers.
6838 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6843 Two XScale instructions are special cases of these:
6845 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
6846 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
6848 Result unpredictable if Rd or Rn is R15. */
6853 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6854 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
6855 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6856 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6857 inst
.instruction
|= inst
.operands
[4].reg
;
6863 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
6864 if (inst
.operands
[1].present
)
6866 inst
.instruction
|= CPSI_MMOD
;
6867 inst
.instruction
|= inst
.operands
[1].imm
;
6874 inst
.instruction
|= inst
.operands
[0].imm
;
6880 /* There is no IT instruction in ARM mode. We
6881 process it but do not generate code for it. */
6888 int base_reg
= inst
.operands
[0].reg
;
6889 int range
= inst
.operands
[1].imm
;
6891 inst
.instruction
|= base_reg
<< 16;
6892 inst
.instruction
|= range
;
6894 if (inst
.operands
[1].writeback
)
6895 inst
.instruction
|= LDM_TYPE_2_OR_3
;
6897 if (inst
.operands
[0].writeback
)
6899 inst
.instruction
|= WRITE_BACK
;
6900 /* Check for unpredictable uses of writeback. */
6901 if (inst
.instruction
& LOAD_BIT
)
6903 /* Not allowed in LDM type 2. */
6904 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
6905 && ((range
& (1 << REG_PC
)) == 0))
6906 as_warn (_("writeback of base register is UNPREDICTABLE"));
6907 /* Only allowed if base reg not in list for other types. */
6908 else if (range
& (1 << base_reg
))
6909 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
6913 /* Not allowed for type 2. */
6914 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
6915 as_warn (_("writeback of base register is UNPREDICTABLE"));
6916 /* Only allowed if base reg not in list, or first in list. */
6917 else if ((range
& (1 << base_reg
))
6918 && (range
& ((1 << base_reg
) - 1)))
6919 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
6924 /* ARMv5TE load-consecutive (argument parse)
6933 constraint (inst
.operands
[0].reg
% 2 != 0,
6934 _("first destination register must be even"));
6935 constraint (inst
.operands
[1].present
6936 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
6937 _("can only load two consecutive registers"));
6938 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
6939 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
6941 if (!inst
.operands
[1].present
)
6942 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
6944 if (inst
.instruction
& LOAD_BIT
)
6946 /* encode_arm_addr_mode_3 will diagnose overlap between the base
6947 register and the first register written; we have to diagnose
6948 overlap between the base and the second register written here. */
6950 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
6951 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
6952 as_warn (_("base register written back, and overlaps "
6953 "second destination register"));
6955 /* For an index-register load, the index register must not overlap the
6956 destination (even if not write-back). */
6957 else if (inst
.operands
[2].immisreg
6958 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
6959 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
6960 as_warn (_("index register overlaps destination register"));
6963 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6964 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
6970 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
6971 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
6972 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
6973 || inst
.operands
[1].negative
6974 /* This can arise if the programmer has written
6976 or if they have mistakenly used a register name as the last
6979 It is very difficult to distinguish between these two cases
6980 because "rX" might actually be a label. ie the register
6981 name has been occluded by a symbol of the same name. So we
6982 just generate a general 'bad addressing mode' type error
6983 message and leave it up to the programmer to discover the
6984 true cause and fix their mistake. */
6985 || (inst
.operands
[1].reg
== REG_PC
),
6988 constraint (inst
.reloc
.exp
.X_op
!= O_constant
6989 || inst
.reloc
.exp
.X_add_number
!= 0,
6990 _("offset must be zero in ARM encoding"));
6992 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6993 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6994 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7000 constraint (inst
.operands
[0].reg
% 2 != 0,
7001 _("even register required"));
7002 constraint (inst
.operands
[1].present
7003 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7004 _("can only load two consecutive registers"));
7005 /* If op 1 were present and equal to PC, this function wouldn't
7006 have been called in the first place. */
7007 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7009 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7010 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7016 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7017 if (!inst
.operands
[1].isreg
)
7018 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7020 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7026 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7028 if (inst
.operands
[1].preind
)
7030 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7031 || inst
.reloc
.exp
.X_add_number
!= 0,
7032 _("this instruction requires a post-indexed address"));
7034 inst
.operands
[1].preind
= 0;
7035 inst
.operands
[1].postind
= 1;
7036 inst
.operands
[1].writeback
= 1;
7038 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7039 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7042 /* Halfword and signed-byte load/store operations. */
7047 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7048 if (!inst
.operands
[1].isreg
)
7049 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7051 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7057 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7059 if (inst
.operands
[1].preind
)
7061 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7062 || inst
.reloc
.exp
.X_add_number
!= 0,
7063 _("this instruction requires a post-indexed address"));
7065 inst
.operands
[1].preind
= 0;
7066 inst
.operands
[1].postind
= 1;
7067 inst
.operands
[1].writeback
= 1;
7069 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7070 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7073 /* Co-processor register load/store.
7074 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7078 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7079 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7080 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7086 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7087 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7088 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7089 && !(inst
.instruction
& 0x00400000))
7090 as_tsktsk (_("Rd and Rm should be different in mla"));
7092 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7093 inst
.instruction
|= inst
.operands
[1].reg
;
7094 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7095 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7101 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7102 encode_arm_shifter_operand (1);
7105 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7112 top
= (inst
.instruction
& 0x00400000) != 0;
7113 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7114 _(":lower16: not allowed this instruction"));
7115 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7116 _(":upper16: not allowed instruction"));
7117 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7118 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7120 imm
= inst
.reloc
.exp
.X_add_number
;
7121 /* The value is in two pieces: 0:11, 16:19. */
7122 inst
.instruction
|= (imm
& 0x00000fff);
7123 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7127 static void do_vfp_nsyn_opcode (const char *);
7130 do_vfp_nsyn_mrs (void)
7132 if (inst
.operands
[0].isvec
)
7134 if (inst
.operands
[1].reg
!= 1)
7135 first_error (_("operand 1 must be FPSCR"));
7136 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7137 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7138 do_vfp_nsyn_opcode ("fmstat");
7140 else if (inst
.operands
[1].isvec
)
7141 do_vfp_nsyn_opcode ("fmrx");
7149 do_vfp_nsyn_msr (void)
7151 if (inst
.operands
[0].isvec
)
7152 do_vfp_nsyn_opcode ("fmxr");
7162 if (do_vfp_nsyn_mrs () == SUCCESS
)
7165 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7166 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7168 _("'CPSR' or 'SPSR' expected"));
7169 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7170 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7173 /* Two possible forms:
7174 "{C|S}PSR_<field>, Rm",
7175 "{C|S}PSR_f, #expression". */
7180 if (do_vfp_nsyn_msr () == SUCCESS
)
7183 inst
.instruction
|= inst
.operands
[0].imm
;
7184 if (inst
.operands
[1].isreg
)
7185 inst
.instruction
|= inst
.operands
[1].reg
;
7188 inst
.instruction
|= INST_IMMEDIATE
;
7189 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7190 inst
.reloc
.pc_rel
= 0;
7197 if (!inst
.operands
[2].present
)
7198 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7199 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7200 inst
.instruction
|= inst
.operands
[1].reg
;
7201 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7203 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7204 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7205 as_tsktsk (_("Rd and Rm should be different in mul"));
7208 /* Long Multiply Parser
7209 UMULL RdLo, RdHi, Rm, Rs
7210 SMULL RdLo, RdHi, Rm, Rs
7211 UMLAL RdLo, RdHi, Rm, Rs
7212 SMLAL RdLo, RdHi, Rm, Rs. */
7217 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7218 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7219 inst
.instruction
|= inst
.operands
[2].reg
;
7220 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7222 /* rdhi and rdlo must be different. */
7223 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7224 as_tsktsk (_("rdhi and rdlo must be different"));
7226 /* rdhi, rdlo and rm must all be different before armv6. */
7227 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7228 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7229 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7230 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7236 if (inst
.operands
[0].present
)
7238 /* Architectural NOP hints are CPSR sets with no bits selected. */
7239 inst
.instruction
&= 0xf0000000;
7240 inst
.instruction
|= 0x0320f000 + inst
.operands
[0].imm
;
7244 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7245 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7246 Condition defaults to COND_ALWAYS.
7247 Error if Rd, Rn or Rm are R15. */
7252 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7253 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7254 inst
.instruction
|= inst
.operands
[2].reg
;
7255 if (inst
.operands
[3].present
)
7256 encode_arm_shift (3);
7259 /* ARM V6 PKHTB (Argument Parse). */
7264 if (!inst
.operands
[3].present
)
7266 /* If the shift specifier is omitted, turn the instruction
7267 into pkhbt rd, rm, rn. */
7268 inst
.instruction
&= 0xfff00010;
7269 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7270 inst
.instruction
|= inst
.operands
[1].reg
;
7271 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7275 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7276 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7277 inst
.instruction
|= inst
.operands
[2].reg
;
7278 encode_arm_shift (3);
7282 /* ARMv5TE: Preload-Cache
7286 Syntactically, like LDR with B=1, W=0, L=1. */
7291 constraint (!inst
.operands
[0].isreg
,
7292 _("'[' expected after PLD mnemonic"));
7293 constraint (inst
.operands
[0].postind
,
7294 _("post-indexed expression used in preload instruction"));
7295 constraint (inst
.operands
[0].writeback
,
7296 _("writeback used in preload instruction"));
7297 constraint (!inst
.operands
[0].preind
,
7298 _("unindexed addressing used in preload instruction"));
7299 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7302 /* ARMv7: PLI <addr_mode> */
7306 constraint (!inst
.operands
[0].isreg
,
7307 _("'[' expected after PLI mnemonic"));
7308 constraint (inst
.operands
[0].postind
,
7309 _("post-indexed expression used in preload instruction"));
7310 constraint (inst
.operands
[0].writeback
,
7311 _("writeback used in preload instruction"));
7312 constraint (!inst
.operands
[0].preind
,
7313 _("unindexed addressing used in preload instruction"));
7314 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7315 inst
.instruction
&= ~PRE_INDEX
;
7321 inst
.operands
[1] = inst
.operands
[0];
7322 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7323 inst
.operands
[0].isreg
= 1;
7324 inst
.operands
[0].writeback
= 1;
7325 inst
.operands
[0].reg
= REG_SP
;
7329 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7330 word at the specified address and the following word
7332 Unconditionally executed.
7333 Error if Rn is R15. */
7338 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7339 if (inst
.operands
[0].writeback
)
7340 inst
.instruction
|= WRITE_BACK
;
7343 /* ARM V6 ssat (argument parse). */
7348 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7349 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7350 inst
.instruction
|= inst
.operands
[2].reg
;
7352 if (inst
.operands
[3].present
)
7353 encode_arm_shift (3);
7356 /* ARM V6 usat (argument parse). */
7361 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7362 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7363 inst
.instruction
|= inst
.operands
[2].reg
;
7365 if (inst
.operands
[3].present
)
7366 encode_arm_shift (3);
7369 /* ARM V6 ssat16 (argument parse). */
7374 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7375 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7376 inst
.instruction
|= inst
.operands
[2].reg
;
7382 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7383 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7384 inst
.instruction
|= inst
.operands
[2].reg
;
7387 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7388 preserving the other bits.
7390 setend <endian_specifier>, where <endian_specifier> is either
7396 if (inst
.operands
[0].imm
)
7397 inst
.instruction
|= 0x200;
7403 unsigned int Rm
= (inst
.operands
[1].present
7404 ? inst
.operands
[1].reg
7405 : inst
.operands
[0].reg
);
7407 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7408 inst
.instruction
|= Rm
;
7409 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7411 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7412 inst
.instruction
|= SHIFT_BY_REG
;
7415 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7421 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7422 inst
.reloc
.pc_rel
= 0;
7428 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7429 inst
.reloc
.pc_rel
= 0;
7432 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7433 SMLAxy{cond} Rd,Rm,Rs,Rn
7434 SMLAWy{cond} Rd,Rm,Rs,Rn
7435 Error if any register is R15. */
7440 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7441 inst
.instruction
|= inst
.operands
[1].reg
;
7442 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7443 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7446 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7447 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7448 Error if any register is R15.
7449 Warning if Rdlo == Rdhi. */
7454 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7455 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7456 inst
.instruction
|= inst
.operands
[2].reg
;
7457 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7459 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7460 as_tsktsk (_("rdhi and rdlo must be different"));
7463 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7464 SMULxy{cond} Rd,Rm,Rs
7465 Error if any register is R15. */
7470 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7471 inst
.instruction
|= inst
.operands
[1].reg
;
7472 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7475 /* ARM V6 srs (argument parse). The variable fields in the encoding are
7476 the same for both ARM and Thumb-2. */
7483 if (inst
.operands
[0].present
)
7485 reg
= inst
.operands
[0].reg
;
7486 constraint (reg
!= 13, _("SRS base register must be r13"));
7491 inst
.instruction
|= reg
<< 16;
7492 inst
.instruction
|= inst
.operands
[1].imm
;
7493 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
7494 inst
.instruction
|= WRITE_BACK
;
7497 /* ARM V6 strex (argument parse). */
7502 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7503 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7504 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7505 || inst
.operands
[2].negative
7506 /* See comment in do_ldrex(). */
7507 || (inst
.operands
[2].reg
== REG_PC
),
7510 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7511 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
7513 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7514 || inst
.reloc
.exp
.X_add_number
!= 0,
7515 _("offset must be zero in ARM encoding"));
7517 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7518 inst
.instruction
|= inst
.operands
[1].reg
;
7519 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7520 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7526 constraint (inst
.operands
[1].reg
% 2 != 0,
7527 _("even register required"));
7528 constraint (inst
.operands
[2].present
7529 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
7530 _("can only store two consecutive registers"));
7531 /* If op 2 were present and equal to PC, this function wouldn't
7532 have been called in the first place. */
7533 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
7535 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7536 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
7537 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
7540 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7541 inst
.instruction
|= inst
.operands
[1].reg
;
7542 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7545 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7546 extends it to 32-bits, and adds the result to a value in another
7547 register. You can specify a rotation by 0, 8, 16, or 24 bits
7548 before extracting the 16-bit value.
7549 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7550 Condition defaults to COND_ALWAYS.
7551 Error if any register uses R15. */
7556 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7557 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7558 inst
.instruction
|= inst
.operands
[2].reg
;
7559 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
7564 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
7565 Condition defaults to COND_ALWAYS.
7566 Error if any register uses R15. */
7571 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7572 inst
.instruction
|= inst
.operands
[1].reg
;
7573 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
7576 /* VFP instructions. In a logical order: SP variant first, monad
7577 before dyad, arithmetic then move then load/store. */
7580 do_vfp_sp_monadic (void)
7582 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7583 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7587 do_vfp_sp_dyadic (void)
7589 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7590 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7591 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7595 do_vfp_sp_compare_z (void)
7597 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7601 do_vfp_dp_sp_cvt (void)
7603 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7604 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7608 do_vfp_sp_dp_cvt (void)
7610 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7611 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7615 do_vfp_reg_from_sp (void)
7617 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7618 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7622 do_vfp_reg2_from_sp2 (void)
7624 constraint (inst
.operands
[2].imm
!= 2,
7625 _("only two consecutive VFP SP registers allowed here"));
7626 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7627 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7628 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7632 do_vfp_sp_from_reg (void)
7634 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
7635 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7639 do_vfp_sp2_from_reg2 (void)
7641 constraint (inst
.operands
[0].imm
!= 2,
7642 _("only two consecutive VFP SP registers allowed here"));
7643 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
7644 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7645 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7649 do_vfp_sp_ldst (void)
7651 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7652 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7656 do_vfp_dp_ldst (void)
7658 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7659 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7664 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
7666 if (inst
.operands
[0].writeback
)
7667 inst
.instruction
|= WRITE_BACK
;
7669 constraint (ldstm_type
!= VFP_LDSTMIA
,
7670 _("this addressing mode requires base-register writeback"));
7671 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7672 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
7673 inst
.instruction
|= inst
.operands
[1].imm
;
7677 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
7681 if (inst
.operands
[0].writeback
)
7682 inst
.instruction
|= WRITE_BACK
;
7684 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
7685 _("this addressing mode requires base-register writeback"));
7687 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7688 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7690 count
= inst
.operands
[1].imm
<< 1;
7691 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
7694 inst
.instruction
|= count
;
7698 do_vfp_sp_ldstmia (void)
7700 vfp_sp_ldstm (VFP_LDSTMIA
);
7704 do_vfp_sp_ldstmdb (void)
7706 vfp_sp_ldstm (VFP_LDSTMDB
);
7710 do_vfp_dp_ldstmia (void)
7712 vfp_dp_ldstm (VFP_LDSTMIA
);
7716 do_vfp_dp_ldstmdb (void)
7718 vfp_dp_ldstm (VFP_LDSTMDB
);
7722 do_vfp_xp_ldstmia (void)
7724 vfp_dp_ldstm (VFP_LDSTMIAX
);
7728 do_vfp_xp_ldstmdb (void)
7730 vfp_dp_ldstm (VFP_LDSTMDBX
);
7734 do_vfp_dp_rd_rm (void)
7736 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7737 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7741 do_vfp_dp_rn_rd (void)
7743 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
7744 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7748 do_vfp_dp_rd_rn (void)
7750 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7751 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7755 do_vfp_dp_rd_rn_rm (void)
7757 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7758 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7759 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
7765 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7769 do_vfp_dp_rm_rd_rn (void)
7771 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
7772 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7773 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
7776 /* VFPv3 instructions. */
7778 do_vfp_sp_const (void)
7780 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7781 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
7782 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
7786 do_vfp_dp_const (void)
7788 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7789 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
7790 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
7794 vfp_conv (int srcsize
)
7796 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
7797 inst
.instruction
|= (immbits
& 1) << 5;
7798 inst
.instruction
|= (immbits
>> 1);
7802 do_vfp_sp_conv_16 (void)
7804 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7809 do_vfp_dp_conv_16 (void)
7811 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7816 do_vfp_sp_conv_32 (void)
7818 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7823 do_vfp_dp_conv_32 (void)
7825 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7829 /* FPA instructions. Also in a logical order. */
7834 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7835 inst
.instruction
|= inst
.operands
[1].reg
;
7839 do_fpa_ldmstm (void)
7841 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7842 switch (inst
.operands
[1].imm
)
7844 case 1: inst
.instruction
|= CP_T_X
; break;
7845 case 2: inst
.instruction
|= CP_T_Y
; break;
7846 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
7851 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
7853 /* The instruction specified "ea" or "fd", so we can only accept
7854 [Rn]{!}. The instruction does not really support stacking or
7855 unstacking, so we have to emulate these by setting appropriate
7856 bits and offsets. */
7857 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7858 || inst
.reloc
.exp
.X_add_number
!= 0,
7859 _("this instruction does not support indexing"));
7861 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
7862 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
7864 if (!(inst
.instruction
& INDEX_UP
))
7865 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
7867 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
7869 inst
.operands
[2].preind
= 0;
7870 inst
.operands
[2].postind
= 1;
7874 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7877 /* iWMMXt instructions: strictly in alphabetical order. */
7880 do_iwmmxt_tandorc (void)
7882 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
7886 do_iwmmxt_textrc (void)
7888 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7889 inst
.instruction
|= inst
.operands
[1].imm
;
7893 do_iwmmxt_textrm (void)
7895 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7896 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7897 inst
.instruction
|= inst
.operands
[2].imm
;
7901 do_iwmmxt_tinsr (void)
7903 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7904 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7905 inst
.instruction
|= inst
.operands
[2].imm
;
7909 do_iwmmxt_tmia (void)
7911 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
7912 inst
.instruction
|= inst
.operands
[1].reg
;
7913 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7917 do_iwmmxt_waligni (void)
7919 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7920 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7921 inst
.instruction
|= inst
.operands
[2].reg
;
7922 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
7926 do_iwmmxt_wmerge (void)
7928 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7929 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7930 inst
.instruction
|= inst
.operands
[2].reg
;
7931 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
7935 do_iwmmxt_wmov (void)
7937 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
7938 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7939 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7940 inst
.instruction
|= inst
.operands
[1].reg
;
7944 do_iwmmxt_wldstbh (void)
7947 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7949 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
7951 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
7952 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
7956 do_iwmmxt_wldstw (void)
7958 /* RIWR_RIWC clears .isreg for a control register. */
7959 if (!inst
.operands
[0].isreg
)
7961 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7962 inst
.instruction
|= 0xf0000000;
7965 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7966 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7970 do_iwmmxt_wldstd (void)
7972 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7973 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
7974 && inst
.operands
[1].immisreg
)
7976 inst
.instruction
&= ~0x1a000ff;
7977 inst
.instruction
|= (0xf << 28);
7978 if (inst
.operands
[1].preind
)
7979 inst
.instruction
|= PRE_INDEX
;
7980 if (!inst
.operands
[1].negative
)
7981 inst
.instruction
|= INDEX_UP
;
7982 if (inst
.operands
[1].writeback
)
7983 inst
.instruction
|= WRITE_BACK
;
7984 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7985 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
7986 inst
.instruction
|= inst
.operands
[1].imm
;
7989 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
7993 do_iwmmxt_wshufh (void)
7995 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7996 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7997 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
7998 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8002 do_iwmmxt_wzero (void)
8004 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8005 inst
.instruction
|= inst
.operands
[0].reg
;
8006 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8007 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8011 do_iwmmxt_wrwrwr_or_imm5 (void)
8013 if (inst
.operands
[2].isreg
)
8016 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8017 _("immediate operand requires iWMMXt2"));
8019 if (inst
.operands
[2].imm
== 0)
8021 switch ((inst
.instruction
>> 20) & 0xf)
8027 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8028 inst
.operands
[2].imm
= 16;
8029 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8035 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8036 inst
.operands
[2].imm
= 32;
8037 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8044 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8046 wrn
= (inst
.instruction
>> 16) & 0xf;
8047 inst
.instruction
&= 0xff0fff0f;
8048 inst
.instruction
|= wrn
;
8049 /* Bail out here; the instruction is now assembled. */
8054 /* Map 32 -> 0, etc. */
8055 inst
.operands
[2].imm
&= 0x1f;
8056 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8060 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8061 operations first, then control, shift, and load/store. */
8063 /* Insns like "foo X,Y,Z". */
8066 do_mav_triple (void)
8068 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8069 inst
.instruction
|= inst
.operands
[1].reg
;
8070 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8073 /* Insns like "foo W,X,Y,Z".
8074 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8079 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8080 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8081 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8082 inst
.instruction
|= inst
.operands
[3].reg
;
8085 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8089 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8092 /* Maverick shift immediate instructions.
8093 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8094 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8099 int imm
= inst
.operands
[2].imm
;
8101 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8102 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8104 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8105 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8106 Bit 4 should be 0. */
8107 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8109 inst
.instruction
|= imm
;
8112 /* XScale instructions. Also sorted arithmetic before move. */
8114 /* Xscale multiply-accumulate (argument parse)
8117 MIAxycc acc0,Rm,Rs. */
8122 inst
.instruction
|= inst
.operands
[1].reg
;
8123 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8126 /* Xscale move-accumulator-register (argument parse)
8128 MARcc acc0,RdLo,RdHi. */
8133 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8134 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8137 /* Xscale move-register-accumulator (argument parse)
8139 MRAcc RdLo,RdHi,acc0. */
8144 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8145 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8146 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8149 /* Encoding functions relevant only to Thumb. */
8151 /* inst.operands[i] is a shifted-register operand; encode
8152 it into inst.instruction in the format used by Thumb32. */
8155 encode_thumb32_shifted_operand (int i
)
8157 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8158 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8160 constraint (inst
.operands
[i
].immisreg
,
8161 _("shift by register not allowed in thumb mode"));
8162 inst
.instruction
|= inst
.operands
[i
].reg
;
8163 if (shift
== SHIFT_RRX
)
8164 inst
.instruction
|= SHIFT_ROR
<< 4;
8167 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8168 _("expression too complex"));
8170 constraint (value
> 32
8171 || (value
== 32 && (shift
== SHIFT_LSL
8172 || shift
== SHIFT_ROR
)),
8173 _("shift expression is too large"));
8177 else if (value
== 32)
8180 inst
.instruction
|= shift
<< 4;
8181 inst
.instruction
|= (value
& 0x1c) << 10;
8182 inst
.instruction
|= (value
& 0x03) << 6;
8187 /* inst.operands[i] was set up by parse_address. Encode it into a
8188 Thumb32 format load or store instruction. Reject forms that cannot
8189 be used with such instructions. If is_t is true, reject forms that
8190 cannot be used with a T instruction; if is_d is true, reject forms
8191 that cannot be used with a D instruction. */
8194 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8196 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8198 constraint (!inst
.operands
[i
].isreg
,
8199 _("Instruction does not support =N addresses"));
8201 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8202 if (inst
.operands
[i
].immisreg
)
8204 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
8205 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8206 constraint (inst
.operands
[i
].negative
,
8207 _("Thumb does not support negative register indexing"));
8208 constraint (inst
.operands
[i
].postind
,
8209 _("Thumb does not support register post-indexing"));
8210 constraint (inst
.operands
[i
].writeback
,
8211 _("Thumb does not support register indexing with writeback"));
8212 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8213 _("Thumb supports only LSL in shifted register indexing"));
8215 inst
.instruction
|= inst
.operands
[i
].imm
;
8216 if (inst
.operands
[i
].shifted
)
8218 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8219 _("expression too complex"));
8220 constraint (inst
.reloc
.exp
.X_add_number
< 0
8221 || inst
.reloc
.exp
.X_add_number
> 3,
8222 _("shift out of range"));
8223 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8225 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8227 else if (inst
.operands
[i
].preind
)
8229 constraint (is_pc
&& inst
.operands
[i
].writeback
,
8230 _("cannot use writeback with PC-relative addressing"));
8231 constraint (is_t
&& inst
.operands
[i
].writeback
,
8232 _("cannot use writeback with this instruction"));
8236 inst
.instruction
|= 0x01000000;
8237 if (inst
.operands
[i
].writeback
)
8238 inst
.instruction
|= 0x00200000;
8242 inst
.instruction
|= 0x00000c00;
8243 if (inst
.operands
[i
].writeback
)
8244 inst
.instruction
|= 0x00000100;
8246 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8248 else if (inst
.operands
[i
].postind
)
8250 assert (inst
.operands
[i
].writeback
);
8251 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8252 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8255 inst
.instruction
|= 0x00200000;
8257 inst
.instruction
|= 0x00000900;
8258 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8260 else /* unindexed - only for coprocessor */
8261 inst
.error
= _("instruction does not accept unindexed addressing");
8264 /* Table of Thumb instructions which exist in both 16- and 32-bit
8265 encodings (the latter only in post-V6T2 cores). The index is the
8266 value used in the insns table below. When there is more than one
8267 possible 16-bit encoding for the instruction, this table always
8269 Also contains several pseudo-instructions used during relaxation. */
8270 #define T16_32_TAB \
8271 X(adc, 4140, eb400000), \
8272 X(adcs, 4140, eb500000), \
8273 X(add, 1c00, eb000000), \
8274 X(adds, 1c00, eb100000), \
8275 X(addi, 0000, f1000000), \
8276 X(addis, 0000, f1100000), \
8277 X(add_pc,000f, f20f0000), \
8278 X(add_sp,000d, f10d0000), \
8279 X(adr, 000f, f20f0000), \
8280 X(and, 4000, ea000000), \
8281 X(ands, 4000, ea100000), \
8282 X(asr, 1000, fa40f000), \
8283 X(asrs, 1000, fa50f000), \
8284 X(b, e000, f000b000), \
8285 X(bcond, d000, f0008000), \
8286 X(bic, 4380, ea200000), \
8287 X(bics, 4380, ea300000), \
8288 X(cmn, 42c0, eb100f00), \
8289 X(cmp, 2800, ebb00f00), \
8290 X(cpsie, b660, f3af8400), \
8291 X(cpsid, b670, f3af8600), \
8292 X(cpy, 4600, ea4f0000), \
8293 X(dec_sp,80dd, f1ad0d00), \
8294 X(eor, 4040, ea800000), \
8295 X(eors, 4040, ea900000), \
8296 X(inc_sp,00dd, f10d0d00), \
8297 X(ldmia, c800, e8900000), \
8298 X(ldr, 6800, f8500000), \
8299 X(ldrb, 7800, f8100000), \
8300 X(ldrh, 8800, f8300000), \
8301 X(ldrsb, 5600, f9100000), \
8302 X(ldrsh, 5e00, f9300000), \
8303 X(ldr_pc,4800, f85f0000), \
8304 X(ldr_pc2,4800, f85f0000), \
8305 X(ldr_sp,9800, f85d0000), \
8306 X(lsl, 0000, fa00f000), \
8307 X(lsls, 0000, fa10f000), \
8308 X(lsr, 0800, fa20f000), \
8309 X(lsrs, 0800, fa30f000), \
8310 X(mov, 2000, ea4f0000), \
8311 X(movs, 2000, ea5f0000), \
8312 X(mul, 4340, fb00f000), \
8313 X(muls, 4340, ffffffff), /* no 32b muls */ \
8314 X(mvn, 43c0, ea6f0000), \
8315 X(mvns, 43c0, ea7f0000), \
8316 X(neg, 4240, f1c00000), /* rsb #0 */ \
8317 X(negs, 4240, f1d00000), /* rsbs #0 */ \
8318 X(orr, 4300, ea400000), \
8319 X(orrs, 4300, ea500000), \
8320 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8321 X(push, b400, e92d0000), /* stmdb sp!,... */ \
8322 X(rev, ba00, fa90f080), \
8323 X(rev16, ba40, fa90f090), \
8324 X(revsh, bac0, fa90f0b0), \
8325 X(ror, 41c0, fa60f000), \
8326 X(rors, 41c0, fa70f000), \
8327 X(sbc, 4180, eb600000), \
8328 X(sbcs, 4180, eb700000), \
8329 X(stmia, c000, e8800000), \
8330 X(str, 6000, f8400000), \
8331 X(strb, 7000, f8000000), \
8332 X(strh, 8000, f8200000), \
8333 X(str_sp,9000, f84d0000), \
8334 X(sub, 1e00, eba00000), \
8335 X(subs, 1e00, ebb00000), \
8336 X(subi, 8000, f1a00000), \
8337 X(subis, 8000, f1b00000), \
8338 X(sxtb, b240, fa4ff080), \
8339 X(sxth, b200, fa0ff080), \
8340 X(tst, 4200, ea100f00), \
8341 X(uxtb, b2c0, fa5ff080), \
8342 X(uxth, b280, fa1ff080), \
8343 X(nop, bf00, f3af8000), \
8344 X(yield, bf10, f3af8001), \
8345 X(wfe, bf20, f3af8002), \
8346 X(wfi, bf30, f3af8003), \
8347 X(sev, bf40, f3af9004), /* typo, 8004? */
8349 /* To catch errors in encoding functions, the codes are all offset by
8350 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8351 as 16-bit instructions. */
8352 #define X(a,b,c) T_MNEM_##a
8353 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8356 #define X(a,b,c) 0x##b
8357 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8358 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8361 #define X(a,b,c) 0x##c
8362 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8363 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8364 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8368 /* Thumb instruction encoders, in alphabetical order. */
8372 do_t_add_sub_w (void)
8376 Rd
= inst
.operands
[0].reg
;
8377 Rn
= inst
.operands
[1].reg
;
8379 constraint (Rd
== 15, _("PC not allowed as destination"));
8380 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8381 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8384 /* Parse an add or subtract instruction. We get here with inst.instruction
8385 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8392 Rd
= inst
.operands
[0].reg
;
8393 Rs
= (inst
.operands
[1].present
8394 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8395 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8403 flags
= (inst
.instruction
== T_MNEM_adds
8404 || inst
.instruction
== T_MNEM_subs
);
8406 narrow
= (current_it_mask
== 0);
8408 narrow
= (current_it_mask
!= 0);
8409 if (!inst
.operands
[2].isreg
)
8413 add
= (inst
.instruction
== T_MNEM_add
8414 || inst
.instruction
== T_MNEM_adds
);
8416 if (inst
.size_req
!= 4)
8418 /* Attempt to use a narrow opcode, with relaxation if
8420 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8421 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8422 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8423 opcode
= T_MNEM_add_sp
;
8424 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8425 opcode
= T_MNEM_add_pc
;
8426 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8429 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8431 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8435 inst
.instruction
= THUMB_OP16(opcode
);
8436 inst
.instruction
|= (Rd
<< 4) | Rs
;
8437 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8438 if (inst
.size_req
!= 2)
8439 inst
.relax
= opcode
;
8442 constraint (inst
.size_req
== 2, BAD_HIREG
);
8444 if (inst
.size_req
== 4
8445 || (inst
.size_req
!= 2 && !opcode
))
8449 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
8450 _("only SUBS PC, LR, #const allowed"));
8451 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8452 _("expression too complex"));
8453 constraint (inst
.reloc
.exp
.X_add_number
< 0
8454 || inst
.reloc
.exp
.X_add_number
> 0xff,
8455 _("immediate value out of range"));
8456 inst
.instruction
= T2_SUBS_PC_LR
8457 | inst
.reloc
.exp
.X_add_number
;
8458 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8461 else if (Rs
== REG_PC
)
8463 /* Always use addw/subw. */
8464 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
8465 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8469 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8470 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
8473 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8475 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
8477 inst
.instruction
|= Rd
<< 8;
8478 inst
.instruction
|= Rs
<< 16;
8483 Rn
= inst
.operands
[2].reg
;
8484 /* See if we can do this with a 16-bit instruction. */
8485 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
8487 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8492 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
8493 || inst
.instruction
== T_MNEM_add
)
8496 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8500 if (inst
.instruction
== T_MNEM_add
)
8504 inst
.instruction
= T_OPCODE_ADD_HI
;
8505 inst
.instruction
|= (Rd
& 8) << 4;
8506 inst
.instruction
|= (Rd
& 7);
8507 inst
.instruction
|= Rn
<< 3;
8510 /* ... because addition is commutative! */
8513 inst
.instruction
= T_OPCODE_ADD_HI
;
8514 inst
.instruction
|= (Rd
& 8) << 4;
8515 inst
.instruction
|= (Rd
& 7);
8516 inst
.instruction
|= Rs
<< 3;
8521 /* If we get here, it can't be done in 16 bits. */
8522 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
8523 _("shift must be constant"));
8524 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8525 inst
.instruction
|= Rd
<< 8;
8526 inst
.instruction
|= Rs
<< 16;
8527 encode_thumb32_shifted_operand (2);
8532 constraint (inst
.instruction
== T_MNEM_adds
8533 || inst
.instruction
== T_MNEM_subs
,
8536 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
8538 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
8539 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
8542 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8544 inst
.instruction
|= (Rd
<< 4) | Rs
;
8545 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8549 Rn
= inst
.operands
[2].reg
;
8550 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
8552 /* We now have Rd, Rs, and Rn set to registers. */
8553 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8555 /* Can't do this for SUB. */
8556 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
8557 inst
.instruction
= T_OPCODE_ADD_HI
;
8558 inst
.instruction
|= (Rd
& 8) << 4;
8559 inst
.instruction
|= (Rd
& 7);
8561 inst
.instruction
|= Rn
<< 3;
8563 inst
.instruction
|= Rs
<< 3;
8565 constraint (1, _("dest must overlap one source register"));
8569 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8570 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
8571 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8579 if (unified_syntax
&& inst
.size_req
== 0 && inst
.operands
[0].reg
<= 7)
8581 /* Defer to section relaxation. */
8582 inst
.relax
= inst
.instruction
;
8583 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8584 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8586 else if (unified_syntax
&& inst
.size_req
!= 2)
8588 /* Generate a 32-bit opcode. */
8589 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8590 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8591 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
8592 inst
.reloc
.pc_rel
= 1;
8596 /* Generate a 16-bit opcode. */
8597 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8598 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8599 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
8600 inst
.reloc
.pc_rel
= 1;
8602 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8606 /* Arithmetic instructions for which there is just one 16-bit
8607 instruction encoding, and it allows only two low registers.
8608 For maximal compatibility with ARM syntax, we allow three register
8609 operands even when Thumb-32 instructions are not available, as long
8610 as the first two are identical. For instance, both "sbc r0,r1" and
8611 "sbc r0,r0,r1" are allowed. */
8617 Rd
= inst
.operands
[0].reg
;
8618 Rs
= (inst
.operands
[1].present
8619 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8620 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8621 Rn
= inst
.operands
[2].reg
;
8625 if (!inst
.operands
[2].isreg
)
8627 /* For an immediate, we always generate a 32-bit opcode;
8628 section relaxation will shrink it later if possible. */
8629 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8630 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8631 inst
.instruction
|= Rd
<< 8;
8632 inst
.instruction
|= Rs
<< 16;
8633 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8639 /* See if we can do this with a 16-bit instruction. */
8640 if (THUMB_SETS_FLAGS (inst
.instruction
))
8641 narrow
= current_it_mask
== 0;
8643 narrow
= current_it_mask
!= 0;
8645 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8647 if (inst
.operands
[2].shifted
)
8649 if (inst
.size_req
== 4)
8655 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8656 inst
.instruction
|= Rd
;
8657 inst
.instruction
|= Rn
<< 3;
8661 /* If we get here, it can't be done in 16 bits. */
8662 constraint (inst
.operands
[2].shifted
8663 && inst
.operands
[2].immisreg
,
8664 _("shift must be constant"));
8665 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8666 inst
.instruction
|= Rd
<< 8;
8667 inst
.instruction
|= Rs
<< 16;
8668 encode_thumb32_shifted_operand (2);
8673 /* On its face this is a lie - the instruction does set the
8674 flags. However, the only supported mnemonic in this mode
8676 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8678 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8679 _("unshifted register required"));
8680 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8681 constraint (Rd
!= Rs
,
8682 _("dest and source1 must be the same register"));
8684 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8685 inst
.instruction
|= Rd
;
8686 inst
.instruction
|= Rn
<< 3;
8690 /* Similarly, but for instructions where the arithmetic operation is
8691 commutative, so we can allow either of them to be different from
8692 the destination operand in a 16-bit instruction. For instance, all
8693 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
8700 Rd
= inst
.operands
[0].reg
;
8701 Rs
= (inst
.operands
[1].present
8702 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8703 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8704 Rn
= inst
.operands
[2].reg
;
8708 if (!inst
.operands
[2].isreg
)
8710 /* For an immediate, we always generate a 32-bit opcode;
8711 section relaxation will shrink it later if possible. */
8712 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8713 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8714 inst
.instruction
|= Rd
<< 8;
8715 inst
.instruction
|= Rs
<< 16;
8716 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8722 /* See if we can do this with a 16-bit instruction. */
8723 if (THUMB_SETS_FLAGS (inst
.instruction
))
8724 narrow
= current_it_mask
== 0;
8726 narrow
= current_it_mask
!= 0;
8728 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8730 if (inst
.operands
[2].shifted
)
8732 if (inst
.size_req
== 4)
8739 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8740 inst
.instruction
|= Rd
;
8741 inst
.instruction
|= Rn
<< 3;
8746 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8747 inst
.instruction
|= Rd
;
8748 inst
.instruction
|= Rs
<< 3;
8753 /* If we get here, it can't be done in 16 bits. */
8754 constraint (inst
.operands
[2].shifted
8755 && inst
.operands
[2].immisreg
,
8756 _("shift must be constant"));
8757 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8758 inst
.instruction
|= Rd
<< 8;
8759 inst
.instruction
|= Rs
<< 16;
8760 encode_thumb32_shifted_operand (2);
8765 /* On its face this is a lie - the instruction does set the
8766 flags. However, the only supported mnemonic in this mode
8768 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8770 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8771 _("unshifted register required"));
8772 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8774 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8775 inst
.instruction
|= Rd
;
8778 inst
.instruction
|= Rn
<< 3;
8780 inst
.instruction
|= Rs
<< 3;
8782 constraint (1, _("dest must overlap one source register"));
8789 if (inst
.operands
[0].present
)
8791 constraint ((inst
.instruction
& 0xf0) != 0x40
8792 && inst
.operands
[0].imm
!= 0xf,
8793 _("bad barrier type"));
8794 inst
.instruction
|= inst
.operands
[0].imm
;
8797 inst
.instruction
|= 0xf;
8803 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8804 constraint (msb
> 32, _("bit-field extends past end of register"));
8805 /* The instruction encoding stores the LSB and MSB,
8806 not the LSB and width. */
8807 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8808 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
8809 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
8810 inst
.instruction
|= msb
- 1;
8818 /* #0 in second position is alternative syntax for bfc, which is
8819 the same instruction but with REG_PC in the Rm field. */
8820 if (!inst
.operands
[1].isreg
)
8821 inst
.operands
[1].reg
= REG_PC
;
8823 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8824 constraint (msb
> 32, _("bit-field extends past end of register"));
8825 /* The instruction encoding stores the LSB and MSB,
8826 not the LSB and width. */
8827 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8828 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8829 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8830 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8831 inst
.instruction
|= msb
- 1;
8837 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8838 _("bit-field extends past end of register"));
8839 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8840 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8841 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8842 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8843 inst
.instruction
|= inst
.operands
[3].imm
- 1;
8846 /* ARM V5 Thumb BLX (argument parse)
8847 BLX <target_addr> which is BLX(1)
8848 BLX <Rm> which is BLX(2)
8849 Unfortunately, there are two different opcodes for this mnemonic.
8850 So, the insns[].value is not used, and the code here zaps values
8851 into inst.instruction.
8853 ??? How to take advantage of the additional two bits of displacement
8854 available in Thumb32 mode? Need new relocation? */
8859 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8860 if (inst
.operands
[0].isreg
)
8861 /* We have a register, so this is BLX(2). */
8862 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8865 /* No register. This must be BLX(1). */
8866 inst
.instruction
= 0xf000e800;
8868 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8869 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8872 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
8873 inst
.reloc
.pc_rel
= 1;
8883 if (current_it_mask
)
8885 /* Conditional branches inside IT blocks are encoded as unconditional
8888 /* A branch must be the last instruction in an IT block. */
8889 constraint (current_it_mask
!= 0x10, BAD_BRANCH
);
8894 if (cond
!= COND_ALWAYS
)
8895 opcode
= T_MNEM_bcond
;
8897 opcode
= inst
.instruction
;
8899 if (unified_syntax
&& inst
.size_req
== 4)
8901 inst
.instruction
= THUMB_OP32(opcode
);
8902 if (cond
== COND_ALWAYS
)
8903 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
8906 assert (cond
!= 0xF);
8907 inst
.instruction
|= cond
<< 22;
8908 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
8913 inst
.instruction
= THUMB_OP16(opcode
);
8914 if (cond
== COND_ALWAYS
)
8915 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
8918 inst
.instruction
|= cond
<< 8;
8919 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
8921 /* Allow section relaxation. */
8922 if (unified_syntax
&& inst
.size_req
!= 2)
8923 inst
.relax
= opcode
;
8926 inst
.reloc
.pc_rel
= 1;
8932 constraint (inst
.cond
!= COND_ALWAYS
,
8933 _("instruction is always unconditional"));
8934 if (inst
.operands
[0].present
)
8936 constraint (inst
.operands
[0].imm
> 255,
8937 _("immediate value out of range"));
8938 inst
.instruction
|= inst
.operands
[0].imm
;
8943 do_t_branch23 (void)
8945 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8946 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8947 inst
.reloc
.pc_rel
= 1;
8949 /* If the destination of the branch is a defined symbol which does not have
8950 the THUMB_FUNC attribute, then we must be calling a function which has
8951 the (interfacearm) attribute. We look for the Thumb entry point to that
8952 function and change the branch to refer to that function instead. */
8953 if ( inst
.reloc
.exp
.X_op
== O_symbol
8954 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8955 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8956 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8957 inst
.reloc
.exp
.X_add_symbol
=
8958 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
8964 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8965 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8966 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
8967 should cause the alignment to be checked once it is known. This is
8968 because BX PC only works if the instruction is word aligned. */
8974 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8975 if (inst
.operands
[0].reg
== REG_PC
)
8976 as_tsktsk (_("use of r15 in bxj is not really useful"));
8978 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8984 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8985 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8986 inst
.instruction
|= inst
.operands
[1].reg
;
8992 constraint (current_it_mask
, BAD_NOT_IT
);
8993 inst
.instruction
|= inst
.operands
[0].imm
;
8999 constraint (current_it_mask
, BAD_NOT_IT
);
9001 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9002 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9004 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9005 inst
.instruction
= 0xf3af8000;
9006 inst
.instruction
|= imod
<< 9;
9007 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9008 if (inst
.operands
[1].present
)
9009 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9013 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9014 && (inst
.operands
[0].imm
& 4),
9015 _("selected processor does not support 'A' form "
9016 "of this instruction"));
9017 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9018 _("Thumb does not support the 2-argument "
9019 "form of this instruction"));
9020 inst
.instruction
|= inst
.operands
[0].imm
;
9024 /* THUMB CPY instruction (argument parse). */
9029 if (inst
.size_req
== 4)
9031 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9032 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9033 inst
.instruction
|= inst
.operands
[1].reg
;
9037 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9038 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9039 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9046 constraint (current_it_mask
, BAD_NOT_IT
);
9047 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9048 inst
.instruction
|= inst
.operands
[0].reg
;
9049 inst
.reloc
.pc_rel
= 1;
9050 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9056 inst
.instruction
|= inst
.operands
[0].imm
;
9062 if (!inst
.operands
[1].present
)
9063 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9064 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9065 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9066 inst
.instruction
|= inst
.operands
[2].reg
;
9072 if (unified_syntax
&& inst
.size_req
== 4)
9073 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9075 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9081 unsigned int cond
= inst
.operands
[0].imm
;
9083 constraint (current_it_mask
, BAD_NOT_IT
);
9084 current_it_mask
= (inst
.instruction
& 0xf) | 0x10;
9087 /* If the condition is a negative condition, invert the mask. */
9088 if ((cond
& 0x1) == 0x0)
9090 unsigned int mask
= inst
.instruction
& 0x000f;
9092 if ((mask
& 0x7) == 0)
9093 /* no conversion needed */;
9094 else if ((mask
& 0x3) == 0)
9096 else if ((mask
& 0x1) == 0)
9101 inst
.instruction
&= 0xfff0;
9102 inst
.instruction
|= mask
;
9105 inst
.instruction
|= cond
<< 4;
9108 /* Helper function used for both push/pop and ldm/stm. */
9110 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9114 load
= (inst
.instruction
& (1 << 20)) != 0;
9116 if (mask
& (1 << 13))
9117 inst
.error
= _("SP not allowed in register list");
9120 if (mask
& (1 << 14)
9121 && mask
& (1 << 15))
9122 inst
.error
= _("LR and PC should not both be in register list");
9124 if ((mask
& (1 << base
)) != 0
9126 as_warn (_("base register should not be in register list "
9127 "when written back"));
9131 if (mask
& (1 << 15))
9132 inst
.error
= _("PC not allowed in register list");
9134 if (mask
& (1 << base
))
9135 as_warn (_("value stored for r%d is UNPREDICTABLE"), base
);
9138 if ((mask
& (mask
- 1)) == 0)
9140 /* Single register transfers implemented as str/ldr. */
9143 if (inst
.instruction
& (1 << 23))
9144 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9146 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9150 if (inst
.instruction
& (1 << 23))
9151 inst
.instruction
= 0x00800000; /* ia -> [base] */
9153 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9156 inst
.instruction
|= 0xf8400000;
9158 inst
.instruction
|= 0x00100000;
9160 mask
= ffs (mask
) - 1;
9164 inst
.instruction
|= WRITE_BACK
;
9166 inst
.instruction
|= mask
;
9167 inst
.instruction
|= base
<< 16;
9173 /* This really doesn't seem worth it. */
9174 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9175 _("expression too complex"));
9176 constraint (inst
.operands
[1].writeback
,
9177 _("Thumb load/store multiple does not support {reglist}^"));
9185 /* See if we can use a 16-bit instruction. */
9186 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9187 && inst
.size_req
!= 4
9188 && !(inst
.operands
[1].imm
& ~0xff))
9190 mask
= 1 << inst
.operands
[0].reg
;
9192 if (inst
.operands
[0].reg
<= 7
9193 && (inst
.instruction
== T_MNEM_stmia
9194 ? inst
.operands
[0].writeback
9195 : (inst
.operands
[0].writeback
9196 == !(inst
.operands
[1].imm
& mask
))))
9198 if (inst
.instruction
== T_MNEM_stmia
9199 && (inst
.operands
[1].imm
& mask
)
9200 && (inst
.operands
[1].imm
& (mask
- 1)))
9201 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9202 inst
.operands
[0].reg
);
9204 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9205 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9206 inst
.instruction
|= inst
.operands
[1].imm
;
9209 else if (inst
.operands
[0] .reg
== REG_SP
9210 && inst
.operands
[0].writeback
)
9212 inst
.instruction
= THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9213 ? T_MNEM_push
: T_MNEM_pop
);
9214 inst
.instruction
|= inst
.operands
[1].imm
;
9221 if (inst
.instruction
< 0xffff)
9222 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9224 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
9225 inst
.operands
[0].writeback
);
9230 constraint (inst
.operands
[0].reg
> 7
9231 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9232 constraint (inst
.instruction
!= T_MNEM_ldmia
9233 && inst
.instruction
!= T_MNEM_stmia
,
9234 _("Thumb-2 instruction only valid in unified syntax"));
9235 if (inst
.instruction
== T_MNEM_stmia
)
9237 if (!inst
.operands
[0].writeback
)
9238 as_warn (_("this instruction will write back the base register"));
9239 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9240 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9241 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9242 inst
.operands
[0].reg
);
9246 if (!inst
.operands
[0].writeback
9247 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9248 as_warn (_("this instruction will write back the base register"));
9249 else if (inst
.operands
[0].writeback
9250 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9251 as_warn (_("this instruction will not write back the base register"));
9254 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9255 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9256 inst
.instruction
|= inst
.operands
[1].imm
;
9263 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9264 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9265 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9266 || inst
.operands
[1].negative
,
9269 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9270 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9271 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9277 if (!inst
.operands
[1].present
)
9279 constraint (inst
.operands
[0].reg
== REG_LR
,
9280 _("r14 not allowed as first register "
9281 "when second register is omitted"));
9282 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9284 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9287 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9288 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9289 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9295 unsigned long opcode
;
9298 opcode
= inst
.instruction
;
9301 if (!inst
.operands
[1].isreg
)
9303 if (opcode
<= 0xffff)
9304 inst
.instruction
= THUMB_OP32 (opcode
);
9305 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9308 if (inst
.operands
[1].isreg
9309 && !inst
.operands
[1].writeback
9310 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9311 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9313 && inst
.size_req
!= 4)
9315 /* Insn may have a 16-bit form. */
9316 Rn
= inst
.operands
[1].reg
;
9317 if (inst
.operands
[1].immisreg
)
9319 inst
.instruction
= THUMB_OP16 (opcode
);
9321 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9324 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9325 && opcode
!= T_MNEM_ldrsb
)
9326 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9327 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9334 if (inst
.reloc
.pc_rel
)
9335 opcode
= T_MNEM_ldr_pc2
;
9337 opcode
= T_MNEM_ldr_pc
;
9341 if (opcode
== T_MNEM_ldr
)
9342 opcode
= T_MNEM_ldr_sp
;
9344 opcode
= T_MNEM_str_sp
;
9346 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9350 inst
.instruction
= inst
.operands
[0].reg
;
9351 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9353 inst
.instruction
|= THUMB_OP16 (opcode
);
9354 if (inst
.size_req
== 2)
9355 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9357 inst
.relax
= opcode
;
9361 /* Definitely a 32-bit variant. */
9362 inst
.instruction
= THUMB_OP32 (opcode
);
9363 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9364 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9368 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9370 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9372 /* Only [Rn,Rm] is acceptable. */
9373 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9374 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9375 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9376 || inst
.operands
[1].negative
,
9377 _("Thumb does not support this addressing mode"));
9378 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9382 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9383 if (!inst
.operands
[1].isreg
)
9384 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9387 constraint (!inst
.operands
[1].preind
9388 || inst
.operands
[1].shifted
9389 || inst
.operands
[1].writeback
,
9390 _("Thumb does not support this addressing mode"));
9391 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9393 constraint (inst
.instruction
& 0x0600,
9394 _("byte or halfword not valid for base register"));
9395 constraint (inst
.operands
[1].reg
== REG_PC
9396 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9397 _("r15 based store not allowed"));
9398 constraint (inst
.operands
[1].immisreg
,
9399 _("invalid base register for register offset"));
9401 if (inst
.operands
[1].reg
== REG_PC
)
9402 inst
.instruction
= T_OPCODE_LDR_PC
;
9403 else if (inst
.instruction
& THUMB_LOAD_BIT
)
9404 inst
.instruction
= T_OPCODE_LDR_SP
;
9406 inst
.instruction
= T_OPCODE_STR_SP
;
9408 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9409 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9413 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
9414 if (!inst
.operands
[1].immisreg
)
9416 /* Immediate offset. */
9417 inst
.instruction
|= inst
.operands
[0].reg
;
9418 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9419 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9423 /* Register offset. */
9424 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
9425 constraint (inst
.operands
[1].negative
,
9426 _("Thumb does not support this addressing mode"));
9429 switch (inst
.instruction
)
9431 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
9432 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
9433 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
9434 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
9435 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
9436 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
9437 case 0x5600 /* ldrsb */:
9438 case 0x5e00 /* ldrsh */: break;
9442 inst
.instruction
|= inst
.operands
[0].reg
;
9443 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9444 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
9450 if (!inst
.operands
[1].present
)
9452 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9453 constraint (inst
.operands
[0].reg
== REG_LR
,
9454 _("r14 not allowed here"));
9456 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9457 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9458 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
9464 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9465 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
9471 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9472 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9473 inst
.instruction
|= inst
.operands
[2].reg
;
9474 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9480 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9481 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9482 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9483 inst
.instruction
|= inst
.operands
[3].reg
;
9491 int r0off
= (inst
.instruction
== T_MNEM_mov
9492 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
9493 unsigned long opcode
;
9495 bfd_boolean low_regs
;
9497 low_regs
= (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7);
9498 opcode
= inst
.instruction
;
9499 if (current_it_mask
)
9500 narrow
= opcode
!= T_MNEM_movs
;
9502 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
9503 if (inst
.size_req
== 4
9504 || inst
.operands
[1].shifted
)
9507 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
9508 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
9509 && !inst
.operands
[1].shifted
9510 && inst
.operands
[0].reg
== REG_PC
9511 && inst
.operands
[1].reg
== REG_LR
)
9513 inst
.instruction
= T2_SUBS_PC_LR
;
9517 if (!inst
.operands
[1].isreg
)
9519 /* Immediate operand. */
9520 if (current_it_mask
== 0 && opcode
== T_MNEM_mov
)
9522 if (low_regs
&& narrow
)
9524 inst
.instruction
= THUMB_OP16 (opcode
);
9525 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9526 if (inst
.size_req
== 2)
9527 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9529 inst
.relax
= opcode
;
9533 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9534 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9535 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9536 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9539 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
9540 && (inst
.instruction
== T_MNEM_mov
9541 || inst
.instruction
== T_MNEM_movs
))
9543 /* Register shifts are encoded as separate shift instructions. */
9544 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
9546 if (current_it_mask
)
9551 if (inst
.size_req
== 4)
9554 if (!low_regs
|| inst
.operands
[1].imm
> 7)
9557 if (inst
.operands
[0].reg
!= inst
.operands
[1].reg
)
9560 switch (inst
.operands
[1].shift_kind
)
9563 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
9566 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
9569 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
9572 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
9578 inst
.instruction
= opcode
;
9581 inst
.instruction
|= inst
.operands
[0].reg
;
9582 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
9587 inst
.instruction
|= CONDS_BIT
;
9589 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9590 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9591 inst
.instruction
|= inst
.operands
[1].imm
;
9596 /* Some mov with immediate shift have narrow variants.
9597 Register shifts are handled above. */
9598 if (low_regs
&& inst
.operands
[1].shifted
9599 && (inst
.instruction
== T_MNEM_mov
9600 || inst
.instruction
== T_MNEM_movs
))
9602 if (current_it_mask
)
9603 narrow
= (inst
.instruction
== T_MNEM_mov
);
9605 narrow
= (inst
.instruction
== T_MNEM_movs
);
9610 switch (inst
.operands
[1].shift_kind
)
9612 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
9613 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
9614 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
9615 default: narrow
= FALSE
; break;
9621 inst
.instruction
|= inst
.operands
[0].reg
;
9622 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9623 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
9627 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9628 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9629 encode_thumb32_shifted_operand (1);
9633 switch (inst
.instruction
)
9636 inst
.instruction
= T_OPCODE_MOV_HR
;
9637 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9638 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9639 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9643 /* We know we have low registers at this point.
9644 Generate ADD Rd, Rs, #0. */
9645 inst
.instruction
= T_OPCODE_ADD_I3
;
9646 inst
.instruction
|= inst
.operands
[0].reg
;
9647 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9653 inst
.instruction
= T_OPCODE_CMP_LR
;
9654 inst
.instruction
|= inst
.operands
[0].reg
;
9655 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9659 inst
.instruction
= T_OPCODE_CMP_HR
;
9660 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9661 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9662 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9669 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9670 if (inst
.operands
[1].isreg
)
9672 if (inst
.operands
[0].reg
< 8 && inst
.operands
[1].reg
< 8)
9674 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
9675 since a MOV instruction produces unpredictable results. */
9676 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9677 inst
.instruction
= T_OPCODE_ADD_I3
;
9679 inst
.instruction
= T_OPCODE_CMP_LR
;
9681 inst
.instruction
|= inst
.operands
[0].reg
;
9682 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9686 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9687 inst
.instruction
= T_OPCODE_MOV_HR
;
9689 inst
.instruction
= T_OPCODE_CMP_HR
;
9695 constraint (inst
.operands
[0].reg
> 7,
9696 _("only lo regs allowed with immediate"));
9697 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9698 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9708 top
= (inst
.instruction
& 0x00800000) != 0;
9709 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
9711 constraint (top
, _(":lower16: not allowed this instruction"));
9712 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
9714 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
9716 constraint (!top
, _(":upper16: not allowed this instruction"));
9717 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
9720 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9721 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9723 imm
= inst
.reloc
.exp
.X_add_number
;
9724 inst
.instruction
|= (imm
& 0xf000) << 4;
9725 inst
.instruction
|= (imm
& 0x0800) << 15;
9726 inst
.instruction
|= (imm
& 0x0700) << 4;
9727 inst
.instruction
|= (imm
& 0x00ff);
9736 int r0off
= (inst
.instruction
== T_MNEM_mvn
9737 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
9740 if (inst
.size_req
== 4
9741 || inst
.instruction
> 0xffff
9742 || inst
.operands
[1].shifted
9743 || inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9745 else if (inst
.instruction
== T_MNEM_cmn
)
9747 else if (THUMB_SETS_FLAGS (inst
.instruction
))
9748 narrow
= (current_it_mask
== 0);
9750 narrow
= (current_it_mask
!= 0);
9752 if (!inst
.operands
[1].isreg
)
9754 /* For an immediate, we always generate a 32-bit opcode;
9755 section relaxation will shrink it later if possible. */
9756 if (inst
.instruction
< 0xffff)
9757 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9758 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9759 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9760 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9764 /* See if we can do this with a 16-bit instruction. */
9767 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9768 inst
.instruction
|= inst
.operands
[0].reg
;
9769 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9773 constraint (inst
.operands
[1].shifted
9774 && inst
.operands
[1].immisreg
,
9775 _("shift must be constant"));
9776 if (inst
.instruction
< 0xffff)
9777 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9778 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9779 encode_thumb32_shifted_operand (1);
9785 constraint (inst
.instruction
> 0xffff
9786 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
9787 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
9788 _("unshifted register required"));
9789 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9792 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9793 inst
.instruction
|= inst
.operands
[0].reg
;
9794 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9803 if (do_vfp_nsyn_mrs () == SUCCESS
)
9806 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
9809 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
9810 _("selected processor does not support "
9811 "requested special purpose register"));
9815 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9816 _("selected processor does not support "
9817 "requested special purpose register %x"));
9818 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9819 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
9820 _("'CPSR' or 'SPSR' expected"));
9823 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9824 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9825 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
9833 if (do_vfp_nsyn_msr () == SUCCESS
)
9836 constraint (!inst
.operands
[1].isreg
,
9837 _("Thumb encoding does not support an immediate here"));
9838 flags
= inst
.operands
[0].imm
;
9841 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9842 _("selected processor does not support "
9843 "requested special purpose register"));
9847 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
9848 _("selected processor does not support "
9849 "requested special purpose register"));
9852 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9853 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
9854 inst
.instruction
|= (flags
& 0xff);
9855 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9861 if (!inst
.operands
[2].present
)
9862 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9864 /* There is no 32-bit MULS and no 16-bit MUL. */
9865 if (unified_syntax
&& inst
.instruction
== T_MNEM_mul
)
9867 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9868 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9869 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9870 inst
.instruction
|= inst
.operands
[2].reg
<< 0;
9874 constraint (!unified_syntax
9875 && inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
9876 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9879 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9880 inst
.instruction
|= inst
.operands
[0].reg
;
9882 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9883 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9884 else if (inst
.operands
[0].reg
== inst
.operands
[2].reg
)
9885 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9887 constraint (1, _("dest must overlap one source register"));
9894 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9895 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9896 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9897 inst
.instruction
|= inst
.operands
[3].reg
;
9899 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9900 as_tsktsk (_("rdhi and rdlo must be different"));
9908 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
9910 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9911 inst
.instruction
|= inst
.operands
[0].imm
;
9915 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9916 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
9921 constraint (inst
.operands
[0].present
,
9922 _("Thumb does not support NOP with hints"));
9923 inst
.instruction
= 0x46c0;
9934 if (THUMB_SETS_FLAGS (inst
.instruction
))
9935 narrow
= (current_it_mask
== 0);
9937 narrow
= (current_it_mask
!= 0);
9938 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9940 if (inst
.size_req
== 4)
9945 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9946 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9947 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9951 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9952 inst
.instruction
|= inst
.operands
[0].reg
;
9953 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9958 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9960 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9962 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9963 inst
.instruction
|= inst
.operands
[0].reg
;
9964 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9971 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9972 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9973 inst
.instruction
|= inst
.operands
[2].reg
;
9974 if (inst
.operands
[3].present
)
9976 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
9977 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9978 _("expression too complex"));
9979 inst
.instruction
|= (val
& 0x1c) << 10;
9980 inst
.instruction
|= (val
& 0x03) << 6;
9987 if (!inst
.operands
[3].present
)
9988 inst
.instruction
&= ~0x00000020;
9995 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9999 do_t_push_pop (void)
10003 constraint (inst
.operands
[0].writeback
,
10004 _("push/pop do not support {reglist}^"));
10005 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10006 _("expression too complex"));
10008 mask
= inst
.operands
[0].imm
;
10009 if ((mask
& ~0xff) == 0)
10010 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
10011 else if ((inst
.instruction
== T_MNEM_push
10012 && (mask
& ~0xff) == 1 << REG_LR
)
10013 || (inst
.instruction
== T_MNEM_pop
10014 && (mask
& ~0xff) == 1 << REG_PC
))
10016 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10017 inst
.instruction
|= THUMB_PP_PC_LR
;
10018 inst
.instruction
|= mask
& 0xff;
10020 else if (unified_syntax
)
10022 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10023 encode_thumb2_ldmstm (13, mask
, TRUE
);
10027 inst
.error
= _("invalid register list to push/pop instruction");
10035 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10036 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10042 if (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
10043 && inst
.size_req
!= 4)
10045 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10046 inst
.instruction
|= inst
.operands
[0].reg
;
10047 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10049 else if (unified_syntax
)
10051 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10052 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10053 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10054 inst
.instruction
|= inst
.operands
[1].reg
;
10057 inst
.error
= BAD_HIREG
;
10065 Rd
= inst
.operands
[0].reg
;
10066 Rs
= (inst
.operands
[1].present
10067 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10068 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10070 inst
.instruction
|= Rd
<< 8;
10071 inst
.instruction
|= Rs
<< 16;
10072 if (!inst
.operands
[2].isreg
)
10074 bfd_boolean narrow
;
10076 if ((inst
.instruction
& 0x00100000) != 0)
10077 narrow
= (current_it_mask
== 0);
10079 narrow
= (current_it_mask
!= 0);
10081 if (Rd
> 7 || Rs
> 7)
10084 if (inst
.size_req
== 4 || !unified_syntax
)
10087 if (inst
.reloc
.exp
.X_op
!= O_constant
10088 || inst
.reloc
.exp
.X_add_number
!= 0)
10091 /* Turn rsb #0 into 16-bit neg. We should probably do this via
10092 relaxation, but it doesn't seem worth the hassle. */
10095 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10096 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
10097 inst
.instruction
|= Rs
<< 3;
10098 inst
.instruction
|= Rd
;
10102 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10103 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10107 encode_thumb32_shifted_operand (2);
10113 constraint (current_it_mask
, BAD_NOT_IT
);
10114 if (inst
.operands
[0].imm
)
10115 inst
.instruction
|= 0x8;
10121 if (!inst
.operands
[1].present
)
10122 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
10124 if (unified_syntax
)
10126 bfd_boolean narrow
;
10129 switch (inst
.instruction
)
10132 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
10134 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
10136 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
10138 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
10142 if (THUMB_SETS_FLAGS (inst
.instruction
))
10143 narrow
= (current_it_mask
== 0);
10145 narrow
= (current_it_mask
!= 0);
10146 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10148 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
10150 if (inst
.operands
[2].isreg
10151 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
10152 || inst
.operands
[2].reg
> 7))
10154 if (inst
.size_req
== 4)
10159 if (inst
.operands
[2].isreg
)
10161 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10162 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10163 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10164 inst
.instruction
|= inst
.operands
[2].reg
;
10168 inst
.operands
[1].shifted
= 1;
10169 inst
.operands
[1].shift_kind
= shift_kind
;
10170 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
10171 ? T_MNEM_movs
: T_MNEM_mov
);
10172 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10173 encode_thumb32_shifted_operand (1);
10174 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
10175 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10180 if (inst
.operands
[2].isreg
)
10182 switch (shift_kind
)
10184 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10185 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10186 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10187 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10191 inst
.instruction
|= inst
.operands
[0].reg
;
10192 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10196 switch (shift_kind
)
10198 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10199 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10200 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10203 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10204 inst
.instruction
|= inst
.operands
[0].reg
;
10205 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10211 constraint (inst
.operands
[0].reg
> 7
10212 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
10213 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10215 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
10217 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
10218 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
10219 _("source1 and dest must be same register"));
10221 switch (inst
.instruction
)
10223 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10224 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10225 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10226 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10230 inst
.instruction
|= inst
.operands
[0].reg
;
10231 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10235 switch (inst
.instruction
)
10237 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10238 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10239 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10240 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
10243 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10244 inst
.instruction
|= inst
.operands
[0].reg
;
10245 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10253 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10254 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10255 inst
.instruction
|= inst
.operands
[2].reg
;
10261 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10262 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10263 _("expression too complex"));
10264 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10265 inst
.instruction
|= (value
& 0xf000) >> 12;
10266 inst
.instruction
|= (value
& 0x0ff0);
10267 inst
.instruction
|= (value
& 0x000f) << 16;
10273 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10274 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10275 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10277 if (inst
.operands
[3].present
)
10279 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10280 _("expression too complex"));
10282 if (inst
.reloc
.exp
.X_add_number
!= 0)
10284 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10285 inst
.instruction
|= 0x00200000; /* sh bit */
10286 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10287 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10289 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10296 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10297 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10298 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10304 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10305 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10306 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10307 || inst
.operands
[2].negative
,
10310 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10311 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10312 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10313 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10319 if (!inst
.operands
[2].present
)
10320 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
10322 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10323 || inst
.operands
[0].reg
== inst
.operands
[2].reg
10324 || inst
.operands
[0].reg
== inst
.operands
[3].reg
10325 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
10328 inst
.instruction
|= inst
.operands
[0].reg
;
10329 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10330 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10331 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10337 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10338 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10339 inst
.instruction
|= inst
.operands
[2].reg
;
10340 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
10346 if (inst
.instruction
<= 0xffff && inst
.size_req
!= 4
10347 && inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
10348 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
10350 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10351 inst
.instruction
|= inst
.operands
[0].reg
;
10352 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10354 else if (unified_syntax
)
10356 if (inst
.instruction
<= 0xffff)
10357 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10358 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10359 inst
.instruction
|= inst
.operands
[1].reg
;
10360 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
10364 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
10365 _("Thumb encoding does not support rotation"));
10366 constraint (1, BAD_HIREG
);
10373 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
10381 half
= (inst
.instruction
& 0x10) != 0;
10382 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
10383 constraint (inst
.operands
[0].immisreg
,
10384 _("instruction requires register index"));
10385 constraint (inst
.operands
[0].imm
== 15,
10386 _("PC is not a valid index register"));
10387 constraint (!half
&& inst
.operands
[0].shifted
,
10388 _("instruction does not allow shifted index"));
10389 inst
.instruction
|= (inst
.operands
[0].reg
<< 16) | inst
.operands
[0].imm
;
10395 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10396 inst
.instruction
|= inst
.operands
[1].imm
;
10397 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10399 if (inst
.operands
[3].present
)
10401 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10402 _("expression too complex"));
10403 if (inst
.reloc
.exp
.X_add_number
!= 0)
10405 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10406 inst
.instruction
|= 0x00200000; /* sh bit */
10408 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10409 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10411 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10418 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10419 inst
.instruction
|= inst
.operands
[1].imm
;
10420 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10423 /* Neon instruction encoder helpers. */
10425 /* Encodings for the different types for various Neon opcodes. */
10427 /* An "invalid" code for the following tables. */
10430 struct neon_tab_entry
10433 unsigned float_or_poly
;
10434 unsigned scalar_or_imm
;
10437 /* Map overloaded Neon opcodes to their respective encodings. */
10438 #define NEON_ENC_TAB \
10439 X(vabd, 0x0000700, 0x1200d00, N_INV), \
10440 X(vmax, 0x0000600, 0x0000f00, N_INV), \
10441 X(vmin, 0x0000610, 0x0200f00, N_INV), \
10442 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
10443 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
10444 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
10445 X(vadd, 0x0000800, 0x0000d00, N_INV), \
10446 X(vsub, 0x1000800, 0x0200d00, N_INV), \
10447 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
10448 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
10449 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
10450 /* Register variants of the following two instructions are encoded as
10451 vcge / vcgt with the operands reversed. */ \
10452 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
10453 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
10454 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
10455 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
10456 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
10457 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
10458 X(vmlal, 0x0800800, N_INV, 0x0800240), \
10459 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
10460 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
10461 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
10462 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
10463 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
10464 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
10465 X(vshl, 0x0000400, N_INV, 0x0800510), \
10466 X(vqshl, 0x0000410, N_INV, 0x0800710), \
10467 X(vand, 0x0000110, N_INV, 0x0800030), \
10468 X(vbic, 0x0100110, N_INV, 0x0800030), \
10469 X(veor, 0x1000110, N_INV, N_INV), \
10470 X(vorn, 0x0300110, N_INV, 0x0800010), \
10471 X(vorr, 0x0200110, N_INV, 0x0800010), \
10472 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
10473 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
10474 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
10475 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
10476 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
10477 X(vst1, 0x0000000, 0x0800000, N_INV), \
10478 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
10479 X(vst2, 0x0000100, 0x0800100, N_INV), \
10480 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
10481 X(vst3, 0x0000200, 0x0800200, N_INV), \
10482 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
10483 X(vst4, 0x0000300, 0x0800300, N_INV), \
10484 X(vmovn, 0x1b20200, N_INV, N_INV), \
10485 X(vtrn, 0x1b20080, N_INV, N_INV), \
10486 X(vqmovn, 0x1b20200, N_INV, N_INV), \
10487 X(vqmovun, 0x1b20240, N_INV, N_INV), \
10488 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
10489 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \
10490 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \
10491 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
10492 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
10493 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
10494 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
10498 #define X(OPC,I,F,S) N_MNEM_##OPC
10503 static const struct neon_tab_entry neon_enc_tab
[] =
10505 #define X(OPC,I,F,S) { (I), (F), (S) }
10510 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10511 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10512 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10513 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10514 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10515 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10516 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10517 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10518 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10519 #define NEON_ENC_SINGLE(X) \
10520 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
10521 #define NEON_ENC_DOUBLE(X) \
10522 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
10524 /* Define shapes for instruction operands. The following mnemonic characters
10525 are used in this table:
10527 F - VFP S<n> register
10528 D - Neon D<n> register
10529 Q - Neon Q<n> register
10533 L - D<n> register list
10535 This table is used to generate various data:
10536 - enumerations of the form NS_DDR to be used as arguments to
10538 - a table classifying shapes into single, double, quad, mixed.
10539 - a table used to drive neon_select_shape. */
10541 #define NEON_SHAPE_DEF \
10542 X(3, (D, D, D), DOUBLE), \
10543 X(3, (Q, Q, Q), QUAD), \
10544 X(3, (D, D, I), DOUBLE), \
10545 X(3, (Q, Q, I), QUAD), \
10546 X(3, (D, D, S), DOUBLE), \
10547 X(3, (Q, Q, S), QUAD), \
10548 X(2, (D, D), DOUBLE), \
10549 X(2, (Q, Q), QUAD), \
10550 X(2, (D, S), DOUBLE), \
10551 X(2, (Q, S), QUAD), \
10552 X(2, (D, R), DOUBLE), \
10553 X(2, (Q, R), QUAD), \
10554 X(2, (D, I), DOUBLE), \
10555 X(2, (Q, I), QUAD), \
10556 X(3, (D, L, D), DOUBLE), \
10557 X(2, (D, Q), MIXED), \
10558 X(2, (Q, D), MIXED), \
10559 X(3, (D, Q, I), MIXED), \
10560 X(3, (Q, D, I), MIXED), \
10561 X(3, (Q, D, D), MIXED), \
10562 X(3, (D, Q, Q), MIXED), \
10563 X(3, (Q, Q, D), MIXED), \
10564 X(3, (Q, D, S), MIXED), \
10565 X(3, (D, Q, S), MIXED), \
10566 X(4, (D, D, D, I), DOUBLE), \
10567 X(4, (Q, Q, Q, I), QUAD), \
10568 X(2, (F, F), SINGLE), \
10569 X(3, (F, F, F), SINGLE), \
10570 X(2, (F, I), SINGLE), \
10571 X(2, (F, D), MIXED), \
10572 X(2, (D, F), MIXED), \
10573 X(3, (F, F, I), MIXED), \
10574 X(4, (R, R, F, F), SINGLE), \
10575 X(4, (F, F, R, R), SINGLE), \
10576 X(3, (D, R, R), DOUBLE), \
10577 X(3, (R, R, D), DOUBLE), \
10578 X(2, (S, R), SINGLE), \
10579 X(2, (R, S), SINGLE), \
10580 X(2, (F, R), SINGLE), \
10581 X(2, (R, F), SINGLE)
10583 #define S2(A,B) NS_##A##B
10584 #define S3(A,B,C) NS_##A##B##C
10585 #define S4(A,B,C,D) NS_##A##B##C##D
10587 #define X(N, L, C) S##N L
10600 enum neon_shape_class
10608 #define X(N, L, C) SC_##C
10610 static enum neon_shape_class neon_shape_class
[] =
10628 /* Register widths of above. */
10629 static unsigned neon_shape_el_size
[] =
10640 struct neon_shape_info
10643 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
10646 #define S2(A,B) { SE_##A, SE_##B }
10647 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
10648 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
10650 #define X(N, L, C) { N, S##N L }
10652 static struct neon_shape_info neon_shape_tab
[] =
10662 /* Bit masks used in type checking given instructions.
10663 'N_EQK' means the type must be the same as (or based on in some way) the key
10664 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
10665 set, various other bits can be set as well in order to modify the meaning of
10666 the type constraint. */
10668 enum neon_type_mask
10690 N_KEY
= 0x100000, /* key element (main type specifier). */
10691 N_EQK
= 0x200000, /* given operand has the same type & size as the key. */
10692 N_VFP
= 0x400000, /* VFP mode: operand size must match register width. */
10693 N_DBL
= 0x000001, /* if N_EQK, this operand is twice the size. */
10694 N_HLF
= 0x000002, /* if N_EQK, this operand is half the size. */
10695 N_SGN
= 0x000004, /* if N_EQK, this operand is forced to be signed. */
10696 N_UNS
= 0x000008, /* if N_EQK, this operand is forced to be unsigned. */
10697 N_INT
= 0x000010, /* if N_EQK, this operand is forced to be integer. */
10698 N_FLT
= 0x000020, /* if N_EQK, this operand is forced to be float. */
10699 N_SIZ
= 0x000040, /* if N_EQK, this operand is forced to be size-only. */
10701 N_MAX_NONSPECIAL
= N_F64
10704 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
10706 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
10707 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
10708 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
10709 #define N_SUF_32 (N_SU_32 | N_F32)
10710 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
10711 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
10713 /* Pass this as the first type argument to neon_check_type to ignore types
10715 #define N_IGNORE_TYPE (N_KEY | N_EQK)
10717 /* Select a "shape" for the current instruction (describing register types or
10718 sizes) from a list of alternatives. Return NS_NULL if the current instruction
10719 doesn't fit. For non-polymorphic shapes, checking is usually done as a
10720 function of operand parsing, so this function doesn't need to be called.
10721 Shapes should be listed in order of decreasing length. */
10723 static enum neon_shape
10724 neon_select_shape (enum neon_shape shape
, ...)
10727 enum neon_shape first_shape
= shape
;
10729 /* Fix missing optional operands. FIXME: we don't know at this point how
10730 many arguments we should have, so this makes the assumption that we have
10731 > 1. This is true of all current Neon opcodes, I think, but may not be
10732 true in the future. */
10733 if (!inst
.operands
[1].present
)
10734 inst
.operands
[1] = inst
.operands
[0];
10736 va_start (ap
, shape
);
10738 for (; shape
!= NS_NULL
; shape
= va_arg (ap
, int))
10743 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
10745 if (!inst
.operands
[j
].present
)
10751 switch (neon_shape_tab
[shape
].el
[j
])
10754 if (!(inst
.operands
[j
].isreg
10755 && inst
.operands
[j
].isvec
10756 && inst
.operands
[j
].issingle
10757 && !inst
.operands
[j
].isquad
))
10762 if (!(inst
.operands
[j
].isreg
10763 && inst
.operands
[j
].isvec
10764 && !inst
.operands
[j
].isquad
10765 && !inst
.operands
[j
].issingle
))
10770 if (!(inst
.operands
[j
].isreg
10771 && !inst
.operands
[j
].isvec
))
10776 if (!(inst
.operands
[j
].isreg
10777 && inst
.operands
[j
].isvec
10778 && inst
.operands
[j
].isquad
10779 && !inst
.operands
[j
].issingle
))
10784 if (!(!inst
.operands
[j
].isreg
10785 && !inst
.operands
[j
].isscalar
))
10790 if (!(!inst
.operands
[j
].isreg
10791 && inst
.operands
[j
].isscalar
))
10805 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
10806 first_error (_("invalid instruction shape"));
10811 /* True if SHAPE is predominantly a quadword operation (most of the time, this
10812 means the Q bit should be set). */
10815 neon_quad (enum neon_shape shape
)
10817 return neon_shape_class
[shape
] == SC_QUAD
;
10821 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
10824 /* Allow modification to be made to types which are constrained to be
10825 based on the key element, based on bits set alongside N_EQK. */
10826 if ((typebits
& N_EQK
) != 0)
10828 if ((typebits
& N_HLF
) != 0)
10830 else if ((typebits
& N_DBL
) != 0)
10832 if ((typebits
& N_SGN
) != 0)
10833 *g_type
= NT_signed
;
10834 else if ((typebits
& N_UNS
) != 0)
10835 *g_type
= NT_unsigned
;
10836 else if ((typebits
& N_INT
) != 0)
10837 *g_type
= NT_integer
;
10838 else if ((typebits
& N_FLT
) != 0)
10839 *g_type
= NT_float
;
10840 else if ((typebits
& N_SIZ
) != 0)
10841 *g_type
= NT_untyped
;
10845 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
10846 operand type, i.e. the single type specified in a Neon instruction when it
10847 is the only one given. */
10849 static struct neon_type_el
10850 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
10852 struct neon_type_el dest
= *key
;
10854 assert ((thisarg
& N_EQK
) != 0);
10856 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
10861 /* Convert Neon type and size into compact bitmask representation. */
10863 static enum neon_type_mask
10864 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
10871 case 8: return N_8
;
10872 case 16: return N_16
;
10873 case 32: return N_32
;
10874 case 64: return N_64
;
10882 case 8: return N_I8
;
10883 case 16: return N_I16
;
10884 case 32: return N_I32
;
10885 case 64: return N_I64
;
10893 case 32: return N_F32
;
10894 case 64: return N_F64
;
10902 case 8: return N_P8
;
10903 case 16: return N_P16
;
10911 case 8: return N_S8
;
10912 case 16: return N_S16
;
10913 case 32: return N_S32
;
10914 case 64: return N_S64
;
10922 case 8: return N_U8
;
10923 case 16: return N_U16
;
10924 case 32: return N_U32
;
10925 case 64: return N_U64
;
10936 /* Convert compact Neon bitmask type representation to a type and size. Only
10937 handles the case where a single bit is set in the mask. */
10940 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
10941 enum neon_type_mask mask
)
10943 if ((mask
& N_EQK
) != 0)
10946 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
10948 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
10950 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
10952 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
10957 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
10959 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
10960 *type
= NT_unsigned
;
10961 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
10962 *type
= NT_integer
;
10963 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
10964 *type
= NT_untyped
;
10965 else if ((mask
& (N_P8
| N_P16
)) != 0)
10967 else if ((mask
& (N_F32
| N_F64
)) != 0)
10975 /* Modify a bitmask of allowed types. This is only needed for type
10979 modify_types_allowed (unsigned allowed
, unsigned mods
)
10982 enum neon_el_type type
;
10988 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
10990 if (el_type_of_type_chk (&type
, &size
, allowed
& i
) == SUCCESS
)
10992 neon_modify_type_size (mods
, &type
, &size
);
10993 destmask
|= type_chk_of_el_type (type
, size
);
11000 /* Check type and return type classification.
11001 The manual states (paraphrase): If one datatype is given, it indicates the
11003 - the second operand, if there is one
11004 - the operand, if there is no second operand
11005 - the result, if there are no operands.
11006 This isn't quite good enough though, so we use a concept of a "key" datatype
11007 which is set on a per-instruction basis, which is the one which matters when
11008 only one data type is written.
11009 Note: this function has side-effects (e.g. filling in missing operands). All
11010 Neon instructions should call it before performing bit encoding. */
11012 static struct neon_type_el
11013 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
11016 unsigned i
, pass
, key_el
= 0;
11017 unsigned types
[NEON_MAX_TYPE_ELS
];
11018 enum neon_el_type k_type
= NT_invtype
;
11019 unsigned k_size
= -1u;
11020 struct neon_type_el badtype
= {NT_invtype
, -1};
11021 unsigned key_allowed
= 0;
11023 /* Optional registers in Neon instructions are always (not) in operand 1.
11024 Fill in the missing operand here, if it was omitted. */
11025 if (els
> 1 && !inst
.operands
[1].present
)
11026 inst
.operands
[1] = inst
.operands
[0];
11028 /* Suck up all the varargs. */
11030 for (i
= 0; i
< els
; i
++)
11032 unsigned thisarg
= va_arg (ap
, unsigned);
11033 if (thisarg
== N_IGNORE_TYPE
)
11038 types
[i
] = thisarg
;
11039 if ((thisarg
& N_KEY
) != 0)
11044 if (inst
.vectype
.elems
> 0)
11045 for (i
= 0; i
< els
; i
++)
11046 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
11048 first_error (_("types specified in both the mnemonic and operands"));
11052 /* Duplicate inst.vectype elements here as necessary.
11053 FIXME: No idea if this is exactly the same as the ARM assembler,
11054 particularly when an insn takes one register and one non-register
11056 if (inst
.vectype
.elems
== 1 && els
> 1)
11059 inst
.vectype
.elems
= els
;
11060 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
11061 for (j
= 0; j
< els
; j
++)
11063 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11066 else if (inst
.vectype
.elems
== 0 && els
> 0)
11069 /* No types were given after the mnemonic, so look for types specified
11070 after each operand. We allow some flexibility here; as long as the
11071 "key" operand has a type, we can infer the others. */
11072 for (j
= 0; j
< els
; j
++)
11073 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
11074 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
11076 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
11078 for (j
= 0; j
< els
; j
++)
11079 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
11080 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11085 first_error (_("operand types can't be inferred"));
11089 else if (inst
.vectype
.elems
!= els
)
11091 first_error (_("type specifier has the wrong number of parts"));
11095 for (pass
= 0; pass
< 2; pass
++)
11097 for (i
= 0; i
< els
; i
++)
11099 unsigned thisarg
= types
[i
];
11100 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
11101 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
11102 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
11103 unsigned g_size
= inst
.vectype
.el
[i
].size
;
11105 /* Decay more-specific signed & unsigned types to sign-insensitive
11106 integer types if sign-specific variants are unavailable. */
11107 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
11108 && (types_allowed
& N_SU_ALL
) == 0)
11109 g_type
= NT_integer
;
11111 /* If only untyped args are allowed, decay any more specific types to
11112 them. Some instructions only care about signs for some element
11113 sizes, so handle that properly. */
11114 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
11115 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
11116 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
11117 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
11118 g_type
= NT_untyped
;
11122 if ((thisarg
& N_KEY
) != 0)
11126 key_allowed
= thisarg
& ~N_KEY
;
11131 if ((thisarg
& N_VFP
) != 0)
11133 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
11134 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
11136 /* In VFP mode, operands must match register widths. If we
11137 have a key operand, use its width, else use the width of
11138 the current operand. */
11144 if (regwidth
!= match
)
11146 first_error (_("operand size must match register width"));
11151 if ((thisarg
& N_EQK
) == 0)
11153 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
11155 if ((given_type
& types_allowed
) == 0)
11157 first_error (_("bad type in Neon instruction"));
11163 enum neon_el_type mod_k_type
= k_type
;
11164 unsigned mod_k_size
= k_size
;
11165 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
11166 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
11168 first_error (_("inconsistent types in Neon instruction"));
11176 return inst
.vectype
.el
[key_el
];
11179 /* Neon-style VFP instruction forwarding. */
11181 /* Thumb VFP instructions have 0xE in the condition field. */
11184 do_vfp_cond_or_thumb (void)
11187 inst
.instruction
|= 0xe0000000;
11189 inst
.instruction
|= inst
.cond
<< 28;
11192 /* Look up and encode a simple mnemonic, for use as a helper function for the
11193 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
11194 etc. It is assumed that operand parsing has already been done, and that the
11195 operands are in the form expected by the given opcode (this isn't necessarily
11196 the same as the form in which they were parsed, hence some massaging must
11197 take place before this function is called).
11198 Checks current arch version against that in the looked-up opcode. */
11201 do_vfp_nsyn_opcode (const char *opname
)
11203 const struct asm_opcode
*opcode
;
11205 opcode
= hash_find (arm_ops_hsh
, opname
);
11210 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
11211 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
11216 inst
.instruction
= opcode
->tvalue
;
11217 opcode
->tencode ();
11221 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
11222 opcode
->aencode ();
11227 do_vfp_nsyn_add_sub (enum neon_shape rs
)
11229 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
11234 do_vfp_nsyn_opcode ("fadds");
11236 do_vfp_nsyn_opcode ("fsubs");
11241 do_vfp_nsyn_opcode ("faddd");
11243 do_vfp_nsyn_opcode ("fsubd");
11247 /* Check operand types to see if this is a VFP instruction, and if so call
11251 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
11253 enum neon_shape rs
;
11254 struct neon_type_el et
;
11259 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11260 et
= neon_check_type (2, rs
,
11261 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11265 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11266 et
= neon_check_type (3, rs
,
11267 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11274 if (et
.type
!= NT_invtype
)
11286 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
11288 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
11293 do_vfp_nsyn_opcode ("fmacs");
11295 do_vfp_nsyn_opcode ("fmscs");
11300 do_vfp_nsyn_opcode ("fmacd");
11302 do_vfp_nsyn_opcode ("fmscd");
11307 do_vfp_nsyn_mul (enum neon_shape rs
)
11310 do_vfp_nsyn_opcode ("fmuls");
11312 do_vfp_nsyn_opcode ("fmuld");
11316 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
11318 int is_neg
= (inst
.instruction
& 0x80) != 0;
11319 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
11324 do_vfp_nsyn_opcode ("fnegs");
11326 do_vfp_nsyn_opcode ("fabss");
11331 do_vfp_nsyn_opcode ("fnegd");
11333 do_vfp_nsyn_opcode ("fabsd");
11337 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
11338 insns belong to Neon, and are handled elsewhere. */
11341 do_vfp_nsyn_ldm_stm (int is_dbmode
)
11343 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
11347 do_vfp_nsyn_opcode ("fldmdbs");
11349 do_vfp_nsyn_opcode ("fldmias");
11354 do_vfp_nsyn_opcode ("fstmdbs");
11356 do_vfp_nsyn_opcode ("fstmias");
11361 do_vfp_nsyn_sqrt (void)
11363 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11364 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11367 do_vfp_nsyn_opcode ("fsqrts");
11369 do_vfp_nsyn_opcode ("fsqrtd");
11373 do_vfp_nsyn_div (void)
11375 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11376 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11377 N_F32
| N_F64
| N_KEY
| N_VFP
);
11380 do_vfp_nsyn_opcode ("fdivs");
11382 do_vfp_nsyn_opcode ("fdivd");
11386 do_vfp_nsyn_nmul (void)
11388 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11389 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11390 N_F32
| N_F64
| N_KEY
| N_VFP
);
11394 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11395 do_vfp_sp_dyadic ();
11399 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11400 do_vfp_dp_rd_rn_rm ();
11402 do_vfp_cond_or_thumb ();
11406 do_vfp_nsyn_cmp (void)
11408 if (inst
.operands
[1].isreg
)
11410 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11411 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11415 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11416 do_vfp_sp_monadic ();
11420 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11421 do_vfp_dp_rd_rm ();
11426 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
11427 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
11429 switch (inst
.instruction
& 0x0fffffff)
11432 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
11435 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
11443 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11444 do_vfp_sp_compare_z ();
11448 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11452 do_vfp_cond_or_thumb ();
11456 nsyn_insert_sp (void)
11458 inst
.operands
[1] = inst
.operands
[0];
11459 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
11460 inst
.operands
[0].reg
= 13;
11461 inst
.operands
[0].isreg
= 1;
11462 inst
.operands
[0].writeback
= 1;
11463 inst
.operands
[0].present
= 1;
11467 do_vfp_nsyn_push (void)
11470 if (inst
.operands
[1].issingle
)
11471 do_vfp_nsyn_opcode ("fstmdbs");
11473 do_vfp_nsyn_opcode ("fstmdbd");
11477 do_vfp_nsyn_pop (void)
11480 if (inst
.operands
[1].issingle
)
11481 do_vfp_nsyn_opcode ("fldmias");
11483 do_vfp_nsyn_opcode ("fldmiad");
11486 /* Fix up Neon data-processing instructions, ORing in the correct bits for
11487 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
11490 neon_dp_fixup (unsigned i
)
11494 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
11508 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
11512 neon_logbits (unsigned x
)
11514 return ffs (x
) - 4;
11517 #define LOW4(R) ((R) & 0xf)
11518 #define HI1(R) (((R) >> 4) & 1)
11520 /* Encode insns with bit pattern:
11522 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
11523 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
11525 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
11526 different meaning for some instruction. */
11529 neon_three_same (int isquad
, int ubit
, int size
)
11531 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11532 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11533 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
11534 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
11535 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
11536 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
11537 inst
.instruction
|= (isquad
!= 0) << 6;
11538 inst
.instruction
|= (ubit
!= 0) << 24;
11540 inst
.instruction
|= neon_logbits (size
) << 20;
11542 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11545 /* Encode instructions of the form:
11547 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
11548 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
11550 Don't write size if SIZE == -1. */
11553 neon_two_same (int qbit
, int ubit
, int size
)
11555 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11556 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11557 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11558 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11559 inst
.instruction
|= (qbit
!= 0) << 6;
11560 inst
.instruction
|= (ubit
!= 0) << 24;
11563 inst
.instruction
|= neon_logbits (size
) << 18;
11565 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11568 /* Neon instruction encoders, in approximate order of appearance. */
11571 do_neon_dyadic_i_su (void)
11573 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11574 struct neon_type_el et
= neon_check_type (3, rs
,
11575 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
11576 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11580 do_neon_dyadic_i64_su (void)
11582 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11583 struct neon_type_el et
= neon_check_type (3, rs
,
11584 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11585 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11589 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
11592 unsigned size
= et
.size
>> 3;
11593 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11594 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11595 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11596 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11597 inst
.instruction
|= (isquad
!= 0) << 6;
11598 inst
.instruction
|= immbits
<< 16;
11599 inst
.instruction
|= (size
>> 3) << 7;
11600 inst
.instruction
|= (size
& 0x7) << 19;
11602 inst
.instruction
|= (uval
!= 0) << 24;
11604 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11608 do_neon_shl_imm (void)
11610 if (!inst
.operands
[2].isreg
)
11612 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11613 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
11614 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11615 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
11619 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11620 struct neon_type_el et
= neon_check_type (3, rs
,
11621 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11624 /* VSHL/VQSHL 3-register variants have syntax such as:
11626 whereas other 3-register operations encoded by neon_three_same have
11629 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
11631 tmp
= inst
.operands
[2].reg
;
11632 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11633 inst
.operands
[1].reg
= tmp
;
11634 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11635 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11640 do_neon_qshl_imm (void)
11642 if (!inst
.operands
[2].isreg
)
11644 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11645 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
11647 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11648 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
11649 inst
.operands
[2].imm
);
11653 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11654 struct neon_type_el et
= neon_check_type (3, rs
,
11655 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11658 /* See note in do_neon_shl_imm. */
11659 tmp
= inst
.operands
[2].reg
;
11660 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11661 inst
.operands
[1].reg
= tmp
;
11662 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11663 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11668 do_neon_rshl (void)
11670 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11671 struct neon_type_el et
= neon_check_type (3, rs
,
11672 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11675 tmp
= inst
.operands
[2].reg
;
11676 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11677 inst
.operands
[1].reg
= tmp
;
11678 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11682 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
11684 /* Handle .I8 pseudo-instructions. */
11687 /* Unfortunately, this will make everything apart from zero out-of-range.
11688 FIXME is this the intended semantics? There doesn't seem much point in
11689 accepting .I8 if so. */
11690 immediate
|= immediate
<< 8;
11696 if (immediate
== (immediate
& 0x000000ff))
11698 *immbits
= immediate
;
11701 else if (immediate
== (immediate
& 0x0000ff00))
11703 *immbits
= immediate
>> 8;
11706 else if (immediate
== (immediate
& 0x00ff0000))
11708 *immbits
= immediate
>> 16;
11711 else if (immediate
== (immediate
& 0xff000000))
11713 *immbits
= immediate
>> 24;
11716 if ((immediate
& 0xffff) != (immediate
>> 16))
11717 goto bad_immediate
;
11718 immediate
&= 0xffff;
11721 if (immediate
== (immediate
& 0x000000ff))
11723 *immbits
= immediate
;
11726 else if (immediate
== (immediate
& 0x0000ff00))
11728 *immbits
= immediate
>> 8;
11733 first_error (_("immediate value out of range"));
11737 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
11741 neon_bits_same_in_bytes (unsigned imm
)
11743 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
11744 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
11745 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
11746 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
11749 /* For immediate of above form, return 0bABCD. */
11752 neon_squash_bits (unsigned imm
)
11754 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
11755 | ((imm
& 0x01000000) >> 21);
11758 /* Compress quarter-float representation to 0b...000 abcdefgh. */
11761 neon_qfloat_bits (unsigned imm
)
11763 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
11766 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
11767 the instruction. *OP is passed as the initial value of the op field, and
11768 may be set to a different value depending on the constant (i.e.
11769 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
11770 MVN). If the immediate looks like a repeated pattern then also
11771 try smaller element sizes. */
11774 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
11775 unsigned *immbits
, int *op
, int size
,
11776 enum neon_el_type type
)
11778 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
11780 if (type
== NT_float
&& !float_p
)
11783 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
11785 if (size
!= 32 || *op
== 1)
11787 *immbits
= neon_qfloat_bits (immlo
);
11793 if (neon_bits_same_in_bytes (immhi
)
11794 && neon_bits_same_in_bytes (immlo
))
11798 *immbits
= (neon_squash_bits (immhi
) << 4)
11799 | neon_squash_bits (immlo
);
11804 if (immhi
!= immlo
)
11810 if (immlo
== (immlo
& 0x000000ff))
11815 else if (immlo
== (immlo
& 0x0000ff00))
11817 *immbits
= immlo
>> 8;
11820 else if (immlo
== (immlo
& 0x00ff0000))
11822 *immbits
= immlo
>> 16;
11825 else if (immlo
== (immlo
& 0xff000000))
11827 *immbits
= immlo
>> 24;
11830 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
11832 *immbits
= (immlo
>> 8) & 0xff;
11835 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
11837 *immbits
= (immlo
>> 16) & 0xff;
11841 if ((immlo
& 0xffff) != (immlo
>> 16))
11848 if (immlo
== (immlo
& 0x000000ff))
11853 else if (immlo
== (immlo
& 0x0000ff00))
11855 *immbits
= immlo
>> 8;
11859 if ((immlo
& 0xff) != (immlo
>> 8))
11864 if (immlo
== (immlo
& 0x000000ff))
11866 /* Don't allow MVN with 8-bit immediate. */
11876 /* Write immediate bits [7:0] to the following locations:
11878 |28/24|23 19|18 16|15 4|3 0|
11879 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
11881 This function is used by VMOV/VMVN/VORR/VBIC. */
11884 neon_write_immbits (unsigned immbits
)
11886 inst
.instruction
|= immbits
& 0xf;
11887 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
11888 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
11891 /* Invert low-order SIZE bits of XHI:XLO. */
11894 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
11896 unsigned immlo
= xlo
? *xlo
: 0;
11897 unsigned immhi
= xhi
? *xhi
: 0;
11902 immlo
= (~immlo
) & 0xff;
11906 immlo
= (~immlo
) & 0xffff;
11910 immhi
= (~immhi
) & 0xffffffff;
11911 /* fall through. */
11914 immlo
= (~immlo
) & 0xffffffff;
11929 do_neon_logic (void)
11931 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
11933 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11934 neon_check_type (3, rs
, N_IGNORE_TYPE
);
11935 /* U bit and size field were set as part of the bitmask. */
11936 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11937 neon_three_same (neon_quad (rs
), 0, -1);
11941 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
11942 struct neon_type_el et
= neon_check_type (2, rs
,
11943 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
11944 enum neon_opc opcode
= inst
.instruction
& 0x0fffffff;
11948 if (et
.type
== NT_invtype
)
11951 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11953 immbits
= inst
.operands
[1].imm
;
11956 /* .i64 is a pseudo-op, so the immediate must be a repeating
11958 if (immbits
!= (inst
.operands
[1].regisimm
?
11959 inst
.operands
[1].reg
: 0))
11961 /* Set immbits to an invalid constant. */
11962 immbits
= 0xdeadbeef;
11969 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11973 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11977 /* Pseudo-instruction for VBIC. */
11978 neon_invert_size (&immbits
, 0, et
.size
);
11979 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11983 /* Pseudo-instruction for VORR. */
11984 neon_invert_size (&immbits
, 0, et
.size
);
11985 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11995 inst
.instruction
|= neon_quad (rs
) << 6;
11996 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11997 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11998 inst
.instruction
|= cmode
<< 8;
11999 neon_write_immbits (immbits
);
12001 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12006 do_neon_bitfield (void)
12008 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12009 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12010 neon_three_same (neon_quad (rs
), 0, -1);
12014 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
12017 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12018 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
12020 if (et
.type
== NT_float
)
12022 inst
.instruction
= NEON_ENC_FLOAT (inst
.instruction
);
12023 neon_three_same (neon_quad (rs
), 0, -1);
12027 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12028 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
12033 do_neon_dyadic_if_su (void)
12035 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12039 do_neon_dyadic_if_su_d (void)
12041 /* This version only allow D registers, but that constraint is enforced during
12042 operand parsing so we don't need to do anything extra here. */
12043 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12047 do_neon_dyadic_if_i_d (void)
12049 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12050 affected if we specify unsigned args. */
12051 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12054 enum vfp_or_neon_is_neon_bits
12057 NEON_CHECK_ARCH
= 2
12060 /* Call this function if an instruction which may have belonged to the VFP or
12061 Neon instruction sets, but turned out to be a Neon instruction (due to the
12062 operand types involved, etc.). We have to check and/or fix-up a couple of
12065 - Make sure the user hasn't attempted to make a Neon instruction
12067 - Alter the value in the condition code field if necessary.
12068 - Make sure that the arch supports Neon instructions.
12070 Which of these operations take place depends on bits from enum
12071 vfp_or_neon_is_neon_bits.
12073 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
12074 current instruction's condition is COND_ALWAYS, the condition field is
12075 changed to inst.uncond_value. This is necessary because instructions shared
12076 between VFP and Neon may be conditional for the VFP variants only, and the
12077 unconditional Neon version must have, e.g., 0xF in the condition field. */
12080 vfp_or_neon_is_neon (unsigned check
)
12082 /* Conditions are always legal in Thumb mode (IT blocks). */
12083 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
12085 if (inst
.cond
!= COND_ALWAYS
)
12087 first_error (_(BAD_COND
));
12090 if (inst
.uncond_value
!= -1)
12091 inst
.instruction
|= inst
.uncond_value
<< 28;
12094 if ((check
& NEON_CHECK_ARCH
)
12095 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
12097 first_error (_(BAD_FPU
));
12105 do_neon_addsub_if_i (void)
12107 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
12110 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12113 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12114 affected if we specify unsigned args. */
12115 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
12118 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
12120 V<op> A,B (A is operand 0, B is operand 2)
12125 so handle that case specially. */
12128 neon_exchange_operands (void)
12130 void *scratch
= alloca (sizeof (inst
.operands
[0]));
12131 if (inst
.operands
[1].present
)
12133 /* Swap operands[1] and operands[2]. */
12134 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
12135 inst
.operands
[1] = inst
.operands
[2];
12136 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
12140 inst
.operands
[1] = inst
.operands
[2];
12141 inst
.operands
[2] = inst
.operands
[0];
12146 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
12148 if (inst
.operands
[2].isreg
)
12151 neon_exchange_operands ();
12152 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
12156 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12157 struct neon_type_el et
= neon_check_type (2, rs
,
12158 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
12160 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12161 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12162 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12163 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12164 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12165 inst
.instruction
|= neon_quad (rs
) << 6;
12166 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12167 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12169 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12176 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
12180 do_neon_cmp_inv (void)
12182 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
12188 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
12191 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
12192 scalars, which are encoded in 5 bits, M : Rm.
12193 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
12194 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
12198 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
12200 unsigned regno
= NEON_SCALAR_REG (scalar
);
12201 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
12206 if (regno
> 7 || elno
> 3)
12208 return regno
| (elno
<< 3);
12211 if (regno
> 15 || elno
> 1)
12213 return regno
| (elno
<< 4);
12217 first_error (_("scalar out of range for multiply instruction"));
12223 /* Encode multiply / multiply-accumulate scalar instructions. */
12226 neon_mul_mac (struct neon_type_el et
, int ubit
)
12230 /* Give a more helpful error message if we have an invalid type. */
12231 if (et
.type
== NT_invtype
)
12234 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
12235 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12236 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12237 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12238 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12239 inst
.instruction
|= LOW4 (scalar
);
12240 inst
.instruction
|= HI1 (scalar
) << 5;
12241 inst
.instruction
|= (et
.type
== NT_float
) << 8;
12242 inst
.instruction
|= neon_logbits (et
.size
) << 20;
12243 inst
.instruction
|= (ubit
!= 0) << 24;
12245 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12249 do_neon_mac_maybe_scalar (void)
12251 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
12254 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12257 if (inst
.operands
[2].isscalar
)
12259 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
12260 struct neon_type_el et
= neon_check_type (3, rs
,
12261 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
12262 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12263 neon_mul_mac (et
, neon_quad (rs
));
12267 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12268 affected if we specify unsigned args. */
12269 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12276 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12277 struct neon_type_el et
= neon_check_type (3, rs
,
12278 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12279 neon_three_same (neon_quad (rs
), 0, et
.size
);
12282 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
12283 same types as the MAC equivalents. The polynomial type for this instruction
12284 is encoded the same as the integer type. */
12289 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
12292 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12295 if (inst
.operands
[2].isscalar
)
12296 do_neon_mac_maybe_scalar ();
12298 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
12302 do_neon_qdmulh (void)
12304 if (inst
.operands
[2].isscalar
)
12306 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
12307 struct neon_type_el et
= neon_check_type (3, rs
,
12308 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
12309 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12310 neon_mul_mac (et
, neon_quad (rs
));
12314 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12315 struct neon_type_el et
= neon_check_type (3, rs
,
12316 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
12317 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12318 /* The U bit (rounding) comes from bit mask. */
12319 neon_three_same (neon_quad (rs
), 0, et
.size
);
12324 do_neon_fcmp_absolute (void)
12326 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12327 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12328 /* Size field comes from bit mask. */
12329 neon_three_same (neon_quad (rs
), 1, -1);
12333 do_neon_fcmp_absolute_inv (void)
12335 neon_exchange_operands ();
12336 do_neon_fcmp_absolute ();
12340 do_neon_step (void)
12342 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12343 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12344 neon_three_same (neon_quad (rs
), 0, -1);
12348 do_neon_abs_neg (void)
12350 enum neon_shape rs
;
12351 struct neon_type_el et
;
12353 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
12356 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12359 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12360 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
12362 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12363 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12364 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12365 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12366 inst
.instruction
|= neon_quad (rs
) << 6;
12367 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12368 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12370 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12376 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12377 struct neon_type_el et
= neon_check_type (2, rs
,
12378 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12379 int imm
= inst
.operands
[2].imm
;
12380 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12381 _("immediate out of range for insert"));
12382 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12388 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12389 struct neon_type_el et
= neon_check_type (2, rs
,
12390 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12391 int imm
= inst
.operands
[2].imm
;
12392 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12393 _("immediate out of range for insert"));
12394 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
12398 do_neon_qshlu_imm (void)
12400 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12401 struct neon_type_el et
= neon_check_type (2, rs
,
12402 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
12403 int imm
= inst
.operands
[2].imm
;
12404 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12405 _("immediate out of range for shift"));
12406 /* Only encodes the 'U present' variant of the instruction.
12407 In this case, signed types have OP (bit 8) set to 0.
12408 Unsigned types have OP set to 1. */
12409 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
12410 /* The rest of the bits are the same as other immediate shifts. */
12411 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12415 do_neon_qmovn (void)
12417 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12418 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12419 /* Saturating move where operands can be signed or unsigned, and the
12420 destination has the same signedness. */
12421 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12422 if (et
.type
== NT_unsigned
)
12423 inst
.instruction
|= 0xc0;
12425 inst
.instruction
|= 0x80;
12426 neon_two_same (0, 1, et
.size
/ 2);
12430 do_neon_qmovun (void)
12432 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12433 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12434 /* Saturating move with unsigned results. Operands must be signed. */
12435 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12436 neon_two_same (0, 1, et
.size
/ 2);
12440 do_neon_rshift_sat_narrow (void)
12442 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12443 or unsigned. If operands are unsigned, results must also be unsigned. */
12444 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12445 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12446 int imm
= inst
.operands
[2].imm
;
12447 /* This gets the bounds check, size encoding and immediate bits calculation
12451 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
12452 VQMOVN.I<size> <Dd>, <Qm>. */
12455 inst
.operands
[2].present
= 0;
12456 inst
.instruction
= N_MNEM_vqmovn
;
12461 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12462 _("immediate out of range"));
12463 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
12467 do_neon_rshift_sat_narrow_u (void)
12469 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12470 or unsigned. If operands are unsigned, results must also be unsigned. */
12471 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12472 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12473 int imm
= inst
.operands
[2].imm
;
12474 /* This gets the bounds check, size encoding and immediate bits calculation
12478 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
12479 VQMOVUN.I<size> <Dd>, <Qm>. */
12482 inst
.operands
[2].present
= 0;
12483 inst
.instruction
= N_MNEM_vqmovun
;
12488 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12489 _("immediate out of range"));
12490 /* FIXME: The manual is kind of unclear about what value U should have in
12491 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
12493 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
12497 do_neon_movn (void)
12499 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12500 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12501 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12502 neon_two_same (0, 1, et
.size
/ 2);
12506 do_neon_rshift_narrow (void)
12508 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12509 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12510 int imm
= inst
.operands
[2].imm
;
12511 /* This gets the bounds check, size encoding and immediate bits calculation
12515 /* If immediate is zero then we are a pseudo-instruction for
12516 VMOVN.I<size> <Dd>, <Qm> */
12519 inst
.operands
[2].present
= 0;
12520 inst
.instruction
= N_MNEM_vmovn
;
12525 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12526 _("immediate out of range for narrowing operation"));
12527 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
12531 do_neon_shll (void)
12533 /* FIXME: Type checking when lengthening. */
12534 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
12535 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
12536 unsigned imm
= inst
.operands
[2].imm
;
12538 if (imm
== et
.size
)
12540 /* Maximum shift variant. */
12541 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12542 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12543 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12544 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12545 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12546 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12548 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12552 /* A more-specific type check for non-max versions. */
12553 et
= neon_check_type (2, NS_QDI
,
12554 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12555 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12556 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
12560 /* Check the various types for the VCVT instruction, and return which version
12561 the current instruction is. */
12564 neon_cvt_flavour (enum neon_shape rs
)
12566 #define CVT_VAR(C,X,Y) \
12567 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
12568 if (et.type != NT_invtype) \
12570 inst.error = NULL; \
12573 struct neon_type_el et
;
12574 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
12575 || rs
== NS_FF
) ? N_VFP
: 0;
12576 /* The instruction versions which take an immediate take one register
12577 argument, which is extended to the width of the full register. Thus the
12578 "source" and "destination" registers must have the same width. Hack that
12579 here by making the size equal to the key (wider, in this case) operand. */
12580 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
12582 CVT_VAR (0, N_S32
, N_F32
);
12583 CVT_VAR (1, N_U32
, N_F32
);
12584 CVT_VAR (2, N_F32
, N_S32
);
12585 CVT_VAR (3, N_F32
, N_U32
);
12589 /* VFP instructions. */
12590 CVT_VAR (4, N_F32
, N_F64
);
12591 CVT_VAR (5, N_F64
, N_F32
);
12592 CVT_VAR (6, N_S32
, N_F64
| key
);
12593 CVT_VAR (7, N_U32
, N_F64
| key
);
12594 CVT_VAR (8, N_F64
| key
, N_S32
);
12595 CVT_VAR (9, N_F64
| key
, N_U32
);
12596 /* VFP instructions with bitshift. */
12597 CVT_VAR (10, N_F32
| key
, N_S16
);
12598 CVT_VAR (11, N_F32
| key
, N_U16
);
12599 CVT_VAR (12, N_F64
| key
, N_S16
);
12600 CVT_VAR (13, N_F64
| key
, N_U16
);
12601 CVT_VAR (14, N_S16
, N_F32
| key
);
12602 CVT_VAR (15, N_U16
, N_F32
| key
);
12603 CVT_VAR (16, N_S16
, N_F64
| key
);
12604 CVT_VAR (17, N_U16
, N_F64
| key
);
12610 /* Neon-syntax VFP conversions. */
12613 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
12615 const char *opname
= 0;
12617 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
12619 /* Conversions with immediate bitshift. */
12620 const char *enc
[] =
12642 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12644 opname
= enc
[flavour
];
12645 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12646 _("operands 0 and 1 must be the same register"));
12647 inst
.operands
[1] = inst
.operands
[2];
12648 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
12653 /* Conversions without bitshift. */
12654 const char *enc
[] =
12668 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12669 opname
= enc
[flavour
];
12673 do_vfp_nsyn_opcode (opname
);
12677 do_vfp_nsyn_cvtz (void)
12679 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
12680 int flavour
= neon_cvt_flavour (rs
);
12681 const char *enc
[] =
12693 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
12694 do_vfp_nsyn_opcode (enc
[flavour
]);
12700 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
12701 NS_FD
, NS_DF
, NS_FF
, NS_NULL
);
12702 int flavour
= neon_cvt_flavour (rs
);
12704 /* VFP rather than Neon conversions. */
12707 do_vfp_nsyn_cvt (rs
, flavour
);
12716 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12719 /* Fixed-point conversion with #0 immediate is encoded as an
12720 integer conversion. */
12721 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
12723 unsigned immbits
= 32 - inst
.operands
[2].imm
;
12724 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
12725 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12727 inst
.instruction
|= enctab
[flavour
];
12728 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12729 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12730 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12731 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12732 inst
.instruction
|= neon_quad (rs
) << 6;
12733 inst
.instruction
|= 1 << 21;
12734 inst
.instruction
|= immbits
<< 16;
12736 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12744 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
12746 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12748 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12752 inst
.instruction
|= enctab
[flavour
];
12754 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12755 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12756 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12757 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12758 inst
.instruction
|= neon_quad (rs
) << 6;
12759 inst
.instruction
|= 2 << 18;
12761 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12766 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
12767 do_vfp_nsyn_cvt (rs
, flavour
);
12772 neon_move_immediate (void)
12774 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12775 struct neon_type_el et
= neon_check_type (2, rs
,
12776 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12777 unsigned immlo
, immhi
= 0, immbits
;
12778 int op
, cmode
, float_p
;
12780 constraint (et
.type
== NT_invtype
,
12781 _("operand size must be specified for immediate VMOV"));
12783 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
12784 op
= (inst
.instruction
& (1 << 5)) != 0;
12786 immlo
= inst
.operands
[1].imm
;
12787 if (inst
.operands
[1].regisimm
)
12788 immhi
= inst
.operands
[1].reg
;
12790 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
12791 _("immediate has bits set outside the operand size"));
12793 float_p
= inst
.operands
[1].immisfloat
;
12795 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
12796 et
.size
, et
.type
)) == FAIL
)
12798 /* Invert relevant bits only. */
12799 neon_invert_size (&immlo
, &immhi
, et
.size
);
12800 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
12801 with one or the other; those cases are caught by
12802 neon_cmode_for_move_imm. */
12804 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
12805 &op
, et
.size
, et
.type
)) == FAIL
)
12807 first_error (_("immediate out of range"));
12812 inst
.instruction
&= ~(1 << 5);
12813 inst
.instruction
|= op
<< 5;
12815 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12816 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12817 inst
.instruction
|= neon_quad (rs
) << 6;
12818 inst
.instruction
|= cmode
<< 8;
12820 neon_write_immbits (immbits
);
12826 if (inst
.operands
[1].isreg
)
12828 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12830 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12831 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12832 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12833 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12834 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12835 inst
.instruction
|= neon_quad (rs
) << 6;
12839 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12840 neon_move_immediate ();
12843 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12846 /* Encode instructions of form:
12848 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12849 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
12852 neon_mixed_length (struct neon_type_el et
, unsigned size
)
12854 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12855 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12856 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12857 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12858 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12859 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12860 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
12861 inst
.instruction
|= neon_logbits (size
) << 20;
12863 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12867 do_neon_dyadic_long (void)
12869 /* FIXME: Type checking for lengthening op. */
12870 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12871 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12872 neon_mixed_length (et
, et
.size
);
12876 do_neon_abal (void)
12878 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12879 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12880 neon_mixed_length (et
, et
.size
);
12884 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
12886 if (inst
.operands
[2].isscalar
)
12888 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
12889 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
12890 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12891 neon_mul_mac (et
, et
.type
== NT_unsigned
);
12895 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12896 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
12897 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12898 neon_mixed_length (et
, et
.size
);
12903 do_neon_mac_maybe_scalar_long (void)
12905 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
12909 do_neon_dyadic_wide (void)
12911 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
12912 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12913 neon_mixed_length (et
, et
.size
);
12917 do_neon_dyadic_narrow (void)
12919 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12920 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
12921 /* Operand sign is unimportant, and the U bit is part of the opcode,
12922 so force the operand type to integer. */
12923 et
.type
= NT_integer
;
12924 neon_mixed_length (et
, et
.size
/ 2);
12928 do_neon_mul_sat_scalar_long (void)
12930 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
12934 do_neon_vmull (void)
12936 if (inst
.operands
[2].isscalar
)
12937 do_neon_mac_maybe_scalar_long ();
12940 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12941 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
12942 if (et
.type
== NT_poly
)
12943 inst
.instruction
= NEON_ENC_POLY (inst
.instruction
);
12945 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12946 /* For polynomial encoding, size field must be 0b00 and the U bit must be
12947 zero. Should be OK as-is. */
12948 neon_mixed_length (et
, et
.size
);
12955 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
12956 struct neon_type_el et
= neon_check_type (3, rs
,
12957 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12958 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
12959 constraint (imm
>= (neon_quad (rs
) ? 16 : 8), _("shift out of range"));
12960 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12961 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12962 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12963 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12964 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12965 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12966 inst
.instruction
|= neon_quad (rs
) << 6;
12967 inst
.instruction
|= imm
<< 8;
12969 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12975 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12976 struct neon_type_el et
= neon_check_type (2, rs
,
12977 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12978 unsigned op
= (inst
.instruction
>> 7) & 3;
12979 /* N (width of reversed regions) is encoded as part of the bitmask. We
12980 extract it here to check the elements to be reversed are smaller.
12981 Otherwise we'd get a reserved instruction. */
12982 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
12983 assert (elsize
!= 0);
12984 constraint (et
.size
>= elsize
,
12985 _("elements must be smaller than reversal region"));
12986 neon_two_same (neon_quad (rs
), 1, et
.size
);
12992 if (inst
.operands
[1].isscalar
)
12994 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
12995 struct neon_type_el et
= neon_check_type (2, rs
,
12996 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12997 unsigned sizebits
= et
.size
>> 3;
12998 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
12999 int logsize
= neon_logbits (et
.size
);
13000 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
13002 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
13005 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13006 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13007 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13008 inst
.instruction
|= LOW4 (dm
);
13009 inst
.instruction
|= HI1 (dm
) << 5;
13010 inst
.instruction
|= neon_quad (rs
) << 6;
13011 inst
.instruction
|= x
<< 17;
13012 inst
.instruction
|= sizebits
<< 16;
13014 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13018 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
13019 struct neon_type_el et
= neon_check_type (2, rs
,
13020 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13021 /* Duplicate ARM register to lanes of vector. */
13022 inst
.instruction
= NEON_ENC_ARMREG (inst
.instruction
);
13025 case 8: inst
.instruction
|= 0x400000; break;
13026 case 16: inst
.instruction
|= 0x000020; break;
13027 case 32: inst
.instruction
|= 0x000000; break;
13030 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13031 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
13032 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
13033 inst
.instruction
|= neon_quad (rs
) << 21;
13034 /* The encoding for this instruction is identical for the ARM and Thumb
13035 variants, except for the condition field. */
13036 do_vfp_cond_or_thumb ();
13040 /* VMOV has particularly many variations. It can be one of:
13041 0. VMOV<c><q> <Qd>, <Qm>
13042 1. VMOV<c><q> <Dd>, <Dm>
13043 (Register operations, which are VORR with Rm = Rn.)
13044 2. VMOV<c><q>.<dt> <Qd>, #<imm>
13045 3. VMOV<c><q>.<dt> <Dd>, #<imm>
13047 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
13048 (ARM register to scalar.)
13049 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
13050 (Two ARM registers to vector.)
13051 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
13052 (Scalar to ARM register.)
13053 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
13054 (Vector to two ARM registers.)
13055 8. VMOV.F32 <Sd>, <Sm>
13056 9. VMOV.F64 <Dd>, <Dm>
13057 (VFP register moves.)
13058 10. VMOV.F32 <Sd>, #imm
13059 11. VMOV.F64 <Dd>, #imm
13060 (VFP float immediate load.)
13061 12. VMOV <Rd>, <Sm>
13062 (VFP single to ARM reg.)
13063 13. VMOV <Sd>, <Rm>
13064 (ARM reg to VFP single.)
13065 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
13066 (Two ARM regs to two VFP singles.)
13067 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
13068 (Two VFP singles to two ARM regs.)
13070 These cases can be disambiguated using neon_select_shape, except cases 1/9
13071 and 3/11 which depend on the operand type too.
13073 All the encoded bits are hardcoded by this function.
13075 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
13076 Cases 5, 7 may be used with VFPv2 and above.
13078 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
13079 can specify a type where it doesn't make sense to, and is ignored). */
13084 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
13085 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
13087 struct neon_type_el et
;
13088 const char *ldconst
= 0;
13092 case NS_DD
: /* case 1/9. */
13093 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
13094 /* It is not an error here if no type is given. */
13096 if (et
.type
== NT_float
&& et
.size
== 64)
13098 do_vfp_nsyn_opcode ("fcpyd");
13101 /* fall through. */
13103 case NS_QQ
: /* case 0/1. */
13105 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13107 /* The architecture manual I have doesn't explicitly state which
13108 value the U bit should have for register->register moves, but
13109 the equivalent VORR instruction has U = 0, so do that. */
13110 inst
.instruction
= 0x0200110;
13111 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13112 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13113 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13114 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13115 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13116 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13117 inst
.instruction
|= neon_quad (rs
) << 6;
13119 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13123 case NS_DI
: /* case 3/11. */
13124 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
13126 if (et
.type
== NT_float
&& et
.size
== 64)
13128 /* case 11 (fconstd). */
13129 ldconst
= "fconstd";
13130 goto encode_fconstd
;
13132 /* fall through. */
13134 case NS_QI
: /* case 2/3. */
13135 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13137 inst
.instruction
= 0x0800010;
13138 neon_move_immediate ();
13139 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13142 case NS_SR
: /* case 4. */
13144 unsigned bcdebits
= 0;
13145 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
13146 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13147 int logsize
= neon_logbits (et
.size
);
13148 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
13149 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
13151 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
13153 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
13154 && et
.size
!= 32, _(BAD_FPU
));
13155 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
13156 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
13160 case 8: bcdebits
= 0x8; break;
13161 case 16: bcdebits
= 0x1; break;
13162 case 32: bcdebits
= 0x0; break;
13166 bcdebits
|= x
<< logsize
;
13168 inst
.instruction
= 0xe000b10;
13169 do_vfp_cond_or_thumb ();
13170 inst
.instruction
|= LOW4 (dn
) << 16;
13171 inst
.instruction
|= HI1 (dn
) << 7;
13172 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13173 inst
.instruction
|= (bcdebits
& 3) << 5;
13174 inst
.instruction
|= (bcdebits
>> 2) << 21;
13178 case NS_DRR
: /* case 5 (fmdrr). */
13179 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
13182 inst
.instruction
= 0xc400b10;
13183 do_vfp_cond_or_thumb ();
13184 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
13185 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
13186 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13187 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13190 case NS_RS
: /* case 6. */
13192 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
13193 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
13194 unsigned logsize
= neon_logbits (et
.size
);
13195 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
13196 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
13197 unsigned abcdebits
= 0;
13199 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
13201 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
13202 && et
.size
!= 32, _(BAD_FPU
));
13203 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
13204 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
13208 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
13209 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
13210 case 32: abcdebits
= 0x00; break;
13214 abcdebits
|= x
<< logsize
;
13215 inst
.instruction
= 0xe100b10;
13216 do_vfp_cond_or_thumb ();
13217 inst
.instruction
|= LOW4 (dn
) << 16;
13218 inst
.instruction
|= HI1 (dn
) << 7;
13219 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
13220 inst
.instruction
|= (abcdebits
& 3) << 5;
13221 inst
.instruction
|= (abcdebits
>> 2) << 21;
13225 case NS_RRD
: /* case 7 (fmrrd). */
13226 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
13229 inst
.instruction
= 0xc500b10;
13230 do_vfp_cond_or_thumb ();
13231 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
13232 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13233 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13234 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13237 case NS_FF
: /* case 8 (fcpys). */
13238 do_vfp_nsyn_opcode ("fcpys");
13241 case NS_FI
: /* case 10 (fconsts). */
13242 ldconst
= "fconsts";
13244 if (is_quarter_float (inst
.operands
[1].imm
))
13246 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
13247 do_vfp_nsyn_opcode (ldconst
);
13250 first_error (_("immediate out of range"));
13253 case NS_RF
: /* case 12 (fmrs). */
13254 do_vfp_nsyn_opcode ("fmrs");
13257 case NS_FR
: /* case 13 (fmsr). */
13258 do_vfp_nsyn_opcode ("fmsr");
13261 /* The encoders for the fmrrs and fmsrr instructions expect three operands
13262 (one of which is a list), but we have parsed four. Do some fiddling to
13263 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
13265 case NS_RRFF
: /* case 14 (fmrrs). */
13266 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
13267 _("VFP registers must be adjacent"));
13268 inst
.operands
[2].imm
= 2;
13269 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
13270 do_vfp_nsyn_opcode ("fmrrs");
13273 case NS_FFRR
: /* case 15 (fmsrr). */
13274 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
13275 _("VFP registers must be adjacent"));
13276 inst
.operands
[1] = inst
.operands
[2];
13277 inst
.operands
[2] = inst
.operands
[3];
13278 inst
.operands
[0].imm
= 2;
13279 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
13280 do_vfp_nsyn_opcode ("fmsrr");
13289 do_neon_rshift_round_imm (void)
13291 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13292 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
13293 int imm
= inst
.operands
[2].imm
;
13295 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
13298 inst
.operands
[2].present
= 0;
13303 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13304 _("immediate out of range for shift"));
13305 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
13310 do_neon_movl (void)
13312 struct neon_type_el et
= neon_check_type (2, NS_QD
,
13313 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13314 unsigned sizebits
= et
.size
>> 3;
13315 inst
.instruction
|= sizebits
<< 19;
13316 neon_two_same (0, et
.type
== NT_unsigned
, -1);
13322 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13323 struct neon_type_el et
= neon_check_type (2, rs
,
13324 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13325 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13326 neon_two_same (neon_quad (rs
), 1, et
.size
);
13330 do_neon_zip_uzp (void)
13332 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13333 struct neon_type_el et
= neon_check_type (2, rs
,
13334 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13335 if (rs
== NS_DD
&& et
.size
== 32)
13337 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
13338 inst
.instruction
= N_MNEM_vtrn
;
13342 neon_two_same (neon_quad (rs
), 1, et
.size
);
13346 do_neon_sat_abs_neg (void)
13348 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13349 struct neon_type_el et
= neon_check_type (2, rs
,
13350 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13351 neon_two_same (neon_quad (rs
), 1, et
.size
);
13355 do_neon_pair_long (void)
13357 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13358 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
13359 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
13360 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
13361 neon_two_same (neon_quad (rs
), 1, et
.size
);
13365 do_neon_recip_est (void)
13367 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13368 struct neon_type_el et
= neon_check_type (2, rs
,
13369 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
13370 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13371 neon_two_same (neon_quad (rs
), 1, et
.size
);
13377 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13378 struct neon_type_el et
= neon_check_type (2, rs
,
13379 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13380 neon_two_same (neon_quad (rs
), 1, et
.size
);
13386 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13387 struct neon_type_el et
= neon_check_type (2, rs
,
13388 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
13389 neon_two_same (neon_quad (rs
), 1, et
.size
);
13395 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13396 struct neon_type_el et
= neon_check_type (2, rs
,
13397 N_EQK
| N_INT
, N_8
| N_KEY
);
13398 neon_two_same (neon_quad (rs
), 1, et
.size
);
13404 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13405 neon_two_same (neon_quad (rs
), 1, -1);
13409 do_neon_tbl_tbx (void)
13411 unsigned listlenbits
;
13412 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
13414 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
13416 first_error (_("bad list length for table lookup"));
13420 listlenbits
= inst
.operands
[1].imm
- 1;
13421 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13422 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13423 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13424 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13425 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13426 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13427 inst
.instruction
|= listlenbits
<< 8;
13429 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13433 do_neon_ldm_stm (void)
13435 /* P, U and L bits are part of bitmask. */
13436 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
13437 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
13439 if (inst
.operands
[1].issingle
)
13441 do_vfp_nsyn_ldm_stm (is_dbmode
);
13445 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
13446 _("writeback (!) must be used for VLDMDB and VSTMDB"));
13448 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
13449 _("register list must contain at least 1 and at most 16 "
13452 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
13453 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
13454 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13455 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
13457 inst
.instruction
|= offsetbits
;
13459 do_vfp_cond_or_thumb ();
13463 do_neon_ldr_str (void)
13465 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
13467 if (inst
.operands
[0].issingle
)
13470 do_vfp_nsyn_opcode ("flds");
13472 do_vfp_nsyn_opcode ("fsts");
13477 do_vfp_nsyn_opcode ("fldd");
13479 do_vfp_nsyn_opcode ("fstd");
13483 /* "interleave" version also handles non-interleaving register VLD1/VST1
13487 do_neon_ld_st_interleave (void)
13489 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
13490 N_8
| N_16
| N_32
| N_64
);
13491 unsigned alignbits
= 0;
13493 /* The bits in this table go:
13494 0: register stride of one (0) or two (1)
13495 1,2: register list length, minus one (1, 2, 3, 4).
13496 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
13497 We use -1 for invalid entries. */
13498 const int typetable
[] =
13500 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
13501 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
13502 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
13503 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
13507 if (et
.type
== NT_invtype
)
13510 if (inst
.operands
[1].immisalign
)
13511 switch (inst
.operands
[1].imm
>> 8)
13513 case 64: alignbits
= 1; break;
13515 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13516 goto bad_alignment
;
13520 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13521 goto bad_alignment
;
13526 first_error (_("bad alignment"));
13530 inst
.instruction
|= alignbits
<< 4;
13531 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13533 /* Bits [4:6] of the immediate in a list specifier encode register stride
13534 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
13535 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
13536 up the right value for "type" in a table based on this value and the given
13537 list style, then stick it back. */
13538 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
13539 | (((inst
.instruction
>> 8) & 3) << 3);
13541 typebits
= typetable
[idx
];
13543 constraint (typebits
== -1, _("bad list type for instruction"));
13545 inst
.instruction
&= ~0xf00;
13546 inst
.instruction
|= typebits
<< 8;
13549 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
13550 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
13551 otherwise. The variable arguments are a list of pairs of legal (size, align)
13552 values, terminated with -1. */
13555 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
13558 int result
= FAIL
, thissize
, thisalign
;
13560 if (!inst
.operands
[1].immisalign
)
13566 va_start (ap
, do_align
);
13570 thissize
= va_arg (ap
, int);
13571 if (thissize
== -1)
13573 thisalign
= va_arg (ap
, int);
13575 if (size
== thissize
&& align
== thisalign
)
13578 while (result
!= SUCCESS
);
13582 if (result
== SUCCESS
)
13585 first_error (_("unsupported alignment for instruction"));
13591 do_neon_ld_st_lane (void)
13593 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13594 int align_good
, do_align
= 0;
13595 int logsize
= neon_logbits (et
.size
);
13596 int align
= inst
.operands
[1].imm
>> 8;
13597 int n
= (inst
.instruction
>> 8) & 3;
13598 int max_el
= 64 / et
.size
;
13600 if (et
.type
== NT_invtype
)
13603 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
13604 _("bad list length"));
13605 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
13606 _("scalar index out of range"));
13607 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
13609 _("stride of 2 unavailable when element size is 8"));
13613 case 0: /* VLD1 / VST1. */
13614 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
13616 if (align_good
== FAIL
)
13620 unsigned alignbits
= 0;
13623 case 16: alignbits
= 0x1; break;
13624 case 32: alignbits
= 0x3; break;
13627 inst
.instruction
|= alignbits
<< 4;
13631 case 1: /* VLD2 / VST2. */
13632 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
13634 if (align_good
== FAIL
)
13637 inst
.instruction
|= 1 << 4;
13640 case 2: /* VLD3 / VST3. */
13641 constraint (inst
.operands
[1].immisalign
,
13642 _("can't use alignment with this instruction"));
13645 case 3: /* VLD4 / VST4. */
13646 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13647 16, 64, 32, 64, 32, 128, -1);
13648 if (align_good
== FAIL
)
13652 unsigned alignbits
= 0;
13655 case 8: alignbits
= 0x1; break;
13656 case 16: alignbits
= 0x1; break;
13657 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
13660 inst
.instruction
|= alignbits
<< 4;
13667 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
13668 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13669 inst
.instruction
|= 1 << (4 + logsize
);
13671 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
13672 inst
.instruction
|= logsize
<< 10;
13675 /* Encode single n-element structure to all lanes VLD<n> instructions. */
13678 do_neon_ld_dup (void)
13680 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13681 int align_good
, do_align
= 0;
13683 if (et
.type
== NT_invtype
)
13686 switch ((inst
.instruction
>> 8) & 3)
13688 case 0: /* VLD1. */
13689 assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
13690 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13691 &do_align
, 16, 16, 32, 32, -1);
13692 if (align_good
== FAIL
)
13694 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
13697 case 2: inst
.instruction
|= 1 << 5; break;
13698 default: first_error (_("bad list length")); return;
13700 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13703 case 1: /* VLD2. */
13704 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13705 &do_align
, 8, 16, 16, 32, 32, 64, -1);
13706 if (align_good
== FAIL
)
13708 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
13709 _("bad list length"));
13710 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13711 inst
.instruction
|= 1 << 5;
13712 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13715 case 2: /* VLD3. */
13716 constraint (inst
.operands
[1].immisalign
,
13717 _("can't use alignment with this instruction"));
13718 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
13719 _("bad list length"));
13720 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13721 inst
.instruction
|= 1 << 5;
13722 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13725 case 3: /* VLD4. */
13727 int align
= inst
.operands
[1].imm
>> 8;
13728 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13729 16, 64, 32, 64, 32, 128, -1);
13730 if (align_good
== FAIL
)
13732 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
13733 _("bad list length"));
13734 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13735 inst
.instruction
|= 1 << 5;
13736 if (et
.size
== 32 && align
== 128)
13737 inst
.instruction
|= 0x3 << 6;
13739 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13746 inst
.instruction
|= do_align
<< 4;
13749 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
13750 apart from bits [11:4]. */
13753 do_neon_ldx_stx (void)
13755 switch (NEON_LANE (inst
.operands
[0].imm
))
13757 case NEON_INTERLEAVE_LANES
:
13758 inst
.instruction
= NEON_ENC_INTERLV (inst
.instruction
);
13759 do_neon_ld_st_interleave ();
13762 case NEON_ALL_LANES
:
13763 inst
.instruction
= NEON_ENC_DUP (inst
.instruction
);
13768 inst
.instruction
= NEON_ENC_LANE (inst
.instruction
);
13769 do_neon_ld_st_lane ();
13772 /* L bit comes from bit mask. */
13773 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13774 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13775 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13777 if (inst
.operands
[1].postind
)
13779 int postreg
= inst
.operands
[1].imm
& 0xf;
13780 constraint (!inst
.operands
[1].immisreg
,
13781 _("post-index must be a register"));
13782 constraint (postreg
== 0xd || postreg
== 0xf,
13783 _("bad register for post-index"));
13784 inst
.instruction
|= postreg
;
13786 else if (inst
.operands
[1].writeback
)
13788 inst
.instruction
|= 0xd;
13791 inst
.instruction
|= 0xf;
13794 inst
.instruction
|= 0xf9000000;
13796 inst
.instruction
|= 0xf4000000;
13799 /* Overall per-instruction processing. */
13801 /* We need to be able to fix up arbitrary expressions in some statements.
13802 This is so that we can handle symbols that are an arbitrary distance from
13803 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
13804 which returns part of an address in a form which will be valid for
13805 a data instruction. We do this by pushing the expression into a symbol
13806 in the expr_section, and creating a fix for that. */
13809 fix_new_arm (fragS
* frag
,
13824 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
13828 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
13833 /* Mark whether the fix is to a THUMB instruction, or an ARM
13835 new_fix
->tc_fix_data
= thumb_mode
;
13838 /* Create a frg for an instruction requiring relaxation. */
13840 output_relax_insn (void)
13846 /* The size of the instruction is unknown, so tie the debug info to the
13847 start of the instruction. */
13848 dwarf2_emit_insn (0);
13850 switch (inst
.reloc
.exp
.X_op
)
13853 sym
= inst
.reloc
.exp
.X_add_symbol
;
13854 offset
= inst
.reloc
.exp
.X_add_number
;
13858 offset
= inst
.reloc
.exp
.X_add_number
;
13861 sym
= make_expr_symbol (&inst
.reloc
.exp
);
13865 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
13866 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
13867 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
13870 /* Write a 32-bit thumb instruction to buf. */
13872 put_thumb32_insn (char * buf
, unsigned long insn
)
13874 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
13875 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
13879 output_inst (const char * str
)
13885 as_bad ("%s -- `%s'", inst
.error
, str
);
13890 output_relax_insn ();
13893 if (inst
.size
== 0)
13896 to
= frag_more (inst
.size
);
13898 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
13900 assert (inst
.size
== (2 * THUMB_SIZE
));
13901 put_thumb32_insn (to
, inst
.instruction
);
13903 else if (inst
.size
> INSN_SIZE
)
13905 assert (inst
.size
== (2 * INSN_SIZE
));
13906 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
13907 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
13910 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
13912 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
13913 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
13914 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
13917 dwarf2_emit_insn (inst
.size
);
13920 /* Tag values used in struct asm_opcode's tag field. */
13923 OT_unconditional
, /* Instruction cannot be conditionalized.
13924 The ARM condition field is still 0xE. */
13925 OT_unconditionalF
, /* Instruction cannot be conditionalized
13926 and carries 0xF in its ARM condition field. */
13927 OT_csuffix
, /* Instruction takes a conditional suffix. */
13928 OT_csuffixF
, /* Some forms of the instruction take a conditional
13929 suffix, others place 0xF where the condition field
13931 OT_cinfix3
, /* Instruction takes a conditional infix,
13932 beginning at character index 3. (In
13933 unified mode, it becomes a suffix.) */
13934 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
13935 tsts, cmps, cmns, and teqs. */
13936 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
13937 character index 3, even in unified mode. Used for
13938 legacy instructions where suffix and infix forms
13939 may be ambiguous. */
13940 OT_csuf_or_in3
, /* Instruction takes either a conditional
13941 suffix or an infix at character index 3. */
13942 OT_odd_infix_unc
, /* This is the unconditional variant of an
13943 instruction that takes a conditional infix
13944 at an unusual position. In unified mode,
13945 this variant will accept a suffix. */
13946 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
13947 are the conditional variants of instructions that
13948 take conditional infixes in unusual positions.
13949 The infix appears at character index
13950 (tag - OT_odd_infix_0). These are not accepted
13951 in unified mode. */
13954 /* Subroutine of md_assemble, responsible for looking up the primary
13955 opcode from the mnemonic the user wrote. STR points to the
13956 beginning of the mnemonic.
13958 This is not simply a hash table lookup, because of conditional
13959 variants. Most instructions have conditional variants, which are
13960 expressed with a _conditional affix_ to the mnemonic. If we were
13961 to encode each conditional variant as a literal string in the opcode
13962 table, it would have approximately 20,000 entries.
13964 Most mnemonics take this affix as a suffix, and in unified syntax,
13965 'most' is upgraded to 'all'. However, in the divided syntax, some
13966 instructions take the affix as an infix, notably the s-variants of
13967 the arithmetic instructions. Of those instructions, all but six
13968 have the infix appear after the third character of the mnemonic.
13970 Accordingly, the algorithm for looking up primary opcodes given
13973 1. Look up the identifier in the opcode table.
13974 If we find a match, go to step U.
13976 2. Look up the last two characters of the identifier in the
13977 conditions table. If we find a match, look up the first N-2
13978 characters of the identifier in the opcode table. If we
13979 find a match, go to step CE.
13981 3. Look up the fourth and fifth characters of the identifier in
13982 the conditions table. If we find a match, extract those
13983 characters from the identifier, and look up the remaining
13984 characters in the opcode table. If we find a match, go
13989 U. Examine the tag field of the opcode structure, in case this is
13990 one of the six instructions with its conditional infix in an
13991 unusual place. If it is, the tag tells us where to find the
13992 infix; look it up in the conditions table and set inst.cond
13993 accordingly. Otherwise, this is an unconditional instruction.
13994 Again set inst.cond accordingly. Return the opcode structure.
13996 CE. Examine the tag field to make sure this is an instruction that
13997 should receive a conditional suffix. If it is not, fail.
13998 Otherwise, set inst.cond from the suffix we already looked up,
13999 and return the opcode structure.
14001 CM. Examine the tag field to make sure this is an instruction that
14002 should receive a conditional infix after the third character.
14003 If it is not, fail. Otherwise, undo the edits to the current
14004 line of input and proceed as for case CE. */
14006 static const struct asm_opcode
*
14007 opcode_lookup (char **str
)
14011 const struct asm_opcode
*opcode
;
14012 const struct asm_cond
*cond
;
14014 bfd_boolean neon_supported
;
14016 neon_supported
= ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
);
14018 /* Scan up to the end of the mnemonic, which must end in white space,
14019 '.' (in unified mode, or for Neon instructions), or end of string. */
14020 for (base
= end
= *str
; *end
!= '\0'; end
++)
14021 if (*end
== ' ' || ((unified_syntax
|| neon_supported
) && *end
== '.'))
14027 /* Handle a possible width suffix and/or Neon type suffix. */
14032 /* The .w and .n suffixes are only valid if the unified syntax is in
14034 if (unified_syntax
&& end
[1] == 'w')
14036 else if (unified_syntax
&& end
[1] == 'n')
14041 inst
.vectype
.elems
= 0;
14043 *str
= end
+ offset
;
14045 if (end
[offset
] == '.')
14047 /* See if we have a Neon type suffix (possible in either unified or
14048 non-unified ARM syntax mode). */
14049 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
14052 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
14058 /* Look for unaffixed or special-case affixed mnemonic. */
14059 opcode
= hash_find_n (arm_ops_hsh
, base
, end
- base
);
14063 if (opcode
->tag
< OT_odd_infix_0
)
14065 inst
.cond
= COND_ALWAYS
;
14069 if (unified_syntax
)
14070 as_warn (_("conditional infixes are deprecated in unified syntax"));
14071 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
14072 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14075 inst
.cond
= cond
->value
;
14079 /* Cannot have a conditional suffix on a mnemonic of less than two
14081 if (end
- base
< 3)
14084 /* Look for suffixed mnemonic. */
14086 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14087 opcode
= hash_find_n (arm_ops_hsh
, base
, affix
- base
);
14088 if (opcode
&& cond
)
14091 switch (opcode
->tag
)
14093 case OT_cinfix3_legacy
:
14094 /* Ignore conditional suffixes matched on infix only mnemonics. */
14098 case OT_cinfix3_deprecated
:
14099 case OT_odd_infix_unc
:
14100 if (!unified_syntax
)
14102 /* else fall through */
14106 case OT_csuf_or_in3
:
14107 inst
.cond
= cond
->value
;
14110 case OT_unconditional
:
14111 case OT_unconditionalF
:
14114 inst
.cond
= cond
->value
;
14118 /* delayed diagnostic */
14119 inst
.error
= BAD_COND
;
14120 inst
.cond
= COND_ALWAYS
;
14129 /* Cannot have a usual-position infix on a mnemonic of less than
14130 six characters (five would be a suffix). */
14131 if (end
- base
< 6)
14134 /* Look for infixed mnemonic in the usual position. */
14136 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14140 memcpy (save
, affix
, 2);
14141 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
14142 opcode
= hash_find_n (arm_ops_hsh
, base
, (end
- base
) - 2);
14143 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
14144 memcpy (affix
, save
, 2);
14147 && (opcode
->tag
== OT_cinfix3
14148 || opcode
->tag
== OT_cinfix3_deprecated
14149 || opcode
->tag
== OT_csuf_or_in3
14150 || opcode
->tag
== OT_cinfix3_legacy
))
14154 && (opcode
->tag
== OT_cinfix3
14155 || opcode
->tag
== OT_cinfix3_deprecated
))
14156 as_warn (_("conditional infixes are deprecated in unified syntax"));
14158 inst
.cond
= cond
->value
;
14166 md_assemble (char *str
)
14169 const struct asm_opcode
* opcode
;
14171 /* Align the previous label if needed. */
14172 if (last_label_seen
!= NULL
)
14174 symbol_set_frag (last_label_seen
, frag_now
);
14175 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
14176 S_SET_SEGMENT (last_label_seen
, now_seg
);
14179 memset (&inst
, '\0', sizeof (inst
));
14180 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
14182 opcode
= opcode_lookup (&p
);
14185 /* It wasn't an instruction, but it might be a register alias of
14186 the form alias .req reg, or a Neon .dn/.qn directive. */
14187 if (!create_register_alias (str
, p
)
14188 && !create_neon_reg_alias (str
, p
))
14189 as_bad (_("bad instruction `%s'"), str
);
14194 if (opcode
->tag
== OT_cinfix3_deprecated
)
14195 as_warn (_("s suffix on comparison instruction is deprecated"));
14197 /* The value which unconditional instructions should have in place of the
14198 condition field. */
14199 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
14203 arm_feature_set variant
;
14205 variant
= cpu_variant
;
14206 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
14207 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
14208 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
14209 /* Check that this instruction is supported for this CPU. */
14210 if (!opcode
->tvariant
14211 || (thumb_mode
== 1
14212 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
14214 as_bad (_("selected processor does not support `%s'"), str
);
14217 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
14218 && opcode
->tencode
!= do_t_branch
)
14220 as_bad (_("Thumb does not support conditional execution"));
14224 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
) && !inst
.size_req
)
14226 /* Implicit require narrow instructions on Thumb-1. This avoids
14227 relaxation accidentally introducing Thumb-2 instructions. */
14228 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
)
14232 /* Check conditional suffixes. */
14233 if (current_it_mask
)
14236 cond
= current_cc
^ ((current_it_mask
>> 4) & 1) ^ 1;
14237 current_it_mask
<<= 1;
14238 current_it_mask
&= 0x1f;
14239 /* The BKPT instruction is unconditional even in an IT block. */
14241 && cond
!= inst
.cond
&& opcode
->tencode
!= do_t_bkpt
)
14243 as_bad (_("incorrect condition in IT block"));
14247 else if (inst
.cond
!= COND_ALWAYS
&& opcode
->tencode
!= do_t_branch
)
14249 as_bad (_("thumb conditional instruction not in IT block"));
14253 mapping_state (MAP_THUMB
);
14254 inst
.instruction
= opcode
->tvalue
;
14256 if (!parse_operands (p
, opcode
->operands
))
14257 opcode
->tencode ();
14259 /* Clear current_it_mask at the end of an IT block. */
14260 if (current_it_mask
== 0x10)
14261 current_it_mask
= 0;
14263 if (!(inst
.error
|| inst
.relax
))
14265 assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
14266 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
14267 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
14269 as_bad (_("cannot honor width suffix -- `%s'"), str
);
14274 /* Something has gone badly wrong if we try to relax a fixed size
14276 assert (inst
.size_req
== 0 || !inst
.relax
);
14278 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
14279 *opcode
->tvariant
);
14280 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
14281 set those bits when Thumb-2 32-bit instructions are seen. ie.
14282 anything other than bl/blx.
14283 This is overly pessimistic for relaxable instructions. */
14284 if ((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
14286 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
14289 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
14293 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
14294 is_bx
= (opcode
->aencode
== do_bx
);
14296 /* Check that this instruction is supported for this CPU. */
14297 if (!(is_bx
&& fix_v4bx
)
14298 && !(opcode
->avariant
&&
14299 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
14301 as_bad (_("selected processor does not support `%s'"), str
);
14306 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
14310 mapping_state (MAP_ARM
);
14311 inst
.instruction
= opcode
->avalue
;
14312 if (opcode
->tag
== OT_unconditionalF
)
14313 inst
.instruction
|= 0xF << 28;
14315 inst
.instruction
|= inst
.cond
<< 28;
14316 inst
.size
= INSN_SIZE
;
14317 if (!parse_operands (p
, opcode
->operands
))
14318 opcode
->aencode ();
14319 /* Arm mode bx is marked as both v4T and v5 because it's still required
14320 on a hypothetical non-thumb v5 core. */
14322 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
14324 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
14325 *opcode
->avariant
);
14329 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
14336 /* Various frobbings of labels and their addresses. */
14339 arm_start_line_hook (void)
14341 last_label_seen
= NULL
;
14345 arm_frob_label (symbolS
* sym
)
14347 last_label_seen
= sym
;
14349 ARM_SET_THUMB (sym
, thumb_mode
);
14351 #if defined OBJ_COFF || defined OBJ_ELF
14352 ARM_SET_INTERWORK (sym
, support_interwork
);
14355 /* Note - do not allow local symbols (.Lxxx) to be labelled
14356 as Thumb functions. This is because these labels, whilst
14357 they exist inside Thumb code, are not the entry points for
14358 possible ARM->Thumb calls. Also, these labels can be used
14359 as part of a computed goto or switch statement. eg gcc
14360 can generate code that looks like this:
14362 ldr r2, [pc, .Laaa]
14372 The first instruction loads the address of the jump table.
14373 The second instruction converts a table index into a byte offset.
14374 The third instruction gets the jump address out of the table.
14375 The fourth instruction performs the jump.
14377 If the address stored at .Laaa is that of a symbol which has the
14378 Thumb_Func bit set, then the linker will arrange for this address
14379 to have the bottom bit set, which in turn would mean that the
14380 address computation performed by the third instruction would end
14381 up with the bottom bit set. Since the ARM is capable of unaligned
14382 word loads, the instruction would then load the incorrect address
14383 out of the jump table, and chaos would ensue. */
14384 if (label_is_thumb_function_name
14385 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
14386 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
14388 /* When the address of a Thumb function is taken the bottom
14389 bit of that address should be set. This will allow
14390 interworking between Arm and Thumb functions to work
14393 THUMB_SET_FUNC (sym
, 1);
14395 label_is_thumb_function_name
= FALSE
;
14398 dwarf2_emit_label (sym
);
14402 arm_data_in_code (void)
14404 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
14406 *input_line_pointer
= '/';
14407 input_line_pointer
+= 5;
14408 *input_line_pointer
= 0;
14416 arm_canonicalize_symbol_name (char * name
)
14420 if (thumb_mode
&& (len
= strlen (name
)) > 5
14421 && streq (name
+ len
- 5, "/data"))
14422 *(name
+ len
- 5) = 0;
14427 /* Table of all register names defined by default. The user can
14428 define additional names with .req. Note that all register names
14429 should appear in both upper and lowercase variants. Some registers
14430 also have mixed-case names. */
14432 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
14433 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
14434 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
14435 #define REGSET(p,t) \
14436 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
14437 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
14438 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
14439 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
14440 #define REGSETH(p,t) \
14441 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
14442 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
14443 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
14444 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
14445 #define REGSET2(p,t) \
14446 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
14447 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
14448 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
14449 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
14451 static const struct reg_entry reg_names
[] =
14453 /* ARM integer registers. */
14454 REGSET(r
, RN
), REGSET(R
, RN
),
14456 /* ATPCS synonyms. */
14457 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
14458 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
14459 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
14461 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
14462 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
14463 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
14465 /* Well-known aliases. */
14466 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
14467 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
14469 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
14470 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
14472 /* Coprocessor numbers. */
14473 REGSET(p
, CP
), REGSET(P
, CP
),
14475 /* Coprocessor register numbers. The "cr" variants are for backward
14477 REGSET(c
, CN
), REGSET(C
, CN
),
14478 REGSET(cr
, CN
), REGSET(CR
, CN
),
14480 /* FPA registers. */
14481 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
14482 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
14484 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
14485 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
14487 /* VFP SP registers. */
14488 REGSET(s
,VFS
), REGSET(S
,VFS
),
14489 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
14491 /* VFP DP Registers. */
14492 REGSET(d
,VFD
), REGSET(D
,VFD
),
14493 /* Extra Neon DP registers. */
14494 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
14496 /* Neon QP registers. */
14497 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
14499 /* VFP control registers. */
14500 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
14501 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
14502 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
14503 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
14504 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
14505 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
14507 /* Maverick DSP coprocessor registers. */
14508 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
14509 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
14511 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
14512 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
14513 REGDEF(dspsc
,0,DSPSC
),
14515 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
14516 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
14517 REGDEF(DSPSC
,0,DSPSC
),
14519 /* iWMMXt data registers - p0, c0-15. */
14520 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
14522 /* iWMMXt control registers - p1, c0-3. */
14523 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
14524 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
14525 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
14526 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
14528 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
14529 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
14530 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
14531 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
14532 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
14534 /* XScale accumulator registers. */
14535 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
14541 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
14542 within psr_required_here. */
14543 static const struct asm_psr psrs
[] =
14545 /* Backward compatibility notation. Note that "all" is no longer
14546 truly all possible PSR bits. */
14547 {"all", PSR_c
| PSR_f
},
14551 /* Individual flags. */
14556 /* Combinations of flags. */
14557 {"fs", PSR_f
| PSR_s
},
14558 {"fx", PSR_f
| PSR_x
},
14559 {"fc", PSR_f
| PSR_c
},
14560 {"sf", PSR_s
| PSR_f
},
14561 {"sx", PSR_s
| PSR_x
},
14562 {"sc", PSR_s
| PSR_c
},
14563 {"xf", PSR_x
| PSR_f
},
14564 {"xs", PSR_x
| PSR_s
},
14565 {"xc", PSR_x
| PSR_c
},
14566 {"cf", PSR_c
| PSR_f
},
14567 {"cs", PSR_c
| PSR_s
},
14568 {"cx", PSR_c
| PSR_x
},
14569 {"fsx", PSR_f
| PSR_s
| PSR_x
},
14570 {"fsc", PSR_f
| PSR_s
| PSR_c
},
14571 {"fxs", PSR_f
| PSR_x
| PSR_s
},
14572 {"fxc", PSR_f
| PSR_x
| PSR_c
},
14573 {"fcs", PSR_f
| PSR_c
| PSR_s
},
14574 {"fcx", PSR_f
| PSR_c
| PSR_x
},
14575 {"sfx", PSR_s
| PSR_f
| PSR_x
},
14576 {"sfc", PSR_s
| PSR_f
| PSR_c
},
14577 {"sxf", PSR_s
| PSR_x
| PSR_f
},
14578 {"sxc", PSR_s
| PSR_x
| PSR_c
},
14579 {"scf", PSR_s
| PSR_c
| PSR_f
},
14580 {"scx", PSR_s
| PSR_c
| PSR_x
},
14581 {"xfs", PSR_x
| PSR_f
| PSR_s
},
14582 {"xfc", PSR_x
| PSR_f
| PSR_c
},
14583 {"xsf", PSR_x
| PSR_s
| PSR_f
},
14584 {"xsc", PSR_x
| PSR_s
| PSR_c
},
14585 {"xcf", PSR_x
| PSR_c
| PSR_f
},
14586 {"xcs", PSR_x
| PSR_c
| PSR_s
},
14587 {"cfs", PSR_c
| PSR_f
| PSR_s
},
14588 {"cfx", PSR_c
| PSR_f
| PSR_x
},
14589 {"csf", PSR_c
| PSR_s
| PSR_f
},
14590 {"csx", PSR_c
| PSR_s
| PSR_x
},
14591 {"cxf", PSR_c
| PSR_x
| PSR_f
},
14592 {"cxs", PSR_c
| PSR_x
| PSR_s
},
14593 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
14594 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
14595 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
14596 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
14597 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
14598 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
14599 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
14600 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
14601 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
14602 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
14603 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
14604 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
14605 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
14606 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
14607 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
14608 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
14609 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
14610 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
14611 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
14612 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
14613 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
14614 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
14615 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
14616 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
14619 /* Table of V7M psr names. */
14620 static const struct asm_psr v7m_psrs
[] =
14622 {"apsr", 0 }, {"APSR", 0 },
14623 {"iapsr", 1 }, {"IAPSR", 1 },
14624 {"eapsr", 2 }, {"EAPSR", 2 },
14625 {"psr", 3 }, {"PSR", 3 },
14626 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
14627 {"ipsr", 5 }, {"IPSR", 5 },
14628 {"epsr", 6 }, {"EPSR", 6 },
14629 {"iepsr", 7 }, {"IEPSR", 7 },
14630 {"msp", 8 }, {"MSP", 8 },
14631 {"psp", 9 }, {"PSP", 9 },
14632 {"primask", 16}, {"PRIMASK", 16},
14633 {"basepri", 17}, {"BASEPRI", 17},
14634 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
14635 {"faultmask", 19}, {"FAULTMASK", 19},
14636 {"control", 20}, {"CONTROL", 20}
14639 /* Table of all shift-in-operand names. */
14640 static const struct asm_shift_name shift_names
[] =
14642 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
14643 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
14644 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
14645 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
14646 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
14647 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
14650 /* Table of all explicit relocation names. */
14652 static struct reloc_entry reloc_names
[] =
14654 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
14655 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
14656 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
14657 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
14658 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
14659 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
14660 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
14661 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
14662 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
14663 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
14664 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
14668 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
14669 static const struct asm_cond conds
[] =
14673 {"cs", 0x2}, {"hs", 0x2},
14674 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
14688 static struct asm_barrier_opt barrier_opt_names
[] =
14696 /* Table of ARM-format instructions. */
14698 /* Macros for gluing together operand strings. N.B. In all cases
14699 other than OPS0, the trailing OP_stop comes from default
14700 zero-initialization of the unspecified elements of the array. */
14701 #define OPS0() { OP_stop, }
14702 #define OPS1(a) { OP_##a, }
14703 #define OPS2(a,b) { OP_##a,OP_##b, }
14704 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
14705 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
14706 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
14707 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
14709 /* These macros abstract out the exact format of the mnemonic table and
14710 save some repeated characters. */
14712 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
14713 #define TxCE(mnem, op, top, nops, ops, ae, te) \
14714 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
14715 THUMB_VARIANT, do_##ae, do_##te }
14717 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
14718 a T_MNEM_xyz enumerator. */
14719 #define TCE(mnem, aop, top, nops, ops, ae, te) \
14720 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
14721 #define tCE(mnem, aop, top, nops, ops, ae, te) \
14722 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14724 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
14725 infix after the third character. */
14726 #define TxC3(mnem, op, top, nops, ops, ae, te) \
14727 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
14728 THUMB_VARIANT, do_##ae, do_##te }
14729 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
14730 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
14731 THUMB_VARIANT, do_##ae, do_##te }
14732 #define TC3(mnem, aop, top, nops, ops, ae, te) \
14733 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
14734 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
14735 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
14736 #define tC3(mnem, aop, top, nops, ops, ae, te) \
14737 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14738 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
14739 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14741 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
14742 appear in the condition table. */
14743 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
14744 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14745 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
14747 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
14748 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
14749 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
14750 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
14751 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
14752 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
14753 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
14754 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
14755 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
14756 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
14757 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
14758 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
14759 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
14760 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
14761 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
14762 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
14763 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
14764 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
14765 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
14766 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
14768 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
14769 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
14770 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
14771 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
14773 /* Mnemonic that cannot be conditionalized. The ARM condition-code
14774 field is still 0xE. Many of the Thumb variants can be executed
14775 conditionally, so this is checked separately. */
14776 #define TUE(mnem, op, top, nops, ops, ae, te) \
14777 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
14778 THUMB_VARIANT, do_##ae, do_##te }
14780 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
14781 condition code field. */
14782 #define TUF(mnem, op, top, nops, ops, ae, te) \
14783 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
14784 THUMB_VARIANT, do_##ae, do_##te }
14786 /* ARM-only variants of all the above. */
14787 #define CE(mnem, op, nops, ops, ae) \
14788 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14790 #define C3(mnem, op, nops, ops, ae) \
14791 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14793 /* Legacy mnemonics that always have conditional infix after the third
14795 #define CL(mnem, op, nops, ops, ae) \
14796 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14797 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14799 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
14800 #define cCE(mnem, op, nops, ops, ae) \
14801 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14803 /* Legacy coprocessor instructions where conditional infix and conditional
14804 suffix are ambiguous. For consistency this includes all FPA instructions,
14805 not just the potentially ambiguous ones. */
14806 #define cCL(mnem, op, nops, ops, ae) \
14807 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14808 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14810 /* Coprocessor, takes either a suffix or a position-3 infix
14811 (for an FPA corner case). */
14812 #define C3E(mnem, op, nops, ops, ae) \
14813 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
14814 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14816 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
14817 { #m1 #m2 #m3, OPS##nops ops, \
14818 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14819 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14821 #define CM(m1, m2, op, nops, ops, ae) \
14822 xCM_(m1, , m2, op, nops, ops, ae), \
14823 xCM_(m1, eq, m2, op, nops, ops, ae), \
14824 xCM_(m1, ne, m2, op, nops, ops, ae), \
14825 xCM_(m1, cs, m2, op, nops, ops, ae), \
14826 xCM_(m1, hs, m2, op, nops, ops, ae), \
14827 xCM_(m1, cc, m2, op, nops, ops, ae), \
14828 xCM_(m1, ul, m2, op, nops, ops, ae), \
14829 xCM_(m1, lo, m2, op, nops, ops, ae), \
14830 xCM_(m1, mi, m2, op, nops, ops, ae), \
14831 xCM_(m1, pl, m2, op, nops, ops, ae), \
14832 xCM_(m1, vs, m2, op, nops, ops, ae), \
14833 xCM_(m1, vc, m2, op, nops, ops, ae), \
14834 xCM_(m1, hi, m2, op, nops, ops, ae), \
14835 xCM_(m1, ls, m2, op, nops, ops, ae), \
14836 xCM_(m1, ge, m2, op, nops, ops, ae), \
14837 xCM_(m1, lt, m2, op, nops, ops, ae), \
14838 xCM_(m1, gt, m2, op, nops, ops, ae), \
14839 xCM_(m1, le, m2, op, nops, ops, ae), \
14840 xCM_(m1, al, m2, op, nops, ops, ae)
14842 #define UE(mnem, op, nops, ops, ae) \
14843 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14845 #define UF(mnem, op, nops, ops, ae) \
14846 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14848 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
14849 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
14850 use the same encoding function for each. */
14851 #define NUF(mnem, op, nops, ops, enc) \
14852 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
14853 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14855 /* Neon data processing, version which indirects through neon_enc_tab for
14856 the various overloaded versions of opcodes. */
14857 #define nUF(mnem, op, nops, ops, enc) \
14858 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \
14859 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14861 /* Neon insn with conditional suffix for the ARM version, non-overloaded
14863 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
14864 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
14865 THUMB_VARIANT, do_##enc, do_##enc }
14867 #define NCE(mnem, op, nops, ops, enc) \
14868 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14870 #define NCEF(mnem, op, nops, ops, enc) \
14871 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14873 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
14874 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
14875 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \
14876 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14878 #define nCE(mnem, op, nops, ops, enc) \
14879 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14881 #define nCEF(mnem, op, nops, ops, enc) \
14882 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14886 /* Thumb-only, unconditional. */
14887 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
14889 static const struct asm_opcode insns
[] =
14891 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
14892 #define THUMB_VARIANT &arm_ext_v4t
14893 tCE(and, 0000000, and, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14894 tC3(ands
, 0100000, ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14895 tCE(eor
, 0200000, eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14896 tC3(eors
, 0300000, eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14897 tCE(sub
, 0400000, sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14898 tC3(subs
, 0500000, subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14899 tCE(add
, 0800000, add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14900 tC3(adds
, 0900000, adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14901 tCE(adc
, 0a00000
, adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14902 tC3(adcs
, 0b00000, adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14903 tCE(sbc
, 0c00000
, sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14904 tC3(sbcs
, 0d00000
, sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14905 tCE(orr
, 1800000, orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14906 tC3(orrs
, 1900000, orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14907 tCE(bic
, 1c00000
, bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14908 tC3(bics
, 1d00000
, bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14910 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
14911 for setting PSR flag bits. They are obsolete in V6 and do not
14912 have Thumb equivalents. */
14913 tCE(tst
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14914 tC3w(tsts
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14915 CL(tstp
, 110f000
, 2, (RR
, SH
), cmp
),
14916 tCE(cmp
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14917 tC3w(cmps
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14918 CL(cmpp
, 150f000
, 2, (RR
, SH
), cmp
),
14919 tCE(cmn
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14920 tC3w(cmns
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14921 CL(cmnp
, 170f000
, 2, (RR
, SH
), cmp
),
14923 tCE(mov
, 1a00000
, mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14924 tC3(movs
, 1b00000
, movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14925 tCE(mvn
, 1e00000
, mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14926 tC3(mvns
, 1f00000
, mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14928 tCE(ldr
, 4100000, ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14929 tC3(ldrb
, 4500000, ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14930 tCE(str
, 4000000, str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14931 tC3(strb
, 4400000, strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14933 tCE(stm
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14934 tC3(stmia
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14935 tC3(stmea
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14936 tCE(ldm
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14937 tC3(ldmia
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14938 tC3(ldmfd
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14940 TCE(swi
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14941 TCE(svc
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14942 tCE(b
, a000000
, b
, 1, (EXPr
), branch
, t_branch
),
14943 TCE(bl
, b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
14946 tCE(adr
, 28f0000
, adr
, 2, (RR
, EXP
), adr
, t_adr
),
14947 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
14948 tCE(nop
, 1a00000
, nop
, 1, (oI255c
), nop
, t_nop
),
14950 /* Thumb-compatibility pseudo ops. */
14951 tCE(lsl
, 1a00000
, lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14952 tC3(lsls
, 1b00000
, lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14953 tCE(lsr
, 1a00020
, lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14954 tC3(lsrs
, 1b00020
, lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14955 tCE(asr
, 1a00040
, asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14956 tC3(asrs
, 1b00040
, asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14957 tCE(ror
, 1a00060
, ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14958 tC3(rors
, 1b00060
, rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14959 tCE(neg
, 2600000, neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
14960 tC3(negs
, 2700000, negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
14961 tCE(push
, 92d0000
, push
, 1, (REGLST
), push_pop
, t_push_pop
),
14962 tCE(pop
, 8bd0000
, pop
, 1, (REGLST
), push_pop
, t_push_pop
),
14964 /* These may simplify to neg. */
14965 TCE(rsb
, 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14966 TC3(rsbs
, 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14968 #undef THUMB_VARIANT
14969 #define THUMB_VARIANT &arm_ext_v6
14970 TCE(cpy
, 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
14972 /* V1 instructions with no Thumb analogue prior to V6T2. */
14973 #undef THUMB_VARIANT
14974 #define THUMB_VARIANT &arm_ext_v6t2
14975 TCE(teq
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14976 TC3w(teqs
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14977 CL(teqp
, 130f000
, 2, (RR
, SH
), cmp
),
14979 TC3(ldrt
, 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14980 TC3(ldrbt
, 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14981 TC3(strt
, 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14982 TC3(strbt
, 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14984 TC3(stmdb
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14985 TC3(stmfd
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14987 TC3(ldmdb
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14988 TC3(ldmea
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14990 /* V1 instructions with no Thumb analogue at all. */
14991 CE(rsc
, 0e00000
, 3, (RR
, oRR
, SH
), arit
),
14992 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
14994 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
14995 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
14996 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
14997 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
14998 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
14999 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
15000 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
15001 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
15004 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
15005 #undef THUMB_VARIANT
15006 #define THUMB_VARIANT &arm_ext_v4t
15007 tCE(mul
, 0000090, mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
15008 tC3(muls
, 0100090, muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
15010 #undef THUMB_VARIANT
15011 #define THUMB_VARIANT &arm_ext_v6t2
15012 TCE(mla
, 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
15013 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
15015 /* Generic coprocessor instructions. */
15016 TCE(cdp
, e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
15017 TCE(ldc
, c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15018 TC3(ldcl
, c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15019 TCE(stc
, c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15020 TC3(stcl
, c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15021 TCE(mcr
, e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15022 TCE(mrc
, e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15025 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
15026 CE(swp
, 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
15027 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
15030 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
15031 TCE(mrs
, 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
15032 TCE(msr
, 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
15035 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
15036 TCE(smull
, 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15037 CM(smull
,s
, 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15038 TCE(umull
, 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15039 CM(umull
,s
, 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15040 TCE(smlal
, 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15041 CM(smlal
,s
, 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15042 TCE(umlal
, 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15043 CM(umlal
,s
, 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15046 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
15047 #undef THUMB_VARIANT
15048 #define THUMB_VARIANT &arm_ext_v4t
15049 tC3(ldrh
, 01000b0
, ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15050 tC3(strh
, 00000b0
, strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15051 tC3(ldrsh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15052 tC3(ldrsb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15053 tCM(ld
,sh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15054 tCM(ld
,sb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15057 #define ARM_VARIANT &arm_ext_v4t_5
15058 /* ARM Architecture 4T. */
15059 /* Note: bx (and blx) are required on V5, even if the processor does
15060 not support Thumb. */
15061 TCE(bx
, 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
15064 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
15065 #undef THUMB_VARIANT
15066 #define THUMB_VARIANT &arm_ext_v5t
15067 /* Note: blx has 2 variants; the .value coded here is for
15068 BLX(2). Only this variant has conditional execution. */
15069 TCE(blx
, 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
15070 TUE(bkpt
, 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
15072 #undef THUMB_VARIANT
15073 #define THUMB_VARIANT &arm_ext_v6t2
15074 TCE(clz
, 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
15075 TUF(ldc2
, c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15076 TUF(ldc2l
, c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15077 TUF(stc2
, c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15078 TUF(stc2l
, c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15079 TUF(cdp2
, e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
15080 TUF(mcr2
, e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15081 TUF(mrc2
, e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15084 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
15085 TCE(smlabb
, 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15086 TCE(smlatb
, 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15087 TCE(smlabt
, 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15088 TCE(smlatt
, 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15090 TCE(smlawb
, 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15091 TCE(smlawt
, 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15093 TCE(smlalbb
, 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15094 TCE(smlaltb
, 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15095 TCE(smlalbt
, 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15096 TCE(smlaltt
, 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15098 TCE(smulbb
, 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15099 TCE(smultb
, 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15100 TCE(smulbt
, 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15101 TCE(smultt
, 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15103 TCE(smulwb
, 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15104 TCE(smulwt
, 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15106 TCE(qadd
, 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15107 TCE(qdadd
, 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15108 TCE(qsub
, 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15109 TCE(qdsub
, 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15112 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
15113 TUF(pld
, 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
15114 TC3(ldrd
, 00000d0
, e8500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
15115 TC3(strd
, 00000f0
, e8400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
15117 TCE(mcrr
, c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15118 TCE(mrrc
, c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15121 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
15122 TCE(bxj
, 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
15125 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
15126 #undef THUMB_VARIANT
15127 #define THUMB_VARIANT &arm_ext_v6
15128 TUF(cpsie
, 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
15129 TUF(cpsid
, 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
15130 tCE(rev
, 6bf0f30
, rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15131 tCE(rev16
, 6bf0fb0
, rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15132 tCE(revsh
, 6ff0fb0
, revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15133 tCE(sxth
, 6bf0070
, sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15134 tCE(uxth
, 6ff0070
, uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15135 tCE(sxtb
, 6af0070
, sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15136 tCE(uxtb
, 6ef0070
, uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15137 TUF(setend
, 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
15139 #undef THUMB_VARIANT
15140 #define THUMB_VARIANT &arm_ext_v6t2
15141 TCE(ldrex
, 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
15142 TCE(strex
, 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
15143 TUF(mcrr2
, c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15144 TUF(mrrc2
, c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15146 TCE(ssat
, 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
15147 TCE(usat
, 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
15149 /* ARM V6 not included in V7M (eg. integer SIMD). */
15150 #undef THUMB_VARIANT
15151 #define THUMB_VARIANT &arm_ext_v6_notm
15152 TUF(cps
, 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
15153 TCE(pkhbt
, 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
15154 TCE(pkhtb
, 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
15155 TCE(qadd16
, 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15156 TCE(qadd8
, 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15157 TCE(qaddsubx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15158 TCE(qsub16
, 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15159 TCE(qsub8
, 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15160 TCE(qsubaddx
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15161 TCE(sadd16
, 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15162 TCE(sadd8
, 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15163 TCE(saddsubx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15164 TCE(shadd16
, 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15165 TCE(shadd8
, 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15166 TCE(shaddsubx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15167 TCE(shsub16
, 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15168 TCE(shsub8
, 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15169 TCE(shsubaddx
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15170 TCE(ssub16
, 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15171 TCE(ssub8
, 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15172 TCE(ssubaddx
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15173 TCE(uadd16
, 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15174 TCE(uadd8
, 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15175 TCE(uaddsubx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15176 TCE(uhadd16
, 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15177 TCE(uhadd8
, 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15178 TCE(uhaddsubx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15179 TCE(uhsub16
, 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15180 TCE(uhsub8
, 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15181 TCE(uhsubaddx
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15182 TCE(uqadd16
, 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15183 TCE(uqadd8
, 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15184 TCE(uqaddsubx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15185 TCE(uqsub16
, 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15186 TCE(uqsub8
, 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15187 TCE(uqsubaddx
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15188 TCE(usub16
, 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15189 TCE(usub8
, 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15190 TCE(usubaddx
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15191 TUF(rfeia
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
15192 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
15193 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
15194 TUF(rfedb
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
15195 TUF(rfefd
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
15196 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
15197 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
15198 TUF(rfeed
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
15199 TCE(sxtah
, 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15200 TCE(sxtab16
, 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15201 TCE(sxtab
, 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15202 TCE(sxtb16
, 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15203 TCE(uxtah
, 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15204 TCE(uxtab16
, 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15205 TCE(uxtab
, 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15206 TCE(uxtb16
, 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15207 TCE(sel
, 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15208 TCE(smlad
, 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15209 TCE(smladx
, 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15210 TCE(smlald
, 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15211 TCE(smlaldx
, 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15212 TCE(smlsd
, 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15213 TCE(smlsdx
, 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15214 TCE(smlsld
, 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15215 TCE(smlsldx
, 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15216 TCE(smmla
, 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15217 TCE(smmlar
, 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15218 TCE(smmls
, 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15219 TCE(smmlsr
, 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15220 TCE(smmul
, 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15221 TCE(smmulr
, 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15222 TCE(smuad
, 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15223 TCE(smuadx
, 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15224 TCE(smusd
, 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15225 TCE(smusdx
, 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15226 TUF(srsia
, 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
15227 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
15228 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
15229 TUF(srsdb
, 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
15230 TCE(ssat16
, 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
15231 TCE(umaal
, 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
15232 TCE(usad8
, 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15233 TCE(usada8
, 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15234 TCE(usat16
, 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
15237 #define ARM_VARIANT &arm_ext_v6k
15238 #undef THUMB_VARIANT
15239 #define THUMB_VARIANT &arm_ext_v6k
15240 tCE(yield
, 320f001
, yield
, 0, (), noargs
, t_hint
),
15241 tCE(wfe
, 320f002
, wfe
, 0, (), noargs
, t_hint
),
15242 tCE(wfi
, 320f003
, wfi
, 0, (), noargs
, t_hint
),
15243 tCE(sev
, 320f004
, sev
, 0, (), noargs
, t_hint
),
15245 #undef THUMB_VARIANT
15246 #define THUMB_VARIANT &arm_ext_v6_notm
15247 TCE(ldrexd
, 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
15248 TCE(strexd
, 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
15250 #undef THUMB_VARIANT
15251 #define THUMB_VARIANT &arm_ext_v6t2
15252 TCE(ldrexb
, 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
15253 TCE(ldrexh
, 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
15254 TCE(strexb
, 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
15255 TCE(strexh
, 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
15256 TUF(clrex
, 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
15259 #define ARM_VARIANT &arm_ext_v6z
15260 TCE(smc
, 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
15263 #define ARM_VARIANT &arm_ext_v6t2
15264 TCE(bfc
, 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
15265 TCE(bfi
, 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
15266 TCE(sbfx
, 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
15267 TCE(ubfx
, 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
15269 TCE(mls
, 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
15270 TCE(movw
, 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
15271 TCE(movt
, 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
15272 TCE(rbit
, 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
15274 TC3(ldrht
, 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15275 TC3(ldrsht
, 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15276 TC3(ldrsbt
, 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15277 TC3(strht
, 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15279 UT(cbnz
, b900
, 2, (RR
, EXP
), t_cbz
),
15280 UT(cbz
, b100
, 2, (RR
, EXP
), t_cbz
),
15281 /* ARM does not really have an IT instruction, so always allow it. */
15283 #define ARM_VARIANT &arm_ext_v1
15284 TUE(it
, 0, bf08
, 1, (COND
), it
, t_it
),
15285 TUE(itt
, 0, bf0c
, 1, (COND
), it
, t_it
),
15286 TUE(ite
, 0, bf04
, 1, (COND
), it
, t_it
),
15287 TUE(ittt
, 0, bf0e
, 1, (COND
), it
, t_it
),
15288 TUE(itet
, 0, bf06
, 1, (COND
), it
, t_it
),
15289 TUE(itte
, 0, bf0a
, 1, (COND
), it
, t_it
),
15290 TUE(itee
, 0, bf02
, 1, (COND
), it
, t_it
),
15291 TUE(itttt
, 0, bf0f
, 1, (COND
), it
, t_it
),
15292 TUE(itett
, 0, bf07
, 1, (COND
), it
, t_it
),
15293 TUE(ittet
, 0, bf0b
, 1, (COND
), it
, t_it
),
15294 TUE(iteet
, 0, bf03
, 1, (COND
), it
, t_it
),
15295 TUE(ittte
, 0, bf0d
, 1, (COND
), it
, t_it
),
15296 TUE(itete
, 0, bf05
, 1, (COND
), it
, t_it
),
15297 TUE(ittee
, 0, bf09
, 1, (COND
), it
, t_it
),
15298 TUE(iteee
, 0, bf01
, 1, (COND
), it
, t_it
),
15300 /* Thumb2 only instructions. */
15302 #define ARM_VARIANT NULL
15304 TCE(addw
, 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
15305 TCE(subw
, 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
15306 TCE(tbb
, 0, e8d0f000
, 1, (TB
), 0, t_tb
),
15307 TCE(tbh
, 0, e8d0f010
, 1, (TB
), 0, t_tb
),
15309 /* Thumb-2 hardware division instructions (R and M profiles only). */
15310 #undef THUMB_VARIANT
15311 #define THUMB_VARIANT &arm_ext_div
15312 TCE(sdiv
, 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
15313 TCE(udiv
, 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
15315 /* ARM V7 instructions. */
15317 #define ARM_VARIANT &arm_ext_v7
15318 #undef THUMB_VARIANT
15319 #define THUMB_VARIANT &arm_ext_v7
15320 TUF(pli
, 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
15321 TCE(dbg
, 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
15322 TUF(dmb
, 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
15323 TUF(dsb
, 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
15324 TUF(isb
, 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
15327 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
15328 cCE(wfs
, e200110
, 1, (RR
), rd
),
15329 cCE(rfs
, e300110
, 1, (RR
), rd
),
15330 cCE(wfc
, e400110
, 1, (RR
), rd
),
15331 cCE(rfc
, e500110
, 1, (RR
), rd
),
15333 cCL(ldfs
, c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15334 cCL(ldfd
, c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15335 cCL(ldfe
, c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15336 cCL(ldfp
, c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15338 cCL(stfs
, c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15339 cCL(stfd
, c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15340 cCL(stfe
, c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15341 cCL(stfp
, c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15343 cCL(mvfs
, e008100
, 2, (RF
, RF_IF
), rd_rm
),
15344 cCL(mvfsp
, e008120
, 2, (RF
, RF_IF
), rd_rm
),
15345 cCL(mvfsm
, e008140
, 2, (RF
, RF_IF
), rd_rm
),
15346 cCL(mvfsz
, e008160
, 2, (RF
, RF_IF
), rd_rm
),
15347 cCL(mvfd
, e008180
, 2, (RF
, RF_IF
), rd_rm
),
15348 cCL(mvfdp
, e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
15349 cCL(mvfdm
, e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
15350 cCL(mvfdz
, e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
15351 cCL(mvfe
, e088100
, 2, (RF
, RF_IF
), rd_rm
),
15352 cCL(mvfep
, e088120
, 2, (RF
, RF_IF
), rd_rm
),
15353 cCL(mvfem
, e088140
, 2, (RF
, RF_IF
), rd_rm
),
15354 cCL(mvfez
, e088160
, 2, (RF
, RF_IF
), rd_rm
),
15356 cCL(mnfs
, e108100
, 2, (RF
, RF_IF
), rd_rm
),
15357 cCL(mnfsp
, e108120
, 2, (RF
, RF_IF
), rd_rm
),
15358 cCL(mnfsm
, e108140
, 2, (RF
, RF_IF
), rd_rm
),
15359 cCL(mnfsz
, e108160
, 2, (RF
, RF_IF
), rd_rm
),
15360 cCL(mnfd
, e108180
, 2, (RF
, RF_IF
), rd_rm
),
15361 cCL(mnfdp
, e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
15362 cCL(mnfdm
, e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
15363 cCL(mnfdz
, e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
15364 cCL(mnfe
, e188100
, 2, (RF
, RF_IF
), rd_rm
),
15365 cCL(mnfep
, e188120
, 2, (RF
, RF_IF
), rd_rm
),
15366 cCL(mnfem
, e188140
, 2, (RF
, RF_IF
), rd_rm
),
15367 cCL(mnfez
, e188160
, 2, (RF
, RF_IF
), rd_rm
),
15369 cCL(abss
, e208100
, 2, (RF
, RF_IF
), rd_rm
),
15370 cCL(abssp
, e208120
, 2, (RF
, RF_IF
), rd_rm
),
15371 cCL(abssm
, e208140
, 2, (RF
, RF_IF
), rd_rm
),
15372 cCL(abssz
, e208160
, 2, (RF
, RF_IF
), rd_rm
),
15373 cCL(absd
, e208180
, 2, (RF
, RF_IF
), rd_rm
),
15374 cCL(absdp
, e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
15375 cCL(absdm
, e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
15376 cCL(absdz
, e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
15377 cCL(abse
, e288100
, 2, (RF
, RF_IF
), rd_rm
),
15378 cCL(absep
, e288120
, 2, (RF
, RF_IF
), rd_rm
),
15379 cCL(absem
, e288140
, 2, (RF
, RF_IF
), rd_rm
),
15380 cCL(absez
, e288160
, 2, (RF
, RF_IF
), rd_rm
),
15382 cCL(rnds
, e308100
, 2, (RF
, RF_IF
), rd_rm
),
15383 cCL(rndsp
, e308120
, 2, (RF
, RF_IF
), rd_rm
),
15384 cCL(rndsm
, e308140
, 2, (RF
, RF_IF
), rd_rm
),
15385 cCL(rndsz
, e308160
, 2, (RF
, RF_IF
), rd_rm
),
15386 cCL(rndd
, e308180
, 2, (RF
, RF_IF
), rd_rm
),
15387 cCL(rnddp
, e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
15388 cCL(rnddm
, e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
15389 cCL(rnddz
, e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
15390 cCL(rnde
, e388100
, 2, (RF
, RF_IF
), rd_rm
),
15391 cCL(rndep
, e388120
, 2, (RF
, RF_IF
), rd_rm
),
15392 cCL(rndem
, e388140
, 2, (RF
, RF_IF
), rd_rm
),
15393 cCL(rndez
, e388160
, 2, (RF
, RF_IF
), rd_rm
),
15395 cCL(sqts
, e408100
, 2, (RF
, RF_IF
), rd_rm
),
15396 cCL(sqtsp
, e408120
, 2, (RF
, RF_IF
), rd_rm
),
15397 cCL(sqtsm
, e408140
, 2, (RF
, RF_IF
), rd_rm
),
15398 cCL(sqtsz
, e408160
, 2, (RF
, RF_IF
), rd_rm
),
15399 cCL(sqtd
, e408180
, 2, (RF
, RF_IF
), rd_rm
),
15400 cCL(sqtdp
, e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
15401 cCL(sqtdm
, e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
15402 cCL(sqtdz
, e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
15403 cCL(sqte
, e488100
, 2, (RF
, RF_IF
), rd_rm
),
15404 cCL(sqtep
, e488120
, 2, (RF
, RF_IF
), rd_rm
),
15405 cCL(sqtem
, e488140
, 2, (RF
, RF_IF
), rd_rm
),
15406 cCL(sqtez
, e488160
, 2, (RF
, RF_IF
), rd_rm
),
15408 cCL(logs
, e508100
, 2, (RF
, RF_IF
), rd_rm
),
15409 cCL(logsp
, e508120
, 2, (RF
, RF_IF
), rd_rm
),
15410 cCL(logsm
, e508140
, 2, (RF
, RF_IF
), rd_rm
),
15411 cCL(logsz
, e508160
, 2, (RF
, RF_IF
), rd_rm
),
15412 cCL(logd
, e508180
, 2, (RF
, RF_IF
), rd_rm
),
15413 cCL(logdp
, e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
15414 cCL(logdm
, e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
15415 cCL(logdz
, e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
15416 cCL(loge
, e588100
, 2, (RF
, RF_IF
), rd_rm
),
15417 cCL(logep
, e588120
, 2, (RF
, RF_IF
), rd_rm
),
15418 cCL(logem
, e588140
, 2, (RF
, RF_IF
), rd_rm
),
15419 cCL(logez
, e588160
, 2, (RF
, RF_IF
), rd_rm
),
15421 cCL(lgns
, e608100
, 2, (RF
, RF_IF
), rd_rm
),
15422 cCL(lgnsp
, e608120
, 2, (RF
, RF_IF
), rd_rm
),
15423 cCL(lgnsm
, e608140
, 2, (RF
, RF_IF
), rd_rm
),
15424 cCL(lgnsz
, e608160
, 2, (RF
, RF_IF
), rd_rm
),
15425 cCL(lgnd
, e608180
, 2, (RF
, RF_IF
), rd_rm
),
15426 cCL(lgndp
, e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
15427 cCL(lgndm
, e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
15428 cCL(lgndz
, e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
15429 cCL(lgne
, e688100
, 2, (RF
, RF_IF
), rd_rm
),
15430 cCL(lgnep
, e688120
, 2, (RF
, RF_IF
), rd_rm
),
15431 cCL(lgnem
, e688140
, 2, (RF
, RF_IF
), rd_rm
),
15432 cCL(lgnez
, e688160
, 2, (RF
, RF_IF
), rd_rm
),
15434 cCL(exps
, e708100
, 2, (RF
, RF_IF
), rd_rm
),
15435 cCL(expsp
, e708120
, 2, (RF
, RF_IF
), rd_rm
),
15436 cCL(expsm
, e708140
, 2, (RF
, RF_IF
), rd_rm
),
15437 cCL(expsz
, e708160
, 2, (RF
, RF_IF
), rd_rm
),
15438 cCL(expd
, e708180
, 2, (RF
, RF_IF
), rd_rm
),
15439 cCL(expdp
, e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
15440 cCL(expdm
, e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
15441 cCL(expdz
, e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
15442 cCL(expe
, e788100
, 2, (RF
, RF_IF
), rd_rm
),
15443 cCL(expep
, e788120
, 2, (RF
, RF_IF
), rd_rm
),
15444 cCL(expem
, e788140
, 2, (RF
, RF_IF
), rd_rm
),
15445 cCL(expdz
, e788160
, 2, (RF
, RF_IF
), rd_rm
),
15447 cCL(sins
, e808100
, 2, (RF
, RF_IF
), rd_rm
),
15448 cCL(sinsp
, e808120
, 2, (RF
, RF_IF
), rd_rm
),
15449 cCL(sinsm
, e808140
, 2, (RF
, RF_IF
), rd_rm
),
15450 cCL(sinsz
, e808160
, 2, (RF
, RF_IF
), rd_rm
),
15451 cCL(sind
, e808180
, 2, (RF
, RF_IF
), rd_rm
),
15452 cCL(sindp
, e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
15453 cCL(sindm
, e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
15454 cCL(sindz
, e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
15455 cCL(sine
, e888100
, 2, (RF
, RF_IF
), rd_rm
),
15456 cCL(sinep
, e888120
, 2, (RF
, RF_IF
), rd_rm
),
15457 cCL(sinem
, e888140
, 2, (RF
, RF_IF
), rd_rm
),
15458 cCL(sinez
, e888160
, 2, (RF
, RF_IF
), rd_rm
),
15460 cCL(coss
, e908100
, 2, (RF
, RF_IF
), rd_rm
),
15461 cCL(cossp
, e908120
, 2, (RF
, RF_IF
), rd_rm
),
15462 cCL(cossm
, e908140
, 2, (RF
, RF_IF
), rd_rm
),
15463 cCL(cossz
, e908160
, 2, (RF
, RF_IF
), rd_rm
),
15464 cCL(cosd
, e908180
, 2, (RF
, RF_IF
), rd_rm
),
15465 cCL(cosdp
, e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
15466 cCL(cosdm
, e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
15467 cCL(cosdz
, e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
15468 cCL(cose
, e988100
, 2, (RF
, RF_IF
), rd_rm
),
15469 cCL(cosep
, e988120
, 2, (RF
, RF_IF
), rd_rm
),
15470 cCL(cosem
, e988140
, 2, (RF
, RF_IF
), rd_rm
),
15471 cCL(cosez
, e988160
, 2, (RF
, RF_IF
), rd_rm
),
15473 cCL(tans
, ea08100
, 2, (RF
, RF_IF
), rd_rm
),
15474 cCL(tansp
, ea08120
, 2, (RF
, RF_IF
), rd_rm
),
15475 cCL(tansm
, ea08140
, 2, (RF
, RF_IF
), rd_rm
),
15476 cCL(tansz
, ea08160
, 2, (RF
, RF_IF
), rd_rm
),
15477 cCL(tand
, ea08180
, 2, (RF
, RF_IF
), rd_rm
),
15478 cCL(tandp
, ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
15479 cCL(tandm
, ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
15480 cCL(tandz
, ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
15481 cCL(tane
, ea88100
, 2, (RF
, RF_IF
), rd_rm
),
15482 cCL(tanep
, ea88120
, 2, (RF
, RF_IF
), rd_rm
),
15483 cCL(tanem
, ea88140
, 2, (RF
, RF_IF
), rd_rm
),
15484 cCL(tanez
, ea88160
, 2, (RF
, RF_IF
), rd_rm
),
15486 cCL(asns
, eb08100
, 2, (RF
, RF_IF
), rd_rm
),
15487 cCL(asnsp
, eb08120
, 2, (RF
, RF_IF
), rd_rm
),
15488 cCL(asnsm
, eb08140
, 2, (RF
, RF_IF
), rd_rm
),
15489 cCL(asnsz
, eb08160
, 2, (RF
, RF_IF
), rd_rm
),
15490 cCL(asnd
, eb08180
, 2, (RF
, RF_IF
), rd_rm
),
15491 cCL(asndp
, eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
15492 cCL(asndm
, eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
15493 cCL(asndz
, eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
15494 cCL(asne
, eb88100
, 2, (RF
, RF_IF
), rd_rm
),
15495 cCL(asnep
, eb88120
, 2, (RF
, RF_IF
), rd_rm
),
15496 cCL(asnem
, eb88140
, 2, (RF
, RF_IF
), rd_rm
),
15497 cCL(asnez
, eb88160
, 2, (RF
, RF_IF
), rd_rm
),
15499 cCL(acss
, ec08100
, 2, (RF
, RF_IF
), rd_rm
),
15500 cCL(acssp
, ec08120
, 2, (RF
, RF_IF
), rd_rm
),
15501 cCL(acssm
, ec08140
, 2, (RF
, RF_IF
), rd_rm
),
15502 cCL(acssz
, ec08160
, 2, (RF
, RF_IF
), rd_rm
),
15503 cCL(acsd
, ec08180
, 2, (RF
, RF_IF
), rd_rm
),
15504 cCL(acsdp
, ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
15505 cCL(acsdm
, ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
15506 cCL(acsdz
, ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
15507 cCL(acse
, ec88100
, 2, (RF
, RF_IF
), rd_rm
),
15508 cCL(acsep
, ec88120
, 2, (RF
, RF_IF
), rd_rm
),
15509 cCL(acsem
, ec88140
, 2, (RF
, RF_IF
), rd_rm
),
15510 cCL(acsez
, ec88160
, 2, (RF
, RF_IF
), rd_rm
),
15512 cCL(atns
, ed08100
, 2, (RF
, RF_IF
), rd_rm
),
15513 cCL(atnsp
, ed08120
, 2, (RF
, RF_IF
), rd_rm
),
15514 cCL(atnsm
, ed08140
, 2, (RF
, RF_IF
), rd_rm
),
15515 cCL(atnsz
, ed08160
, 2, (RF
, RF_IF
), rd_rm
),
15516 cCL(atnd
, ed08180
, 2, (RF
, RF_IF
), rd_rm
),
15517 cCL(atndp
, ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
15518 cCL(atndm
, ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
15519 cCL(atndz
, ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
15520 cCL(atne
, ed88100
, 2, (RF
, RF_IF
), rd_rm
),
15521 cCL(atnep
, ed88120
, 2, (RF
, RF_IF
), rd_rm
),
15522 cCL(atnem
, ed88140
, 2, (RF
, RF_IF
), rd_rm
),
15523 cCL(atnez
, ed88160
, 2, (RF
, RF_IF
), rd_rm
),
15525 cCL(urds
, ee08100
, 2, (RF
, RF_IF
), rd_rm
),
15526 cCL(urdsp
, ee08120
, 2, (RF
, RF_IF
), rd_rm
),
15527 cCL(urdsm
, ee08140
, 2, (RF
, RF_IF
), rd_rm
),
15528 cCL(urdsz
, ee08160
, 2, (RF
, RF_IF
), rd_rm
),
15529 cCL(urdd
, ee08180
, 2, (RF
, RF_IF
), rd_rm
),
15530 cCL(urddp
, ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
15531 cCL(urddm
, ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
15532 cCL(urddz
, ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
15533 cCL(urde
, ee88100
, 2, (RF
, RF_IF
), rd_rm
),
15534 cCL(urdep
, ee88120
, 2, (RF
, RF_IF
), rd_rm
),
15535 cCL(urdem
, ee88140
, 2, (RF
, RF_IF
), rd_rm
),
15536 cCL(urdez
, ee88160
, 2, (RF
, RF_IF
), rd_rm
),
15538 cCL(nrms
, ef08100
, 2, (RF
, RF_IF
), rd_rm
),
15539 cCL(nrmsp
, ef08120
, 2, (RF
, RF_IF
), rd_rm
),
15540 cCL(nrmsm
, ef08140
, 2, (RF
, RF_IF
), rd_rm
),
15541 cCL(nrmsz
, ef08160
, 2, (RF
, RF_IF
), rd_rm
),
15542 cCL(nrmd
, ef08180
, 2, (RF
, RF_IF
), rd_rm
),
15543 cCL(nrmdp
, ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
15544 cCL(nrmdm
, ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
15545 cCL(nrmdz
, ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
15546 cCL(nrme
, ef88100
, 2, (RF
, RF_IF
), rd_rm
),
15547 cCL(nrmep
, ef88120
, 2, (RF
, RF_IF
), rd_rm
),
15548 cCL(nrmem
, ef88140
, 2, (RF
, RF_IF
), rd_rm
),
15549 cCL(nrmez
, ef88160
, 2, (RF
, RF_IF
), rd_rm
),
15551 cCL(adfs
, e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15552 cCL(adfsp
, e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15553 cCL(adfsm
, e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15554 cCL(adfsz
, e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15555 cCL(adfd
, e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15556 cCL(adfdp
, e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15557 cCL(adfdm
, e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15558 cCL(adfdz
, e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15559 cCL(adfe
, e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15560 cCL(adfep
, e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15561 cCL(adfem
, e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15562 cCL(adfez
, e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15564 cCL(sufs
, e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15565 cCL(sufsp
, e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15566 cCL(sufsm
, e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15567 cCL(sufsz
, e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15568 cCL(sufd
, e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15569 cCL(sufdp
, e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15570 cCL(sufdm
, e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15571 cCL(sufdz
, e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15572 cCL(sufe
, e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15573 cCL(sufep
, e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15574 cCL(sufem
, e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15575 cCL(sufez
, e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15577 cCL(rsfs
, e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15578 cCL(rsfsp
, e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15579 cCL(rsfsm
, e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15580 cCL(rsfsz
, e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15581 cCL(rsfd
, e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15582 cCL(rsfdp
, e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15583 cCL(rsfdm
, e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15584 cCL(rsfdz
, e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15585 cCL(rsfe
, e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15586 cCL(rsfep
, e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15587 cCL(rsfem
, e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15588 cCL(rsfez
, e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15590 cCL(mufs
, e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15591 cCL(mufsp
, e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15592 cCL(mufsm
, e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15593 cCL(mufsz
, e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15594 cCL(mufd
, e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15595 cCL(mufdp
, e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15596 cCL(mufdm
, e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15597 cCL(mufdz
, e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15598 cCL(mufe
, e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15599 cCL(mufep
, e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15600 cCL(mufem
, e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15601 cCL(mufez
, e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15603 cCL(dvfs
, e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15604 cCL(dvfsp
, e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15605 cCL(dvfsm
, e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15606 cCL(dvfsz
, e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15607 cCL(dvfd
, e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15608 cCL(dvfdp
, e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15609 cCL(dvfdm
, e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15610 cCL(dvfdz
, e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15611 cCL(dvfe
, e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15612 cCL(dvfep
, e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15613 cCL(dvfem
, e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15614 cCL(dvfez
, e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15616 cCL(rdfs
, e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15617 cCL(rdfsp
, e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15618 cCL(rdfsm
, e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15619 cCL(rdfsz
, e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15620 cCL(rdfd
, e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15621 cCL(rdfdp
, e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15622 cCL(rdfdm
, e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15623 cCL(rdfdz
, e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15624 cCL(rdfe
, e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15625 cCL(rdfep
, e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15626 cCL(rdfem
, e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15627 cCL(rdfez
, e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15629 cCL(pows
, e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15630 cCL(powsp
, e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15631 cCL(powsm
, e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15632 cCL(powsz
, e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15633 cCL(powd
, e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15634 cCL(powdp
, e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15635 cCL(powdm
, e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15636 cCL(powdz
, e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15637 cCL(powe
, e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15638 cCL(powep
, e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15639 cCL(powem
, e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15640 cCL(powez
, e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15642 cCL(rpws
, e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15643 cCL(rpwsp
, e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15644 cCL(rpwsm
, e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15645 cCL(rpwsz
, e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15646 cCL(rpwd
, e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15647 cCL(rpwdp
, e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15648 cCL(rpwdm
, e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15649 cCL(rpwdz
, e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15650 cCL(rpwe
, e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15651 cCL(rpwep
, e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15652 cCL(rpwem
, e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15653 cCL(rpwez
, e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15655 cCL(rmfs
, e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15656 cCL(rmfsp
, e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15657 cCL(rmfsm
, e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15658 cCL(rmfsz
, e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15659 cCL(rmfd
, e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15660 cCL(rmfdp
, e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15661 cCL(rmfdm
, e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15662 cCL(rmfdz
, e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15663 cCL(rmfe
, e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15664 cCL(rmfep
, e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15665 cCL(rmfem
, e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15666 cCL(rmfez
, e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15668 cCL(fmls
, e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15669 cCL(fmlsp
, e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15670 cCL(fmlsm
, e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15671 cCL(fmlsz
, e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15672 cCL(fmld
, e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15673 cCL(fmldp
, e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15674 cCL(fmldm
, e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15675 cCL(fmldz
, e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15676 cCL(fmle
, e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15677 cCL(fmlep
, e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15678 cCL(fmlem
, e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15679 cCL(fmlez
, e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15681 cCL(fdvs
, ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15682 cCL(fdvsp
, ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15683 cCL(fdvsm
, ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15684 cCL(fdvsz
, ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15685 cCL(fdvd
, ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15686 cCL(fdvdp
, ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15687 cCL(fdvdm
, ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15688 cCL(fdvdz
, ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15689 cCL(fdve
, ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15690 cCL(fdvep
, ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15691 cCL(fdvem
, ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15692 cCL(fdvez
, ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15694 cCL(frds
, eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15695 cCL(frdsp
, eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15696 cCL(frdsm
, eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15697 cCL(frdsz
, eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15698 cCL(frdd
, eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15699 cCL(frddp
, eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15700 cCL(frddm
, eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15701 cCL(frddz
, eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15702 cCL(frde
, eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15703 cCL(frdep
, eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15704 cCL(frdem
, eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15705 cCL(frdez
, eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15707 cCL(pols
, ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15708 cCL(polsp
, ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15709 cCL(polsm
, ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15710 cCL(polsz
, ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15711 cCL(pold
, ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15712 cCL(poldp
, ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15713 cCL(poldm
, ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15714 cCL(poldz
, ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15715 cCL(pole
, ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15716 cCL(polep
, ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15717 cCL(polem
, ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15718 cCL(polez
, ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15720 cCE(cmf
, e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15721 C3E(cmfe
, ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15722 cCE(cnf
, eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15723 C3E(cnfe
, ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15725 cCL(flts
, e000110
, 2, (RF
, RR
), rn_rd
),
15726 cCL(fltsp
, e000130
, 2, (RF
, RR
), rn_rd
),
15727 cCL(fltsm
, e000150
, 2, (RF
, RR
), rn_rd
),
15728 cCL(fltsz
, e000170
, 2, (RF
, RR
), rn_rd
),
15729 cCL(fltd
, e000190
, 2, (RF
, RR
), rn_rd
),
15730 cCL(fltdp
, e0001b0
, 2, (RF
, RR
), rn_rd
),
15731 cCL(fltdm
, e0001d0
, 2, (RF
, RR
), rn_rd
),
15732 cCL(fltdz
, e0001f0
, 2, (RF
, RR
), rn_rd
),
15733 cCL(flte
, e080110
, 2, (RF
, RR
), rn_rd
),
15734 cCL(fltep
, e080130
, 2, (RF
, RR
), rn_rd
),
15735 cCL(fltem
, e080150
, 2, (RF
, RR
), rn_rd
),
15736 cCL(fltez
, e080170
, 2, (RF
, RR
), rn_rd
),
15738 /* The implementation of the FIX instruction is broken on some
15739 assemblers, in that it accepts a precision specifier as well as a
15740 rounding specifier, despite the fact that this is meaningless.
15741 To be more compatible, we accept it as well, though of course it
15742 does not set any bits. */
15743 cCE(fix
, e100110
, 2, (RR
, RF
), rd_rm
),
15744 cCL(fixp
, e100130
, 2, (RR
, RF
), rd_rm
),
15745 cCL(fixm
, e100150
, 2, (RR
, RF
), rd_rm
),
15746 cCL(fixz
, e100170
, 2, (RR
, RF
), rd_rm
),
15747 cCL(fixsp
, e100130
, 2, (RR
, RF
), rd_rm
),
15748 cCL(fixsm
, e100150
, 2, (RR
, RF
), rd_rm
),
15749 cCL(fixsz
, e100170
, 2, (RR
, RF
), rd_rm
),
15750 cCL(fixdp
, e100130
, 2, (RR
, RF
), rd_rm
),
15751 cCL(fixdm
, e100150
, 2, (RR
, RF
), rd_rm
),
15752 cCL(fixdz
, e100170
, 2, (RR
, RF
), rd_rm
),
15753 cCL(fixep
, e100130
, 2, (RR
, RF
), rd_rm
),
15754 cCL(fixem
, e100150
, 2, (RR
, RF
), rd_rm
),
15755 cCL(fixez
, e100170
, 2, (RR
, RF
), rd_rm
),
15757 /* Instructions that were new with the real FPA, call them V2. */
15759 #define ARM_VARIANT &fpu_fpa_ext_v2
15760 cCE(lfm
, c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15761 cCL(lfmfd
, c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15762 cCL(lfmea
, d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15763 cCE(sfm
, c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15764 cCL(sfmfd
, d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15765 cCL(sfmea
, c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15768 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
15769 /* Moves and type conversions. */
15770 cCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15771 cCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
15772 cCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
15773 cCE(fmstat
, ef1fa10
, 0, (), noargs
),
15774 cCE(fsitos
, eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15775 cCE(fuitos
, eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15776 cCE(ftosis
, ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15777 cCE(ftosizs
, ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15778 cCE(ftouis
, ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15779 cCE(ftouizs
, ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15780 cCE(fmrx
, ef00a10
, 2, (RR
, RVC
), rd_rn
),
15781 cCE(fmxr
, ee00a10
, 2, (RVC
, RR
), rn_rd
),
15783 /* Memory operations. */
15784 cCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15785 cCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15786 cCE(fldmias
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15787 cCE(fldmfds
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15788 cCE(fldmdbs
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15789 cCE(fldmeas
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15790 cCE(fldmiax
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15791 cCE(fldmfdx
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15792 cCE(fldmdbx
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15793 cCE(fldmeax
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15794 cCE(fstmias
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15795 cCE(fstmeas
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15796 cCE(fstmdbs
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15797 cCE(fstmfds
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15798 cCE(fstmiax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15799 cCE(fstmeax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15800 cCE(fstmdbx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15801 cCE(fstmfdx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15803 /* Monadic operations. */
15804 cCE(fabss
, eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15805 cCE(fnegs
, eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15806 cCE(fsqrts
, eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15808 /* Dyadic operations. */
15809 cCE(fadds
, e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15810 cCE(fsubs
, e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15811 cCE(fmuls
, e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15812 cCE(fdivs
, e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15813 cCE(fmacs
, e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15814 cCE(fmscs
, e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15815 cCE(fnmuls
, e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15816 cCE(fnmacs
, e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15817 cCE(fnmscs
, e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15820 cCE(fcmps
, eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15821 cCE(fcmpzs
, eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
15822 cCE(fcmpes
, eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15823 cCE(fcmpezs
, eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
15826 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
15827 /* Moves and type conversions. */
15828 cCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15829 cCE(fcvtds
, eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15830 cCE(fcvtsd
, eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15831 cCE(fmdhr
, e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15832 cCE(fmdlr
, e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15833 cCE(fmrdh
, e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15834 cCE(fmrdl
, e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15835 cCE(fsitod
, eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15836 cCE(fuitod
, eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15837 cCE(ftosid
, ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15838 cCE(ftosizd
, ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15839 cCE(ftouid
, ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15840 cCE(ftouizd
, ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15842 /* Memory operations. */
15843 cCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15844 cCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15845 cCE(fldmiad
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15846 cCE(fldmfdd
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15847 cCE(fldmdbd
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15848 cCE(fldmead
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15849 cCE(fstmiad
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15850 cCE(fstmead
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15851 cCE(fstmdbd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15852 cCE(fstmfdd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15854 /* Monadic operations. */
15855 cCE(fabsd
, eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15856 cCE(fnegd
, eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15857 cCE(fsqrtd
, eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15859 /* Dyadic operations. */
15860 cCE(faddd
, e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15861 cCE(fsubd
, e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15862 cCE(fmuld
, e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15863 cCE(fdivd
, e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15864 cCE(fmacd
, e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15865 cCE(fmscd
, e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15866 cCE(fnmuld
, e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15867 cCE(fnmacd
, e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15868 cCE(fnmscd
, e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15871 cCE(fcmpd
, eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15872 cCE(fcmpzd
, eb50b40
, 1, (RVD
), vfp_dp_rd
),
15873 cCE(fcmped
, eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15874 cCE(fcmpezd
, eb50bc0
, 1, (RVD
), vfp_dp_rd
),
15877 #define ARM_VARIANT &fpu_vfp_ext_v2
15878 cCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
15879 cCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
15880 cCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
15881 cCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
15883 /* Instructions which may belong to either the Neon or VFP instruction sets.
15884 Individual encoder functions perform additional architecture checks. */
15886 #define ARM_VARIANT &fpu_vfp_ext_v1xd
15887 #undef THUMB_VARIANT
15888 #define THUMB_VARIANT &fpu_vfp_ext_v1xd
15889 /* These mnemonics are unique to VFP. */
15890 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
15891 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
15892 nCE(vnmul
, vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15893 nCE(vnmla
, vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15894 nCE(vnmls
, vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15895 nCE(vcmp
, vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15896 nCE(vcmpe
, vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15897 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
15898 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
15899 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
15901 /* Mnemonics shared by Neon and VFP. */
15902 nCEF(vmul
, vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
15903 nCEF(vmla
, vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15904 nCEF(vmls
, vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15906 nCEF(vadd
, vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15907 nCEF(vsub
, vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15909 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15910 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15912 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15913 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15914 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15915 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15916 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15917 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15918 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15919 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15921 nCEF(vcvt
, vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
15923 /* NOTE: All VMOV encoding is special-cased! */
15924 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
15925 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
15927 #undef THUMB_VARIANT
15928 #define THUMB_VARIANT &fpu_neon_ext_v1
15930 #define ARM_VARIANT &fpu_neon_ext_v1
15931 /* Data processing with three registers of the same length. */
15932 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
15933 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
15934 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
15935 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15936 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15937 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15938 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15939 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15940 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15941 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
15942 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15943 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15944 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15945 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15946 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
15947 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
15948 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
15949 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
15950 /* If not immediate, fall back to neon_dyadic_i64_su.
15951 shl_imm should accept I8 I16 I32 I64,
15952 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
15953 nUF(vshl
, vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
15954 nUF(vshlq
, vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
15955 nUF(vqshl
, vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
15956 nUF(vqshlq
, vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
15957 /* Logic ops, types optional & ignored. */
15958 nUF(vand
, vand
, 2, (RNDQ
, NILO
), neon_logic
),
15959 nUF(vandq
, vand
, 2, (RNQ
, NILO
), neon_logic
),
15960 nUF(vbic
, vbic
, 2, (RNDQ
, NILO
), neon_logic
),
15961 nUF(vbicq
, vbic
, 2, (RNQ
, NILO
), neon_logic
),
15962 nUF(vorr
, vorr
, 2, (RNDQ
, NILO
), neon_logic
),
15963 nUF(vorrq
, vorr
, 2, (RNQ
, NILO
), neon_logic
),
15964 nUF(vorn
, vorn
, 2, (RNDQ
, NILO
), neon_logic
),
15965 nUF(vornq
, vorn
, 2, (RNQ
, NILO
), neon_logic
),
15966 nUF(veor
, veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
15967 nUF(veorq
, veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
15968 /* Bitfield ops, untyped. */
15969 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15970 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15971 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15972 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15973 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15974 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15975 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
15976 nUF(vabd
, vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15977 nUF(vabdq
, vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15978 nUF(vmax
, vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15979 nUF(vmaxq
, vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15980 nUF(vmin
, vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15981 nUF(vminq
, vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15982 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
15983 back to neon_dyadic_if_su. */
15984 nUF(vcge
, vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
15985 nUF(vcgeq
, vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
15986 nUF(vcgt
, vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
15987 nUF(vcgtq
, vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
15988 nUF(vclt
, vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
15989 nUF(vcltq
, vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
15990 nUF(vcle
, vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
15991 nUF(vcleq
, vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
15992 /* Comparison. Type I8 I16 I32 F32. */
15993 nUF(vceq
, vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
15994 nUF(vceqq
, vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
15995 /* As above, D registers only. */
15996 nUF(vpmax
, vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
15997 nUF(vpmin
, vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
15998 /* Int and float variants, signedness unimportant. */
15999 nUF(vmlaq
, vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
16000 nUF(vmlsq
, vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
16001 nUF(vpadd
, vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
16002 /* Add/sub take types I8 I16 I32 I64 F32. */
16003 nUF(vaddq
, vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
16004 nUF(vsubq
, vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
16005 /* vtst takes sizes 8, 16, 32. */
16006 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
16007 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
16008 /* VMUL takes I8 I16 I32 F32 P8. */
16009 nUF(vmulq
, vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
16010 /* VQD{R}MULH takes S16 S32. */
16011 nUF(vqdmulh
, vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
16012 nUF(vqdmulhq
, vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
16013 nUF(vqrdmulh
, vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
16014 nUF(vqrdmulhq
, vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
16015 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
16016 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
16017 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
16018 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
16019 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
16020 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
16021 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
16022 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
16023 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
16024 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
16025 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
16026 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
16028 /* Two address, int/float. Types S8 S16 S32 F32. */
16029 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
16030 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
16032 /* Data processing with two registers and a shift amount. */
16033 /* Right shifts, and variants with rounding.
16034 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
16035 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
16036 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
16037 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
16038 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
16039 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
16040 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
16041 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
16042 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
16043 /* Shift and insert. Sizes accepted 8 16 32 64. */
16044 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
16045 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
16046 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
16047 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
16048 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
16049 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
16050 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
16051 /* Right shift immediate, saturating & narrowing, with rounding variants.
16052 Types accepted S16 S32 S64 U16 U32 U64. */
16053 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
16054 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
16055 /* As above, unsigned. Types accepted S16 S32 S64. */
16056 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
16057 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
16058 /* Right shift narrowing. Types accepted I16 I32 I64. */
16059 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
16060 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
16061 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
16062 nUF(vshll
, vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
16063 /* CVT with optional immediate for fixed-point variant. */
16064 nUF(vcvtq
, vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
16066 nUF(vmvn
, vmvn
, 2, (RNDQ
, RNDQ_IMVNb
), neon_mvn
),
16067 nUF(vmvnq
, vmvn
, 2, (RNQ
, RNDQ_IMVNb
), neon_mvn
),
16069 /* Data processing, three registers of different lengths. */
16070 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
16071 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
16072 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16073 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16074 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16075 /* If not scalar, fall back to neon_dyadic_long.
16076 Vector types as above, scalar types S16 S32 U16 U32. */
16077 nUF(vmlal
, vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
16078 nUF(vmlsl
, vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
16079 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
16080 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
16081 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
16082 /* Dyadic, narrowing insns. Types I16 I32 I64. */
16083 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16084 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16085 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16086 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16087 /* Saturating doubling multiplies. Types S16 S32. */
16088 nUF(vqdmlal
, vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16089 nUF(vqdmlsl
, vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16090 nUF(vqdmull
, vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16091 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
16092 S16 S32 U16 U32. */
16093 nUF(vmull
, vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
16095 /* Extract. Size 8. */
16096 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
16097 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
16099 /* Two registers, miscellaneous. */
16100 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
16101 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
16102 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
16103 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
16104 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
16105 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
16106 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
16107 /* Vector replicate. Sizes 8 16 32. */
16108 nCE(vdup
, vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
16109 nCE(vdupq
, vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
16110 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
16111 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
16112 /* VMOVN. Types I16 I32 I64. */
16113 nUF(vmovn
, vmovn
, 2, (RND
, RNQ
), neon_movn
),
16114 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
16115 nUF(vqmovn
, vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
16116 /* VQMOVUN. Types S16 S32 S64. */
16117 nUF(vqmovun
, vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
16118 /* VZIP / VUZP. Sizes 8 16 32. */
16119 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
16120 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
16121 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
16122 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
16123 /* VQABS / VQNEG. Types S8 S16 S32. */
16124 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
16125 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
16126 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
16127 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
16128 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
16129 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
16130 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
16131 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
16132 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
16133 /* Reciprocal estimates. Types U32 F32. */
16134 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
16135 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
16136 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
16137 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
16138 /* VCLS. Types S8 S16 S32. */
16139 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
16140 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
16141 /* VCLZ. Types I8 I16 I32. */
16142 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
16143 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
16144 /* VCNT. Size 8. */
16145 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
16146 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
16147 /* Two address, untyped. */
16148 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
16149 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
16150 /* VTRN. Sizes 8 16 32. */
16151 nUF(vtrn
, vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
16152 nUF(vtrnq
, vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
16154 /* Table lookup. Size 8. */
16155 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
16156 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
16158 #undef THUMB_VARIANT
16159 #define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
16161 #define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
16162 /* Neon element/structure load/store. */
16163 nUF(vld1
, vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16164 nUF(vst1
, vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16165 nUF(vld2
, vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16166 nUF(vst2
, vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16167 nUF(vld3
, vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16168 nUF(vst3
, vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16169 nUF(vld4
, vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16170 nUF(vst4
, vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16172 #undef THUMB_VARIANT
16173 #define THUMB_VARIANT &fpu_vfp_ext_v3
16175 #define ARM_VARIANT &fpu_vfp_ext_v3
16176 cCE(fconsts
, eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
16177 cCE(fconstd
, eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
16178 cCE(fshtos
, eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16179 cCE(fshtod
, eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16180 cCE(fsltos
, eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16181 cCE(fsltod
, eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16182 cCE(fuhtos
, ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16183 cCE(fuhtod
, ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16184 cCE(fultos
, ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16185 cCE(fultod
, ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16186 cCE(ftoshs
, ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16187 cCE(ftoshd
, ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16188 cCE(ftosls
, ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16189 cCE(ftosld
, ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16190 cCE(ftouhs
, ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16191 cCE(ftouhd
, ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16192 cCE(ftouls
, ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16193 cCE(ftould
, ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16195 #undef THUMB_VARIANT
16197 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
16198 cCE(mia
, e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16199 cCE(miaph
, e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16200 cCE(miabb
, e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16201 cCE(miabt
, e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16202 cCE(miatb
, e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16203 cCE(miatt
, e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16204 cCE(mar
, c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
16205 cCE(mra
, c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
16208 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
16209 cCE(tandcb
, e13f130
, 1, (RR
), iwmmxt_tandorc
),
16210 cCE(tandch
, e53f130
, 1, (RR
), iwmmxt_tandorc
),
16211 cCE(tandcw
, e93f130
, 1, (RR
), iwmmxt_tandorc
),
16212 cCE(tbcstb
, e400010
, 2, (RIWR
, RR
), rn_rd
),
16213 cCE(tbcsth
, e400050
, 2, (RIWR
, RR
), rn_rd
),
16214 cCE(tbcstw
, e400090
, 2, (RIWR
, RR
), rn_rd
),
16215 cCE(textrcb
, e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
16216 cCE(textrch
, e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
16217 cCE(textrcw
, e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
16218 cCE(textrmub
, e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16219 cCE(textrmuh
, e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16220 cCE(textrmuw
, e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16221 cCE(textrmsb
, e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16222 cCE(textrmsh
, e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16223 cCE(textrmsw
, e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16224 cCE(tinsrb
, e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16225 cCE(tinsrh
, e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16226 cCE(tinsrw
, e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16227 cCE(tmcr
, e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
16228 cCE(tmcrr
, c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
16229 cCE(tmia
, e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16230 cCE(tmiaph
, e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16231 cCE(tmiabb
, e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16232 cCE(tmiabt
, e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16233 cCE(tmiatb
, e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16234 cCE(tmiatt
, e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16235 cCE(tmovmskb
, e100030
, 2, (RR
, RIWR
), rd_rn
),
16236 cCE(tmovmskh
, e500030
, 2, (RR
, RIWR
), rd_rn
),
16237 cCE(tmovmskw
, e900030
, 2, (RR
, RIWR
), rd_rn
),
16238 cCE(tmrc
, e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
16239 cCE(tmrrc
, c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
16240 cCE(torcb
, e13f150
, 1, (RR
), iwmmxt_tandorc
),
16241 cCE(torch
, e53f150
, 1, (RR
), iwmmxt_tandorc
),
16242 cCE(torcw
, e93f150
, 1, (RR
), iwmmxt_tandorc
),
16243 cCE(waccb
, e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16244 cCE(wacch
, e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16245 cCE(waccw
, e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16246 cCE(waddbss
, e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16247 cCE(waddb
, e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16248 cCE(waddbus
, e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16249 cCE(waddhss
, e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16250 cCE(waddh
, e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16251 cCE(waddhus
, e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16252 cCE(waddwss
, eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16253 cCE(waddw
, e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16254 cCE(waddwus
, e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16255 cCE(waligni
, e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
16256 cCE(walignr0
, e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16257 cCE(walignr1
, e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16258 cCE(walignr2
, ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16259 cCE(walignr3
, eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16260 cCE(wand
, e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16261 cCE(wandn
, e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16262 cCE(wavg2b
, e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16263 cCE(wavg2br
, e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16264 cCE(wavg2h
, ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16265 cCE(wavg2hr
, ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16266 cCE(wcmpeqb
, e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16267 cCE(wcmpeqh
, e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16268 cCE(wcmpeqw
, e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16269 cCE(wcmpgtub
, e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16270 cCE(wcmpgtuh
, e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16271 cCE(wcmpgtuw
, e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16272 cCE(wcmpgtsb
, e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16273 cCE(wcmpgtsh
, e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16274 cCE(wcmpgtsw
, eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16275 cCE(wldrb
, c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16276 cCE(wldrh
, c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16277 cCE(wldrw
, c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
16278 cCE(wldrd
, c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
16279 cCE(wmacs
, e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16280 cCE(wmacsz
, e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16281 cCE(wmacu
, e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16282 cCE(wmacuz
, e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16283 cCE(wmadds
, ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16284 cCE(wmaddu
, e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16285 cCE(wmaxsb
, e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16286 cCE(wmaxsh
, e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16287 cCE(wmaxsw
, ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16288 cCE(wmaxub
, e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16289 cCE(wmaxuh
, e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16290 cCE(wmaxuw
, e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16291 cCE(wminsb
, e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16292 cCE(wminsh
, e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16293 cCE(wminsw
, eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16294 cCE(wminub
, e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16295 cCE(wminuh
, e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16296 cCE(wminuw
, e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16297 cCE(wmov
, e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
16298 cCE(wmulsm
, e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16299 cCE(wmulsl
, e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16300 cCE(wmulum
, e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16301 cCE(wmulul
, e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16302 cCE(wor
, e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16303 cCE(wpackhss
, e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16304 cCE(wpackhus
, e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16305 cCE(wpackwss
, eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16306 cCE(wpackwus
, e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16307 cCE(wpackdss
, ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16308 cCE(wpackdus
, ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16309 cCE(wrorh
, e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16310 cCE(wrorhg
, e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16311 cCE(wrorw
, eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16312 cCE(wrorwg
, eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16313 cCE(wrord
, ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16314 cCE(wrordg
, ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16315 cCE(wsadb
, e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16316 cCE(wsadbz
, e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16317 cCE(wsadh
, e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16318 cCE(wsadhz
, e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16319 cCE(wshufh
, e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
16320 cCE(wsllh
, e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16321 cCE(wsllhg
, e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16322 cCE(wsllw
, e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16323 cCE(wsllwg
, e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16324 cCE(wslld
, ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16325 cCE(wslldg
, ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16326 cCE(wsrah
, e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16327 cCE(wsrahg
, e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16328 cCE(wsraw
, e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16329 cCE(wsrawg
, e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16330 cCE(wsrad
, ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16331 cCE(wsradg
, ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16332 cCE(wsrlh
, e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16333 cCE(wsrlhg
, e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16334 cCE(wsrlw
, ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16335 cCE(wsrlwg
, ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16336 cCE(wsrld
, ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16337 cCE(wsrldg
, ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16338 cCE(wstrb
, c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16339 cCE(wstrh
, c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16340 cCE(wstrw
, c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
16341 cCE(wstrd
, c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
16342 cCE(wsubbss
, e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16343 cCE(wsubb
, e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16344 cCE(wsubbus
, e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16345 cCE(wsubhss
, e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16346 cCE(wsubh
, e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16347 cCE(wsubhus
, e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16348 cCE(wsubwss
, eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16349 cCE(wsubw
, e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16350 cCE(wsubwus
, e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16351 cCE(wunpckehub
,e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16352 cCE(wunpckehuh
,e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16353 cCE(wunpckehuw
,e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16354 cCE(wunpckehsb
,e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16355 cCE(wunpckehsh
,e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16356 cCE(wunpckehsw
,ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16357 cCE(wunpckihb
, e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16358 cCE(wunpckihh
, e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16359 cCE(wunpckihw
, e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16360 cCE(wunpckelub
,e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16361 cCE(wunpckeluh
,e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16362 cCE(wunpckeluw
,e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16363 cCE(wunpckelsb
,e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16364 cCE(wunpckelsh
,e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16365 cCE(wunpckelsw
,ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16366 cCE(wunpckilb
, e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16367 cCE(wunpckilh
, e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16368 cCE(wunpckilw
, e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16369 cCE(wxor
, e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16370 cCE(wzero
, e300000
, 1, (RIWR
), iwmmxt_wzero
),
16373 #define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
16374 cCE(torvscb
, e13f190
, 1, (RR
), iwmmxt_tandorc
),
16375 cCE(torvsch
, e53f190
, 1, (RR
), iwmmxt_tandorc
),
16376 cCE(torvscw
, e93f190
, 1, (RR
), iwmmxt_tandorc
),
16377 cCE(wabsb
, e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16378 cCE(wabsh
, e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16379 cCE(wabsw
, ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16380 cCE(wabsdiffb
, e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16381 cCE(wabsdiffh
, e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16382 cCE(wabsdiffw
, e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16383 cCE(waddbhusl
, e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16384 cCE(waddbhusm
, e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16385 cCE(waddhc
, e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16386 cCE(waddwc
, ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16387 cCE(waddsubhx
, ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16388 cCE(wavg4
, e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16389 cCE(wavg4r
, e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16390 cCE(wmaddsn
, ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16391 cCE(wmaddsx
, eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16392 cCE(wmaddun
, ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16393 cCE(wmaddux
, e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16394 cCE(wmerge
, e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
16395 cCE(wmiabb
, e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16396 cCE(wmiabt
, e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16397 cCE(wmiatb
, e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16398 cCE(wmiatt
, e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16399 cCE(wmiabbn
, e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16400 cCE(wmiabtn
, e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16401 cCE(wmiatbn
, e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16402 cCE(wmiattn
, e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16403 cCE(wmiawbb
, e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16404 cCE(wmiawbt
, e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16405 cCE(wmiawtb
, ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16406 cCE(wmiawtt
, eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16407 cCE(wmiawbbn
, ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16408 cCE(wmiawbtn
, ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16409 cCE(wmiawtbn
, ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16410 cCE(wmiawttn
, ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16411 cCE(wmulsmr
, ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16412 cCE(wmulumr
, ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16413 cCE(wmulwumr
, ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16414 cCE(wmulwsmr
, ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16415 cCE(wmulwum
, ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16416 cCE(wmulwsm
, ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16417 cCE(wmulwl
, eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16418 cCE(wqmiabb
, e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16419 cCE(wqmiabt
, e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16420 cCE(wqmiatb
, ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16421 cCE(wqmiatt
, eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16422 cCE(wqmiabbn
, ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16423 cCE(wqmiabtn
, ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16424 cCE(wqmiatbn
, ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16425 cCE(wqmiattn
, ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16426 cCE(wqmulm
, e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16427 cCE(wqmulmr
, e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16428 cCE(wqmulwm
, ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16429 cCE(wqmulwmr
, ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16430 cCE(wsubaddhx
, ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16433 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
16434 cCE(cfldrs
, c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
16435 cCE(cfldrd
, c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
16436 cCE(cfldr32
, c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
16437 cCE(cfldr64
, c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
16438 cCE(cfstrs
, c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
16439 cCE(cfstrd
, c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
16440 cCE(cfstr32
, c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
16441 cCE(cfstr64
, c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
16442 cCE(cfmvsr
, e000450
, 2, (RMF
, RR
), rn_rd
),
16443 cCE(cfmvrs
, e100450
, 2, (RR
, RMF
), rd_rn
),
16444 cCE(cfmvdlr
, e000410
, 2, (RMD
, RR
), rn_rd
),
16445 cCE(cfmvrdl
, e100410
, 2, (RR
, RMD
), rd_rn
),
16446 cCE(cfmvdhr
, e000430
, 2, (RMD
, RR
), rn_rd
),
16447 cCE(cfmvrdh
, e100430
, 2, (RR
, RMD
), rd_rn
),
16448 cCE(cfmv64lr
, e000510
, 2, (RMDX
, RR
), rn_rd
),
16449 cCE(cfmvr64l
, e100510
, 2, (RR
, RMDX
), rd_rn
),
16450 cCE(cfmv64hr
, e000530
, 2, (RMDX
, RR
), rn_rd
),
16451 cCE(cfmvr64h
, e100530
, 2, (RR
, RMDX
), rd_rn
),
16452 cCE(cfmval32
, e200440
, 2, (RMAX
, RMFX
), rd_rn
),
16453 cCE(cfmv32al
, e100440
, 2, (RMFX
, RMAX
), rd_rn
),
16454 cCE(cfmvam32
, e200460
, 2, (RMAX
, RMFX
), rd_rn
),
16455 cCE(cfmv32am
, e100460
, 2, (RMFX
, RMAX
), rd_rn
),
16456 cCE(cfmvah32
, e200480
, 2, (RMAX
, RMFX
), rd_rn
),
16457 cCE(cfmv32ah
, e100480
, 2, (RMFX
, RMAX
), rd_rn
),
16458 cCE(cfmva32
, e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
16459 cCE(cfmv32a
, e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
16460 cCE(cfmva64
, e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
16461 cCE(cfmv64a
, e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
16462 cCE(cfmvsc32
, e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
16463 cCE(cfmv32sc
, e1004e0
, 2, (RMDX
, RMDS
), rd
),
16464 cCE(cfcpys
, e000400
, 2, (RMF
, RMF
), rd_rn
),
16465 cCE(cfcpyd
, e000420
, 2, (RMD
, RMD
), rd_rn
),
16466 cCE(cfcvtsd
, e000460
, 2, (RMD
, RMF
), rd_rn
),
16467 cCE(cfcvtds
, e000440
, 2, (RMF
, RMD
), rd_rn
),
16468 cCE(cfcvt32s
, e000480
, 2, (RMF
, RMFX
), rd_rn
),
16469 cCE(cfcvt32d
, e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
16470 cCE(cfcvt64s
, e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
16471 cCE(cfcvt64d
, e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
16472 cCE(cfcvts32
, e100580
, 2, (RMFX
, RMF
), rd_rn
),
16473 cCE(cfcvtd32
, e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
16474 cCE(cftruncs32
,e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
16475 cCE(cftruncd32
,e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
16476 cCE(cfrshl32
, e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
16477 cCE(cfrshl64
, e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
16478 cCE(cfsh32
, e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
16479 cCE(cfsh64
, e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
16480 cCE(cfcmps
, e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
16481 cCE(cfcmpd
, e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
16482 cCE(cfcmp32
, e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
16483 cCE(cfcmp64
, e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
16484 cCE(cfabss
, e300400
, 2, (RMF
, RMF
), rd_rn
),
16485 cCE(cfabsd
, e300420
, 2, (RMD
, RMD
), rd_rn
),
16486 cCE(cfnegs
, e300440
, 2, (RMF
, RMF
), rd_rn
),
16487 cCE(cfnegd
, e300460
, 2, (RMD
, RMD
), rd_rn
),
16488 cCE(cfadds
, e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16489 cCE(cfaddd
, e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16490 cCE(cfsubs
, e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16491 cCE(cfsubd
, e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16492 cCE(cfmuls
, e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16493 cCE(cfmuld
, e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16494 cCE(cfabs32
, e300500
, 2, (RMFX
, RMFX
), rd_rn
),
16495 cCE(cfabs64
, e300520
, 2, (RMDX
, RMDX
), rd_rn
),
16496 cCE(cfneg32
, e300540
, 2, (RMFX
, RMFX
), rd_rn
),
16497 cCE(cfneg64
, e300560
, 2, (RMDX
, RMDX
), rd_rn
),
16498 cCE(cfadd32
, e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16499 cCE(cfadd64
, e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16500 cCE(cfsub32
, e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16501 cCE(cfsub64
, e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16502 cCE(cfmul32
, e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16503 cCE(cfmul64
, e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16504 cCE(cfmac32
, e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16505 cCE(cfmsc32
, e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16506 cCE(cfmadd32
, e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
16507 cCE(cfmsub32
, e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
16508 cCE(cfmadda32
, e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
16509 cCE(cfmsuba32
, e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
16512 #undef THUMB_VARIANT
16539 /* MD interface: bits in the object file. */
16541 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
16542 for use in the a.out file, and stores them in the array pointed to by buf.
16543 This knows about the endian-ness of the target machine and does
16544 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
16545 2 (short) and 4 (long) Floating numbers are put out as a series of
16546 LITTLENUMS (shorts, here at least). */
16549 md_number_to_chars (char * buf
, valueT val
, int n
)
16551 if (target_big_endian
)
16552 number_to_chars_bigendian (buf
, val
, n
);
16554 number_to_chars_littleendian (buf
, val
, n
);
16558 md_chars_to_number (char * buf
, int n
)
16561 unsigned char * where
= (unsigned char *) buf
;
16563 if (target_big_endian
)
16568 result
|= (*where
++ & 255);
16576 result
|= (where
[n
] & 255);
16583 /* MD interface: Sections. */
16585 /* Estimate the size of a frag before relaxing. Assume everything fits in
16589 md_estimate_size_before_relax (fragS
* fragp
,
16590 segT segtype ATTRIBUTE_UNUSED
)
16596 /* Convert a machine dependent frag. */
16599 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
16601 unsigned long insn
;
16602 unsigned long old_op
;
16610 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16612 old_op
= bfd_get_16(abfd
, buf
);
16613 if (fragp
->fr_symbol
)
16615 exp
.X_op
= O_symbol
;
16616 exp
.X_add_symbol
= fragp
->fr_symbol
;
16620 exp
.X_op
= O_constant
;
16622 exp
.X_add_number
= fragp
->fr_offset
;
16623 opcode
= fragp
->fr_subtype
;
16626 case T_MNEM_ldr_pc
:
16627 case T_MNEM_ldr_pc2
:
16628 case T_MNEM_ldr_sp
:
16629 case T_MNEM_str_sp
:
16636 if (fragp
->fr_var
== 4)
16638 insn
= THUMB_OP32 (opcode
);
16639 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
16641 insn
|= (old_op
& 0x700) << 4;
16645 insn
|= (old_op
& 7) << 12;
16646 insn
|= (old_op
& 0x38) << 13;
16648 insn
|= 0x00000c00;
16649 put_thumb32_insn (buf
, insn
);
16650 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
16654 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
16656 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
16659 if (fragp
->fr_var
== 4)
16661 insn
= THUMB_OP32 (opcode
);
16662 insn
|= (old_op
& 0xf0) << 4;
16663 put_thumb32_insn (buf
, insn
);
16664 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
16668 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16669 exp
.X_add_number
-= 4;
16677 if (fragp
->fr_var
== 4)
16679 int r0off
= (opcode
== T_MNEM_mov
16680 || opcode
== T_MNEM_movs
) ? 0 : 8;
16681 insn
= THUMB_OP32 (opcode
);
16682 insn
= (insn
& 0xe1ffffff) | 0x10000000;
16683 insn
|= (old_op
& 0x700) << r0off
;
16684 put_thumb32_insn (buf
, insn
);
16685 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16689 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
16694 if (fragp
->fr_var
== 4)
16696 insn
= THUMB_OP32(opcode
);
16697 put_thumb32_insn (buf
, insn
);
16698 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
16701 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
16705 if (fragp
->fr_var
== 4)
16707 insn
= THUMB_OP32(opcode
);
16708 insn
|= (old_op
& 0xf00) << 14;
16709 put_thumb32_insn (buf
, insn
);
16710 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
16713 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
16716 case T_MNEM_add_sp
:
16717 case T_MNEM_add_pc
:
16718 case T_MNEM_inc_sp
:
16719 case T_MNEM_dec_sp
:
16720 if (fragp
->fr_var
== 4)
16722 /* ??? Choose between add and addw. */
16723 insn
= THUMB_OP32 (opcode
);
16724 insn
|= (old_op
& 0xf0) << 4;
16725 put_thumb32_insn (buf
, insn
);
16726 if (opcode
== T_MNEM_add_pc
)
16727 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
16729 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16732 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16740 if (fragp
->fr_var
== 4)
16742 insn
= THUMB_OP32 (opcode
);
16743 insn
|= (old_op
& 0xf0) << 4;
16744 insn
|= (old_op
& 0xf) << 16;
16745 put_thumb32_insn (buf
, insn
);
16746 if (insn
& (1 << 20))
16747 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16749 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16752 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16758 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
16760 fixp
->fx_file
= fragp
->fr_file
;
16761 fixp
->fx_line
= fragp
->fr_line
;
16762 fragp
->fr_fix
+= fragp
->fr_var
;
16765 /* Return the size of a relaxable immediate operand instruction.
16766 SHIFT and SIZE specify the form of the allowable immediate. */
16768 relax_immediate (fragS
*fragp
, int size
, int shift
)
16774 /* ??? Should be able to do better than this. */
16775 if (fragp
->fr_symbol
)
16778 low
= (1 << shift
) - 1;
16779 mask
= (1 << (shift
+ size
)) - (1 << shift
);
16780 offset
= fragp
->fr_offset
;
16781 /* Force misaligned offsets to 32-bit variant. */
16784 if (offset
& ~mask
)
16789 /* Get the address of a symbol during relaxation. */
16791 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
16797 sym
= fragp
->fr_symbol
;
16798 sym_frag
= symbol_get_frag (sym
);
16799 know (S_GET_SEGMENT (sym
) != absolute_section
16800 || sym_frag
== &zero_address_frag
);
16801 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
16803 /* If frag has yet to be reached on this pass, assume it will
16804 move by STRETCH just as we did. If this is not so, it will
16805 be because some frag between grows, and that will force
16809 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
16813 /* Adjust stretch for any alignment frag. Note that if have
16814 been expanding the earlier code, the symbol may be
16815 defined in what appears to be an earlier frag. FIXME:
16816 This doesn't handle the fr_subtype field, which specifies
16817 a maximum number of bytes to skip when doing an
16819 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
16821 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
16824 stretch
= - ((- stretch
)
16825 & ~ ((1 << (int) f
->fr_offset
) - 1));
16827 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
16839 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
16842 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
16847 /* Assume worst case for symbols not known to be in the same section. */
16848 if (!S_IS_DEFINED (fragp
->fr_symbol
)
16849 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16852 val
= relaxed_symbol_addr (fragp
, stretch
);
16853 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16854 addr
= (addr
+ 4) & ~3;
16855 /* Force misaligned targets to 32-bit variant. */
16859 if (val
< 0 || val
> 1020)
16864 /* Return the size of a relaxable add/sub immediate instruction. */
16866 relax_addsub (fragS
*fragp
, asection
*sec
)
16871 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16872 op
= bfd_get_16(sec
->owner
, buf
);
16873 if ((op
& 0xf) == ((op
>> 4) & 0xf))
16874 return relax_immediate (fragp
, 8, 0);
16876 return relax_immediate (fragp
, 3, 0);
16880 /* Return the size of a relaxable branch instruction. BITS is the
16881 size of the offset field in the narrow instruction. */
16884 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
16890 /* Assume worst case for symbols not known to be in the same section. */
16891 if (!S_IS_DEFINED (fragp
->fr_symbol
)
16892 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16895 val
= relaxed_symbol_addr (fragp
, stretch
);
16896 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16899 /* Offset is a signed value *2 */
16901 if (val
>= limit
|| val
< -limit
)
16907 /* Relax a machine dependent frag. This returns the amount by which
16908 the current size of the frag should change. */
16911 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
16916 oldsize
= fragp
->fr_var
;
16917 switch (fragp
->fr_subtype
)
16919 case T_MNEM_ldr_pc2
:
16920 newsize
= relax_adr (fragp
, sec
, stretch
);
16922 case T_MNEM_ldr_pc
:
16923 case T_MNEM_ldr_sp
:
16924 case T_MNEM_str_sp
:
16925 newsize
= relax_immediate (fragp
, 8, 2);
16929 newsize
= relax_immediate (fragp
, 5, 2);
16933 newsize
= relax_immediate (fragp
, 5, 1);
16937 newsize
= relax_immediate (fragp
, 5, 0);
16940 newsize
= relax_adr (fragp
, sec
, stretch
);
16946 newsize
= relax_immediate (fragp
, 8, 0);
16949 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
16952 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
16954 case T_MNEM_add_sp
:
16955 case T_MNEM_add_pc
:
16956 newsize
= relax_immediate (fragp
, 8, 2);
16958 case T_MNEM_inc_sp
:
16959 case T_MNEM_dec_sp
:
16960 newsize
= relax_immediate (fragp
, 7, 2);
16966 newsize
= relax_addsub (fragp
, sec
);
16972 fragp
->fr_var
= newsize
;
16973 /* Freeze wide instructions that are at or before the same location as
16974 in the previous pass. This avoids infinite loops.
16975 Don't freeze them unconditionally because targets may be artificially
16976 misaligned by the expansion of preceding frags. */
16977 if (stretch
<= 0 && newsize
> 2)
16979 md_convert_frag (sec
->owner
, sec
, fragp
);
16983 return newsize
- oldsize
;
16986 /* Round up a section size to the appropriate boundary. */
16989 md_section_align (segT segment ATTRIBUTE_UNUSED
,
16992 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
16993 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
16995 /* For a.out, force the section size to be aligned. If we don't do
16996 this, BFD will align it for us, but it will not write out the
16997 final bytes of the section. This may be a bug in BFD, but it is
16998 easier to fix it here since that is how the other a.out targets
17002 align
= bfd_get_section_alignment (stdoutput
, segment
);
17003 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
17010 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
17011 of an rs_align_code fragment. */
17014 arm_handle_align (fragS
* fragP
)
17016 static char const arm_noop
[4] = { 0x00, 0x00, 0xa0, 0xe1 };
17017 static char const thumb_noop
[2] = { 0xc0, 0x46 };
17018 static char const arm_bigend_noop
[4] = { 0xe1, 0xa0, 0x00, 0x00 };
17019 static char const thumb_bigend_noop
[2] = { 0x46, 0xc0 };
17021 int bytes
, fix
, noop_size
;
17025 if (fragP
->fr_type
!= rs_align_code
)
17028 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
17029 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
17032 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
17033 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
17035 if (fragP
->tc_frag_data
)
17037 if (target_big_endian
)
17038 noop
= thumb_bigend_noop
;
17041 noop_size
= sizeof (thumb_noop
);
17045 if (target_big_endian
)
17046 noop
= arm_bigend_noop
;
17049 noop_size
= sizeof (arm_noop
);
17052 if (bytes
& (noop_size
- 1))
17054 fix
= bytes
& (noop_size
- 1);
17055 memset (p
, 0, fix
);
17060 while (bytes
>= noop_size
)
17062 memcpy (p
, noop
, noop_size
);
17064 bytes
-= noop_size
;
17068 fragP
->fr_fix
+= fix
;
17069 fragP
->fr_var
= noop_size
;
17072 /* Called from md_do_align. Used to create an alignment
17073 frag in a code section. */
17076 arm_frag_align_code (int n
, int max
)
17080 /* We assume that there will never be a requirement
17081 to support alignments greater than 32 bytes. */
17082 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
17083 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
17085 p
= frag_var (rs_align_code
,
17086 MAX_MEM_FOR_RS_ALIGN_CODE
,
17088 (relax_substateT
) max
,
17095 /* Perform target specific initialisation of a frag. */
17098 arm_init_frag (fragS
* fragP
)
17100 /* Record whether this frag is in an ARM or a THUMB area. */
17101 fragP
->tc_frag_data
= thumb_mode
;
17105 /* When we change sections we need to issue a new mapping symbol. */
17108 arm_elf_change_section (void)
17111 segment_info_type
*seginfo
;
17113 /* Link an unlinked unwind index table section to the .text section. */
17114 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
17115 && elf_linked_to_section (now_seg
) == NULL
)
17116 elf_linked_to_section (now_seg
) = text_section
;
17118 if (!SEG_NORMAL (now_seg
))
17121 flags
= bfd_get_section_flags (stdoutput
, now_seg
);
17123 /* We can ignore sections that only contain debug info. */
17124 if ((flags
& SEC_ALLOC
) == 0)
17127 seginfo
= seg_info (now_seg
);
17128 mapstate
= seginfo
->tc_segment_info_data
.mapstate
;
17129 marked_pr_dependency
= seginfo
->tc_segment_info_data
.marked_pr_dependency
;
17133 arm_elf_section_type (const char * str
, size_t len
)
17135 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
17136 return SHT_ARM_EXIDX
;
17141 /* Code to deal with unwinding tables. */
17143 static void add_unwind_adjustsp (offsetT
);
17145 /* Generate any deferred unwind frame offset. */
17148 flush_pending_unwind (void)
17152 offset
= unwind
.pending_offset
;
17153 unwind
.pending_offset
= 0;
17155 add_unwind_adjustsp (offset
);
17158 /* Add an opcode to this list for this function. Two-byte opcodes should
17159 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
17163 add_unwind_opcode (valueT op
, int length
)
17165 /* Add any deferred stack adjustment. */
17166 if (unwind
.pending_offset
)
17167 flush_pending_unwind ();
17169 unwind
.sp_restored
= 0;
17171 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
17173 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
17174 if (unwind
.opcodes
)
17175 unwind
.opcodes
= xrealloc (unwind
.opcodes
,
17176 unwind
.opcode_alloc
);
17178 unwind
.opcodes
= xmalloc (unwind
.opcode_alloc
);
17183 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
17185 unwind
.opcode_count
++;
17189 /* Add unwind opcodes to adjust the stack pointer. */
17192 add_unwind_adjustsp (offsetT offset
)
17196 if (offset
> 0x200)
17198 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
17203 /* Long form: 0xb2, uleb128. */
17204 /* This might not fit in a word so add the individual bytes,
17205 remembering the list is built in reverse order. */
17206 o
= (valueT
) ((offset
- 0x204) >> 2);
17208 add_unwind_opcode (0, 1);
17210 /* Calculate the uleb128 encoding of the offset. */
17214 bytes
[n
] = o
& 0x7f;
17220 /* Add the insn. */
17222 add_unwind_opcode (bytes
[n
- 1], 1);
17223 add_unwind_opcode (0xb2, 1);
17225 else if (offset
> 0x100)
17227 /* Two short opcodes. */
17228 add_unwind_opcode (0x3f, 1);
17229 op
= (offset
- 0x104) >> 2;
17230 add_unwind_opcode (op
, 1);
17232 else if (offset
> 0)
17234 /* Short opcode. */
17235 op
= (offset
- 4) >> 2;
17236 add_unwind_opcode (op
, 1);
17238 else if (offset
< 0)
17241 while (offset
> 0x100)
17243 add_unwind_opcode (0x7f, 1);
17246 op
= ((offset
- 4) >> 2) | 0x40;
17247 add_unwind_opcode (op
, 1);
17251 /* Finish the list of unwind opcodes for this function. */
17253 finish_unwind_opcodes (void)
17257 if (unwind
.fp_used
)
17259 /* Adjust sp as necessary. */
17260 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
17261 flush_pending_unwind ();
17263 /* After restoring sp from the frame pointer. */
17264 op
= 0x90 | unwind
.fp_reg
;
17265 add_unwind_opcode (op
, 1);
17268 flush_pending_unwind ();
17272 /* Start an exception table entry. If idx is nonzero this is an index table
17276 start_unwind_section (const segT text_seg
, int idx
)
17278 const char * text_name
;
17279 const char * prefix
;
17280 const char * prefix_once
;
17281 const char * group_name
;
17285 size_t sec_name_len
;
17292 prefix
= ELF_STRING_ARM_unwind
;
17293 prefix_once
= ELF_STRING_ARM_unwind_once
;
17294 type
= SHT_ARM_EXIDX
;
17298 prefix
= ELF_STRING_ARM_unwind_info
;
17299 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
17300 type
= SHT_PROGBITS
;
17303 text_name
= segment_name (text_seg
);
17304 if (streq (text_name
, ".text"))
17307 if (strncmp (text_name
, ".gnu.linkonce.t.",
17308 strlen (".gnu.linkonce.t.")) == 0)
17310 prefix
= prefix_once
;
17311 text_name
+= strlen (".gnu.linkonce.t.");
17314 prefix_len
= strlen (prefix
);
17315 text_len
= strlen (text_name
);
17316 sec_name_len
= prefix_len
+ text_len
;
17317 sec_name
= xmalloc (sec_name_len
+ 1);
17318 memcpy (sec_name
, prefix
, prefix_len
);
17319 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
17320 sec_name
[prefix_len
+ text_len
] = '\0';
17326 /* Handle COMDAT group. */
17327 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
17329 group_name
= elf_group_name (text_seg
);
17330 if (group_name
== NULL
)
17332 as_bad (_("Group section `%s' has no group signature"),
17333 segment_name (text_seg
));
17334 ignore_rest_of_line ();
17337 flags
|= SHF_GROUP
;
17341 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
17343 /* Set the section link for index tables. */
17345 elf_linked_to_section (now_seg
) = text_seg
;
17349 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
17350 personality routine data. Returns zero, or the index table value for
17351 and inline entry. */
17354 create_unwind_entry (int have_data
)
17359 /* The current word of data. */
17361 /* The number of bytes left in this word. */
17364 finish_unwind_opcodes ();
17366 /* Remember the current text section. */
17367 unwind
.saved_seg
= now_seg
;
17368 unwind
.saved_subseg
= now_subseg
;
17370 start_unwind_section (now_seg
, 0);
17372 if (unwind
.personality_routine
== NULL
)
17374 if (unwind
.personality_index
== -2)
17377 as_bad (_("handlerdata in cantunwind frame"));
17378 return 1; /* EXIDX_CANTUNWIND. */
17381 /* Use a default personality routine if none is specified. */
17382 if (unwind
.personality_index
== -1)
17384 if (unwind
.opcode_count
> 3)
17385 unwind
.personality_index
= 1;
17387 unwind
.personality_index
= 0;
17390 /* Space for the personality routine entry. */
17391 if (unwind
.personality_index
== 0)
17393 if (unwind
.opcode_count
> 3)
17394 as_bad (_("too many unwind opcodes for personality routine 0"));
17398 /* All the data is inline in the index table. */
17401 while (unwind
.opcode_count
> 0)
17403 unwind
.opcode_count
--;
17404 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
17408 /* Pad with "finish" opcodes. */
17410 data
= (data
<< 8) | 0xb0;
17417 /* We get two opcodes "free" in the first word. */
17418 size
= unwind
.opcode_count
- 2;
17421 /* An extra byte is required for the opcode count. */
17422 size
= unwind
.opcode_count
+ 1;
17424 size
= (size
+ 3) >> 2;
17426 as_bad (_("too many unwind opcodes"));
17428 frag_align (2, 0, 0);
17429 record_alignment (now_seg
, 2);
17430 unwind
.table_entry
= expr_build_dot ();
17432 /* Allocate the table entry. */
17433 ptr
= frag_more ((size
<< 2) + 4);
17434 where
= frag_now_fix () - ((size
<< 2) + 4);
17436 switch (unwind
.personality_index
)
17439 /* ??? Should this be a PLT generating relocation? */
17440 /* Custom personality routine. */
17441 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
17442 BFD_RELOC_ARM_PREL31
);
17447 /* Set the first byte to the number of additional words. */
17452 /* ABI defined personality routines. */
17454 /* Three opcodes bytes are packed into the first word. */
17461 /* The size and first two opcode bytes go in the first word. */
17462 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
17467 /* Should never happen. */
17471 /* Pack the opcodes into words (MSB first), reversing the list at the same
17473 while (unwind
.opcode_count
> 0)
17477 md_number_to_chars (ptr
, data
, 4);
17482 unwind
.opcode_count
--;
17484 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
17487 /* Finish off the last word. */
17490 /* Pad with "finish" opcodes. */
17492 data
= (data
<< 8) | 0xb0;
17494 md_number_to_chars (ptr
, data
, 4);
17499 /* Add an empty descriptor if there is no user-specified data. */
17500 ptr
= frag_more (4);
17501 md_number_to_chars (ptr
, 0, 4);
17508 /* Initialize the DWARF-2 unwind information for this procedure. */
17511 tc_arm_frame_initial_instructions (void)
17513 cfi_add_CFA_def_cfa (REG_SP
, 0);
17515 #endif /* OBJ_ELF */
17517 /* Convert REGNAME to a DWARF-2 register number. */
17520 tc_arm_regname_to_dw2regnum (char *regname
)
17522 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
17532 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
17536 expr
.X_op
= O_secrel
;
17537 expr
.X_add_symbol
= symbol
;
17538 expr
.X_add_number
= 0;
17539 emit_expr (&expr
, size
);
17543 /* MD interface: Symbol and relocation handling. */
17545 /* Return the address within the segment that a PC-relative fixup is
17546 relative to. For ARM, PC-relative fixups applied to instructions
17547 are generally relative to the location of the fixup plus 8 bytes.
17548 Thumb branches are offset by 4, and Thumb loads relative to PC
17549 require special handling. */
17552 md_pcrel_from_section (fixS
* fixP
, segT seg
)
17554 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
17556 /* If this is pc-relative and we are going to emit a relocation
17557 then we just want to put out any pipeline compensation that the linker
17558 will need. Otherwise we want to use the calculated base.
17559 For WinCE we skip the bias for externals as well, since this
17560 is how the MS ARM-CE assembler behaves and we want to be compatible. */
17562 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
17563 || (arm_force_relocation (fixP
)
17565 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
17570 switch (fixP
->fx_r_type
)
17572 /* PC relative addressing on the Thumb is slightly odd as the
17573 bottom two bits of the PC are forced to zero for the
17574 calculation. This happens *after* application of the
17575 pipeline offset. However, Thumb adrl already adjusts for
17576 this, so we need not do it again. */
17577 case BFD_RELOC_ARM_THUMB_ADD
:
17580 case BFD_RELOC_ARM_THUMB_OFFSET
:
17581 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
17582 case BFD_RELOC_ARM_T32_ADD_PC12
:
17583 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
17584 return (base
+ 4) & ~3;
17586 /* Thumb branches are simply offset by +4. */
17587 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
17588 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
17589 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
17590 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
17591 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
17592 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
17593 case BFD_RELOC_THUMB_PCREL_BLX
:
17596 /* ARM mode branches are offset by +8. However, the Windows CE
17597 loader expects the relocation not to take this into account. */
17598 case BFD_RELOC_ARM_PCREL_BRANCH
:
17599 case BFD_RELOC_ARM_PCREL_CALL
:
17600 case BFD_RELOC_ARM_PCREL_JUMP
:
17601 case BFD_RELOC_ARM_PCREL_BLX
:
17602 case BFD_RELOC_ARM_PLT32
:
17604 /* When handling fixups immediately, because we have already
17605 discovered the value of a symbol, or the address of the frag involved
17606 we must account for the offset by +8, as the OS loader will never see the reloc.
17607 see fixup_segment() in write.c
17608 The S_IS_EXTERNAL test handles the case of global symbols.
17609 Those need the calculated base, not just the pipe compensation the linker will need. */
17611 && fixP
->fx_addsy
!= NULL
17612 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
17613 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
17620 /* ARM mode loads relative to PC are also offset by +8. Unlike
17621 branches, the Windows CE loader *does* expect the relocation
17622 to take this into account. */
17623 case BFD_RELOC_ARM_OFFSET_IMM
:
17624 case BFD_RELOC_ARM_OFFSET_IMM8
:
17625 case BFD_RELOC_ARM_HWLITERAL
:
17626 case BFD_RELOC_ARM_LITERAL
:
17627 case BFD_RELOC_ARM_CP_OFF_IMM
:
17631 /* Other PC-relative relocations are un-offset. */
17637 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
17638 Otherwise we have no need to default values of symbols. */
17641 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
17644 if (name
[0] == '_' && name
[1] == 'G'
17645 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
17649 if (symbol_find (name
))
17650 as_bad (_("GOT already in the symbol table"));
17652 GOT_symbol
= symbol_new (name
, undefined_section
,
17653 (valueT
) 0, & zero_address_frag
);
17663 /* Subroutine of md_apply_fix. Check to see if an immediate can be
17664 computed as two separate immediate values, added together. We
17665 already know that this value cannot be computed by just one ARM
17668 static unsigned int
17669 validate_immediate_twopart (unsigned int val
,
17670 unsigned int * highpart
)
17675 for (i
= 0; i
< 32; i
+= 2)
17676 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
17682 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
17684 else if (a
& 0xff0000)
17686 if (a
& 0xff000000)
17688 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
17692 assert (a
& 0xff000000);
17693 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
17696 return (a
& 0xff) | (i
<< 7);
17703 validate_offset_imm (unsigned int val
, int hwse
)
17705 if ((hwse
&& val
> 255) || val
> 4095)
17710 /* Subroutine of md_apply_fix. Do those data_ops which can take a
17711 negative immediate constant by altering the instruction. A bit of
17716 by inverting the second operand, and
17719 by negating the second operand. */
17722 negate_data_op (unsigned long * instruction
,
17723 unsigned long value
)
17726 unsigned long negated
, inverted
;
17728 negated
= encode_arm_immediate (-value
);
17729 inverted
= encode_arm_immediate (~value
);
17731 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
17734 /* First negates. */
17735 case OPCODE_SUB
: /* ADD <-> SUB */
17736 new_inst
= OPCODE_ADD
;
17741 new_inst
= OPCODE_SUB
;
17745 case OPCODE_CMP
: /* CMP <-> CMN */
17746 new_inst
= OPCODE_CMN
;
17751 new_inst
= OPCODE_CMP
;
17755 /* Now Inverted ops. */
17756 case OPCODE_MOV
: /* MOV <-> MVN */
17757 new_inst
= OPCODE_MVN
;
17762 new_inst
= OPCODE_MOV
;
17766 case OPCODE_AND
: /* AND <-> BIC */
17767 new_inst
= OPCODE_BIC
;
17772 new_inst
= OPCODE_AND
;
17776 case OPCODE_ADC
: /* ADC <-> SBC */
17777 new_inst
= OPCODE_SBC
;
17782 new_inst
= OPCODE_ADC
;
17786 /* We cannot do anything. */
17791 if (value
== (unsigned) FAIL
)
17794 *instruction
&= OPCODE_MASK
;
17795 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
17799 /* Like negate_data_op, but for Thumb-2. */
17801 static unsigned int
17802 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
17806 unsigned int negated
, inverted
;
17808 negated
= encode_thumb32_immediate (-value
);
17809 inverted
= encode_thumb32_immediate (~value
);
17811 rd
= (*instruction
>> 8) & 0xf;
17812 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
17815 /* ADD <-> SUB. Includes CMP <-> CMN. */
17816 case T2_OPCODE_SUB
:
17817 new_inst
= T2_OPCODE_ADD
;
17821 case T2_OPCODE_ADD
:
17822 new_inst
= T2_OPCODE_SUB
;
17826 /* ORR <-> ORN. Includes MOV <-> MVN. */
17827 case T2_OPCODE_ORR
:
17828 new_inst
= T2_OPCODE_ORN
;
17832 case T2_OPCODE_ORN
:
17833 new_inst
= T2_OPCODE_ORR
;
17837 /* AND <-> BIC. TST has no inverted equivalent. */
17838 case T2_OPCODE_AND
:
17839 new_inst
= T2_OPCODE_BIC
;
17846 case T2_OPCODE_BIC
:
17847 new_inst
= T2_OPCODE_AND
;
17852 case T2_OPCODE_ADC
:
17853 new_inst
= T2_OPCODE_SBC
;
17857 case T2_OPCODE_SBC
:
17858 new_inst
= T2_OPCODE_ADC
;
17862 /* We cannot do anything. */
17867 if (value
== (unsigned int)FAIL
)
17870 *instruction
&= T2_OPCODE_MASK
;
17871 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
17875 /* Read a 32-bit thumb instruction from buf. */
17876 static unsigned long
17877 get_thumb32_insn (char * buf
)
17879 unsigned long insn
;
17880 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
17881 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17887 /* We usually want to set the low bit on the address of thumb function
17888 symbols. In particular .word foo - . should have the low bit set.
17889 Generic code tries to fold the difference of two symbols to
17890 a constant. Prevent this and force a relocation when the first symbols
17891 is a thumb function. */
17893 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
17895 if (op
== O_subtract
17896 && l
->X_op
== O_symbol
17897 && r
->X_op
== O_symbol
17898 && THUMB_IS_FUNC (l
->X_add_symbol
))
17900 l
->X_op
= O_subtract
;
17901 l
->X_op_symbol
= r
->X_add_symbol
;
17902 l
->X_add_number
-= r
->X_add_number
;
17905 /* Process as normal. */
17910 md_apply_fix (fixS
* fixP
,
17914 offsetT value
= * valP
;
17916 unsigned int newimm
;
17917 unsigned long temp
;
17919 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
17921 assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
17923 /* Note whether this will delete the relocation. */
17925 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
17928 /* On a 64-bit host, silently truncate 'value' to 32 bits for
17929 consistency with the behaviour on 32-bit hosts. Remember value
17931 value
&= 0xffffffff;
17932 value
^= 0x80000000;
17933 value
-= 0x80000000;
17936 fixP
->fx_addnumber
= value
;
17938 /* Same treatment for fixP->fx_offset. */
17939 fixP
->fx_offset
&= 0xffffffff;
17940 fixP
->fx_offset
^= 0x80000000;
17941 fixP
->fx_offset
-= 0x80000000;
17943 switch (fixP
->fx_r_type
)
17945 case BFD_RELOC_NONE
:
17946 /* This will need to go in the object file. */
17950 case BFD_RELOC_ARM_IMMEDIATE
:
17951 /* We claim that this fixup has been processed here,
17952 even if in fact we generate an error because we do
17953 not have a reloc for it, so tc_gen_reloc will reject it. */
17957 && ! S_IS_DEFINED (fixP
->fx_addsy
))
17959 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17960 _("undefined symbol %s used as an immediate value"),
17961 S_GET_NAME (fixP
->fx_addsy
));
17965 newimm
= encode_arm_immediate (value
);
17966 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17968 /* If the instruction will fail, see if we can fix things up by
17969 changing the opcode. */
17970 if (newimm
== (unsigned int) FAIL
17971 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
17973 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17974 _("invalid constant (%lx) after fixup"),
17975 (unsigned long) value
);
17979 newimm
|= (temp
& 0xfffff000);
17980 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
17983 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
17985 unsigned int highpart
= 0;
17986 unsigned int newinsn
= 0xe1a00000; /* nop. */
17988 newimm
= encode_arm_immediate (value
);
17989 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17991 /* If the instruction will fail, see if we can fix things up by
17992 changing the opcode. */
17993 if (newimm
== (unsigned int) FAIL
17994 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
17996 /* No ? OK - try using two ADD instructions to generate
17998 newimm
= validate_immediate_twopart (value
, & highpart
);
18000 /* Yes - then make sure that the second instruction is
18002 if (newimm
!= (unsigned int) FAIL
)
18004 /* Still No ? Try using a negated value. */
18005 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
18006 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
18007 /* Otherwise - give up. */
18010 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18011 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
18016 /* Replace the first operand in the 2nd instruction (which
18017 is the PC) with the destination register. We have
18018 already added in the PC in the first instruction and we
18019 do not want to do it again. */
18020 newinsn
&= ~ 0xf0000;
18021 newinsn
|= ((newinsn
& 0x0f000) << 4);
18024 newimm
|= (temp
& 0xfffff000);
18025 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
18027 highpart
|= (newinsn
& 0xfffff000);
18028 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
18032 case BFD_RELOC_ARM_OFFSET_IMM
:
18033 if (!fixP
->fx_done
&& seg
->use_rela_p
)
18036 case BFD_RELOC_ARM_LITERAL
:
18042 if (validate_offset_imm (value
, 0) == FAIL
)
18044 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
18045 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18046 _("invalid literal constant: pool needs to be closer"));
18048 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18049 _("bad immediate value for offset (%ld)"),
18054 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18055 newval
&= 0xff7ff000;
18056 newval
|= value
| (sign
? INDEX_UP
: 0);
18057 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18060 case BFD_RELOC_ARM_OFFSET_IMM8
:
18061 case BFD_RELOC_ARM_HWLITERAL
:
18067 if (validate_offset_imm (value
, 1) == FAIL
)
18069 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
18070 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18071 _("invalid literal constant: pool needs to be closer"));
18073 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
18078 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18079 newval
&= 0xff7ff0f0;
18080 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
18081 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18084 case BFD_RELOC_ARM_T32_OFFSET_U8
:
18085 if (value
< 0 || value
> 1020 || value
% 4 != 0)
18086 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18087 _("bad immediate value for offset (%ld)"), (long) value
);
18090 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
18092 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
18095 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
18096 /* This is a complicated relocation used for all varieties of Thumb32
18097 load/store instruction with immediate offset:
18099 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
18100 *4, optional writeback(W)
18101 (doubleword load/store)
18103 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
18104 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
18105 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
18106 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
18107 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
18109 Uppercase letters indicate bits that are already encoded at
18110 this point. Lowercase letters are our problem. For the
18111 second block of instructions, the secondary opcode nybble
18112 (bits 8..11) is present, and bit 23 is zero, even if this is
18113 a PC-relative operation. */
18114 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18116 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
18118 if ((newval
& 0xf0000000) == 0xe0000000)
18120 /* Doubleword load/store: 8-bit offset, scaled by 4. */
18122 newval
|= (1 << 23);
18125 if (value
% 4 != 0)
18127 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18128 _("offset not a multiple of 4"));
18134 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18135 _("offset out of range"));
18140 else if ((newval
& 0x000f0000) == 0x000f0000)
18142 /* PC-relative, 12-bit offset. */
18144 newval
|= (1 << 23);
18149 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18150 _("offset out of range"));
18155 else if ((newval
& 0x00000100) == 0x00000100)
18157 /* Writeback: 8-bit, +/- offset. */
18159 newval
|= (1 << 9);
18164 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18165 _("offset out of range"));
18170 else if ((newval
& 0x00000f00) == 0x00000e00)
18172 /* T-instruction: positive 8-bit offset. */
18173 if (value
< 0 || value
> 0xff)
18175 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18176 _("offset out of range"));
18184 /* Positive 12-bit or negative 8-bit offset. */
18188 newval
|= (1 << 23);
18198 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18199 _("offset out of range"));
18206 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
18207 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
18210 case BFD_RELOC_ARM_SHIFT_IMM
:
18211 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18212 if (((unsigned long) value
) > 32
18214 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
18216 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18217 _("shift expression is too large"));
18222 /* Shifts of zero must be done as lsl. */
18224 else if (value
== 32)
18226 newval
&= 0xfffff07f;
18227 newval
|= (value
& 0x1f) << 7;
18228 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18231 case BFD_RELOC_ARM_T32_IMMEDIATE
:
18232 case BFD_RELOC_ARM_T32_ADD_IMM
:
18233 case BFD_RELOC_ARM_T32_IMM12
:
18234 case BFD_RELOC_ARM_T32_ADD_PC12
:
18235 /* We claim that this fixup has been processed here,
18236 even if in fact we generate an error because we do
18237 not have a reloc for it, so tc_gen_reloc will reject it. */
18241 && ! S_IS_DEFINED (fixP
->fx_addsy
))
18243 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18244 _("undefined symbol %s used as an immediate value"),
18245 S_GET_NAME (fixP
->fx_addsy
));
18249 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18251 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
18254 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
18255 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
18257 newimm
= encode_thumb32_immediate (value
);
18258 if (newimm
== (unsigned int) FAIL
)
18259 newimm
= thumb32_negate_data_op (&newval
, value
);
18261 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
18262 && newimm
== (unsigned int) FAIL
)
18264 /* Turn add/sum into addw/subw. */
18265 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
18266 newval
= (newval
& 0xfeffffff) | 0x02000000;
18268 /* 12 bit immediate for addw/subw. */
18272 newval
^= 0x00a00000;
18275 newimm
= (unsigned int) FAIL
;
18280 if (newimm
== (unsigned int)FAIL
)
18282 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18283 _("invalid constant (%lx) after fixup"),
18284 (unsigned long) value
);
18288 newval
|= (newimm
& 0x800) << 15;
18289 newval
|= (newimm
& 0x700) << 4;
18290 newval
|= (newimm
& 0x0ff);
18292 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
18293 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
18296 case BFD_RELOC_ARM_SMC
:
18297 if (((unsigned long) value
) > 0xffff)
18298 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18299 _("invalid smc expression"));
18300 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18301 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
18302 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18305 case BFD_RELOC_ARM_SWI
:
18306 if (fixP
->tc_fix_data
!= 0)
18308 if (((unsigned long) value
) > 0xff)
18309 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18310 _("invalid swi expression"));
18311 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18313 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18317 if (((unsigned long) value
) > 0x00ffffff)
18318 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18319 _("invalid swi expression"));
18320 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18322 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18326 case BFD_RELOC_ARM_MULTI
:
18327 if (((unsigned long) value
) > 0xffff)
18328 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18329 _("invalid expression in load/store multiple"));
18330 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
18331 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18335 case BFD_RELOC_ARM_PCREL_CALL
:
18336 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18337 if ((newval
& 0xf0000000) == 0xf0000000)
18341 goto arm_branch_common
;
18343 case BFD_RELOC_ARM_PCREL_JUMP
:
18344 case BFD_RELOC_ARM_PLT32
:
18346 case BFD_RELOC_ARM_PCREL_BRANCH
:
18348 goto arm_branch_common
;
18350 case BFD_RELOC_ARM_PCREL_BLX
:
18353 /* We are going to store value (shifted right by two) in the
18354 instruction, in a 24 bit, signed field. Bits 26 through 32 either
18355 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
18356 also be be clear. */
18358 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18359 _("misaligned branch destination"));
18360 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
18361 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
18362 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18363 _("branch out of range"));
18365 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18367 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18368 newval
|= (value
>> 2) & 0x00ffffff;
18369 /* Set the H bit on BLX instructions. */
18373 newval
|= 0x01000000;
18375 newval
&= ~0x01000000;
18377 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18381 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
18382 /* CBZ can only branch forward. */
18384 /* Attempts to use CBZ to branch to the next instruction
18385 (which, strictly speaking, are prohibited) will be turned into
18388 FIXME: It may be better to remove the instruction completely and
18389 perform relaxation. */
18392 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18393 newval
= 0xbf00; /* NOP encoding T1 */
18394 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18399 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18400 _("branch out of range"));
18402 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18404 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18405 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
18406 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18411 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
18412 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
18413 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18414 _("branch out of range"));
18416 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18418 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18419 newval
|= (value
& 0x1ff) >> 1;
18420 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18424 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
18425 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
18426 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18427 _("branch out of range"));
18429 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18431 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18432 newval
|= (value
& 0xfff) >> 1;
18433 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18437 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
18438 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
18439 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18440 _("conditional branch out of range"));
18442 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18445 addressT S
, J1
, J2
, lo
, hi
;
18447 S
= (value
& 0x00100000) >> 20;
18448 J2
= (value
& 0x00080000) >> 19;
18449 J1
= (value
& 0x00040000) >> 18;
18450 hi
= (value
& 0x0003f000) >> 12;
18451 lo
= (value
& 0x00000ffe) >> 1;
18453 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18454 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18455 newval
|= (S
<< 10) | hi
;
18456 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
18457 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18458 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18462 case BFD_RELOC_THUMB_PCREL_BLX
:
18463 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
18464 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
18465 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18466 _("branch out of range"));
18468 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
18469 /* For a BLX instruction, make sure that the relocation is rounded up
18470 to a word boundary. This follows the semantics of the instruction
18471 which specifies that bit 1 of the target address will come from bit
18472 1 of the base address. */
18473 value
= (value
+ 1) & ~ 1;
18475 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18479 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18480 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18481 newval
|= (value
& 0x7fffff) >> 12;
18482 newval2
|= (value
& 0xfff) >> 1;
18483 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18484 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18488 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
18489 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
18490 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18491 _("branch out of range"));
18493 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18496 addressT S
, I1
, I2
, lo
, hi
;
18498 S
= (value
& 0x01000000) >> 24;
18499 I1
= (value
& 0x00800000) >> 23;
18500 I2
= (value
& 0x00400000) >> 22;
18501 hi
= (value
& 0x003ff000) >> 12;
18502 lo
= (value
& 0x00000ffe) >> 1;
18507 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18508 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18509 newval
|= (S
<< 10) | hi
;
18510 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
18511 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18512 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18517 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18518 md_number_to_chars (buf
, value
, 1);
18522 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18523 md_number_to_chars (buf
, value
, 2);
18527 case BFD_RELOC_ARM_TLS_GD32
:
18528 case BFD_RELOC_ARM_TLS_LE32
:
18529 case BFD_RELOC_ARM_TLS_IE32
:
18530 case BFD_RELOC_ARM_TLS_LDM32
:
18531 case BFD_RELOC_ARM_TLS_LDO32
:
18532 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
18535 case BFD_RELOC_ARM_GOT32
:
18536 case BFD_RELOC_ARM_GOTOFF
:
18537 case BFD_RELOC_ARM_TARGET2
:
18538 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18539 md_number_to_chars (buf
, 0, 4);
18543 case BFD_RELOC_RVA
:
18545 case BFD_RELOC_ARM_TARGET1
:
18546 case BFD_RELOC_ARM_ROSEGREL32
:
18547 case BFD_RELOC_ARM_SBREL32
:
18548 case BFD_RELOC_32_PCREL
:
18550 case BFD_RELOC_32_SECREL
:
18552 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18554 /* For WinCE we only do this for pcrel fixups. */
18555 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
18557 md_number_to_chars (buf
, value
, 4);
18561 case BFD_RELOC_ARM_PREL31
:
18562 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18564 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
18565 if ((value
^ (value
>> 1)) & 0x40000000)
18567 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18568 _("rel31 relocation overflow"));
18570 newval
|= value
& 0x7fffffff;
18571 md_number_to_chars (buf
, newval
, 4);
18576 case BFD_RELOC_ARM_CP_OFF_IMM
:
18577 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
18578 if (value
< -1023 || value
> 1023 || (value
& 3))
18579 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18580 _("co-processor offset out of range"));
18585 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18586 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18587 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18589 newval
= get_thumb32_insn (buf
);
18590 newval
&= 0xff7fff00;
18591 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
18592 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18593 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18594 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18596 put_thumb32_insn (buf
, newval
);
18599 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
18600 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
18601 if (value
< -255 || value
> 255)
18602 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18603 _("co-processor offset out of range"));
18605 goto cp_off_common
;
18607 case BFD_RELOC_ARM_THUMB_OFFSET
:
18608 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18609 /* Exactly what ranges, and where the offset is inserted depends
18610 on the type of instruction, we can establish this from the
18612 switch (newval
>> 12)
18614 case 4: /* PC load. */
18615 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
18616 forced to zero for these loads; md_pcrel_from has already
18617 compensated for this. */
18619 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18620 _("invalid offset, target not word aligned (0x%08lX)"),
18621 (((unsigned long) fixP
->fx_frag
->fr_address
18622 + (unsigned long) fixP
->fx_where
) & ~3)
18623 + (unsigned long) value
);
18625 if (value
& ~0x3fc)
18626 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18627 _("invalid offset, value too big (0x%08lX)"),
18630 newval
|= value
>> 2;
18633 case 9: /* SP load/store. */
18634 if (value
& ~0x3fc)
18635 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18636 _("invalid offset, value too big (0x%08lX)"),
18638 newval
|= value
>> 2;
18641 case 6: /* Word load/store. */
18643 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18644 _("invalid offset, value too big (0x%08lX)"),
18646 newval
|= value
<< 4; /* 6 - 2. */
18649 case 7: /* Byte load/store. */
18651 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18652 _("invalid offset, value too big (0x%08lX)"),
18654 newval
|= value
<< 6;
18657 case 8: /* Halfword load/store. */
18659 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18660 _("invalid offset, value too big (0x%08lX)"),
18662 newval
|= value
<< 5; /* 6 - 1. */
18666 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18667 "Unable to process relocation for thumb opcode: %lx",
18668 (unsigned long) newval
);
18671 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18674 case BFD_RELOC_ARM_THUMB_ADD
:
18675 /* This is a complicated relocation, since we use it for all of
18676 the following immediate relocations:
18680 9bit ADD/SUB SP word-aligned
18681 10bit ADD PC/SP word-aligned
18683 The type of instruction being processed is encoded in the
18690 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18692 int rd
= (newval
>> 4) & 0xf;
18693 int rs
= newval
& 0xf;
18694 int subtract
= !!(newval
& 0x8000);
18696 /* Check for HI regs, only very restricted cases allowed:
18697 Adjusting SP, and using PC or SP to get an address. */
18698 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
18699 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
18700 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18701 _("invalid Hi register with immediate"));
18703 /* If value is negative, choose the opposite instruction. */
18707 subtract
= !subtract
;
18709 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18710 _("immediate value out of range"));
18715 if (value
& ~0x1fc)
18716 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18717 _("invalid immediate for stack address calculation"));
18718 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
18719 newval
|= value
>> 2;
18721 else if (rs
== REG_PC
|| rs
== REG_SP
)
18723 if (subtract
|| value
& ~0x3fc)
18724 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18725 _("invalid immediate for address calculation (value = 0x%08lX)"),
18726 (unsigned long) value
);
18727 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
18729 newval
|= value
>> 2;
18734 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18735 _("immediate value out of range"));
18736 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
18737 newval
|= (rd
<< 8) | value
;
18742 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18743 _("immediate value out of range"));
18744 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
18745 newval
|= rd
| (rs
<< 3) | (value
<< 6);
18748 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18751 case BFD_RELOC_ARM_THUMB_IMM
:
18752 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18753 if (value
< 0 || value
> 255)
18754 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18755 _("invalid immediate: %ld is out of range"),
18758 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18761 case BFD_RELOC_ARM_THUMB_SHIFT
:
18762 /* 5bit shift value (0..32). LSL cannot take 32. */
18763 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
18764 temp
= newval
& 0xf800;
18765 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
18766 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18767 _("invalid shift value: %ld"), (long) value
);
18768 /* Shifts of zero must be encoded as LSL. */
18770 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
18771 /* Shifts of 32 are encoded as zero. */
18772 else if (value
== 32)
18774 newval
|= value
<< 6;
18775 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18778 case BFD_RELOC_VTABLE_INHERIT
:
18779 case BFD_RELOC_VTABLE_ENTRY
:
18783 case BFD_RELOC_ARM_MOVW
:
18784 case BFD_RELOC_ARM_MOVT
:
18785 case BFD_RELOC_ARM_THUMB_MOVW
:
18786 case BFD_RELOC_ARM_THUMB_MOVT
:
18787 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18789 /* REL format relocations are limited to a 16-bit addend. */
18790 if (!fixP
->fx_done
)
18792 if (value
< -0x1000 || value
> 0xffff)
18793 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18794 _("offset out of range"));
18796 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
18797 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18802 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
18803 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18805 newval
= get_thumb32_insn (buf
);
18806 newval
&= 0xfbf08f00;
18807 newval
|= (value
& 0xf000) << 4;
18808 newval
|= (value
& 0x0800) << 15;
18809 newval
|= (value
& 0x0700) << 4;
18810 newval
|= (value
& 0x00ff);
18811 put_thumb32_insn (buf
, newval
);
18815 newval
= md_chars_to_number (buf
, 4);
18816 newval
&= 0xfff0f000;
18817 newval
|= value
& 0x0fff;
18818 newval
|= (value
& 0xf000) << 4;
18819 md_number_to_chars (buf
, newval
, 4);
18824 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
18825 case BFD_RELOC_ARM_ALU_PC_G0
:
18826 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
18827 case BFD_RELOC_ARM_ALU_PC_G1
:
18828 case BFD_RELOC_ARM_ALU_PC_G2
:
18829 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
18830 case BFD_RELOC_ARM_ALU_SB_G0
:
18831 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
18832 case BFD_RELOC_ARM_ALU_SB_G1
:
18833 case BFD_RELOC_ARM_ALU_SB_G2
:
18834 assert (!fixP
->fx_done
);
18835 if (!seg
->use_rela_p
)
18838 bfd_vma encoded_addend
;
18839 bfd_vma addend_abs
= abs (value
);
18841 /* Check that the absolute value of the addend can be
18842 expressed as an 8-bit constant plus a rotation. */
18843 encoded_addend
= encode_arm_immediate (addend_abs
);
18844 if (encoded_addend
== (unsigned int) FAIL
)
18845 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18846 _("the offset 0x%08lX is not representable"),
18847 (unsigned long) addend_abs
);
18849 /* Extract the instruction. */
18850 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18852 /* If the addend is positive, use an ADD instruction.
18853 Otherwise use a SUB. Take care not to destroy the S bit. */
18854 insn
&= 0xff1fffff;
18860 /* Place the encoded addend into the first 12 bits of the
18862 insn
&= 0xfffff000;
18863 insn
|= encoded_addend
;
18865 /* Update the instruction. */
18866 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18870 case BFD_RELOC_ARM_LDR_PC_G0
:
18871 case BFD_RELOC_ARM_LDR_PC_G1
:
18872 case BFD_RELOC_ARM_LDR_PC_G2
:
18873 case BFD_RELOC_ARM_LDR_SB_G0
:
18874 case BFD_RELOC_ARM_LDR_SB_G1
:
18875 case BFD_RELOC_ARM_LDR_SB_G2
:
18876 assert (!fixP
->fx_done
);
18877 if (!seg
->use_rela_p
)
18880 bfd_vma addend_abs
= abs (value
);
18882 /* Check that the absolute value of the addend can be
18883 encoded in 12 bits. */
18884 if (addend_abs
>= 0x1000)
18885 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18886 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
18887 (unsigned long) addend_abs
);
18889 /* Extract the instruction. */
18890 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18892 /* If the addend is negative, clear bit 23 of the instruction.
18893 Otherwise set it. */
18895 insn
&= ~(1 << 23);
18899 /* Place the absolute value of the addend into the first 12 bits
18900 of the instruction. */
18901 insn
&= 0xfffff000;
18902 insn
|= addend_abs
;
18904 /* Update the instruction. */
18905 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18909 case BFD_RELOC_ARM_LDRS_PC_G0
:
18910 case BFD_RELOC_ARM_LDRS_PC_G1
:
18911 case BFD_RELOC_ARM_LDRS_PC_G2
:
18912 case BFD_RELOC_ARM_LDRS_SB_G0
:
18913 case BFD_RELOC_ARM_LDRS_SB_G1
:
18914 case BFD_RELOC_ARM_LDRS_SB_G2
:
18915 assert (!fixP
->fx_done
);
18916 if (!seg
->use_rela_p
)
18919 bfd_vma addend_abs
= abs (value
);
18921 /* Check that the absolute value of the addend can be
18922 encoded in 8 bits. */
18923 if (addend_abs
>= 0x100)
18924 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18925 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
18926 (unsigned long) addend_abs
);
18928 /* Extract the instruction. */
18929 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18931 /* If the addend is negative, clear bit 23 of the instruction.
18932 Otherwise set it. */
18934 insn
&= ~(1 << 23);
18938 /* Place the first four bits of the absolute value of the addend
18939 into the first 4 bits of the instruction, and the remaining
18940 four into bits 8 .. 11. */
18941 insn
&= 0xfffff0f0;
18942 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
18944 /* Update the instruction. */
18945 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18949 case BFD_RELOC_ARM_LDC_PC_G0
:
18950 case BFD_RELOC_ARM_LDC_PC_G1
:
18951 case BFD_RELOC_ARM_LDC_PC_G2
:
18952 case BFD_RELOC_ARM_LDC_SB_G0
:
18953 case BFD_RELOC_ARM_LDC_SB_G1
:
18954 case BFD_RELOC_ARM_LDC_SB_G2
:
18955 assert (!fixP
->fx_done
);
18956 if (!seg
->use_rela_p
)
18959 bfd_vma addend_abs
= abs (value
);
18961 /* Check that the absolute value of the addend is a multiple of
18962 four and, when divided by four, fits in 8 bits. */
18963 if (addend_abs
& 0x3)
18964 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18965 _("bad offset 0x%08lX (must be word-aligned)"),
18966 (unsigned long) addend_abs
);
18968 if ((addend_abs
>> 2) > 0xff)
18969 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18970 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
18971 (unsigned long) addend_abs
);
18973 /* Extract the instruction. */
18974 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18976 /* If the addend is negative, clear bit 23 of the instruction.
18977 Otherwise set it. */
18979 insn
&= ~(1 << 23);
18983 /* Place the addend (divided by four) into the first eight
18984 bits of the instruction. */
18985 insn
&= 0xfffffff0;
18986 insn
|= addend_abs
>> 2;
18988 /* Update the instruction. */
18989 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18993 case BFD_RELOC_ARM_V4BX
:
18994 /* This will need to go in the object file. */
18998 case BFD_RELOC_UNUSED
:
19000 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19001 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
19005 /* Translate internal representation of relocation info to BFD target
19009 tc_gen_reloc (asection
*section
, fixS
*fixp
)
19012 bfd_reloc_code_real_type code
;
19014 reloc
= xmalloc (sizeof (arelent
));
19016 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
19017 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
19018 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
19020 if (fixp
->fx_pcrel
)
19022 if (section
->use_rela_p
)
19023 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
19025 fixp
->fx_offset
= reloc
->address
;
19027 reloc
->addend
= fixp
->fx_offset
;
19029 switch (fixp
->fx_r_type
)
19032 if (fixp
->fx_pcrel
)
19034 code
= BFD_RELOC_8_PCREL
;
19039 if (fixp
->fx_pcrel
)
19041 code
= BFD_RELOC_16_PCREL
;
19046 if (fixp
->fx_pcrel
)
19048 code
= BFD_RELOC_32_PCREL
;
19052 case BFD_RELOC_ARM_MOVW
:
19053 if (fixp
->fx_pcrel
)
19055 code
= BFD_RELOC_ARM_MOVW_PCREL
;
19059 case BFD_RELOC_ARM_MOVT
:
19060 if (fixp
->fx_pcrel
)
19062 code
= BFD_RELOC_ARM_MOVT_PCREL
;
19066 case BFD_RELOC_ARM_THUMB_MOVW
:
19067 if (fixp
->fx_pcrel
)
19069 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
19073 case BFD_RELOC_ARM_THUMB_MOVT
:
19074 if (fixp
->fx_pcrel
)
19076 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
19080 case BFD_RELOC_NONE
:
19081 case BFD_RELOC_ARM_PCREL_BRANCH
:
19082 case BFD_RELOC_ARM_PCREL_BLX
:
19083 case BFD_RELOC_RVA
:
19084 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19085 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19086 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19087 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19088 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19089 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19090 case BFD_RELOC_THUMB_PCREL_BLX
:
19091 case BFD_RELOC_VTABLE_ENTRY
:
19092 case BFD_RELOC_VTABLE_INHERIT
:
19094 case BFD_RELOC_32_SECREL
:
19096 code
= fixp
->fx_r_type
;
19099 case BFD_RELOC_ARM_LITERAL
:
19100 case BFD_RELOC_ARM_HWLITERAL
:
19101 /* If this is called then the a literal has
19102 been referenced across a section boundary. */
19103 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19104 _("literal referenced across section boundary"));
19108 case BFD_RELOC_ARM_GOT32
:
19109 case BFD_RELOC_ARM_GOTOFF
:
19110 case BFD_RELOC_ARM_PLT32
:
19111 case BFD_RELOC_ARM_TARGET1
:
19112 case BFD_RELOC_ARM_ROSEGREL32
:
19113 case BFD_RELOC_ARM_SBREL32
:
19114 case BFD_RELOC_ARM_PREL31
:
19115 case BFD_RELOC_ARM_TARGET2
:
19116 case BFD_RELOC_ARM_TLS_LE32
:
19117 case BFD_RELOC_ARM_TLS_LDO32
:
19118 case BFD_RELOC_ARM_PCREL_CALL
:
19119 case BFD_RELOC_ARM_PCREL_JUMP
:
19120 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
19121 case BFD_RELOC_ARM_ALU_PC_G0
:
19122 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
19123 case BFD_RELOC_ARM_ALU_PC_G1
:
19124 case BFD_RELOC_ARM_ALU_PC_G2
:
19125 case BFD_RELOC_ARM_LDR_PC_G0
:
19126 case BFD_RELOC_ARM_LDR_PC_G1
:
19127 case BFD_RELOC_ARM_LDR_PC_G2
:
19128 case BFD_RELOC_ARM_LDRS_PC_G0
:
19129 case BFD_RELOC_ARM_LDRS_PC_G1
:
19130 case BFD_RELOC_ARM_LDRS_PC_G2
:
19131 case BFD_RELOC_ARM_LDC_PC_G0
:
19132 case BFD_RELOC_ARM_LDC_PC_G1
:
19133 case BFD_RELOC_ARM_LDC_PC_G2
:
19134 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
19135 case BFD_RELOC_ARM_ALU_SB_G0
:
19136 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
19137 case BFD_RELOC_ARM_ALU_SB_G1
:
19138 case BFD_RELOC_ARM_ALU_SB_G2
:
19139 case BFD_RELOC_ARM_LDR_SB_G0
:
19140 case BFD_RELOC_ARM_LDR_SB_G1
:
19141 case BFD_RELOC_ARM_LDR_SB_G2
:
19142 case BFD_RELOC_ARM_LDRS_SB_G0
:
19143 case BFD_RELOC_ARM_LDRS_SB_G1
:
19144 case BFD_RELOC_ARM_LDRS_SB_G2
:
19145 case BFD_RELOC_ARM_LDC_SB_G0
:
19146 case BFD_RELOC_ARM_LDC_SB_G1
:
19147 case BFD_RELOC_ARM_LDC_SB_G2
:
19148 case BFD_RELOC_ARM_V4BX
:
19149 code
= fixp
->fx_r_type
;
19152 case BFD_RELOC_ARM_TLS_GD32
:
19153 case BFD_RELOC_ARM_TLS_IE32
:
19154 case BFD_RELOC_ARM_TLS_LDM32
:
19155 /* BFD will include the symbol's address in the addend.
19156 But we don't want that, so subtract it out again here. */
19157 if (!S_IS_COMMON (fixp
->fx_addsy
))
19158 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
19159 code
= fixp
->fx_r_type
;
19163 case BFD_RELOC_ARM_IMMEDIATE
:
19164 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19165 _("internal relocation (type: IMMEDIATE) not fixed up"));
19168 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
19169 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19170 _("ADRL used for a symbol not defined in the same file"));
19173 case BFD_RELOC_ARM_OFFSET_IMM
:
19174 if (section
->use_rela_p
)
19176 code
= fixp
->fx_r_type
;
19180 if (fixp
->fx_addsy
!= NULL
19181 && !S_IS_DEFINED (fixp
->fx_addsy
)
19182 && S_IS_LOCAL (fixp
->fx_addsy
))
19184 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19185 _("undefined local label `%s'"),
19186 S_GET_NAME (fixp
->fx_addsy
));
19190 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19191 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
19198 switch (fixp
->fx_r_type
)
19200 case BFD_RELOC_NONE
: type
= "NONE"; break;
19201 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
19202 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
19203 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
19204 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
19205 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
19206 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
19207 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
19208 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
19209 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
19210 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
19211 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
19212 default: type
= _("<unknown>"); break;
19214 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19215 _("cannot represent %s relocation in this object file format"),
19222 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
19224 && fixp
->fx_addsy
== GOT_symbol
)
19226 code
= BFD_RELOC_ARM_GOTPC
;
19227 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
19231 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
19233 if (reloc
->howto
== NULL
)
19235 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19236 _("cannot represent %s relocation in this object file format"),
19237 bfd_get_reloc_code_name (code
));
19241 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
19242 vtable entry to be used in the relocation's section offset. */
19243 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
19244 reloc
->address
= fixp
->fx_offset
;
19249 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
19252 cons_fix_new_arm (fragS
* frag
,
19257 bfd_reloc_code_real_type type
;
19261 FIXME: @@ Should look at CPU word size. */
19265 type
= BFD_RELOC_8
;
19268 type
= BFD_RELOC_16
;
19272 type
= BFD_RELOC_32
;
19275 type
= BFD_RELOC_64
;
19280 if (exp
->X_op
== O_secrel
)
19282 exp
->X_op
= O_symbol
;
19283 type
= BFD_RELOC_32_SECREL
;
19287 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
19290 #if defined OBJ_COFF || defined OBJ_ELF
19292 arm_validate_fix (fixS
* fixP
)
19294 /* If the destination of the branch is a defined symbol which does not have
19295 the THUMB_FUNC attribute, then we must be calling a function which has
19296 the (interfacearm) attribute. We look for the Thumb entry point to that
19297 function and change the branch to refer to that function instead. */
19298 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
19299 && fixP
->fx_addsy
!= NULL
19300 && S_IS_DEFINED (fixP
->fx_addsy
)
19301 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
19303 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
19309 arm_force_relocation (struct fix
* fixp
)
19311 #if defined (OBJ_COFF) && defined (TE_PE)
19312 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
19316 /* Resolve these relocations even if the symbol is extern or weak. */
19317 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
19318 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
19319 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
19320 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
19321 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
19322 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
19323 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
19326 /* Always leave these relocations for the linker. */
19327 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
19328 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
19329 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
19332 /* Always generate relocations against function symbols. */
19333 if (fixp
->fx_r_type
== BFD_RELOC_32
19335 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
19338 return generic_force_reloc (fixp
);
19341 #if defined (OBJ_ELF) || defined (OBJ_COFF)
19342 /* Relocations against function names must be left unadjusted,
19343 so that the linker can use this information to generate interworking
19344 stubs. The MIPS version of this function
19345 also prevents relocations that are mips-16 specific, but I do not
19346 know why it does this.
19349 There is one other problem that ought to be addressed here, but
19350 which currently is not: Taking the address of a label (rather
19351 than a function) and then later jumping to that address. Such
19352 addresses also ought to have their bottom bit set (assuming that
19353 they reside in Thumb code), but at the moment they will not. */
19356 arm_fix_adjustable (fixS
* fixP
)
19358 if (fixP
->fx_addsy
== NULL
)
19361 /* Preserve relocations against symbols with function type. */
19362 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
19365 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
19366 && fixP
->fx_subsy
== NULL
)
19369 /* We need the symbol name for the VTABLE entries. */
19370 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
19371 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
19374 /* Don't allow symbols to be discarded on GOT related relocs. */
19375 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
19376 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
19377 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
19378 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
19379 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
19380 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
19381 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
19382 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
19383 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
19386 /* Similarly for group relocations. */
19387 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
19388 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
19389 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
19394 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
19399 elf32_arm_target_format (void)
19402 return (target_big_endian
19403 ? "elf32-bigarm-symbian"
19404 : "elf32-littlearm-symbian");
19405 #elif defined (TE_VXWORKS)
19406 return (target_big_endian
19407 ? "elf32-bigarm-vxworks"
19408 : "elf32-littlearm-vxworks");
19410 if (target_big_endian
)
19411 return "elf32-bigarm";
19413 return "elf32-littlearm";
19418 armelf_frob_symbol (symbolS
* symp
,
19421 elf_frob_symbol (symp
, puntp
);
19425 /* MD interface: Finalization. */
19427 /* A good place to do this, although this was probably not intended
19428 for this kind of use. We need to dump the literal pool before
19429 references are made to a null symbol pointer. */
19434 literal_pool
* pool
;
19436 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
19438 /* Put it at the end of the relevant section. */
19439 subseg_set (pool
->section
, pool
->sub_section
);
19441 arm_elf_change_section ();
19447 /* Adjust the symbol table. This marks Thumb symbols as distinct from
19451 arm_adjust_symtab (void)
19456 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
19458 if (ARM_IS_THUMB (sym
))
19460 if (THUMB_IS_FUNC (sym
))
19462 /* Mark the symbol as a Thumb function. */
19463 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
19464 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
19465 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
19467 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
19468 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
19470 as_bad (_("%s: unexpected function type: %d"),
19471 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
19473 else switch (S_GET_STORAGE_CLASS (sym
))
19476 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
19479 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
19482 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
19490 if (ARM_IS_INTERWORK (sym
))
19491 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
19498 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
19500 if (ARM_IS_THUMB (sym
))
19502 elf_symbol_type
* elf_sym
;
19504 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
19505 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
19507 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
19508 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
19510 /* If it's a .thumb_func, declare it as so,
19511 otherwise tag label as .code 16. */
19512 if (THUMB_IS_FUNC (sym
))
19513 elf_sym
->internal_elf_sym
.st_info
=
19514 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
19515 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
19516 elf_sym
->internal_elf_sym
.st_info
=
19517 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
19524 /* MD interface: Initialization. */
19527 set_constant_flonums (void)
19531 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
19532 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
19536 /* Auto-select Thumb mode if it's the only available instruction set for the
19537 given architecture. */
19540 autoselect_thumb_from_cpu_variant (void)
19542 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
19543 opcode_select (16);
19552 if ( (arm_ops_hsh
= hash_new ()) == NULL
19553 || (arm_cond_hsh
= hash_new ()) == NULL
19554 || (arm_shift_hsh
= hash_new ()) == NULL
19555 || (arm_psr_hsh
= hash_new ()) == NULL
19556 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
19557 || (arm_reg_hsh
= hash_new ()) == NULL
19558 || (arm_reloc_hsh
= hash_new ()) == NULL
19559 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
19560 as_fatal (_("virtual memory exhausted"));
19562 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
19563 hash_insert (arm_ops_hsh
, insns
[i
].template, (PTR
) (insns
+ i
));
19564 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
19565 hash_insert (arm_cond_hsh
, conds
[i
].template, (PTR
) (conds
+ i
));
19566 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
19567 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (PTR
) (shift_names
+ i
));
19568 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
19569 hash_insert (arm_psr_hsh
, psrs
[i
].template, (PTR
) (psrs
+ i
));
19570 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
19571 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template, (PTR
) (v7m_psrs
+ i
));
19572 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
19573 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (PTR
) (reg_names
+ i
));
19575 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
19577 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template,
19578 (PTR
) (barrier_opt_names
+ i
));
19580 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
19581 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (PTR
) (reloc_names
+ i
));
19584 set_constant_flonums ();
19586 /* Set the cpu variant based on the command-line options. We prefer
19587 -mcpu= over -march= if both are set (as for GCC); and we prefer
19588 -mfpu= over any other way of setting the floating point unit.
19589 Use of legacy options with new options are faulted. */
19592 if (mcpu_cpu_opt
|| march_cpu_opt
)
19593 as_bad (_("use of old and new-style options to set CPU type"));
19595 mcpu_cpu_opt
= legacy_cpu
;
19597 else if (!mcpu_cpu_opt
)
19598 mcpu_cpu_opt
= march_cpu_opt
;
19603 as_bad (_("use of old and new-style options to set FPU type"));
19605 mfpu_opt
= legacy_fpu
;
19607 else if (!mfpu_opt
)
19609 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
19610 /* Some environments specify a default FPU. If they don't, infer it
19611 from the processor. */
19613 mfpu_opt
= mcpu_fpu_opt
;
19615 mfpu_opt
= march_fpu_opt
;
19617 mfpu_opt
= &fpu_default
;
19623 if (mcpu_cpu_opt
!= NULL
)
19624 mfpu_opt
= &fpu_default
;
19625 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
19626 mfpu_opt
= &fpu_arch_vfp_v2
;
19628 mfpu_opt
= &fpu_arch_fpa
;
19634 mcpu_cpu_opt
= &cpu_default
;
19635 selected_cpu
= cpu_default
;
19639 selected_cpu
= *mcpu_cpu_opt
;
19641 mcpu_cpu_opt
= &arm_arch_any
;
19644 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
19646 autoselect_thumb_from_cpu_variant ();
19648 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
19650 #if defined OBJ_COFF || defined OBJ_ELF
19652 unsigned int flags
= 0;
19654 #if defined OBJ_ELF
19655 flags
= meabi_flags
;
19657 switch (meabi_flags
)
19659 case EF_ARM_EABI_UNKNOWN
:
19661 /* Set the flags in the private structure. */
19662 if (uses_apcs_26
) flags
|= F_APCS26
;
19663 if (support_interwork
) flags
|= F_INTERWORK
;
19664 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
19665 if (pic_code
) flags
|= F_PIC
;
19666 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
19667 flags
|= F_SOFT_FLOAT
;
19669 switch (mfloat_abi_opt
)
19671 case ARM_FLOAT_ABI_SOFT
:
19672 case ARM_FLOAT_ABI_SOFTFP
:
19673 flags
|= F_SOFT_FLOAT
;
19676 case ARM_FLOAT_ABI_HARD
:
19677 if (flags
& F_SOFT_FLOAT
)
19678 as_bad (_("hard-float conflicts with specified fpu"));
19682 /* Using pure-endian doubles (even if soft-float). */
19683 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
19684 flags
|= F_VFP_FLOAT
;
19686 #if defined OBJ_ELF
19687 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
19688 flags
|= EF_ARM_MAVERICK_FLOAT
;
19691 case EF_ARM_EABI_VER4
:
19692 case EF_ARM_EABI_VER5
:
19693 /* No additional flags to set. */
19700 bfd_set_private_flags (stdoutput
, flags
);
19702 /* We have run out flags in the COFF header to encode the
19703 status of ATPCS support, so instead we create a dummy,
19704 empty, debug section called .arm.atpcs. */
19709 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
19713 bfd_set_section_flags
19714 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
19715 bfd_set_section_size (stdoutput
, sec
, 0);
19716 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
19722 /* Record the CPU type as well. */
19723 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
19724 mach
= bfd_mach_arm_iWMMXt2
;
19725 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
19726 mach
= bfd_mach_arm_iWMMXt
;
19727 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
19728 mach
= bfd_mach_arm_XScale
;
19729 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
19730 mach
= bfd_mach_arm_ep9312
;
19731 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
19732 mach
= bfd_mach_arm_5TE
;
19733 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
19735 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19736 mach
= bfd_mach_arm_5T
;
19738 mach
= bfd_mach_arm_5
;
19740 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
19742 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19743 mach
= bfd_mach_arm_4T
;
19745 mach
= bfd_mach_arm_4
;
19747 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
19748 mach
= bfd_mach_arm_3M
;
19749 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
19750 mach
= bfd_mach_arm_3
;
19751 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
19752 mach
= bfd_mach_arm_2a
;
19753 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
19754 mach
= bfd_mach_arm_2
;
19756 mach
= bfd_mach_arm_unknown
;
19758 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
19761 /* Command line processing. */
19764 Invocation line includes a switch not recognized by the base assembler.
19765 See if it's a processor-specific option.
19767 This routine is somewhat complicated by the need for backwards
19768 compatibility (since older releases of gcc can't be changed).
19769 The new options try to make the interface as compatible as
19772 New options (supported) are:
19774 -mcpu=<cpu name> Assemble for selected processor
19775 -march=<architecture name> Assemble for selected architecture
19776 -mfpu=<fpu architecture> Assemble for selected FPU.
19777 -EB/-mbig-endian Big-endian
19778 -EL/-mlittle-endian Little-endian
19779 -k Generate PIC code
19780 -mthumb Start in Thumb mode
19781 -mthumb-interwork Code supports ARM/Thumb interworking
19783 For now we will also provide support for:
19785 -mapcs-32 32-bit Program counter
19786 -mapcs-26 26-bit Program counter
19787 -macps-float Floats passed in FP registers
19788 -mapcs-reentrant Reentrant code
19790 (sometime these will probably be replaced with -mapcs=<list of options>
19791 and -matpcs=<list of options>)
19793 The remaining options are only supported for back-wards compatibility.
19794 Cpu variants, the arm part is optional:
19795 -m[arm]1 Currently not supported.
19796 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
19797 -m[arm]3 Arm 3 processor
19798 -m[arm]6[xx], Arm 6 processors
19799 -m[arm]7[xx][t][[d]m] Arm 7 processors
19800 -m[arm]8[10] Arm 8 processors
19801 -m[arm]9[20][tdmi] Arm 9 processors
19802 -mstrongarm[110[0]] StrongARM processors
19803 -mxscale XScale processors
19804 -m[arm]v[2345[t[e]]] Arm architectures
19805 -mall All (except the ARM1)
19807 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
19808 -mfpe-old (No float load/store multiples)
19809 -mvfpxd VFP Single precision
19811 -mno-fpu Disable all floating point instructions
19813 The following CPU names are recognized:
19814 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
19815 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
19816 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
19817 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
19818 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
19819 arm10t arm10e, arm1020t, arm1020e, arm10200e,
19820 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
19824 const char * md_shortopts
= "m:k";
19826 #ifdef ARM_BI_ENDIAN
19827 #define OPTION_EB (OPTION_MD_BASE + 0)
19828 #define OPTION_EL (OPTION_MD_BASE + 1)
19830 #if TARGET_BYTES_BIG_ENDIAN
19831 #define OPTION_EB (OPTION_MD_BASE + 0)
19833 #define OPTION_EL (OPTION_MD_BASE + 1)
19836 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
19838 struct option md_longopts
[] =
19841 {"EB", no_argument
, NULL
, OPTION_EB
},
19844 {"EL", no_argument
, NULL
, OPTION_EL
},
19846 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
19847 {NULL
, no_argument
, NULL
, 0}
19850 size_t md_longopts_size
= sizeof (md_longopts
);
19852 struct arm_option_table
19854 char *option
; /* Option name to match. */
19855 char *help
; /* Help information. */
19856 int *var
; /* Variable to change. */
19857 int value
; /* What to change it to. */
19858 char *deprecated
; /* If non-null, print this message. */
19861 struct arm_option_table arm_opts
[] =
19863 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
19864 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
19865 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
19866 &support_interwork
, 1, NULL
},
19867 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
19868 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
19869 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
19871 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
19872 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
19873 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
19874 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
19877 /* These are recognized by the assembler, but have no affect on code. */
19878 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
19879 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
19880 {NULL
, NULL
, NULL
, 0, NULL
}
19883 struct arm_legacy_option_table
19885 char *option
; /* Option name to match. */
19886 const arm_feature_set
**var
; /* Variable to change. */
19887 const arm_feature_set value
; /* What to change it to. */
19888 char *deprecated
; /* If non-null, print this message. */
19891 const struct arm_legacy_option_table arm_legacy_opts
[] =
19893 /* DON'T add any new processors to this list -- we want the whole list
19894 to go away... Add them to the processors table instead. */
19895 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19896 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19897 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19898 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19899 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19900 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19901 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19902 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19903 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19904 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19905 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19906 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19907 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19908 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19909 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19910 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19911 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19912 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19913 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19914 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19915 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19916 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19917 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19918 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19919 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19920 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19921 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19922 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19923 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19924 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19925 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19926 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19927 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19928 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19929 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19930 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19931 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19932 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19933 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19934 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19935 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19936 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19937 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19938 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19939 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19940 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19941 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19942 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19943 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19944 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19945 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19946 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19947 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19948 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19949 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19950 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19951 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19952 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19953 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19954 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19955 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19956 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19957 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19958 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19959 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19960 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19961 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19962 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19963 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
19964 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
19965 N_("use -mcpu=strongarm110")},
19966 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
19967 N_("use -mcpu=strongarm1100")},
19968 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
19969 N_("use -mcpu=strongarm1110")},
19970 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
19971 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
19972 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
19974 /* Architecture variants -- don't add any more to this list either. */
19975 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19976 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19977 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19978 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19979 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19980 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19981 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19982 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19983 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19984 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19985 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
19986 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
19987 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
19988 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
19989 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
19990 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
19991 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
19992 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
19994 /* Floating point variants -- don't add any more to this list either. */
19995 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
19996 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
19997 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
19998 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
19999 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
20001 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
20004 struct arm_cpu_option_table
20007 const arm_feature_set value
;
20008 /* For some CPUs we assume an FPU unless the user explicitly sets
20010 const arm_feature_set default_fpu
;
20011 /* The canonical name of the CPU, or NULL to use NAME converted to upper
20013 const char *canonical_name
;
20016 /* This list should, at a minimum, contain all the cpu names
20017 recognized by GCC. */
20018 static const struct arm_cpu_option_table arm_cpus
[] =
20020 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
20021 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
20022 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
20023 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
20024 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
20025 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20026 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20027 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20028 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20029 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20030 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20031 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20032 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20033 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20034 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20035 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20036 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20037 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20038 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20039 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20040 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20041 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20042 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20043 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20044 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20045 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20046 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20047 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20048 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20049 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20050 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20051 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20052 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20053 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20054 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20055 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20056 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20057 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20058 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20059 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
20060 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20061 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20062 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20063 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20064 /* For V5 or later processors we default to using VFP; but the user
20065 should really set the FPU type explicitly. */
20066 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20067 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20068 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
20069 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
20070 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
20071 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20072 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
20073 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20074 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20075 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
20076 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20077 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20078 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20079 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20080 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20081 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
20082 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20083 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20084 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20085 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
20086 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
20087 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
20088 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
20089 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
20090 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
20091 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
20092 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
20093 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
20094 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
20095 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
20096 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
20097 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE(0, FPU_VFP_V3
20098 | FPU_NEON_EXT_V1
),
20100 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
20101 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
20102 /* ??? XSCALE is really an architecture. */
20103 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
20104 /* ??? iwmmxt is not a processor. */
20105 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
20106 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
20107 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
20109 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
20110 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
20113 struct arm_arch_option_table
20116 const arm_feature_set value
;
20117 const arm_feature_set default_fpu
;
20120 /* This list should, at a minimum, contain all the architecture names
20121 recognized by GCC. */
20122 static const struct arm_arch_option_table arm_archs
[] =
20124 {"all", ARM_ANY
, FPU_ARCH_FPA
},
20125 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
20126 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
20127 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
20128 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
20129 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
20130 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
20131 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
20132 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
20133 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
20134 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
20135 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
20136 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
20137 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
20138 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
20139 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
20140 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
20141 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
20142 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
20143 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
20144 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
20145 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
20146 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
20147 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
20148 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
20149 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
20150 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
20151 /* The official spelling of the ARMv7 profile variants is the dashed form.
20152 Accept the non-dashed form for compatibility with old toolchains. */
20153 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
20154 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
20155 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
20156 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
20157 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
20158 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
20159 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
20160 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
20161 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
20162 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
20165 /* ISA extensions in the co-processor space. */
20166 struct arm_option_cpu_value_table
20169 const arm_feature_set value
;
20172 static const struct arm_option_cpu_value_table arm_extensions
[] =
20174 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
20175 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
20176 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
20177 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
20178 {NULL
, ARM_ARCH_NONE
}
20181 /* This list should, at a minimum, contain all the fpu names
20182 recognized by GCC. */
20183 static const struct arm_option_cpu_value_table arm_fpus
[] =
20185 {"softfpa", FPU_NONE
},
20186 {"fpe", FPU_ARCH_FPE
},
20187 {"fpe2", FPU_ARCH_FPE
},
20188 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
20189 {"fpa", FPU_ARCH_FPA
},
20190 {"fpa10", FPU_ARCH_FPA
},
20191 {"fpa11", FPU_ARCH_FPA
},
20192 {"arm7500fe", FPU_ARCH_FPA
},
20193 {"softvfp", FPU_ARCH_VFP
},
20194 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
20195 {"vfp", FPU_ARCH_VFP_V2
},
20196 {"vfp9", FPU_ARCH_VFP_V2
},
20197 {"vfp3", FPU_ARCH_VFP_V3
},
20198 {"vfp10", FPU_ARCH_VFP_V2
},
20199 {"vfp10-r0", FPU_ARCH_VFP_V1
},
20200 {"vfpxd", FPU_ARCH_VFP_V1xD
},
20201 {"arm1020t", FPU_ARCH_VFP_V1
},
20202 {"arm1020e", FPU_ARCH_VFP_V2
},
20203 {"arm1136jfs", FPU_ARCH_VFP_V2
},
20204 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
20205 {"maverick", FPU_ARCH_MAVERICK
},
20206 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
20207 {NULL
, ARM_ARCH_NONE
}
20210 struct arm_option_value_table
20216 static const struct arm_option_value_table arm_float_abis
[] =
20218 {"hard", ARM_FLOAT_ABI_HARD
},
20219 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
20220 {"soft", ARM_FLOAT_ABI_SOFT
},
20225 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
20226 static const struct arm_option_value_table arm_eabis
[] =
20228 {"gnu", EF_ARM_EABI_UNKNOWN
},
20229 {"4", EF_ARM_EABI_VER4
},
20230 {"5", EF_ARM_EABI_VER5
},
20235 struct arm_long_option_table
20237 char * option
; /* Substring to match. */
20238 char * help
; /* Help information. */
20239 int (* func
) (char * subopt
); /* Function to decode sub-option. */
20240 char * deprecated
; /* If non-null, print this message. */
20244 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
20246 arm_feature_set
*ext_set
= xmalloc (sizeof (arm_feature_set
));
20248 /* Copy the feature set, so that we can modify it. */
20249 *ext_set
= **opt_p
;
20252 while (str
!= NULL
&& *str
!= 0)
20254 const struct arm_option_cpu_value_table
* opt
;
20260 as_bad (_("invalid architectural extension"));
20265 ext
= strchr (str
, '+');
20268 optlen
= ext
- str
;
20270 optlen
= strlen (str
);
20274 as_bad (_("missing architectural extension"));
20278 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
20279 if (strncmp (opt
->name
, str
, optlen
) == 0)
20281 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
20285 if (opt
->name
== NULL
)
20287 as_bad (_("unknown architectural extension `%s'"), str
);
20298 arm_parse_cpu (char * str
)
20300 const struct arm_cpu_option_table
* opt
;
20301 char * ext
= strchr (str
, '+');
20305 optlen
= ext
- str
;
20307 optlen
= strlen (str
);
20311 as_bad (_("missing cpu name `%s'"), str
);
20315 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
20316 if (strncmp (opt
->name
, str
, optlen
) == 0)
20318 mcpu_cpu_opt
= &opt
->value
;
20319 mcpu_fpu_opt
= &opt
->default_fpu
;
20320 if (opt
->canonical_name
)
20321 strcpy (selected_cpu_name
, opt
->canonical_name
);
20325 for (i
= 0; i
< optlen
; i
++)
20326 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20327 selected_cpu_name
[i
] = 0;
20331 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
20336 as_bad (_("unknown cpu `%s'"), str
);
20341 arm_parse_arch (char * str
)
20343 const struct arm_arch_option_table
*opt
;
20344 char *ext
= strchr (str
, '+');
20348 optlen
= ext
- str
;
20350 optlen
= strlen (str
);
20354 as_bad (_("missing architecture name `%s'"), str
);
20358 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
20359 if (streq (opt
->name
, str
))
20361 march_cpu_opt
= &opt
->value
;
20362 march_fpu_opt
= &opt
->default_fpu
;
20363 strcpy (selected_cpu_name
, opt
->name
);
20366 return arm_parse_extension (ext
, &march_cpu_opt
);
20371 as_bad (_("unknown architecture `%s'\n"), str
);
20376 arm_parse_fpu (char * str
)
20378 const struct arm_option_cpu_value_table
* opt
;
20380 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
20381 if (streq (opt
->name
, str
))
20383 mfpu_opt
= &opt
->value
;
20387 as_bad (_("unknown floating point format `%s'\n"), str
);
20392 arm_parse_float_abi (char * str
)
20394 const struct arm_option_value_table
* opt
;
20396 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
20397 if (streq (opt
->name
, str
))
20399 mfloat_abi_opt
= opt
->value
;
20403 as_bad (_("unknown floating point abi `%s'\n"), str
);
20409 arm_parse_eabi (char * str
)
20411 const struct arm_option_value_table
*opt
;
20413 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
20414 if (streq (opt
->name
, str
))
20416 meabi_flags
= opt
->value
;
20419 as_bad (_("unknown EABI `%s'\n"), str
);
20424 struct arm_long_option_table arm_long_opts
[] =
20426 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
20427 arm_parse_cpu
, NULL
},
20428 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
20429 arm_parse_arch
, NULL
},
20430 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
20431 arm_parse_fpu
, NULL
},
20432 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
20433 arm_parse_float_abi
, NULL
},
20435 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
20436 arm_parse_eabi
, NULL
},
20438 {NULL
, NULL
, 0, NULL
}
20442 md_parse_option (int c
, char * arg
)
20444 struct arm_option_table
*opt
;
20445 const struct arm_legacy_option_table
*fopt
;
20446 struct arm_long_option_table
*lopt
;
20452 target_big_endian
= 1;
20458 target_big_endian
= 0;
20462 case OPTION_FIX_V4BX
:
20467 /* Listing option. Just ignore these, we don't support additional
20472 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
20474 if (c
== opt
->option
[0]
20475 && ((arg
== NULL
&& opt
->option
[1] == 0)
20476 || streq (arg
, opt
->option
+ 1)))
20478 #if WARN_DEPRECATED
20479 /* If the option is deprecated, tell the user. */
20480 if (opt
->deprecated
!= NULL
)
20481 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
20482 arg
? arg
: "", _(opt
->deprecated
));
20485 if (opt
->var
!= NULL
)
20486 *opt
->var
= opt
->value
;
20492 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
20494 if (c
== fopt
->option
[0]
20495 && ((arg
== NULL
&& fopt
->option
[1] == 0)
20496 || streq (arg
, fopt
->option
+ 1)))
20498 #if WARN_DEPRECATED
20499 /* If the option is deprecated, tell the user. */
20500 if (fopt
->deprecated
!= NULL
)
20501 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
20502 arg
? arg
: "", _(fopt
->deprecated
));
20505 if (fopt
->var
!= NULL
)
20506 *fopt
->var
= &fopt
->value
;
20512 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
20514 /* These options are expected to have an argument. */
20515 if (c
== lopt
->option
[0]
20517 && strncmp (arg
, lopt
->option
+ 1,
20518 strlen (lopt
->option
+ 1)) == 0)
20520 #if WARN_DEPRECATED
20521 /* If the option is deprecated, tell the user. */
20522 if (lopt
->deprecated
!= NULL
)
20523 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
20524 _(lopt
->deprecated
));
20527 /* Call the sup-option parser. */
20528 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
20539 md_show_usage (FILE * fp
)
20541 struct arm_option_table
*opt
;
20542 struct arm_long_option_table
*lopt
;
20544 fprintf (fp
, _(" ARM-specific assembler options:\n"));
20546 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
20547 if (opt
->help
!= NULL
)
20548 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
20550 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
20551 if (lopt
->help
!= NULL
)
20552 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
20556 -EB assemble code for a big-endian cpu\n"));
20561 -EL assemble code for a little-endian cpu\n"));
20565 --fix-v4bx Allow BX in ARMv4 code\n"));
20573 arm_feature_set flags
;
20574 } cpu_arch_ver_table
;
20576 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
20577 least features first. */
20578 static const cpu_arch_ver_table cpu_arch_ver
[] =
20583 {4, ARM_ARCH_V5TE
},
20584 {5, ARM_ARCH_V5TEJ
},
20588 {9, ARM_ARCH_V6T2
},
20589 {10, ARM_ARCH_V7A
},
20590 {10, ARM_ARCH_V7R
},
20591 {10, ARM_ARCH_V7M
},
20595 /* Set the public EABI object attributes. */
20597 aeabi_set_public_attributes (void)
20600 arm_feature_set flags
;
20601 arm_feature_set tmp
;
20602 const cpu_arch_ver_table
*p
;
20604 /* Choose the architecture based on the capabilities of the requested cpu
20605 (if any) and/or the instructions actually used. */
20606 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
20607 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
20608 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
20609 /*Allow the user to override the reported architecture. */
20612 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
20613 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
20618 for (p
= cpu_arch_ver
; p
->val
; p
++)
20620 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
20623 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
20627 /* Tag_CPU_name. */
20628 if (selected_cpu_name
[0])
20632 p
= selected_cpu_name
;
20633 if (strncmp (p
, "armv", 4) == 0)
20638 for (i
= 0; p
[i
]; i
++)
20639 p
[i
] = TOUPPER (p
[i
]);
20641 bfd_elf_add_proc_attr_string (stdoutput
, 5, p
);
20643 /* Tag_CPU_arch. */
20644 bfd_elf_add_proc_attr_int (stdoutput
, 6, arch
);
20645 /* Tag_CPU_arch_profile. */
20646 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
20647 bfd_elf_add_proc_attr_int (stdoutput
, 7, 'A');
20648 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
20649 bfd_elf_add_proc_attr_int (stdoutput
, 7, 'R');
20650 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
))
20651 bfd_elf_add_proc_attr_int (stdoutput
, 7, 'M');
20652 /* Tag_ARM_ISA_use. */
20653 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_full
))
20654 bfd_elf_add_proc_attr_int (stdoutput
, 8, 1);
20655 /* Tag_THUMB_ISA_use. */
20656 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_full
))
20657 bfd_elf_add_proc_attr_int (stdoutput
, 9,
20658 ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
) ? 2 : 1);
20659 /* Tag_VFP_arch. */
20660 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v3
)
20661 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v3
))
20662 bfd_elf_add_proc_attr_int (stdoutput
, 10, 3);
20663 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v2
)
20664 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v2
))
20665 bfd_elf_add_proc_attr_int (stdoutput
, 10, 2);
20666 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1
)
20667 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1
)
20668 || ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1xd
)
20669 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1xd
))
20670 bfd_elf_add_proc_attr_int (stdoutput
, 10, 1);
20671 /* Tag_WMMX_arch. */
20672 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_cext_iwmmxt
)
20673 || ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_cext_iwmmxt
))
20674 bfd_elf_add_proc_attr_int (stdoutput
, 11, 1);
20675 /* Tag_NEON_arch. */
20676 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_neon_ext_v1
)
20677 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_neon_ext_v1
))
20678 bfd_elf_add_proc_attr_int (stdoutput
, 12, 1);
20681 /* Add the default contents for the .ARM.attributes section. */
20685 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
20688 aeabi_set_public_attributes ();
20690 #endif /* OBJ_ELF */
20693 /* Parse a .cpu directive. */
20696 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
20698 const struct arm_cpu_option_table
*opt
;
20702 name
= input_line_pointer
;
20703 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20704 input_line_pointer
++;
20705 saved_char
= *input_line_pointer
;
20706 *input_line_pointer
= 0;
20708 /* Skip the first "all" entry. */
20709 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
20710 if (streq (opt
->name
, name
))
20712 mcpu_cpu_opt
= &opt
->value
;
20713 selected_cpu
= opt
->value
;
20714 if (opt
->canonical_name
)
20715 strcpy (selected_cpu_name
, opt
->canonical_name
);
20719 for (i
= 0; opt
->name
[i
]; i
++)
20720 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20721 selected_cpu_name
[i
] = 0;
20723 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20724 *input_line_pointer
= saved_char
;
20725 demand_empty_rest_of_line ();
20728 as_bad (_("unknown cpu `%s'"), name
);
20729 *input_line_pointer
= saved_char
;
20730 ignore_rest_of_line ();
20734 /* Parse a .arch directive. */
20737 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
20739 const struct arm_arch_option_table
*opt
;
20743 name
= input_line_pointer
;
20744 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20745 input_line_pointer
++;
20746 saved_char
= *input_line_pointer
;
20747 *input_line_pointer
= 0;
20749 /* Skip the first "all" entry. */
20750 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
20751 if (streq (opt
->name
, name
))
20753 mcpu_cpu_opt
= &opt
->value
;
20754 selected_cpu
= opt
->value
;
20755 strcpy (selected_cpu_name
, opt
->name
);
20756 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20757 *input_line_pointer
= saved_char
;
20758 demand_empty_rest_of_line ();
20762 as_bad (_("unknown architecture `%s'\n"), name
);
20763 *input_line_pointer
= saved_char
;
20764 ignore_rest_of_line ();
20768 /* Parse a .object_arch directive. */
20771 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
20773 const struct arm_arch_option_table
*opt
;
20777 name
= input_line_pointer
;
20778 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20779 input_line_pointer
++;
20780 saved_char
= *input_line_pointer
;
20781 *input_line_pointer
= 0;
20783 /* Skip the first "all" entry. */
20784 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
20785 if (streq (opt
->name
, name
))
20787 object_arch
= &opt
->value
;
20788 *input_line_pointer
= saved_char
;
20789 demand_empty_rest_of_line ();
20793 as_bad (_("unknown architecture `%s'\n"), name
);
20794 *input_line_pointer
= saved_char
;
20795 ignore_rest_of_line ();
20799 /* Parse a .fpu directive. */
20802 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
20804 const struct arm_option_cpu_value_table
*opt
;
20808 name
= input_line_pointer
;
20809 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20810 input_line_pointer
++;
20811 saved_char
= *input_line_pointer
;
20812 *input_line_pointer
= 0;
20814 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
20815 if (streq (opt
->name
, name
))
20817 mfpu_opt
= &opt
->value
;
20818 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20819 *input_line_pointer
= saved_char
;
20820 demand_empty_rest_of_line ();
20824 as_bad (_("unknown floating point format `%s'\n"), name
);
20825 *input_line_pointer
= saved_char
;
20826 ignore_rest_of_line ();
20829 /* Copy symbol information. */
20831 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
20833 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);