1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
45 #define WARN_DEPRECATED 1
48 /* Must be at least the size of the largest unwind opcode (currently two). */
49 #define ARM_OPCODE_CHUNK_SIZE 8
51 /* This structure holds the unwinding state. */
56 symbolS
* table_entry
;
57 symbolS
* personality_routine
;
58 int personality_index
;
59 /* The segment containing the function. */
62 /* Opcodes generated from this function. */
63 unsigned char * opcodes
;
66 /* The number of bytes pushed to the stack. */
68 /* We don't add stack adjustment opcodes immediately so that we can merge
69 multiple adjustments. We can also omit the final adjustment
70 when using a frame pointer. */
71 offsetT pending_offset
;
72 /* These two fields are set by both unwind_movsp and unwind_setfp. They
73 hold the reg+offset to use when restoring sp from a frame pointer. */
76 /* Nonzero if an unwind_setfp directive has been seen. */
78 /* Nonzero if the last opcode restores sp from fp_reg. */
79 unsigned sp_restored
:1;
82 /* Bit N indicates that an R_ARM_NONE relocation has been output for
83 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
84 emitted only once per section, to save unnecessary bloat. */
85 static unsigned int marked_pr_dependency
= 0;
89 /* Results from operand parsing worker functions. */
93 PARSE_OPERAND_SUCCESS
,
95 PARSE_OPERAND_FAIL_NO_BACKTRACK
96 } parse_operand_result
;
101 ARM_FLOAT_ABI_SOFTFP
,
105 /* Types of processor to assemble for. */
107 #if defined __XSCALE__
108 #define CPU_DEFAULT ARM_ARCH_XSCALE
110 #if defined __thumb__
111 #define CPU_DEFAULT ARM_ARCH_V5T
118 # define FPU_DEFAULT FPU_ARCH_FPA
119 # elif defined (TE_NetBSD)
121 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
123 /* Legacy a.out format. */
124 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
126 # elif defined (TE_VXWORKS)
127 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
129 /* For backwards compatibility, default to FPA. */
130 # define FPU_DEFAULT FPU_ARCH_FPA
132 #endif /* ifndef FPU_DEFAULT */
134 #define streq(a, b) (strcmp (a, b) == 0)
136 static arm_feature_set cpu_variant
;
137 static arm_feature_set arm_arch_used
;
138 static arm_feature_set thumb_arch_used
;
140 /* Flags stored in private area of BFD structure. */
141 static int uses_apcs_26
= FALSE
;
142 static int atpcs
= FALSE
;
143 static int support_interwork
= FALSE
;
144 static int uses_apcs_float
= FALSE
;
145 static int pic_code
= FALSE
;
147 /* Variables that we set while parsing command-line options. Once all
148 options have been read we re-process these values to set the real
150 static const arm_feature_set
*legacy_cpu
= NULL
;
151 static const arm_feature_set
*legacy_fpu
= NULL
;
153 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
154 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
155 static const arm_feature_set
*march_cpu_opt
= NULL
;
156 static const arm_feature_set
*march_fpu_opt
= NULL
;
157 static const arm_feature_set
*mfpu_opt
= NULL
;
158 static const arm_feature_set
*object_arch
= NULL
;
160 /* Constants for known architecture features. */
161 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
162 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
163 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
164 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
165 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
166 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
167 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
168 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
169 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
172 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
175 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
176 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
177 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
178 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
179 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
180 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
181 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
182 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
183 static const arm_feature_set arm_ext_v4t_5
=
184 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
185 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
186 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
187 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
188 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
189 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
190 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
191 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
192 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
193 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
194 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
195 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
196 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
197 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
198 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
200 static const arm_feature_set arm_arch_any
= ARM_ANY
;
201 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
202 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
203 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
205 static const arm_feature_set arm_cext_iwmmxt2
=
206 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
207 static const arm_feature_set arm_cext_iwmmxt
=
208 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
209 static const arm_feature_set arm_cext_xscale
=
210 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
211 static const arm_feature_set arm_cext_maverick
=
212 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
213 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
214 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
215 static const arm_feature_set fpu_vfp_ext_v1xd
=
216 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
217 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
218 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
219 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
220 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
221 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
222 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
224 static int mfloat_abi_opt
= -1;
225 /* Record user cpu selection for object attributes. */
226 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
227 /* Must be long enough to hold any of the names in arm_cpus. */
228 static char selected_cpu_name
[16];
231 static int meabi_flags
= EABI_DEFAULT
;
233 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
239 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
244 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
245 symbolS
* GOT_symbol
;
248 /* 0: assemble for ARM,
249 1: assemble for Thumb,
250 2: assemble for Thumb even though target CPU does not support thumb
252 static int thumb_mode
= 0;
254 /* If unified_syntax is true, we are processing the new unified
255 ARM/Thumb syntax. Important differences from the old ARM mode:
257 - Immediate operands do not require a # prefix.
258 - Conditional affixes always appear at the end of the
259 instruction. (For backward compatibility, those instructions
260 that formerly had them in the middle, continue to accept them
262 - The IT instruction may appear, and if it does is validated
263 against subsequent conditional affixes. It does not generate
266 Important differences from the old Thumb mode:
268 - Immediate operands do not require a # prefix.
269 - Most of the V6T2 instructions are only available in unified mode.
270 - The .N and .W suffixes are recognized and honored (it is an error
271 if they cannot be honored).
272 - All instructions set the flags if and only if they have an 's' affix.
273 - Conditional affixes may be used. They are validated against
274 preceding IT instructions. Unlike ARM mode, you cannot use a
275 conditional affix except in the scope of an IT instruction. */
277 static bfd_boolean unified_syntax
= FALSE
;
292 enum neon_el_type type
;
296 #define NEON_MAX_TYPE_ELS 4
300 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
307 unsigned long instruction
;
311 /* "uncond_value" is set to the value in place of the conditional field in
312 unconditional versions of the instruction, or -1 if nothing is
315 struct neon_type vectype
;
316 /* Set to the opcode if the instruction needs relaxation.
317 Zero if the instruction is not relaxed. */
321 bfd_reloc_code_real_type type
;
330 struct neon_type_el vectype
;
331 unsigned present
: 1; /* Operand present. */
332 unsigned isreg
: 1; /* Operand was a register. */
333 unsigned immisreg
: 1; /* .imm field is a second register. */
334 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
335 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
336 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
337 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
338 instructions. This allows us to disambiguate ARM <-> vector insns. */
339 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
340 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
341 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
342 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
343 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
344 unsigned writeback
: 1; /* Operand has trailing ! */
345 unsigned preind
: 1; /* Preindexed address. */
346 unsigned postind
: 1; /* Postindexed address. */
347 unsigned negative
: 1; /* Index register was negated. */
348 unsigned shifted
: 1; /* Shift applied to operation. */
349 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
353 static struct arm_it inst
;
355 #define NUM_FLOAT_VALS 8
357 const char * fp_const
[] =
359 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
362 /* Number of littlenums required to hold an extended precision number. */
363 #define MAX_LITTLENUMS 6
365 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
375 #define CP_T_X 0x00008000
376 #define CP_T_Y 0x00400000
378 #define CONDS_BIT 0x00100000
379 #define LOAD_BIT 0x00100000
381 #define DOUBLE_LOAD_FLAG 0x00000001
385 const char * template;
389 #define COND_ALWAYS 0xE
393 const char *template;
397 struct asm_barrier_opt
399 const char *template;
403 /* The bit that distinguishes CPSR and SPSR. */
404 #define SPSR_BIT (1 << 22)
406 /* The individual PSR flag bits. */
407 #define PSR_c (1 << 16)
408 #define PSR_x (1 << 17)
409 #define PSR_s (1 << 18)
410 #define PSR_f (1 << 19)
415 bfd_reloc_code_real_type reloc
;
420 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
421 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
426 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
429 /* Bits for DEFINED field in neon_typed_alias. */
430 #define NTA_HASTYPE 1
431 #define NTA_HASINDEX 2
433 struct neon_typed_alias
435 unsigned char defined
;
437 struct neon_type_el eltype
;
440 /* ARM register categories. This includes coprocessor numbers and various
441 architecture extensions' registers. */
467 /* Structure for a hash table entry for a register.
468 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
469 information which states whether a vector type or index is specified (for a
470 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
474 unsigned char number
;
476 unsigned char builtin
;
477 struct neon_typed_alias
*neon
;
480 /* Diagnostics used when we don't get a register of the expected type. */
481 const char *const reg_expected_msgs
[] =
483 N_("ARM register expected"),
484 N_("bad or missing co-processor number"),
485 N_("co-processor register expected"),
486 N_("FPA register expected"),
487 N_("VFP single precision register expected"),
488 N_("VFP/Neon double precision register expected"),
489 N_("Neon quad precision register expected"),
490 N_("VFP single or double precision register expected"),
491 N_("Neon double or quad precision register expected"),
492 N_("VFP single, double or Neon quad precision register expected"),
493 N_("VFP system register expected"),
494 N_("Maverick MVF register expected"),
495 N_("Maverick MVD register expected"),
496 N_("Maverick MVFX register expected"),
497 N_("Maverick MVDX register expected"),
498 N_("Maverick MVAX register expected"),
499 N_("Maverick DSPSC register expected"),
500 N_("iWMMXt data register expected"),
501 N_("iWMMXt control register expected"),
502 N_("iWMMXt scalar register expected"),
503 N_("XScale accumulator register expected"),
506 /* Some well known registers that we refer to directly elsewhere. */
511 /* ARM instructions take 4bytes in the object file, Thumb instructions
517 /* Basic string to match. */
518 const char *template;
520 /* Parameters to instruction. */
521 unsigned char operands
[8];
523 /* Conditional tag - see opcode_lookup. */
524 unsigned int tag
: 4;
526 /* Basic instruction code. */
527 unsigned int avalue
: 28;
529 /* Thumb-format instruction code. */
532 /* Which architecture variant provides this instruction. */
533 const arm_feature_set
*avariant
;
534 const arm_feature_set
*tvariant
;
536 /* Function to call to encode instruction in ARM format. */
537 void (* aencode
) (void);
539 /* Function to call to encode instruction in Thumb format. */
540 void (* tencode
) (void);
543 /* Defines for various bits that we will want to toggle. */
544 #define INST_IMMEDIATE 0x02000000
545 #define OFFSET_REG 0x02000000
546 #define HWOFFSET_IMM 0x00400000
547 #define SHIFT_BY_REG 0x00000010
548 #define PRE_INDEX 0x01000000
549 #define INDEX_UP 0x00800000
550 #define WRITE_BACK 0x00200000
551 #define LDM_TYPE_2_OR_3 0x00400000
552 #define CPSI_MMOD 0x00020000
554 #define LITERAL_MASK 0xf000f000
555 #define OPCODE_MASK 0xfe1fffff
556 #define V4_STR_BIT 0x00000020
558 #define T2_SUBS_PC_LR 0xf3de8f00
560 #define DATA_OP_SHIFT 21
562 #define T2_OPCODE_MASK 0xfe1fffff
563 #define T2_DATA_OP_SHIFT 21
565 /* Codes to distinguish the arithmetic instructions. */
576 #define OPCODE_CMP 10
577 #define OPCODE_CMN 11
578 #define OPCODE_ORR 12
579 #define OPCODE_MOV 13
580 #define OPCODE_BIC 14
581 #define OPCODE_MVN 15
583 #define T2_OPCODE_AND 0
584 #define T2_OPCODE_BIC 1
585 #define T2_OPCODE_ORR 2
586 #define T2_OPCODE_ORN 3
587 #define T2_OPCODE_EOR 4
588 #define T2_OPCODE_ADD 8
589 #define T2_OPCODE_ADC 10
590 #define T2_OPCODE_SBC 11
591 #define T2_OPCODE_SUB 13
592 #define T2_OPCODE_RSB 14
594 #define T_OPCODE_MUL 0x4340
595 #define T_OPCODE_TST 0x4200
596 #define T_OPCODE_CMN 0x42c0
597 #define T_OPCODE_NEG 0x4240
598 #define T_OPCODE_MVN 0x43c0
600 #define T_OPCODE_ADD_R3 0x1800
601 #define T_OPCODE_SUB_R3 0x1a00
602 #define T_OPCODE_ADD_HI 0x4400
603 #define T_OPCODE_ADD_ST 0xb000
604 #define T_OPCODE_SUB_ST 0xb080
605 #define T_OPCODE_ADD_SP 0xa800
606 #define T_OPCODE_ADD_PC 0xa000
607 #define T_OPCODE_ADD_I8 0x3000
608 #define T_OPCODE_SUB_I8 0x3800
609 #define T_OPCODE_ADD_I3 0x1c00
610 #define T_OPCODE_SUB_I3 0x1e00
612 #define T_OPCODE_ASR_R 0x4100
613 #define T_OPCODE_LSL_R 0x4080
614 #define T_OPCODE_LSR_R 0x40c0
615 #define T_OPCODE_ROR_R 0x41c0
616 #define T_OPCODE_ASR_I 0x1000
617 #define T_OPCODE_LSL_I 0x0000
618 #define T_OPCODE_LSR_I 0x0800
620 #define T_OPCODE_MOV_I8 0x2000
621 #define T_OPCODE_CMP_I8 0x2800
622 #define T_OPCODE_CMP_LR 0x4280
623 #define T_OPCODE_MOV_HR 0x4600
624 #define T_OPCODE_CMP_HR 0x4500
626 #define T_OPCODE_LDR_PC 0x4800
627 #define T_OPCODE_LDR_SP 0x9800
628 #define T_OPCODE_STR_SP 0x9000
629 #define T_OPCODE_LDR_IW 0x6800
630 #define T_OPCODE_STR_IW 0x6000
631 #define T_OPCODE_LDR_IH 0x8800
632 #define T_OPCODE_STR_IH 0x8000
633 #define T_OPCODE_LDR_IB 0x7800
634 #define T_OPCODE_STR_IB 0x7000
635 #define T_OPCODE_LDR_RW 0x5800
636 #define T_OPCODE_STR_RW 0x5000
637 #define T_OPCODE_LDR_RH 0x5a00
638 #define T_OPCODE_STR_RH 0x5200
639 #define T_OPCODE_LDR_RB 0x5c00
640 #define T_OPCODE_STR_RB 0x5400
642 #define T_OPCODE_PUSH 0xb400
643 #define T_OPCODE_POP 0xbc00
645 #define T_OPCODE_BRANCH 0xe000
647 #define THUMB_SIZE 2 /* Size of thumb instruction. */
648 #define THUMB_PP_PC_LR 0x0100
649 #define THUMB_LOAD_BIT 0x0800
650 #define THUMB2_LOAD_BIT 0x00100000
652 #define BAD_ARGS _("bad arguments to instruction")
653 #define BAD_PC _("r15 not allowed here")
654 #define BAD_COND _("instruction cannot be conditional")
655 #define BAD_OVERLAP _("registers may not be the same")
656 #define BAD_HIREG _("lo register required")
657 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
658 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
659 #define BAD_BRANCH _("branch must be last instruction in IT block")
660 #define BAD_NOT_IT _("instruction not allowed in IT block")
661 #define BAD_FPU _("selected FPU does not support instruction")
663 static struct hash_control
*arm_ops_hsh
;
664 static struct hash_control
*arm_cond_hsh
;
665 static struct hash_control
*arm_shift_hsh
;
666 static struct hash_control
*arm_psr_hsh
;
667 static struct hash_control
*arm_v7m_psr_hsh
;
668 static struct hash_control
*arm_reg_hsh
;
669 static struct hash_control
*arm_reloc_hsh
;
670 static struct hash_control
*arm_barrier_opt_hsh
;
672 /* Stuff needed to resolve the label ambiguity
682 symbolS
* last_label_seen
;
683 static int label_is_thumb_function_name
= FALSE
;
685 /* Literal pool structure. Held on a per-section
686 and per-sub-section basis. */
688 #define MAX_LITERAL_POOL_SIZE 1024
689 typedef struct literal_pool
691 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
692 unsigned int next_free_entry
;
697 struct literal_pool
* next
;
700 /* Pointer to a linked list of literal pools. */
701 literal_pool
* list_of_pools
= NULL
;
703 /* State variables for IT block handling. */
704 static bfd_boolean current_it_mask
= 0;
705 static int current_cc
;
710 /* This array holds the chars that always start a comment. If the
711 pre-processor is disabled, these aren't very useful. */
712 const char comment_chars
[] = "@";
714 /* This array holds the chars that only start a comment at the beginning of
715 a line. If the line seems to have the form '# 123 filename'
716 .line and .file directives will appear in the pre-processed output. */
717 /* Note that input_file.c hand checks for '#' at the beginning of the
718 first line of the input file. This is because the compiler outputs
719 #NO_APP at the beginning of its output. */
720 /* Also note that comments like this one will always work. */
721 const char line_comment_chars
[] = "#";
723 const char line_separator_chars
[] = ";";
725 /* Chars that can be used to separate mant
726 from exp in floating point numbers. */
727 const char EXP_CHARS
[] = "eE";
729 /* Chars that mean this number is a floating point constant. */
733 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
735 /* Prefix characters that indicate the start of an immediate
737 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
739 /* Separator character handling. */
741 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
744 skip_past_char (char ** str
, char c
)
754 #define skip_past_comma(str) skip_past_char (str, ',')
756 /* Arithmetic expressions (possibly involving symbols). */
758 /* Return TRUE if anything in the expression is a bignum. */
761 walk_no_bignums (symbolS
* sp
)
763 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
766 if (symbol_get_value_expression (sp
)->X_add_symbol
)
768 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
769 || (symbol_get_value_expression (sp
)->X_op_symbol
770 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
776 static int in_my_get_expression
= 0;
778 /* Third argument to my_get_expression. */
779 #define GE_NO_PREFIX 0
780 #define GE_IMM_PREFIX 1
781 #define GE_OPT_PREFIX 2
782 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
783 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
784 #define GE_OPT_PREFIX_BIG 3
787 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
792 /* In unified syntax, all prefixes are optional. */
794 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
799 case GE_NO_PREFIX
: break;
801 if (!is_immediate_prefix (**str
))
803 inst
.error
= _("immediate expression requires a # prefix");
809 case GE_OPT_PREFIX_BIG
:
810 if (is_immediate_prefix (**str
))
816 memset (ep
, 0, sizeof (expressionS
));
818 save_in
= input_line_pointer
;
819 input_line_pointer
= *str
;
820 in_my_get_expression
= 1;
821 seg
= expression (ep
);
822 in_my_get_expression
= 0;
824 if (ep
->X_op
== O_illegal
)
826 /* We found a bad expression in md_operand(). */
827 *str
= input_line_pointer
;
828 input_line_pointer
= save_in
;
829 if (inst
.error
== NULL
)
830 inst
.error
= _("bad expression");
835 if (seg
!= absolute_section
836 && seg
!= text_section
837 && seg
!= data_section
838 && seg
!= bss_section
839 && seg
!= undefined_section
)
841 inst
.error
= _("bad segment");
842 *str
= input_line_pointer
;
843 input_line_pointer
= save_in
;
848 /* Get rid of any bignums now, so that we don't generate an error for which
849 we can't establish a line number later on. Big numbers are never valid
850 in instructions, which is where this routine is always called. */
851 if (prefix_mode
!= GE_OPT_PREFIX_BIG
852 && (ep
->X_op
== O_big
854 && (walk_no_bignums (ep
->X_add_symbol
)
856 && walk_no_bignums (ep
->X_op_symbol
))))))
858 inst
.error
= _("invalid constant");
859 *str
= input_line_pointer
;
860 input_line_pointer
= save_in
;
864 *str
= input_line_pointer
;
865 input_line_pointer
= save_in
;
869 /* Turn a string in input_line_pointer into a floating point constant
870 of type TYPE, and store the appropriate bytes in *LITP. The number
871 of LITTLENUMS emitted is stored in *SIZEP. An error message is
872 returned, or NULL on OK.
874 Note that fp constants aren't represent in the normal way on the ARM.
875 In big endian mode, things are as expected. However, in little endian
876 mode fp constants are big-endian word-wise, and little-endian byte-wise
877 within the words. For example, (double) 1.1 in big endian mode is
878 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
879 the byte sequence 99 99 f1 3f 9a 99 99 99.
881 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
884 md_atof (int type
, char * litP
, int * sizeP
)
887 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
919 return _("bad call to MD_ATOF()");
922 t
= atof_ieee (input_line_pointer
, type
, words
);
924 input_line_pointer
= t
;
927 if (target_big_endian
)
929 for (i
= 0; i
< prec
; i
++)
931 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
937 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
938 for (i
= prec
- 1; i
>= 0; i
--)
940 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
944 /* For a 4 byte float the order of elements in `words' is 1 0.
945 For an 8 byte float the order is 1 0 3 2. */
946 for (i
= 0; i
< prec
; i
+= 2)
948 md_number_to_chars (litP
, (valueT
) words
[i
+ 1], 2);
949 md_number_to_chars (litP
+ 2, (valueT
) words
[i
], 2);
957 /* We handle all bad expressions here, so that we can report the faulty
958 instruction in the error message. */
960 md_operand (expressionS
* expr
)
962 if (in_my_get_expression
)
963 expr
->X_op
= O_illegal
;
966 /* Immediate values. */
968 /* Generic immediate-value read function for use in directives.
969 Accepts anything that 'expression' can fold to a constant.
970 *val receives the number. */
973 immediate_for_directive (int *val
)
976 exp
.X_op
= O_illegal
;
978 if (is_immediate_prefix (*input_line_pointer
))
980 input_line_pointer
++;
984 if (exp
.X_op
!= O_constant
)
986 as_bad (_("expected #constant"));
987 ignore_rest_of_line ();
990 *val
= exp
.X_add_number
;
995 /* Register parsing. */
997 /* Generic register parser. CCP points to what should be the
998 beginning of a register name. If it is indeed a valid register
999 name, advance CCP over it and return the reg_entry structure;
1000 otherwise return NULL. Does not issue diagnostics. */
1002 static struct reg_entry
*
1003 arm_reg_parse_multi (char **ccp
)
1007 struct reg_entry
*reg
;
1009 #ifdef REGISTER_PREFIX
1010 if (*start
!= REGISTER_PREFIX
)
1014 #ifdef OPTIONAL_REGISTER_PREFIX
1015 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1020 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1025 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1027 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1037 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1038 enum arm_reg_type type
)
1040 /* Alternative syntaxes are accepted for a few register classes. */
1047 /* Generic coprocessor register names are allowed for these. */
1048 if (reg
&& reg
->type
== REG_TYPE_CN
)
1053 /* For backward compatibility, a bare number is valid here. */
1055 unsigned long processor
= strtoul (start
, ccp
, 10);
1056 if (*ccp
!= start
&& processor
<= 15)
1060 case REG_TYPE_MMXWC
:
1061 /* WC includes WCG. ??? I'm not sure this is true for all
1062 instructions that take WC registers. */
1063 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1074 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1075 return value is the register number or FAIL. */
1078 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1081 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1084 /* Do not allow a scalar (reg+index) to parse as a register. */
1085 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1088 if (reg
&& reg
->type
== type
)
1091 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1098 /* Parse a Neon type specifier. *STR should point at the leading '.'
1099 character. Does no verification at this stage that the type fits the opcode
1106 Can all be legally parsed by this function.
1108 Fills in neon_type struct pointer with parsed information, and updates STR
1109 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1110 type, FAIL if not. */
1113 parse_neon_type (struct neon_type
*type
, char **str
)
1120 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1122 enum neon_el_type thistype
= NT_untyped
;
1123 unsigned thissize
= -1u;
1130 /* Just a size without an explicit type. */
1134 switch (TOLOWER (*ptr
))
1136 case 'i': thistype
= NT_integer
; break;
1137 case 'f': thistype
= NT_float
; break;
1138 case 'p': thistype
= NT_poly
; break;
1139 case 's': thistype
= NT_signed
; break;
1140 case 'u': thistype
= NT_unsigned
; break;
1142 thistype
= NT_float
;
1147 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1153 /* .f is an abbreviation for .f32. */
1154 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1159 thissize
= strtoul (ptr
, &ptr
, 10);
1161 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1164 as_bad (_("bad size %d in type specifier"), thissize
);
1172 type
->el
[type
->elems
].type
= thistype
;
1173 type
->el
[type
->elems
].size
= thissize
;
1178 /* Empty/missing type is not a successful parse. */
1179 if (type
->elems
== 0)
1187 /* Errors may be set multiple times during parsing or bit encoding
1188 (particularly in the Neon bits), but usually the earliest error which is set
1189 will be the most meaningful. Avoid overwriting it with later (cascading)
1190 errors by calling this function. */
1193 first_error (const char *err
)
1199 /* Parse a single type, e.g. ".s32", leading period included. */
1201 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1204 struct neon_type optype
;
1208 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1210 if (optype
.elems
== 1)
1211 *vectype
= optype
.el
[0];
1214 first_error (_("only one type should be specified for operand"));
1220 first_error (_("vector type expected"));
1232 /* Special meanings for indices (which have a range of 0-7), which will fit into
1235 #define NEON_ALL_LANES 15
1236 #define NEON_INTERLEAVE_LANES 14
1238 /* Parse either a register or a scalar, with an optional type. Return the
1239 register number, and optionally fill in the actual type of the register
1240 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1241 type/index information in *TYPEINFO. */
1244 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1245 enum arm_reg_type
*rtype
,
1246 struct neon_typed_alias
*typeinfo
)
1249 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1250 struct neon_typed_alias atype
;
1251 struct neon_type_el parsetype
;
1255 atype
.eltype
.type
= NT_invtype
;
1256 atype
.eltype
.size
= -1;
1258 /* Try alternate syntax for some types of register. Note these are mutually
1259 exclusive with the Neon syntax extensions. */
1262 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1270 /* Undo polymorphism when a set of register types may be accepted. */
1271 if ((type
== REG_TYPE_NDQ
1272 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1273 || (type
== REG_TYPE_VFSD
1274 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1275 || (type
== REG_TYPE_NSDQ
1276 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1277 || reg
->type
== REG_TYPE_NQ
))
1278 || (type
== REG_TYPE_MMXWC
1279 && (reg
->type
== REG_TYPE_MMXWCG
)))
1282 if (type
!= reg
->type
)
1288 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1290 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1292 first_error (_("can't redefine type for operand"));
1295 atype
.defined
|= NTA_HASTYPE
;
1296 atype
.eltype
= parsetype
;
1299 if (skip_past_char (&str
, '[') == SUCCESS
)
1301 if (type
!= REG_TYPE_VFD
)
1303 first_error (_("only D registers may be indexed"));
1307 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1309 first_error (_("can't change index for operand"));
1313 atype
.defined
|= NTA_HASINDEX
;
1315 if (skip_past_char (&str
, ']') == SUCCESS
)
1316 atype
.index
= NEON_ALL_LANES
;
1321 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1323 if (exp
.X_op
!= O_constant
)
1325 first_error (_("constant expression required"));
1329 if (skip_past_char (&str
, ']') == FAIL
)
1332 atype
.index
= exp
.X_add_number
;
1347 /* Like arm_reg_parse, but allow allow the following extra features:
1348 - If RTYPE is non-zero, return the (possibly restricted) type of the
1349 register (e.g. Neon double or quad reg when either has been requested).
1350 - If this is a Neon vector type with additional type information, fill
1351 in the struct pointed to by VECTYPE (if non-NULL).
1352 This function will fault on encountering a scalar.
1356 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1357 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1359 struct neon_typed_alias atype
;
1361 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1366 /* Do not allow a scalar (reg+index) to parse as a register. */
1367 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1369 first_error (_("register operand expected, but got scalar"));
1374 *vectype
= atype
.eltype
;
1381 #define NEON_SCALAR_REG(X) ((X) >> 4)
1382 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1384 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1385 have enough information to be able to do a good job bounds-checking. So, we
1386 just do easy checks here, and do further checks later. */
1389 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1393 struct neon_typed_alias atype
;
1395 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1397 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1400 if (atype
.index
== NEON_ALL_LANES
)
1402 first_error (_("scalar must have an index"));
1405 else if (atype
.index
>= 64 / elsize
)
1407 first_error (_("scalar index out of range"));
1412 *type
= atype
.eltype
;
1416 return reg
* 16 + atype
.index
;
1419 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1421 parse_reg_list (char ** strp
)
1423 char * str
= * strp
;
1427 /* We come back here if we get ranges concatenated by '+' or '|'. */
1442 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1444 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1454 first_error (_("bad range in register list"));
1458 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1460 if (range
& (1 << i
))
1462 (_("Warning: duplicated register (r%d) in register list"),
1470 if (range
& (1 << reg
))
1471 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1473 else if (reg
<= cur_reg
)
1474 as_tsktsk (_("Warning: register range not in ascending order"));
1479 while (skip_past_comma (&str
) != FAIL
1480 || (in_range
= 1, *str
++ == '-'));
1485 first_error (_("missing `}'"));
1493 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1496 if (expr
.X_op
== O_constant
)
1498 if (expr
.X_add_number
1499 != (expr
.X_add_number
& 0x0000ffff))
1501 inst
.error
= _("invalid register mask");
1505 if ((range
& expr
.X_add_number
) != 0)
1507 int regno
= range
& expr
.X_add_number
;
1510 regno
= (1 << regno
) - 1;
1512 (_("Warning: duplicated register (r%d) in register list"),
1516 range
|= expr
.X_add_number
;
1520 if (inst
.reloc
.type
!= 0)
1522 inst
.error
= _("expression too complex");
1526 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1527 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1528 inst
.reloc
.pc_rel
= 0;
1532 if (*str
== '|' || *str
== '+')
1538 while (another_range
);
1544 /* Types of registers in a list. */
1553 /* Parse a VFP register list. If the string is invalid return FAIL.
1554 Otherwise return the number of registers, and set PBASE to the first
1555 register. Parses registers of type ETYPE.
1556 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1557 - Q registers can be used to specify pairs of D registers
1558 - { } can be omitted from around a singleton register list
1559 FIXME: This is not implemented, as it would require backtracking in
1562 This could be done (the meaning isn't really ambiguous), but doesn't
1563 fit in well with the current parsing framework.
1564 - 32 D registers may be used (also true for VFPv3).
1565 FIXME: Types are ignored in these register lists, which is probably a
1569 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1574 enum arm_reg_type regtype
= 0;
1578 unsigned long mask
= 0;
1583 inst
.error
= _("expecting {");
1592 regtype
= REG_TYPE_VFS
;
1597 regtype
= REG_TYPE_VFD
;
1600 case REGLIST_NEON_D
:
1601 regtype
= REG_TYPE_NDQ
;
1605 if (etype
!= REGLIST_VFP_S
)
1607 /* VFPv3 allows 32 D registers. */
1608 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
1612 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1615 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1622 base_reg
= max_regs
;
1626 int setmask
= 1, addregs
= 1;
1628 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1630 if (new_base
== FAIL
)
1632 first_error (_(reg_expected_msgs
[regtype
]));
1636 if (new_base
>= max_regs
)
1638 first_error (_("register out of range in list"));
1642 /* Note: a value of 2 * n is returned for the register Q<n>. */
1643 if (regtype
== REG_TYPE_NQ
)
1649 if (new_base
< base_reg
)
1650 base_reg
= new_base
;
1652 if (mask
& (setmask
<< new_base
))
1654 first_error (_("invalid register list"));
1658 if ((mask
>> new_base
) != 0 && ! warned
)
1660 as_tsktsk (_("register list not in ascending order"));
1664 mask
|= setmask
<< new_base
;
1667 if (*str
== '-') /* We have the start of a range expression */
1673 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1676 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1680 if (high_range
>= max_regs
)
1682 first_error (_("register out of range in list"));
1686 if (regtype
== REG_TYPE_NQ
)
1687 high_range
= high_range
+ 1;
1689 if (high_range
<= new_base
)
1691 inst
.error
= _("register range not in ascending order");
1695 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1697 if (mask
& (setmask
<< new_base
))
1699 inst
.error
= _("invalid register list");
1703 mask
|= setmask
<< new_base
;
1708 while (skip_past_comma (&str
) != FAIL
);
1712 /* Sanity check -- should have raised a parse error above. */
1713 if (count
== 0 || count
> max_regs
)
1718 /* Final test -- the registers must be consecutive. */
1720 for (i
= 0; i
< count
; i
++)
1722 if ((mask
& (1u << i
)) == 0)
1724 inst
.error
= _("non-contiguous register range");
1734 /* True if two alias types are the same. */
1737 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1745 if (a
->defined
!= b
->defined
)
1748 if ((a
->defined
& NTA_HASTYPE
) != 0
1749 && (a
->eltype
.type
!= b
->eltype
.type
1750 || a
->eltype
.size
!= b
->eltype
.size
))
1753 if ((a
->defined
& NTA_HASINDEX
) != 0
1754 && (a
->index
!= b
->index
))
1760 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1761 The base register is put in *PBASE.
1762 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1764 The register stride (minus one) is put in bit 4 of the return value.
1765 Bits [6:5] encode the list length (minus one).
1766 The type of the list elements is put in *ELTYPE, if non-NULL. */
1768 #define NEON_LANE(X) ((X) & 0xf)
1769 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1770 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1773 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1774 struct neon_type_el
*eltype
)
1781 int leading_brace
= 0;
1782 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1784 const char *const incr_error
= "register stride must be 1 or 2";
1785 const char *const type_error
= "mismatched element/structure types in list";
1786 struct neon_typed_alias firsttype
;
1788 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1793 struct neon_typed_alias atype
;
1794 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1798 first_error (_(reg_expected_msgs
[rtype
]));
1805 if (rtype
== REG_TYPE_NQ
)
1812 else if (reg_incr
== -1)
1814 reg_incr
= getreg
- base_reg
;
1815 if (reg_incr
< 1 || reg_incr
> 2)
1817 first_error (_(incr_error
));
1821 else if (getreg
!= base_reg
+ reg_incr
* count
)
1823 first_error (_(incr_error
));
1827 if (!neon_alias_types_same (&atype
, &firsttype
))
1829 first_error (_(type_error
));
1833 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1837 struct neon_typed_alias htype
;
1838 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1840 lane
= NEON_INTERLEAVE_LANES
;
1841 else if (lane
!= NEON_INTERLEAVE_LANES
)
1843 first_error (_(type_error
));
1848 else if (reg_incr
!= 1)
1850 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1854 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1857 first_error (_(reg_expected_msgs
[rtype
]));
1860 if (!neon_alias_types_same (&htype
, &firsttype
))
1862 first_error (_(type_error
));
1865 count
+= hireg
+ dregs
- getreg
;
1869 /* If we're using Q registers, we can't use [] or [n] syntax. */
1870 if (rtype
== REG_TYPE_NQ
)
1876 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1880 else if (lane
!= atype
.index
)
1882 first_error (_(type_error
));
1886 else if (lane
== -1)
1887 lane
= NEON_INTERLEAVE_LANES
;
1888 else if (lane
!= NEON_INTERLEAVE_LANES
)
1890 first_error (_(type_error
));
1895 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1897 /* No lane set by [x]. We must be interleaving structures. */
1899 lane
= NEON_INTERLEAVE_LANES
;
1902 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
1903 || (count
> 1 && reg_incr
== -1))
1905 first_error (_("error parsing element/structure list"));
1909 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
1911 first_error (_("expected }"));
1919 *eltype
= firsttype
.eltype
;
1924 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
1927 /* Parse an explicit relocation suffix on an expression. This is
1928 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1929 arm_reloc_hsh contains no entries, so this function can only
1930 succeed if there is no () after the word. Returns -1 on error,
1931 BFD_RELOC_UNUSED if there wasn't any suffix. */
1933 parse_reloc (char **str
)
1935 struct reloc_entry
*r
;
1939 return BFD_RELOC_UNUSED
;
1944 while (*q
&& *q
!= ')' && *q
!= ',')
1949 if ((r
= hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
1956 /* Directives: register aliases. */
1958 static struct reg_entry
*
1959 insert_reg_alias (char *str
, int number
, int type
)
1961 struct reg_entry
*new;
1964 if ((new = hash_find (arm_reg_hsh
, str
)) != 0)
1967 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
1969 /* Only warn about a redefinition if it's not defined as the
1971 else if (new->number
!= number
|| new->type
!= type
)
1972 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1977 name
= xstrdup (str
);
1978 new = xmalloc (sizeof (struct reg_entry
));
1981 new->number
= number
;
1983 new->builtin
= FALSE
;
1986 if (hash_insert (arm_reg_hsh
, name
, (PTR
) new))
1993 insert_neon_reg_alias (char *str
, int number
, int type
,
1994 struct neon_typed_alias
*atype
)
1996 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2000 first_error (_("attempt to redefine typed alias"));
2006 reg
->neon
= xmalloc (sizeof (struct neon_typed_alias
));
2007 *reg
->neon
= *atype
;
2011 /* Look for the .req directive. This is of the form:
2013 new_register_name .req existing_register_name
2015 If we find one, or if it looks sufficiently like one that we want to
2016 handle any error here, return non-zero. Otherwise return zero. */
2019 create_register_alias (char * newname
, char *p
)
2021 struct reg_entry
*old
;
2022 char *oldname
, *nbuf
;
2025 /* The input scrubber ensures that whitespace after the mnemonic is
2026 collapsed to single spaces. */
2028 if (strncmp (oldname
, " .req ", 6) != 0)
2032 if (*oldname
== '\0')
2035 old
= hash_find (arm_reg_hsh
, oldname
);
2038 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2042 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2043 the desired alias name, and p points to its end. If not, then
2044 the desired alias name is in the global original_case_string. */
2045 #ifdef TC_CASE_SENSITIVE
2048 newname
= original_case_string
;
2049 nlen
= strlen (newname
);
2052 nbuf
= alloca (nlen
+ 1);
2053 memcpy (nbuf
, newname
, nlen
);
2056 /* Create aliases under the new name as stated; an all-lowercase
2057 version of the new name; and an all-uppercase version of the new
2059 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2061 for (p
= nbuf
; *p
; p
++)
2064 if (strncmp (nbuf
, newname
, nlen
))
2065 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2067 for (p
= nbuf
; *p
; p
++)
2070 if (strncmp (nbuf
, newname
, nlen
))
2071 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2076 /* Create a Neon typed/indexed register alias using directives, e.g.:
2081 These typed registers can be used instead of the types specified after the
2082 Neon mnemonic, so long as all operands given have types. Types can also be
2083 specified directly, e.g.:
2084 vadd d0.s32, d1.s32, d2.s32
2088 create_neon_reg_alias (char *newname
, char *p
)
2090 enum arm_reg_type basetype
;
2091 struct reg_entry
*basereg
;
2092 struct reg_entry mybasereg
;
2093 struct neon_type ntype
;
2094 struct neon_typed_alias typeinfo
;
2095 char *namebuf
, *nameend
;
2098 typeinfo
.defined
= 0;
2099 typeinfo
.eltype
.type
= NT_invtype
;
2100 typeinfo
.eltype
.size
= -1;
2101 typeinfo
.index
= -1;
2105 if (strncmp (p
, " .dn ", 5) == 0)
2106 basetype
= REG_TYPE_VFD
;
2107 else if (strncmp (p
, " .qn ", 5) == 0)
2108 basetype
= REG_TYPE_NQ
;
2117 basereg
= arm_reg_parse_multi (&p
);
2119 if (basereg
&& basereg
->type
!= basetype
)
2121 as_bad (_("bad type for register"));
2125 if (basereg
== NULL
)
2128 /* Try parsing as an integer. */
2129 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2130 if (exp
.X_op
!= O_constant
)
2132 as_bad (_("expression must be constant"));
2135 basereg
= &mybasereg
;
2136 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2142 typeinfo
= *basereg
->neon
;
2144 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2146 /* We got a type. */
2147 if (typeinfo
.defined
& NTA_HASTYPE
)
2149 as_bad (_("can't redefine the type of a register alias"));
2153 typeinfo
.defined
|= NTA_HASTYPE
;
2154 if (ntype
.elems
!= 1)
2156 as_bad (_("you must specify a single type only"));
2159 typeinfo
.eltype
= ntype
.el
[0];
2162 if (skip_past_char (&p
, '[') == SUCCESS
)
2165 /* We got a scalar index. */
2167 if (typeinfo
.defined
& NTA_HASINDEX
)
2169 as_bad (_("can't redefine the index of a scalar alias"));
2173 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2175 if (exp
.X_op
!= O_constant
)
2177 as_bad (_("scalar index must be constant"));
2181 typeinfo
.defined
|= NTA_HASINDEX
;
2182 typeinfo
.index
= exp
.X_add_number
;
2184 if (skip_past_char (&p
, ']') == FAIL
)
2186 as_bad (_("expecting ]"));
2191 namelen
= nameend
- newname
;
2192 namebuf
= alloca (namelen
+ 1);
2193 strncpy (namebuf
, newname
, namelen
);
2194 namebuf
[namelen
] = '\0';
2196 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2197 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2199 /* Insert name in all uppercase. */
2200 for (p
= namebuf
; *p
; p
++)
2203 if (strncmp (namebuf
, newname
, namelen
))
2204 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2205 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2207 /* Insert name in all lowercase. */
2208 for (p
= namebuf
; *p
; p
++)
2211 if (strncmp (namebuf
, newname
, namelen
))
2212 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2213 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2218 /* Should never be called, as .req goes between the alias and the
2219 register name, not at the beginning of the line. */
2221 s_req (int a ATTRIBUTE_UNUSED
)
2223 as_bad (_("invalid syntax for .req directive"));
2227 s_dn (int a ATTRIBUTE_UNUSED
)
2229 as_bad (_("invalid syntax for .dn directive"));
2233 s_qn (int a ATTRIBUTE_UNUSED
)
2235 as_bad (_("invalid syntax for .qn directive"));
2238 /* The .unreq directive deletes an alias which was previously defined
2239 by .req. For example:
2245 s_unreq (int a ATTRIBUTE_UNUSED
)
2250 name
= input_line_pointer
;
2252 while (*input_line_pointer
!= 0
2253 && *input_line_pointer
!= ' '
2254 && *input_line_pointer
!= '\n')
2255 ++input_line_pointer
;
2257 saved_char
= *input_line_pointer
;
2258 *input_line_pointer
= 0;
2261 as_bad (_("invalid syntax for .unreq directive"));
2264 struct reg_entry
*reg
= hash_find (arm_reg_hsh
, name
);
2267 as_bad (_("unknown register alias '%s'"), name
);
2268 else if (reg
->builtin
)
2269 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2273 hash_delete (arm_reg_hsh
, name
);
2274 free ((char *) reg
->name
);
2281 *input_line_pointer
= saved_char
;
2282 demand_empty_rest_of_line ();
2285 /* Directives: Instruction set selection. */
2288 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2289 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2290 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2291 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2293 static enum mstate mapstate
= MAP_UNDEFINED
;
2296 mapping_state (enum mstate state
)
2299 const char * symname
;
2302 if (mapstate
== state
)
2303 /* The mapping symbol has already been emitted.
2304 There is nothing else to do. */
2313 type
= BSF_NO_FLAGS
;
2317 type
= BSF_NO_FLAGS
;
2321 type
= BSF_NO_FLAGS
;
2329 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2331 symbolP
= symbol_new (symname
, now_seg
, (valueT
) frag_now_fix (), frag_now
);
2332 symbol_table_insert (symbolP
);
2333 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2338 THUMB_SET_FUNC (symbolP
, 0);
2339 ARM_SET_THUMB (symbolP
, 0);
2340 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2344 THUMB_SET_FUNC (symbolP
, 1);
2345 ARM_SET_THUMB (symbolP
, 1);
2346 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2355 #define mapping_state(x) /* nothing */
2358 /* Find the real, Thumb encoded start of a Thumb function. */
2361 find_real_start (symbolS
* symbolP
)
2364 const char * name
= S_GET_NAME (symbolP
);
2365 symbolS
* new_target
;
2367 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2368 #define STUB_NAME ".real_start_of"
2373 /* The compiler may generate BL instructions to local labels because
2374 it needs to perform a branch to a far away location. These labels
2375 do not have a corresponding ".real_start_of" label. We check
2376 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2377 the ".real_start_of" convention for nonlocal branches. */
2378 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2381 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2382 new_target
= symbol_find (real_start
);
2384 if (new_target
== NULL
)
2386 as_warn ("Failed to find real start of function: %s\n", name
);
2387 new_target
= symbolP
;
2394 opcode_select (int width
)
2401 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2402 as_bad (_("selected processor does not support THUMB opcodes"));
2405 /* No need to force the alignment, since we will have been
2406 coming from ARM mode, which is word-aligned. */
2407 record_alignment (now_seg
, 1);
2409 mapping_state (MAP_THUMB
);
2415 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2416 as_bad (_("selected processor does not support ARM opcodes"));
2421 frag_align (2, 0, 0);
2423 record_alignment (now_seg
, 1);
2425 mapping_state (MAP_ARM
);
2429 as_bad (_("invalid instruction size selected (%d)"), width
);
2434 s_arm (int ignore ATTRIBUTE_UNUSED
)
2437 demand_empty_rest_of_line ();
2441 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2444 demand_empty_rest_of_line ();
2448 s_code (int unused ATTRIBUTE_UNUSED
)
2452 temp
= get_absolute_expression ();
2457 opcode_select (temp
);
2461 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2466 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2468 /* If we are not already in thumb mode go into it, EVEN if
2469 the target processor does not support thumb instructions.
2470 This is used by gcc/config/arm/lib1funcs.asm for example
2471 to compile interworking support functions even if the
2472 target processor should not support interworking. */
2476 record_alignment (now_seg
, 1);
2479 demand_empty_rest_of_line ();
2483 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2487 /* The following label is the name/address of the start of a Thumb function.
2488 We need to know this for the interworking support. */
2489 label_is_thumb_function_name
= TRUE
;
2492 /* Perform a .set directive, but also mark the alias as
2493 being a thumb function. */
2496 s_thumb_set (int equiv
)
2498 /* XXX the following is a duplicate of the code for s_set() in read.c
2499 We cannot just call that code as we need to get at the symbol that
2506 /* Especial apologies for the random logic:
2507 This just grew, and could be parsed much more simply!
2509 name
= input_line_pointer
;
2510 delim
= get_symbol_end ();
2511 end_name
= input_line_pointer
;
2514 if (*input_line_pointer
!= ',')
2517 as_bad (_("expected comma after name \"%s\""), name
);
2519 ignore_rest_of_line ();
2523 input_line_pointer
++;
2526 if (name
[0] == '.' && name
[1] == '\0')
2528 /* XXX - this should not happen to .thumb_set. */
2532 if ((symbolP
= symbol_find (name
)) == NULL
2533 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2536 /* When doing symbol listings, play games with dummy fragments living
2537 outside the normal fragment chain to record the file and line info
2539 if (listing
& LISTING_SYMBOLS
)
2541 extern struct list_info_struct
* listing_tail
;
2542 fragS
* dummy_frag
= xmalloc (sizeof (fragS
));
2544 memset (dummy_frag
, 0, sizeof (fragS
));
2545 dummy_frag
->fr_type
= rs_fill
;
2546 dummy_frag
->line
= listing_tail
;
2547 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2548 dummy_frag
->fr_symbol
= symbolP
;
2552 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2555 /* "set" symbols are local unless otherwise specified. */
2556 SF_SET_LOCAL (symbolP
);
2557 #endif /* OBJ_COFF */
2558 } /* Make a new symbol. */
2560 symbol_table_insert (symbolP
);
2565 && S_IS_DEFINED (symbolP
)
2566 && S_GET_SEGMENT (symbolP
) != reg_section
)
2567 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2569 pseudo_set (symbolP
);
2571 demand_empty_rest_of_line ();
2573 /* XXX Now we come to the Thumb specific bit of code. */
2575 THUMB_SET_FUNC (symbolP
, 1);
2576 ARM_SET_THUMB (symbolP
, 1);
2577 #if defined OBJ_ELF || defined OBJ_COFF
2578 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2582 /* Directives: Mode selection. */
2584 /* .syntax [unified|divided] - choose the new unified syntax
2585 (same for Arm and Thumb encoding, modulo slight differences in what
2586 can be represented) or the old divergent syntax for each mode. */
2588 s_syntax (int unused ATTRIBUTE_UNUSED
)
2592 name
= input_line_pointer
;
2593 delim
= get_symbol_end ();
2595 if (!strcasecmp (name
, "unified"))
2596 unified_syntax
= TRUE
;
2597 else if (!strcasecmp (name
, "divided"))
2598 unified_syntax
= FALSE
;
2601 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2604 *input_line_pointer
= delim
;
2605 demand_empty_rest_of_line ();
2608 /* Directives: sectioning and alignment. */
2610 /* Same as s_align_ptwo but align 0 => align 2. */
2613 s_align (int unused ATTRIBUTE_UNUSED
)
2618 long max_alignment
= 15;
2620 temp
= get_absolute_expression ();
2621 if (temp
> max_alignment
)
2622 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2625 as_bad (_("alignment negative. 0 assumed."));
2629 if (*input_line_pointer
== ',')
2631 input_line_pointer
++;
2632 temp_fill
= get_absolute_expression ();
2644 /* Only make a frag if we HAVE to. */
2645 if (temp
&& !need_pass_2
)
2647 if (!fill_p
&& subseg_text_p (now_seg
))
2648 frag_align_code (temp
, 0);
2650 frag_align (temp
, (int) temp_fill
, 0);
2652 demand_empty_rest_of_line ();
2654 record_alignment (now_seg
, temp
);
2658 s_bss (int ignore ATTRIBUTE_UNUSED
)
2660 /* We don't support putting frags in the BSS segment, we fake it by
2661 marking in_bss, then looking at s_skip for clues. */
2662 subseg_set (bss_section
, 0);
2663 demand_empty_rest_of_line ();
2664 mapping_state (MAP_DATA
);
2668 s_even (int ignore ATTRIBUTE_UNUSED
)
2670 /* Never make frag if expect extra pass. */
2672 frag_align (1, 0, 0);
2674 record_alignment (now_seg
, 1);
2676 demand_empty_rest_of_line ();
2679 /* Directives: Literal pools. */
2681 static literal_pool
*
2682 find_literal_pool (void)
2684 literal_pool
* pool
;
2686 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2688 if (pool
->section
== now_seg
2689 && pool
->sub_section
== now_subseg
)
2696 static literal_pool
*
2697 find_or_make_literal_pool (void)
2699 /* Next literal pool ID number. */
2700 static unsigned int latest_pool_num
= 1;
2701 literal_pool
* pool
;
2703 pool
= find_literal_pool ();
2707 /* Create a new pool. */
2708 pool
= xmalloc (sizeof (* pool
));
2712 pool
->next_free_entry
= 0;
2713 pool
->section
= now_seg
;
2714 pool
->sub_section
= now_subseg
;
2715 pool
->next
= list_of_pools
;
2716 pool
->symbol
= NULL
;
2718 /* Add it to the list. */
2719 list_of_pools
= pool
;
2722 /* New pools, and emptied pools, will have a NULL symbol. */
2723 if (pool
->symbol
== NULL
)
2725 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2726 (valueT
) 0, &zero_address_frag
);
2727 pool
->id
= latest_pool_num
++;
2734 /* Add the literal in the global 'inst'
2735 structure to the relevent literal pool. */
2738 add_to_lit_pool (void)
2740 literal_pool
* pool
;
2743 pool
= find_or_make_literal_pool ();
2745 /* Check if this literal value is already in the pool. */
2746 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2748 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2749 && (inst
.reloc
.exp
.X_op
== O_constant
)
2750 && (pool
->literals
[entry
].X_add_number
2751 == inst
.reloc
.exp
.X_add_number
)
2752 && (pool
->literals
[entry
].X_unsigned
2753 == inst
.reloc
.exp
.X_unsigned
))
2756 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2757 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2758 && (pool
->literals
[entry
].X_add_number
2759 == inst
.reloc
.exp
.X_add_number
)
2760 && (pool
->literals
[entry
].X_add_symbol
2761 == inst
.reloc
.exp
.X_add_symbol
)
2762 && (pool
->literals
[entry
].X_op_symbol
2763 == inst
.reloc
.exp
.X_op_symbol
))
2767 /* Do we need to create a new entry? */
2768 if (entry
== pool
->next_free_entry
)
2770 if (entry
>= MAX_LITERAL_POOL_SIZE
)
2772 inst
.error
= _("literal pool overflow");
2776 pool
->literals
[entry
] = inst
.reloc
.exp
;
2777 pool
->next_free_entry
+= 1;
2780 inst
.reloc
.exp
.X_op
= O_symbol
;
2781 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
2782 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
2787 /* Can't use symbol_new here, so have to create a symbol and then at
2788 a later date assign it a value. Thats what these functions do. */
2791 symbol_locate (symbolS
* symbolP
,
2792 const char * name
, /* It is copied, the caller can modify. */
2793 segT segment
, /* Segment identifier (SEG_<something>). */
2794 valueT valu
, /* Symbol value. */
2795 fragS
* frag
) /* Associated fragment. */
2797 unsigned int name_length
;
2798 char * preserved_copy_of_name
;
2800 name_length
= strlen (name
) + 1; /* +1 for \0. */
2801 obstack_grow (¬es
, name
, name_length
);
2802 preserved_copy_of_name
= obstack_finish (¬es
);
2804 #ifdef tc_canonicalize_symbol_name
2805 preserved_copy_of_name
=
2806 tc_canonicalize_symbol_name (preserved_copy_of_name
);
2809 S_SET_NAME (symbolP
, preserved_copy_of_name
);
2811 S_SET_SEGMENT (symbolP
, segment
);
2812 S_SET_VALUE (symbolP
, valu
);
2813 symbol_clear_list_pointers (symbolP
);
2815 symbol_set_frag (symbolP
, frag
);
2817 /* Link to end of symbol chain. */
2819 extern int symbol_table_frozen
;
2821 if (symbol_table_frozen
)
2825 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
2827 obj_symbol_new_hook (symbolP
);
2829 #ifdef tc_symbol_new_hook
2830 tc_symbol_new_hook (symbolP
);
2834 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
2835 #endif /* DEBUG_SYMS */
2840 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
2843 literal_pool
* pool
;
2846 pool
= find_literal_pool ();
2848 || pool
->symbol
== NULL
2849 || pool
->next_free_entry
== 0)
2852 mapping_state (MAP_DATA
);
2854 /* Align pool as you have word accesses.
2855 Only make a frag if we have to. */
2857 frag_align (2, 0, 0);
2859 record_alignment (now_seg
, 2);
2861 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
2863 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
2864 (valueT
) frag_now_fix (), frag_now
);
2865 symbol_table_insert (pool
->symbol
);
2867 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
2869 #if defined OBJ_COFF || defined OBJ_ELF
2870 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
2873 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2874 /* First output the expression in the instruction to the pool. */
2875 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
2877 /* Mark the pool as empty. */
2878 pool
->next_free_entry
= 0;
2879 pool
->symbol
= NULL
;
2883 /* Forward declarations for functions below, in the MD interface
2885 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
2886 static valueT
create_unwind_entry (int);
2887 static void start_unwind_section (const segT
, int);
2888 static void add_unwind_opcode (valueT
, int);
2889 static void flush_pending_unwind (void);
2891 /* Directives: Data. */
2894 s_arm_elf_cons (int nbytes
)
2898 #ifdef md_flush_pending_output
2899 md_flush_pending_output ();
2902 if (is_it_end_of_statement ())
2904 demand_empty_rest_of_line ();
2908 #ifdef md_cons_align
2909 md_cons_align (nbytes
);
2912 mapping_state (MAP_DATA
);
2916 char *base
= input_line_pointer
;
2920 if (exp
.X_op
!= O_symbol
)
2921 emit_expr (&exp
, (unsigned int) nbytes
);
2924 char *before_reloc
= input_line_pointer
;
2925 reloc
= parse_reloc (&input_line_pointer
);
2928 as_bad (_("unrecognized relocation suffix"));
2929 ignore_rest_of_line ();
2932 else if (reloc
== BFD_RELOC_UNUSED
)
2933 emit_expr (&exp
, (unsigned int) nbytes
);
2936 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
2937 int size
= bfd_get_reloc_size (howto
);
2939 if (reloc
== BFD_RELOC_ARM_PLT32
)
2941 as_bad (_("(plt) is only valid on branch targets"));
2942 reloc
= BFD_RELOC_UNUSED
;
2947 as_bad (_("%s relocations do not fit in %d bytes"),
2948 howto
->name
, nbytes
);
2951 /* We've parsed an expression stopping at O_symbol.
2952 But there may be more expression left now that we
2953 have parsed the relocation marker. Parse it again.
2954 XXX Surely there is a cleaner way to do this. */
2955 char *p
= input_line_pointer
;
2957 char *save_buf
= alloca (input_line_pointer
- base
);
2958 memcpy (save_buf
, base
, input_line_pointer
- base
);
2959 memmove (base
+ (input_line_pointer
- before_reloc
),
2960 base
, before_reloc
- base
);
2962 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
2964 memcpy (base
, save_buf
, p
- base
);
2966 offset
= nbytes
- size
;
2967 p
= frag_more ((int) nbytes
);
2968 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
2969 size
, &exp
, 0, reloc
);
2974 while (*input_line_pointer
++ == ',');
2976 /* Put terminator back into stream. */
2977 input_line_pointer
--;
2978 demand_empty_rest_of_line ();
2982 /* Parse a .rel31 directive. */
2985 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
2992 if (*input_line_pointer
== '1')
2993 highbit
= 0x80000000;
2994 else if (*input_line_pointer
!= '0')
2995 as_bad (_("expected 0 or 1"));
2997 input_line_pointer
++;
2998 if (*input_line_pointer
!= ',')
2999 as_bad (_("missing comma"));
3000 input_line_pointer
++;
3002 #ifdef md_flush_pending_output
3003 md_flush_pending_output ();
3006 #ifdef md_cons_align
3010 mapping_state (MAP_DATA
);
3015 md_number_to_chars (p
, highbit
, 4);
3016 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3017 BFD_RELOC_ARM_PREL31
);
3019 demand_empty_rest_of_line ();
3022 /* Directives: AEABI stack-unwind tables. */
3024 /* Parse an unwind_fnstart directive. Simply records the current location. */
3027 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3029 demand_empty_rest_of_line ();
3030 /* Mark the start of the function. */
3031 unwind
.proc_start
= expr_build_dot ();
3033 /* Reset the rest of the unwind info. */
3034 unwind
.opcode_count
= 0;
3035 unwind
.table_entry
= NULL
;
3036 unwind
.personality_routine
= NULL
;
3037 unwind
.personality_index
= -1;
3038 unwind
.frame_size
= 0;
3039 unwind
.fp_offset
= 0;
3042 unwind
.sp_restored
= 0;
3046 /* Parse a handlerdata directive. Creates the exception handling table entry
3047 for the function. */
3050 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3052 demand_empty_rest_of_line ();
3053 if (unwind
.table_entry
)
3054 as_bad (_("dupicate .handlerdata directive"));
3056 create_unwind_entry (1);
3059 /* Parse an unwind_fnend directive. Generates the index table entry. */
3062 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3068 demand_empty_rest_of_line ();
3070 /* Add eh table entry. */
3071 if (unwind
.table_entry
== NULL
)
3072 val
= create_unwind_entry (0);
3076 /* Add index table entry. This is two words. */
3077 start_unwind_section (unwind
.saved_seg
, 1);
3078 frag_align (2, 0, 0);
3079 record_alignment (now_seg
, 2);
3081 ptr
= frag_more (8);
3082 where
= frag_now_fix () - 8;
3084 /* Self relative offset of the function start. */
3085 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3086 BFD_RELOC_ARM_PREL31
);
3088 /* Indicate dependency on EHABI-defined personality routines to the
3089 linker, if it hasn't been done already. */
3090 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3091 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3093 static const char *const name
[] = {
3094 "__aeabi_unwind_cpp_pr0",
3095 "__aeabi_unwind_cpp_pr1",
3096 "__aeabi_unwind_cpp_pr2"
3098 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3099 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3100 marked_pr_dependency
|= 1 << unwind
.personality_index
;
3101 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3102 = marked_pr_dependency
;
3106 /* Inline exception table entry. */
3107 md_number_to_chars (ptr
+ 4, val
, 4);
3109 /* Self relative offset of the table entry. */
3110 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3111 BFD_RELOC_ARM_PREL31
);
3113 /* Restore the original section. */
3114 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3118 /* Parse an unwind_cantunwind directive. */
3121 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3123 demand_empty_rest_of_line ();
3124 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3125 as_bad (_("personality routine specified for cantunwind frame"));
3127 unwind
.personality_index
= -2;
3131 /* Parse a personalityindex directive. */
3134 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3138 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3139 as_bad (_("duplicate .personalityindex directive"));
3143 if (exp
.X_op
!= O_constant
3144 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3146 as_bad (_("bad personality routine number"));
3147 ignore_rest_of_line ();
3151 unwind
.personality_index
= exp
.X_add_number
;
3153 demand_empty_rest_of_line ();
3157 /* Parse a personality directive. */
3160 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3164 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3165 as_bad (_("duplicate .personality directive"));
3167 name
= input_line_pointer
;
3168 c
= get_symbol_end ();
3169 p
= input_line_pointer
;
3170 unwind
.personality_routine
= symbol_find_or_make (name
);
3172 demand_empty_rest_of_line ();
3176 /* Parse a directive saving core registers. */
3179 s_arm_unwind_save_core (void)
3185 range
= parse_reg_list (&input_line_pointer
);
3188 as_bad (_("expected register list"));
3189 ignore_rest_of_line ();
3193 demand_empty_rest_of_line ();
3195 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3196 into .unwind_save {..., sp...}. We aren't bothered about the value of
3197 ip because it is clobbered by calls. */
3198 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3199 && (range
& 0x3000) == 0x1000)
3201 unwind
.opcode_count
--;
3202 unwind
.sp_restored
= 0;
3203 range
= (range
| 0x2000) & ~0x1000;
3204 unwind
.pending_offset
= 0;
3210 /* See if we can use the short opcodes. These pop a block of up to 8
3211 registers starting with r4, plus maybe r14. */
3212 for (n
= 0; n
< 8; n
++)
3214 /* Break at the first non-saved register. */
3215 if ((range
& (1 << (n
+ 4))) == 0)
3218 /* See if there are any other bits set. */
3219 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3221 /* Use the long form. */
3222 op
= 0x8000 | ((range
>> 4) & 0xfff);
3223 add_unwind_opcode (op
, 2);
3227 /* Use the short form. */
3229 op
= 0xa8; /* Pop r14. */
3231 op
= 0xa0; /* Do not pop r14. */
3233 add_unwind_opcode (op
, 1);
3240 op
= 0xb100 | (range
& 0xf);
3241 add_unwind_opcode (op
, 2);
3244 /* Record the number of bytes pushed. */
3245 for (n
= 0; n
< 16; n
++)
3247 if (range
& (1 << n
))
3248 unwind
.frame_size
+= 4;
3253 /* Parse a directive saving FPA registers. */
3256 s_arm_unwind_save_fpa (int reg
)
3262 /* Get Number of registers to transfer. */
3263 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3266 exp
.X_op
= O_illegal
;
3268 if (exp
.X_op
!= O_constant
)
3270 as_bad (_("expected , <constant>"));
3271 ignore_rest_of_line ();
3275 num_regs
= exp
.X_add_number
;
3277 if (num_regs
< 1 || num_regs
> 4)
3279 as_bad (_("number of registers must be in the range [1:4]"));
3280 ignore_rest_of_line ();
3284 demand_empty_rest_of_line ();
3289 op
= 0xb4 | (num_regs
- 1);
3290 add_unwind_opcode (op
, 1);
3295 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3296 add_unwind_opcode (op
, 2);
3298 unwind
.frame_size
+= num_regs
* 12;
3302 /* Parse a directive saving VFP registers for ARMv6 and above. */
3305 s_arm_unwind_save_vfp_armv6 (void)
3310 int num_vfpv3_regs
= 0;
3311 int num_regs_below_16
;
3313 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3316 as_bad (_("expected register list"));
3317 ignore_rest_of_line ();
3321 demand_empty_rest_of_line ();
3323 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3324 than FSTMX/FLDMX-style ones). */
3326 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3328 num_vfpv3_regs
= count
;
3329 else if (start
+ count
> 16)
3330 num_vfpv3_regs
= start
+ count
- 16;
3332 if (num_vfpv3_regs
> 0)
3334 int start_offset
= start
> 16 ? start
- 16 : 0;
3335 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3336 add_unwind_opcode (op
, 2);
3339 /* Generate opcode for registers numbered in the range 0 .. 15. */
3340 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3341 assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3342 if (num_regs_below_16
> 0)
3344 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3345 add_unwind_opcode (op
, 2);
3348 unwind
.frame_size
+= count
* 8;
3352 /* Parse a directive saving VFP registers for pre-ARMv6. */
3355 s_arm_unwind_save_vfp (void)
3361 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3364 as_bad (_("expected register list"));
3365 ignore_rest_of_line ();
3369 demand_empty_rest_of_line ();
3374 op
= 0xb8 | (count
- 1);
3375 add_unwind_opcode (op
, 1);
3380 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3381 add_unwind_opcode (op
, 2);
3383 unwind
.frame_size
+= count
* 8 + 4;
3387 /* Parse a directive saving iWMMXt data registers. */
3390 s_arm_unwind_save_mmxwr (void)
3398 if (*input_line_pointer
== '{')
3399 input_line_pointer
++;
3403 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3407 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3412 as_tsktsk (_("register list not in ascending order"));
3415 if (*input_line_pointer
== '-')
3417 input_line_pointer
++;
3418 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3421 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3424 else if (reg
>= hi_reg
)
3426 as_bad (_("bad register range"));
3429 for (; reg
< hi_reg
; reg
++)
3433 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3435 if (*input_line_pointer
== '}')
3436 input_line_pointer
++;
3438 demand_empty_rest_of_line ();
3440 /* Generate any deferred opcodes because we're going to be looking at
3442 flush_pending_unwind ();
3444 for (i
= 0; i
< 16; i
++)
3446 if (mask
& (1 << i
))
3447 unwind
.frame_size
+= 8;
3450 /* Attempt to combine with a previous opcode. We do this because gcc
3451 likes to output separate unwind directives for a single block of
3453 if (unwind
.opcode_count
> 0)
3455 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3456 if ((i
& 0xf8) == 0xc0)
3459 /* Only merge if the blocks are contiguous. */
3462 if ((mask
& 0xfe00) == (1 << 9))
3464 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3465 unwind
.opcode_count
--;
3468 else if (i
== 6 && unwind
.opcode_count
>= 2)
3470 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3474 op
= 0xffff << (reg
- 1);
3476 && ((mask
& op
) == (1u << (reg
- 1))))
3478 op
= (1 << (reg
+ i
+ 1)) - 1;
3479 op
&= ~((1 << reg
) - 1);
3481 unwind
.opcode_count
-= 2;
3488 /* We want to generate opcodes in the order the registers have been
3489 saved, ie. descending order. */
3490 for (reg
= 15; reg
>= -1; reg
--)
3492 /* Save registers in blocks. */
3494 || !(mask
& (1 << reg
)))
3496 /* We found an unsaved reg. Generate opcodes to save the
3497 preceeding block. */
3503 op
= 0xc0 | (hi_reg
- 10);
3504 add_unwind_opcode (op
, 1);
3509 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3510 add_unwind_opcode (op
, 2);
3519 ignore_rest_of_line ();
3523 s_arm_unwind_save_mmxwcg (void)
3530 if (*input_line_pointer
== '{')
3531 input_line_pointer
++;
3535 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3539 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3545 as_tsktsk (_("register list not in ascending order"));
3548 if (*input_line_pointer
== '-')
3550 input_line_pointer
++;
3551 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3554 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3557 else if (reg
>= hi_reg
)
3559 as_bad (_("bad register range"));
3562 for (; reg
< hi_reg
; reg
++)
3566 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3568 if (*input_line_pointer
== '}')
3569 input_line_pointer
++;
3571 demand_empty_rest_of_line ();
3573 /* Generate any deferred opcodes because we're going to be looking at
3575 flush_pending_unwind ();
3577 for (reg
= 0; reg
< 16; reg
++)
3579 if (mask
& (1 << reg
))
3580 unwind
.frame_size
+= 4;
3583 add_unwind_opcode (op
, 2);
3586 ignore_rest_of_line ();
3590 /* Parse an unwind_save directive.
3591 If the argument is non-zero, this is a .vsave directive. */
3594 s_arm_unwind_save (int arch_v6
)
3597 struct reg_entry
*reg
;
3598 bfd_boolean had_brace
= FALSE
;
3600 /* Figure out what sort of save we have. */
3601 peek
= input_line_pointer
;
3609 reg
= arm_reg_parse_multi (&peek
);
3613 as_bad (_("register expected"));
3614 ignore_rest_of_line ();
3623 as_bad (_("FPA .unwind_save does not take a register list"));
3624 ignore_rest_of_line ();
3627 s_arm_unwind_save_fpa (reg
->number
);
3630 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
3633 s_arm_unwind_save_vfp_armv6 ();
3635 s_arm_unwind_save_vfp ();
3637 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
3638 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
3641 as_bad (_(".unwind_save does not support this kind of register"));
3642 ignore_rest_of_line ();
3647 /* Parse an unwind_movsp directive. */
3650 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
3656 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3659 as_bad (_(reg_expected_msgs
[REG_TYPE_RN
]));
3660 ignore_rest_of_line ();
3664 /* Optional constant. */
3665 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3667 if (immediate_for_directive (&offset
) == FAIL
)
3673 demand_empty_rest_of_line ();
3675 if (reg
== REG_SP
|| reg
== REG_PC
)
3677 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
3681 if (unwind
.fp_reg
!= REG_SP
)
3682 as_bad (_("unexpected .unwind_movsp directive"));
3684 /* Generate opcode to restore the value. */
3686 add_unwind_opcode (op
, 1);
3688 /* Record the information for later. */
3689 unwind
.fp_reg
= reg
;
3690 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3691 unwind
.sp_restored
= 1;
3694 /* Parse an unwind_pad directive. */
3697 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
3701 if (immediate_for_directive (&offset
) == FAIL
)
3706 as_bad (_("stack increment must be multiple of 4"));
3707 ignore_rest_of_line ();
3711 /* Don't generate any opcodes, just record the details for later. */
3712 unwind
.frame_size
+= offset
;
3713 unwind
.pending_offset
+= offset
;
3715 demand_empty_rest_of_line ();
3718 /* Parse an unwind_setfp directive. */
3721 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
3727 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3728 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3731 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3733 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
3735 as_bad (_("expected <reg>, <reg>"));
3736 ignore_rest_of_line ();
3740 /* Optional constant. */
3741 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3743 if (immediate_for_directive (&offset
) == FAIL
)
3749 demand_empty_rest_of_line ();
3751 if (sp_reg
!= 13 && sp_reg
!= unwind
.fp_reg
)
3753 as_bad (_("register must be either sp or set by a previous"
3754 "unwind_movsp directive"));
3758 /* Don't generate any opcodes, just record the information for later. */
3759 unwind
.fp_reg
= fp_reg
;
3762 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3764 unwind
.fp_offset
-= offset
;
3767 /* Parse an unwind_raw directive. */
3770 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
3773 /* This is an arbitrary limit. */
3774 unsigned char op
[16];
3778 if (exp
.X_op
== O_constant
3779 && skip_past_comma (&input_line_pointer
) != FAIL
)
3781 unwind
.frame_size
+= exp
.X_add_number
;
3785 exp
.X_op
= O_illegal
;
3787 if (exp
.X_op
!= O_constant
)
3789 as_bad (_("expected <offset>, <opcode>"));
3790 ignore_rest_of_line ();
3796 /* Parse the opcode. */
3801 as_bad (_("unwind opcode too long"));
3802 ignore_rest_of_line ();
3804 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
3806 as_bad (_("invalid unwind opcode"));
3807 ignore_rest_of_line ();
3810 op
[count
++] = exp
.X_add_number
;
3812 /* Parse the next byte. */
3813 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3819 /* Add the opcode bytes in reverse order. */
3821 add_unwind_opcode (op
[count
], 1);
3823 demand_empty_rest_of_line ();
3827 /* Parse a .eabi_attribute directive. */
3830 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
3833 bfd_boolean is_string
;
3840 if (exp
.X_op
!= O_constant
)
3843 tag
= exp
.X_add_number
;
3844 if (tag
== 4 || tag
== 5 || tag
== 32 || (tag
> 32 && (tag
& 1) != 0))
3849 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3851 if (tag
== 32 || !is_string
)
3854 if (exp
.X_op
!= O_constant
)
3856 as_bad (_("expected numeric constant"));
3857 ignore_rest_of_line ();
3860 i
= exp
.X_add_number
;
3862 if (tag
== Tag_compatibility
3863 && skip_past_comma (&input_line_pointer
) == FAIL
)
3865 as_bad (_("expected comma"));
3866 ignore_rest_of_line ();
3871 skip_whitespace(input_line_pointer
);
3872 if (*input_line_pointer
!= '"')
3874 input_line_pointer
++;
3875 s
= input_line_pointer
;
3876 while (*input_line_pointer
&& *input_line_pointer
!= '"')
3877 input_line_pointer
++;
3878 if (*input_line_pointer
!= '"')
3880 saved_char
= *input_line_pointer
;
3881 *input_line_pointer
= 0;
3889 if (tag
== Tag_compatibility
)
3890 elf32_arm_add_eabi_attr_compat (stdoutput
, i
, s
);
3892 elf32_arm_add_eabi_attr_string (stdoutput
, tag
, s
);
3894 elf32_arm_add_eabi_attr_int (stdoutput
, tag
, i
);
3898 *input_line_pointer
= saved_char
;
3899 input_line_pointer
++;
3901 demand_empty_rest_of_line ();
3904 as_bad (_("bad string constant"));
3905 ignore_rest_of_line ();
3908 as_bad (_("expected <tag> , <value>"));
3909 ignore_rest_of_line ();
3911 #endif /* OBJ_ELF */
3913 static void s_arm_arch (int);
3914 static void s_arm_object_arch (int);
3915 static void s_arm_cpu (int);
3916 static void s_arm_fpu (int);
3921 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
3928 if (exp
.X_op
== O_symbol
)
3929 exp
.X_op
= O_secrel
;
3931 emit_expr (&exp
, 4);
3933 while (*input_line_pointer
++ == ',');
3935 input_line_pointer
--;
3936 demand_empty_rest_of_line ();
3940 /* This table describes all the machine specific pseudo-ops the assembler
3941 has to support. The fields are:
3942 pseudo-op name without dot
3943 function to call to execute this pseudo-op
3944 Integer arg to pass to the function. */
3946 const pseudo_typeS md_pseudo_table
[] =
3948 /* Never called because '.req' does not start a line. */
3949 { "req", s_req
, 0 },
3950 /* Following two are likewise never called. */
3953 { "unreq", s_unreq
, 0 },
3954 { "bss", s_bss
, 0 },
3955 { "align", s_align
, 0 },
3956 { "arm", s_arm
, 0 },
3957 { "thumb", s_thumb
, 0 },
3958 { "code", s_code
, 0 },
3959 { "force_thumb", s_force_thumb
, 0 },
3960 { "thumb_func", s_thumb_func
, 0 },
3961 { "thumb_set", s_thumb_set
, 0 },
3962 { "even", s_even
, 0 },
3963 { "ltorg", s_ltorg
, 0 },
3964 { "pool", s_ltorg
, 0 },
3965 { "syntax", s_syntax
, 0 },
3966 { "cpu", s_arm_cpu
, 0 },
3967 { "arch", s_arm_arch
, 0 },
3968 { "object_arch", s_arm_object_arch
, 0 },
3969 { "fpu", s_arm_fpu
, 0 },
3971 { "word", s_arm_elf_cons
, 4 },
3972 { "long", s_arm_elf_cons
, 4 },
3973 { "rel31", s_arm_rel31
, 0 },
3974 { "fnstart", s_arm_unwind_fnstart
, 0 },
3975 { "fnend", s_arm_unwind_fnend
, 0 },
3976 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
3977 { "personality", s_arm_unwind_personality
, 0 },
3978 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
3979 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
3980 { "save", s_arm_unwind_save
, 0 },
3981 { "vsave", s_arm_unwind_save
, 1 },
3982 { "movsp", s_arm_unwind_movsp
, 0 },
3983 { "pad", s_arm_unwind_pad
, 0 },
3984 { "setfp", s_arm_unwind_setfp
, 0 },
3985 { "unwind_raw", s_arm_unwind_raw
, 0 },
3986 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
3990 /* These are used for dwarf. */
3994 /* These are used for dwarf2. */
3995 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
3996 { "loc", dwarf2_directive_loc
, 0 },
3997 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
3999 { "extend", float_cons
, 'x' },
4000 { "ldouble", float_cons
, 'x' },
4001 { "packed", float_cons
, 'p' },
4003 {"secrel32", pe_directive_secrel
, 0},
4008 /* Parser functions used exclusively in instruction operands. */
4010 /* Generic immediate-value read function for use in insn parsing.
4011 STR points to the beginning of the immediate (the leading #);
4012 VAL receives the value; if the value is outside [MIN, MAX]
4013 issue an error. PREFIX_OPT is true if the immediate prefix is
4017 parse_immediate (char **str
, int *val
, int min
, int max
,
4018 bfd_boolean prefix_opt
)
4021 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4022 if (exp
.X_op
!= O_constant
)
4024 inst
.error
= _("constant expression required");
4028 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4030 inst
.error
= _("immediate value out of range");
4034 *val
= exp
.X_add_number
;
4038 /* Less-generic immediate-value read function with the possibility of loading a
4039 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4040 instructions. Puts the result directly in inst.operands[i]. */
4043 parse_big_immediate (char **str
, int i
)
4048 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4050 if (exp
.X_op
== O_constant
)
4052 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4053 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4054 O_constant. We have to be careful not to break compilation for
4055 32-bit X_add_number, though. */
4056 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4058 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4059 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4060 inst
.operands
[i
].regisimm
= 1;
4063 else if (exp
.X_op
== O_big
4064 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4065 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4067 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4068 /* Bignums have their least significant bits in
4069 generic_bignum[0]. Make sure we put 32 bits in imm and
4070 32 bits in reg, in a (hopefully) portable way. */
4071 assert (parts
!= 0);
4072 inst
.operands
[i
].imm
= 0;
4073 for (j
= 0; j
< parts
; j
++, idx
++)
4074 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4075 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4076 inst
.operands
[i
].reg
= 0;
4077 for (j
= 0; j
< parts
; j
++, idx
++)
4078 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4079 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4080 inst
.operands
[i
].regisimm
= 1;
4090 /* Returns the pseudo-register number of an FPA immediate constant,
4091 or FAIL if there isn't a valid constant here. */
4094 parse_fpa_immediate (char ** str
)
4096 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4102 /* First try and match exact strings, this is to guarantee
4103 that some formats will work even for cross assembly. */
4105 for (i
= 0; fp_const
[i
]; i
++)
4107 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4111 *str
+= strlen (fp_const
[i
]);
4112 if (is_end_of_line
[(unsigned char) **str
])
4118 /* Just because we didn't get a match doesn't mean that the constant
4119 isn't valid, just that it is in a format that we don't
4120 automatically recognize. Try parsing it with the standard
4121 expression routines. */
4123 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4125 /* Look for a raw floating point number. */
4126 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4127 && is_end_of_line
[(unsigned char) *save_in
])
4129 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4131 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4133 if (words
[j
] != fp_values
[i
][j
])
4137 if (j
== MAX_LITTLENUMS
)
4145 /* Try and parse a more complex expression, this will probably fail
4146 unless the code uses a floating point prefix (eg "0f"). */
4147 save_in
= input_line_pointer
;
4148 input_line_pointer
= *str
;
4149 if (expression (&exp
) == absolute_section
4150 && exp
.X_op
== O_big
4151 && exp
.X_add_number
< 0)
4153 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4155 if (gen_to_words (words
, 5, (long) 15) == 0)
4157 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4159 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4161 if (words
[j
] != fp_values
[i
][j
])
4165 if (j
== MAX_LITTLENUMS
)
4167 *str
= input_line_pointer
;
4168 input_line_pointer
= save_in
;
4175 *str
= input_line_pointer
;
4176 input_line_pointer
= save_in
;
4177 inst
.error
= _("invalid FPA immediate expression");
4181 /* Returns 1 if a number has "quarter-precision" float format
4182 0baBbbbbbc defgh000 00000000 00000000. */
4185 is_quarter_float (unsigned imm
)
4187 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4188 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4191 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4192 0baBbbbbbc defgh000 00000000 00000000.
4193 The zero and minus-zero cases need special handling, since they can't be
4194 encoded in the "quarter-precision" float format, but can nonetheless be
4195 loaded as integer constants. */
4198 parse_qfloat_immediate (char **ccp
, int *immed
)
4202 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4203 int found_fpchar
= 0;
4205 skip_past_char (&str
, '#');
4207 /* We must not accidentally parse an integer as a floating-point number. Make
4208 sure that the value we parse is not an integer by checking for special
4209 characters '.' or 'e'.
4210 FIXME: This is a horrible hack, but doing better is tricky because type
4211 information isn't in a very usable state at parse time. */
4213 skip_whitespace (fpnum
);
4215 if (strncmp (fpnum
, "0x", 2) == 0)
4219 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4220 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4230 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4232 unsigned fpword
= 0;
4235 /* Our FP word must be 32 bits (single-precision FP). */
4236 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4238 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4242 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4255 /* Shift operands. */
4258 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4261 struct asm_shift_name
4264 enum shift_kind kind
;
4267 /* Third argument to parse_shift. */
4268 enum parse_shift_mode
4270 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4271 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4272 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4273 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4274 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4277 /* Parse a <shift> specifier on an ARM data processing instruction.
4278 This has three forms:
4280 (LSL|LSR|ASL|ASR|ROR) Rs
4281 (LSL|LSR|ASL|ASR|ROR) #imm
4284 Note that ASL is assimilated to LSL in the instruction encoding, and
4285 RRX to ROR #0 (which cannot be written as such). */
4288 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4290 const struct asm_shift_name
*shift_name
;
4291 enum shift_kind shift
;
4296 for (p
= *str
; ISALPHA (*p
); p
++)
4301 inst
.error
= _("shift expression expected");
4305 shift_name
= hash_find_n (arm_shift_hsh
, *str
, p
- *str
);
4307 if (shift_name
== NULL
)
4309 inst
.error
= _("shift expression expected");
4313 shift
= shift_name
->kind
;
4317 case NO_SHIFT_RESTRICT
:
4318 case SHIFT_IMMEDIATE
: break;
4320 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4321 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4323 inst
.error
= _("'LSL' or 'ASR' required");
4328 case SHIFT_LSL_IMMEDIATE
:
4329 if (shift
!= SHIFT_LSL
)
4331 inst
.error
= _("'LSL' required");
4336 case SHIFT_ASR_IMMEDIATE
:
4337 if (shift
!= SHIFT_ASR
)
4339 inst
.error
= _("'ASR' required");
4347 if (shift
!= SHIFT_RRX
)
4349 /* Whitespace can appear here if the next thing is a bare digit. */
4350 skip_whitespace (p
);
4352 if (mode
== NO_SHIFT_RESTRICT
4353 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4355 inst
.operands
[i
].imm
= reg
;
4356 inst
.operands
[i
].immisreg
= 1;
4358 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4361 inst
.operands
[i
].shift_kind
= shift
;
4362 inst
.operands
[i
].shifted
= 1;
4367 /* Parse a <shifter_operand> for an ARM data processing instruction:
4370 #<immediate>, <rotate>
4374 where <shift> is defined by parse_shift above, and <rotate> is a
4375 multiple of 2 between 0 and 30. Validation of immediate operands
4376 is deferred to md_apply_fix. */
4379 parse_shifter_operand (char **str
, int i
)
4384 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4386 inst
.operands
[i
].reg
= value
;
4387 inst
.operands
[i
].isreg
= 1;
4389 /* parse_shift will override this if appropriate */
4390 inst
.reloc
.exp
.X_op
= O_constant
;
4391 inst
.reloc
.exp
.X_add_number
= 0;
4393 if (skip_past_comma (str
) == FAIL
)
4396 /* Shift operation on register. */
4397 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4400 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4403 if (skip_past_comma (str
) == SUCCESS
)
4405 /* #x, y -- ie explicit rotation by Y. */
4406 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
4409 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4411 inst
.error
= _("constant expression expected");
4415 value
= expr
.X_add_number
;
4416 if (value
< 0 || value
> 30 || value
% 2 != 0)
4418 inst
.error
= _("invalid rotation");
4421 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4423 inst
.error
= _("invalid constant");
4427 /* Convert to decoded value. md_apply_fix will put it back. */
4428 inst
.reloc
.exp
.X_add_number
4429 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4430 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4433 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4434 inst
.reloc
.pc_rel
= 0;
4438 /* Group relocation information. Each entry in the table contains the
4439 textual name of the relocation as may appear in assembler source
4440 and must end with a colon.
4441 Along with this textual name are the relocation codes to be used if
4442 the corresponding instruction is an ALU instruction (ADD or SUB only),
4443 an LDR, an LDRS, or an LDC. */
4445 struct group_reloc_table_entry
4456 /* Varieties of non-ALU group relocation. */
4463 static struct group_reloc_table_entry group_reloc_table
[] =
4464 { /* Program counter relative: */
4466 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4471 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4472 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4473 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4474 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4476 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4481 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4482 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4483 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4484 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4486 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4487 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4488 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4489 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4490 /* Section base relative */
4492 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4497 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4498 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4499 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4500 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4502 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4507 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4508 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4509 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4510 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4512 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4513 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4514 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4515 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4517 /* Given the address of a pointer pointing to the textual name of a group
4518 relocation as may appear in assembler source, attempt to find its details
4519 in group_reloc_table. The pointer will be updated to the character after
4520 the trailing colon. On failure, FAIL will be returned; SUCCESS
4521 otherwise. On success, *entry will be updated to point at the relevant
4522 group_reloc_table entry. */
4525 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4528 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4530 int length
= strlen (group_reloc_table
[i
].name
);
4532 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0 &&
4533 (*str
)[length
] == ':')
4535 *out
= &group_reloc_table
[i
];
4536 *str
+= (length
+ 1);
4544 /* Parse a <shifter_operand> for an ARM data processing instruction
4545 (as for parse_shifter_operand) where group relocations are allowed:
4548 #<immediate>, <rotate>
4549 #:<group_reloc>:<expression>
4553 where <group_reloc> is one of the strings defined in group_reloc_table.
4554 The hashes are optional.
4556 Everything else is as for parse_shifter_operand. */
4558 static parse_operand_result
4559 parse_shifter_operand_group_reloc (char **str
, int i
)
4561 /* Determine if we have the sequence of characters #: or just :
4562 coming next. If we do, then we check for a group relocation.
4563 If we don't, punt the whole lot to parse_shifter_operand. */
4565 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4566 || (*str
)[0] == ':')
4568 struct group_reloc_table_entry
*entry
;
4570 if ((*str
)[0] == '#')
4575 /* Try to parse a group relocation. Anything else is an error. */
4576 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4578 inst
.error
= _("unknown group relocation");
4579 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4582 /* We now have the group relocation table entry corresponding to
4583 the name in the assembler source. Next, we parse the expression. */
4584 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4585 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4587 /* Record the relocation type (always the ALU variant here). */
4588 inst
.reloc
.type
= entry
->alu_code
;
4589 assert (inst
.reloc
.type
!= 0);
4591 return PARSE_OPERAND_SUCCESS
;
4594 return parse_shifter_operand (str
, i
) == SUCCESS
4595 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4597 /* Never reached. */
4600 /* Parse all forms of an ARM address expression. Information is written
4601 to inst.operands[i] and/or inst.reloc.
4603 Preindexed addressing (.preind=1):
4605 [Rn, #offset] .reg=Rn .reloc.exp=offset
4606 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4607 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4608 .shift_kind=shift .reloc.exp=shift_imm
4610 These three may have a trailing ! which causes .writeback to be set also.
4612 Postindexed addressing (.postind=1, .writeback=1):
4614 [Rn], #offset .reg=Rn .reloc.exp=offset
4615 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4616 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4617 .shift_kind=shift .reloc.exp=shift_imm
4619 Unindexed addressing (.preind=0, .postind=0):
4621 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4625 [Rn]{!} shorthand for [Rn,#0]{!}
4626 =immediate .isreg=0 .reloc.exp=immediate
4627 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4629 It is the caller's responsibility to check for addressing modes not
4630 supported by the instruction, and to set inst.reloc.type. */
4632 static parse_operand_result
4633 parse_address_main (char **str
, int i
, int group_relocations
,
4634 group_reloc_type group_type
)
4639 if (skip_past_char (&p
, '[') == FAIL
)
4641 if (skip_past_char (&p
, '=') == FAIL
)
4643 /* bare address - translate to PC-relative offset */
4644 inst
.reloc
.pc_rel
= 1;
4645 inst
.operands
[i
].reg
= REG_PC
;
4646 inst
.operands
[i
].isreg
= 1;
4647 inst
.operands
[i
].preind
= 1;
4649 /* else a load-constant pseudo op, no special treatment needed here */
4651 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4652 return PARSE_OPERAND_FAIL
;
4655 return PARSE_OPERAND_SUCCESS
;
4658 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4660 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4661 return PARSE_OPERAND_FAIL
;
4663 inst
.operands
[i
].reg
= reg
;
4664 inst
.operands
[i
].isreg
= 1;
4666 if (skip_past_comma (&p
) == SUCCESS
)
4668 inst
.operands
[i
].preind
= 1;
4671 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4673 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4675 inst
.operands
[i
].imm
= reg
;
4676 inst
.operands
[i
].immisreg
= 1;
4678 if (skip_past_comma (&p
) == SUCCESS
)
4679 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4680 return PARSE_OPERAND_FAIL
;
4682 else if (skip_past_char (&p
, ':') == SUCCESS
)
4684 /* FIXME: '@' should be used here, but it's filtered out by generic
4685 code before we get to see it here. This may be subject to
4688 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4689 if (exp
.X_op
!= O_constant
)
4691 inst
.error
= _("alignment must be constant");
4692 return PARSE_OPERAND_FAIL
;
4694 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4695 inst
.operands
[i
].immisalign
= 1;
4696 /* Alignments are not pre-indexes. */
4697 inst
.operands
[i
].preind
= 0;
4701 if (inst
.operands
[i
].negative
)
4703 inst
.operands
[i
].negative
= 0;
4707 if (group_relocations
&&
4708 ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
4711 struct group_reloc_table_entry
*entry
;
4713 /* Skip over the #: or : sequence. */
4719 /* Try to parse a group relocation. Anything else is an
4721 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
4723 inst
.error
= _("unknown group relocation");
4724 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4727 /* We now have the group relocation table entry corresponding to
4728 the name in the assembler source. Next, we parse the
4730 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4731 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4733 /* Record the relocation type. */
4737 inst
.reloc
.type
= entry
->ldr_code
;
4741 inst
.reloc
.type
= entry
->ldrs_code
;
4745 inst
.reloc
.type
= entry
->ldc_code
;
4752 if (inst
.reloc
.type
== 0)
4754 inst
.error
= _("this group relocation is not allowed on this instruction");
4755 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4759 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4760 return PARSE_OPERAND_FAIL
;
4764 if (skip_past_char (&p
, ']') == FAIL
)
4766 inst
.error
= _("']' expected");
4767 return PARSE_OPERAND_FAIL
;
4770 if (skip_past_char (&p
, '!') == SUCCESS
)
4771 inst
.operands
[i
].writeback
= 1;
4773 else if (skip_past_comma (&p
) == SUCCESS
)
4775 if (skip_past_char (&p
, '{') == SUCCESS
)
4777 /* [Rn], {expr} - unindexed, with option */
4778 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
4779 0, 255, TRUE
) == FAIL
)
4780 return PARSE_OPERAND_FAIL
;
4782 if (skip_past_char (&p
, '}') == FAIL
)
4784 inst
.error
= _("'}' expected at end of 'option' field");
4785 return PARSE_OPERAND_FAIL
;
4787 if (inst
.operands
[i
].preind
)
4789 inst
.error
= _("cannot combine index with option");
4790 return PARSE_OPERAND_FAIL
;
4793 return PARSE_OPERAND_SUCCESS
;
4797 inst
.operands
[i
].postind
= 1;
4798 inst
.operands
[i
].writeback
= 1;
4800 if (inst
.operands
[i
].preind
)
4802 inst
.error
= _("cannot combine pre- and post-indexing");
4803 return PARSE_OPERAND_FAIL
;
4807 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4809 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4811 /* We might be using the immediate for alignment already. If we
4812 are, OR the register number into the low-order bits. */
4813 if (inst
.operands
[i
].immisalign
)
4814 inst
.operands
[i
].imm
|= reg
;
4816 inst
.operands
[i
].imm
= reg
;
4817 inst
.operands
[i
].immisreg
= 1;
4819 if (skip_past_comma (&p
) == SUCCESS
)
4820 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4821 return PARSE_OPERAND_FAIL
;
4825 if (inst
.operands
[i
].negative
)
4827 inst
.operands
[i
].negative
= 0;
4830 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4831 return PARSE_OPERAND_FAIL
;
4836 /* If at this point neither .preind nor .postind is set, we have a
4837 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
4838 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
4840 inst
.operands
[i
].preind
= 1;
4841 inst
.reloc
.exp
.X_op
= O_constant
;
4842 inst
.reloc
.exp
.X_add_number
= 0;
4845 return PARSE_OPERAND_SUCCESS
;
4849 parse_address (char **str
, int i
)
4851 return parse_address_main (str
, i
, 0, 0) == PARSE_OPERAND_SUCCESS
4855 static parse_operand_result
4856 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
4858 return parse_address_main (str
, i
, 1, type
);
4861 /* Parse an operand for a MOVW or MOVT instruction. */
4863 parse_half (char **str
)
4868 skip_past_char (&p
, '#');
4869 if (strncasecmp (p
, ":lower16:", 9) == 0)
4870 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
4871 else if (strncasecmp (p
, ":upper16:", 9) == 0)
4872 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
4874 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4880 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4883 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4885 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4887 inst
.error
= _("constant expression expected");
4890 if (inst
.reloc
.exp
.X_add_number
< 0
4891 || inst
.reloc
.exp
.X_add_number
> 0xffff)
4893 inst
.error
= _("immediate value out of range");
4901 /* Miscellaneous. */
4903 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
4904 or a bitmask suitable to be or-ed into the ARM msr instruction. */
4906 parse_psr (char **str
)
4909 unsigned long psr_field
;
4910 const struct asm_psr
*psr
;
4913 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
4914 feature for ease of use and backwards compatibility. */
4916 if (strncasecmp (p
, "SPSR", 4) == 0)
4917 psr_field
= SPSR_BIT
;
4918 else if (strncasecmp (p
, "CPSR", 4) == 0)
4925 while (ISALNUM (*p
) || *p
== '_');
4927 psr
= hash_find_n (arm_v7m_psr_hsh
, start
, p
- start
);
4938 /* A suffix follows. */
4944 while (ISALNUM (*p
) || *p
== '_');
4946 psr
= hash_find_n (arm_psr_hsh
, start
, p
- start
);
4950 psr_field
|= psr
->field
;
4955 goto error
; /* Garbage after "[CS]PSR". */
4957 psr_field
|= (PSR_c
| PSR_f
);
4963 inst
.error
= _("flag for {c}psr instruction expected");
4967 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
4968 value suitable for splatting into the AIF field of the instruction. */
4971 parse_cps_flags (char **str
)
4980 case '\0': case ',':
4983 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
4984 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
4985 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
4988 inst
.error
= _("unrecognized CPS flag");
4993 if (saw_a_flag
== 0)
4995 inst
.error
= _("missing CPS flags");
5003 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5004 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5007 parse_endian_specifier (char **str
)
5012 if (strncasecmp (s
, "BE", 2))
5014 else if (strncasecmp (s
, "LE", 2))
5018 inst
.error
= _("valid endian specifiers are be or le");
5022 if (ISALNUM (s
[2]) || s
[2] == '_')
5024 inst
.error
= _("valid endian specifiers are be or le");
5029 return little_endian
;
5032 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5033 value suitable for poking into the rotate field of an sxt or sxta
5034 instruction, or FAIL on error. */
5037 parse_ror (char **str
)
5042 if (strncasecmp (s
, "ROR", 3) == 0)
5046 inst
.error
= _("missing rotation field after comma");
5050 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5055 case 0: *str
= s
; return 0x0;
5056 case 8: *str
= s
; return 0x1;
5057 case 16: *str
= s
; return 0x2;
5058 case 24: *str
= s
; return 0x3;
5061 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5066 /* Parse a conditional code (from conds[] below). The value returned is in the
5067 range 0 .. 14, or FAIL. */
5069 parse_cond (char **str
)
5072 const struct asm_cond
*c
;
5075 while (ISALPHA (*q
))
5078 c
= hash_find_n (arm_cond_hsh
, p
, q
- p
);
5081 inst
.error
= _("condition required");
5089 /* Parse an option for a barrier instruction. Returns the encoding for the
5092 parse_barrier (char **str
)
5095 const struct asm_barrier_opt
*o
;
5098 while (ISALPHA (*q
))
5101 o
= hash_find_n (arm_barrier_opt_hsh
, p
, q
- p
);
5109 /* Parse the operands of a table branch instruction. Similar to a memory
5112 parse_tb (char **str
)
5117 if (skip_past_char (&p
, '[') == FAIL
)
5119 inst
.error
= _("'[' expected");
5123 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5125 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5128 inst
.operands
[0].reg
= reg
;
5130 if (skip_past_comma (&p
) == FAIL
)
5132 inst
.error
= _("',' expected");
5136 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5138 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5141 inst
.operands
[0].imm
= reg
;
5143 if (skip_past_comma (&p
) == SUCCESS
)
5145 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5147 if (inst
.reloc
.exp
.X_add_number
!= 1)
5149 inst
.error
= _("invalid shift");
5152 inst
.operands
[0].shifted
= 1;
5155 if (skip_past_char (&p
, ']') == FAIL
)
5157 inst
.error
= _("']' expected");
5164 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5165 information on the types the operands can take and how they are encoded.
5166 Up to four operands may be read; this function handles setting the
5167 ".present" field for each read operand itself.
5168 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5169 else returns FAIL. */
5172 parse_neon_mov (char **str
, int *which_operand
)
5174 int i
= *which_operand
, val
;
5175 enum arm_reg_type rtype
;
5177 struct neon_type_el optype
;
5179 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5181 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5182 inst
.operands
[i
].reg
= val
;
5183 inst
.operands
[i
].isscalar
= 1;
5184 inst
.operands
[i
].vectype
= optype
;
5185 inst
.operands
[i
++].present
= 1;
5187 if (skip_past_comma (&ptr
) == FAIL
)
5190 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5193 inst
.operands
[i
].reg
= val
;
5194 inst
.operands
[i
].isreg
= 1;
5195 inst
.operands
[i
].present
= 1;
5197 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5200 /* Cases 0, 1, 2, 3, 5 (D only). */
5201 if (skip_past_comma (&ptr
) == FAIL
)
5204 inst
.operands
[i
].reg
= val
;
5205 inst
.operands
[i
].isreg
= 1;
5206 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5207 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5208 inst
.operands
[i
].isvec
= 1;
5209 inst
.operands
[i
].vectype
= optype
;
5210 inst
.operands
[i
++].present
= 1;
5212 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5214 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5215 Case 13: VMOV <Sd>, <Rm> */
5216 inst
.operands
[i
].reg
= val
;
5217 inst
.operands
[i
].isreg
= 1;
5218 inst
.operands
[i
].present
= 1;
5220 if (rtype
== REG_TYPE_NQ
)
5222 first_error (_("can't use Neon quad register here"));
5225 else if (rtype
!= REG_TYPE_VFS
)
5228 if (skip_past_comma (&ptr
) == FAIL
)
5230 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5232 inst
.operands
[i
].reg
= val
;
5233 inst
.operands
[i
].isreg
= 1;
5234 inst
.operands
[i
].present
= 1;
5237 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5238 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5239 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5240 Case 10: VMOV.F32 <Sd>, #<imm>
5241 Case 11: VMOV.F64 <Dd>, #<imm> */
5242 inst
.operands
[i
].immisfloat
= 1;
5243 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5244 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5245 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5247 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5250 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5251 Case 1: VMOV<c><q> <Dd>, <Dm>
5252 Case 8: VMOV.F32 <Sd>, <Sm>
5253 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5255 inst
.operands
[i
].reg
= val
;
5256 inst
.operands
[i
].isreg
= 1;
5257 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5258 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5259 inst
.operands
[i
].isvec
= 1;
5260 inst
.operands
[i
].vectype
= optype
;
5261 inst
.operands
[i
].present
= 1;
5263 if (skip_past_comma (&ptr
) == SUCCESS
)
5268 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5271 inst
.operands
[i
].reg
= val
;
5272 inst
.operands
[i
].isreg
= 1;
5273 inst
.operands
[i
++].present
= 1;
5275 if (skip_past_comma (&ptr
) == FAIL
)
5278 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5281 inst
.operands
[i
].reg
= val
;
5282 inst
.operands
[i
].isreg
= 1;
5283 inst
.operands
[i
++].present
= 1;
5288 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5292 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5295 inst
.operands
[i
].reg
= val
;
5296 inst
.operands
[i
].isreg
= 1;
5297 inst
.operands
[i
++].present
= 1;
5299 if (skip_past_comma (&ptr
) == FAIL
)
5302 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5304 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5305 inst
.operands
[i
].reg
= val
;
5306 inst
.operands
[i
].isscalar
= 1;
5307 inst
.operands
[i
].present
= 1;
5308 inst
.operands
[i
].vectype
= optype
;
5310 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5312 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5313 inst
.operands
[i
].reg
= val
;
5314 inst
.operands
[i
].isreg
= 1;
5315 inst
.operands
[i
++].present
= 1;
5317 if (skip_past_comma (&ptr
) == FAIL
)
5320 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5323 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5327 inst
.operands
[i
].reg
= val
;
5328 inst
.operands
[i
].isreg
= 1;
5329 inst
.operands
[i
].isvec
= 1;
5330 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5331 inst
.operands
[i
].vectype
= optype
;
5332 inst
.operands
[i
].present
= 1;
5334 if (rtype
== REG_TYPE_VFS
)
5338 if (skip_past_comma (&ptr
) == FAIL
)
5340 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5343 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5346 inst
.operands
[i
].reg
= val
;
5347 inst
.operands
[i
].isreg
= 1;
5348 inst
.operands
[i
].isvec
= 1;
5349 inst
.operands
[i
].issingle
= 1;
5350 inst
.operands
[i
].vectype
= optype
;
5351 inst
.operands
[i
].present
= 1;
5354 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5358 inst
.operands
[i
].reg
= val
;
5359 inst
.operands
[i
].isreg
= 1;
5360 inst
.operands
[i
].isvec
= 1;
5361 inst
.operands
[i
].issingle
= 1;
5362 inst
.operands
[i
].vectype
= optype
;
5363 inst
.operands
[i
++].present
= 1;
5368 first_error (_("parse error"));
5372 /* Successfully parsed the operands. Update args. */
5378 first_error (_("expected comma"));
5382 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5386 /* Matcher codes for parse_operands. */
5387 enum operand_parse_code
5389 OP_stop
, /* end of line */
5391 OP_RR
, /* ARM register */
5392 OP_RRnpc
, /* ARM register, not r15 */
5393 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5394 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5395 OP_RCP
, /* Coprocessor number */
5396 OP_RCN
, /* Coprocessor register */
5397 OP_RF
, /* FPA register */
5398 OP_RVS
, /* VFP single precision register */
5399 OP_RVD
, /* VFP double precision register (0..15) */
5400 OP_RND
, /* Neon double precision register (0..31) */
5401 OP_RNQ
, /* Neon quad precision register */
5402 OP_RVSD
, /* VFP single or double precision register */
5403 OP_RNDQ
, /* Neon double or quad precision register */
5404 OP_RNSDQ
, /* Neon single, double or quad precision register */
5405 OP_RNSC
, /* Neon scalar D[X] */
5406 OP_RVC
, /* VFP control register */
5407 OP_RMF
, /* Maverick F register */
5408 OP_RMD
, /* Maverick D register */
5409 OP_RMFX
, /* Maverick FX register */
5410 OP_RMDX
, /* Maverick DX register */
5411 OP_RMAX
, /* Maverick AX register */
5412 OP_RMDS
, /* Maverick DSPSC register */
5413 OP_RIWR
, /* iWMMXt wR register */
5414 OP_RIWC
, /* iWMMXt wC register */
5415 OP_RIWG
, /* iWMMXt wCG register */
5416 OP_RXA
, /* XScale accumulator register */
5418 OP_REGLST
, /* ARM register list */
5419 OP_VRSLST
, /* VFP single-precision register list */
5420 OP_VRDLST
, /* VFP double-precision register list */
5421 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5422 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5423 OP_NSTRLST
, /* Neon element/structure list */
5425 OP_NILO
, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5426 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5427 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5428 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5429 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5430 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5431 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5432 OP_VMOV
, /* Neon VMOV operands. */
5433 OP_RNDQ_IMVNb
,/* Neon D or Q reg, or immediate good for VMVN. */
5434 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5435 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5437 OP_I0
, /* immediate zero */
5438 OP_I7
, /* immediate value 0 .. 7 */
5439 OP_I15
, /* 0 .. 15 */
5440 OP_I16
, /* 1 .. 16 */
5441 OP_I16z
, /* 0 .. 16 */
5442 OP_I31
, /* 0 .. 31 */
5443 OP_I31w
, /* 0 .. 31, optional trailing ! */
5444 OP_I32
, /* 1 .. 32 */
5445 OP_I32z
, /* 0 .. 32 */
5446 OP_I63
, /* 0 .. 63 */
5447 OP_I63s
, /* -64 .. 63 */
5448 OP_I64
, /* 1 .. 64 */
5449 OP_I64z
, /* 0 .. 64 */
5450 OP_I255
, /* 0 .. 255 */
5452 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5453 OP_I7b
, /* 0 .. 7 */
5454 OP_I15b
, /* 0 .. 15 */
5455 OP_I31b
, /* 0 .. 31 */
5457 OP_SH
, /* shifter operand */
5458 OP_SHG
, /* shifter operand with possible group relocation */
5459 OP_ADDR
, /* Memory address expression (any mode) */
5460 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5461 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5462 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5463 OP_EXP
, /* arbitrary expression */
5464 OP_EXPi
, /* same, with optional immediate prefix */
5465 OP_EXPr
, /* same, with optional relocation suffix */
5466 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5468 OP_CPSF
, /* CPS flags */
5469 OP_ENDI
, /* Endianness specifier */
5470 OP_PSR
, /* CPSR/SPSR mask for msr */
5471 OP_COND
, /* conditional code */
5472 OP_TB
, /* Table branch. */
5474 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5475 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5477 OP_RRnpc_I0
, /* ARM register or literal 0 */
5478 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5479 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5480 OP_RF_IF
, /* FPA register or immediate */
5481 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5482 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5484 /* Optional operands. */
5485 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5486 OP_oI31b
, /* 0 .. 31 */
5487 OP_oI32b
, /* 1 .. 32 */
5488 OP_oIffffb
, /* 0 .. 65535 */
5489 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5491 OP_oRR
, /* ARM register */
5492 OP_oRRnpc
, /* ARM register, not the PC */
5493 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5494 OP_oRND
, /* Optional Neon double precision register */
5495 OP_oRNQ
, /* Optional Neon quad precision register */
5496 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5497 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5498 OP_oSHll
, /* LSL immediate */
5499 OP_oSHar
, /* ASR immediate */
5500 OP_oSHllar
, /* LSL or ASR immediate */
5501 OP_oROR
, /* ROR 0/8/16/24 */
5502 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5504 OP_FIRST_OPTIONAL
= OP_oI7b
5507 /* Generic instruction operand parser. This does no encoding and no
5508 semantic validation; it merely squirrels values away in the inst
5509 structure. Returns SUCCESS or FAIL depending on whether the
5510 specified grammar matched. */
5512 parse_operands (char *str
, const unsigned char *pattern
)
5514 unsigned const char *upat
= pattern
;
5515 char *backtrack_pos
= 0;
5516 const char *backtrack_error
= 0;
5517 int i
, val
, backtrack_index
= 0;
5518 enum arm_reg_type rtype
;
5519 parse_operand_result result
;
5521 #define po_char_or_fail(chr) do { \
5522 if (skip_past_char (&str, chr) == FAIL) \
5526 #define po_reg_or_fail(regtype) do { \
5527 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5528 &inst.operands[i].vectype); \
5531 first_error (_(reg_expected_msgs[regtype])); \
5534 inst.operands[i].reg = val; \
5535 inst.operands[i].isreg = 1; \
5536 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5537 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5538 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5539 || rtype == REG_TYPE_VFD \
5540 || rtype == REG_TYPE_NQ); \
5543 #define po_reg_or_goto(regtype, label) do { \
5544 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5545 &inst.operands[i].vectype); \
5549 inst.operands[i].reg = val; \
5550 inst.operands[i].isreg = 1; \
5551 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5552 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5553 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5554 || rtype == REG_TYPE_VFD \
5555 || rtype == REG_TYPE_NQ); \
5558 #define po_imm_or_fail(min, max, popt) do { \
5559 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5561 inst.operands[i].imm = val; \
5564 #define po_scalar_or_goto(elsz, label) do { \
5565 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \
5568 inst.operands[i].reg = val; \
5569 inst.operands[i].isscalar = 1; \
5572 #define po_misc_or_fail(expr) do { \
5577 #define po_misc_or_fail_no_backtrack(expr) do { \
5579 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
5580 backtrack_pos = 0; \
5581 if (result != PARSE_OPERAND_SUCCESS) \
5585 skip_whitespace (str
);
5587 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5589 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5591 /* Remember where we are in case we need to backtrack. */
5592 assert (!backtrack_pos
);
5593 backtrack_pos
= str
;
5594 backtrack_error
= inst
.error
;
5595 backtrack_index
= i
;
5598 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
5599 po_char_or_fail (',');
5607 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5608 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5609 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5610 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5611 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5612 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5614 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5615 case OP_RVC
: po_reg_or_fail (REG_TYPE_VFC
); break;
5616 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5617 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5618 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5619 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5620 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5621 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5622 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5623 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5624 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5625 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5627 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
5629 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
5630 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
5632 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
5634 /* Neon scalar. Using an element size of 8 means that some invalid
5635 scalars are accepted here, so deal with those in later code. */
5636 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
5638 /* WARNING: We can expand to two operands here. This has the potential
5639 to totally confuse the backtracking mechanism! It will be OK at
5640 least as long as we don't try to use optional args as well,
5644 po_reg_or_goto (REG_TYPE_NDQ
, try_imm
);
5645 inst
.operands
[i
].present
= 1;
5647 skip_past_comma (&str
);
5648 po_reg_or_goto (REG_TYPE_NDQ
, one_reg_only
);
5651 /* Optional register operand was omitted. Unfortunately, it's in
5652 operands[i-1] and we need it to be in inst.operands[i]. Fix that
5653 here (this is a bit grotty). */
5654 inst
.operands
[i
] = inst
.operands
[i
-1];
5655 inst
.operands
[i
-1].present
= 0;
5658 /* There's a possibility of getting a 64-bit immediate here, so
5659 we need special handling. */
5660 if (parse_big_immediate (&str
, i
) == FAIL
)
5662 inst
.error
= _("immediate value is out of range");
5670 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
5673 po_imm_or_fail (0, 0, TRUE
);
5678 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
5683 po_scalar_or_goto (8, try_rr
);
5686 po_reg_or_fail (REG_TYPE_RN
);
5692 po_scalar_or_goto (8, try_nsdq
);
5695 po_reg_or_fail (REG_TYPE_NSDQ
);
5701 po_scalar_or_goto (8, try_ndq
);
5704 po_reg_or_fail (REG_TYPE_NDQ
);
5710 po_scalar_or_goto (8, try_vfd
);
5713 po_reg_or_fail (REG_TYPE_VFD
);
5718 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
5719 not careful then bad things might happen. */
5720 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
5725 po_reg_or_goto (REG_TYPE_NDQ
, try_mvnimm
);
5728 /* There's a possibility of getting a 64-bit immediate here, so
5729 we need special handling. */
5730 if (parse_big_immediate (&str
, i
) == FAIL
)
5732 inst
.error
= _("immediate value is out of range");
5740 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
5743 po_imm_or_fail (0, 63, TRUE
);
5748 po_char_or_fail ('[');
5749 po_reg_or_fail (REG_TYPE_RN
);
5750 po_char_or_fail (']');
5755 po_reg_or_fail (REG_TYPE_RN
);
5756 if (skip_past_char (&str
, '!') == SUCCESS
)
5757 inst
.operands
[i
].writeback
= 1;
5761 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
5762 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
5763 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
5764 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
5765 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
5766 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
5767 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
5768 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
5769 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
5770 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
5771 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
5772 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
5774 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
5776 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
5777 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
5779 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
5780 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
5781 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
5783 /* Immediate variants */
5785 po_char_or_fail ('{');
5786 po_imm_or_fail (0, 255, TRUE
);
5787 po_char_or_fail ('}');
5791 /* The expression parser chokes on a trailing !, so we have
5792 to find it first and zap it. */
5795 while (*s
&& *s
!= ',')
5800 inst
.operands
[i
].writeback
= 1;
5802 po_imm_or_fail (0, 31, TRUE
);
5810 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5815 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5820 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5822 if (inst
.reloc
.exp
.X_op
== O_symbol
)
5824 val
= parse_reloc (&str
);
5827 inst
.error
= _("unrecognized relocation suffix");
5830 else if (val
!= BFD_RELOC_UNUSED
)
5832 inst
.operands
[i
].imm
= val
;
5833 inst
.operands
[i
].hasreloc
= 1;
5838 /* Operand for MOVW or MOVT. */
5840 po_misc_or_fail (parse_half (&str
));
5843 /* Register or expression */
5844 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
5845 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
5847 /* Register or immediate */
5848 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
5849 I0
: po_imm_or_fail (0, 0, FALSE
); break;
5851 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
5853 if (!is_immediate_prefix (*str
))
5856 val
= parse_fpa_immediate (&str
);
5859 /* FPA immediates are encoded as registers 8-15.
5860 parse_fpa_immediate has already applied the offset. */
5861 inst
.operands
[i
].reg
= val
;
5862 inst
.operands
[i
].isreg
= 1;
5865 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
5866 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
5868 /* Two kinds of register */
5871 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5873 || (rege
->type
!= REG_TYPE_MMXWR
5874 && rege
->type
!= REG_TYPE_MMXWC
5875 && rege
->type
!= REG_TYPE_MMXWCG
))
5877 inst
.error
= _("iWMMXt data or control register expected");
5880 inst
.operands
[i
].reg
= rege
->number
;
5881 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
5887 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5889 || (rege
->type
!= REG_TYPE_MMXWC
5890 && rege
->type
!= REG_TYPE_MMXWCG
))
5892 inst
.error
= _("iWMMXt control register expected");
5895 inst
.operands
[i
].reg
= rege
->number
;
5896 inst
.operands
[i
].isreg
= 1;
5901 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
5902 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
5903 case OP_oROR
: val
= parse_ror (&str
); break;
5904 case OP_PSR
: val
= parse_psr (&str
); break;
5905 case OP_COND
: val
= parse_cond (&str
); break;
5906 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
5909 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
5910 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
5913 val
= parse_psr (&str
);
5917 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
5920 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
5922 if (strncasecmp (str
, "APSR_", 5) == 0)
5929 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
5930 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
5931 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
5932 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
5933 default: found
= 16;
5937 inst
.operands
[i
].isvec
= 1;
5944 po_misc_or_fail (parse_tb (&str
));
5947 /* Register lists */
5949 val
= parse_reg_list (&str
);
5952 inst
.operands
[1].writeback
= 1;
5958 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
5962 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
5966 /* Allow Q registers too. */
5967 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5972 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5974 inst
.operands
[i
].issingle
= 1;
5979 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5984 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
5985 &inst
.operands
[i
].vectype
);
5988 /* Addressing modes */
5990 po_misc_or_fail (parse_address (&str
, i
));
5994 po_misc_or_fail_no_backtrack (
5995 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
5999 po_misc_or_fail_no_backtrack (
6000 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6004 po_misc_or_fail_no_backtrack (
6005 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6009 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6013 po_misc_or_fail_no_backtrack (
6014 parse_shifter_operand_group_reloc (&str
, i
));
6018 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6022 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6026 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6030 as_fatal ("unhandled operand code %d", upat
[i
]);
6033 /* Various value-based sanity checks and shared operations. We
6034 do not signal immediate failures for the register constraints;
6035 this allows a syntax error to take precedence. */
6044 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6045 inst
.error
= BAD_PC
;
6063 inst
.operands
[i
].imm
= val
;
6070 /* If we get here, this operand was successfully parsed. */
6071 inst
.operands
[i
].present
= 1;
6075 inst
.error
= BAD_ARGS
;
6080 /* The parse routine should already have set inst.error, but set a
6081 defaut here just in case. */
6083 inst
.error
= _("syntax error");
6087 /* Do not backtrack over a trailing optional argument that
6088 absorbed some text. We will only fail again, with the
6089 'garbage following instruction' error message, which is
6090 probably less helpful than the current one. */
6091 if (backtrack_index
== i
&& backtrack_pos
!= str
6092 && upat
[i
+1] == OP_stop
)
6095 inst
.error
= _("syntax error");
6099 /* Try again, skipping the optional argument at backtrack_pos. */
6100 str
= backtrack_pos
;
6101 inst
.error
= backtrack_error
;
6102 inst
.operands
[backtrack_index
].present
= 0;
6103 i
= backtrack_index
;
6107 /* Check that we have parsed all the arguments. */
6108 if (*str
!= '\0' && !inst
.error
)
6109 inst
.error
= _("garbage following instruction");
6111 return inst
.error
? FAIL
: SUCCESS
;
6114 #undef po_char_or_fail
6115 #undef po_reg_or_fail
6116 #undef po_reg_or_goto
6117 #undef po_imm_or_fail
6118 #undef po_scalar_or_fail
6120 /* Shorthand macro for instruction encoding functions issuing errors. */
6121 #define constraint(expr, err) do { \
6129 /* Functions for operand encoding. ARM, then Thumb. */
6131 #define rotate_left(v, n) (v << n | v >> (32 - n))
6133 /* If VAL can be encoded in the immediate field of an ARM instruction,
6134 return the encoded form. Otherwise, return FAIL. */
6137 encode_arm_immediate (unsigned int val
)
6141 for (i
= 0; i
< 32; i
+= 2)
6142 if ((a
= rotate_left (val
, i
)) <= 0xff)
6143 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6148 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6149 return the encoded form. Otherwise, return FAIL. */
6151 encode_thumb32_immediate (unsigned int val
)
6158 for (i
= 1; i
<= 24; i
++)
6161 if ((val
& ~(0xff << i
)) == 0)
6162 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6166 if (val
== ((a
<< 16) | a
))
6168 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6172 if (val
== ((a
<< 16) | a
))
6173 return 0x200 | (a
>> 8);
6177 /* Encode a VFP SP or DP register number into inst.instruction. */
6180 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6182 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6185 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
6188 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6191 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6196 first_error (_("D register out of range for selected VFP version"));
6204 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6208 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6212 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6216 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6220 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6224 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6232 /* Encode a <shift> in an ARM-format instruction. The immediate,
6233 if any, is handled by md_apply_fix. */
6235 encode_arm_shift (int i
)
6237 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6238 inst
.instruction
|= SHIFT_ROR
<< 5;
6241 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6242 if (inst
.operands
[i
].immisreg
)
6244 inst
.instruction
|= SHIFT_BY_REG
;
6245 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6248 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6253 encode_arm_shifter_operand (int i
)
6255 if (inst
.operands
[i
].isreg
)
6257 inst
.instruction
|= inst
.operands
[i
].reg
;
6258 encode_arm_shift (i
);
6261 inst
.instruction
|= INST_IMMEDIATE
;
6264 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6266 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6268 assert (inst
.operands
[i
].isreg
);
6269 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6271 if (inst
.operands
[i
].preind
)
6275 inst
.error
= _("instruction does not accept preindexed addressing");
6278 inst
.instruction
|= PRE_INDEX
;
6279 if (inst
.operands
[i
].writeback
)
6280 inst
.instruction
|= WRITE_BACK
;
6283 else if (inst
.operands
[i
].postind
)
6285 assert (inst
.operands
[i
].writeback
);
6287 inst
.instruction
|= WRITE_BACK
;
6289 else /* unindexed - only for coprocessor */
6291 inst
.error
= _("instruction does not accept unindexed addressing");
6295 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6296 && (((inst
.instruction
& 0x000f0000) >> 16)
6297 == ((inst
.instruction
& 0x0000f000) >> 12)))
6298 as_warn ((inst
.instruction
& LOAD_BIT
)
6299 ? _("destination register same as write-back base")
6300 : _("source register same as write-back base"));
6303 /* inst.operands[i] was set up by parse_address. Encode it into an
6304 ARM-format mode 2 load or store instruction. If is_t is true,
6305 reject forms that cannot be used with a T instruction (i.e. not
6308 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6310 encode_arm_addr_mode_common (i
, is_t
);
6312 if (inst
.operands
[i
].immisreg
)
6314 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6315 inst
.instruction
|= inst
.operands
[i
].imm
;
6316 if (!inst
.operands
[i
].negative
)
6317 inst
.instruction
|= INDEX_UP
;
6318 if (inst
.operands
[i
].shifted
)
6320 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6321 inst
.instruction
|= SHIFT_ROR
<< 5;
6324 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6325 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6329 else /* immediate offset in inst.reloc */
6331 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6332 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6336 /* inst.operands[i] was set up by parse_address. Encode it into an
6337 ARM-format mode 3 load or store instruction. Reject forms that
6338 cannot be used with such instructions. If is_t is true, reject
6339 forms that cannot be used with a T instruction (i.e. not
6342 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6344 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6346 inst
.error
= _("instruction does not accept scaled register index");
6350 encode_arm_addr_mode_common (i
, is_t
);
6352 if (inst
.operands
[i
].immisreg
)
6354 inst
.instruction
|= inst
.operands
[i
].imm
;
6355 if (!inst
.operands
[i
].negative
)
6356 inst
.instruction
|= INDEX_UP
;
6358 else /* immediate offset in inst.reloc */
6360 inst
.instruction
|= HWOFFSET_IMM
;
6361 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6362 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6366 /* inst.operands[i] was set up by parse_address. Encode it into an
6367 ARM-format instruction. Reject all forms which cannot be encoded
6368 into a coprocessor load/store instruction. If wb_ok is false,
6369 reject use of writeback; if unind_ok is false, reject use of
6370 unindexed addressing. If reloc_override is not 0, use it instead
6371 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6372 (in which case it is preserved). */
6375 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6377 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6379 assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6381 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6383 assert (!inst
.operands
[i
].writeback
);
6386 inst
.error
= _("instruction does not support unindexed addressing");
6389 inst
.instruction
|= inst
.operands
[i
].imm
;
6390 inst
.instruction
|= INDEX_UP
;
6394 if (inst
.operands
[i
].preind
)
6395 inst
.instruction
|= PRE_INDEX
;
6397 if (inst
.operands
[i
].writeback
)
6399 if (inst
.operands
[i
].reg
== REG_PC
)
6401 inst
.error
= _("pc may not be used with write-back");
6406 inst
.error
= _("instruction does not support writeback");
6409 inst
.instruction
|= WRITE_BACK
;
6413 inst
.reloc
.type
= reloc_override
;
6414 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6415 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6416 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6419 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6421 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6427 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6428 Determine whether it can be performed with a move instruction; if
6429 it can, convert inst.instruction to that move instruction and
6430 return 1; if it can't, convert inst.instruction to a literal-pool
6431 load and return 0. If this is not a valid thing to do in the
6432 current context, set inst.error and return 1.
6434 inst.operands[i] describes the destination register. */
6437 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6442 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6446 if ((inst
.instruction
& tbit
) == 0)
6448 inst
.error
= _("invalid pseudo operation");
6451 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6453 inst
.error
= _("constant expression expected");
6456 if (inst
.reloc
.exp
.X_op
== O_constant
)
6460 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6462 /* This can be done with a mov(1) instruction. */
6463 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6464 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6470 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6473 /* This can be done with a mov instruction. */
6474 inst
.instruction
&= LITERAL_MASK
;
6475 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6476 inst
.instruction
|= value
& 0xfff;
6480 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6483 /* This can be done with a mvn instruction. */
6484 inst
.instruction
&= LITERAL_MASK
;
6485 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6486 inst
.instruction
|= value
& 0xfff;
6492 if (add_to_lit_pool () == FAIL
)
6494 inst
.error
= _("literal pool insertion failed");
6497 inst
.operands
[1].reg
= REG_PC
;
6498 inst
.operands
[1].isreg
= 1;
6499 inst
.operands
[1].preind
= 1;
6500 inst
.reloc
.pc_rel
= 1;
6501 inst
.reloc
.type
= (thumb_p
6502 ? BFD_RELOC_ARM_THUMB_OFFSET
6504 ? BFD_RELOC_ARM_HWLITERAL
6505 : BFD_RELOC_ARM_LITERAL
));
6509 /* Functions for instruction encoding, sorted by subarchitecture.
6510 First some generics; their names are taken from the conventional
6511 bit positions for register arguments in ARM format instructions. */
6521 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6527 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6528 inst
.instruction
|= inst
.operands
[1].reg
;
6534 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6535 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6541 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6542 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6548 unsigned Rn
= inst
.operands
[2].reg
;
6549 /* Enforce restrictions on SWP instruction. */
6550 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6551 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6552 _("Rn must not overlap other operands"));
6553 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6554 inst
.instruction
|= inst
.operands
[1].reg
;
6555 inst
.instruction
|= Rn
<< 16;
6561 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6562 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6563 inst
.instruction
|= inst
.operands
[2].reg
;
6569 inst
.instruction
|= inst
.operands
[0].reg
;
6570 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6571 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6577 inst
.instruction
|= inst
.operands
[0].imm
;
6583 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6584 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6587 /* ARM instructions, in alphabetical order by function name (except
6588 that wrapper functions appear immediately after the function they
6591 /* This is a pseudo-op of the form "adr rd, label" to be converted
6592 into a relative address of the form "add rd, pc, #label-.-8". */
6597 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6599 /* Frag hacking will turn this into a sub instruction if the offset turns
6600 out to be negative. */
6601 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6602 inst
.reloc
.pc_rel
= 1;
6603 inst
.reloc
.exp
.X_add_number
-= 8;
6606 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6607 into a relative address of the form:
6608 add rd, pc, #low(label-.-8)"
6609 add rd, rd, #high(label-.-8)" */
6614 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6616 /* Frag hacking will turn this into a sub instruction if the offset turns
6617 out to be negative. */
6618 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
6619 inst
.reloc
.pc_rel
= 1;
6620 inst
.size
= INSN_SIZE
* 2;
6621 inst
.reloc
.exp
.X_add_number
-= 8;
6627 if (!inst
.operands
[1].present
)
6628 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
6629 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6630 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6631 encode_arm_shifter_operand (2);
6637 if (inst
.operands
[0].present
)
6639 constraint ((inst
.instruction
& 0xf0) != 0x40
6640 && inst
.operands
[0].imm
!= 0xf,
6641 "bad barrier type");
6642 inst
.instruction
|= inst
.operands
[0].imm
;
6645 inst
.instruction
|= 0xf;
6651 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
6652 constraint (msb
> 32, _("bit-field extends past end of register"));
6653 /* The instruction encoding stores the LSB and MSB,
6654 not the LSB and width. */
6655 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6656 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
6657 inst
.instruction
|= (msb
- 1) << 16;
6665 /* #0 in second position is alternative syntax for bfc, which is
6666 the same instruction but with REG_PC in the Rm field. */
6667 if (!inst
.operands
[1].isreg
)
6668 inst
.operands
[1].reg
= REG_PC
;
6670 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
6671 constraint (msb
> 32, _("bit-field extends past end of register"));
6672 /* The instruction encoding stores the LSB and MSB,
6673 not the LSB and width. */
6674 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6675 inst
.instruction
|= inst
.operands
[1].reg
;
6676 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6677 inst
.instruction
|= (msb
- 1) << 16;
6683 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
6684 _("bit-field extends past end of register"));
6685 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6686 inst
.instruction
|= inst
.operands
[1].reg
;
6687 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6688 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
6691 /* ARM V5 breakpoint instruction (argument parse)
6692 BKPT <16 bit unsigned immediate>
6693 Instruction is not conditional.
6694 The bit pattern given in insns[] has the COND_ALWAYS condition,
6695 and it is an error if the caller tried to override that. */
6700 /* Top 12 of 16 bits to bits 19:8. */
6701 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
6703 /* Bottom 4 of 16 bits to bits 3:0. */
6704 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
6708 encode_branch (int default_reloc
)
6710 if (inst
.operands
[0].hasreloc
)
6712 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
6713 _("the only suffix valid here is '(plt)'"));
6714 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
6718 inst
.reloc
.type
= default_reloc
;
6720 inst
.reloc
.pc_rel
= 1;
6727 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6728 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6731 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6738 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6740 if (inst
.cond
== COND_ALWAYS
)
6741 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6743 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6747 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6750 /* ARM V5 branch-link-exchange instruction (argument parse)
6751 BLX <target_addr> ie BLX(1)
6752 BLX{<condition>} <Rm> ie BLX(2)
6753 Unfortunately, there are two different opcodes for this mnemonic.
6754 So, the insns[].value is not used, and the code here zaps values
6755 into inst.instruction.
6756 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
6761 if (inst
.operands
[0].isreg
)
6763 /* Arg is a register; the opcode provided by insns[] is correct.
6764 It is not illegal to do "blx pc", just useless. */
6765 if (inst
.operands
[0].reg
== REG_PC
)
6766 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
6768 inst
.instruction
|= inst
.operands
[0].reg
;
6772 /* Arg is an address; this instruction cannot be executed
6773 conditionally, and the opcode must be adjusted. */
6774 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
6775 inst
.instruction
= 0xfa000000;
6777 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6778 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6781 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
6788 if (inst
.operands
[0].reg
== REG_PC
)
6789 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
6791 inst
.instruction
|= inst
.operands
[0].reg
;
6795 /* ARM v5TEJ. Jump to Jazelle code. */
6800 if (inst
.operands
[0].reg
== REG_PC
)
6801 as_tsktsk (_("use of r15 in bxj is not really useful"));
6803 inst
.instruction
|= inst
.operands
[0].reg
;
6806 /* Co-processor data operation:
6807 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
6808 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
6812 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6813 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
6814 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6815 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6816 inst
.instruction
|= inst
.operands
[4].reg
;
6817 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6823 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6824 encode_arm_shifter_operand (1);
6827 /* Transfer between coprocessor and ARM registers.
6828 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
6833 No special properties. */
6838 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6839 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
6840 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6841 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6842 inst
.instruction
|= inst
.operands
[4].reg
;
6843 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6846 /* Transfer between coprocessor register and pair of ARM registers.
6847 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6852 Two XScale instructions are special cases of these:
6854 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
6855 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
6857 Result unpredicatable if Rd or Rn is R15. */
6862 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6863 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
6864 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6865 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6866 inst
.instruction
|= inst
.operands
[4].reg
;
6872 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
6873 if (inst
.operands
[1].present
)
6875 inst
.instruction
|= CPSI_MMOD
;
6876 inst
.instruction
|= inst
.operands
[1].imm
;
6883 inst
.instruction
|= inst
.operands
[0].imm
;
6889 /* There is no IT instruction in ARM mode. We
6890 process it but do not generate code for it. */
6897 int base_reg
= inst
.operands
[0].reg
;
6898 int range
= inst
.operands
[1].imm
;
6900 inst
.instruction
|= base_reg
<< 16;
6901 inst
.instruction
|= range
;
6903 if (inst
.operands
[1].writeback
)
6904 inst
.instruction
|= LDM_TYPE_2_OR_3
;
6906 if (inst
.operands
[0].writeback
)
6908 inst
.instruction
|= WRITE_BACK
;
6909 /* Check for unpredictable uses of writeback. */
6910 if (inst
.instruction
& LOAD_BIT
)
6912 /* Not allowed in LDM type 2. */
6913 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
6914 && ((range
& (1 << REG_PC
)) == 0))
6915 as_warn (_("writeback of base register is UNPREDICTABLE"));
6916 /* Only allowed if base reg not in list for other types. */
6917 else if (range
& (1 << base_reg
))
6918 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
6922 /* Not allowed for type 2. */
6923 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
6924 as_warn (_("writeback of base register is UNPREDICTABLE"));
6925 /* Only allowed if base reg not in list, or first in list. */
6926 else if ((range
& (1 << base_reg
))
6927 && (range
& ((1 << base_reg
) - 1)))
6928 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
6933 /* ARMv5TE load-consecutive (argument parse)
6942 constraint (inst
.operands
[0].reg
% 2 != 0,
6943 _("first destination register must be even"));
6944 constraint (inst
.operands
[1].present
6945 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
6946 _("can only load two consecutive registers"));
6947 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
6948 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
6950 if (!inst
.operands
[1].present
)
6951 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
6953 if (inst
.instruction
& LOAD_BIT
)
6955 /* encode_arm_addr_mode_3 will diagnose overlap between the base
6956 register and the first register written; we have to diagnose
6957 overlap between the base and the second register written here. */
6959 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
6960 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
6961 as_warn (_("base register written back, and overlaps "
6962 "second destination register"));
6964 /* For an index-register load, the index register must not overlap the
6965 destination (even if not write-back). */
6966 else if (inst
.operands
[2].immisreg
6967 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
6968 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
6969 as_warn (_("index register overlaps destination register"));
6972 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6973 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
6979 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
6980 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
6981 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
6982 || inst
.operands
[1].negative
6983 /* This can arise if the programmer has written
6985 or if they have mistakenly used a register name as the last
6988 It is very difficult to distinguish between these two cases
6989 because "rX" might actually be a label. ie the register
6990 name has been occluded by a symbol of the same name. So we
6991 just generate a general 'bad addressing mode' type error
6992 message and leave it up to the programmer to discover the
6993 true cause and fix their mistake. */
6994 || (inst
.operands
[1].reg
== REG_PC
),
6997 constraint (inst
.reloc
.exp
.X_op
!= O_constant
6998 || inst
.reloc
.exp
.X_add_number
!= 0,
6999 _("offset must be zero in ARM encoding"));
7001 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7002 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7003 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7009 constraint (inst
.operands
[0].reg
% 2 != 0,
7010 _("even register required"));
7011 constraint (inst
.operands
[1].present
7012 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7013 _("can only load two consecutive registers"));
7014 /* If op 1 were present and equal to PC, this function wouldn't
7015 have been called in the first place. */
7016 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7018 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7019 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7025 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7026 if (!inst
.operands
[1].isreg
)
7027 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7029 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7035 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7037 if (inst
.operands
[1].preind
)
7039 constraint (inst
.reloc
.exp
.X_op
!= O_constant
||
7040 inst
.reloc
.exp
.X_add_number
!= 0,
7041 _("this instruction requires a post-indexed address"));
7043 inst
.operands
[1].preind
= 0;
7044 inst
.operands
[1].postind
= 1;
7045 inst
.operands
[1].writeback
= 1;
7047 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7048 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7051 /* Halfword and signed-byte load/store operations. */
7056 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7057 if (!inst
.operands
[1].isreg
)
7058 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7060 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7066 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7068 if (inst
.operands
[1].preind
)
7070 constraint (inst
.reloc
.exp
.X_op
!= O_constant
||
7071 inst
.reloc
.exp
.X_add_number
!= 0,
7072 _("this instruction requires a post-indexed address"));
7074 inst
.operands
[1].preind
= 0;
7075 inst
.operands
[1].postind
= 1;
7076 inst
.operands
[1].writeback
= 1;
7078 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7079 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7082 /* Co-processor register load/store.
7083 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7087 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7088 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7089 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7095 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7096 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7097 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7098 && !(inst
.instruction
& 0x00400000))
7099 as_tsktsk (_("Rd and Rm should be different in mla"));
7101 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7102 inst
.instruction
|= inst
.operands
[1].reg
;
7103 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7104 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7110 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7111 encode_arm_shifter_operand (1);
7114 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7121 top
= (inst
.instruction
& 0x00400000) != 0;
7122 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7123 _(":lower16: not allowed this instruction"));
7124 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7125 _(":upper16: not allowed instruction"));
7126 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7127 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7129 imm
= inst
.reloc
.exp
.X_add_number
;
7130 /* The value is in two pieces: 0:11, 16:19. */
7131 inst
.instruction
|= (imm
& 0x00000fff);
7132 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7136 static void do_vfp_nsyn_opcode (const char *);
7139 do_vfp_nsyn_mrs (void)
7141 if (inst
.operands
[0].isvec
)
7143 if (inst
.operands
[1].reg
!= 1)
7144 first_error (_("operand 1 must be FPSCR"));
7145 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7146 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7147 do_vfp_nsyn_opcode ("fmstat");
7149 else if (inst
.operands
[1].isvec
)
7150 do_vfp_nsyn_opcode ("fmrx");
7158 do_vfp_nsyn_msr (void)
7160 if (inst
.operands
[0].isvec
)
7161 do_vfp_nsyn_opcode ("fmxr");
7171 if (do_vfp_nsyn_mrs () == SUCCESS
)
7174 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7175 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7177 _("'CPSR' or 'SPSR' expected"));
7178 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7179 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7182 /* Two possible forms:
7183 "{C|S}PSR_<field>, Rm",
7184 "{C|S}PSR_f, #expression". */
7189 if (do_vfp_nsyn_msr () == SUCCESS
)
7192 inst
.instruction
|= inst
.operands
[0].imm
;
7193 if (inst
.operands
[1].isreg
)
7194 inst
.instruction
|= inst
.operands
[1].reg
;
7197 inst
.instruction
|= INST_IMMEDIATE
;
7198 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7199 inst
.reloc
.pc_rel
= 0;
7206 if (!inst
.operands
[2].present
)
7207 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7208 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7209 inst
.instruction
|= inst
.operands
[1].reg
;
7210 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7212 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7213 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7214 as_tsktsk (_("Rd and Rm should be different in mul"));
7217 /* Long Multiply Parser
7218 UMULL RdLo, RdHi, Rm, Rs
7219 SMULL RdLo, RdHi, Rm, Rs
7220 UMLAL RdLo, RdHi, Rm, Rs
7221 SMLAL RdLo, RdHi, Rm, Rs. */
7226 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7227 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7228 inst
.instruction
|= inst
.operands
[2].reg
;
7229 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7231 /* rdhi, rdlo and rm must all be different. */
7232 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7233 || inst
.operands
[0].reg
== inst
.operands
[2].reg
7234 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7235 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7241 if (inst
.operands
[0].present
)
7243 /* Architectural NOP hints are CPSR sets with no bits selected. */
7244 inst
.instruction
&= 0xf0000000;
7245 inst
.instruction
|= 0x0320f000 + inst
.operands
[0].imm
;
7249 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7250 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7251 Condition defaults to COND_ALWAYS.
7252 Error if Rd, Rn or Rm are R15. */
7257 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7258 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7259 inst
.instruction
|= inst
.operands
[2].reg
;
7260 if (inst
.operands
[3].present
)
7261 encode_arm_shift (3);
7264 /* ARM V6 PKHTB (Argument Parse). */
7269 if (!inst
.operands
[3].present
)
7271 /* If the shift specifier is omitted, turn the instruction
7272 into pkhbt rd, rm, rn. */
7273 inst
.instruction
&= 0xfff00010;
7274 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7275 inst
.instruction
|= inst
.operands
[1].reg
;
7276 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7280 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7281 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7282 inst
.instruction
|= inst
.operands
[2].reg
;
7283 encode_arm_shift (3);
7287 /* ARMv5TE: Preload-Cache
7291 Syntactically, like LDR with B=1, W=0, L=1. */
7296 constraint (!inst
.operands
[0].isreg
,
7297 _("'[' expected after PLD mnemonic"));
7298 constraint (inst
.operands
[0].postind
,
7299 _("post-indexed expression used in preload instruction"));
7300 constraint (inst
.operands
[0].writeback
,
7301 _("writeback used in preload instruction"));
7302 constraint (!inst
.operands
[0].preind
,
7303 _("unindexed addressing used in preload instruction"));
7304 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7307 /* ARMv7: PLI <addr_mode> */
7311 constraint (!inst
.operands
[0].isreg
,
7312 _("'[' expected after PLI mnemonic"));
7313 constraint (inst
.operands
[0].postind
,
7314 _("post-indexed expression used in preload instruction"));
7315 constraint (inst
.operands
[0].writeback
,
7316 _("writeback used in preload instruction"));
7317 constraint (!inst
.operands
[0].preind
,
7318 _("unindexed addressing used in preload instruction"));
7319 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7320 inst
.instruction
&= ~PRE_INDEX
;
7326 inst
.operands
[1] = inst
.operands
[0];
7327 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7328 inst
.operands
[0].isreg
= 1;
7329 inst
.operands
[0].writeback
= 1;
7330 inst
.operands
[0].reg
= REG_SP
;
7334 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7335 word at the specified address and the following word
7337 Unconditionally executed.
7338 Error if Rn is R15. */
7343 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7344 if (inst
.operands
[0].writeback
)
7345 inst
.instruction
|= WRITE_BACK
;
7348 /* ARM V6 ssat (argument parse). */
7353 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7354 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7355 inst
.instruction
|= inst
.operands
[2].reg
;
7357 if (inst
.operands
[3].present
)
7358 encode_arm_shift (3);
7361 /* ARM V6 usat (argument parse). */
7366 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7367 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7368 inst
.instruction
|= inst
.operands
[2].reg
;
7370 if (inst
.operands
[3].present
)
7371 encode_arm_shift (3);
7374 /* ARM V6 ssat16 (argument parse). */
7379 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7380 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7381 inst
.instruction
|= inst
.operands
[2].reg
;
7387 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7388 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7389 inst
.instruction
|= inst
.operands
[2].reg
;
7392 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7393 preserving the other bits.
7395 setend <endian_specifier>, where <endian_specifier> is either
7401 if (inst
.operands
[0].imm
)
7402 inst
.instruction
|= 0x200;
7408 unsigned int Rm
= (inst
.operands
[1].present
7409 ? inst
.operands
[1].reg
7410 : inst
.operands
[0].reg
);
7412 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7413 inst
.instruction
|= Rm
;
7414 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7416 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7417 inst
.instruction
|= SHIFT_BY_REG
;
7420 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7426 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7427 inst
.reloc
.pc_rel
= 0;
7433 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7434 inst
.reloc
.pc_rel
= 0;
7437 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7438 SMLAxy{cond} Rd,Rm,Rs,Rn
7439 SMLAWy{cond} Rd,Rm,Rs,Rn
7440 Error if any register is R15. */
7445 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7446 inst
.instruction
|= inst
.operands
[1].reg
;
7447 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7448 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7451 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7452 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7453 Error if any register is R15.
7454 Warning if Rdlo == Rdhi. */
7459 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7460 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7461 inst
.instruction
|= inst
.operands
[2].reg
;
7462 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7464 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7465 as_tsktsk (_("rdhi and rdlo must be different"));
7468 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7469 SMULxy{cond} Rd,Rm,Rs
7470 Error if any register is R15. */
7475 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7476 inst
.instruction
|= inst
.operands
[1].reg
;
7477 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7480 /* ARM V6 srs (argument parse). The variable fields in the encoding are
7481 the same for both ARM and Thumb-2. */
7488 if (inst
.operands
[0].present
)
7490 reg
= inst
.operands
[0].reg
;
7491 constraint (reg
!= 13, _("SRS base register must be r13"));
7496 inst
.instruction
|= reg
<< 16;
7497 inst
.instruction
|= inst
.operands
[1].imm
;
7498 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
7499 inst
.instruction
|= WRITE_BACK
;
7502 /* ARM V6 strex (argument parse). */
7507 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7508 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7509 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7510 || inst
.operands
[2].negative
7511 /* See comment in do_ldrex(). */
7512 || (inst
.operands
[2].reg
== REG_PC
),
7515 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7516 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
7518 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7519 || inst
.reloc
.exp
.X_add_number
!= 0,
7520 _("offset must be zero in ARM encoding"));
7522 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7523 inst
.instruction
|= inst
.operands
[1].reg
;
7524 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7525 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7531 constraint (inst
.operands
[1].reg
% 2 != 0,
7532 _("even register required"));
7533 constraint (inst
.operands
[2].present
7534 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
7535 _("can only store two consecutive registers"));
7536 /* If op 2 were present and equal to PC, this function wouldn't
7537 have been called in the first place. */
7538 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
7540 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7541 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
7542 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
7545 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7546 inst
.instruction
|= inst
.operands
[1].reg
;
7547 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7550 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7551 extends it to 32-bits, and adds the result to a value in another
7552 register. You can specify a rotation by 0, 8, 16, or 24 bits
7553 before extracting the 16-bit value.
7554 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7555 Condition defaults to COND_ALWAYS.
7556 Error if any register uses R15. */
7561 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7562 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7563 inst
.instruction
|= inst
.operands
[2].reg
;
7564 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
7569 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
7570 Condition defaults to COND_ALWAYS.
7571 Error if any register uses R15. */
7576 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7577 inst
.instruction
|= inst
.operands
[1].reg
;
7578 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
7581 /* VFP instructions. In a logical order: SP variant first, monad
7582 before dyad, arithmetic then move then load/store. */
7585 do_vfp_sp_monadic (void)
7587 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7588 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7592 do_vfp_sp_dyadic (void)
7594 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7595 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7596 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7600 do_vfp_sp_compare_z (void)
7602 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7606 do_vfp_dp_sp_cvt (void)
7608 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7609 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7613 do_vfp_sp_dp_cvt (void)
7615 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7616 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7620 do_vfp_reg_from_sp (void)
7622 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7623 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7627 do_vfp_reg2_from_sp2 (void)
7629 constraint (inst
.operands
[2].imm
!= 2,
7630 _("only two consecutive VFP SP registers allowed here"));
7631 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7632 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7633 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7637 do_vfp_sp_from_reg (void)
7639 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
7640 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7644 do_vfp_sp2_from_reg2 (void)
7646 constraint (inst
.operands
[0].imm
!= 2,
7647 _("only two consecutive VFP SP registers allowed here"));
7648 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
7649 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7650 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7654 do_vfp_sp_ldst (void)
7656 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7657 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7661 do_vfp_dp_ldst (void)
7663 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7664 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7669 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
7671 if (inst
.operands
[0].writeback
)
7672 inst
.instruction
|= WRITE_BACK
;
7674 constraint (ldstm_type
!= VFP_LDSTMIA
,
7675 _("this addressing mode requires base-register writeback"));
7676 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7677 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
7678 inst
.instruction
|= inst
.operands
[1].imm
;
7682 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
7686 if (inst
.operands
[0].writeback
)
7687 inst
.instruction
|= WRITE_BACK
;
7689 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
7690 _("this addressing mode requires base-register writeback"));
7692 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7693 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7695 count
= inst
.operands
[1].imm
<< 1;
7696 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
7699 inst
.instruction
|= count
;
7703 do_vfp_sp_ldstmia (void)
7705 vfp_sp_ldstm (VFP_LDSTMIA
);
7709 do_vfp_sp_ldstmdb (void)
7711 vfp_sp_ldstm (VFP_LDSTMDB
);
7715 do_vfp_dp_ldstmia (void)
7717 vfp_dp_ldstm (VFP_LDSTMIA
);
7721 do_vfp_dp_ldstmdb (void)
7723 vfp_dp_ldstm (VFP_LDSTMDB
);
7727 do_vfp_xp_ldstmia (void)
7729 vfp_dp_ldstm (VFP_LDSTMIAX
);
7733 do_vfp_xp_ldstmdb (void)
7735 vfp_dp_ldstm (VFP_LDSTMDBX
);
7739 do_vfp_dp_rd_rm (void)
7741 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7742 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7746 do_vfp_dp_rn_rd (void)
7748 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
7749 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7753 do_vfp_dp_rd_rn (void)
7755 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7756 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7760 do_vfp_dp_rd_rn_rm (void)
7762 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7763 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7764 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
7770 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7774 do_vfp_dp_rm_rd_rn (void)
7776 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
7777 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7778 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
7781 /* VFPv3 instructions. */
7783 do_vfp_sp_const (void)
7785 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7786 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
7787 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
7791 do_vfp_dp_const (void)
7793 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7794 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
7795 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
7799 vfp_conv (int srcsize
)
7801 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
7802 inst
.instruction
|= (immbits
& 1) << 5;
7803 inst
.instruction
|= (immbits
>> 1);
7807 do_vfp_sp_conv_16 (void)
7809 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7814 do_vfp_dp_conv_16 (void)
7816 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7821 do_vfp_sp_conv_32 (void)
7823 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7828 do_vfp_dp_conv_32 (void)
7830 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7835 /* FPA instructions. Also in a logical order. */
7840 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7841 inst
.instruction
|= inst
.operands
[1].reg
;
7845 do_fpa_ldmstm (void)
7847 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7848 switch (inst
.operands
[1].imm
)
7850 case 1: inst
.instruction
|= CP_T_X
; break;
7851 case 2: inst
.instruction
|= CP_T_Y
; break;
7852 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
7857 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
7859 /* The instruction specified "ea" or "fd", so we can only accept
7860 [Rn]{!}. The instruction does not really support stacking or
7861 unstacking, so we have to emulate these by setting appropriate
7862 bits and offsets. */
7863 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7864 || inst
.reloc
.exp
.X_add_number
!= 0,
7865 _("this instruction does not support indexing"));
7867 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
7868 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
7870 if (!(inst
.instruction
& INDEX_UP
))
7871 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
7873 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
7875 inst
.operands
[2].preind
= 0;
7876 inst
.operands
[2].postind
= 1;
7880 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7884 /* iWMMXt instructions: strictly in alphabetical order. */
7887 do_iwmmxt_tandorc (void)
7889 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
7893 do_iwmmxt_textrc (void)
7895 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7896 inst
.instruction
|= inst
.operands
[1].imm
;
7900 do_iwmmxt_textrm (void)
7902 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7903 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7904 inst
.instruction
|= inst
.operands
[2].imm
;
7908 do_iwmmxt_tinsr (void)
7910 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7911 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7912 inst
.instruction
|= inst
.operands
[2].imm
;
7916 do_iwmmxt_tmia (void)
7918 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
7919 inst
.instruction
|= inst
.operands
[1].reg
;
7920 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7924 do_iwmmxt_waligni (void)
7926 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7927 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7928 inst
.instruction
|= inst
.operands
[2].reg
;
7929 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
7933 do_iwmmxt_wmerge (void)
7935 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7936 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7937 inst
.instruction
|= inst
.operands
[2].reg
;
7938 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
7942 do_iwmmxt_wmov (void)
7944 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
7945 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7946 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7947 inst
.instruction
|= inst
.operands
[1].reg
;
7951 do_iwmmxt_wldstbh (void)
7954 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7956 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
7958 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
7959 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
7963 do_iwmmxt_wldstw (void)
7965 /* RIWR_RIWC clears .isreg for a control register. */
7966 if (!inst
.operands
[0].isreg
)
7968 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7969 inst
.instruction
|= 0xf0000000;
7972 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7973 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7977 do_iwmmxt_wldstd (void)
7979 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7980 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
7981 && inst
.operands
[1].immisreg
)
7983 inst
.instruction
&= ~0x1a000ff;
7984 inst
.instruction
|= (0xf << 28);
7985 if (inst
.operands
[1].preind
)
7986 inst
.instruction
|= PRE_INDEX
;
7987 if (!inst
.operands
[1].negative
)
7988 inst
.instruction
|= INDEX_UP
;
7989 if (inst
.operands
[1].writeback
)
7990 inst
.instruction
|= WRITE_BACK
;
7991 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7992 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
7993 inst
.instruction
|= inst
.operands
[1].imm
;
7996 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8000 do_iwmmxt_wshufh (void)
8002 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8003 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8004 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8005 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8009 do_iwmmxt_wzero (void)
8011 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8012 inst
.instruction
|= inst
.operands
[0].reg
;
8013 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8014 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8018 do_iwmmxt_wrwrwr_or_imm5 (void)
8020 if (inst
.operands
[2].isreg
)
8023 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8024 _("immediate operand requires iWMMXt2"));
8026 if (inst
.operands
[2].imm
== 0)
8028 switch ((inst
.instruction
>> 20) & 0xf)
8034 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8035 inst
.operands
[2].imm
= 16;
8036 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8042 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8043 inst
.operands
[2].imm
= 32;
8044 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8051 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8053 wrn
= (inst
.instruction
>> 16) & 0xf;
8054 inst
.instruction
&= 0xff0fff0f;
8055 inst
.instruction
|= wrn
;
8056 /* Bail out here; the instruction is now assembled. */
8061 /* Map 32 -> 0, etc. */
8062 inst
.operands
[2].imm
&= 0x1f;
8063 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8067 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8068 operations first, then control, shift, and load/store. */
8070 /* Insns like "foo X,Y,Z". */
8073 do_mav_triple (void)
8075 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8076 inst
.instruction
|= inst
.operands
[1].reg
;
8077 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8080 /* Insns like "foo W,X,Y,Z".
8081 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8086 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8087 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8088 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8089 inst
.instruction
|= inst
.operands
[3].reg
;
8092 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8096 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8099 /* Maverick shift immediate instructions.
8100 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8101 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8106 int imm
= inst
.operands
[2].imm
;
8108 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8109 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8111 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8112 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8113 Bit 4 should be 0. */
8114 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8116 inst
.instruction
|= imm
;
8119 /* XScale instructions. Also sorted arithmetic before move. */
8121 /* Xscale multiply-accumulate (argument parse)
8124 MIAxycc acc0,Rm,Rs. */
8129 inst
.instruction
|= inst
.operands
[1].reg
;
8130 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8133 /* Xscale move-accumulator-register (argument parse)
8135 MARcc acc0,RdLo,RdHi. */
8140 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8141 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8144 /* Xscale move-register-accumulator (argument parse)
8146 MRAcc RdLo,RdHi,acc0. */
8151 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8152 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8153 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8156 /* Encoding functions relevant only to Thumb. */
8158 /* inst.operands[i] is a shifted-register operand; encode
8159 it into inst.instruction in the format used by Thumb32. */
8162 encode_thumb32_shifted_operand (int i
)
8164 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8165 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8167 constraint (inst
.operands
[i
].immisreg
,
8168 _("shift by register not allowed in thumb mode"));
8169 inst
.instruction
|= inst
.operands
[i
].reg
;
8170 if (shift
== SHIFT_RRX
)
8171 inst
.instruction
|= SHIFT_ROR
<< 4;
8174 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8175 _("expression too complex"));
8177 constraint (value
> 32
8178 || (value
== 32 && (shift
== SHIFT_LSL
8179 || shift
== SHIFT_ROR
)),
8180 _("shift expression is too large"));
8184 else if (value
== 32)
8187 inst
.instruction
|= shift
<< 4;
8188 inst
.instruction
|= (value
& 0x1c) << 10;
8189 inst
.instruction
|= (value
& 0x03) << 6;
8194 /* inst.operands[i] was set up by parse_address. Encode it into a
8195 Thumb32 format load or store instruction. Reject forms that cannot
8196 be used with such instructions. If is_t is true, reject forms that
8197 cannot be used with a T instruction; if is_d is true, reject forms
8198 that cannot be used with a D instruction. */
8201 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8203 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8205 constraint (!inst
.operands
[i
].isreg
,
8206 _("Instruction does not support =N addresses"));
8208 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8209 if (inst
.operands
[i
].immisreg
)
8211 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
8212 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8213 constraint (inst
.operands
[i
].negative
,
8214 _("Thumb does not support negative register indexing"));
8215 constraint (inst
.operands
[i
].postind
,
8216 _("Thumb does not support register post-indexing"));
8217 constraint (inst
.operands
[i
].writeback
,
8218 _("Thumb does not support register indexing with writeback"));
8219 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8220 _("Thumb supports only LSL in shifted register indexing"));
8222 inst
.instruction
|= inst
.operands
[i
].imm
;
8223 if (inst
.operands
[i
].shifted
)
8225 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8226 _("expression too complex"));
8227 constraint (inst
.reloc
.exp
.X_add_number
< 0
8228 || inst
.reloc
.exp
.X_add_number
> 3,
8229 _("shift out of range"));
8230 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8232 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8234 else if (inst
.operands
[i
].preind
)
8236 constraint (is_pc
&& inst
.operands
[i
].writeback
,
8237 _("cannot use writeback with PC-relative addressing"));
8238 constraint (is_t
&& inst
.operands
[i
].writeback
,
8239 _("cannot use writeback with this instruction"));
8243 inst
.instruction
|= 0x01000000;
8244 if (inst
.operands
[i
].writeback
)
8245 inst
.instruction
|= 0x00200000;
8249 inst
.instruction
|= 0x00000c00;
8250 if (inst
.operands
[i
].writeback
)
8251 inst
.instruction
|= 0x00000100;
8253 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8255 else if (inst
.operands
[i
].postind
)
8257 assert (inst
.operands
[i
].writeback
);
8258 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8259 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8262 inst
.instruction
|= 0x00200000;
8264 inst
.instruction
|= 0x00000900;
8265 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8267 else /* unindexed - only for coprocessor */
8268 inst
.error
= _("instruction does not accept unindexed addressing");
8271 /* Table of Thumb instructions which exist in both 16- and 32-bit
8272 encodings (the latter only in post-V6T2 cores). The index is the
8273 value used in the insns table below. When there is more than one
8274 possible 16-bit encoding for the instruction, this table always
8276 Also contains several pseudo-instructions used during relaxation. */
8277 #define T16_32_TAB \
8278 X(adc, 4140, eb400000), \
8279 X(adcs, 4140, eb500000), \
8280 X(add, 1c00, eb000000), \
8281 X(adds, 1c00, eb100000), \
8282 X(addi, 0000, f1000000), \
8283 X(addis, 0000, f1100000), \
8284 X(add_pc,000f, f20f0000), \
8285 X(add_sp,000d, f10d0000), \
8286 X(adr, 000f, f20f0000), \
8287 X(and, 4000, ea000000), \
8288 X(ands, 4000, ea100000), \
8289 X(asr, 1000, fa40f000), \
8290 X(asrs, 1000, fa50f000), \
8291 X(b, e000, f000b000), \
8292 X(bcond, d000, f0008000), \
8293 X(bic, 4380, ea200000), \
8294 X(bics, 4380, ea300000), \
8295 X(cmn, 42c0, eb100f00), \
8296 X(cmp, 2800, ebb00f00), \
8297 X(cpsie, b660, f3af8400), \
8298 X(cpsid, b670, f3af8600), \
8299 X(cpy, 4600, ea4f0000), \
8300 X(dec_sp,80dd, f1ad0d00), \
8301 X(eor, 4040, ea800000), \
8302 X(eors, 4040, ea900000), \
8303 X(inc_sp,00dd, f10d0d00), \
8304 X(ldmia, c800, e8900000), \
8305 X(ldr, 6800, f8500000), \
8306 X(ldrb, 7800, f8100000), \
8307 X(ldrh, 8800, f8300000), \
8308 X(ldrsb, 5600, f9100000), \
8309 X(ldrsh, 5e00, f9300000), \
8310 X(ldr_pc,4800, f85f0000), \
8311 X(ldr_pc2,4800, f85f0000), \
8312 X(ldr_sp,9800, f85d0000), \
8313 X(lsl, 0000, fa00f000), \
8314 X(lsls, 0000, fa10f000), \
8315 X(lsr, 0800, fa20f000), \
8316 X(lsrs, 0800, fa30f000), \
8317 X(mov, 2000, ea4f0000), \
8318 X(movs, 2000, ea5f0000), \
8319 X(mul, 4340, fb00f000), \
8320 X(muls, 4340, ffffffff), /* no 32b muls */ \
8321 X(mvn, 43c0, ea6f0000), \
8322 X(mvns, 43c0, ea7f0000), \
8323 X(neg, 4240, f1c00000), /* rsb #0 */ \
8324 X(negs, 4240, f1d00000), /* rsbs #0 */ \
8325 X(orr, 4300, ea400000), \
8326 X(orrs, 4300, ea500000), \
8327 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8328 X(push, b400, e92d0000), /* stmdb sp!,... */ \
8329 X(rev, ba00, fa90f080), \
8330 X(rev16, ba40, fa90f090), \
8331 X(revsh, bac0, fa90f0b0), \
8332 X(ror, 41c0, fa60f000), \
8333 X(rors, 41c0, fa70f000), \
8334 X(sbc, 4180, eb600000), \
8335 X(sbcs, 4180, eb700000), \
8336 X(stmia, c000, e8800000), \
8337 X(str, 6000, f8400000), \
8338 X(strb, 7000, f8000000), \
8339 X(strh, 8000, f8200000), \
8340 X(str_sp,9000, f84d0000), \
8341 X(sub, 1e00, eba00000), \
8342 X(subs, 1e00, ebb00000), \
8343 X(subi, 8000, f1a00000), \
8344 X(subis, 8000, f1b00000), \
8345 X(sxtb, b240, fa4ff080), \
8346 X(sxth, b200, fa0ff080), \
8347 X(tst, 4200, ea100f00), \
8348 X(uxtb, b2c0, fa5ff080), \
8349 X(uxth, b280, fa1ff080), \
8350 X(nop, bf00, f3af8000), \
8351 X(yield, bf10, f3af8001), \
8352 X(wfe, bf20, f3af8002), \
8353 X(wfi, bf30, f3af8003), \
8354 X(sev, bf40, f3af9004), /* typo, 8004? */
8356 /* To catch errors in encoding functions, the codes are all offset by
8357 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8358 as 16-bit instructions. */
8359 #define X(a,b,c) T_MNEM_##a
8360 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8363 #define X(a,b,c) 0x##b
8364 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8365 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8368 #define X(a,b,c) 0x##c
8369 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8370 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8371 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8375 /* Thumb instruction encoders, in alphabetical order. */
8379 do_t_add_sub_w (void)
8383 Rd
= inst
.operands
[0].reg
;
8384 Rn
= inst
.operands
[1].reg
;
8386 constraint (Rd
== 15, _("PC not allowed as destination"));
8387 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8388 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8391 /* Parse an add or subtract instruction. We get here with inst.instruction
8392 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8399 Rd
= inst
.operands
[0].reg
;
8400 Rs
= (inst
.operands
[1].present
8401 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8402 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8410 flags
= (inst
.instruction
== T_MNEM_adds
8411 || inst
.instruction
== T_MNEM_subs
);
8413 narrow
= (current_it_mask
== 0);
8415 narrow
= (current_it_mask
!= 0);
8416 if (!inst
.operands
[2].isreg
)
8420 add
= (inst
.instruction
== T_MNEM_add
8421 || inst
.instruction
== T_MNEM_adds
);
8423 if (inst
.size_req
!= 4)
8425 /* Attempt to use a narrow opcode, with relaxation if
8427 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8428 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8429 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8430 opcode
= T_MNEM_add_sp
;
8431 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8432 opcode
= T_MNEM_add_pc
;
8433 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8436 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8438 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8442 inst
.instruction
= THUMB_OP16(opcode
);
8443 inst
.instruction
|= (Rd
<< 4) | Rs
;
8444 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8445 if (inst
.size_req
!= 2)
8446 inst
.relax
= opcode
;
8449 constraint (inst
.size_req
== 2, BAD_HIREG
);
8451 if (inst
.size_req
== 4
8452 || (inst
.size_req
!= 2 && !opcode
))
8456 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
8457 _("only SUBS PC, LR, #const allowed"));
8458 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8459 _("expression too complex"));
8460 constraint (inst
.reloc
.exp
.X_add_number
< 0
8461 || inst
.reloc
.exp
.X_add_number
> 0xff,
8462 _("immediate value out of range"));
8463 inst
.instruction
= T2_SUBS_PC_LR
8464 | inst
.reloc
.exp
.X_add_number
;
8465 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8468 else if (Rs
== REG_PC
)
8470 /* Always use addw/subw. */
8471 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
8472 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8476 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8477 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
8480 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8482 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
8484 inst
.instruction
|= Rd
<< 8;
8485 inst
.instruction
|= Rs
<< 16;
8490 Rn
= inst
.operands
[2].reg
;
8491 /* See if we can do this with a 16-bit instruction. */
8492 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
8494 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8499 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
8500 || inst
.instruction
== T_MNEM_add
)
8503 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8507 if (inst
.instruction
== T_MNEM_add
)
8511 inst
.instruction
= T_OPCODE_ADD_HI
;
8512 inst
.instruction
|= (Rd
& 8) << 4;
8513 inst
.instruction
|= (Rd
& 7);
8514 inst
.instruction
|= Rn
<< 3;
8517 /* ... because addition is commutative! */
8520 inst
.instruction
= T_OPCODE_ADD_HI
;
8521 inst
.instruction
|= (Rd
& 8) << 4;
8522 inst
.instruction
|= (Rd
& 7);
8523 inst
.instruction
|= Rs
<< 3;
8528 /* If we get here, it can't be done in 16 bits. */
8529 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
8530 _("shift must be constant"));
8531 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8532 inst
.instruction
|= Rd
<< 8;
8533 inst
.instruction
|= Rs
<< 16;
8534 encode_thumb32_shifted_operand (2);
8539 constraint (inst
.instruction
== T_MNEM_adds
8540 || inst
.instruction
== T_MNEM_subs
,
8543 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
8545 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
8546 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
8549 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8551 inst
.instruction
|= (Rd
<< 4) | Rs
;
8552 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8556 Rn
= inst
.operands
[2].reg
;
8557 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
8559 /* We now have Rd, Rs, and Rn set to registers. */
8560 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8562 /* Can't do this for SUB. */
8563 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
8564 inst
.instruction
= T_OPCODE_ADD_HI
;
8565 inst
.instruction
|= (Rd
& 8) << 4;
8566 inst
.instruction
|= (Rd
& 7);
8568 inst
.instruction
|= Rn
<< 3;
8570 inst
.instruction
|= Rs
<< 3;
8572 constraint (1, _("dest must overlap one source register"));
8576 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8577 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
8578 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8586 if (unified_syntax
&& inst
.size_req
== 0 && inst
.operands
[0].reg
<= 7)
8588 /* Defer to section relaxation. */
8589 inst
.relax
= inst
.instruction
;
8590 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8591 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8593 else if (unified_syntax
&& inst
.size_req
!= 2)
8595 /* Generate a 32-bit opcode. */
8596 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8597 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8598 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
8599 inst
.reloc
.pc_rel
= 1;
8603 /* Generate a 16-bit opcode. */
8604 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8605 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8606 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
8607 inst
.reloc
.pc_rel
= 1;
8609 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8613 /* Arithmetic instructions for which there is just one 16-bit
8614 instruction encoding, and it allows only two low registers.
8615 For maximal compatibility with ARM syntax, we allow three register
8616 operands even when Thumb-32 instructions are not available, as long
8617 as the first two are identical. For instance, both "sbc r0,r1" and
8618 "sbc r0,r0,r1" are allowed. */
8624 Rd
= inst
.operands
[0].reg
;
8625 Rs
= (inst
.operands
[1].present
8626 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8627 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8628 Rn
= inst
.operands
[2].reg
;
8632 if (!inst
.operands
[2].isreg
)
8634 /* For an immediate, we always generate a 32-bit opcode;
8635 section relaxation will shrink it later if possible. */
8636 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8637 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8638 inst
.instruction
|= Rd
<< 8;
8639 inst
.instruction
|= Rs
<< 16;
8640 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8646 /* See if we can do this with a 16-bit instruction. */
8647 if (THUMB_SETS_FLAGS (inst
.instruction
))
8648 narrow
= current_it_mask
== 0;
8650 narrow
= current_it_mask
!= 0;
8652 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8654 if (inst
.operands
[2].shifted
)
8656 if (inst
.size_req
== 4)
8662 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8663 inst
.instruction
|= Rd
;
8664 inst
.instruction
|= Rn
<< 3;
8668 /* If we get here, it can't be done in 16 bits. */
8669 constraint (inst
.operands
[2].shifted
8670 && inst
.operands
[2].immisreg
,
8671 _("shift must be constant"));
8672 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8673 inst
.instruction
|= Rd
<< 8;
8674 inst
.instruction
|= Rs
<< 16;
8675 encode_thumb32_shifted_operand (2);
8680 /* On its face this is a lie - the instruction does set the
8681 flags. However, the only supported mnemonic in this mode
8683 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8685 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8686 _("unshifted register required"));
8687 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8688 constraint (Rd
!= Rs
,
8689 _("dest and source1 must be the same register"));
8691 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8692 inst
.instruction
|= Rd
;
8693 inst
.instruction
|= Rn
<< 3;
8697 /* Similarly, but for instructions where the arithmetic operation is
8698 commutative, so we can allow either of them to be different from
8699 the destination operand in a 16-bit instruction. For instance, all
8700 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
8707 Rd
= inst
.operands
[0].reg
;
8708 Rs
= (inst
.operands
[1].present
8709 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8710 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8711 Rn
= inst
.operands
[2].reg
;
8715 if (!inst
.operands
[2].isreg
)
8717 /* For an immediate, we always generate a 32-bit opcode;
8718 section relaxation will shrink it later if possible. */
8719 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8720 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8721 inst
.instruction
|= Rd
<< 8;
8722 inst
.instruction
|= Rs
<< 16;
8723 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8729 /* See if we can do this with a 16-bit instruction. */
8730 if (THUMB_SETS_FLAGS (inst
.instruction
))
8731 narrow
= current_it_mask
== 0;
8733 narrow
= current_it_mask
!= 0;
8735 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8737 if (inst
.operands
[2].shifted
)
8739 if (inst
.size_req
== 4)
8746 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8747 inst
.instruction
|= Rd
;
8748 inst
.instruction
|= Rn
<< 3;
8753 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8754 inst
.instruction
|= Rd
;
8755 inst
.instruction
|= Rs
<< 3;
8760 /* If we get here, it can't be done in 16 bits. */
8761 constraint (inst
.operands
[2].shifted
8762 && inst
.operands
[2].immisreg
,
8763 _("shift must be constant"));
8764 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8765 inst
.instruction
|= Rd
<< 8;
8766 inst
.instruction
|= Rs
<< 16;
8767 encode_thumb32_shifted_operand (2);
8772 /* On its face this is a lie - the instruction does set the
8773 flags. However, the only supported mnemonic in this mode
8775 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8777 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8778 _("unshifted register required"));
8779 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8781 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8782 inst
.instruction
|= Rd
;
8785 inst
.instruction
|= Rn
<< 3;
8787 inst
.instruction
|= Rs
<< 3;
8789 constraint (1, _("dest must overlap one source register"));
8796 if (inst
.operands
[0].present
)
8798 constraint ((inst
.instruction
& 0xf0) != 0x40
8799 && inst
.operands
[0].imm
!= 0xf,
8800 "bad barrier type");
8801 inst
.instruction
|= inst
.operands
[0].imm
;
8804 inst
.instruction
|= 0xf;
8810 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8811 constraint (msb
> 32, _("bit-field extends past end of register"));
8812 /* The instruction encoding stores the LSB and MSB,
8813 not the LSB and width. */
8814 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8815 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
8816 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
8817 inst
.instruction
|= msb
- 1;
8825 /* #0 in second position is alternative syntax for bfc, which is
8826 the same instruction but with REG_PC in the Rm field. */
8827 if (!inst
.operands
[1].isreg
)
8828 inst
.operands
[1].reg
= REG_PC
;
8830 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8831 constraint (msb
> 32, _("bit-field extends past end of register"));
8832 /* The instruction encoding stores the LSB and MSB,
8833 not the LSB and width. */
8834 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8835 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8836 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8837 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8838 inst
.instruction
|= msb
- 1;
8844 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8845 _("bit-field extends past end of register"));
8846 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8847 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8848 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8849 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8850 inst
.instruction
|= inst
.operands
[3].imm
- 1;
8853 /* ARM V5 Thumb BLX (argument parse)
8854 BLX <target_addr> which is BLX(1)
8855 BLX <Rm> which is BLX(2)
8856 Unfortunately, there are two different opcodes for this mnemonic.
8857 So, the insns[].value is not used, and the code here zaps values
8858 into inst.instruction.
8860 ??? How to take advantage of the additional two bits of displacement
8861 available in Thumb32 mode? Need new relocation? */
8866 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8867 if (inst
.operands
[0].isreg
)
8868 /* We have a register, so this is BLX(2). */
8869 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8872 /* No register. This must be BLX(1). */
8873 inst
.instruction
= 0xf000e800;
8875 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8876 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8879 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
8880 inst
.reloc
.pc_rel
= 1;
8890 if (current_it_mask
)
8892 /* Conditional branches inside IT blocks are encoded as unconditional
8895 /* A branch must be the last instruction in an IT block. */
8896 constraint (current_it_mask
!= 0x10, BAD_BRANCH
);
8901 if (cond
!= COND_ALWAYS
)
8902 opcode
= T_MNEM_bcond
;
8904 opcode
= inst
.instruction
;
8906 if (unified_syntax
&& inst
.size_req
== 4)
8908 inst
.instruction
= THUMB_OP32(opcode
);
8909 if (cond
== COND_ALWAYS
)
8910 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
8913 assert (cond
!= 0xF);
8914 inst
.instruction
|= cond
<< 22;
8915 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
8920 inst
.instruction
= THUMB_OP16(opcode
);
8921 if (cond
== COND_ALWAYS
)
8922 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
8925 inst
.instruction
|= cond
<< 8;
8926 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
8928 /* Allow section relaxation. */
8929 if (unified_syntax
&& inst
.size_req
!= 2)
8930 inst
.relax
= opcode
;
8933 inst
.reloc
.pc_rel
= 1;
8939 constraint (inst
.cond
!= COND_ALWAYS
,
8940 _("instruction is always unconditional"));
8941 if (inst
.operands
[0].present
)
8943 constraint (inst
.operands
[0].imm
> 255,
8944 _("immediate value out of range"));
8945 inst
.instruction
|= inst
.operands
[0].imm
;
8950 do_t_branch23 (void)
8952 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8953 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8954 inst
.reloc
.pc_rel
= 1;
8956 /* If the destination of the branch is a defined symbol which does not have
8957 the THUMB_FUNC attribute, then we must be calling a function which has
8958 the (interfacearm) attribute. We look for the Thumb entry point to that
8959 function and change the branch to refer to that function instead. */
8960 if ( inst
.reloc
.exp
.X_op
== O_symbol
8961 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8962 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8963 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8964 inst
.reloc
.exp
.X_add_symbol
=
8965 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
8971 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8972 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8973 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
8974 should cause the alignment to be checked once it is known. This is
8975 because BX PC only works if the instruction is word aligned. */
8981 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8982 if (inst
.operands
[0].reg
== REG_PC
)
8983 as_tsktsk (_("use of r15 in bxj is not really useful"));
8985 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8991 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8992 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8993 inst
.instruction
|= inst
.operands
[1].reg
;
8999 constraint (current_it_mask
, BAD_NOT_IT
);
9000 inst
.instruction
|= inst
.operands
[0].imm
;
9006 constraint (current_it_mask
, BAD_NOT_IT
);
9008 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9009 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9011 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9012 inst
.instruction
= 0xf3af8000;
9013 inst
.instruction
|= imod
<< 9;
9014 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9015 if (inst
.operands
[1].present
)
9016 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9020 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9021 && (inst
.operands
[0].imm
& 4),
9022 _("selected processor does not support 'A' form "
9023 "of this instruction"));
9024 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9025 _("Thumb does not support the 2-argument "
9026 "form of this instruction"));
9027 inst
.instruction
|= inst
.operands
[0].imm
;
9031 /* THUMB CPY instruction (argument parse). */
9036 if (inst
.size_req
== 4)
9038 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9039 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9040 inst
.instruction
|= inst
.operands
[1].reg
;
9044 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9045 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9046 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9053 constraint (current_it_mask
, BAD_NOT_IT
);
9054 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9055 inst
.instruction
|= inst
.operands
[0].reg
;
9056 inst
.reloc
.pc_rel
= 1;
9057 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9063 inst
.instruction
|= inst
.operands
[0].imm
;
9069 if (!inst
.operands
[1].present
)
9070 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9071 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9072 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9073 inst
.instruction
|= inst
.operands
[2].reg
;
9079 if (unified_syntax
&& inst
.size_req
== 4)
9080 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9082 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9088 unsigned int cond
= inst
.operands
[0].imm
;
9090 constraint (current_it_mask
, BAD_NOT_IT
);
9091 current_it_mask
= (inst
.instruction
& 0xf) | 0x10;
9094 /* If the condition is a negative condition, invert the mask. */
9095 if ((cond
& 0x1) == 0x0)
9097 unsigned int mask
= inst
.instruction
& 0x000f;
9099 if ((mask
& 0x7) == 0)
9100 /* no conversion needed */;
9101 else if ((mask
& 0x3) == 0)
9103 else if ((mask
& 0x1) == 0)
9108 inst
.instruction
&= 0xfff0;
9109 inst
.instruction
|= mask
;
9112 inst
.instruction
|= cond
<< 4;
9115 /* Helper function used for both push/pop and ldm/stm. */
9117 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9121 load
= (inst
.instruction
& (1 << 20)) != 0;
9123 if (mask
& (1 << 13))
9124 inst
.error
= _("SP not allowed in register list");
9127 if (mask
& (1 << 14)
9128 && mask
& (1 << 15))
9129 inst
.error
= _("LR and PC should not both be in register list");
9131 if ((mask
& (1 << base
)) != 0
9133 as_warn (_("base register should not be in register list "
9134 "when written back"));
9138 if (mask
& (1 << 15))
9139 inst
.error
= _("PC not allowed in register list");
9141 if (mask
& (1 << base
))
9142 as_warn (_("value stored for r%d is UNPREDICTABLE"), base
);
9145 if ((mask
& (mask
- 1)) == 0)
9147 /* Single register transfers implemented as str/ldr. */
9150 if (inst
.instruction
& (1 << 23))
9151 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9153 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9157 if (inst
.instruction
& (1 << 23))
9158 inst
.instruction
= 0x00800000; /* ia -> [base] */
9160 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9163 inst
.instruction
|= 0xf8400000;
9165 inst
.instruction
|= 0x00100000;
9167 mask
= ffs(mask
) - 1;
9171 inst
.instruction
|= WRITE_BACK
;
9173 inst
.instruction
|= mask
;
9174 inst
.instruction
|= base
<< 16;
9180 /* This really doesn't seem worth it. */
9181 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9182 _("expression too complex"));
9183 constraint (inst
.operands
[1].writeback
,
9184 _("Thumb load/store multiple does not support {reglist}^"));
9192 /* See if we can use a 16-bit instruction. */
9193 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9194 && inst
.size_req
!= 4
9195 && !(inst
.operands
[1].imm
& ~0xff))
9197 mask
= 1 << inst
.operands
[0].reg
;
9199 if (inst
.operands
[0].reg
<= 7
9200 && (inst
.instruction
== T_MNEM_stmia
9201 ? inst
.operands
[0].writeback
9202 : (inst
.operands
[0].writeback
9203 == !(inst
.operands
[1].imm
& mask
))))
9205 if (inst
.instruction
== T_MNEM_stmia
9206 && (inst
.operands
[1].imm
& mask
)
9207 && (inst
.operands
[1].imm
& (mask
- 1)))
9208 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9209 inst
.operands
[0].reg
);
9211 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9212 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9213 inst
.instruction
|= inst
.operands
[1].imm
;
9216 else if (inst
.operands
[0] .reg
== REG_SP
9217 && inst
.operands
[0].writeback
)
9219 inst
.instruction
= THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9220 ? T_MNEM_push
: T_MNEM_pop
);
9221 inst
.instruction
|= inst
.operands
[1].imm
;
9228 if (inst
.instruction
< 0xffff)
9229 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9231 encode_thumb2_ldmstm(inst
.operands
[0].reg
, inst
.operands
[1].imm
,
9232 inst
.operands
[0].writeback
);
9237 constraint (inst
.operands
[0].reg
> 7
9238 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9239 constraint (inst
.instruction
!= T_MNEM_ldmia
9240 && inst
.instruction
!= T_MNEM_stmia
,
9241 _("Thumb-2 instruction only valid in unified syntax"));
9242 if (inst
.instruction
== T_MNEM_stmia
)
9244 if (!inst
.operands
[0].writeback
)
9245 as_warn (_("this instruction will write back the base register"));
9246 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9247 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9248 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9249 inst
.operands
[0].reg
);
9253 if (!inst
.operands
[0].writeback
9254 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9255 as_warn (_("this instruction will write back the base register"));
9256 else if (inst
.operands
[0].writeback
9257 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9258 as_warn (_("this instruction will not write back the base register"));
9261 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9262 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9263 inst
.instruction
|= inst
.operands
[1].imm
;
9270 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9271 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9272 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9273 || inst
.operands
[1].negative
,
9276 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9277 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9278 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9284 if (!inst
.operands
[1].present
)
9286 constraint (inst
.operands
[0].reg
== REG_LR
,
9287 _("r14 not allowed as first register "
9288 "when second register is omitted"));
9289 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9291 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9294 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9295 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9296 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9302 unsigned long opcode
;
9305 opcode
= inst
.instruction
;
9308 if (!inst
.operands
[1].isreg
)
9310 if (opcode
<= 0xffff)
9311 inst
.instruction
= THUMB_OP32 (opcode
);
9312 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9315 if (inst
.operands
[1].isreg
9316 && !inst
.operands
[1].writeback
9317 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9318 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9320 && inst
.size_req
!= 4)
9322 /* Insn may have a 16-bit form. */
9323 Rn
= inst
.operands
[1].reg
;
9324 if (inst
.operands
[1].immisreg
)
9326 inst
.instruction
= THUMB_OP16 (opcode
);
9328 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9331 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9332 && opcode
!= T_MNEM_ldrsb
)
9333 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9334 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9341 if (inst
.reloc
.pc_rel
)
9342 opcode
= T_MNEM_ldr_pc2
;
9344 opcode
= T_MNEM_ldr_pc
;
9348 if (opcode
== T_MNEM_ldr
)
9349 opcode
= T_MNEM_ldr_sp
;
9351 opcode
= T_MNEM_str_sp
;
9353 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9357 inst
.instruction
= inst
.operands
[0].reg
;
9358 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9360 inst
.instruction
|= THUMB_OP16 (opcode
);
9361 if (inst
.size_req
== 2)
9362 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9364 inst
.relax
= opcode
;
9368 /* Definitely a 32-bit variant. */
9369 inst
.instruction
= THUMB_OP32 (opcode
);
9370 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9371 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9375 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9377 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9379 /* Only [Rn,Rm] is acceptable. */
9380 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9381 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9382 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9383 || inst
.operands
[1].negative
,
9384 _("Thumb does not support this addressing mode"));
9385 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9389 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9390 if (!inst
.operands
[1].isreg
)
9391 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9394 constraint (!inst
.operands
[1].preind
9395 || inst
.operands
[1].shifted
9396 || inst
.operands
[1].writeback
,
9397 _("Thumb does not support this addressing mode"));
9398 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9400 constraint (inst
.instruction
& 0x0600,
9401 _("byte or halfword not valid for base register"));
9402 constraint (inst
.operands
[1].reg
== REG_PC
9403 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9404 _("r15 based store not allowed"));
9405 constraint (inst
.operands
[1].immisreg
,
9406 _("invalid base register for register offset"));
9408 if (inst
.operands
[1].reg
== REG_PC
)
9409 inst
.instruction
= T_OPCODE_LDR_PC
;
9410 else if (inst
.instruction
& THUMB_LOAD_BIT
)
9411 inst
.instruction
= T_OPCODE_LDR_SP
;
9413 inst
.instruction
= T_OPCODE_STR_SP
;
9415 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9416 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9420 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
9421 if (!inst
.operands
[1].immisreg
)
9423 /* Immediate offset. */
9424 inst
.instruction
|= inst
.operands
[0].reg
;
9425 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9426 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9430 /* Register offset. */
9431 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
9432 constraint (inst
.operands
[1].negative
,
9433 _("Thumb does not support this addressing mode"));
9436 switch (inst
.instruction
)
9438 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
9439 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
9440 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
9441 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
9442 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
9443 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
9444 case 0x5600 /* ldrsb */:
9445 case 0x5e00 /* ldrsh */: break;
9449 inst
.instruction
|= inst
.operands
[0].reg
;
9450 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9451 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
9457 if (!inst
.operands
[1].present
)
9459 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9460 constraint (inst
.operands
[0].reg
== REG_LR
,
9461 _("r14 not allowed here"));
9463 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9464 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9465 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
9472 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9473 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
9479 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9480 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9481 inst
.instruction
|= inst
.operands
[2].reg
;
9482 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9488 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9489 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9490 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9491 inst
.instruction
|= inst
.operands
[3].reg
;
9499 int r0off
= (inst
.instruction
== T_MNEM_mov
9500 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
9501 unsigned long opcode
;
9503 bfd_boolean low_regs
;
9505 low_regs
= (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7);
9506 opcode
= inst
.instruction
;
9507 if (current_it_mask
)
9508 narrow
= opcode
!= T_MNEM_movs
;
9510 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
9511 if (inst
.size_req
== 4
9512 || inst
.operands
[1].shifted
)
9515 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
9516 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
9517 && !inst
.operands
[1].shifted
9518 && inst
.operands
[0].reg
== REG_PC
9519 && inst
.operands
[1].reg
== REG_LR
)
9521 inst
.instruction
= T2_SUBS_PC_LR
;
9525 if (!inst
.operands
[1].isreg
)
9527 /* Immediate operand. */
9528 if (current_it_mask
== 0 && opcode
== T_MNEM_mov
)
9530 if (low_regs
&& narrow
)
9532 inst
.instruction
= THUMB_OP16 (opcode
);
9533 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9534 if (inst
.size_req
== 2)
9535 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9537 inst
.relax
= opcode
;
9541 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9542 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9543 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9544 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9547 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
9548 && (inst
.instruction
== T_MNEM_mov
9549 || inst
.instruction
== T_MNEM_movs
))
9551 /* Register shifts are encoded as separate shift instructions. */
9552 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
9554 if (current_it_mask
)
9559 if (inst
.size_req
== 4)
9562 if (!low_regs
|| inst
.operands
[1].imm
> 7)
9565 if (inst
.operands
[0].reg
!= inst
.operands
[1].reg
)
9568 switch (inst
.operands
[1].shift_kind
)
9571 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
9574 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
9577 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
9580 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
9586 inst
.instruction
= opcode
;
9589 inst
.instruction
|= inst
.operands
[0].reg
;
9590 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
9595 inst
.instruction
|= CONDS_BIT
;
9597 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9598 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9599 inst
.instruction
|= inst
.operands
[1].imm
;
9604 /* Some mov with immediate shift have narrow variants.
9605 Register shifts are handled above. */
9606 if (low_regs
&& inst
.operands
[1].shifted
9607 && (inst
.instruction
== T_MNEM_mov
9608 || inst
.instruction
== T_MNEM_movs
))
9610 if (current_it_mask
)
9611 narrow
= (inst
.instruction
== T_MNEM_mov
);
9613 narrow
= (inst
.instruction
== T_MNEM_movs
);
9618 switch (inst
.operands
[1].shift_kind
)
9620 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
9621 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
9622 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
9623 default: narrow
= FALSE
; break;
9629 inst
.instruction
|= inst
.operands
[0].reg
;
9630 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9631 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
9635 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9636 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9637 encode_thumb32_shifted_operand (1);
9641 switch (inst
.instruction
)
9644 inst
.instruction
= T_OPCODE_MOV_HR
;
9645 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9646 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9647 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9651 /* We know we have low registers at this point.
9652 Generate ADD Rd, Rs, #0. */
9653 inst
.instruction
= T_OPCODE_ADD_I3
;
9654 inst
.instruction
|= inst
.operands
[0].reg
;
9655 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9661 inst
.instruction
= T_OPCODE_CMP_LR
;
9662 inst
.instruction
|= inst
.operands
[0].reg
;
9663 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9667 inst
.instruction
= T_OPCODE_CMP_HR
;
9668 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9669 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9670 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9677 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9678 if (inst
.operands
[1].isreg
)
9680 if (inst
.operands
[0].reg
< 8 && inst
.operands
[1].reg
< 8)
9682 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
9683 since a MOV instruction produces unpredictable results. */
9684 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9685 inst
.instruction
= T_OPCODE_ADD_I3
;
9687 inst
.instruction
= T_OPCODE_CMP_LR
;
9689 inst
.instruction
|= inst
.operands
[0].reg
;
9690 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9694 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9695 inst
.instruction
= T_OPCODE_MOV_HR
;
9697 inst
.instruction
= T_OPCODE_CMP_HR
;
9703 constraint (inst
.operands
[0].reg
> 7,
9704 _("only lo regs allowed with immediate"));
9705 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9706 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9716 top
= (inst
.instruction
& 0x00800000) != 0;
9717 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
9719 constraint (top
, _(":lower16: not allowed this instruction"));
9720 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
9722 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
9724 constraint (!top
, _(":upper16: not allowed this instruction"));
9725 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
9728 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9729 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9731 imm
= inst
.reloc
.exp
.X_add_number
;
9732 inst
.instruction
|= (imm
& 0xf000) << 4;
9733 inst
.instruction
|= (imm
& 0x0800) << 15;
9734 inst
.instruction
|= (imm
& 0x0700) << 4;
9735 inst
.instruction
|= (imm
& 0x00ff);
9744 int r0off
= (inst
.instruction
== T_MNEM_mvn
9745 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
9748 if (inst
.size_req
== 4
9749 || inst
.instruction
> 0xffff
9750 || inst
.operands
[1].shifted
9751 || inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9753 else if (inst
.instruction
== T_MNEM_cmn
)
9755 else if (THUMB_SETS_FLAGS (inst
.instruction
))
9756 narrow
= (current_it_mask
== 0);
9758 narrow
= (current_it_mask
!= 0);
9760 if (!inst
.operands
[1].isreg
)
9762 /* For an immediate, we always generate a 32-bit opcode;
9763 section relaxation will shrink it later if possible. */
9764 if (inst
.instruction
< 0xffff)
9765 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9766 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9767 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9768 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9772 /* See if we can do this with a 16-bit instruction. */
9775 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9776 inst
.instruction
|= inst
.operands
[0].reg
;
9777 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9781 constraint (inst
.operands
[1].shifted
9782 && inst
.operands
[1].immisreg
,
9783 _("shift must be constant"));
9784 if (inst
.instruction
< 0xffff)
9785 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9786 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9787 encode_thumb32_shifted_operand (1);
9793 constraint (inst
.instruction
> 0xffff
9794 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
9795 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
9796 _("unshifted register required"));
9797 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9800 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9801 inst
.instruction
|= inst
.operands
[0].reg
;
9802 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9811 if (do_vfp_nsyn_mrs () == SUCCESS
)
9814 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
9817 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
9818 _("selected processor does not support "
9819 "requested special purpose register"));
9823 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9824 _("selected processor does not support "
9825 "requested special purpose register %x"));
9826 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9827 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
9828 _("'CPSR' or 'SPSR' expected"));
9831 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9832 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9833 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
9841 if (do_vfp_nsyn_msr () == SUCCESS
)
9844 constraint (!inst
.operands
[1].isreg
,
9845 _("Thumb encoding does not support an immediate here"));
9846 flags
= inst
.operands
[0].imm
;
9849 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9850 _("selected processor does not support "
9851 "requested special purpose register"));
9855 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
9856 _("selected processor does not support "
9857 "requested special purpose register"));
9860 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9861 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
9862 inst
.instruction
|= (flags
& 0xff);
9863 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9869 if (!inst
.operands
[2].present
)
9870 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9872 /* There is no 32-bit MULS and no 16-bit MUL. */
9873 if (unified_syntax
&& inst
.instruction
== T_MNEM_mul
)
9875 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9876 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9877 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9878 inst
.instruction
|= inst
.operands
[2].reg
<< 0;
9882 constraint (!unified_syntax
9883 && inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
9884 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9887 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9888 inst
.instruction
|= inst
.operands
[0].reg
;
9890 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9891 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9892 else if (inst
.operands
[0].reg
== inst
.operands
[2].reg
)
9893 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9895 constraint (1, _("dest must overlap one source register"));
9902 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9903 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9904 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9905 inst
.instruction
|= inst
.operands
[3].reg
;
9907 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9908 as_tsktsk (_("rdhi and rdlo must be different"));
9916 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
9918 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9919 inst
.instruction
|= inst
.operands
[0].imm
;
9923 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9924 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
9929 constraint (inst
.operands
[0].present
,
9930 _("Thumb does not support NOP with hints"));
9931 inst
.instruction
= 0x46c0;
9942 if (THUMB_SETS_FLAGS (inst
.instruction
))
9943 narrow
= (current_it_mask
== 0);
9945 narrow
= (current_it_mask
!= 0);
9946 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9948 if (inst
.size_req
== 4)
9953 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9954 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9955 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9959 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9960 inst
.instruction
|= inst
.operands
[0].reg
;
9961 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9966 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9968 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9970 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9971 inst
.instruction
|= inst
.operands
[0].reg
;
9972 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9979 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9980 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9981 inst
.instruction
|= inst
.operands
[2].reg
;
9982 if (inst
.operands
[3].present
)
9984 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
9985 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9986 _("expression too complex"));
9987 inst
.instruction
|= (val
& 0x1c) << 10;
9988 inst
.instruction
|= (val
& 0x03) << 6;
9995 if (!inst
.operands
[3].present
)
9996 inst
.instruction
&= ~0x00000020;
10003 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10007 do_t_push_pop (void)
10011 constraint (inst
.operands
[0].writeback
,
10012 _("push/pop do not support {reglist}^"));
10013 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10014 _("expression too complex"));
10016 mask
= inst
.operands
[0].imm
;
10017 if ((mask
& ~0xff) == 0)
10018 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
10019 else if ((inst
.instruction
== T_MNEM_push
10020 && (mask
& ~0xff) == 1 << REG_LR
)
10021 || (inst
.instruction
== T_MNEM_pop
10022 && (mask
& ~0xff) == 1 << REG_PC
))
10024 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10025 inst
.instruction
|= THUMB_PP_PC_LR
;
10026 inst
.instruction
|= mask
& 0xff;
10028 else if (unified_syntax
)
10030 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10031 encode_thumb2_ldmstm(13, mask
, TRUE
);
10035 inst
.error
= _("invalid register list to push/pop instruction");
10043 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10044 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10050 if (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
10051 && inst
.size_req
!= 4)
10053 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10054 inst
.instruction
|= inst
.operands
[0].reg
;
10055 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10057 else if (unified_syntax
)
10059 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10060 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10061 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10062 inst
.instruction
|= inst
.operands
[1].reg
;
10065 inst
.error
= BAD_HIREG
;
10073 Rd
= inst
.operands
[0].reg
;
10074 Rs
= (inst
.operands
[1].present
10075 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10076 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10078 inst
.instruction
|= Rd
<< 8;
10079 inst
.instruction
|= Rs
<< 16;
10080 if (!inst
.operands
[2].isreg
)
10082 bfd_boolean narrow
;
10084 if ((inst
.instruction
& 0x00100000) != 0)
10085 narrow
= (current_it_mask
== 0);
10087 narrow
= (current_it_mask
!= 0);
10089 if (Rd
> 7 || Rs
> 7)
10092 if (inst
.size_req
== 4 || !unified_syntax
)
10095 if (inst
.reloc
.exp
.X_op
!= O_constant
10096 || inst
.reloc
.exp
.X_add_number
!= 0)
10099 /* Turn rsb #0 into 16-bit neg. We should probably do this via
10100 relaxation, but it doesn't seem worth the hassle. */
10103 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10104 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
10105 inst
.instruction
|= Rs
<< 3;
10106 inst
.instruction
|= Rd
;
10110 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10111 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10115 encode_thumb32_shifted_operand (2);
10121 constraint (current_it_mask
, BAD_NOT_IT
);
10122 if (inst
.operands
[0].imm
)
10123 inst
.instruction
|= 0x8;
10129 if (!inst
.operands
[1].present
)
10130 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
10132 if (unified_syntax
)
10134 bfd_boolean narrow
;
10137 switch (inst
.instruction
)
10140 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
10142 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
10144 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
10146 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
10150 if (THUMB_SETS_FLAGS (inst
.instruction
))
10151 narrow
= (current_it_mask
== 0);
10153 narrow
= (current_it_mask
!= 0);
10154 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10156 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
10158 if (inst
.operands
[2].isreg
10159 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
10160 || inst
.operands
[2].reg
> 7))
10162 if (inst
.size_req
== 4)
10167 if (inst
.operands
[2].isreg
)
10169 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10170 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10171 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10172 inst
.instruction
|= inst
.operands
[2].reg
;
10176 inst
.operands
[1].shifted
= 1;
10177 inst
.operands
[1].shift_kind
= shift_kind
;
10178 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
10179 ? T_MNEM_movs
: T_MNEM_mov
);
10180 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10181 encode_thumb32_shifted_operand (1);
10182 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
10183 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10188 if (inst
.operands
[2].isreg
)
10190 switch (shift_kind
)
10192 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10193 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10194 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10195 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10199 inst
.instruction
|= inst
.operands
[0].reg
;
10200 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10204 switch (shift_kind
)
10206 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10207 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10208 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10211 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10212 inst
.instruction
|= inst
.operands
[0].reg
;
10213 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10219 constraint (inst
.operands
[0].reg
> 7
10220 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
10221 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10223 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
10225 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
10226 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
10227 _("source1 and dest must be same register"));
10229 switch (inst
.instruction
)
10231 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10232 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10233 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10234 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10238 inst
.instruction
|= inst
.operands
[0].reg
;
10239 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10243 switch (inst
.instruction
)
10245 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10246 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10247 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10248 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
10251 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10252 inst
.instruction
|= inst
.operands
[0].reg
;
10253 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10261 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10262 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10263 inst
.instruction
|= inst
.operands
[2].reg
;
10269 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10270 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10271 _("expression too complex"));
10272 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10273 inst
.instruction
|= (value
& 0xf000) >> 12;
10274 inst
.instruction
|= (value
& 0x0ff0);
10275 inst
.instruction
|= (value
& 0x000f) << 16;
10281 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10282 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10283 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10285 if (inst
.operands
[3].present
)
10287 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10288 _("expression too complex"));
10290 if (inst
.reloc
.exp
.X_add_number
!= 0)
10292 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10293 inst
.instruction
|= 0x00200000; /* sh bit */
10294 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10295 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10297 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10304 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10305 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10306 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10312 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10313 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10314 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10315 || inst
.operands
[2].negative
,
10318 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10319 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10320 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10321 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10327 if (!inst
.operands
[2].present
)
10328 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
10330 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10331 || inst
.operands
[0].reg
== inst
.operands
[2].reg
10332 || inst
.operands
[0].reg
== inst
.operands
[3].reg
10333 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
10336 inst
.instruction
|= inst
.operands
[0].reg
;
10337 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10338 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10339 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10345 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10346 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10347 inst
.instruction
|= inst
.operands
[2].reg
;
10348 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
10354 if (inst
.instruction
<= 0xffff && inst
.size_req
!= 4
10355 && inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
10356 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
10358 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10359 inst
.instruction
|= inst
.operands
[0].reg
;
10360 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10362 else if (unified_syntax
)
10364 if (inst
.instruction
<= 0xffff)
10365 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10366 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10367 inst
.instruction
|= inst
.operands
[1].reg
;
10368 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
10372 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
10373 _("Thumb encoding does not support rotation"));
10374 constraint (1, BAD_HIREG
);
10381 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
10389 half
= (inst
.instruction
& 0x10) != 0;
10390 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
10391 constraint (inst
.operands
[0].immisreg
,
10392 _("instruction requires register index"));
10393 constraint (inst
.operands
[0].imm
== 15,
10394 _("PC is not a valid index register"));
10395 constraint (!half
&& inst
.operands
[0].shifted
,
10396 _("instruction does not allow shifted index"));
10397 inst
.instruction
|= (inst
.operands
[0].reg
<< 16) | inst
.operands
[0].imm
;
10403 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10404 inst
.instruction
|= inst
.operands
[1].imm
;
10405 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10407 if (inst
.operands
[3].present
)
10409 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10410 _("expression too complex"));
10411 if (inst
.reloc
.exp
.X_add_number
!= 0)
10413 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10414 inst
.instruction
|= 0x00200000; /* sh bit */
10416 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10417 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10419 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10426 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10427 inst
.instruction
|= inst
.operands
[1].imm
;
10428 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10431 /* Neon instruction encoder helpers. */
10433 /* Encodings for the different types for various Neon opcodes. */
10435 /* An "invalid" code for the following tables. */
10438 struct neon_tab_entry
10441 unsigned float_or_poly
;
10442 unsigned scalar_or_imm
;
10445 /* Map overloaded Neon opcodes to their respective encodings. */
10446 #define NEON_ENC_TAB \
10447 X(vabd, 0x0000700, 0x1200d00, N_INV), \
10448 X(vmax, 0x0000600, 0x0000f00, N_INV), \
10449 X(vmin, 0x0000610, 0x0200f00, N_INV), \
10450 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
10451 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
10452 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
10453 X(vadd, 0x0000800, 0x0000d00, N_INV), \
10454 X(vsub, 0x1000800, 0x0200d00, N_INV), \
10455 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
10456 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
10457 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
10458 /* Register variants of the following two instructions are encoded as
10459 vcge / vcgt with the operands reversed. */ \
10460 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
10461 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
10462 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
10463 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
10464 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
10465 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
10466 X(vmlal, 0x0800800, N_INV, 0x0800240), \
10467 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
10468 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
10469 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
10470 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
10471 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
10472 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
10473 X(vshl, 0x0000400, N_INV, 0x0800510), \
10474 X(vqshl, 0x0000410, N_INV, 0x0800710), \
10475 X(vand, 0x0000110, N_INV, 0x0800030), \
10476 X(vbic, 0x0100110, N_INV, 0x0800030), \
10477 X(veor, 0x1000110, N_INV, N_INV), \
10478 X(vorn, 0x0300110, N_INV, 0x0800010), \
10479 X(vorr, 0x0200110, N_INV, 0x0800010), \
10480 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
10481 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
10482 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
10483 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
10484 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
10485 X(vst1, 0x0000000, 0x0800000, N_INV), \
10486 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
10487 X(vst2, 0x0000100, 0x0800100, N_INV), \
10488 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
10489 X(vst3, 0x0000200, 0x0800200, N_INV), \
10490 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
10491 X(vst4, 0x0000300, 0x0800300, N_INV), \
10492 X(vmovn, 0x1b20200, N_INV, N_INV), \
10493 X(vtrn, 0x1b20080, N_INV, N_INV), \
10494 X(vqmovn, 0x1b20200, N_INV, N_INV), \
10495 X(vqmovun, 0x1b20240, N_INV, N_INV), \
10496 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
10497 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \
10498 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \
10499 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
10500 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
10501 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
10502 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
10506 #define X(OPC,I,F,S) N_MNEM_##OPC
10511 static const struct neon_tab_entry neon_enc_tab
[] =
10513 #define X(OPC,I,F,S) { (I), (F), (S) }
10518 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10519 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10520 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10521 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10522 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10523 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10524 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10525 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10526 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10527 #define NEON_ENC_SINGLE(X) \
10528 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
10529 #define NEON_ENC_DOUBLE(X) \
10530 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
10532 /* Define shapes for instruction operands. The following mnemonic characters
10533 are used in this table:
10535 F - VFP S<n> register
10536 D - Neon D<n> register
10537 Q - Neon Q<n> register
10541 L - D<n> register list
10543 This table is used to generate various data:
10544 - enumerations of the form NS_DDR to be used as arguments to
10546 - a table classifying shapes into single, double, quad, mixed.
10547 - a table used to drive neon_select_shape.
10550 #define NEON_SHAPE_DEF \
10551 X(3, (D, D, D), DOUBLE), \
10552 X(3, (Q, Q, Q), QUAD), \
10553 X(3, (D, D, I), DOUBLE), \
10554 X(3, (Q, Q, I), QUAD), \
10555 X(3, (D, D, S), DOUBLE), \
10556 X(3, (Q, Q, S), QUAD), \
10557 X(2, (D, D), DOUBLE), \
10558 X(2, (Q, Q), QUAD), \
10559 X(2, (D, S), DOUBLE), \
10560 X(2, (Q, S), QUAD), \
10561 X(2, (D, R), DOUBLE), \
10562 X(2, (Q, R), QUAD), \
10563 X(2, (D, I), DOUBLE), \
10564 X(2, (Q, I), QUAD), \
10565 X(3, (D, L, D), DOUBLE), \
10566 X(2, (D, Q), MIXED), \
10567 X(2, (Q, D), MIXED), \
10568 X(3, (D, Q, I), MIXED), \
10569 X(3, (Q, D, I), MIXED), \
10570 X(3, (Q, D, D), MIXED), \
10571 X(3, (D, Q, Q), MIXED), \
10572 X(3, (Q, Q, D), MIXED), \
10573 X(3, (Q, D, S), MIXED), \
10574 X(3, (D, Q, S), MIXED), \
10575 X(4, (D, D, D, I), DOUBLE), \
10576 X(4, (Q, Q, Q, I), QUAD), \
10577 X(2, (F, F), SINGLE), \
10578 X(3, (F, F, F), SINGLE), \
10579 X(2, (F, I), SINGLE), \
10580 X(2, (F, D), MIXED), \
10581 X(2, (D, F), MIXED), \
10582 X(3, (F, F, I), MIXED), \
10583 X(4, (R, R, F, F), SINGLE), \
10584 X(4, (F, F, R, R), SINGLE), \
10585 X(3, (D, R, R), DOUBLE), \
10586 X(3, (R, R, D), DOUBLE), \
10587 X(2, (S, R), SINGLE), \
10588 X(2, (R, S), SINGLE), \
10589 X(2, (F, R), SINGLE), \
10590 X(2, (R, F), SINGLE)
10592 #define S2(A,B) NS_##A##B
10593 #define S3(A,B,C) NS_##A##B##C
10594 #define S4(A,B,C,D) NS_##A##B##C##D
10596 #define X(N, L, C) S##N L
10609 enum neon_shape_class
10617 #define X(N, L, C) SC_##C
10619 static enum neon_shape_class neon_shape_class
[] =
10637 /* Register widths of above. */
10638 static unsigned neon_shape_el_size
[] =
10649 struct neon_shape_info
10652 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
10655 #define S2(A,B) { SE_##A, SE_##B }
10656 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
10657 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
10659 #define X(N, L, C) { N, S##N L }
10661 static struct neon_shape_info neon_shape_tab
[] =
10671 /* Bit masks used in type checking given instructions.
10672 'N_EQK' means the type must be the same as (or based on in some way) the key
10673 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
10674 set, various other bits can be set as well in order to modify the meaning of
10675 the type constraint. */
10677 enum neon_type_mask
10699 N_KEY
= 0x100000, /* key element (main type specifier). */
10700 N_EQK
= 0x200000, /* given operand has the same type & size as the key. */
10701 N_VFP
= 0x400000, /* VFP mode: operand size must match register width. */
10702 N_DBL
= 0x000001, /* if N_EQK, this operand is twice the size. */
10703 N_HLF
= 0x000002, /* if N_EQK, this operand is half the size. */
10704 N_SGN
= 0x000004, /* if N_EQK, this operand is forced to be signed. */
10705 N_UNS
= 0x000008, /* if N_EQK, this operand is forced to be unsigned. */
10706 N_INT
= 0x000010, /* if N_EQK, this operand is forced to be integer. */
10707 N_FLT
= 0x000020, /* if N_EQK, this operand is forced to be float. */
10708 N_SIZ
= 0x000040, /* if N_EQK, this operand is forced to be size-only. */
10710 N_MAX_NONSPECIAL
= N_F64
10713 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
10715 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
10716 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
10717 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
10718 #define N_SUF_32 (N_SU_32 | N_F32)
10719 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
10720 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
10722 /* Pass this as the first type argument to neon_check_type to ignore types
10724 #define N_IGNORE_TYPE (N_KEY | N_EQK)
10726 /* Select a "shape" for the current instruction (describing register types or
10727 sizes) from a list of alternatives. Return NS_NULL if the current instruction
10728 doesn't fit. For non-polymorphic shapes, checking is usually done as a
10729 function of operand parsing, so this function doesn't need to be called.
10730 Shapes should be listed in order of decreasing length. */
10732 static enum neon_shape
10733 neon_select_shape (enum neon_shape shape
, ...)
10736 enum neon_shape first_shape
= shape
;
10738 /* Fix missing optional operands. FIXME: we don't know at this point how
10739 many arguments we should have, so this makes the assumption that we have
10740 > 1. This is true of all current Neon opcodes, I think, but may not be
10741 true in the future. */
10742 if (!inst
.operands
[1].present
)
10743 inst
.operands
[1] = inst
.operands
[0];
10745 va_start (ap
, shape
);
10747 for (; shape
!= NS_NULL
; shape
= va_arg (ap
, int))
10752 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
10754 if (!inst
.operands
[j
].present
)
10760 switch (neon_shape_tab
[shape
].el
[j
])
10763 if (!(inst
.operands
[j
].isreg
10764 && inst
.operands
[j
].isvec
10765 && inst
.operands
[j
].issingle
10766 && !inst
.operands
[j
].isquad
))
10771 if (!(inst
.operands
[j
].isreg
10772 && inst
.operands
[j
].isvec
10773 && !inst
.operands
[j
].isquad
10774 && !inst
.operands
[j
].issingle
))
10779 if (!(inst
.operands
[j
].isreg
10780 && !inst
.operands
[j
].isvec
))
10785 if (!(inst
.operands
[j
].isreg
10786 && inst
.operands
[j
].isvec
10787 && inst
.operands
[j
].isquad
10788 && !inst
.operands
[j
].issingle
))
10793 if (!(!inst
.operands
[j
].isreg
10794 && !inst
.operands
[j
].isscalar
))
10799 if (!(!inst
.operands
[j
].isreg
10800 && inst
.operands
[j
].isscalar
))
10814 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
10815 first_error (_("invalid instruction shape"));
10820 /* True if SHAPE is predominantly a quadword operation (most of the time, this
10821 means the Q bit should be set). */
10824 neon_quad (enum neon_shape shape
)
10826 return neon_shape_class
[shape
] == SC_QUAD
;
10830 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
10833 /* Allow modification to be made to types which are constrained to be
10834 based on the key element, based on bits set alongside N_EQK. */
10835 if ((typebits
& N_EQK
) != 0)
10837 if ((typebits
& N_HLF
) != 0)
10839 else if ((typebits
& N_DBL
) != 0)
10841 if ((typebits
& N_SGN
) != 0)
10842 *g_type
= NT_signed
;
10843 else if ((typebits
& N_UNS
) != 0)
10844 *g_type
= NT_unsigned
;
10845 else if ((typebits
& N_INT
) != 0)
10846 *g_type
= NT_integer
;
10847 else if ((typebits
& N_FLT
) != 0)
10848 *g_type
= NT_float
;
10849 else if ((typebits
& N_SIZ
) != 0)
10850 *g_type
= NT_untyped
;
10854 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
10855 operand type, i.e. the single type specified in a Neon instruction when it
10856 is the only one given. */
10858 static struct neon_type_el
10859 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
10861 struct neon_type_el dest
= *key
;
10863 assert ((thisarg
& N_EQK
) != 0);
10865 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
10870 /* Convert Neon type and size into compact bitmask representation. */
10872 static enum neon_type_mask
10873 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
10880 case 8: return N_8
;
10881 case 16: return N_16
;
10882 case 32: return N_32
;
10883 case 64: return N_64
;
10891 case 8: return N_I8
;
10892 case 16: return N_I16
;
10893 case 32: return N_I32
;
10894 case 64: return N_I64
;
10902 case 32: return N_F32
;
10903 case 64: return N_F64
;
10911 case 8: return N_P8
;
10912 case 16: return N_P16
;
10920 case 8: return N_S8
;
10921 case 16: return N_S16
;
10922 case 32: return N_S32
;
10923 case 64: return N_S64
;
10931 case 8: return N_U8
;
10932 case 16: return N_U16
;
10933 case 32: return N_U32
;
10934 case 64: return N_U64
;
10945 /* Convert compact Neon bitmask type representation to a type and size. Only
10946 handles the case where a single bit is set in the mask. */
10949 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
10950 enum neon_type_mask mask
)
10952 if ((mask
& N_EQK
) != 0)
10955 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
10957 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
10959 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
10961 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
10966 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
10968 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
10969 *type
= NT_unsigned
;
10970 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
10971 *type
= NT_integer
;
10972 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
10973 *type
= NT_untyped
;
10974 else if ((mask
& (N_P8
| N_P16
)) != 0)
10976 else if ((mask
& (N_F32
| N_F64
)) != 0)
10984 /* Modify a bitmask of allowed types. This is only needed for type
10988 modify_types_allowed (unsigned allowed
, unsigned mods
)
10991 enum neon_el_type type
;
10997 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
10999 if (el_type_of_type_chk (&type
, &size
, allowed
& i
) == SUCCESS
)
11001 neon_modify_type_size (mods
, &type
, &size
);
11002 destmask
|= type_chk_of_el_type (type
, size
);
11009 /* Check type and return type classification.
11010 The manual states (paraphrase): If one datatype is given, it indicates the
11012 - the second operand, if there is one
11013 - the operand, if there is no second operand
11014 - the result, if there are no operands.
11015 This isn't quite good enough though, so we use a concept of a "key" datatype
11016 which is set on a per-instruction basis, which is the one which matters when
11017 only one data type is written.
11018 Note: this function has side-effects (e.g. filling in missing operands). All
11019 Neon instructions should call it before performing bit encoding. */
11021 static struct neon_type_el
11022 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
11025 unsigned i
, pass
, key_el
= 0;
11026 unsigned types
[NEON_MAX_TYPE_ELS
];
11027 enum neon_el_type k_type
= NT_invtype
;
11028 unsigned k_size
= -1u;
11029 struct neon_type_el badtype
= {NT_invtype
, -1};
11030 unsigned key_allowed
= 0;
11032 /* Optional registers in Neon instructions are always (not) in operand 1.
11033 Fill in the missing operand here, if it was omitted. */
11034 if (els
> 1 && !inst
.operands
[1].present
)
11035 inst
.operands
[1] = inst
.operands
[0];
11037 /* Suck up all the varargs. */
11039 for (i
= 0; i
< els
; i
++)
11041 unsigned thisarg
= va_arg (ap
, unsigned);
11042 if (thisarg
== N_IGNORE_TYPE
)
11047 types
[i
] = thisarg
;
11048 if ((thisarg
& N_KEY
) != 0)
11053 if (inst
.vectype
.elems
> 0)
11054 for (i
= 0; i
< els
; i
++)
11055 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
11057 first_error (_("types specified in both the mnemonic and operands"));
11061 /* Duplicate inst.vectype elements here as necessary.
11062 FIXME: No idea if this is exactly the same as the ARM assembler,
11063 particularly when an insn takes one register and one non-register
11065 if (inst
.vectype
.elems
== 1 && els
> 1)
11068 inst
.vectype
.elems
= els
;
11069 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
11070 for (j
= 0; j
< els
; j
++)
11072 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11075 else if (inst
.vectype
.elems
== 0 && els
> 0)
11078 /* No types were given after the mnemonic, so look for types specified
11079 after each operand. We allow some flexibility here; as long as the
11080 "key" operand has a type, we can infer the others. */
11081 for (j
= 0; j
< els
; j
++)
11082 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
11083 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
11085 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
11087 for (j
= 0; j
< els
; j
++)
11088 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
11089 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11094 first_error (_("operand types can't be inferred"));
11098 else if (inst
.vectype
.elems
!= els
)
11100 first_error (_("type specifier has the wrong number of parts"));
11104 for (pass
= 0; pass
< 2; pass
++)
11106 for (i
= 0; i
< els
; i
++)
11108 unsigned thisarg
= types
[i
];
11109 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
11110 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
11111 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
11112 unsigned g_size
= inst
.vectype
.el
[i
].size
;
11114 /* Decay more-specific signed & unsigned types to sign-insensitive
11115 integer types if sign-specific variants are unavailable. */
11116 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
11117 && (types_allowed
& N_SU_ALL
) == 0)
11118 g_type
= NT_integer
;
11120 /* If only untyped args are allowed, decay any more specific types to
11121 them. Some instructions only care about signs for some element
11122 sizes, so handle that properly. */
11123 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
11124 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
11125 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
11126 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
11127 g_type
= NT_untyped
;
11131 if ((thisarg
& N_KEY
) != 0)
11135 key_allowed
= thisarg
& ~N_KEY
;
11140 if ((thisarg
& N_VFP
) != 0)
11142 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
11143 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
11145 /* In VFP mode, operands must match register widths. If we
11146 have a key operand, use its width, else use the width of
11147 the current operand. */
11153 if (regwidth
!= match
)
11155 first_error (_("operand size must match register width"));
11160 if ((thisarg
& N_EQK
) == 0)
11162 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
11164 if ((given_type
& types_allowed
) == 0)
11166 first_error (_("bad type in Neon instruction"));
11172 enum neon_el_type mod_k_type
= k_type
;
11173 unsigned mod_k_size
= k_size
;
11174 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
11175 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
11177 first_error (_("inconsistent types in Neon instruction"));
11185 return inst
.vectype
.el
[key_el
];
11188 /* Neon-style VFP instruction forwarding. */
11190 /* Thumb VFP instructions have 0xE in the condition field. */
11193 do_vfp_cond_or_thumb (void)
11196 inst
.instruction
|= 0xe0000000;
11198 inst
.instruction
|= inst
.cond
<< 28;
11201 /* Look up and encode a simple mnemonic, for use as a helper function for the
11202 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
11203 etc. It is assumed that operand parsing has already been done, and that the
11204 operands are in the form expected by the given opcode (this isn't necessarily
11205 the same as the form in which they were parsed, hence some massaging must
11206 take place before this function is called).
11207 Checks current arch version against that in the looked-up opcode. */
11210 do_vfp_nsyn_opcode (const char *opname
)
11212 const struct asm_opcode
*opcode
;
11214 opcode
= hash_find (arm_ops_hsh
, opname
);
11219 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
11220 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
11225 inst
.instruction
= opcode
->tvalue
;
11226 opcode
->tencode ();
11230 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
11231 opcode
->aencode ();
11236 do_vfp_nsyn_add_sub (enum neon_shape rs
)
11238 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
11243 do_vfp_nsyn_opcode ("fadds");
11245 do_vfp_nsyn_opcode ("fsubs");
11250 do_vfp_nsyn_opcode ("faddd");
11252 do_vfp_nsyn_opcode ("fsubd");
11256 /* Check operand types to see if this is a VFP instruction, and if so call
11260 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
11262 enum neon_shape rs
;
11263 struct neon_type_el et
;
11268 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11269 et
= neon_check_type (2, rs
,
11270 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11274 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11275 et
= neon_check_type (3, rs
,
11276 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11283 if (et
.type
!= NT_invtype
)
11295 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
11297 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
11302 do_vfp_nsyn_opcode ("fmacs");
11304 do_vfp_nsyn_opcode ("fmscs");
11309 do_vfp_nsyn_opcode ("fmacd");
11311 do_vfp_nsyn_opcode ("fmscd");
11316 do_vfp_nsyn_mul (enum neon_shape rs
)
11319 do_vfp_nsyn_opcode ("fmuls");
11321 do_vfp_nsyn_opcode ("fmuld");
11325 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
11327 int is_neg
= (inst
.instruction
& 0x80) != 0;
11328 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
11333 do_vfp_nsyn_opcode ("fnegs");
11335 do_vfp_nsyn_opcode ("fabss");
11340 do_vfp_nsyn_opcode ("fnegd");
11342 do_vfp_nsyn_opcode ("fabsd");
11346 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
11347 insns belong to Neon, and are handled elsewhere. */
11350 do_vfp_nsyn_ldm_stm (int is_dbmode
)
11352 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
11356 do_vfp_nsyn_opcode ("fldmdbs");
11358 do_vfp_nsyn_opcode ("fldmias");
11363 do_vfp_nsyn_opcode ("fstmdbs");
11365 do_vfp_nsyn_opcode ("fstmias");
11370 do_vfp_nsyn_sqrt (void)
11372 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11373 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11376 do_vfp_nsyn_opcode ("fsqrts");
11378 do_vfp_nsyn_opcode ("fsqrtd");
11382 do_vfp_nsyn_div (void)
11384 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11385 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11386 N_F32
| N_F64
| N_KEY
| N_VFP
);
11389 do_vfp_nsyn_opcode ("fdivs");
11391 do_vfp_nsyn_opcode ("fdivd");
11395 do_vfp_nsyn_nmul (void)
11397 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11398 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11399 N_F32
| N_F64
| N_KEY
| N_VFP
);
11403 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11404 do_vfp_sp_dyadic ();
11408 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11409 do_vfp_dp_rd_rn_rm ();
11411 do_vfp_cond_or_thumb ();
11415 do_vfp_nsyn_cmp (void)
11417 if (inst
.operands
[1].isreg
)
11419 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11420 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11424 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11425 do_vfp_sp_monadic ();
11429 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11430 do_vfp_dp_rd_rm ();
11435 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
11436 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
11438 switch (inst
.instruction
& 0x0fffffff)
11441 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
11444 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
11452 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11453 do_vfp_sp_compare_z ();
11457 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11461 do_vfp_cond_or_thumb ();
11465 nsyn_insert_sp (void)
11467 inst
.operands
[1] = inst
.operands
[0];
11468 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
11469 inst
.operands
[0].reg
= 13;
11470 inst
.operands
[0].isreg
= 1;
11471 inst
.operands
[0].writeback
= 1;
11472 inst
.operands
[0].present
= 1;
11476 do_vfp_nsyn_push (void)
11479 if (inst
.operands
[1].issingle
)
11480 do_vfp_nsyn_opcode ("fstmdbs");
11482 do_vfp_nsyn_opcode ("fstmdbd");
11486 do_vfp_nsyn_pop (void)
11489 if (inst
.operands
[1].issingle
)
11490 do_vfp_nsyn_opcode ("fldmias");
11492 do_vfp_nsyn_opcode ("fldmiad");
11495 /* Fix up Neon data-processing instructions, ORing in the correct bits for
11496 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
11499 neon_dp_fixup (unsigned i
)
11503 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
11517 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
11521 neon_logbits (unsigned x
)
11523 return ffs (x
) - 4;
11526 #define LOW4(R) ((R) & 0xf)
11527 #define HI1(R) (((R) >> 4) & 1)
11529 /* Encode insns with bit pattern:
11531 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
11532 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
11534 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
11535 different meaning for some instruction. */
11538 neon_three_same (int isquad
, int ubit
, int size
)
11540 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11541 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11542 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
11543 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
11544 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
11545 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
11546 inst
.instruction
|= (isquad
!= 0) << 6;
11547 inst
.instruction
|= (ubit
!= 0) << 24;
11549 inst
.instruction
|= neon_logbits (size
) << 20;
11551 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11554 /* Encode instructions of the form:
11556 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
11557 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
11559 Don't write size if SIZE == -1. */
11562 neon_two_same (int qbit
, int ubit
, int size
)
11564 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11565 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11566 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11567 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11568 inst
.instruction
|= (qbit
!= 0) << 6;
11569 inst
.instruction
|= (ubit
!= 0) << 24;
11572 inst
.instruction
|= neon_logbits (size
) << 18;
11574 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11577 /* Neon instruction encoders, in approximate order of appearance. */
11580 do_neon_dyadic_i_su (void)
11582 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11583 struct neon_type_el et
= neon_check_type (3, rs
,
11584 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
11585 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11589 do_neon_dyadic_i64_su (void)
11591 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11592 struct neon_type_el et
= neon_check_type (3, rs
,
11593 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11594 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11598 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
11601 unsigned size
= et
.size
>> 3;
11602 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11603 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11604 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11605 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11606 inst
.instruction
|= (isquad
!= 0) << 6;
11607 inst
.instruction
|= immbits
<< 16;
11608 inst
.instruction
|= (size
>> 3) << 7;
11609 inst
.instruction
|= (size
& 0x7) << 19;
11611 inst
.instruction
|= (uval
!= 0) << 24;
11613 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11617 do_neon_shl_imm (void)
11619 if (!inst
.operands
[2].isreg
)
11621 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11622 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
11623 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11624 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
11628 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11629 struct neon_type_el et
= neon_check_type (3, rs
,
11630 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11633 /* VSHL/VQSHL 3-register variants have syntax such as:
11635 whereas other 3-register operations encoded by neon_three_same have
11638 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
11640 tmp
= inst
.operands
[2].reg
;
11641 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11642 inst
.operands
[1].reg
= tmp
;
11643 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11644 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11649 do_neon_qshl_imm (void)
11651 if (!inst
.operands
[2].isreg
)
11653 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11654 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
11656 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11657 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
11658 inst
.operands
[2].imm
);
11662 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11663 struct neon_type_el et
= neon_check_type (3, rs
,
11664 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11667 /* See note in do_neon_shl_imm. */
11668 tmp
= inst
.operands
[2].reg
;
11669 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11670 inst
.operands
[1].reg
= tmp
;
11671 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11672 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11677 do_neon_rshl (void)
11679 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11680 struct neon_type_el et
= neon_check_type (3, rs
,
11681 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11684 tmp
= inst
.operands
[2].reg
;
11685 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11686 inst
.operands
[1].reg
= tmp
;
11687 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11691 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
11693 /* Handle .I8 pseudo-instructions. */
11696 /* Unfortunately, this will make everything apart from zero out-of-range.
11697 FIXME is this the intended semantics? There doesn't seem much point in
11698 accepting .I8 if so. */
11699 immediate
|= immediate
<< 8;
11705 if (immediate
== (immediate
& 0x000000ff))
11707 *immbits
= immediate
;
11710 else if (immediate
== (immediate
& 0x0000ff00))
11712 *immbits
= immediate
>> 8;
11715 else if (immediate
== (immediate
& 0x00ff0000))
11717 *immbits
= immediate
>> 16;
11720 else if (immediate
== (immediate
& 0xff000000))
11722 *immbits
= immediate
>> 24;
11725 if ((immediate
& 0xffff) != (immediate
>> 16))
11726 goto bad_immediate
;
11727 immediate
&= 0xffff;
11730 if (immediate
== (immediate
& 0x000000ff))
11732 *immbits
= immediate
;
11735 else if (immediate
== (immediate
& 0x0000ff00))
11737 *immbits
= immediate
>> 8;
11742 first_error (_("immediate value out of range"));
11746 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
11750 neon_bits_same_in_bytes (unsigned imm
)
11752 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
11753 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
11754 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
11755 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
11758 /* For immediate of above form, return 0bABCD. */
11761 neon_squash_bits (unsigned imm
)
11763 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
11764 | ((imm
& 0x01000000) >> 21);
11767 /* Compress quarter-float representation to 0b...000 abcdefgh. */
11770 neon_qfloat_bits (unsigned imm
)
11772 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
11775 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
11776 the instruction. *OP is passed as the initial value of the op field, and
11777 may be set to a different value depending on the constant (i.e.
11778 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
11779 MVN). If the immediate looks like a repeated parttern then also
11780 try smaller element sizes. */
11783 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
11784 unsigned *immbits
, int *op
, int size
,
11785 enum neon_el_type type
)
11787 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
11789 if (type
== NT_float
&& !float_p
)
11792 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
11794 if (size
!= 32 || *op
== 1)
11796 *immbits
= neon_qfloat_bits (immlo
);
11802 if (neon_bits_same_in_bytes (immhi
)
11803 && neon_bits_same_in_bytes (immlo
))
11807 *immbits
= (neon_squash_bits (immhi
) << 4)
11808 | neon_squash_bits (immlo
);
11813 if (immhi
!= immlo
)
11819 if (immlo
== (immlo
& 0x000000ff))
11824 else if (immlo
== (immlo
& 0x0000ff00))
11826 *immbits
= immlo
>> 8;
11829 else if (immlo
== (immlo
& 0x00ff0000))
11831 *immbits
= immlo
>> 16;
11834 else if (immlo
== (immlo
& 0xff000000))
11836 *immbits
= immlo
>> 24;
11839 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
11841 *immbits
= (immlo
>> 8) & 0xff;
11844 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
11846 *immbits
= (immlo
>> 16) & 0xff;
11850 if ((immlo
& 0xffff) != (immlo
>> 16))
11857 if (immlo
== (immlo
& 0x000000ff))
11862 else if (immlo
== (immlo
& 0x0000ff00))
11864 *immbits
= immlo
>> 8;
11868 if ((immlo
& 0xff) != (immlo
>> 8))
11873 if (immlo
== (immlo
& 0x000000ff))
11875 /* Don't allow MVN with 8-bit immediate. */
11885 /* Write immediate bits [7:0] to the following locations:
11887 |28/24|23 19|18 16|15 4|3 0|
11888 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
11890 This function is used by VMOV/VMVN/VORR/VBIC. */
11893 neon_write_immbits (unsigned immbits
)
11895 inst
.instruction
|= immbits
& 0xf;
11896 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
11897 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
11900 /* Invert low-order SIZE bits of XHI:XLO. */
11903 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
11905 unsigned immlo
= xlo
? *xlo
: 0;
11906 unsigned immhi
= xhi
? *xhi
: 0;
11911 immlo
= (~immlo
) & 0xff;
11915 immlo
= (~immlo
) & 0xffff;
11919 immhi
= (~immhi
) & 0xffffffff;
11920 /* fall through. */
11923 immlo
= (~immlo
) & 0xffffffff;
11938 do_neon_logic (void)
11940 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
11942 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11943 neon_check_type (3, rs
, N_IGNORE_TYPE
);
11944 /* U bit and size field were set as part of the bitmask. */
11945 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11946 neon_three_same (neon_quad (rs
), 0, -1);
11950 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
11951 struct neon_type_el et
= neon_check_type (2, rs
,
11952 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
11953 enum neon_opc opcode
= inst
.instruction
& 0x0fffffff;
11957 if (et
.type
== NT_invtype
)
11960 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11962 immbits
= inst
.operands
[1].imm
;
11965 /* .i64 is a pseudo-op, so the immediate must be a repeating
11967 if (immbits
!= (inst
.operands
[1].regisimm
?
11968 inst
.operands
[1].reg
: 0))
11970 /* Set immbits to an invalid constant. */
11971 immbits
= 0xdeadbeef;
11978 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11982 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11986 /* Pseudo-instruction for VBIC. */
11987 neon_invert_size (&immbits
, 0, et
.size
);
11988 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11992 /* Pseudo-instruction for VORR. */
11993 neon_invert_size (&immbits
, 0, et
.size
);
11994 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12004 inst
.instruction
|= neon_quad (rs
) << 6;
12005 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12006 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12007 inst
.instruction
|= cmode
<< 8;
12008 neon_write_immbits (immbits
);
12010 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12015 do_neon_bitfield (void)
12017 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12018 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12019 neon_three_same (neon_quad (rs
), 0, -1);
12023 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
12026 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12027 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
12029 if (et
.type
== NT_float
)
12031 inst
.instruction
= NEON_ENC_FLOAT (inst
.instruction
);
12032 neon_three_same (neon_quad (rs
), 0, -1);
12036 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12037 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
12042 do_neon_dyadic_if_su (void)
12044 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12048 do_neon_dyadic_if_su_d (void)
12050 /* This version only allow D registers, but that constraint is enforced during
12051 operand parsing so we don't need to do anything extra here. */
12052 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12056 do_neon_dyadic_if_i_d (void)
12058 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12059 affected if we specify unsigned args. */
12060 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12063 enum vfp_or_neon_is_neon_bits
12066 NEON_CHECK_ARCH
= 2
12069 /* Call this function if an instruction which may have belonged to the VFP or
12070 Neon instruction sets, but turned out to be a Neon instruction (due to the
12071 operand types involved, etc.). We have to check and/or fix-up a couple of
12074 - Make sure the user hasn't attempted to make a Neon instruction
12076 - Alter the value in the condition code field if necessary.
12077 - Make sure that the arch supports Neon instructions.
12079 Which of these operations take place depends on bits from enum
12080 vfp_or_neon_is_neon_bits.
12082 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
12083 current instruction's condition is COND_ALWAYS, the condition field is
12084 changed to inst.uncond_value. This is necessary because instructions shared
12085 between VFP and Neon may be conditional for the VFP variants only, and the
12086 unconditional Neon version must have, e.g., 0xF in the condition field. */
12089 vfp_or_neon_is_neon (unsigned check
)
12091 /* Conditions are always legal in Thumb mode (IT blocks). */
12092 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
12094 if (inst
.cond
!= COND_ALWAYS
)
12096 first_error (_(BAD_COND
));
12099 if (inst
.uncond_value
!= -1)
12100 inst
.instruction
|= inst
.uncond_value
<< 28;
12103 if ((check
& NEON_CHECK_ARCH
)
12104 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
12106 first_error (_(BAD_FPU
));
12114 do_neon_addsub_if_i (void)
12116 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
12119 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12122 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12123 affected if we specify unsigned args. */
12124 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
12127 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
12129 V<op> A,B (A is operand 0, B is operand 2)
12134 so handle that case specially. */
12137 neon_exchange_operands (void)
12139 void *scratch
= alloca (sizeof (inst
.operands
[0]));
12140 if (inst
.operands
[1].present
)
12142 /* Swap operands[1] and operands[2]. */
12143 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
12144 inst
.operands
[1] = inst
.operands
[2];
12145 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
12149 inst
.operands
[1] = inst
.operands
[2];
12150 inst
.operands
[2] = inst
.operands
[0];
12155 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
12157 if (inst
.operands
[2].isreg
)
12160 neon_exchange_operands ();
12161 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
12165 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12166 struct neon_type_el et
= neon_check_type (2, rs
,
12167 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
12169 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12170 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12171 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12172 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12173 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12174 inst
.instruction
|= neon_quad (rs
) << 6;
12175 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12176 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12178 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12185 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
12189 do_neon_cmp_inv (void)
12191 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
12197 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
12200 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
12201 scalars, which are encoded in 5 bits, M : Rm.
12202 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
12203 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
12207 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
12209 unsigned regno
= NEON_SCALAR_REG (scalar
);
12210 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
12215 if (regno
> 7 || elno
> 3)
12217 return regno
| (elno
<< 3);
12220 if (regno
> 15 || elno
> 1)
12222 return regno
| (elno
<< 4);
12226 first_error (_("scalar out of range for multiply instruction"));
12232 /* Encode multiply / multiply-accumulate scalar instructions. */
12235 neon_mul_mac (struct neon_type_el et
, int ubit
)
12239 /* Give a more helpful error message if we have an invalid type. */
12240 if (et
.type
== NT_invtype
)
12243 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
12244 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12245 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12246 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12247 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12248 inst
.instruction
|= LOW4 (scalar
);
12249 inst
.instruction
|= HI1 (scalar
) << 5;
12250 inst
.instruction
|= (et
.type
== NT_float
) << 8;
12251 inst
.instruction
|= neon_logbits (et
.size
) << 20;
12252 inst
.instruction
|= (ubit
!= 0) << 24;
12254 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12258 do_neon_mac_maybe_scalar (void)
12260 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
12263 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12266 if (inst
.operands
[2].isscalar
)
12268 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
12269 struct neon_type_el et
= neon_check_type (3, rs
,
12270 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
12271 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12272 neon_mul_mac (et
, neon_quad (rs
));
12276 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12277 affected if we specify unsigned args. */
12278 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12285 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12286 struct neon_type_el et
= neon_check_type (3, rs
,
12287 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12288 neon_three_same (neon_quad (rs
), 0, et
.size
);
12291 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
12292 same types as the MAC equivalents. The polynomial type for this instruction
12293 is encoded the same as the integer type. */
12298 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
12301 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12304 if (inst
.operands
[2].isscalar
)
12305 do_neon_mac_maybe_scalar ();
12307 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
12311 do_neon_qdmulh (void)
12313 if (inst
.operands
[2].isscalar
)
12315 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
12316 struct neon_type_el et
= neon_check_type (3, rs
,
12317 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
12318 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12319 neon_mul_mac (et
, neon_quad (rs
));
12323 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12324 struct neon_type_el et
= neon_check_type (3, rs
,
12325 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
12326 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12327 /* The U bit (rounding) comes from bit mask. */
12328 neon_three_same (neon_quad (rs
), 0, et
.size
);
12333 do_neon_fcmp_absolute (void)
12335 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12336 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12337 /* Size field comes from bit mask. */
12338 neon_three_same (neon_quad (rs
), 1, -1);
12342 do_neon_fcmp_absolute_inv (void)
12344 neon_exchange_operands ();
12345 do_neon_fcmp_absolute ();
12349 do_neon_step (void)
12351 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12352 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12353 neon_three_same (neon_quad (rs
), 0, -1);
12357 do_neon_abs_neg (void)
12359 enum neon_shape rs
;
12360 struct neon_type_el et
;
12362 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
12365 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12368 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12369 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
12371 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12372 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12373 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12374 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12375 inst
.instruction
|= neon_quad (rs
) << 6;
12376 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12377 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12379 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12385 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12386 struct neon_type_el et
= neon_check_type (2, rs
,
12387 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12388 int imm
= inst
.operands
[2].imm
;
12389 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12390 _("immediate out of range for insert"));
12391 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12397 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12398 struct neon_type_el et
= neon_check_type (2, rs
,
12399 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12400 int imm
= inst
.operands
[2].imm
;
12401 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12402 _("immediate out of range for insert"));
12403 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
12407 do_neon_qshlu_imm (void)
12409 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12410 struct neon_type_el et
= neon_check_type (2, rs
,
12411 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
12412 int imm
= inst
.operands
[2].imm
;
12413 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12414 _("immediate out of range for shift"));
12415 /* Only encodes the 'U present' variant of the instruction.
12416 In this case, signed types have OP (bit 8) set to 0.
12417 Unsigned types have OP set to 1. */
12418 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
12419 /* The rest of the bits are the same as other immediate shifts. */
12420 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12424 do_neon_qmovn (void)
12426 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12427 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12428 /* Saturating move where operands can be signed or unsigned, and the
12429 destination has the same signedness. */
12430 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12431 if (et
.type
== NT_unsigned
)
12432 inst
.instruction
|= 0xc0;
12434 inst
.instruction
|= 0x80;
12435 neon_two_same (0, 1, et
.size
/ 2);
12439 do_neon_qmovun (void)
12441 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12442 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12443 /* Saturating move with unsigned results. Operands must be signed. */
12444 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12445 neon_two_same (0, 1, et
.size
/ 2);
12449 do_neon_rshift_sat_narrow (void)
12451 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12452 or unsigned. If operands are unsigned, results must also be unsigned. */
12453 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12454 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12455 int imm
= inst
.operands
[2].imm
;
12456 /* This gets the bounds check, size encoding and immediate bits calculation
12460 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
12461 VQMOVN.I<size> <Dd>, <Qm>. */
12464 inst
.operands
[2].present
= 0;
12465 inst
.instruction
= N_MNEM_vqmovn
;
12470 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12471 _("immediate out of range"));
12472 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
12476 do_neon_rshift_sat_narrow_u (void)
12478 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12479 or unsigned. If operands are unsigned, results must also be unsigned. */
12480 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12481 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12482 int imm
= inst
.operands
[2].imm
;
12483 /* This gets the bounds check, size encoding and immediate bits calculation
12487 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
12488 VQMOVUN.I<size> <Dd>, <Qm>. */
12491 inst
.operands
[2].present
= 0;
12492 inst
.instruction
= N_MNEM_vqmovun
;
12497 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12498 _("immediate out of range"));
12499 /* FIXME: The manual is kind of unclear about what value U should have in
12500 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
12502 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
12506 do_neon_movn (void)
12508 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12509 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12510 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12511 neon_two_same (0, 1, et
.size
/ 2);
12515 do_neon_rshift_narrow (void)
12517 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12518 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12519 int imm
= inst
.operands
[2].imm
;
12520 /* This gets the bounds check, size encoding and immediate bits calculation
12524 /* If immediate is zero then we are a pseudo-instruction for
12525 VMOVN.I<size> <Dd>, <Qm> */
12528 inst
.operands
[2].present
= 0;
12529 inst
.instruction
= N_MNEM_vmovn
;
12534 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12535 _("immediate out of range for narrowing operation"));
12536 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
12540 do_neon_shll (void)
12542 /* FIXME: Type checking when lengthening. */
12543 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
12544 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
12545 unsigned imm
= inst
.operands
[2].imm
;
12547 if (imm
== et
.size
)
12549 /* Maximum shift variant. */
12550 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12551 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12552 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12553 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12554 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12555 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12557 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12561 /* A more-specific type check for non-max versions. */
12562 et
= neon_check_type (2, NS_QDI
,
12563 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12564 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12565 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
12569 /* Check the various types for the VCVT instruction, and return which version
12570 the current instruction is. */
12573 neon_cvt_flavour (enum neon_shape rs
)
12575 #define CVT_VAR(C,X,Y) \
12576 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
12577 if (et.type != NT_invtype) \
12579 inst.error = NULL; \
12582 struct neon_type_el et
;
12583 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
12584 || rs
== NS_FF
) ? N_VFP
: 0;
12585 /* The instruction versions which take an immediate take one register
12586 argument, which is extended to the width of the full register. Thus the
12587 "source" and "destination" registers must have the same width. Hack that
12588 here by making the size equal to the key (wider, in this case) operand. */
12589 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
12591 CVT_VAR (0, N_S32
, N_F32
);
12592 CVT_VAR (1, N_U32
, N_F32
);
12593 CVT_VAR (2, N_F32
, N_S32
);
12594 CVT_VAR (3, N_F32
, N_U32
);
12598 /* VFP instructions. */
12599 CVT_VAR (4, N_F32
, N_F64
);
12600 CVT_VAR (5, N_F64
, N_F32
);
12601 CVT_VAR (6, N_S32
, N_F64
| key
);
12602 CVT_VAR (7, N_U32
, N_F64
| key
);
12603 CVT_VAR (8, N_F64
| key
, N_S32
);
12604 CVT_VAR (9, N_F64
| key
, N_U32
);
12605 /* VFP instructions with bitshift. */
12606 CVT_VAR (10, N_F32
| key
, N_S16
);
12607 CVT_VAR (11, N_F32
| key
, N_U16
);
12608 CVT_VAR (12, N_F64
| key
, N_S16
);
12609 CVT_VAR (13, N_F64
| key
, N_U16
);
12610 CVT_VAR (14, N_S16
, N_F32
| key
);
12611 CVT_VAR (15, N_U16
, N_F32
| key
);
12612 CVT_VAR (16, N_S16
, N_F64
| key
);
12613 CVT_VAR (17, N_U16
, N_F64
| key
);
12619 /* Neon-syntax VFP conversions. */
12622 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
12624 const char *opname
= 0;
12626 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
12628 /* Conversions with immediate bitshift. */
12629 const char *enc
[] =
12651 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12653 opname
= enc
[flavour
];
12654 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12655 _("operands 0 and 1 must be the same register"));
12656 inst
.operands
[1] = inst
.operands
[2];
12657 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
12662 /* Conversions without bitshift. */
12663 const char *enc
[] =
12677 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12678 opname
= enc
[flavour
];
12682 do_vfp_nsyn_opcode (opname
);
12686 do_vfp_nsyn_cvtz (void)
12688 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
12689 int flavour
= neon_cvt_flavour (rs
);
12690 const char *enc
[] =
12702 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
12703 do_vfp_nsyn_opcode (enc
[flavour
]);
12709 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
12710 NS_FD
, NS_DF
, NS_FF
, NS_NULL
);
12711 int flavour
= neon_cvt_flavour (rs
);
12713 /* VFP rather than Neon conversions. */
12716 do_vfp_nsyn_cvt (rs
, flavour
);
12725 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12728 /* Fixed-point conversion with #0 immediate is encoded as an
12729 integer conversion. */
12730 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
12732 unsigned immbits
= 32 - inst
.operands
[2].imm
;
12733 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
12734 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12736 inst
.instruction
|= enctab
[flavour
];
12737 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12738 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12739 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12740 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12741 inst
.instruction
|= neon_quad (rs
) << 6;
12742 inst
.instruction
|= 1 << 21;
12743 inst
.instruction
|= immbits
<< 16;
12745 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12753 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
12755 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12757 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12761 inst
.instruction
|= enctab
[flavour
];
12763 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12764 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12765 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12766 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12767 inst
.instruction
|= neon_quad (rs
) << 6;
12768 inst
.instruction
|= 2 << 18;
12770 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12775 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
12776 do_vfp_nsyn_cvt (rs
, flavour
);
12781 neon_move_immediate (void)
12783 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12784 struct neon_type_el et
= neon_check_type (2, rs
,
12785 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12786 unsigned immlo
, immhi
= 0, immbits
;
12787 int op
, cmode
, float_p
;
12789 constraint (et
.type
== NT_invtype
,
12790 _("operand size must be specified for immediate VMOV"));
12792 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
12793 op
= (inst
.instruction
& (1 << 5)) != 0;
12795 immlo
= inst
.operands
[1].imm
;
12796 if (inst
.operands
[1].regisimm
)
12797 immhi
= inst
.operands
[1].reg
;
12799 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
12800 _("immediate has bits set outside the operand size"));
12802 float_p
= inst
.operands
[1].immisfloat
;
12804 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
12805 et
.size
, et
.type
)) == FAIL
)
12807 /* Invert relevant bits only. */
12808 neon_invert_size (&immlo
, &immhi
, et
.size
);
12809 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
12810 with one or the other; those cases are caught by
12811 neon_cmode_for_move_imm. */
12813 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
12814 &op
, et
.size
, et
.type
)) == FAIL
)
12816 first_error (_("immediate out of range"));
12821 inst
.instruction
&= ~(1 << 5);
12822 inst
.instruction
|= op
<< 5;
12824 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12825 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12826 inst
.instruction
|= neon_quad (rs
) << 6;
12827 inst
.instruction
|= cmode
<< 8;
12829 neon_write_immbits (immbits
);
12835 if (inst
.operands
[1].isreg
)
12837 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12839 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12840 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12841 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12842 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12843 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12844 inst
.instruction
|= neon_quad (rs
) << 6;
12848 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12849 neon_move_immediate ();
12852 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12855 /* Encode instructions of form:
12857 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12858 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm |
12863 neon_mixed_length (struct neon_type_el et
, unsigned size
)
12865 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12866 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12867 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12868 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12869 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12870 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12871 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
12872 inst
.instruction
|= neon_logbits (size
) << 20;
12874 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12878 do_neon_dyadic_long (void)
12880 /* FIXME: Type checking for lengthening op. */
12881 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12882 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12883 neon_mixed_length (et
, et
.size
);
12887 do_neon_abal (void)
12889 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12890 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12891 neon_mixed_length (et
, et
.size
);
12895 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
12897 if (inst
.operands
[2].isscalar
)
12899 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
12900 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
12901 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12902 neon_mul_mac (et
, et
.type
== NT_unsigned
);
12906 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12907 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
12908 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12909 neon_mixed_length (et
, et
.size
);
12914 do_neon_mac_maybe_scalar_long (void)
12916 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
12920 do_neon_dyadic_wide (void)
12922 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
12923 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12924 neon_mixed_length (et
, et
.size
);
12928 do_neon_dyadic_narrow (void)
12930 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12931 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
12932 /* Operand sign is unimportant, and the U bit is part of the opcode,
12933 so force the operand type to integer. */
12934 et
.type
= NT_integer
;
12935 neon_mixed_length (et
, et
.size
/ 2);
12939 do_neon_mul_sat_scalar_long (void)
12941 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
12945 do_neon_vmull (void)
12947 if (inst
.operands
[2].isscalar
)
12948 do_neon_mac_maybe_scalar_long ();
12951 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12952 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
12953 if (et
.type
== NT_poly
)
12954 inst
.instruction
= NEON_ENC_POLY (inst
.instruction
);
12956 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12957 /* For polynomial encoding, size field must be 0b00 and the U bit must be
12958 zero. Should be OK as-is. */
12959 neon_mixed_length (et
, et
.size
);
12966 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
12967 struct neon_type_el et
= neon_check_type (3, rs
,
12968 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12969 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
12970 constraint (imm
>= (neon_quad (rs
) ? 16 : 8), _("shift out of range"));
12971 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12972 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12973 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12974 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12975 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12976 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12977 inst
.instruction
|= neon_quad (rs
) << 6;
12978 inst
.instruction
|= imm
<< 8;
12980 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12986 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12987 struct neon_type_el et
= neon_check_type (2, rs
,
12988 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12989 unsigned op
= (inst
.instruction
>> 7) & 3;
12990 /* N (width of reversed regions) is encoded as part of the bitmask. We
12991 extract it here to check the elements to be reversed are smaller.
12992 Otherwise we'd get a reserved instruction. */
12993 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
12994 assert (elsize
!= 0);
12995 constraint (et
.size
>= elsize
,
12996 _("elements must be smaller than reversal region"));
12997 neon_two_same (neon_quad (rs
), 1, et
.size
);
13003 if (inst
.operands
[1].isscalar
)
13005 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
13006 struct neon_type_el et
= neon_check_type (2, rs
,
13007 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13008 unsigned sizebits
= et
.size
>> 3;
13009 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
13010 int logsize
= neon_logbits (et
.size
);
13011 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
13013 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
13016 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13017 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13018 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13019 inst
.instruction
|= LOW4 (dm
);
13020 inst
.instruction
|= HI1 (dm
) << 5;
13021 inst
.instruction
|= neon_quad (rs
) << 6;
13022 inst
.instruction
|= x
<< 17;
13023 inst
.instruction
|= sizebits
<< 16;
13025 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13029 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
13030 struct neon_type_el et
= neon_check_type (2, rs
,
13031 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13032 /* Duplicate ARM register to lanes of vector. */
13033 inst
.instruction
= NEON_ENC_ARMREG (inst
.instruction
);
13036 case 8: inst
.instruction
|= 0x400000; break;
13037 case 16: inst
.instruction
|= 0x000020; break;
13038 case 32: inst
.instruction
|= 0x000000; break;
13041 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13042 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
13043 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
13044 inst
.instruction
|= neon_quad (rs
) << 21;
13045 /* The encoding for this instruction is identical for the ARM and Thumb
13046 variants, except for the condition field. */
13047 do_vfp_cond_or_thumb ();
13051 /* VMOV has particularly many variations. It can be one of:
13052 0. VMOV<c><q> <Qd>, <Qm>
13053 1. VMOV<c><q> <Dd>, <Dm>
13054 (Register operations, which are VORR with Rm = Rn.)
13055 2. VMOV<c><q>.<dt> <Qd>, #<imm>
13056 3. VMOV<c><q>.<dt> <Dd>, #<imm>
13058 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
13059 (ARM register to scalar.)
13060 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
13061 (Two ARM registers to vector.)
13062 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
13063 (Scalar to ARM register.)
13064 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
13065 (Vector to two ARM registers.)
13066 8. VMOV.F32 <Sd>, <Sm>
13067 9. VMOV.F64 <Dd>, <Dm>
13068 (VFP register moves.)
13069 10. VMOV.F32 <Sd>, #imm
13070 11. VMOV.F64 <Dd>, #imm
13071 (VFP float immediate load.)
13072 12. VMOV <Rd>, <Sm>
13073 (VFP single to ARM reg.)
13074 13. VMOV <Sd>, <Rm>
13075 (ARM reg to VFP single.)
13076 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
13077 (Two ARM regs to two VFP singles.)
13078 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
13079 (Two VFP singles to two ARM regs.)
13081 These cases can be disambiguated using neon_select_shape, except cases 1/9
13082 and 3/11 which depend on the operand type too.
13084 All the encoded bits are hardcoded by this function.
13086 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
13087 Cases 5, 7 may be used with VFPv2 and above.
13089 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
13090 can specify a type where it doesn't make sense to, and is ignored).
13096 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
13097 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
13099 struct neon_type_el et
;
13100 const char *ldconst
= 0;
13104 case NS_DD
: /* case 1/9. */
13105 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
13106 /* It is not an error here if no type is given. */
13108 if (et
.type
== NT_float
&& et
.size
== 64)
13110 do_vfp_nsyn_opcode ("fcpyd");
13113 /* fall through. */
13115 case NS_QQ
: /* case 0/1. */
13117 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13119 /* The architecture manual I have doesn't explicitly state which
13120 value the U bit should have for register->register moves, but
13121 the equivalent VORR instruction has U = 0, so do that. */
13122 inst
.instruction
= 0x0200110;
13123 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13124 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13125 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13126 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13127 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13128 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13129 inst
.instruction
|= neon_quad (rs
) << 6;
13131 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13135 case NS_DI
: /* case 3/11. */
13136 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
13138 if (et
.type
== NT_float
&& et
.size
== 64)
13140 /* case 11 (fconstd). */
13141 ldconst
= "fconstd";
13142 goto encode_fconstd
;
13144 /* fall through. */
13146 case NS_QI
: /* case 2/3. */
13147 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13149 inst
.instruction
= 0x0800010;
13150 neon_move_immediate ();
13151 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13154 case NS_SR
: /* case 4. */
13156 unsigned bcdebits
= 0;
13157 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
13158 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13159 int logsize
= neon_logbits (et
.size
);
13160 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
13161 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
13163 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
13165 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
13166 && et
.size
!= 32, _(BAD_FPU
));
13167 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
13168 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
13172 case 8: bcdebits
= 0x8; break;
13173 case 16: bcdebits
= 0x1; break;
13174 case 32: bcdebits
= 0x0; break;
13178 bcdebits
|= x
<< logsize
;
13180 inst
.instruction
= 0xe000b10;
13181 do_vfp_cond_or_thumb ();
13182 inst
.instruction
|= LOW4 (dn
) << 16;
13183 inst
.instruction
|= HI1 (dn
) << 7;
13184 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13185 inst
.instruction
|= (bcdebits
& 3) << 5;
13186 inst
.instruction
|= (bcdebits
>> 2) << 21;
13190 case NS_DRR
: /* case 5 (fmdrr). */
13191 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
13194 inst
.instruction
= 0xc400b10;
13195 do_vfp_cond_or_thumb ();
13196 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
13197 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
13198 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13199 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13202 case NS_RS
: /* case 6. */
13204 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
13205 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
13206 unsigned logsize
= neon_logbits (et
.size
);
13207 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
13208 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
13209 unsigned abcdebits
= 0;
13211 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
13213 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
13214 && et
.size
!= 32, _(BAD_FPU
));
13215 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
13216 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
13220 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
13221 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
13222 case 32: abcdebits
= 0x00; break;
13226 abcdebits
|= x
<< logsize
;
13227 inst
.instruction
= 0xe100b10;
13228 do_vfp_cond_or_thumb ();
13229 inst
.instruction
|= LOW4 (dn
) << 16;
13230 inst
.instruction
|= HI1 (dn
) << 7;
13231 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
13232 inst
.instruction
|= (abcdebits
& 3) << 5;
13233 inst
.instruction
|= (abcdebits
>> 2) << 21;
13237 case NS_RRD
: /* case 7 (fmrrd). */
13238 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
13241 inst
.instruction
= 0xc500b10;
13242 do_vfp_cond_or_thumb ();
13243 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
13244 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13245 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13246 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13249 case NS_FF
: /* case 8 (fcpys). */
13250 do_vfp_nsyn_opcode ("fcpys");
13253 case NS_FI
: /* case 10 (fconsts). */
13254 ldconst
= "fconsts";
13256 if (is_quarter_float (inst
.operands
[1].imm
))
13258 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
13259 do_vfp_nsyn_opcode (ldconst
);
13262 first_error (_("immediate out of range"));
13265 case NS_RF
: /* case 12 (fmrs). */
13266 do_vfp_nsyn_opcode ("fmrs");
13269 case NS_FR
: /* case 13 (fmsr). */
13270 do_vfp_nsyn_opcode ("fmsr");
13273 /* The encoders for the fmrrs and fmsrr instructions expect three operands
13274 (one of which is a list), but we have parsed four. Do some fiddling to
13275 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
13277 case NS_RRFF
: /* case 14 (fmrrs). */
13278 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
13279 _("VFP registers must be adjacent"));
13280 inst
.operands
[2].imm
= 2;
13281 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
13282 do_vfp_nsyn_opcode ("fmrrs");
13285 case NS_FFRR
: /* case 15 (fmsrr). */
13286 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
13287 _("VFP registers must be adjacent"));
13288 inst
.operands
[1] = inst
.operands
[2];
13289 inst
.operands
[2] = inst
.operands
[3];
13290 inst
.operands
[0].imm
= 2;
13291 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
13292 do_vfp_nsyn_opcode ("fmsrr");
13301 do_neon_rshift_round_imm (void)
13303 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13304 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
13305 int imm
= inst
.operands
[2].imm
;
13307 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
13310 inst
.operands
[2].present
= 0;
13315 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13316 _("immediate out of range for shift"));
13317 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
13322 do_neon_movl (void)
13324 struct neon_type_el et
= neon_check_type (2, NS_QD
,
13325 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13326 unsigned sizebits
= et
.size
>> 3;
13327 inst
.instruction
|= sizebits
<< 19;
13328 neon_two_same (0, et
.type
== NT_unsigned
, -1);
13334 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13335 struct neon_type_el et
= neon_check_type (2, rs
,
13336 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13337 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13338 neon_two_same (neon_quad (rs
), 1, et
.size
);
13342 do_neon_zip_uzp (void)
13344 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13345 struct neon_type_el et
= neon_check_type (2, rs
,
13346 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13347 if (rs
== NS_DD
&& et
.size
== 32)
13349 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
13350 inst
.instruction
= N_MNEM_vtrn
;
13354 neon_two_same (neon_quad (rs
), 1, et
.size
);
13358 do_neon_sat_abs_neg (void)
13360 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13361 struct neon_type_el et
= neon_check_type (2, rs
,
13362 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13363 neon_two_same (neon_quad (rs
), 1, et
.size
);
13367 do_neon_pair_long (void)
13369 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13370 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
13371 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
13372 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
13373 neon_two_same (neon_quad (rs
), 1, et
.size
);
13377 do_neon_recip_est (void)
13379 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13380 struct neon_type_el et
= neon_check_type (2, rs
,
13381 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
13382 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13383 neon_two_same (neon_quad (rs
), 1, et
.size
);
13389 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13390 struct neon_type_el et
= neon_check_type (2, rs
,
13391 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13392 neon_two_same (neon_quad (rs
), 1, et
.size
);
13398 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13399 struct neon_type_el et
= neon_check_type (2, rs
,
13400 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
13401 neon_two_same (neon_quad (rs
), 1, et
.size
);
13407 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13408 struct neon_type_el et
= neon_check_type (2, rs
,
13409 N_EQK
| N_INT
, N_8
| N_KEY
);
13410 neon_two_same (neon_quad (rs
), 1, et
.size
);
13416 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13417 neon_two_same (neon_quad (rs
), 1, -1);
13421 do_neon_tbl_tbx (void)
13423 unsigned listlenbits
;
13424 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
13426 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
13428 first_error (_("bad list length for table lookup"));
13432 listlenbits
= inst
.operands
[1].imm
- 1;
13433 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13434 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13435 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13436 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13437 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13438 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13439 inst
.instruction
|= listlenbits
<< 8;
13441 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13445 do_neon_ldm_stm (void)
13447 /* P, U and L bits are part of bitmask. */
13448 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
13449 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
13451 if (inst
.operands
[1].issingle
)
13453 do_vfp_nsyn_ldm_stm (is_dbmode
);
13457 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
13458 _("writeback (!) must be used for VLDMDB and VSTMDB"));
13460 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
13461 _("register list must contain at least 1 and at most 16 "
13464 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
13465 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
13466 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13467 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
13469 inst
.instruction
|= offsetbits
;
13471 do_vfp_cond_or_thumb ();
13475 do_neon_ldr_str (void)
13477 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
13479 if (inst
.operands
[0].issingle
)
13482 do_vfp_nsyn_opcode ("flds");
13484 do_vfp_nsyn_opcode ("fsts");
13489 do_vfp_nsyn_opcode ("fldd");
13491 do_vfp_nsyn_opcode ("fstd");
13495 /* "interleave" version also handles non-interleaving register VLD1/VST1
13499 do_neon_ld_st_interleave (void)
13501 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
13502 N_8
| N_16
| N_32
| N_64
);
13503 unsigned alignbits
= 0;
13505 /* The bits in this table go:
13506 0: register stride of one (0) or two (1)
13507 1,2: register list length, minus one (1, 2, 3, 4).
13508 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
13509 We use -1 for invalid entries. */
13510 const int typetable
[] =
13512 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
13513 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
13514 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
13515 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
13519 if (et
.type
== NT_invtype
)
13522 if (inst
.operands
[1].immisalign
)
13523 switch (inst
.operands
[1].imm
>> 8)
13525 case 64: alignbits
= 1; break;
13527 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13528 goto bad_alignment
;
13532 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13533 goto bad_alignment
;
13538 first_error (_("bad alignment"));
13542 inst
.instruction
|= alignbits
<< 4;
13543 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13545 /* Bits [4:6] of the immediate in a list specifier encode register stride
13546 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
13547 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
13548 up the right value for "type" in a table based on this value and the given
13549 list style, then stick it back. */
13550 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
13551 | (((inst
.instruction
>> 8) & 3) << 3);
13553 typebits
= typetable
[idx
];
13555 constraint (typebits
== -1, _("bad list type for instruction"));
13557 inst
.instruction
&= ~0xf00;
13558 inst
.instruction
|= typebits
<< 8;
13561 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
13562 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
13563 otherwise. The variable arguments are a list of pairs of legal (size, align)
13564 values, terminated with -1. */
13567 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
13570 int result
= FAIL
, thissize
, thisalign
;
13572 if (!inst
.operands
[1].immisalign
)
13578 va_start (ap
, do_align
);
13582 thissize
= va_arg (ap
, int);
13583 if (thissize
== -1)
13585 thisalign
= va_arg (ap
, int);
13587 if (size
== thissize
&& align
== thisalign
)
13590 while (result
!= SUCCESS
);
13594 if (result
== SUCCESS
)
13597 first_error (_("unsupported alignment for instruction"));
13603 do_neon_ld_st_lane (void)
13605 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13606 int align_good
, do_align
= 0;
13607 int logsize
= neon_logbits (et
.size
);
13608 int align
= inst
.operands
[1].imm
>> 8;
13609 int n
= (inst
.instruction
>> 8) & 3;
13610 int max_el
= 64 / et
.size
;
13612 if (et
.type
== NT_invtype
)
13615 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
13616 _("bad list length"));
13617 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
13618 _("scalar index out of range"));
13619 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
13621 _("stride of 2 unavailable when element size is 8"));
13625 case 0: /* VLD1 / VST1. */
13626 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
13628 if (align_good
== FAIL
)
13632 unsigned alignbits
= 0;
13635 case 16: alignbits
= 0x1; break;
13636 case 32: alignbits
= 0x3; break;
13639 inst
.instruction
|= alignbits
<< 4;
13643 case 1: /* VLD2 / VST2. */
13644 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
13646 if (align_good
== FAIL
)
13649 inst
.instruction
|= 1 << 4;
13652 case 2: /* VLD3 / VST3. */
13653 constraint (inst
.operands
[1].immisalign
,
13654 _("can't use alignment with this instruction"));
13657 case 3: /* VLD4 / VST4. */
13658 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13659 16, 64, 32, 64, 32, 128, -1);
13660 if (align_good
== FAIL
)
13664 unsigned alignbits
= 0;
13667 case 8: alignbits
= 0x1; break;
13668 case 16: alignbits
= 0x1; break;
13669 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
13672 inst
.instruction
|= alignbits
<< 4;
13679 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
13680 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13681 inst
.instruction
|= 1 << (4 + logsize
);
13683 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
13684 inst
.instruction
|= logsize
<< 10;
13687 /* Encode single n-element structure to all lanes VLD<n> instructions. */
13690 do_neon_ld_dup (void)
13692 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13693 int align_good
, do_align
= 0;
13695 if (et
.type
== NT_invtype
)
13698 switch ((inst
.instruction
>> 8) & 3)
13700 case 0: /* VLD1. */
13701 assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
13702 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13703 &do_align
, 16, 16, 32, 32, -1);
13704 if (align_good
== FAIL
)
13706 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
13709 case 2: inst
.instruction
|= 1 << 5; break;
13710 default: first_error (_("bad list length")); return;
13712 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13715 case 1: /* VLD2. */
13716 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13717 &do_align
, 8, 16, 16, 32, 32, 64, -1);
13718 if (align_good
== FAIL
)
13720 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
13721 _("bad list length"));
13722 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13723 inst
.instruction
|= 1 << 5;
13724 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13727 case 2: /* VLD3. */
13728 constraint (inst
.operands
[1].immisalign
,
13729 _("can't use alignment with this instruction"));
13730 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
13731 _("bad list length"));
13732 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13733 inst
.instruction
|= 1 << 5;
13734 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13737 case 3: /* VLD4. */
13739 int align
= inst
.operands
[1].imm
>> 8;
13740 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13741 16, 64, 32, 64, 32, 128, -1);
13742 if (align_good
== FAIL
)
13744 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
13745 _("bad list length"));
13746 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13747 inst
.instruction
|= 1 << 5;
13748 if (et
.size
== 32 && align
== 128)
13749 inst
.instruction
|= 0x3 << 6;
13751 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13758 inst
.instruction
|= do_align
<< 4;
13761 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
13762 apart from bits [11:4]. */
13765 do_neon_ldx_stx (void)
13767 switch (NEON_LANE (inst
.operands
[0].imm
))
13769 case NEON_INTERLEAVE_LANES
:
13770 inst
.instruction
= NEON_ENC_INTERLV (inst
.instruction
);
13771 do_neon_ld_st_interleave ();
13774 case NEON_ALL_LANES
:
13775 inst
.instruction
= NEON_ENC_DUP (inst
.instruction
);
13780 inst
.instruction
= NEON_ENC_LANE (inst
.instruction
);
13781 do_neon_ld_st_lane ();
13784 /* L bit comes from bit mask. */
13785 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13786 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13787 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13789 if (inst
.operands
[1].postind
)
13791 int postreg
= inst
.operands
[1].imm
& 0xf;
13792 constraint (!inst
.operands
[1].immisreg
,
13793 _("post-index must be a register"));
13794 constraint (postreg
== 0xd || postreg
== 0xf,
13795 _("bad register for post-index"));
13796 inst
.instruction
|= postreg
;
13798 else if (inst
.operands
[1].writeback
)
13800 inst
.instruction
|= 0xd;
13803 inst
.instruction
|= 0xf;
13806 inst
.instruction
|= 0xf9000000;
13808 inst
.instruction
|= 0xf4000000;
13812 /* Overall per-instruction processing. */
13814 /* We need to be able to fix up arbitrary expressions in some statements.
13815 This is so that we can handle symbols that are an arbitrary distance from
13816 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
13817 which returns part of an address in a form which will be valid for
13818 a data instruction. We do this by pushing the expression into a symbol
13819 in the expr_section, and creating a fix for that. */
13822 fix_new_arm (fragS
* frag
,
13837 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
13841 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
13846 /* Mark whether the fix is to a THUMB instruction, or an ARM
13848 new_fix
->tc_fix_data
= thumb_mode
;
13851 /* Create a frg for an instruction requiring relaxation. */
13853 output_relax_insn (void)
13859 /* The size of the instruction is unknown, so tie the debug info to the
13860 start of the instruction. */
13861 dwarf2_emit_insn (0);
13863 switch (inst
.reloc
.exp
.X_op
)
13866 sym
= inst
.reloc
.exp
.X_add_symbol
;
13867 offset
= inst
.reloc
.exp
.X_add_number
;
13871 offset
= inst
.reloc
.exp
.X_add_number
;
13874 sym
= make_expr_symbol (&inst
.reloc
.exp
);
13878 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
13879 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
13880 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
13883 /* Write a 32-bit thumb instruction to buf. */
13885 put_thumb32_insn (char * buf
, unsigned long insn
)
13887 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
13888 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
13892 output_inst (const char * str
)
13898 as_bad ("%s -- `%s'", inst
.error
, str
);
13902 output_relax_insn();
13905 if (inst
.size
== 0)
13908 to
= frag_more (inst
.size
);
13910 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
13912 assert (inst
.size
== (2 * THUMB_SIZE
));
13913 put_thumb32_insn (to
, inst
.instruction
);
13915 else if (inst
.size
> INSN_SIZE
)
13917 assert (inst
.size
== (2 * INSN_SIZE
));
13918 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
13919 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
13922 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
13924 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
13925 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
13926 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
13929 dwarf2_emit_insn (inst
.size
);
13932 /* Tag values used in struct asm_opcode's tag field. */
13935 OT_unconditional
, /* Instruction cannot be conditionalized.
13936 The ARM condition field is still 0xE. */
13937 OT_unconditionalF
, /* Instruction cannot be conditionalized
13938 and carries 0xF in its ARM condition field. */
13939 OT_csuffix
, /* Instruction takes a conditional suffix. */
13940 OT_csuffixF
, /* Some forms of the instruction take a conditional
13941 suffix, others place 0xF where the condition field
13943 OT_cinfix3
, /* Instruction takes a conditional infix,
13944 beginning at character index 3. (In
13945 unified mode, it becomes a suffix.) */
13946 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
13947 tsts, cmps, cmns, and teqs. */
13948 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
13949 character index 3, even in unified mode. Used for
13950 legacy instructions where suffix and infix forms
13951 may be ambiguous. */
13952 OT_csuf_or_in3
, /* Instruction takes either a conditional
13953 suffix or an infix at character index 3. */
13954 OT_odd_infix_unc
, /* This is the unconditional variant of an
13955 instruction that takes a conditional infix
13956 at an unusual position. In unified mode,
13957 this variant will accept a suffix. */
13958 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
13959 are the conditional variants of instructions that
13960 take conditional infixes in unusual positions.
13961 The infix appears at character index
13962 (tag - OT_odd_infix_0). These are not accepted
13963 in unified mode. */
13966 /* Subroutine of md_assemble, responsible for looking up the primary
13967 opcode from the mnemonic the user wrote. STR points to the
13968 beginning of the mnemonic.
13970 This is not simply a hash table lookup, because of conditional
13971 variants. Most instructions have conditional variants, which are
13972 expressed with a _conditional affix_ to the mnemonic. If we were
13973 to encode each conditional variant as a literal string in the opcode
13974 table, it would have approximately 20,000 entries.
13976 Most mnemonics take this affix as a suffix, and in unified syntax,
13977 'most' is upgraded to 'all'. However, in the divided syntax, some
13978 instructions take the affix as an infix, notably the s-variants of
13979 the arithmetic instructions. Of those instructions, all but six
13980 have the infix appear after the third character of the mnemonic.
13982 Accordingly, the algorithm for looking up primary opcodes given
13985 1. Look up the identifier in the opcode table.
13986 If we find a match, go to step U.
13988 2. Look up the last two characters of the identifier in the
13989 conditions table. If we find a match, look up the first N-2
13990 characters of the identifier in the opcode table. If we
13991 find a match, go to step CE.
13993 3. Look up the fourth and fifth characters of the identifier in
13994 the conditions table. If we find a match, extract those
13995 characters from the identifier, and look up the remaining
13996 characters in the opcode table. If we find a match, go
14001 U. Examine the tag field of the opcode structure, in case this is
14002 one of the six instructions with its conditional infix in an
14003 unusual place. If it is, the tag tells us where to find the
14004 infix; look it up in the conditions table and set inst.cond
14005 accordingly. Otherwise, this is an unconditional instruction.
14006 Again set inst.cond accordingly. Return the opcode structure.
14008 CE. Examine the tag field to make sure this is an instruction that
14009 should receive a conditional suffix. If it is not, fail.
14010 Otherwise, set inst.cond from the suffix we already looked up,
14011 and return the opcode structure.
14013 CM. Examine the tag field to make sure this is an instruction that
14014 should receive a conditional infix after the third character.
14015 If it is not, fail. Otherwise, undo the edits to the current
14016 line of input and proceed as for case CE. */
14018 static const struct asm_opcode
*
14019 opcode_lookup (char **str
)
14023 const struct asm_opcode
*opcode
;
14024 const struct asm_cond
*cond
;
14026 bfd_boolean neon_supported
;
14028 neon_supported
= ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
);
14030 /* Scan up to the end of the mnemonic, which must end in white space,
14031 '.' (in unified mode, or for Neon instructions), or end of string. */
14032 for (base
= end
= *str
; *end
!= '\0'; end
++)
14033 if (*end
== ' ' || ((unified_syntax
|| neon_supported
) && *end
== '.'))
14039 /* Handle a possible width suffix and/or Neon type suffix. */
14044 /* The .w and .n suffixes are only valid if the unified syntax is in
14046 if (unified_syntax
&& end
[1] == 'w')
14048 else if (unified_syntax
&& end
[1] == 'n')
14053 inst
.vectype
.elems
= 0;
14055 *str
= end
+ offset
;
14057 if (end
[offset
] == '.')
14059 /* See if we have a Neon type suffix (possible in either unified or
14060 non-unified ARM syntax mode). */
14061 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
14064 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
14070 /* Look for unaffixed or special-case affixed mnemonic. */
14071 opcode
= hash_find_n (arm_ops_hsh
, base
, end
- base
);
14075 if (opcode
->tag
< OT_odd_infix_0
)
14077 inst
.cond
= COND_ALWAYS
;
14081 if (unified_syntax
)
14082 as_warn (_("conditional infixes are deprecated in unified syntax"));
14083 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
14084 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14087 inst
.cond
= cond
->value
;
14091 /* Cannot have a conditional suffix on a mnemonic of less than two
14093 if (end
- base
< 3)
14096 /* Look for suffixed mnemonic. */
14098 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14099 opcode
= hash_find_n (arm_ops_hsh
, base
, affix
- base
);
14100 if (opcode
&& cond
)
14103 switch (opcode
->tag
)
14105 case OT_cinfix3_legacy
:
14106 /* Ignore conditional suffixes matched on infix only mnemonics. */
14110 case OT_cinfix3_deprecated
:
14111 case OT_odd_infix_unc
:
14112 if (!unified_syntax
)
14114 /* else fall through */
14118 case OT_csuf_or_in3
:
14119 inst
.cond
= cond
->value
;
14122 case OT_unconditional
:
14123 case OT_unconditionalF
:
14126 inst
.cond
= cond
->value
;
14130 /* delayed diagnostic */
14131 inst
.error
= BAD_COND
;
14132 inst
.cond
= COND_ALWAYS
;
14141 /* Cannot have a usual-position infix on a mnemonic of less than
14142 six characters (five would be a suffix). */
14143 if (end
- base
< 6)
14146 /* Look for infixed mnemonic in the usual position. */
14148 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14152 memcpy (save
, affix
, 2);
14153 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
14154 opcode
= hash_find_n (arm_ops_hsh
, base
, (end
- base
) - 2);
14155 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
14156 memcpy (affix
, save
, 2);
14159 && (opcode
->tag
== OT_cinfix3
14160 || opcode
->tag
== OT_cinfix3_deprecated
14161 || opcode
->tag
== OT_csuf_or_in3
14162 || opcode
->tag
== OT_cinfix3_legacy
))
14166 && (opcode
->tag
== OT_cinfix3
14167 || opcode
->tag
== OT_cinfix3_deprecated
))
14168 as_warn (_("conditional infixes are deprecated in unified syntax"));
14170 inst
.cond
= cond
->value
;
14178 md_assemble (char *str
)
14181 const struct asm_opcode
* opcode
;
14183 /* Align the previous label if needed. */
14184 if (last_label_seen
!= NULL
)
14186 symbol_set_frag (last_label_seen
, frag_now
);
14187 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
14188 S_SET_SEGMENT (last_label_seen
, now_seg
);
14191 memset (&inst
, '\0', sizeof (inst
));
14192 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
14194 opcode
= opcode_lookup (&p
);
14197 /* It wasn't an instruction, but it might be a register alias of
14198 the form alias .req reg, or a Neon .dn/.qn directive. */
14199 if (!create_register_alias (str
, p
)
14200 && !create_neon_reg_alias (str
, p
))
14201 as_bad (_("bad instruction `%s'"), str
);
14206 if (opcode
->tag
== OT_cinfix3_deprecated
)
14207 as_warn (_("s suffix on comparison instruction is deprecated"));
14209 /* The value which unconditional instructions should have in place of the
14210 condition field. */
14211 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
14215 arm_feature_set variant
;
14217 variant
= cpu_variant
;
14218 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
14219 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
14220 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
14221 /* Check that this instruction is supported for this CPU. */
14222 if (!opcode
->tvariant
14223 || (thumb_mode
== 1
14224 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
14226 as_bad (_("selected processor does not support `%s'"), str
);
14229 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
14230 && opcode
->tencode
!= do_t_branch
)
14232 as_bad (_("Thumb does not support conditional execution"));
14236 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
) && !inst
.size_req
)
14238 /* Implicit require narrow instructions on Thumb-1. This avoids
14239 relaxation accidentally introducing Thumb-2 instructions. */
14240 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
)
14244 /* Check conditional suffixes. */
14245 if (current_it_mask
)
14248 cond
= current_cc
^ ((current_it_mask
>> 4) & 1) ^ 1;
14249 current_it_mask
<<= 1;
14250 current_it_mask
&= 0x1f;
14251 /* The BKPT instruction is unconditional even in an IT block. */
14253 && cond
!= inst
.cond
&& opcode
->tencode
!= do_t_bkpt
)
14255 as_bad (_("incorrect condition in IT block"));
14259 else if (inst
.cond
!= COND_ALWAYS
&& opcode
->tencode
!= do_t_branch
)
14261 as_bad (_("thumb conditional instrunction not in IT block"));
14265 mapping_state (MAP_THUMB
);
14266 inst
.instruction
= opcode
->tvalue
;
14268 if (!parse_operands (p
, opcode
->operands
))
14269 opcode
->tencode ();
14271 /* Clear current_it_mask at the end of an IT block. */
14272 if (current_it_mask
== 0x10)
14273 current_it_mask
= 0;
14275 if (!(inst
.error
|| inst
.relax
))
14277 assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
14278 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
14279 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
14281 as_bad (_("cannot honor width suffix -- `%s'"), str
);
14286 /* Something has gone badly wrong if we try to relax a fixed size
14288 assert (inst
.size_req
== 0 || !inst
.relax
);
14290 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
14291 *opcode
->tvariant
);
14292 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
14293 set those bits when Thumb-2 32-bit instructions are seen. ie.
14294 anything other than bl/blx.
14295 This is overly pessimistic for relaxable instructions. */
14296 if ((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
14298 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
14301 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
14303 /* Check that this instruction is supported for this CPU. */
14304 if (!opcode
->avariant
||
14305 !ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
))
14307 as_bad (_("selected processor does not support `%s'"), str
);
14312 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
14316 mapping_state (MAP_ARM
);
14317 inst
.instruction
= opcode
->avalue
;
14318 if (opcode
->tag
== OT_unconditionalF
)
14319 inst
.instruction
|= 0xF << 28;
14321 inst
.instruction
|= inst
.cond
<< 28;
14322 inst
.size
= INSN_SIZE
;
14323 if (!parse_operands (p
, opcode
->operands
))
14324 opcode
->aencode ();
14325 /* Arm mode bx is marked as both v4T and v5 because it's still required
14326 on a hypothetical non-thumb v5 core. */
14327 if (ARM_CPU_HAS_FEATURE (*opcode
->avariant
, arm_ext_v4t
)
14328 || ARM_CPU_HAS_FEATURE (*opcode
->avariant
, arm_ext_v5
))
14329 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
14331 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
14332 *opcode
->avariant
);
14336 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
14343 /* Various frobbings of labels and their addresses. */
14346 arm_start_line_hook (void)
14348 last_label_seen
= NULL
;
14352 arm_frob_label (symbolS
* sym
)
14354 last_label_seen
= sym
;
14356 ARM_SET_THUMB (sym
, thumb_mode
);
14358 #if defined OBJ_COFF || defined OBJ_ELF
14359 ARM_SET_INTERWORK (sym
, support_interwork
);
14362 /* Note - do not allow local symbols (.Lxxx) to be labeled
14363 as Thumb functions. This is because these labels, whilst
14364 they exist inside Thumb code, are not the entry points for
14365 possible ARM->Thumb calls. Also, these labels can be used
14366 as part of a computed goto or switch statement. eg gcc
14367 can generate code that looks like this:
14369 ldr r2, [pc, .Laaa]
14379 The first instruction loads the address of the jump table.
14380 The second instruction converts a table index into a byte offset.
14381 The third instruction gets the jump address out of the table.
14382 The fourth instruction performs the jump.
14384 If the address stored at .Laaa is that of a symbol which has the
14385 Thumb_Func bit set, then the linker will arrange for this address
14386 to have the bottom bit set, which in turn would mean that the
14387 address computation performed by the third instruction would end
14388 up with the bottom bit set. Since the ARM is capable of unaligned
14389 word loads, the instruction would then load the incorrect address
14390 out of the jump table, and chaos would ensue. */
14391 if (label_is_thumb_function_name
14392 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
14393 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
14395 /* When the address of a Thumb function is taken the bottom
14396 bit of that address should be set. This will allow
14397 interworking between Arm and Thumb functions to work
14400 THUMB_SET_FUNC (sym
, 1);
14402 label_is_thumb_function_name
= FALSE
;
14405 dwarf2_emit_label (sym
);
14409 arm_data_in_code (void)
14411 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
14413 *input_line_pointer
= '/';
14414 input_line_pointer
+= 5;
14415 *input_line_pointer
= 0;
14423 arm_canonicalize_symbol_name (char * name
)
14427 if (thumb_mode
&& (len
= strlen (name
)) > 5
14428 && streq (name
+ len
- 5, "/data"))
14429 *(name
+ len
- 5) = 0;
14434 /* Table of all register names defined by default. The user can
14435 define additional names with .req. Note that all register names
14436 should appear in both upper and lowercase variants. Some registers
14437 also have mixed-case names. */
14439 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
14440 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
14441 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
14442 #define REGSET(p,t) \
14443 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
14444 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
14445 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
14446 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
14447 #define REGSETH(p,t) \
14448 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
14449 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
14450 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
14451 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
14452 #define REGSET2(p,t) \
14453 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
14454 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
14455 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
14456 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
14458 static const struct reg_entry reg_names
[] =
14460 /* ARM integer registers. */
14461 REGSET(r
, RN
), REGSET(R
, RN
),
14463 /* ATPCS synonyms. */
14464 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
14465 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
14466 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
14468 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
14469 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
14470 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
14472 /* Well-known aliases. */
14473 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
14474 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
14476 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
14477 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
14479 /* Coprocessor numbers. */
14480 REGSET(p
, CP
), REGSET(P
, CP
),
14482 /* Coprocessor register numbers. The "cr" variants are for backward
14484 REGSET(c
, CN
), REGSET(C
, CN
),
14485 REGSET(cr
, CN
), REGSET(CR
, CN
),
14487 /* FPA registers. */
14488 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
14489 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
14491 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
14492 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
14494 /* VFP SP registers. */
14495 REGSET(s
,VFS
), REGSET(S
,VFS
),
14496 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
14498 /* VFP DP Registers. */
14499 REGSET(d
,VFD
), REGSET(D
,VFD
),
14500 /* Extra Neon DP registers. */
14501 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
14503 /* Neon QP registers. */
14504 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
14506 /* VFP control registers. */
14507 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
14508 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
14510 /* Maverick DSP coprocessor registers. */
14511 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
14512 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
14514 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
14515 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
14516 REGDEF(dspsc
,0,DSPSC
),
14518 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
14519 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
14520 REGDEF(DSPSC
,0,DSPSC
),
14522 /* iWMMXt data registers - p0, c0-15. */
14523 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
14525 /* iWMMXt control registers - p1, c0-3. */
14526 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
14527 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
14528 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
14529 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
14531 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
14532 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
14533 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
14534 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
14535 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
14537 /* XScale accumulator registers. */
14538 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
14544 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
14545 within psr_required_here. */
14546 static const struct asm_psr psrs
[] =
14548 /* Backward compatibility notation. Note that "all" is no longer
14549 truly all possible PSR bits. */
14550 {"all", PSR_c
| PSR_f
},
14554 /* Individual flags. */
14559 /* Combinations of flags. */
14560 {"fs", PSR_f
| PSR_s
},
14561 {"fx", PSR_f
| PSR_x
},
14562 {"fc", PSR_f
| PSR_c
},
14563 {"sf", PSR_s
| PSR_f
},
14564 {"sx", PSR_s
| PSR_x
},
14565 {"sc", PSR_s
| PSR_c
},
14566 {"xf", PSR_x
| PSR_f
},
14567 {"xs", PSR_x
| PSR_s
},
14568 {"xc", PSR_x
| PSR_c
},
14569 {"cf", PSR_c
| PSR_f
},
14570 {"cs", PSR_c
| PSR_s
},
14571 {"cx", PSR_c
| PSR_x
},
14572 {"fsx", PSR_f
| PSR_s
| PSR_x
},
14573 {"fsc", PSR_f
| PSR_s
| PSR_c
},
14574 {"fxs", PSR_f
| PSR_x
| PSR_s
},
14575 {"fxc", PSR_f
| PSR_x
| PSR_c
},
14576 {"fcs", PSR_f
| PSR_c
| PSR_s
},
14577 {"fcx", PSR_f
| PSR_c
| PSR_x
},
14578 {"sfx", PSR_s
| PSR_f
| PSR_x
},
14579 {"sfc", PSR_s
| PSR_f
| PSR_c
},
14580 {"sxf", PSR_s
| PSR_x
| PSR_f
},
14581 {"sxc", PSR_s
| PSR_x
| PSR_c
},
14582 {"scf", PSR_s
| PSR_c
| PSR_f
},
14583 {"scx", PSR_s
| PSR_c
| PSR_x
},
14584 {"xfs", PSR_x
| PSR_f
| PSR_s
},
14585 {"xfc", PSR_x
| PSR_f
| PSR_c
},
14586 {"xsf", PSR_x
| PSR_s
| PSR_f
},
14587 {"xsc", PSR_x
| PSR_s
| PSR_c
},
14588 {"xcf", PSR_x
| PSR_c
| PSR_f
},
14589 {"xcs", PSR_x
| PSR_c
| PSR_s
},
14590 {"cfs", PSR_c
| PSR_f
| PSR_s
},
14591 {"cfx", PSR_c
| PSR_f
| PSR_x
},
14592 {"csf", PSR_c
| PSR_s
| PSR_f
},
14593 {"csx", PSR_c
| PSR_s
| PSR_x
},
14594 {"cxf", PSR_c
| PSR_x
| PSR_f
},
14595 {"cxs", PSR_c
| PSR_x
| PSR_s
},
14596 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
14597 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
14598 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
14599 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
14600 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
14601 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
14602 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
14603 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
14604 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
14605 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
14606 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
14607 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
14608 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
14609 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
14610 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
14611 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
14612 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
14613 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
14614 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
14615 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
14616 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
14617 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
14618 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
14619 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
14622 /* Table of V7M psr names. */
14623 static const struct asm_psr v7m_psrs
[] =
14625 {"apsr", 0 }, {"APSR", 0 },
14626 {"iapsr", 1 }, {"IAPSR", 1 },
14627 {"eapsr", 2 }, {"EAPSR", 2 },
14628 {"psr", 3 }, {"PSR", 3 },
14629 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
14630 {"ipsr", 5 }, {"IPSR", 5 },
14631 {"epsr", 6 }, {"EPSR", 6 },
14632 {"iepsr", 7 }, {"IEPSR", 7 },
14633 {"msp", 8 }, {"MSP", 8 },
14634 {"psp", 9 }, {"PSP", 9 },
14635 {"primask", 16}, {"PRIMASK", 16},
14636 {"basepri", 17}, {"BASEPRI", 17},
14637 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
14638 {"faultmask", 19}, {"FAULTMASK", 19},
14639 {"control", 20}, {"CONTROL", 20}
14642 /* Table of all shift-in-operand names. */
14643 static const struct asm_shift_name shift_names
[] =
14645 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
14646 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
14647 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
14648 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
14649 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
14650 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
14653 /* Table of all explicit relocation names. */
14655 static struct reloc_entry reloc_names
[] =
14657 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
14658 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
14659 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
14660 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
14661 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
14662 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
14663 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
14664 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
14665 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
14666 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
14667 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
14671 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
14672 static const struct asm_cond conds
[] =
14676 {"cs", 0x2}, {"hs", 0x2},
14677 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
14691 static struct asm_barrier_opt barrier_opt_names
[] =
14699 /* Table of ARM-format instructions. */
14701 /* Macros for gluing together operand strings. N.B. In all cases
14702 other than OPS0, the trailing OP_stop comes from default
14703 zero-initialization of the unspecified elements of the array. */
14704 #define OPS0() { OP_stop, }
14705 #define OPS1(a) { OP_##a, }
14706 #define OPS2(a,b) { OP_##a,OP_##b, }
14707 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
14708 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
14709 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
14710 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
14712 /* These macros abstract out the exact format of the mnemonic table and
14713 save some repeated characters. */
14715 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
14716 #define TxCE(mnem, op, top, nops, ops, ae, te) \
14717 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
14718 THUMB_VARIANT, do_##ae, do_##te }
14720 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
14721 a T_MNEM_xyz enumerator. */
14722 #define TCE(mnem, aop, top, nops, ops, ae, te) \
14723 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
14724 #define tCE(mnem, aop, top, nops, ops, ae, te) \
14725 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14727 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
14728 infix after the third character. */
14729 #define TxC3(mnem, op, top, nops, ops, ae, te) \
14730 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
14731 THUMB_VARIANT, do_##ae, do_##te }
14732 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
14733 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
14734 THUMB_VARIANT, do_##ae, do_##te }
14735 #define TC3(mnem, aop, top, nops, ops, ae, te) \
14736 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
14737 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
14738 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
14739 #define tC3(mnem, aop, top, nops, ops, ae, te) \
14740 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14741 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
14742 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14744 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
14745 appear in the condition table. */
14746 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
14747 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14748 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
14750 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
14751 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
14752 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
14753 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
14754 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
14755 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
14756 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
14757 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
14758 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
14759 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
14760 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
14761 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
14762 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
14763 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
14764 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
14765 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
14766 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
14767 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
14768 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
14769 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
14771 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
14772 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
14773 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
14774 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
14776 /* Mnemonic that cannot be conditionalized. The ARM condition-code
14777 field is still 0xE. Many of the Thumb variants can be executed
14778 conditionally, so this is checked separately. */
14779 #define TUE(mnem, op, top, nops, ops, ae, te) \
14780 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
14781 THUMB_VARIANT, do_##ae, do_##te }
14783 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
14784 condition code field. */
14785 #define TUF(mnem, op, top, nops, ops, ae, te) \
14786 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
14787 THUMB_VARIANT, do_##ae, do_##te }
14789 /* ARM-only variants of all the above. */
14790 #define CE(mnem, op, nops, ops, ae) \
14791 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14793 #define C3(mnem, op, nops, ops, ae) \
14794 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14796 /* Legacy mnemonics that always have conditional infix after the third
14798 #define CL(mnem, op, nops, ops, ae) \
14799 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14800 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14802 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
14803 #define cCE(mnem, op, nops, ops, ae) \
14804 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14806 /* Legacy coprocessor instructions where conditional infix and conditional
14807 suffix are ambiguous. For consistency this includes all FPA instructions,
14808 not just the potentially ambiguous ones. */
14809 #define cCL(mnem, op, nops, ops, ae) \
14810 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14811 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14813 /* Coprocessor, takes either a suffix or a position-3 infix
14814 (for an FPA corner case). */
14815 #define C3E(mnem, op, nops, ops, ae) \
14816 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
14817 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14819 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
14820 { #m1 #m2 #m3, OPS##nops ops, \
14821 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14822 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14824 #define CM(m1, m2, op, nops, ops, ae) \
14825 xCM_(m1, , m2, op, nops, ops, ae), \
14826 xCM_(m1, eq, m2, op, nops, ops, ae), \
14827 xCM_(m1, ne, m2, op, nops, ops, ae), \
14828 xCM_(m1, cs, m2, op, nops, ops, ae), \
14829 xCM_(m1, hs, m2, op, nops, ops, ae), \
14830 xCM_(m1, cc, m2, op, nops, ops, ae), \
14831 xCM_(m1, ul, m2, op, nops, ops, ae), \
14832 xCM_(m1, lo, m2, op, nops, ops, ae), \
14833 xCM_(m1, mi, m2, op, nops, ops, ae), \
14834 xCM_(m1, pl, m2, op, nops, ops, ae), \
14835 xCM_(m1, vs, m2, op, nops, ops, ae), \
14836 xCM_(m1, vc, m2, op, nops, ops, ae), \
14837 xCM_(m1, hi, m2, op, nops, ops, ae), \
14838 xCM_(m1, ls, m2, op, nops, ops, ae), \
14839 xCM_(m1, ge, m2, op, nops, ops, ae), \
14840 xCM_(m1, lt, m2, op, nops, ops, ae), \
14841 xCM_(m1, gt, m2, op, nops, ops, ae), \
14842 xCM_(m1, le, m2, op, nops, ops, ae), \
14843 xCM_(m1, al, m2, op, nops, ops, ae)
14845 #define UE(mnem, op, nops, ops, ae) \
14846 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14848 #define UF(mnem, op, nops, ops, ae) \
14849 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14851 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
14852 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
14853 use the same encoding function for each. */
14854 #define NUF(mnem, op, nops, ops, enc) \
14855 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
14856 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14858 /* Neon data processing, version which indirects through neon_enc_tab for
14859 the various overloaded versions of opcodes. */
14860 #define nUF(mnem, op, nops, ops, enc) \
14861 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \
14862 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14864 /* Neon insn with conditional suffix for the ARM version, non-overloaded
14866 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
14867 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
14868 THUMB_VARIANT, do_##enc, do_##enc }
14870 #define NCE(mnem, op, nops, ops, enc) \
14871 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14873 #define NCEF(mnem, op, nops, ops, enc) \
14874 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14876 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
14877 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
14878 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \
14879 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14881 #define nCE(mnem, op, nops, ops, enc) \
14882 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14884 #define nCEF(mnem, op, nops, ops, enc) \
14885 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14889 /* Thumb-only, unconditional. */
14890 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
14892 static const struct asm_opcode insns
[] =
14894 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
14895 #define THUMB_VARIANT &arm_ext_v4t
14896 tCE(and, 0000000, and, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14897 tC3(ands
, 0100000, ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14898 tCE(eor
, 0200000, eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14899 tC3(eors
, 0300000, eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14900 tCE(sub
, 0400000, sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14901 tC3(subs
, 0500000, subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14902 tCE(add
, 0800000, add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14903 tC3(adds
, 0900000, adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14904 tCE(adc
, 0a00000
, adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14905 tC3(adcs
, 0b00000, adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14906 tCE(sbc
, 0c00000
, sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14907 tC3(sbcs
, 0d00000
, sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14908 tCE(orr
, 1800000, orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14909 tC3(orrs
, 1900000, orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14910 tCE(bic
, 1c00000
, bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14911 tC3(bics
, 1d00000
, bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14913 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
14914 for setting PSR flag bits. They are obsolete in V6 and do not
14915 have Thumb equivalents. */
14916 tCE(tst
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14917 tC3w(tsts
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14918 CL(tstp
, 110f000
, 2, (RR
, SH
), cmp
),
14919 tCE(cmp
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14920 tC3w(cmps
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14921 CL(cmpp
, 150f000
, 2, (RR
, SH
), cmp
),
14922 tCE(cmn
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14923 tC3w(cmns
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14924 CL(cmnp
, 170f000
, 2, (RR
, SH
), cmp
),
14926 tCE(mov
, 1a00000
, mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14927 tC3(movs
, 1b00000
, movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14928 tCE(mvn
, 1e00000
, mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14929 tC3(mvns
, 1f00000
, mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14931 tCE(ldr
, 4100000, ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14932 tC3(ldrb
, 4500000, ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14933 tCE(str
, 4000000, str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14934 tC3(strb
, 4400000, strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14936 tCE(stm
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14937 tC3(stmia
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14938 tC3(stmea
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14939 tCE(ldm
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14940 tC3(ldmia
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14941 tC3(ldmfd
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14943 TCE(swi
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14944 TCE(svc
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14945 tCE(b
, a000000
, b
, 1, (EXPr
), branch
, t_branch
),
14946 TCE(bl
, b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
14949 tCE(adr
, 28f0000
, adr
, 2, (RR
, EXP
), adr
, t_adr
),
14950 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
14951 tCE(nop
, 1a00000
, nop
, 1, (oI255c
), nop
, t_nop
),
14953 /* Thumb-compatibility pseudo ops. */
14954 tCE(lsl
, 1a00000
, lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14955 tC3(lsls
, 1b00000
, lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14956 tCE(lsr
, 1a00020
, lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14957 tC3(lsrs
, 1b00020
, lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14958 tCE(asr
, 1a00040
, asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14959 tC3(asrs
, 1b00040
, asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14960 tCE(ror
, 1a00060
, ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14961 tC3(rors
, 1b00060
, rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14962 tCE(neg
, 2600000, neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
14963 tC3(negs
, 2700000, negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
14964 tCE(push
, 92d0000
, push
, 1, (REGLST
), push_pop
, t_push_pop
),
14965 tCE(pop
, 8bd0000
, pop
, 1, (REGLST
), push_pop
, t_push_pop
),
14967 /* These may simplify to neg. */
14968 TCE(rsb
, 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14969 TC3(rsbs
, 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14971 #undef THUMB_VARIANT
14972 #define THUMB_VARIANT &arm_ext_v6
14973 TCE(cpy
, 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
14975 /* V1 instructions with no Thumb analogue prior to V6T2. */
14976 #undef THUMB_VARIANT
14977 #define THUMB_VARIANT &arm_ext_v6t2
14978 TCE(teq
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14979 TC3w(teqs
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14980 CL(teqp
, 130f000
, 2, (RR
, SH
), cmp
),
14982 TC3(ldrt
, 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14983 TC3(ldrbt
, 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14984 TC3(strt
, 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14985 TC3(strbt
, 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14987 TC3(stmdb
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14988 TC3(stmfd
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14990 TC3(ldmdb
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14991 TC3(ldmea
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14993 /* V1 instructions with no Thumb analogue at all. */
14994 CE(rsc
, 0e00000
, 3, (RR
, oRR
, SH
), arit
),
14995 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
14997 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
14998 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
14999 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
15000 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
15001 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
15002 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
15003 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
15004 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
15007 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
15008 #undef THUMB_VARIANT
15009 #define THUMB_VARIANT &arm_ext_v4t
15010 tCE(mul
, 0000090, mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
15011 tC3(muls
, 0100090, muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
15013 #undef THUMB_VARIANT
15014 #define THUMB_VARIANT &arm_ext_v6t2
15015 TCE(mla
, 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
15016 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
15018 /* Generic coprocessor instructions. */
15019 TCE(cdp
, e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
15020 TCE(ldc
, c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15021 TC3(ldcl
, c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15022 TCE(stc
, c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15023 TC3(stcl
, c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15024 TCE(mcr
, e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15025 TCE(mrc
, e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15028 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
15029 CE(swp
, 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
15030 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
15033 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
15034 TCE(mrs
, 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
15035 TCE(msr
, 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
15038 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
15039 TCE(smull
, 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15040 CM(smull
,s
, 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15041 TCE(umull
, 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15042 CM(umull
,s
, 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15043 TCE(smlal
, 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15044 CM(smlal
,s
, 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15045 TCE(umlal
, 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15046 CM(umlal
,s
, 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15049 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
15050 #undef THUMB_VARIANT
15051 #define THUMB_VARIANT &arm_ext_v4t
15052 tC3(ldrh
, 01000b0
, ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15053 tC3(strh
, 00000b0
, strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15054 tC3(ldrsh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15055 tC3(ldrsb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15056 tCM(ld
,sh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15057 tCM(ld
,sb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15060 #define ARM_VARIANT &arm_ext_v4t_5
15061 /* ARM Architecture 4T. */
15062 /* Note: bx (and blx) are required on V5, even if the processor does
15063 not support Thumb. */
15064 TCE(bx
, 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
15067 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
15068 #undef THUMB_VARIANT
15069 #define THUMB_VARIANT &arm_ext_v5t
15070 /* Note: blx has 2 variants; the .value coded here is for
15071 BLX(2). Only this variant has conditional execution. */
15072 TCE(blx
, 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
15073 TUE(bkpt
, 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
15075 #undef THUMB_VARIANT
15076 #define THUMB_VARIANT &arm_ext_v6t2
15077 TCE(clz
, 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
15078 TUF(ldc2
, c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15079 TUF(ldc2l
, c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15080 TUF(stc2
, c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15081 TUF(stc2l
, c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15082 TUF(cdp2
, e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
15083 TUF(mcr2
, e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15084 TUF(mrc2
, e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15087 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
15088 TCE(smlabb
, 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15089 TCE(smlatb
, 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15090 TCE(smlabt
, 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15091 TCE(smlatt
, 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15093 TCE(smlawb
, 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15094 TCE(smlawt
, 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15096 TCE(smlalbb
, 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15097 TCE(smlaltb
, 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15098 TCE(smlalbt
, 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15099 TCE(smlaltt
, 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15101 TCE(smulbb
, 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15102 TCE(smultb
, 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15103 TCE(smulbt
, 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15104 TCE(smultt
, 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15106 TCE(smulwb
, 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15107 TCE(smulwt
, 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15109 TCE(qadd
, 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15110 TCE(qdadd
, 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15111 TCE(qsub
, 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15112 TCE(qdsub
, 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15115 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
15116 TUF(pld
, 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
15117 TC3(ldrd
, 00000d0
, e8500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
15118 TC3(strd
, 00000f0
, e8400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
15120 TCE(mcrr
, c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15121 TCE(mrrc
, c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15124 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
15125 TCE(bxj
, 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
15128 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
15129 #undef THUMB_VARIANT
15130 #define THUMB_VARIANT &arm_ext_v6
15131 TUF(cpsie
, 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
15132 TUF(cpsid
, 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
15133 tCE(rev
, 6bf0f30
, rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15134 tCE(rev16
, 6bf0fb0
, rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15135 tCE(revsh
, 6ff0fb0
, revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15136 tCE(sxth
, 6bf0070
, sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15137 tCE(uxth
, 6ff0070
, uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15138 tCE(sxtb
, 6af0070
, sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15139 tCE(uxtb
, 6ef0070
, uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15140 TUF(setend
, 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
15142 #undef THUMB_VARIANT
15143 #define THUMB_VARIANT &arm_ext_v6t2
15144 TCE(ldrex
, 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
15145 TCE(strex
, 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
15146 TUF(mcrr2
, c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15147 TUF(mrrc2
, c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15149 TCE(ssat
, 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
15150 TCE(usat
, 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
15152 /* ARM V6 not included in V7M (eg. integer SIMD). */
15153 #undef THUMB_VARIANT
15154 #define THUMB_VARIANT &arm_ext_v6_notm
15155 TUF(cps
, 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
15156 TCE(pkhbt
, 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
15157 TCE(pkhtb
, 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
15158 TCE(qadd16
, 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15159 TCE(qadd8
, 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15160 TCE(qaddsubx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15161 TCE(qsub16
, 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15162 TCE(qsub8
, 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15163 TCE(qsubaddx
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15164 TCE(sadd16
, 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15165 TCE(sadd8
, 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15166 TCE(saddsubx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15167 TCE(shadd16
, 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15168 TCE(shadd8
, 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15169 TCE(shaddsubx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15170 TCE(shsub16
, 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15171 TCE(shsub8
, 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15172 TCE(shsubaddx
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15173 TCE(ssub16
, 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15174 TCE(ssub8
, 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15175 TCE(ssubaddx
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15176 TCE(uadd16
, 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15177 TCE(uadd8
, 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15178 TCE(uaddsubx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15179 TCE(uhadd16
, 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15180 TCE(uhadd8
, 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15181 TCE(uhaddsubx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15182 TCE(uhsub16
, 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15183 TCE(uhsub8
, 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15184 TCE(uhsubaddx
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15185 TCE(uqadd16
, 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15186 TCE(uqadd8
, 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15187 TCE(uqaddsubx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15188 TCE(uqsub16
, 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15189 TCE(uqsub8
, 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15190 TCE(uqsubaddx
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15191 TCE(usub16
, 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15192 TCE(usub8
, 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15193 TCE(usubaddx
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15194 TUF(rfeia
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
15195 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
15196 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
15197 TUF(rfedb
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
15198 TUF(rfefd
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
15199 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
15200 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
15201 TUF(rfeed
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
15202 TCE(sxtah
, 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15203 TCE(sxtab16
, 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15204 TCE(sxtab
, 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15205 TCE(sxtb16
, 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15206 TCE(uxtah
, 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15207 TCE(uxtab16
, 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15208 TCE(uxtab
, 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15209 TCE(uxtb16
, 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15210 TCE(sel
, 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15211 TCE(smlad
, 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15212 TCE(smladx
, 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15213 TCE(smlald
, 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15214 TCE(smlaldx
, 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15215 TCE(smlsd
, 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15216 TCE(smlsdx
, 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15217 TCE(smlsld
, 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15218 TCE(smlsldx
, 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15219 TCE(smmla
, 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15220 TCE(smmlar
, 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15221 TCE(smmls
, 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15222 TCE(smmlsr
, 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15223 TCE(smmul
, 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15224 TCE(smmulr
, 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15225 TCE(smuad
, 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15226 TCE(smuadx
, 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15227 TCE(smusd
, 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15228 TCE(smusdx
, 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15229 TUF(srsia
, 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
15230 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
15231 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
15232 TUF(srsdb
, 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
15233 TCE(ssat16
, 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
15234 TCE(umaal
, 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
15235 TCE(usad8
, 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15236 TCE(usada8
, 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15237 TCE(usat16
, 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
15240 #define ARM_VARIANT &arm_ext_v6k
15241 #undef THUMB_VARIANT
15242 #define THUMB_VARIANT &arm_ext_v6k
15243 tCE(yield
, 320f001
, yield
, 0, (), noargs
, t_hint
),
15244 tCE(wfe
, 320f002
, wfe
, 0, (), noargs
, t_hint
),
15245 tCE(wfi
, 320f003
, wfi
, 0, (), noargs
, t_hint
),
15246 tCE(sev
, 320f004
, sev
, 0, (), noargs
, t_hint
),
15248 #undef THUMB_VARIANT
15249 #define THUMB_VARIANT &arm_ext_v6_notm
15250 TCE(ldrexd
, 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
15251 TCE(strexd
, 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
15253 #undef THUMB_VARIANT
15254 #define THUMB_VARIANT &arm_ext_v6t2
15255 TCE(ldrexb
, 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
15256 TCE(ldrexh
, 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
15257 TCE(strexb
, 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
15258 TCE(strexh
, 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
15259 TUF(clrex
, 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
15262 #define ARM_VARIANT &arm_ext_v6z
15263 TCE(smc
, 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
15266 #define ARM_VARIANT &arm_ext_v6t2
15267 TCE(bfc
, 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
15268 TCE(bfi
, 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
15269 TCE(sbfx
, 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
15270 TCE(ubfx
, 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
15272 TCE(mls
, 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
15273 TCE(movw
, 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
15274 TCE(movt
, 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
15275 TCE(rbit
, 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
15277 TC3(ldrht
, 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15278 TC3(ldrsht
, 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15279 TC3(ldrsbt
, 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15280 TC3(strht
, 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15282 UT(cbnz
, b900
, 2, (RR
, EXP
), t_cbz
),
15283 UT(cbz
, b100
, 2, (RR
, EXP
), t_cbz
),
15284 /* ARM does not really have an IT instruction, so always allow it. */
15286 #define ARM_VARIANT &arm_ext_v1
15287 TUE(it
, 0, bf08
, 1, (COND
), it
, t_it
),
15288 TUE(itt
, 0, bf0c
, 1, (COND
), it
, t_it
),
15289 TUE(ite
, 0, bf04
, 1, (COND
), it
, t_it
),
15290 TUE(ittt
, 0, bf0e
, 1, (COND
), it
, t_it
),
15291 TUE(itet
, 0, bf06
, 1, (COND
), it
, t_it
),
15292 TUE(itte
, 0, bf0a
, 1, (COND
), it
, t_it
),
15293 TUE(itee
, 0, bf02
, 1, (COND
), it
, t_it
),
15294 TUE(itttt
, 0, bf0f
, 1, (COND
), it
, t_it
),
15295 TUE(itett
, 0, bf07
, 1, (COND
), it
, t_it
),
15296 TUE(ittet
, 0, bf0b
, 1, (COND
), it
, t_it
),
15297 TUE(iteet
, 0, bf03
, 1, (COND
), it
, t_it
),
15298 TUE(ittte
, 0, bf0d
, 1, (COND
), it
, t_it
),
15299 TUE(itete
, 0, bf05
, 1, (COND
), it
, t_it
),
15300 TUE(ittee
, 0, bf09
, 1, (COND
), it
, t_it
),
15301 TUE(iteee
, 0, bf01
, 1, (COND
), it
, t_it
),
15303 /* Thumb2 only instructions. */
15305 #define ARM_VARIANT NULL
15307 TCE(addw
, 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
15308 TCE(subw
, 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
15309 TCE(tbb
, 0, e8d0f000
, 1, (TB
), 0, t_tb
),
15310 TCE(tbh
, 0, e8d0f010
, 1, (TB
), 0, t_tb
),
15312 /* Thumb-2 hardware division instructions (R and M profiles only). */
15313 #undef THUMB_VARIANT
15314 #define THUMB_VARIANT &arm_ext_div
15315 TCE(sdiv
, 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
15316 TCE(udiv
, 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
15318 /* ARM V7 instructions. */
15320 #define ARM_VARIANT &arm_ext_v7
15321 #undef THUMB_VARIANT
15322 #define THUMB_VARIANT &arm_ext_v7
15323 TUF(pli
, 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
15324 TCE(dbg
, 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
15325 TUF(dmb
, 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
15326 TUF(dsb
, 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
15327 TUF(isb
, 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
15330 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
15331 cCE(wfs
, e200110
, 1, (RR
), rd
),
15332 cCE(rfs
, e300110
, 1, (RR
), rd
),
15333 cCE(wfc
, e400110
, 1, (RR
), rd
),
15334 cCE(rfc
, e500110
, 1, (RR
), rd
),
15336 cCL(ldfs
, c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15337 cCL(ldfd
, c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15338 cCL(ldfe
, c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15339 cCL(ldfp
, c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15341 cCL(stfs
, c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15342 cCL(stfd
, c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15343 cCL(stfe
, c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15344 cCL(stfp
, c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15346 cCL(mvfs
, e008100
, 2, (RF
, RF_IF
), rd_rm
),
15347 cCL(mvfsp
, e008120
, 2, (RF
, RF_IF
), rd_rm
),
15348 cCL(mvfsm
, e008140
, 2, (RF
, RF_IF
), rd_rm
),
15349 cCL(mvfsz
, e008160
, 2, (RF
, RF_IF
), rd_rm
),
15350 cCL(mvfd
, e008180
, 2, (RF
, RF_IF
), rd_rm
),
15351 cCL(mvfdp
, e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
15352 cCL(mvfdm
, e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
15353 cCL(mvfdz
, e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
15354 cCL(mvfe
, e088100
, 2, (RF
, RF_IF
), rd_rm
),
15355 cCL(mvfep
, e088120
, 2, (RF
, RF_IF
), rd_rm
),
15356 cCL(mvfem
, e088140
, 2, (RF
, RF_IF
), rd_rm
),
15357 cCL(mvfez
, e088160
, 2, (RF
, RF_IF
), rd_rm
),
15359 cCL(mnfs
, e108100
, 2, (RF
, RF_IF
), rd_rm
),
15360 cCL(mnfsp
, e108120
, 2, (RF
, RF_IF
), rd_rm
),
15361 cCL(mnfsm
, e108140
, 2, (RF
, RF_IF
), rd_rm
),
15362 cCL(mnfsz
, e108160
, 2, (RF
, RF_IF
), rd_rm
),
15363 cCL(mnfd
, e108180
, 2, (RF
, RF_IF
), rd_rm
),
15364 cCL(mnfdp
, e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
15365 cCL(mnfdm
, e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
15366 cCL(mnfdz
, e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
15367 cCL(mnfe
, e188100
, 2, (RF
, RF_IF
), rd_rm
),
15368 cCL(mnfep
, e188120
, 2, (RF
, RF_IF
), rd_rm
),
15369 cCL(mnfem
, e188140
, 2, (RF
, RF_IF
), rd_rm
),
15370 cCL(mnfez
, e188160
, 2, (RF
, RF_IF
), rd_rm
),
15372 cCL(abss
, e208100
, 2, (RF
, RF_IF
), rd_rm
),
15373 cCL(abssp
, e208120
, 2, (RF
, RF_IF
), rd_rm
),
15374 cCL(abssm
, e208140
, 2, (RF
, RF_IF
), rd_rm
),
15375 cCL(abssz
, e208160
, 2, (RF
, RF_IF
), rd_rm
),
15376 cCL(absd
, e208180
, 2, (RF
, RF_IF
), rd_rm
),
15377 cCL(absdp
, e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
15378 cCL(absdm
, e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
15379 cCL(absdz
, e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
15380 cCL(abse
, e288100
, 2, (RF
, RF_IF
), rd_rm
),
15381 cCL(absep
, e288120
, 2, (RF
, RF_IF
), rd_rm
),
15382 cCL(absem
, e288140
, 2, (RF
, RF_IF
), rd_rm
),
15383 cCL(absez
, e288160
, 2, (RF
, RF_IF
), rd_rm
),
15385 cCL(rnds
, e308100
, 2, (RF
, RF_IF
), rd_rm
),
15386 cCL(rndsp
, e308120
, 2, (RF
, RF_IF
), rd_rm
),
15387 cCL(rndsm
, e308140
, 2, (RF
, RF_IF
), rd_rm
),
15388 cCL(rndsz
, e308160
, 2, (RF
, RF_IF
), rd_rm
),
15389 cCL(rndd
, e308180
, 2, (RF
, RF_IF
), rd_rm
),
15390 cCL(rnddp
, e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
15391 cCL(rnddm
, e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
15392 cCL(rnddz
, e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
15393 cCL(rnde
, e388100
, 2, (RF
, RF_IF
), rd_rm
),
15394 cCL(rndep
, e388120
, 2, (RF
, RF_IF
), rd_rm
),
15395 cCL(rndem
, e388140
, 2, (RF
, RF_IF
), rd_rm
),
15396 cCL(rndez
, e388160
, 2, (RF
, RF_IF
), rd_rm
),
15398 cCL(sqts
, e408100
, 2, (RF
, RF_IF
), rd_rm
),
15399 cCL(sqtsp
, e408120
, 2, (RF
, RF_IF
), rd_rm
),
15400 cCL(sqtsm
, e408140
, 2, (RF
, RF_IF
), rd_rm
),
15401 cCL(sqtsz
, e408160
, 2, (RF
, RF_IF
), rd_rm
),
15402 cCL(sqtd
, e408180
, 2, (RF
, RF_IF
), rd_rm
),
15403 cCL(sqtdp
, e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
15404 cCL(sqtdm
, e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
15405 cCL(sqtdz
, e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
15406 cCL(sqte
, e488100
, 2, (RF
, RF_IF
), rd_rm
),
15407 cCL(sqtep
, e488120
, 2, (RF
, RF_IF
), rd_rm
),
15408 cCL(sqtem
, e488140
, 2, (RF
, RF_IF
), rd_rm
),
15409 cCL(sqtez
, e488160
, 2, (RF
, RF_IF
), rd_rm
),
15411 cCL(logs
, e508100
, 2, (RF
, RF_IF
), rd_rm
),
15412 cCL(logsp
, e508120
, 2, (RF
, RF_IF
), rd_rm
),
15413 cCL(logsm
, e508140
, 2, (RF
, RF_IF
), rd_rm
),
15414 cCL(logsz
, e508160
, 2, (RF
, RF_IF
), rd_rm
),
15415 cCL(logd
, e508180
, 2, (RF
, RF_IF
), rd_rm
),
15416 cCL(logdp
, e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
15417 cCL(logdm
, e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
15418 cCL(logdz
, e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
15419 cCL(loge
, e588100
, 2, (RF
, RF_IF
), rd_rm
),
15420 cCL(logep
, e588120
, 2, (RF
, RF_IF
), rd_rm
),
15421 cCL(logem
, e588140
, 2, (RF
, RF_IF
), rd_rm
),
15422 cCL(logez
, e588160
, 2, (RF
, RF_IF
), rd_rm
),
15424 cCL(lgns
, e608100
, 2, (RF
, RF_IF
), rd_rm
),
15425 cCL(lgnsp
, e608120
, 2, (RF
, RF_IF
), rd_rm
),
15426 cCL(lgnsm
, e608140
, 2, (RF
, RF_IF
), rd_rm
),
15427 cCL(lgnsz
, e608160
, 2, (RF
, RF_IF
), rd_rm
),
15428 cCL(lgnd
, e608180
, 2, (RF
, RF_IF
), rd_rm
),
15429 cCL(lgndp
, e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
15430 cCL(lgndm
, e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
15431 cCL(lgndz
, e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
15432 cCL(lgne
, e688100
, 2, (RF
, RF_IF
), rd_rm
),
15433 cCL(lgnep
, e688120
, 2, (RF
, RF_IF
), rd_rm
),
15434 cCL(lgnem
, e688140
, 2, (RF
, RF_IF
), rd_rm
),
15435 cCL(lgnez
, e688160
, 2, (RF
, RF_IF
), rd_rm
),
15437 cCL(exps
, e708100
, 2, (RF
, RF_IF
), rd_rm
),
15438 cCL(expsp
, e708120
, 2, (RF
, RF_IF
), rd_rm
),
15439 cCL(expsm
, e708140
, 2, (RF
, RF_IF
), rd_rm
),
15440 cCL(expsz
, e708160
, 2, (RF
, RF_IF
), rd_rm
),
15441 cCL(expd
, e708180
, 2, (RF
, RF_IF
), rd_rm
),
15442 cCL(expdp
, e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
15443 cCL(expdm
, e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
15444 cCL(expdz
, e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
15445 cCL(expe
, e788100
, 2, (RF
, RF_IF
), rd_rm
),
15446 cCL(expep
, e788120
, 2, (RF
, RF_IF
), rd_rm
),
15447 cCL(expem
, e788140
, 2, (RF
, RF_IF
), rd_rm
),
15448 cCL(expdz
, e788160
, 2, (RF
, RF_IF
), rd_rm
),
15450 cCL(sins
, e808100
, 2, (RF
, RF_IF
), rd_rm
),
15451 cCL(sinsp
, e808120
, 2, (RF
, RF_IF
), rd_rm
),
15452 cCL(sinsm
, e808140
, 2, (RF
, RF_IF
), rd_rm
),
15453 cCL(sinsz
, e808160
, 2, (RF
, RF_IF
), rd_rm
),
15454 cCL(sind
, e808180
, 2, (RF
, RF_IF
), rd_rm
),
15455 cCL(sindp
, e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
15456 cCL(sindm
, e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
15457 cCL(sindz
, e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
15458 cCL(sine
, e888100
, 2, (RF
, RF_IF
), rd_rm
),
15459 cCL(sinep
, e888120
, 2, (RF
, RF_IF
), rd_rm
),
15460 cCL(sinem
, e888140
, 2, (RF
, RF_IF
), rd_rm
),
15461 cCL(sinez
, e888160
, 2, (RF
, RF_IF
), rd_rm
),
15463 cCL(coss
, e908100
, 2, (RF
, RF_IF
), rd_rm
),
15464 cCL(cossp
, e908120
, 2, (RF
, RF_IF
), rd_rm
),
15465 cCL(cossm
, e908140
, 2, (RF
, RF_IF
), rd_rm
),
15466 cCL(cossz
, e908160
, 2, (RF
, RF_IF
), rd_rm
),
15467 cCL(cosd
, e908180
, 2, (RF
, RF_IF
), rd_rm
),
15468 cCL(cosdp
, e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
15469 cCL(cosdm
, e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
15470 cCL(cosdz
, e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
15471 cCL(cose
, e988100
, 2, (RF
, RF_IF
), rd_rm
),
15472 cCL(cosep
, e988120
, 2, (RF
, RF_IF
), rd_rm
),
15473 cCL(cosem
, e988140
, 2, (RF
, RF_IF
), rd_rm
),
15474 cCL(cosez
, e988160
, 2, (RF
, RF_IF
), rd_rm
),
15476 cCL(tans
, ea08100
, 2, (RF
, RF_IF
), rd_rm
),
15477 cCL(tansp
, ea08120
, 2, (RF
, RF_IF
), rd_rm
),
15478 cCL(tansm
, ea08140
, 2, (RF
, RF_IF
), rd_rm
),
15479 cCL(tansz
, ea08160
, 2, (RF
, RF_IF
), rd_rm
),
15480 cCL(tand
, ea08180
, 2, (RF
, RF_IF
), rd_rm
),
15481 cCL(tandp
, ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
15482 cCL(tandm
, ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
15483 cCL(tandz
, ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
15484 cCL(tane
, ea88100
, 2, (RF
, RF_IF
), rd_rm
),
15485 cCL(tanep
, ea88120
, 2, (RF
, RF_IF
), rd_rm
),
15486 cCL(tanem
, ea88140
, 2, (RF
, RF_IF
), rd_rm
),
15487 cCL(tanez
, ea88160
, 2, (RF
, RF_IF
), rd_rm
),
15489 cCL(asns
, eb08100
, 2, (RF
, RF_IF
), rd_rm
),
15490 cCL(asnsp
, eb08120
, 2, (RF
, RF_IF
), rd_rm
),
15491 cCL(asnsm
, eb08140
, 2, (RF
, RF_IF
), rd_rm
),
15492 cCL(asnsz
, eb08160
, 2, (RF
, RF_IF
), rd_rm
),
15493 cCL(asnd
, eb08180
, 2, (RF
, RF_IF
), rd_rm
),
15494 cCL(asndp
, eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
15495 cCL(asndm
, eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
15496 cCL(asndz
, eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
15497 cCL(asne
, eb88100
, 2, (RF
, RF_IF
), rd_rm
),
15498 cCL(asnep
, eb88120
, 2, (RF
, RF_IF
), rd_rm
),
15499 cCL(asnem
, eb88140
, 2, (RF
, RF_IF
), rd_rm
),
15500 cCL(asnez
, eb88160
, 2, (RF
, RF_IF
), rd_rm
),
15502 cCL(acss
, ec08100
, 2, (RF
, RF_IF
), rd_rm
),
15503 cCL(acssp
, ec08120
, 2, (RF
, RF_IF
), rd_rm
),
15504 cCL(acssm
, ec08140
, 2, (RF
, RF_IF
), rd_rm
),
15505 cCL(acssz
, ec08160
, 2, (RF
, RF_IF
), rd_rm
),
15506 cCL(acsd
, ec08180
, 2, (RF
, RF_IF
), rd_rm
),
15507 cCL(acsdp
, ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
15508 cCL(acsdm
, ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
15509 cCL(acsdz
, ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
15510 cCL(acse
, ec88100
, 2, (RF
, RF_IF
), rd_rm
),
15511 cCL(acsep
, ec88120
, 2, (RF
, RF_IF
), rd_rm
),
15512 cCL(acsem
, ec88140
, 2, (RF
, RF_IF
), rd_rm
),
15513 cCL(acsez
, ec88160
, 2, (RF
, RF_IF
), rd_rm
),
15515 cCL(atns
, ed08100
, 2, (RF
, RF_IF
), rd_rm
),
15516 cCL(atnsp
, ed08120
, 2, (RF
, RF_IF
), rd_rm
),
15517 cCL(atnsm
, ed08140
, 2, (RF
, RF_IF
), rd_rm
),
15518 cCL(atnsz
, ed08160
, 2, (RF
, RF_IF
), rd_rm
),
15519 cCL(atnd
, ed08180
, 2, (RF
, RF_IF
), rd_rm
),
15520 cCL(atndp
, ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
15521 cCL(atndm
, ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
15522 cCL(atndz
, ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
15523 cCL(atne
, ed88100
, 2, (RF
, RF_IF
), rd_rm
),
15524 cCL(atnep
, ed88120
, 2, (RF
, RF_IF
), rd_rm
),
15525 cCL(atnem
, ed88140
, 2, (RF
, RF_IF
), rd_rm
),
15526 cCL(atnez
, ed88160
, 2, (RF
, RF_IF
), rd_rm
),
15528 cCL(urds
, ee08100
, 2, (RF
, RF_IF
), rd_rm
),
15529 cCL(urdsp
, ee08120
, 2, (RF
, RF_IF
), rd_rm
),
15530 cCL(urdsm
, ee08140
, 2, (RF
, RF_IF
), rd_rm
),
15531 cCL(urdsz
, ee08160
, 2, (RF
, RF_IF
), rd_rm
),
15532 cCL(urdd
, ee08180
, 2, (RF
, RF_IF
), rd_rm
),
15533 cCL(urddp
, ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
15534 cCL(urddm
, ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
15535 cCL(urddz
, ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
15536 cCL(urde
, ee88100
, 2, (RF
, RF_IF
), rd_rm
),
15537 cCL(urdep
, ee88120
, 2, (RF
, RF_IF
), rd_rm
),
15538 cCL(urdem
, ee88140
, 2, (RF
, RF_IF
), rd_rm
),
15539 cCL(urdez
, ee88160
, 2, (RF
, RF_IF
), rd_rm
),
15541 cCL(nrms
, ef08100
, 2, (RF
, RF_IF
), rd_rm
),
15542 cCL(nrmsp
, ef08120
, 2, (RF
, RF_IF
), rd_rm
),
15543 cCL(nrmsm
, ef08140
, 2, (RF
, RF_IF
), rd_rm
),
15544 cCL(nrmsz
, ef08160
, 2, (RF
, RF_IF
), rd_rm
),
15545 cCL(nrmd
, ef08180
, 2, (RF
, RF_IF
), rd_rm
),
15546 cCL(nrmdp
, ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
15547 cCL(nrmdm
, ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
15548 cCL(nrmdz
, ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
15549 cCL(nrme
, ef88100
, 2, (RF
, RF_IF
), rd_rm
),
15550 cCL(nrmep
, ef88120
, 2, (RF
, RF_IF
), rd_rm
),
15551 cCL(nrmem
, ef88140
, 2, (RF
, RF_IF
), rd_rm
),
15552 cCL(nrmez
, ef88160
, 2, (RF
, RF_IF
), rd_rm
),
15554 cCL(adfs
, e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15555 cCL(adfsp
, e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15556 cCL(adfsm
, e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15557 cCL(adfsz
, e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15558 cCL(adfd
, e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15559 cCL(adfdp
, e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15560 cCL(adfdm
, e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15561 cCL(adfdz
, e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15562 cCL(adfe
, e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15563 cCL(adfep
, e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15564 cCL(adfem
, e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15565 cCL(adfez
, e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15567 cCL(sufs
, e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15568 cCL(sufsp
, e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15569 cCL(sufsm
, e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15570 cCL(sufsz
, e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15571 cCL(sufd
, e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15572 cCL(sufdp
, e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15573 cCL(sufdm
, e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15574 cCL(sufdz
, e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15575 cCL(sufe
, e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15576 cCL(sufep
, e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15577 cCL(sufem
, e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15578 cCL(sufez
, e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15580 cCL(rsfs
, e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15581 cCL(rsfsp
, e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15582 cCL(rsfsm
, e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15583 cCL(rsfsz
, e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15584 cCL(rsfd
, e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15585 cCL(rsfdp
, e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15586 cCL(rsfdm
, e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15587 cCL(rsfdz
, e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15588 cCL(rsfe
, e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15589 cCL(rsfep
, e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15590 cCL(rsfem
, e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15591 cCL(rsfez
, e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15593 cCL(mufs
, e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15594 cCL(mufsp
, e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15595 cCL(mufsm
, e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15596 cCL(mufsz
, e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15597 cCL(mufd
, e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15598 cCL(mufdp
, e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15599 cCL(mufdm
, e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15600 cCL(mufdz
, e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15601 cCL(mufe
, e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15602 cCL(mufep
, e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15603 cCL(mufem
, e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15604 cCL(mufez
, e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15606 cCL(dvfs
, e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15607 cCL(dvfsp
, e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15608 cCL(dvfsm
, e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15609 cCL(dvfsz
, e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15610 cCL(dvfd
, e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15611 cCL(dvfdp
, e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15612 cCL(dvfdm
, e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15613 cCL(dvfdz
, e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15614 cCL(dvfe
, e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15615 cCL(dvfep
, e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15616 cCL(dvfem
, e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15617 cCL(dvfez
, e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15619 cCL(rdfs
, e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15620 cCL(rdfsp
, e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15621 cCL(rdfsm
, e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15622 cCL(rdfsz
, e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15623 cCL(rdfd
, e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15624 cCL(rdfdp
, e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15625 cCL(rdfdm
, e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15626 cCL(rdfdz
, e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15627 cCL(rdfe
, e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15628 cCL(rdfep
, e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15629 cCL(rdfem
, e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15630 cCL(rdfez
, e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15632 cCL(pows
, e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15633 cCL(powsp
, e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15634 cCL(powsm
, e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15635 cCL(powsz
, e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15636 cCL(powd
, e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15637 cCL(powdp
, e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15638 cCL(powdm
, e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15639 cCL(powdz
, e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15640 cCL(powe
, e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15641 cCL(powep
, e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15642 cCL(powem
, e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15643 cCL(powez
, e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15645 cCL(rpws
, e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15646 cCL(rpwsp
, e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15647 cCL(rpwsm
, e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15648 cCL(rpwsz
, e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15649 cCL(rpwd
, e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15650 cCL(rpwdp
, e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15651 cCL(rpwdm
, e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15652 cCL(rpwdz
, e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15653 cCL(rpwe
, e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15654 cCL(rpwep
, e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15655 cCL(rpwem
, e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15656 cCL(rpwez
, e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15658 cCL(rmfs
, e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15659 cCL(rmfsp
, e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15660 cCL(rmfsm
, e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15661 cCL(rmfsz
, e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15662 cCL(rmfd
, e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15663 cCL(rmfdp
, e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15664 cCL(rmfdm
, e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15665 cCL(rmfdz
, e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15666 cCL(rmfe
, e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15667 cCL(rmfep
, e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15668 cCL(rmfem
, e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15669 cCL(rmfez
, e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15671 cCL(fmls
, e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15672 cCL(fmlsp
, e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15673 cCL(fmlsm
, e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15674 cCL(fmlsz
, e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15675 cCL(fmld
, e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15676 cCL(fmldp
, e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15677 cCL(fmldm
, e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15678 cCL(fmldz
, e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15679 cCL(fmle
, e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15680 cCL(fmlep
, e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15681 cCL(fmlem
, e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15682 cCL(fmlez
, e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15684 cCL(fdvs
, ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15685 cCL(fdvsp
, ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15686 cCL(fdvsm
, ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15687 cCL(fdvsz
, ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15688 cCL(fdvd
, ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15689 cCL(fdvdp
, ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15690 cCL(fdvdm
, ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15691 cCL(fdvdz
, ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15692 cCL(fdve
, ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15693 cCL(fdvep
, ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15694 cCL(fdvem
, ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15695 cCL(fdvez
, ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15697 cCL(frds
, eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15698 cCL(frdsp
, eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15699 cCL(frdsm
, eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15700 cCL(frdsz
, eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15701 cCL(frdd
, eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15702 cCL(frddp
, eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15703 cCL(frddm
, eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15704 cCL(frddz
, eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15705 cCL(frde
, eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15706 cCL(frdep
, eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15707 cCL(frdem
, eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15708 cCL(frdez
, eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15710 cCL(pols
, ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15711 cCL(polsp
, ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15712 cCL(polsm
, ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15713 cCL(polsz
, ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15714 cCL(pold
, ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15715 cCL(poldp
, ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15716 cCL(poldm
, ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15717 cCL(poldz
, ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15718 cCL(pole
, ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15719 cCL(polep
, ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15720 cCL(polem
, ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15721 cCL(polez
, ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15723 cCE(cmf
, e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15724 C3E(cmfe
, ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15725 cCE(cnf
, eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15726 C3E(cnfe
, ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15728 cCL(flts
, e000110
, 2, (RF
, RR
), rn_rd
),
15729 cCL(fltsp
, e000130
, 2, (RF
, RR
), rn_rd
),
15730 cCL(fltsm
, e000150
, 2, (RF
, RR
), rn_rd
),
15731 cCL(fltsz
, e000170
, 2, (RF
, RR
), rn_rd
),
15732 cCL(fltd
, e000190
, 2, (RF
, RR
), rn_rd
),
15733 cCL(fltdp
, e0001b0
, 2, (RF
, RR
), rn_rd
),
15734 cCL(fltdm
, e0001d0
, 2, (RF
, RR
), rn_rd
),
15735 cCL(fltdz
, e0001f0
, 2, (RF
, RR
), rn_rd
),
15736 cCL(flte
, e080110
, 2, (RF
, RR
), rn_rd
),
15737 cCL(fltep
, e080130
, 2, (RF
, RR
), rn_rd
),
15738 cCL(fltem
, e080150
, 2, (RF
, RR
), rn_rd
),
15739 cCL(fltez
, e080170
, 2, (RF
, RR
), rn_rd
),
15741 /* The implementation of the FIX instruction is broken on some
15742 assemblers, in that it accepts a precision specifier as well as a
15743 rounding specifier, despite the fact that this is meaningless.
15744 To be more compatible, we accept it as well, though of course it
15745 does not set any bits. */
15746 cCE(fix
, e100110
, 2, (RR
, RF
), rd_rm
),
15747 cCL(fixp
, e100130
, 2, (RR
, RF
), rd_rm
),
15748 cCL(fixm
, e100150
, 2, (RR
, RF
), rd_rm
),
15749 cCL(fixz
, e100170
, 2, (RR
, RF
), rd_rm
),
15750 cCL(fixsp
, e100130
, 2, (RR
, RF
), rd_rm
),
15751 cCL(fixsm
, e100150
, 2, (RR
, RF
), rd_rm
),
15752 cCL(fixsz
, e100170
, 2, (RR
, RF
), rd_rm
),
15753 cCL(fixdp
, e100130
, 2, (RR
, RF
), rd_rm
),
15754 cCL(fixdm
, e100150
, 2, (RR
, RF
), rd_rm
),
15755 cCL(fixdz
, e100170
, 2, (RR
, RF
), rd_rm
),
15756 cCL(fixep
, e100130
, 2, (RR
, RF
), rd_rm
),
15757 cCL(fixem
, e100150
, 2, (RR
, RF
), rd_rm
),
15758 cCL(fixez
, e100170
, 2, (RR
, RF
), rd_rm
),
15760 /* Instructions that were new with the real FPA, call them V2. */
15762 #define ARM_VARIANT &fpu_fpa_ext_v2
15763 cCE(lfm
, c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15764 cCL(lfmfd
, c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15765 cCL(lfmea
, d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15766 cCE(sfm
, c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15767 cCL(sfmfd
, d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15768 cCL(sfmea
, c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15771 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
15772 /* Moves and type conversions. */
15773 cCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15774 cCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
15775 cCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
15776 cCE(fmstat
, ef1fa10
, 0, (), noargs
),
15777 cCE(fsitos
, eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15778 cCE(fuitos
, eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15779 cCE(ftosis
, ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15780 cCE(ftosizs
, ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15781 cCE(ftouis
, ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15782 cCE(ftouizs
, ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15783 cCE(fmrx
, ef00a10
, 2, (RR
, RVC
), rd_rn
),
15784 cCE(fmxr
, ee00a10
, 2, (RVC
, RR
), rn_rd
),
15786 /* Memory operations. */
15787 cCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15788 cCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15789 cCE(fldmias
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15790 cCE(fldmfds
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15791 cCE(fldmdbs
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15792 cCE(fldmeas
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15793 cCE(fldmiax
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15794 cCE(fldmfdx
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15795 cCE(fldmdbx
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15796 cCE(fldmeax
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15797 cCE(fstmias
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15798 cCE(fstmeas
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15799 cCE(fstmdbs
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15800 cCE(fstmfds
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15801 cCE(fstmiax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15802 cCE(fstmeax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15803 cCE(fstmdbx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15804 cCE(fstmfdx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15806 /* Monadic operations. */
15807 cCE(fabss
, eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15808 cCE(fnegs
, eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15809 cCE(fsqrts
, eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15811 /* Dyadic operations. */
15812 cCE(fadds
, e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15813 cCE(fsubs
, e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15814 cCE(fmuls
, e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15815 cCE(fdivs
, e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15816 cCE(fmacs
, e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15817 cCE(fmscs
, e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15818 cCE(fnmuls
, e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15819 cCE(fnmacs
, e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15820 cCE(fnmscs
, e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15823 cCE(fcmps
, eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15824 cCE(fcmpzs
, eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
15825 cCE(fcmpes
, eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15826 cCE(fcmpezs
, eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
15829 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
15830 /* Moves and type conversions. */
15831 cCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15832 cCE(fcvtds
, eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15833 cCE(fcvtsd
, eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15834 cCE(fmdhr
, e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15835 cCE(fmdlr
, e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15836 cCE(fmrdh
, e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15837 cCE(fmrdl
, e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15838 cCE(fsitod
, eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15839 cCE(fuitod
, eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15840 cCE(ftosid
, ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15841 cCE(ftosizd
, ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15842 cCE(ftouid
, ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15843 cCE(ftouizd
, ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15845 /* Memory operations. */
15846 cCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15847 cCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15848 cCE(fldmiad
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15849 cCE(fldmfdd
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15850 cCE(fldmdbd
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15851 cCE(fldmead
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15852 cCE(fstmiad
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15853 cCE(fstmead
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15854 cCE(fstmdbd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15855 cCE(fstmfdd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15857 /* Monadic operations. */
15858 cCE(fabsd
, eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15859 cCE(fnegd
, eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15860 cCE(fsqrtd
, eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15862 /* Dyadic operations. */
15863 cCE(faddd
, e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15864 cCE(fsubd
, e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15865 cCE(fmuld
, e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15866 cCE(fdivd
, e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15867 cCE(fmacd
, e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15868 cCE(fmscd
, e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15869 cCE(fnmuld
, e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15870 cCE(fnmacd
, e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15871 cCE(fnmscd
, e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15874 cCE(fcmpd
, eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15875 cCE(fcmpzd
, eb50b40
, 1, (RVD
), vfp_dp_rd
),
15876 cCE(fcmped
, eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15877 cCE(fcmpezd
, eb50bc0
, 1, (RVD
), vfp_dp_rd
),
15880 #define ARM_VARIANT &fpu_vfp_ext_v2
15881 cCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
15882 cCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
15883 cCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
15884 cCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
15886 /* Instructions which may belong to either the Neon or VFP instruction sets.
15887 Individual encoder functions perform additional architecture checks. */
15889 #define ARM_VARIANT &fpu_vfp_ext_v1xd
15890 #undef THUMB_VARIANT
15891 #define THUMB_VARIANT &fpu_vfp_ext_v1xd
15892 /* These mnemonics are unique to VFP. */
15893 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
15894 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
15895 nCE(vnmul
, vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15896 nCE(vnmla
, vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15897 nCE(vnmls
, vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15898 nCE(vcmp
, vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15899 nCE(vcmpe
, vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15900 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
15901 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
15902 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
15904 /* Mnemonics shared by Neon and VFP. */
15905 nCEF(vmul
, vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
15906 nCEF(vmla
, vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15907 nCEF(vmls
, vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15909 nCEF(vadd
, vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15910 nCEF(vsub
, vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15912 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15913 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15915 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15916 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15917 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15918 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15919 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15920 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15921 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15922 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15924 nCEF(vcvt
, vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
15926 /* NOTE: All VMOV encoding is special-cased! */
15927 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
15928 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
15930 #undef THUMB_VARIANT
15931 #define THUMB_VARIANT &fpu_neon_ext_v1
15933 #define ARM_VARIANT &fpu_neon_ext_v1
15934 /* Data processing with three registers of the same length. */
15935 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
15936 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
15937 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
15938 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15939 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15940 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15941 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15942 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15943 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15944 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
15945 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15946 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15947 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15948 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15949 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
15950 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
15951 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
15952 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
15953 /* If not immediate, fall back to neon_dyadic_i64_su.
15954 shl_imm should accept I8 I16 I32 I64,
15955 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
15956 nUF(vshl
, vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
15957 nUF(vshlq
, vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
15958 nUF(vqshl
, vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
15959 nUF(vqshlq
, vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
15960 /* Logic ops, types optional & ignored. */
15961 nUF(vand
, vand
, 2, (RNDQ
, NILO
), neon_logic
),
15962 nUF(vandq
, vand
, 2, (RNQ
, NILO
), neon_logic
),
15963 nUF(vbic
, vbic
, 2, (RNDQ
, NILO
), neon_logic
),
15964 nUF(vbicq
, vbic
, 2, (RNQ
, NILO
), neon_logic
),
15965 nUF(vorr
, vorr
, 2, (RNDQ
, NILO
), neon_logic
),
15966 nUF(vorrq
, vorr
, 2, (RNQ
, NILO
), neon_logic
),
15967 nUF(vorn
, vorn
, 2, (RNDQ
, NILO
), neon_logic
),
15968 nUF(vornq
, vorn
, 2, (RNQ
, NILO
), neon_logic
),
15969 nUF(veor
, veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
15970 nUF(veorq
, veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
15971 /* Bitfield ops, untyped. */
15972 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15973 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15974 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15975 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15976 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15977 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15978 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
15979 nUF(vabd
, vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15980 nUF(vabdq
, vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15981 nUF(vmax
, vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15982 nUF(vmaxq
, vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15983 nUF(vmin
, vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15984 nUF(vminq
, vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15985 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
15986 back to neon_dyadic_if_su. */
15987 nUF(vcge
, vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
15988 nUF(vcgeq
, vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
15989 nUF(vcgt
, vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
15990 nUF(vcgtq
, vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
15991 nUF(vclt
, vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
15992 nUF(vcltq
, vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
15993 nUF(vcle
, vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
15994 nUF(vcleq
, vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
15995 /* Comparison. Type I8 I16 I32 F32. */
15996 nUF(vceq
, vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
15997 nUF(vceqq
, vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
15998 /* As above, D registers only. */
15999 nUF(vpmax
, vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
16000 nUF(vpmin
, vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
16001 /* Int and float variants, signedness unimportant. */
16002 nUF(vmlaq
, vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
16003 nUF(vmlsq
, vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
16004 nUF(vpadd
, vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
16005 /* Add/sub take types I8 I16 I32 I64 F32. */
16006 nUF(vaddq
, vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
16007 nUF(vsubq
, vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
16008 /* vtst takes sizes 8, 16, 32. */
16009 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
16010 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
16011 /* VMUL takes I8 I16 I32 F32 P8. */
16012 nUF(vmulq
, vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
16013 /* VQD{R}MULH takes S16 S32. */
16014 nUF(vqdmulh
, vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
16015 nUF(vqdmulhq
, vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
16016 nUF(vqrdmulh
, vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
16017 nUF(vqrdmulhq
, vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
16018 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
16019 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
16020 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
16021 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
16022 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
16023 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
16024 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
16025 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
16026 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
16027 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
16028 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
16029 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
16031 /* Two address, int/float. Types S8 S16 S32 F32. */
16032 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
16033 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
16035 /* Data processing with two registers and a shift amount. */
16036 /* Right shifts, and variants with rounding.
16037 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
16038 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
16039 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
16040 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
16041 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
16042 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
16043 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
16044 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
16045 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
16046 /* Shift and insert. Sizes accepted 8 16 32 64. */
16047 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
16048 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
16049 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
16050 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
16051 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
16052 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
16053 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
16054 /* Right shift immediate, saturating & narrowing, with rounding variants.
16055 Types accepted S16 S32 S64 U16 U32 U64. */
16056 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
16057 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
16058 /* As above, unsigned. Types accepted S16 S32 S64. */
16059 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
16060 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
16061 /* Right shift narrowing. Types accepted I16 I32 I64. */
16062 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
16063 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
16064 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
16065 nUF(vshll
, vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
16066 /* CVT with optional immediate for fixed-point variant. */
16067 nUF(vcvtq
, vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
16069 nUF(vmvn
, vmvn
, 2, (RNDQ
, RNDQ_IMVNb
), neon_mvn
),
16070 nUF(vmvnq
, vmvn
, 2, (RNQ
, RNDQ_IMVNb
), neon_mvn
),
16072 /* Data processing, three registers of different lengths. */
16073 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
16074 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
16075 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16076 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16077 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16078 /* If not scalar, fall back to neon_dyadic_long.
16079 Vector types as above, scalar types S16 S32 U16 U32. */
16080 nUF(vmlal
, vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
16081 nUF(vmlsl
, vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
16082 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
16083 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
16084 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
16085 /* Dyadic, narrowing insns. Types I16 I32 I64. */
16086 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16087 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16088 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16089 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16090 /* Saturating doubling multiplies. Types S16 S32. */
16091 nUF(vqdmlal
, vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16092 nUF(vqdmlsl
, vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16093 nUF(vqdmull
, vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16094 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
16095 S16 S32 U16 U32. */
16096 nUF(vmull
, vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
16098 /* Extract. Size 8. */
16099 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
16100 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
16102 /* Two registers, miscellaneous. */
16103 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
16104 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
16105 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
16106 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
16107 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
16108 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
16109 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
16110 /* Vector replicate. Sizes 8 16 32. */
16111 nCE(vdup
, vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
16112 nCE(vdupq
, vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
16113 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
16114 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
16115 /* VMOVN. Types I16 I32 I64. */
16116 nUF(vmovn
, vmovn
, 2, (RND
, RNQ
), neon_movn
),
16117 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
16118 nUF(vqmovn
, vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
16119 /* VQMOVUN. Types S16 S32 S64. */
16120 nUF(vqmovun
, vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
16121 /* VZIP / VUZP. Sizes 8 16 32. */
16122 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
16123 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
16124 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
16125 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
16126 /* VQABS / VQNEG. Types S8 S16 S32. */
16127 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
16128 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
16129 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
16130 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
16131 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
16132 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
16133 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
16134 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
16135 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
16136 /* Reciprocal estimates. Types U32 F32. */
16137 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
16138 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
16139 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
16140 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
16141 /* VCLS. Types S8 S16 S32. */
16142 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
16143 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
16144 /* VCLZ. Types I8 I16 I32. */
16145 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
16146 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
16147 /* VCNT. Size 8. */
16148 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
16149 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
16150 /* Two address, untyped. */
16151 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
16152 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
16153 /* VTRN. Sizes 8 16 32. */
16154 nUF(vtrn
, vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
16155 nUF(vtrnq
, vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
16157 /* Table lookup. Size 8. */
16158 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
16159 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
16161 #undef THUMB_VARIANT
16162 #define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
16164 #define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
16165 /* Neon element/structure load/store. */
16166 nUF(vld1
, vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16167 nUF(vst1
, vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16168 nUF(vld2
, vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16169 nUF(vst2
, vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16170 nUF(vld3
, vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16171 nUF(vst3
, vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16172 nUF(vld4
, vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16173 nUF(vst4
, vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16175 #undef THUMB_VARIANT
16176 #define THUMB_VARIANT &fpu_vfp_ext_v3
16178 #define ARM_VARIANT &fpu_vfp_ext_v3
16179 cCE(fconsts
, eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
16180 cCE(fconstd
, eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
16181 cCE(fshtos
, eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16182 cCE(fshtod
, eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16183 cCE(fsltos
, eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16184 cCE(fsltod
, eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16185 cCE(fuhtos
, ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16186 cCE(fuhtod
, ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16187 cCE(fultos
, ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16188 cCE(fultod
, ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16189 cCE(ftoshs
, ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16190 cCE(ftoshd
, ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16191 cCE(ftosls
, ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16192 cCE(ftosld
, ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16193 cCE(ftouhs
, ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16194 cCE(ftouhd
, ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16195 cCE(ftouls
, ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16196 cCE(ftould
, ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16198 #undef THUMB_VARIANT
16200 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
16201 cCE(mia
, e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16202 cCE(miaph
, e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16203 cCE(miabb
, e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16204 cCE(miabt
, e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16205 cCE(miatb
, e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16206 cCE(miatt
, e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16207 cCE(mar
, c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
16208 cCE(mra
, c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
16211 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
16212 cCE(tandcb
, e13f130
, 1, (RR
), iwmmxt_tandorc
),
16213 cCE(tandch
, e53f130
, 1, (RR
), iwmmxt_tandorc
),
16214 cCE(tandcw
, e93f130
, 1, (RR
), iwmmxt_tandorc
),
16215 cCE(tbcstb
, e400010
, 2, (RIWR
, RR
), rn_rd
),
16216 cCE(tbcsth
, e400050
, 2, (RIWR
, RR
), rn_rd
),
16217 cCE(tbcstw
, e400090
, 2, (RIWR
, RR
), rn_rd
),
16218 cCE(textrcb
, e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
16219 cCE(textrch
, e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
16220 cCE(textrcw
, e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
16221 cCE(textrmub
, e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16222 cCE(textrmuh
, e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16223 cCE(textrmuw
, e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16224 cCE(textrmsb
, e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16225 cCE(textrmsh
, e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16226 cCE(textrmsw
, e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16227 cCE(tinsrb
, e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16228 cCE(tinsrh
, e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16229 cCE(tinsrw
, e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16230 cCE(tmcr
, e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
16231 cCE(tmcrr
, c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
16232 cCE(tmia
, e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16233 cCE(tmiaph
, e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16234 cCE(tmiabb
, e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16235 cCE(tmiabt
, e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16236 cCE(tmiatb
, e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16237 cCE(tmiatt
, e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16238 cCE(tmovmskb
, e100030
, 2, (RR
, RIWR
), rd_rn
),
16239 cCE(tmovmskh
, e500030
, 2, (RR
, RIWR
), rd_rn
),
16240 cCE(tmovmskw
, e900030
, 2, (RR
, RIWR
), rd_rn
),
16241 cCE(tmrc
, e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
16242 cCE(tmrrc
, c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
16243 cCE(torcb
, e13f150
, 1, (RR
), iwmmxt_tandorc
),
16244 cCE(torch
, e53f150
, 1, (RR
), iwmmxt_tandorc
),
16245 cCE(torcw
, e93f150
, 1, (RR
), iwmmxt_tandorc
),
16246 cCE(waccb
, e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16247 cCE(wacch
, e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16248 cCE(waccw
, e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16249 cCE(waddbss
, e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16250 cCE(waddb
, e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16251 cCE(waddbus
, e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16252 cCE(waddhss
, e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16253 cCE(waddh
, e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16254 cCE(waddhus
, e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16255 cCE(waddwss
, eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16256 cCE(waddw
, e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16257 cCE(waddwus
, e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16258 cCE(waligni
, e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
16259 cCE(walignr0
, e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16260 cCE(walignr1
, e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16261 cCE(walignr2
, ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16262 cCE(walignr3
, eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16263 cCE(wand
, e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16264 cCE(wandn
, e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16265 cCE(wavg2b
, e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16266 cCE(wavg2br
, e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16267 cCE(wavg2h
, ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16268 cCE(wavg2hr
, ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16269 cCE(wcmpeqb
, e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16270 cCE(wcmpeqh
, e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16271 cCE(wcmpeqw
, e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16272 cCE(wcmpgtub
, e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16273 cCE(wcmpgtuh
, e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16274 cCE(wcmpgtuw
, e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16275 cCE(wcmpgtsb
, e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16276 cCE(wcmpgtsh
, e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16277 cCE(wcmpgtsw
, eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16278 cCE(wldrb
, c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16279 cCE(wldrh
, c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16280 cCE(wldrw
, c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
16281 cCE(wldrd
, c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
16282 cCE(wmacs
, e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16283 cCE(wmacsz
, e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16284 cCE(wmacu
, e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16285 cCE(wmacuz
, e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16286 cCE(wmadds
, ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16287 cCE(wmaddu
, e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16288 cCE(wmaxsb
, e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16289 cCE(wmaxsh
, e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16290 cCE(wmaxsw
, ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16291 cCE(wmaxub
, e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16292 cCE(wmaxuh
, e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16293 cCE(wmaxuw
, e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16294 cCE(wminsb
, e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16295 cCE(wminsh
, e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16296 cCE(wminsw
, eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16297 cCE(wminub
, e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16298 cCE(wminuh
, e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16299 cCE(wminuw
, e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16300 cCE(wmov
, e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
16301 cCE(wmulsm
, e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16302 cCE(wmulsl
, e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16303 cCE(wmulum
, e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16304 cCE(wmulul
, e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16305 cCE(wor
, e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16306 cCE(wpackhss
, e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16307 cCE(wpackhus
, e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16308 cCE(wpackwss
, eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16309 cCE(wpackwus
, e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16310 cCE(wpackdss
, ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16311 cCE(wpackdus
, ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16312 cCE(wrorh
, e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16313 cCE(wrorhg
, e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16314 cCE(wrorw
, eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16315 cCE(wrorwg
, eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16316 cCE(wrord
, ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16317 cCE(wrordg
, ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16318 cCE(wsadb
, e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16319 cCE(wsadbz
, e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16320 cCE(wsadh
, e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16321 cCE(wsadhz
, e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16322 cCE(wshufh
, e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
16323 cCE(wsllh
, e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16324 cCE(wsllhg
, e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16325 cCE(wsllw
, e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16326 cCE(wsllwg
, e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16327 cCE(wslld
, ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16328 cCE(wslldg
, ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16329 cCE(wsrah
, e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16330 cCE(wsrahg
, e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16331 cCE(wsraw
, e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16332 cCE(wsrawg
, e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16333 cCE(wsrad
, ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16334 cCE(wsradg
, ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16335 cCE(wsrlh
, e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16336 cCE(wsrlhg
, e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16337 cCE(wsrlw
, ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16338 cCE(wsrlwg
, ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16339 cCE(wsrld
, ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16340 cCE(wsrldg
, ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16341 cCE(wstrb
, c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16342 cCE(wstrh
, c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16343 cCE(wstrw
, c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
16344 cCE(wstrd
, c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
16345 cCE(wsubbss
, e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16346 cCE(wsubb
, e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16347 cCE(wsubbus
, e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16348 cCE(wsubhss
, e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16349 cCE(wsubh
, e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16350 cCE(wsubhus
, e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16351 cCE(wsubwss
, eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16352 cCE(wsubw
, e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16353 cCE(wsubwus
, e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16354 cCE(wunpckehub
,e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16355 cCE(wunpckehuh
,e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16356 cCE(wunpckehuw
,e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16357 cCE(wunpckehsb
,e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16358 cCE(wunpckehsh
,e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16359 cCE(wunpckehsw
,ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16360 cCE(wunpckihb
, e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16361 cCE(wunpckihh
, e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16362 cCE(wunpckihw
, e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16363 cCE(wunpckelub
,e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16364 cCE(wunpckeluh
,e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16365 cCE(wunpckeluw
,e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16366 cCE(wunpckelsb
,e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16367 cCE(wunpckelsh
,e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16368 cCE(wunpckelsw
,ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16369 cCE(wunpckilb
, e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16370 cCE(wunpckilh
, e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16371 cCE(wunpckilw
, e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16372 cCE(wxor
, e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16373 cCE(wzero
, e300000
, 1, (RIWR
), iwmmxt_wzero
),
16376 #define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
16377 cCE(torvscb
, e13f190
, 1, (RR
), iwmmxt_tandorc
),
16378 cCE(torvsch
, e53f190
, 1, (RR
), iwmmxt_tandorc
),
16379 cCE(torvscw
, e93f190
, 1, (RR
), iwmmxt_tandorc
),
16380 cCE(wabsb
, e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16381 cCE(wabsh
, e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16382 cCE(wabsw
, ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16383 cCE(wabsdiffb
, e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16384 cCE(wabsdiffh
, e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16385 cCE(wabsdiffw
, e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16386 cCE(waddbhusl
, e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16387 cCE(waddbhusm
, e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16388 cCE(waddhc
, e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16389 cCE(waddwc
, ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16390 cCE(waddsubhx
, ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16391 cCE(wavg4
, e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16392 cCE(wavg4r
, e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16393 cCE(wmaddsn
, ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16394 cCE(wmaddsx
, eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16395 cCE(wmaddun
, ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16396 cCE(wmaddux
, e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16397 cCE(wmerge
, e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
16398 cCE(wmiabb
, e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16399 cCE(wmiabt
, e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16400 cCE(wmiatb
, e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16401 cCE(wmiatt
, e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16402 cCE(wmiabbn
, e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16403 cCE(wmiabtn
, e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16404 cCE(wmiatbn
, e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16405 cCE(wmiattn
, e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16406 cCE(wmiawbb
, e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16407 cCE(wmiawbt
, e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16408 cCE(wmiawtb
, ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16409 cCE(wmiawtt
, eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16410 cCE(wmiawbbn
, ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16411 cCE(wmiawbtn
, ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16412 cCE(wmiawtbn
, ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16413 cCE(wmiawttn
, ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16414 cCE(wmulsmr
, ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16415 cCE(wmulumr
, ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16416 cCE(wmulwumr
, ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16417 cCE(wmulwsmr
, ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16418 cCE(wmulwum
, ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16419 cCE(wmulwsm
, ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16420 cCE(wmulwl
, eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16421 cCE(wqmiabb
, e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16422 cCE(wqmiabt
, e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16423 cCE(wqmiatb
, ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16424 cCE(wqmiatt
, eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16425 cCE(wqmiabbn
, ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16426 cCE(wqmiabtn
, ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16427 cCE(wqmiatbn
, ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16428 cCE(wqmiattn
, ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16429 cCE(wqmulm
, e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16430 cCE(wqmulmr
, e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16431 cCE(wqmulwm
, ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16432 cCE(wqmulwmr
, ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16433 cCE(wsubaddhx
, ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16436 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
16437 cCE(cfldrs
, c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
16438 cCE(cfldrd
, c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
16439 cCE(cfldr32
, c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
16440 cCE(cfldr64
, c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
16441 cCE(cfstrs
, c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
16442 cCE(cfstrd
, c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
16443 cCE(cfstr32
, c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
16444 cCE(cfstr64
, c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
16445 cCE(cfmvsr
, e000450
, 2, (RMF
, RR
), rn_rd
),
16446 cCE(cfmvrs
, e100450
, 2, (RR
, RMF
), rd_rn
),
16447 cCE(cfmvdlr
, e000410
, 2, (RMD
, RR
), rn_rd
),
16448 cCE(cfmvrdl
, e100410
, 2, (RR
, RMD
), rd_rn
),
16449 cCE(cfmvdhr
, e000430
, 2, (RMD
, RR
), rn_rd
),
16450 cCE(cfmvrdh
, e100430
, 2, (RR
, RMD
), rd_rn
),
16451 cCE(cfmv64lr
, e000510
, 2, (RMDX
, RR
), rn_rd
),
16452 cCE(cfmvr64l
, e100510
, 2, (RR
, RMDX
), rd_rn
),
16453 cCE(cfmv64hr
, e000530
, 2, (RMDX
, RR
), rn_rd
),
16454 cCE(cfmvr64h
, e100530
, 2, (RR
, RMDX
), rd_rn
),
16455 cCE(cfmval32
, e200440
, 2, (RMAX
, RMFX
), rd_rn
),
16456 cCE(cfmv32al
, e100440
, 2, (RMFX
, RMAX
), rd_rn
),
16457 cCE(cfmvam32
, e200460
, 2, (RMAX
, RMFX
), rd_rn
),
16458 cCE(cfmv32am
, e100460
, 2, (RMFX
, RMAX
), rd_rn
),
16459 cCE(cfmvah32
, e200480
, 2, (RMAX
, RMFX
), rd_rn
),
16460 cCE(cfmv32ah
, e100480
, 2, (RMFX
, RMAX
), rd_rn
),
16461 cCE(cfmva32
, e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
16462 cCE(cfmv32a
, e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
16463 cCE(cfmva64
, e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
16464 cCE(cfmv64a
, e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
16465 cCE(cfmvsc32
, e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
16466 cCE(cfmv32sc
, e1004e0
, 2, (RMDX
, RMDS
), rd
),
16467 cCE(cfcpys
, e000400
, 2, (RMF
, RMF
), rd_rn
),
16468 cCE(cfcpyd
, e000420
, 2, (RMD
, RMD
), rd_rn
),
16469 cCE(cfcvtsd
, e000460
, 2, (RMD
, RMF
), rd_rn
),
16470 cCE(cfcvtds
, e000440
, 2, (RMF
, RMD
), rd_rn
),
16471 cCE(cfcvt32s
, e000480
, 2, (RMF
, RMFX
), rd_rn
),
16472 cCE(cfcvt32d
, e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
16473 cCE(cfcvt64s
, e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
16474 cCE(cfcvt64d
, e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
16475 cCE(cfcvts32
, e100580
, 2, (RMFX
, RMF
), rd_rn
),
16476 cCE(cfcvtd32
, e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
16477 cCE(cftruncs32
,e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
16478 cCE(cftruncd32
,e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
16479 cCE(cfrshl32
, e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
16480 cCE(cfrshl64
, e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
16481 cCE(cfsh32
, e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
16482 cCE(cfsh64
, e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
16483 cCE(cfcmps
, e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
16484 cCE(cfcmpd
, e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
16485 cCE(cfcmp32
, e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
16486 cCE(cfcmp64
, e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
16487 cCE(cfabss
, e300400
, 2, (RMF
, RMF
), rd_rn
),
16488 cCE(cfabsd
, e300420
, 2, (RMD
, RMD
), rd_rn
),
16489 cCE(cfnegs
, e300440
, 2, (RMF
, RMF
), rd_rn
),
16490 cCE(cfnegd
, e300460
, 2, (RMD
, RMD
), rd_rn
),
16491 cCE(cfadds
, e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16492 cCE(cfaddd
, e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16493 cCE(cfsubs
, e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16494 cCE(cfsubd
, e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16495 cCE(cfmuls
, e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16496 cCE(cfmuld
, e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16497 cCE(cfabs32
, e300500
, 2, (RMFX
, RMFX
), rd_rn
),
16498 cCE(cfabs64
, e300520
, 2, (RMDX
, RMDX
), rd_rn
),
16499 cCE(cfneg32
, e300540
, 2, (RMFX
, RMFX
), rd_rn
),
16500 cCE(cfneg64
, e300560
, 2, (RMDX
, RMDX
), rd_rn
),
16501 cCE(cfadd32
, e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16502 cCE(cfadd64
, e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16503 cCE(cfsub32
, e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16504 cCE(cfsub64
, e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16505 cCE(cfmul32
, e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16506 cCE(cfmul64
, e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16507 cCE(cfmac32
, e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16508 cCE(cfmsc32
, e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16509 cCE(cfmadd32
, e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
16510 cCE(cfmsub32
, e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
16511 cCE(cfmadda32
, e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
16512 cCE(cfmsuba32
, e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
16515 #undef THUMB_VARIANT
16542 /* MD interface: bits in the object file. */
16544 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
16545 for use in the a.out file, and stores them in the array pointed to by buf.
16546 This knows about the endian-ness of the target machine and does
16547 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
16548 2 (short) and 4 (long) Floating numbers are put out as a series of
16549 LITTLENUMS (shorts, here at least). */
16552 md_number_to_chars (char * buf
, valueT val
, int n
)
16554 if (target_big_endian
)
16555 number_to_chars_bigendian (buf
, val
, n
);
16557 number_to_chars_littleendian (buf
, val
, n
);
16561 md_chars_to_number (char * buf
, int n
)
16564 unsigned char * where
= (unsigned char *) buf
;
16566 if (target_big_endian
)
16571 result
|= (*where
++ & 255);
16579 result
|= (where
[n
] & 255);
16586 /* MD interface: Sections. */
16588 /* Estimate the size of a frag before relaxing. Assume everything fits in
16592 md_estimate_size_before_relax (fragS
* fragp
,
16593 segT segtype ATTRIBUTE_UNUSED
)
16599 /* Convert a machine dependent frag. */
16602 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
16604 unsigned long insn
;
16605 unsigned long old_op
;
16613 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16615 old_op
= bfd_get_16(abfd
, buf
);
16616 if (fragp
->fr_symbol
) {
16617 exp
.X_op
= O_symbol
;
16618 exp
.X_add_symbol
= fragp
->fr_symbol
;
16620 exp
.X_op
= O_constant
;
16622 exp
.X_add_number
= fragp
->fr_offset
;
16623 opcode
= fragp
->fr_subtype
;
16626 case T_MNEM_ldr_pc
:
16627 case T_MNEM_ldr_pc2
:
16628 case T_MNEM_ldr_sp
:
16629 case T_MNEM_str_sp
:
16636 if (fragp
->fr_var
== 4)
16638 insn
= THUMB_OP32(opcode
);
16639 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
16641 insn
|= (old_op
& 0x700) << 4;
16645 insn
|= (old_op
& 7) << 12;
16646 insn
|= (old_op
& 0x38) << 13;
16648 insn
|= 0x00000c00;
16649 put_thumb32_insn (buf
, insn
);
16650 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
16654 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
16656 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
16659 if (fragp
->fr_var
== 4)
16661 insn
= THUMB_OP32 (opcode
);
16662 insn
|= (old_op
& 0xf0) << 4;
16663 put_thumb32_insn (buf
, insn
);
16664 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
16668 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16669 exp
.X_add_number
-= 4;
16677 if (fragp
->fr_var
== 4)
16679 int r0off
= (opcode
== T_MNEM_mov
16680 || opcode
== T_MNEM_movs
) ? 0 : 8;
16681 insn
= THUMB_OP32 (opcode
);
16682 insn
= (insn
& 0xe1ffffff) | 0x10000000;
16683 insn
|= (old_op
& 0x700) << r0off
;
16684 put_thumb32_insn (buf
, insn
);
16685 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16689 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
16694 if (fragp
->fr_var
== 4)
16696 insn
= THUMB_OP32(opcode
);
16697 put_thumb32_insn (buf
, insn
);
16698 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
16701 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
16705 if (fragp
->fr_var
== 4)
16707 insn
= THUMB_OP32(opcode
);
16708 insn
|= (old_op
& 0xf00) << 14;
16709 put_thumb32_insn (buf
, insn
);
16710 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
16713 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
16716 case T_MNEM_add_sp
:
16717 case T_MNEM_add_pc
:
16718 case T_MNEM_inc_sp
:
16719 case T_MNEM_dec_sp
:
16720 if (fragp
->fr_var
== 4)
16722 /* ??? Choose between add and addw. */
16723 insn
= THUMB_OP32 (opcode
);
16724 insn
|= (old_op
& 0xf0) << 4;
16725 put_thumb32_insn (buf
, insn
);
16726 if (opcode
== T_MNEM_add_pc
)
16727 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
16729 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16732 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16740 if (fragp
->fr_var
== 4)
16742 insn
= THUMB_OP32 (opcode
);
16743 insn
|= (old_op
& 0xf0) << 4;
16744 insn
|= (old_op
& 0xf) << 16;
16745 put_thumb32_insn (buf
, insn
);
16746 if (insn
& (1 << 20))
16747 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16749 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16752 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16758 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
16760 fixp
->fx_file
= fragp
->fr_file
;
16761 fixp
->fx_line
= fragp
->fr_line
;
16762 fragp
->fr_fix
+= fragp
->fr_var
;
16765 /* Return the size of a relaxable immediate operand instruction.
16766 SHIFT and SIZE specify the form of the allowable immediate. */
16768 relax_immediate (fragS
*fragp
, int size
, int shift
)
16774 /* ??? Should be able to do better than this. */
16775 if (fragp
->fr_symbol
)
16778 low
= (1 << shift
) - 1;
16779 mask
= (1 << (shift
+ size
)) - (1 << shift
);
16780 offset
= fragp
->fr_offset
;
16781 /* Force misaligned offsets to 32-bit variant. */
16784 if (offset
& ~mask
)
16789 /* Get the address of a symbol during relaxation. */
16791 relaxed_symbol_addr(fragS
*fragp
, long stretch
)
16797 sym
= fragp
->fr_symbol
;
16798 sym_frag
= symbol_get_frag (sym
);
16799 know (S_GET_SEGMENT (sym
) != absolute_section
16800 || sym_frag
== &zero_address_frag
);
16801 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
16803 /* If frag has yet to be reached on this pass, assume it will
16804 move by STRETCH just as we did. If this is not so, it will
16805 be because some frag between grows, and that will force
16809 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
16815 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
16818 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
16823 /* Assume worst case for symbols not known to be in the same section. */
16824 if (!S_IS_DEFINED(fragp
->fr_symbol
)
16825 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16828 val
= relaxed_symbol_addr(fragp
, stretch
);
16829 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16830 addr
= (addr
+ 4) & ~3;
16831 /* Force misaligned targets to 32-bit variant. */
16835 if (val
< 0 || val
> 1020)
16840 /* Return the size of a relaxable add/sub immediate instruction. */
16842 relax_addsub (fragS
*fragp
, asection
*sec
)
16847 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16848 op
= bfd_get_16(sec
->owner
, buf
);
16849 if ((op
& 0xf) == ((op
>> 4) & 0xf))
16850 return relax_immediate (fragp
, 8, 0);
16852 return relax_immediate (fragp
, 3, 0);
16856 /* Return the size of a relaxable branch instruction. BITS is the
16857 size of the offset field in the narrow instruction. */
16860 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
16866 /* Assume worst case for symbols not known to be in the same section. */
16867 if (!S_IS_DEFINED(fragp
->fr_symbol
)
16868 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16871 val
= relaxed_symbol_addr(fragp
, stretch
);
16872 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16875 /* Offset is a signed value *2 */
16877 if (val
>= limit
|| val
< -limit
)
16883 /* Relax a machine dependent frag. This returns the amount by which
16884 the current size of the frag should change. */
16887 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
16892 oldsize
= fragp
->fr_var
;
16893 switch (fragp
->fr_subtype
)
16895 case T_MNEM_ldr_pc2
:
16896 newsize
= relax_adr(fragp
, sec
, stretch
);
16898 case T_MNEM_ldr_pc
:
16899 case T_MNEM_ldr_sp
:
16900 case T_MNEM_str_sp
:
16901 newsize
= relax_immediate(fragp
, 8, 2);
16905 newsize
= relax_immediate(fragp
, 5, 2);
16909 newsize
= relax_immediate(fragp
, 5, 1);
16913 newsize
= relax_immediate(fragp
, 5, 0);
16916 newsize
= relax_adr(fragp
, sec
, stretch
);
16922 newsize
= relax_immediate(fragp
, 8, 0);
16925 newsize
= relax_branch(fragp
, sec
, 11, stretch
);
16928 newsize
= relax_branch(fragp
, sec
, 8, stretch
);
16930 case T_MNEM_add_sp
:
16931 case T_MNEM_add_pc
:
16932 newsize
= relax_immediate (fragp
, 8, 2);
16934 case T_MNEM_inc_sp
:
16935 case T_MNEM_dec_sp
:
16936 newsize
= relax_immediate (fragp
, 7, 2);
16942 newsize
= relax_addsub (fragp
, sec
);
16948 fragp
->fr_var
= newsize
;
16949 /* Freeze wide instructions that are at or before the same location as
16950 in the previous pass. This avoids infinite loops.
16951 Don't freeze them unconditionally because targets may be artificialy
16952 misaligned by the expansion of preceeding frags. */
16953 if (stretch
<= 0 && newsize
> 2)
16955 md_convert_frag (sec
->owner
, sec
, fragp
);
16959 return newsize
- oldsize
;
16962 /* Round up a section size to the appropriate boundary. */
16965 md_section_align (segT segment ATTRIBUTE_UNUSED
,
16968 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
16969 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
16971 /* For a.out, force the section size to be aligned. If we don't do
16972 this, BFD will align it for us, but it will not write out the
16973 final bytes of the section. This may be a bug in BFD, but it is
16974 easier to fix it here since that is how the other a.out targets
16978 align
= bfd_get_section_alignment (stdoutput
, segment
);
16979 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
16986 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
16987 of an rs_align_code fragment. */
16990 arm_handle_align (fragS
* fragP
)
16992 static char const arm_noop
[4] = { 0x00, 0x00, 0xa0, 0xe1 };
16993 static char const thumb_noop
[2] = { 0xc0, 0x46 };
16994 static char const arm_bigend_noop
[4] = { 0xe1, 0xa0, 0x00, 0x00 };
16995 static char const thumb_bigend_noop
[2] = { 0x46, 0xc0 };
16997 int bytes
, fix
, noop_size
;
17001 if (fragP
->fr_type
!= rs_align_code
)
17004 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
17005 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
17008 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
17009 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
17011 if (fragP
->tc_frag_data
)
17013 if (target_big_endian
)
17014 noop
= thumb_bigend_noop
;
17017 noop_size
= sizeof (thumb_noop
);
17021 if (target_big_endian
)
17022 noop
= arm_bigend_noop
;
17025 noop_size
= sizeof (arm_noop
);
17028 if (bytes
& (noop_size
- 1))
17030 fix
= bytes
& (noop_size
- 1);
17031 memset (p
, 0, fix
);
17036 while (bytes
>= noop_size
)
17038 memcpy (p
, noop
, noop_size
);
17040 bytes
-= noop_size
;
17044 fragP
->fr_fix
+= fix
;
17045 fragP
->fr_var
= noop_size
;
17048 /* Called from md_do_align. Used to create an alignment
17049 frag in a code section. */
17052 arm_frag_align_code (int n
, int max
)
17056 /* We assume that there will never be a requirement
17057 to support alignments greater than 32 bytes. */
17058 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
17059 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
17061 p
= frag_var (rs_align_code
,
17062 MAX_MEM_FOR_RS_ALIGN_CODE
,
17064 (relax_substateT
) max
,
17071 /* Perform target specific initialisation of a frag. */
17074 arm_init_frag (fragS
* fragP
)
17076 /* Record whether this frag is in an ARM or a THUMB area. */
17077 fragP
->tc_frag_data
= thumb_mode
;
17081 /* When we change sections we need to issue a new mapping symbol. */
17084 arm_elf_change_section (void)
17087 segment_info_type
*seginfo
;
17089 /* Link an unlinked unwind index table section to the .text section. */
17090 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
17091 && elf_linked_to_section (now_seg
) == NULL
)
17092 elf_linked_to_section (now_seg
) = text_section
;
17094 if (!SEG_NORMAL (now_seg
))
17097 flags
= bfd_get_section_flags (stdoutput
, now_seg
);
17099 /* We can ignore sections that only contain debug info. */
17100 if ((flags
& SEC_ALLOC
) == 0)
17103 seginfo
= seg_info (now_seg
);
17104 mapstate
= seginfo
->tc_segment_info_data
.mapstate
;
17105 marked_pr_dependency
= seginfo
->tc_segment_info_data
.marked_pr_dependency
;
17109 arm_elf_section_type (const char * str
, size_t len
)
17111 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
17112 return SHT_ARM_EXIDX
;
17117 /* Code to deal with unwinding tables. */
17119 static void add_unwind_adjustsp (offsetT
);
17121 /* Cenerate and deferred unwind frame offset. */
17124 flush_pending_unwind (void)
17128 offset
= unwind
.pending_offset
;
17129 unwind
.pending_offset
= 0;
17131 add_unwind_adjustsp (offset
);
17134 /* Add an opcode to this list for this function. Two-byte opcodes should
17135 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
17139 add_unwind_opcode (valueT op
, int length
)
17141 /* Add any deferred stack adjustment. */
17142 if (unwind
.pending_offset
)
17143 flush_pending_unwind ();
17145 unwind
.sp_restored
= 0;
17147 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
17149 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
17150 if (unwind
.opcodes
)
17151 unwind
.opcodes
= xrealloc (unwind
.opcodes
,
17152 unwind
.opcode_alloc
);
17154 unwind
.opcodes
= xmalloc (unwind
.opcode_alloc
);
17159 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
17161 unwind
.opcode_count
++;
17165 /* Add unwind opcodes to adjust the stack pointer. */
17168 add_unwind_adjustsp (offsetT offset
)
17172 if (offset
> 0x200)
17174 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
17179 /* Long form: 0xb2, uleb128. */
17180 /* This might not fit in a word so add the individual bytes,
17181 remembering the list is built in reverse order. */
17182 o
= (valueT
) ((offset
- 0x204) >> 2);
17184 add_unwind_opcode (0, 1);
17186 /* Calculate the uleb128 encoding of the offset. */
17190 bytes
[n
] = o
& 0x7f;
17196 /* Add the insn. */
17198 add_unwind_opcode (bytes
[n
- 1], 1);
17199 add_unwind_opcode (0xb2, 1);
17201 else if (offset
> 0x100)
17203 /* Two short opcodes. */
17204 add_unwind_opcode (0x3f, 1);
17205 op
= (offset
- 0x104) >> 2;
17206 add_unwind_opcode (op
, 1);
17208 else if (offset
> 0)
17210 /* Short opcode. */
17211 op
= (offset
- 4) >> 2;
17212 add_unwind_opcode (op
, 1);
17214 else if (offset
< 0)
17217 while (offset
> 0x100)
17219 add_unwind_opcode (0x7f, 1);
17222 op
= ((offset
- 4) >> 2) | 0x40;
17223 add_unwind_opcode (op
, 1);
17227 /* Finish the list of unwind opcodes for this function. */
17229 finish_unwind_opcodes (void)
17233 if (unwind
.fp_used
)
17235 /* Adjust sp as necessary. */
17236 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
17237 flush_pending_unwind ();
17239 /* After restoring sp from the frame pointer. */
17240 op
= 0x90 | unwind
.fp_reg
;
17241 add_unwind_opcode (op
, 1);
17244 flush_pending_unwind ();
17248 /* Start an exception table entry. If idx is nonzero this is an index table
17252 start_unwind_section (const segT text_seg
, int idx
)
17254 const char * text_name
;
17255 const char * prefix
;
17256 const char * prefix_once
;
17257 const char * group_name
;
17261 size_t sec_name_len
;
17268 prefix
= ELF_STRING_ARM_unwind
;
17269 prefix_once
= ELF_STRING_ARM_unwind_once
;
17270 type
= SHT_ARM_EXIDX
;
17274 prefix
= ELF_STRING_ARM_unwind_info
;
17275 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
17276 type
= SHT_PROGBITS
;
17279 text_name
= segment_name (text_seg
);
17280 if (streq (text_name
, ".text"))
17283 if (strncmp (text_name
, ".gnu.linkonce.t.",
17284 strlen (".gnu.linkonce.t.")) == 0)
17286 prefix
= prefix_once
;
17287 text_name
+= strlen (".gnu.linkonce.t.");
17290 prefix_len
= strlen (prefix
);
17291 text_len
= strlen (text_name
);
17292 sec_name_len
= prefix_len
+ text_len
;
17293 sec_name
= xmalloc (sec_name_len
+ 1);
17294 memcpy (sec_name
, prefix
, prefix_len
);
17295 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
17296 sec_name
[prefix_len
+ text_len
] = '\0';
17302 /* Handle COMDAT group. */
17303 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
17305 group_name
= elf_group_name (text_seg
);
17306 if (group_name
== NULL
)
17308 as_bad ("Group section `%s' has no group signature",
17309 segment_name (text_seg
));
17310 ignore_rest_of_line ();
17313 flags
|= SHF_GROUP
;
17317 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
17319 /* Set the setion link for index tables. */
17321 elf_linked_to_section (now_seg
) = text_seg
;
17325 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
17326 personality routine data. Returns zero, or the index table value for
17327 and inline entry. */
17330 create_unwind_entry (int have_data
)
17335 /* The current word of data. */
17337 /* The number of bytes left in this word. */
17340 finish_unwind_opcodes ();
17342 /* Remember the current text section. */
17343 unwind
.saved_seg
= now_seg
;
17344 unwind
.saved_subseg
= now_subseg
;
17346 start_unwind_section (now_seg
, 0);
17348 if (unwind
.personality_routine
== NULL
)
17350 if (unwind
.personality_index
== -2)
17353 as_bad (_("handerdata in cantunwind frame"));
17354 return 1; /* EXIDX_CANTUNWIND. */
17357 /* Use a default personality routine if none is specified. */
17358 if (unwind
.personality_index
== -1)
17360 if (unwind
.opcode_count
> 3)
17361 unwind
.personality_index
= 1;
17363 unwind
.personality_index
= 0;
17366 /* Space for the personality routine entry. */
17367 if (unwind
.personality_index
== 0)
17369 if (unwind
.opcode_count
> 3)
17370 as_bad (_("too many unwind opcodes for personality routine 0"));
17374 /* All the data is inline in the index table. */
17377 while (unwind
.opcode_count
> 0)
17379 unwind
.opcode_count
--;
17380 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
17384 /* Pad with "finish" opcodes. */
17386 data
= (data
<< 8) | 0xb0;
17393 /* We get two opcodes "free" in the first word. */
17394 size
= unwind
.opcode_count
- 2;
17397 /* An extra byte is required for the opcode count. */
17398 size
= unwind
.opcode_count
+ 1;
17400 size
= (size
+ 3) >> 2;
17402 as_bad (_("too many unwind opcodes"));
17404 frag_align (2, 0, 0);
17405 record_alignment (now_seg
, 2);
17406 unwind
.table_entry
= expr_build_dot ();
17408 /* Allocate the table entry. */
17409 ptr
= frag_more ((size
<< 2) + 4);
17410 where
= frag_now_fix () - ((size
<< 2) + 4);
17412 switch (unwind
.personality_index
)
17415 /* ??? Should this be a PLT generating relocation? */
17416 /* Custom personality routine. */
17417 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
17418 BFD_RELOC_ARM_PREL31
);
17423 /* Set the first byte to the number of additional words. */
17428 /* ABI defined personality routines. */
17430 /* Three opcodes bytes are packed into the first word. */
17437 /* The size and first two opcode bytes go in the first word. */
17438 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
17443 /* Should never happen. */
17447 /* Pack the opcodes into words (MSB first), reversing the list at the same
17449 while (unwind
.opcode_count
> 0)
17453 md_number_to_chars (ptr
, data
, 4);
17458 unwind
.opcode_count
--;
17460 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
17463 /* Finish off the last word. */
17466 /* Pad with "finish" opcodes. */
17468 data
= (data
<< 8) | 0xb0;
17470 md_number_to_chars (ptr
, data
, 4);
17475 /* Add an empty descriptor if there is no user-specified data. */
17476 ptr
= frag_more (4);
17477 md_number_to_chars (ptr
, 0, 4);
17484 /* Initialize the DWARF-2 unwind information for this procedure. */
17487 tc_arm_frame_initial_instructions (void)
17489 cfi_add_CFA_def_cfa (REG_SP
, 0);
17491 #endif /* OBJ_ELF */
17493 /* Convert REGNAME to a DWARF-2 register number. */
17496 tc_arm_regname_to_dw2regnum (char *regname
)
17498 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
17508 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
17512 expr
.X_op
= O_secrel
;
17513 expr
.X_add_symbol
= symbol
;
17514 expr
.X_add_number
= 0;
17515 emit_expr (&expr
, size
);
17519 /* MD interface: Symbol and relocation handling. */
17521 /* Return the address within the segment that a PC-relative fixup is
17522 relative to. For ARM, PC-relative fixups applied to instructions
17523 are generally relative to the location of the fixup plus 8 bytes.
17524 Thumb branches are offset by 4, and Thumb loads relative to PC
17525 require special handling. */
17528 md_pcrel_from_section (fixS
* fixP
, segT seg
)
17530 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
17532 /* If this is pc-relative and we are going to emit a relocation
17533 then we just want to put out any pipeline compensation that the linker
17534 will need. Otherwise we want to use the calculated base.
17535 For WinCE we skip the bias for externals as well, since this
17536 is how the MS ARM-CE assembler behaves and we want to be compatible. */
17538 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
17539 || (arm_force_relocation (fixP
)
17541 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
17546 switch (fixP
->fx_r_type
)
17548 /* PC relative addressing on the Thumb is slightly odd as the
17549 bottom two bits of the PC are forced to zero for the
17550 calculation. This happens *after* application of the
17551 pipeline offset. However, Thumb adrl already adjusts for
17552 this, so we need not do it again. */
17553 case BFD_RELOC_ARM_THUMB_ADD
:
17556 case BFD_RELOC_ARM_THUMB_OFFSET
:
17557 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
17558 case BFD_RELOC_ARM_T32_ADD_PC12
:
17559 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
17560 return (base
+ 4) & ~3;
17562 /* Thumb branches are simply offset by +4. */
17563 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
17564 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
17565 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
17566 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
17567 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
17568 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
17569 case BFD_RELOC_THUMB_PCREL_BLX
:
17572 /* ARM mode branches are offset by +8. However, the Windows CE
17573 loader expects the relocation not to take this into account. */
17574 case BFD_RELOC_ARM_PCREL_BRANCH
:
17575 case BFD_RELOC_ARM_PCREL_CALL
:
17576 case BFD_RELOC_ARM_PCREL_JUMP
:
17577 case BFD_RELOC_ARM_PCREL_BLX
:
17578 case BFD_RELOC_ARM_PLT32
:
17580 /* When handling fixups immediately, because we have already
17581 discovered the value of a symbol, or the address of the frag involved
17582 we must account for the offset by +8, as the OS loader will never see the reloc.
17583 see fixup_segment() in write.c
17584 The S_IS_EXTERNAL test handles the case of global symbols.
17585 Those need the calculated base, not just the pipe compensation the linker will need. */
17587 && fixP
->fx_addsy
!= NULL
17588 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
17589 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
17596 /* ARM mode loads relative to PC are also offset by +8. Unlike
17597 branches, the Windows CE loader *does* expect the relocation
17598 to take this into account. */
17599 case BFD_RELOC_ARM_OFFSET_IMM
:
17600 case BFD_RELOC_ARM_OFFSET_IMM8
:
17601 case BFD_RELOC_ARM_HWLITERAL
:
17602 case BFD_RELOC_ARM_LITERAL
:
17603 case BFD_RELOC_ARM_CP_OFF_IMM
:
17607 /* Other PC-relative relocations are un-offset. */
17613 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
17614 Otherwise we have no need to default values of symbols. */
17617 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
17620 if (name
[0] == '_' && name
[1] == 'G'
17621 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
17625 if (symbol_find (name
))
17626 as_bad ("GOT already in the symbol table");
17628 GOT_symbol
= symbol_new (name
, undefined_section
,
17629 (valueT
) 0, & zero_address_frag
);
17639 /* Subroutine of md_apply_fix. Check to see if an immediate can be
17640 computed as two separate immediate values, added together. We
17641 already know that this value cannot be computed by just one ARM
17644 static unsigned int
17645 validate_immediate_twopart (unsigned int val
,
17646 unsigned int * highpart
)
17651 for (i
= 0; i
< 32; i
+= 2)
17652 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
17658 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
17660 else if (a
& 0xff0000)
17662 if (a
& 0xff000000)
17664 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
17668 assert (a
& 0xff000000);
17669 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
17672 return (a
& 0xff) | (i
<< 7);
17679 validate_offset_imm (unsigned int val
, int hwse
)
17681 if ((hwse
&& val
> 255) || val
> 4095)
17686 /* Subroutine of md_apply_fix. Do those data_ops which can take a
17687 negative immediate constant by altering the instruction. A bit of
17692 by inverting the second operand, and
17695 by negating the second operand. */
17698 negate_data_op (unsigned long * instruction
,
17699 unsigned long value
)
17702 unsigned long negated
, inverted
;
17704 negated
= encode_arm_immediate (-value
);
17705 inverted
= encode_arm_immediate (~value
);
17707 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
17710 /* First negates. */
17711 case OPCODE_SUB
: /* ADD <-> SUB */
17712 new_inst
= OPCODE_ADD
;
17717 new_inst
= OPCODE_SUB
;
17721 case OPCODE_CMP
: /* CMP <-> CMN */
17722 new_inst
= OPCODE_CMN
;
17727 new_inst
= OPCODE_CMP
;
17731 /* Now Inverted ops. */
17732 case OPCODE_MOV
: /* MOV <-> MVN */
17733 new_inst
= OPCODE_MVN
;
17738 new_inst
= OPCODE_MOV
;
17742 case OPCODE_AND
: /* AND <-> BIC */
17743 new_inst
= OPCODE_BIC
;
17748 new_inst
= OPCODE_AND
;
17752 case OPCODE_ADC
: /* ADC <-> SBC */
17753 new_inst
= OPCODE_SBC
;
17758 new_inst
= OPCODE_ADC
;
17762 /* We cannot do anything. */
17767 if (value
== (unsigned) FAIL
)
17770 *instruction
&= OPCODE_MASK
;
17771 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
17775 /* Like negate_data_op, but for Thumb-2. */
17777 static unsigned int
17778 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
17782 unsigned int negated
, inverted
;
17784 negated
= encode_thumb32_immediate (-value
);
17785 inverted
= encode_thumb32_immediate (~value
);
17787 rd
= (*instruction
>> 8) & 0xf;
17788 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
17791 /* ADD <-> SUB. Includes CMP <-> CMN. */
17792 case T2_OPCODE_SUB
:
17793 new_inst
= T2_OPCODE_ADD
;
17797 case T2_OPCODE_ADD
:
17798 new_inst
= T2_OPCODE_SUB
;
17802 /* ORR <-> ORN. Includes MOV <-> MVN. */
17803 case T2_OPCODE_ORR
:
17804 new_inst
= T2_OPCODE_ORN
;
17808 case T2_OPCODE_ORN
:
17809 new_inst
= T2_OPCODE_ORR
;
17813 /* AND <-> BIC. TST has no inverted equivalent. */
17814 case T2_OPCODE_AND
:
17815 new_inst
= T2_OPCODE_BIC
;
17822 case T2_OPCODE_BIC
:
17823 new_inst
= T2_OPCODE_AND
;
17828 case T2_OPCODE_ADC
:
17829 new_inst
= T2_OPCODE_SBC
;
17833 case T2_OPCODE_SBC
:
17834 new_inst
= T2_OPCODE_ADC
;
17838 /* We cannot do anything. */
17843 if (value
== (unsigned int)FAIL
)
17846 *instruction
&= T2_OPCODE_MASK
;
17847 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
17851 /* Read a 32-bit thumb instruction from buf. */
17852 static unsigned long
17853 get_thumb32_insn (char * buf
)
17855 unsigned long insn
;
17856 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
17857 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17863 /* We usually want to set the low bit on the address of thumb function
17864 symbols. In particular .word foo - . should have the low bit set.
17865 Generic code tries to fold the difference of two symbols to
17866 a constant. Prevent this and force a relocation when the first symbols
17867 is a thumb function. */
17869 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
17871 if (op
== O_subtract
17872 && l
->X_op
== O_symbol
17873 && r
->X_op
== O_symbol
17874 && THUMB_IS_FUNC (l
->X_add_symbol
))
17876 l
->X_op
= O_subtract
;
17877 l
->X_op_symbol
= r
->X_add_symbol
;
17878 l
->X_add_number
-= r
->X_add_number
;
17881 /* Process as normal. */
17886 md_apply_fix (fixS
* fixP
,
17890 offsetT value
= * valP
;
17892 unsigned int newimm
;
17893 unsigned long temp
;
17895 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
17897 assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
17899 /* Note whether this will delete the relocation. */
17901 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
17904 /* On a 64-bit host, silently truncate 'value' to 32 bits for
17905 consistency with the behavior on 32-bit hosts. Remember value
17907 value
&= 0xffffffff;
17908 value
^= 0x80000000;
17909 value
-= 0x80000000;
17912 fixP
->fx_addnumber
= value
;
17914 /* Same treatment for fixP->fx_offset. */
17915 fixP
->fx_offset
&= 0xffffffff;
17916 fixP
->fx_offset
^= 0x80000000;
17917 fixP
->fx_offset
-= 0x80000000;
17919 switch (fixP
->fx_r_type
)
17921 case BFD_RELOC_NONE
:
17922 /* This will need to go in the object file. */
17926 case BFD_RELOC_ARM_IMMEDIATE
:
17927 /* We claim that this fixup has been processed here,
17928 even if in fact we generate an error because we do
17929 not have a reloc for it, so tc_gen_reloc will reject it. */
17933 && ! S_IS_DEFINED (fixP
->fx_addsy
))
17935 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17936 _("undefined symbol %s used as an immediate value"),
17937 S_GET_NAME (fixP
->fx_addsy
));
17941 newimm
= encode_arm_immediate (value
);
17942 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17944 /* If the instruction will fail, see if we can fix things up by
17945 changing the opcode. */
17946 if (newimm
== (unsigned int) FAIL
17947 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
17949 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17950 _("invalid constant (%lx) after fixup"),
17951 (unsigned long) value
);
17955 newimm
|= (temp
& 0xfffff000);
17956 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
17959 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
17961 unsigned int highpart
= 0;
17962 unsigned int newinsn
= 0xe1a00000; /* nop. */
17964 newimm
= encode_arm_immediate (value
);
17965 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17967 /* If the instruction will fail, see if we can fix things up by
17968 changing the opcode. */
17969 if (newimm
== (unsigned int) FAIL
17970 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
17972 /* No ? OK - try using two ADD instructions to generate
17974 newimm
= validate_immediate_twopart (value
, & highpart
);
17976 /* Yes - then make sure that the second instruction is
17978 if (newimm
!= (unsigned int) FAIL
)
17980 /* Still No ? Try using a negated value. */
17981 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
17982 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
17983 /* Otherwise - give up. */
17986 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17987 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
17992 /* Replace the first operand in the 2nd instruction (which
17993 is the PC) with the destination register. We have
17994 already added in the PC in the first instruction and we
17995 do not want to do it again. */
17996 newinsn
&= ~ 0xf0000;
17997 newinsn
|= ((newinsn
& 0x0f000) << 4);
18000 newimm
|= (temp
& 0xfffff000);
18001 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
18003 highpart
|= (newinsn
& 0xfffff000);
18004 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
18008 case BFD_RELOC_ARM_OFFSET_IMM
:
18009 if (!fixP
->fx_done
&& seg
->use_rela_p
)
18012 case BFD_RELOC_ARM_LITERAL
:
18018 if (validate_offset_imm (value
, 0) == FAIL
)
18020 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
18021 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18022 _("invalid literal constant: pool needs to be closer"));
18024 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18025 _("bad immediate value for offset (%ld)"),
18030 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18031 newval
&= 0xff7ff000;
18032 newval
|= value
| (sign
? INDEX_UP
: 0);
18033 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18036 case BFD_RELOC_ARM_OFFSET_IMM8
:
18037 case BFD_RELOC_ARM_HWLITERAL
:
18043 if (validate_offset_imm (value
, 1) == FAIL
)
18045 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
18046 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18047 _("invalid literal constant: pool needs to be closer"));
18049 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
18054 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18055 newval
&= 0xff7ff0f0;
18056 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
18057 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18060 case BFD_RELOC_ARM_T32_OFFSET_U8
:
18061 if (value
< 0 || value
> 1020 || value
% 4 != 0)
18062 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18063 _("bad immediate value for offset (%ld)"), (long) value
);
18066 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
18068 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
18071 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
18072 /* This is a complicated relocation used for all varieties of Thumb32
18073 load/store instruction with immediate offset:
18075 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
18076 *4, optional writeback(W)
18077 (doubleword load/store)
18079 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
18080 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
18081 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
18082 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
18083 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
18085 Uppercase letters indicate bits that are already encoded at
18086 this point. Lowercase letters are our problem. For the
18087 second block of instructions, the secondary opcode nybble
18088 (bits 8..11) is present, and bit 23 is zero, even if this is
18089 a PC-relative operation. */
18090 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18092 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
18094 if ((newval
& 0xf0000000) == 0xe0000000)
18096 /* Doubleword load/store: 8-bit offset, scaled by 4. */
18098 newval
|= (1 << 23);
18101 if (value
% 4 != 0)
18103 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18104 _("offset not a multiple of 4"));
18110 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18111 _("offset out of range"));
18116 else if ((newval
& 0x000f0000) == 0x000f0000)
18118 /* PC-relative, 12-bit offset. */
18120 newval
|= (1 << 23);
18125 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18126 _("offset out of range"));
18131 else if ((newval
& 0x00000100) == 0x00000100)
18133 /* Writeback: 8-bit, +/- offset. */
18135 newval
|= (1 << 9);
18140 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18141 _("offset out of range"));
18146 else if ((newval
& 0x00000f00) == 0x00000e00)
18148 /* T-instruction: positive 8-bit offset. */
18149 if (value
< 0 || value
> 0xff)
18151 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18152 _("offset out of range"));
18160 /* Positive 12-bit or negative 8-bit offset. */
18164 newval
|= (1 << 23);
18174 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18175 _("offset out of range"));
18182 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
18183 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
18186 case BFD_RELOC_ARM_SHIFT_IMM
:
18187 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18188 if (((unsigned long) value
) > 32
18190 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
18192 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18193 _("shift expression is too large"));
18198 /* Shifts of zero must be done as lsl. */
18200 else if (value
== 32)
18202 newval
&= 0xfffff07f;
18203 newval
|= (value
& 0x1f) << 7;
18204 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18207 case BFD_RELOC_ARM_T32_IMMEDIATE
:
18208 case BFD_RELOC_ARM_T32_ADD_IMM
:
18209 case BFD_RELOC_ARM_T32_IMM12
:
18210 case BFD_RELOC_ARM_T32_ADD_PC12
:
18211 /* We claim that this fixup has been processed here,
18212 even if in fact we generate an error because we do
18213 not have a reloc for it, so tc_gen_reloc will reject it. */
18217 && ! S_IS_DEFINED (fixP
->fx_addsy
))
18219 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18220 _("undefined symbol %s used as an immediate value"),
18221 S_GET_NAME (fixP
->fx_addsy
));
18225 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18227 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
18230 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
18231 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
18233 newimm
= encode_thumb32_immediate (value
);
18234 if (newimm
== (unsigned int) FAIL
)
18235 newimm
= thumb32_negate_data_op (&newval
, value
);
18237 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
18238 && newimm
== (unsigned int) FAIL
)
18240 /* Turn add/sum into addw/subw. */
18241 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
18242 newval
= (newval
& 0xfeffffff) | 0x02000000;
18244 /* 12 bit immediate for addw/subw. */
18248 newval
^= 0x00a00000;
18251 newimm
= (unsigned int) FAIL
;
18256 if (newimm
== (unsigned int)FAIL
)
18258 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18259 _("invalid constant (%lx) after fixup"),
18260 (unsigned long) value
);
18264 newval
|= (newimm
& 0x800) << 15;
18265 newval
|= (newimm
& 0x700) << 4;
18266 newval
|= (newimm
& 0x0ff);
18268 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
18269 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
18272 case BFD_RELOC_ARM_SMC
:
18273 if (((unsigned long) value
) > 0xffff)
18274 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18275 _("invalid smc expression"));
18276 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18277 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
18278 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18281 case BFD_RELOC_ARM_SWI
:
18282 if (fixP
->tc_fix_data
!= 0)
18284 if (((unsigned long) value
) > 0xff)
18285 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18286 _("invalid swi expression"));
18287 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18289 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18293 if (((unsigned long) value
) > 0x00ffffff)
18294 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18295 _("invalid swi expression"));
18296 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18298 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18302 case BFD_RELOC_ARM_MULTI
:
18303 if (((unsigned long) value
) > 0xffff)
18304 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18305 _("invalid expression in load/store multiple"));
18306 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
18307 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18311 case BFD_RELOC_ARM_PCREL_CALL
:
18312 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18313 if ((newval
& 0xf0000000) == 0xf0000000)
18317 goto arm_branch_common
;
18319 case BFD_RELOC_ARM_PCREL_JUMP
:
18320 case BFD_RELOC_ARM_PLT32
:
18322 case BFD_RELOC_ARM_PCREL_BRANCH
:
18324 goto arm_branch_common
;
18326 case BFD_RELOC_ARM_PCREL_BLX
:
18329 /* We are going to store value (shifted right by two) in the
18330 instruction, in a 24 bit, signed field. Bits 26 through 32 either
18331 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
18332 also be be clear. */
18334 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18335 _("misaligned branch destination"));
18336 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
18337 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
18338 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18339 _("branch out of range"));
18341 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18343 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18344 newval
|= (value
>> 2) & 0x00ffffff;
18345 /* Set the H bit on BLX instructions. */
18349 newval
|= 0x01000000;
18351 newval
&= ~0x01000000;
18353 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18357 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
18358 /* CBZ can only branch forward. */
18360 /* Attempts to use CBZ to branch to the next instruction
18361 (which, strictly speaking, are prohibited) will be turned into
18364 FIXME: It may be better to remove the instruction completely and
18365 perform relaxation. */
18368 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18369 newval
= 0xbf00; /* NOP encoding T1 */
18370 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18375 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18376 _("branch out of range"));
18378 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18380 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18381 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
18382 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18387 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
18388 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
18389 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18390 _("branch out of range"));
18392 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18394 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18395 newval
|= (value
& 0x1ff) >> 1;
18396 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18400 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
18401 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
18402 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18403 _("branch out of range"));
18405 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18407 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18408 newval
|= (value
& 0xfff) >> 1;
18409 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18413 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
18414 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
18415 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18416 _("conditional branch out of range"));
18418 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18421 addressT S
, J1
, J2
, lo
, hi
;
18423 S
= (value
& 0x00100000) >> 20;
18424 J2
= (value
& 0x00080000) >> 19;
18425 J1
= (value
& 0x00040000) >> 18;
18426 hi
= (value
& 0x0003f000) >> 12;
18427 lo
= (value
& 0x00000ffe) >> 1;
18429 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18430 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18431 newval
|= (S
<< 10) | hi
;
18432 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
18433 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18434 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18438 case BFD_RELOC_THUMB_PCREL_BLX
:
18439 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
18440 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
18441 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18442 _("branch out of range"));
18444 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
18445 /* For a BLX instruction, make sure that the relocation is rounded up
18446 to a word boundary. This follows the semantics of the instruction
18447 which specifies that bit 1 of the target address will come from bit
18448 1 of the base address. */
18449 value
= (value
+ 1) & ~ 1;
18451 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18455 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18456 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18457 newval
|= (value
& 0x7fffff) >> 12;
18458 newval2
|= (value
& 0xfff) >> 1;
18459 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18460 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18464 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
18465 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
18466 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18467 _("branch out of range"));
18469 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18472 addressT S
, I1
, I2
, lo
, hi
;
18474 S
= (value
& 0x01000000) >> 24;
18475 I1
= (value
& 0x00800000) >> 23;
18476 I2
= (value
& 0x00400000) >> 22;
18477 hi
= (value
& 0x003ff000) >> 12;
18478 lo
= (value
& 0x00000ffe) >> 1;
18483 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18484 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18485 newval
|= (S
<< 10) | hi
;
18486 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
18487 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18488 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18493 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18494 md_number_to_chars (buf
, value
, 1);
18498 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18499 md_number_to_chars (buf
, value
, 2);
18503 case BFD_RELOC_ARM_TLS_GD32
:
18504 case BFD_RELOC_ARM_TLS_LE32
:
18505 case BFD_RELOC_ARM_TLS_IE32
:
18506 case BFD_RELOC_ARM_TLS_LDM32
:
18507 case BFD_RELOC_ARM_TLS_LDO32
:
18508 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
18511 case BFD_RELOC_ARM_GOT32
:
18512 case BFD_RELOC_ARM_GOTOFF
:
18513 case BFD_RELOC_ARM_TARGET2
:
18514 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18515 md_number_to_chars (buf
, 0, 4);
18519 case BFD_RELOC_RVA
:
18521 case BFD_RELOC_ARM_TARGET1
:
18522 case BFD_RELOC_ARM_ROSEGREL32
:
18523 case BFD_RELOC_ARM_SBREL32
:
18524 case BFD_RELOC_32_PCREL
:
18526 case BFD_RELOC_32_SECREL
:
18528 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18530 /* For WinCE we only do this for pcrel fixups. */
18531 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
18533 md_number_to_chars (buf
, value
, 4);
18537 case BFD_RELOC_ARM_PREL31
:
18538 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18540 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
18541 if ((value
^ (value
>> 1)) & 0x40000000)
18543 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18544 _("rel31 relocation overflow"));
18546 newval
|= value
& 0x7fffffff;
18547 md_number_to_chars (buf
, newval
, 4);
18552 case BFD_RELOC_ARM_CP_OFF_IMM
:
18553 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
18554 if (value
< -1023 || value
> 1023 || (value
& 3))
18555 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18556 _("co-processor offset out of range"));
18561 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18562 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18563 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18565 newval
= get_thumb32_insn (buf
);
18566 newval
&= 0xff7fff00;
18567 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
18568 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18569 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18570 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18572 put_thumb32_insn (buf
, newval
);
18575 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
18576 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
18577 if (value
< -255 || value
> 255)
18578 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18579 _("co-processor offset out of range"));
18581 goto cp_off_common
;
18583 case BFD_RELOC_ARM_THUMB_OFFSET
:
18584 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18585 /* Exactly what ranges, and where the offset is inserted depends
18586 on the type of instruction, we can establish this from the
18588 switch (newval
>> 12)
18590 case 4: /* PC load. */
18591 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
18592 forced to zero for these loads; md_pcrel_from has already
18593 compensated for this. */
18595 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18596 _("invalid offset, target not word aligned (0x%08lX)"),
18597 (((unsigned long) fixP
->fx_frag
->fr_address
18598 + (unsigned long) fixP
->fx_where
) & ~3)
18599 + (unsigned long) value
);
18601 if (value
& ~0x3fc)
18602 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18603 _("invalid offset, value too big (0x%08lX)"),
18606 newval
|= value
>> 2;
18609 case 9: /* SP load/store. */
18610 if (value
& ~0x3fc)
18611 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18612 _("invalid offset, value too big (0x%08lX)"),
18614 newval
|= value
>> 2;
18617 case 6: /* Word load/store. */
18619 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18620 _("invalid offset, value too big (0x%08lX)"),
18622 newval
|= value
<< 4; /* 6 - 2. */
18625 case 7: /* Byte load/store. */
18627 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18628 _("invalid offset, value too big (0x%08lX)"),
18630 newval
|= value
<< 6;
18633 case 8: /* Halfword load/store. */
18635 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18636 _("invalid offset, value too big (0x%08lX)"),
18638 newval
|= value
<< 5; /* 6 - 1. */
18642 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18643 "Unable to process relocation for thumb opcode: %lx",
18644 (unsigned long) newval
);
18647 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18650 case BFD_RELOC_ARM_THUMB_ADD
:
18651 /* This is a complicated relocation, since we use it for all of
18652 the following immediate relocations:
18656 9bit ADD/SUB SP word-aligned
18657 10bit ADD PC/SP word-aligned
18659 The type of instruction being processed is encoded in the
18666 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18668 int rd
= (newval
>> 4) & 0xf;
18669 int rs
= newval
& 0xf;
18670 int subtract
= !!(newval
& 0x8000);
18672 /* Check for HI regs, only very restricted cases allowed:
18673 Adjusting SP, and using PC or SP to get an address. */
18674 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
18675 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
18676 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18677 _("invalid Hi register with immediate"));
18679 /* If value is negative, choose the opposite instruction. */
18683 subtract
= !subtract
;
18685 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18686 _("immediate value out of range"));
18691 if (value
& ~0x1fc)
18692 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18693 _("invalid immediate for stack address calculation"));
18694 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
18695 newval
|= value
>> 2;
18697 else if (rs
== REG_PC
|| rs
== REG_SP
)
18699 if (subtract
|| value
& ~0x3fc)
18700 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18701 _("invalid immediate for address calculation (value = 0x%08lX)"),
18702 (unsigned long) value
);
18703 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
18705 newval
|= value
>> 2;
18710 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18711 _("immediate value out of range"));
18712 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
18713 newval
|= (rd
<< 8) | value
;
18718 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18719 _("immediate value out of range"));
18720 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
18721 newval
|= rd
| (rs
<< 3) | (value
<< 6);
18724 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18727 case BFD_RELOC_ARM_THUMB_IMM
:
18728 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18729 if (value
< 0 || value
> 255)
18730 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18731 _("invalid immediate: %ld is too large"),
18734 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18737 case BFD_RELOC_ARM_THUMB_SHIFT
:
18738 /* 5bit shift value (0..32). LSL cannot take 32. */
18739 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
18740 temp
= newval
& 0xf800;
18741 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
18742 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18743 _("invalid shift value: %ld"), (long) value
);
18744 /* Shifts of zero must be encoded as LSL. */
18746 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
18747 /* Shifts of 32 are encoded as zero. */
18748 else if (value
== 32)
18750 newval
|= value
<< 6;
18751 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18754 case BFD_RELOC_VTABLE_INHERIT
:
18755 case BFD_RELOC_VTABLE_ENTRY
:
18759 case BFD_RELOC_ARM_MOVW
:
18760 case BFD_RELOC_ARM_MOVT
:
18761 case BFD_RELOC_ARM_THUMB_MOVW
:
18762 case BFD_RELOC_ARM_THUMB_MOVT
:
18763 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18765 /* REL format relocations are limited to a 16-bit addend. */
18766 if (!fixP
->fx_done
)
18768 if (value
< -0x1000 || value
> 0xffff)
18769 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18770 _("offset too big"));
18772 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
18773 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18778 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
18779 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18781 newval
= get_thumb32_insn (buf
);
18782 newval
&= 0xfbf08f00;
18783 newval
|= (value
& 0xf000) << 4;
18784 newval
|= (value
& 0x0800) << 15;
18785 newval
|= (value
& 0x0700) << 4;
18786 newval
|= (value
& 0x00ff);
18787 put_thumb32_insn (buf
, newval
);
18791 newval
= md_chars_to_number (buf
, 4);
18792 newval
&= 0xfff0f000;
18793 newval
|= value
& 0x0fff;
18794 newval
|= (value
& 0xf000) << 4;
18795 md_number_to_chars (buf
, newval
, 4);
18800 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
18801 case BFD_RELOC_ARM_ALU_PC_G0
:
18802 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
18803 case BFD_RELOC_ARM_ALU_PC_G1
:
18804 case BFD_RELOC_ARM_ALU_PC_G2
:
18805 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
18806 case BFD_RELOC_ARM_ALU_SB_G0
:
18807 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
18808 case BFD_RELOC_ARM_ALU_SB_G1
:
18809 case BFD_RELOC_ARM_ALU_SB_G2
:
18810 assert (!fixP
->fx_done
);
18811 if (!seg
->use_rela_p
)
18814 bfd_vma encoded_addend
;
18815 bfd_vma addend_abs
= abs (value
);
18817 /* Check that the absolute value of the addend can be
18818 expressed as an 8-bit constant plus a rotation. */
18819 encoded_addend
= encode_arm_immediate (addend_abs
);
18820 if (encoded_addend
== (unsigned int) FAIL
)
18821 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18822 _("the offset 0x%08lX is not representable"),
18825 /* Extract the instruction. */
18826 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18828 /* If the addend is positive, use an ADD instruction.
18829 Otherwise use a SUB. Take care not to destroy the S bit. */
18830 insn
&= 0xff1fffff;
18836 /* Place the encoded addend into the first 12 bits of the
18838 insn
&= 0xfffff000;
18839 insn
|= encoded_addend
;
18841 /* Update the instruction. */
18842 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18846 case BFD_RELOC_ARM_LDR_PC_G0
:
18847 case BFD_RELOC_ARM_LDR_PC_G1
:
18848 case BFD_RELOC_ARM_LDR_PC_G2
:
18849 case BFD_RELOC_ARM_LDR_SB_G0
:
18850 case BFD_RELOC_ARM_LDR_SB_G1
:
18851 case BFD_RELOC_ARM_LDR_SB_G2
:
18852 assert (!fixP
->fx_done
);
18853 if (!seg
->use_rela_p
)
18856 bfd_vma addend_abs
= abs (value
);
18858 /* Check that the absolute value of the addend can be
18859 encoded in 12 bits. */
18860 if (addend_abs
>= 0x1000)
18861 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18862 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
18865 /* Extract the instruction. */
18866 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18868 /* If the addend is negative, clear bit 23 of the instruction.
18869 Otherwise set it. */
18871 insn
&= ~(1 << 23);
18875 /* Place the absolute value of the addend into the first 12 bits
18876 of the instruction. */
18877 insn
&= 0xfffff000;
18878 insn
|= addend_abs
;
18880 /* Update the instruction. */
18881 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18885 case BFD_RELOC_ARM_LDRS_PC_G0
:
18886 case BFD_RELOC_ARM_LDRS_PC_G1
:
18887 case BFD_RELOC_ARM_LDRS_PC_G2
:
18888 case BFD_RELOC_ARM_LDRS_SB_G0
:
18889 case BFD_RELOC_ARM_LDRS_SB_G1
:
18890 case BFD_RELOC_ARM_LDRS_SB_G2
:
18891 assert (!fixP
->fx_done
);
18892 if (!seg
->use_rela_p
)
18895 bfd_vma addend_abs
= abs (value
);
18897 /* Check that the absolute value of the addend can be
18898 encoded in 8 bits. */
18899 if (addend_abs
>= 0x100)
18900 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18901 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
18904 /* Extract the instruction. */
18905 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18907 /* If the addend is negative, clear bit 23 of the instruction.
18908 Otherwise set it. */
18910 insn
&= ~(1 << 23);
18914 /* Place the first four bits of the absolute value of the addend
18915 into the first 4 bits of the instruction, and the remaining
18916 four into bits 8 .. 11. */
18917 insn
&= 0xfffff0f0;
18918 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
18920 /* Update the instruction. */
18921 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18925 case BFD_RELOC_ARM_LDC_PC_G0
:
18926 case BFD_RELOC_ARM_LDC_PC_G1
:
18927 case BFD_RELOC_ARM_LDC_PC_G2
:
18928 case BFD_RELOC_ARM_LDC_SB_G0
:
18929 case BFD_RELOC_ARM_LDC_SB_G1
:
18930 case BFD_RELOC_ARM_LDC_SB_G2
:
18931 assert (!fixP
->fx_done
);
18932 if (!seg
->use_rela_p
)
18935 bfd_vma addend_abs
= abs (value
);
18937 /* Check that the absolute value of the addend is a multiple of
18938 four and, when divided by four, fits in 8 bits. */
18939 if (addend_abs
& 0x3)
18940 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18941 _("bad offset 0x%08lX (must be word-aligned)"),
18944 if ((addend_abs
>> 2) > 0xff)
18945 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18946 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
18949 /* Extract the instruction. */
18950 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18952 /* If the addend is negative, clear bit 23 of the instruction.
18953 Otherwise set it. */
18955 insn
&= ~(1 << 23);
18959 /* Place the addend (divided by four) into the first eight
18960 bits of the instruction. */
18961 insn
&= 0xfffffff0;
18962 insn
|= addend_abs
>> 2;
18964 /* Update the instruction. */
18965 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18969 case BFD_RELOC_UNUSED
:
18971 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18972 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
18976 /* Translate internal representation of relocation info to BFD target
18980 tc_gen_reloc (asection
*section
, fixS
*fixp
)
18983 bfd_reloc_code_real_type code
;
18985 reloc
= xmalloc (sizeof (arelent
));
18987 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
18988 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18989 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18991 if (fixp
->fx_pcrel
)
18993 if (section
->use_rela_p
)
18994 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
18996 fixp
->fx_offset
= reloc
->address
;
18998 reloc
->addend
= fixp
->fx_offset
;
19000 switch (fixp
->fx_r_type
)
19003 if (fixp
->fx_pcrel
)
19005 code
= BFD_RELOC_8_PCREL
;
19010 if (fixp
->fx_pcrel
)
19012 code
= BFD_RELOC_16_PCREL
;
19017 if (fixp
->fx_pcrel
)
19019 code
= BFD_RELOC_32_PCREL
;
19023 case BFD_RELOC_ARM_MOVW
:
19024 if (fixp
->fx_pcrel
)
19026 code
= BFD_RELOC_ARM_MOVW_PCREL
;
19030 case BFD_RELOC_ARM_MOVT
:
19031 if (fixp
->fx_pcrel
)
19033 code
= BFD_RELOC_ARM_MOVT_PCREL
;
19037 case BFD_RELOC_ARM_THUMB_MOVW
:
19038 if (fixp
->fx_pcrel
)
19040 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
19044 case BFD_RELOC_ARM_THUMB_MOVT
:
19045 if (fixp
->fx_pcrel
)
19047 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
19051 case BFD_RELOC_NONE
:
19052 case BFD_RELOC_ARM_PCREL_BRANCH
:
19053 case BFD_RELOC_ARM_PCREL_BLX
:
19054 case BFD_RELOC_RVA
:
19055 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19056 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19057 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19058 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19059 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19060 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19061 case BFD_RELOC_THUMB_PCREL_BLX
:
19062 case BFD_RELOC_VTABLE_ENTRY
:
19063 case BFD_RELOC_VTABLE_INHERIT
:
19065 case BFD_RELOC_32_SECREL
:
19067 code
= fixp
->fx_r_type
;
19070 case BFD_RELOC_ARM_LITERAL
:
19071 case BFD_RELOC_ARM_HWLITERAL
:
19072 /* If this is called then the a literal has
19073 been referenced across a section boundary. */
19074 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19075 _("literal referenced across section boundary"));
19079 case BFD_RELOC_ARM_GOT32
:
19080 case BFD_RELOC_ARM_GOTOFF
:
19081 case BFD_RELOC_ARM_PLT32
:
19082 case BFD_RELOC_ARM_TARGET1
:
19083 case BFD_RELOC_ARM_ROSEGREL32
:
19084 case BFD_RELOC_ARM_SBREL32
:
19085 case BFD_RELOC_ARM_PREL31
:
19086 case BFD_RELOC_ARM_TARGET2
:
19087 case BFD_RELOC_ARM_TLS_LE32
:
19088 case BFD_RELOC_ARM_TLS_LDO32
:
19089 case BFD_RELOC_ARM_PCREL_CALL
:
19090 case BFD_RELOC_ARM_PCREL_JUMP
:
19091 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
19092 case BFD_RELOC_ARM_ALU_PC_G0
:
19093 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
19094 case BFD_RELOC_ARM_ALU_PC_G1
:
19095 case BFD_RELOC_ARM_ALU_PC_G2
:
19096 case BFD_RELOC_ARM_LDR_PC_G0
:
19097 case BFD_RELOC_ARM_LDR_PC_G1
:
19098 case BFD_RELOC_ARM_LDR_PC_G2
:
19099 case BFD_RELOC_ARM_LDRS_PC_G0
:
19100 case BFD_RELOC_ARM_LDRS_PC_G1
:
19101 case BFD_RELOC_ARM_LDRS_PC_G2
:
19102 case BFD_RELOC_ARM_LDC_PC_G0
:
19103 case BFD_RELOC_ARM_LDC_PC_G1
:
19104 case BFD_RELOC_ARM_LDC_PC_G2
:
19105 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
19106 case BFD_RELOC_ARM_ALU_SB_G0
:
19107 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
19108 case BFD_RELOC_ARM_ALU_SB_G1
:
19109 case BFD_RELOC_ARM_ALU_SB_G2
:
19110 case BFD_RELOC_ARM_LDR_SB_G0
:
19111 case BFD_RELOC_ARM_LDR_SB_G1
:
19112 case BFD_RELOC_ARM_LDR_SB_G2
:
19113 case BFD_RELOC_ARM_LDRS_SB_G0
:
19114 case BFD_RELOC_ARM_LDRS_SB_G1
:
19115 case BFD_RELOC_ARM_LDRS_SB_G2
:
19116 case BFD_RELOC_ARM_LDC_SB_G0
:
19117 case BFD_RELOC_ARM_LDC_SB_G1
:
19118 case BFD_RELOC_ARM_LDC_SB_G2
:
19119 code
= fixp
->fx_r_type
;
19122 case BFD_RELOC_ARM_TLS_GD32
:
19123 case BFD_RELOC_ARM_TLS_IE32
:
19124 case BFD_RELOC_ARM_TLS_LDM32
:
19125 /* BFD will include the symbol's address in the addend.
19126 But we don't want that, so subtract it out again here. */
19127 if (!S_IS_COMMON (fixp
->fx_addsy
))
19128 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
19129 code
= fixp
->fx_r_type
;
19133 case BFD_RELOC_ARM_IMMEDIATE
:
19134 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19135 _("internal relocation (type: IMMEDIATE) not fixed up"));
19138 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
19139 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19140 _("ADRL used for a symbol not defined in the same file"));
19143 case BFD_RELOC_ARM_OFFSET_IMM
:
19144 if (section
->use_rela_p
)
19146 code
= fixp
->fx_r_type
;
19150 if (fixp
->fx_addsy
!= NULL
19151 && !S_IS_DEFINED (fixp
->fx_addsy
)
19152 && S_IS_LOCAL (fixp
->fx_addsy
))
19154 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19155 _("undefined local label `%s'"),
19156 S_GET_NAME (fixp
->fx_addsy
));
19160 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19161 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
19168 switch (fixp
->fx_r_type
)
19170 case BFD_RELOC_NONE
: type
= "NONE"; break;
19171 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
19172 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
19173 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
19174 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
19175 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
19176 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
19177 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
19178 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
19179 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
19180 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
19181 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
19182 default: type
= _("<unknown>"); break;
19184 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19185 _("cannot represent %s relocation in this object file format"),
19192 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
19194 && fixp
->fx_addsy
== GOT_symbol
)
19196 code
= BFD_RELOC_ARM_GOTPC
;
19197 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
19201 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
19203 if (reloc
->howto
== NULL
)
19205 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19206 _("cannot represent %s relocation in this object file format"),
19207 bfd_get_reloc_code_name (code
));
19211 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
19212 vtable entry to be used in the relocation's section offset. */
19213 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
19214 reloc
->address
= fixp
->fx_offset
;
19219 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
19222 cons_fix_new_arm (fragS
* frag
,
19227 bfd_reloc_code_real_type type
;
19231 FIXME: @@ Should look at CPU word size. */
19235 type
= BFD_RELOC_8
;
19238 type
= BFD_RELOC_16
;
19242 type
= BFD_RELOC_32
;
19245 type
= BFD_RELOC_64
;
19250 if (exp
->X_op
== O_secrel
)
19252 exp
->X_op
= O_symbol
;
19253 type
= BFD_RELOC_32_SECREL
;
19257 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
19260 #if defined OBJ_COFF || defined OBJ_ELF
19262 arm_validate_fix (fixS
* fixP
)
19264 /* If the destination of the branch is a defined symbol which does not have
19265 the THUMB_FUNC attribute, then we must be calling a function which has
19266 the (interfacearm) attribute. We look for the Thumb entry point to that
19267 function and change the branch to refer to that function instead. */
19268 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
19269 && fixP
->fx_addsy
!= NULL
19270 && S_IS_DEFINED (fixP
->fx_addsy
)
19271 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
19273 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
19279 arm_force_relocation (struct fix
* fixp
)
19281 #if defined (OBJ_COFF) && defined (TE_PE)
19282 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
19286 /* Resolve these relocations even if the symbol is extern or weak. */
19287 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
19288 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
19289 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
19290 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
19291 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
19292 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
19293 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
19296 /* Always leave these relocations for the linker. */
19297 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
19298 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
19299 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
19302 /* Always generate relocations against function symbols. */
19303 if (fixp
->fx_r_type
== BFD_RELOC_32
19305 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
19308 return generic_force_reloc (fixp
);
19311 #if defined (OBJ_ELF) || defined (OBJ_COFF)
19312 /* Relocations against function names must be left unadjusted,
19313 so that the linker can use this information to generate interworking
19314 stubs. The MIPS version of this function
19315 also prevents relocations that are mips-16 specific, but I do not
19316 know why it does this.
19319 There is one other problem that ought to be addressed here, but
19320 which currently is not: Taking the address of a label (rather
19321 than a function) and then later jumping to that address. Such
19322 addresses also ought to have their bottom bit set (assuming that
19323 they reside in Thumb code), but at the moment they will not. */
19326 arm_fix_adjustable (fixS
* fixP
)
19328 if (fixP
->fx_addsy
== NULL
)
19331 /* Preserve relocations against symbols with function type. */
19332 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
19335 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
19336 && fixP
->fx_subsy
== NULL
)
19339 /* We need the symbol name for the VTABLE entries. */
19340 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
19341 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
19344 /* Don't allow symbols to be discarded on GOT related relocs. */
19345 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
19346 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
19347 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
19348 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
19349 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
19350 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
19351 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
19352 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
19353 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
19356 /* Similarly for group relocations. */
19357 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
19358 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
19359 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
19364 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
19369 elf32_arm_target_format (void)
19372 return (target_big_endian
19373 ? "elf32-bigarm-symbian"
19374 : "elf32-littlearm-symbian");
19375 #elif defined (TE_VXWORKS)
19376 return (target_big_endian
19377 ? "elf32-bigarm-vxworks"
19378 : "elf32-littlearm-vxworks");
19380 if (target_big_endian
)
19381 return "elf32-bigarm";
19383 return "elf32-littlearm";
19388 armelf_frob_symbol (symbolS
* symp
,
19391 elf_frob_symbol (symp
, puntp
);
19395 /* MD interface: Finalization. */
19397 /* A good place to do this, although this was probably not intended
19398 for this kind of use. We need to dump the literal pool before
19399 references are made to a null symbol pointer. */
19404 literal_pool
* pool
;
19406 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
19408 /* Put it at the end of the relevent section. */
19409 subseg_set (pool
->section
, pool
->sub_section
);
19411 arm_elf_change_section ();
19417 /* Adjust the symbol table. This marks Thumb symbols as distinct from
19421 arm_adjust_symtab (void)
19426 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
19428 if (ARM_IS_THUMB (sym
))
19430 if (THUMB_IS_FUNC (sym
))
19432 /* Mark the symbol as a Thumb function. */
19433 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
19434 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
19435 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
19437 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
19438 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
19440 as_bad (_("%s: unexpected function type: %d"),
19441 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
19443 else switch (S_GET_STORAGE_CLASS (sym
))
19446 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
19449 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
19452 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
19460 if (ARM_IS_INTERWORK (sym
))
19461 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
19468 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
19470 if (ARM_IS_THUMB (sym
))
19472 elf_symbol_type
* elf_sym
;
19474 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
19475 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
19477 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
19478 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
19480 /* If it's a .thumb_func, declare it as so,
19481 otherwise tag label as .code 16. */
19482 if (THUMB_IS_FUNC (sym
))
19483 elf_sym
->internal_elf_sym
.st_info
=
19484 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
19485 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
19486 elf_sym
->internal_elf_sym
.st_info
=
19487 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
19494 /* MD interface: Initialization. */
19497 set_constant_flonums (void)
19501 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
19502 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
19506 /* Auto-select Thumb mode if it's the only available instruction set for the
19507 given architecture. */
19510 autoselect_thumb_from_cpu_variant (void)
19512 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
19513 opcode_select (16);
19522 if ( (arm_ops_hsh
= hash_new ()) == NULL
19523 || (arm_cond_hsh
= hash_new ()) == NULL
19524 || (arm_shift_hsh
= hash_new ()) == NULL
19525 || (arm_psr_hsh
= hash_new ()) == NULL
19526 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
19527 || (arm_reg_hsh
= hash_new ()) == NULL
19528 || (arm_reloc_hsh
= hash_new ()) == NULL
19529 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
19530 as_fatal (_("virtual memory exhausted"));
19532 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
19533 hash_insert (arm_ops_hsh
, insns
[i
].template, (PTR
) (insns
+ i
));
19534 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
19535 hash_insert (arm_cond_hsh
, conds
[i
].template, (PTR
) (conds
+ i
));
19536 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
19537 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (PTR
) (shift_names
+ i
));
19538 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
19539 hash_insert (arm_psr_hsh
, psrs
[i
].template, (PTR
) (psrs
+ i
));
19540 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
19541 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template, (PTR
) (v7m_psrs
+ i
));
19542 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
19543 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (PTR
) (reg_names
+ i
));
19545 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
19547 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template,
19548 (PTR
) (barrier_opt_names
+ i
));
19550 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
19551 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (PTR
) (reloc_names
+ i
));
19554 set_constant_flonums ();
19556 /* Set the cpu variant based on the command-line options. We prefer
19557 -mcpu= over -march= if both are set (as for GCC); and we prefer
19558 -mfpu= over any other way of setting the floating point unit.
19559 Use of legacy options with new options are faulted. */
19562 if (mcpu_cpu_opt
|| march_cpu_opt
)
19563 as_bad (_("use of old and new-style options to set CPU type"));
19565 mcpu_cpu_opt
= legacy_cpu
;
19567 else if (!mcpu_cpu_opt
)
19568 mcpu_cpu_opt
= march_cpu_opt
;
19573 as_bad (_("use of old and new-style options to set FPU type"));
19575 mfpu_opt
= legacy_fpu
;
19577 else if (!mfpu_opt
)
19579 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
19580 /* Some environments specify a default FPU. If they don't, infer it
19581 from the processor. */
19583 mfpu_opt
= mcpu_fpu_opt
;
19585 mfpu_opt
= march_fpu_opt
;
19587 mfpu_opt
= &fpu_default
;
19593 if (mcpu_cpu_opt
!= NULL
)
19594 mfpu_opt
= &fpu_default
;
19595 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
19596 mfpu_opt
= &fpu_arch_vfp_v2
;
19598 mfpu_opt
= &fpu_arch_fpa
;
19604 mcpu_cpu_opt
= &cpu_default
;
19605 selected_cpu
= cpu_default
;
19609 selected_cpu
= *mcpu_cpu_opt
;
19611 mcpu_cpu_opt
= &arm_arch_any
;
19614 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
19616 autoselect_thumb_from_cpu_variant ();
19618 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
19620 #if defined OBJ_COFF || defined OBJ_ELF
19622 unsigned int flags
= 0;
19624 #if defined OBJ_ELF
19625 flags
= meabi_flags
;
19627 switch (meabi_flags
)
19629 case EF_ARM_EABI_UNKNOWN
:
19631 /* Set the flags in the private structure. */
19632 if (uses_apcs_26
) flags
|= F_APCS26
;
19633 if (support_interwork
) flags
|= F_INTERWORK
;
19634 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
19635 if (pic_code
) flags
|= F_PIC
;
19636 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
19637 flags
|= F_SOFT_FLOAT
;
19639 switch (mfloat_abi_opt
)
19641 case ARM_FLOAT_ABI_SOFT
:
19642 case ARM_FLOAT_ABI_SOFTFP
:
19643 flags
|= F_SOFT_FLOAT
;
19646 case ARM_FLOAT_ABI_HARD
:
19647 if (flags
& F_SOFT_FLOAT
)
19648 as_bad (_("hard-float conflicts with specified fpu"));
19652 /* Using pure-endian doubles (even if soft-float). */
19653 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
19654 flags
|= F_VFP_FLOAT
;
19656 #if defined OBJ_ELF
19657 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
19658 flags
|= EF_ARM_MAVERICK_FLOAT
;
19661 case EF_ARM_EABI_VER4
:
19662 case EF_ARM_EABI_VER5
:
19663 /* No additional flags to set. */
19670 bfd_set_private_flags (stdoutput
, flags
);
19672 /* We have run out flags in the COFF header to encode the
19673 status of ATPCS support, so instead we create a dummy,
19674 empty, debug section called .arm.atpcs. */
19679 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
19683 bfd_set_section_flags
19684 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
19685 bfd_set_section_size (stdoutput
, sec
, 0);
19686 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
19692 /* Record the CPU type as well. */
19693 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
19694 mach
= bfd_mach_arm_iWMMXt2
;
19695 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
19696 mach
= bfd_mach_arm_iWMMXt
;
19697 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
19698 mach
= bfd_mach_arm_XScale
;
19699 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
19700 mach
= bfd_mach_arm_ep9312
;
19701 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
19702 mach
= bfd_mach_arm_5TE
;
19703 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
19705 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19706 mach
= bfd_mach_arm_5T
;
19708 mach
= bfd_mach_arm_5
;
19710 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
19712 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19713 mach
= bfd_mach_arm_4T
;
19715 mach
= bfd_mach_arm_4
;
19717 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
19718 mach
= bfd_mach_arm_3M
;
19719 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
19720 mach
= bfd_mach_arm_3
;
19721 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
19722 mach
= bfd_mach_arm_2a
;
19723 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
19724 mach
= bfd_mach_arm_2
;
19726 mach
= bfd_mach_arm_unknown
;
19728 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
19731 /* Command line processing. */
19734 Invocation line includes a switch not recognized by the base assembler.
19735 See if it's a processor-specific option.
19737 This routine is somewhat complicated by the need for backwards
19738 compatibility (since older releases of gcc can't be changed).
19739 The new options try to make the interface as compatible as
19742 New options (supported) are:
19744 -mcpu=<cpu name> Assemble for selected processor
19745 -march=<architecture name> Assemble for selected architecture
19746 -mfpu=<fpu architecture> Assemble for selected FPU.
19747 -EB/-mbig-endian Big-endian
19748 -EL/-mlittle-endian Little-endian
19749 -k Generate PIC code
19750 -mthumb Start in Thumb mode
19751 -mthumb-interwork Code supports ARM/Thumb interworking
19753 For now we will also provide support for:
19755 -mapcs-32 32-bit Program counter
19756 -mapcs-26 26-bit Program counter
19757 -macps-float Floats passed in FP registers
19758 -mapcs-reentrant Reentrant code
19760 (sometime these will probably be replaced with -mapcs=<list of options>
19761 and -matpcs=<list of options>)
19763 The remaining options are only supported for back-wards compatibility.
19764 Cpu variants, the arm part is optional:
19765 -m[arm]1 Currently not supported.
19766 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
19767 -m[arm]3 Arm 3 processor
19768 -m[arm]6[xx], Arm 6 processors
19769 -m[arm]7[xx][t][[d]m] Arm 7 processors
19770 -m[arm]8[10] Arm 8 processors
19771 -m[arm]9[20][tdmi] Arm 9 processors
19772 -mstrongarm[110[0]] StrongARM processors
19773 -mxscale XScale processors
19774 -m[arm]v[2345[t[e]]] Arm architectures
19775 -mall All (except the ARM1)
19777 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
19778 -mfpe-old (No float load/store multiples)
19779 -mvfpxd VFP Single precision
19781 -mno-fpu Disable all floating point instructions
19783 The following CPU names are recognized:
19784 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
19785 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
19786 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
19787 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
19788 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
19789 arm10t arm10e, arm1020t, arm1020e, arm10200e,
19790 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
19794 const char * md_shortopts
= "m:k";
19796 #ifdef ARM_BI_ENDIAN
19797 #define OPTION_EB (OPTION_MD_BASE + 0)
19798 #define OPTION_EL (OPTION_MD_BASE + 1)
19800 #if TARGET_BYTES_BIG_ENDIAN
19801 #define OPTION_EB (OPTION_MD_BASE + 0)
19803 #define OPTION_EL (OPTION_MD_BASE + 1)
19807 struct option md_longopts
[] =
19810 {"EB", no_argument
, NULL
, OPTION_EB
},
19813 {"EL", no_argument
, NULL
, OPTION_EL
},
19815 {NULL
, no_argument
, NULL
, 0}
19818 size_t md_longopts_size
= sizeof (md_longopts
);
19820 struct arm_option_table
19822 char *option
; /* Option name to match. */
19823 char *help
; /* Help information. */
19824 int *var
; /* Variable to change. */
19825 int value
; /* What to change it to. */
19826 char *deprecated
; /* If non-null, print this message. */
19829 struct arm_option_table arm_opts
[] =
19831 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
19832 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
19833 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
19834 &support_interwork
, 1, NULL
},
19835 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
19836 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
19837 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
19839 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
19840 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
19841 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
19842 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
19845 /* These are recognized by the assembler, but have no affect on code. */
19846 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
19847 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
19848 {NULL
, NULL
, NULL
, 0, NULL
}
19851 struct arm_legacy_option_table
19853 char *option
; /* Option name to match. */
19854 const arm_feature_set
**var
; /* Variable to change. */
19855 const arm_feature_set value
; /* What to change it to. */
19856 char *deprecated
; /* If non-null, print this message. */
19859 const struct arm_legacy_option_table arm_legacy_opts
[] =
19861 /* DON'T add any new processors to this list -- we want the whole list
19862 to go away... Add them to the processors table instead. */
19863 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19864 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19865 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19866 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19867 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19868 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19869 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19870 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19871 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19872 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19873 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19874 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19875 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19876 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19877 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19878 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19879 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19880 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19881 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19882 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19883 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19884 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19885 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19886 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19887 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19888 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19889 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19890 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19891 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19892 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19893 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19894 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19895 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19896 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19897 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19898 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19899 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19900 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19901 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19902 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19903 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19904 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19905 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19906 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19907 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19908 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19909 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19910 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19911 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19912 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19913 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19914 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19915 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19916 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19917 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19918 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19919 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19920 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19921 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19922 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19923 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19924 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19925 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19926 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19927 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19928 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19929 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19930 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19931 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
19932 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
19933 N_("use -mcpu=strongarm110")},
19934 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
19935 N_("use -mcpu=strongarm1100")},
19936 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
19937 N_("use -mcpu=strongarm1110")},
19938 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
19939 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
19940 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
19942 /* Architecture variants -- don't add any more to this list either. */
19943 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19944 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19945 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19946 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19947 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19948 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19949 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19950 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19951 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19952 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19953 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
19954 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
19955 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
19956 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
19957 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
19958 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
19959 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
19960 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
19962 /* Floating point variants -- don't add any more to this list either. */
19963 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
19964 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
19965 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
19966 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
19967 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
19969 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
19972 struct arm_cpu_option_table
19975 const arm_feature_set value
;
19976 /* For some CPUs we assume an FPU unless the user explicitly sets
19978 const arm_feature_set default_fpu
;
19979 /* The canonical name of the CPU, or NULL to use NAME converted to upper
19981 const char *canonical_name
;
19984 /* This list should, at a minimum, contain all the cpu names
19985 recognized by GCC. */
19986 static const struct arm_cpu_option_table arm_cpus
[] =
19988 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
19989 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
19990 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
19991 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
19992 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
19993 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19994 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19995 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19996 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19997 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19998 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19999 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20000 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20001 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20002 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20003 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20004 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20005 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20006 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20007 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20008 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20009 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20010 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20011 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20012 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20013 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20014 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20015 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20016 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20017 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20018 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20019 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20020 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20021 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20022 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20023 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20024 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20025 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20026 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20027 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
20028 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20029 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20030 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20031 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20032 /* For V5 or later processors we default to using VFP; but the user
20033 should really set the FPU type explicitly. */
20034 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20035 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20036 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
20037 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
20038 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
20039 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20040 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
20041 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20042 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20043 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
20044 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20045 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20046 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20047 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20048 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20049 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
20050 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20051 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20052 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20053 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
20054 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
20055 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
20056 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
20057 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
20058 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
20059 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
20060 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
20061 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
20062 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
20063 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
20064 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
20065 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE(0, FPU_VFP_V3
20066 | FPU_NEON_EXT_V1
),
20068 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
20069 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
20070 /* ??? XSCALE is really an architecture. */
20071 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
20072 /* ??? iwmmxt is not a processor. */
20073 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
20074 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
20075 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
20077 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
20078 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
20081 struct arm_arch_option_table
20084 const arm_feature_set value
;
20085 const arm_feature_set default_fpu
;
20088 /* This list should, at a minimum, contain all the architecture names
20089 recognized by GCC. */
20090 static const struct arm_arch_option_table arm_archs
[] =
20092 {"all", ARM_ANY
, FPU_ARCH_FPA
},
20093 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
20094 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
20095 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
20096 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
20097 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
20098 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
20099 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
20100 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
20101 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
20102 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
20103 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
20104 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
20105 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
20106 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
20107 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
20108 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
20109 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
20110 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
20111 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
20112 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
20113 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
20114 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
20115 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
20116 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
20117 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
20118 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
20119 /* The official spelling of the ARMv7 profile variants is the dashed form.
20120 Accept the non-dashed form for compatibility with old toolchains. */
20121 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
20122 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
20123 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
20124 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
20125 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
20126 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
20127 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
20128 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
20129 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
20130 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
20133 /* ISA extensions in the co-processor space. */
20134 struct arm_option_cpu_value_table
20137 const arm_feature_set value
;
20140 static const struct arm_option_cpu_value_table arm_extensions
[] =
20142 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
20143 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
20144 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
20145 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
20146 {NULL
, ARM_ARCH_NONE
}
20149 /* This list should, at a minimum, contain all the fpu names
20150 recognized by GCC. */
20151 static const struct arm_option_cpu_value_table arm_fpus
[] =
20153 {"softfpa", FPU_NONE
},
20154 {"fpe", FPU_ARCH_FPE
},
20155 {"fpe2", FPU_ARCH_FPE
},
20156 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
20157 {"fpa", FPU_ARCH_FPA
},
20158 {"fpa10", FPU_ARCH_FPA
},
20159 {"fpa11", FPU_ARCH_FPA
},
20160 {"arm7500fe", FPU_ARCH_FPA
},
20161 {"softvfp", FPU_ARCH_VFP
},
20162 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
20163 {"vfp", FPU_ARCH_VFP_V2
},
20164 {"vfp9", FPU_ARCH_VFP_V2
},
20165 {"vfp3", FPU_ARCH_VFP_V3
},
20166 {"vfp10", FPU_ARCH_VFP_V2
},
20167 {"vfp10-r0", FPU_ARCH_VFP_V1
},
20168 {"vfpxd", FPU_ARCH_VFP_V1xD
},
20169 {"arm1020t", FPU_ARCH_VFP_V1
},
20170 {"arm1020e", FPU_ARCH_VFP_V2
},
20171 {"arm1136jfs", FPU_ARCH_VFP_V2
},
20172 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
20173 {"maverick", FPU_ARCH_MAVERICK
},
20174 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
20175 {NULL
, ARM_ARCH_NONE
}
20178 struct arm_option_value_table
20184 static const struct arm_option_value_table arm_float_abis
[] =
20186 {"hard", ARM_FLOAT_ABI_HARD
},
20187 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
20188 {"soft", ARM_FLOAT_ABI_SOFT
},
20193 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
20194 static const struct arm_option_value_table arm_eabis
[] =
20196 {"gnu", EF_ARM_EABI_UNKNOWN
},
20197 {"4", EF_ARM_EABI_VER4
},
20198 {"5", EF_ARM_EABI_VER5
},
20203 struct arm_long_option_table
20205 char * option
; /* Substring to match. */
20206 char * help
; /* Help information. */
20207 int (* func
) (char * subopt
); /* Function to decode sub-option. */
20208 char * deprecated
; /* If non-null, print this message. */
20212 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
20214 arm_feature_set
*ext_set
= xmalloc (sizeof (arm_feature_set
));
20216 /* Copy the feature set, so that we can modify it. */
20217 *ext_set
= **opt_p
;
20220 while (str
!= NULL
&& *str
!= 0)
20222 const struct arm_option_cpu_value_table
* opt
;
20228 as_bad (_("invalid architectural extension"));
20233 ext
= strchr (str
, '+');
20236 optlen
= ext
- str
;
20238 optlen
= strlen (str
);
20242 as_bad (_("missing architectural extension"));
20246 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
20247 if (strncmp (opt
->name
, str
, optlen
) == 0)
20249 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
20253 if (opt
->name
== NULL
)
20255 as_bad (_("unknown architectural extnsion `%s'"), str
);
20266 arm_parse_cpu (char * str
)
20268 const struct arm_cpu_option_table
* opt
;
20269 char * ext
= strchr (str
, '+');
20273 optlen
= ext
- str
;
20275 optlen
= strlen (str
);
20279 as_bad (_("missing cpu name `%s'"), str
);
20283 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
20284 if (strncmp (opt
->name
, str
, optlen
) == 0)
20286 mcpu_cpu_opt
= &opt
->value
;
20287 mcpu_fpu_opt
= &opt
->default_fpu
;
20288 if (opt
->canonical_name
)
20289 strcpy(selected_cpu_name
, opt
->canonical_name
);
20293 for (i
= 0; i
< optlen
; i
++)
20294 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20295 selected_cpu_name
[i
] = 0;
20299 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
20304 as_bad (_("unknown cpu `%s'"), str
);
20309 arm_parse_arch (char * str
)
20311 const struct arm_arch_option_table
*opt
;
20312 char *ext
= strchr (str
, '+');
20316 optlen
= ext
- str
;
20318 optlen
= strlen (str
);
20322 as_bad (_("missing architecture name `%s'"), str
);
20326 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
20327 if (streq (opt
->name
, str
))
20329 march_cpu_opt
= &opt
->value
;
20330 march_fpu_opt
= &opt
->default_fpu
;
20331 strcpy(selected_cpu_name
, opt
->name
);
20334 return arm_parse_extension (ext
, &march_cpu_opt
);
20339 as_bad (_("unknown architecture `%s'\n"), str
);
20344 arm_parse_fpu (char * str
)
20346 const struct arm_option_cpu_value_table
* opt
;
20348 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
20349 if (streq (opt
->name
, str
))
20351 mfpu_opt
= &opt
->value
;
20355 as_bad (_("unknown floating point format `%s'\n"), str
);
20360 arm_parse_float_abi (char * str
)
20362 const struct arm_option_value_table
* opt
;
20364 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
20365 if (streq (opt
->name
, str
))
20367 mfloat_abi_opt
= opt
->value
;
20371 as_bad (_("unknown floating point abi `%s'\n"), str
);
20377 arm_parse_eabi (char * str
)
20379 const struct arm_option_value_table
*opt
;
20381 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
20382 if (streq (opt
->name
, str
))
20384 meabi_flags
= opt
->value
;
20387 as_bad (_("unknown EABI `%s'\n"), str
);
20392 struct arm_long_option_table arm_long_opts
[] =
20394 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
20395 arm_parse_cpu
, NULL
},
20396 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
20397 arm_parse_arch
, NULL
},
20398 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
20399 arm_parse_fpu
, NULL
},
20400 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
20401 arm_parse_float_abi
, NULL
},
20403 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
20404 arm_parse_eabi
, NULL
},
20406 {NULL
, NULL
, 0, NULL
}
20410 md_parse_option (int c
, char * arg
)
20412 struct arm_option_table
*opt
;
20413 const struct arm_legacy_option_table
*fopt
;
20414 struct arm_long_option_table
*lopt
;
20420 target_big_endian
= 1;
20426 target_big_endian
= 0;
20431 /* Listing option. Just ignore these, we don't support additional
20436 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
20438 if (c
== opt
->option
[0]
20439 && ((arg
== NULL
&& opt
->option
[1] == 0)
20440 || streq (arg
, opt
->option
+ 1)))
20442 #if WARN_DEPRECATED
20443 /* If the option is deprecated, tell the user. */
20444 if (opt
->deprecated
!= NULL
)
20445 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
20446 arg
? arg
: "", _(opt
->deprecated
));
20449 if (opt
->var
!= NULL
)
20450 *opt
->var
= opt
->value
;
20456 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
20458 if (c
== fopt
->option
[0]
20459 && ((arg
== NULL
&& fopt
->option
[1] == 0)
20460 || streq (arg
, fopt
->option
+ 1)))
20462 #if WARN_DEPRECATED
20463 /* If the option is deprecated, tell the user. */
20464 if (fopt
->deprecated
!= NULL
)
20465 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
20466 arg
? arg
: "", _(fopt
->deprecated
));
20469 if (fopt
->var
!= NULL
)
20470 *fopt
->var
= &fopt
->value
;
20476 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
20478 /* These options are expected to have an argument. */
20479 if (c
== lopt
->option
[0]
20481 && strncmp (arg
, lopt
->option
+ 1,
20482 strlen (lopt
->option
+ 1)) == 0)
20484 #if WARN_DEPRECATED
20485 /* If the option is deprecated, tell the user. */
20486 if (lopt
->deprecated
!= NULL
)
20487 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
20488 _(lopt
->deprecated
));
20491 /* Call the sup-option parser. */
20492 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
20503 md_show_usage (FILE * fp
)
20505 struct arm_option_table
*opt
;
20506 struct arm_long_option_table
*lopt
;
20508 fprintf (fp
, _(" ARM-specific assembler options:\n"));
20510 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
20511 if (opt
->help
!= NULL
)
20512 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
20514 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
20515 if (lopt
->help
!= NULL
)
20516 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
20520 -EB assemble code for a big-endian cpu\n"));
20525 -EL assemble code for a little-endian cpu\n"));
20534 arm_feature_set flags
;
20535 } cpu_arch_ver_table
;
20537 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
20538 least features first. */
20539 static const cpu_arch_ver_table cpu_arch_ver
[] =
20544 {4, ARM_ARCH_V5TE
},
20545 {5, ARM_ARCH_V5TEJ
},
20549 {9, ARM_ARCH_V6T2
},
20550 {10, ARM_ARCH_V7A
},
20551 {10, ARM_ARCH_V7R
},
20552 {10, ARM_ARCH_V7M
},
20556 /* Set the public EABI object attributes. */
20558 aeabi_set_public_attributes (void)
20561 arm_feature_set flags
;
20562 arm_feature_set tmp
;
20563 const cpu_arch_ver_table
*p
;
20565 /* Choose the architecture based on the capabilities of the requested cpu
20566 (if any) and/or the instructions actually used. */
20567 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
20568 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
20569 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
20570 /*Allow the user to override the reported architecture. */
20573 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
20574 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
20579 for (p
= cpu_arch_ver
; p
->val
; p
++)
20581 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
20584 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
20588 /* Tag_CPU_name. */
20589 if (selected_cpu_name
[0])
20593 p
= selected_cpu_name
;
20594 if (strncmp(p
, "armv", 4) == 0)
20599 for (i
= 0; p
[i
]; i
++)
20600 p
[i
] = TOUPPER (p
[i
]);
20602 elf32_arm_add_eabi_attr_string (stdoutput
, 5, p
);
20604 /* Tag_CPU_arch. */
20605 elf32_arm_add_eabi_attr_int (stdoutput
, 6, arch
);
20606 /* Tag_CPU_arch_profile. */
20607 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
20608 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'A');
20609 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
20610 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'R');
20611 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
))
20612 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'M');
20613 /* Tag_ARM_ISA_use. */
20614 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_full
))
20615 elf32_arm_add_eabi_attr_int (stdoutput
, 8, 1);
20616 /* Tag_THUMB_ISA_use. */
20617 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_full
))
20618 elf32_arm_add_eabi_attr_int (stdoutput
, 9,
20619 ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
) ? 2 : 1);
20620 /* Tag_VFP_arch. */
20621 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v3
)
20622 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v3
))
20623 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 3);
20624 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v2
)
20625 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v2
))
20626 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 2);
20627 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1
)
20628 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1
)
20629 || ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1xd
)
20630 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1xd
))
20631 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 1);
20632 /* Tag_WMMX_arch. */
20633 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_cext_iwmmxt
)
20634 || ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_cext_iwmmxt
))
20635 elf32_arm_add_eabi_attr_int (stdoutput
, 11, 1);
20636 /* Tag_NEON_arch. */
20637 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_neon_ext_v1
)
20638 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_neon_ext_v1
))
20639 elf32_arm_add_eabi_attr_int (stdoutput
, 12, 1);
20642 /* Add the .ARM.attributes section. */
20651 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
20654 aeabi_set_public_attributes ();
20655 size
= elf32_arm_eabi_attr_size (stdoutput
);
20656 s
= subseg_new (".ARM.attributes", 0);
20657 bfd_set_section_flags (stdoutput
, s
, SEC_READONLY
| SEC_DATA
);
20658 addr
= frag_now_fix ();
20659 p
= frag_more (size
);
20660 elf32_arm_set_eabi_attr_contents (stdoutput
, (bfd_byte
*)p
, size
);
20662 #endif /* OBJ_ELF */
20665 /* Parse a .cpu directive. */
20668 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
20670 const struct arm_cpu_option_table
*opt
;
20674 name
= input_line_pointer
;
20675 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20676 input_line_pointer
++;
20677 saved_char
= *input_line_pointer
;
20678 *input_line_pointer
= 0;
20680 /* Skip the first "all" entry. */
20681 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
20682 if (streq (opt
->name
, name
))
20684 mcpu_cpu_opt
= &opt
->value
;
20685 selected_cpu
= opt
->value
;
20686 if (opt
->canonical_name
)
20687 strcpy(selected_cpu_name
, opt
->canonical_name
);
20691 for (i
= 0; opt
->name
[i
]; i
++)
20692 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20693 selected_cpu_name
[i
] = 0;
20695 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20696 *input_line_pointer
= saved_char
;
20697 demand_empty_rest_of_line ();
20700 as_bad (_("unknown cpu `%s'"), name
);
20701 *input_line_pointer
= saved_char
;
20702 ignore_rest_of_line ();
20706 /* Parse a .arch directive. */
20709 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
20711 const struct arm_arch_option_table
*opt
;
20715 name
= input_line_pointer
;
20716 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20717 input_line_pointer
++;
20718 saved_char
= *input_line_pointer
;
20719 *input_line_pointer
= 0;
20721 /* Skip the first "all" entry. */
20722 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
20723 if (streq (opt
->name
, name
))
20725 mcpu_cpu_opt
= &opt
->value
;
20726 selected_cpu
= opt
->value
;
20727 strcpy(selected_cpu_name
, opt
->name
);
20728 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20729 *input_line_pointer
= saved_char
;
20730 demand_empty_rest_of_line ();
20734 as_bad (_("unknown architecture `%s'\n"), name
);
20735 *input_line_pointer
= saved_char
;
20736 ignore_rest_of_line ();
20740 /* Parse a .object_arch directive. */
20743 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
20745 const struct arm_arch_option_table
*opt
;
20749 name
= input_line_pointer
;
20750 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20751 input_line_pointer
++;
20752 saved_char
= *input_line_pointer
;
20753 *input_line_pointer
= 0;
20755 /* Skip the first "all" entry. */
20756 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
20757 if (streq (opt
->name
, name
))
20759 object_arch
= &opt
->value
;
20760 *input_line_pointer
= saved_char
;
20761 demand_empty_rest_of_line ();
20765 as_bad (_("unknown architecture `%s'\n"), name
);
20766 *input_line_pointer
= saved_char
;
20767 ignore_rest_of_line ();
20771 /* Parse a .fpu directive. */
20774 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
20776 const struct arm_option_cpu_value_table
*opt
;
20780 name
= input_line_pointer
;
20781 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20782 input_line_pointer
++;
20783 saved_char
= *input_line_pointer
;
20784 *input_line_pointer
= 0;
20786 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
20787 if (streq (opt
->name
, name
))
20789 mfpu_opt
= &opt
->value
;
20790 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20791 *input_line_pointer
= saved_char
;
20792 demand_empty_rest_of_line ();
20796 as_bad (_("unknown floating point format `%s'\n"), name
);
20797 *input_line_pointer
= saved_char
;
20798 ignore_rest_of_line ();
20801 /* Copy symbol information. */
20803 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
20805 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);