1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dwarf2dbg.h"
41 #include "dw2gencfi.h"
44 /* XXX Set this to 1 after the next binutils release. */
45 #define WARN_DEPRECATED 0
48 /* Must be at least the size of the largest unwind opcode (currently two). */
49 #define ARM_OPCODE_CHUNK_SIZE 8
51 /* This structure holds the unwinding state. */
56 symbolS
* table_entry
;
57 symbolS
* personality_routine
;
58 int personality_index
;
59 /* The segment containing the function. */
62 /* Opcodes generated from this function. */
63 unsigned char * opcodes
;
66 /* The number of bytes pushed to the stack. */
68 /* We don't add stack adjustment opcodes immediately so that we can merge
69 multiple adjustments. We can also omit the final adjustment
70 when using a frame pointer. */
71 offsetT pending_offset
;
72 /* These two fields are set by both unwind_movsp and unwind_setfp. They
73 hold the reg+offset to use when restoring sp from a frame pointer. */
76 /* Nonzero if an unwind_setfp directive has been seen. */
78 /* Nonzero if the last opcode restores sp from fp_reg. */
79 unsigned sp_restored
:1;
82 /* Bit N indicates that an R_ARM_NONE relocation has been output for
83 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
84 emitted only once per section, to save unnecessary bloat. */
85 static unsigned int marked_pr_dependency
= 0;
89 /* Results from operand parsing worker functions. */
93 PARSE_OPERAND_SUCCESS
,
95 PARSE_OPERAND_FAIL_NO_BACKTRACK
96 } parse_operand_result
;
101 ARM_FLOAT_ABI_SOFTFP
,
105 /* Types of processor to assemble for. */
107 #if defined __XSCALE__
108 #define CPU_DEFAULT ARM_ARCH_XSCALE
110 #if defined __thumb__
111 #define CPU_DEFAULT ARM_ARCH_V5T
118 # define FPU_DEFAULT FPU_ARCH_FPA
119 # elif defined (TE_NetBSD)
121 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
123 /* Legacy a.out format. */
124 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
126 # elif defined (TE_VXWORKS)
127 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
129 /* For backwards compatibility, default to FPA. */
130 # define FPU_DEFAULT FPU_ARCH_FPA
132 #endif /* ifndef FPU_DEFAULT */
134 #define streq(a, b) (strcmp (a, b) == 0)
136 static arm_feature_set cpu_variant
;
137 static arm_feature_set arm_arch_used
;
138 static arm_feature_set thumb_arch_used
;
140 /* Flags stored in private area of BFD structure. */
141 static int uses_apcs_26
= FALSE
;
142 static int atpcs
= FALSE
;
143 static int support_interwork
= FALSE
;
144 static int uses_apcs_float
= FALSE
;
145 static int pic_code
= FALSE
;
147 /* Variables that we set while parsing command-line options. Once all
148 options have been read we re-process these values to set the real
150 static const arm_feature_set
*legacy_cpu
= NULL
;
151 static const arm_feature_set
*legacy_fpu
= NULL
;
153 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
154 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
155 static const arm_feature_set
*march_cpu_opt
= NULL
;
156 static const arm_feature_set
*march_fpu_opt
= NULL
;
157 static const arm_feature_set
*mfpu_opt
= NULL
;
159 /* Constants for known architecture features. */
160 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
161 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
162 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
163 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
164 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
165 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
166 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
167 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
168 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
171 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
174 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
175 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
176 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
177 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
178 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
179 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
180 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
181 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
182 static const arm_feature_set arm_ext_v4t_5
=
183 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
184 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
185 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
186 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
187 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
188 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
189 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
190 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
191 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
192 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
199 static const arm_feature_set arm_arch_any
= ARM_ANY
;
200 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
201 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
202 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
204 static const arm_feature_set arm_cext_iwmmxt
=
205 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
206 static const arm_feature_set arm_cext_xscale
=
207 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
208 static const arm_feature_set arm_cext_maverick
=
209 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
210 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
211 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
212 static const arm_feature_set fpu_vfp_ext_v1xd
=
213 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
214 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
215 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
216 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
217 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
218 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
219 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
221 static int mfloat_abi_opt
= -1;
222 /* Record user cpu selection for object attributes. */
223 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
224 /* Must be long enough to hold any of the names in arm_cpus. */
225 static char selected_cpu_name
[16];
228 static int meabi_flags
= EABI_DEFAULT
;
230 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
235 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
236 symbolS
* GOT_symbol
;
239 /* 0: assemble for ARM,
240 1: assemble for Thumb,
241 2: assemble for Thumb even though target CPU does not support thumb
243 static int thumb_mode
= 0;
245 /* If unified_syntax is true, we are processing the new unified
246 ARM/Thumb syntax. Important differences from the old ARM mode:
248 - Immediate operands do not require a # prefix.
249 - Conditional affixes always appear at the end of the
250 instruction. (For backward compatibility, those instructions
251 that formerly had them in the middle, continue to accept them
253 - The IT instruction may appear, and if it does is validated
254 against subsequent conditional affixes. It does not generate
257 Important differences from the old Thumb mode:
259 - Immediate operands do not require a # prefix.
260 - Most of the V6T2 instructions are only available in unified mode.
261 - The .N and .W suffixes are recognized and honored (it is an error
262 if they cannot be honored).
263 - All instructions set the flags if and only if they have an 's' affix.
264 - Conditional affixes may be used. They are validated against
265 preceding IT instructions. Unlike ARM mode, you cannot use a
266 conditional affix except in the scope of an IT instruction. */
268 static bfd_boolean unified_syntax
= FALSE
;
283 enum neon_el_type type
;
287 #define NEON_MAX_TYPE_ELS 4
291 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
298 unsigned long instruction
;
302 /* "uncond_value" is set to the value in place of the conditional field in
303 unconditional versions of the instruction, or -1 if nothing is
306 struct neon_type vectype
;
307 /* Set to the opcode if the instruction needs relaxation.
308 Zero if the instruction is not relaxed. */
312 bfd_reloc_code_real_type type
;
321 struct neon_type_el vectype
;
322 unsigned present
: 1; /* Operand present. */
323 unsigned isreg
: 1; /* Operand was a register. */
324 unsigned immisreg
: 1; /* .imm field is a second register. */
325 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
326 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
327 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
328 instructions. This allows us to disambiguate ARM <-> vector insns. */
329 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
330 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
331 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
332 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
333 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
334 unsigned writeback
: 1; /* Operand has trailing ! */
335 unsigned preind
: 1; /* Preindexed address. */
336 unsigned postind
: 1; /* Postindexed address. */
337 unsigned negative
: 1; /* Index register was negated. */
338 unsigned shifted
: 1; /* Shift applied to operation. */
339 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
343 static struct arm_it inst
;
345 #define NUM_FLOAT_VALS 8
347 const char * fp_const
[] =
349 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
352 /* Number of littlenums required to hold an extended precision number. */
353 #define MAX_LITTLENUMS 6
355 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
365 #define CP_T_X 0x00008000
366 #define CP_T_Y 0x00400000
368 #define CONDS_BIT 0x00100000
369 #define LOAD_BIT 0x00100000
371 #define DOUBLE_LOAD_FLAG 0x00000001
375 const char * template;
379 #define COND_ALWAYS 0xE
383 const char *template;
387 struct asm_barrier_opt
389 const char *template;
393 /* The bit that distinguishes CPSR and SPSR. */
394 #define SPSR_BIT (1 << 22)
396 /* The individual PSR flag bits. */
397 #define PSR_c (1 << 16)
398 #define PSR_x (1 << 17)
399 #define PSR_s (1 << 18)
400 #define PSR_f (1 << 19)
405 bfd_reloc_code_real_type reloc
;
410 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
411 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
416 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
419 /* Bits for DEFINED field in neon_typed_alias. */
420 #define NTA_HASTYPE 1
421 #define NTA_HASINDEX 2
423 struct neon_typed_alias
425 unsigned char defined
;
427 struct neon_type_el eltype
;
430 /* ARM register categories. This includes coprocessor numbers and various
431 architecture extensions' registers. */
457 /* Structure for a hash table entry for a register.
458 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
459 information which states whether a vector type or index is specified (for a
460 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
464 unsigned char number
;
466 unsigned char builtin
;
467 struct neon_typed_alias
*neon
;
470 /* Diagnostics used when we don't get a register of the expected type. */
471 const char *const reg_expected_msgs
[] =
473 N_("ARM register expected"),
474 N_("bad or missing co-processor number"),
475 N_("co-processor register expected"),
476 N_("FPA register expected"),
477 N_("VFP single precision register expected"),
478 N_("VFP/Neon double precision register expected"),
479 N_("Neon quad precision register expected"),
480 N_("VFP single or double precision register expected"),
481 N_("Neon double or quad precision register expected"),
482 N_("VFP single, double or Neon quad precision register expected"),
483 N_("VFP system register expected"),
484 N_("Maverick MVF register expected"),
485 N_("Maverick MVD register expected"),
486 N_("Maverick MVFX register expected"),
487 N_("Maverick MVDX register expected"),
488 N_("Maverick MVAX register expected"),
489 N_("Maverick DSPSC register expected"),
490 N_("iWMMXt data register expected"),
491 N_("iWMMXt control register expected"),
492 N_("iWMMXt scalar register expected"),
493 N_("XScale accumulator register expected"),
496 /* Some well known registers that we refer to directly elsewhere. */
501 /* ARM instructions take 4bytes in the object file, Thumb instructions
507 /* Basic string to match. */
508 const char *template;
510 /* Parameters to instruction. */
511 unsigned char operands
[8];
513 /* Conditional tag - see opcode_lookup. */
514 unsigned int tag
: 4;
516 /* Basic instruction code. */
517 unsigned int avalue
: 28;
519 /* Thumb-format instruction code. */
522 /* Which architecture variant provides this instruction. */
523 const arm_feature_set
*avariant
;
524 const arm_feature_set
*tvariant
;
526 /* Function to call to encode instruction in ARM format. */
527 void (* aencode
) (void);
529 /* Function to call to encode instruction in Thumb format. */
530 void (* tencode
) (void);
533 /* Defines for various bits that we will want to toggle. */
534 #define INST_IMMEDIATE 0x02000000
535 #define OFFSET_REG 0x02000000
536 #define HWOFFSET_IMM 0x00400000
537 #define SHIFT_BY_REG 0x00000010
538 #define PRE_INDEX 0x01000000
539 #define INDEX_UP 0x00800000
540 #define WRITE_BACK 0x00200000
541 #define LDM_TYPE_2_OR_3 0x00400000
543 #define LITERAL_MASK 0xf000f000
544 #define OPCODE_MASK 0xfe1fffff
545 #define V4_STR_BIT 0x00000020
547 #define DATA_OP_SHIFT 21
549 #define T2_OPCODE_MASK 0xfe1fffff
550 #define T2_DATA_OP_SHIFT 21
552 /* Codes to distinguish the arithmetic instructions. */
563 #define OPCODE_CMP 10
564 #define OPCODE_CMN 11
565 #define OPCODE_ORR 12
566 #define OPCODE_MOV 13
567 #define OPCODE_BIC 14
568 #define OPCODE_MVN 15
570 #define T2_OPCODE_AND 0
571 #define T2_OPCODE_BIC 1
572 #define T2_OPCODE_ORR 2
573 #define T2_OPCODE_ORN 3
574 #define T2_OPCODE_EOR 4
575 #define T2_OPCODE_ADD 8
576 #define T2_OPCODE_ADC 10
577 #define T2_OPCODE_SBC 11
578 #define T2_OPCODE_SUB 13
579 #define T2_OPCODE_RSB 14
581 #define T_OPCODE_MUL 0x4340
582 #define T_OPCODE_TST 0x4200
583 #define T_OPCODE_CMN 0x42c0
584 #define T_OPCODE_NEG 0x4240
585 #define T_OPCODE_MVN 0x43c0
587 #define T_OPCODE_ADD_R3 0x1800
588 #define T_OPCODE_SUB_R3 0x1a00
589 #define T_OPCODE_ADD_HI 0x4400
590 #define T_OPCODE_ADD_ST 0xb000
591 #define T_OPCODE_SUB_ST 0xb080
592 #define T_OPCODE_ADD_SP 0xa800
593 #define T_OPCODE_ADD_PC 0xa000
594 #define T_OPCODE_ADD_I8 0x3000
595 #define T_OPCODE_SUB_I8 0x3800
596 #define T_OPCODE_ADD_I3 0x1c00
597 #define T_OPCODE_SUB_I3 0x1e00
599 #define T_OPCODE_ASR_R 0x4100
600 #define T_OPCODE_LSL_R 0x4080
601 #define T_OPCODE_LSR_R 0x40c0
602 #define T_OPCODE_ROR_R 0x41c0
603 #define T_OPCODE_ASR_I 0x1000
604 #define T_OPCODE_LSL_I 0x0000
605 #define T_OPCODE_LSR_I 0x0800
607 #define T_OPCODE_MOV_I8 0x2000
608 #define T_OPCODE_CMP_I8 0x2800
609 #define T_OPCODE_CMP_LR 0x4280
610 #define T_OPCODE_MOV_HR 0x4600
611 #define T_OPCODE_CMP_HR 0x4500
613 #define T_OPCODE_LDR_PC 0x4800
614 #define T_OPCODE_LDR_SP 0x9800
615 #define T_OPCODE_STR_SP 0x9000
616 #define T_OPCODE_LDR_IW 0x6800
617 #define T_OPCODE_STR_IW 0x6000
618 #define T_OPCODE_LDR_IH 0x8800
619 #define T_OPCODE_STR_IH 0x8000
620 #define T_OPCODE_LDR_IB 0x7800
621 #define T_OPCODE_STR_IB 0x7000
622 #define T_OPCODE_LDR_RW 0x5800
623 #define T_OPCODE_STR_RW 0x5000
624 #define T_OPCODE_LDR_RH 0x5a00
625 #define T_OPCODE_STR_RH 0x5200
626 #define T_OPCODE_LDR_RB 0x5c00
627 #define T_OPCODE_STR_RB 0x5400
629 #define T_OPCODE_PUSH 0xb400
630 #define T_OPCODE_POP 0xbc00
632 #define T_OPCODE_BRANCH 0xe000
634 #define THUMB_SIZE 2 /* Size of thumb instruction. */
635 #define THUMB_PP_PC_LR 0x0100
636 #define THUMB_LOAD_BIT 0x0800
637 #define THUMB2_LOAD_BIT 0x00100000
639 #define BAD_ARGS _("bad arguments to instruction")
640 #define BAD_PC _("r15 not allowed here")
641 #define BAD_COND _("instruction cannot be conditional")
642 #define BAD_OVERLAP _("registers may not be the same")
643 #define BAD_HIREG _("lo register required")
644 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
645 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
646 #define BAD_BRANCH _("branch must be last instruction in IT block")
647 #define BAD_NOT_IT _("instruction not allowed in IT block")
648 #define BAD_FPU _("selected FPU does not support instruction")
650 static struct hash_control
*arm_ops_hsh
;
651 static struct hash_control
*arm_cond_hsh
;
652 static struct hash_control
*arm_shift_hsh
;
653 static struct hash_control
*arm_psr_hsh
;
654 static struct hash_control
*arm_v7m_psr_hsh
;
655 static struct hash_control
*arm_reg_hsh
;
656 static struct hash_control
*arm_reloc_hsh
;
657 static struct hash_control
*arm_barrier_opt_hsh
;
659 /* Stuff needed to resolve the label ambiguity
669 symbolS
* last_label_seen
;
670 static int label_is_thumb_function_name
= FALSE
;
672 /* Literal pool structure. Held on a per-section
673 and per-sub-section basis. */
675 #define MAX_LITERAL_POOL_SIZE 1024
676 typedef struct literal_pool
678 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
679 unsigned int next_free_entry
;
684 struct literal_pool
* next
;
687 /* Pointer to a linked list of literal pools. */
688 literal_pool
* list_of_pools
= NULL
;
690 /* State variables for IT block handling. */
691 static bfd_boolean current_it_mask
= 0;
692 static int current_cc
;
697 /* This array holds the chars that always start a comment. If the
698 pre-processor is disabled, these aren't very useful. */
699 const char comment_chars
[] = "@";
701 /* This array holds the chars that only start a comment at the beginning of
702 a line. If the line seems to have the form '# 123 filename'
703 .line and .file directives will appear in the pre-processed output. */
704 /* Note that input_file.c hand checks for '#' at the beginning of the
705 first line of the input file. This is because the compiler outputs
706 #NO_APP at the beginning of its output. */
707 /* Also note that comments like this one will always work. */
708 const char line_comment_chars
[] = "#";
710 const char line_separator_chars
[] = ";";
712 /* Chars that can be used to separate mant
713 from exp in floating point numbers. */
714 const char EXP_CHARS
[] = "eE";
716 /* Chars that mean this number is a floating point constant. */
720 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
722 /* Prefix characters that indicate the start of an immediate
724 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
726 /* Separator character handling. */
728 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
731 skip_past_char (char ** str
, char c
)
741 #define skip_past_comma(str) skip_past_char (str, ',')
743 /* Arithmetic expressions (possibly involving symbols). */
745 /* Return TRUE if anything in the expression is a bignum. */
748 walk_no_bignums (symbolS
* sp
)
750 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
753 if (symbol_get_value_expression (sp
)->X_add_symbol
)
755 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
756 || (symbol_get_value_expression (sp
)->X_op_symbol
757 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
763 static int in_my_get_expression
= 0;
765 /* Third argument to my_get_expression. */
766 #define GE_NO_PREFIX 0
767 #define GE_IMM_PREFIX 1
768 #define GE_OPT_PREFIX 2
769 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
770 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
771 #define GE_OPT_PREFIX_BIG 3
774 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
779 /* In unified syntax, all prefixes are optional. */
781 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
786 case GE_NO_PREFIX
: break;
788 if (!is_immediate_prefix (**str
))
790 inst
.error
= _("immediate expression requires a # prefix");
796 case GE_OPT_PREFIX_BIG
:
797 if (is_immediate_prefix (**str
))
803 memset (ep
, 0, sizeof (expressionS
));
805 save_in
= input_line_pointer
;
806 input_line_pointer
= *str
;
807 in_my_get_expression
= 1;
808 seg
= expression (ep
);
809 in_my_get_expression
= 0;
811 if (ep
->X_op
== O_illegal
)
813 /* We found a bad expression in md_operand(). */
814 *str
= input_line_pointer
;
815 input_line_pointer
= save_in
;
816 if (inst
.error
== NULL
)
817 inst
.error
= _("bad expression");
822 if (seg
!= absolute_section
823 && seg
!= text_section
824 && seg
!= data_section
825 && seg
!= bss_section
826 && seg
!= undefined_section
)
828 inst
.error
= _("bad segment");
829 *str
= input_line_pointer
;
830 input_line_pointer
= save_in
;
835 /* Get rid of any bignums now, so that we don't generate an error for which
836 we can't establish a line number later on. Big numbers are never valid
837 in instructions, which is where this routine is always called. */
838 if (prefix_mode
!= GE_OPT_PREFIX_BIG
839 && (ep
->X_op
== O_big
841 && (walk_no_bignums (ep
->X_add_symbol
)
843 && walk_no_bignums (ep
->X_op_symbol
))))))
845 inst
.error
= _("invalid constant");
846 *str
= input_line_pointer
;
847 input_line_pointer
= save_in
;
851 *str
= input_line_pointer
;
852 input_line_pointer
= save_in
;
856 /* Turn a string in input_line_pointer into a floating point constant
857 of type TYPE, and store the appropriate bytes in *LITP. The number
858 of LITTLENUMS emitted is stored in *SIZEP. An error message is
859 returned, or NULL on OK.
861 Note that fp constants aren't represent in the normal way on the ARM.
862 In big endian mode, things are as expected. However, in little endian
863 mode fp constants are big-endian word-wise, and little-endian byte-wise
864 within the words. For example, (double) 1.1 in big endian mode is
865 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
866 the byte sequence 99 99 f1 3f 9a 99 99 99.
868 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
871 md_atof (int type
, char * litP
, int * sizeP
)
874 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
906 return _("bad call to MD_ATOF()");
909 t
= atof_ieee (input_line_pointer
, type
, words
);
911 input_line_pointer
= t
;
914 if (target_big_endian
)
916 for (i
= 0; i
< prec
; i
++)
918 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
924 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
925 for (i
= prec
- 1; i
>= 0; i
--)
927 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
931 /* For a 4 byte float the order of elements in `words' is 1 0.
932 For an 8 byte float the order is 1 0 3 2. */
933 for (i
= 0; i
< prec
; i
+= 2)
935 md_number_to_chars (litP
, (valueT
) words
[i
+ 1], 2);
936 md_number_to_chars (litP
+ 2, (valueT
) words
[i
], 2);
944 /* We handle all bad expressions here, so that we can report the faulty
945 instruction in the error message. */
947 md_operand (expressionS
* expr
)
949 if (in_my_get_expression
)
950 expr
->X_op
= O_illegal
;
953 /* Immediate values. */
955 /* Generic immediate-value read function for use in directives.
956 Accepts anything that 'expression' can fold to a constant.
957 *val receives the number. */
960 immediate_for_directive (int *val
)
963 exp
.X_op
= O_illegal
;
965 if (is_immediate_prefix (*input_line_pointer
))
967 input_line_pointer
++;
971 if (exp
.X_op
!= O_constant
)
973 as_bad (_("expected #constant"));
974 ignore_rest_of_line ();
977 *val
= exp
.X_add_number
;
982 /* Register parsing. */
984 /* Generic register parser. CCP points to what should be the
985 beginning of a register name. If it is indeed a valid register
986 name, advance CCP over it and return the reg_entry structure;
987 otherwise return NULL. Does not issue diagnostics. */
989 static struct reg_entry
*
990 arm_reg_parse_multi (char **ccp
)
994 struct reg_entry
*reg
;
996 #ifdef REGISTER_PREFIX
997 if (*start
!= REGISTER_PREFIX
)
1001 #ifdef OPTIONAL_REGISTER_PREFIX
1002 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1007 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1012 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1014 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1024 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1025 enum arm_reg_type type
)
1027 /* Alternative syntaxes are accepted for a few register classes. */
1034 /* Generic coprocessor register names are allowed for these. */
1035 if (reg
&& reg
->type
== REG_TYPE_CN
)
1040 /* For backward compatibility, a bare number is valid here. */
1042 unsigned long processor
= strtoul (start
, ccp
, 10);
1043 if (*ccp
!= start
&& processor
<= 15)
1047 case REG_TYPE_MMXWC
:
1048 /* WC includes WCG. ??? I'm not sure this is true for all
1049 instructions that take WC registers. */
1050 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1061 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1062 return value is the register number or FAIL. */
1065 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1068 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1071 /* Do not allow a scalar (reg+index) to parse as a register. */
1072 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1075 if (reg
&& reg
->type
== type
)
1078 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1085 /* Parse a Neon type specifier. *STR should point at the leading '.'
1086 character. Does no verification at this stage that the type fits the opcode
1093 Can all be legally parsed by this function.
1095 Fills in neon_type struct pointer with parsed information, and updates STR
1096 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1097 type, FAIL if not. */
1100 parse_neon_type (struct neon_type
*type
, char **str
)
1107 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1109 enum neon_el_type thistype
= NT_untyped
;
1110 unsigned thissize
= -1u;
1117 /* Just a size without an explicit type. */
1121 switch (TOLOWER (*ptr
))
1123 case 'i': thistype
= NT_integer
; break;
1124 case 'f': thistype
= NT_float
; break;
1125 case 'p': thistype
= NT_poly
; break;
1126 case 's': thistype
= NT_signed
; break;
1127 case 'u': thistype
= NT_unsigned
; break;
1129 thistype
= NT_float
;
1134 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1140 /* .f is an abbreviation for .f32. */
1141 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1146 thissize
= strtoul (ptr
, &ptr
, 10);
1148 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1151 as_bad (_("bad size %d in type specifier"), thissize
);
1159 type
->el
[type
->elems
].type
= thistype
;
1160 type
->el
[type
->elems
].size
= thissize
;
1165 /* Empty/missing type is not a successful parse. */
1166 if (type
->elems
== 0)
1174 /* Errors may be set multiple times during parsing or bit encoding
1175 (particularly in the Neon bits), but usually the earliest error which is set
1176 will be the most meaningful. Avoid overwriting it with later (cascading)
1177 errors by calling this function. */
1180 first_error (const char *err
)
1186 /* Parse a single type, e.g. ".s32", leading period included. */
1188 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1191 struct neon_type optype
;
1195 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1197 if (optype
.elems
== 1)
1198 *vectype
= optype
.el
[0];
1201 first_error (_("only one type should be specified for operand"));
1207 first_error (_("vector type expected"));
1219 /* Special meanings for indices (which have a range of 0-7), which will fit into
1222 #define NEON_ALL_LANES 15
1223 #define NEON_INTERLEAVE_LANES 14
1225 /* Parse either a register or a scalar, with an optional type. Return the
1226 register number, and optionally fill in the actual type of the register
1227 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1228 type/index information in *TYPEINFO. */
1231 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1232 enum arm_reg_type
*rtype
,
1233 struct neon_typed_alias
*typeinfo
)
1236 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1237 struct neon_typed_alias atype
;
1238 struct neon_type_el parsetype
;
1242 atype
.eltype
.type
= NT_invtype
;
1243 atype
.eltype
.size
= -1;
1245 /* Try alternate syntax for some types of register. Note these are mutually
1246 exclusive with the Neon syntax extensions. */
1249 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1257 /* Undo polymorphism when a set of register types may be accepted. */
1258 if ((type
== REG_TYPE_NDQ
1259 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1260 || (type
== REG_TYPE_VFSD
1261 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1262 || (type
== REG_TYPE_NSDQ
1263 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1264 || reg
->type
== REG_TYPE_NQ
)))
1267 if (type
!= reg
->type
)
1273 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1275 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1277 first_error (_("can't redefine type for operand"));
1280 atype
.defined
|= NTA_HASTYPE
;
1281 atype
.eltype
= parsetype
;
1284 if (skip_past_char (&str
, '[') == SUCCESS
)
1286 if (type
!= REG_TYPE_VFD
)
1288 first_error (_("only D registers may be indexed"));
1292 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1294 first_error (_("can't change index for operand"));
1298 atype
.defined
|= NTA_HASINDEX
;
1300 if (skip_past_char (&str
, ']') == SUCCESS
)
1301 atype
.index
= NEON_ALL_LANES
;
1306 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1308 if (exp
.X_op
!= O_constant
)
1310 first_error (_("constant expression required"));
1314 if (skip_past_char (&str
, ']') == FAIL
)
1317 atype
.index
= exp
.X_add_number
;
1332 /* Like arm_reg_parse, but allow allow the following extra features:
1333 - If RTYPE is non-zero, return the (possibly restricted) type of the
1334 register (e.g. Neon double or quad reg when either has been requested).
1335 - If this is a Neon vector type with additional type information, fill
1336 in the struct pointed to by VECTYPE (if non-NULL).
1337 This function will fault on encountering a scalar.
1341 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1342 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1344 struct neon_typed_alias atype
;
1346 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1351 /* Do not allow a scalar (reg+index) to parse as a register. */
1352 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1354 first_error (_("register operand expected, but got scalar"));
1359 *vectype
= atype
.eltype
;
1366 #define NEON_SCALAR_REG(X) ((X) >> 4)
1367 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1369 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1370 have enough information to be able to do a good job bounds-checking. So, we
1371 just do easy checks here, and do further checks later. */
1374 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1378 struct neon_typed_alias atype
;
1380 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1382 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1385 if (atype
.index
== NEON_ALL_LANES
)
1387 first_error (_("scalar must have an index"));
1390 else if (atype
.index
>= 64 / elsize
)
1392 first_error (_("scalar index out of range"));
1397 *type
= atype
.eltype
;
1401 return reg
* 16 + atype
.index
;
1404 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1406 parse_reg_list (char ** strp
)
1408 char * str
= * strp
;
1412 /* We come back here if we get ranges concatenated by '+' or '|'. */
1427 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1429 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1439 first_error (_("bad range in register list"));
1443 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1445 if (range
& (1 << i
))
1447 (_("Warning: duplicated register (r%d) in register list"),
1455 if (range
& (1 << reg
))
1456 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1458 else if (reg
<= cur_reg
)
1459 as_tsktsk (_("Warning: register range not in ascending order"));
1464 while (skip_past_comma (&str
) != FAIL
1465 || (in_range
= 1, *str
++ == '-'));
1470 first_error (_("missing `}'"));
1478 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1481 if (expr
.X_op
== O_constant
)
1483 if (expr
.X_add_number
1484 != (expr
.X_add_number
& 0x0000ffff))
1486 inst
.error
= _("invalid register mask");
1490 if ((range
& expr
.X_add_number
) != 0)
1492 int regno
= range
& expr
.X_add_number
;
1495 regno
= (1 << regno
) - 1;
1497 (_("Warning: duplicated register (r%d) in register list"),
1501 range
|= expr
.X_add_number
;
1505 if (inst
.reloc
.type
!= 0)
1507 inst
.error
= _("expression too complex");
1511 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1512 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1513 inst
.reloc
.pc_rel
= 0;
1517 if (*str
== '|' || *str
== '+')
1523 while (another_range
);
1529 /* Types of registers in a list. */
1538 /* Parse a VFP register list. If the string is invalid return FAIL.
1539 Otherwise return the number of registers, and set PBASE to the first
1540 register. Parses registers of type ETYPE.
1541 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1542 - Q registers can be used to specify pairs of D registers
1543 - { } can be omitted from around a singleton register list
1544 FIXME: This is not implemented, as it would require backtracking in
1547 This could be done (the meaning isn't really ambiguous), but doesn't
1548 fit in well with the current parsing framework.
1549 - 32 D registers may be used (also true for VFPv3).
1550 FIXME: Types are ignored in these register lists, which is probably a
1554 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1559 enum arm_reg_type regtype
= 0;
1563 unsigned long mask
= 0;
1568 inst
.error
= _("expecting {");
1577 regtype
= REG_TYPE_VFS
;
1582 regtype
= REG_TYPE_VFD
;
1585 case REGLIST_NEON_D
:
1586 regtype
= REG_TYPE_NDQ
;
1590 if (etype
!= REGLIST_VFP_S
)
1592 /* VFPv3 allows 32 D registers. */
1593 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
1597 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1600 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1607 base_reg
= max_regs
;
1611 int setmask
= 1, addregs
= 1;
1613 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1615 if (new_base
== FAIL
)
1617 first_error (_(reg_expected_msgs
[regtype
]));
1621 if (new_base
>= max_regs
)
1623 first_error (_("register out of range in list"));
1627 /* Note: a value of 2 * n is returned for the register Q<n>. */
1628 if (regtype
== REG_TYPE_NQ
)
1634 if (new_base
< base_reg
)
1635 base_reg
= new_base
;
1637 if (mask
& (setmask
<< new_base
))
1639 first_error (_("invalid register list"));
1643 if ((mask
>> new_base
) != 0 && ! warned
)
1645 as_tsktsk (_("register list not in ascending order"));
1649 mask
|= setmask
<< new_base
;
1652 if (*str
== '-') /* We have the start of a range expression */
1658 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1661 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1665 if (high_range
>= max_regs
)
1667 first_error (_("register out of range in list"));
1671 if (regtype
== REG_TYPE_NQ
)
1672 high_range
= high_range
+ 1;
1674 if (high_range
<= new_base
)
1676 inst
.error
= _("register range not in ascending order");
1680 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1682 if (mask
& (setmask
<< new_base
))
1684 inst
.error
= _("invalid register list");
1688 mask
|= setmask
<< new_base
;
1693 while (skip_past_comma (&str
) != FAIL
);
1697 /* Sanity check -- should have raised a parse error above. */
1698 if (count
== 0 || count
> max_regs
)
1703 /* Final test -- the registers must be consecutive. */
1705 for (i
= 0; i
< count
; i
++)
1707 if ((mask
& (1u << i
)) == 0)
1709 inst
.error
= _("non-contiguous register range");
1719 /* True if two alias types are the same. */
1722 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1730 if (a
->defined
!= b
->defined
)
1733 if ((a
->defined
& NTA_HASTYPE
) != 0
1734 && (a
->eltype
.type
!= b
->eltype
.type
1735 || a
->eltype
.size
!= b
->eltype
.size
))
1738 if ((a
->defined
& NTA_HASINDEX
) != 0
1739 && (a
->index
!= b
->index
))
1745 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1746 The base register is put in *PBASE.
1747 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1749 The register stride (minus one) is put in bit 4 of the return value.
1750 Bits [6:5] encode the list length (minus one).
1751 The type of the list elements is put in *ELTYPE, if non-NULL. */
1753 #define NEON_LANE(X) ((X) & 0xf)
1754 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1755 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1758 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1759 struct neon_type_el
*eltype
)
1766 int leading_brace
= 0;
1767 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1769 const char *const incr_error
= "register stride must be 1 or 2";
1770 const char *const type_error
= "mismatched element/structure types in list";
1771 struct neon_typed_alias firsttype
;
1773 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1778 struct neon_typed_alias atype
;
1779 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1783 first_error (_(reg_expected_msgs
[rtype
]));
1790 if (rtype
== REG_TYPE_NQ
)
1797 else if (reg_incr
== -1)
1799 reg_incr
= getreg
- base_reg
;
1800 if (reg_incr
< 1 || reg_incr
> 2)
1802 first_error (_(incr_error
));
1806 else if (getreg
!= base_reg
+ reg_incr
* count
)
1808 first_error (_(incr_error
));
1812 if (!neon_alias_types_same (&atype
, &firsttype
))
1814 first_error (_(type_error
));
1818 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1822 struct neon_typed_alias htype
;
1823 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1825 lane
= NEON_INTERLEAVE_LANES
;
1826 else if (lane
!= NEON_INTERLEAVE_LANES
)
1828 first_error (_(type_error
));
1833 else if (reg_incr
!= 1)
1835 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1839 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1842 first_error (_(reg_expected_msgs
[rtype
]));
1845 if (!neon_alias_types_same (&htype
, &firsttype
))
1847 first_error (_(type_error
));
1850 count
+= hireg
+ dregs
- getreg
;
1854 /* If we're using Q registers, we can't use [] or [n] syntax. */
1855 if (rtype
== REG_TYPE_NQ
)
1861 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1865 else if (lane
!= atype
.index
)
1867 first_error (_(type_error
));
1871 else if (lane
== -1)
1872 lane
= NEON_INTERLEAVE_LANES
;
1873 else if (lane
!= NEON_INTERLEAVE_LANES
)
1875 first_error (_(type_error
));
1880 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1882 /* No lane set by [x]. We must be interleaving structures. */
1884 lane
= NEON_INTERLEAVE_LANES
;
1887 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
1888 || (count
> 1 && reg_incr
== -1))
1890 first_error (_("error parsing element/structure list"));
1894 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
1896 first_error (_("expected }"));
1904 *eltype
= firsttype
.eltype
;
1909 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
1912 /* Parse an explicit relocation suffix on an expression. This is
1913 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1914 arm_reloc_hsh contains no entries, so this function can only
1915 succeed if there is no () after the word. Returns -1 on error,
1916 BFD_RELOC_UNUSED if there wasn't any suffix. */
1918 parse_reloc (char **str
)
1920 struct reloc_entry
*r
;
1924 return BFD_RELOC_UNUSED
;
1929 while (*q
&& *q
!= ')' && *q
!= ',')
1934 if ((r
= hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
1941 /* Directives: register aliases. */
1943 static struct reg_entry
*
1944 insert_reg_alias (char *str
, int number
, int type
)
1946 struct reg_entry
*new;
1949 if ((new = hash_find (arm_reg_hsh
, str
)) != 0)
1952 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
1954 /* Only warn about a redefinition if it's not defined as the
1956 else if (new->number
!= number
|| new->type
!= type
)
1957 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1962 name
= xstrdup (str
);
1963 new = xmalloc (sizeof (struct reg_entry
));
1966 new->number
= number
;
1968 new->builtin
= FALSE
;
1971 if (hash_insert (arm_reg_hsh
, name
, (PTR
) new))
1978 insert_neon_reg_alias (char *str
, int number
, int type
,
1979 struct neon_typed_alias
*atype
)
1981 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
1985 first_error (_("attempt to redefine typed alias"));
1991 reg
->neon
= xmalloc (sizeof (struct neon_typed_alias
));
1992 *reg
->neon
= *atype
;
1996 /* Look for the .req directive. This is of the form:
1998 new_register_name .req existing_register_name
2000 If we find one, or if it looks sufficiently like one that we want to
2001 handle any error here, return non-zero. Otherwise return zero. */
2004 create_register_alias (char * newname
, char *p
)
2006 struct reg_entry
*old
;
2007 char *oldname
, *nbuf
;
2010 /* The input scrubber ensures that whitespace after the mnemonic is
2011 collapsed to single spaces. */
2013 if (strncmp (oldname
, " .req ", 6) != 0)
2017 if (*oldname
== '\0')
2020 old
= hash_find (arm_reg_hsh
, oldname
);
2023 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2027 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2028 the desired alias name, and p points to its end. If not, then
2029 the desired alias name is in the global original_case_string. */
2030 #ifdef TC_CASE_SENSITIVE
2033 newname
= original_case_string
;
2034 nlen
= strlen (newname
);
2037 nbuf
= alloca (nlen
+ 1);
2038 memcpy (nbuf
, newname
, nlen
);
2041 /* Create aliases under the new name as stated; an all-lowercase
2042 version of the new name; and an all-uppercase version of the new
2044 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2046 for (p
= nbuf
; *p
; p
++)
2049 if (strncmp (nbuf
, newname
, nlen
))
2050 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2052 for (p
= nbuf
; *p
; p
++)
2055 if (strncmp (nbuf
, newname
, nlen
))
2056 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2061 /* Create a Neon typed/indexed register alias using directives, e.g.:
2066 These typed registers can be used instead of the types specified after the
2067 Neon mnemonic, so long as all operands given have types. Types can also be
2068 specified directly, e.g.:
2069 vadd d0.s32, d1.s32, d2.s32
2073 create_neon_reg_alias (char *newname
, char *p
)
2075 enum arm_reg_type basetype
;
2076 struct reg_entry
*basereg
;
2077 struct reg_entry mybasereg
;
2078 struct neon_type ntype
;
2079 struct neon_typed_alias typeinfo
;
2080 char *namebuf
, *nameend
;
2083 typeinfo
.defined
= 0;
2084 typeinfo
.eltype
.type
= NT_invtype
;
2085 typeinfo
.eltype
.size
= -1;
2086 typeinfo
.index
= -1;
2090 if (strncmp (p
, " .dn ", 5) == 0)
2091 basetype
= REG_TYPE_VFD
;
2092 else if (strncmp (p
, " .qn ", 5) == 0)
2093 basetype
= REG_TYPE_NQ
;
2102 basereg
= arm_reg_parse_multi (&p
);
2104 if (basereg
&& basereg
->type
!= basetype
)
2106 as_bad (_("bad type for register"));
2110 if (basereg
== NULL
)
2113 /* Try parsing as an integer. */
2114 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2115 if (exp
.X_op
!= O_constant
)
2117 as_bad (_("expression must be constant"));
2120 basereg
= &mybasereg
;
2121 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2127 typeinfo
= *basereg
->neon
;
2129 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2131 /* We got a type. */
2132 if (typeinfo
.defined
& NTA_HASTYPE
)
2134 as_bad (_("can't redefine the type of a register alias"));
2138 typeinfo
.defined
|= NTA_HASTYPE
;
2139 if (ntype
.elems
!= 1)
2141 as_bad (_("you must specify a single type only"));
2144 typeinfo
.eltype
= ntype
.el
[0];
2147 if (skip_past_char (&p
, '[') == SUCCESS
)
2150 /* We got a scalar index. */
2152 if (typeinfo
.defined
& NTA_HASINDEX
)
2154 as_bad (_("can't redefine the index of a scalar alias"));
2158 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2160 if (exp
.X_op
!= O_constant
)
2162 as_bad (_("scalar index must be constant"));
2166 typeinfo
.defined
|= NTA_HASINDEX
;
2167 typeinfo
.index
= exp
.X_add_number
;
2169 if (skip_past_char (&p
, ']') == FAIL
)
2171 as_bad (_("expecting ]"));
2176 namelen
= nameend
- newname
;
2177 namebuf
= alloca (namelen
+ 1);
2178 strncpy (namebuf
, newname
, namelen
);
2179 namebuf
[namelen
] = '\0';
2181 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2182 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2184 /* Insert name in all uppercase. */
2185 for (p
= namebuf
; *p
; p
++)
2188 if (strncmp (namebuf
, newname
, namelen
))
2189 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2190 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2192 /* Insert name in all lowercase. */
2193 for (p
= namebuf
; *p
; p
++)
2196 if (strncmp (namebuf
, newname
, namelen
))
2197 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2198 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2203 /* Should never be called, as .req goes between the alias and the
2204 register name, not at the beginning of the line. */
2206 s_req (int a ATTRIBUTE_UNUSED
)
2208 as_bad (_("invalid syntax for .req directive"));
2212 s_dn (int a ATTRIBUTE_UNUSED
)
2214 as_bad (_("invalid syntax for .dn directive"));
2218 s_qn (int a ATTRIBUTE_UNUSED
)
2220 as_bad (_("invalid syntax for .qn directive"));
2223 /* The .unreq directive deletes an alias which was previously defined
2224 by .req. For example:
2230 s_unreq (int a ATTRIBUTE_UNUSED
)
2235 name
= input_line_pointer
;
2237 while (*input_line_pointer
!= 0
2238 && *input_line_pointer
!= ' '
2239 && *input_line_pointer
!= '\n')
2240 ++input_line_pointer
;
2242 saved_char
= *input_line_pointer
;
2243 *input_line_pointer
= 0;
2246 as_bad (_("invalid syntax for .unreq directive"));
2249 struct reg_entry
*reg
= hash_find (arm_reg_hsh
, name
);
2252 as_bad (_("unknown register alias '%s'"), name
);
2253 else if (reg
->builtin
)
2254 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2258 hash_delete (arm_reg_hsh
, name
);
2259 free ((char *) reg
->name
);
2266 *input_line_pointer
= saved_char
;
2267 demand_empty_rest_of_line ();
2270 /* Directives: Instruction set selection. */
2273 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2274 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2275 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2276 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2278 static enum mstate mapstate
= MAP_UNDEFINED
;
2281 mapping_state (enum mstate state
)
2284 const char * symname
;
2287 if (mapstate
== state
)
2288 /* The mapping symbol has already been emitted.
2289 There is nothing else to do. */
2298 type
= BSF_NO_FLAGS
;
2302 type
= BSF_NO_FLAGS
;
2306 type
= BSF_NO_FLAGS
;
2314 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2316 symbolP
= symbol_new (symname
, now_seg
, (valueT
) frag_now_fix (), frag_now
);
2317 symbol_table_insert (symbolP
);
2318 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2323 THUMB_SET_FUNC (symbolP
, 0);
2324 ARM_SET_THUMB (symbolP
, 0);
2325 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2329 THUMB_SET_FUNC (symbolP
, 1);
2330 ARM_SET_THUMB (symbolP
, 1);
2331 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2340 #define mapping_state(x) /* nothing */
2343 /* Find the real, Thumb encoded start of a Thumb function. */
2346 find_real_start (symbolS
* symbolP
)
2349 const char * name
= S_GET_NAME (symbolP
);
2350 symbolS
* new_target
;
2352 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2353 #define STUB_NAME ".real_start_of"
2358 /* The compiler may generate BL instructions to local labels because
2359 it needs to perform a branch to a far away location. These labels
2360 do not have a corresponding ".real_start_of" label. We check
2361 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2362 the ".real_start_of" convention for nonlocal branches. */
2363 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2366 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2367 new_target
= symbol_find (real_start
);
2369 if (new_target
== NULL
)
2371 as_warn ("Failed to find real start of function: %s\n", name
);
2372 new_target
= symbolP
;
2379 opcode_select (int width
)
2386 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2387 as_bad (_("selected processor does not support THUMB opcodes"));
2390 /* No need to force the alignment, since we will have been
2391 coming from ARM mode, which is word-aligned. */
2392 record_alignment (now_seg
, 1);
2394 mapping_state (MAP_THUMB
);
2400 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2401 as_bad (_("selected processor does not support ARM opcodes"));
2406 frag_align (2, 0, 0);
2408 record_alignment (now_seg
, 1);
2410 mapping_state (MAP_ARM
);
2414 as_bad (_("invalid instruction size selected (%d)"), width
);
2419 s_arm (int ignore ATTRIBUTE_UNUSED
)
2422 demand_empty_rest_of_line ();
2426 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2429 demand_empty_rest_of_line ();
2433 s_code (int unused ATTRIBUTE_UNUSED
)
2437 temp
= get_absolute_expression ();
2442 opcode_select (temp
);
2446 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2451 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2453 /* If we are not already in thumb mode go into it, EVEN if
2454 the target processor does not support thumb instructions.
2455 This is used by gcc/config/arm/lib1funcs.asm for example
2456 to compile interworking support functions even if the
2457 target processor should not support interworking. */
2461 record_alignment (now_seg
, 1);
2464 demand_empty_rest_of_line ();
2468 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2472 /* The following label is the name/address of the start of a Thumb function.
2473 We need to know this for the interworking support. */
2474 label_is_thumb_function_name
= TRUE
;
2477 /* Perform a .set directive, but also mark the alias as
2478 being a thumb function. */
2481 s_thumb_set (int equiv
)
2483 /* XXX the following is a duplicate of the code for s_set() in read.c
2484 We cannot just call that code as we need to get at the symbol that
2491 /* Especial apologies for the random logic:
2492 This just grew, and could be parsed much more simply!
2494 name
= input_line_pointer
;
2495 delim
= get_symbol_end ();
2496 end_name
= input_line_pointer
;
2499 if (*input_line_pointer
!= ',')
2502 as_bad (_("expected comma after name \"%s\""), name
);
2504 ignore_rest_of_line ();
2508 input_line_pointer
++;
2511 if (name
[0] == '.' && name
[1] == '\0')
2513 /* XXX - this should not happen to .thumb_set. */
2517 if ((symbolP
= symbol_find (name
)) == NULL
2518 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2521 /* When doing symbol listings, play games with dummy fragments living
2522 outside the normal fragment chain to record the file and line info
2524 if (listing
& LISTING_SYMBOLS
)
2526 extern struct list_info_struct
* listing_tail
;
2527 fragS
* dummy_frag
= xmalloc (sizeof (fragS
));
2529 memset (dummy_frag
, 0, sizeof (fragS
));
2530 dummy_frag
->fr_type
= rs_fill
;
2531 dummy_frag
->line
= listing_tail
;
2532 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2533 dummy_frag
->fr_symbol
= symbolP
;
2537 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2540 /* "set" symbols are local unless otherwise specified. */
2541 SF_SET_LOCAL (symbolP
);
2542 #endif /* OBJ_COFF */
2543 } /* Make a new symbol. */
2545 symbol_table_insert (symbolP
);
2550 && S_IS_DEFINED (symbolP
)
2551 && S_GET_SEGMENT (symbolP
) != reg_section
)
2552 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2554 pseudo_set (symbolP
);
2556 demand_empty_rest_of_line ();
2558 /* XXX Now we come to the Thumb specific bit of code. */
2560 THUMB_SET_FUNC (symbolP
, 1);
2561 ARM_SET_THUMB (symbolP
, 1);
2562 #if defined OBJ_ELF || defined OBJ_COFF
2563 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2567 /* Directives: Mode selection. */
2569 /* .syntax [unified|divided] - choose the new unified syntax
2570 (same for Arm and Thumb encoding, modulo slight differences in what
2571 can be represented) or the old divergent syntax for each mode. */
2573 s_syntax (int unused ATTRIBUTE_UNUSED
)
2577 name
= input_line_pointer
;
2578 delim
= get_symbol_end ();
2580 if (!strcasecmp (name
, "unified"))
2581 unified_syntax
= TRUE
;
2582 else if (!strcasecmp (name
, "divided"))
2583 unified_syntax
= FALSE
;
2586 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2589 *input_line_pointer
= delim
;
2590 demand_empty_rest_of_line ();
2593 /* Directives: sectioning and alignment. */
2595 /* Same as s_align_ptwo but align 0 => align 2. */
2598 s_align (int unused ATTRIBUTE_UNUSED
)
2602 long max_alignment
= 15;
2604 temp
= get_absolute_expression ();
2605 if (temp
> max_alignment
)
2606 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2609 as_bad (_("alignment negative. 0 assumed."));
2613 if (*input_line_pointer
== ',')
2615 input_line_pointer
++;
2616 temp_fill
= get_absolute_expression ();
2624 /* Only make a frag if we HAVE to. */
2625 if (temp
&& !need_pass_2
)
2626 frag_align (temp
, (int) temp_fill
, 0);
2627 demand_empty_rest_of_line ();
2629 record_alignment (now_seg
, temp
);
2633 s_bss (int ignore ATTRIBUTE_UNUSED
)
2635 /* We don't support putting frags in the BSS segment, we fake it by
2636 marking in_bss, then looking at s_skip for clues. */
2637 subseg_set (bss_section
, 0);
2638 demand_empty_rest_of_line ();
2639 mapping_state (MAP_DATA
);
2643 s_even (int ignore ATTRIBUTE_UNUSED
)
2645 /* Never make frag if expect extra pass. */
2647 frag_align (1, 0, 0);
2649 record_alignment (now_seg
, 1);
2651 demand_empty_rest_of_line ();
2654 /* Directives: Literal pools. */
2656 static literal_pool
*
2657 find_literal_pool (void)
2659 literal_pool
* pool
;
2661 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2663 if (pool
->section
== now_seg
2664 && pool
->sub_section
== now_subseg
)
2671 static literal_pool
*
2672 find_or_make_literal_pool (void)
2674 /* Next literal pool ID number. */
2675 static unsigned int latest_pool_num
= 1;
2676 literal_pool
* pool
;
2678 pool
= find_literal_pool ();
2682 /* Create a new pool. */
2683 pool
= xmalloc (sizeof (* pool
));
2687 pool
->next_free_entry
= 0;
2688 pool
->section
= now_seg
;
2689 pool
->sub_section
= now_subseg
;
2690 pool
->next
= list_of_pools
;
2691 pool
->symbol
= NULL
;
2693 /* Add it to the list. */
2694 list_of_pools
= pool
;
2697 /* New pools, and emptied pools, will have a NULL symbol. */
2698 if (pool
->symbol
== NULL
)
2700 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2701 (valueT
) 0, &zero_address_frag
);
2702 pool
->id
= latest_pool_num
++;
2709 /* Add the literal in the global 'inst'
2710 structure to the relevent literal pool. */
2713 add_to_lit_pool (void)
2715 literal_pool
* pool
;
2718 pool
= find_or_make_literal_pool ();
2720 /* Check if this literal value is already in the pool. */
2721 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2723 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2724 && (inst
.reloc
.exp
.X_op
== O_constant
)
2725 && (pool
->literals
[entry
].X_add_number
2726 == inst
.reloc
.exp
.X_add_number
)
2727 && (pool
->literals
[entry
].X_unsigned
2728 == inst
.reloc
.exp
.X_unsigned
))
2731 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2732 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2733 && (pool
->literals
[entry
].X_add_number
2734 == inst
.reloc
.exp
.X_add_number
)
2735 && (pool
->literals
[entry
].X_add_symbol
2736 == inst
.reloc
.exp
.X_add_symbol
)
2737 && (pool
->literals
[entry
].X_op_symbol
2738 == inst
.reloc
.exp
.X_op_symbol
))
2742 /* Do we need to create a new entry? */
2743 if (entry
== pool
->next_free_entry
)
2745 if (entry
>= MAX_LITERAL_POOL_SIZE
)
2747 inst
.error
= _("literal pool overflow");
2751 pool
->literals
[entry
] = inst
.reloc
.exp
;
2752 pool
->next_free_entry
+= 1;
2755 inst
.reloc
.exp
.X_op
= O_symbol
;
2756 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
2757 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
2762 /* Can't use symbol_new here, so have to create a symbol and then at
2763 a later date assign it a value. Thats what these functions do. */
2766 symbol_locate (symbolS
* symbolP
,
2767 const char * name
, /* It is copied, the caller can modify. */
2768 segT segment
, /* Segment identifier (SEG_<something>). */
2769 valueT valu
, /* Symbol value. */
2770 fragS
* frag
) /* Associated fragment. */
2772 unsigned int name_length
;
2773 char * preserved_copy_of_name
;
2775 name_length
= strlen (name
) + 1; /* +1 for \0. */
2776 obstack_grow (¬es
, name
, name_length
);
2777 preserved_copy_of_name
= obstack_finish (¬es
);
2779 #ifdef tc_canonicalize_symbol_name
2780 preserved_copy_of_name
=
2781 tc_canonicalize_symbol_name (preserved_copy_of_name
);
2784 S_SET_NAME (symbolP
, preserved_copy_of_name
);
2786 S_SET_SEGMENT (symbolP
, segment
);
2787 S_SET_VALUE (symbolP
, valu
);
2788 symbol_clear_list_pointers (symbolP
);
2790 symbol_set_frag (symbolP
, frag
);
2792 /* Link to end of symbol chain. */
2794 extern int symbol_table_frozen
;
2796 if (symbol_table_frozen
)
2800 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
2802 obj_symbol_new_hook (symbolP
);
2804 #ifdef tc_symbol_new_hook
2805 tc_symbol_new_hook (symbolP
);
2809 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
2810 #endif /* DEBUG_SYMS */
2815 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
2818 literal_pool
* pool
;
2821 pool
= find_literal_pool ();
2823 || pool
->symbol
== NULL
2824 || pool
->next_free_entry
== 0)
2827 mapping_state (MAP_DATA
);
2829 /* Align pool as you have word accesses.
2830 Only make a frag if we have to. */
2832 frag_align (2, 0, 0);
2834 record_alignment (now_seg
, 2);
2836 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
2838 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
2839 (valueT
) frag_now_fix (), frag_now
);
2840 symbol_table_insert (pool
->symbol
);
2842 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
2844 #if defined OBJ_COFF || defined OBJ_ELF
2845 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
2848 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2849 /* First output the expression in the instruction to the pool. */
2850 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
2852 /* Mark the pool as empty. */
2853 pool
->next_free_entry
= 0;
2854 pool
->symbol
= NULL
;
2858 /* Forward declarations for functions below, in the MD interface
2860 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
2861 static valueT
create_unwind_entry (int);
2862 static void start_unwind_section (const segT
, int);
2863 static void add_unwind_opcode (valueT
, int);
2864 static void flush_pending_unwind (void);
2866 /* Directives: Data. */
2869 s_arm_elf_cons (int nbytes
)
2873 #ifdef md_flush_pending_output
2874 md_flush_pending_output ();
2877 if (is_it_end_of_statement ())
2879 demand_empty_rest_of_line ();
2883 #ifdef md_cons_align
2884 md_cons_align (nbytes
);
2887 mapping_state (MAP_DATA
);
2891 char *base
= input_line_pointer
;
2895 if (exp
.X_op
!= O_symbol
)
2896 emit_expr (&exp
, (unsigned int) nbytes
);
2899 char *before_reloc
= input_line_pointer
;
2900 reloc
= parse_reloc (&input_line_pointer
);
2903 as_bad (_("unrecognized relocation suffix"));
2904 ignore_rest_of_line ();
2907 else if (reloc
== BFD_RELOC_UNUSED
)
2908 emit_expr (&exp
, (unsigned int) nbytes
);
2911 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
2912 int size
= bfd_get_reloc_size (howto
);
2914 if (reloc
== BFD_RELOC_ARM_PLT32
)
2916 as_bad (_("(plt) is only valid on branch targets"));
2917 reloc
= BFD_RELOC_UNUSED
;
2922 as_bad (_("%s relocations do not fit in %d bytes"),
2923 howto
->name
, nbytes
);
2926 /* We've parsed an expression stopping at O_symbol.
2927 But there may be more expression left now that we
2928 have parsed the relocation marker. Parse it again.
2929 XXX Surely there is a cleaner way to do this. */
2930 char *p
= input_line_pointer
;
2932 char *save_buf
= alloca (input_line_pointer
- base
);
2933 memcpy (save_buf
, base
, input_line_pointer
- base
);
2934 memmove (base
+ (input_line_pointer
- before_reloc
),
2935 base
, before_reloc
- base
);
2937 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
2939 memcpy (base
, save_buf
, p
- base
);
2941 offset
= nbytes
- size
;
2942 p
= frag_more ((int) nbytes
);
2943 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
2944 size
, &exp
, 0, reloc
);
2949 while (*input_line_pointer
++ == ',');
2951 /* Put terminator back into stream. */
2952 input_line_pointer
--;
2953 demand_empty_rest_of_line ();
2957 /* Parse a .rel31 directive. */
2960 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
2967 if (*input_line_pointer
== '1')
2968 highbit
= 0x80000000;
2969 else if (*input_line_pointer
!= '0')
2970 as_bad (_("expected 0 or 1"));
2972 input_line_pointer
++;
2973 if (*input_line_pointer
!= ',')
2974 as_bad (_("missing comma"));
2975 input_line_pointer
++;
2977 #ifdef md_flush_pending_output
2978 md_flush_pending_output ();
2981 #ifdef md_cons_align
2985 mapping_state (MAP_DATA
);
2990 md_number_to_chars (p
, highbit
, 4);
2991 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
2992 BFD_RELOC_ARM_PREL31
);
2994 demand_empty_rest_of_line ();
2997 /* Directives: AEABI stack-unwind tables. */
2999 /* Parse an unwind_fnstart directive. Simply records the current location. */
3002 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3004 demand_empty_rest_of_line ();
3005 /* Mark the start of the function. */
3006 unwind
.proc_start
= expr_build_dot ();
3008 /* Reset the rest of the unwind info. */
3009 unwind
.opcode_count
= 0;
3010 unwind
.table_entry
= NULL
;
3011 unwind
.personality_routine
= NULL
;
3012 unwind
.personality_index
= -1;
3013 unwind
.frame_size
= 0;
3014 unwind
.fp_offset
= 0;
3017 unwind
.sp_restored
= 0;
3021 /* Parse a handlerdata directive. Creates the exception handling table entry
3022 for the function. */
3025 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3027 demand_empty_rest_of_line ();
3028 if (unwind
.table_entry
)
3029 as_bad (_("dupicate .handlerdata directive"));
3031 create_unwind_entry (1);
3034 /* Parse an unwind_fnend directive. Generates the index table entry. */
3037 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3043 demand_empty_rest_of_line ();
3045 /* Add eh table entry. */
3046 if (unwind
.table_entry
== NULL
)
3047 val
= create_unwind_entry (0);
3051 /* Add index table entry. This is two words. */
3052 start_unwind_section (unwind
.saved_seg
, 1);
3053 frag_align (2, 0, 0);
3054 record_alignment (now_seg
, 2);
3056 ptr
= frag_more (8);
3057 where
= frag_now_fix () - 8;
3059 /* Self relative offset of the function start. */
3060 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3061 BFD_RELOC_ARM_PREL31
);
3063 /* Indicate dependency on EHABI-defined personality routines to the
3064 linker, if it hasn't been done already. */
3065 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3066 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3068 static const char *const name
[] = {
3069 "__aeabi_unwind_cpp_pr0",
3070 "__aeabi_unwind_cpp_pr1",
3071 "__aeabi_unwind_cpp_pr2"
3073 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3074 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3075 marked_pr_dependency
|= 1 << unwind
.personality_index
;
3076 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3077 = marked_pr_dependency
;
3081 /* Inline exception table entry. */
3082 md_number_to_chars (ptr
+ 4, val
, 4);
3084 /* Self relative offset of the table entry. */
3085 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3086 BFD_RELOC_ARM_PREL31
);
3088 /* Restore the original section. */
3089 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3093 /* Parse an unwind_cantunwind directive. */
3096 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3098 demand_empty_rest_of_line ();
3099 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3100 as_bad (_("personality routine specified for cantunwind frame"));
3102 unwind
.personality_index
= -2;
3106 /* Parse a personalityindex directive. */
3109 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3113 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3114 as_bad (_("duplicate .personalityindex directive"));
3118 if (exp
.X_op
!= O_constant
3119 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3121 as_bad (_("bad personality routine number"));
3122 ignore_rest_of_line ();
3126 unwind
.personality_index
= exp
.X_add_number
;
3128 demand_empty_rest_of_line ();
3132 /* Parse a personality directive. */
3135 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3139 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3140 as_bad (_("duplicate .personality directive"));
3142 name
= input_line_pointer
;
3143 c
= get_symbol_end ();
3144 p
= input_line_pointer
;
3145 unwind
.personality_routine
= symbol_find_or_make (name
);
3147 demand_empty_rest_of_line ();
3151 /* Parse a directive saving core registers. */
3154 s_arm_unwind_save_core (void)
3160 range
= parse_reg_list (&input_line_pointer
);
3163 as_bad (_("expected register list"));
3164 ignore_rest_of_line ();
3168 demand_empty_rest_of_line ();
3170 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3171 into .unwind_save {..., sp...}. We aren't bothered about the value of
3172 ip because it is clobbered by calls. */
3173 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3174 && (range
& 0x3000) == 0x1000)
3176 unwind
.opcode_count
--;
3177 unwind
.sp_restored
= 0;
3178 range
= (range
| 0x2000) & ~0x1000;
3179 unwind
.pending_offset
= 0;
3185 /* See if we can use the short opcodes. These pop a block of up to 8
3186 registers starting with r4, plus maybe r14. */
3187 for (n
= 0; n
< 8; n
++)
3189 /* Break at the first non-saved register. */
3190 if ((range
& (1 << (n
+ 4))) == 0)
3193 /* See if there are any other bits set. */
3194 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3196 /* Use the long form. */
3197 op
= 0x8000 | ((range
>> 4) & 0xfff);
3198 add_unwind_opcode (op
, 2);
3202 /* Use the short form. */
3204 op
= 0xa8; /* Pop r14. */
3206 op
= 0xa0; /* Do not pop r14. */
3208 add_unwind_opcode (op
, 1);
3215 op
= 0xb100 | (range
& 0xf);
3216 add_unwind_opcode (op
, 2);
3219 /* Record the number of bytes pushed. */
3220 for (n
= 0; n
< 16; n
++)
3222 if (range
& (1 << n
))
3223 unwind
.frame_size
+= 4;
3228 /* Parse a directive saving FPA registers. */
3231 s_arm_unwind_save_fpa (int reg
)
3237 /* Get Number of registers to transfer. */
3238 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3241 exp
.X_op
= O_illegal
;
3243 if (exp
.X_op
!= O_constant
)
3245 as_bad (_("expected , <constant>"));
3246 ignore_rest_of_line ();
3250 num_regs
= exp
.X_add_number
;
3252 if (num_regs
< 1 || num_regs
> 4)
3254 as_bad (_("number of registers must be in the range [1:4]"));
3255 ignore_rest_of_line ();
3259 demand_empty_rest_of_line ();
3264 op
= 0xb4 | (num_regs
- 1);
3265 add_unwind_opcode (op
, 1);
3270 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3271 add_unwind_opcode (op
, 2);
3273 unwind
.frame_size
+= num_regs
* 12;
3277 /* Parse a directive saving VFP registers. */
3280 s_arm_unwind_save_vfp (void)
3286 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3289 as_bad (_("expected register list"));
3290 ignore_rest_of_line ();
3294 demand_empty_rest_of_line ();
3299 op
= 0xb8 | (count
- 1);
3300 add_unwind_opcode (op
, 1);
3305 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3306 add_unwind_opcode (op
, 2);
3308 unwind
.frame_size
+= count
* 8 + 4;
3312 /* Parse a directive saving iWMMXt data registers. */
3315 s_arm_unwind_save_mmxwr (void)
3323 if (*input_line_pointer
== '{')
3324 input_line_pointer
++;
3328 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3332 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3337 as_tsktsk (_("register list not in ascending order"));
3340 if (*input_line_pointer
== '-')
3342 input_line_pointer
++;
3343 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3346 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3349 else if (reg
>= hi_reg
)
3351 as_bad (_("bad register range"));
3354 for (; reg
< hi_reg
; reg
++)
3358 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3360 if (*input_line_pointer
== '}')
3361 input_line_pointer
++;
3363 demand_empty_rest_of_line ();
3365 /* Generate any deferred opcodes because we're going to be looking at
3367 flush_pending_unwind ();
3369 for (i
= 0; i
< 16; i
++)
3371 if (mask
& (1 << i
))
3372 unwind
.frame_size
+= 8;
3375 /* Attempt to combine with a previous opcode. We do this because gcc
3376 likes to output separate unwind directives for a single block of
3378 if (unwind
.opcode_count
> 0)
3380 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3381 if ((i
& 0xf8) == 0xc0)
3384 /* Only merge if the blocks are contiguous. */
3387 if ((mask
& 0xfe00) == (1 << 9))
3389 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3390 unwind
.opcode_count
--;
3393 else if (i
== 6 && unwind
.opcode_count
>= 2)
3395 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3399 op
= 0xffff << (reg
- 1);
3401 || ((mask
& op
) == (1u << (reg
- 1))))
3403 op
= (1 << (reg
+ i
+ 1)) - 1;
3404 op
&= ~((1 << reg
) - 1);
3406 unwind
.opcode_count
-= 2;
3413 /* We want to generate opcodes in the order the registers have been
3414 saved, ie. descending order. */
3415 for (reg
= 15; reg
>= -1; reg
--)
3417 /* Save registers in blocks. */
3419 || !(mask
& (1 << reg
)))
3421 /* We found an unsaved reg. Generate opcodes to save the
3422 preceeding block. */
3428 op
= 0xc0 | (hi_reg
- 10);
3429 add_unwind_opcode (op
, 1);
3434 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3435 add_unwind_opcode (op
, 2);
3444 ignore_rest_of_line ();
3448 s_arm_unwind_save_mmxwcg (void)
3455 if (*input_line_pointer
== '{')
3456 input_line_pointer
++;
3460 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3464 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3470 as_tsktsk (_("register list not in ascending order"));
3473 if (*input_line_pointer
== '-')
3475 input_line_pointer
++;
3476 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3479 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3482 else if (reg
>= hi_reg
)
3484 as_bad (_("bad register range"));
3487 for (; reg
< hi_reg
; reg
++)
3491 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3493 if (*input_line_pointer
== '}')
3494 input_line_pointer
++;
3496 demand_empty_rest_of_line ();
3498 /* Generate any deferred opcodes because we're going to be looking at
3500 flush_pending_unwind ();
3502 for (reg
= 0; reg
< 16; reg
++)
3504 if (mask
& (1 << reg
))
3505 unwind
.frame_size
+= 4;
3508 add_unwind_opcode (op
, 2);
3511 ignore_rest_of_line ();
3515 /* Parse an unwind_save directive. */
3518 s_arm_unwind_save (int ignored ATTRIBUTE_UNUSED
)
3521 struct reg_entry
*reg
;
3522 bfd_boolean had_brace
= FALSE
;
3524 /* Figure out what sort of save we have. */
3525 peek
= input_line_pointer
;
3533 reg
= arm_reg_parse_multi (&peek
);
3537 as_bad (_("register expected"));
3538 ignore_rest_of_line ();
3547 as_bad (_("FPA .unwind_save does not take a register list"));
3548 ignore_rest_of_line ();
3551 s_arm_unwind_save_fpa (reg
->number
);
3554 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
3555 case REG_TYPE_VFD
: s_arm_unwind_save_vfp (); return;
3556 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
3557 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
3560 as_bad (_(".unwind_save does not support this kind of register"));
3561 ignore_rest_of_line ();
3566 /* Parse an unwind_movsp directive. */
3569 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
3574 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3577 as_bad (_(reg_expected_msgs
[REG_TYPE_RN
]));
3578 ignore_rest_of_line ();
3581 demand_empty_rest_of_line ();
3583 if (reg
== REG_SP
|| reg
== REG_PC
)
3585 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
3589 if (unwind
.fp_reg
!= REG_SP
)
3590 as_bad (_("unexpected .unwind_movsp directive"));
3592 /* Generate opcode to restore the value. */
3594 add_unwind_opcode (op
, 1);
3596 /* Record the information for later. */
3597 unwind
.fp_reg
= reg
;
3598 unwind
.fp_offset
= unwind
.frame_size
;
3599 unwind
.sp_restored
= 1;
3602 /* Parse an unwind_pad directive. */
3605 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
3609 if (immediate_for_directive (&offset
) == FAIL
)
3614 as_bad (_("stack increment must be multiple of 4"));
3615 ignore_rest_of_line ();
3619 /* Don't generate any opcodes, just record the details for later. */
3620 unwind
.frame_size
+= offset
;
3621 unwind
.pending_offset
+= offset
;
3623 demand_empty_rest_of_line ();
3626 /* Parse an unwind_setfp directive. */
3629 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
3635 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3636 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3639 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3641 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
3643 as_bad (_("expected <reg>, <reg>"));
3644 ignore_rest_of_line ();
3648 /* Optional constant. */
3649 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3651 if (immediate_for_directive (&offset
) == FAIL
)
3657 demand_empty_rest_of_line ();
3659 if (sp_reg
!= 13 && sp_reg
!= unwind
.fp_reg
)
3661 as_bad (_("register must be either sp or set by a previous"
3662 "unwind_movsp directive"));
3666 /* Don't generate any opcodes, just record the information for later. */
3667 unwind
.fp_reg
= fp_reg
;
3670 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3672 unwind
.fp_offset
-= offset
;
3675 /* Parse an unwind_raw directive. */
3678 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
3681 /* This is an arbitrary limit. */
3682 unsigned char op
[16];
3686 if (exp
.X_op
== O_constant
3687 && skip_past_comma (&input_line_pointer
) != FAIL
)
3689 unwind
.frame_size
+= exp
.X_add_number
;
3693 exp
.X_op
= O_illegal
;
3695 if (exp
.X_op
!= O_constant
)
3697 as_bad (_("expected <offset>, <opcode>"));
3698 ignore_rest_of_line ();
3704 /* Parse the opcode. */
3709 as_bad (_("unwind opcode too long"));
3710 ignore_rest_of_line ();
3712 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
3714 as_bad (_("invalid unwind opcode"));
3715 ignore_rest_of_line ();
3718 op
[count
++] = exp
.X_add_number
;
3720 /* Parse the next byte. */
3721 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3727 /* Add the opcode bytes in reverse order. */
3729 add_unwind_opcode (op
[count
], 1);
3731 demand_empty_rest_of_line ();
3735 /* Parse a .eabi_attribute directive. */
3738 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
3741 bfd_boolean is_string
;
3748 if (exp
.X_op
!= O_constant
)
3751 tag
= exp
.X_add_number
;
3752 if (tag
== 4 || tag
== 5 || tag
== 32 || (tag
> 32 && (tag
& 1) != 0))
3757 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3759 if (tag
== 32 || !is_string
)
3762 if (exp
.X_op
!= O_constant
)
3764 as_bad (_("expected numeric constant"));
3765 ignore_rest_of_line ();
3768 i
= exp
.X_add_number
;
3770 if (tag
== Tag_compatibility
3771 && skip_past_comma (&input_line_pointer
) == FAIL
)
3773 as_bad (_("expected comma"));
3774 ignore_rest_of_line ();
3779 skip_whitespace(input_line_pointer
);
3780 if (*input_line_pointer
!= '"')
3782 input_line_pointer
++;
3783 s
= input_line_pointer
;
3784 while (*input_line_pointer
&& *input_line_pointer
!= '"')
3785 input_line_pointer
++;
3786 if (*input_line_pointer
!= '"')
3788 saved_char
= *input_line_pointer
;
3789 *input_line_pointer
= 0;
3797 if (tag
== Tag_compatibility
)
3798 elf32_arm_add_eabi_attr_compat (stdoutput
, i
, s
);
3800 elf32_arm_add_eabi_attr_string (stdoutput
, tag
, s
);
3802 elf32_arm_add_eabi_attr_int (stdoutput
, tag
, i
);
3806 *input_line_pointer
= saved_char
;
3807 input_line_pointer
++;
3809 demand_empty_rest_of_line ();
3812 as_bad (_("bad string constant"));
3813 ignore_rest_of_line ();
3816 as_bad (_("expected <tag> , <value>"));
3817 ignore_rest_of_line ();
3819 #endif /* OBJ_ELF */
3821 static void s_arm_arch (int);
3822 static void s_arm_cpu (int);
3823 static void s_arm_fpu (int);
3825 /* This table describes all the machine specific pseudo-ops the assembler
3826 has to support. The fields are:
3827 pseudo-op name without dot
3828 function to call to execute this pseudo-op
3829 Integer arg to pass to the function. */
3831 const pseudo_typeS md_pseudo_table
[] =
3833 /* Never called because '.req' does not start a line. */
3834 { "req", s_req
, 0 },
3835 /* Following two are likewise never called. */
3838 { "unreq", s_unreq
, 0 },
3839 { "bss", s_bss
, 0 },
3840 { "align", s_align
, 0 },
3841 { "arm", s_arm
, 0 },
3842 { "thumb", s_thumb
, 0 },
3843 { "code", s_code
, 0 },
3844 { "force_thumb", s_force_thumb
, 0 },
3845 { "thumb_func", s_thumb_func
, 0 },
3846 { "thumb_set", s_thumb_set
, 0 },
3847 { "even", s_even
, 0 },
3848 { "ltorg", s_ltorg
, 0 },
3849 { "pool", s_ltorg
, 0 },
3850 { "syntax", s_syntax
, 0 },
3851 { "cpu", s_arm_cpu
, 0 },
3852 { "arch", s_arm_arch
, 0 },
3853 { "fpu", s_arm_fpu
, 0 },
3855 { "word", s_arm_elf_cons
, 4 },
3856 { "long", s_arm_elf_cons
, 4 },
3857 { "rel31", s_arm_rel31
, 0 },
3858 { "fnstart", s_arm_unwind_fnstart
, 0 },
3859 { "fnend", s_arm_unwind_fnend
, 0 },
3860 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
3861 { "personality", s_arm_unwind_personality
, 0 },
3862 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
3863 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
3864 { "save", s_arm_unwind_save
, 0 },
3865 { "movsp", s_arm_unwind_movsp
, 0 },
3866 { "pad", s_arm_unwind_pad
, 0 },
3867 { "setfp", s_arm_unwind_setfp
, 0 },
3868 { "unwind_raw", s_arm_unwind_raw
, 0 },
3869 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
3873 { "extend", float_cons
, 'x' },
3874 { "ldouble", float_cons
, 'x' },
3875 { "packed", float_cons
, 'p' },
3879 /* Parser functions used exclusively in instruction operands. */
3881 /* Generic immediate-value read function for use in insn parsing.
3882 STR points to the beginning of the immediate (the leading #);
3883 VAL receives the value; if the value is outside [MIN, MAX]
3884 issue an error. PREFIX_OPT is true if the immediate prefix is
3888 parse_immediate (char **str
, int *val
, int min
, int max
,
3889 bfd_boolean prefix_opt
)
3892 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
3893 if (exp
.X_op
!= O_constant
)
3895 inst
.error
= _("constant expression required");
3899 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
3901 inst
.error
= _("immediate value out of range");
3905 *val
= exp
.X_add_number
;
3909 /* Less-generic immediate-value read function with the possibility of loading a
3910 big (64-bit) immediate, as required by Neon VMOV and VMVN immediate
3911 instructions. Puts the result directly in inst.operands[i]. */
3914 parse_big_immediate (char **str
, int i
)
3919 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
3921 if (exp
.X_op
== O_constant
)
3922 inst
.operands
[i
].imm
= exp
.X_add_number
;
3923 else if (exp
.X_op
== O_big
3924 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
3925 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
3927 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
3928 /* Bignums have their least significant bits in
3929 generic_bignum[0]. Make sure we put 32 bits in imm and
3930 32 bits in reg, in a (hopefully) portable way. */
3931 assert (parts
!= 0);
3932 inst
.operands
[i
].imm
= 0;
3933 for (j
= 0; j
< parts
; j
++, idx
++)
3934 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
3935 << (LITTLENUM_NUMBER_OF_BITS
* j
);
3936 inst
.operands
[i
].reg
= 0;
3937 for (j
= 0; j
< parts
; j
++, idx
++)
3938 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
3939 << (LITTLENUM_NUMBER_OF_BITS
* j
);
3940 inst
.operands
[i
].regisimm
= 1;
3950 /* Returns the pseudo-register number of an FPA immediate constant,
3951 or FAIL if there isn't a valid constant here. */
3954 parse_fpa_immediate (char ** str
)
3956 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
3962 /* First try and match exact strings, this is to guarantee
3963 that some formats will work even for cross assembly. */
3965 for (i
= 0; fp_const
[i
]; i
++)
3967 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
3971 *str
+= strlen (fp_const
[i
]);
3972 if (is_end_of_line
[(unsigned char) **str
])
3978 /* Just because we didn't get a match doesn't mean that the constant
3979 isn't valid, just that it is in a format that we don't
3980 automatically recognize. Try parsing it with the standard
3981 expression routines. */
3983 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
3985 /* Look for a raw floating point number. */
3986 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
3987 && is_end_of_line
[(unsigned char) *save_in
])
3989 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
3991 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
3993 if (words
[j
] != fp_values
[i
][j
])
3997 if (j
== MAX_LITTLENUMS
)
4005 /* Try and parse a more complex expression, this will probably fail
4006 unless the code uses a floating point prefix (eg "0f"). */
4007 save_in
= input_line_pointer
;
4008 input_line_pointer
= *str
;
4009 if (expression (&exp
) == absolute_section
4010 && exp
.X_op
== O_big
4011 && exp
.X_add_number
< 0)
4013 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4015 if (gen_to_words (words
, 5, (long) 15) == 0)
4017 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4019 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4021 if (words
[j
] != fp_values
[i
][j
])
4025 if (j
== MAX_LITTLENUMS
)
4027 *str
= input_line_pointer
;
4028 input_line_pointer
= save_in
;
4035 *str
= input_line_pointer
;
4036 input_line_pointer
= save_in
;
4037 inst
.error
= _("invalid FPA immediate expression");
4041 /* Returns 1 if a number has "quarter-precision" float format
4042 0baBbbbbbc defgh000 00000000 00000000. */
4045 is_quarter_float (unsigned imm
)
4047 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4048 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4051 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4052 0baBbbbbbc defgh000 00000000 00000000.
4053 The minus-zero case needs special handling, since it can't be encoded in the
4054 "quarter-precision" float format, but can nonetheless be loaded as an integer
4058 parse_qfloat_immediate (char **ccp
, int *immed
)
4061 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4063 skip_past_char (&str
, '#');
4065 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4067 unsigned fpword
= 0;
4070 /* Our FP word must be 32 bits (single-precision FP). */
4071 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4073 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4077 if (is_quarter_float (fpword
) || fpword
== 0x80000000)
4090 /* Shift operands. */
4093 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4096 struct asm_shift_name
4099 enum shift_kind kind
;
4102 /* Third argument to parse_shift. */
4103 enum parse_shift_mode
4105 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4106 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4107 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4108 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4109 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4112 /* Parse a <shift> specifier on an ARM data processing instruction.
4113 This has three forms:
4115 (LSL|LSR|ASL|ASR|ROR) Rs
4116 (LSL|LSR|ASL|ASR|ROR) #imm
4119 Note that ASL is assimilated to LSL in the instruction encoding, and
4120 RRX to ROR #0 (which cannot be written as such). */
4123 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4125 const struct asm_shift_name
*shift_name
;
4126 enum shift_kind shift
;
4131 for (p
= *str
; ISALPHA (*p
); p
++)
4136 inst
.error
= _("shift expression expected");
4140 shift_name
= hash_find_n (arm_shift_hsh
, *str
, p
- *str
);
4142 if (shift_name
== NULL
)
4144 inst
.error
= _("shift expression expected");
4148 shift
= shift_name
->kind
;
4152 case NO_SHIFT_RESTRICT
:
4153 case SHIFT_IMMEDIATE
: break;
4155 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4156 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4158 inst
.error
= _("'LSL' or 'ASR' required");
4163 case SHIFT_LSL_IMMEDIATE
:
4164 if (shift
!= SHIFT_LSL
)
4166 inst
.error
= _("'LSL' required");
4171 case SHIFT_ASR_IMMEDIATE
:
4172 if (shift
!= SHIFT_ASR
)
4174 inst
.error
= _("'ASR' required");
4182 if (shift
!= SHIFT_RRX
)
4184 /* Whitespace can appear here if the next thing is a bare digit. */
4185 skip_whitespace (p
);
4187 if (mode
== NO_SHIFT_RESTRICT
4188 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4190 inst
.operands
[i
].imm
= reg
;
4191 inst
.operands
[i
].immisreg
= 1;
4193 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4196 inst
.operands
[i
].shift_kind
= shift
;
4197 inst
.operands
[i
].shifted
= 1;
4202 /* Parse a <shifter_operand> for an ARM data processing instruction:
4205 #<immediate>, <rotate>
4209 where <shift> is defined by parse_shift above, and <rotate> is a
4210 multiple of 2 between 0 and 30. Validation of immediate operands
4211 is deferred to md_apply_fix. */
4214 parse_shifter_operand (char **str
, int i
)
4219 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4221 inst
.operands
[i
].reg
= value
;
4222 inst
.operands
[i
].isreg
= 1;
4224 /* parse_shift will override this if appropriate */
4225 inst
.reloc
.exp
.X_op
= O_constant
;
4226 inst
.reloc
.exp
.X_add_number
= 0;
4228 if (skip_past_comma (str
) == FAIL
)
4231 /* Shift operation on register. */
4232 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4235 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4238 if (skip_past_comma (str
) == SUCCESS
)
4240 /* #x, y -- ie explicit rotation by Y. */
4241 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
4244 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4246 inst
.error
= _("constant expression expected");
4250 value
= expr
.X_add_number
;
4251 if (value
< 0 || value
> 30 || value
% 2 != 0)
4253 inst
.error
= _("invalid rotation");
4256 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4258 inst
.error
= _("invalid constant");
4262 /* Convert to decoded value. md_apply_fix will put it back. */
4263 inst
.reloc
.exp
.X_add_number
4264 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4265 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4268 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4269 inst
.reloc
.pc_rel
= 0;
4273 /* Group relocation information. Each entry in the table contains the
4274 textual name of the relocation as may appear in assembler source
4275 and must end with a colon.
4276 Along with this textual name are the relocation codes to be used if
4277 the corresponding instruction is an ALU instruction (ADD or SUB only),
4278 an LDR, an LDRS, or an LDC. */
4280 struct group_reloc_table_entry
4291 /* Varieties of non-ALU group relocation. */
4298 static struct group_reloc_table_entry group_reloc_table
[] =
4299 { /* Program counter relative: */
4301 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4306 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4307 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4308 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4309 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4311 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4316 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4317 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4318 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4319 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4321 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4322 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4323 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4324 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4325 /* Section base relative */
4327 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4332 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4333 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4334 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4335 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4337 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4342 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4343 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4344 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4345 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4347 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4348 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4349 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4350 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4352 /* Given the address of a pointer pointing to the textual name of a group
4353 relocation as may appear in assembler source, attempt to find its details
4354 in group_reloc_table. The pointer will be updated to the character after
4355 the trailing colon. On failure, FAIL will be returned; SUCCESS
4356 otherwise. On success, *entry will be updated to point at the relevant
4357 group_reloc_table entry. */
4360 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4363 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4365 int length
= strlen (group_reloc_table
[i
].name
);
4367 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0 &&
4368 (*str
)[length
] == ':')
4370 *out
= &group_reloc_table
[i
];
4371 *str
+= (length
+ 1);
4379 /* Parse a <shifter_operand> for an ARM data processing instruction
4380 (as for parse_shifter_operand) where group relocations are allowed:
4383 #<immediate>, <rotate>
4384 #:<group_reloc>:<expression>
4388 where <group_reloc> is one of the strings defined in group_reloc_table.
4389 The hashes are optional.
4391 Everything else is as for parse_shifter_operand. */
4393 static parse_operand_result
4394 parse_shifter_operand_group_reloc (char **str
, int i
)
4396 /* Determine if we have the sequence of characters #: or just :
4397 coming next. If we do, then we check for a group relocation.
4398 If we don't, punt the whole lot to parse_shifter_operand. */
4400 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4401 || (*str
)[0] == ':')
4403 struct group_reloc_table_entry
*entry
;
4405 if ((*str
)[0] == '#')
4410 /* Try to parse a group relocation. Anything else is an error. */
4411 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4413 inst
.error
= _("unknown group relocation");
4414 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4417 /* We now have the group relocation table entry corresponding to
4418 the name in the assembler source. Next, we parse the expression. */
4419 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4420 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4422 /* Record the relocation type (always the ALU variant here). */
4423 inst
.reloc
.type
= entry
->alu_code
;
4424 assert (inst
.reloc
.type
!= 0);
4426 return PARSE_OPERAND_SUCCESS
;
4429 return parse_shifter_operand (str
, i
) == SUCCESS
4430 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4432 /* Never reached. */
4435 /* Parse all forms of an ARM address expression. Information is written
4436 to inst.operands[i] and/or inst.reloc.
4438 Preindexed addressing (.preind=1):
4440 [Rn, #offset] .reg=Rn .reloc.exp=offset
4441 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4442 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4443 .shift_kind=shift .reloc.exp=shift_imm
4445 These three may have a trailing ! which causes .writeback to be set also.
4447 Postindexed addressing (.postind=1, .writeback=1):
4449 [Rn], #offset .reg=Rn .reloc.exp=offset
4450 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4451 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4452 .shift_kind=shift .reloc.exp=shift_imm
4454 Unindexed addressing (.preind=0, .postind=0):
4456 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4460 [Rn]{!} shorthand for [Rn,#0]{!}
4461 =immediate .isreg=0 .reloc.exp=immediate
4462 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4464 It is the caller's responsibility to check for addressing modes not
4465 supported by the instruction, and to set inst.reloc.type. */
4467 static parse_operand_result
4468 parse_address_main (char **str
, int i
, int group_relocations
,
4469 group_reloc_type group_type
)
4474 if (skip_past_char (&p
, '[') == FAIL
)
4476 if (skip_past_char (&p
, '=') == FAIL
)
4478 /* bare address - translate to PC-relative offset */
4479 inst
.reloc
.pc_rel
= 1;
4480 inst
.operands
[i
].reg
= REG_PC
;
4481 inst
.operands
[i
].isreg
= 1;
4482 inst
.operands
[i
].preind
= 1;
4484 /* else a load-constant pseudo op, no special treatment needed here */
4486 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4487 return PARSE_OPERAND_FAIL
;
4490 return PARSE_OPERAND_SUCCESS
;
4493 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4495 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4496 return PARSE_OPERAND_FAIL
;
4498 inst
.operands
[i
].reg
= reg
;
4499 inst
.operands
[i
].isreg
= 1;
4501 if (skip_past_comma (&p
) == SUCCESS
)
4503 inst
.operands
[i
].preind
= 1;
4506 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4508 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4510 inst
.operands
[i
].imm
= reg
;
4511 inst
.operands
[i
].immisreg
= 1;
4513 if (skip_past_comma (&p
) == SUCCESS
)
4514 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4515 return PARSE_OPERAND_FAIL
;
4517 else if (skip_past_char (&p
, ':') == SUCCESS
)
4519 /* FIXME: '@' should be used here, but it's filtered out by generic
4520 code before we get to see it here. This may be subject to
4523 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4524 if (exp
.X_op
!= O_constant
)
4526 inst
.error
= _("alignment must be constant");
4527 return PARSE_OPERAND_FAIL
;
4529 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4530 inst
.operands
[i
].immisalign
= 1;
4531 /* Alignments are not pre-indexes. */
4532 inst
.operands
[i
].preind
= 0;
4536 if (inst
.operands
[i
].negative
)
4538 inst
.operands
[i
].negative
= 0;
4542 if (group_relocations
&&
4543 ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
4546 struct group_reloc_table_entry
*entry
;
4548 /* Skip over the #: or : sequence. */
4554 /* Try to parse a group relocation. Anything else is an
4556 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
4558 inst
.error
= _("unknown group relocation");
4559 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4562 /* We now have the group relocation table entry corresponding to
4563 the name in the assembler source. Next, we parse the
4565 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4566 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4568 /* Record the relocation type. */
4572 inst
.reloc
.type
= entry
->ldr_code
;
4576 inst
.reloc
.type
= entry
->ldrs_code
;
4580 inst
.reloc
.type
= entry
->ldc_code
;
4587 if (inst
.reloc
.type
== 0)
4589 inst
.error
= _("this group relocation is not allowed on this instruction");
4590 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4594 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4595 return PARSE_OPERAND_FAIL
;
4599 if (skip_past_char (&p
, ']') == FAIL
)
4601 inst
.error
= _("']' expected");
4602 return PARSE_OPERAND_FAIL
;
4605 if (skip_past_char (&p
, '!') == SUCCESS
)
4606 inst
.operands
[i
].writeback
= 1;
4608 else if (skip_past_comma (&p
) == SUCCESS
)
4610 if (skip_past_char (&p
, '{') == SUCCESS
)
4612 /* [Rn], {expr} - unindexed, with option */
4613 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
4614 0, 255, TRUE
) == FAIL
)
4615 return PARSE_OPERAND_FAIL
;
4617 if (skip_past_char (&p
, '}') == FAIL
)
4619 inst
.error
= _("'}' expected at end of 'option' field");
4620 return PARSE_OPERAND_FAIL
;
4622 if (inst
.operands
[i
].preind
)
4624 inst
.error
= _("cannot combine index with option");
4625 return PARSE_OPERAND_FAIL
;
4628 return PARSE_OPERAND_SUCCESS
;
4632 inst
.operands
[i
].postind
= 1;
4633 inst
.operands
[i
].writeback
= 1;
4635 if (inst
.operands
[i
].preind
)
4637 inst
.error
= _("cannot combine pre- and post-indexing");
4638 return PARSE_OPERAND_FAIL
;
4642 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4644 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4646 /* We might be using the immediate for alignment already. If we
4647 are, OR the register number into the low-order bits. */
4648 if (inst
.operands
[i
].immisalign
)
4649 inst
.operands
[i
].imm
|= reg
;
4651 inst
.operands
[i
].imm
= reg
;
4652 inst
.operands
[i
].immisreg
= 1;
4654 if (skip_past_comma (&p
) == SUCCESS
)
4655 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4656 return PARSE_OPERAND_FAIL
;
4660 if (inst
.operands
[i
].negative
)
4662 inst
.operands
[i
].negative
= 0;
4665 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4666 return PARSE_OPERAND_FAIL
;
4671 /* If at this point neither .preind nor .postind is set, we have a
4672 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
4673 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
4675 inst
.operands
[i
].preind
= 1;
4676 inst
.reloc
.exp
.X_op
= O_constant
;
4677 inst
.reloc
.exp
.X_add_number
= 0;
4680 return PARSE_OPERAND_SUCCESS
;
4684 parse_address (char **str
, int i
)
4686 return parse_address_main (str
, i
, 0, 0) == PARSE_OPERAND_SUCCESS
4690 static parse_operand_result
4691 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
4693 return parse_address_main (str
, i
, 1, type
);
4696 /* Parse an operand for a MOVW or MOVT instruction. */
4698 parse_half (char **str
)
4703 skip_past_char (&p
, '#');
4704 if (strncasecmp (p
, ":lower16:", 9) == 0)
4705 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
4706 else if (strncasecmp (p
, ":upper16:", 9) == 0)
4707 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
4709 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4715 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4718 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4720 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4722 inst
.error
= _("constant expression expected");
4725 if (inst
.reloc
.exp
.X_add_number
< 0
4726 || inst
.reloc
.exp
.X_add_number
> 0xffff)
4728 inst
.error
= _("immediate value out of range");
4736 /* Miscellaneous. */
4738 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
4739 or a bitmask suitable to be or-ed into the ARM msr instruction. */
4741 parse_psr (char **str
)
4744 unsigned long psr_field
;
4745 const struct asm_psr
*psr
;
4748 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
4749 feature for ease of use and backwards compatibility. */
4751 if (strncasecmp (p
, "SPSR", 4) == 0)
4752 psr_field
= SPSR_BIT
;
4753 else if (strncasecmp (p
, "CPSR", 4) == 0)
4760 while (ISALNUM (*p
) || *p
== '_');
4762 psr
= hash_find_n (arm_v7m_psr_hsh
, start
, p
- start
);
4773 /* A suffix follows. */
4779 while (ISALNUM (*p
) || *p
== '_');
4781 psr
= hash_find_n (arm_psr_hsh
, start
, p
- start
);
4785 psr_field
|= psr
->field
;
4790 goto error
; /* Garbage after "[CS]PSR". */
4792 psr_field
|= (PSR_c
| PSR_f
);
4798 inst
.error
= _("flag for {c}psr instruction expected");
4802 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
4803 value suitable for splatting into the AIF field of the instruction. */
4806 parse_cps_flags (char **str
)
4815 case '\0': case ',':
4818 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
4819 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
4820 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
4823 inst
.error
= _("unrecognized CPS flag");
4828 if (saw_a_flag
== 0)
4830 inst
.error
= _("missing CPS flags");
4838 /* Parse an endian specifier ("BE" or "LE", case insensitive);
4839 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
4842 parse_endian_specifier (char **str
)
4847 if (strncasecmp (s
, "BE", 2))
4849 else if (strncasecmp (s
, "LE", 2))
4853 inst
.error
= _("valid endian specifiers are be or le");
4857 if (ISALNUM (s
[2]) || s
[2] == '_')
4859 inst
.error
= _("valid endian specifiers are be or le");
4864 return little_endian
;
4867 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
4868 value suitable for poking into the rotate field of an sxt or sxta
4869 instruction, or FAIL on error. */
4872 parse_ror (char **str
)
4877 if (strncasecmp (s
, "ROR", 3) == 0)
4881 inst
.error
= _("missing rotation field after comma");
4885 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
4890 case 0: *str
= s
; return 0x0;
4891 case 8: *str
= s
; return 0x1;
4892 case 16: *str
= s
; return 0x2;
4893 case 24: *str
= s
; return 0x3;
4896 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
4901 /* Parse a conditional code (from conds[] below). The value returned is in the
4902 range 0 .. 14, or FAIL. */
4904 parse_cond (char **str
)
4907 const struct asm_cond
*c
;
4910 while (ISALPHA (*q
))
4913 c
= hash_find_n (arm_cond_hsh
, p
, q
- p
);
4916 inst
.error
= _("condition required");
4924 /* Parse an option for a barrier instruction. Returns the encoding for the
4927 parse_barrier (char **str
)
4930 const struct asm_barrier_opt
*o
;
4933 while (ISALPHA (*q
))
4936 o
= hash_find_n (arm_barrier_opt_hsh
, p
, q
- p
);
4944 /* Parse the operands of a table branch instruction. Similar to a memory
4947 parse_tb (char **str
)
4952 if (skip_past_char (&p
, '[') == FAIL
)
4954 inst
.error
= _("'[' expected");
4958 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4960 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4963 inst
.operands
[0].reg
= reg
;
4965 if (skip_past_comma (&p
) == FAIL
)
4967 inst
.error
= _("',' expected");
4971 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4973 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4976 inst
.operands
[0].imm
= reg
;
4978 if (skip_past_comma (&p
) == SUCCESS
)
4980 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
4982 if (inst
.reloc
.exp
.X_add_number
!= 1)
4984 inst
.error
= _("invalid shift");
4987 inst
.operands
[0].shifted
= 1;
4990 if (skip_past_char (&p
, ']') == FAIL
)
4992 inst
.error
= _("']' expected");
4999 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5000 information on the types the operands can take and how they are encoded.
5001 Up to four operands may be read; this function handles setting the
5002 ".present" field for each read operand itself.
5003 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5004 else returns FAIL. */
5007 parse_neon_mov (char **str
, int *which_operand
)
5009 int i
= *which_operand
, val
;
5010 enum arm_reg_type rtype
;
5012 struct neon_type_el optype
;
5014 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5016 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5017 inst
.operands
[i
].reg
= val
;
5018 inst
.operands
[i
].isscalar
= 1;
5019 inst
.operands
[i
].vectype
= optype
;
5020 inst
.operands
[i
++].present
= 1;
5022 if (skip_past_comma (&ptr
) == FAIL
)
5025 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5028 inst
.operands
[i
].reg
= val
;
5029 inst
.operands
[i
].isreg
= 1;
5030 inst
.operands
[i
].present
= 1;
5032 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5035 /* Cases 0, 1, 2, 3, 5 (D only). */
5036 if (skip_past_comma (&ptr
) == FAIL
)
5039 inst
.operands
[i
].reg
= val
;
5040 inst
.operands
[i
].isreg
= 1;
5041 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5042 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5043 inst
.operands
[i
].isvec
= 1;
5044 inst
.operands
[i
].vectype
= optype
;
5045 inst
.operands
[i
++].present
= 1;
5047 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5049 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5050 Case 13: VMOV <Sd>, <Rm> */
5051 inst
.operands
[i
].reg
= val
;
5052 inst
.operands
[i
].isreg
= 1;
5053 inst
.operands
[i
].present
= 1;
5055 if (rtype
== REG_TYPE_NQ
)
5057 first_error (_("can't use Neon quad register here"));
5060 else if (rtype
!= REG_TYPE_VFS
)
5063 if (skip_past_comma (&ptr
) == FAIL
)
5065 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5067 inst
.operands
[i
].reg
= val
;
5068 inst
.operands
[i
].isreg
= 1;
5069 inst
.operands
[i
].present
= 1;
5072 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5073 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5074 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5075 Case 10: VMOV.F32 <Sd>, #<imm>
5076 Case 11: VMOV.F64 <Dd>, #<imm> */
5078 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5079 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5080 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5082 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5085 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5086 Case 1: VMOV<c><q> <Dd>, <Dm>
5087 Case 8: VMOV.F32 <Sd>, <Sm>
5088 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5090 inst
.operands
[i
].reg
= val
;
5091 inst
.operands
[i
].isreg
= 1;
5092 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5093 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5094 inst
.operands
[i
].isvec
= 1;
5095 inst
.operands
[i
].vectype
= optype
;
5096 inst
.operands
[i
].present
= 1;
5098 if (skip_past_comma (&ptr
) == SUCCESS
)
5103 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5106 inst
.operands
[i
].reg
= val
;
5107 inst
.operands
[i
].isreg
= 1;
5108 inst
.operands
[i
++].present
= 1;
5110 if (skip_past_comma (&ptr
) == FAIL
)
5113 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5116 inst
.operands
[i
].reg
= val
;
5117 inst
.operands
[i
].isreg
= 1;
5118 inst
.operands
[i
++].present
= 1;
5123 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5127 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5130 inst
.operands
[i
].reg
= val
;
5131 inst
.operands
[i
].isreg
= 1;
5132 inst
.operands
[i
++].present
= 1;
5134 if (skip_past_comma (&ptr
) == FAIL
)
5137 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5139 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5140 inst
.operands
[i
].reg
= val
;
5141 inst
.operands
[i
].isscalar
= 1;
5142 inst
.operands
[i
].present
= 1;
5143 inst
.operands
[i
].vectype
= optype
;
5145 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5147 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5148 inst
.operands
[i
].reg
= val
;
5149 inst
.operands
[i
].isreg
= 1;
5150 inst
.operands
[i
++].present
= 1;
5152 if (skip_past_comma (&ptr
) == FAIL
)
5155 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5158 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5162 inst
.operands
[i
].reg
= val
;
5163 inst
.operands
[i
].isreg
= 1;
5164 inst
.operands
[i
].isvec
= 1;
5165 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5166 inst
.operands
[i
].vectype
= optype
;
5167 inst
.operands
[i
].present
= 1;
5169 if (rtype
== REG_TYPE_VFS
)
5173 if (skip_past_comma (&ptr
) == FAIL
)
5175 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5178 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5181 inst
.operands
[i
].reg
= val
;
5182 inst
.operands
[i
].isreg
= 1;
5183 inst
.operands
[i
].isvec
= 1;
5184 inst
.operands
[i
].issingle
= 1;
5185 inst
.operands
[i
].vectype
= optype
;
5186 inst
.operands
[i
].present
= 1;
5189 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5193 inst
.operands
[i
].reg
= val
;
5194 inst
.operands
[i
].isreg
= 1;
5195 inst
.operands
[i
].isvec
= 1;
5196 inst
.operands
[i
].issingle
= 1;
5197 inst
.operands
[i
].vectype
= optype
;
5198 inst
.operands
[i
++].present
= 1;
5203 first_error (_("parse error"));
5207 /* Successfully parsed the operands. Update args. */
5213 first_error (_("expected comma"));
5217 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5221 /* Matcher codes for parse_operands. */
5222 enum operand_parse_code
5224 OP_stop
, /* end of line */
5226 OP_RR
, /* ARM register */
5227 OP_RRnpc
, /* ARM register, not r15 */
5228 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5229 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5230 OP_RCP
, /* Coprocessor number */
5231 OP_RCN
, /* Coprocessor register */
5232 OP_RF
, /* FPA register */
5233 OP_RVS
, /* VFP single precision register */
5234 OP_RVD
, /* VFP double precision register (0..15) */
5235 OP_RND
, /* Neon double precision register (0..31) */
5236 OP_RNQ
, /* Neon quad precision register */
5237 OP_RVSD
, /* VFP single or double precision register */
5238 OP_RNDQ
, /* Neon double or quad precision register */
5239 OP_RNSDQ
, /* Neon single, double or quad precision register */
5240 OP_RNSC
, /* Neon scalar D[X] */
5241 OP_RVC
, /* VFP control register */
5242 OP_RMF
, /* Maverick F register */
5243 OP_RMD
, /* Maverick D register */
5244 OP_RMFX
, /* Maverick FX register */
5245 OP_RMDX
, /* Maverick DX register */
5246 OP_RMAX
, /* Maverick AX register */
5247 OP_RMDS
, /* Maverick DSPSC register */
5248 OP_RIWR
, /* iWMMXt wR register */
5249 OP_RIWC
, /* iWMMXt wC register */
5250 OP_RIWG
, /* iWMMXt wCG register */
5251 OP_RXA
, /* XScale accumulator register */
5253 OP_REGLST
, /* ARM register list */
5254 OP_VRSLST
, /* VFP single-precision register list */
5255 OP_VRDLST
, /* VFP double-precision register list */
5256 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5257 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5258 OP_NSTRLST
, /* Neon element/structure list */
5260 OP_NILO
, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5261 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5262 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5263 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5264 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5265 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5266 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5267 OP_VMOV
, /* Neon VMOV operands. */
5268 OP_RNDQ_IMVNb
,/* Neon D or Q reg, or immediate good for VMVN. */
5269 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5271 OP_I0
, /* immediate zero */
5272 OP_I7
, /* immediate value 0 .. 7 */
5273 OP_I15
, /* 0 .. 15 */
5274 OP_I16
, /* 1 .. 16 */
5275 OP_I16z
, /* 0 .. 16 */
5276 OP_I31
, /* 0 .. 31 */
5277 OP_I31w
, /* 0 .. 31, optional trailing ! */
5278 OP_I32
, /* 1 .. 32 */
5279 OP_I32z
, /* 0 .. 32 */
5280 OP_I63
, /* 0 .. 63 */
5281 OP_I63s
, /* -64 .. 63 */
5282 OP_I64
, /* 1 .. 64 */
5283 OP_I64z
, /* 0 .. 64 */
5284 OP_I255
, /* 0 .. 255 */
5286 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5287 OP_I7b
, /* 0 .. 7 */
5288 OP_I15b
, /* 0 .. 15 */
5289 OP_I31b
, /* 0 .. 31 */
5291 OP_SH
, /* shifter operand */
5292 OP_SHG
, /* shifter operand with possible group relocation */
5293 OP_ADDR
, /* Memory address expression (any mode) */
5294 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5295 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5296 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5297 OP_EXP
, /* arbitrary expression */
5298 OP_EXPi
, /* same, with optional immediate prefix */
5299 OP_EXPr
, /* same, with optional relocation suffix */
5300 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5302 OP_CPSF
, /* CPS flags */
5303 OP_ENDI
, /* Endianness specifier */
5304 OP_PSR
, /* CPSR/SPSR mask for msr */
5305 OP_COND
, /* conditional code */
5306 OP_TB
, /* Table branch. */
5308 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5309 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5311 OP_RRnpc_I0
, /* ARM register or literal 0 */
5312 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5313 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5314 OP_RF_IF
, /* FPA register or immediate */
5315 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5317 /* Optional operands. */
5318 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5319 OP_oI31b
, /* 0 .. 31 */
5320 OP_oI32b
, /* 1 .. 32 */
5321 OP_oIffffb
, /* 0 .. 65535 */
5322 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5324 OP_oRR
, /* ARM register */
5325 OP_oRRnpc
, /* ARM register, not the PC */
5326 OP_oRND
, /* Optional Neon double precision register */
5327 OP_oRNQ
, /* Optional Neon quad precision register */
5328 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5329 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5330 OP_oSHll
, /* LSL immediate */
5331 OP_oSHar
, /* ASR immediate */
5332 OP_oSHllar
, /* LSL or ASR immediate */
5333 OP_oROR
, /* ROR 0/8/16/24 */
5334 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5336 OP_FIRST_OPTIONAL
= OP_oI7b
5339 /* Generic instruction operand parser. This does no encoding and no
5340 semantic validation; it merely squirrels values away in the inst
5341 structure. Returns SUCCESS or FAIL depending on whether the
5342 specified grammar matched. */
5344 parse_operands (char *str
, const unsigned char *pattern
)
5346 unsigned const char *upat
= pattern
;
5347 char *backtrack_pos
= 0;
5348 const char *backtrack_error
= 0;
5349 int i
, val
, backtrack_index
= 0;
5350 enum arm_reg_type rtype
;
5351 parse_operand_result result
;
5353 #define po_char_or_fail(chr) do { \
5354 if (skip_past_char (&str, chr) == FAIL) \
5358 #define po_reg_or_fail(regtype) do { \
5359 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5360 &inst.operands[i].vectype); \
5363 first_error (_(reg_expected_msgs[regtype])); \
5366 inst.operands[i].reg = val; \
5367 inst.operands[i].isreg = 1; \
5368 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5369 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5370 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5371 || rtype == REG_TYPE_VFD \
5372 || rtype == REG_TYPE_NQ); \
5375 #define po_reg_or_goto(regtype, label) do { \
5376 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5377 &inst.operands[i].vectype); \
5381 inst.operands[i].reg = val; \
5382 inst.operands[i].isreg = 1; \
5383 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5384 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5385 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5386 || rtype == REG_TYPE_VFD \
5387 || rtype == REG_TYPE_NQ); \
5390 #define po_imm_or_fail(min, max, popt) do { \
5391 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5393 inst.operands[i].imm = val; \
5396 #define po_scalar_or_goto(elsz, label) do { \
5397 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \
5400 inst.operands[i].reg = val; \
5401 inst.operands[i].isscalar = 1; \
5404 #define po_misc_or_fail(expr) do { \
5409 #define po_misc_or_fail_no_backtrack(expr) do { \
5411 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
5412 backtrack_pos = 0; \
5413 if (result != PARSE_OPERAND_SUCCESS) \
5417 skip_whitespace (str
);
5419 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5421 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5423 /* Remember where we are in case we need to backtrack. */
5424 assert (!backtrack_pos
);
5425 backtrack_pos
= str
;
5426 backtrack_error
= inst
.error
;
5427 backtrack_index
= i
;
5431 po_char_or_fail (',');
5439 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5440 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5441 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5442 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5443 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5444 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5446 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5447 case OP_RVC
: po_reg_or_fail (REG_TYPE_VFC
); break;
5448 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5449 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5450 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5451 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5452 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5453 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5454 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5455 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5456 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5457 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5459 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
5461 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
5462 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
5464 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
5466 /* Neon scalar. Using an element size of 8 means that some invalid
5467 scalars are accepted here, so deal with those in later code. */
5468 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
5470 /* WARNING: We can expand to two operands here. This has the potential
5471 to totally confuse the backtracking mechanism! It will be OK at
5472 least as long as we don't try to use optional args as well,
5476 po_reg_or_goto (REG_TYPE_NDQ
, try_imm
);
5478 skip_past_comma (&str
);
5479 po_reg_or_goto (REG_TYPE_NDQ
, one_reg_only
);
5482 /* Optional register operand was omitted. Unfortunately, it's in
5483 operands[i-1] and we need it to be in inst.operands[i]. Fix that
5484 here (this is a bit grotty). */
5485 inst
.operands
[i
] = inst
.operands
[i
-1];
5486 inst
.operands
[i
-1].present
= 0;
5489 /* Immediate gets verified properly later, so accept any now. */
5490 po_imm_or_fail (INT_MIN
, INT_MAX
, TRUE
);
5496 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
5499 po_imm_or_fail (0, 0, TRUE
);
5504 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
5509 po_scalar_or_goto (8, try_rr
);
5512 po_reg_or_fail (REG_TYPE_RN
);
5518 po_scalar_or_goto (8, try_nsdq
);
5521 po_reg_or_fail (REG_TYPE_NSDQ
);
5527 po_scalar_or_goto (8, try_ndq
);
5530 po_reg_or_fail (REG_TYPE_NDQ
);
5536 po_scalar_or_goto (8, try_vfd
);
5539 po_reg_or_fail (REG_TYPE_VFD
);
5544 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
5545 not careful then bad things might happen. */
5546 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
5551 po_reg_or_goto (REG_TYPE_NDQ
, try_mvnimm
);
5554 /* There's a possibility of getting a 64-bit immediate here, so
5555 we need special handling. */
5556 if (parse_big_immediate (&str
, i
) == FAIL
)
5558 inst
.error
= _("immediate value is out of range");
5566 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
5569 po_imm_or_fail (0, 63, TRUE
);
5574 po_char_or_fail ('[');
5575 po_reg_or_fail (REG_TYPE_RN
);
5576 po_char_or_fail (']');
5580 po_reg_or_fail (REG_TYPE_RN
);
5581 if (skip_past_char (&str
, '!') == SUCCESS
)
5582 inst
.operands
[i
].writeback
= 1;
5586 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
5587 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
5588 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
5589 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
5590 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
5591 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
5592 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
5593 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
5594 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
5595 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
5596 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
5597 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
5599 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
5601 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
5602 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
5604 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
5605 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
5606 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
5608 /* Immediate variants */
5610 po_char_or_fail ('{');
5611 po_imm_or_fail (0, 255, TRUE
);
5612 po_char_or_fail ('}');
5616 /* The expression parser chokes on a trailing !, so we have
5617 to find it first and zap it. */
5620 while (*s
&& *s
!= ',')
5625 inst
.operands
[i
].writeback
= 1;
5627 po_imm_or_fail (0, 31, TRUE
);
5635 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5640 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5645 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5647 if (inst
.reloc
.exp
.X_op
== O_symbol
)
5649 val
= parse_reloc (&str
);
5652 inst
.error
= _("unrecognized relocation suffix");
5655 else if (val
!= BFD_RELOC_UNUSED
)
5657 inst
.operands
[i
].imm
= val
;
5658 inst
.operands
[i
].hasreloc
= 1;
5663 /* Operand for MOVW or MOVT. */
5665 po_misc_or_fail (parse_half (&str
));
5668 /* Register or expression */
5669 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
5670 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
5672 /* Register or immediate */
5673 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
5674 I0
: po_imm_or_fail (0, 0, FALSE
); break;
5676 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
5678 if (!is_immediate_prefix (*str
))
5681 val
= parse_fpa_immediate (&str
);
5684 /* FPA immediates are encoded as registers 8-15.
5685 parse_fpa_immediate has already applied the offset. */
5686 inst
.operands
[i
].reg
= val
;
5687 inst
.operands
[i
].isreg
= 1;
5690 /* Two kinds of register */
5693 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5694 if (rege
->type
!= REG_TYPE_MMXWR
5695 && rege
->type
!= REG_TYPE_MMXWC
5696 && rege
->type
!= REG_TYPE_MMXWCG
)
5698 inst
.error
= _("iWMMXt data or control register expected");
5701 inst
.operands
[i
].reg
= rege
->number
;
5702 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
5707 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
5708 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
5709 case OP_oROR
: val
= parse_ror (&str
); break;
5710 case OP_PSR
: val
= parse_psr (&str
); break;
5711 case OP_COND
: val
= parse_cond (&str
); break;
5712 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
5715 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
5716 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
5719 val
= parse_psr (&str
);
5723 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
5726 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
5728 if (strncasecmp (str
, "APSR_", 5) == 0)
5735 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
5736 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
5737 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
5738 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
5739 default: found
= 16;
5743 inst
.operands
[i
].isvec
= 1;
5750 po_misc_or_fail (parse_tb (&str
));
5753 /* Register lists */
5755 val
= parse_reg_list (&str
);
5758 inst
.operands
[1].writeback
= 1;
5764 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
5768 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
5772 /* Allow Q registers too. */
5773 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5778 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5780 inst
.operands
[i
].issingle
= 1;
5785 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5790 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
5791 &inst
.operands
[i
].vectype
);
5794 /* Addressing modes */
5796 po_misc_or_fail (parse_address (&str
, i
));
5800 po_misc_or_fail_no_backtrack (
5801 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
5805 po_misc_or_fail_no_backtrack (
5806 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
5810 po_misc_or_fail_no_backtrack (
5811 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
5815 po_misc_or_fail (parse_shifter_operand (&str
, i
));
5819 po_misc_or_fail_no_backtrack (
5820 parse_shifter_operand_group_reloc (&str
, i
));
5824 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
5828 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
5832 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
5836 as_fatal ("unhandled operand code %d", upat
[i
]);
5839 /* Various value-based sanity checks and shared operations. We
5840 do not signal immediate failures for the register constraints;
5841 this allows a syntax error to take precedence. */
5849 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
5850 inst
.error
= BAD_PC
;
5868 inst
.operands
[i
].imm
= val
;
5875 /* If we get here, this operand was successfully parsed. */
5876 inst
.operands
[i
].present
= 1;
5880 inst
.error
= BAD_ARGS
;
5885 /* The parse routine should already have set inst.error, but set a
5886 defaut here just in case. */
5888 inst
.error
= _("syntax error");
5892 /* Do not backtrack over a trailing optional argument that
5893 absorbed some text. We will only fail again, with the
5894 'garbage following instruction' error message, which is
5895 probably less helpful than the current one. */
5896 if (backtrack_index
== i
&& backtrack_pos
!= str
5897 && upat
[i
+1] == OP_stop
)
5900 inst
.error
= _("syntax error");
5904 /* Try again, skipping the optional argument at backtrack_pos. */
5905 str
= backtrack_pos
;
5906 inst
.error
= backtrack_error
;
5907 inst
.operands
[backtrack_index
].present
= 0;
5908 i
= backtrack_index
;
5912 /* Check that we have parsed all the arguments. */
5913 if (*str
!= '\0' && !inst
.error
)
5914 inst
.error
= _("garbage following instruction");
5916 return inst
.error
? FAIL
: SUCCESS
;
5919 #undef po_char_or_fail
5920 #undef po_reg_or_fail
5921 #undef po_reg_or_goto
5922 #undef po_imm_or_fail
5923 #undef po_scalar_or_fail
5925 /* Shorthand macro for instruction encoding functions issuing errors. */
5926 #define constraint(expr, err) do { \
5934 /* Functions for operand encoding. ARM, then Thumb. */
5936 #define rotate_left(v, n) (v << n | v >> (32 - n))
5938 /* If VAL can be encoded in the immediate field of an ARM instruction,
5939 return the encoded form. Otherwise, return FAIL. */
5942 encode_arm_immediate (unsigned int val
)
5946 for (i
= 0; i
< 32; i
+= 2)
5947 if ((a
= rotate_left (val
, i
)) <= 0xff)
5948 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
5953 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
5954 return the encoded form. Otherwise, return FAIL. */
5956 encode_thumb32_immediate (unsigned int val
)
5963 for (i
= 1; i
<= 24; i
++)
5966 if ((val
& ~(0xff << i
)) == 0)
5967 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
5971 if (val
== ((a
<< 16) | a
))
5973 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
5977 if (val
== ((a
<< 16) | a
))
5978 return 0x200 | (a
>> 8);
5982 /* Encode a VFP SP or DP register number into inst.instruction. */
5985 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
5987 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
5990 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
5993 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
5996 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6001 first_error (_("D register out of range for selected VFP version"));
6009 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6013 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6017 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6021 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6025 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6029 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6037 /* Encode a <shift> in an ARM-format instruction. The immediate,
6038 if any, is handled by md_apply_fix. */
6040 encode_arm_shift (int i
)
6042 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6043 inst
.instruction
|= SHIFT_ROR
<< 5;
6046 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6047 if (inst
.operands
[i
].immisreg
)
6049 inst
.instruction
|= SHIFT_BY_REG
;
6050 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6053 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6058 encode_arm_shifter_operand (int i
)
6060 if (inst
.operands
[i
].isreg
)
6062 inst
.instruction
|= inst
.operands
[i
].reg
;
6063 encode_arm_shift (i
);
6066 inst
.instruction
|= INST_IMMEDIATE
;
6069 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6071 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6073 assert (inst
.operands
[i
].isreg
);
6074 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6076 if (inst
.operands
[i
].preind
)
6080 inst
.error
= _("instruction does not accept preindexed addressing");
6083 inst
.instruction
|= PRE_INDEX
;
6084 if (inst
.operands
[i
].writeback
)
6085 inst
.instruction
|= WRITE_BACK
;
6088 else if (inst
.operands
[i
].postind
)
6090 assert (inst
.operands
[i
].writeback
);
6092 inst
.instruction
|= WRITE_BACK
;
6094 else /* unindexed - only for coprocessor */
6096 inst
.error
= _("instruction does not accept unindexed addressing");
6100 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6101 && (((inst
.instruction
& 0x000f0000) >> 16)
6102 == ((inst
.instruction
& 0x0000f000) >> 12)))
6103 as_warn ((inst
.instruction
& LOAD_BIT
)
6104 ? _("destination register same as write-back base")
6105 : _("source register same as write-back base"));
6108 /* inst.operands[i] was set up by parse_address. Encode it into an
6109 ARM-format mode 2 load or store instruction. If is_t is true,
6110 reject forms that cannot be used with a T instruction (i.e. not
6113 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6115 encode_arm_addr_mode_common (i
, is_t
);
6117 if (inst
.operands
[i
].immisreg
)
6119 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6120 inst
.instruction
|= inst
.operands
[i
].imm
;
6121 if (!inst
.operands
[i
].negative
)
6122 inst
.instruction
|= INDEX_UP
;
6123 if (inst
.operands
[i
].shifted
)
6125 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6126 inst
.instruction
|= SHIFT_ROR
<< 5;
6129 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6130 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6134 else /* immediate offset in inst.reloc */
6136 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6137 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6141 /* inst.operands[i] was set up by parse_address. Encode it into an
6142 ARM-format mode 3 load or store instruction. Reject forms that
6143 cannot be used with such instructions. If is_t is true, reject
6144 forms that cannot be used with a T instruction (i.e. not
6147 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6149 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6151 inst
.error
= _("instruction does not accept scaled register index");
6155 encode_arm_addr_mode_common (i
, is_t
);
6157 if (inst
.operands
[i
].immisreg
)
6159 inst
.instruction
|= inst
.operands
[i
].imm
;
6160 if (!inst
.operands
[i
].negative
)
6161 inst
.instruction
|= INDEX_UP
;
6163 else /* immediate offset in inst.reloc */
6165 inst
.instruction
|= HWOFFSET_IMM
;
6166 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6167 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6171 /* inst.operands[i] was set up by parse_address. Encode it into an
6172 ARM-format instruction. Reject all forms which cannot be encoded
6173 into a coprocessor load/store instruction. If wb_ok is false,
6174 reject use of writeback; if unind_ok is false, reject use of
6175 unindexed addressing. If reloc_override is not 0, use it instead
6176 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6177 (in which case it is preserved). */
6180 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6182 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6184 assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6186 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6188 assert (!inst
.operands
[i
].writeback
);
6191 inst
.error
= _("instruction does not support unindexed addressing");
6194 inst
.instruction
|= inst
.operands
[i
].imm
;
6195 inst
.instruction
|= INDEX_UP
;
6199 if (inst
.operands
[i
].preind
)
6200 inst
.instruction
|= PRE_INDEX
;
6202 if (inst
.operands
[i
].writeback
)
6204 if (inst
.operands
[i
].reg
== REG_PC
)
6206 inst
.error
= _("pc may not be used with write-back");
6211 inst
.error
= _("instruction does not support writeback");
6214 inst
.instruction
|= WRITE_BACK
;
6218 inst
.reloc
.type
= reloc_override
;
6219 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6220 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6221 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6224 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6226 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6232 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6233 Determine whether it can be performed with a move instruction; if
6234 it can, convert inst.instruction to that move instruction and
6235 return 1; if it can't, convert inst.instruction to a literal-pool
6236 load and return 0. If this is not a valid thing to do in the
6237 current context, set inst.error and return 1.
6239 inst.operands[i] describes the destination register. */
6242 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6247 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6251 if ((inst
.instruction
& tbit
) == 0)
6253 inst
.error
= _("invalid pseudo operation");
6256 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6258 inst
.error
= _("constant expression expected");
6261 if (inst
.reloc
.exp
.X_op
== O_constant
)
6265 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6267 /* This can be done with a mov(1) instruction. */
6268 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6269 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6275 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6278 /* This can be done with a mov instruction. */
6279 inst
.instruction
&= LITERAL_MASK
;
6280 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6281 inst
.instruction
|= value
& 0xfff;
6285 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6288 /* This can be done with a mvn instruction. */
6289 inst
.instruction
&= LITERAL_MASK
;
6290 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6291 inst
.instruction
|= value
& 0xfff;
6297 if (add_to_lit_pool () == FAIL
)
6299 inst
.error
= _("literal pool insertion failed");
6302 inst
.operands
[1].reg
= REG_PC
;
6303 inst
.operands
[1].isreg
= 1;
6304 inst
.operands
[1].preind
= 1;
6305 inst
.reloc
.pc_rel
= 1;
6306 inst
.reloc
.type
= (thumb_p
6307 ? BFD_RELOC_ARM_THUMB_OFFSET
6309 ? BFD_RELOC_ARM_HWLITERAL
6310 : BFD_RELOC_ARM_LITERAL
));
6314 /* Functions for instruction encoding, sorted by subarchitecture.
6315 First some generics; their names are taken from the conventional
6316 bit positions for register arguments in ARM format instructions. */
6326 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6332 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6333 inst
.instruction
|= inst
.operands
[1].reg
;
6339 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6340 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6346 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6347 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6353 unsigned Rn
= inst
.operands
[2].reg
;
6354 /* Enforce restrictions on SWP instruction. */
6355 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6356 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6357 _("Rn must not overlap other operands"));
6358 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6359 inst
.instruction
|= inst
.operands
[1].reg
;
6360 inst
.instruction
|= Rn
<< 16;
6366 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6367 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6368 inst
.instruction
|= inst
.operands
[2].reg
;
6374 inst
.instruction
|= inst
.operands
[0].reg
;
6375 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6376 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6382 inst
.instruction
|= inst
.operands
[0].imm
;
6388 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6389 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6392 /* ARM instructions, in alphabetical order by function name (except
6393 that wrapper functions appear immediately after the function they
6396 /* This is a pseudo-op of the form "adr rd, label" to be converted
6397 into a relative address of the form "add rd, pc, #label-.-8". */
6402 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6404 /* Frag hacking will turn this into a sub instruction if the offset turns
6405 out to be negative. */
6406 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6407 inst
.reloc
.pc_rel
= 1;
6408 inst
.reloc
.exp
.X_add_number
-= 8;
6411 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6412 into a relative address of the form:
6413 add rd, pc, #low(label-.-8)"
6414 add rd, rd, #high(label-.-8)" */
6419 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6421 /* Frag hacking will turn this into a sub instruction if the offset turns
6422 out to be negative. */
6423 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
6424 inst
.reloc
.pc_rel
= 1;
6425 inst
.size
= INSN_SIZE
* 2;
6426 inst
.reloc
.exp
.X_add_number
-= 8;
6432 if (!inst
.operands
[1].present
)
6433 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
6434 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6435 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6436 encode_arm_shifter_operand (2);
6442 if (inst
.operands
[0].present
)
6444 constraint ((inst
.instruction
& 0xf0) != 0x40
6445 && inst
.operands
[0].imm
!= 0xf,
6446 "bad barrier type");
6447 inst
.instruction
|= inst
.operands
[0].imm
;
6450 inst
.instruction
|= 0xf;
6456 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
6457 constraint (msb
> 32, _("bit-field extends past end of register"));
6458 /* The instruction encoding stores the LSB and MSB,
6459 not the LSB and width. */
6460 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6461 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
6462 inst
.instruction
|= (msb
- 1) << 16;
6470 /* #0 in second position is alternative syntax for bfc, which is
6471 the same instruction but with REG_PC in the Rm field. */
6472 if (!inst
.operands
[1].isreg
)
6473 inst
.operands
[1].reg
= REG_PC
;
6475 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
6476 constraint (msb
> 32, _("bit-field extends past end of register"));
6477 /* The instruction encoding stores the LSB and MSB,
6478 not the LSB and width. */
6479 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6480 inst
.instruction
|= inst
.operands
[1].reg
;
6481 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6482 inst
.instruction
|= (msb
- 1) << 16;
6488 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
6489 _("bit-field extends past end of register"));
6490 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6491 inst
.instruction
|= inst
.operands
[1].reg
;
6492 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6493 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
6496 /* ARM V5 breakpoint instruction (argument parse)
6497 BKPT <16 bit unsigned immediate>
6498 Instruction is not conditional.
6499 The bit pattern given in insns[] has the COND_ALWAYS condition,
6500 and it is an error if the caller tried to override that. */
6505 /* Top 12 of 16 bits to bits 19:8. */
6506 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
6508 /* Bottom 4 of 16 bits to bits 3:0. */
6509 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
6513 encode_branch (int default_reloc
)
6515 if (inst
.operands
[0].hasreloc
)
6517 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
6518 _("the only suffix valid here is '(plt)'"));
6519 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
6523 inst
.reloc
.type
= default_reloc
;
6525 inst
.reloc
.pc_rel
= 1;
6532 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6533 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6536 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6543 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6545 if (inst
.cond
== COND_ALWAYS
)
6546 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6548 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6552 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6555 /* ARM V5 branch-link-exchange instruction (argument parse)
6556 BLX <target_addr> ie BLX(1)
6557 BLX{<condition>} <Rm> ie BLX(2)
6558 Unfortunately, there are two different opcodes for this mnemonic.
6559 So, the insns[].value is not used, and the code here zaps values
6560 into inst.instruction.
6561 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
6566 if (inst
.operands
[0].isreg
)
6568 /* Arg is a register; the opcode provided by insns[] is correct.
6569 It is not illegal to do "blx pc", just useless. */
6570 if (inst
.operands
[0].reg
== REG_PC
)
6571 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
6573 inst
.instruction
|= inst
.operands
[0].reg
;
6577 /* Arg is an address; this instruction cannot be executed
6578 conditionally, and the opcode must be adjusted. */
6579 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
6580 inst
.instruction
= 0xfa000000;
6582 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6583 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6586 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
6593 if (inst
.operands
[0].reg
== REG_PC
)
6594 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
6596 inst
.instruction
|= inst
.operands
[0].reg
;
6600 /* ARM v5TEJ. Jump to Jazelle code. */
6605 if (inst
.operands
[0].reg
== REG_PC
)
6606 as_tsktsk (_("use of r15 in bxj is not really useful"));
6608 inst
.instruction
|= inst
.operands
[0].reg
;
6611 /* Co-processor data operation:
6612 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
6613 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
6617 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6618 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
6619 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6620 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6621 inst
.instruction
|= inst
.operands
[4].reg
;
6622 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6628 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6629 encode_arm_shifter_operand (1);
6632 /* Transfer between coprocessor and ARM registers.
6633 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
6638 No special properties. */
6643 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6644 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
6645 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6646 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6647 inst
.instruction
|= inst
.operands
[4].reg
;
6648 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6651 /* Transfer between coprocessor register and pair of ARM registers.
6652 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6657 Two XScale instructions are special cases of these:
6659 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
6660 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
6662 Result unpredicatable if Rd or Rn is R15. */
6667 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6668 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
6669 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6670 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6671 inst
.instruction
|= inst
.operands
[4].reg
;
6677 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
6678 inst
.instruction
|= inst
.operands
[1].imm
;
6684 inst
.instruction
|= inst
.operands
[0].imm
;
6690 /* There is no IT instruction in ARM mode. We
6691 process it but do not generate code for it. */
6698 int base_reg
= inst
.operands
[0].reg
;
6699 int range
= inst
.operands
[1].imm
;
6701 inst
.instruction
|= base_reg
<< 16;
6702 inst
.instruction
|= range
;
6704 if (inst
.operands
[1].writeback
)
6705 inst
.instruction
|= LDM_TYPE_2_OR_3
;
6707 if (inst
.operands
[0].writeback
)
6709 inst
.instruction
|= WRITE_BACK
;
6710 /* Check for unpredictable uses of writeback. */
6711 if (inst
.instruction
& LOAD_BIT
)
6713 /* Not allowed in LDM type 2. */
6714 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
6715 && ((range
& (1 << REG_PC
)) == 0))
6716 as_warn (_("writeback of base register is UNPREDICTABLE"));
6717 /* Only allowed if base reg not in list for other types. */
6718 else if (range
& (1 << base_reg
))
6719 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
6723 /* Not allowed for type 2. */
6724 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
6725 as_warn (_("writeback of base register is UNPREDICTABLE"));
6726 /* Only allowed if base reg not in list, or first in list. */
6727 else if ((range
& (1 << base_reg
))
6728 && (range
& ((1 << base_reg
) - 1)))
6729 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
6734 /* ARMv5TE load-consecutive (argument parse)
6743 constraint (inst
.operands
[0].reg
% 2 != 0,
6744 _("first destination register must be even"));
6745 constraint (inst
.operands
[1].present
6746 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
6747 _("can only load two consecutive registers"));
6748 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
6749 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
6751 if (!inst
.operands
[1].present
)
6752 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
6754 if (inst
.instruction
& LOAD_BIT
)
6756 /* encode_arm_addr_mode_3 will diagnose overlap between the base
6757 register and the first register written; we have to diagnose
6758 overlap between the base and the second register written here. */
6760 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
6761 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
6762 as_warn (_("base register written back, and overlaps "
6763 "second destination register"));
6765 /* For an index-register load, the index register must not overlap the
6766 destination (even if not write-back). */
6767 else if (inst
.operands
[2].immisreg
6768 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
6769 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
6770 as_warn (_("index register overlaps destination register"));
6773 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6774 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
6780 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
6781 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
6782 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
6783 || inst
.operands
[1].negative
6784 /* This can arise if the programmer has written
6786 or if they have mistakenly used a register name as the last
6789 It is very difficult to distinguish between these two cases
6790 because "rX" might actually be a label. ie the register
6791 name has been occluded by a symbol of the same name. So we
6792 just generate a general 'bad addressing mode' type error
6793 message and leave it up to the programmer to discover the
6794 true cause and fix their mistake. */
6795 || (inst
.operands
[1].reg
== REG_PC
),
6798 constraint (inst
.reloc
.exp
.X_op
!= O_constant
6799 || inst
.reloc
.exp
.X_add_number
!= 0,
6800 _("offset must be zero in ARM encoding"));
6802 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6803 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6804 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6810 constraint (inst
.operands
[0].reg
% 2 != 0,
6811 _("even register required"));
6812 constraint (inst
.operands
[1].present
6813 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
6814 _("can only load two consecutive registers"));
6815 /* If op 1 were present and equal to PC, this function wouldn't
6816 have been called in the first place. */
6817 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
6819 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6820 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6826 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6827 if (!inst
.operands
[1].isreg
)
6828 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
6830 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
6836 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
6838 if (inst
.operands
[1].preind
)
6840 constraint (inst
.reloc
.exp
.X_op
!= O_constant
||
6841 inst
.reloc
.exp
.X_add_number
!= 0,
6842 _("this instruction requires a post-indexed address"));
6844 inst
.operands
[1].preind
= 0;
6845 inst
.operands
[1].postind
= 1;
6846 inst
.operands
[1].writeback
= 1;
6848 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6849 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
6852 /* Halfword and signed-byte load/store operations. */
6857 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6858 if (!inst
.operands
[1].isreg
)
6859 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
6861 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
6867 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
6869 if (inst
.operands
[1].preind
)
6871 constraint (inst
.reloc
.exp
.X_op
!= O_constant
||
6872 inst
.reloc
.exp
.X_add_number
!= 0,
6873 _("this instruction requires a post-indexed address"));
6875 inst
.operands
[1].preind
= 0;
6876 inst
.operands
[1].postind
= 1;
6877 inst
.operands
[1].writeback
= 1;
6879 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6880 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
6883 /* Co-processor register load/store.
6884 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
6888 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6889 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6890 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
6896 /* This restriction does not apply to mls (nor to mla in v6, but
6897 that's hard to detect at present). */
6898 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
6899 && !(inst
.instruction
& 0x00400000))
6900 as_tsktsk (_("rd and rm should be different in mla"));
6902 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6903 inst
.instruction
|= inst
.operands
[1].reg
;
6904 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
6905 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
6912 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6913 encode_arm_shifter_operand (1);
6916 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
6923 top
= (inst
.instruction
& 0x00400000) != 0;
6924 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
6925 _(":lower16: not allowed this instruction"));
6926 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
6927 _(":upper16: not allowed instruction"));
6928 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6929 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6931 imm
= inst
.reloc
.exp
.X_add_number
;
6932 /* The value is in two pieces: 0:11, 16:19. */
6933 inst
.instruction
|= (imm
& 0x00000fff);
6934 inst
.instruction
|= (imm
& 0x0000f000) << 4;
6938 static void do_vfp_nsyn_opcode (const char *);
6941 do_vfp_nsyn_mrs (void)
6943 if (inst
.operands
[0].isvec
)
6945 if (inst
.operands
[1].reg
!= 1)
6946 first_error (_("operand 1 must be FPSCR"));
6947 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
6948 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
6949 do_vfp_nsyn_opcode ("fmstat");
6951 else if (inst
.operands
[1].isvec
)
6952 do_vfp_nsyn_opcode ("fmrx");
6960 do_vfp_nsyn_msr (void)
6962 if (inst
.operands
[0].isvec
)
6963 do_vfp_nsyn_opcode ("fmxr");
6973 if (do_vfp_nsyn_mrs () == SUCCESS
)
6976 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
6977 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
6979 _("'CPSR' or 'SPSR' expected"));
6980 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6981 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
6984 /* Two possible forms:
6985 "{C|S}PSR_<field>, Rm",
6986 "{C|S}PSR_f, #expression". */
6991 if (do_vfp_nsyn_msr () == SUCCESS
)
6994 inst
.instruction
|= inst
.operands
[0].imm
;
6995 if (inst
.operands
[1].isreg
)
6996 inst
.instruction
|= inst
.operands
[1].reg
;
6999 inst
.instruction
|= INST_IMMEDIATE
;
7000 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7001 inst
.reloc
.pc_rel
= 0;
7008 if (!inst
.operands
[2].present
)
7009 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7010 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7011 inst
.instruction
|= inst
.operands
[1].reg
;
7012 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7014 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7015 as_tsktsk (_("rd and rm should be different in mul"));
7018 /* Long Multiply Parser
7019 UMULL RdLo, RdHi, Rm, Rs
7020 SMULL RdLo, RdHi, Rm, Rs
7021 UMLAL RdLo, RdHi, Rm, Rs
7022 SMLAL RdLo, RdHi, Rm, Rs. */
7027 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7028 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7029 inst
.instruction
|= inst
.operands
[2].reg
;
7030 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7032 /* rdhi, rdlo and rm must all be different. */
7033 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7034 || inst
.operands
[0].reg
== inst
.operands
[2].reg
7035 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7036 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7042 if (inst
.operands
[0].present
)
7044 /* Architectural NOP hints are CPSR sets with no bits selected. */
7045 inst
.instruction
&= 0xf0000000;
7046 inst
.instruction
|= 0x0320f000 + inst
.operands
[0].imm
;
7050 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7051 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7052 Condition defaults to COND_ALWAYS.
7053 Error if Rd, Rn or Rm are R15. */
7058 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7059 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7060 inst
.instruction
|= inst
.operands
[2].reg
;
7061 if (inst
.operands
[3].present
)
7062 encode_arm_shift (3);
7065 /* ARM V6 PKHTB (Argument Parse). */
7070 if (!inst
.operands
[3].present
)
7072 /* If the shift specifier is omitted, turn the instruction
7073 into pkhbt rd, rm, rn. */
7074 inst
.instruction
&= 0xfff00010;
7075 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7076 inst
.instruction
|= inst
.operands
[1].reg
;
7077 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7081 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7082 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7083 inst
.instruction
|= inst
.operands
[2].reg
;
7084 encode_arm_shift (3);
7088 /* ARMv5TE: Preload-Cache
7092 Syntactically, like LDR with B=1, W=0, L=1. */
7097 constraint (!inst
.operands
[0].isreg
,
7098 _("'[' expected after PLD mnemonic"));
7099 constraint (inst
.operands
[0].postind
,
7100 _("post-indexed expression used in preload instruction"));
7101 constraint (inst
.operands
[0].writeback
,
7102 _("writeback used in preload instruction"));
7103 constraint (!inst
.operands
[0].preind
,
7104 _("unindexed addressing used in preload instruction"));
7105 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7108 /* ARMv7: PLI <addr_mode> */
7112 constraint (!inst
.operands
[0].isreg
,
7113 _("'[' expected after PLI mnemonic"));
7114 constraint (inst
.operands
[0].postind
,
7115 _("post-indexed expression used in preload instruction"));
7116 constraint (inst
.operands
[0].writeback
,
7117 _("writeback used in preload instruction"));
7118 constraint (!inst
.operands
[0].preind
,
7119 _("unindexed addressing used in preload instruction"));
7120 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7121 inst
.instruction
&= ~PRE_INDEX
;
7127 inst
.operands
[1] = inst
.operands
[0];
7128 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7129 inst
.operands
[0].isreg
= 1;
7130 inst
.operands
[0].writeback
= 1;
7131 inst
.operands
[0].reg
= REG_SP
;
7135 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7136 word at the specified address and the following word
7138 Unconditionally executed.
7139 Error if Rn is R15. */
7144 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7145 if (inst
.operands
[0].writeback
)
7146 inst
.instruction
|= WRITE_BACK
;
7149 /* ARM V6 ssat (argument parse). */
7154 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7155 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7156 inst
.instruction
|= inst
.operands
[2].reg
;
7158 if (inst
.operands
[3].present
)
7159 encode_arm_shift (3);
7162 /* ARM V6 usat (argument parse). */
7167 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7168 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7169 inst
.instruction
|= inst
.operands
[2].reg
;
7171 if (inst
.operands
[3].present
)
7172 encode_arm_shift (3);
7175 /* ARM V6 ssat16 (argument parse). */
7180 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7181 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7182 inst
.instruction
|= inst
.operands
[2].reg
;
7188 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7189 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7190 inst
.instruction
|= inst
.operands
[2].reg
;
7193 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7194 preserving the other bits.
7196 setend <endian_specifier>, where <endian_specifier> is either
7202 if (inst
.operands
[0].imm
)
7203 inst
.instruction
|= 0x200;
7209 unsigned int Rm
= (inst
.operands
[1].present
7210 ? inst
.operands
[1].reg
7211 : inst
.operands
[0].reg
);
7213 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7214 inst
.instruction
|= Rm
;
7215 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7217 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7218 inst
.instruction
|= SHIFT_BY_REG
;
7221 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7227 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7228 inst
.reloc
.pc_rel
= 0;
7234 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7235 inst
.reloc
.pc_rel
= 0;
7238 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7239 SMLAxy{cond} Rd,Rm,Rs,Rn
7240 SMLAWy{cond} Rd,Rm,Rs,Rn
7241 Error if any register is R15. */
7246 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7247 inst
.instruction
|= inst
.operands
[1].reg
;
7248 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7249 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7252 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7253 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7254 Error if any register is R15.
7255 Warning if Rdlo == Rdhi. */
7260 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7261 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7262 inst
.instruction
|= inst
.operands
[2].reg
;
7263 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7265 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7266 as_tsktsk (_("rdhi and rdlo must be different"));
7269 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7270 SMULxy{cond} Rd,Rm,Rs
7271 Error if any register is R15. */
7276 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7277 inst
.instruction
|= inst
.operands
[1].reg
;
7278 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7281 /* ARM V6 srs (argument parse). */
7286 inst
.instruction
|= inst
.operands
[0].imm
;
7287 if (inst
.operands
[0].writeback
)
7288 inst
.instruction
|= WRITE_BACK
;
7291 /* ARM V6 strex (argument parse). */
7296 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7297 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7298 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7299 || inst
.operands
[2].negative
7300 /* See comment in do_ldrex(). */
7301 || (inst
.operands
[2].reg
== REG_PC
),
7304 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7305 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
7307 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7308 || inst
.reloc
.exp
.X_add_number
!= 0,
7309 _("offset must be zero in ARM encoding"));
7311 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7312 inst
.instruction
|= inst
.operands
[1].reg
;
7313 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7314 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7320 constraint (inst
.operands
[1].reg
% 2 != 0,
7321 _("even register required"));
7322 constraint (inst
.operands
[2].present
7323 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
7324 _("can only store two consecutive registers"));
7325 /* If op 2 were present and equal to PC, this function wouldn't
7326 have been called in the first place. */
7327 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
7329 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7330 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
7331 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
7334 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7335 inst
.instruction
|= inst
.operands
[1].reg
;
7336 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7339 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7340 extends it to 32-bits, and adds the result to a value in another
7341 register. You can specify a rotation by 0, 8, 16, or 24 bits
7342 before extracting the 16-bit value.
7343 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7344 Condition defaults to COND_ALWAYS.
7345 Error if any register uses R15. */
7350 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7351 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7352 inst
.instruction
|= inst
.operands
[2].reg
;
7353 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
7358 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
7359 Condition defaults to COND_ALWAYS.
7360 Error if any register uses R15. */
7365 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7366 inst
.instruction
|= inst
.operands
[1].reg
;
7367 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
7370 /* VFP instructions. In a logical order: SP variant first, monad
7371 before dyad, arithmetic then move then load/store. */
7374 do_vfp_sp_monadic (void)
7376 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7377 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7381 do_vfp_sp_dyadic (void)
7383 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7384 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7385 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7389 do_vfp_sp_compare_z (void)
7391 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7395 do_vfp_dp_sp_cvt (void)
7397 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7398 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7402 do_vfp_sp_dp_cvt (void)
7404 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7405 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7409 do_vfp_reg_from_sp (void)
7411 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7412 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7416 do_vfp_reg2_from_sp2 (void)
7418 constraint (inst
.operands
[2].imm
!= 2,
7419 _("only two consecutive VFP SP registers allowed here"));
7420 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7421 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7422 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7426 do_vfp_sp_from_reg (void)
7428 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
7429 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7433 do_vfp_sp2_from_reg2 (void)
7435 constraint (inst
.operands
[0].imm
!= 2,
7436 _("only two consecutive VFP SP registers allowed here"));
7437 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
7438 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7439 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7443 do_vfp_sp_ldst (void)
7445 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7446 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7450 do_vfp_dp_ldst (void)
7452 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7453 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7458 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
7460 if (inst
.operands
[0].writeback
)
7461 inst
.instruction
|= WRITE_BACK
;
7463 constraint (ldstm_type
!= VFP_LDSTMIA
,
7464 _("this addressing mode requires base-register writeback"));
7465 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7466 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
7467 inst
.instruction
|= inst
.operands
[1].imm
;
7471 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
7475 if (inst
.operands
[0].writeback
)
7476 inst
.instruction
|= WRITE_BACK
;
7478 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
7479 _("this addressing mode requires base-register writeback"));
7481 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7482 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7484 count
= inst
.operands
[1].imm
<< 1;
7485 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
7488 inst
.instruction
|= count
;
7492 do_vfp_sp_ldstmia (void)
7494 vfp_sp_ldstm (VFP_LDSTMIA
);
7498 do_vfp_sp_ldstmdb (void)
7500 vfp_sp_ldstm (VFP_LDSTMDB
);
7504 do_vfp_dp_ldstmia (void)
7506 vfp_dp_ldstm (VFP_LDSTMIA
);
7510 do_vfp_dp_ldstmdb (void)
7512 vfp_dp_ldstm (VFP_LDSTMDB
);
7516 do_vfp_xp_ldstmia (void)
7518 vfp_dp_ldstm (VFP_LDSTMIAX
);
7522 do_vfp_xp_ldstmdb (void)
7524 vfp_dp_ldstm (VFP_LDSTMDBX
);
7528 do_vfp_dp_rd_rm (void)
7530 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7531 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7535 do_vfp_dp_rn_rd (void)
7537 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
7538 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7542 do_vfp_dp_rd_rn (void)
7544 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7545 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7549 do_vfp_dp_rd_rn_rm (void)
7551 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7552 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7553 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
7559 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7563 do_vfp_dp_rm_rd_rn (void)
7565 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
7566 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7567 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
7570 /* VFPv3 instructions. */
7572 do_vfp_sp_const (void)
7574 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7575 inst
.instruction
|= (inst
.operands
[1].imm
& 15) << 16;
7576 inst
.instruction
|= (inst
.operands
[1].imm
>> 4);
7580 do_vfp_dp_const (void)
7582 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7583 inst
.instruction
|= (inst
.operands
[1].imm
& 15) << 16;
7584 inst
.instruction
|= (inst
.operands
[1].imm
>> 4);
7588 vfp_conv (int srcsize
)
7590 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
7591 inst
.instruction
|= (immbits
& 1) << 5;
7592 inst
.instruction
|= (immbits
>> 1);
7596 do_vfp_sp_conv_16 (void)
7598 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7603 do_vfp_dp_conv_16 (void)
7605 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7610 do_vfp_sp_conv_32 (void)
7612 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7617 do_vfp_dp_conv_32 (void)
7619 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7624 /* FPA instructions. Also in a logical order. */
7629 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7630 inst
.instruction
|= inst
.operands
[1].reg
;
7634 do_fpa_ldmstm (void)
7636 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7637 switch (inst
.operands
[1].imm
)
7639 case 1: inst
.instruction
|= CP_T_X
; break;
7640 case 2: inst
.instruction
|= CP_T_Y
; break;
7641 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
7646 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
7648 /* The instruction specified "ea" or "fd", so we can only accept
7649 [Rn]{!}. The instruction does not really support stacking or
7650 unstacking, so we have to emulate these by setting appropriate
7651 bits and offsets. */
7652 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7653 || inst
.reloc
.exp
.X_add_number
!= 0,
7654 _("this instruction does not support indexing"));
7656 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
7657 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
7659 if (!(inst
.instruction
& INDEX_UP
))
7660 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
7662 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
7664 inst
.operands
[2].preind
= 0;
7665 inst
.operands
[2].postind
= 1;
7669 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7673 /* iWMMXt instructions: strictly in alphabetical order. */
7676 do_iwmmxt_tandorc (void)
7678 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
7682 do_iwmmxt_textrc (void)
7684 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7685 inst
.instruction
|= inst
.operands
[1].imm
;
7689 do_iwmmxt_textrm (void)
7691 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7692 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7693 inst
.instruction
|= inst
.operands
[2].imm
;
7697 do_iwmmxt_tinsr (void)
7699 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7700 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7701 inst
.instruction
|= inst
.operands
[2].imm
;
7705 do_iwmmxt_tmia (void)
7707 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
7708 inst
.instruction
|= inst
.operands
[1].reg
;
7709 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7713 do_iwmmxt_waligni (void)
7715 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7716 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7717 inst
.instruction
|= inst
.operands
[2].reg
;
7718 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
7722 do_iwmmxt_wmov (void)
7724 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
7725 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7726 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7727 inst
.instruction
|= inst
.operands
[1].reg
;
7731 do_iwmmxt_wldstbh (void)
7734 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7736 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
7738 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
7739 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
7743 do_iwmmxt_wldstw (void)
7745 /* RIWR_RIWC clears .isreg for a control register. */
7746 if (!inst
.operands
[0].isreg
)
7748 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7749 inst
.instruction
|= 0xf0000000;
7752 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7753 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7757 do_iwmmxt_wldstd (void)
7759 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7760 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
7764 do_iwmmxt_wshufh (void)
7766 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7767 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7768 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
7769 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
7773 do_iwmmxt_wzero (void)
7775 /* WZERO reg is an alias for WANDN reg, reg, reg. */
7776 inst
.instruction
|= inst
.operands
[0].reg
;
7777 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7778 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7781 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
7782 operations first, then control, shift, and load/store. */
7784 /* Insns like "foo X,Y,Z". */
7787 do_mav_triple (void)
7789 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7790 inst
.instruction
|= inst
.operands
[1].reg
;
7791 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7794 /* Insns like "foo W,X,Y,Z".
7795 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
7800 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
7801 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7802 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7803 inst
.instruction
|= inst
.operands
[3].reg
;
7806 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
7810 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7813 /* Maverick shift immediate instructions.
7814 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
7815 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
7820 int imm
= inst
.operands
[2].imm
;
7822 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7823 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7825 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
7826 Bits 5-7 of the insn should have bits 4-6 of the immediate.
7827 Bit 4 should be 0. */
7828 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
7830 inst
.instruction
|= imm
;
7833 /* XScale instructions. Also sorted arithmetic before move. */
7835 /* Xscale multiply-accumulate (argument parse)
7838 MIAxycc acc0,Rm,Rs. */
7843 inst
.instruction
|= inst
.operands
[1].reg
;
7844 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7847 /* Xscale move-accumulator-register (argument parse)
7849 MARcc acc0,RdLo,RdHi. */
7854 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7855 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7858 /* Xscale move-register-accumulator (argument parse)
7860 MRAcc RdLo,RdHi,acc0. */
7865 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
7866 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7867 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7870 /* Encoding functions relevant only to Thumb. */
7872 /* inst.operands[i] is a shifted-register operand; encode
7873 it into inst.instruction in the format used by Thumb32. */
7876 encode_thumb32_shifted_operand (int i
)
7878 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
7879 unsigned int shift
= inst
.operands
[i
].shift_kind
;
7881 constraint (inst
.operands
[i
].immisreg
,
7882 _("shift by register not allowed in thumb mode"));
7883 inst
.instruction
|= inst
.operands
[i
].reg
;
7884 if (shift
== SHIFT_RRX
)
7885 inst
.instruction
|= SHIFT_ROR
<< 4;
7888 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
7889 _("expression too complex"));
7891 constraint (value
> 32
7892 || (value
== 32 && (shift
== SHIFT_LSL
7893 || shift
== SHIFT_ROR
)),
7894 _("shift expression is too large"));
7898 else if (value
== 32)
7901 inst
.instruction
|= shift
<< 4;
7902 inst
.instruction
|= (value
& 0x1c) << 10;
7903 inst
.instruction
|= (value
& 0x03) << 6;
7908 /* inst.operands[i] was set up by parse_address. Encode it into a
7909 Thumb32 format load or store instruction. Reject forms that cannot
7910 be used with such instructions. If is_t is true, reject forms that
7911 cannot be used with a T instruction; if is_d is true, reject forms
7912 that cannot be used with a D instruction. */
7915 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
7917 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7919 constraint (!inst
.operands
[i
].isreg
,
7920 _("Instruction does not support =N addresses"));
7922 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7923 if (inst
.operands
[i
].immisreg
)
7925 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
7926 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
7927 constraint (inst
.operands
[i
].negative
,
7928 _("Thumb does not support negative register indexing"));
7929 constraint (inst
.operands
[i
].postind
,
7930 _("Thumb does not support register post-indexing"));
7931 constraint (inst
.operands
[i
].writeback
,
7932 _("Thumb does not support register indexing with writeback"));
7933 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
7934 _("Thumb supports only LSL in shifted register indexing"));
7936 inst
.instruction
|= inst
.operands
[i
].imm
;
7937 if (inst
.operands
[i
].shifted
)
7939 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
7940 _("expression too complex"));
7941 constraint (inst
.reloc
.exp
.X_add_number
< 0
7942 || inst
.reloc
.exp
.X_add_number
> 3,
7943 _("shift out of range"));
7944 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
7946 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7948 else if (inst
.operands
[i
].preind
)
7950 constraint (is_pc
&& inst
.operands
[i
].writeback
,
7951 _("cannot use writeback with PC-relative addressing"));
7952 constraint (is_t
&& inst
.operands
[i
].writeback
,
7953 _("cannot use writeback with this instruction"));
7957 inst
.instruction
|= 0x01000000;
7958 if (inst
.operands
[i
].writeback
)
7959 inst
.instruction
|= 0x00200000;
7963 inst
.instruction
|= 0x00000c00;
7964 if (inst
.operands
[i
].writeback
)
7965 inst
.instruction
|= 0x00000100;
7967 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
7969 else if (inst
.operands
[i
].postind
)
7971 assert (inst
.operands
[i
].writeback
);
7972 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
7973 constraint (is_t
, _("cannot use post-indexing with this instruction"));
7976 inst
.instruction
|= 0x00200000;
7978 inst
.instruction
|= 0x00000900;
7979 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
7981 else /* unindexed - only for coprocessor */
7982 inst
.error
= _("instruction does not accept unindexed addressing");
7985 /* Table of Thumb instructions which exist in both 16- and 32-bit
7986 encodings (the latter only in post-V6T2 cores). The index is the
7987 value used in the insns table below. When there is more than one
7988 possible 16-bit encoding for the instruction, this table always
7990 Also contains several pseudo-instructions used during relaxation. */
7991 #define T16_32_TAB \
7992 X(adc, 4140, eb400000), \
7993 X(adcs, 4140, eb500000), \
7994 X(add, 1c00, eb000000), \
7995 X(adds, 1c00, eb100000), \
7996 X(addi, 0000, f1000000), \
7997 X(addis, 0000, f1100000), \
7998 X(add_pc,000f, f20f0000), \
7999 X(add_sp,000d, f10d0000), \
8000 X(adr, 000f, f20f0000), \
8001 X(and, 4000, ea000000), \
8002 X(ands, 4000, ea100000), \
8003 X(asr, 1000, fa40f000), \
8004 X(asrs, 1000, fa50f000), \
8005 X(b, e000, f000b000), \
8006 X(bcond, d000, f0008000), \
8007 X(bic, 4380, ea200000), \
8008 X(bics, 4380, ea300000), \
8009 X(cmn, 42c0, eb100f00), \
8010 X(cmp, 2800, ebb00f00), \
8011 X(cpsie, b660, f3af8400), \
8012 X(cpsid, b670, f3af8600), \
8013 X(cpy, 4600, ea4f0000), \
8014 X(dec_sp,80dd, f1bd0d00), \
8015 X(eor, 4040, ea800000), \
8016 X(eors, 4040, ea900000), \
8017 X(inc_sp,00dd, f10d0d00), \
8018 X(ldmia, c800, e8900000), \
8019 X(ldr, 6800, f8500000), \
8020 X(ldrb, 7800, f8100000), \
8021 X(ldrh, 8800, f8300000), \
8022 X(ldrsb, 5600, f9100000), \
8023 X(ldrsh, 5e00, f9300000), \
8024 X(ldr_pc,4800, f85f0000), \
8025 X(ldr_pc2,4800, f85f0000), \
8026 X(ldr_sp,9800, f85d0000), \
8027 X(lsl, 0000, fa00f000), \
8028 X(lsls, 0000, fa10f000), \
8029 X(lsr, 0800, fa20f000), \
8030 X(lsrs, 0800, fa30f000), \
8031 X(mov, 2000, ea4f0000), \
8032 X(movs, 2000, ea5f0000), \
8033 X(mul, 4340, fb00f000), \
8034 X(muls, 4340, ffffffff), /* no 32b muls */ \
8035 X(mvn, 43c0, ea6f0000), \
8036 X(mvns, 43c0, ea7f0000), \
8037 X(neg, 4240, f1c00000), /* rsb #0 */ \
8038 X(negs, 4240, f1d00000), /* rsbs #0 */ \
8039 X(orr, 4300, ea400000), \
8040 X(orrs, 4300, ea500000), \
8041 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8042 X(push, b400, e92d0000), /* stmdb sp!,... */ \
8043 X(rev, ba00, fa90f080), \
8044 X(rev16, ba40, fa90f090), \
8045 X(revsh, bac0, fa90f0b0), \
8046 X(ror, 41c0, fa60f000), \
8047 X(rors, 41c0, fa70f000), \
8048 X(sbc, 4180, eb600000), \
8049 X(sbcs, 4180, eb700000), \
8050 X(stmia, c000, e8800000), \
8051 X(str, 6000, f8400000), \
8052 X(strb, 7000, f8000000), \
8053 X(strh, 8000, f8200000), \
8054 X(str_sp,9000, f84d0000), \
8055 X(sub, 1e00, eba00000), \
8056 X(subs, 1e00, ebb00000), \
8057 X(subi, 8000, f1a00000), \
8058 X(subis, 8000, f1b00000), \
8059 X(sxtb, b240, fa4ff080), \
8060 X(sxth, b200, fa0ff080), \
8061 X(tst, 4200, ea100f00), \
8062 X(uxtb, b2c0, fa5ff080), \
8063 X(uxth, b280, fa1ff080), \
8064 X(nop, bf00, f3af8000), \
8065 X(yield, bf10, f3af8001), \
8066 X(wfe, bf20, f3af8002), \
8067 X(wfi, bf30, f3af8003), \
8068 X(sev, bf40, f3af9004), /* typo, 8004? */
8070 /* To catch errors in encoding functions, the codes are all offset by
8071 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8072 as 16-bit instructions. */
8073 #define X(a,b,c) T_MNEM_##a
8074 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8077 #define X(a,b,c) 0x##b
8078 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8079 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8082 #define X(a,b,c) 0x##c
8083 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8084 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8085 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8089 /* Thumb instruction encoders, in alphabetical order. */
8093 do_t_add_sub_w (void)
8097 Rd
= inst
.operands
[0].reg
;
8098 Rn
= inst
.operands
[1].reg
;
8100 constraint (Rd
== 15, _("PC not allowed as destination"));
8101 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8102 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8105 /* Parse an add or subtract instruction. We get here with inst.instruction
8106 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8113 Rd
= inst
.operands
[0].reg
;
8114 Rs
= (inst
.operands
[1].present
8115 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8116 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8124 flags
= (inst
.instruction
== T_MNEM_adds
8125 || inst
.instruction
== T_MNEM_subs
);
8127 narrow
= (current_it_mask
== 0);
8129 narrow
= (current_it_mask
!= 0);
8130 if (!inst
.operands
[2].isreg
)
8133 if (inst
.size_req
!= 4)
8137 add
= (inst
.instruction
== T_MNEM_add
8138 || inst
.instruction
== T_MNEM_adds
);
8139 /* Attempt to use a narrow opcode, with relaxation if
8141 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8142 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8143 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8144 opcode
= T_MNEM_add_sp
;
8145 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8146 opcode
= T_MNEM_add_pc
;
8147 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8150 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8152 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8156 inst
.instruction
= THUMB_OP16(opcode
);
8157 inst
.instruction
|= (Rd
<< 4) | Rs
;
8158 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8159 if (inst
.size_req
!= 2)
8160 inst
.relax
= opcode
;
8163 constraint (inst
.size_req
== 2, BAD_HIREG
);
8165 if (inst
.size_req
== 4
8166 || (inst
.size_req
!= 2 && !opcode
))
8168 /* ??? Convert large immediates to addw/subw. */
8169 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8170 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8171 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8172 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8173 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8178 Rn
= inst
.operands
[2].reg
;
8179 /* See if we can do this with a 16-bit instruction. */
8180 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
8182 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8187 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
8188 || inst
.instruction
== T_MNEM_add
)
8191 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8195 if (inst
.instruction
== T_MNEM_add
)
8199 inst
.instruction
= T_OPCODE_ADD_HI
;
8200 inst
.instruction
|= (Rd
& 8) << 4;
8201 inst
.instruction
|= (Rd
& 7);
8202 inst
.instruction
|= Rn
<< 3;
8205 /* ... because addition is commutative! */
8208 inst
.instruction
= T_OPCODE_ADD_HI
;
8209 inst
.instruction
|= (Rd
& 8) << 4;
8210 inst
.instruction
|= (Rd
& 7);
8211 inst
.instruction
|= Rs
<< 3;
8216 /* If we get here, it can't be done in 16 bits. */
8217 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
8218 _("shift must be constant"));
8219 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8220 inst
.instruction
|= Rd
<< 8;
8221 inst
.instruction
|= Rs
<< 16;
8222 encode_thumb32_shifted_operand (2);
8227 constraint (inst
.instruction
== T_MNEM_adds
8228 || inst
.instruction
== T_MNEM_subs
,
8231 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
8233 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
8234 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
8237 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8239 inst
.instruction
|= (Rd
<< 4) | Rs
;
8240 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8244 Rn
= inst
.operands
[2].reg
;
8245 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
8247 /* We now have Rd, Rs, and Rn set to registers. */
8248 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8250 /* Can't do this for SUB. */
8251 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
8252 inst
.instruction
= T_OPCODE_ADD_HI
;
8253 inst
.instruction
|= (Rd
& 8) << 4;
8254 inst
.instruction
|= (Rd
& 7);
8256 inst
.instruction
|= Rn
<< 3;
8258 inst
.instruction
|= Rs
<< 3;
8260 constraint (1, _("dest must overlap one source register"));
8264 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8265 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
8266 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8274 if (unified_syntax
&& inst
.size_req
== 0 && inst
.operands
[0].reg
<= 7)
8276 /* Defer to section relaxation. */
8277 inst
.relax
= inst
.instruction
;
8278 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8279 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8281 else if (unified_syntax
&& inst
.size_req
!= 2)
8283 /* Generate a 32-bit opcode. */
8284 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8285 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8286 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
8287 inst
.reloc
.pc_rel
= 1;
8291 /* Generate a 16-bit opcode. */
8292 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8293 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8294 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
8295 inst
.reloc
.pc_rel
= 1;
8297 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8301 /* Arithmetic instructions for which there is just one 16-bit
8302 instruction encoding, and it allows only two low registers.
8303 For maximal compatibility with ARM syntax, we allow three register
8304 operands even when Thumb-32 instructions are not available, as long
8305 as the first two are identical. For instance, both "sbc r0,r1" and
8306 "sbc r0,r0,r1" are allowed. */
8312 Rd
= inst
.operands
[0].reg
;
8313 Rs
= (inst
.operands
[1].present
8314 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8315 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8316 Rn
= inst
.operands
[2].reg
;
8320 if (!inst
.operands
[2].isreg
)
8322 /* For an immediate, we always generate a 32-bit opcode;
8323 section relaxation will shrink it later if possible. */
8324 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8325 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8326 inst
.instruction
|= Rd
<< 8;
8327 inst
.instruction
|= Rs
<< 16;
8328 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8334 /* See if we can do this with a 16-bit instruction. */
8335 if (THUMB_SETS_FLAGS (inst
.instruction
))
8336 narrow
= current_it_mask
== 0;
8338 narrow
= current_it_mask
!= 0;
8340 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8342 if (inst
.operands
[2].shifted
)
8344 if (inst
.size_req
== 4)
8350 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8351 inst
.instruction
|= Rd
;
8352 inst
.instruction
|= Rn
<< 3;
8356 /* If we get here, it can't be done in 16 bits. */
8357 constraint (inst
.operands
[2].shifted
8358 && inst
.operands
[2].immisreg
,
8359 _("shift must be constant"));
8360 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8361 inst
.instruction
|= Rd
<< 8;
8362 inst
.instruction
|= Rs
<< 16;
8363 encode_thumb32_shifted_operand (2);
8368 /* On its face this is a lie - the instruction does set the
8369 flags. However, the only supported mnemonic in this mode
8371 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8373 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8374 _("unshifted register required"));
8375 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8376 constraint (Rd
!= Rs
,
8377 _("dest and source1 must be the same register"));
8379 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8380 inst
.instruction
|= Rd
;
8381 inst
.instruction
|= Rn
<< 3;
8385 /* Similarly, but for instructions where the arithmetic operation is
8386 commutative, so we can allow either of them to be different from
8387 the destination operand in a 16-bit instruction. For instance, all
8388 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
8395 Rd
= inst
.operands
[0].reg
;
8396 Rs
= (inst
.operands
[1].present
8397 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8398 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8399 Rn
= inst
.operands
[2].reg
;
8403 if (!inst
.operands
[2].isreg
)
8405 /* For an immediate, we always generate a 32-bit opcode;
8406 section relaxation will shrink it later if possible. */
8407 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8408 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8409 inst
.instruction
|= Rd
<< 8;
8410 inst
.instruction
|= Rs
<< 16;
8411 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8417 /* See if we can do this with a 16-bit instruction. */
8418 if (THUMB_SETS_FLAGS (inst
.instruction
))
8419 narrow
= current_it_mask
== 0;
8421 narrow
= current_it_mask
!= 0;
8423 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8425 if (inst
.operands
[2].shifted
)
8427 if (inst
.size_req
== 4)
8434 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8435 inst
.instruction
|= Rd
;
8436 inst
.instruction
|= Rn
<< 3;
8441 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8442 inst
.instruction
|= Rd
;
8443 inst
.instruction
|= Rs
<< 3;
8448 /* If we get here, it can't be done in 16 bits. */
8449 constraint (inst
.operands
[2].shifted
8450 && inst
.operands
[2].immisreg
,
8451 _("shift must be constant"));
8452 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8453 inst
.instruction
|= Rd
<< 8;
8454 inst
.instruction
|= Rs
<< 16;
8455 encode_thumb32_shifted_operand (2);
8460 /* On its face this is a lie - the instruction does set the
8461 flags. However, the only supported mnemonic in this mode
8463 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8465 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8466 _("unshifted register required"));
8467 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8469 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8470 inst
.instruction
|= Rd
;
8473 inst
.instruction
|= Rn
<< 3;
8475 inst
.instruction
|= Rs
<< 3;
8477 constraint (1, _("dest must overlap one source register"));
8484 if (inst
.operands
[0].present
)
8486 constraint ((inst
.instruction
& 0xf0) != 0x40
8487 && inst
.operands
[0].imm
!= 0xf,
8488 "bad barrier type");
8489 inst
.instruction
|= inst
.operands
[0].imm
;
8492 inst
.instruction
|= 0xf;
8498 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8499 constraint (msb
> 32, _("bit-field extends past end of register"));
8500 /* The instruction encoding stores the LSB and MSB,
8501 not the LSB and width. */
8502 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8503 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
8504 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
8505 inst
.instruction
|= msb
- 1;
8513 /* #0 in second position is alternative syntax for bfc, which is
8514 the same instruction but with REG_PC in the Rm field. */
8515 if (!inst
.operands
[1].isreg
)
8516 inst
.operands
[1].reg
= REG_PC
;
8518 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8519 constraint (msb
> 32, _("bit-field extends past end of register"));
8520 /* The instruction encoding stores the LSB and MSB,
8521 not the LSB and width. */
8522 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8523 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8524 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8525 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8526 inst
.instruction
|= msb
- 1;
8532 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8533 _("bit-field extends past end of register"));
8534 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8535 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8536 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8537 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8538 inst
.instruction
|= inst
.operands
[3].imm
- 1;
8541 /* ARM V5 Thumb BLX (argument parse)
8542 BLX <target_addr> which is BLX(1)
8543 BLX <Rm> which is BLX(2)
8544 Unfortunately, there are two different opcodes for this mnemonic.
8545 So, the insns[].value is not used, and the code here zaps values
8546 into inst.instruction.
8548 ??? How to take advantage of the additional two bits of displacement
8549 available in Thumb32 mode? Need new relocation? */
8554 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8555 if (inst
.operands
[0].isreg
)
8556 /* We have a register, so this is BLX(2). */
8557 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8560 /* No register. This must be BLX(1). */
8561 inst
.instruction
= 0xf000e800;
8563 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8564 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8567 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
8568 inst
.reloc
.pc_rel
= 1;
8578 if (current_it_mask
)
8580 /* Conditional branches inside IT blocks are encoded as unconditional
8583 /* A branch must be the last instruction in an IT block. */
8584 constraint (current_it_mask
!= 0x10, BAD_BRANCH
);
8589 if (cond
!= COND_ALWAYS
)
8590 opcode
= T_MNEM_bcond
;
8592 opcode
= inst
.instruction
;
8594 if (unified_syntax
&& inst
.size_req
== 4)
8596 inst
.instruction
= THUMB_OP32(opcode
);
8597 if (cond
== COND_ALWAYS
)
8598 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
8601 assert (cond
!= 0xF);
8602 inst
.instruction
|= cond
<< 22;
8603 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
8608 inst
.instruction
= THUMB_OP16(opcode
);
8609 if (cond
== COND_ALWAYS
)
8610 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
8613 inst
.instruction
|= cond
<< 8;
8614 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
8616 /* Allow section relaxation. */
8617 if (unified_syntax
&& inst
.size_req
!= 2)
8618 inst
.relax
= opcode
;
8621 inst
.reloc
.pc_rel
= 1;
8627 constraint (inst
.cond
!= COND_ALWAYS
,
8628 _("instruction is always unconditional"));
8629 if (inst
.operands
[0].present
)
8631 constraint (inst
.operands
[0].imm
> 255,
8632 _("immediate value out of range"));
8633 inst
.instruction
|= inst
.operands
[0].imm
;
8638 do_t_branch23 (void)
8640 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8641 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8642 inst
.reloc
.pc_rel
= 1;
8644 /* If the destination of the branch is a defined symbol which does not have
8645 the THUMB_FUNC attribute, then we must be calling a function which has
8646 the (interfacearm) attribute. We look for the Thumb entry point to that
8647 function and change the branch to refer to that function instead. */
8648 if ( inst
.reloc
.exp
.X_op
== O_symbol
8649 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8650 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8651 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8652 inst
.reloc
.exp
.X_add_symbol
=
8653 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
8659 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8660 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8661 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
8662 should cause the alignment to be checked once it is known. This is
8663 because BX PC only works if the instruction is word aligned. */
8669 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8670 if (inst
.operands
[0].reg
== REG_PC
)
8671 as_tsktsk (_("use of r15 in bxj is not really useful"));
8673 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8679 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8680 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8681 inst
.instruction
|= inst
.operands
[1].reg
;
8687 constraint (current_it_mask
, BAD_NOT_IT
);
8688 inst
.instruction
|= inst
.operands
[0].imm
;
8694 constraint (current_it_mask
, BAD_NOT_IT
);
8696 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
8697 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
8699 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
8700 inst
.instruction
= 0xf3af8000;
8701 inst
.instruction
|= imod
<< 9;
8702 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
8703 if (inst
.operands
[1].present
)
8704 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
8708 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
8709 && (inst
.operands
[0].imm
& 4),
8710 _("selected processor does not support 'A' form "
8711 "of this instruction"));
8712 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
8713 _("Thumb does not support the 2-argument "
8714 "form of this instruction"));
8715 inst
.instruction
|= inst
.operands
[0].imm
;
8719 /* THUMB CPY instruction (argument parse). */
8724 if (inst
.size_req
== 4)
8726 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
8727 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8728 inst
.instruction
|= inst
.operands
[1].reg
;
8732 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
8733 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
8734 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
8741 constraint (current_it_mask
, BAD_NOT_IT
);
8742 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
8743 inst
.instruction
|= inst
.operands
[0].reg
;
8744 inst
.reloc
.pc_rel
= 1;
8745 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
8751 inst
.instruction
|= inst
.operands
[0].imm
;
8757 if (!inst
.operands
[1].present
)
8758 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8759 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8760 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8761 inst
.instruction
|= inst
.operands
[2].reg
;
8767 if (unified_syntax
&& inst
.size_req
== 4)
8768 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8770 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8776 unsigned int cond
= inst
.operands
[0].imm
;
8778 constraint (current_it_mask
, BAD_NOT_IT
);
8779 current_it_mask
= (inst
.instruction
& 0xf) | 0x10;
8782 /* If the condition is a negative condition, invert the mask. */
8783 if ((cond
& 0x1) == 0x0)
8785 unsigned int mask
= inst
.instruction
& 0x000f;
8787 if ((mask
& 0x7) == 0)
8788 /* no conversion needed */;
8789 else if ((mask
& 0x3) == 0)
8791 else if ((mask
& 0x1) == 0)
8796 inst
.instruction
&= 0xfff0;
8797 inst
.instruction
|= mask
;
8800 inst
.instruction
|= cond
<< 4;
8806 /* This really doesn't seem worth it. */
8807 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
8808 _("expression too complex"));
8809 constraint (inst
.operands
[1].writeback
,
8810 _("Thumb load/store multiple does not support {reglist}^"));
8814 /* See if we can use a 16-bit instruction. */
8815 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
8816 && inst
.size_req
!= 4
8817 && inst
.operands
[0].reg
<= 7
8818 && !(inst
.operands
[1].imm
& ~0xff)
8819 && (inst
.instruction
== T_MNEM_stmia
8820 ? inst
.operands
[0].writeback
8821 : (inst
.operands
[0].writeback
8822 == !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))))
8824 if (inst
.instruction
== T_MNEM_stmia
8825 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
8826 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
8827 as_warn (_("value stored for r%d is UNPREDICTABLE"),
8828 inst
.operands
[0].reg
);
8830 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8831 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8832 inst
.instruction
|= inst
.operands
[1].imm
;
8836 if (inst
.operands
[1].imm
& (1 << 13))
8837 as_warn (_("SP should not be in register list"));
8838 if (inst
.instruction
== T_MNEM_stmia
)
8840 if (inst
.operands
[1].imm
& (1 << 15))
8841 as_warn (_("PC should not be in register list"));
8842 if (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
8843 as_warn (_("value stored for r%d is UNPREDICTABLE"),
8844 inst
.operands
[0].reg
);
8848 if (inst
.operands
[1].imm
& (1 << 14)
8849 && inst
.operands
[1].imm
& (1 << 15))
8850 as_warn (_("LR and PC should not both be in register list"));
8851 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
8852 && inst
.operands
[0].writeback
)
8853 as_warn (_("base register should not be in register list "
8854 "when written back"));
8856 if (inst
.instruction
< 0xffff)
8857 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8858 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8859 inst
.instruction
|= inst
.operands
[1].imm
;
8860 if (inst
.operands
[0].writeback
)
8861 inst
.instruction
|= WRITE_BACK
;
8866 constraint (inst
.operands
[0].reg
> 7
8867 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
8868 if (inst
.instruction
== T_MNEM_stmia
)
8870 if (!inst
.operands
[0].writeback
)
8871 as_warn (_("this instruction will write back the base register"));
8872 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
8873 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
8874 as_warn (_("value stored for r%d is UNPREDICTABLE"),
8875 inst
.operands
[0].reg
);
8879 if (!inst
.operands
[0].writeback
8880 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
8881 as_warn (_("this instruction will write back the base register"));
8882 else if (inst
.operands
[0].writeback
8883 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
8884 as_warn (_("this instruction will not write back the base register"));
8887 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8888 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8889 inst
.instruction
|= inst
.operands
[1].imm
;
8896 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8897 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8898 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8899 || inst
.operands
[1].negative
,
8902 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8903 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8904 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
8910 if (!inst
.operands
[1].present
)
8912 constraint (inst
.operands
[0].reg
== REG_LR
,
8913 _("r14 not allowed as first register "
8914 "when second register is omitted"));
8915 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8917 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
8920 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8921 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
8922 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8928 unsigned long opcode
;
8931 opcode
= inst
.instruction
;
8934 if (!inst
.operands
[1].isreg
)
8936 if (opcode
<= 0xffff)
8937 inst
.instruction
= THUMB_OP32 (opcode
);
8938 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
8941 if (inst
.operands
[1].isreg
8942 && !inst
.operands
[1].writeback
8943 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
8944 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
8946 && inst
.size_req
!= 4)
8948 /* Insn may have a 16-bit form. */
8949 Rn
= inst
.operands
[1].reg
;
8950 if (inst
.operands
[1].immisreg
)
8952 inst
.instruction
= THUMB_OP16 (opcode
);
8954 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
8957 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
8958 && opcode
!= T_MNEM_ldrsb
)
8959 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
8960 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
8967 if (inst
.reloc
.pc_rel
)
8968 opcode
= T_MNEM_ldr_pc2
;
8970 opcode
= T_MNEM_ldr_pc
;
8974 if (opcode
== T_MNEM_ldr
)
8975 opcode
= T_MNEM_ldr_sp
;
8977 opcode
= T_MNEM_str_sp
;
8979 inst
.instruction
= inst
.operands
[0].reg
<< 8;
8983 inst
.instruction
= inst
.operands
[0].reg
;
8984 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
8986 inst
.instruction
|= THUMB_OP16 (opcode
);
8987 if (inst
.size_req
== 2)
8988 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
8990 inst
.relax
= opcode
;
8994 /* Definitely a 32-bit variant. */
8995 inst
.instruction
= THUMB_OP32 (opcode
);
8996 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8997 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9001 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9003 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9005 /* Only [Rn,Rm] is acceptable. */
9006 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9007 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9008 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9009 || inst
.operands
[1].negative
,
9010 _("Thumb does not support this addressing mode"));
9011 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9015 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9016 if (!inst
.operands
[1].isreg
)
9017 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9020 constraint (!inst
.operands
[1].preind
9021 || inst
.operands
[1].shifted
9022 || inst
.operands
[1].writeback
,
9023 _("Thumb does not support this addressing mode"));
9024 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9026 constraint (inst
.instruction
& 0x0600,
9027 _("byte or halfword not valid for base register"));
9028 constraint (inst
.operands
[1].reg
== REG_PC
9029 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9030 _("r15 based store not allowed"));
9031 constraint (inst
.operands
[1].immisreg
,
9032 _("invalid base register for register offset"));
9034 if (inst
.operands
[1].reg
== REG_PC
)
9035 inst
.instruction
= T_OPCODE_LDR_PC
;
9036 else if (inst
.instruction
& THUMB_LOAD_BIT
)
9037 inst
.instruction
= T_OPCODE_LDR_SP
;
9039 inst
.instruction
= T_OPCODE_STR_SP
;
9041 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9042 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9046 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
9047 if (!inst
.operands
[1].immisreg
)
9049 /* Immediate offset. */
9050 inst
.instruction
|= inst
.operands
[0].reg
;
9051 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9052 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9056 /* Register offset. */
9057 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
9058 constraint (inst
.operands
[1].negative
,
9059 _("Thumb does not support this addressing mode"));
9062 switch (inst
.instruction
)
9064 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
9065 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
9066 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
9067 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
9068 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
9069 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
9070 case 0x5600 /* ldrsb */:
9071 case 0x5e00 /* ldrsh */: break;
9075 inst
.instruction
|= inst
.operands
[0].reg
;
9076 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9077 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
9083 if (!inst
.operands
[1].present
)
9085 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9086 constraint (inst
.operands
[0].reg
== REG_LR
,
9087 _("r14 not allowed here"));
9089 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9090 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9091 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
9098 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9099 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
9105 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9106 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9107 inst
.instruction
|= inst
.operands
[2].reg
;
9108 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9114 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9115 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9116 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9117 inst
.instruction
|= inst
.operands
[3].reg
;
9125 int r0off
= (inst
.instruction
== T_MNEM_mov
9126 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
9127 unsigned long opcode
;
9129 bfd_boolean low_regs
;
9131 low_regs
= (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7);
9132 opcode
= inst
.instruction
;
9133 if (current_it_mask
)
9134 narrow
= opcode
!= T_MNEM_movs
;
9136 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
9137 if (inst
.size_req
== 4
9138 || inst
.operands
[1].shifted
)
9141 if (!inst
.operands
[1].isreg
)
9143 /* Immediate operand. */
9144 if (current_it_mask
== 0 && opcode
== T_MNEM_mov
)
9146 if (low_regs
&& narrow
)
9148 inst
.instruction
= THUMB_OP16 (opcode
);
9149 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9150 if (inst
.size_req
== 2)
9151 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9153 inst
.relax
= opcode
;
9157 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9158 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9159 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9160 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9165 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9166 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9167 encode_thumb32_shifted_operand (1);
9170 switch (inst
.instruction
)
9173 inst
.instruction
= T_OPCODE_MOV_HR
;
9174 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9175 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9176 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9180 /* We know we have low registers at this point.
9181 Generate ADD Rd, Rs, #0. */
9182 inst
.instruction
= T_OPCODE_ADD_I3
;
9183 inst
.instruction
|= inst
.operands
[0].reg
;
9184 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9190 inst
.instruction
= T_OPCODE_CMP_LR
;
9191 inst
.instruction
|= inst
.operands
[0].reg
;
9192 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9196 inst
.instruction
= T_OPCODE_CMP_HR
;
9197 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9198 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9199 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9206 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9207 if (inst
.operands
[1].isreg
)
9209 if (inst
.operands
[0].reg
< 8 && inst
.operands
[1].reg
< 8)
9211 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
9212 since a MOV instruction produces unpredictable results. */
9213 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9214 inst
.instruction
= T_OPCODE_ADD_I3
;
9216 inst
.instruction
= T_OPCODE_CMP_LR
;
9218 inst
.instruction
|= inst
.operands
[0].reg
;
9219 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9223 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9224 inst
.instruction
= T_OPCODE_MOV_HR
;
9226 inst
.instruction
= T_OPCODE_CMP_HR
;
9232 constraint (inst
.operands
[0].reg
> 7,
9233 _("only lo regs allowed with immediate"));
9234 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9235 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9245 top
= (inst
.instruction
& 0x00800000) != 0;
9246 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
9248 constraint (top
, _(":lower16: not allowed this instruction"));
9249 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
9251 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
9253 constraint (!top
, _(":upper16: not allowed this instruction"));
9254 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
9257 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9258 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9260 imm
= inst
.reloc
.exp
.X_add_number
;
9261 inst
.instruction
|= (imm
& 0xf000) << 4;
9262 inst
.instruction
|= (imm
& 0x0800) << 15;
9263 inst
.instruction
|= (imm
& 0x0700) << 4;
9264 inst
.instruction
|= (imm
& 0x00ff);
9273 int r0off
= (inst
.instruction
== T_MNEM_mvn
9274 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
9277 if (inst
.size_req
== 4
9278 || inst
.instruction
> 0xffff
9279 || inst
.operands
[1].shifted
9280 || inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9282 else if (inst
.instruction
== T_MNEM_cmn
)
9284 else if (THUMB_SETS_FLAGS (inst
.instruction
))
9285 narrow
= (current_it_mask
== 0);
9287 narrow
= (current_it_mask
!= 0);
9289 if (!inst
.operands
[1].isreg
)
9291 /* For an immediate, we always generate a 32-bit opcode;
9292 section relaxation will shrink it later if possible. */
9293 if (inst
.instruction
< 0xffff)
9294 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9295 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9296 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9297 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9301 /* See if we can do this with a 16-bit instruction. */
9304 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9305 inst
.instruction
|= inst
.operands
[0].reg
;
9306 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9310 constraint (inst
.operands
[1].shifted
9311 && inst
.operands
[1].immisreg
,
9312 _("shift must be constant"));
9313 if (inst
.instruction
< 0xffff)
9314 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9315 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9316 encode_thumb32_shifted_operand (1);
9322 constraint (inst
.instruction
> 0xffff
9323 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
9324 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
9325 _("unshifted register required"));
9326 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9329 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9330 inst
.instruction
|= inst
.operands
[0].reg
;
9331 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9340 if (do_vfp_nsyn_mrs () == SUCCESS
)
9343 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
9346 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
9347 _("selected processor does not support "
9348 "requested special purpose register"));
9352 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9353 _("selected processor does not support "
9354 "requested special purpose register %x"));
9355 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9356 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
9357 _("'CPSR' or 'SPSR' expected"));
9360 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9361 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9362 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
9370 if (do_vfp_nsyn_msr () == SUCCESS
)
9373 constraint (!inst
.operands
[1].isreg
,
9374 _("Thumb encoding does not support an immediate here"));
9375 flags
= inst
.operands
[0].imm
;
9378 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9379 _("selected processor does not support "
9380 "requested special purpose register"));
9384 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
9385 _("selected processor does not support "
9386 "requested special purpose register"));
9389 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9390 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
9391 inst
.instruction
|= (flags
& 0xff);
9392 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9398 if (!inst
.operands
[2].present
)
9399 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9401 /* There is no 32-bit MULS and no 16-bit MUL. */
9402 if (unified_syntax
&& inst
.instruction
== T_MNEM_mul
)
9404 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9405 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9406 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9407 inst
.instruction
|= inst
.operands
[2].reg
<< 0;
9411 constraint (!unified_syntax
9412 && inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
9413 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9416 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9417 inst
.instruction
|= inst
.operands
[0].reg
;
9419 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9420 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9421 else if (inst
.operands
[0].reg
== inst
.operands
[2].reg
)
9422 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9424 constraint (1, _("dest must overlap one source register"));
9431 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9432 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9433 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9434 inst
.instruction
|= inst
.operands
[3].reg
;
9436 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9437 as_tsktsk (_("rdhi and rdlo must be different"));
9445 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
9447 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9448 inst
.instruction
|= inst
.operands
[0].imm
;
9452 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9453 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
9458 constraint (inst
.operands
[0].present
,
9459 _("Thumb does not support NOP with hints"));
9460 inst
.instruction
= 0x46c0;
9471 if (THUMB_SETS_FLAGS (inst
.instruction
))
9472 narrow
= (current_it_mask
== 0);
9474 narrow
= (current_it_mask
!= 0);
9475 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9477 if (inst
.size_req
== 4)
9482 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9483 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9484 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9488 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9489 inst
.instruction
|= inst
.operands
[0].reg
;
9490 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9495 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9497 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9499 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9500 inst
.instruction
|= inst
.operands
[0].reg
;
9501 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9508 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9509 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9510 inst
.instruction
|= inst
.operands
[2].reg
;
9511 if (inst
.operands
[3].present
)
9513 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
9514 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9515 _("expression too complex"));
9516 inst
.instruction
|= (val
& 0x1c) << 10;
9517 inst
.instruction
|= (val
& 0x03) << 6;
9524 if (!inst
.operands
[3].present
)
9525 inst
.instruction
&= ~0x00000020;
9532 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9536 do_t_push_pop (void)
9540 constraint (inst
.operands
[0].writeback
,
9541 _("push/pop do not support {reglist}^"));
9542 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9543 _("expression too complex"));
9545 mask
= inst
.operands
[0].imm
;
9546 if ((mask
& ~0xff) == 0)
9547 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9548 else if ((inst
.instruction
== T_MNEM_push
9549 && (mask
& ~0xff) == 1 << REG_LR
)
9550 || (inst
.instruction
== T_MNEM_pop
9551 && (mask
& ~0xff) == 1 << REG_PC
))
9553 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9554 inst
.instruction
|= THUMB_PP_PC_LR
;
9557 else if (unified_syntax
)
9559 if (mask
& (1 << 13))
9560 inst
.error
= _("SP not allowed in register list");
9561 if (inst
.instruction
== T_MNEM_push
)
9563 if (mask
& (1 << 15))
9564 inst
.error
= _("PC not allowed in register list");
9568 if (mask
& (1 << 14)
9569 && mask
& (1 << 15))
9570 inst
.error
= _("LR and PC should not both be in register list");
9572 if ((mask
& (mask
- 1)) == 0)
9574 /* Single register push/pop implemented as str/ldr. */
9575 if (inst
.instruction
== T_MNEM_push
)
9576 inst
.instruction
= 0xf84d0d04; /* str reg, [sp, #-4]! */
9578 inst
.instruction
= 0xf85d0b04; /* ldr reg, [sp], #4 */
9579 mask
= ffs(mask
) - 1;
9583 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9587 inst
.error
= _("invalid register list to push/pop instruction");
9591 inst
.instruction
|= mask
;
9597 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9598 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9604 if (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
9605 && inst
.size_req
!= 4)
9607 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9608 inst
.instruction
|= inst
.operands
[0].reg
;
9609 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9611 else if (unified_syntax
)
9613 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9614 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9615 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9616 inst
.instruction
|= inst
.operands
[1].reg
;
9619 inst
.error
= BAD_HIREG
;
9627 Rd
= inst
.operands
[0].reg
;
9628 Rs
= (inst
.operands
[1].present
9629 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9630 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9632 inst
.instruction
|= Rd
<< 8;
9633 inst
.instruction
|= Rs
<< 16;
9634 if (!inst
.operands
[2].isreg
)
9636 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9637 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9640 encode_thumb32_shifted_operand (2);
9646 constraint (current_it_mask
, BAD_NOT_IT
);
9647 if (inst
.operands
[0].imm
)
9648 inst
.instruction
|= 0x8;
9654 if (!inst
.operands
[1].present
)
9655 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9662 switch (inst
.instruction
)
9665 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
9667 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
9669 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
9671 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
9675 if (THUMB_SETS_FLAGS (inst
.instruction
))
9676 narrow
= (current_it_mask
== 0);
9678 narrow
= (current_it_mask
!= 0);
9679 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9681 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
9683 if (inst
.operands
[2].isreg
9684 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
9685 || inst
.operands
[2].reg
> 7))
9687 if (inst
.size_req
== 4)
9692 if (inst
.operands
[2].isreg
)
9694 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9695 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9696 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9697 inst
.instruction
|= inst
.operands
[2].reg
;
9701 inst
.operands
[1].shifted
= 1;
9702 inst
.operands
[1].shift_kind
= shift_kind
;
9703 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
9704 ? T_MNEM_movs
: T_MNEM_mov
);
9705 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9706 encode_thumb32_shifted_operand (1);
9707 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
9708 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9713 if (inst
.operands
[2].isreg
)
9717 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
9718 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
9719 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
9720 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
9724 inst
.instruction
|= inst
.operands
[0].reg
;
9725 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9731 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
9732 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
9733 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
9736 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
9737 inst
.instruction
|= inst
.operands
[0].reg
;
9738 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9744 constraint (inst
.operands
[0].reg
> 7
9745 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
9746 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9748 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
9750 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
9751 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
9752 _("source1 and dest must be same register"));
9754 switch (inst
.instruction
)
9756 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
9757 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
9758 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
9759 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
9763 inst
.instruction
|= inst
.operands
[0].reg
;
9764 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9768 switch (inst
.instruction
)
9770 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
9771 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
9772 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
9773 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
9776 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
9777 inst
.instruction
|= inst
.operands
[0].reg
;
9778 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9786 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9787 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9788 inst
.instruction
|= inst
.operands
[2].reg
;
9794 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9795 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9796 _("expression too complex"));
9797 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9798 inst
.instruction
|= (value
& 0xf000) >> 12;
9799 inst
.instruction
|= (value
& 0x0ff0);
9800 inst
.instruction
|= (value
& 0x000f) << 16;
9806 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9807 inst
.instruction
|= inst
.operands
[1].imm
- 1;
9808 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9810 if (inst
.operands
[3].present
)
9812 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9813 _("expression too complex"));
9815 if (inst
.reloc
.exp
.X_add_number
!= 0)
9817 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
9818 inst
.instruction
|= 0x00200000; /* sh bit */
9819 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
9820 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
9822 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9829 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9830 inst
.instruction
|= inst
.operands
[1].imm
- 1;
9831 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9837 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9838 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9839 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9840 || inst
.operands
[2].negative
,
9843 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9844 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9845 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9846 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9852 if (!inst
.operands
[2].present
)
9853 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
9855 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9856 || inst
.operands
[0].reg
== inst
.operands
[2].reg
9857 || inst
.operands
[0].reg
== inst
.operands
[3].reg
9858 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
9861 inst
.instruction
|= inst
.operands
[0].reg
;
9862 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9863 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9864 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9870 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9871 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9872 inst
.instruction
|= inst
.operands
[2].reg
;
9873 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
9879 if (inst
.instruction
<= 0xffff && inst
.size_req
!= 4
9880 && inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
9881 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
9883 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9884 inst
.instruction
|= inst
.operands
[0].reg
;
9885 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9887 else if (unified_syntax
)
9889 if (inst
.instruction
<= 0xffff)
9890 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9891 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9892 inst
.instruction
|= inst
.operands
[1].reg
;
9893 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
9897 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
9898 _("Thumb encoding does not support rotation"));
9899 constraint (1, BAD_HIREG
);
9906 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9914 half
= (inst
.instruction
& 0x10) != 0;
9915 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
9916 constraint (inst
.operands
[0].immisreg
,
9917 _("instruction requires register index"));
9918 constraint (inst
.operands
[0].imm
== 15,
9919 _("PC is not a valid index register"));
9920 constraint (!half
&& inst
.operands
[0].shifted
,
9921 _("instruction does not allow shifted index"));
9922 inst
.instruction
|= (inst
.operands
[0].reg
<< 16) | inst
.operands
[0].imm
;
9928 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9929 inst
.instruction
|= inst
.operands
[1].imm
;
9930 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9932 if (inst
.operands
[3].present
)
9934 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9935 _("expression too complex"));
9936 if (inst
.reloc
.exp
.X_add_number
!= 0)
9938 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
9939 inst
.instruction
|= 0x00200000; /* sh bit */
9941 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
9942 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
9944 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9951 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9952 inst
.instruction
|= inst
.operands
[1].imm
;
9953 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9956 /* Neon instruction encoder helpers. */
9958 /* Encodings for the different types for various Neon opcodes. */
9960 /* An "invalid" code for the following tables. */
9963 struct neon_tab_entry
9966 unsigned float_or_poly
;
9967 unsigned scalar_or_imm
;
9970 /* Map overloaded Neon opcodes to their respective encodings. */
9971 #define NEON_ENC_TAB \
9972 X(vabd, 0x0000700, 0x1200d00, N_INV), \
9973 X(vmax, 0x0000600, 0x0000f00, N_INV), \
9974 X(vmin, 0x0000610, 0x0200f00, N_INV), \
9975 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
9976 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
9977 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
9978 X(vadd, 0x0000800, 0x0000d00, N_INV), \
9979 X(vsub, 0x1000800, 0x0200d00, N_INV), \
9980 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
9981 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
9982 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
9983 /* Register variants of the following two instructions are encoded as
9984 vcge / vcgt with the operands reversed. */ \
9985 X(vclt, 0x0000310, 0x1000e00, 0x1b10200), \
9986 X(vcle, 0x0000300, 0x1200e00, 0x1b10180), \
9987 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
9988 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
9989 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
9990 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
9991 X(vmlal, 0x0800800, N_INV, 0x0800240), \
9992 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
9993 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
9994 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
9995 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
9996 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
9997 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
9998 X(vshl, 0x0000400, N_INV, 0x0800510), \
9999 X(vqshl, 0x0000410, N_INV, 0x0800710), \
10000 X(vand, 0x0000110, N_INV, 0x0800030), \
10001 X(vbic, 0x0100110, N_INV, 0x0800030), \
10002 X(veor, 0x1000110, N_INV, N_INV), \
10003 X(vorn, 0x0300110, N_INV, 0x0800010), \
10004 X(vorr, 0x0200110, N_INV, 0x0800010), \
10005 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
10006 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
10007 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
10008 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
10009 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
10010 X(vst1, 0x0000000, 0x0800000, N_INV), \
10011 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
10012 X(vst2, 0x0000100, 0x0800100, N_INV), \
10013 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
10014 X(vst3, 0x0000200, 0x0800200, N_INV), \
10015 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
10016 X(vst4, 0x0000300, 0x0800300, N_INV), \
10017 X(vmovn, 0x1b20200, N_INV, N_INV), \
10018 X(vtrn, 0x1b20080, N_INV, N_INV), \
10019 X(vqmovn, 0x1b20200, N_INV, N_INV), \
10020 X(vqmovun, 0x1b20240, N_INV, N_INV), \
10021 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
10022 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \
10023 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \
10024 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
10025 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
10026 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
10027 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
10031 #define X(OPC,I,F,S) N_MNEM_##OPC
10036 static const struct neon_tab_entry neon_enc_tab
[] =
10038 #define X(OPC,I,F,S) { (I), (F), (S) }
10043 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10044 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10045 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10046 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10047 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10048 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10049 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10050 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10051 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10052 #define NEON_ENC_SINGLE(X) \
10053 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
10054 #define NEON_ENC_DOUBLE(X) \
10055 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
10057 /* Define shapes for instruction operands. The following mnemonic characters
10058 are used in this table:
10060 F - VFP S<n> register
10061 D - Neon D<n> register
10062 Q - Neon Q<n> register
10066 L - D<n> register list
10068 This table is used to generate various data:
10069 - enumerations of the form NS_DDR to be used as arguments to
10071 - a table classifying shapes into single, double, quad, mixed.
10072 - a table used to drive neon_select_shape.
10075 #define NEON_SHAPE_DEF \
10076 X(3, (D, D, D), DOUBLE), \
10077 X(3, (Q, Q, Q), QUAD), \
10078 X(3, (D, D, I), DOUBLE), \
10079 X(3, (Q, Q, I), QUAD), \
10080 X(3, (D, D, S), DOUBLE), \
10081 X(3, (Q, Q, S), QUAD), \
10082 X(2, (D, D), DOUBLE), \
10083 X(2, (Q, Q), QUAD), \
10084 X(2, (D, S), DOUBLE), \
10085 X(2, (Q, S), QUAD), \
10086 X(2, (D, R), DOUBLE), \
10087 X(2, (Q, R), QUAD), \
10088 X(2, (D, I), DOUBLE), \
10089 X(2, (Q, I), QUAD), \
10090 X(3, (D, L, D), DOUBLE), \
10091 X(2, (D, Q), MIXED), \
10092 X(2, (Q, D), MIXED), \
10093 X(3, (D, Q, I), MIXED), \
10094 X(3, (Q, D, I), MIXED), \
10095 X(3, (Q, D, D), MIXED), \
10096 X(3, (D, Q, Q), MIXED), \
10097 X(3, (Q, Q, D), MIXED), \
10098 X(3, (Q, D, S), MIXED), \
10099 X(3, (D, Q, S), MIXED), \
10100 X(4, (D, D, D, I), DOUBLE), \
10101 X(4, (Q, Q, Q, I), QUAD), \
10102 X(2, (F, F), SINGLE), \
10103 X(3, (F, F, F), SINGLE), \
10104 X(2, (F, I), SINGLE), \
10105 X(2, (F, D), MIXED), \
10106 X(2, (D, F), MIXED), \
10107 X(3, (F, F, I), MIXED), \
10108 X(4, (R, R, F, F), SINGLE), \
10109 X(4, (F, F, R, R), SINGLE), \
10110 X(3, (D, R, R), DOUBLE), \
10111 X(3, (R, R, D), DOUBLE), \
10112 X(2, (S, R), SINGLE), \
10113 X(2, (R, S), SINGLE), \
10114 X(2, (F, R), SINGLE), \
10115 X(2, (R, F), SINGLE)
10117 #define S2(A,B) NS_##A##B
10118 #define S3(A,B,C) NS_##A##B##C
10119 #define S4(A,B,C,D) NS_##A##B##C##D
10121 #define X(N, L, C) S##N L
10134 enum neon_shape_class
10142 #define X(N, L, C) SC_##C
10144 static enum neon_shape_class neon_shape_class
[] =
10162 /* Register widths of above. */
10163 static unsigned neon_shape_el_size
[] =
10174 struct neon_shape_info
10177 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
10180 #define S2(A,B) { SE_##A, SE_##B }
10181 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
10182 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
10184 #define X(N, L, C) { N, S##N L }
10186 static struct neon_shape_info neon_shape_tab
[] =
10196 /* Bit masks used in type checking given instructions.
10197 'N_EQK' means the type must be the same as (or based on in some way) the key
10198 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
10199 set, various other bits can be set as well in order to modify the meaning of
10200 the type constraint. */
10202 enum neon_type_mask
10224 N_KEY
= 0x100000, /* key element (main type specifier). */
10225 N_EQK
= 0x200000, /* given operand has the same type & size as the key. */
10226 N_VFP
= 0x400000, /* VFP mode: operand size must match register width. */
10227 N_DBL
= 0x000001, /* if N_EQK, this operand is twice the size. */
10228 N_HLF
= 0x000002, /* if N_EQK, this operand is half the size. */
10229 N_SGN
= 0x000004, /* if N_EQK, this operand is forced to be signed. */
10230 N_UNS
= 0x000008, /* if N_EQK, this operand is forced to be unsigned. */
10231 N_INT
= 0x000010, /* if N_EQK, this operand is forced to be integer. */
10232 N_FLT
= 0x000020, /* if N_EQK, this operand is forced to be float. */
10233 N_SIZ
= 0x000040, /* if N_EQK, this operand is forced to be size-only. */
10235 N_MAX_NONSPECIAL
= N_F64
10238 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
10240 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
10241 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
10242 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
10243 #define N_SUF_32 (N_SU_32 | N_F32)
10244 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
10245 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
10247 /* Pass this as the first type argument to neon_check_type to ignore types
10249 #define N_IGNORE_TYPE (N_KEY | N_EQK)
10251 /* Select a "shape" for the current instruction (describing register types or
10252 sizes) from a list of alternatives. Return NS_NULL if the current instruction
10253 doesn't fit. For non-polymorphic shapes, checking is usually done as a
10254 function of operand parsing, so this function doesn't need to be called.
10255 Shapes should be listed in order of decreasing length. */
10257 static enum neon_shape
10258 neon_select_shape (enum neon_shape shape
, ...)
10261 enum neon_shape first_shape
= shape
;
10263 /* Fix missing optional operands. FIXME: we don't know at this point how
10264 many arguments we should have, so this makes the assumption that we have
10265 > 1. This is true of all current Neon opcodes, I think, but may not be
10266 true in the future. */
10267 if (!inst
.operands
[1].present
)
10268 inst
.operands
[1] = inst
.operands
[0];
10270 va_start (ap
, shape
);
10272 for (; shape
!= NS_NULL
; shape
= va_arg (ap
, int))
10277 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
10279 if (!inst
.operands
[j
].present
)
10285 switch (neon_shape_tab
[shape
].el
[j
])
10288 if (!(inst
.operands
[j
].isreg
10289 && inst
.operands
[j
].isvec
10290 && inst
.operands
[j
].issingle
10291 && !inst
.operands
[j
].isquad
))
10296 if (!(inst
.operands
[j
].isreg
10297 && inst
.operands
[j
].isvec
10298 && !inst
.operands
[j
].isquad
10299 && !inst
.operands
[j
].issingle
))
10304 if (!(inst
.operands
[j
].isreg
10305 && !inst
.operands
[j
].isvec
))
10310 if (!(inst
.operands
[j
].isreg
10311 && inst
.operands
[j
].isvec
10312 && inst
.operands
[j
].isquad
10313 && !inst
.operands
[j
].issingle
))
10318 if (!(!inst
.operands
[j
].isreg
10319 && !inst
.operands
[j
].isscalar
))
10324 if (!(!inst
.operands
[j
].isreg
10325 && inst
.operands
[j
].isscalar
))
10339 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
10340 first_error (_("invalid instruction shape"));
10345 /* True if SHAPE is predominantly a quadword operation (most of the time, this
10346 means the Q bit should be set). */
10349 neon_quad (enum neon_shape shape
)
10351 return neon_shape_class
[shape
] == SC_QUAD
;
10355 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
10358 /* Allow modification to be made to types which are constrained to be
10359 based on the key element, based on bits set alongside N_EQK. */
10360 if ((typebits
& N_EQK
) != 0)
10362 if ((typebits
& N_HLF
) != 0)
10364 else if ((typebits
& N_DBL
) != 0)
10366 if ((typebits
& N_SGN
) != 0)
10367 *g_type
= NT_signed
;
10368 else if ((typebits
& N_UNS
) != 0)
10369 *g_type
= NT_unsigned
;
10370 else if ((typebits
& N_INT
) != 0)
10371 *g_type
= NT_integer
;
10372 else if ((typebits
& N_FLT
) != 0)
10373 *g_type
= NT_float
;
10374 else if ((typebits
& N_SIZ
) != 0)
10375 *g_type
= NT_untyped
;
10379 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
10380 operand type, i.e. the single type specified in a Neon instruction when it
10381 is the only one given. */
10383 static struct neon_type_el
10384 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
10386 struct neon_type_el dest
= *key
;
10388 assert ((thisarg
& N_EQK
) != 0);
10390 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
10395 /* Convert Neon type and size into compact bitmask representation. */
10397 static enum neon_type_mask
10398 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
10405 case 8: return N_8
;
10406 case 16: return N_16
;
10407 case 32: return N_32
;
10408 case 64: return N_64
;
10416 case 8: return N_I8
;
10417 case 16: return N_I16
;
10418 case 32: return N_I32
;
10419 case 64: return N_I64
;
10427 case 32: return N_F32
;
10428 case 64: return N_F64
;
10436 case 8: return N_P8
;
10437 case 16: return N_P16
;
10445 case 8: return N_S8
;
10446 case 16: return N_S16
;
10447 case 32: return N_S32
;
10448 case 64: return N_S64
;
10456 case 8: return N_U8
;
10457 case 16: return N_U16
;
10458 case 32: return N_U32
;
10459 case 64: return N_U64
;
10470 /* Convert compact Neon bitmask type representation to a type and size. Only
10471 handles the case where a single bit is set in the mask. */
10474 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
10475 enum neon_type_mask mask
)
10477 if ((mask
& N_EQK
) != 0)
10480 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
10482 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
10484 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
10486 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
10491 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
10493 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
10494 *type
= NT_unsigned
;
10495 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
10496 *type
= NT_integer
;
10497 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
10498 *type
= NT_untyped
;
10499 else if ((mask
& (N_P8
| N_P16
)) != 0)
10501 else if ((mask
& (N_F32
| N_F64
)) != 0)
10509 /* Modify a bitmask of allowed types. This is only needed for type
10513 modify_types_allowed (unsigned allowed
, unsigned mods
)
10516 enum neon_el_type type
;
10522 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
10524 if (el_type_of_type_chk (&type
, &size
, allowed
& i
) == SUCCESS
)
10526 neon_modify_type_size (mods
, &type
, &size
);
10527 destmask
|= type_chk_of_el_type (type
, size
);
10534 /* Check type and return type classification.
10535 The manual states (paraphrase): If one datatype is given, it indicates the
10537 - the second operand, if there is one
10538 - the operand, if there is no second operand
10539 - the result, if there are no operands.
10540 This isn't quite good enough though, so we use a concept of a "key" datatype
10541 which is set on a per-instruction basis, which is the one which matters when
10542 only one data type is written.
10543 Note: this function has side-effects (e.g. filling in missing operands). All
10544 Neon instructions should call it before performing bit encoding. */
10546 static struct neon_type_el
10547 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
10550 unsigned i
, pass
, key_el
= 0;
10551 unsigned types
[NEON_MAX_TYPE_ELS
];
10552 enum neon_el_type k_type
= NT_invtype
;
10553 unsigned k_size
= -1u;
10554 struct neon_type_el badtype
= {NT_invtype
, -1};
10555 unsigned key_allowed
= 0;
10557 /* Optional registers in Neon instructions are always (not) in operand 1.
10558 Fill in the missing operand here, if it was omitted. */
10559 if (els
> 1 && !inst
.operands
[1].present
)
10560 inst
.operands
[1] = inst
.operands
[0];
10562 /* Suck up all the varargs. */
10564 for (i
= 0; i
< els
; i
++)
10566 unsigned thisarg
= va_arg (ap
, unsigned);
10567 if (thisarg
== N_IGNORE_TYPE
)
10572 types
[i
] = thisarg
;
10573 if ((thisarg
& N_KEY
) != 0)
10578 if (inst
.vectype
.elems
> 0)
10579 for (i
= 0; i
< els
; i
++)
10580 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
10582 first_error (_("types specified in both the mnemonic and operands"));
10586 /* Duplicate inst.vectype elements here as necessary.
10587 FIXME: No idea if this is exactly the same as the ARM assembler,
10588 particularly when an insn takes one register and one non-register
10590 if (inst
.vectype
.elems
== 1 && els
> 1)
10593 inst
.vectype
.elems
= els
;
10594 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
10595 for (j
= 0; j
< els
; j
++)
10597 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
10600 else if (inst
.vectype
.elems
== 0 && els
> 0)
10603 /* No types were given after the mnemonic, so look for types specified
10604 after each operand. We allow some flexibility here; as long as the
10605 "key" operand has a type, we can infer the others. */
10606 for (j
= 0; j
< els
; j
++)
10607 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
10608 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
10610 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
10612 for (j
= 0; j
< els
; j
++)
10613 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
10614 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
10619 first_error (_("operand types can't be inferred"));
10623 else if (inst
.vectype
.elems
!= els
)
10625 first_error (_("type specifier has the wrong number of parts"));
10629 for (pass
= 0; pass
< 2; pass
++)
10631 for (i
= 0; i
< els
; i
++)
10633 unsigned thisarg
= types
[i
];
10634 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
10635 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
10636 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
10637 unsigned g_size
= inst
.vectype
.el
[i
].size
;
10639 /* Decay more-specific signed & unsigned types to sign-insensitive
10640 integer types if sign-specific variants are unavailable. */
10641 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
10642 && (types_allowed
& N_SU_ALL
) == 0)
10643 g_type
= NT_integer
;
10645 /* If only untyped args are allowed, decay any more specific types to
10646 them. Some instructions only care about signs for some element
10647 sizes, so handle that properly. */
10648 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
10649 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
10650 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
10651 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
10652 g_type
= NT_untyped
;
10656 if ((thisarg
& N_KEY
) != 0)
10660 key_allowed
= thisarg
& ~N_KEY
;
10665 if ((thisarg
& N_VFP
) != 0)
10667 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
10668 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
10670 /* In VFP mode, operands must match register widths. If we
10671 have a key operand, use its width, else use the width of
10672 the current operand. */
10678 if (regwidth
!= match
)
10680 first_error (_("operand size must match register width"));
10685 if ((thisarg
& N_EQK
) == 0)
10687 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
10689 if ((given_type
& types_allowed
) == 0)
10691 first_error (_("bad type in Neon instruction"));
10697 enum neon_el_type mod_k_type
= k_type
;
10698 unsigned mod_k_size
= k_size
;
10699 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
10700 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
10702 first_error (_("inconsistent types in Neon instruction"));
10710 return inst
.vectype
.el
[key_el
];
10713 /* Neon-style VFP instruction forwarding. */
10715 /* Thumb VFP instructions have 0xE in the condition field. */
10718 do_vfp_cond_or_thumb (void)
10721 inst
.instruction
|= 0xe0000000;
10723 inst
.instruction
|= inst
.cond
<< 28;
10726 /* Look up and encode a simple mnemonic, for use as a helper function for the
10727 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
10728 etc. It is assumed that operand parsing has already been done, and that the
10729 operands are in the form expected by the given opcode (this isn't necessarily
10730 the same as the form in which they were parsed, hence some massaging must
10731 take place before this function is called).
10732 Checks current arch version against that in the looked-up opcode. */
10735 do_vfp_nsyn_opcode (const char *opname
)
10737 const struct asm_opcode
*opcode
;
10739 opcode
= hash_find (arm_ops_hsh
, opname
);
10744 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
10745 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
10750 inst
.instruction
= opcode
->tvalue
;
10751 opcode
->tencode ();
10755 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
10756 opcode
->aencode ();
10761 do_vfp_nsyn_add_sub (enum neon_shape rs
)
10763 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
10768 do_vfp_nsyn_opcode ("fadds");
10770 do_vfp_nsyn_opcode ("fsubs");
10775 do_vfp_nsyn_opcode ("faddd");
10777 do_vfp_nsyn_opcode ("fsubd");
10781 /* Check operand types to see if this is a VFP instruction, and if so call
10785 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
10787 enum neon_shape rs
;
10788 struct neon_type_el et
;
10793 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
10794 et
= neon_check_type (2, rs
,
10795 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
10799 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
10800 et
= neon_check_type (3, rs
,
10801 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
10808 if (et
.type
!= NT_invtype
)
10820 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
10822 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
10827 do_vfp_nsyn_opcode ("fmacs");
10829 do_vfp_nsyn_opcode ("fmscs");
10834 do_vfp_nsyn_opcode ("fmacd");
10836 do_vfp_nsyn_opcode ("fmscd");
10841 do_vfp_nsyn_mul (enum neon_shape rs
)
10844 do_vfp_nsyn_opcode ("fmuls");
10846 do_vfp_nsyn_opcode ("fmuld");
10850 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
10852 int is_neg
= (inst
.instruction
& 0x80) != 0;
10853 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
10858 do_vfp_nsyn_opcode ("fnegs");
10860 do_vfp_nsyn_opcode ("fabss");
10865 do_vfp_nsyn_opcode ("fnegd");
10867 do_vfp_nsyn_opcode ("fabsd");
10871 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
10872 insns belong to Neon, and are handled elsewhere. */
10875 do_vfp_nsyn_ldm_stm (int is_dbmode
)
10877 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
10881 do_vfp_nsyn_opcode ("fldmdbs");
10883 do_vfp_nsyn_opcode ("fldmias");
10888 do_vfp_nsyn_opcode ("fstmdbs");
10890 do_vfp_nsyn_opcode ("fstmias");
10895 do_vfp_nsyn_sqrt (void)
10897 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
10898 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
10901 do_vfp_nsyn_opcode ("fsqrts");
10903 do_vfp_nsyn_opcode ("fsqrtd");
10907 do_vfp_nsyn_div (void)
10909 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
10910 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
10911 N_F32
| N_F64
| N_KEY
| N_VFP
);
10914 do_vfp_nsyn_opcode ("fdivs");
10916 do_vfp_nsyn_opcode ("fdivd");
10920 do_vfp_nsyn_nmul (void)
10922 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
10923 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
10924 N_F32
| N_F64
| N_KEY
| N_VFP
);
10928 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
10929 do_vfp_sp_dyadic ();
10933 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
10934 do_vfp_dp_rd_rn_rm ();
10936 do_vfp_cond_or_thumb ();
10940 do_vfp_nsyn_cmp (void)
10942 if (inst
.operands
[1].isreg
)
10944 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
10945 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
10949 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
10950 do_vfp_sp_monadic ();
10954 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
10955 do_vfp_dp_rd_rm ();
10960 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
10961 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
10963 switch (inst
.instruction
& 0x0fffffff)
10966 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
10969 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
10977 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
10978 do_vfp_sp_compare_z ();
10982 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
10986 do_vfp_cond_or_thumb ();
10990 nsyn_insert_sp (void)
10992 inst
.operands
[1] = inst
.operands
[0];
10993 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
10994 inst
.operands
[0].reg
= 13;
10995 inst
.operands
[0].isreg
= 1;
10996 inst
.operands
[0].writeback
= 1;
10997 inst
.operands
[0].present
= 1;
11001 do_vfp_nsyn_push (void)
11004 if (inst
.operands
[1].issingle
)
11005 do_vfp_nsyn_opcode ("fstmdbs");
11007 do_vfp_nsyn_opcode ("fstmdbd");
11011 do_vfp_nsyn_pop (void)
11014 if (inst
.operands
[1].issingle
)
11015 do_vfp_nsyn_opcode ("fldmdbs");
11017 do_vfp_nsyn_opcode ("fldmdbd");
11020 /* Fix up Neon data-processing instructions, ORing in the correct bits for
11021 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
11024 neon_dp_fixup (unsigned i
)
11028 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
11042 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
11046 neon_logbits (unsigned x
)
11048 return ffs (x
) - 4;
11051 #define LOW4(R) ((R) & 0xf)
11052 #define HI1(R) (((R) >> 4) & 1)
11054 /* Encode insns with bit pattern:
11056 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
11057 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
11059 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
11060 different meaning for some instruction. */
11063 neon_three_same (int isquad
, int ubit
, int size
)
11065 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11066 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11067 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
11068 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
11069 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
11070 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
11071 inst
.instruction
|= (isquad
!= 0) << 6;
11072 inst
.instruction
|= (ubit
!= 0) << 24;
11074 inst
.instruction
|= neon_logbits (size
) << 20;
11076 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11079 /* Encode instructions of the form:
11081 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
11082 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
11084 Don't write size if SIZE == -1. */
11087 neon_two_same (int qbit
, int ubit
, int size
)
11089 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11090 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11091 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11092 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11093 inst
.instruction
|= (qbit
!= 0) << 6;
11094 inst
.instruction
|= (ubit
!= 0) << 24;
11097 inst
.instruction
|= neon_logbits (size
) << 18;
11099 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11102 /* Neon instruction encoders, in approximate order of appearance. */
11105 do_neon_dyadic_i_su (void)
11107 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11108 struct neon_type_el et
= neon_check_type (3, rs
,
11109 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
11110 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11114 do_neon_dyadic_i64_su (void)
11116 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11117 struct neon_type_el et
= neon_check_type (3, rs
,
11118 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11119 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11123 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
11126 unsigned size
= et
.size
>> 3;
11127 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11128 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11129 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11130 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11131 inst
.instruction
|= (isquad
!= 0) << 6;
11132 inst
.instruction
|= immbits
<< 16;
11133 inst
.instruction
|= (size
>> 3) << 7;
11134 inst
.instruction
|= (size
& 0x7) << 19;
11136 inst
.instruction
|= (uval
!= 0) << 24;
11138 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11142 do_neon_shl_imm (void)
11144 if (!inst
.operands
[2].isreg
)
11146 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11147 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
11148 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11149 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
11153 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11154 struct neon_type_el et
= neon_check_type (3, rs
,
11155 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11156 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11157 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11162 do_neon_qshl_imm (void)
11164 if (!inst
.operands
[2].isreg
)
11166 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11167 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
11168 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11169 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
11170 inst
.operands
[2].imm
);
11174 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11175 struct neon_type_el et
= neon_check_type (3, rs
,
11176 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11177 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11178 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11183 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
11185 /* Handle .I8 and .I64 as pseudo-instructions. */
11189 /* Unfortunately, this will make everything apart from zero out-of-range.
11190 FIXME is this the intended semantics? There doesn't seem much point in
11191 accepting .I8 if so. */
11192 immediate
|= immediate
<< 8;
11196 /* Similarly, anything other than zero will be replicated in bits [63:32],
11197 which probably isn't want we want if we specified .I64. */
11198 if (immediate
!= 0)
11199 goto bad_immediate
;
11205 if (immediate
== (immediate
& 0x000000ff))
11207 *immbits
= immediate
;
11208 return (size
== 16) ? 0x9 : 0x1;
11210 else if (immediate
== (immediate
& 0x0000ff00))
11212 *immbits
= immediate
>> 8;
11213 return (size
== 16) ? 0xb : 0x3;
11215 else if (immediate
== (immediate
& 0x00ff0000))
11217 *immbits
= immediate
>> 16;
11220 else if (immediate
== (immediate
& 0xff000000))
11222 *immbits
= immediate
>> 24;
11227 first_error (_("immediate value out of range"));
11231 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
11235 neon_bits_same_in_bytes (unsigned imm
)
11237 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
11238 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
11239 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
11240 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
11243 /* For immediate of above form, return 0bABCD. */
11246 neon_squash_bits (unsigned imm
)
11248 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
11249 | ((imm
& 0x01000000) >> 21);
11252 /* Compress quarter-float representation to 0b...000 abcdefgh. */
11255 neon_qfloat_bits (unsigned imm
)
11257 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
11260 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
11261 the instruction. *OP is passed as the initial value of the op field, and
11262 may be set to a different value depending on the constant (i.e.
11263 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
11267 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, unsigned *immbits
,
11268 int *op
, int size
, enum neon_el_type type
)
11270 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
11272 if (size
!= 32 || *op
== 1)
11274 *immbits
= neon_qfloat_bits (immlo
);
11277 else if (size
== 64 && neon_bits_same_in_bytes (immhi
)
11278 && neon_bits_same_in_bytes (immlo
))
11280 /* Check this one first so we don't have to bother with immhi in later
11284 *immbits
= (neon_squash_bits (immhi
) << 4) | neon_squash_bits (immlo
);
11288 else if (immhi
!= 0)
11290 else if (immlo
== (immlo
& 0x000000ff))
11292 /* 64-bit case was already handled. Don't allow MVN with 8-bit
11294 if ((size
!= 8 && size
!= 16 && size
!= 32)
11295 || (size
== 8 && *op
== 1))
11298 return (size
== 8) ? 0xe : (size
== 16) ? 0x8 : 0x0;
11300 else if (immlo
== (immlo
& 0x0000ff00))
11302 if (size
!= 16 && size
!= 32)
11304 *immbits
= immlo
>> 8;
11305 return (size
== 16) ? 0xa : 0x2;
11307 else if (immlo
== (immlo
& 0x00ff0000))
11311 *immbits
= immlo
>> 16;
11314 else if (immlo
== (immlo
& 0xff000000))
11318 *immbits
= immlo
>> 24;
11321 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
11325 *immbits
= (immlo
>> 8) & 0xff;
11328 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
11332 *immbits
= (immlo
>> 16) & 0xff;
11339 /* Write immediate bits [7:0] to the following locations:
11341 |28/24|23 19|18 16|15 4|3 0|
11342 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
11344 This function is used by VMOV/VMVN/VORR/VBIC. */
11347 neon_write_immbits (unsigned immbits
)
11349 inst
.instruction
|= immbits
& 0xf;
11350 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
11351 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
11354 /* Invert low-order SIZE bits of XHI:XLO. */
11357 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
11359 unsigned immlo
= xlo
? *xlo
: 0;
11360 unsigned immhi
= xhi
? *xhi
: 0;
11365 immlo
= (~immlo
) & 0xff;
11369 immlo
= (~immlo
) & 0xffff;
11373 immhi
= (~immhi
) & 0xffffffff;
11374 /* fall through. */
11377 immlo
= (~immlo
) & 0xffffffff;
11392 do_neon_logic (void)
11394 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
11396 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11397 neon_check_type (3, rs
, N_IGNORE_TYPE
);
11398 /* U bit and size field were set as part of the bitmask. */
11399 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11400 neon_three_same (neon_quad (rs
), 0, -1);
11404 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
11405 struct neon_type_el et
= neon_check_type (2, rs
,
11406 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
11407 enum neon_opc opcode
= inst
.instruction
& 0x0fffffff;
11411 if (et
.type
== NT_invtype
)
11414 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11419 cmode
= neon_cmode_for_logic_imm (inst
.operands
[1].imm
, &immbits
,
11424 cmode
= neon_cmode_for_logic_imm (inst
.operands
[1].imm
, &immbits
,
11429 /* Pseudo-instruction for VBIC. */
11430 immbits
= inst
.operands
[1].imm
;
11431 neon_invert_size (&immbits
, 0, et
.size
);
11432 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11436 /* Pseudo-instruction for VORR. */
11437 immbits
= inst
.operands
[1].imm
;
11438 neon_invert_size (&immbits
, 0, et
.size
);
11439 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11449 inst
.instruction
|= neon_quad (rs
) << 6;
11450 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11451 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11452 inst
.instruction
|= cmode
<< 8;
11453 neon_write_immbits (immbits
);
11455 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11460 do_neon_bitfield (void)
11462 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11463 neon_check_type (3, rs
, N_IGNORE_TYPE
);
11464 neon_three_same (neon_quad (rs
), 0, -1);
11468 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
11471 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11472 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
11474 if (et
.type
== NT_float
)
11476 inst
.instruction
= NEON_ENC_FLOAT (inst
.instruction
);
11477 neon_three_same (neon_quad (rs
), 0, -1);
11481 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11482 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
11487 do_neon_dyadic_if_su (void)
11489 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
11493 do_neon_dyadic_if_su_d (void)
11495 /* This version only allow D registers, but that constraint is enforced during
11496 operand parsing so we don't need to do anything extra here. */
11497 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
11501 do_neon_dyadic_if_i (void)
11503 neon_dyadic_misc (NT_unsigned
, N_IF_32
, 0);
11507 do_neon_dyadic_if_i_d (void)
11509 neon_dyadic_misc (NT_unsigned
, N_IF_32
, 0);
11512 enum vfp_or_neon_is_neon_bits
11515 NEON_CHECK_ARCH
= 2
11518 /* Call this function if an instruction which may have belonged to the VFP or
11519 Neon instruction sets, but turned out to be a Neon instruction (due to the
11520 operand types involved, etc.). We have to check and/or fix-up a couple of
11523 - Make sure the user hasn't attempted to make a Neon instruction
11525 - Alter the value in the condition code field if necessary.
11526 - Make sure that the arch supports Neon instructions.
11528 Which of these operations take place depends on bits from enum
11529 vfp_or_neon_is_neon_bits.
11531 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
11532 current instruction's condition is COND_ALWAYS, the condition field is
11533 changed to inst.uncond_value. This is necessary because instructions shared
11534 between VFP and Neon may be conditional for the VFP variants only, and the
11535 unconditional Neon version must have, e.g., 0xF in the condition field. */
11538 vfp_or_neon_is_neon (unsigned check
)
11540 /* Conditions are always legal in Thumb mode (IT blocks). */
11541 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
11543 if (inst
.cond
!= COND_ALWAYS
)
11545 first_error (_(BAD_COND
));
11548 if (inst
.uncond_value
!= -1)
11549 inst
.instruction
|= inst
.uncond_value
<< 28;
11552 if ((check
& NEON_CHECK_ARCH
)
11553 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
11555 first_error (_(BAD_FPU
));
11563 do_neon_addsub_if_i (void)
11565 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
11568 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11571 /* The "untyped" case can't happen. Do this to stop the "U" bit being
11572 affected if we specify unsigned args. */
11573 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
11576 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
11578 V<op> A,B (A is operand 0, B is operand 2)
11583 so handle that case specially. */
11586 neon_exchange_operands (void)
11588 void *scratch
= alloca (sizeof (inst
.operands
[0]));
11589 if (inst
.operands
[1].present
)
11591 /* Swap operands[1] and operands[2]. */
11592 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
11593 inst
.operands
[1] = inst
.operands
[2];
11594 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
11598 inst
.operands
[1] = inst
.operands
[2];
11599 inst
.operands
[2] = inst
.operands
[0];
11604 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
11606 if (inst
.operands
[2].isreg
)
11609 neon_exchange_operands ();
11610 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
11614 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11615 struct neon_type_el et
= neon_check_type (2, rs
,
11616 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
11618 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11619 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11620 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11621 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11622 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11623 inst
.instruction
|= neon_quad (rs
) << 6;
11624 inst
.instruction
|= (et
.type
== NT_float
) << 10;
11625 inst
.instruction
|= neon_logbits (et
.size
) << 18;
11627 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11634 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
11638 do_neon_cmp_inv (void)
11640 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
11646 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
11649 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
11650 scalars, which are encoded in 5 bits, M : Rm.
11651 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
11652 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
11656 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
11658 unsigned regno
= NEON_SCALAR_REG (scalar
);
11659 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
11664 if (regno
> 7 || elno
> 3)
11666 return regno
| (elno
<< 3);
11669 if (regno
> 15 || elno
> 1)
11671 return regno
| (elno
<< 4);
11675 first_error (_("scalar out of range for multiply instruction"));
11681 /* Encode multiply / multiply-accumulate scalar instructions. */
11684 neon_mul_mac (struct neon_type_el et
, int ubit
)
11688 /* Give a more helpful error message if we have an invalid type. */
11689 if (et
.type
== NT_invtype
)
11692 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
11693 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11694 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11695 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
11696 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
11697 inst
.instruction
|= LOW4 (scalar
);
11698 inst
.instruction
|= HI1 (scalar
) << 5;
11699 inst
.instruction
|= (et
.type
== NT_float
) << 8;
11700 inst
.instruction
|= neon_logbits (et
.size
) << 20;
11701 inst
.instruction
|= (ubit
!= 0) << 24;
11703 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11707 do_neon_mac_maybe_scalar (void)
11709 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
11712 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11715 if (inst
.operands
[2].isscalar
)
11717 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
11718 struct neon_type_el et
= neon_check_type (3, rs
,
11719 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
11720 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
11721 neon_mul_mac (et
, neon_quad (rs
));
11724 do_neon_dyadic_if_i ();
11730 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11731 struct neon_type_el et
= neon_check_type (3, rs
,
11732 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
11733 neon_three_same (neon_quad (rs
), 0, et
.size
);
11736 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
11737 same types as the MAC equivalents. The polynomial type for this instruction
11738 is encoded the same as the integer type. */
11743 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
11746 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11749 if (inst
.operands
[2].isscalar
)
11750 do_neon_mac_maybe_scalar ();
11752 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
11756 do_neon_qdmulh (void)
11758 if (inst
.operands
[2].isscalar
)
11760 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
11761 struct neon_type_el et
= neon_check_type (3, rs
,
11762 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
11763 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
11764 neon_mul_mac (et
, neon_quad (rs
));
11768 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11769 struct neon_type_el et
= neon_check_type (3, rs
,
11770 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
11771 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11772 /* The U bit (rounding) comes from bit mask. */
11773 neon_three_same (neon_quad (rs
), 0, et
.size
);
11778 do_neon_fcmp_absolute (void)
11780 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11781 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
11782 /* Size field comes from bit mask. */
11783 neon_three_same (neon_quad (rs
), 1, -1);
11787 do_neon_fcmp_absolute_inv (void)
11789 neon_exchange_operands ();
11790 do_neon_fcmp_absolute ();
11794 do_neon_step (void)
11796 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11797 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
11798 neon_three_same (neon_quad (rs
), 0, -1);
11802 do_neon_abs_neg (void)
11804 enum neon_shape rs
;
11805 struct neon_type_el et
;
11807 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
11810 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11813 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
11814 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
11816 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11817 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11818 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11819 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11820 inst
.instruction
|= neon_quad (rs
) << 6;
11821 inst
.instruction
|= (et
.type
== NT_float
) << 10;
11822 inst
.instruction
|= neon_logbits (et
.size
) << 18;
11824 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11830 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11831 struct neon_type_el et
= neon_check_type (2, rs
,
11832 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
11833 int imm
= inst
.operands
[2].imm
;
11834 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
11835 _("immediate out of range for insert"));
11836 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
11842 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11843 struct neon_type_el et
= neon_check_type (2, rs
,
11844 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
11845 int imm
= inst
.operands
[2].imm
;
11846 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
11847 _("immediate out of range for insert"));
11848 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
11852 do_neon_qshlu_imm (void)
11854 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11855 struct neon_type_el et
= neon_check_type (2, rs
,
11856 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
11857 int imm
= inst
.operands
[2].imm
;
11858 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
11859 _("immediate out of range for shift"));
11860 /* Only encodes the 'U present' variant of the instruction.
11861 In this case, signed types have OP (bit 8) set to 0.
11862 Unsigned types have OP set to 1. */
11863 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
11864 /* The rest of the bits are the same as other immediate shifts. */
11865 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
11869 do_neon_qmovn (void)
11871 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
11872 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
11873 /* Saturating move where operands can be signed or unsigned, and the
11874 destination has the same signedness. */
11875 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11876 if (et
.type
== NT_unsigned
)
11877 inst
.instruction
|= 0xc0;
11879 inst
.instruction
|= 0x80;
11880 neon_two_same (0, 1, et
.size
/ 2);
11884 do_neon_qmovun (void)
11886 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
11887 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
11888 /* Saturating move with unsigned results. Operands must be signed. */
11889 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11890 neon_two_same (0, 1, et
.size
/ 2);
11894 do_neon_rshift_sat_narrow (void)
11896 /* FIXME: Types for narrowing. If operands are signed, results can be signed
11897 or unsigned. If operands are unsigned, results must also be unsigned. */
11898 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
11899 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
11900 int imm
= inst
.operands
[2].imm
;
11901 /* This gets the bounds check, size encoding and immediate bits calculation
11905 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
11906 VQMOVN.I<size> <Dd>, <Qm>. */
11909 inst
.operands
[2].present
= 0;
11910 inst
.instruction
= N_MNEM_vqmovn
;
11915 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
11916 _("immediate out of range"));
11917 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
11921 do_neon_rshift_sat_narrow_u (void)
11923 /* FIXME: Types for narrowing. If operands are signed, results can be signed
11924 or unsigned. If operands are unsigned, results must also be unsigned. */
11925 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
11926 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
11927 int imm
= inst
.operands
[2].imm
;
11928 /* This gets the bounds check, size encoding and immediate bits calculation
11932 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
11933 VQMOVUN.I<size> <Dd>, <Qm>. */
11936 inst
.operands
[2].present
= 0;
11937 inst
.instruction
= N_MNEM_vqmovun
;
11942 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
11943 _("immediate out of range"));
11944 /* FIXME: The manual is kind of unclear about what value U should have in
11945 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
11947 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
11951 do_neon_movn (void)
11953 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
11954 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
11955 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11956 neon_two_same (0, 1, et
.size
/ 2);
11960 do_neon_rshift_narrow (void)
11962 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
11963 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
11964 int imm
= inst
.operands
[2].imm
;
11965 /* This gets the bounds check, size encoding and immediate bits calculation
11969 /* If immediate is zero then we are a pseudo-instruction for
11970 VMOVN.I<size> <Dd>, <Qm> */
11973 inst
.operands
[2].present
= 0;
11974 inst
.instruction
= N_MNEM_vmovn
;
11979 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
11980 _("immediate out of range for narrowing operation"));
11981 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
11985 do_neon_shll (void)
11987 /* FIXME: Type checking when lengthening. */
11988 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
11989 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
11990 unsigned imm
= inst
.operands
[2].imm
;
11992 if (imm
== et
.size
)
11994 /* Maximum shift variant. */
11995 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11996 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11997 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11998 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11999 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12000 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12002 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12006 /* A more-specific type check for non-max versions. */
12007 et
= neon_check_type (2, NS_QDI
,
12008 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12009 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12010 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
12014 /* Check the various types for the VCVT instruction, and return which version
12015 the current instruction is. */
12018 neon_cvt_flavour (enum neon_shape rs
)
12020 #define CVT_VAR(C,X,Y) \
12021 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
12022 if (et.type != NT_invtype) \
12024 inst.error = NULL; \
12027 struct neon_type_el et
;
12028 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
12029 || rs
== NS_FF
) ? N_VFP
: 0;
12030 /* The instruction versions which take an immediate take one register
12031 argument, which is extended to the width of the full register. Thus the
12032 "source" and "destination" registers must have the same width. Hack that
12033 here by making the size equal to the key (wider, in this case) operand. */
12034 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
12036 CVT_VAR (0, N_S32
, N_F32
);
12037 CVT_VAR (1, N_U32
, N_F32
);
12038 CVT_VAR (2, N_F32
, N_S32
);
12039 CVT_VAR (3, N_F32
, N_U32
);
12043 /* VFP instructions. */
12044 CVT_VAR (4, N_F32
, N_F64
);
12045 CVT_VAR (5, N_F64
, N_F32
);
12046 CVT_VAR (6, N_S32
, N_F64
| key
);
12047 CVT_VAR (7, N_U32
, N_F64
| key
);
12048 CVT_VAR (8, N_F64
| key
, N_S32
);
12049 CVT_VAR (9, N_F64
| key
, N_U32
);
12050 /* VFP instructions with bitshift. */
12051 CVT_VAR (10, N_F32
| key
, N_S16
);
12052 CVT_VAR (11, N_F32
| key
, N_U16
);
12053 CVT_VAR (12, N_F64
| key
, N_S16
);
12054 CVT_VAR (13, N_F64
| key
, N_U16
);
12055 CVT_VAR (14, N_S16
, N_F32
| key
);
12056 CVT_VAR (15, N_U16
, N_F32
| key
);
12057 CVT_VAR (16, N_S16
, N_F64
| key
);
12058 CVT_VAR (17, N_U16
, N_F64
| key
);
12064 /* Neon-syntax VFP conversions. */
12067 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
12069 const char *opname
= 0;
12071 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
12073 /* Conversions with immediate bitshift. */
12074 const char *enc
[] =
12096 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12098 opname
= enc
[flavour
];
12099 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12100 _("operands 0 and 1 must be the same register"));
12101 inst
.operands
[1] = inst
.operands
[2];
12102 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
12107 /* Conversions without bitshift. */
12108 const char *enc
[] =
12122 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12123 opname
= enc
[flavour
];
12127 do_vfp_nsyn_opcode (opname
);
12131 do_vfp_nsyn_cvtz (void)
12133 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
12134 int flavour
= neon_cvt_flavour (rs
);
12135 const char *enc
[] =
12147 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
12148 do_vfp_nsyn_opcode (enc
[flavour
]);
12154 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
12155 NS_FD
, NS_DF
, NS_FF
, NS_NULL
);
12156 int flavour
= neon_cvt_flavour (rs
);
12158 /* VFP rather than Neon conversions. */
12161 do_vfp_nsyn_cvt (rs
, flavour
);
12170 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12173 /* Fixed-point conversion with #0 immediate is encoded as an
12174 integer conversion. */
12175 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
12177 unsigned immbits
= 32 - inst
.operands
[2].imm
;
12178 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
12179 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12181 inst
.instruction
|= enctab
[flavour
];
12182 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12183 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12184 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12185 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12186 inst
.instruction
|= neon_quad (rs
) << 6;
12187 inst
.instruction
|= 1 << 21;
12188 inst
.instruction
|= immbits
<< 16;
12190 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12198 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
12200 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12202 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12206 inst
.instruction
|= enctab
[flavour
];
12208 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12209 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12210 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12211 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12212 inst
.instruction
|= neon_quad (rs
) << 6;
12213 inst
.instruction
|= 2 << 18;
12215 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12220 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
12221 do_vfp_nsyn_cvt (rs
, flavour
);
12226 neon_move_immediate (void)
12228 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12229 struct neon_type_el et
= neon_check_type (2, rs
,
12230 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12231 unsigned immlo
, immhi
= 0, immbits
;
12234 constraint (et
.type
== NT_invtype
,
12235 _("operand size must be specified for immediate VMOV"));
12237 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
12238 op
= (inst
.instruction
& (1 << 5)) != 0;
12240 immlo
= inst
.operands
[1].imm
;
12241 if (inst
.operands
[1].regisimm
)
12242 immhi
= inst
.operands
[1].reg
;
12244 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
12245 _("immediate has bits set outside the operand size"));
12247 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, &immbits
, &op
,
12248 et
.size
, et
.type
)) == FAIL
)
12250 /* Invert relevant bits only. */
12251 neon_invert_size (&immlo
, &immhi
, et
.size
);
12252 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
12253 with one or the other; those cases are caught by
12254 neon_cmode_for_move_imm. */
12256 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, &immbits
, &op
,
12257 et
.size
, et
.type
)) == FAIL
)
12259 first_error (_("immediate out of range"));
12264 inst
.instruction
&= ~(1 << 5);
12265 inst
.instruction
|= op
<< 5;
12267 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12268 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12269 inst
.instruction
|= neon_quad (rs
) << 6;
12270 inst
.instruction
|= cmode
<< 8;
12272 neon_write_immbits (immbits
);
12278 if (inst
.operands
[1].isreg
)
12280 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12282 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12283 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12284 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12285 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12286 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12287 inst
.instruction
|= neon_quad (rs
) << 6;
12291 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12292 neon_move_immediate ();
12295 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12298 /* Encode instructions of form:
12300 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12301 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm |
12306 neon_mixed_length (struct neon_type_el et
, unsigned size
)
12308 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12309 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12310 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12311 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12312 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12313 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12314 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
12315 inst
.instruction
|= neon_logbits (size
) << 20;
12317 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12321 do_neon_dyadic_long (void)
12323 /* FIXME: Type checking for lengthening op. */
12324 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12325 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12326 neon_mixed_length (et
, et
.size
);
12330 do_neon_abal (void)
12332 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12333 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12334 neon_mixed_length (et
, et
.size
);
12338 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
12340 if (inst
.operands
[2].isscalar
)
12342 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
12343 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
12344 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12345 neon_mul_mac (et
, et
.type
== NT_unsigned
);
12349 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12350 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
12351 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12352 neon_mixed_length (et
, et
.size
);
12357 do_neon_mac_maybe_scalar_long (void)
12359 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
12363 do_neon_dyadic_wide (void)
12365 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
12366 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12367 neon_mixed_length (et
, et
.size
);
12371 do_neon_dyadic_narrow (void)
12373 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12374 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
12375 neon_mixed_length (et
, et
.size
/ 2);
12379 do_neon_mul_sat_scalar_long (void)
12381 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
12385 do_neon_vmull (void)
12387 if (inst
.operands
[2].isscalar
)
12388 do_neon_mac_maybe_scalar_long ();
12391 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12392 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
12393 if (et
.type
== NT_poly
)
12394 inst
.instruction
= NEON_ENC_POLY (inst
.instruction
);
12396 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12397 /* For polynomial encoding, size field must be 0b00 and the U bit must be
12398 zero. Should be OK as-is. */
12399 neon_mixed_length (et
, et
.size
);
12406 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
12407 struct neon_type_el et
= neon_check_type (3, rs
,
12408 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12409 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
12410 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12411 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12412 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12413 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12414 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12415 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12416 inst
.instruction
|= neon_quad (rs
) << 6;
12417 inst
.instruction
|= imm
<< 8;
12419 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12425 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12426 struct neon_type_el et
= neon_check_type (2, rs
,
12427 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12428 unsigned op
= (inst
.instruction
>> 7) & 3;
12429 /* N (width of reversed regions) is encoded as part of the bitmask. We
12430 extract it here to check the elements to be reversed are smaller.
12431 Otherwise we'd get a reserved instruction. */
12432 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
12433 assert (elsize
!= 0);
12434 constraint (et
.size
>= elsize
,
12435 _("elements must be smaller than reversal region"));
12436 neon_two_same (neon_quad (rs
), 1, et
.size
);
12442 if (inst
.operands
[1].isscalar
)
12444 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
12445 struct neon_type_el et
= neon_check_type (2, rs
,
12446 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12447 unsigned sizebits
= et
.size
>> 3;
12448 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
12449 int logsize
= neon_logbits (et
.size
);
12450 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
12452 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
12455 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12456 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12457 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12458 inst
.instruction
|= LOW4 (dm
);
12459 inst
.instruction
|= HI1 (dm
) << 5;
12460 inst
.instruction
|= neon_quad (rs
) << 6;
12461 inst
.instruction
|= x
<< 17;
12462 inst
.instruction
|= sizebits
<< 16;
12464 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12468 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
12469 struct neon_type_el et
= neon_check_type (2, rs
,
12470 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
12471 /* Duplicate ARM register to lanes of vector. */
12472 inst
.instruction
= NEON_ENC_ARMREG (inst
.instruction
);
12475 case 8: inst
.instruction
|= 0x400000; break;
12476 case 16: inst
.instruction
|= 0x000020; break;
12477 case 32: inst
.instruction
|= 0x000000; break;
12480 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
12481 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
12482 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
12483 inst
.instruction
|= neon_quad (rs
) << 21;
12484 /* The encoding for this instruction is identical for the ARM and Thumb
12485 variants, except for the condition field. */
12486 do_vfp_cond_or_thumb ();
12490 /* VMOV has particularly many variations. It can be one of:
12491 0. VMOV<c><q> <Qd>, <Qm>
12492 1. VMOV<c><q> <Dd>, <Dm>
12493 (Register operations, which are VORR with Rm = Rn.)
12494 2. VMOV<c><q>.<dt> <Qd>, #<imm>
12495 3. VMOV<c><q>.<dt> <Dd>, #<imm>
12497 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
12498 (ARM register to scalar.)
12499 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
12500 (Two ARM registers to vector.)
12501 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
12502 (Scalar to ARM register.)
12503 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
12504 (Vector to two ARM registers.)
12505 8. VMOV.F32 <Sd>, <Sm>
12506 9. VMOV.F64 <Dd>, <Dm>
12507 (VFP register moves.)
12508 10. VMOV.F32 <Sd>, #imm
12509 11. VMOV.F64 <Dd>, #imm
12510 (VFP float immediate load.)
12511 12. VMOV <Rd>, <Sm>
12512 (VFP single to ARM reg.)
12513 13. VMOV <Sd>, <Rm>
12514 (ARM reg to VFP single.)
12515 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
12516 (Two ARM regs to two VFP singles.)
12517 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
12518 (Two VFP singles to two ARM regs.)
12520 These cases can be disambiguated using neon_select_shape, except cases 1/9
12521 and 3/11 which depend on the operand type too.
12523 All the encoded bits are hardcoded by this function.
12525 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
12526 Cases 5, 7 may be used with VFPv2 and above.
12528 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
12529 can specify a type where it doesn't make sense to, and is ignored).
12535 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
12536 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
12538 struct neon_type_el et
;
12539 const char *ldconst
= 0;
12543 case NS_DD
: /* case 1/9. */
12544 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
12545 /* It is not an error here if no type is given. */
12547 if (et
.type
== NT_float
&& et
.size
== 64)
12549 do_vfp_nsyn_opcode ("fcpyd");
12552 /* fall through. */
12554 case NS_QQ
: /* case 0/1. */
12556 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12558 /* The architecture manual I have doesn't explicitly state which
12559 value the U bit should have for register->register moves, but
12560 the equivalent VORR instruction has U = 0, so do that. */
12561 inst
.instruction
= 0x0200110;
12562 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12563 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12564 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12565 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12566 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12567 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12568 inst
.instruction
|= neon_quad (rs
) << 6;
12570 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12574 case NS_DI
: /* case 3/11. */
12575 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
12577 if (et
.type
== NT_float
&& et
.size
== 64)
12579 /* case 11 (fconstd). */
12580 ldconst
= "fconstd";
12581 goto encode_fconstd
;
12583 /* fall through. */
12585 case NS_QI
: /* case 2/3. */
12586 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12588 inst
.instruction
= 0x0800010;
12589 neon_move_immediate ();
12590 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12593 case NS_SR
: /* case 4. */
12595 unsigned bcdebits
= 0;
12596 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
12597 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
12598 int logsize
= neon_logbits (et
.size
);
12599 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
12600 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
12602 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
12604 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
12605 && et
.size
!= 32, _(BAD_FPU
));
12606 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
12607 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
12611 case 8: bcdebits
= 0x8; break;
12612 case 16: bcdebits
= 0x1; break;
12613 case 32: bcdebits
= 0x0; break;
12617 bcdebits
|= x
<< logsize
;
12619 inst
.instruction
= 0xe000b10;
12620 do_vfp_cond_or_thumb ();
12621 inst
.instruction
|= LOW4 (dn
) << 16;
12622 inst
.instruction
|= HI1 (dn
) << 7;
12623 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12624 inst
.instruction
|= (bcdebits
& 3) << 5;
12625 inst
.instruction
|= (bcdebits
>> 2) << 21;
12629 case NS_DRR
: /* case 5 (fmdrr). */
12630 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
12633 inst
.instruction
= 0xc400b10;
12634 do_vfp_cond_or_thumb ();
12635 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
12636 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
12637 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12638 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12641 case NS_RS
: /* case 6. */
12643 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
12644 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
12645 unsigned logsize
= neon_logbits (et
.size
);
12646 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
12647 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
12648 unsigned abcdebits
= 0;
12650 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
12652 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
12653 && et
.size
!= 32, _(BAD_FPU
));
12654 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
12655 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
12659 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
12660 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
12661 case 32: abcdebits
= 0x00; break;
12665 abcdebits
|= x
<< logsize
;
12666 inst
.instruction
= 0xe100b10;
12667 do_vfp_cond_or_thumb ();
12668 inst
.instruction
|= LOW4 (dn
) << 16;
12669 inst
.instruction
|= HI1 (dn
) << 7;
12670 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12671 inst
.instruction
|= (abcdebits
& 3) << 5;
12672 inst
.instruction
|= (abcdebits
>> 2) << 21;
12676 case NS_RRD
: /* case 7 (fmrrd). */
12677 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
12680 inst
.instruction
= 0xc500b10;
12681 do_vfp_cond_or_thumb ();
12682 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12683 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12684 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12685 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12688 case NS_FF
: /* case 8 (fcpys). */
12689 do_vfp_nsyn_opcode ("fcpys");
12692 case NS_FI
: /* case 10 (fconsts). */
12693 ldconst
= "fconsts";
12695 if (is_quarter_float (inst
.operands
[1].imm
))
12697 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
12698 do_vfp_nsyn_opcode (ldconst
);
12701 first_error (_("immediate out of range"));
12704 case NS_RF
: /* case 12 (fmrs). */
12705 do_vfp_nsyn_opcode ("fmrs");
12708 case NS_FR
: /* case 13 (fmsr). */
12709 do_vfp_nsyn_opcode ("fmsr");
12712 /* The encoders for the fmrrs and fmsrr instructions expect three operands
12713 (one of which is a list), but we have parsed four. Do some fiddling to
12714 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
12716 case NS_RRFF
: /* case 14 (fmrrs). */
12717 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
12718 _("VFP registers must be adjacent"));
12719 inst
.operands
[2].imm
= 2;
12720 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
12721 do_vfp_nsyn_opcode ("fmrrs");
12724 case NS_FFRR
: /* case 15 (fmsrr). */
12725 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
12726 _("VFP registers must be adjacent"));
12727 inst
.operands
[1] = inst
.operands
[2];
12728 inst
.operands
[2] = inst
.operands
[3];
12729 inst
.operands
[0].imm
= 2;
12730 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
12731 do_vfp_nsyn_opcode ("fmsrr");
12740 do_neon_rshift_round_imm (void)
12742 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12743 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12744 int imm
= inst
.operands
[2].imm
;
12746 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
12749 inst
.operands
[2].present
= 0;
12754 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12755 _("immediate out of range for shift"));
12756 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12761 do_neon_movl (void)
12763 struct neon_type_el et
= neon_check_type (2, NS_QD
,
12764 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12765 unsigned sizebits
= et
.size
>> 3;
12766 inst
.instruction
|= sizebits
<< 19;
12767 neon_two_same (0, et
.type
== NT_unsigned
, -1);
12773 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12774 struct neon_type_el et
= neon_check_type (2, rs
,
12775 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12776 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12777 neon_two_same (neon_quad (rs
), 1, et
.size
);
12781 do_neon_zip_uzp (void)
12783 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12784 struct neon_type_el et
= neon_check_type (2, rs
,
12785 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12786 if (rs
== NS_DD
&& et
.size
== 32)
12788 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
12789 inst
.instruction
= N_MNEM_vtrn
;
12793 neon_two_same (neon_quad (rs
), 1, et
.size
);
12797 do_neon_sat_abs_neg (void)
12799 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12800 struct neon_type_el et
= neon_check_type (2, rs
,
12801 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
12802 neon_two_same (neon_quad (rs
), 1, et
.size
);
12806 do_neon_pair_long (void)
12808 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12809 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
12810 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
12811 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
12812 neon_two_same (neon_quad (rs
), 1, et
.size
);
12816 do_neon_recip_est (void)
12818 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12819 struct neon_type_el et
= neon_check_type (2, rs
,
12820 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
12821 inst
.instruction
|= (et
.type
== NT_float
) << 8;
12822 neon_two_same (neon_quad (rs
), 1, et
.size
);
12828 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12829 struct neon_type_el et
= neon_check_type (2, rs
,
12830 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
12831 neon_two_same (neon_quad (rs
), 1, et
.size
);
12837 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12838 struct neon_type_el et
= neon_check_type (2, rs
,
12839 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
12840 neon_two_same (neon_quad (rs
), 1, et
.size
);
12846 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12847 struct neon_type_el et
= neon_check_type (2, rs
,
12848 N_EQK
| N_INT
, N_8
| N_KEY
);
12849 neon_two_same (neon_quad (rs
), 1, et
.size
);
12855 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12856 neon_two_same (neon_quad (rs
), 1, -1);
12860 do_neon_tbl_tbx (void)
12862 unsigned listlenbits
;
12863 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
12865 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
12867 first_error (_("bad list length for table lookup"));
12871 listlenbits
= inst
.operands
[1].imm
- 1;
12872 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12873 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12874 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12875 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12876 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12877 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12878 inst
.instruction
|= listlenbits
<< 8;
12880 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12884 do_neon_ldm_stm (void)
12886 /* P, U and L bits are part of bitmask. */
12887 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
12888 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
12890 if (inst
.operands
[1].issingle
)
12892 do_vfp_nsyn_ldm_stm (is_dbmode
);
12896 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
12897 _("writeback (!) must be used for VLDMDB and VSTMDB"));
12899 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
12900 _("register list must contain at least 1 and at most 16 "
12903 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
12904 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
12905 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
12906 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
12908 inst
.instruction
|= offsetbits
;
12910 do_vfp_cond_or_thumb ();
12914 do_neon_ldr_str (void)
12916 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
12918 if (inst
.operands
[0].issingle
)
12921 do_vfp_nsyn_opcode ("flds");
12923 do_vfp_nsyn_opcode ("fsts");
12928 do_vfp_nsyn_opcode ("fldd");
12930 do_vfp_nsyn_opcode ("fstd");
12934 /* "interleave" version also handles non-interleaving register VLD1/VST1
12938 do_neon_ld_st_interleave (void)
12940 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
12941 N_8
| N_16
| N_32
| N_64
);
12942 unsigned alignbits
= 0;
12944 /* The bits in this table go:
12945 0: register stride of one (0) or two (1)
12946 1,2: register list length, minus one (1, 2, 3, 4).
12947 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
12948 We use -1 for invalid entries. */
12949 const int typetable
[] =
12951 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
12952 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
12953 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
12954 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
12958 if (et
.type
== NT_invtype
)
12961 if (inst
.operands
[1].immisalign
)
12962 switch (inst
.operands
[1].imm
>> 8)
12964 case 64: alignbits
= 1; break;
12966 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
12967 goto bad_alignment
;
12971 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
12972 goto bad_alignment
;
12977 first_error (_("bad alignment"));
12981 inst
.instruction
|= alignbits
<< 4;
12982 inst
.instruction
|= neon_logbits (et
.size
) << 6;
12984 /* Bits [4:6] of the immediate in a list specifier encode register stride
12985 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
12986 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
12987 up the right value for "type" in a table based on this value and the given
12988 list style, then stick it back. */
12989 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
12990 | (((inst
.instruction
>> 8) & 3) << 3);
12992 typebits
= typetable
[idx
];
12994 constraint (typebits
== -1, _("bad list type for instruction"));
12996 inst
.instruction
&= ~0xf00;
12997 inst
.instruction
|= typebits
<< 8;
13000 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
13001 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
13002 otherwise. The variable arguments are a list of pairs of legal (size, align)
13003 values, terminated with -1. */
13006 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
13009 int result
= FAIL
, thissize
, thisalign
;
13011 if (!inst
.operands
[1].immisalign
)
13017 va_start (ap
, do_align
);
13021 thissize
= va_arg (ap
, int);
13022 if (thissize
== -1)
13024 thisalign
= va_arg (ap
, int);
13026 if (size
== thissize
&& align
== thisalign
)
13029 while (result
!= SUCCESS
);
13033 if (result
== SUCCESS
)
13036 first_error (_("unsupported alignment for instruction"));
13042 do_neon_ld_st_lane (void)
13044 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13045 int align_good
, do_align
= 0;
13046 int logsize
= neon_logbits (et
.size
);
13047 int align
= inst
.operands
[1].imm
>> 8;
13048 int n
= (inst
.instruction
>> 8) & 3;
13049 int max_el
= 64 / et
.size
;
13051 if (et
.type
== NT_invtype
)
13054 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
13055 _("bad list length"));
13056 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
13057 _("scalar index out of range"));
13058 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
13060 _("stride of 2 unavailable when element size is 8"));
13064 case 0: /* VLD1 / VST1. */
13065 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
13067 if (align_good
== FAIL
)
13071 unsigned alignbits
= 0;
13074 case 16: alignbits
= 0x1; break;
13075 case 32: alignbits
= 0x3; break;
13078 inst
.instruction
|= alignbits
<< 4;
13082 case 1: /* VLD2 / VST2. */
13083 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
13085 if (align_good
== FAIL
)
13088 inst
.instruction
|= 1 << 4;
13091 case 2: /* VLD3 / VST3. */
13092 constraint (inst
.operands
[1].immisalign
,
13093 _("can't use alignment with this instruction"));
13096 case 3: /* VLD4 / VST4. */
13097 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13098 16, 64, 32, 64, 32, 128, -1);
13099 if (align_good
== FAIL
)
13103 unsigned alignbits
= 0;
13106 case 8: alignbits
= 0x1; break;
13107 case 16: alignbits
= 0x1; break;
13108 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
13111 inst
.instruction
|= alignbits
<< 4;
13118 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
13119 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13120 inst
.instruction
|= 1 << (4 + logsize
);
13122 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
13123 inst
.instruction
|= logsize
<< 10;
13126 /* Encode single n-element structure to all lanes VLD<n> instructions. */
13129 do_neon_ld_dup (void)
13131 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13132 int align_good
, do_align
= 0;
13134 if (et
.type
== NT_invtype
)
13137 switch ((inst
.instruction
>> 8) & 3)
13139 case 0: /* VLD1. */
13140 assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
13141 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13142 &do_align
, 16, 16, 32, 32, -1);
13143 if (align_good
== FAIL
)
13145 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
13148 case 2: inst
.instruction
|= 1 << 5; break;
13149 default: first_error (_("bad list length")); return;
13151 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13154 case 1: /* VLD2. */
13155 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13156 &do_align
, 8, 16, 16, 32, 32, 64, -1);
13157 if (align_good
== FAIL
)
13159 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
13160 _("bad list length"));
13161 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13162 inst
.instruction
|= 1 << 5;
13163 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13166 case 2: /* VLD3. */
13167 constraint (inst
.operands
[1].immisalign
,
13168 _("can't use alignment with this instruction"));
13169 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
13170 _("bad list length"));
13171 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13172 inst
.instruction
|= 1 << 5;
13173 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13176 case 3: /* VLD4. */
13178 int align
= inst
.operands
[1].imm
>> 8;
13179 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13180 16, 64, 32, 64, 32, 128, -1);
13181 if (align_good
== FAIL
)
13183 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
13184 _("bad list length"));
13185 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13186 inst
.instruction
|= 1 << 5;
13187 if (et
.size
== 32 && align
== 128)
13188 inst
.instruction
|= 0x3 << 6;
13190 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13197 inst
.instruction
|= do_align
<< 4;
13200 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
13201 apart from bits [11:4]. */
13204 do_neon_ldx_stx (void)
13206 switch (NEON_LANE (inst
.operands
[0].imm
))
13208 case NEON_INTERLEAVE_LANES
:
13209 inst
.instruction
= NEON_ENC_INTERLV (inst
.instruction
);
13210 do_neon_ld_st_interleave ();
13213 case NEON_ALL_LANES
:
13214 inst
.instruction
= NEON_ENC_DUP (inst
.instruction
);
13219 inst
.instruction
= NEON_ENC_LANE (inst
.instruction
);
13220 do_neon_ld_st_lane ();
13223 /* L bit comes from bit mask. */
13224 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13225 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13226 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13228 if (inst
.operands
[1].postind
)
13230 int postreg
= inst
.operands
[1].imm
& 0xf;
13231 constraint (!inst
.operands
[1].immisreg
,
13232 _("post-index must be a register"));
13233 constraint (postreg
== 0xd || postreg
== 0xf,
13234 _("bad register for post-index"));
13235 inst
.instruction
|= postreg
;
13237 else if (inst
.operands
[1].writeback
)
13239 inst
.instruction
|= 0xd;
13242 inst
.instruction
|= 0xf;
13245 inst
.instruction
|= 0xf9000000;
13247 inst
.instruction
|= 0xf4000000;
13251 /* Overall per-instruction processing. */
13253 /* We need to be able to fix up arbitrary expressions in some statements.
13254 This is so that we can handle symbols that are an arbitrary distance from
13255 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
13256 which returns part of an address in a form which will be valid for
13257 a data instruction. We do this by pushing the expression into a symbol
13258 in the expr_section, and creating a fix for that. */
13261 fix_new_arm (fragS
* frag
,
13276 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
13280 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
13285 /* Mark whether the fix is to a THUMB instruction, or an ARM
13287 new_fix
->tc_fix_data
= thumb_mode
;
13290 /* Create a frg for an instruction requiring relaxation. */
13292 output_relax_insn (void)
13299 /* The size of the instruction is unknown, so tie the debug info to the
13300 start of the instruction. */
13301 dwarf2_emit_insn (0);
13304 switch (inst
.reloc
.exp
.X_op
)
13307 sym
= inst
.reloc
.exp
.X_add_symbol
;
13308 offset
= inst
.reloc
.exp
.X_add_number
;
13312 offset
= inst
.reloc
.exp
.X_add_number
;
13315 sym
= make_expr_symbol (&inst
.reloc
.exp
);
13319 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
13320 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
13321 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
13324 /* Write a 32-bit thumb instruction to buf. */
13326 put_thumb32_insn (char * buf
, unsigned long insn
)
13328 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
13329 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
13333 output_inst (const char * str
)
13339 as_bad ("%s -- `%s'", inst
.error
, str
);
13343 output_relax_insn();
13346 if (inst
.size
== 0)
13349 to
= frag_more (inst
.size
);
13351 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
13353 assert (inst
.size
== (2 * THUMB_SIZE
));
13354 put_thumb32_insn (to
, inst
.instruction
);
13356 else if (inst
.size
> INSN_SIZE
)
13358 assert (inst
.size
== (2 * INSN_SIZE
));
13359 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
13360 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
13363 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
13365 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
13366 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
13367 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
13371 dwarf2_emit_insn (inst
.size
);
13375 /* Tag values used in struct asm_opcode's tag field. */
13378 OT_unconditional
, /* Instruction cannot be conditionalized.
13379 The ARM condition field is still 0xE. */
13380 OT_unconditionalF
, /* Instruction cannot be conditionalized
13381 and carries 0xF in its ARM condition field. */
13382 OT_csuffix
, /* Instruction takes a conditional suffix. */
13383 OT_csuffixF
, /* Some forms of the instruction take a conditional
13384 suffix, others place 0xF where the condition field
13386 OT_cinfix3
, /* Instruction takes a conditional infix,
13387 beginning at character index 3. (In
13388 unified mode, it becomes a suffix.) */
13389 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
13390 tsts, cmps, cmns, and teqs. */
13391 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
13392 character index 3, even in unified mode. Used for
13393 legacy instructions where suffix and infix forms
13394 may be ambiguous. */
13395 OT_csuf_or_in3
, /* Instruction takes either a conditional
13396 suffix or an infix at character index 3. */
13397 OT_odd_infix_unc
, /* This is the unconditional variant of an
13398 instruction that takes a conditional infix
13399 at an unusual position. In unified mode,
13400 this variant will accept a suffix. */
13401 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
13402 are the conditional variants of instructions that
13403 take conditional infixes in unusual positions.
13404 The infix appears at character index
13405 (tag - OT_odd_infix_0). These are not accepted
13406 in unified mode. */
13409 /* Subroutine of md_assemble, responsible for looking up the primary
13410 opcode from the mnemonic the user wrote. STR points to the
13411 beginning of the mnemonic.
13413 This is not simply a hash table lookup, because of conditional
13414 variants. Most instructions have conditional variants, which are
13415 expressed with a _conditional affix_ to the mnemonic. If we were
13416 to encode each conditional variant as a literal string in the opcode
13417 table, it would have approximately 20,000 entries.
13419 Most mnemonics take this affix as a suffix, and in unified syntax,
13420 'most' is upgraded to 'all'. However, in the divided syntax, some
13421 instructions take the affix as an infix, notably the s-variants of
13422 the arithmetic instructions. Of those instructions, all but six
13423 have the infix appear after the third character of the mnemonic.
13425 Accordingly, the algorithm for looking up primary opcodes given
13428 1. Look up the identifier in the opcode table.
13429 If we find a match, go to step U.
13431 2. Look up the last two characters of the identifier in the
13432 conditions table. If we find a match, look up the first N-2
13433 characters of the identifier in the opcode table. If we
13434 find a match, go to step CE.
13436 3. Look up the fourth and fifth characters of the identifier in
13437 the conditions table. If we find a match, extract those
13438 characters from the identifier, and look up the remaining
13439 characters in the opcode table. If we find a match, go
13444 U. Examine the tag field of the opcode structure, in case this is
13445 one of the six instructions with its conditional infix in an
13446 unusual place. If it is, the tag tells us where to find the
13447 infix; look it up in the conditions table and set inst.cond
13448 accordingly. Otherwise, this is an unconditional instruction.
13449 Again set inst.cond accordingly. Return the opcode structure.
13451 CE. Examine the tag field to make sure this is an instruction that
13452 should receive a conditional suffix. If it is not, fail.
13453 Otherwise, set inst.cond from the suffix we already looked up,
13454 and return the opcode structure.
13456 CM. Examine the tag field to make sure this is an instruction that
13457 should receive a conditional infix after the third character.
13458 If it is not, fail. Otherwise, undo the edits to the current
13459 line of input and proceed as for case CE. */
13461 static const struct asm_opcode
*
13462 opcode_lookup (char **str
)
13466 const struct asm_opcode
*opcode
;
13467 const struct asm_cond
*cond
;
13470 /* Scan up to the end of the mnemonic, which must end in white space,
13471 '.' (in unified mode only), or end of string. */
13472 for (base
= end
= *str
; *end
!= '\0'; end
++)
13473 if (*end
== ' ' || (unified_syntax
&& *end
== '.'))
13479 /* Handle a possible width suffix and/or Neon type suffix. */
13486 else if (end
[1] == 'n')
13491 inst
.vectype
.elems
= 0;
13493 *str
= end
+ offset
;
13495 if (end
[offset
] == '.')
13497 /* See if we have a Neon type suffix. */
13498 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
13501 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
13507 /* Look for unaffixed or special-case affixed mnemonic. */
13508 opcode
= hash_find_n (arm_ops_hsh
, base
, end
- base
);
13512 if (opcode
->tag
< OT_odd_infix_0
)
13514 inst
.cond
= COND_ALWAYS
;
13518 if (unified_syntax
)
13519 as_warn (_("conditional infixes are deprecated in unified syntax"));
13520 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
13521 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
13524 inst
.cond
= cond
->value
;
13528 /* Cannot have a conditional suffix on a mnemonic of less than two
13530 if (end
- base
< 3)
13533 /* Look for suffixed mnemonic. */
13535 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
13536 opcode
= hash_find_n (arm_ops_hsh
, base
, affix
- base
);
13537 if (opcode
&& cond
)
13540 switch (opcode
->tag
)
13542 case OT_cinfix3_legacy
:
13543 /* Ignore conditional suffixes matched on infix only mnemonics. */
13547 case OT_cinfix3_deprecated
:
13548 case OT_odd_infix_unc
:
13549 if (!unified_syntax
)
13551 /* else fall through */
13555 case OT_csuf_or_in3
:
13556 inst
.cond
= cond
->value
;
13559 case OT_unconditional
:
13560 case OT_unconditionalF
:
13563 inst
.cond
= cond
->value
;
13567 /* delayed diagnostic */
13568 inst
.error
= BAD_COND
;
13569 inst
.cond
= COND_ALWAYS
;
13578 /* Cannot have a usual-position infix on a mnemonic of less than
13579 six characters (five would be a suffix). */
13580 if (end
- base
< 6)
13583 /* Look for infixed mnemonic in the usual position. */
13585 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
13589 memcpy (save
, affix
, 2);
13590 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
13591 opcode
= hash_find_n (arm_ops_hsh
, base
, (end
- base
) - 2);
13592 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
13593 memcpy (affix
, save
, 2);
13596 && (opcode
->tag
== OT_cinfix3
13597 || opcode
->tag
== OT_cinfix3_deprecated
13598 || opcode
->tag
== OT_csuf_or_in3
13599 || opcode
->tag
== OT_cinfix3_legacy
))
13603 && (opcode
->tag
== OT_cinfix3
13604 || opcode
->tag
== OT_cinfix3_deprecated
))
13605 as_warn (_("conditional infixes are deprecated in unified syntax"));
13607 inst
.cond
= cond
->value
;
13615 md_assemble (char *str
)
13618 const struct asm_opcode
* opcode
;
13620 /* Align the previous label if needed. */
13621 if (last_label_seen
!= NULL
)
13623 symbol_set_frag (last_label_seen
, frag_now
);
13624 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
13625 S_SET_SEGMENT (last_label_seen
, now_seg
);
13628 memset (&inst
, '\0', sizeof (inst
));
13629 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13631 opcode
= opcode_lookup (&p
);
13634 /* It wasn't an instruction, but it might be a register alias of
13635 the form alias .req reg, or a Neon .dn/.qn directive. */
13636 if (!create_register_alias (str
, p
)
13637 && !create_neon_reg_alias (str
, p
))
13638 as_bad (_("bad instruction `%s'"), str
);
13643 if (opcode
->tag
== OT_cinfix3_deprecated
)
13644 as_warn (_("s suffix on comparison instruction is deprecated"));
13646 /* The value which unconditional instructions should have in place of the
13647 condition field. */
13648 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
13652 arm_feature_set variant
;
13654 variant
= cpu_variant
;
13655 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
13656 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
13657 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
13658 /* Check that this instruction is supported for this CPU. */
13659 if (!opcode
->tvariant
13660 || (thumb_mode
== 1
13661 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
13663 as_bad (_("selected processor does not support `%s'"), str
);
13666 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
13667 && opcode
->tencode
!= do_t_branch
)
13669 as_bad (_("Thumb does not support conditional execution"));
13673 /* Check conditional suffixes. */
13674 if (current_it_mask
)
13677 cond
= current_cc
^ ((current_it_mask
>> 4) & 1) ^ 1;
13678 current_it_mask
<<= 1;
13679 current_it_mask
&= 0x1f;
13680 /* The BKPT instruction is unconditional even in an IT block. */
13682 && cond
!= inst
.cond
&& opcode
->tencode
!= do_t_bkpt
)
13684 as_bad (_("incorrect condition in IT block"));
13688 else if (inst
.cond
!= COND_ALWAYS
&& opcode
->tencode
!= do_t_branch
)
13690 as_bad (_("thumb conditional instrunction not in IT block"));
13694 mapping_state (MAP_THUMB
);
13695 inst
.instruction
= opcode
->tvalue
;
13697 if (!parse_operands (p
, opcode
->operands
))
13698 opcode
->tencode ();
13700 /* Clear current_it_mask at the end of an IT block. */
13701 if (current_it_mask
== 0x10)
13702 current_it_mask
= 0;
13704 if (!(inst
.error
|| inst
.relax
))
13706 assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
13707 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
13708 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
13710 as_bad (_("cannot honor width suffix -- `%s'"), str
);
13714 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13715 *opcode
->tvariant
);
13716 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
13717 set those bits when Thumb-2 32-bit instructions are seen. ie.
13718 anything other than bl/blx.
13719 This is overly pessimistic for relaxable instructions. */
13720 if ((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
13722 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13727 /* Check that this instruction is supported for this CPU. */
13728 if (!opcode
->avariant
||
13729 !ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
))
13731 as_bad (_("selected processor does not support `%s'"), str
);
13736 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
13740 mapping_state (MAP_ARM
);
13741 inst
.instruction
= opcode
->avalue
;
13742 if (opcode
->tag
== OT_unconditionalF
)
13743 inst
.instruction
|= 0xF << 28;
13745 inst
.instruction
|= inst
.cond
<< 28;
13746 inst
.size
= INSN_SIZE
;
13747 if (!parse_operands (p
, opcode
->operands
))
13748 opcode
->aencode ();
13749 /* Arm mode bx is marked as both v4T and v5 because it's still required
13750 on a hypothetical non-thumb v5 core. */
13751 if (ARM_CPU_HAS_FEATURE (*opcode
->avariant
, arm_ext_v4t
)
13752 || ARM_CPU_HAS_FEATURE (*opcode
->avariant
, arm_ext_v5
))
13753 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
13755 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
13756 *opcode
->avariant
);
13761 /* Various frobbings of labels and their addresses. */
13764 arm_start_line_hook (void)
13766 last_label_seen
= NULL
;
13770 arm_frob_label (symbolS
* sym
)
13772 last_label_seen
= sym
;
13774 ARM_SET_THUMB (sym
, thumb_mode
);
13776 #if defined OBJ_COFF || defined OBJ_ELF
13777 ARM_SET_INTERWORK (sym
, support_interwork
);
13780 /* Note - do not allow local symbols (.Lxxx) to be labeled
13781 as Thumb functions. This is because these labels, whilst
13782 they exist inside Thumb code, are not the entry points for
13783 possible ARM->Thumb calls. Also, these labels can be used
13784 as part of a computed goto or switch statement. eg gcc
13785 can generate code that looks like this:
13787 ldr r2, [pc, .Laaa]
13797 The first instruction loads the address of the jump table.
13798 The second instruction converts a table index into a byte offset.
13799 The third instruction gets the jump address out of the table.
13800 The fourth instruction performs the jump.
13802 If the address stored at .Laaa is that of a symbol which has the
13803 Thumb_Func bit set, then the linker will arrange for this address
13804 to have the bottom bit set, which in turn would mean that the
13805 address computation performed by the third instruction would end
13806 up with the bottom bit set. Since the ARM is capable of unaligned
13807 word loads, the instruction would then load the incorrect address
13808 out of the jump table, and chaos would ensue. */
13809 if (label_is_thumb_function_name
13810 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
13811 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
13813 /* When the address of a Thumb function is taken the bottom
13814 bit of that address should be set. This will allow
13815 interworking between Arm and Thumb functions to work
13818 THUMB_SET_FUNC (sym
, 1);
13820 label_is_thumb_function_name
= FALSE
;
13824 dwarf2_emit_label (sym
);
13829 arm_data_in_code (void)
13831 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
13833 *input_line_pointer
= '/';
13834 input_line_pointer
+= 5;
13835 *input_line_pointer
= 0;
13843 arm_canonicalize_symbol_name (char * name
)
13847 if (thumb_mode
&& (len
= strlen (name
)) > 5
13848 && streq (name
+ len
- 5, "/data"))
13849 *(name
+ len
- 5) = 0;
13854 /* Table of all register names defined by default. The user can
13855 define additional names with .req. Note that all register names
13856 should appear in both upper and lowercase variants. Some registers
13857 also have mixed-case names. */
13859 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
13860 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
13861 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
13862 #define REGSET(p,t) \
13863 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
13864 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
13865 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
13866 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
13867 #define REGSETH(p,t) \
13868 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
13869 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
13870 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
13871 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
13872 #define REGSET2(p,t) \
13873 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
13874 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
13875 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
13876 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
13878 static const struct reg_entry reg_names
[] =
13880 /* ARM integer registers. */
13881 REGSET(r
, RN
), REGSET(R
, RN
),
13883 /* ATPCS synonyms. */
13884 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
13885 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
13886 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
13888 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
13889 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
13890 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
13892 /* Well-known aliases. */
13893 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
13894 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
13896 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
13897 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
13899 /* Coprocessor numbers. */
13900 REGSET(p
, CP
), REGSET(P
, CP
),
13902 /* Coprocessor register numbers. The "cr" variants are for backward
13904 REGSET(c
, CN
), REGSET(C
, CN
),
13905 REGSET(cr
, CN
), REGSET(CR
, CN
),
13907 /* FPA registers. */
13908 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
13909 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
13911 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
13912 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
13914 /* VFP SP registers. */
13915 REGSET(s
,VFS
), REGSET(S
,VFS
),
13916 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
13918 /* VFP DP Registers. */
13919 REGSET(d
,VFD
), REGSET(D
,VFD
),
13920 /* Extra Neon DP registers. */
13921 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
13923 /* Neon QP registers. */
13924 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
13926 /* VFP control registers. */
13927 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
13928 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
13930 /* Maverick DSP coprocessor registers. */
13931 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
13932 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
13934 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
13935 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
13936 REGDEF(dspsc
,0,DSPSC
),
13938 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
13939 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
13940 REGDEF(DSPSC
,0,DSPSC
),
13942 /* iWMMXt data registers - p0, c0-15. */
13943 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
13945 /* iWMMXt control registers - p1, c0-3. */
13946 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
13947 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
13948 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
13949 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
13951 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
13952 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
13953 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
13954 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
13955 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
13957 /* XScale accumulator registers. */
13958 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
13964 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
13965 within psr_required_here. */
13966 static const struct asm_psr psrs
[] =
13968 /* Backward compatibility notation. Note that "all" is no longer
13969 truly all possible PSR bits. */
13970 {"all", PSR_c
| PSR_f
},
13974 /* Individual flags. */
13979 /* Combinations of flags. */
13980 {"fs", PSR_f
| PSR_s
},
13981 {"fx", PSR_f
| PSR_x
},
13982 {"fc", PSR_f
| PSR_c
},
13983 {"sf", PSR_s
| PSR_f
},
13984 {"sx", PSR_s
| PSR_x
},
13985 {"sc", PSR_s
| PSR_c
},
13986 {"xf", PSR_x
| PSR_f
},
13987 {"xs", PSR_x
| PSR_s
},
13988 {"xc", PSR_x
| PSR_c
},
13989 {"cf", PSR_c
| PSR_f
},
13990 {"cs", PSR_c
| PSR_s
},
13991 {"cx", PSR_c
| PSR_x
},
13992 {"fsx", PSR_f
| PSR_s
| PSR_x
},
13993 {"fsc", PSR_f
| PSR_s
| PSR_c
},
13994 {"fxs", PSR_f
| PSR_x
| PSR_s
},
13995 {"fxc", PSR_f
| PSR_x
| PSR_c
},
13996 {"fcs", PSR_f
| PSR_c
| PSR_s
},
13997 {"fcx", PSR_f
| PSR_c
| PSR_x
},
13998 {"sfx", PSR_s
| PSR_f
| PSR_x
},
13999 {"sfc", PSR_s
| PSR_f
| PSR_c
},
14000 {"sxf", PSR_s
| PSR_x
| PSR_f
},
14001 {"sxc", PSR_s
| PSR_x
| PSR_c
},
14002 {"scf", PSR_s
| PSR_c
| PSR_f
},
14003 {"scx", PSR_s
| PSR_c
| PSR_x
},
14004 {"xfs", PSR_x
| PSR_f
| PSR_s
},
14005 {"xfc", PSR_x
| PSR_f
| PSR_c
},
14006 {"xsf", PSR_x
| PSR_s
| PSR_f
},
14007 {"xsc", PSR_x
| PSR_s
| PSR_c
},
14008 {"xcf", PSR_x
| PSR_c
| PSR_f
},
14009 {"xcs", PSR_x
| PSR_c
| PSR_s
},
14010 {"cfs", PSR_c
| PSR_f
| PSR_s
},
14011 {"cfx", PSR_c
| PSR_f
| PSR_x
},
14012 {"csf", PSR_c
| PSR_s
| PSR_f
},
14013 {"csx", PSR_c
| PSR_s
| PSR_x
},
14014 {"cxf", PSR_c
| PSR_x
| PSR_f
},
14015 {"cxs", PSR_c
| PSR_x
| PSR_s
},
14016 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
14017 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
14018 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
14019 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
14020 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
14021 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
14022 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
14023 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
14024 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
14025 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
14026 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
14027 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
14028 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
14029 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
14030 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
14031 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
14032 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
14033 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
14034 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
14035 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
14036 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
14037 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
14038 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
14039 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
14042 /* Table of V7M psr names. */
14043 static const struct asm_psr v7m_psrs
[] =
14056 {"basepri_max", 18},
14061 /* Table of all shift-in-operand names. */
14062 static const struct asm_shift_name shift_names
[] =
14064 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
14065 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
14066 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
14067 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
14068 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
14069 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
14072 /* Table of all explicit relocation names. */
14074 static struct reloc_entry reloc_names
[] =
14076 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
14077 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
14078 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
14079 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
14080 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
14081 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
14082 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
14083 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
14084 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
14085 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
14086 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
14090 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
14091 static const struct asm_cond conds
[] =
14095 {"cs", 0x2}, {"hs", 0x2},
14096 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
14110 static struct asm_barrier_opt barrier_opt_names
[] =
14118 /* Table of ARM-format instructions. */
14120 /* Macros for gluing together operand strings. N.B. In all cases
14121 other than OPS0, the trailing OP_stop comes from default
14122 zero-initialization of the unspecified elements of the array. */
14123 #define OPS0() { OP_stop, }
14124 #define OPS1(a) { OP_##a, }
14125 #define OPS2(a,b) { OP_##a,OP_##b, }
14126 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
14127 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
14128 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
14129 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
14131 /* These macros abstract out the exact format of the mnemonic table and
14132 save some repeated characters. */
14134 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
14135 #define TxCE(mnem, op, top, nops, ops, ae, te) \
14136 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
14137 THUMB_VARIANT, do_##ae, do_##te }
14139 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
14140 a T_MNEM_xyz enumerator. */
14141 #define TCE(mnem, aop, top, nops, ops, ae, te) \
14142 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
14143 #define tCE(mnem, aop, top, nops, ops, ae, te) \
14144 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14146 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
14147 infix after the third character. */
14148 #define TxC3(mnem, op, top, nops, ops, ae, te) \
14149 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
14150 THUMB_VARIANT, do_##ae, do_##te }
14151 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
14152 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
14153 THUMB_VARIANT, do_##ae, do_##te }
14154 #define TC3(mnem, aop, top, nops, ops, ae, te) \
14155 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
14156 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
14157 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
14158 #define tC3(mnem, aop, top, nops, ops, ae, te) \
14159 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14160 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
14161 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14163 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
14164 appear in the condition table. */
14165 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
14166 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14167 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
14169 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
14170 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
14171 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
14172 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
14173 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
14174 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
14175 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
14176 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
14177 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
14178 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
14179 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
14180 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
14181 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
14182 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
14183 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
14184 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
14185 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
14186 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
14187 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
14188 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
14190 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
14191 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
14192 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
14193 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
14195 /* Mnemonic that cannot be conditionalized. The ARM condition-code
14196 field is still 0xE. Many of the Thumb variants can be executed
14197 conditionally, so this is checked separately. */
14198 #define TUE(mnem, op, top, nops, ops, ae, te) \
14199 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
14200 THUMB_VARIANT, do_##ae, do_##te }
14202 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
14203 condition code field. */
14204 #define TUF(mnem, op, top, nops, ops, ae, te) \
14205 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
14206 THUMB_VARIANT, do_##ae, do_##te }
14208 /* ARM-only variants of all the above. */
14209 #define CE(mnem, op, nops, ops, ae) \
14210 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14212 #define C3(mnem, op, nops, ops, ae) \
14213 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14215 /* Legacy mnemonics that always have conditional infix after the third
14217 #define CL(mnem, op, nops, ops, ae) \
14218 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14219 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14221 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
14222 #define cCE(mnem, op, nops, ops, ae) \
14223 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14225 /* Legacy coprocessor instructions where conditional infix and conditional
14226 suffix are ambiguous. For consistency this includes all FPA instructions,
14227 not just the potentially ambiguous ones. */
14228 #define cCL(mnem, op, nops, ops, ae) \
14229 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14230 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14232 /* Coprocessor, takes either a suffix or a position-3 infix
14233 (for an FPA corner case). */
14234 #define C3E(mnem, op, nops, ops, ae) \
14235 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
14236 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14238 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
14239 { #m1 #m2 #m3, OPS##nops ops, \
14240 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14241 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14243 #define CM(m1, m2, op, nops, ops, ae) \
14244 xCM_(m1, , m2, op, nops, ops, ae), \
14245 xCM_(m1, eq, m2, op, nops, ops, ae), \
14246 xCM_(m1, ne, m2, op, nops, ops, ae), \
14247 xCM_(m1, cs, m2, op, nops, ops, ae), \
14248 xCM_(m1, hs, m2, op, nops, ops, ae), \
14249 xCM_(m1, cc, m2, op, nops, ops, ae), \
14250 xCM_(m1, ul, m2, op, nops, ops, ae), \
14251 xCM_(m1, lo, m2, op, nops, ops, ae), \
14252 xCM_(m1, mi, m2, op, nops, ops, ae), \
14253 xCM_(m1, pl, m2, op, nops, ops, ae), \
14254 xCM_(m1, vs, m2, op, nops, ops, ae), \
14255 xCM_(m1, vc, m2, op, nops, ops, ae), \
14256 xCM_(m1, hi, m2, op, nops, ops, ae), \
14257 xCM_(m1, ls, m2, op, nops, ops, ae), \
14258 xCM_(m1, ge, m2, op, nops, ops, ae), \
14259 xCM_(m1, lt, m2, op, nops, ops, ae), \
14260 xCM_(m1, gt, m2, op, nops, ops, ae), \
14261 xCM_(m1, le, m2, op, nops, ops, ae), \
14262 xCM_(m1, al, m2, op, nops, ops, ae)
14264 #define UE(mnem, op, nops, ops, ae) \
14265 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14267 #define UF(mnem, op, nops, ops, ae) \
14268 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14270 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
14271 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
14272 use the same encoding function for each. */
14273 #define NUF(mnem, op, nops, ops, enc) \
14274 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
14275 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14277 /* Neon data processing, version which indirects through neon_enc_tab for
14278 the various overloaded versions of opcodes. */
14279 #define nUF(mnem, op, nops, ops, enc) \
14280 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \
14281 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14283 /* Neon insn with conditional suffix for the ARM version, non-overloaded
14285 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
14286 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
14287 THUMB_VARIANT, do_##enc, do_##enc }
14289 #define NCE(mnem, op, nops, ops, enc) \
14290 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14292 #define NCEF(mnem, op, nops, ops, enc) \
14293 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14295 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
14296 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
14297 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \
14298 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14300 #define nCE(mnem, op, nops, ops, enc) \
14301 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14303 #define nCEF(mnem, op, nops, ops, enc) \
14304 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14308 /* Thumb-only, unconditional. */
14309 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
14311 static const struct asm_opcode insns
[] =
14313 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
14314 #define THUMB_VARIANT &arm_ext_v4t
14315 tCE(and, 0000000, and, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14316 tC3(ands
, 0100000, ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14317 tCE(eor
, 0200000, eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14318 tC3(eors
, 0300000, eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14319 tCE(sub
, 0400000, sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14320 tC3(subs
, 0500000, subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14321 tCE(add
, 0800000, add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14322 tC3(adds
, 0900000, adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14323 tCE(adc
, 0a00000
, adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14324 tC3(adcs
, 0b00000, adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14325 tCE(sbc
, 0c00000
, sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14326 tC3(sbcs
, 0d00000
, sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14327 tCE(orr
, 1800000, orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14328 tC3(orrs
, 1900000, orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14329 tCE(bic
, 1c00000
, bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14330 tC3(bics
, 1d00000
, bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14332 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
14333 for setting PSR flag bits. They are obsolete in V6 and do not
14334 have Thumb equivalents. */
14335 tCE(tst
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14336 tC3w(tsts
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14337 CL(tstp
, 110f000
, 2, (RR
, SH
), cmp
),
14338 tCE(cmp
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14339 tC3w(cmps
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14340 CL(cmpp
, 150f000
, 2, (RR
, SH
), cmp
),
14341 tCE(cmn
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14342 tC3w(cmns
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14343 CL(cmnp
, 170f000
, 2, (RR
, SH
), cmp
),
14345 tCE(mov
, 1a00000
, mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14346 tC3(movs
, 1b00000
, movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14347 tCE(mvn
, 1e00000
, mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14348 tC3(mvns
, 1f00000
, mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14350 tCE(ldr
, 4100000, ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14351 tC3(ldrb
, 4500000, ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14352 tCE(str
, 4000000, str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14353 tC3(strb
, 4400000, strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14355 tCE(stm
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14356 tC3(stmia
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14357 tC3(stmea
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14358 tCE(ldm
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14359 tC3(ldmia
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14360 tC3(ldmfd
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14362 TCE(swi
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14363 TCE(svc
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14364 tCE(b
, a000000
, b
, 1, (EXPr
), branch
, t_branch
),
14365 TCE(bl
, b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
14368 tCE(adr
, 28f0000
, adr
, 2, (RR
, EXP
), adr
, t_adr
),
14369 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
14370 tCE(nop
, 1a00000
, nop
, 1, (oI255c
), nop
, t_nop
),
14372 /* Thumb-compatibility pseudo ops. */
14373 tCE(lsl
, 1a00000
, lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14374 tC3(lsls
, 1b00000
, lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14375 tCE(lsr
, 1a00020
, lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14376 tC3(lsrs
, 1b00020
, lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14377 tCE(asr
, 1a00040
, asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14378 tC3(asrs
, 1b00040
, asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14379 tCE(ror
, 1a00060
, ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14380 tC3(rors
, 1b00060
, rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14381 tCE(neg
, 2600000, neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
14382 tC3(negs
, 2700000, negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
14383 tCE(push
, 92d0000
, push
, 1, (REGLST
), push_pop
, t_push_pop
),
14384 tCE(pop
, 8bd0000
, pop
, 1, (REGLST
), push_pop
, t_push_pop
),
14386 #undef THUMB_VARIANT
14387 #define THUMB_VARIANT &arm_ext_v6
14388 TCE(cpy
, 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
14390 /* V1 instructions with no Thumb analogue prior to V6T2. */
14391 #undef THUMB_VARIANT
14392 #define THUMB_VARIANT &arm_ext_v6t2
14393 TCE(rsb
, 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14394 TC3(rsbs
, 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14395 TCE(teq
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14396 TC3w(teqs
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14397 CL(teqp
, 130f000
, 2, (RR
, SH
), cmp
),
14399 TC3(ldrt
, 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14400 TC3(ldrbt
, 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14401 TC3(strt
, 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14402 TC3(strbt
, 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14404 TC3(stmdb
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14405 TC3(stmfd
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14407 TC3(ldmdb
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14408 TC3(ldmea
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14410 /* V1 instructions with no Thumb analogue at all. */
14411 CE(rsc
, 0e00000
, 3, (RR
, oRR
, SH
), arit
),
14412 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
14414 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
14415 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
14416 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
14417 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
14418 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
14419 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
14420 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
14421 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
14424 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
14425 #undef THUMB_VARIANT
14426 #define THUMB_VARIANT &arm_ext_v4t
14427 tCE(mul
, 0000090, mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
14428 tC3(muls
, 0100090, muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
14430 #undef THUMB_VARIANT
14431 #define THUMB_VARIANT &arm_ext_v6t2
14432 TCE(mla
, 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
14433 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
14435 /* Generic coprocessor instructions. */
14436 TCE(cdp
, e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
14437 TCE(ldc
, c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14438 TC3(ldcl
, c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14439 TCE(stc
, c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14440 TC3(stcl
, c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14441 TCE(mcr
, e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14442 TCE(mrc
, e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14445 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
14446 CE(swp
, 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
14447 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
14450 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
14451 TCE(mrs
, 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
14452 TCE(msr
, 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
14455 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
14456 TCE(smull
, 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14457 CM(smull
,s
, 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14458 TCE(umull
, 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14459 CM(umull
,s
, 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14460 TCE(smlal
, 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14461 CM(smlal
,s
, 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14462 TCE(umlal
, 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14463 CM(umlal
,s
, 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14466 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
14467 #undef THUMB_VARIANT
14468 #define THUMB_VARIANT &arm_ext_v4t
14469 tC3(ldrh
, 01000b0
, ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14470 tC3(strh
, 00000b0
, strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14471 tC3(ldrsh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14472 tC3(ldrsb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14473 tCM(ld
,sh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14474 tCM(ld
,sb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14477 #define ARM_VARIANT &arm_ext_v4t_5
14478 /* ARM Architecture 4T. */
14479 /* Note: bx (and blx) are required on V5, even if the processor does
14480 not support Thumb. */
14481 TCE(bx
, 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
14484 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
14485 #undef THUMB_VARIANT
14486 #define THUMB_VARIANT &arm_ext_v5t
14487 /* Note: blx has 2 variants; the .value coded here is for
14488 BLX(2). Only this variant has conditional execution. */
14489 TCE(blx
, 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
14490 TUE(bkpt
, 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
14492 #undef THUMB_VARIANT
14493 #define THUMB_VARIANT &arm_ext_v6t2
14494 TCE(clz
, 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
14495 TUF(ldc2
, c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14496 TUF(ldc2l
, c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14497 TUF(stc2
, c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14498 TUF(stc2l
, c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14499 TUF(cdp2
, e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
14500 TUF(mcr2
, e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14501 TUF(mrc2
, e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14504 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
14505 TCE(smlabb
, 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14506 TCE(smlatb
, 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14507 TCE(smlabt
, 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14508 TCE(smlatt
, 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14510 TCE(smlawb
, 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14511 TCE(smlawt
, 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14513 TCE(smlalbb
, 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14514 TCE(smlaltb
, 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14515 TCE(smlalbt
, 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14516 TCE(smlaltt
, 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14518 TCE(smulbb
, 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14519 TCE(smultb
, 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14520 TCE(smulbt
, 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14521 TCE(smultt
, 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14523 TCE(smulwb
, 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14524 TCE(smulwt
, 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14526 TCE(qadd
, 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14527 TCE(qdadd
, 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14528 TCE(qsub
, 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14529 TCE(qdsub
, 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14532 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
14533 TUF(pld
, 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
14534 TC3(ldrd
, 00000d0
, e9500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
14535 TC3(strd
, 00000f0
, e9400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
14537 TCE(mcrr
, c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14538 TCE(mrrc
, c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14541 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
14542 TCE(bxj
, 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
14545 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
14546 #undef THUMB_VARIANT
14547 #define THUMB_VARIANT &arm_ext_v6
14548 TUF(cpsie
, 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
14549 TUF(cpsid
, 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
14550 tCE(rev
, 6bf0f30
, rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
14551 tCE(rev16
, 6bf0fb0
, rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
14552 tCE(revsh
, 6ff0fb0
, revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
14553 tCE(sxth
, 6bf0070
, sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14554 tCE(uxth
, 6ff0070
, uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14555 tCE(sxtb
, 6af0070
, sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14556 tCE(uxtb
, 6ef0070
, uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14557 TUF(setend
, 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
14559 #undef THUMB_VARIANT
14560 #define THUMB_VARIANT &arm_ext_v6t2
14561 TCE(ldrex
, 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
14562 TUF(mcrr2
, c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14563 TUF(mrrc2
, c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14565 TCE(ssat
, 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
14566 TCE(usat
, 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
14568 /* ARM V6 not included in V7M (eg. integer SIMD). */
14569 #undef THUMB_VARIANT
14570 #define THUMB_VARIANT &arm_ext_v6_notm
14571 TUF(cps
, 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
14572 TCE(pkhbt
, 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
14573 TCE(pkhtb
, 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
14574 TCE(qadd16
, 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14575 TCE(qadd8
, 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14576 TCE(qaddsubx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14577 TCE(qsub16
, 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14578 TCE(qsub8
, 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14579 TCE(qsubaddx
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14580 TCE(sadd16
, 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14581 TCE(sadd8
, 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14582 TCE(saddsubx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14583 TCE(shadd16
, 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14584 TCE(shadd8
, 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14585 TCE(shaddsubx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14586 TCE(shsub16
, 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14587 TCE(shsub8
, 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14588 TCE(shsubaddx
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14589 TCE(ssub16
, 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14590 TCE(ssub8
, 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14591 TCE(ssubaddx
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14592 TCE(uadd16
, 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14593 TCE(uadd8
, 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14594 TCE(uaddsubx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14595 TCE(uhadd16
, 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14596 TCE(uhadd8
, 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14597 TCE(uhaddsubx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14598 TCE(uhsub16
, 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14599 TCE(uhsub8
, 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14600 TCE(uhsubaddx
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14601 TCE(uqadd16
, 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14602 TCE(uqadd8
, 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14603 TCE(uqaddsubx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14604 TCE(uqsub16
, 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14605 TCE(uqsub8
, 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14606 TCE(uqsubaddx
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14607 TCE(usub16
, 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14608 TCE(usub8
, 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14609 TCE(usubaddx
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14610 TUF(rfeia
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
14611 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
14612 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
14613 TUF(rfedb
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
14614 TUF(rfefd
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
14615 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
14616 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
14617 TUF(rfeed
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
14618 TCE(sxtah
, 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14619 TCE(sxtab16
, 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14620 TCE(sxtab
, 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14621 TCE(sxtb16
, 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14622 TCE(uxtah
, 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14623 TCE(uxtab16
, 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14624 TCE(uxtab
, 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14625 TCE(uxtb16
, 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14626 TCE(sel
, 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14627 TCE(smlad
, 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14628 TCE(smladx
, 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14629 TCE(smlald
, 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14630 TCE(smlaldx
, 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14631 TCE(smlsd
, 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14632 TCE(smlsdx
, 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14633 TCE(smlsld
, 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14634 TCE(smlsldx
, 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14635 TCE(smmla
, 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14636 TCE(smmlar
, 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14637 TCE(smmls
, 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14638 TCE(smmlsr
, 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14639 TCE(smmul
, 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14640 TCE(smmulr
, 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14641 TCE(smuad
, 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14642 TCE(smuadx
, 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14643 TCE(smusd
, 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14644 TCE(smusdx
, 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14645 TUF(srsia
, 8cd0500
, e980c000
, 1, (I31w
), srs
, srs
),
14646 UF(srsib
, 9cd0500
, 1, (I31w
), srs
),
14647 UF(srsda
, 84d0500
, 1, (I31w
), srs
),
14648 TUF(srsdb
, 94d0500
, e800c000
, 1, (I31w
), srs
, srs
),
14649 TCE(ssat16
, 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
14650 TCE(strex
, 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
14651 TCE(umaal
, 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
14652 TCE(usad8
, 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14653 TCE(usada8
, 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14654 TCE(usat16
, 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
14657 #define ARM_VARIANT &arm_ext_v6k
14658 #undef THUMB_VARIANT
14659 #define THUMB_VARIANT &arm_ext_v6k
14660 tCE(yield
, 320f001
, yield
, 0, (), noargs
, t_hint
),
14661 tCE(wfe
, 320f002
, wfe
, 0, (), noargs
, t_hint
),
14662 tCE(wfi
, 320f003
, wfi
, 0, (), noargs
, t_hint
),
14663 tCE(sev
, 320f004
, sev
, 0, (), noargs
, t_hint
),
14665 #undef THUMB_VARIANT
14666 #define THUMB_VARIANT &arm_ext_v6_notm
14667 TCE(ldrexd
, 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
14668 TCE(strexd
, 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
14670 #undef THUMB_VARIANT
14671 #define THUMB_VARIANT &arm_ext_v6t2
14672 TCE(ldrexb
, 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
14673 TCE(ldrexh
, 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
14674 TCE(strexb
, 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
14675 TCE(strexh
, 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
14676 TUF(clrex
, 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
14679 #define ARM_VARIANT &arm_ext_v6z
14680 TCE(smc
, 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
14683 #define ARM_VARIANT &arm_ext_v6t2
14684 TCE(bfc
, 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
14685 TCE(bfi
, 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
14686 TCE(sbfx
, 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
14687 TCE(ubfx
, 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
14689 TCE(mls
, 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
14690 TCE(movw
, 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
14691 TCE(movt
, 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
14692 TCE(rbit
, 3ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
14694 TC3(ldrht
, 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
14695 TC3(ldrsht
, 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
14696 TC3(ldrsbt
, 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
14697 TC3(strht
, 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
14699 UT(cbnz
, b900
, 2, (RR
, EXP
), t_czb
),
14700 UT(cbz
, b100
, 2, (RR
, EXP
), t_czb
),
14701 /* ARM does not really have an IT instruction. */
14702 TUE(it
, 0, bf08
, 1, (COND
), it
, t_it
),
14703 TUE(itt
, 0, bf0c
, 1, (COND
), it
, t_it
),
14704 TUE(ite
, 0, bf04
, 1, (COND
), it
, t_it
),
14705 TUE(ittt
, 0, bf0e
, 1, (COND
), it
, t_it
),
14706 TUE(itet
, 0, bf06
, 1, (COND
), it
, t_it
),
14707 TUE(itte
, 0, bf0a
, 1, (COND
), it
, t_it
),
14708 TUE(itee
, 0, bf02
, 1, (COND
), it
, t_it
),
14709 TUE(itttt
, 0, bf0f
, 1, (COND
), it
, t_it
),
14710 TUE(itett
, 0, bf07
, 1, (COND
), it
, t_it
),
14711 TUE(ittet
, 0, bf0b
, 1, (COND
), it
, t_it
),
14712 TUE(iteet
, 0, bf03
, 1, (COND
), it
, t_it
),
14713 TUE(ittte
, 0, bf0d
, 1, (COND
), it
, t_it
),
14714 TUE(itete
, 0, bf05
, 1, (COND
), it
, t_it
),
14715 TUE(ittee
, 0, bf09
, 1, (COND
), it
, t_it
),
14716 TUE(iteee
, 0, bf01
, 1, (COND
), it
, t_it
),
14718 /* Thumb2 only instructions. */
14720 #define ARM_VARIANT NULL
14722 TCE(addw
, 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
14723 TCE(subw
, 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
14724 TCE(tbb
, 0, e8d0f000
, 1, (TB
), 0, t_tb
),
14725 TCE(tbh
, 0, e8d0f010
, 1, (TB
), 0, t_tb
),
14727 /* Thumb-2 hardware division instructions (R and M profiles only). */
14728 #undef THUMB_VARIANT
14729 #define THUMB_VARIANT &arm_ext_div
14730 TCE(sdiv
, 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
14731 TCE(udiv
, 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
14733 /* ARM V7 instructions. */
14735 #define ARM_VARIANT &arm_ext_v7
14736 #undef THUMB_VARIANT
14737 #define THUMB_VARIANT &arm_ext_v7
14738 TUF(pli
, 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
14739 TCE(dbg
, 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
14740 TUF(dmb
, 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
14741 TUF(dsb
, 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
14742 TUF(isb
, 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
14745 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
14746 cCE(wfs
, e200110
, 1, (RR
), rd
),
14747 cCE(rfs
, e300110
, 1, (RR
), rd
),
14748 cCE(wfc
, e400110
, 1, (RR
), rd
),
14749 cCE(rfc
, e500110
, 1, (RR
), rd
),
14751 cCL(ldfs
, c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14752 cCL(ldfd
, c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14753 cCL(ldfe
, c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14754 cCL(ldfp
, c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14756 cCL(stfs
, c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14757 cCL(stfd
, c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14758 cCL(stfe
, c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14759 cCL(stfp
, c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14761 cCL(mvfs
, e008100
, 2, (RF
, RF_IF
), rd_rm
),
14762 cCL(mvfsp
, e008120
, 2, (RF
, RF_IF
), rd_rm
),
14763 cCL(mvfsm
, e008140
, 2, (RF
, RF_IF
), rd_rm
),
14764 cCL(mvfsz
, e008160
, 2, (RF
, RF_IF
), rd_rm
),
14765 cCL(mvfd
, e008180
, 2, (RF
, RF_IF
), rd_rm
),
14766 cCL(mvfdp
, e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
14767 cCL(mvfdm
, e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
14768 cCL(mvfdz
, e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
14769 cCL(mvfe
, e088100
, 2, (RF
, RF_IF
), rd_rm
),
14770 cCL(mvfep
, e088120
, 2, (RF
, RF_IF
), rd_rm
),
14771 cCL(mvfem
, e088140
, 2, (RF
, RF_IF
), rd_rm
),
14772 cCL(mvfez
, e088160
, 2, (RF
, RF_IF
), rd_rm
),
14774 cCL(mnfs
, e108100
, 2, (RF
, RF_IF
), rd_rm
),
14775 cCL(mnfsp
, e108120
, 2, (RF
, RF_IF
), rd_rm
),
14776 cCL(mnfsm
, e108140
, 2, (RF
, RF_IF
), rd_rm
),
14777 cCL(mnfsz
, e108160
, 2, (RF
, RF_IF
), rd_rm
),
14778 cCL(mnfd
, e108180
, 2, (RF
, RF_IF
), rd_rm
),
14779 cCL(mnfdp
, e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
14780 cCL(mnfdm
, e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
14781 cCL(mnfdz
, e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
14782 cCL(mnfe
, e188100
, 2, (RF
, RF_IF
), rd_rm
),
14783 cCL(mnfep
, e188120
, 2, (RF
, RF_IF
), rd_rm
),
14784 cCL(mnfem
, e188140
, 2, (RF
, RF_IF
), rd_rm
),
14785 cCL(mnfez
, e188160
, 2, (RF
, RF_IF
), rd_rm
),
14787 cCL(abss
, e208100
, 2, (RF
, RF_IF
), rd_rm
),
14788 cCL(abssp
, e208120
, 2, (RF
, RF_IF
), rd_rm
),
14789 cCL(abssm
, e208140
, 2, (RF
, RF_IF
), rd_rm
),
14790 cCL(abssz
, e208160
, 2, (RF
, RF_IF
), rd_rm
),
14791 cCL(absd
, e208180
, 2, (RF
, RF_IF
), rd_rm
),
14792 cCL(absdp
, e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
14793 cCL(absdm
, e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
14794 cCL(absdz
, e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
14795 cCL(abse
, e288100
, 2, (RF
, RF_IF
), rd_rm
),
14796 cCL(absep
, e288120
, 2, (RF
, RF_IF
), rd_rm
),
14797 cCL(absem
, e288140
, 2, (RF
, RF_IF
), rd_rm
),
14798 cCL(absez
, e288160
, 2, (RF
, RF_IF
), rd_rm
),
14800 cCL(rnds
, e308100
, 2, (RF
, RF_IF
), rd_rm
),
14801 cCL(rndsp
, e308120
, 2, (RF
, RF_IF
), rd_rm
),
14802 cCL(rndsm
, e308140
, 2, (RF
, RF_IF
), rd_rm
),
14803 cCL(rndsz
, e308160
, 2, (RF
, RF_IF
), rd_rm
),
14804 cCL(rndd
, e308180
, 2, (RF
, RF_IF
), rd_rm
),
14805 cCL(rnddp
, e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
14806 cCL(rnddm
, e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
14807 cCL(rnddz
, e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
14808 cCL(rnde
, e388100
, 2, (RF
, RF_IF
), rd_rm
),
14809 cCL(rndep
, e388120
, 2, (RF
, RF_IF
), rd_rm
),
14810 cCL(rndem
, e388140
, 2, (RF
, RF_IF
), rd_rm
),
14811 cCL(rndez
, e388160
, 2, (RF
, RF_IF
), rd_rm
),
14813 cCL(sqts
, e408100
, 2, (RF
, RF_IF
), rd_rm
),
14814 cCL(sqtsp
, e408120
, 2, (RF
, RF_IF
), rd_rm
),
14815 cCL(sqtsm
, e408140
, 2, (RF
, RF_IF
), rd_rm
),
14816 cCL(sqtsz
, e408160
, 2, (RF
, RF_IF
), rd_rm
),
14817 cCL(sqtd
, e408180
, 2, (RF
, RF_IF
), rd_rm
),
14818 cCL(sqtdp
, e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
14819 cCL(sqtdm
, e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
14820 cCL(sqtdz
, e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
14821 cCL(sqte
, e488100
, 2, (RF
, RF_IF
), rd_rm
),
14822 cCL(sqtep
, e488120
, 2, (RF
, RF_IF
), rd_rm
),
14823 cCL(sqtem
, e488140
, 2, (RF
, RF_IF
), rd_rm
),
14824 cCL(sqtez
, e488160
, 2, (RF
, RF_IF
), rd_rm
),
14826 cCL(logs
, e508100
, 2, (RF
, RF_IF
), rd_rm
),
14827 cCL(logsp
, e508120
, 2, (RF
, RF_IF
), rd_rm
),
14828 cCL(logsm
, e508140
, 2, (RF
, RF_IF
), rd_rm
),
14829 cCL(logsz
, e508160
, 2, (RF
, RF_IF
), rd_rm
),
14830 cCL(logd
, e508180
, 2, (RF
, RF_IF
), rd_rm
),
14831 cCL(logdp
, e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
14832 cCL(logdm
, e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
14833 cCL(logdz
, e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
14834 cCL(loge
, e588100
, 2, (RF
, RF_IF
), rd_rm
),
14835 cCL(logep
, e588120
, 2, (RF
, RF_IF
), rd_rm
),
14836 cCL(logem
, e588140
, 2, (RF
, RF_IF
), rd_rm
),
14837 cCL(logez
, e588160
, 2, (RF
, RF_IF
), rd_rm
),
14839 cCL(lgns
, e608100
, 2, (RF
, RF_IF
), rd_rm
),
14840 cCL(lgnsp
, e608120
, 2, (RF
, RF_IF
), rd_rm
),
14841 cCL(lgnsm
, e608140
, 2, (RF
, RF_IF
), rd_rm
),
14842 cCL(lgnsz
, e608160
, 2, (RF
, RF_IF
), rd_rm
),
14843 cCL(lgnd
, e608180
, 2, (RF
, RF_IF
), rd_rm
),
14844 cCL(lgndp
, e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
14845 cCL(lgndm
, e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
14846 cCL(lgndz
, e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
14847 cCL(lgne
, e688100
, 2, (RF
, RF_IF
), rd_rm
),
14848 cCL(lgnep
, e688120
, 2, (RF
, RF_IF
), rd_rm
),
14849 cCL(lgnem
, e688140
, 2, (RF
, RF_IF
), rd_rm
),
14850 cCL(lgnez
, e688160
, 2, (RF
, RF_IF
), rd_rm
),
14852 cCL(exps
, e708100
, 2, (RF
, RF_IF
), rd_rm
),
14853 cCL(expsp
, e708120
, 2, (RF
, RF_IF
), rd_rm
),
14854 cCL(expsm
, e708140
, 2, (RF
, RF_IF
), rd_rm
),
14855 cCL(expsz
, e708160
, 2, (RF
, RF_IF
), rd_rm
),
14856 cCL(expd
, e708180
, 2, (RF
, RF_IF
), rd_rm
),
14857 cCL(expdp
, e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
14858 cCL(expdm
, e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
14859 cCL(expdz
, e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
14860 cCL(expe
, e788100
, 2, (RF
, RF_IF
), rd_rm
),
14861 cCL(expep
, e788120
, 2, (RF
, RF_IF
), rd_rm
),
14862 cCL(expem
, e788140
, 2, (RF
, RF_IF
), rd_rm
),
14863 cCL(expdz
, e788160
, 2, (RF
, RF_IF
), rd_rm
),
14865 cCL(sins
, e808100
, 2, (RF
, RF_IF
), rd_rm
),
14866 cCL(sinsp
, e808120
, 2, (RF
, RF_IF
), rd_rm
),
14867 cCL(sinsm
, e808140
, 2, (RF
, RF_IF
), rd_rm
),
14868 cCL(sinsz
, e808160
, 2, (RF
, RF_IF
), rd_rm
),
14869 cCL(sind
, e808180
, 2, (RF
, RF_IF
), rd_rm
),
14870 cCL(sindp
, e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
14871 cCL(sindm
, e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
14872 cCL(sindz
, e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
14873 cCL(sine
, e888100
, 2, (RF
, RF_IF
), rd_rm
),
14874 cCL(sinep
, e888120
, 2, (RF
, RF_IF
), rd_rm
),
14875 cCL(sinem
, e888140
, 2, (RF
, RF_IF
), rd_rm
),
14876 cCL(sinez
, e888160
, 2, (RF
, RF_IF
), rd_rm
),
14878 cCL(coss
, e908100
, 2, (RF
, RF_IF
), rd_rm
),
14879 cCL(cossp
, e908120
, 2, (RF
, RF_IF
), rd_rm
),
14880 cCL(cossm
, e908140
, 2, (RF
, RF_IF
), rd_rm
),
14881 cCL(cossz
, e908160
, 2, (RF
, RF_IF
), rd_rm
),
14882 cCL(cosd
, e908180
, 2, (RF
, RF_IF
), rd_rm
),
14883 cCL(cosdp
, e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
14884 cCL(cosdm
, e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
14885 cCL(cosdz
, e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
14886 cCL(cose
, e988100
, 2, (RF
, RF_IF
), rd_rm
),
14887 cCL(cosep
, e988120
, 2, (RF
, RF_IF
), rd_rm
),
14888 cCL(cosem
, e988140
, 2, (RF
, RF_IF
), rd_rm
),
14889 cCL(cosez
, e988160
, 2, (RF
, RF_IF
), rd_rm
),
14891 cCL(tans
, ea08100
, 2, (RF
, RF_IF
), rd_rm
),
14892 cCL(tansp
, ea08120
, 2, (RF
, RF_IF
), rd_rm
),
14893 cCL(tansm
, ea08140
, 2, (RF
, RF_IF
), rd_rm
),
14894 cCL(tansz
, ea08160
, 2, (RF
, RF_IF
), rd_rm
),
14895 cCL(tand
, ea08180
, 2, (RF
, RF_IF
), rd_rm
),
14896 cCL(tandp
, ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
14897 cCL(tandm
, ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
14898 cCL(tandz
, ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
14899 cCL(tane
, ea88100
, 2, (RF
, RF_IF
), rd_rm
),
14900 cCL(tanep
, ea88120
, 2, (RF
, RF_IF
), rd_rm
),
14901 cCL(tanem
, ea88140
, 2, (RF
, RF_IF
), rd_rm
),
14902 cCL(tanez
, ea88160
, 2, (RF
, RF_IF
), rd_rm
),
14904 cCL(asns
, eb08100
, 2, (RF
, RF_IF
), rd_rm
),
14905 cCL(asnsp
, eb08120
, 2, (RF
, RF_IF
), rd_rm
),
14906 cCL(asnsm
, eb08140
, 2, (RF
, RF_IF
), rd_rm
),
14907 cCL(asnsz
, eb08160
, 2, (RF
, RF_IF
), rd_rm
),
14908 cCL(asnd
, eb08180
, 2, (RF
, RF_IF
), rd_rm
),
14909 cCL(asndp
, eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
14910 cCL(asndm
, eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
14911 cCL(asndz
, eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
14912 cCL(asne
, eb88100
, 2, (RF
, RF_IF
), rd_rm
),
14913 cCL(asnep
, eb88120
, 2, (RF
, RF_IF
), rd_rm
),
14914 cCL(asnem
, eb88140
, 2, (RF
, RF_IF
), rd_rm
),
14915 cCL(asnez
, eb88160
, 2, (RF
, RF_IF
), rd_rm
),
14917 cCL(acss
, ec08100
, 2, (RF
, RF_IF
), rd_rm
),
14918 cCL(acssp
, ec08120
, 2, (RF
, RF_IF
), rd_rm
),
14919 cCL(acssm
, ec08140
, 2, (RF
, RF_IF
), rd_rm
),
14920 cCL(acssz
, ec08160
, 2, (RF
, RF_IF
), rd_rm
),
14921 cCL(acsd
, ec08180
, 2, (RF
, RF_IF
), rd_rm
),
14922 cCL(acsdp
, ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
14923 cCL(acsdm
, ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
14924 cCL(acsdz
, ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
14925 cCL(acse
, ec88100
, 2, (RF
, RF_IF
), rd_rm
),
14926 cCL(acsep
, ec88120
, 2, (RF
, RF_IF
), rd_rm
),
14927 cCL(acsem
, ec88140
, 2, (RF
, RF_IF
), rd_rm
),
14928 cCL(acsez
, ec88160
, 2, (RF
, RF_IF
), rd_rm
),
14930 cCL(atns
, ed08100
, 2, (RF
, RF_IF
), rd_rm
),
14931 cCL(atnsp
, ed08120
, 2, (RF
, RF_IF
), rd_rm
),
14932 cCL(atnsm
, ed08140
, 2, (RF
, RF_IF
), rd_rm
),
14933 cCL(atnsz
, ed08160
, 2, (RF
, RF_IF
), rd_rm
),
14934 cCL(atnd
, ed08180
, 2, (RF
, RF_IF
), rd_rm
),
14935 cCL(atndp
, ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
14936 cCL(atndm
, ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
14937 cCL(atndz
, ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
14938 cCL(atne
, ed88100
, 2, (RF
, RF_IF
), rd_rm
),
14939 cCL(atnep
, ed88120
, 2, (RF
, RF_IF
), rd_rm
),
14940 cCL(atnem
, ed88140
, 2, (RF
, RF_IF
), rd_rm
),
14941 cCL(atnez
, ed88160
, 2, (RF
, RF_IF
), rd_rm
),
14943 cCL(urds
, ee08100
, 2, (RF
, RF_IF
), rd_rm
),
14944 cCL(urdsp
, ee08120
, 2, (RF
, RF_IF
), rd_rm
),
14945 cCL(urdsm
, ee08140
, 2, (RF
, RF_IF
), rd_rm
),
14946 cCL(urdsz
, ee08160
, 2, (RF
, RF_IF
), rd_rm
),
14947 cCL(urdd
, ee08180
, 2, (RF
, RF_IF
), rd_rm
),
14948 cCL(urddp
, ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
14949 cCL(urddm
, ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
14950 cCL(urddz
, ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
14951 cCL(urde
, ee88100
, 2, (RF
, RF_IF
), rd_rm
),
14952 cCL(urdep
, ee88120
, 2, (RF
, RF_IF
), rd_rm
),
14953 cCL(urdem
, ee88140
, 2, (RF
, RF_IF
), rd_rm
),
14954 cCL(urdez
, ee88160
, 2, (RF
, RF_IF
), rd_rm
),
14956 cCL(nrms
, ef08100
, 2, (RF
, RF_IF
), rd_rm
),
14957 cCL(nrmsp
, ef08120
, 2, (RF
, RF_IF
), rd_rm
),
14958 cCL(nrmsm
, ef08140
, 2, (RF
, RF_IF
), rd_rm
),
14959 cCL(nrmsz
, ef08160
, 2, (RF
, RF_IF
), rd_rm
),
14960 cCL(nrmd
, ef08180
, 2, (RF
, RF_IF
), rd_rm
),
14961 cCL(nrmdp
, ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
14962 cCL(nrmdm
, ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
14963 cCL(nrmdz
, ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
14964 cCL(nrme
, ef88100
, 2, (RF
, RF_IF
), rd_rm
),
14965 cCL(nrmep
, ef88120
, 2, (RF
, RF_IF
), rd_rm
),
14966 cCL(nrmem
, ef88140
, 2, (RF
, RF_IF
), rd_rm
),
14967 cCL(nrmez
, ef88160
, 2, (RF
, RF_IF
), rd_rm
),
14969 cCL(adfs
, e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
14970 cCL(adfsp
, e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
14971 cCL(adfsm
, e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
14972 cCL(adfsz
, e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
14973 cCL(adfd
, e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
14974 cCL(adfdp
, e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
14975 cCL(adfdm
, e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
14976 cCL(adfdz
, e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
14977 cCL(adfe
, e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
14978 cCL(adfep
, e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
14979 cCL(adfem
, e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
14980 cCL(adfez
, e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
14982 cCL(sufs
, e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
14983 cCL(sufsp
, e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
14984 cCL(sufsm
, e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
14985 cCL(sufsz
, e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
14986 cCL(sufd
, e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
14987 cCL(sufdp
, e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
14988 cCL(sufdm
, e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
14989 cCL(sufdz
, e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
14990 cCL(sufe
, e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
14991 cCL(sufep
, e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
14992 cCL(sufem
, e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
14993 cCL(sufez
, e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
14995 cCL(rsfs
, e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
14996 cCL(rsfsp
, e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
14997 cCL(rsfsm
, e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
14998 cCL(rsfsz
, e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
14999 cCL(rsfd
, e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15000 cCL(rsfdp
, e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15001 cCL(rsfdm
, e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15002 cCL(rsfdz
, e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15003 cCL(rsfe
, e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15004 cCL(rsfep
, e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15005 cCL(rsfem
, e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15006 cCL(rsfez
, e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15008 cCL(mufs
, e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15009 cCL(mufsp
, e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15010 cCL(mufsm
, e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15011 cCL(mufsz
, e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15012 cCL(mufd
, e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15013 cCL(mufdp
, e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15014 cCL(mufdm
, e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15015 cCL(mufdz
, e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15016 cCL(mufe
, e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15017 cCL(mufep
, e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15018 cCL(mufem
, e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15019 cCL(mufez
, e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15021 cCL(dvfs
, e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15022 cCL(dvfsp
, e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15023 cCL(dvfsm
, e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15024 cCL(dvfsz
, e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15025 cCL(dvfd
, e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15026 cCL(dvfdp
, e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15027 cCL(dvfdm
, e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15028 cCL(dvfdz
, e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15029 cCL(dvfe
, e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15030 cCL(dvfep
, e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15031 cCL(dvfem
, e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15032 cCL(dvfez
, e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15034 cCL(rdfs
, e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15035 cCL(rdfsp
, e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15036 cCL(rdfsm
, e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15037 cCL(rdfsz
, e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15038 cCL(rdfd
, e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15039 cCL(rdfdp
, e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15040 cCL(rdfdm
, e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15041 cCL(rdfdz
, e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15042 cCL(rdfe
, e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15043 cCL(rdfep
, e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15044 cCL(rdfem
, e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15045 cCL(rdfez
, e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15047 cCL(pows
, e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15048 cCL(powsp
, e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15049 cCL(powsm
, e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15050 cCL(powsz
, e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15051 cCL(powd
, e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15052 cCL(powdp
, e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15053 cCL(powdm
, e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15054 cCL(powdz
, e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15055 cCL(powe
, e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15056 cCL(powep
, e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15057 cCL(powem
, e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15058 cCL(powez
, e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15060 cCL(rpws
, e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15061 cCL(rpwsp
, e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15062 cCL(rpwsm
, e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15063 cCL(rpwsz
, e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15064 cCL(rpwd
, e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15065 cCL(rpwdp
, e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15066 cCL(rpwdm
, e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15067 cCL(rpwdz
, e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15068 cCL(rpwe
, e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15069 cCL(rpwep
, e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15070 cCL(rpwem
, e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15071 cCL(rpwez
, e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15073 cCL(rmfs
, e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15074 cCL(rmfsp
, e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15075 cCL(rmfsm
, e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15076 cCL(rmfsz
, e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15077 cCL(rmfd
, e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15078 cCL(rmfdp
, e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15079 cCL(rmfdm
, e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15080 cCL(rmfdz
, e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15081 cCL(rmfe
, e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15082 cCL(rmfep
, e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15083 cCL(rmfem
, e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15084 cCL(rmfez
, e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15086 cCL(fmls
, e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15087 cCL(fmlsp
, e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15088 cCL(fmlsm
, e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15089 cCL(fmlsz
, e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15090 cCL(fmld
, e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15091 cCL(fmldp
, e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15092 cCL(fmldm
, e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15093 cCL(fmldz
, e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15094 cCL(fmle
, e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15095 cCL(fmlep
, e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15096 cCL(fmlem
, e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15097 cCL(fmlez
, e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15099 cCL(fdvs
, ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15100 cCL(fdvsp
, ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15101 cCL(fdvsm
, ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15102 cCL(fdvsz
, ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15103 cCL(fdvd
, ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15104 cCL(fdvdp
, ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15105 cCL(fdvdm
, ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15106 cCL(fdvdz
, ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15107 cCL(fdve
, ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15108 cCL(fdvep
, ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15109 cCL(fdvem
, ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15110 cCL(fdvez
, ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15112 cCL(frds
, eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15113 cCL(frdsp
, eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15114 cCL(frdsm
, eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15115 cCL(frdsz
, eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15116 cCL(frdd
, eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15117 cCL(frddp
, eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15118 cCL(frddm
, eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15119 cCL(frddz
, eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15120 cCL(frde
, eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15121 cCL(frdep
, eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15122 cCL(frdem
, eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15123 cCL(frdez
, eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15125 cCL(pols
, ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15126 cCL(polsp
, ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15127 cCL(polsm
, ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15128 cCL(polsz
, ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15129 cCL(pold
, ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15130 cCL(poldp
, ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15131 cCL(poldm
, ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15132 cCL(poldz
, ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15133 cCL(pole
, ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15134 cCL(polep
, ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15135 cCL(polem
, ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15136 cCL(polez
, ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15138 cCE(cmf
, e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15139 C3E(cmfe
, ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15140 cCE(cnf
, eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15141 C3E(cnfe
, ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15143 cCL(flts
, e000110
, 2, (RF
, RR
), rn_rd
),
15144 cCL(fltsp
, e000130
, 2, (RF
, RR
), rn_rd
),
15145 cCL(fltsm
, e000150
, 2, (RF
, RR
), rn_rd
),
15146 cCL(fltsz
, e000170
, 2, (RF
, RR
), rn_rd
),
15147 cCL(fltd
, e000190
, 2, (RF
, RR
), rn_rd
),
15148 cCL(fltdp
, e0001b0
, 2, (RF
, RR
), rn_rd
),
15149 cCL(fltdm
, e0001d0
, 2, (RF
, RR
), rn_rd
),
15150 cCL(fltdz
, e0001f0
, 2, (RF
, RR
), rn_rd
),
15151 cCL(flte
, e080110
, 2, (RF
, RR
), rn_rd
),
15152 cCL(fltep
, e080130
, 2, (RF
, RR
), rn_rd
),
15153 cCL(fltem
, e080150
, 2, (RF
, RR
), rn_rd
),
15154 cCL(fltez
, e080170
, 2, (RF
, RR
), rn_rd
),
15156 /* The implementation of the FIX instruction is broken on some
15157 assemblers, in that it accepts a precision specifier as well as a
15158 rounding specifier, despite the fact that this is meaningless.
15159 To be more compatible, we accept it as well, though of course it
15160 does not set any bits. */
15161 cCE(fix
, e100110
, 2, (RR
, RF
), rd_rm
),
15162 cCL(fixp
, e100130
, 2, (RR
, RF
), rd_rm
),
15163 cCL(fixm
, e100150
, 2, (RR
, RF
), rd_rm
),
15164 cCL(fixz
, e100170
, 2, (RR
, RF
), rd_rm
),
15165 cCL(fixsp
, e100130
, 2, (RR
, RF
), rd_rm
),
15166 cCL(fixsm
, e100150
, 2, (RR
, RF
), rd_rm
),
15167 cCL(fixsz
, e100170
, 2, (RR
, RF
), rd_rm
),
15168 cCL(fixdp
, e100130
, 2, (RR
, RF
), rd_rm
),
15169 cCL(fixdm
, e100150
, 2, (RR
, RF
), rd_rm
),
15170 cCL(fixdz
, e100170
, 2, (RR
, RF
), rd_rm
),
15171 cCL(fixep
, e100130
, 2, (RR
, RF
), rd_rm
),
15172 cCL(fixem
, e100150
, 2, (RR
, RF
), rd_rm
),
15173 cCL(fixez
, e100170
, 2, (RR
, RF
), rd_rm
),
15175 /* Instructions that were new with the real FPA, call them V2. */
15177 #define ARM_VARIANT &fpu_fpa_ext_v2
15178 cCE(lfm
, c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15179 cCL(lfmfd
, c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15180 cCL(lfmea
, d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15181 cCE(sfm
, c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15182 cCL(sfmfd
, d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15183 cCL(sfmea
, c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15186 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
15187 /* Moves and type conversions. */
15188 cCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15189 cCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
15190 cCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
15191 cCE(fmstat
, ef1fa10
, 0, (), noargs
),
15192 cCE(fsitos
, eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15193 cCE(fuitos
, eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15194 cCE(ftosis
, ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15195 cCE(ftosizs
, ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15196 cCE(ftouis
, ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15197 cCE(ftouizs
, ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15198 cCE(fmrx
, ef00a10
, 2, (RR
, RVC
), rd_rn
),
15199 cCE(fmxr
, ee00a10
, 2, (RVC
, RR
), rn_rd
),
15201 /* Memory operations. */
15202 cCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15203 cCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15204 cCE(fldmias
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15205 cCE(fldmfds
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15206 cCE(fldmdbs
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15207 cCE(fldmeas
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15208 cCE(fldmiax
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15209 cCE(fldmfdx
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15210 cCE(fldmdbx
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15211 cCE(fldmeax
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15212 cCE(fstmias
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15213 cCE(fstmeas
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15214 cCE(fstmdbs
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15215 cCE(fstmfds
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15216 cCE(fstmiax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15217 cCE(fstmeax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15218 cCE(fstmdbx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15219 cCE(fstmfdx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15221 /* Monadic operations. */
15222 cCE(fabss
, eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15223 cCE(fnegs
, eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15224 cCE(fsqrts
, eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15226 /* Dyadic operations. */
15227 cCE(fadds
, e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15228 cCE(fsubs
, e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15229 cCE(fmuls
, e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15230 cCE(fdivs
, e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15231 cCE(fmacs
, e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15232 cCE(fmscs
, e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15233 cCE(fnmuls
, e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15234 cCE(fnmacs
, e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15235 cCE(fnmscs
, e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15238 cCE(fcmps
, eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15239 cCE(fcmpzs
, eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
15240 cCE(fcmpes
, eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15241 cCE(fcmpezs
, eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
15244 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
15245 /* Moves and type conversions. */
15246 cCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15247 cCE(fcvtds
, eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15248 cCE(fcvtsd
, eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15249 cCE(fmdhr
, e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15250 cCE(fmdlr
, e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15251 cCE(fmrdh
, e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15252 cCE(fmrdl
, e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15253 cCE(fsitod
, eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15254 cCE(fuitod
, eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15255 cCE(ftosid
, ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15256 cCE(ftosizd
, ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15257 cCE(ftouid
, ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15258 cCE(ftouizd
, ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15260 /* Memory operations. */
15261 cCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15262 cCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15263 cCE(fldmiad
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15264 cCE(fldmfdd
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15265 cCE(fldmdbd
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15266 cCE(fldmead
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15267 cCE(fstmiad
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15268 cCE(fstmead
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15269 cCE(fstmdbd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15270 cCE(fstmfdd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15272 /* Monadic operations. */
15273 cCE(fabsd
, eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15274 cCE(fnegd
, eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15275 cCE(fsqrtd
, eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15277 /* Dyadic operations. */
15278 cCE(faddd
, e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15279 cCE(fsubd
, e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15280 cCE(fmuld
, e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15281 cCE(fdivd
, e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15282 cCE(fmacd
, e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15283 cCE(fmscd
, e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15284 cCE(fnmuld
, e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15285 cCE(fnmacd
, e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15286 cCE(fnmscd
, e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15289 cCE(fcmpd
, eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15290 cCE(fcmpzd
, eb50b40
, 1, (RVD
), vfp_dp_rd
),
15291 cCE(fcmped
, eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15292 cCE(fcmpezd
, eb50bc0
, 1, (RVD
), vfp_dp_rd
),
15295 #define ARM_VARIANT &fpu_vfp_ext_v2
15296 cCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
15297 cCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
15298 cCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
15299 cCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
15301 /* Instructions which may belong to either the Neon or VFP instruction sets.
15302 Individual encoder functions perform additional architecture checks. */
15304 #define ARM_VARIANT &fpu_vfp_ext_v1xd
15305 #undef THUMB_VARIANT
15306 #define THUMB_VARIANT &fpu_vfp_ext_v1xd
15307 /* These mnemonics are unique to VFP. */
15308 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
15309 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
15310 nCE(vnmul
, vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15311 nCE(vnmla
, vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15312 nCE(vnmls
, vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15313 nCE(vcmp
, vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15314 nCE(vcmpe
, vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15315 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
15316 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
15317 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
15319 /* Mnemonics shared by Neon and VFP. */
15320 nCEF(vmul
, vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
15321 nCEF(vmla
, vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15322 nCEF(vmls
, vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15324 nCEF(vadd
, vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15325 nCEF(vsub
, vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15327 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15328 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15330 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15331 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15332 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15333 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15334 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15335 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15336 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15337 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15339 nCEF(vcvt
, vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
15341 /* NOTE: All VMOV encoding is special-cased! */
15342 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
15343 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
15345 #undef THUMB_VARIANT
15346 #define THUMB_VARIANT &fpu_neon_ext_v1
15348 #define ARM_VARIANT &fpu_neon_ext_v1
15349 /* Data processing with three registers of the same length. */
15350 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
15351 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
15352 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
15353 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15354 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15355 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15356 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15357 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15358 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15359 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
15360 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15361 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15362 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15363 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15364 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15365 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15366 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15367 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15368 /* If not immediate, fall back to neon_dyadic_i64_su.
15369 shl_imm should accept I8 I16 I32 I64,
15370 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
15371 nUF(vshl
, vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
15372 nUF(vshlq
, vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
15373 nUF(vqshl
, vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
15374 nUF(vqshlq
, vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
15375 /* Logic ops, types optional & ignored. */
15376 nUF(vand
, vand
, 2, (RNDQ
, NILO
), neon_logic
),
15377 nUF(vandq
, vand
, 2, (RNQ
, NILO
), neon_logic
),
15378 nUF(vbic
, vbic
, 2, (RNDQ
, NILO
), neon_logic
),
15379 nUF(vbicq
, vbic
, 2, (RNQ
, NILO
), neon_logic
),
15380 nUF(vorr
, vorr
, 2, (RNDQ
, NILO
), neon_logic
),
15381 nUF(vorrq
, vorr
, 2, (RNQ
, NILO
), neon_logic
),
15382 nUF(vorn
, vorn
, 2, (RNDQ
, NILO
), neon_logic
),
15383 nUF(vornq
, vorn
, 2, (RNQ
, NILO
), neon_logic
),
15384 nUF(veor
, veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
15385 nUF(veorq
, veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
15386 /* Bitfield ops, untyped. */
15387 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15388 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15389 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15390 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15391 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15392 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15393 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
15394 nUF(vabd
, vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15395 nUF(vabdq
, vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15396 nUF(vmax
, vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15397 nUF(vmaxq
, vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15398 nUF(vmin
, vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15399 nUF(vminq
, vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15400 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
15401 back to neon_dyadic_if_su. */
15402 nUF(vcge
, vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
15403 nUF(vcgeq
, vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
15404 nUF(vcgt
, vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
15405 nUF(vcgtq
, vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
15406 nUF(vclt
, vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
15407 nUF(vcltq
, vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
15408 nUF(vcle
, vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
15409 nUF(vcleq
, vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
15410 /* Comparison. Type I8 I16 I32 F32. Non-immediate -> neon_dyadic_if_i. */
15411 nUF(vceq
, vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
15412 nUF(vceqq
, vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
15413 /* As above, D registers only. */
15414 nUF(vpmax
, vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
15415 nUF(vpmin
, vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
15416 /* Int and float variants, signedness unimportant. */
15417 /* If not scalar, fall back to neon_dyadic_if_i. */
15418 nUF(vmlaq
, vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
15419 nUF(vmlsq
, vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
15420 nUF(vpadd
, vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
15421 /* Add/sub take types I8 I16 I32 I64 F32. */
15422 nUF(vaddq
, vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
15423 nUF(vsubq
, vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
15424 /* vtst takes sizes 8, 16, 32. */
15425 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
15426 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
15427 /* VMUL takes I8 I16 I32 F32 P8. */
15428 nUF(vmulq
, vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
15429 /* VQD{R}MULH takes S16 S32. */
15430 nUF(vqdmulh
, vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
15431 nUF(vqdmulhq
, vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
15432 nUF(vqrdmulh
, vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
15433 nUF(vqrdmulhq
, vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
15434 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
15435 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
15436 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
15437 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
15438 NUF(vaclt
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
15439 NUF(vacltq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
15440 NUF(vacle
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
15441 NUF(vacleq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
15442 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
15443 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
15444 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
15445 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
15447 /* Two address, int/float. Types S8 S16 S32 F32. */
15448 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
15449 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
15451 /* Data processing with two registers and a shift amount. */
15452 /* Right shifts, and variants with rounding.
15453 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
15454 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
15455 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
15456 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
15457 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
15458 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
15459 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
15460 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
15461 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
15462 /* Shift and insert. Sizes accepted 8 16 32 64. */
15463 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
15464 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
15465 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
15466 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
15467 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
15468 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
15469 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
15470 /* Right shift immediate, saturating & narrowing, with rounding variants.
15471 Types accepted S16 S32 S64 U16 U32 U64. */
15472 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
15473 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
15474 /* As above, unsigned. Types accepted S16 S32 S64. */
15475 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
15476 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
15477 /* Right shift narrowing. Types accepted I16 I32 I64. */
15478 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
15479 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
15480 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
15481 nUF(vshll
, vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
15482 /* CVT with optional immediate for fixed-point variant. */
15483 nUF(vcvtq
, vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
15485 nUF(vmvn
, vmvn
, 2, (RNDQ
, RNDQ_IMVNb
), neon_mvn
),
15486 nUF(vmvnq
, vmvn
, 2, (RNQ
, RNDQ_IMVNb
), neon_mvn
),
15488 /* Data processing, three registers of different lengths. */
15489 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
15490 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
15491 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
15492 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
15493 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
15494 /* If not scalar, fall back to neon_dyadic_long.
15495 Vector types as above, scalar types S16 S32 U16 U32. */
15496 nUF(vmlal
, vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
15497 nUF(vmlsl
, vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
15498 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
15499 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
15500 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
15501 /* Dyadic, narrowing insns. Types I16 I32 I64. */
15502 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15503 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15504 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15505 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15506 /* Saturating doubling multiplies. Types S16 S32. */
15507 nUF(vqdmlal
, vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
15508 nUF(vqdmlsl
, vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
15509 nUF(vqdmull
, vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
15510 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
15511 S16 S32 U16 U32. */
15512 nUF(vmull
, vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
15514 /* Extract. Size 8. */
15515 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I7
), neon_ext
),
15516 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I7
), neon_ext
),
15518 /* Two registers, miscellaneous. */
15519 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
15520 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
15521 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
15522 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
15523 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
15524 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
15525 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
15526 /* Vector replicate. Sizes 8 16 32. */
15527 nCE(vdup
, vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
15528 nCE(vdupq
, vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
15529 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
15530 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
15531 /* VMOVN. Types I16 I32 I64. */
15532 nUF(vmovn
, vmovn
, 2, (RND
, RNQ
), neon_movn
),
15533 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
15534 nUF(vqmovn
, vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
15535 /* VQMOVUN. Types S16 S32 S64. */
15536 nUF(vqmovun
, vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
15537 /* VZIP / VUZP. Sizes 8 16 32. */
15538 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
15539 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
15540 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
15541 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
15542 /* VQABS / VQNEG. Types S8 S16 S32. */
15543 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
15544 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
15545 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
15546 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
15547 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
15548 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
15549 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
15550 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
15551 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
15552 /* Reciprocal estimates. Types U32 F32. */
15553 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
15554 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
15555 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
15556 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
15557 /* VCLS. Types S8 S16 S32. */
15558 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
15559 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
15560 /* VCLZ. Types I8 I16 I32. */
15561 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
15562 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
15563 /* VCNT. Size 8. */
15564 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
15565 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
15566 /* Two address, untyped. */
15567 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
15568 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
15569 /* VTRN. Sizes 8 16 32. */
15570 nUF(vtrn
, vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
15571 nUF(vtrnq
, vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
15573 /* Table lookup. Size 8. */
15574 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
15575 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
15577 #undef THUMB_VARIANT
15578 #define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
15580 #define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
15581 /* Neon element/structure load/store. */
15582 nUF(vld1
, vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15583 nUF(vst1
, vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15584 nUF(vld2
, vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15585 nUF(vst2
, vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15586 nUF(vld3
, vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15587 nUF(vst3
, vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15588 nUF(vld4
, vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15589 nUF(vst4
, vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15591 #undef THUMB_VARIANT
15592 #define THUMB_VARIANT &fpu_vfp_ext_v3
15594 #define ARM_VARIANT &fpu_vfp_ext_v3
15595 cCE(fconsts
, eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
15596 cCE(fconstd
, eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
15597 cCE(fshtos
, eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15598 cCE(fshtod
, eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15599 cCE(fsltos
, eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15600 cCE(fsltod
, eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15601 cCE(fuhtos
, ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15602 cCE(fuhtod
, ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15603 cCE(fultos
, ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15604 cCE(fultod
, ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15605 cCE(ftoshs
, ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15606 cCE(ftoshd
, ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15607 cCE(ftosls
, ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15608 cCE(ftosld
, ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15609 cCE(ftouhs
, ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15610 cCE(ftouhd
, ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15611 cCE(ftouls
, ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15612 cCE(ftould
, ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15614 #undef THUMB_VARIANT
15616 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
15617 cCE(mia
, e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15618 cCE(miaph
, e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15619 cCE(miabb
, e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15620 cCE(miabt
, e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15621 cCE(miatb
, e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15622 cCE(miatt
, e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15623 cCE(mar
, c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
15624 cCE(mra
, c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
15627 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
15628 cCE(tandcb
, e13f130
, 1, (RR
), iwmmxt_tandorc
),
15629 cCE(tandch
, e53f130
, 1, (RR
), iwmmxt_tandorc
),
15630 cCE(tandcw
, e93f130
, 1, (RR
), iwmmxt_tandorc
),
15631 cCE(tbcstb
, e400010
, 2, (RIWR
, RR
), rn_rd
),
15632 cCE(tbcsth
, e400050
, 2, (RIWR
, RR
), rn_rd
),
15633 cCE(tbcstw
, e400090
, 2, (RIWR
, RR
), rn_rd
),
15634 cCE(textrcb
, e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
15635 cCE(textrch
, e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
15636 cCE(textrcw
, e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
15637 cCE(textrmub
, e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15638 cCE(textrmuh
, e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15639 cCE(textrmuw
, e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15640 cCE(textrmsb
, e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15641 cCE(textrmsh
, e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15642 cCE(textrmsw
, e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15643 cCE(tinsrb
, e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
15644 cCE(tinsrh
, e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
15645 cCE(tinsrw
, e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
15646 cCE(tmcr
, e000110
, 2, (RIWC
, RR
), rn_rd
),
15647 cCE(tmcrr
, c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
15648 cCE(tmia
, e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15649 cCE(tmiaph
, e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15650 cCE(tmiabb
, e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15651 cCE(tmiabt
, e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15652 cCE(tmiatb
, e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15653 cCE(tmiatt
, e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15654 cCE(tmovmskb
, e100030
, 2, (RR
, RIWR
), rd_rn
),
15655 cCE(tmovmskh
, e500030
, 2, (RR
, RIWR
), rd_rn
),
15656 cCE(tmovmskw
, e900030
, 2, (RR
, RIWR
), rd_rn
),
15657 cCE(tmrc
, e100110
, 2, (RR
, RIWC
), rd_rn
),
15658 cCE(tmrrc
, c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
15659 cCE(torcb
, e13f150
, 1, (RR
), iwmmxt_tandorc
),
15660 cCE(torch
, e53f150
, 1, (RR
), iwmmxt_tandorc
),
15661 cCE(torcw
, e93f150
, 1, (RR
), iwmmxt_tandorc
),
15662 cCE(waccb
, e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
15663 cCE(wacch
, e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
15664 cCE(waccw
, e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
15665 cCE(waddbss
, e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15666 cCE(waddb
, e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15667 cCE(waddbus
, e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15668 cCE(waddhss
, e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15669 cCE(waddh
, e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15670 cCE(waddhus
, e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15671 cCE(waddwss
, eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15672 cCE(waddw
, e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15673 cCE(waddwus
, e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15674 cCE(waligni
, e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
15675 cCE(walignr0
, e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15676 cCE(walignr1
, e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15677 cCE(walignr2
, ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15678 cCE(walignr3
, eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15679 cCE(wand
, e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15680 cCE(wandn
, e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15681 cCE(wavg2b
, e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15682 cCE(wavg2br
, e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15683 cCE(wavg2h
, ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15684 cCE(wavg2hr
, ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15685 cCE(wcmpeqb
, e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15686 cCE(wcmpeqh
, e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15687 cCE(wcmpeqw
, e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15688 cCE(wcmpgtub
, e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15689 cCE(wcmpgtuh
, e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15690 cCE(wcmpgtuw
, e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15691 cCE(wcmpgtsb
, e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15692 cCE(wcmpgtsh
, e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15693 cCE(wcmpgtsw
, eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15694 cCE(wldrb
, c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
15695 cCE(wldrh
, c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
15696 cCE(wldrw
, c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
15697 cCE(wldrd
, c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
15698 cCE(wmacs
, e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15699 cCE(wmacsz
, e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15700 cCE(wmacu
, e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15701 cCE(wmacuz
, e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15702 cCE(wmadds
, ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15703 cCE(wmaddu
, e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15704 cCE(wmaxsb
, e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15705 cCE(wmaxsh
, e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15706 cCE(wmaxsw
, ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15707 cCE(wmaxub
, e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15708 cCE(wmaxuh
, e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15709 cCE(wmaxuw
, e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15710 cCE(wminsb
, e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15711 cCE(wminsh
, e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15712 cCE(wminsw
, eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15713 cCE(wminub
, e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15714 cCE(wminuh
, e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15715 cCE(wminuw
, e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15716 cCE(wmov
, e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
15717 cCE(wmulsm
, e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15718 cCE(wmulsl
, e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15719 cCE(wmulum
, e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15720 cCE(wmulul
, e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15721 cCE(wor
, e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15722 cCE(wpackhss
, e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15723 cCE(wpackhus
, e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15724 cCE(wpackwss
, eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15725 cCE(wpackwus
, e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15726 cCE(wpackdss
, ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15727 cCE(wpackdus
, ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15728 cCE(wrorh
, e700040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15729 cCE(wrorhg
, e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15730 cCE(wrorw
, eb00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15731 cCE(wrorwg
, eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15732 cCE(wrord
, ef00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15733 cCE(wrordg
, ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15734 cCE(wsadb
, e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15735 cCE(wsadbz
, e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15736 cCE(wsadh
, e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15737 cCE(wsadhz
, e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15738 cCE(wshufh
, e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
15739 cCE(wsllh
, e500040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15740 cCE(wsllhg
, e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15741 cCE(wsllw
, e900040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15742 cCE(wsllwg
, e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15743 cCE(wslld
, ed00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15744 cCE(wslldg
, ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15745 cCE(wsrah
, e400040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15746 cCE(wsrahg
, e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15747 cCE(wsraw
, e800040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15748 cCE(wsrawg
, e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15749 cCE(wsrad
, ec00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15750 cCE(wsradg
, ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15751 cCE(wsrlh
, e600040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15752 cCE(wsrlhg
, e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15753 cCE(wsrlw
, ea00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15754 cCE(wsrlwg
, ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15755 cCE(wsrld
, ee00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15756 cCE(wsrldg
, ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15757 cCE(wstrb
, c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
15758 cCE(wstrh
, c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
15759 cCE(wstrw
, c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
15760 cCE(wstrd
, c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
15761 cCE(wsubbss
, e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15762 cCE(wsubb
, e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15763 cCE(wsubbus
, e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15764 cCE(wsubhss
, e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15765 cCE(wsubh
, e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15766 cCE(wsubhus
, e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15767 cCE(wsubwss
, eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15768 cCE(wsubw
, e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15769 cCE(wsubwus
, e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15770 cCE(wunpckehub
,e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15771 cCE(wunpckehuh
,e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15772 cCE(wunpckehuw
,e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15773 cCE(wunpckehsb
,e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15774 cCE(wunpckehsh
,e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15775 cCE(wunpckehsw
,ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15776 cCE(wunpckihb
, e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15777 cCE(wunpckihh
, e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15778 cCE(wunpckihw
, e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15779 cCE(wunpckelub
,e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15780 cCE(wunpckeluh
,e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15781 cCE(wunpckeluw
,e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15782 cCE(wunpckelsb
,e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15783 cCE(wunpckelsh
,e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15784 cCE(wunpckelsw
,ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15785 cCE(wunpckilb
, e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15786 cCE(wunpckilh
, e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15787 cCE(wunpckilw
, e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15788 cCE(wxor
, e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15789 cCE(wzero
, e300000
, 1, (RIWR
), iwmmxt_wzero
),
15792 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
15793 cCE(cfldrs
, c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
15794 cCE(cfldrd
, c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
15795 cCE(cfldr32
, c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
15796 cCE(cfldr64
, c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
15797 cCE(cfstrs
, c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
15798 cCE(cfstrd
, c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
15799 cCE(cfstr32
, c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
15800 cCE(cfstr64
, c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
15801 cCE(cfmvsr
, e000450
, 2, (RMF
, RR
), rn_rd
),
15802 cCE(cfmvrs
, e100450
, 2, (RR
, RMF
), rd_rn
),
15803 cCE(cfmvdlr
, e000410
, 2, (RMD
, RR
), rn_rd
),
15804 cCE(cfmvrdl
, e100410
, 2, (RR
, RMD
), rd_rn
),
15805 cCE(cfmvdhr
, e000430
, 2, (RMD
, RR
), rn_rd
),
15806 cCE(cfmvrdh
, e100430
, 2, (RR
, RMD
), rd_rn
),
15807 cCE(cfmv64lr
, e000510
, 2, (RMDX
, RR
), rn_rd
),
15808 cCE(cfmvr64l
, e100510
, 2, (RR
, RMDX
), rd_rn
),
15809 cCE(cfmv64hr
, e000530
, 2, (RMDX
, RR
), rn_rd
),
15810 cCE(cfmvr64h
, e100530
, 2, (RR
, RMDX
), rd_rn
),
15811 cCE(cfmval32
, e200440
, 2, (RMAX
, RMFX
), rd_rn
),
15812 cCE(cfmv32al
, e100440
, 2, (RMFX
, RMAX
), rd_rn
),
15813 cCE(cfmvam32
, e200460
, 2, (RMAX
, RMFX
), rd_rn
),
15814 cCE(cfmv32am
, e100460
, 2, (RMFX
, RMAX
), rd_rn
),
15815 cCE(cfmvah32
, e200480
, 2, (RMAX
, RMFX
), rd_rn
),
15816 cCE(cfmv32ah
, e100480
, 2, (RMFX
, RMAX
), rd_rn
),
15817 cCE(cfmva32
, e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
15818 cCE(cfmv32a
, e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
15819 cCE(cfmva64
, e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
15820 cCE(cfmv64a
, e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
15821 cCE(cfmvsc32
, e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
15822 cCE(cfmv32sc
, e1004e0
, 2, (RMDX
, RMDS
), rd
),
15823 cCE(cfcpys
, e000400
, 2, (RMF
, RMF
), rd_rn
),
15824 cCE(cfcpyd
, e000420
, 2, (RMD
, RMD
), rd_rn
),
15825 cCE(cfcvtsd
, e000460
, 2, (RMD
, RMF
), rd_rn
),
15826 cCE(cfcvtds
, e000440
, 2, (RMF
, RMD
), rd_rn
),
15827 cCE(cfcvt32s
, e000480
, 2, (RMF
, RMFX
), rd_rn
),
15828 cCE(cfcvt32d
, e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
15829 cCE(cfcvt64s
, e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
15830 cCE(cfcvt64d
, e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
15831 cCE(cfcvts32
, e100580
, 2, (RMFX
, RMF
), rd_rn
),
15832 cCE(cfcvtd32
, e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
15833 cCE(cftruncs32
,e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
15834 cCE(cftruncd32
,e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
15835 cCE(cfrshl32
, e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
15836 cCE(cfrshl64
, e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
15837 cCE(cfsh32
, e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
15838 cCE(cfsh64
, e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
15839 cCE(cfcmps
, e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
15840 cCE(cfcmpd
, e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
15841 cCE(cfcmp32
, e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
15842 cCE(cfcmp64
, e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
15843 cCE(cfabss
, e300400
, 2, (RMF
, RMF
), rd_rn
),
15844 cCE(cfabsd
, e300420
, 2, (RMD
, RMD
), rd_rn
),
15845 cCE(cfnegs
, e300440
, 2, (RMF
, RMF
), rd_rn
),
15846 cCE(cfnegd
, e300460
, 2, (RMD
, RMD
), rd_rn
),
15847 cCE(cfadds
, e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
15848 cCE(cfaddd
, e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
15849 cCE(cfsubs
, e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
15850 cCE(cfsubd
, e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
15851 cCE(cfmuls
, e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
15852 cCE(cfmuld
, e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
15853 cCE(cfabs32
, e300500
, 2, (RMFX
, RMFX
), rd_rn
),
15854 cCE(cfabs64
, e300520
, 2, (RMDX
, RMDX
), rd_rn
),
15855 cCE(cfneg32
, e300540
, 2, (RMFX
, RMFX
), rd_rn
),
15856 cCE(cfneg64
, e300560
, 2, (RMDX
, RMDX
), rd_rn
),
15857 cCE(cfadd32
, e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15858 cCE(cfadd64
, e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
15859 cCE(cfsub32
, e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15860 cCE(cfsub64
, e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
15861 cCE(cfmul32
, e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15862 cCE(cfmul64
, e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
15863 cCE(cfmac32
, e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15864 cCE(cfmsc32
, e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15865 cCE(cfmadd32
, e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
15866 cCE(cfmsub32
, e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
15867 cCE(cfmadda32
, e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
15868 cCE(cfmsuba32
, e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
15871 #undef THUMB_VARIANT
15898 /* MD interface: bits in the object file. */
15900 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
15901 for use in the a.out file, and stores them in the array pointed to by buf.
15902 This knows about the endian-ness of the target machine and does
15903 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
15904 2 (short) and 4 (long) Floating numbers are put out as a series of
15905 LITTLENUMS (shorts, here at least). */
15908 md_number_to_chars (char * buf
, valueT val
, int n
)
15910 if (target_big_endian
)
15911 number_to_chars_bigendian (buf
, val
, n
);
15913 number_to_chars_littleendian (buf
, val
, n
);
15917 md_chars_to_number (char * buf
, int n
)
15920 unsigned char * where
= (unsigned char *) buf
;
15922 if (target_big_endian
)
15927 result
|= (*where
++ & 255);
15935 result
|= (where
[n
] & 255);
15942 /* MD interface: Sections. */
15944 /* Estimate the size of a frag before relaxing. Assume everything fits in
15948 md_estimate_size_before_relax (fragS
* fragp
,
15949 segT segtype ATTRIBUTE_UNUSED
)
15955 /* Convert a machine dependent frag. */
15958 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
15960 unsigned long insn
;
15961 unsigned long old_op
;
15969 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
15971 old_op
= bfd_get_16(abfd
, buf
);
15972 if (fragp
->fr_symbol
) {
15973 exp
.X_op
= O_symbol
;
15974 exp
.X_add_symbol
= fragp
->fr_symbol
;
15976 exp
.X_op
= O_constant
;
15978 exp
.X_add_number
= fragp
->fr_offset
;
15979 opcode
= fragp
->fr_subtype
;
15982 case T_MNEM_ldr_pc
:
15983 case T_MNEM_ldr_pc2
:
15984 case T_MNEM_ldr_sp
:
15985 case T_MNEM_str_sp
:
15992 if (fragp
->fr_var
== 4)
15994 insn
= THUMB_OP32(opcode
);
15995 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
15997 insn
|= (old_op
& 0x700) << 4;
16001 insn
|= (old_op
& 7) << 12;
16002 insn
|= (old_op
& 0x38) << 13;
16004 insn
|= 0x00000c00;
16005 put_thumb32_insn (buf
, insn
);
16006 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
16010 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
16012 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
16015 if (fragp
->fr_var
== 4)
16017 insn
= THUMB_OP32 (opcode
);
16018 insn
|= (old_op
& 0xf0) << 4;
16019 put_thumb32_insn (buf
, insn
);
16020 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
16024 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16025 exp
.X_add_number
-= 4;
16033 if (fragp
->fr_var
== 4)
16035 int r0off
= (opcode
== T_MNEM_mov
16036 || opcode
== T_MNEM_movs
) ? 0 : 8;
16037 insn
= THUMB_OP32 (opcode
);
16038 insn
= (insn
& 0xe1ffffff) | 0x10000000;
16039 insn
|= (old_op
& 0x700) << r0off
;
16040 put_thumb32_insn (buf
, insn
);
16041 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16045 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
16050 if (fragp
->fr_var
== 4)
16052 insn
= THUMB_OP32(opcode
);
16053 put_thumb32_insn (buf
, insn
);
16054 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
16057 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
16061 if (fragp
->fr_var
== 4)
16063 insn
= THUMB_OP32(opcode
);
16064 insn
|= (old_op
& 0xf00) << 14;
16065 put_thumb32_insn (buf
, insn
);
16066 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
16069 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
16072 case T_MNEM_add_sp
:
16073 case T_MNEM_add_pc
:
16074 case T_MNEM_inc_sp
:
16075 case T_MNEM_dec_sp
:
16076 if (fragp
->fr_var
== 4)
16078 /* ??? Choose between add and addw. */
16079 insn
= THUMB_OP32 (opcode
);
16080 insn
|= (old_op
& 0xf0) << 4;
16081 put_thumb32_insn (buf
, insn
);
16082 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16085 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16093 if (fragp
->fr_var
== 4)
16095 insn
= THUMB_OP32 (opcode
);
16096 insn
|= (old_op
& 0xf0) << 4;
16097 insn
|= (old_op
& 0xf) << 16;
16098 put_thumb32_insn (buf
, insn
);
16099 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16102 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16108 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
16110 fixp
->fx_file
= fragp
->fr_file
;
16111 fixp
->fx_line
= fragp
->fr_line
;
16112 fragp
->fr_fix
+= fragp
->fr_var
;
16115 /* Return the size of a relaxable immediate operand instruction.
16116 SHIFT and SIZE specify the form of the allowable immediate. */
16118 relax_immediate (fragS
*fragp
, int size
, int shift
)
16124 /* ??? Should be able to do better than this. */
16125 if (fragp
->fr_symbol
)
16128 low
= (1 << shift
) - 1;
16129 mask
= (1 << (shift
+ size
)) - (1 << shift
);
16130 offset
= fragp
->fr_offset
;
16131 /* Force misaligned offsets to 32-bit variant. */
16134 if (offset
& ~mask
)
16139 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
16142 relax_adr (fragS
*fragp
, asection
*sec
)
16147 /* Assume worst case for symbols not known to be in the same section. */
16148 if (!S_IS_DEFINED(fragp
->fr_symbol
)
16149 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16152 val
= S_GET_VALUE(fragp
->fr_symbol
) + fragp
->fr_offset
;
16153 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16154 addr
= (addr
+ 4) & ~3;
16155 /* Fix the insn as the 4-byte version if the target address is not
16156 sufficiently aligned. This is prevents an infinite loop when two
16157 instructions have contradictory range/alignment requirements. */
16161 if (val
< 0 || val
> 1020)
16166 /* Return the size of a relaxable add/sub immediate instruction. */
16168 relax_addsub (fragS
*fragp
, asection
*sec
)
16173 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16174 op
= bfd_get_16(sec
->owner
, buf
);
16175 if ((op
& 0xf) == ((op
>> 4) & 0xf))
16176 return relax_immediate (fragp
, 8, 0);
16178 return relax_immediate (fragp
, 3, 0);
16182 /* Return the size of a relaxable branch instruction. BITS is the
16183 size of the offset field in the narrow instruction. */
16186 relax_branch (fragS
*fragp
, asection
*sec
, int bits
)
16192 /* Assume worst case for symbols not known to be in the same section. */
16193 if (!S_IS_DEFINED(fragp
->fr_symbol
)
16194 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16197 val
= S_GET_VALUE(fragp
->fr_symbol
) + fragp
->fr_offset
;
16198 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16201 /* Offset is a signed value *2 */
16203 if (val
>= limit
|| val
< -limit
)
16209 /* Relax a machine dependent frag. This returns the amount by which
16210 the current size of the frag should change. */
16213 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
16218 oldsize
= fragp
->fr_var
;
16219 switch (fragp
->fr_subtype
)
16221 case T_MNEM_ldr_pc2
:
16222 newsize
= relax_adr(fragp
, sec
);
16224 case T_MNEM_ldr_pc
:
16225 case T_MNEM_ldr_sp
:
16226 case T_MNEM_str_sp
:
16227 newsize
= relax_immediate(fragp
, 8, 2);
16231 newsize
= relax_immediate(fragp
, 5, 2);
16235 newsize
= relax_immediate(fragp
, 5, 1);
16239 newsize
= relax_immediate(fragp
, 5, 0);
16242 newsize
= relax_adr(fragp
, sec
);
16248 newsize
= relax_immediate(fragp
, 8, 0);
16251 newsize
= relax_branch(fragp
, sec
, 11);
16254 newsize
= relax_branch(fragp
, sec
, 8);
16256 case T_MNEM_add_sp
:
16257 case T_MNEM_add_pc
:
16258 newsize
= relax_immediate (fragp
, 8, 2);
16260 case T_MNEM_inc_sp
:
16261 case T_MNEM_dec_sp
:
16262 newsize
= relax_immediate (fragp
, 7, 2);
16268 newsize
= relax_addsub (fragp
, sec
);
16275 fragp
->fr_var
= -newsize
;
16276 md_convert_frag (sec
->owner
, sec
, fragp
);
16278 return -(newsize
+ oldsize
);
16280 fragp
->fr_var
= newsize
;
16281 return newsize
- oldsize
;
16284 /* Round up a section size to the appropriate boundary. */
16287 md_section_align (segT segment ATTRIBUTE_UNUSED
,
16293 /* Round all sects to multiple of 4. */
16294 return (size
+ 3) & ~3;
16298 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
16299 of an rs_align_code fragment. */
16302 arm_handle_align (fragS
* fragP
)
16304 static char const arm_noop
[4] = { 0x00, 0x00, 0xa0, 0xe1 };
16305 static char const thumb_noop
[2] = { 0xc0, 0x46 };
16306 static char const arm_bigend_noop
[4] = { 0xe1, 0xa0, 0x00, 0x00 };
16307 static char const thumb_bigend_noop
[2] = { 0x46, 0xc0 };
16309 int bytes
, fix
, noop_size
;
16313 if (fragP
->fr_type
!= rs_align_code
)
16316 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
16317 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
16320 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
16321 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
16323 if (fragP
->tc_frag_data
)
16325 if (target_big_endian
)
16326 noop
= thumb_bigend_noop
;
16329 noop_size
= sizeof (thumb_noop
);
16333 if (target_big_endian
)
16334 noop
= arm_bigend_noop
;
16337 noop_size
= sizeof (arm_noop
);
16340 if (bytes
& (noop_size
- 1))
16342 fix
= bytes
& (noop_size
- 1);
16343 memset (p
, 0, fix
);
16348 while (bytes
>= noop_size
)
16350 memcpy (p
, noop
, noop_size
);
16352 bytes
-= noop_size
;
16356 fragP
->fr_fix
+= fix
;
16357 fragP
->fr_var
= noop_size
;
16360 /* Called from md_do_align. Used to create an alignment
16361 frag in a code section. */
16364 arm_frag_align_code (int n
, int max
)
16368 /* We assume that there will never be a requirement
16369 to support alignments greater than 32 bytes. */
16370 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
16371 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
16373 p
= frag_var (rs_align_code
,
16374 MAX_MEM_FOR_RS_ALIGN_CODE
,
16376 (relax_substateT
) max
,
16383 /* Perform target specific initialisation of a frag. */
16386 arm_init_frag (fragS
* fragP
)
16388 /* Record whether this frag is in an ARM or a THUMB area. */
16389 fragP
->tc_frag_data
= thumb_mode
;
16393 /* When we change sections we need to issue a new mapping symbol. */
16396 arm_elf_change_section (void)
16399 segment_info_type
*seginfo
;
16401 /* Link an unlinked unwind index table section to the .text section. */
16402 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
16403 && elf_linked_to_section (now_seg
) == NULL
)
16404 elf_linked_to_section (now_seg
) = text_section
;
16406 if (!SEG_NORMAL (now_seg
))
16409 flags
= bfd_get_section_flags (stdoutput
, now_seg
);
16411 /* We can ignore sections that only contain debug info. */
16412 if ((flags
& SEC_ALLOC
) == 0)
16415 seginfo
= seg_info (now_seg
);
16416 mapstate
= seginfo
->tc_segment_info_data
.mapstate
;
16417 marked_pr_dependency
= seginfo
->tc_segment_info_data
.marked_pr_dependency
;
16421 arm_elf_section_type (const char * str
, size_t len
)
16423 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
16424 return SHT_ARM_EXIDX
;
16429 /* Code to deal with unwinding tables. */
16431 static void add_unwind_adjustsp (offsetT
);
16433 /* Cenerate and deferred unwind frame offset. */
16436 flush_pending_unwind (void)
16440 offset
= unwind
.pending_offset
;
16441 unwind
.pending_offset
= 0;
16443 add_unwind_adjustsp (offset
);
16446 /* Add an opcode to this list for this function. Two-byte opcodes should
16447 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
16451 add_unwind_opcode (valueT op
, int length
)
16453 /* Add any deferred stack adjustment. */
16454 if (unwind
.pending_offset
)
16455 flush_pending_unwind ();
16457 unwind
.sp_restored
= 0;
16459 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
16461 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
16462 if (unwind
.opcodes
)
16463 unwind
.opcodes
= xrealloc (unwind
.opcodes
,
16464 unwind
.opcode_alloc
);
16466 unwind
.opcodes
= xmalloc (unwind
.opcode_alloc
);
16471 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
16473 unwind
.opcode_count
++;
16477 /* Add unwind opcodes to adjust the stack pointer. */
16480 add_unwind_adjustsp (offsetT offset
)
16484 if (offset
> 0x200)
16486 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
16491 /* Long form: 0xb2, uleb128. */
16492 /* This might not fit in a word so add the individual bytes,
16493 remembering the list is built in reverse order. */
16494 o
= (valueT
) ((offset
- 0x204) >> 2);
16496 add_unwind_opcode (0, 1);
16498 /* Calculate the uleb128 encoding of the offset. */
16502 bytes
[n
] = o
& 0x7f;
16508 /* Add the insn. */
16510 add_unwind_opcode (bytes
[n
- 1], 1);
16511 add_unwind_opcode (0xb2, 1);
16513 else if (offset
> 0x100)
16515 /* Two short opcodes. */
16516 add_unwind_opcode (0x3f, 1);
16517 op
= (offset
- 0x104) >> 2;
16518 add_unwind_opcode (op
, 1);
16520 else if (offset
> 0)
16522 /* Short opcode. */
16523 op
= (offset
- 4) >> 2;
16524 add_unwind_opcode (op
, 1);
16526 else if (offset
< 0)
16529 while (offset
> 0x100)
16531 add_unwind_opcode (0x7f, 1);
16534 op
= ((offset
- 4) >> 2) | 0x40;
16535 add_unwind_opcode (op
, 1);
16539 /* Finish the list of unwind opcodes for this function. */
16541 finish_unwind_opcodes (void)
16545 if (unwind
.fp_used
)
16547 /* Adjust sp as necessary. */
16548 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
16549 flush_pending_unwind ();
16551 /* After restoring sp from the frame pointer. */
16552 op
= 0x90 | unwind
.fp_reg
;
16553 add_unwind_opcode (op
, 1);
16556 flush_pending_unwind ();
16560 /* Start an exception table entry. If idx is nonzero this is an index table
16564 start_unwind_section (const segT text_seg
, int idx
)
16566 const char * text_name
;
16567 const char * prefix
;
16568 const char * prefix_once
;
16569 const char * group_name
;
16573 size_t sec_name_len
;
16580 prefix
= ELF_STRING_ARM_unwind
;
16581 prefix_once
= ELF_STRING_ARM_unwind_once
;
16582 type
= SHT_ARM_EXIDX
;
16586 prefix
= ELF_STRING_ARM_unwind_info
;
16587 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
16588 type
= SHT_PROGBITS
;
16591 text_name
= segment_name (text_seg
);
16592 if (streq (text_name
, ".text"))
16595 if (strncmp (text_name
, ".gnu.linkonce.t.",
16596 strlen (".gnu.linkonce.t.")) == 0)
16598 prefix
= prefix_once
;
16599 text_name
+= strlen (".gnu.linkonce.t.");
16602 prefix_len
= strlen (prefix
);
16603 text_len
= strlen (text_name
);
16604 sec_name_len
= prefix_len
+ text_len
;
16605 sec_name
= xmalloc (sec_name_len
+ 1);
16606 memcpy (sec_name
, prefix
, prefix_len
);
16607 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
16608 sec_name
[prefix_len
+ text_len
] = '\0';
16614 /* Handle COMDAT group. */
16615 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
16617 group_name
= elf_group_name (text_seg
);
16618 if (group_name
== NULL
)
16620 as_bad ("Group section `%s' has no group signature",
16621 segment_name (text_seg
));
16622 ignore_rest_of_line ();
16625 flags
|= SHF_GROUP
;
16629 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
16631 /* Set the setion link for index tables. */
16633 elf_linked_to_section (now_seg
) = text_seg
;
16637 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
16638 personality routine data. Returns zero, or the index table value for
16639 and inline entry. */
16642 create_unwind_entry (int have_data
)
16647 /* The current word of data. */
16649 /* The number of bytes left in this word. */
16652 finish_unwind_opcodes ();
16654 /* Remember the current text section. */
16655 unwind
.saved_seg
= now_seg
;
16656 unwind
.saved_subseg
= now_subseg
;
16658 start_unwind_section (now_seg
, 0);
16660 if (unwind
.personality_routine
== NULL
)
16662 if (unwind
.personality_index
== -2)
16665 as_bad (_("handerdata in cantunwind frame"));
16666 return 1; /* EXIDX_CANTUNWIND. */
16669 /* Use a default personality routine if none is specified. */
16670 if (unwind
.personality_index
== -1)
16672 if (unwind
.opcode_count
> 3)
16673 unwind
.personality_index
= 1;
16675 unwind
.personality_index
= 0;
16678 /* Space for the personality routine entry. */
16679 if (unwind
.personality_index
== 0)
16681 if (unwind
.opcode_count
> 3)
16682 as_bad (_("too many unwind opcodes for personality routine 0"));
16686 /* All the data is inline in the index table. */
16689 while (unwind
.opcode_count
> 0)
16691 unwind
.opcode_count
--;
16692 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
16696 /* Pad with "finish" opcodes. */
16698 data
= (data
<< 8) | 0xb0;
16705 /* We get two opcodes "free" in the first word. */
16706 size
= unwind
.opcode_count
- 2;
16709 /* An extra byte is required for the opcode count. */
16710 size
= unwind
.opcode_count
+ 1;
16712 size
= (size
+ 3) >> 2;
16714 as_bad (_("too many unwind opcodes"));
16716 frag_align (2, 0, 0);
16717 record_alignment (now_seg
, 2);
16718 unwind
.table_entry
= expr_build_dot ();
16720 /* Allocate the table entry. */
16721 ptr
= frag_more ((size
<< 2) + 4);
16722 where
= frag_now_fix () - ((size
<< 2) + 4);
16724 switch (unwind
.personality_index
)
16727 /* ??? Should this be a PLT generating relocation? */
16728 /* Custom personality routine. */
16729 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
16730 BFD_RELOC_ARM_PREL31
);
16735 /* Set the first byte to the number of additional words. */
16740 /* ABI defined personality routines. */
16742 /* Three opcodes bytes are packed into the first word. */
16749 /* The size and first two opcode bytes go in the first word. */
16750 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
16755 /* Should never happen. */
16759 /* Pack the opcodes into words (MSB first), reversing the list at the same
16761 while (unwind
.opcode_count
> 0)
16765 md_number_to_chars (ptr
, data
, 4);
16770 unwind
.opcode_count
--;
16772 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
16775 /* Finish off the last word. */
16778 /* Pad with "finish" opcodes. */
16780 data
= (data
<< 8) | 0xb0;
16782 md_number_to_chars (ptr
, data
, 4);
16787 /* Add an empty descriptor if there is no user-specified data. */
16788 ptr
= frag_more (4);
16789 md_number_to_chars (ptr
, 0, 4);
16795 /* Convert REGNAME to a DWARF-2 register number. */
16798 tc_arm_regname_to_dw2regnum (char *regname
)
16800 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
16808 /* Initialize the DWARF-2 unwind information for this procedure. */
16811 tc_arm_frame_initial_instructions (void)
16813 cfi_add_CFA_def_cfa (REG_SP
, 0);
16815 #endif /* OBJ_ELF */
16818 /* MD interface: Symbol and relocation handling. */
16820 /* Return the address within the segment that a PC-relative fixup is
16821 relative to. For ARM, PC-relative fixups applied to instructions
16822 are generally relative to the location of the fixup plus 8 bytes.
16823 Thumb branches are offset by 4, and Thumb loads relative to PC
16824 require special handling. */
16827 md_pcrel_from_section (fixS
* fixP
, segT seg
)
16829 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
16831 /* If this is pc-relative and we are going to emit a relocation
16832 then we just want to put out any pipeline compensation that the linker
16833 will need. Otherwise we want to use the calculated base.
16834 For WinCE we skip the bias for externals as well, since this
16835 is how the MS ARM-CE assembler behaves and we want to be compatible. */
16837 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
16838 || (arm_force_relocation (fixP
)
16840 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
16845 switch (fixP
->fx_r_type
)
16847 /* PC relative addressing on the Thumb is slightly odd as the
16848 bottom two bits of the PC are forced to zero for the
16849 calculation. This happens *after* application of the
16850 pipeline offset. However, Thumb adrl already adjusts for
16851 this, so we need not do it again. */
16852 case BFD_RELOC_ARM_THUMB_ADD
:
16855 case BFD_RELOC_ARM_THUMB_OFFSET
:
16856 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
16857 case BFD_RELOC_ARM_T32_ADD_PC12
:
16858 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
16859 return (base
+ 4) & ~3;
16861 /* Thumb branches are simply offset by +4. */
16862 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
16863 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
16864 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
16865 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
16866 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
16867 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
16868 case BFD_RELOC_THUMB_PCREL_BLX
:
16871 /* ARM mode branches are offset by +8. However, the Windows CE
16872 loader expects the relocation not to take this into account. */
16873 case BFD_RELOC_ARM_PCREL_BRANCH
:
16874 case BFD_RELOC_ARM_PCREL_CALL
:
16875 case BFD_RELOC_ARM_PCREL_JUMP
:
16876 case BFD_RELOC_ARM_PCREL_BLX
:
16877 case BFD_RELOC_ARM_PLT32
:
16879 /* When handling fixups immediately, because we have already
16880 discovered the value of a symbol, or the address of the frag involved
16881 we must account for the offset by +8, as the OS loader will never see the reloc.
16882 see fixup_segment() in write.c
16883 The S_IS_EXTERNAL test handles the case of global symbols.
16884 Those need the calculated base, not just the pipe compensation the linker will need. */
16886 && fixP
->fx_addsy
!= NULL
16887 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
16888 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
16895 /* ARM mode loads relative to PC are also offset by +8. Unlike
16896 branches, the Windows CE loader *does* expect the relocation
16897 to take this into account. */
16898 case BFD_RELOC_ARM_OFFSET_IMM
:
16899 case BFD_RELOC_ARM_OFFSET_IMM8
:
16900 case BFD_RELOC_ARM_HWLITERAL
:
16901 case BFD_RELOC_ARM_LITERAL
:
16902 case BFD_RELOC_ARM_CP_OFF_IMM
:
16906 /* Other PC-relative relocations are un-offset. */
16912 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
16913 Otherwise we have no need to default values of symbols. */
16916 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
16919 if (name
[0] == '_' && name
[1] == 'G'
16920 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
16924 if (symbol_find (name
))
16925 as_bad ("GOT already in the symbol table");
16927 GOT_symbol
= symbol_new (name
, undefined_section
,
16928 (valueT
) 0, & zero_address_frag
);
16938 /* Subroutine of md_apply_fix. Check to see if an immediate can be
16939 computed as two separate immediate values, added together. We
16940 already know that this value cannot be computed by just one ARM
16943 static unsigned int
16944 validate_immediate_twopart (unsigned int val
,
16945 unsigned int * highpart
)
16950 for (i
= 0; i
< 32; i
+= 2)
16951 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
16957 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
16959 else if (a
& 0xff0000)
16961 if (a
& 0xff000000)
16963 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
16967 assert (a
& 0xff000000);
16968 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
16971 return (a
& 0xff) | (i
<< 7);
16978 validate_offset_imm (unsigned int val
, int hwse
)
16980 if ((hwse
&& val
> 255) || val
> 4095)
16985 /* Subroutine of md_apply_fix. Do those data_ops which can take a
16986 negative immediate constant by altering the instruction. A bit of
16991 by inverting the second operand, and
16994 by negating the second operand. */
16997 negate_data_op (unsigned long * instruction
,
16998 unsigned long value
)
17001 unsigned long negated
, inverted
;
17003 negated
= encode_arm_immediate (-value
);
17004 inverted
= encode_arm_immediate (~value
);
17006 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
17009 /* First negates. */
17010 case OPCODE_SUB
: /* ADD <-> SUB */
17011 new_inst
= OPCODE_ADD
;
17016 new_inst
= OPCODE_SUB
;
17020 case OPCODE_CMP
: /* CMP <-> CMN */
17021 new_inst
= OPCODE_CMN
;
17026 new_inst
= OPCODE_CMP
;
17030 /* Now Inverted ops. */
17031 case OPCODE_MOV
: /* MOV <-> MVN */
17032 new_inst
= OPCODE_MVN
;
17037 new_inst
= OPCODE_MOV
;
17041 case OPCODE_AND
: /* AND <-> BIC */
17042 new_inst
= OPCODE_BIC
;
17047 new_inst
= OPCODE_AND
;
17051 case OPCODE_ADC
: /* ADC <-> SBC */
17052 new_inst
= OPCODE_SBC
;
17057 new_inst
= OPCODE_ADC
;
17061 /* We cannot do anything. */
17066 if (value
== (unsigned) FAIL
)
17069 *instruction
&= OPCODE_MASK
;
17070 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
17074 /* Like negate_data_op, but for Thumb-2. */
17076 static unsigned int
17077 thumb32_negate_data_op (offsetT
*instruction
, offsetT value
)
17081 offsetT negated
, inverted
;
17083 negated
= encode_thumb32_immediate (-value
);
17084 inverted
= encode_thumb32_immediate (~value
);
17086 rd
= (*instruction
>> 8) & 0xf;
17087 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
17090 /* ADD <-> SUB. Includes CMP <-> CMN. */
17091 case T2_OPCODE_SUB
:
17092 new_inst
= T2_OPCODE_ADD
;
17096 case T2_OPCODE_ADD
:
17097 new_inst
= T2_OPCODE_SUB
;
17101 /* ORR <-> ORN. Includes MOV <-> MVN. */
17102 case T2_OPCODE_ORR
:
17103 new_inst
= T2_OPCODE_ORN
;
17107 case T2_OPCODE_ORN
:
17108 new_inst
= T2_OPCODE_ORR
;
17112 /* AND <-> BIC. TST has no inverted equivalent. */
17113 case T2_OPCODE_AND
:
17114 new_inst
= T2_OPCODE_BIC
;
17121 case T2_OPCODE_BIC
:
17122 new_inst
= T2_OPCODE_AND
;
17127 case T2_OPCODE_ADC
:
17128 new_inst
= T2_OPCODE_SBC
;
17132 case T2_OPCODE_SBC
:
17133 new_inst
= T2_OPCODE_ADC
;
17137 /* We cannot do anything. */
17145 *instruction
&= T2_OPCODE_MASK
;
17146 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
17150 /* Read a 32-bit thumb instruction from buf. */
17151 static unsigned long
17152 get_thumb32_insn (char * buf
)
17154 unsigned long insn
;
17155 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
17156 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17162 /* We usually want to set the low bit on the address of thumb function
17163 symbols. In particular .word foo - . should have the low bit set.
17164 Generic code tries to fold the difference of two symbols to
17165 a constant. Prevent this and force a relocation when the first symbols
17166 is a thumb function. */
17168 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
17170 if (op
== O_subtract
17171 && l
->X_op
== O_symbol
17172 && r
->X_op
== O_symbol
17173 && THUMB_IS_FUNC (l
->X_add_symbol
))
17175 l
->X_op
= O_subtract
;
17176 l
->X_op_symbol
= r
->X_add_symbol
;
17177 l
->X_add_number
-= r
->X_add_number
;
17180 /* Process as normal. */
17185 md_apply_fix (fixS
* fixP
,
17189 offsetT value
= * valP
;
17191 unsigned int newimm
;
17192 unsigned long temp
;
17194 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
17196 assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
17198 /* Note whether this will delete the relocation. */
17200 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
17203 /* On a 64-bit host, silently truncate 'value' to 32 bits for
17204 consistency with the behavior on 32-bit hosts. Remember value
17206 value
&= 0xffffffff;
17207 value
^= 0x80000000;
17208 value
-= 0x80000000;
17211 fixP
->fx_addnumber
= value
;
17213 /* Same treatment for fixP->fx_offset. */
17214 fixP
->fx_offset
&= 0xffffffff;
17215 fixP
->fx_offset
^= 0x80000000;
17216 fixP
->fx_offset
-= 0x80000000;
17218 switch (fixP
->fx_r_type
)
17220 case BFD_RELOC_NONE
:
17221 /* This will need to go in the object file. */
17225 case BFD_RELOC_ARM_IMMEDIATE
:
17226 /* We claim that this fixup has been processed here,
17227 even if in fact we generate an error because we do
17228 not have a reloc for it, so tc_gen_reloc will reject it. */
17232 && ! S_IS_DEFINED (fixP
->fx_addsy
))
17234 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17235 _("undefined symbol %s used as an immediate value"),
17236 S_GET_NAME (fixP
->fx_addsy
));
17240 newimm
= encode_arm_immediate (value
);
17241 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17243 /* If the instruction will fail, see if we can fix things up by
17244 changing the opcode. */
17245 if (newimm
== (unsigned int) FAIL
17246 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
17248 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17249 _("invalid constant (%lx) after fixup"),
17250 (unsigned long) value
);
17254 newimm
|= (temp
& 0xfffff000);
17255 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
17258 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
17260 unsigned int highpart
= 0;
17261 unsigned int newinsn
= 0xe1a00000; /* nop. */
17263 newimm
= encode_arm_immediate (value
);
17264 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17266 /* If the instruction will fail, see if we can fix things up by
17267 changing the opcode. */
17268 if (newimm
== (unsigned int) FAIL
17269 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
17271 /* No ? OK - try using two ADD instructions to generate
17273 newimm
= validate_immediate_twopart (value
, & highpart
);
17275 /* Yes - then make sure that the second instruction is
17277 if (newimm
!= (unsigned int) FAIL
)
17279 /* Still No ? Try using a negated value. */
17280 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
17281 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
17282 /* Otherwise - give up. */
17285 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17286 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
17291 /* Replace the first operand in the 2nd instruction (which
17292 is the PC) with the destination register. We have
17293 already added in the PC in the first instruction and we
17294 do not want to do it again. */
17295 newinsn
&= ~ 0xf0000;
17296 newinsn
|= ((newinsn
& 0x0f000) << 4);
17299 newimm
|= (temp
& 0xfffff000);
17300 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
17302 highpart
|= (newinsn
& 0xfffff000);
17303 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
17307 case BFD_RELOC_ARM_OFFSET_IMM
:
17308 if (!fixP
->fx_done
&& seg
->use_rela_p
)
17311 case BFD_RELOC_ARM_LITERAL
:
17317 if (validate_offset_imm (value
, 0) == FAIL
)
17319 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
17320 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17321 _("invalid literal constant: pool needs to be closer"));
17323 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17324 _("bad immediate value for offset (%ld)"),
17329 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17330 newval
&= 0xff7ff000;
17331 newval
|= value
| (sign
? INDEX_UP
: 0);
17332 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17335 case BFD_RELOC_ARM_OFFSET_IMM8
:
17336 case BFD_RELOC_ARM_HWLITERAL
:
17342 if (validate_offset_imm (value
, 1) == FAIL
)
17344 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
17345 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17346 _("invalid literal constant: pool needs to be closer"));
17348 as_bad (_("bad immediate value for half-word offset (%ld)"),
17353 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17354 newval
&= 0xff7ff0f0;
17355 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
17356 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17359 case BFD_RELOC_ARM_T32_OFFSET_U8
:
17360 if (value
< 0 || value
> 1020 || value
% 4 != 0)
17361 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17362 _("bad immediate value for offset (%ld)"), (long) value
);
17365 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
17367 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
17370 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
17371 /* This is a complicated relocation used for all varieties of Thumb32
17372 load/store instruction with immediate offset:
17374 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
17375 *4, optional writeback(W)
17376 (doubleword load/store)
17378 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
17379 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
17380 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
17381 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
17382 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
17384 Uppercase letters indicate bits that are already encoded at
17385 this point. Lowercase letters are our problem. For the
17386 second block of instructions, the secondary opcode nybble
17387 (bits 8..11) is present, and bit 23 is zero, even if this is
17388 a PC-relative operation. */
17389 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17391 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
17393 if ((newval
& 0xf0000000) == 0xe0000000)
17395 /* Doubleword load/store: 8-bit offset, scaled by 4. */
17397 newval
|= (1 << 23);
17400 if (value
% 4 != 0)
17402 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17403 _("offset not a multiple of 4"));
17409 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17410 _("offset out of range"));
17415 else if ((newval
& 0x000f0000) == 0x000f0000)
17417 /* PC-relative, 12-bit offset. */
17419 newval
|= (1 << 23);
17424 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17425 _("offset out of range"));
17430 else if ((newval
& 0x00000100) == 0x00000100)
17432 /* Writeback: 8-bit, +/- offset. */
17434 newval
|= (1 << 9);
17439 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17440 _("offset out of range"));
17445 else if ((newval
& 0x00000f00) == 0x00000e00)
17447 /* T-instruction: positive 8-bit offset. */
17448 if (value
< 0 || value
> 0xff)
17450 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17451 _("offset out of range"));
17459 /* Positive 12-bit or negative 8-bit offset. */
17463 newval
|= (1 << 23);
17473 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17474 _("offset out of range"));
17481 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
17482 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
17485 case BFD_RELOC_ARM_SHIFT_IMM
:
17486 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17487 if (((unsigned long) value
) > 32
17489 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
17491 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17492 _("shift expression is too large"));
17497 /* Shifts of zero must be done as lsl. */
17499 else if (value
== 32)
17501 newval
&= 0xfffff07f;
17502 newval
|= (value
& 0x1f) << 7;
17503 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17506 case BFD_RELOC_ARM_T32_IMMEDIATE
:
17507 case BFD_RELOC_ARM_T32_IMM12
:
17508 case BFD_RELOC_ARM_T32_ADD_PC12
:
17509 /* We claim that this fixup has been processed here,
17510 even if in fact we generate an error because we do
17511 not have a reloc for it, so tc_gen_reloc will reject it. */
17515 && ! S_IS_DEFINED (fixP
->fx_addsy
))
17517 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17518 _("undefined symbol %s used as an immediate value"),
17519 S_GET_NAME (fixP
->fx_addsy
));
17523 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17525 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
17527 /* FUTURE: Implement analogue of negate_data_op for T32. */
17528 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
)
17530 newimm
= encode_thumb32_immediate (value
);
17531 if (newimm
== (unsigned int) FAIL
)
17532 newimm
= thumb32_negate_data_op (&newval
, value
);
17536 /* 12 bit immediate for addw/subw. */
17540 newval
^= 0x00a00000;
17543 newimm
= (unsigned int) FAIL
;
17548 if (newimm
== (unsigned int)FAIL
)
17550 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17551 _("invalid constant (%lx) after fixup"),
17552 (unsigned long) value
);
17556 newval
|= (newimm
& 0x800) << 15;
17557 newval
|= (newimm
& 0x700) << 4;
17558 newval
|= (newimm
& 0x0ff);
17560 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
17561 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
17564 case BFD_RELOC_ARM_SMC
:
17565 if (((unsigned long) value
) > 0xffff)
17566 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17567 _("invalid smc expression"));
17568 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17569 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
17570 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17573 case BFD_RELOC_ARM_SWI
:
17574 if (fixP
->tc_fix_data
!= 0)
17576 if (((unsigned long) value
) > 0xff)
17577 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17578 _("invalid swi expression"));
17579 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17581 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17585 if (((unsigned long) value
) > 0x00ffffff)
17586 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17587 _("invalid swi expression"));
17588 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17590 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17594 case BFD_RELOC_ARM_MULTI
:
17595 if (((unsigned long) value
) > 0xffff)
17596 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17597 _("invalid expression in load/store multiple"));
17598 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
17599 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17603 case BFD_RELOC_ARM_PCREL_CALL
:
17604 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17605 if ((newval
& 0xf0000000) == 0xf0000000)
17609 goto arm_branch_common
;
17611 case BFD_RELOC_ARM_PCREL_JUMP
:
17612 case BFD_RELOC_ARM_PLT32
:
17614 case BFD_RELOC_ARM_PCREL_BRANCH
:
17616 goto arm_branch_common
;
17618 case BFD_RELOC_ARM_PCREL_BLX
:
17621 /* We are going to store value (shifted right by two) in the
17622 instruction, in a 24 bit, signed field. Bits 26 through 32 either
17623 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
17624 also be be clear. */
17626 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17627 _("misaligned branch destination"));
17628 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
17629 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
17630 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17631 _("branch out of range"));
17633 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17635 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17636 newval
|= (value
>> 2) & 0x00ffffff;
17637 /* Set the H bit on BLX instructions. */
17641 newval
|= 0x01000000;
17643 newval
&= ~0x01000000;
17645 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17649 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CZB */
17650 /* CZB can only branch forward. */
17652 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17653 _("branch out of range"));
17655 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17657 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17658 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
17659 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17663 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
17664 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
17665 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17666 _("branch out of range"));
17668 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17670 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17671 newval
|= (value
& 0x1ff) >> 1;
17672 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17676 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
17677 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
17678 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17679 _("branch out of range"));
17681 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17683 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17684 newval
|= (value
& 0xfff) >> 1;
17685 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17689 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
17690 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
17691 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17692 _("conditional branch out of range"));
17694 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17697 addressT S
, J1
, J2
, lo
, hi
;
17699 S
= (value
& 0x00100000) >> 20;
17700 J2
= (value
& 0x00080000) >> 19;
17701 J1
= (value
& 0x00040000) >> 18;
17702 hi
= (value
& 0x0003f000) >> 12;
17703 lo
= (value
& 0x00000ffe) >> 1;
17705 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17706 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17707 newval
|= (S
<< 10) | hi
;
17708 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
17709 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17710 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
17714 case BFD_RELOC_THUMB_PCREL_BLX
:
17715 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
17716 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
17717 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17718 _("branch out of range"));
17720 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
17721 /* For a BLX instruction, make sure that the relocation is rounded up
17722 to a word boundary. This follows the semantics of the instruction
17723 which specifies that bit 1 of the target address will come from bit
17724 1 of the base address. */
17725 value
= (value
+ 1) & ~ 1;
17727 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17731 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17732 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17733 newval
|= (value
& 0x7fffff) >> 12;
17734 newval2
|= (value
& 0xfff) >> 1;
17735 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17736 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
17740 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
17741 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
17742 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17743 _("branch out of range"));
17745 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17748 addressT S
, I1
, I2
, lo
, hi
;
17750 S
= (value
& 0x01000000) >> 24;
17751 I1
= (value
& 0x00800000) >> 23;
17752 I2
= (value
& 0x00400000) >> 22;
17753 hi
= (value
& 0x003ff000) >> 12;
17754 lo
= (value
& 0x00000ffe) >> 1;
17759 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17760 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17761 newval
|= (S
<< 10) | hi
;
17762 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
17763 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17764 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
17769 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17770 md_number_to_chars (buf
, value
, 1);
17774 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17775 md_number_to_chars (buf
, value
, 2);
17779 case BFD_RELOC_ARM_TLS_GD32
:
17780 case BFD_RELOC_ARM_TLS_LE32
:
17781 case BFD_RELOC_ARM_TLS_IE32
:
17782 case BFD_RELOC_ARM_TLS_LDM32
:
17783 case BFD_RELOC_ARM_TLS_LDO32
:
17784 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
17787 case BFD_RELOC_ARM_GOT32
:
17788 case BFD_RELOC_ARM_GOTOFF
:
17789 case BFD_RELOC_ARM_TARGET2
:
17790 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17791 md_number_to_chars (buf
, 0, 4);
17795 case BFD_RELOC_RVA
:
17797 case BFD_RELOC_ARM_TARGET1
:
17798 case BFD_RELOC_ARM_ROSEGREL32
:
17799 case BFD_RELOC_ARM_SBREL32
:
17800 case BFD_RELOC_32_PCREL
:
17801 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17803 /* For WinCE we only do this for pcrel fixups. */
17804 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
17806 md_number_to_chars (buf
, value
, 4);
17810 case BFD_RELOC_ARM_PREL31
:
17811 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17813 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
17814 if ((value
^ (value
>> 1)) & 0x40000000)
17816 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17817 _("rel31 relocation overflow"));
17819 newval
|= value
& 0x7fffffff;
17820 md_number_to_chars (buf
, newval
, 4);
17825 case BFD_RELOC_ARM_CP_OFF_IMM
:
17826 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
17827 if (value
< -1023 || value
> 1023 || (value
& 3))
17828 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17829 _("co-processor offset out of range"));
17834 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
17835 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
17836 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17838 newval
= get_thumb32_insn (buf
);
17839 newval
&= 0xff7fff00;
17840 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
17842 newval
&= ~WRITE_BACK
;
17843 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
17844 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
17845 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17847 put_thumb32_insn (buf
, newval
);
17850 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
17851 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
17852 if (value
< -255 || value
> 255)
17853 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17854 _("co-processor offset out of range"));
17856 goto cp_off_common
;
17858 case BFD_RELOC_ARM_THUMB_OFFSET
:
17859 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17860 /* Exactly what ranges, and where the offset is inserted depends
17861 on the type of instruction, we can establish this from the
17863 switch (newval
>> 12)
17865 case 4: /* PC load. */
17866 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
17867 forced to zero for these loads; md_pcrel_from has already
17868 compensated for this. */
17870 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17871 _("invalid offset, target not word aligned (0x%08lX)"),
17872 (((unsigned long) fixP
->fx_frag
->fr_address
17873 + (unsigned long) fixP
->fx_where
) & ~3)
17874 + (unsigned long) value
);
17876 if (value
& ~0x3fc)
17877 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17878 _("invalid offset, value too big (0x%08lX)"),
17881 newval
|= value
>> 2;
17884 case 9: /* SP load/store. */
17885 if (value
& ~0x3fc)
17886 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17887 _("invalid offset, value too big (0x%08lX)"),
17889 newval
|= value
>> 2;
17892 case 6: /* Word load/store. */
17894 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17895 _("invalid offset, value too big (0x%08lX)"),
17897 newval
|= value
<< 4; /* 6 - 2. */
17900 case 7: /* Byte load/store. */
17902 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17903 _("invalid offset, value too big (0x%08lX)"),
17905 newval
|= value
<< 6;
17908 case 8: /* Halfword load/store. */
17910 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17911 _("invalid offset, value too big (0x%08lX)"),
17913 newval
|= value
<< 5; /* 6 - 1. */
17917 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17918 "Unable to process relocation for thumb opcode: %lx",
17919 (unsigned long) newval
);
17922 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17925 case BFD_RELOC_ARM_THUMB_ADD
:
17926 /* This is a complicated relocation, since we use it for all of
17927 the following immediate relocations:
17931 9bit ADD/SUB SP word-aligned
17932 10bit ADD PC/SP word-aligned
17934 The type of instruction being processed is encoded in the
17941 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17943 int rd
= (newval
>> 4) & 0xf;
17944 int rs
= newval
& 0xf;
17945 int subtract
= !!(newval
& 0x8000);
17947 /* Check for HI regs, only very restricted cases allowed:
17948 Adjusting SP, and using PC or SP to get an address. */
17949 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
17950 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
17951 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17952 _("invalid Hi register with immediate"));
17954 /* If value is negative, choose the opposite instruction. */
17958 subtract
= !subtract
;
17960 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17961 _("immediate value out of range"));
17966 if (value
& ~0x1fc)
17967 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17968 _("invalid immediate for stack address calculation"));
17969 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
17970 newval
|= value
>> 2;
17972 else if (rs
== REG_PC
|| rs
== REG_SP
)
17974 if (subtract
|| value
& ~0x3fc)
17975 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17976 _("invalid immediate for address calculation (value = 0x%08lX)"),
17977 (unsigned long) value
);
17978 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
17980 newval
|= value
>> 2;
17985 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17986 _("immediate value out of range"));
17987 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
17988 newval
|= (rd
<< 8) | value
;
17993 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17994 _("immediate value out of range"));
17995 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
17996 newval
|= rd
| (rs
<< 3) | (value
<< 6);
17999 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18002 case BFD_RELOC_ARM_THUMB_IMM
:
18003 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18004 if (value
< 0 || value
> 255)
18005 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18006 _("invalid immediate: %ld is too large"),
18009 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18012 case BFD_RELOC_ARM_THUMB_SHIFT
:
18013 /* 5bit shift value (0..32). LSL cannot take 32. */
18014 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
18015 temp
= newval
& 0xf800;
18016 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
18017 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18018 _("invalid shift value: %ld"), (long) value
);
18019 /* Shifts of zero must be encoded as LSL. */
18021 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
18022 /* Shifts of 32 are encoded as zero. */
18023 else if (value
== 32)
18025 newval
|= value
<< 6;
18026 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18029 case BFD_RELOC_VTABLE_INHERIT
:
18030 case BFD_RELOC_VTABLE_ENTRY
:
18034 case BFD_RELOC_ARM_MOVW
:
18035 case BFD_RELOC_ARM_MOVT
:
18036 case BFD_RELOC_ARM_THUMB_MOVW
:
18037 case BFD_RELOC_ARM_THUMB_MOVT
:
18038 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18040 /* REL format relocations are limited to a 16-bit addend. */
18041 if (!fixP
->fx_done
)
18043 if (value
< -0x1000 || value
> 0xffff)
18044 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18045 _("offset too big"));
18047 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
18048 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18053 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
18054 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18056 newval
= get_thumb32_insn (buf
);
18057 newval
&= 0xfbf08f00;
18058 newval
|= (value
& 0xf000) << 4;
18059 newval
|= (value
& 0x0800) << 15;
18060 newval
|= (value
& 0x0700) << 4;
18061 newval
|= (value
& 0x00ff);
18062 put_thumb32_insn (buf
, newval
);
18066 newval
= md_chars_to_number (buf
, 4);
18067 newval
&= 0xfff0f000;
18068 newval
|= value
& 0x0fff;
18069 newval
|= (value
& 0xf000) << 4;
18070 md_number_to_chars (buf
, newval
, 4);
18075 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
18076 case BFD_RELOC_ARM_ALU_PC_G0
:
18077 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
18078 case BFD_RELOC_ARM_ALU_PC_G1
:
18079 case BFD_RELOC_ARM_ALU_PC_G2
:
18080 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
18081 case BFD_RELOC_ARM_ALU_SB_G0
:
18082 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
18083 case BFD_RELOC_ARM_ALU_SB_G1
:
18084 case BFD_RELOC_ARM_ALU_SB_G2
:
18085 assert (!fixP
->fx_done
);
18086 if (!seg
->use_rela_p
)
18089 bfd_vma encoded_addend
;
18090 bfd_vma addend_abs
= abs (value
);
18092 /* Check that the absolute value of the addend can be
18093 expressed as an 8-bit constant plus a rotation. */
18094 encoded_addend
= encode_arm_immediate (addend_abs
);
18095 if (encoded_addend
== (unsigned int) FAIL
)
18096 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18097 _("the offset 0x%08lX is not representable"),
18100 /* Extract the instruction. */
18101 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18103 /* If the addend is positive, use an ADD instruction.
18104 Otherwise use a SUB. Take care not to destroy the S bit. */
18105 insn
&= 0xff1fffff;
18111 /* Place the encoded addend into the first 12 bits of the
18113 insn
&= 0xfffff000;
18114 insn
|= encoded_addend
;
18116 /* Update the instruction. */
18117 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18121 case BFD_RELOC_ARM_LDR_PC_G0
:
18122 case BFD_RELOC_ARM_LDR_PC_G1
:
18123 case BFD_RELOC_ARM_LDR_PC_G2
:
18124 case BFD_RELOC_ARM_LDR_SB_G0
:
18125 case BFD_RELOC_ARM_LDR_SB_G1
:
18126 case BFD_RELOC_ARM_LDR_SB_G2
:
18127 assert (!fixP
->fx_done
);
18128 if (!seg
->use_rela_p
)
18131 bfd_vma addend_abs
= abs (value
);
18133 /* Check that the absolute value of the addend can be
18134 encoded in 12 bits. */
18135 if (addend_abs
>= 0x1000)
18136 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18137 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
18140 /* Extract the instruction. */
18141 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18143 /* If the addend is negative, clear bit 23 of the instruction.
18144 Otherwise set it. */
18146 insn
&= ~(1 << 23);
18150 /* Place the absolute value of the addend into the first 12 bits
18151 of the instruction. */
18152 insn
&= 0xfffff000;
18153 insn
|= addend_abs
;
18155 /* Update the instruction. */
18156 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18160 case BFD_RELOC_ARM_LDRS_PC_G0
:
18161 case BFD_RELOC_ARM_LDRS_PC_G1
:
18162 case BFD_RELOC_ARM_LDRS_PC_G2
:
18163 case BFD_RELOC_ARM_LDRS_SB_G0
:
18164 case BFD_RELOC_ARM_LDRS_SB_G1
:
18165 case BFD_RELOC_ARM_LDRS_SB_G2
:
18166 assert (!fixP
->fx_done
);
18167 if (!seg
->use_rela_p
)
18170 bfd_vma addend_abs
= abs (value
);
18172 /* Check that the absolute value of the addend can be
18173 encoded in 8 bits. */
18174 if (addend_abs
>= 0x100)
18175 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18176 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
18179 /* Extract the instruction. */
18180 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18182 /* If the addend is negative, clear bit 23 of the instruction.
18183 Otherwise set it. */
18185 insn
&= ~(1 << 23);
18189 /* Place the first four bits of the absolute value of the addend
18190 into the first 4 bits of the instruction, and the remaining
18191 four into bits 8 .. 11. */
18192 insn
&= 0xfffff0f0;
18193 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
18195 /* Update the instruction. */
18196 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18200 case BFD_RELOC_ARM_LDC_PC_G0
:
18201 case BFD_RELOC_ARM_LDC_PC_G1
:
18202 case BFD_RELOC_ARM_LDC_PC_G2
:
18203 case BFD_RELOC_ARM_LDC_SB_G0
:
18204 case BFD_RELOC_ARM_LDC_SB_G1
:
18205 case BFD_RELOC_ARM_LDC_SB_G2
:
18206 assert (!fixP
->fx_done
);
18207 if (!seg
->use_rela_p
)
18210 bfd_vma addend_abs
= abs (value
);
18212 /* Check that the absolute value of the addend is a multiple of
18213 four and, when divided by four, fits in 8 bits. */
18214 if (addend_abs
& 0x3)
18215 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18216 _("bad offset 0x%08lX (must be word-aligned)"),
18219 if ((addend_abs
>> 2) > 0xff)
18220 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18221 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
18224 /* Extract the instruction. */
18225 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18227 /* If the addend is negative, clear bit 23 of the instruction.
18228 Otherwise set it. */
18230 insn
&= ~(1 << 23);
18234 /* Place the addend (divided by four) into the first eight
18235 bits of the instruction. */
18236 insn
&= 0xfffffff0;
18237 insn
|= addend_abs
>> 2;
18239 /* Update the instruction. */
18240 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18244 case BFD_RELOC_UNUSED
:
18246 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18247 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
18251 /* Translate internal representation of relocation info to BFD target
18255 tc_gen_reloc (asection
*section
, fixS
*fixp
)
18258 bfd_reloc_code_real_type code
;
18260 reloc
= xmalloc (sizeof (arelent
));
18262 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
18263 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18264 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18266 if (fixp
->fx_pcrel
)
18268 if (section
->use_rela_p
)
18269 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
18271 fixp
->fx_offset
= reloc
->address
;
18273 reloc
->addend
= fixp
->fx_offset
;
18275 switch (fixp
->fx_r_type
)
18278 if (fixp
->fx_pcrel
)
18280 code
= BFD_RELOC_8_PCREL
;
18285 if (fixp
->fx_pcrel
)
18287 code
= BFD_RELOC_16_PCREL
;
18292 if (fixp
->fx_pcrel
)
18294 code
= BFD_RELOC_32_PCREL
;
18298 case BFD_RELOC_ARM_MOVW
:
18299 if (fixp
->fx_pcrel
)
18301 code
= BFD_RELOC_ARM_MOVW_PCREL
;
18305 case BFD_RELOC_ARM_MOVT
:
18306 if (fixp
->fx_pcrel
)
18308 code
= BFD_RELOC_ARM_MOVT_PCREL
;
18312 case BFD_RELOC_ARM_THUMB_MOVW
:
18313 if (fixp
->fx_pcrel
)
18315 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
18319 case BFD_RELOC_ARM_THUMB_MOVT
:
18320 if (fixp
->fx_pcrel
)
18322 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
18326 case BFD_RELOC_NONE
:
18327 case BFD_RELOC_ARM_PCREL_BRANCH
:
18328 case BFD_RELOC_ARM_PCREL_BLX
:
18329 case BFD_RELOC_RVA
:
18330 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
18331 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
18332 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
18333 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
18334 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
18335 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
18336 case BFD_RELOC_THUMB_PCREL_BLX
:
18337 case BFD_RELOC_VTABLE_ENTRY
:
18338 case BFD_RELOC_VTABLE_INHERIT
:
18339 code
= fixp
->fx_r_type
;
18342 case BFD_RELOC_ARM_LITERAL
:
18343 case BFD_RELOC_ARM_HWLITERAL
:
18344 /* If this is called then the a literal has
18345 been referenced across a section boundary. */
18346 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18347 _("literal referenced across section boundary"));
18351 case BFD_RELOC_ARM_GOT32
:
18352 case BFD_RELOC_ARM_GOTOFF
:
18353 case BFD_RELOC_ARM_PLT32
:
18354 case BFD_RELOC_ARM_TARGET1
:
18355 case BFD_RELOC_ARM_ROSEGREL32
:
18356 case BFD_RELOC_ARM_SBREL32
:
18357 case BFD_RELOC_ARM_PREL31
:
18358 case BFD_RELOC_ARM_TARGET2
:
18359 case BFD_RELOC_ARM_TLS_LE32
:
18360 case BFD_RELOC_ARM_TLS_LDO32
:
18361 case BFD_RELOC_ARM_PCREL_CALL
:
18362 case BFD_RELOC_ARM_PCREL_JUMP
:
18363 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
18364 case BFD_RELOC_ARM_ALU_PC_G0
:
18365 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
18366 case BFD_RELOC_ARM_ALU_PC_G1
:
18367 case BFD_RELOC_ARM_ALU_PC_G2
:
18368 case BFD_RELOC_ARM_LDR_PC_G0
:
18369 case BFD_RELOC_ARM_LDR_PC_G1
:
18370 case BFD_RELOC_ARM_LDR_PC_G2
:
18371 case BFD_RELOC_ARM_LDRS_PC_G0
:
18372 case BFD_RELOC_ARM_LDRS_PC_G1
:
18373 case BFD_RELOC_ARM_LDRS_PC_G2
:
18374 case BFD_RELOC_ARM_LDC_PC_G0
:
18375 case BFD_RELOC_ARM_LDC_PC_G1
:
18376 case BFD_RELOC_ARM_LDC_PC_G2
:
18377 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
18378 case BFD_RELOC_ARM_ALU_SB_G0
:
18379 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
18380 case BFD_RELOC_ARM_ALU_SB_G1
:
18381 case BFD_RELOC_ARM_ALU_SB_G2
:
18382 case BFD_RELOC_ARM_LDR_SB_G0
:
18383 case BFD_RELOC_ARM_LDR_SB_G1
:
18384 case BFD_RELOC_ARM_LDR_SB_G2
:
18385 case BFD_RELOC_ARM_LDRS_SB_G0
:
18386 case BFD_RELOC_ARM_LDRS_SB_G1
:
18387 case BFD_RELOC_ARM_LDRS_SB_G2
:
18388 case BFD_RELOC_ARM_LDC_SB_G0
:
18389 case BFD_RELOC_ARM_LDC_SB_G1
:
18390 case BFD_RELOC_ARM_LDC_SB_G2
:
18391 code
= fixp
->fx_r_type
;
18394 case BFD_RELOC_ARM_TLS_GD32
:
18395 case BFD_RELOC_ARM_TLS_IE32
:
18396 case BFD_RELOC_ARM_TLS_LDM32
:
18397 /* BFD will include the symbol's address in the addend.
18398 But we don't want that, so subtract it out again here. */
18399 if (!S_IS_COMMON (fixp
->fx_addsy
))
18400 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
18401 code
= fixp
->fx_r_type
;
18405 case BFD_RELOC_ARM_IMMEDIATE
:
18406 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18407 _("internal relocation (type: IMMEDIATE) not fixed up"));
18410 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
18411 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18412 _("ADRL used for a symbol not defined in the same file"));
18415 case BFD_RELOC_ARM_OFFSET_IMM
:
18416 if (section
->use_rela_p
)
18418 code
= fixp
->fx_r_type
;
18422 if (fixp
->fx_addsy
!= NULL
18423 && !S_IS_DEFINED (fixp
->fx_addsy
)
18424 && S_IS_LOCAL (fixp
->fx_addsy
))
18426 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18427 _("undefined local label `%s'"),
18428 S_GET_NAME (fixp
->fx_addsy
));
18432 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18433 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
18440 switch (fixp
->fx_r_type
)
18442 case BFD_RELOC_NONE
: type
= "NONE"; break;
18443 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
18444 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
18445 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
18446 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
18447 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
18448 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
18449 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
18450 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
18451 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
18452 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
18453 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
18454 default: type
= _("<unknown>"); break;
18456 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18457 _("cannot represent %s relocation in this object file format"),
18464 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
18466 && fixp
->fx_addsy
== GOT_symbol
)
18468 code
= BFD_RELOC_ARM_GOTPC
;
18469 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
18473 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18475 if (reloc
->howto
== NULL
)
18477 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18478 _("cannot represent %s relocation in this object file format"),
18479 bfd_get_reloc_code_name (code
));
18483 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
18484 vtable entry to be used in the relocation's section offset. */
18485 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18486 reloc
->address
= fixp
->fx_offset
;
18491 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
18494 cons_fix_new_arm (fragS
* frag
,
18499 bfd_reloc_code_real_type type
;
18503 FIXME: @@ Should look at CPU word size. */
18507 type
= BFD_RELOC_8
;
18510 type
= BFD_RELOC_16
;
18514 type
= BFD_RELOC_32
;
18517 type
= BFD_RELOC_64
;
18521 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
18524 #if defined OBJ_COFF || defined OBJ_ELF
18526 arm_validate_fix (fixS
* fixP
)
18528 /* If the destination of the branch is a defined symbol which does not have
18529 the THUMB_FUNC attribute, then we must be calling a function which has
18530 the (interfacearm) attribute. We look for the Thumb entry point to that
18531 function and change the branch to refer to that function instead. */
18532 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
18533 && fixP
->fx_addsy
!= NULL
18534 && S_IS_DEFINED (fixP
->fx_addsy
)
18535 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
18537 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
18543 arm_force_relocation (struct fix
* fixp
)
18545 #if defined (OBJ_COFF) && defined (TE_PE)
18546 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
18550 /* Resolve these relocations even if the symbol is extern or weak. */
18551 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
18552 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
18553 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
18554 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
18555 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
18556 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
18559 /* Always leave these relocations for the linker. */
18560 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
18561 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
18562 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
18565 return generic_force_reloc (fixp
);
18570 arm_fix_adjustable (fixS
* fixP
)
18572 /* This is a little hack to help the gas/arm/adrl.s test. It prevents
18573 local labels from being added to the output symbol table when they
18574 are used with the ADRL pseudo op. The ADRL relocation should always
18575 be resolved before the binbary is emitted, so it is safe to say that
18576 it is adjustable. */
18577 if (fixP
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
)
18580 /* This is a hack for the gas/all/redef2.s test. This test causes symbols
18581 to be cloned, and without this test relocs would still be generated
18582 against the original, pre-cloned symbol. Such symbols would not appear
18583 in the symbol table however, and so a valid reloc could not be
18584 generated. So check to see if the fixup is against a symbol which has
18585 been removed from the symbol chain, and if it is, then allow it to be
18586 adjusted into a reloc against a section symbol. */
18587 if (fixP
->fx_addsy
!= NULL
18588 && ! S_IS_LOCAL (fixP
->fx_addsy
)
18589 && symbol_next (fixP
->fx_addsy
) == NULL
18590 && symbol_next (fixP
->fx_addsy
) == symbol_previous (fixP
->fx_addsy
))
18598 /* Relocations against function names must be left unadjusted,
18599 so that the linker can use this information to generate interworking
18600 stubs. The MIPS version of this function
18601 also prevents relocations that are mips-16 specific, but I do not
18602 know why it does this.
18605 There is one other problem that ought to be addressed here, but
18606 which currently is not: Taking the address of a label (rather
18607 than a function) and then later jumping to that address. Such
18608 addresses also ought to have their bottom bit set (assuming that
18609 they reside in Thumb code), but at the moment they will not. */
18612 arm_fix_adjustable (fixS
* fixP
)
18614 if (fixP
->fx_addsy
== NULL
)
18617 /* Preserve relocations against symbols with function type. */
18618 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
18621 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
18622 && fixP
->fx_subsy
== NULL
)
18625 /* We need the symbol name for the VTABLE entries. */
18626 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
18627 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18630 /* Don't allow symbols to be discarded on GOT related relocs. */
18631 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
18632 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
18633 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
18634 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
18635 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
18636 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
18637 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
18638 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
18639 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
18642 /* Similarly for group relocations. */
18643 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
18644 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
18645 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
18652 elf32_arm_target_format (void)
18655 return (target_big_endian
18656 ? "elf32-bigarm-symbian"
18657 : "elf32-littlearm-symbian");
18658 #elif defined (TE_VXWORKS)
18659 return (target_big_endian
18660 ? "elf32-bigarm-vxworks"
18661 : "elf32-littlearm-vxworks");
18663 if (target_big_endian
)
18664 return "elf32-bigarm";
18666 return "elf32-littlearm";
18671 armelf_frob_symbol (symbolS
* symp
,
18674 elf_frob_symbol (symp
, puntp
);
18678 /* MD interface: Finalization. */
18680 /* A good place to do this, although this was probably not intended
18681 for this kind of use. We need to dump the literal pool before
18682 references are made to a null symbol pointer. */
18687 literal_pool
* pool
;
18689 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
18691 /* Put it at the end of the relevent section. */
18692 subseg_set (pool
->section
, pool
->sub_section
);
18694 arm_elf_change_section ();
18700 /* Adjust the symbol table. This marks Thumb symbols as distinct from
18704 arm_adjust_symtab (void)
18709 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
18711 if (ARM_IS_THUMB (sym
))
18713 if (THUMB_IS_FUNC (sym
))
18715 /* Mark the symbol as a Thumb function. */
18716 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
18717 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
18718 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
18720 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
18721 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
18723 as_bad (_("%s: unexpected function type: %d"),
18724 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
18726 else switch (S_GET_STORAGE_CLASS (sym
))
18729 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
18732 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
18735 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
18743 if (ARM_IS_INTERWORK (sym
))
18744 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
18751 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
18753 if (ARM_IS_THUMB (sym
))
18755 elf_symbol_type
* elf_sym
;
18757 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
18758 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
18760 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
18761 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
18763 /* If it's a .thumb_func, declare it as so,
18764 otherwise tag label as .code 16. */
18765 if (THUMB_IS_FUNC (sym
))
18766 elf_sym
->internal_elf_sym
.st_info
=
18767 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
18769 elf_sym
->internal_elf_sym
.st_info
=
18770 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
18777 /* MD interface: Initialization. */
18780 set_constant_flonums (void)
18784 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
18785 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
18795 if ( (arm_ops_hsh
= hash_new ()) == NULL
18796 || (arm_cond_hsh
= hash_new ()) == NULL
18797 || (arm_shift_hsh
= hash_new ()) == NULL
18798 || (arm_psr_hsh
= hash_new ()) == NULL
18799 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
18800 || (arm_reg_hsh
= hash_new ()) == NULL
18801 || (arm_reloc_hsh
= hash_new ()) == NULL
18802 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
18803 as_fatal (_("virtual memory exhausted"));
18805 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
18806 hash_insert (arm_ops_hsh
, insns
[i
].template, (PTR
) (insns
+ i
));
18807 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
18808 hash_insert (arm_cond_hsh
, conds
[i
].template, (PTR
) (conds
+ i
));
18809 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
18810 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (PTR
) (shift_names
+ i
));
18811 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
18812 hash_insert (arm_psr_hsh
, psrs
[i
].template, (PTR
) (psrs
+ i
));
18813 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
18814 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template, (PTR
) (v7m_psrs
+ i
));
18815 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
18816 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (PTR
) (reg_names
+ i
));
18818 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
18820 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template,
18821 (PTR
) (barrier_opt_names
+ i
));
18823 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
18824 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (PTR
) (reloc_names
+ i
));
18827 set_constant_flonums ();
18829 /* Set the cpu variant based on the command-line options. We prefer
18830 -mcpu= over -march= if both are set (as for GCC); and we prefer
18831 -mfpu= over any other way of setting the floating point unit.
18832 Use of legacy options with new options are faulted. */
18835 if (mcpu_cpu_opt
|| march_cpu_opt
)
18836 as_bad (_("use of old and new-style options to set CPU type"));
18838 mcpu_cpu_opt
= legacy_cpu
;
18840 else if (!mcpu_cpu_opt
)
18841 mcpu_cpu_opt
= march_cpu_opt
;
18846 as_bad (_("use of old and new-style options to set FPU type"));
18848 mfpu_opt
= legacy_fpu
;
18850 else if (!mfpu_opt
)
18852 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
18853 /* Some environments specify a default FPU. If they don't, infer it
18854 from the processor. */
18856 mfpu_opt
= mcpu_fpu_opt
;
18858 mfpu_opt
= march_fpu_opt
;
18860 mfpu_opt
= &fpu_default
;
18867 mfpu_opt
= &fpu_default
;
18868 else if (ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
18869 mfpu_opt
= &fpu_arch_vfp_v2
;
18871 mfpu_opt
= &fpu_arch_fpa
;
18877 mcpu_cpu_opt
= &cpu_default
;
18878 selected_cpu
= cpu_default
;
18882 selected_cpu
= *mcpu_cpu_opt
;
18884 mcpu_cpu_opt
= &arm_arch_any
;
18887 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
18889 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
18891 #if defined OBJ_COFF || defined OBJ_ELF
18893 unsigned int flags
= 0;
18895 #if defined OBJ_ELF
18896 flags
= meabi_flags
;
18898 switch (meabi_flags
)
18900 case EF_ARM_EABI_UNKNOWN
:
18902 /* Set the flags in the private structure. */
18903 if (uses_apcs_26
) flags
|= F_APCS26
;
18904 if (support_interwork
) flags
|= F_INTERWORK
;
18905 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
18906 if (pic_code
) flags
|= F_PIC
;
18907 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
18908 flags
|= F_SOFT_FLOAT
;
18910 switch (mfloat_abi_opt
)
18912 case ARM_FLOAT_ABI_SOFT
:
18913 case ARM_FLOAT_ABI_SOFTFP
:
18914 flags
|= F_SOFT_FLOAT
;
18917 case ARM_FLOAT_ABI_HARD
:
18918 if (flags
& F_SOFT_FLOAT
)
18919 as_bad (_("hard-float conflicts with specified fpu"));
18923 /* Using pure-endian doubles (even if soft-float). */
18924 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
18925 flags
|= F_VFP_FLOAT
;
18927 #if defined OBJ_ELF
18928 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
18929 flags
|= EF_ARM_MAVERICK_FLOAT
;
18932 case EF_ARM_EABI_VER4
:
18933 case EF_ARM_EABI_VER5
:
18934 /* No additional flags to set. */
18941 bfd_set_private_flags (stdoutput
, flags
);
18943 /* We have run out flags in the COFF header to encode the
18944 status of ATPCS support, so instead we create a dummy,
18945 empty, debug section called .arm.atpcs. */
18950 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
18954 bfd_set_section_flags
18955 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
18956 bfd_set_section_size (stdoutput
, sec
, 0);
18957 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
18963 /* Record the CPU type as well. */
18964 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
18965 mach
= bfd_mach_arm_iWMMXt
;
18966 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
18967 mach
= bfd_mach_arm_XScale
;
18968 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
18969 mach
= bfd_mach_arm_ep9312
;
18970 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
18971 mach
= bfd_mach_arm_5TE
;
18972 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
18974 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
18975 mach
= bfd_mach_arm_5T
;
18977 mach
= bfd_mach_arm_5
;
18979 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
18981 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
18982 mach
= bfd_mach_arm_4T
;
18984 mach
= bfd_mach_arm_4
;
18986 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
18987 mach
= bfd_mach_arm_3M
;
18988 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
18989 mach
= bfd_mach_arm_3
;
18990 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
18991 mach
= bfd_mach_arm_2a
;
18992 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
18993 mach
= bfd_mach_arm_2
;
18995 mach
= bfd_mach_arm_unknown
;
18997 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
19000 /* Command line processing. */
19003 Invocation line includes a switch not recognized by the base assembler.
19004 See if it's a processor-specific option.
19006 This routine is somewhat complicated by the need for backwards
19007 compatibility (since older releases of gcc can't be changed).
19008 The new options try to make the interface as compatible as
19011 New options (supported) are:
19013 -mcpu=<cpu name> Assemble for selected processor
19014 -march=<architecture name> Assemble for selected architecture
19015 -mfpu=<fpu architecture> Assemble for selected FPU.
19016 -EB/-mbig-endian Big-endian
19017 -EL/-mlittle-endian Little-endian
19018 -k Generate PIC code
19019 -mthumb Start in Thumb mode
19020 -mthumb-interwork Code supports ARM/Thumb interworking
19022 For now we will also provide support for:
19024 -mapcs-32 32-bit Program counter
19025 -mapcs-26 26-bit Program counter
19026 -macps-float Floats passed in FP registers
19027 -mapcs-reentrant Reentrant code
19029 (sometime these will probably be replaced with -mapcs=<list of options>
19030 and -matpcs=<list of options>)
19032 The remaining options are only supported for back-wards compatibility.
19033 Cpu variants, the arm part is optional:
19034 -m[arm]1 Currently not supported.
19035 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
19036 -m[arm]3 Arm 3 processor
19037 -m[arm]6[xx], Arm 6 processors
19038 -m[arm]7[xx][t][[d]m] Arm 7 processors
19039 -m[arm]8[10] Arm 8 processors
19040 -m[arm]9[20][tdmi] Arm 9 processors
19041 -mstrongarm[110[0]] StrongARM processors
19042 -mxscale XScale processors
19043 -m[arm]v[2345[t[e]]] Arm architectures
19044 -mall All (except the ARM1)
19046 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
19047 -mfpe-old (No float load/store multiples)
19048 -mvfpxd VFP Single precision
19050 -mno-fpu Disable all floating point instructions
19052 The following CPU names are recognized:
19053 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
19054 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
19055 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
19056 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
19057 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
19058 arm10t arm10e, arm1020t, arm1020e, arm10200e,
19059 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
19063 const char * md_shortopts
= "m:k";
19065 #ifdef ARM_BI_ENDIAN
19066 #define OPTION_EB (OPTION_MD_BASE + 0)
19067 #define OPTION_EL (OPTION_MD_BASE + 1)
19069 #if TARGET_BYTES_BIG_ENDIAN
19070 #define OPTION_EB (OPTION_MD_BASE + 0)
19072 #define OPTION_EL (OPTION_MD_BASE + 1)
19076 struct option md_longopts
[] =
19079 {"EB", no_argument
, NULL
, OPTION_EB
},
19082 {"EL", no_argument
, NULL
, OPTION_EL
},
19084 {NULL
, no_argument
, NULL
, 0}
19087 size_t md_longopts_size
= sizeof (md_longopts
);
19089 struct arm_option_table
19091 char *option
; /* Option name to match. */
19092 char *help
; /* Help information. */
19093 int *var
; /* Variable to change. */
19094 int value
; /* What to change it to. */
19095 char *deprecated
; /* If non-null, print this message. */
19098 struct arm_option_table arm_opts
[] =
19100 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
19101 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
19102 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
19103 &support_interwork
, 1, NULL
},
19104 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
19105 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
19106 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
19108 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
19109 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
19110 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
19111 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
19114 /* These are recognized by the assembler, but have no affect on code. */
19115 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
19116 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
19117 {NULL
, NULL
, NULL
, 0, NULL
}
19120 struct arm_legacy_option_table
19122 char *option
; /* Option name to match. */
19123 const arm_feature_set
**var
; /* Variable to change. */
19124 const arm_feature_set value
; /* What to change it to. */
19125 char *deprecated
; /* If non-null, print this message. */
19128 const struct arm_legacy_option_table arm_legacy_opts
[] =
19130 /* DON'T add any new processors to this list -- we want the whole list
19131 to go away... Add them to the processors table instead. */
19132 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19133 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19134 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19135 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19136 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19137 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19138 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19139 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19140 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19141 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19142 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19143 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19144 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19145 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19146 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19147 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19148 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19149 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19150 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19151 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19152 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19153 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19154 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19155 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19156 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19157 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19158 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19159 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19160 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19161 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19162 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19163 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19164 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19165 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19166 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19167 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19168 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19169 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19170 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19171 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19172 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19173 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19174 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19175 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19176 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19177 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19178 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19179 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19180 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19181 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19182 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19183 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19184 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19185 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19186 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19187 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19188 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19189 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19190 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19191 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19192 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19193 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19194 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19195 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19196 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19197 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19198 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19199 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19200 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
19201 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
19202 N_("use -mcpu=strongarm110")},
19203 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
19204 N_("use -mcpu=strongarm1100")},
19205 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
19206 N_("use -mcpu=strongarm1110")},
19207 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
19208 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
19209 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
19211 /* Architecture variants -- don't add any more to this list either. */
19212 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19213 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19214 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19215 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19216 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19217 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19218 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19219 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19220 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19221 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19222 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
19223 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
19224 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
19225 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
19226 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
19227 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
19228 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
19229 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
19231 /* Floating point variants -- don't add any more to this list either. */
19232 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
19233 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
19234 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
19235 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
19236 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
19238 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
19241 struct arm_cpu_option_table
19244 const arm_feature_set value
;
19245 /* For some CPUs we assume an FPU unless the user explicitly sets
19247 const arm_feature_set default_fpu
;
19248 /* The canonical name of the CPU, or NULL to use NAME converted to upper
19250 const char *canonical_name
;
19253 /* This list should, at a minimum, contain all the cpu names
19254 recognized by GCC. */
19255 static const struct arm_cpu_option_table arm_cpus
[] =
19257 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
19258 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
19259 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
19260 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
19261 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
19262 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19263 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19264 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19265 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19266 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19267 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19268 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
19269 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19270 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
19271 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19272 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
19273 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19274 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19275 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19276 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19277 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19278 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19279 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19280 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19281 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19282 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19283 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19284 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19285 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19286 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19287 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19288 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19289 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19290 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19291 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19292 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19293 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19294 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19295 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19296 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
19297 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19298 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19299 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19300 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19301 /* For V5 or later processors we default to using VFP; but the user
19302 should really set the FPU type explicitly. */
19303 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
19304 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19305 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
19306 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
19307 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
19308 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
19309 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
19310 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19311 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
19312 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
19313 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19314 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19315 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
19316 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
19317 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19318 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
19319 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
19320 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19321 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19322 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
19323 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
19324 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
19325 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
19326 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
19327 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
19328 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
19329 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
19330 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
19331 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
19332 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
19333 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
19334 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE(0, FPU_VFP_V3
19335 | FPU_NEON_EXT_V1
),
19337 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
19338 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
19339 /* ??? XSCALE is really an architecture. */
19340 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
19341 /* ??? iwmmxt is not a processor. */
19342 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
19343 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
19345 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
19346 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
19349 struct arm_arch_option_table
19352 const arm_feature_set value
;
19353 const arm_feature_set default_fpu
;
19356 /* This list should, at a minimum, contain all the architecture names
19357 recognized by GCC. */
19358 static const struct arm_arch_option_table arm_archs
[] =
19360 {"all", ARM_ANY
, FPU_ARCH_FPA
},
19361 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
19362 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
19363 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
19364 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
19365 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
19366 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
19367 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
19368 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
19369 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
19370 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
19371 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
19372 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
19373 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
19374 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
19375 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
19376 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
19377 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
19378 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
19379 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
19380 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
19381 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
19382 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
19383 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
19384 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
19385 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
19386 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
19387 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
19388 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
19389 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
19390 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
19391 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
19392 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
19395 /* ISA extensions in the co-processor space. */
19396 struct arm_option_cpu_value_table
19399 const arm_feature_set value
;
19402 static const struct arm_option_cpu_value_table arm_extensions
[] =
19404 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
19405 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
19406 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
19407 {NULL
, ARM_ARCH_NONE
}
19410 /* This list should, at a minimum, contain all the fpu names
19411 recognized by GCC. */
19412 static const struct arm_option_cpu_value_table arm_fpus
[] =
19414 {"softfpa", FPU_NONE
},
19415 {"fpe", FPU_ARCH_FPE
},
19416 {"fpe2", FPU_ARCH_FPE
},
19417 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
19418 {"fpa", FPU_ARCH_FPA
},
19419 {"fpa10", FPU_ARCH_FPA
},
19420 {"fpa11", FPU_ARCH_FPA
},
19421 {"arm7500fe", FPU_ARCH_FPA
},
19422 {"softvfp", FPU_ARCH_VFP
},
19423 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
19424 {"vfp", FPU_ARCH_VFP_V2
},
19425 {"vfp9", FPU_ARCH_VFP_V2
},
19426 {"vfp3", FPU_ARCH_VFP_V3
},
19427 {"vfp10", FPU_ARCH_VFP_V2
},
19428 {"vfp10-r0", FPU_ARCH_VFP_V1
},
19429 {"vfpxd", FPU_ARCH_VFP_V1xD
},
19430 {"arm1020t", FPU_ARCH_VFP_V1
},
19431 {"arm1020e", FPU_ARCH_VFP_V2
},
19432 {"arm1136jfs", FPU_ARCH_VFP_V2
},
19433 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
19434 {"maverick", FPU_ARCH_MAVERICK
},
19435 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
19436 {NULL
, ARM_ARCH_NONE
}
19439 struct arm_option_value_table
19445 static const struct arm_option_value_table arm_float_abis
[] =
19447 {"hard", ARM_FLOAT_ABI_HARD
},
19448 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
19449 {"soft", ARM_FLOAT_ABI_SOFT
},
19454 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
19455 static const struct arm_option_value_table arm_eabis
[] =
19457 {"gnu", EF_ARM_EABI_UNKNOWN
},
19458 {"4", EF_ARM_EABI_VER4
},
19459 {"5", EF_ARM_EABI_VER5
},
19464 struct arm_long_option_table
19466 char * option
; /* Substring to match. */
19467 char * help
; /* Help information. */
19468 int (* func
) (char * subopt
); /* Function to decode sub-option. */
19469 char * deprecated
; /* If non-null, print this message. */
19473 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
19475 arm_feature_set
*ext_set
= xmalloc (sizeof (arm_feature_set
));
19477 /* Copy the feature set, so that we can modify it. */
19478 *ext_set
= **opt_p
;
19481 while (str
!= NULL
&& *str
!= 0)
19483 const struct arm_option_cpu_value_table
* opt
;
19489 as_bad (_("invalid architectural extension"));
19494 ext
= strchr (str
, '+');
19497 optlen
= ext
- str
;
19499 optlen
= strlen (str
);
19503 as_bad (_("missing architectural extension"));
19507 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
19508 if (strncmp (opt
->name
, str
, optlen
) == 0)
19510 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
19514 if (opt
->name
== NULL
)
19516 as_bad (_("unknown architectural extnsion `%s'"), str
);
19527 arm_parse_cpu (char * str
)
19529 const struct arm_cpu_option_table
* opt
;
19530 char * ext
= strchr (str
, '+');
19534 optlen
= ext
- str
;
19536 optlen
= strlen (str
);
19540 as_bad (_("missing cpu name `%s'"), str
);
19544 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
19545 if (strncmp (opt
->name
, str
, optlen
) == 0)
19547 mcpu_cpu_opt
= &opt
->value
;
19548 mcpu_fpu_opt
= &opt
->default_fpu
;
19549 if (opt
->canonical_name
)
19550 strcpy(selected_cpu_name
, opt
->canonical_name
);
19554 for (i
= 0; i
< optlen
; i
++)
19555 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
19556 selected_cpu_name
[i
] = 0;
19560 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
19565 as_bad (_("unknown cpu `%s'"), str
);
19570 arm_parse_arch (char * str
)
19572 const struct arm_arch_option_table
*opt
;
19573 char *ext
= strchr (str
, '+');
19577 optlen
= ext
- str
;
19579 optlen
= strlen (str
);
19583 as_bad (_("missing architecture name `%s'"), str
);
19587 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
19588 if (streq (opt
->name
, str
))
19590 march_cpu_opt
= &opt
->value
;
19591 march_fpu_opt
= &opt
->default_fpu
;
19592 strcpy(selected_cpu_name
, opt
->name
);
19595 return arm_parse_extension (ext
, &march_cpu_opt
);
19600 as_bad (_("unknown architecture `%s'\n"), str
);
19605 arm_parse_fpu (char * str
)
19607 const struct arm_option_cpu_value_table
* opt
;
19609 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
19610 if (streq (opt
->name
, str
))
19612 mfpu_opt
= &opt
->value
;
19616 as_bad (_("unknown floating point format `%s'\n"), str
);
19621 arm_parse_float_abi (char * str
)
19623 const struct arm_option_value_table
* opt
;
19625 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
19626 if (streq (opt
->name
, str
))
19628 mfloat_abi_opt
= opt
->value
;
19632 as_bad (_("unknown floating point abi `%s'\n"), str
);
19638 arm_parse_eabi (char * str
)
19640 const struct arm_option_value_table
*opt
;
19642 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
19643 if (streq (opt
->name
, str
))
19645 meabi_flags
= opt
->value
;
19648 as_bad (_("unknown EABI `%s'\n"), str
);
19653 struct arm_long_option_table arm_long_opts
[] =
19655 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
19656 arm_parse_cpu
, NULL
},
19657 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
19658 arm_parse_arch
, NULL
},
19659 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
19660 arm_parse_fpu
, NULL
},
19661 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
19662 arm_parse_float_abi
, NULL
},
19664 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
19665 arm_parse_eabi
, NULL
},
19667 {NULL
, NULL
, 0, NULL
}
19671 md_parse_option (int c
, char * arg
)
19673 struct arm_option_table
*opt
;
19674 const struct arm_legacy_option_table
*fopt
;
19675 struct arm_long_option_table
*lopt
;
19681 target_big_endian
= 1;
19687 target_big_endian
= 0;
19692 /* Listing option. Just ignore these, we don't support additional
19697 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
19699 if (c
== opt
->option
[0]
19700 && ((arg
== NULL
&& opt
->option
[1] == 0)
19701 || streq (arg
, opt
->option
+ 1)))
19703 #if WARN_DEPRECATED
19704 /* If the option is deprecated, tell the user. */
19705 if (opt
->deprecated
!= NULL
)
19706 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
19707 arg
? arg
: "", _(opt
->deprecated
));
19710 if (opt
->var
!= NULL
)
19711 *opt
->var
= opt
->value
;
19717 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
19719 if (c
== fopt
->option
[0]
19720 && ((arg
== NULL
&& fopt
->option
[1] == 0)
19721 || streq (arg
, fopt
->option
+ 1)))
19723 #if WARN_DEPRECATED
19724 /* If the option is deprecated, tell the user. */
19725 if (fopt
->deprecated
!= NULL
)
19726 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
19727 arg
? arg
: "", _(fopt
->deprecated
));
19730 if (fopt
->var
!= NULL
)
19731 *fopt
->var
= &fopt
->value
;
19737 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
19739 /* These options are expected to have an argument. */
19740 if (c
== lopt
->option
[0]
19742 && strncmp (arg
, lopt
->option
+ 1,
19743 strlen (lopt
->option
+ 1)) == 0)
19745 #if WARN_DEPRECATED
19746 /* If the option is deprecated, tell the user. */
19747 if (lopt
->deprecated
!= NULL
)
19748 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
19749 _(lopt
->deprecated
));
19752 /* Call the sup-option parser. */
19753 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
19764 md_show_usage (FILE * fp
)
19766 struct arm_option_table
*opt
;
19767 struct arm_long_option_table
*lopt
;
19769 fprintf (fp
, _(" ARM-specific assembler options:\n"));
19771 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
19772 if (opt
->help
!= NULL
)
19773 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
19775 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
19776 if (lopt
->help
!= NULL
)
19777 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
19781 -EB assemble code for a big-endian cpu\n"));
19786 -EL assemble code for a little-endian cpu\n"));
19795 arm_feature_set flags
;
19796 } cpu_arch_ver_table
;
19798 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
19799 least features first. */
19800 static const cpu_arch_ver_table cpu_arch_ver
[] =
19805 {4, ARM_ARCH_V5TE
},
19806 {5, ARM_ARCH_V5TEJ
},
19810 {9, ARM_ARCH_V6T2
},
19811 {10, ARM_ARCH_V7A
},
19812 {10, ARM_ARCH_V7R
},
19813 {10, ARM_ARCH_V7M
},
19817 /* Set the public EABI object attributes. */
19819 aeabi_set_public_attributes (void)
19822 arm_feature_set flags
;
19823 arm_feature_set tmp
;
19824 const cpu_arch_ver_table
*p
;
19826 /* Choose the architecture based on the capabilities of the requested cpu
19827 (if any) and/or the instructions actually used. */
19828 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
19829 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
19830 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
19834 for (p
= cpu_arch_ver
; p
->val
; p
++)
19836 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
19839 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
19843 /* Tag_CPU_name. */
19844 if (selected_cpu_name
[0])
19848 p
= selected_cpu_name
;
19849 if (strncmp(p
, "armv", 4) == 0)
19854 for (i
= 0; p
[i
]; i
++)
19855 p
[i
] = TOUPPER (p
[i
]);
19857 elf32_arm_add_eabi_attr_string (stdoutput
, 5, p
);
19859 /* Tag_CPU_arch. */
19860 elf32_arm_add_eabi_attr_int (stdoutput
, 6, arch
);
19861 /* Tag_CPU_arch_profile. */
19862 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
19863 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'A');
19864 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
19865 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'R');
19866 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
))
19867 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'M');
19868 /* Tag_ARM_ISA_use. */
19869 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_full
))
19870 elf32_arm_add_eabi_attr_int (stdoutput
, 8, 1);
19871 /* Tag_THUMB_ISA_use. */
19872 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_full
))
19873 elf32_arm_add_eabi_attr_int (stdoutput
, 9,
19874 ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
) ? 2 : 1);
19875 /* Tag_VFP_arch. */
19876 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v3
)
19877 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v3
))
19878 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 3);
19879 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v2
)
19880 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v2
))
19881 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 2);
19882 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1
)
19883 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1
)
19884 || ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1xd
)
19885 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1xd
))
19886 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 1);
19887 /* Tag_WMMX_arch. */
19888 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_cext_iwmmxt
)
19889 || ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_cext_iwmmxt
))
19890 elf32_arm_add_eabi_attr_int (stdoutput
, 11, 1);
19891 /* Tag_NEON_arch. */
19892 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_neon_ext_v1
)
19893 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_neon_ext_v1
))
19894 elf32_arm_add_eabi_attr_int (stdoutput
, 12, 1);
19897 /* Add the .ARM.attributes section. */
19906 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
19909 aeabi_set_public_attributes ();
19910 size
= elf32_arm_eabi_attr_size (stdoutput
);
19911 s
= subseg_new (".ARM.attributes", 0);
19912 bfd_set_section_flags (stdoutput
, s
, SEC_READONLY
| SEC_DATA
);
19913 addr
= frag_now_fix ();
19914 p
= frag_more (size
);
19915 elf32_arm_set_eabi_attr_contents (stdoutput
, (bfd_byte
*)p
, size
);
19917 #endif /* OBJ_ELF */
19920 /* Parse a .cpu directive. */
19923 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
19925 const struct arm_cpu_option_table
*opt
;
19929 name
= input_line_pointer
;
19930 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
19931 input_line_pointer
++;
19932 saved_char
= *input_line_pointer
;
19933 *input_line_pointer
= 0;
19935 /* Skip the first "all" entry. */
19936 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
19937 if (streq (opt
->name
, name
))
19939 mcpu_cpu_opt
= &opt
->value
;
19940 selected_cpu
= opt
->value
;
19941 if (opt
->canonical_name
)
19942 strcpy(selected_cpu_name
, opt
->canonical_name
);
19946 for (i
= 0; opt
->name
[i
]; i
++)
19947 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
19948 selected_cpu_name
[i
] = 0;
19950 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
19951 *input_line_pointer
= saved_char
;
19952 demand_empty_rest_of_line ();
19955 as_bad (_("unknown cpu `%s'"), name
);
19956 *input_line_pointer
= saved_char
;
19957 ignore_rest_of_line ();
19961 /* Parse a .arch directive. */
19964 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
19966 const struct arm_arch_option_table
*opt
;
19970 name
= input_line_pointer
;
19971 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
19972 input_line_pointer
++;
19973 saved_char
= *input_line_pointer
;
19974 *input_line_pointer
= 0;
19976 /* Skip the first "all" entry. */
19977 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
19978 if (streq (opt
->name
, name
))
19980 mcpu_cpu_opt
= &opt
->value
;
19981 selected_cpu
= opt
->value
;
19982 strcpy(selected_cpu_name
, opt
->name
);
19983 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
19984 *input_line_pointer
= saved_char
;
19985 demand_empty_rest_of_line ();
19989 as_bad (_("unknown architecture `%s'\n"), name
);
19990 *input_line_pointer
= saved_char
;
19991 ignore_rest_of_line ();
19995 /* Parse a .fpu directive. */
19998 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
20000 const struct arm_option_cpu_value_table
*opt
;
20004 name
= input_line_pointer
;
20005 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20006 input_line_pointer
++;
20007 saved_char
= *input_line_pointer
;
20008 *input_line_pointer
= 0;
20010 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
20011 if (streq (opt
->name
, name
))
20013 mfpu_opt
= &opt
->value
;
20014 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20015 *input_line_pointer
= saved_char
;
20016 demand_empty_rest_of_line ();
20020 as_bad (_("unknown floating point format `%s'\n"), name
);
20021 *input_line_pointer
= saved_char
;
20022 ignore_rest_of_line ();