1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
45 #define WARN_DEPRECATED 1
48 /* Must be at least the size of the largest unwind opcode (currently two). */
49 #define ARM_OPCODE_CHUNK_SIZE 8
51 /* This structure holds the unwinding state. */
56 symbolS
* table_entry
;
57 symbolS
* personality_routine
;
58 int personality_index
;
59 /* The segment containing the function. */
62 /* Opcodes generated from this function. */
63 unsigned char * opcodes
;
66 /* The number of bytes pushed to the stack. */
68 /* We don't add stack adjustment opcodes immediately so that we can merge
69 multiple adjustments. We can also omit the final adjustment
70 when using a frame pointer. */
71 offsetT pending_offset
;
72 /* These two fields are set by both unwind_movsp and unwind_setfp. They
73 hold the reg+offset to use when restoring sp from a frame pointer. */
76 /* Nonzero if an unwind_setfp directive has been seen. */
78 /* Nonzero if the last opcode restores sp from fp_reg. */
79 unsigned sp_restored
:1;
82 /* Bit N indicates that an R_ARM_NONE relocation has been output for
83 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
84 emitted only once per section, to save unnecessary bloat. */
85 static unsigned int marked_pr_dependency
= 0;
89 /* Results from operand parsing worker functions. */
93 PARSE_OPERAND_SUCCESS
,
95 PARSE_OPERAND_FAIL_NO_BACKTRACK
96 } parse_operand_result
;
101 ARM_FLOAT_ABI_SOFTFP
,
105 /* Types of processor to assemble for. */
107 #if defined __XSCALE__
108 #define CPU_DEFAULT ARM_ARCH_XSCALE
110 #if defined __thumb__
111 #define CPU_DEFAULT ARM_ARCH_V5T
118 # define FPU_DEFAULT FPU_ARCH_FPA
119 # elif defined (TE_NetBSD)
121 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
123 /* Legacy a.out format. */
124 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
126 # elif defined (TE_VXWORKS)
127 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
129 /* For backwards compatibility, default to FPA. */
130 # define FPU_DEFAULT FPU_ARCH_FPA
132 #endif /* ifndef FPU_DEFAULT */
134 #define streq(a, b) (strcmp (a, b) == 0)
136 static arm_feature_set cpu_variant
;
137 static arm_feature_set arm_arch_used
;
138 static arm_feature_set thumb_arch_used
;
140 /* Flags stored in private area of BFD structure. */
141 static int uses_apcs_26
= FALSE
;
142 static int atpcs
= FALSE
;
143 static int support_interwork
= FALSE
;
144 static int uses_apcs_float
= FALSE
;
145 static int pic_code
= FALSE
;
147 /* Variables that we set while parsing command-line options. Once all
148 options have been read we re-process these values to set the real
150 static const arm_feature_set
*legacy_cpu
= NULL
;
151 static const arm_feature_set
*legacy_fpu
= NULL
;
153 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
154 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
155 static const arm_feature_set
*march_cpu_opt
= NULL
;
156 static const arm_feature_set
*march_fpu_opt
= NULL
;
157 static const arm_feature_set
*mfpu_opt
= NULL
;
158 static const arm_feature_set
*object_arch
= NULL
;
160 /* Constants for known architecture features. */
161 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
162 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
163 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
164 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
165 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
166 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
167 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
168 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
169 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
172 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
175 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
176 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
177 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
178 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
179 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
180 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
181 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
182 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
183 static const arm_feature_set arm_ext_v4t_5
=
184 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
185 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
186 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
187 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
188 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
189 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
190 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
191 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
192 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
193 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
194 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
195 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
196 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
197 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
198 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
200 static const arm_feature_set arm_arch_any
= ARM_ANY
;
201 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
202 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
203 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
205 static const arm_feature_set arm_cext_iwmmxt2
=
206 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
207 static const arm_feature_set arm_cext_iwmmxt
=
208 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
209 static const arm_feature_set arm_cext_xscale
=
210 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
211 static const arm_feature_set arm_cext_maverick
=
212 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
213 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
214 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
215 static const arm_feature_set fpu_vfp_ext_v1xd
=
216 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
217 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
218 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
219 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
220 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
221 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
222 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
224 static int mfloat_abi_opt
= -1;
225 /* Record user cpu selection for object attributes. */
226 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
227 /* Must be long enough to hold any of the names in arm_cpus. */
228 static char selected_cpu_name
[16];
231 static int meabi_flags
= EABI_DEFAULT
;
233 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
239 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
244 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
245 symbolS
* GOT_symbol
;
248 /* 0: assemble for ARM,
249 1: assemble for Thumb,
250 2: assemble for Thumb even though target CPU does not support thumb
252 static int thumb_mode
= 0;
254 /* If unified_syntax is true, we are processing the new unified
255 ARM/Thumb syntax. Important differences from the old ARM mode:
257 - Immediate operands do not require a # prefix.
258 - Conditional affixes always appear at the end of the
259 instruction. (For backward compatibility, those instructions
260 that formerly had them in the middle, continue to accept them
262 - The IT instruction may appear, and if it does is validated
263 against subsequent conditional affixes. It does not generate
266 Important differences from the old Thumb mode:
268 - Immediate operands do not require a # prefix.
269 - Most of the V6T2 instructions are only available in unified mode.
270 - The .N and .W suffixes are recognized and honored (it is an error
271 if they cannot be honored).
272 - All instructions set the flags if and only if they have an 's' affix.
273 - Conditional affixes may be used. They are validated against
274 preceding IT instructions. Unlike ARM mode, you cannot use a
275 conditional affix except in the scope of an IT instruction. */
277 static bfd_boolean unified_syntax
= FALSE
;
292 enum neon_el_type type
;
296 #define NEON_MAX_TYPE_ELS 4
300 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
307 unsigned long instruction
;
311 /* "uncond_value" is set to the value in place of the conditional field in
312 unconditional versions of the instruction, or -1 if nothing is
315 struct neon_type vectype
;
316 /* Set to the opcode if the instruction needs relaxation.
317 Zero if the instruction is not relaxed. */
321 bfd_reloc_code_real_type type
;
330 struct neon_type_el vectype
;
331 unsigned present
: 1; /* Operand present. */
332 unsigned isreg
: 1; /* Operand was a register. */
333 unsigned immisreg
: 1; /* .imm field is a second register. */
334 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
335 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
336 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
337 instructions. This allows us to disambiguate ARM <-> vector insns. */
338 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
339 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
340 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
341 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
342 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
343 unsigned writeback
: 1; /* Operand has trailing ! */
344 unsigned preind
: 1; /* Preindexed address. */
345 unsigned postind
: 1; /* Postindexed address. */
346 unsigned negative
: 1; /* Index register was negated. */
347 unsigned shifted
: 1; /* Shift applied to operation. */
348 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
352 static struct arm_it inst
;
354 #define NUM_FLOAT_VALS 8
356 const char * fp_const
[] =
358 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
361 /* Number of littlenums required to hold an extended precision number. */
362 #define MAX_LITTLENUMS 6
364 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
374 #define CP_T_X 0x00008000
375 #define CP_T_Y 0x00400000
377 #define CONDS_BIT 0x00100000
378 #define LOAD_BIT 0x00100000
380 #define DOUBLE_LOAD_FLAG 0x00000001
384 const char * template;
388 #define COND_ALWAYS 0xE
392 const char *template;
396 struct asm_barrier_opt
398 const char *template;
402 /* The bit that distinguishes CPSR and SPSR. */
403 #define SPSR_BIT (1 << 22)
405 /* The individual PSR flag bits. */
406 #define PSR_c (1 << 16)
407 #define PSR_x (1 << 17)
408 #define PSR_s (1 << 18)
409 #define PSR_f (1 << 19)
414 bfd_reloc_code_real_type reloc
;
419 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
420 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
425 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
428 /* Bits for DEFINED field in neon_typed_alias. */
429 #define NTA_HASTYPE 1
430 #define NTA_HASINDEX 2
432 struct neon_typed_alias
434 unsigned char defined
;
436 struct neon_type_el eltype
;
439 /* ARM register categories. This includes coprocessor numbers and various
440 architecture extensions' registers. */
466 /* Structure for a hash table entry for a register.
467 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
468 information which states whether a vector type or index is specified (for a
469 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
473 unsigned char number
;
475 unsigned char builtin
;
476 struct neon_typed_alias
*neon
;
479 /* Diagnostics used when we don't get a register of the expected type. */
480 const char *const reg_expected_msgs
[] =
482 N_("ARM register expected"),
483 N_("bad or missing co-processor number"),
484 N_("co-processor register expected"),
485 N_("FPA register expected"),
486 N_("VFP single precision register expected"),
487 N_("VFP/Neon double precision register expected"),
488 N_("Neon quad precision register expected"),
489 N_("VFP single or double precision register expected"),
490 N_("Neon double or quad precision register expected"),
491 N_("VFP single, double or Neon quad precision register expected"),
492 N_("VFP system register expected"),
493 N_("Maverick MVF register expected"),
494 N_("Maverick MVD register expected"),
495 N_("Maverick MVFX register expected"),
496 N_("Maverick MVDX register expected"),
497 N_("Maverick MVAX register expected"),
498 N_("Maverick DSPSC register expected"),
499 N_("iWMMXt data register expected"),
500 N_("iWMMXt control register expected"),
501 N_("iWMMXt scalar register expected"),
502 N_("XScale accumulator register expected"),
505 /* Some well known registers that we refer to directly elsewhere. */
510 /* ARM instructions take 4bytes in the object file, Thumb instructions
516 /* Basic string to match. */
517 const char *template;
519 /* Parameters to instruction. */
520 unsigned char operands
[8];
522 /* Conditional tag - see opcode_lookup. */
523 unsigned int tag
: 4;
525 /* Basic instruction code. */
526 unsigned int avalue
: 28;
528 /* Thumb-format instruction code. */
531 /* Which architecture variant provides this instruction. */
532 const arm_feature_set
*avariant
;
533 const arm_feature_set
*tvariant
;
535 /* Function to call to encode instruction in ARM format. */
536 void (* aencode
) (void);
538 /* Function to call to encode instruction in Thumb format. */
539 void (* tencode
) (void);
542 /* Defines for various bits that we will want to toggle. */
543 #define INST_IMMEDIATE 0x02000000
544 #define OFFSET_REG 0x02000000
545 #define HWOFFSET_IMM 0x00400000
546 #define SHIFT_BY_REG 0x00000010
547 #define PRE_INDEX 0x01000000
548 #define INDEX_UP 0x00800000
549 #define WRITE_BACK 0x00200000
550 #define LDM_TYPE_2_OR_3 0x00400000
551 #define CPSI_MMOD 0x00020000
553 #define LITERAL_MASK 0xf000f000
554 #define OPCODE_MASK 0xfe1fffff
555 #define V4_STR_BIT 0x00000020
557 #define DATA_OP_SHIFT 21
559 #define T2_OPCODE_MASK 0xfe1fffff
560 #define T2_DATA_OP_SHIFT 21
562 /* Codes to distinguish the arithmetic instructions. */
573 #define OPCODE_CMP 10
574 #define OPCODE_CMN 11
575 #define OPCODE_ORR 12
576 #define OPCODE_MOV 13
577 #define OPCODE_BIC 14
578 #define OPCODE_MVN 15
580 #define T2_OPCODE_AND 0
581 #define T2_OPCODE_BIC 1
582 #define T2_OPCODE_ORR 2
583 #define T2_OPCODE_ORN 3
584 #define T2_OPCODE_EOR 4
585 #define T2_OPCODE_ADD 8
586 #define T2_OPCODE_ADC 10
587 #define T2_OPCODE_SBC 11
588 #define T2_OPCODE_SUB 13
589 #define T2_OPCODE_RSB 14
591 #define T_OPCODE_MUL 0x4340
592 #define T_OPCODE_TST 0x4200
593 #define T_OPCODE_CMN 0x42c0
594 #define T_OPCODE_NEG 0x4240
595 #define T_OPCODE_MVN 0x43c0
597 #define T_OPCODE_ADD_R3 0x1800
598 #define T_OPCODE_SUB_R3 0x1a00
599 #define T_OPCODE_ADD_HI 0x4400
600 #define T_OPCODE_ADD_ST 0xb000
601 #define T_OPCODE_SUB_ST 0xb080
602 #define T_OPCODE_ADD_SP 0xa800
603 #define T_OPCODE_ADD_PC 0xa000
604 #define T_OPCODE_ADD_I8 0x3000
605 #define T_OPCODE_SUB_I8 0x3800
606 #define T_OPCODE_ADD_I3 0x1c00
607 #define T_OPCODE_SUB_I3 0x1e00
609 #define T_OPCODE_ASR_R 0x4100
610 #define T_OPCODE_LSL_R 0x4080
611 #define T_OPCODE_LSR_R 0x40c0
612 #define T_OPCODE_ROR_R 0x41c0
613 #define T_OPCODE_ASR_I 0x1000
614 #define T_OPCODE_LSL_I 0x0000
615 #define T_OPCODE_LSR_I 0x0800
617 #define T_OPCODE_MOV_I8 0x2000
618 #define T_OPCODE_CMP_I8 0x2800
619 #define T_OPCODE_CMP_LR 0x4280
620 #define T_OPCODE_MOV_HR 0x4600
621 #define T_OPCODE_CMP_HR 0x4500
623 #define T_OPCODE_LDR_PC 0x4800
624 #define T_OPCODE_LDR_SP 0x9800
625 #define T_OPCODE_STR_SP 0x9000
626 #define T_OPCODE_LDR_IW 0x6800
627 #define T_OPCODE_STR_IW 0x6000
628 #define T_OPCODE_LDR_IH 0x8800
629 #define T_OPCODE_STR_IH 0x8000
630 #define T_OPCODE_LDR_IB 0x7800
631 #define T_OPCODE_STR_IB 0x7000
632 #define T_OPCODE_LDR_RW 0x5800
633 #define T_OPCODE_STR_RW 0x5000
634 #define T_OPCODE_LDR_RH 0x5a00
635 #define T_OPCODE_STR_RH 0x5200
636 #define T_OPCODE_LDR_RB 0x5c00
637 #define T_OPCODE_STR_RB 0x5400
639 #define T_OPCODE_PUSH 0xb400
640 #define T_OPCODE_POP 0xbc00
642 #define T_OPCODE_BRANCH 0xe000
644 #define THUMB_SIZE 2 /* Size of thumb instruction. */
645 #define THUMB_PP_PC_LR 0x0100
646 #define THUMB_LOAD_BIT 0x0800
647 #define THUMB2_LOAD_BIT 0x00100000
649 #define BAD_ARGS _("bad arguments to instruction")
650 #define BAD_PC _("r15 not allowed here")
651 #define BAD_COND _("instruction cannot be conditional")
652 #define BAD_OVERLAP _("registers may not be the same")
653 #define BAD_HIREG _("lo register required")
654 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
655 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
656 #define BAD_BRANCH _("branch must be last instruction in IT block")
657 #define BAD_NOT_IT _("instruction not allowed in IT block")
658 #define BAD_FPU _("selected FPU does not support instruction")
660 static struct hash_control
*arm_ops_hsh
;
661 static struct hash_control
*arm_cond_hsh
;
662 static struct hash_control
*arm_shift_hsh
;
663 static struct hash_control
*arm_psr_hsh
;
664 static struct hash_control
*arm_v7m_psr_hsh
;
665 static struct hash_control
*arm_reg_hsh
;
666 static struct hash_control
*arm_reloc_hsh
;
667 static struct hash_control
*arm_barrier_opt_hsh
;
669 /* Stuff needed to resolve the label ambiguity
679 symbolS
* last_label_seen
;
680 static int label_is_thumb_function_name
= FALSE
;
682 /* Literal pool structure. Held on a per-section
683 and per-sub-section basis. */
685 #define MAX_LITERAL_POOL_SIZE 1024
686 typedef struct literal_pool
688 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
689 unsigned int next_free_entry
;
694 struct literal_pool
* next
;
697 /* Pointer to a linked list of literal pools. */
698 literal_pool
* list_of_pools
= NULL
;
700 /* State variables for IT block handling. */
701 static bfd_boolean current_it_mask
= 0;
702 static int current_cc
;
707 /* This array holds the chars that always start a comment. If the
708 pre-processor is disabled, these aren't very useful. */
709 const char comment_chars
[] = "@";
711 /* This array holds the chars that only start a comment at the beginning of
712 a line. If the line seems to have the form '# 123 filename'
713 .line and .file directives will appear in the pre-processed output. */
714 /* Note that input_file.c hand checks for '#' at the beginning of the
715 first line of the input file. This is because the compiler outputs
716 #NO_APP at the beginning of its output. */
717 /* Also note that comments like this one will always work. */
718 const char line_comment_chars
[] = "#";
720 const char line_separator_chars
[] = ";";
722 /* Chars that can be used to separate mant
723 from exp in floating point numbers. */
724 const char EXP_CHARS
[] = "eE";
726 /* Chars that mean this number is a floating point constant. */
730 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
732 /* Prefix characters that indicate the start of an immediate
734 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
736 /* Separator character handling. */
738 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
741 skip_past_char (char ** str
, char c
)
751 #define skip_past_comma(str) skip_past_char (str, ',')
753 /* Arithmetic expressions (possibly involving symbols). */
755 /* Return TRUE if anything in the expression is a bignum. */
758 walk_no_bignums (symbolS
* sp
)
760 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
763 if (symbol_get_value_expression (sp
)->X_add_symbol
)
765 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
766 || (symbol_get_value_expression (sp
)->X_op_symbol
767 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
773 static int in_my_get_expression
= 0;
775 /* Third argument to my_get_expression. */
776 #define GE_NO_PREFIX 0
777 #define GE_IMM_PREFIX 1
778 #define GE_OPT_PREFIX 2
779 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
780 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
781 #define GE_OPT_PREFIX_BIG 3
784 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
789 /* In unified syntax, all prefixes are optional. */
791 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
796 case GE_NO_PREFIX
: break;
798 if (!is_immediate_prefix (**str
))
800 inst
.error
= _("immediate expression requires a # prefix");
806 case GE_OPT_PREFIX_BIG
:
807 if (is_immediate_prefix (**str
))
813 memset (ep
, 0, sizeof (expressionS
));
815 save_in
= input_line_pointer
;
816 input_line_pointer
= *str
;
817 in_my_get_expression
= 1;
818 seg
= expression (ep
);
819 in_my_get_expression
= 0;
821 if (ep
->X_op
== O_illegal
)
823 /* We found a bad expression in md_operand(). */
824 *str
= input_line_pointer
;
825 input_line_pointer
= save_in
;
826 if (inst
.error
== NULL
)
827 inst
.error
= _("bad expression");
832 if (seg
!= absolute_section
833 && seg
!= text_section
834 && seg
!= data_section
835 && seg
!= bss_section
836 && seg
!= undefined_section
)
838 inst
.error
= _("bad segment");
839 *str
= input_line_pointer
;
840 input_line_pointer
= save_in
;
845 /* Get rid of any bignums now, so that we don't generate an error for which
846 we can't establish a line number later on. Big numbers are never valid
847 in instructions, which is where this routine is always called. */
848 if (prefix_mode
!= GE_OPT_PREFIX_BIG
849 && (ep
->X_op
== O_big
851 && (walk_no_bignums (ep
->X_add_symbol
)
853 && walk_no_bignums (ep
->X_op_symbol
))))))
855 inst
.error
= _("invalid constant");
856 *str
= input_line_pointer
;
857 input_line_pointer
= save_in
;
861 *str
= input_line_pointer
;
862 input_line_pointer
= save_in
;
866 /* Turn a string in input_line_pointer into a floating point constant
867 of type TYPE, and store the appropriate bytes in *LITP. The number
868 of LITTLENUMS emitted is stored in *SIZEP. An error message is
869 returned, or NULL on OK.
871 Note that fp constants aren't represent in the normal way on the ARM.
872 In big endian mode, things are as expected. However, in little endian
873 mode fp constants are big-endian word-wise, and little-endian byte-wise
874 within the words. For example, (double) 1.1 in big endian mode is
875 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
876 the byte sequence 99 99 f1 3f 9a 99 99 99.
878 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
881 md_atof (int type
, char * litP
, int * sizeP
)
884 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
916 return _("bad call to MD_ATOF()");
919 t
= atof_ieee (input_line_pointer
, type
, words
);
921 input_line_pointer
= t
;
924 if (target_big_endian
)
926 for (i
= 0; i
< prec
; i
++)
928 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
934 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
935 for (i
= prec
- 1; i
>= 0; i
--)
937 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
941 /* For a 4 byte float the order of elements in `words' is 1 0.
942 For an 8 byte float the order is 1 0 3 2. */
943 for (i
= 0; i
< prec
; i
+= 2)
945 md_number_to_chars (litP
, (valueT
) words
[i
+ 1], 2);
946 md_number_to_chars (litP
+ 2, (valueT
) words
[i
], 2);
954 /* We handle all bad expressions here, so that we can report the faulty
955 instruction in the error message. */
957 md_operand (expressionS
* expr
)
959 if (in_my_get_expression
)
960 expr
->X_op
= O_illegal
;
963 /* Immediate values. */
965 /* Generic immediate-value read function for use in directives.
966 Accepts anything that 'expression' can fold to a constant.
967 *val receives the number. */
970 immediate_for_directive (int *val
)
973 exp
.X_op
= O_illegal
;
975 if (is_immediate_prefix (*input_line_pointer
))
977 input_line_pointer
++;
981 if (exp
.X_op
!= O_constant
)
983 as_bad (_("expected #constant"));
984 ignore_rest_of_line ();
987 *val
= exp
.X_add_number
;
992 /* Register parsing. */
994 /* Generic register parser. CCP points to what should be the
995 beginning of a register name. If it is indeed a valid register
996 name, advance CCP over it and return the reg_entry structure;
997 otherwise return NULL. Does not issue diagnostics. */
999 static struct reg_entry
*
1000 arm_reg_parse_multi (char **ccp
)
1004 struct reg_entry
*reg
;
1006 #ifdef REGISTER_PREFIX
1007 if (*start
!= REGISTER_PREFIX
)
1011 #ifdef OPTIONAL_REGISTER_PREFIX
1012 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1017 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1022 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1024 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1034 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1035 enum arm_reg_type type
)
1037 /* Alternative syntaxes are accepted for a few register classes. */
1044 /* Generic coprocessor register names are allowed for these. */
1045 if (reg
&& reg
->type
== REG_TYPE_CN
)
1050 /* For backward compatibility, a bare number is valid here. */
1052 unsigned long processor
= strtoul (start
, ccp
, 10);
1053 if (*ccp
!= start
&& processor
<= 15)
1057 case REG_TYPE_MMXWC
:
1058 /* WC includes WCG. ??? I'm not sure this is true for all
1059 instructions that take WC registers. */
1060 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1071 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1072 return value is the register number or FAIL. */
1075 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1078 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1081 /* Do not allow a scalar (reg+index) to parse as a register. */
1082 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1085 if (reg
&& reg
->type
== type
)
1088 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1095 /* Parse a Neon type specifier. *STR should point at the leading '.'
1096 character. Does no verification at this stage that the type fits the opcode
1103 Can all be legally parsed by this function.
1105 Fills in neon_type struct pointer with parsed information, and updates STR
1106 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1107 type, FAIL if not. */
1110 parse_neon_type (struct neon_type
*type
, char **str
)
1117 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1119 enum neon_el_type thistype
= NT_untyped
;
1120 unsigned thissize
= -1u;
1127 /* Just a size without an explicit type. */
1131 switch (TOLOWER (*ptr
))
1133 case 'i': thistype
= NT_integer
; break;
1134 case 'f': thistype
= NT_float
; break;
1135 case 'p': thistype
= NT_poly
; break;
1136 case 's': thistype
= NT_signed
; break;
1137 case 'u': thistype
= NT_unsigned
; break;
1139 thistype
= NT_float
;
1144 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1150 /* .f is an abbreviation for .f32. */
1151 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1156 thissize
= strtoul (ptr
, &ptr
, 10);
1158 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1161 as_bad (_("bad size %d in type specifier"), thissize
);
1169 type
->el
[type
->elems
].type
= thistype
;
1170 type
->el
[type
->elems
].size
= thissize
;
1175 /* Empty/missing type is not a successful parse. */
1176 if (type
->elems
== 0)
1184 /* Errors may be set multiple times during parsing or bit encoding
1185 (particularly in the Neon bits), but usually the earliest error which is set
1186 will be the most meaningful. Avoid overwriting it with later (cascading)
1187 errors by calling this function. */
1190 first_error (const char *err
)
1196 /* Parse a single type, e.g. ".s32", leading period included. */
1198 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1201 struct neon_type optype
;
1205 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1207 if (optype
.elems
== 1)
1208 *vectype
= optype
.el
[0];
1211 first_error (_("only one type should be specified for operand"));
1217 first_error (_("vector type expected"));
1229 /* Special meanings for indices (which have a range of 0-7), which will fit into
1232 #define NEON_ALL_LANES 15
1233 #define NEON_INTERLEAVE_LANES 14
1235 /* Parse either a register or a scalar, with an optional type. Return the
1236 register number, and optionally fill in the actual type of the register
1237 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1238 type/index information in *TYPEINFO. */
1241 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1242 enum arm_reg_type
*rtype
,
1243 struct neon_typed_alias
*typeinfo
)
1246 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1247 struct neon_typed_alias atype
;
1248 struct neon_type_el parsetype
;
1252 atype
.eltype
.type
= NT_invtype
;
1253 atype
.eltype
.size
= -1;
1255 /* Try alternate syntax for some types of register. Note these are mutually
1256 exclusive with the Neon syntax extensions. */
1259 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1267 /* Undo polymorphism when a set of register types may be accepted. */
1268 if ((type
== REG_TYPE_NDQ
1269 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1270 || (type
== REG_TYPE_VFSD
1271 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1272 || (type
== REG_TYPE_NSDQ
1273 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1274 || reg
->type
== REG_TYPE_NQ
))
1275 || (type
== REG_TYPE_MMXWC
1276 && (reg
->type
== REG_TYPE_MMXWCG
)))
1279 if (type
!= reg
->type
)
1285 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1287 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1289 first_error (_("can't redefine type for operand"));
1292 atype
.defined
|= NTA_HASTYPE
;
1293 atype
.eltype
= parsetype
;
1296 if (skip_past_char (&str
, '[') == SUCCESS
)
1298 if (type
!= REG_TYPE_VFD
)
1300 first_error (_("only D registers may be indexed"));
1304 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1306 first_error (_("can't change index for operand"));
1310 atype
.defined
|= NTA_HASINDEX
;
1312 if (skip_past_char (&str
, ']') == SUCCESS
)
1313 atype
.index
= NEON_ALL_LANES
;
1318 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1320 if (exp
.X_op
!= O_constant
)
1322 first_error (_("constant expression required"));
1326 if (skip_past_char (&str
, ']') == FAIL
)
1329 atype
.index
= exp
.X_add_number
;
1344 /* Like arm_reg_parse, but allow allow the following extra features:
1345 - If RTYPE is non-zero, return the (possibly restricted) type of the
1346 register (e.g. Neon double or quad reg when either has been requested).
1347 - If this is a Neon vector type with additional type information, fill
1348 in the struct pointed to by VECTYPE (if non-NULL).
1349 This function will fault on encountering a scalar.
1353 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1354 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1356 struct neon_typed_alias atype
;
1358 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1363 /* Do not allow a scalar (reg+index) to parse as a register. */
1364 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1366 first_error (_("register operand expected, but got scalar"));
1371 *vectype
= atype
.eltype
;
1378 #define NEON_SCALAR_REG(X) ((X) >> 4)
1379 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1381 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1382 have enough information to be able to do a good job bounds-checking. So, we
1383 just do easy checks here, and do further checks later. */
1386 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1390 struct neon_typed_alias atype
;
1392 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1394 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1397 if (atype
.index
== NEON_ALL_LANES
)
1399 first_error (_("scalar must have an index"));
1402 else if (atype
.index
>= 64 / elsize
)
1404 first_error (_("scalar index out of range"));
1409 *type
= atype
.eltype
;
1413 return reg
* 16 + atype
.index
;
1416 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1418 parse_reg_list (char ** strp
)
1420 char * str
= * strp
;
1424 /* We come back here if we get ranges concatenated by '+' or '|'. */
1439 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1441 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1451 first_error (_("bad range in register list"));
1455 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1457 if (range
& (1 << i
))
1459 (_("Warning: duplicated register (r%d) in register list"),
1467 if (range
& (1 << reg
))
1468 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1470 else if (reg
<= cur_reg
)
1471 as_tsktsk (_("Warning: register range not in ascending order"));
1476 while (skip_past_comma (&str
) != FAIL
1477 || (in_range
= 1, *str
++ == '-'));
1482 first_error (_("missing `}'"));
1490 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1493 if (expr
.X_op
== O_constant
)
1495 if (expr
.X_add_number
1496 != (expr
.X_add_number
& 0x0000ffff))
1498 inst
.error
= _("invalid register mask");
1502 if ((range
& expr
.X_add_number
) != 0)
1504 int regno
= range
& expr
.X_add_number
;
1507 regno
= (1 << regno
) - 1;
1509 (_("Warning: duplicated register (r%d) in register list"),
1513 range
|= expr
.X_add_number
;
1517 if (inst
.reloc
.type
!= 0)
1519 inst
.error
= _("expression too complex");
1523 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1524 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1525 inst
.reloc
.pc_rel
= 0;
1529 if (*str
== '|' || *str
== '+')
1535 while (another_range
);
1541 /* Types of registers in a list. */
1550 /* Parse a VFP register list. If the string is invalid return FAIL.
1551 Otherwise return the number of registers, and set PBASE to the first
1552 register. Parses registers of type ETYPE.
1553 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1554 - Q registers can be used to specify pairs of D registers
1555 - { } can be omitted from around a singleton register list
1556 FIXME: This is not implemented, as it would require backtracking in
1559 This could be done (the meaning isn't really ambiguous), but doesn't
1560 fit in well with the current parsing framework.
1561 - 32 D registers may be used (also true for VFPv3).
1562 FIXME: Types are ignored in these register lists, which is probably a
1566 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1571 enum arm_reg_type regtype
= 0;
1575 unsigned long mask
= 0;
1580 inst
.error
= _("expecting {");
1589 regtype
= REG_TYPE_VFS
;
1594 regtype
= REG_TYPE_VFD
;
1597 case REGLIST_NEON_D
:
1598 regtype
= REG_TYPE_NDQ
;
1602 if (etype
!= REGLIST_VFP_S
)
1604 /* VFPv3 allows 32 D registers. */
1605 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
1609 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1612 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1619 base_reg
= max_regs
;
1623 int setmask
= 1, addregs
= 1;
1625 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1627 if (new_base
== FAIL
)
1629 first_error (_(reg_expected_msgs
[regtype
]));
1633 if (new_base
>= max_regs
)
1635 first_error (_("register out of range in list"));
1639 /* Note: a value of 2 * n is returned for the register Q<n>. */
1640 if (regtype
== REG_TYPE_NQ
)
1646 if (new_base
< base_reg
)
1647 base_reg
= new_base
;
1649 if (mask
& (setmask
<< new_base
))
1651 first_error (_("invalid register list"));
1655 if ((mask
>> new_base
) != 0 && ! warned
)
1657 as_tsktsk (_("register list not in ascending order"));
1661 mask
|= setmask
<< new_base
;
1664 if (*str
== '-') /* We have the start of a range expression */
1670 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1673 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1677 if (high_range
>= max_regs
)
1679 first_error (_("register out of range in list"));
1683 if (regtype
== REG_TYPE_NQ
)
1684 high_range
= high_range
+ 1;
1686 if (high_range
<= new_base
)
1688 inst
.error
= _("register range not in ascending order");
1692 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1694 if (mask
& (setmask
<< new_base
))
1696 inst
.error
= _("invalid register list");
1700 mask
|= setmask
<< new_base
;
1705 while (skip_past_comma (&str
) != FAIL
);
1709 /* Sanity check -- should have raised a parse error above. */
1710 if (count
== 0 || count
> max_regs
)
1715 /* Final test -- the registers must be consecutive. */
1717 for (i
= 0; i
< count
; i
++)
1719 if ((mask
& (1u << i
)) == 0)
1721 inst
.error
= _("non-contiguous register range");
1731 /* True if two alias types are the same. */
1734 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1742 if (a
->defined
!= b
->defined
)
1745 if ((a
->defined
& NTA_HASTYPE
) != 0
1746 && (a
->eltype
.type
!= b
->eltype
.type
1747 || a
->eltype
.size
!= b
->eltype
.size
))
1750 if ((a
->defined
& NTA_HASINDEX
) != 0
1751 && (a
->index
!= b
->index
))
1757 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1758 The base register is put in *PBASE.
1759 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1761 The register stride (minus one) is put in bit 4 of the return value.
1762 Bits [6:5] encode the list length (minus one).
1763 The type of the list elements is put in *ELTYPE, if non-NULL. */
1765 #define NEON_LANE(X) ((X) & 0xf)
1766 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1767 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1770 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1771 struct neon_type_el
*eltype
)
1778 int leading_brace
= 0;
1779 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1781 const char *const incr_error
= "register stride must be 1 or 2";
1782 const char *const type_error
= "mismatched element/structure types in list";
1783 struct neon_typed_alias firsttype
;
1785 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1790 struct neon_typed_alias atype
;
1791 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1795 first_error (_(reg_expected_msgs
[rtype
]));
1802 if (rtype
== REG_TYPE_NQ
)
1809 else if (reg_incr
== -1)
1811 reg_incr
= getreg
- base_reg
;
1812 if (reg_incr
< 1 || reg_incr
> 2)
1814 first_error (_(incr_error
));
1818 else if (getreg
!= base_reg
+ reg_incr
* count
)
1820 first_error (_(incr_error
));
1824 if (!neon_alias_types_same (&atype
, &firsttype
))
1826 first_error (_(type_error
));
1830 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1834 struct neon_typed_alias htype
;
1835 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1837 lane
= NEON_INTERLEAVE_LANES
;
1838 else if (lane
!= NEON_INTERLEAVE_LANES
)
1840 first_error (_(type_error
));
1845 else if (reg_incr
!= 1)
1847 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1851 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1854 first_error (_(reg_expected_msgs
[rtype
]));
1857 if (!neon_alias_types_same (&htype
, &firsttype
))
1859 first_error (_(type_error
));
1862 count
+= hireg
+ dregs
- getreg
;
1866 /* If we're using Q registers, we can't use [] or [n] syntax. */
1867 if (rtype
== REG_TYPE_NQ
)
1873 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1877 else if (lane
!= atype
.index
)
1879 first_error (_(type_error
));
1883 else if (lane
== -1)
1884 lane
= NEON_INTERLEAVE_LANES
;
1885 else if (lane
!= NEON_INTERLEAVE_LANES
)
1887 first_error (_(type_error
));
1892 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1894 /* No lane set by [x]. We must be interleaving structures. */
1896 lane
= NEON_INTERLEAVE_LANES
;
1899 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
1900 || (count
> 1 && reg_incr
== -1))
1902 first_error (_("error parsing element/structure list"));
1906 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
1908 first_error (_("expected }"));
1916 *eltype
= firsttype
.eltype
;
1921 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
1924 /* Parse an explicit relocation suffix on an expression. This is
1925 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1926 arm_reloc_hsh contains no entries, so this function can only
1927 succeed if there is no () after the word. Returns -1 on error,
1928 BFD_RELOC_UNUSED if there wasn't any suffix. */
1930 parse_reloc (char **str
)
1932 struct reloc_entry
*r
;
1936 return BFD_RELOC_UNUSED
;
1941 while (*q
&& *q
!= ')' && *q
!= ',')
1946 if ((r
= hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
1953 /* Directives: register aliases. */
1955 static struct reg_entry
*
1956 insert_reg_alias (char *str
, int number
, int type
)
1958 struct reg_entry
*new;
1961 if ((new = hash_find (arm_reg_hsh
, str
)) != 0)
1964 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
1966 /* Only warn about a redefinition if it's not defined as the
1968 else if (new->number
!= number
|| new->type
!= type
)
1969 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1974 name
= xstrdup (str
);
1975 new = xmalloc (sizeof (struct reg_entry
));
1978 new->number
= number
;
1980 new->builtin
= FALSE
;
1983 if (hash_insert (arm_reg_hsh
, name
, (PTR
) new))
1990 insert_neon_reg_alias (char *str
, int number
, int type
,
1991 struct neon_typed_alias
*atype
)
1993 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
1997 first_error (_("attempt to redefine typed alias"));
2003 reg
->neon
= xmalloc (sizeof (struct neon_typed_alias
));
2004 *reg
->neon
= *atype
;
2008 /* Look for the .req directive. This is of the form:
2010 new_register_name .req existing_register_name
2012 If we find one, or if it looks sufficiently like one that we want to
2013 handle any error here, return non-zero. Otherwise return zero. */
2016 create_register_alias (char * newname
, char *p
)
2018 struct reg_entry
*old
;
2019 char *oldname
, *nbuf
;
2022 /* The input scrubber ensures that whitespace after the mnemonic is
2023 collapsed to single spaces. */
2025 if (strncmp (oldname
, " .req ", 6) != 0)
2029 if (*oldname
== '\0')
2032 old
= hash_find (arm_reg_hsh
, oldname
);
2035 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2039 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2040 the desired alias name, and p points to its end. If not, then
2041 the desired alias name is in the global original_case_string. */
2042 #ifdef TC_CASE_SENSITIVE
2045 newname
= original_case_string
;
2046 nlen
= strlen (newname
);
2049 nbuf
= alloca (nlen
+ 1);
2050 memcpy (nbuf
, newname
, nlen
);
2053 /* Create aliases under the new name as stated; an all-lowercase
2054 version of the new name; and an all-uppercase version of the new
2056 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2058 for (p
= nbuf
; *p
; p
++)
2061 if (strncmp (nbuf
, newname
, nlen
))
2062 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2064 for (p
= nbuf
; *p
; p
++)
2067 if (strncmp (nbuf
, newname
, nlen
))
2068 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2073 /* Create a Neon typed/indexed register alias using directives, e.g.:
2078 These typed registers can be used instead of the types specified after the
2079 Neon mnemonic, so long as all operands given have types. Types can also be
2080 specified directly, e.g.:
2081 vadd d0.s32, d1.s32, d2.s32
2085 create_neon_reg_alias (char *newname
, char *p
)
2087 enum arm_reg_type basetype
;
2088 struct reg_entry
*basereg
;
2089 struct reg_entry mybasereg
;
2090 struct neon_type ntype
;
2091 struct neon_typed_alias typeinfo
;
2092 char *namebuf
, *nameend
;
2095 typeinfo
.defined
= 0;
2096 typeinfo
.eltype
.type
= NT_invtype
;
2097 typeinfo
.eltype
.size
= -1;
2098 typeinfo
.index
= -1;
2102 if (strncmp (p
, " .dn ", 5) == 0)
2103 basetype
= REG_TYPE_VFD
;
2104 else if (strncmp (p
, " .qn ", 5) == 0)
2105 basetype
= REG_TYPE_NQ
;
2114 basereg
= arm_reg_parse_multi (&p
);
2116 if (basereg
&& basereg
->type
!= basetype
)
2118 as_bad (_("bad type for register"));
2122 if (basereg
== NULL
)
2125 /* Try parsing as an integer. */
2126 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2127 if (exp
.X_op
!= O_constant
)
2129 as_bad (_("expression must be constant"));
2132 basereg
= &mybasereg
;
2133 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2139 typeinfo
= *basereg
->neon
;
2141 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2143 /* We got a type. */
2144 if (typeinfo
.defined
& NTA_HASTYPE
)
2146 as_bad (_("can't redefine the type of a register alias"));
2150 typeinfo
.defined
|= NTA_HASTYPE
;
2151 if (ntype
.elems
!= 1)
2153 as_bad (_("you must specify a single type only"));
2156 typeinfo
.eltype
= ntype
.el
[0];
2159 if (skip_past_char (&p
, '[') == SUCCESS
)
2162 /* We got a scalar index. */
2164 if (typeinfo
.defined
& NTA_HASINDEX
)
2166 as_bad (_("can't redefine the index of a scalar alias"));
2170 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2172 if (exp
.X_op
!= O_constant
)
2174 as_bad (_("scalar index must be constant"));
2178 typeinfo
.defined
|= NTA_HASINDEX
;
2179 typeinfo
.index
= exp
.X_add_number
;
2181 if (skip_past_char (&p
, ']') == FAIL
)
2183 as_bad (_("expecting ]"));
2188 namelen
= nameend
- newname
;
2189 namebuf
= alloca (namelen
+ 1);
2190 strncpy (namebuf
, newname
, namelen
);
2191 namebuf
[namelen
] = '\0';
2193 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2194 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2196 /* Insert name in all uppercase. */
2197 for (p
= namebuf
; *p
; p
++)
2200 if (strncmp (namebuf
, newname
, namelen
))
2201 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2202 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2204 /* Insert name in all lowercase. */
2205 for (p
= namebuf
; *p
; p
++)
2208 if (strncmp (namebuf
, newname
, namelen
))
2209 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2210 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2215 /* Should never be called, as .req goes between the alias and the
2216 register name, not at the beginning of the line. */
2218 s_req (int a ATTRIBUTE_UNUSED
)
2220 as_bad (_("invalid syntax for .req directive"));
2224 s_dn (int a ATTRIBUTE_UNUSED
)
2226 as_bad (_("invalid syntax for .dn directive"));
2230 s_qn (int a ATTRIBUTE_UNUSED
)
2232 as_bad (_("invalid syntax for .qn directive"));
2235 /* The .unreq directive deletes an alias which was previously defined
2236 by .req. For example:
2242 s_unreq (int a ATTRIBUTE_UNUSED
)
2247 name
= input_line_pointer
;
2249 while (*input_line_pointer
!= 0
2250 && *input_line_pointer
!= ' '
2251 && *input_line_pointer
!= '\n')
2252 ++input_line_pointer
;
2254 saved_char
= *input_line_pointer
;
2255 *input_line_pointer
= 0;
2258 as_bad (_("invalid syntax for .unreq directive"));
2261 struct reg_entry
*reg
= hash_find (arm_reg_hsh
, name
);
2264 as_bad (_("unknown register alias '%s'"), name
);
2265 else if (reg
->builtin
)
2266 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2270 hash_delete (arm_reg_hsh
, name
);
2271 free ((char *) reg
->name
);
2278 *input_line_pointer
= saved_char
;
2279 demand_empty_rest_of_line ();
2282 /* Directives: Instruction set selection. */
2285 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2286 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2287 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2288 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2290 static enum mstate mapstate
= MAP_UNDEFINED
;
2293 mapping_state (enum mstate state
)
2296 const char * symname
;
2299 if (mapstate
== state
)
2300 /* The mapping symbol has already been emitted.
2301 There is nothing else to do. */
2310 type
= BSF_NO_FLAGS
;
2314 type
= BSF_NO_FLAGS
;
2318 type
= BSF_NO_FLAGS
;
2326 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2328 symbolP
= symbol_new (symname
, now_seg
, (valueT
) frag_now_fix (), frag_now
);
2329 symbol_table_insert (symbolP
);
2330 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2335 THUMB_SET_FUNC (symbolP
, 0);
2336 ARM_SET_THUMB (symbolP
, 0);
2337 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2341 THUMB_SET_FUNC (symbolP
, 1);
2342 ARM_SET_THUMB (symbolP
, 1);
2343 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2352 #define mapping_state(x) /* nothing */
2355 /* Find the real, Thumb encoded start of a Thumb function. */
2358 find_real_start (symbolS
* symbolP
)
2361 const char * name
= S_GET_NAME (symbolP
);
2362 symbolS
* new_target
;
2364 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2365 #define STUB_NAME ".real_start_of"
2370 /* The compiler may generate BL instructions to local labels because
2371 it needs to perform a branch to a far away location. These labels
2372 do not have a corresponding ".real_start_of" label. We check
2373 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2374 the ".real_start_of" convention for nonlocal branches. */
2375 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2378 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2379 new_target
= symbol_find (real_start
);
2381 if (new_target
== NULL
)
2383 as_warn ("Failed to find real start of function: %s\n", name
);
2384 new_target
= symbolP
;
2391 opcode_select (int width
)
2398 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2399 as_bad (_("selected processor does not support THUMB opcodes"));
2402 /* No need to force the alignment, since we will have been
2403 coming from ARM mode, which is word-aligned. */
2404 record_alignment (now_seg
, 1);
2406 mapping_state (MAP_THUMB
);
2412 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2413 as_bad (_("selected processor does not support ARM opcodes"));
2418 frag_align (2, 0, 0);
2420 record_alignment (now_seg
, 1);
2422 mapping_state (MAP_ARM
);
2426 as_bad (_("invalid instruction size selected (%d)"), width
);
2431 s_arm (int ignore ATTRIBUTE_UNUSED
)
2434 demand_empty_rest_of_line ();
2438 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2441 demand_empty_rest_of_line ();
2445 s_code (int unused ATTRIBUTE_UNUSED
)
2449 temp
= get_absolute_expression ();
2454 opcode_select (temp
);
2458 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2463 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2465 /* If we are not already in thumb mode go into it, EVEN if
2466 the target processor does not support thumb instructions.
2467 This is used by gcc/config/arm/lib1funcs.asm for example
2468 to compile interworking support functions even if the
2469 target processor should not support interworking. */
2473 record_alignment (now_seg
, 1);
2476 demand_empty_rest_of_line ();
2480 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2484 /* The following label is the name/address of the start of a Thumb function.
2485 We need to know this for the interworking support. */
2486 label_is_thumb_function_name
= TRUE
;
2489 /* Perform a .set directive, but also mark the alias as
2490 being a thumb function. */
2493 s_thumb_set (int equiv
)
2495 /* XXX the following is a duplicate of the code for s_set() in read.c
2496 We cannot just call that code as we need to get at the symbol that
2503 /* Especial apologies for the random logic:
2504 This just grew, and could be parsed much more simply!
2506 name
= input_line_pointer
;
2507 delim
= get_symbol_end ();
2508 end_name
= input_line_pointer
;
2511 if (*input_line_pointer
!= ',')
2514 as_bad (_("expected comma after name \"%s\""), name
);
2516 ignore_rest_of_line ();
2520 input_line_pointer
++;
2523 if (name
[0] == '.' && name
[1] == '\0')
2525 /* XXX - this should not happen to .thumb_set. */
2529 if ((symbolP
= symbol_find (name
)) == NULL
2530 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2533 /* When doing symbol listings, play games with dummy fragments living
2534 outside the normal fragment chain to record the file and line info
2536 if (listing
& LISTING_SYMBOLS
)
2538 extern struct list_info_struct
* listing_tail
;
2539 fragS
* dummy_frag
= xmalloc (sizeof (fragS
));
2541 memset (dummy_frag
, 0, sizeof (fragS
));
2542 dummy_frag
->fr_type
= rs_fill
;
2543 dummy_frag
->line
= listing_tail
;
2544 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2545 dummy_frag
->fr_symbol
= symbolP
;
2549 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2552 /* "set" symbols are local unless otherwise specified. */
2553 SF_SET_LOCAL (symbolP
);
2554 #endif /* OBJ_COFF */
2555 } /* Make a new symbol. */
2557 symbol_table_insert (symbolP
);
2562 && S_IS_DEFINED (symbolP
)
2563 && S_GET_SEGMENT (symbolP
) != reg_section
)
2564 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2566 pseudo_set (symbolP
);
2568 demand_empty_rest_of_line ();
2570 /* XXX Now we come to the Thumb specific bit of code. */
2572 THUMB_SET_FUNC (symbolP
, 1);
2573 ARM_SET_THUMB (symbolP
, 1);
2574 #if defined OBJ_ELF || defined OBJ_COFF
2575 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2579 /* Directives: Mode selection. */
2581 /* .syntax [unified|divided] - choose the new unified syntax
2582 (same for Arm and Thumb encoding, modulo slight differences in what
2583 can be represented) or the old divergent syntax for each mode. */
2585 s_syntax (int unused ATTRIBUTE_UNUSED
)
2589 name
= input_line_pointer
;
2590 delim
= get_symbol_end ();
2592 if (!strcasecmp (name
, "unified"))
2593 unified_syntax
= TRUE
;
2594 else if (!strcasecmp (name
, "divided"))
2595 unified_syntax
= FALSE
;
2598 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2601 *input_line_pointer
= delim
;
2602 demand_empty_rest_of_line ();
2605 /* Directives: sectioning and alignment. */
2607 /* Same as s_align_ptwo but align 0 => align 2. */
2610 s_align (int unused ATTRIBUTE_UNUSED
)
2614 long max_alignment
= 15;
2616 temp
= get_absolute_expression ();
2617 if (temp
> max_alignment
)
2618 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2621 as_bad (_("alignment negative. 0 assumed."));
2625 if (*input_line_pointer
== ',')
2627 input_line_pointer
++;
2628 temp_fill
= get_absolute_expression ();
2636 /* Only make a frag if we HAVE to. */
2637 if (temp
&& !need_pass_2
)
2638 frag_align (temp
, (int) temp_fill
, 0);
2639 demand_empty_rest_of_line ();
2641 record_alignment (now_seg
, temp
);
2645 s_bss (int ignore ATTRIBUTE_UNUSED
)
2647 /* We don't support putting frags in the BSS segment, we fake it by
2648 marking in_bss, then looking at s_skip for clues. */
2649 subseg_set (bss_section
, 0);
2650 demand_empty_rest_of_line ();
2651 mapping_state (MAP_DATA
);
2655 s_even (int ignore ATTRIBUTE_UNUSED
)
2657 /* Never make frag if expect extra pass. */
2659 frag_align (1, 0, 0);
2661 record_alignment (now_seg
, 1);
2663 demand_empty_rest_of_line ();
2666 /* Directives: Literal pools. */
2668 static literal_pool
*
2669 find_literal_pool (void)
2671 literal_pool
* pool
;
2673 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2675 if (pool
->section
== now_seg
2676 && pool
->sub_section
== now_subseg
)
2683 static literal_pool
*
2684 find_or_make_literal_pool (void)
2686 /* Next literal pool ID number. */
2687 static unsigned int latest_pool_num
= 1;
2688 literal_pool
* pool
;
2690 pool
= find_literal_pool ();
2694 /* Create a new pool. */
2695 pool
= xmalloc (sizeof (* pool
));
2699 pool
->next_free_entry
= 0;
2700 pool
->section
= now_seg
;
2701 pool
->sub_section
= now_subseg
;
2702 pool
->next
= list_of_pools
;
2703 pool
->symbol
= NULL
;
2705 /* Add it to the list. */
2706 list_of_pools
= pool
;
2709 /* New pools, and emptied pools, will have a NULL symbol. */
2710 if (pool
->symbol
== NULL
)
2712 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2713 (valueT
) 0, &zero_address_frag
);
2714 pool
->id
= latest_pool_num
++;
2721 /* Add the literal in the global 'inst'
2722 structure to the relevent literal pool. */
2725 add_to_lit_pool (void)
2727 literal_pool
* pool
;
2730 pool
= find_or_make_literal_pool ();
2732 /* Check if this literal value is already in the pool. */
2733 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2735 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2736 && (inst
.reloc
.exp
.X_op
== O_constant
)
2737 && (pool
->literals
[entry
].X_add_number
2738 == inst
.reloc
.exp
.X_add_number
)
2739 && (pool
->literals
[entry
].X_unsigned
2740 == inst
.reloc
.exp
.X_unsigned
))
2743 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2744 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2745 && (pool
->literals
[entry
].X_add_number
2746 == inst
.reloc
.exp
.X_add_number
)
2747 && (pool
->literals
[entry
].X_add_symbol
2748 == inst
.reloc
.exp
.X_add_symbol
)
2749 && (pool
->literals
[entry
].X_op_symbol
2750 == inst
.reloc
.exp
.X_op_symbol
))
2754 /* Do we need to create a new entry? */
2755 if (entry
== pool
->next_free_entry
)
2757 if (entry
>= MAX_LITERAL_POOL_SIZE
)
2759 inst
.error
= _("literal pool overflow");
2763 pool
->literals
[entry
] = inst
.reloc
.exp
;
2764 pool
->next_free_entry
+= 1;
2767 inst
.reloc
.exp
.X_op
= O_symbol
;
2768 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
2769 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
2774 /* Can't use symbol_new here, so have to create a symbol and then at
2775 a later date assign it a value. Thats what these functions do. */
2778 symbol_locate (symbolS
* symbolP
,
2779 const char * name
, /* It is copied, the caller can modify. */
2780 segT segment
, /* Segment identifier (SEG_<something>). */
2781 valueT valu
, /* Symbol value. */
2782 fragS
* frag
) /* Associated fragment. */
2784 unsigned int name_length
;
2785 char * preserved_copy_of_name
;
2787 name_length
= strlen (name
) + 1; /* +1 for \0. */
2788 obstack_grow (¬es
, name
, name_length
);
2789 preserved_copy_of_name
= obstack_finish (¬es
);
2791 #ifdef tc_canonicalize_symbol_name
2792 preserved_copy_of_name
=
2793 tc_canonicalize_symbol_name (preserved_copy_of_name
);
2796 S_SET_NAME (symbolP
, preserved_copy_of_name
);
2798 S_SET_SEGMENT (symbolP
, segment
);
2799 S_SET_VALUE (symbolP
, valu
);
2800 symbol_clear_list_pointers (symbolP
);
2802 symbol_set_frag (symbolP
, frag
);
2804 /* Link to end of symbol chain. */
2806 extern int symbol_table_frozen
;
2808 if (symbol_table_frozen
)
2812 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
2814 obj_symbol_new_hook (symbolP
);
2816 #ifdef tc_symbol_new_hook
2817 tc_symbol_new_hook (symbolP
);
2821 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
2822 #endif /* DEBUG_SYMS */
2827 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
2830 literal_pool
* pool
;
2833 pool
= find_literal_pool ();
2835 || pool
->symbol
== NULL
2836 || pool
->next_free_entry
== 0)
2839 mapping_state (MAP_DATA
);
2841 /* Align pool as you have word accesses.
2842 Only make a frag if we have to. */
2844 frag_align (2, 0, 0);
2846 record_alignment (now_seg
, 2);
2848 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
2850 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
2851 (valueT
) frag_now_fix (), frag_now
);
2852 symbol_table_insert (pool
->symbol
);
2854 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
2856 #if defined OBJ_COFF || defined OBJ_ELF
2857 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
2860 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2861 /* First output the expression in the instruction to the pool. */
2862 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
2864 /* Mark the pool as empty. */
2865 pool
->next_free_entry
= 0;
2866 pool
->symbol
= NULL
;
2870 /* Forward declarations for functions below, in the MD interface
2872 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
2873 static valueT
create_unwind_entry (int);
2874 static void start_unwind_section (const segT
, int);
2875 static void add_unwind_opcode (valueT
, int);
2876 static void flush_pending_unwind (void);
2878 /* Directives: Data. */
2881 s_arm_elf_cons (int nbytes
)
2885 #ifdef md_flush_pending_output
2886 md_flush_pending_output ();
2889 if (is_it_end_of_statement ())
2891 demand_empty_rest_of_line ();
2895 #ifdef md_cons_align
2896 md_cons_align (nbytes
);
2899 mapping_state (MAP_DATA
);
2903 char *base
= input_line_pointer
;
2907 if (exp
.X_op
!= O_symbol
)
2908 emit_expr (&exp
, (unsigned int) nbytes
);
2911 char *before_reloc
= input_line_pointer
;
2912 reloc
= parse_reloc (&input_line_pointer
);
2915 as_bad (_("unrecognized relocation suffix"));
2916 ignore_rest_of_line ();
2919 else if (reloc
== BFD_RELOC_UNUSED
)
2920 emit_expr (&exp
, (unsigned int) nbytes
);
2923 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
2924 int size
= bfd_get_reloc_size (howto
);
2926 if (reloc
== BFD_RELOC_ARM_PLT32
)
2928 as_bad (_("(plt) is only valid on branch targets"));
2929 reloc
= BFD_RELOC_UNUSED
;
2934 as_bad (_("%s relocations do not fit in %d bytes"),
2935 howto
->name
, nbytes
);
2938 /* We've parsed an expression stopping at O_symbol.
2939 But there may be more expression left now that we
2940 have parsed the relocation marker. Parse it again.
2941 XXX Surely there is a cleaner way to do this. */
2942 char *p
= input_line_pointer
;
2944 char *save_buf
= alloca (input_line_pointer
- base
);
2945 memcpy (save_buf
, base
, input_line_pointer
- base
);
2946 memmove (base
+ (input_line_pointer
- before_reloc
),
2947 base
, before_reloc
- base
);
2949 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
2951 memcpy (base
, save_buf
, p
- base
);
2953 offset
= nbytes
- size
;
2954 p
= frag_more ((int) nbytes
);
2955 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
2956 size
, &exp
, 0, reloc
);
2961 while (*input_line_pointer
++ == ',');
2963 /* Put terminator back into stream. */
2964 input_line_pointer
--;
2965 demand_empty_rest_of_line ();
2969 /* Parse a .rel31 directive. */
2972 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
2979 if (*input_line_pointer
== '1')
2980 highbit
= 0x80000000;
2981 else if (*input_line_pointer
!= '0')
2982 as_bad (_("expected 0 or 1"));
2984 input_line_pointer
++;
2985 if (*input_line_pointer
!= ',')
2986 as_bad (_("missing comma"));
2987 input_line_pointer
++;
2989 #ifdef md_flush_pending_output
2990 md_flush_pending_output ();
2993 #ifdef md_cons_align
2997 mapping_state (MAP_DATA
);
3002 md_number_to_chars (p
, highbit
, 4);
3003 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3004 BFD_RELOC_ARM_PREL31
);
3006 demand_empty_rest_of_line ();
3009 /* Directives: AEABI stack-unwind tables. */
3011 /* Parse an unwind_fnstart directive. Simply records the current location. */
3014 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3016 demand_empty_rest_of_line ();
3017 /* Mark the start of the function. */
3018 unwind
.proc_start
= expr_build_dot ();
3020 /* Reset the rest of the unwind info. */
3021 unwind
.opcode_count
= 0;
3022 unwind
.table_entry
= NULL
;
3023 unwind
.personality_routine
= NULL
;
3024 unwind
.personality_index
= -1;
3025 unwind
.frame_size
= 0;
3026 unwind
.fp_offset
= 0;
3029 unwind
.sp_restored
= 0;
3033 /* Parse a handlerdata directive. Creates the exception handling table entry
3034 for the function. */
3037 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3039 demand_empty_rest_of_line ();
3040 if (unwind
.table_entry
)
3041 as_bad (_("dupicate .handlerdata directive"));
3043 create_unwind_entry (1);
3046 /* Parse an unwind_fnend directive. Generates the index table entry. */
3049 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3055 demand_empty_rest_of_line ();
3057 /* Add eh table entry. */
3058 if (unwind
.table_entry
== NULL
)
3059 val
= create_unwind_entry (0);
3063 /* Add index table entry. This is two words. */
3064 start_unwind_section (unwind
.saved_seg
, 1);
3065 frag_align (2, 0, 0);
3066 record_alignment (now_seg
, 2);
3068 ptr
= frag_more (8);
3069 where
= frag_now_fix () - 8;
3071 /* Self relative offset of the function start. */
3072 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3073 BFD_RELOC_ARM_PREL31
);
3075 /* Indicate dependency on EHABI-defined personality routines to the
3076 linker, if it hasn't been done already. */
3077 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3078 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3080 static const char *const name
[] = {
3081 "__aeabi_unwind_cpp_pr0",
3082 "__aeabi_unwind_cpp_pr1",
3083 "__aeabi_unwind_cpp_pr2"
3085 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3086 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3087 marked_pr_dependency
|= 1 << unwind
.personality_index
;
3088 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3089 = marked_pr_dependency
;
3093 /* Inline exception table entry. */
3094 md_number_to_chars (ptr
+ 4, val
, 4);
3096 /* Self relative offset of the table entry. */
3097 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3098 BFD_RELOC_ARM_PREL31
);
3100 /* Restore the original section. */
3101 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3105 /* Parse an unwind_cantunwind directive. */
3108 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3110 demand_empty_rest_of_line ();
3111 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3112 as_bad (_("personality routine specified for cantunwind frame"));
3114 unwind
.personality_index
= -2;
3118 /* Parse a personalityindex directive. */
3121 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3125 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3126 as_bad (_("duplicate .personalityindex directive"));
3130 if (exp
.X_op
!= O_constant
3131 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3133 as_bad (_("bad personality routine number"));
3134 ignore_rest_of_line ();
3138 unwind
.personality_index
= exp
.X_add_number
;
3140 demand_empty_rest_of_line ();
3144 /* Parse a personality directive. */
3147 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3151 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3152 as_bad (_("duplicate .personality directive"));
3154 name
= input_line_pointer
;
3155 c
= get_symbol_end ();
3156 p
= input_line_pointer
;
3157 unwind
.personality_routine
= symbol_find_or_make (name
);
3159 demand_empty_rest_of_line ();
3163 /* Parse a directive saving core registers. */
3166 s_arm_unwind_save_core (void)
3172 range
= parse_reg_list (&input_line_pointer
);
3175 as_bad (_("expected register list"));
3176 ignore_rest_of_line ();
3180 demand_empty_rest_of_line ();
3182 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3183 into .unwind_save {..., sp...}. We aren't bothered about the value of
3184 ip because it is clobbered by calls. */
3185 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3186 && (range
& 0x3000) == 0x1000)
3188 unwind
.opcode_count
--;
3189 unwind
.sp_restored
= 0;
3190 range
= (range
| 0x2000) & ~0x1000;
3191 unwind
.pending_offset
= 0;
3197 /* See if we can use the short opcodes. These pop a block of up to 8
3198 registers starting with r4, plus maybe r14. */
3199 for (n
= 0; n
< 8; n
++)
3201 /* Break at the first non-saved register. */
3202 if ((range
& (1 << (n
+ 4))) == 0)
3205 /* See if there are any other bits set. */
3206 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3208 /* Use the long form. */
3209 op
= 0x8000 | ((range
>> 4) & 0xfff);
3210 add_unwind_opcode (op
, 2);
3214 /* Use the short form. */
3216 op
= 0xa8; /* Pop r14. */
3218 op
= 0xa0; /* Do not pop r14. */
3220 add_unwind_opcode (op
, 1);
3227 op
= 0xb100 | (range
& 0xf);
3228 add_unwind_opcode (op
, 2);
3231 /* Record the number of bytes pushed. */
3232 for (n
= 0; n
< 16; n
++)
3234 if (range
& (1 << n
))
3235 unwind
.frame_size
+= 4;
3240 /* Parse a directive saving FPA registers. */
3243 s_arm_unwind_save_fpa (int reg
)
3249 /* Get Number of registers to transfer. */
3250 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3253 exp
.X_op
= O_illegal
;
3255 if (exp
.X_op
!= O_constant
)
3257 as_bad (_("expected , <constant>"));
3258 ignore_rest_of_line ();
3262 num_regs
= exp
.X_add_number
;
3264 if (num_regs
< 1 || num_regs
> 4)
3266 as_bad (_("number of registers must be in the range [1:4]"));
3267 ignore_rest_of_line ();
3271 demand_empty_rest_of_line ();
3276 op
= 0xb4 | (num_regs
- 1);
3277 add_unwind_opcode (op
, 1);
3282 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3283 add_unwind_opcode (op
, 2);
3285 unwind
.frame_size
+= num_regs
* 12;
3289 /* Parse a directive saving VFP registers for ARMv6 and above. */
3292 s_arm_unwind_save_vfp_armv6 (void)
3297 int num_vfpv3_regs
= 0;
3298 int num_regs_below_16
;
3300 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3303 as_bad (_("expected register list"));
3304 ignore_rest_of_line ();
3308 demand_empty_rest_of_line ();
3310 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3311 than FSTMX/FLDMX-style ones). */
3313 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3315 num_vfpv3_regs
= count
;
3316 else if (start
+ count
> 16)
3317 num_vfpv3_regs
= start
+ count
- 16;
3319 if (num_vfpv3_regs
> 0)
3321 int start_offset
= start
> 16 ? start
- 16 : 0;
3322 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3323 add_unwind_opcode (op
, 2);
3326 /* Generate opcode for registers numbered in the range 0 .. 15. */
3327 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3328 assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3329 if (num_regs_below_16
> 0)
3331 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3332 add_unwind_opcode (op
, 2);
3335 unwind
.frame_size
+= count
* 8;
3339 /* Parse a directive saving VFP registers for pre-ARMv6. */
3342 s_arm_unwind_save_vfp (void)
3348 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3351 as_bad (_("expected register list"));
3352 ignore_rest_of_line ();
3356 demand_empty_rest_of_line ();
3361 op
= 0xb8 | (count
- 1);
3362 add_unwind_opcode (op
, 1);
3367 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3368 add_unwind_opcode (op
, 2);
3370 unwind
.frame_size
+= count
* 8 + 4;
3374 /* Parse a directive saving iWMMXt data registers. */
3377 s_arm_unwind_save_mmxwr (void)
3385 if (*input_line_pointer
== '{')
3386 input_line_pointer
++;
3390 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3394 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3399 as_tsktsk (_("register list not in ascending order"));
3402 if (*input_line_pointer
== '-')
3404 input_line_pointer
++;
3405 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3408 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3411 else if (reg
>= hi_reg
)
3413 as_bad (_("bad register range"));
3416 for (; reg
< hi_reg
; reg
++)
3420 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3422 if (*input_line_pointer
== '}')
3423 input_line_pointer
++;
3425 demand_empty_rest_of_line ();
3427 /* Generate any deferred opcodes because we're going to be looking at
3429 flush_pending_unwind ();
3431 for (i
= 0; i
< 16; i
++)
3433 if (mask
& (1 << i
))
3434 unwind
.frame_size
+= 8;
3437 /* Attempt to combine with a previous opcode. We do this because gcc
3438 likes to output separate unwind directives for a single block of
3440 if (unwind
.opcode_count
> 0)
3442 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3443 if ((i
& 0xf8) == 0xc0)
3446 /* Only merge if the blocks are contiguous. */
3449 if ((mask
& 0xfe00) == (1 << 9))
3451 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3452 unwind
.opcode_count
--;
3455 else if (i
== 6 && unwind
.opcode_count
>= 2)
3457 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3461 op
= 0xffff << (reg
- 1);
3463 && ((mask
& op
) == (1u << (reg
- 1))))
3465 op
= (1 << (reg
+ i
+ 1)) - 1;
3466 op
&= ~((1 << reg
) - 1);
3468 unwind
.opcode_count
-= 2;
3475 /* We want to generate opcodes in the order the registers have been
3476 saved, ie. descending order. */
3477 for (reg
= 15; reg
>= -1; reg
--)
3479 /* Save registers in blocks. */
3481 || !(mask
& (1 << reg
)))
3483 /* We found an unsaved reg. Generate opcodes to save the
3484 preceeding block. */
3490 op
= 0xc0 | (hi_reg
- 10);
3491 add_unwind_opcode (op
, 1);
3496 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3497 add_unwind_opcode (op
, 2);
3506 ignore_rest_of_line ();
3510 s_arm_unwind_save_mmxwcg (void)
3517 if (*input_line_pointer
== '{')
3518 input_line_pointer
++;
3522 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3526 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3532 as_tsktsk (_("register list not in ascending order"));
3535 if (*input_line_pointer
== '-')
3537 input_line_pointer
++;
3538 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3541 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3544 else if (reg
>= hi_reg
)
3546 as_bad (_("bad register range"));
3549 for (; reg
< hi_reg
; reg
++)
3553 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3555 if (*input_line_pointer
== '}')
3556 input_line_pointer
++;
3558 demand_empty_rest_of_line ();
3560 /* Generate any deferred opcodes because we're going to be looking at
3562 flush_pending_unwind ();
3564 for (reg
= 0; reg
< 16; reg
++)
3566 if (mask
& (1 << reg
))
3567 unwind
.frame_size
+= 4;
3570 add_unwind_opcode (op
, 2);
3573 ignore_rest_of_line ();
3577 /* Parse an unwind_save directive.
3578 If the argument is non-zero, this is a .vsave directive. */
3581 s_arm_unwind_save (int arch_v6
)
3584 struct reg_entry
*reg
;
3585 bfd_boolean had_brace
= FALSE
;
3587 /* Figure out what sort of save we have. */
3588 peek
= input_line_pointer
;
3596 reg
= arm_reg_parse_multi (&peek
);
3600 as_bad (_("register expected"));
3601 ignore_rest_of_line ();
3610 as_bad (_("FPA .unwind_save does not take a register list"));
3611 ignore_rest_of_line ();
3614 s_arm_unwind_save_fpa (reg
->number
);
3617 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
3620 s_arm_unwind_save_vfp_armv6 ();
3622 s_arm_unwind_save_vfp ();
3624 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
3625 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
3628 as_bad (_(".unwind_save does not support this kind of register"));
3629 ignore_rest_of_line ();
3634 /* Parse an unwind_movsp directive. */
3637 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
3643 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3646 as_bad (_(reg_expected_msgs
[REG_TYPE_RN
]));
3647 ignore_rest_of_line ();
3651 /* Optional constant. */
3652 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3654 if (immediate_for_directive (&offset
) == FAIL
)
3660 demand_empty_rest_of_line ();
3662 if (reg
== REG_SP
|| reg
== REG_PC
)
3664 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
3668 if (unwind
.fp_reg
!= REG_SP
)
3669 as_bad (_("unexpected .unwind_movsp directive"));
3671 /* Generate opcode to restore the value. */
3673 add_unwind_opcode (op
, 1);
3675 /* Record the information for later. */
3676 unwind
.fp_reg
= reg
;
3677 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3678 unwind
.sp_restored
= 1;
3681 /* Parse an unwind_pad directive. */
3684 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
3688 if (immediate_for_directive (&offset
) == FAIL
)
3693 as_bad (_("stack increment must be multiple of 4"));
3694 ignore_rest_of_line ();
3698 /* Don't generate any opcodes, just record the details for later. */
3699 unwind
.frame_size
+= offset
;
3700 unwind
.pending_offset
+= offset
;
3702 demand_empty_rest_of_line ();
3705 /* Parse an unwind_setfp directive. */
3708 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
3714 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3715 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3718 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3720 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
3722 as_bad (_("expected <reg>, <reg>"));
3723 ignore_rest_of_line ();
3727 /* Optional constant. */
3728 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3730 if (immediate_for_directive (&offset
) == FAIL
)
3736 demand_empty_rest_of_line ();
3738 if (sp_reg
!= 13 && sp_reg
!= unwind
.fp_reg
)
3740 as_bad (_("register must be either sp or set by a previous"
3741 "unwind_movsp directive"));
3745 /* Don't generate any opcodes, just record the information for later. */
3746 unwind
.fp_reg
= fp_reg
;
3749 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3751 unwind
.fp_offset
-= offset
;
3754 /* Parse an unwind_raw directive. */
3757 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
3760 /* This is an arbitrary limit. */
3761 unsigned char op
[16];
3765 if (exp
.X_op
== O_constant
3766 && skip_past_comma (&input_line_pointer
) != FAIL
)
3768 unwind
.frame_size
+= exp
.X_add_number
;
3772 exp
.X_op
= O_illegal
;
3774 if (exp
.X_op
!= O_constant
)
3776 as_bad (_("expected <offset>, <opcode>"));
3777 ignore_rest_of_line ();
3783 /* Parse the opcode. */
3788 as_bad (_("unwind opcode too long"));
3789 ignore_rest_of_line ();
3791 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
3793 as_bad (_("invalid unwind opcode"));
3794 ignore_rest_of_line ();
3797 op
[count
++] = exp
.X_add_number
;
3799 /* Parse the next byte. */
3800 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3806 /* Add the opcode bytes in reverse order. */
3808 add_unwind_opcode (op
[count
], 1);
3810 demand_empty_rest_of_line ();
3814 /* Parse a .eabi_attribute directive. */
3817 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
3820 bfd_boolean is_string
;
3827 if (exp
.X_op
!= O_constant
)
3830 tag
= exp
.X_add_number
;
3831 if (tag
== 4 || tag
== 5 || tag
== 32 || (tag
> 32 && (tag
& 1) != 0))
3836 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3838 if (tag
== 32 || !is_string
)
3841 if (exp
.X_op
!= O_constant
)
3843 as_bad (_("expected numeric constant"));
3844 ignore_rest_of_line ();
3847 i
= exp
.X_add_number
;
3849 if (tag
== Tag_compatibility
3850 && skip_past_comma (&input_line_pointer
) == FAIL
)
3852 as_bad (_("expected comma"));
3853 ignore_rest_of_line ();
3858 skip_whitespace(input_line_pointer
);
3859 if (*input_line_pointer
!= '"')
3861 input_line_pointer
++;
3862 s
= input_line_pointer
;
3863 while (*input_line_pointer
&& *input_line_pointer
!= '"')
3864 input_line_pointer
++;
3865 if (*input_line_pointer
!= '"')
3867 saved_char
= *input_line_pointer
;
3868 *input_line_pointer
= 0;
3876 if (tag
== Tag_compatibility
)
3877 elf32_arm_add_eabi_attr_compat (stdoutput
, i
, s
);
3879 elf32_arm_add_eabi_attr_string (stdoutput
, tag
, s
);
3881 elf32_arm_add_eabi_attr_int (stdoutput
, tag
, i
);
3885 *input_line_pointer
= saved_char
;
3886 input_line_pointer
++;
3888 demand_empty_rest_of_line ();
3891 as_bad (_("bad string constant"));
3892 ignore_rest_of_line ();
3895 as_bad (_("expected <tag> , <value>"));
3896 ignore_rest_of_line ();
3898 #endif /* OBJ_ELF */
3900 static void s_arm_arch (int);
3901 static void s_arm_object_arch (int);
3902 static void s_arm_cpu (int);
3903 static void s_arm_fpu (int);
3908 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
3915 if (exp
.X_op
== O_symbol
)
3916 exp
.X_op
= O_secrel
;
3918 emit_expr (&exp
, 4);
3920 while (*input_line_pointer
++ == ',');
3922 input_line_pointer
--;
3923 demand_empty_rest_of_line ();
3927 /* This table describes all the machine specific pseudo-ops the assembler
3928 has to support. The fields are:
3929 pseudo-op name without dot
3930 function to call to execute this pseudo-op
3931 Integer arg to pass to the function. */
3933 const pseudo_typeS md_pseudo_table
[] =
3935 /* Never called because '.req' does not start a line. */
3936 { "req", s_req
, 0 },
3937 /* Following two are likewise never called. */
3940 { "unreq", s_unreq
, 0 },
3941 { "bss", s_bss
, 0 },
3942 { "align", s_align
, 0 },
3943 { "arm", s_arm
, 0 },
3944 { "thumb", s_thumb
, 0 },
3945 { "code", s_code
, 0 },
3946 { "force_thumb", s_force_thumb
, 0 },
3947 { "thumb_func", s_thumb_func
, 0 },
3948 { "thumb_set", s_thumb_set
, 0 },
3949 { "even", s_even
, 0 },
3950 { "ltorg", s_ltorg
, 0 },
3951 { "pool", s_ltorg
, 0 },
3952 { "syntax", s_syntax
, 0 },
3953 { "cpu", s_arm_cpu
, 0 },
3954 { "arch", s_arm_arch
, 0 },
3955 { "object_arch", s_arm_object_arch
, 0 },
3956 { "fpu", s_arm_fpu
, 0 },
3958 { "word", s_arm_elf_cons
, 4 },
3959 { "long", s_arm_elf_cons
, 4 },
3960 { "rel31", s_arm_rel31
, 0 },
3961 { "fnstart", s_arm_unwind_fnstart
, 0 },
3962 { "fnend", s_arm_unwind_fnend
, 0 },
3963 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
3964 { "personality", s_arm_unwind_personality
, 0 },
3965 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
3966 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
3967 { "save", s_arm_unwind_save
, 0 },
3968 { "vsave", s_arm_unwind_save
, 1 },
3969 { "movsp", s_arm_unwind_movsp
, 0 },
3970 { "pad", s_arm_unwind_pad
, 0 },
3971 { "setfp", s_arm_unwind_setfp
, 0 },
3972 { "unwind_raw", s_arm_unwind_raw
, 0 },
3973 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
3977 /* These are used for dwarf. */
3981 /* These are used for dwarf2. */
3982 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
3983 { "loc", dwarf2_directive_loc
, 0 },
3984 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
3986 { "extend", float_cons
, 'x' },
3987 { "ldouble", float_cons
, 'x' },
3988 { "packed", float_cons
, 'p' },
3990 {"secrel32", pe_directive_secrel
, 0},
3995 /* Parser functions used exclusively in instruction operands. */
3997 /* Generic immediate-value read function for use in insn parsing.
3998 STR points to the beginning of the immediate (the leading #);
3999 VAL receives the value; if the value is outside [MIN, MAX]
4000 issue an error. PREFIX_OPT is true if the immediate prefix is
4004 parse_immediate (char **str
, int *val
, int min
, int max
,
4005 bfd_boolean prefix_opt
)
4008 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4009 if (exp
.X_op
!= O_constant
)
4011 inst
.error
= _("constant expression required");
4015 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4017 inst
.error
= _("immediate value out of range");
4021 *val
= exp
.X_add_number
;
4025 /* Less-generic immediate-value read function with the possibility of loading a
4026 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4027 instructions. Puts the result directly in inst.operands[i]. */
4030 parse_big_immediate (char **str
, int i
)
4035 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4037 if (exp
.X_op
== O_constant
)
4039 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4040 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4041 O_constant. We have to be careful not to break compilation for
4042 32-bit X_add_number, though. */
4043 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4045 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4046 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4047 inst
.operands
[i
].regisimm
= 1;
4050 else if (exp
.X_op
== O_big
4051 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4052 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4054 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4055 /* Bignums have their least significant bits in
4056 generic_bignum[0]. Make sure we put 32 bits in imm and
4057 32 bits in reg, in a (hopefully) portable way. */
4058 assert (parts
!= 0);
4059 inst
.operands
[i
].imm
= 0;
4060 for (j
= 0; j
< parts
; j
++, idx
++)
4061 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4062 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4063 inst
.operands
[i
].reg
= 0;
4064 for (j
= 0; j
< parts
; j
++, idx
++)
4065 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4066 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4067 inst
.operands
[i
].regisimm
= 1;
4077 /* Returns the pseudo-register number of an FPA immediate constant,
4078 or FAIL if there isn't a valid constant here. */
4081 parse_fpa_immediate (char ** str
)
4083 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4089 /* First try and match exact strings, this is to guarantee
4090 that some formats will work even for cross assembly. */
4092 for (i
= 0; fp_const
[i
]; i
++)
4094 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4098 *str
+= strlen (fp_const
[i
]);
4099 if (is_end_of_line
[(unsigned char) **str
])
4105 /* Just because we didn't get a match doesn't mean that the constant
4106 isn't valid, just that it is in a format that we don't
4107 automatically recognize. Try parsing it with the standard
4108 expression routines. */
4110 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4112 /* Look for a raw floating point number. */
4113 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4114 && is_end_of_line
[(unsigned char) *save_in
])
4116 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4118 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4120 if (words
[j
] != fp_values
[i
][j
])
4124 if (j
== MAX_LITTLENUMS
)
4132 /* Try and parse a more complex expression, this will probably fail
4133 unless the code uses a floating point prefix (eg "0f"). */
4134 save_in
= input_line_pointer
;
4135 input_line_pointer
= *str
;
4136 if (expression (&exp
) == absolute_section
4137 && exp
.X_op
== O_big
4138 && exp
.X_add_number
< 0)
4140 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4142 if (gen_to_words (words
, 5, (long) 15) == 0)
4144 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4146 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4148 if (words
[j
] != fp_values
[i
][j
])
4152 if (j
== MAX_LITTLENUMS
)
4154 *str
= input_line_pointer
;
4155 input_line_pointer
= save_in
;
4162 *str
= input_line_pointer
;
4163 input_line_pointer
= save_in
;
4164 inst
.error
= _("invalid FPA immediate expression");
4168 /* Returns 1 if a number has "quarter-precision" float format
4169 0baBbbbbbc defgh000 00000000 00000000. */
4172 is_quarter_float (unsigned imm
)
4174 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4175 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4178 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4179 0baBbbbbbc defgh000 00000000 00000000.
4180 The minus-zero case needs special handling, since it can't be encoded in the
4181 "quarter-precision" float format, but can nonetheless be loaded as an integer
4185 parse_qfloat_immediate (char **ccp
, int *immed
)
4188 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4190 skip_past_char (&str
, '#');
4192 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4194 unsigned fpword
= 0;
4197 /* Our FP word must be 32 bits (single-precision FP). */
4198 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4200 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4204 if (is_quarter_float (fpword
) || fpword
== 0x80000000)
4217 /* Shift operands. */
4220 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4223 struct asm_shift_name
4226 enum shift_kind kind
;
4229 /* Third argument to parse_shift. */
4230 enum parse_shift_mode
4232 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4233 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4234 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4235 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4236 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4239 /* Parse a <shift> specifier on an ARM data processing instruction.
4240 This has three forms:
4242 (LSL|LSR|ASL|ASR|ROR) Rs
4243 (LSL|LSR|ASL|ASR|ROR) #imm
4246 Note that ASL is assimilated to LSL in the instruction encoding, and
4247 RRX to ROR #0 (which cannot be written as such). */
4250 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4252 const struct asm_shift_name
*shift_name
;
4253 enum shift_kind shift
;
4258 for (p
= *str
; ISALPHA (*p
); p
++)
4263 inst
.error
= _("shift expression expected");
4267 shift_name
= hash_find_n (arm_shift_hsh
, *str
, p
- *str
);
4269 if (shift_name
== NULL
)
4271 inst
.error
= _("shift expression expected");
4275 shift
= shift_name
->kind
;
4279 case NO_SHIFT_RESTRICT
:
4280 case SHIFT_IMMEDIATE
: break;
4282 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4283 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4285 inst
.error
= _("'LSL' or 'ASR' required");
4290 case SHIFT_LSL_IMMEDIATE
:
4291 if (shift
!= SHIFT_LSL
)
4293 inst
.error
= _("'LSL' required");
4298 case SHIFT_ASR_IMMEDIATE
:
4299 if (shift
!= SHIFT_ASR
)
4301 inst
.error
= _("'ASR' required");
4309 if (shift
!= SHIFT_RRX
)
4311 /* Whitespace can appear here if the next thing is a bare digit. */
4312 skip_whitespace (p
);
4314 if (mode
== NO_SHIFT_RESTRICT
4315 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4317 inst
.operands
[i
].imm
= reg
;
4318 inst
.operands
[i
].immisreg
= 1;
4320 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4323 inst
.operands
[i
].shift_kind
= shift
;
4324 inst
.operands
[i
].shifted
= 1;
4329 /* Parse a <shifter_operand> for an ARM data processing instruction:
4332 #<immediate>, <rotate>
4336 where <shift> is defined by parse_shift above, and <rotate> is a
4337 multiple of 2 between 0 and 30. Validation of immediate operands
4338 is deferred to md_apply_fix. */
4341 parse_shifter_operand (char **str
, int i
)
4346 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4348 inst
.operands
[i
].reg
= value
;
4349 inst
.operands
[i
].isreg
= 1;
4351 /* parse_shift will override this if appropriate */
4352 inst
.reloc
.exp
.X_op
= O_constant
;
4353 inst
.reloc
.exp
.X_add_number
= 0;
4355 if (skip_past_comma (str
) == FAIL
)
4358 /* Shift operation on register. */
4359 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4362 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4365 if (skip_past_comma (str
) == SUCCESS
)
4367 /* #x, y -- ie explicit rotation by Y. */
4368 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
4371 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4373 inst
.error
= _("constant expression expected");
4377 value
= expr
.X_add_number
;
4378 if (value
< 0 || value
> 30 || value
% 2 != 0)
4380 inst
.error
= _("invalid rotation");
4383 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4385 inst
.error
= _("invalid constant");
4389 /* Convert to decoded value. md_apply_fix will put it back. */
4390 inst
.reloc
.exp
.X_add_number
4391 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4392 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4395 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4396 inst
.reloc
.pc_rel
= 0;
4400 /* Group relocation information. Each entry in the table contains the
4401 textual name of the relocation as may appear in assembler source
4402 and must end with a colon.
4403 Along with this textual name are the relocation codes to be used if
4404 the corresponding instruction is an ALU instruction (ADD or SUB only),
4405 an LDR, an LDRS, or an LDC. */
4407 struct group_reloc_table_entry
4418 /* Varieties of non-ALU group relocation. */
4425 static struct group_reloc_table_entry group_reloc_table
[] =
4426 { /* Program counter relative: */
4428 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4433 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4434 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4435 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4436 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4438 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4443 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4444 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4445 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4446 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4448 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4449 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4450 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4451 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4452 /* Section base relative */
4454 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4459 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4460 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4461 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4462 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4464 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4469 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4470 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4471 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4472 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4474 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4475 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4476 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4477 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4479 /* Given the address of a pointer pointing to the textual name of a group
4480 relocation as may appear in assembler source, attempt to find its details
4481 in group_reloc_table. The pointer will be updated to the character after
4482 the trailing colon. On failure, FAIL will be returned; SUCCESS
4483 otherwise. On success, *entry will be updated to point at the relevant
4484 group_reloc_table entry. */
4487 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4490 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4492 int length
= strlen (group_reloc_table
[i
].name
);
4494 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0 &&
4495 (*str
)[length
] == ':')
4497 *out
= &group_reloc_table
[i
];
4498 *str
+= (length
+ 1);
4506 /* Parse a <shifter_operand> for an ARM data processing instruction
4507 (as for parse_shifter_operand) where group relocations are allowed:
4510 #<immediate>, <rotate>
4511 #:<group_reloc>:<expression>
4515 where <group_reloc> is one of the strings defined in group_reloc_table.
4516 The hashes are optional.
4518 Everything else is as for parse_shifter_operand. */
4520 static parse_operand_result
4521 parse_shifter_operand_group_reloc (char **str
, int i
)
4523 /* Determine if we have the sequence of characters #: or just :
4524 coming next. If we do, then we check for a group relocation.
4525 If we don't, punt the whole lot to parse_shifter_operand. */
4527 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4528 || (*str
)[0] == ':')
4530 struct group_reloc_table_entry
*entry
;
4532 if ((*str
)[0] == '#')
4537 /* Try to parse a group relocation. Anything else is an error. */
4538 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4540 inst
.error
= _("unknown group relocation");
4541 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4544 /* We now have the group relocation table entry corresponding to
4545 the name in the assembler source. Next, we parse the expression. */
4546 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4547 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4549 /* Record the relocation type (always the ALU variant here). */
4550 inst
.reloc
.type
= entry
->alu_code
;
4551 assert (inst
.reloc
.type
!= 0);
4553 return PARSE_OPERAND_SUCCESS
;
4556 return parse_shifter_operand (str
, i
) == SUCCESS
4557 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4559 /* Never reached. */
4562 /* Parse all forms of an ARM address expression. Information is written
4563 to inst.operands[i] and/or inst.reloc.
4565 Preindexed addressing (.preind=1):
4567 [Rn, #offset] .reg=Rn .reloc.exp=offset
4568 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4569 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4570 .shift_kind=shift .reloc.exp=shift_imm
4572 These three may have a trailing ! which causes .writeback to be set also.
4574 Postindexed addressing (.postind=1, .writeback=1):
4576 [Rn], #offset .reg=Rn .reloc.exp=offset
4577 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4578 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4579 .shift_kind=shift .reloc.exp=shift_imm
4581 Unindexed addressing (.preind=0, .postind=0):
4583 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4587 [Rn]{!} shorthand for [Rn,#0]{!}
4588 =immediate .isreg=0 .reloc.exp=immediate
4589 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4591 It is the caller's responsibility to check for addressing modes not
4592 supported by the instruction, and to set inst.reloc.type. */
4594 static parse_operand_result
4595 parse_address_main (char **str
, int i
, int group_relocations
,
4596 group_reloc_type group_type
)
4601 if (skip_past_char (&p
, '[') == FAIL
)
4603 if (skip_past_char (&p
, '=') == FAIL
)
4605 /* bare address - translate to PC-relative offset */
4606 inst
.reloc
.pc_rel
= 1;
4607 inst
.operands
[i
].reg
= REG_PC
;
4608 inst
.operands
[i
].isreg
= 1;
4609 inst
.operands
[i
].preind
= 1;
4611 /* else a load-constant pseudo op, no special treatment needed here */
4613 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4614 return PARSE_OPERAND_FAIL
;
4617 return PARSE_OPERAND_SUCCESS
;
4620 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4622 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4623 return PARSE_OPERAND_FAIL
;
4625 inst
.operands
[i
].reg
= reg
;
4626 inst
.operands
[i
].isreg
= 1;
4628 if (skip_past_comma (&p
) == SUCCESS
)
4630 inst
.operands
[i
].preind
= 1;
4633 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4635 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4637 inst
.operands
[i
].imm
= reg
;
4638 inst
.operands
[i
].immisreg
= 1;
4640 if (skip_past_comma (&p
) == SUCCESS
)
4641 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4642 return PARSE_OPERAND_FAIL
;
4644 else if (skip_past_char (&p
, ':') == SUCCESS
)
4646 /* FIXME: '@' should be used here, but it's filtered out by generic
4647 code before we get to see it here. This may be subject to
4650 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4651 if (exp
.X_op
!= O_constant
)
4653 inst
.error
= _("alignment must be constant");
4654 return PARSE_OPERAND_FAIL
;
4656 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4657 inst
.operands
[i
].immisalign
= 1;
4658 /* Alignments are not pre-indexes. */
4659 inst
.operands
[i
].preind
= 0;
4663 if (inst
.operands
[i
].negative
)
4665 inst
.operands
[i
].negative
= 0;
4669 if (group_relocations
&&
4670 ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
4673 struct group_reloc_table_entry
*entry
;
4675 /* Skip over the #: or : sequence. */
4681 /* Try to parse a group relocation. Anything else is an
4683 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
4685 inst
.error
= _("unknown group relocation");
4686 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4689 /* We now have the group relocation table entry corresponding to
4690 the name in the assembler source. Next, we parse the
4692 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4693 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4695 /* Record the relocation type. */
4699 inst
.reloc
.type
= entry
->ldr_code
;
4703 inst
.reloc
.type
= entry
->ldrs_code
;
4707 inst
.reloc
.type
= entry
->ldc_code
;
4714 if (inst
.reloc
.type
== 0)
4716 inst
.error
= _("this group relocation is not allowed on this instruction");
4717 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4721 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4722 return PARSE_OPERAND_FAIL
;
4726 if (skip_past_char (&p
, ']') == FAIL
)
4728 inst
.error
= _("']' expected");
4729 return PARSE_OPERAND_FAIL
;
4732 if (skip_past_char (&p
, '!') == SUCCESS
)
4733 inst
.operands
[i
].writeback
= 1;
4735 else if (skip_past_comma (&p
) == SUCCESS
)
4737 if (skip_past_char (&p
, '{') == SUCCESS
)
4739 /* [Rn], {expr} - unindexed, with option */
4740 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
4741 0, 255, TRUE
) == FAIL
)
4742 return PARSE_OPERAND_FAIL
;
4744 if (skip_past_char (&p
, '}') == FAIL
)
4746 inst
.error
= _("'}' expected at end of 'option' field");
4747 return PARSE_OPERAND_FAIL
;
4749 if (inst
.operands
[i
].preind
)
4751 inst
.error
= _("cannot combine index with option");
4752 return PARSE_OPERAND_FAIL
;
4755 return PARSE_OPERAND_SUCCESS
;
4759 inst
.operands
[i
].postind
= 1;
4760 inst
.operands
[i
].writeback
= 1;
4762 if (inst
.operands
[i
].preind
)
4764 inst
.error
= _("cannot combine pre- and post-indexing");
4765 return PARSE_OPERAND_FAIL
;
4769 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4771 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4773 /* We might be using the immediate for alignment already. If we
4774 are, OR the register number into the low-order bits. */
4775 if (inst
.operands
[i
].immisalign
)
4776 inst
.operands
[i
].imm
|= reg
;
4778 inst
.operands
[i
].imm
= reg
;
4779 inst
.operands
[i
].immisreg
= 1;
4781 if (skip_past_comma (&p
) == SUCCESS
)
4782 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4783 return PARSE_OPERAND_FAIL
;
4787 if (inst
.operands
[i
].negative
)
4789 inst
.operands
[i
].negative
= 0;
4792 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4793 return PARSE_OPERAND_FAIL
;
4798 /* If at this point neither .preind nor .postind is set, we have a
4799 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
4800 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
4802 inst
.operands
[i
].preind
= 1;
4803 inst
.reloc
.exp
.X_op
= O_constant
;
4804 inst
.reloc
.exp
.X_add_number
= 0;
4807 return PARSE_OPERAND_SUCCESS
;
4811 parse_address (char **str
, int i
)
4813 return parse_address_main (str
, i
, 0, 0) == PARSE_OPERAND_SUCCESS
4817 static parse_operand_result
4818 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
4820 return parse_address_main (str
, i
, 1, type
);
4823 /* Parse an operand for a MOVW or MOVT instruction. */
4825 parse_half (char **str
)
4830 skip_past_char (&p
, '#');
4831 if (strncasecmp (p
, ":lower16:", 9) == 0)
4832 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
4833 else if (strncasecmp (p
, ":upper16:", 9) == 0)
4834 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
4836 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4842 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4845 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4847 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4849 inst
.error
= _("constant expression expected");
4852 if (inst
.reloc
.exp
.X_add_number
< 0
4853 || inst
.reloc
.exp
.X_add_number
> 0xffff)
4855 inst
.error
= _("immediate value out of range");
4863 /* Miscellaneous. */
4865 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
4866 or a bitmask suitable to be or-ed into the ARM msr instruction. */
4868 parse_psr (char **str
)
4871 unsigned long psr_field
;
4872 const struct asm_psr
*psr
;
4875 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
4876 feature for ease of use and backwards compatibility. */
4878 if (strncasecmp (p
, "SPSR", 4) == 0)
4879 psr_field
= SPSR_BIT
;
4880 else if (strncasecmp (p
, "CPSR", 4) == 0)
4887 while (ISALNUM (*p
) || *p
== '_');
4889 psr
= hash_find_n (arm_v7m_psr_hsh
, start
, p
- start
);
4900 /* A suffix follows. */
4906 while (ISALNUM (*p
) || *p
== '_');
4908 psr
= hash_find_n (arm_psr_hsh
, start
, p
- start
);
4912 psr_field
|= psr
->field
;
4917 goto error
; /* Garbage after "[CS]PSR". */
4919 psr_field
|= (PSR_c
| PSR_f
);
4925 inst
.error
= _("flag for {c}psr instruction expected");
4929 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
4930 value suitable for splatting into the AIF field of the instruction. */
4933 parse_cps_flags (char **str
)
4942 case '\0': case ',':
4945 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
4946 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
4947 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
4950 inst
.error
= _("unrecognized CPS flag");
4955 if (saw_a_flag
== 0)
4957 inst
.error
= _("missing CPS flags");
4965 /* Parse an endian specifier ("BE" or "LE", case insensitive);
4966 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
4969 parse_endian_specifier (char **str
)
4974 if (strncasecmp (s
, "BE", 2))
4976 else if (strncasecmp (s
, "LE", 2))
4980 inst
.error
= _("valid endian specifiers are be or le");
4984 if (ISALNUM (s
[2]) || s
[2] == '_')
4986 inst
.error
= _("valid endian specifiers are be or le");
4991 return little_endian
;
4994 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
4995 value suitable for poking into the rotate field of an sxt or sxta
4996 instruction, or FAIL on error. */
4999 parse_ror (char **str
)
5004 if (strncasecmp (s
, "ROR", 3) == 0)
5008 inst
.error
= _("missing rotation field after comma");
5012 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5017 case 0: *str
= s
; return 0x0;
5018 case 8: *str
= s
; return 0x1;
5019 case 16: *str
= s
; return 0x2;
5020 case 24: *str
= s
; return 0x3;
5023 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5028 /* Parse a conditional code (from conds[] below). The value returned is in the
5029 range 0 .. 14, or FAIL. */
5031 parse_cond (char **str
)
5034 const struct asm_cond
*c
;
5037 while (ISALPHA (*q
))
5040 c
= hash_find_n (arm_cond_hsh
, p
, q
- p
);
5043 inst
.error
= _("condition required");
5051 /* Parse an option for a barrier instruction. Returns the encoding for the
5054 parse_barrier (char **str
)
5057 const struct asm_barrier_opt
*o
;
5060 while (ISALPHA (*q
))
5063 o
= hash_find_n (arm_barrier_opt_hsh
, p
, q
- p
);
5071 /* Parse the operands of a table branch instruction. Similar to a memory
5074 parse_tb (char **str
)
5079 if (skip_past_char (&p
, '[') == FAIL
)
5081 inst
.error
= _("'[' expected");
5085 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5087 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5090 inst
.operands
[0].reg
= reg
;
5092 if (skip_past_comma (&p
) == FAIL
)
5094 inst
.error
= _("',' expected");
5098 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5100 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5103 inst
.operands
[0].imm
= reg
;
5105 if (skip_past_comma (&p
) == SUCCESS
)
5107 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5109 if (inst
.reloc
.exp
.X_add_number
!= 1)
5111 inst
.error
= _("invalid shift");
5114 inst
.operands
[0].shifted
= 1;
5117 if (skip_past_char (&p
, ']') == FAIL
)
5119 inst
.error
= _("']' expected");
5126 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5127 information on the types the operands can take and how they are encoded.
5128 Up to four operands may be read; this function handles setting the
5129 ".present" field for each read operand itself.
5130 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5131 else returns FAIL. */
5134 parse_neon_mov (char **str
, int *which_operand
)
5136 int i
= *which_operand
, val
;
5137 enum arm_reg_type rtype
;
5139 struct neon_type_el optype
;
5141 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5143 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5144 inst
.operands
[i
].reg
= val
;
5145 inst
.operands
[i
].isscalar
= 1;
5146 inst
.operands
[i
].vectype
= optype
;
5147 inst
.operands
[i
++].present
= 1;
5149 if (skip_past_comma (&ptr
) == FAIL
)
5152 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5155 inst
.operands
[i
].reg
= val
;
5156 inst
.operands
[i
].isreg
= 1;
5157 inst
.operands
[i
].present
= 1;
5159 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5162 /* Cases 0, 1, 2, 3, 5 (D only). */
5163 if (skip_past_comma (&ptr
) == FAIL
)
5166 inst
.operands
[i
].reg
= val
;
5167 inst
.operands
[i
].isreg
= 1;
5168 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5169 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5170 inst
.operands
[i
].isvec
= 1;
5171 inst
.operands
[i
].vectype
= optype
;
5172 inst
.operands
[i
++].present
= 1;
5174 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5176 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5177 Case 13: VMOV <Sd>, <Rm> */
5178 inst
.operands
[i
].reg
= val
;
5179 inst
.operands
[i
].isreg
= 1;
5180 inst
.operands
[i
].present
= 1;
5182 if (rtype
== REG_TYPE_NQ
)
5184 first_error (_("can't use Neon quad register here"));
5187 else if (rtype
!= REG_TYPE_VFS
)
5190 if (skip_past_comma (&ptr
) == FAIL
)
5192 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5194 inst
.operands
[i
].reg
= val
;
5195 inst
.operands
[i
].isreg
= 1;
5196 inst
.operands
[i
].present
= 1;
5199 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5200 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5201 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5202 Case 10: VMOV.F32 <Sd>, #<imm>
5203 Case 11: VMOV.F64 <Dd>, #<imm> */
5205 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5206 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5207 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5209 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5212 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5213 Case 1: VMOV<c><q> <Dd>, <Dm>
5214 Case 8: VMOV.F32 <Sd>, <Sm>
5215 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5217 inst
.operands
[i
].reg
= val
;
5218 inst
.operands
[i
].isreg
= 1;
5219 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5220 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5221 inst
.operands
[i
].isvec
= 1;
5222 inst
.operands
[i
].vectype
= optype
;
5223 inst
.operands
[i
].present
= 1;
5225 if (skip_past_comma (&ptr
) == SUCCESS
)
5230 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5233 inst
.operands
[i
].reg
= val
;
5234 inst
.operands
[i
].isreg
= 1;
5235 inst
.operands
[i
++].present
= 1;
5237 if (skip_past_comma (&ptr
) == FAIL
)
5240 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5243 inst
.operands
[i
].reg
= val
;
5244 inst
.operands
[i
].isreg
= 1;
5245 inst
.operands
[i
++].present
= 1;
5250 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5254 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5257 inst
.operands
[i
].reg
= val
;
5258 inst
.operands
[i
].isreg
= 1;
5259 inst
.operands
[i
++].present
= 1;
5261 if (skip_past_comma (&ptr
) == FAIL
)
5264 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5266 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5267 inst
.operands
[i
].reg
= val
;
5268 inst
.operands
[i
].isscalar
= 1;
5269 inst
.operands
[i
].present
= 1;
5270 inst
.operands
[i
].vectype
= optype
;
5272 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5274 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5275 inst
.operands
[i
].reg
= val
;
5276 inst
.operands
[i
].isreg
= 1;
5277 inst
.operands
[i
++].present
= 1;
5279 if (skip_past_comma (&ptr
) == FAIL
)
5282 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5285 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5289 inst
.operands
[i
].reg
= val
;
5290 inst
.operands
[i
].isreg
= 1;
5291 inst
.operands
[i
].isvec
= 1;
5292 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5293 inst
.operands
[i
].vectype
= optype
;
5294 inst
.operands
[i
].present
= 1;
5296 if (rtype
== REG_TYPE_VFS
)
5300 if (skip_past_comma (&ptr
) == FAIL
)
5302 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5305 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5308 inst
.operands
[i
].reg
= val
;
5309 inst
.operands
[i
].isreg
= 1;
5310 inst
.operands
[i
].isvec
= 1;
5311 inst
.operands
[i
].issingle
= 1;
5312 inst
.operands
[i
].vectype
= optype
;
5313 inst
.operands
[i
].present
= 1;
5316 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5320 inst
.operands
[i
].reg
= val
;
5321 inst
.operands
[i
].isreg
= 1;
5322 inst
.operands
[i
].isvec
= 1;
5323 inst
.operands
[i
].issingle
= 1;
5324 inst
.operands
[i
].vectype
= optype
;
5325 inst
.operands
[i
++].present
= 1;
5330 first_error (_("parse error"));
5334 /* Successfully parsed the operands. Update args. */
5340 first_error (_("expected comma"));
5344 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5348 /* Matcher codes for parse_operands. */
5349 enum operand_parse_code
5351 OP_stop
, /* end of line */
5353 OP_RR
, /* ARM register */
5354 OP_RRnpc
, /* ARM register, not r15 */
5355 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5356 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5357 OP_RCP
, /* Coprocessor number */
5358 OP_RCN
, /* Coprocessor register */
5359 OP_RF
, /* FPA register */
5360 OP_RVS
, /* VFP single precision register */
5361 OP_RVD
, /* VFP double precision register (0..15) */
5362 OP_RND
, /* Neon double precision register (0..31) */
5363 OP_RNQ
, /* Neon quad precision register */
5364 OP_RVSD
, /* VFP single or double precision register */
5365 OP_RNDQ
, /* Neon double or quad precision register */
5366 OP_RNSDQ
, /* Neon single, double or quad precision register */
5367 OP_RNSC
, /* Neon scalar D[X] */
5368 OP_RVC
, /* VFP control register */
5369 OP_RMF
, /* Maverick F register */
5370 OP_RMD
, /* Maverick D register */
5371 OP_RMFX
, /* Maverick FX register */
5372 OP_RMDX
, /* Maverick DX register */
5373 OP_RMAX
, /* Maverick AX register */
5374 OP_RMDS
, /* Maverick DSPSC register */
5375 OP_RIWR
, /* iWMMXt wR register */
5376 OP_RIWC
, /* iWMMXt wC register */
5377 OP_RIWG
, /* iWMMXt wCG register */
5378 OP_RXA
, /* XScale accumulator register */
5380 OP_REGLST
, /* ARM register list */
5381 OP_VRSLST
, /* VFP single-precision register list */
5382 OP_VRDLST
, /* VFP double-precision register list */
5383 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5384 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5385 OP_NSTRLST
, /* Neon element/structure list */
5387 OP_NILO
, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5388 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5389 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5390 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5391 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5392 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5393 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5394 OP_VMOV
, /* Neon VMOV operands. */
5395 OP_RNDQ_IMVNb
,/* Neon D or Q reg, or immediate good for VMVN. */
5396 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5397 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5399 OP_I0
, /* immediate zero */
5400 OP_I7
, /* immediate value 0 .. 7 */
5401 OP_I15
, /* 0 .. 15 */
5402 OP_I16
, /* 1 .. 16 */
5403 OP_I16z
, /* 0 .. 16 */
5404 OP_I31
, /* 0 .. 31 */
5405 OP_I31w
, /* 0 .. 31, optional trailing ! */
5406 OP_I32
, /* 1 .. 32 */
5407 OP_I32z
, /* 0 .. 32 */
5408 OP_I63
, /* 0 .. 63 */
5409 OP_I63s
, /* -64 .. 63 */
5410 OP_I64
, /* 1 .. 64 */
5411 OP_I64z
, /* 0 .. 64 */
5412 OP_I255
, /* 0 .. 255 */
5414 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5415 OP_I7b
, /* 0 .. 7 */
5416 OP_I15b
, /* 0 .. 15 */
5417 OP_I31b
, /* 0 .. 31 */
5419 OP_SH
, /* shifter operand */
5420 OP_SHG
, /* shifter operand with possible group relocation */
5421 OP_ADDR
, /* Memory address expression (any mode) */
5422 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5423 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5424 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5425 OP_EXP
, /* arbitrary expression */
5426 OP_EXPi
, /* same, with optional immediate prefix */
5427 OP_EXPr
, /* same, with optional relocation suffix */
5428 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5430 OP_CPSF
, /* CPS flags */
5431 OP_ENDI
, /* Endianness specifier */
5432 OP_PSR
, /* CPSR/SPSR mask for msr */
5433 OP_COND
, /* conditional code */
5434 OP_TB
, /* Table branch. */
5436 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5437 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5439 OP_RRnpc_I0
, /* ARM register or literal 0 */
5440 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5441 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5442 OP_RF_IF
, /* FPA register or immediate */
5443 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5444 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5446 /* Optional operands. */
5447 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5448 OP_oI31b
, /* 0 .. 31 */
5449 OP_oI32b
, /* 1 .. 32 */
5450 OP_oIffffb
, /* 0 .. 65535 */
5451 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5453 OP_oRR
, /* ARM register */
5454 OP_oRRnpc
, /* ARM register, not the PC */
5455 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5456 OP_oRND
, /* Optional Neon double precision register */
5457 OP_oRNQ
, /* Optional Neon quad precision register */
5458 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5459 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5460 OP_oSHll
, /* LSL immediate */
5461 OP_oSHar
, /* ASR immediate */
5462 OP_oSHllar
, /* LSL or ASR immediate */
5463 OP_oROR
, /* ROR 0/8/16/24 */
5464 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5466 OP_FIRST_OPTIONAL
= OP_oI7b
5469 /* Generic instruction operand parser. This does no encoding and no
5470 semantic validation; it merely squirrels values away in the inst
5471 structure. Returns SUCCESS or FAIL depending on whether the
5472 specified grammar matched. */
5474 parse_operands (char *str
, const unsigned char *pattern
)
5476 unsigned const char *upat
= pattern
;
5477 char *backtrack_pos
= 0;
5478 const char *backtrack_error
= 0;
5479 int i
, val
, backtrack_index
= 0;
5480 enum arm_reg_type rtype
;
5481 parse_operand_result result
;
5483 #define po_char_or_fail(chr) do { \
5484 if (skip_past_char (&str, chr) == FAIL) \
5488 #define po_reg_or_fail(regtype) do { \
5489 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5490 &inst.operands[i].vectype); \
5493 first_error (_(reg_expected_msgs[regtype])); \
5496 inst.operands[i].reg = val; \
5497 inst.operands[i].isreg = 1; \
5498 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5499 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5500 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5501 || rtype == REG_TYPE_VFD \
5502 || rtype == REG_TYPE_NQ); \
5505 #define po_reg_or_goto(regtype, label) do { \
5506 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5507 &inst.operands[i].vectype); \
5511 inst.operands[i].reg = val; \
5512 inst.operands[i].isreg = 1; \
5513 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5514 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5515 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5516 || rtype == REG_TYPE_VFD \
5517 || rtype == REG_TYPE_NQ); \
5520 #define po_imm_or_fail(min, max, popt) do { \
5521 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5523 inst.operands[i].imm = val; \
5526 #define po_scalar_or_goto(elsz, label) do { \
5527 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \
5530 inst.operands[i].reg = val; \
5531 inst.operands[i].isscalar = 1; \
5534 #define po_misc_or_fail(expr) do { \
5539 #define po_misc_or_fail_no_backtrack(expr) do { \
5541 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
5542 backtrack_pos = 0; \
5543 if (result != PARSE_OPERAND_SUCCESS) \
5547 skip_whitespace (str
);
5549 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5551 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5553 /* Remember where we are in case we need to backtrack. */
5554 assert (!backtrack_pos
);
5555 backtrack_pos
= str
;
5556 backtrack_error
= inst
.error
;
5557 backtrack_index
= i
;
5560 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
5561 po_char_or_fail (',');
5569 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5570 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5571 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5572 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5573 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5574 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5576 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5577 case OP_RVC
: po_reg_or_fail (REG_TYPE_VFC
); break;
5578 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5579 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5580 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5581 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5582 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5583 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5584 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5585 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5586 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5587 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5589 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
5591 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
5592 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
5594 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
5596 /* Neon scalar. Using an element size of 8 means that some invalid
5597 scalars are accepted here, so deal with those in later code. */
5598 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
5600 /* WARNING: We can expand to two operands here. This has the potential
5601 to totally confuse the backtracking mechanism! It will be OK at
5602 least as long as we don't try to use optional args as well,
5606 po_reg_or_goto (REG_TYPE_NDQ
, try_imm
);
5607 inst
.operands
[i
].present
= 1;
5609 skip_past_comma (&str
);
5610 po_reg_or_goto (REG_TYPE_NDQ
, one_reg_only
);
5613 /* Optional register operand was omitted. Unfortunately, it's in
5614 operands[i-1] and we need it to be in inst.operands[i]. Fix that
5615 here (this is a bit grotty). */
5616 inst
.operands
[i
] = inst
.operands
[i
-1];
5617 inst
.operands
[i
-1].present
= 0;
5620 /* There's a possibility of getting a 64-bit immediate here, so
5621 we need special handling. */
5622 if (parse_big_immediate (&str
, i
) == FAIL
)
5624 inst
.error
= _("immediate value is out of range");
5632 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
5635 po_imm_or_fail (0, 0, TRUE
);
5640 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
5645 po_scalar_or_goto (8, try_rr
);
5648 po_reg_or_fail (REG_TYPE_RN
);
5654 po_scalar_or_goto (8, try_nsdq
);
5657 po_reg_or_fail (REG_TYPE_NSDQ
);
5663 po_scalar_or_goto (8, try_ndq
);
5666 po_reg_or_fail (REG_TYPE_NDQ
);
5672 po_scalar_or_goto (8, try_vfd
);
5675 po_reg_or_fail (REG_TYPE_VFD
);
5680 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
5681 not careful then bad things might happen. */
5682 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
5687 po_reg_or_goto (REG_TYPE_NDQ
, try_mvnimm
);
5690 /* There's a possibility of getting a 64-bit immediate here, so
5691 we need special handling. */
5692 if (parse_big_immediate (&str
, i
) == FAIL
)
5694 inst
.error
= _("immediate value is out of range");
5702 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
5705 po_imm_or_fail (0, 63, TRUE
);
5710 po_char_or_fail ('[');
5711 po_reg_or_fail (REG_TYPE_RN
);
5712 po_char_or_fail (']');
5717 po_reg_or_fail (REG_TYPE_RN
);
5718 if (skip_past_char (&str
, '!') == SUCCESS
)
5719 inst
.operands
[i
].writeback
= 1;
5723 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
5724 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
5725 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
5726 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
5727 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
5728 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
5729 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
5730 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
5731 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
5732 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
5733 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
5734 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
5736 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
5738 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
5739 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
5741 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
5742 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
5743 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
5745 /* Immediate variants */
5747 po_char_or_fail ('{');
5748 po_imm_or_fail (0, 255, TRUE
);
5749 po_char_or_fail ('}');
5753 /* The expression parser chokes on a trailing !, so we have
5754 to find it first and zap it. */
5757 while (*s
&& *s
!= ',')
5762 inst
.operands
[i
].writeback
= 1;
5764 po_imm_or_fail (0, 31, TRUE
);
5772 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5777 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5782 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5784 if (inst
.reloc
.exp
.X_op
== O_symbol
)
5786 val
= parse_reloc (&str
);
5789 inst
.error
= _("unrecognized relocation suffix");
5792 else if (val
!= BFD_RELOC_UNUSED
)
5794 inst
.operands
[i
].imm
= val
;
5795 inst
.operands
[i
].hasreloc
= 1;
5800 /* Operand for MOVW or MOVT. */
5802 po_misc_or_fail (parse_half (&str
));
5805 /* Register or expression */
5806 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
5807 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
5809 /* Register or immediate */
5810 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
5811 I0
: po_imm_or_fail (0, 0, FALSE
); break;
5813 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
5815 if (!is_immediate_prefix (*str
))
5818 val
= parse_fpa_immediate (&str
);
5821 /* FPA immediates are encoded as registers 8-15.
5822 parse_fpa_immediate has already applied the offset. */
5823 inst
.operands
[i
].reg
= val
;
5824 inst
.operands
[i
].isreg
= 1;
5827 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
5828 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
5830 /* Two kinds of register */
5833 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5835 || (rege
->type
!= REG_TYPE_MMXWR
5836 && rege
->type
!= REG_TYPE_MMXWC
5837 && rege
->type
!= REG_TYPE_MMXWCG
))
5839 inst
.error
= _("iWMMXt data or control register expected");
5842 inst
.operands
[i
].reg
= rege
->number
;
5843 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
5849 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5851 || (rege
->type
!= REG_TYPE_MMXWC
5852 && rege
->type
!= REG_TYPE_MMXWCG
))
5854 inst
.error
= _("iWMMXt control register expected");
5857 inst
.operands
[i
].reg
= rege
->number
;
5858 inst
.operands
[i
].isreg
= 1;
5863 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
5864 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
5865 case OP_oROR
: val
= parse_ror (&str
); break;
5866 case OP_PSR
: val
= parse_psr (&str
); break;
5867 case OP_COND
: val
= parse_cond (&str
); break;
5868 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
5871 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
5872 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
5875 val
= parse_psr (&str
);
5879 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
5882 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
5884 if (strncasecmp (str
, "APSR_", 5) == 0)
5891 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
5892 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
5893 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
5894 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
5895 default: found
= 16;
5899 inst
.operands
[i
].isvec
= 1;
5906 po_misc_or_fail (parse_tb (&str
));
5909 /* Register lists */
5911 val
= parse_reg_list (&str
);
5914 inst
.operands
[1].writeback
= 1;
5920 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
5924 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
5928 /* Allow Q registers too. */
5929 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5934 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5936 inst
.operands
[i
].issingle
= 1;
5941 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5946 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
5947 &inst
.operands
[i
].vectype
);
5950 /* Addressing modes */
5952 po_misc_or_fail (parse_address (&str
, i
));
5956 po_misc_or_fail_no_backtrack (
5957 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
5961 po_misc_or_fail_no_backtrack (
5962 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
5966 po_misc_or_fail_no_backtrack (
5967 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
5971 po_misc_or_fail (parse_shifter_operand (&str
, i
));
5975 po_misc_or_fail_no_backtrack (
5976 parse_shifter_operand_group_reloc (&str
, i
));
5980 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
5984 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
5988 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
5992 as_fatal ("unhandled operand code %d", upat
[i
]);
5995 /* Various value-based sanity checks and shared operations. We
5996 do not signal immediate failures for the register constraints;
5997 this allows a syntax error to take precedence. */
6006 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6007 inst
.error
= BAD_PC
;
6025 inst
.operands
[i
].imm
= val
;
6032 /* If we get here, this operand was successfully parsed. */
6033 inst
.operands
[i
].present
= 1;
6037 inst
.error
= BAD_ARGS
;
6042 /* The parse routine should already have set inst.error, but set a
6043 defaut here just in case. */
6045 inst
.error
= _("syntax error");
6049 /* Do not backtrack over a trailing optional argument that
6050 absorbed some text. We will only fail again, with the
6051 'garbage following instruction' error message, which is
6052 probably less helpful than the current one. */
6053 if (backtrack_index
== i
&& backtrack_pos
!= str
6054 && upat
[i
+1] == OP_stop
)
6057 inst
.error
= _("syntax error");
6061 /* Try again, skipping the optional argument at backtrack_pos. */
6062 str
= backtrack_pos
;
6063 inst
.error
= backtrack_error
;
6064 inst
.operands
[backtrack_index
].present
= 0;
6065 i
= backtrack_index
;
6069 /* Check that we have parsed all the arguments. */
6070 if (*str
!= '\0' && !inst
.error
)
6071 inst
.error
= _("garbage following instruction");
6073 return inst
.error
? FAIL
: SUCCESS
;
6076 #undef po_char_or_fail
6077 #undef po_reg_or_fail
6078 #undef po_reg_or_goto
6079 #undef po_imm_or_fail
6080 #undef po_scalar_or_fail
6082 /* Shorthand macro for instruction encoding functions issuing errors. */
6083 #define constraint(expr, err) do { \
6091 /* Functions for operand encoding. ARM, then Thumb. */
6093 #define rotate_left(v, n) (v << n | v >> (32 - n))
6095 /* If VAL can be encoded in the immediate field of an ARM instruction,
6096 return the encoded form. Otherwise, return FAIL. */
6099 encode_arm_immediate (unsigned int val
)
6103 for (i
= 0; i
< 32; i
+= 2)
6104 if ((a
= rotate_left (val
, i
)) <= 0xff)
6105 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6110 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6111 return the encoded form. Otherwise, return FAIL. */
6113 encode_thumb32_immediate (unsigned int val
)
6120 for (i
= 1; i
<= 24; i
++)
6123 if ((val
& ~(0xff << i
)) == 0)
6124 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6128 if (val
== ((a
<< 16) | a
))
6130 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6134 if (val
== ((a
<< 16) | a
))
6135 return 0x200 | (a
>> 8);
6139 /* Encode a VFP SP or DP register number into inst.instruction. */
6142 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6144 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6147 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
6150 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6153 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6158 first_error (_("D register out of range for selected VFP version"));
6166 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6170 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6174 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6178 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6182 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6186 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6194 /* Encode a <shift> in an ARM-format instruction. The immediate,
6195 if any, is handled by md_apply_fix. */
6197 encode_arm_shift (int i
)
6199 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6200 inst
.instruction
|= SHIFT_ROR
<< 5;
6203 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6204 if (inst
.operands
[i
].immisreg
)
6206 inst
.instruction
|= SHIFT_BY_REG
;
6207 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6210 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6215 encode_arm_shifter_operand (int i
)
6217 if (inst
.operands
[i
].isreg
)
6219 inst
.instruction
|= inst
.operands
[i
].reg
;
6220 encode_arm_shift (i
);
6223 inst
.instruction
|= INST_IMMEDIATE
;
6226 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6228 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6230 assert (inst
.operands
[i
].isreg
);
6231 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6233 if (inst
.operands
[i
].preind
)
6237 inst
.error
= _("instruction does not accept preindexed addressing");
6240 inst
.instruction
|= PRE_INDEX
;
6241 if (inst
.operands
[i
].writeback
)
6242 inst
.instruction
|= WRITE_BACK
;
6245 else if (inst
.operands
[i
].postind
)
6247 assert (inst
.operands
[i
].writeback
);
6249 inst
.instruction
|= WRITE_BACK
;
6251 else /* unindexed - only for coprocessor */
6253 inst
.error
= _("instruction does not accept unindexed addressing");
6257 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6258 && (((inst
.instruction
& 0x000f0000) >> 16)
6259 == ((inst
.instruction
& 0x0000f000) >> 12)))
6260 as_warn ((inst
.instruction
& LOAD_BIT
)
6261 ? _("destination register same as write-back base")
6262 : _("source register same as write-back base"));
6265 /* inst.operands[i] was set up by parse_address. Encode it into an
6266 ARM-format mode 2 load or store instruction. If is_t is true,
6267 reject forms that cannot be used with a T instruction (i.e. not
6270 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6272 encode_arm_addr_mode_common (i
, is_t
);
6274 if (inst
.operands
[i
].immisreg
)
6276 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6277 inst
.instruction
|= inst
.operands
[i
].imm
;
6278 if (!inst
.operands
[i
].negative
)
6279 inst
.instruction
|= INDEX_UP
;
6280 if (inst
.operands
[i
].shifted
)
6282 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6283 inst
.instruction
|= SHIFT_ROR
<< 5;
6286 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6287 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6291 else /* immediate offset in inst.reloc */
6293 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6294 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6298 /* inst.operands[i] was set up by parse_address. Encode it into an
6299 ARM-format mode 3 load or store instruction. Reject forms that
6300 cannot be used with such instructions. If is_t is true, reject
6301 forms that cannot be used with a T instruction (i.e. not
6304 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6306 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6308 inst
.error
= _("instruction does not accept scaled register index");
6312 encode_arm_addr_mode_common (i
, is_t
);
6314 if (inst
.operands
[i
].immisreg
)
6316 inst
.instruction
|= inst
.operands
[i
].imm
;
6317 if (!inst
.operands
[i
].negative
)
6318 inst
.instruction
|= INDEX_UP
;
6320 else /* immediate offset in inst.reloc */
6322 inst
.instruction
|= HWOFFSET_IMM
;
6323 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6324 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6328 /* inst.operands[i] was set up by parse_address. Encode it into an
6329 ARM-format instruction. Reject all forms which cannot be encoded
6330 into a coprocessor load/store instruction. If wb_ok is false,
6331 reject use of writeback; if unind_ok is false, reject use of
6332 unindexed addressing. If reloc_override is not 0, use it instead
6333 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6334 (in which case it is preserved). */
6337 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6339 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6341 assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6343 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6345 assert (!inst
.operands
[i
].writeback
);
6348 inst
.error
= _("instruction does not support unindexed addressing");
6351 inst
.instruction
|= inst
.operands
[i
].imm
;
6352 inst
.instruction
|= INDEX_UP
;
6356 if (inst
.operands
[i
].preind
)
6357 inst
.instruction
|= PRE_INDEX
;
6359 if (inst
.operands
[i
].writeback
)
6361 if (inst
.operands
[i
].reg
== REG_PC
)
6363 inst
.error
= _("pc may not be used with write-back");
6368 inst
.error
= _("instruction does not support writeback");
6371 inst
.instruction
|= WRITE_BACK
;
6375 inst
.reloc
.type
= reloc_override
;
6376 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6377 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6378 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6381 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6383 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6389 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6390 Determine whether it can be performed with a move instruction; if
6391 it can, convert inst.instruction to that move instruction and
6392 return 1; if it can't, convert inst.instruction to a literal-pool
6393 load and return 0. If this is not a valid thing to do in the
6394 current context, set inst.error and return 1.
6396 inst.operands[i] describes the destination register. */
6399 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6404 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6408 if ((inst
.instruction
& tbit
) == 0)
6410 inst
.error
= _("invalid pseudo operation");
6413 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6415 inst
.error
= _("constant expression expected");
6418 if (inst
.reloc
.exp
.X_op
== O_constant
)
6422 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6424 /* This can be done with a mov(1) instruction. */
6425 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6426 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6432 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6435 /* This can be done with a mov instruction. */
6436 inst
.instruction
&= LITERAL_MASK
;
6437 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6438 inst
.instruction
|= value
& 0xfff;
6442 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6445 /* This can be done with a mvn instruction. */
6446 inst
.instruction
&= LITERAL_MASK
;
6447 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6448 inst
.instruction
|= value
& 0xfff;
6454 if (add_to_lit_pool () == FAIL
)
6456 inst
.error
= _("literal pool insertion failed");
6459 inst
.operands
[1].reg
= REG_PC
;
6460 inst
.operands
[1].isreg
= 1;
6461 inst
.operands
[1].preind
= 1;
6462 inst
.reloc
.pc_rel
= 1;
6463 inst
.reloc
.type
= (thumb_p
6464 ? BFD_RELOC_ARM_THUMB_OFFSET
6466 ? BFD_RELOC_ARM_HWLITERAL
6467 : BFD_RELOC_ARM_LITERAL
));
6471 /* Functions for instruction encoding, sorted by subarchitecture.
6472 First some generics; their names are taken from the conventional
6473 bit positions for register arguments in ARM format instructions. */
6483 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6489 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6490 inst
.instruction
|= inst
.operands
[1].reg
;
6496 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6497 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6503 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6504 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6510 unsigned Rn
= inst
.operands
[2].reg
;
6511 /* Enforce restrictions on SWP instruction. */
6512 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6513 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6514 _("Rn must not overlap other operands"));
6515 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6516 inst
.instruction
|= inst
.operands
[1].reg
;
6517 inst
.instruction
|= Rn
<< 16;
6523 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6524 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6525 inst
.instruction
|= inst
.operands
[2].reg
;
6531 inst
.instruction
|= inst
.operands
[0].reg
;
6532 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6533 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6539 inst
.instruction
|= inst
.operands
[0].imm
;
6545 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6546 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6549 /* ARM instructions, in alphabetical order by function name (except
6550 that wrapper functions appear immediately after the function they
6553 /* This is a pseudo-op of the form "adr rd, label" to be converted
6554 into a relative address of the form "add rd, pc, #label-.-8". */
6559 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6561 /* Frag hacking will turn this into a sub instruction if the offset turns
6562 out to be negative. */
6563 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6564 inst
.reloc
.pc_rel
= 1;
6565 inst
.reloc
.exp
.X_add_number
-= 8;
6568 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6569 into a relative address of the form:
6570 add rd, pc, #low(label-.-8)"
6571 add rd, rd, #high(label-.-8)" */
6576 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6578 /* Frag hacking will turn this into a sub instruction if the offset turns
6579 out to be negative. */
6580 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
6581 inst
.reloc
.pc_rel
= 1;
6582 inst
.size
= INSN_SIZE
* 2;
6583 inst
.reloc
.exp
.X_add_number
-= 8;
6589 if (!inst
.operands
[1].present
)
6590 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
6591 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6592 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6593 encode_arm_shifter_operand (2);
6599 if (inst
.operands
[0].present
)
6601 constraint ((inst
.instruction
& 0xf0) != 0x40
6602 && inst
.operands
[0].imm
!= 0xf,
6603 "bad barrier type");
6604 inst
.instruction
|= inst
.operands
[0].imm
;
6607 inst
.instruction
|= 0xf;
6613 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
6614 constraint (msb
> 32, _("bit-field extends past end of register"));
6615 /* The instruction encoding stores the LSB and MSB,
6616 not the LSB and width. */
6617 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6618 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
6619 inst
.instruction
|= (msb
- 1) << 16;
6627 /* #0 in second position is alternative syntax for bfc, which is
6628 the same instruction but with REG_PC in the Rm field. */
6629 if (!inst
.operands
[1].isreg
)
6630 inst
.operands
[1].reg
= REG_PC
;
6632 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
6633 constraint (msb
> 32, _("bit-field extends past end of register"));
6634 /* The instruction encoding stores the LSB and MSB,
6635 not the LSB and width. */
6636 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6637 inst
.instruction
|= inst
.operands
[1].reg
;
6638 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6639 inst
.instruction
|= (msb
- 1) << 16;
6645 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
6646 _("bit-field extends past end of register"));
6647 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6648 inst
.instruction
|= inst
.operands
[1].reg
;
6649 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6650 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
6653 /* ARM V5 breakpoint instruction (argument parse)
6654 BKPT <16 bit unsigned immediate>
6655 Instruction is not conditional.
6656 The bit pattern given in insns[] has the COND_ALWAYS condition,
6657 and it is an error if the caller tried to override that. */
6662 /* Top 12 of 16 bits to bits 19:8. */
6663 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
6665 /* Bottom 4 of 16 bits to bits 3:0. */
6666 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
6670 encode_branch (int default_reloc
)
6672 if (inst
.operands
[0].hasreloc
)
6674 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
6675 _("the only suffix valid here is '(plt)'"));
6676 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
6680 inst
.reloc
.type
= default_reloc
;
6682 inst
.reloc
.pc_rel
= 1;
6689 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6690 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6693 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6700 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6702 if (inst
.cond
== COND_ALWAYS
)
6703 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6705 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6709 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6712 /* ARM V5 branch-link-exchange instruction (argument parse)
6713 BLX <target_addr> ie BLX(1)
6714 BLX{<condition>} <Rm> ie BLX(2)
6715 Unfortunately, there are two different opcodes for this mnemonic.
6716 So, the insns[].value is not used, and the code here zaps values
6717 into inst.instruction.
6718 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
6723 if (inst
.operands
[0].isreg
)
6725 /* Arg is a register; the opcode provided by insns[] is correct.
6726 It is not illegal to do "blx pc", just useless. */
6727 if (inst
.operands
[0].reg
== REG_PC
)
6728 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
6730 inst
.instruction
|= inst
.operands
[0].reg
;
6734 /* Arg is an address; this instruction cannot be executed
6735 conditionally, and the opcode must be adjusted. */
6736 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
6737 inst
.instruction
= 0xfa000000;
6739 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6740 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6743 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
6750 if (inst
.operands
[0].reg
== REG_PC
)
6751 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
6753 inst
.instruction
|= inst
.operands
[0].reg
;
6757 /* ARM v5TEJ. Jump to Jazelle code. */
6762 if (inst
.operands
[0].reg
== REG_PC
)
6763 as_tsktsk (_("use of r15 in bxj is not really useful"));
6765 inst
.instruction
|= inst
.operands
[0].reg
;
6768 /* Co-processor data operation:
6769 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
6770 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
6774 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6775 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
6776 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6777 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6778 inst
.instruction
|= inst
.operands
[4].reg
;
6779 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6785 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6786 encode_arm_shifter_operand (1);
6789 /* Transfer between coprocessor and ARM registers.
6790 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
6795 No special properties. */
6800 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6801 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
6802 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6803 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6804 inst
.instruction
|= inst
.operands
[4].reg
;
6805 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6808 /* Transfer between coprocessor register and pair of ARM registers.
6809 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6814 Two XScale instructions are special cases of these:
6816 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
6817 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
6819 Result unpredicatable if Rd or Rn is R15. */
6824 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6825 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
6826 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6827 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6828 inst
.instruction
|= inst
.operands
[4].reg
;
6834 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
6835 if (inst
.operands
[1].present
)
6837 inst
.instruction
|= CPSI_MMOD
;
6838 inst
.instruction
|= inst
.operands
[1].imm
;
6845 inst
.instruction
|= inst
.operands
[0].imm
;
6851 /* There is no IT instruction in ARM mode. We
6852 process it but do not generate code for it. */
6859 int base_reg
= inst
.operands
[0].reg
;
6860 int range
= inst
.operands
[1].imm
;
6862 inst
.instruction
|= base_reg
<< 16;
6863 inst
.instruction
|= range
;
6865 if (inst
.operands
[1].writeback
)
6866 inst
.instruction
|= LDM_TYPE_2_OR_3
;
6868 if (inst
.operands
[0].writeback
)
6870 inst
.instruction
|= WRITE_BACK
;
6871 /* Check for unpredictable uses of writeback. */
6872 if (inst
.instruction
& LOAD_BIT
)
6874 /* Not allowed in LDM type 2. */
6875 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
6876 && ((range
& (1 << REG_PC
)) == 0))
6877 as_warn (_("writeback of base register is UNPREDICTABLE"));
6878 /* Only allowed if base reg not in list for other types. */
6879 else if (range
& (1 << base_reg
))
6880 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
6884 /* Not allowed for type 2. */
6885 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
6886 as_warn (_("writeback of base register is UNPREDICTABLE"));
6887 /* Only allowed if base reg not in list, or first in list. */
6888 else if ((range
& (1 << base_reg
))
6889 && (range
& ((1 << base_reg
) - 1)))
6890 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
6895 /* ARMv5TE load-consecutive (argument parse)
6904 constraint (inst
.operands
[0].reg
% 2 != 0,
6905 _("first destination register must be even"));
6906 constraint (inst
.operands
[1].present
6907 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
6908 _("can only load two consecutive registers"));
6909 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
6910 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
6912 if (!inst
.operands
[1].present
)
6913 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
6915 if (inst
.instruction
& LOAD_BIT
)
6917 /* encode_arm_addr_mode_3 will diagnose overlap between the base
6918 register and the first register written; we have to diagnose
6919 overlap between the base and the second register written here. */
6921 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
6922 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
6923 as_warn (_("base register written back, and overlaps "
6924 "second destination register"));
6926 /* For an index-register load, the index register must not overlap the
6927 destination (even if not write-back). */
6928 else if (inst
.operands
[2].immisreg
6929 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
6930 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
6931 as_warn (_("index register overlaps destination register"));
6934 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6935 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
6941 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
6942 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
6943 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
6944 || inst
.operands
[1].negative
6945 /* This can arise if the programmer has written
6947 or if they have mistakenly used a register name as the last
6950 It is very difficult to distinguish between these two cases
6951 because "rX" might actually be a label. ie the register
6952 name has been occluded by a symbol of the same name. So we
6953 just generate a general 'bad addressing mode' type error
6954 message and leave it up to the programmer to discover the
6955 true cause and fix their mistake. */
6956 || (inst
.operands
[1].reg
== REG_PC
),
6959 constraint (inst
.reloc
.exp
.X_op
!= O_constant
6960 || inst
.reloc
.exp
.X_add_number
!= 0,
6961 _("offset must be zero in ARM encoding"));
6963 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6964 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6965 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6971 constraint (inst
.operands
[0].reg
% 2 != 0,
6972 _("even register required"));
6973 constraint (inst
.operands
[1].present
6974 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
6975 _("can only load two consecutive registers"));
6976 /* If op 1 were present and equal to PC, this function wouldn't
6977 have been called in the first place. */
6978 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
6980 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6981 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6987 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6988 if (!inst
.operands
[1].isreg
)
6989 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
6991 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
6997 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
6999 if (inst
.operands
[1].preind
)
7001 constraint (inst
.reloc
.exp
.X_op
!= O_constant
||
7002 inst
.reloc
.exp
.X_add_number
!= 0,
7003 _("this instruction requires a post-indexed address"));
7005 inst
.operands
[1].preind
= 0;
7006 inst
.operands
[1].postind
= 1;
7007 inst
.operands
[1].writeback
= 1;
7009 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7010 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7013 /* Halfword and signed-byte load/store operations. */
7018 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7019 if (!inst
.operands
[1].isreg
)
7020 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7022 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7028 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7030 if (inst
.operands
[1].preind
)
7032 constraint (inst
.reloc
.exp
.X_op
!= O_constant
||
7033 inst
.reloc
.exp
.X_add_number
!= 0,
7034 _("this instruction requires a post-indexed address"));
7036 inst
.operands
[1].preind
= 0;
7037 inst
.operands
[1].postind
= 1;
7038 inst
.operands
[1].writeback
= 1;
7040 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7041 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7044 /* Co-processor register load/store.
7045 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7049 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7050 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7051 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7057 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7058 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7059 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7060 && !(inst
.instruction
& 0x00400000))
7061 as_tsktsk (_("Rd and Rm should be different in mla"));
7063 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7064 inst
.instruction
|= inst
.operands
[1].reg
;
7065 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7066 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7072 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7073 encode_arm_shifter_operand (1);
7076 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7083 top
= (inst
.instruction
& 0x00400000) != 0;
7084 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7085 _(":lower16: not allowed this instruction"));
7086 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7087 _(":upper16: not allowed instruction"));
7088 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7089 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7091 imm
= inst
.reloc
.exp
.X_add_number
;
7092 /* The value is in two pieces: 0:11, 16:19. */
7093 inst
.instruction
|= (imm
& 0x00000fff);
7094 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7098 static void do_vfp_nsyn_opcode (const char *);
7101 do_vfp_nsyn_mrs (void)
7103 if (inst
.operands
[0].isvec
)
7105 if (inst
.operands
[1].reg
!= 1)
7106 first_error (_("operand 1 must be FPSCR"));
7107 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7108 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7109 do_vfp_nsyn_opcode ("fmstat");
7111 else if (inst
.operands
[1].isvec
)
7112 do_vfp_nsyn_opcode ("fmrx");
7120 do_vfp_nsyn_msr (void)
7122 if (inst
.operands
[0].isvec
)
7123 do_vfp_nsyn_opcode ("fmxr");
7133 if (do_vfp_nsyn_mrs () == SUCCESS
)
7136 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7137 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7139 _("'CPSR' or 'SPSR' expected"));
7140 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7141 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7144 /* Two possible forms:
7145 "{C|S}PSR_<field>, Rm",
7146 "{C|S}PSR_f, #expression". */
7151 if (do_vfp_nsyn_msr () == SUCCESS
)
7154 inst
.instruction
|= inst
.operands
[0].imm
;
7155 if (inst
.operands
[1].isreg
)
7156 inst
.instruction
|= inst
.operands
[1].reg
;
7159 inst
.instruction
|= INST_IMMEDIATE
;
7160 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7161 inst
.reloc
.pc_rel
= 0;
7168 if (!inst
.operands
[2].present
)
7169 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7170 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7171 inst
.instruction
|= inst
.operands
[1].reg
;
7172 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7174 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7175 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7176 as_tsktsk (_("Rd and Rm should be different in mul"));
7179 /* Long Multiply Parser
7180 UMULL RdLo, RdHi, Rm, Rs
7181 SMULL RdLo, RdHi, Rm, Rs
7182 UMLAL RdLo, RdHi, Rm, Rs
7183 SMLAL RdLo, RdHi, Rm, Rs. */
7188 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7189 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7190 inst
.instruction
|= inst
.operands
[2].reg
;
7191 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7193 /* rdhi, rdlo and rm must all be different. */
7194 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7195 || inst
.operands
[0].reg
== inst
.operands
[2].reg
7196 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7197 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7203 if (inst
.operands
[0].present
)
7205 /* Architectural NOP hints are CPSR sets with no bits selected. */
7206 inst
.instruction
&= 0xf0000000;
7207 inst
.instruction
|= 0x0320f000 + inst
.operands
[0].imm
;
7211 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7212 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7213 Condition defaults to COND_ALWAYS.
7214 Error if Rd, Rn or Rm are R15. */
7219 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7220 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7221 inst
.instruction
|= inst
.operands
[2].reg
;
7222 if (inst
.operands
[3].present
)
7223 encode_arm_shift (3);
7226 /* ARM V6 PKHTB (Argument Parse). */
7231 if (!inst
.operands
[3].present
)
7233 /* If the shift specifier is omitted, turn the instruction
7234 into pkhbt rd, rm, rn. */
7235 inst
.instruction
&= 0xfff00010;
7236 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7237 inst
.instruction
|= inst
.operands
[1].reg
;
7238 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7242 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7243 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7244 inst
.instruction
|= inst
.operands
[2].reg
;
7245 encode_arm_shift (3);
7249 /* ARMv5TE: Preload-Cache
7253 Syntactically, like LDR with B=1, W=0, L=1. */
7258 constraint (!inst
.operands
[0].isreg
,
7259 _("'[' expected after PLD mnemonic"));
7260 constraint (inst
.operands
[0].postind
,
7261 _("post-indexed expression used in preload instruction"));
7262 constraint (inst
.operands
[0].writeback
,
7263 _("writeback used in preload instruction"));
7264 constraint (!inst
.operands
[0].preind
,
7265 _("unindexed addressing used in preload instruction"));
7266 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7269 /* ARMv7: PLI <addr_mode> */
7273 constraint (!inst
.operands
[0].isreg
,
7274 _("'[' expected after PLI mnemonic"));
7275 constraint (inst
.operands
[0].postind
,
7276 _("post-indexed expression used in preload instruction"));
7277 constraint (inst
.operands
[0].writeback
,
7278 _("writeback used in preload instruction"));
7279 constraint (!inst
.operands
[0].preind
,
7280 _("unindexed addressing used in preload instruction"));
7281 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7282 inst
.instruction
&= ~PRE_INDEX
;
7288 inst
.operands
[1] = inst
.operands
[0];
7289 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7290 inst
.operands
[0].isreg
= 1;
7291 inst
.operands
[0].writeback
= 1;
7292 inst
.operands
[0].reg
= REG_SP
;
7296 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7297 word at the specified address and the following word
7299 Unconditionally executed.
7300 Error if Rn is R15. */
7305 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7306 if (inst
.operands
[0].writeback
)
7307 inst
.instruction
|= WRITE_BACK
;
7310 /* ARM V6 ssat (argument parse). */
7315 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7316 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7317 inst
.instruction
|= inst
.operands
[2].reg
;
7319 if (inst
.operands
[3].present
)
7320 encode_arm_shift (3);
7323 /* ARM V6 usat (argument parse). */
7328 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7329 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7330 inst
.instruction
|= inst
.operands
[2].reg
;
7332 if (inst
.operands
[3].present
)
7333 encode_arm_shift (3);
7336 /* ARM V6 ssat16 (argument parse). */
7341 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7342 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7343 inst
.instruction
|= inst
.operands
[2].reg
;
7349 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7350 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7351 inst
.instruction
|= inst
.operands
[2].reg
;
7354 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7355 preserving the other bits.
7357 setend <endian_specifier>, where <endian_specifier> is either
7363 if (inst
.operands
[0].imm
)
7364 inst
.instruction
|= 0x200;
7370 unsigned int Rm
= (inst
.operands
[1].present
7371 ? inst
.operands
[1].reg
7372 : inst
.operands
[0].reg
);
7374 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7375 inst
.instruction
|= Rm
;
7376 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7378 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7379 inst
.instruction
|= SHIFT_BY_REG
;
7382 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7388 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7389 inst
.reloc
.pc_rel
= 0;
7395 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7396 inst
.reloc
.pc_rel
= 0;
7399 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7400 SMLAxy{cond} Rd,Rm,Rs,Rn
7401 SMLAWy{cond} Rd,Rm,Rs,Rn
7402 Error if any register is R15. */
7407 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7408 inst
.instruction
|= inst
.operands
[1].reg
;
7409 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7410 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7413 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7414 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7415 Error if any register is R15.
7416 Warning if Rdlo == Rdhi. */
7421 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7422 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7423 inst
.instruction
|= inst
.operands
[2].reg
;
7424 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7426 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7427 as_tsktsk (_("rdhi and rdlo must be different"));
7430 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7431 SMULxy{cond} Rd,Rm,Rs
7432 Error if any register is R15. */
7437 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7438 inst
.instruction
|= inst
.operands
[1].reg
;
7439 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7442 /* ARM V6 srs (argument parse). The variable fields in the encoding are
7443 the same for both ARM and Thumb-2. */
7450 if (inst
.operands
[0].present
)
7452 reg
= inst
.operands
[0].reg
;
7453 constraint (reg
!= 13, _("SRS base register must be r13"));
7458 inst
.instruction
|= reg
<< 16;
7459 inst
.instruction
|= inst
.operands
[1].imm
;
7460 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
7461 inst
.instruction
|= WRITE_BACK
;
7464 /* ARM V6 strex (argument parse). */
7469 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7470 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7471 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7472 || inst
.operands
[2].negative
7473 /* See comment in do_ldrex(). */
7474 || (inst
.operands
[2].reg
== REG_PC
),
7477 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7478 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
7480 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7481 || inst
.reloc
.exp
.X_add_number
!= 0,
7482 _("offset must be zero in ARM encoding"));
7484 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7485 inst
.instruction
|= inst
.operands
[1].reg
;
7486 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7487 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7493 constraint (inst
.operands
[1].reg
% 2 != 0,
7494 _("even register required"));
7495 constraint (inst
.operands
[2].present
7496 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
7497 _("can only store two consecutive registers"));
7498 /* If op 2 were present and equal to PC, this function wouldn't
7499 have been called in the first place. */
7500 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
7502 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7503 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
7504 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
7507 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7508 inst
.instruction
|= inst
.operands
[1].reg
;
7509 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7512 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7513 extends it to 32-bits, and adds the result to a value in another
7514 register. You can specify a rotation by 0, 8, 16, or 24 bits
7515 before extracting the 16-bit value.
7516 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7517 Condition defaults to COND_ALWAYS.
7518 Error if any register uses R15. */
7523 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7524 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7525 inst
.instruction
|= inst
.operands
[2].reg
;
7526 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
7531 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
7532 Condition defaults to COND_ALWAYS.
7533 Error if any register uses R15. */
7538 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7539 inst
.instruction
|= inst
.operands
[1].reg
;
7540 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
7543 /* VFP instructions. In a logical order: SP variant first, monad
7544 before dyad, arithmetic then move then load/store. */
7547 do_vfp_sp_monadic (void)
7549 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7550 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7554 do_vfp_sp_dyadic (void)
7556 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7557 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7558 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7562 do_vfp_sp_compare_z (void)
7564 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7568 do_vfp_dp_sp_cvt (void)
7570 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7571 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7575 do_vfp_sp_dp_cvt (void)
7577 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7578 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7582 do_vfp_reg_from_sp (void)
7584 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7585 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7589 do_vfp_reg2_from_sp2 (void)
7591 constraint (inst
.operands
[2].imm
!= 2,
7592 _("only two consecutive VFP SP registers allowed here"));
7593 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7594 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7595 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7599 do_vfp_sp_from_reg (void)
7601 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
7602 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7606 do_vfp_sp2_from_reg2 (void)
7608 constraint (inst
.operands
[0].imm
!= 2,
7609 _("only two consecutive VFP SP registers allowed here"));
7610 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
7611 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7612 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7616 do_vfp_sp_ldst (void)
7618 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7619 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7623 do_vfp_dp_ldst (void)
7625 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7626 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7631 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
7633 if (inst
.operands
[0].writeback
)
7634 inst
.instruction
|= WRITE_BACK
;
7636 constraint (ldstm_type
!= VFP_LDSTMIA
,
7637 _("this addressing mode requires base-register writeback"));
7638 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7639 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
7640 inst
.instruction
|= inst
.operands
[1].imm
;
7644 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
7648 if (inst
.operands
[0].writeback
)
7649 inst
.instruction
|= WRITE_BACK
;
7651 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
7652 _("this addressing mode requires base-register writeback"));
7654 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7655 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7657 count
= inst
.operands
[1].imm
<< 1;
7658 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
7661 inst
.instruction
|= count
;
7665 do_vfp_sp_ldstmia (void)
7667 vfp_sp_ldstm (VFP_LDSTMIA
);
7671 do_vfp_sp_ldstmdb (void)
7673 vfp_sp_ldstm (VFP_LDSTMDB
);
7677 do_vfp_dp_ldstmia (void)
7679 vfp_dp_ldstm (VFP_LDSTMIA
);
7683 do_vfp_dp_ldstmdb (void)
7685 vfp_dp_ldstm (VFP_LDSTMDB
);
7689 do_vfp_xp_ldstmia (void)
7691 vfp_dp_ldstm (VFP_LDSTMIAX
);
7695 do_vfp_xp_ldstmdb (void)
7697 vfp_dp_ldstm (VFP_LDSTMDBX
);
7701 do_vfp_dp_rd_rm (void)
7703 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7704 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7708 do_vfp_dp_rn_rd (void)
7710 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
7711 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7715 do_vfp_dp_rd_rn (void)
7717 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7718 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7722 do_vfp_dp_rd_rn_rm (void)
7724 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7725 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7726 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
7732 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7736 do_vfp_dp_rm_rd_rn (void)
7738 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
7739 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7740 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
7743 /* VFPv3 instructions. */
7745 do_vfp_sp_const (void)
7747 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7748 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
7749 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
7753 do_vfp_dp_const (void)
7755 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7756 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
7757 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
7761 vfp_conv (int srcsize
)
7763 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
7764 inst
.instruction
|= (immbits
& 1) << 5;
7765 inst
.instruction
|= (immbits
>> 1);
7769 do_vfp_sp_conv_16 (void)
7771 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7776 do_vfp_dp_conv_16 (void)
7778 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7783 do_vfp_sp_conv_32 (void)
7785 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7790 do_vfp_dp_conv_32 (void)
7792 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7797 /* FPA instructions. Also in a logical order. */
7802 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7803 inst
.instruction
|= inst
.operands
[1].reg
;
7807 do_fpa_ldmstm (void)
7809 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7810 switch (inst
.operands
[1].imm
)
7812 case 1: inst
.instruction
|= CP_T_X
; break;
7813 case 2: inst
.instruction
|= CP_T_Y
; break;
7814 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
7819 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
7821 /* The instruction specified "ea" or "fd", so we can only accept
7822 [Rn]{!}. The instruction does not really support stacking or
7823 unstacking, so we have to emulate these by setting appropriate
7824 bits and offsets. */
7825 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7826 || inst
.reloc
.exp
.X_add_number
!= 0,
7827 _("this instruction does not support indexing"));
7829 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
7830 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
7832 if (!(inst
.instruction
& INDEX_UP
))
7833 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
7835 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
7837 inst
.operands
[2].preind
= 0;
7838 inst
.operands
[2].postind
= 1;
7842 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7846 /* iWMMXt instructions: strictly in alphabetical order. */
7849 do_iwmmxt_tandorc (void)
7851 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
7855 do_iwmmxt_textrc (void)
7857 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7858 inst
.instruction
|= inst
.operands
[1].imm
;
7862 do_iwmmxt_textrm (void)
7864 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7865 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7866 inst
.instruction
|= inst
.operands
[2].imm
;
7870 do_iwmmxt_tinsr (void)
7872 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7873 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7874 inst
.instruction
|= inst
.operands
[2].imm
;
7878 do_iwmmxt_tmia (void)
7880 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
7881 inst
.instruction
|= inst
.operands
[1].reg
;
7882 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7886 do_iwmmxt_waligni (void)
7888 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7889 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7890 inst
.instruction
|= inst
.operands
[2].reg
;
7891 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
7895 do_iwmmxt_wmerge (void)
7897 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7898 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7899 inst
.instruction
|= inst
.operands
[2].reg
;
7900 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
7904 do_iwmmxt_wmov (void)
7906 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
7907 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7908 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7909 inst
.instruction
|= inst
.operands
[1].reg
;
7913 do_iwmmxt_wldstbh (void)
7916 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7918 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
7920 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
7921 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
7925 do_iwmmxt_wldstw (void)
7927 /* RIWR_RIWC clears .isreg for a control register. */
7928 if (!inst
.operands
[0].isreg
)
7930 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7931 inst
.instruction
|= 0xf0000000;
7934 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7935 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7939 do_iwmmxt_wldstd (void)
7941 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7942 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
7943 && inst
.operands
[1].immisreg
)
7945 inst
.instruction
&= ~0x1a000ff;
7946 inst
.instruction
|= (0xf << 28);
7947 if (inst
.operands
[1].preind
)
7948 inst
.instruction
|= PRE_INDEX
;
7949 if (!inst
.operands
[1].negative
)
7950 inst
.instruction
|= INDEX_UP
;
7951 if (inst
.operands
[1].writeback
)
7952 inst
.instruction
|= WRITE_BACK
;
7953 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7954 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
7955 inst
.instruction
|= inst
.operands
[1].imm
;
7958 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
7962 do_iwmmxt_wshufh (void)
7964 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7965 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7966 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
7967 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
7971 do_iwmmxt_wzero (void)
7973 /* WZERO reg is an alias for WANDN reg, reg, reg. */
7974 inst
.instruction
|= inst
.operands
[0].reg
;
7975 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7976 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7980 do_iwmmxt_wrwrwr_or_imm5 (void)
7982 if (inst
.operands
[2].isreg
)
7985 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
7986 _("immediate operand requires iWMMXt2"));
7988 if (inst
.operands
[2].imm
== 0)
7990 switch ((inst
.instruction
>> 20) & 0xf)
7996 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
7997 inst
.operands
[2].imm
= 16;
7998 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8004 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8005 inst
.operands
[2].imm
= 32;
8006 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8013 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8015 wrn
= (inst
.instruction
>> 16) & 0xf;
8016 inst
.instruction
&= 0xff0fff0f;
8017 inst
.instruction
|= wrn
;
8018 /* Bail out here; the instruction is now assembled. */
8023 /* Map 32 -> 0, etc. */
8024 inst
.operands
[2].imm
&= 0x1f;
8025 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8029 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8030 operations first, then control, shift, and load/store. */
8032 /* Insns like "foo X,Y,Z". */
8035 do_mav_triple (void)
8037 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8038 inst
.instruction
|= inst
.operands
[1].reg
;
8039 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8042 /* Insns like "foo W,X,Y,Z".
8043 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8048 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8049 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8050 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8051 inst
.instruction
|= inst
.operands
[3].reg
;
8054 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8058 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8061 /* Maverick shift immediate instructions.
8062 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8063 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8068 int imm
= inst
.operands
[2].imm
;
8070 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8071 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8073 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8074 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8075 Bit 4 should be 0. */
8076 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8078 inst
.instruction
|= imm
;
8081 /* XScale instructions. Also sorted arithmetic before move. */
8083 /* Xscale multiply-accumulate (argument parse)
8086 MIAxycc acc0,Rm,Rs. */
8091 inst
.instruction
|= inst
.operands
[1].reg
;
8092 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8095 /* Xscale move-accumulator-register (argument parse)
8097 MARcc acc0,RdLo,RdHi. */
8102 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8103 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8106 /* Xscale move-register-accumulator (argument parse)
8108 MRAcc RdLo,RdHi,acc0. */
8113 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8114 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8115 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8118 /* Encoding functions relevant only to Thumb. */
8120 /* inst.operands[i] is a shifted-register operand; encode
8121 it into inst.instruction in the format used by Thumb32. */
8124 encode_thumb32_shifted_operand (int i
)
8126 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8127 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8129 constraint (inst
.operands
[i
].immisreg
,
8130 _("shift by register not allowed in thumb mode"));
8131 inst
.instruction
|= inst
.operands
[i
].reg
;
8132 if (shift
== SHIFT_RRX
)
8133 inst
.instruction
|= SHIFT_ROR
<< 4;
8136 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8137 _("expression too complex"));
8139 constraint (value
> 32
8140 || (value
== 32 && (shift
== SHIFT_LSL
8141 || shift
== SHIFT_ROR
)),
8142 _("shift expression is too large"));
8146 else if (value
== 32)
8149 inst
.instruction
|= shift
<< 4;
8150 inst
.instruction
|= (value
& 0x1c) << 10;
8151 inst
.instruction
|= (value
& 0x03) << 6;
8156 /* inst.operands[i] was set up by parse_address. Encode it into a
8157 Thumb32 format load or store instruction. Reject forms that cannot
8158 be used with such instructions. If is_t is true, reject forms that
8159 cannot be used with a T instruction; if is_d is true, reject forms
8160 that cannot be used with a D instruction. */
8163 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8165 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8167 constraint (!inst
.operands
[i
].isreg
,
8168 _("Instruction does not support =N addresses"));
8170 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8171 if (inst
.operands
[i
].immisreg
)
8173 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
8174 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8175 constraint (inst
.operands
[i
].negative
,
8176 _("Thumb does not support negative register indexing"));
8177 constraint (inst
.operands
[i
].postind
,
8178 _("Thumb does not support register post-indexing"));
8179 constraint (inst
.operands
[i
].writeback
,
8180 _("Thumb does not support register indexing with writeback"));
8181 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8182 _("Thumb supports only LSL in shifted register indexing"));
8184 inst
.instruction
|= inst
.operands
[i
].imm
;
8185 if (inst
.operands
[i
].shifted
)
8187 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8188 _("expression too complex"));
8189 constraint (inst
.reloc
.exp
.X_add_number
< 0
8190 || inst
.reloc
.exp
.X_add_number
> 3,
8191 _("shift out of range"));
8192 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8194 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8196 else if (inst
.operands
[i
].preind
)
8198 constraint (is_pc
&& inst
.operands
[i
].writeback
,
8199 _("cannot use writeback with PC-relative addressing"));
8200 constraint (is_t
&& inst
.operands
[i
].writeback
,
8201 _("cannot use writeback with this instruction"));
8205 inst
.instruction
|= 0x01000000;
8206 if (inst
.operands
[i
].writeback
)
8207 inst
.instruction
|= 0x00200000;
8211 inst
.instruction
|= 0x00000c00;
8212 if (inst
.operands
[i
].writeback
)
8213 inst
.instruction
|= 0x00000100;
8215 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8217 else if (inst
.operands
[i
].postind
)
8219 assert (inst
.operands
[i
].writeback
);
8220 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8221 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8224 inst
.instruction
|= 0x00200000;
8226 inst
.instruction
|= 0x00000900;
8227 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8229 else /* unindexed - only for coprocessor */
8230 inst
.error
= _("instruction does not accept unindexed addressing");
8233 /* Table of Thumb instructions which exist in both 16- and 32-bit
8234 encodings (the latter only in post-V6T2 cores). The index is the
8235 value used in the insns table below. When there is more than one
8236 possible 16-bit encoding for the instruction, this table always
8238 Also contains several pseudo-instructions used during relaxation. */
8239 #define T16_32_TAB \
8240 X(adc, 4140, eb400000), \
8241 X(adcs, 4140, eb500000), \
8242 X(add, 1c00, eb000000), \
8243 X(adds, 1c00, eb100000), \
8244 X(addi, 0000, f1000000), \
8245 X(addis, 0000, f1100000), \
8246 X(add_pc,000f, f20f0000), \
8247 X(add_sp,000d, f10d0000), \
8248 X(adr, 000f, f20f0000), \
8249 X(and, 4000, ea000000), \
8250 X(ands, 4000, ea100000), \
8251 X(asr, 1000, fa40f000), \
8252 X(asrs, 1000, fa50f000), \
8253 X(b, e000, f000b000), \
8254 X(bcond, d000, f0008000), \
8255 X(bic, 4380, ea200000), \
8256 X(bics, 4380, ea300000), \
8257 X(cmn, 42c0, eb100f00), \
8258 X(cmp, 2800, ebb00f00), \
8259 X(cpsie, b660, f3af8400), \
8260 X(cpsid, b670, f3af8600), \
8261 X(cpy, 4600, ea4f0000), \
8262 X(dec_sp,80dd, f1ad0d00), \
8263 X(eor, 4040, ea800000), \
8264 X(eors, 4040, ea900000), \
8265 X(inc_sp,00dd, f10d0d00), \
8266 X(ldmia, c800, e8900000), \
8267 X(ldr, 6800, f8500000), \
8268 X(ldrb, 7800, f8100000), \
8269 X(ldrh, 8800, f8300000), \
8270 X(ldrsb, 5600, f9100000), \
8271 X(ldrsh, 5e00, f9300000), \
8272 X(ldr_pc,4800, f85f0000), \
8273 X(ldr_pc2,4800, f85f0000), \
8274 X(ldr_sp,9800, f85d0000), \
8275 X(lsl, 0000, fa00f000), \
8276 X(lsls, 0000, fa10f000), \
8277 X(lsr, 0800, fa20f000), \
8278 X(lsrs, 0800, fa30f000), \
8279 X(mov, 2000, ea4f0000), \
8280 X(movs, 2000, ea5f0000), \
8281 X(mul, 4340, fb00f000), \
8282 X(muls, 4340, ffffffff), /* no 32b muls */ \
8283 X(mvn, 43c0, ea6f0000), \
8284 X(mvns, 43c0, ea7f0000), \
8285 X(neg, 4240, f1c00000), /* rsb #0 */ \
8286 X(negs, 4240, f1d00000), /* rsbs #0 */ \
8287 X(orr, 4300, ea400000), \
8288 X(orrs, 4300, ea500000), \
8289 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8290 X(push, b400, e92d0000), /* stmdb sp!,... */ \
8291 X(rev, ba00, fa90f080), \
8292 X(rev16, ba40, fa90f090), \
8293 X(revsh, bac0, fa90f0b0), \
8294 X(ror, 41c0, fa60f000), \
8295 X(rors, 41c0, fa70f000), \
8296 X(sbc, 4180, eb600000), \
8297 X(sbcs, 4180, eb700000), \
8298 X(stmia, c000, e8800000), \
8299 X(str, 6000, f8400000), \
8300 X(strb, 7000, f8000000), \
8301 X(strh, 8000, f8200000), \
8302 X(str_sp,9000, f84d0000), \
8303 X(sub, 1e00, eba00000), \
8304 X(subs, 1e00, ebb00000), \
8305 X(subi, 8000, f1a00000), \
8306 X(subis, 8000, f1b00000), \
8307 X(sxtb, b240, fa4ff080), \
8308 X(sxth, b200, fa0ff080), \
8309 X(tst, 4200, ea100f00), \
8310 X(uxtb, b2c0, fa5ff080), \
8311 X(uxth, b280, fa1ff080), \
8312 X(nop, bf00, f3af8000), \
8313 X(yield, bf10, f3af8001), \
8314 X(wfe, bf20, f3af8002), \
8315 X(wfi, bf30, f3af8003), \
8316 X(sev, bf40, f3af9004), /* typo, 8004? */
8318 /* To catch errors in encoding functions, the codes are all offset by
8319 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8320 as 16-bit instructions. */
8321 #define X(a,b,c) T_MNEM_##a
8322 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8325 #define X(a,b,c) 0x##b
8326 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8327 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8330 #define X(a,b,c) 0x##c
8331 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8332 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8333 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8337 /* Thumb instruction encoders, in alphabetical order. */
8341 do_t_add_sub_w (void)
8345 Rd
= inst
.operands
[0].reg
;
8346 Rn
= inst
.operands
[1].reg
;
8348 constraint (Rd
== 15, _("PC not allowed as destination"));
8349 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8350 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8353 /* Parse an add or subtract instruction. We get here with inst.instruction
8354 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8361 Rd
= inst
.operands
[0].reg
;
8362 Rs
= (inst
.operands
[1].present
8363 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8364 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8372 flags
= (inst
.instruction
== T_MNEM_adds
8373 || inst
.instruction
== T_MNEM_subs
);
8375 narrow
= (current_it_mask
== 0);
8377 narrow
= (current_it_mask
!= 0);
8378 if (!inst
.operands
[2].isreg
)
8382 add
= (inst
.instruction
== T_MNEM_add
8383 || inst
.instruction
== T_MNEM_adds
);
8385 if (inst
.size_req
!= 4)
8387 /* Attempt to use a narrow opcode, with relaxation if
8389 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8390 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8391 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8392 opcode
= T_MNEM_add_sp
;
8393 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8394 opcode
= T_MNEM_add_pc
;
8395 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8398 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8400 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8404 inst
.instruction
= THUMB_OP16(opcode
);
8405 inst
.instruction
|= (Rd
<< 4) | Rs
;
8406 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8407 if (inst
.size_req
!= 2)
8408 inst
.relax
= opcode
;
8411 constraint (inst
.size_req
== 2, BAD_HIREG
);
8413 if (inst
.size_req
== 4
8414 || (inst
.size_req
!= 2 && !opcode
))
8418 /* Always use addw/subw. */
8419 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
8420 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8424 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8425 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
8428 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8430 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
8432 inst
.instruction
|= Rd
<< 8;
8433 inst
.instruction
|= Rs
<< 16;
8438 Rn
= inst
.operands
[2].reg
;
8439 /* See if we can do this with a 16-bit instruction. */
8440 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
8442 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8447 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
8448 || inst
.instruction
== T_MNEM_add
)
8451 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8455 if (inst
.instruction
== T_MNEM_add
)
8459 inst
.instruction
= T_OPCODE_ADD_HI
;
8460 inst
.instruction
|= (Rd
& 8) << 4;
8461 inst
.instruction
|= (Rd
& 7);
8462 inst
.instruction
|= Rn
<< 3;
8465 /* ... because addition is commutative! */
8468 inst
.instruction
= T_OPCODE_ADD_HI
;
8469 inst
.instruction
|= (Rd
& 8) << 4;
8470 inst
.instruction
|= (Rd
& 7);
8471 inst
.instruction
|= Rs
<< 3;
8476 /* If we get here, it can't be done in 16 bits. */
8477 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
8478 _("shift must be constant"));
8479 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8480 inst
.instruction
|= Rd
<< 8;
8481 inst
.instruction
|= Rs
<< 16;
8482 encode_thumb32_shifted_operand (2);
8487 constraint (inst
.instruction
== T_MNEM_adds
8488 || inst
.instruction
== T_MNEM_subs
,
8491 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
8493 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
8494 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
8497 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8499 inst
.instruction
|= (Rd
<< 4) | Rs
;
8500 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8504 Rn
= inst
.operands
[2].reg
;
8505 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
8507 /* We now have Rd, Rs, and Rn set to registers. */
8508 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8510 /* Can't do this for SUB. */
8511 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
8512 inst
.instruction
= T_OPCODE_ADD_HI
;
8513 inst
.instruction
|= (Rd
& 8) << 4;
8514 inst
.instruction
|= (Rd
& 7);
8516 inst
.instruction
|= Rn
<< 3;
8518 inst
.instruction
|= Rs
<< 3;
8520 constraint (1, _("dest must overlap one source register"));
8524 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8525 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
8526 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8534 if (unified_syntax
&& inst
.size_req
== 0 && inst
.operands
[0].reg
<= 7)
8536 /* Defer to section relaxation. */
8537 inst
.relax
= inst
.instruction
;
8538 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8539 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8541 else if (unified_syntax
&& inst
.size_req
!= 2)
8543 /* Generate a 32-bit opcode. */
8544 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8545 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8546 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
8547 inst
.reloc
.pc_rel
= 1;
8551 /* Generate a 16-bit opcode. */
8552 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8553 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8554 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
8555 inst
.reloc
.pc_rel
= 1;
8557 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8561 /* Arithmetic instructions for which there is just one 16-bit
8562 instruction encoding, and it allows only two low registers.
8563 For maximal compatibility with ARM syntax, we allow three register
8564 operands even when Thumb-32 instructions are not available, as long
8565 as the first two are identical. For instance, both "sbc r0,r1" and
8566 "sbc r0,r0,r1" are allowed. */
8572 Rd
= inst
.operands
[0].reg
;
8573 Rs
= (inst
.operands
[1].present
8574 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8575 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8576 Rn
= inst
.operands
[2].reg
;
8580 if (!inst
.operands
[2].isreg
)
8582 /* For an immediate, we always generate a 32-bit opcode;
8583 section relaxation will shrink it later if possible. */
8584 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8585 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8586 inst
.instruction
|= Rd
<< 8;
8587 inst
.instruction
|= Rs
<< 16;
8588 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8594 /* See if we can do this with a 16-bit instruction. */
8595 if (THUMB_SETS_FLAGS (inst
.instruction
))
8596 narrow
= current_it_mask
== 0;
8598 narrow
= current_it_mask
!= 0;
8600 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8602 if (inst
.operands
[2].shifted
)
8604 if (inst
.size_req
== 4)
8610 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8611 inst
.instruction
|= Rd
;
8612 inst
.instruction
|= Rn
<< 3;
8616 /* If we get here, it can't be done in 16 bits. */
8617 constraint (inst
.operands
[2].shifted
8618 && inst
.operands
[2].immisreg
,
8619 _("shift must be constant"));
8620 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8621 inst
.instruction
|= Rd
<< 8;
8622 inst
.instruction
|= Rs
<< 16;
8623 encode_thumb32_shifted_operand (2);
8628 /* On its face this is a lie - the instruction does set the
8629 flags. However, the only supported mnemonic in this mode
8631 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8633 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8634 _("unshifted register required"));
8635 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8636 constraint (Rd
!= Rs
,
8637 _("dest and source1 must be the same register"));
8639 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8640 inst
.instruction
|= Rd
;
8641 inst
.instruction
|= Rn
<< 3;
8645 /* Similarly, but for instructions where the arithmetic operation is
8646 commutative, so we can allow either of them to be different from
8647 the destination operand in a 16-bit instruction. For instance, all
8648 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
8655 Rd
= inst
.operands
[0].reg
;
8656 Rs
= (inst
.operands
[1].present
8657 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8658 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8659 Rn
= inst
.operands
[2].reg
;
8663 if (!inst
.operands
[2].isreg
)
8665 /* For an immediate, we always generate a 32-bit opcode;
8666 section relaxation will shrink it later if possible. */
8667 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8668 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8669 inst
.instruction
|= Rd
<< 8;
8670 inst
.instruction
|= Rs
<< 16;
8671 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8677 /* See if we can do this with a 16-bit instruction. */
8678 if (THUMB_SETS_FLAGS (inst
.instruction
))
8679 narrow
= current_it_mask
== 0;
8681 narrow
= current_it_mask
!= 0;
8683 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8685 if (inst
.operands
[2].shifted
)
8687 if (inst
.size_req
== 4)
8694 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8695 inst
.instruction
|= Rd
;
8696 inst
.instruction
|= Rn
<< 3;
8701 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8702 inst
.instruction
|= Rd
;
8703 inst
.instruction
|= Rs
<< 3;
8708 /* If we get here, it can't be done in 16 bits. */
8709 constraint (inst
.operands
[2].shifted
8710 && inst
.operands
[2].immisreg
,
8711 _("shift must be constant"));
8712 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8713 inst
.instruction
|= Rd
<< 8;
8714 inst
.instruction
|= Rs
<< 16;
8715 encode_thumb32_shifted_operand (2);
8720 /* On its face this is a lie - the instruction does set the
8721 flags. However, the only supported mnemonic in this mode
8723 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8725 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8726 _("unshifted register required"));
8727 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8729 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8730 inst
.instruction
|= Rd
;
8733 inst
.instruction
|= Rn
<< 3;
8735 inst
.instruction
|= Rs
<< 3;
8737 constraint (1, _("dest must overlap one source register"));
8744 if (inst
.operands
[0].present
)
8746 constraint ((inst
.instruction
& 0xf0) != 0x40
8747 && inst
.operands
[0].imm
!= 0xf,
8748 "bad barrier type");
8749 inst
.instruction
|= inst
.operands
[0].imm
;
8752 inst
.instruction
|= 0xf;
8758 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8759 constraint (msb
> 32, _("bit-field extends past end of register"));
8760 /* The instruction encoding stores the LSB and MSB,
8761 not the LSB and width. */
8762 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8763 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
8764 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
8765 inst
.instruction
|= msb
- 1;
8773 /* #0 in second position is alternative syntax for bfc, which is
8774 the same instruction but with REG_PC in the Rm field. */
8775 if (!inst
.operands
[1].isreg
)
8776 inst
.operands
[1].reg
= REG_PC
;
8778 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8779 constraint (msb
> 32, _("bit-field extends past end of register"));
8780 /* The instruction encoding stores the LSB and MSB,
8781 not the LSB and width. */
8782 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8783 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8784 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8785 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8786 inst
.instruction
|= msb
- 1;
8792 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8793 _("bit-field extends past end of register"));
8794 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8795 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8796 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8797 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8798 inst
.instruction
|= inst
.operands
[3].imm
- 1;
8801 /* ARM V5 Thumb BLX (argument parse)
8802 BLX <target_addr> which is BLX(1)
8803 BLX <Rm> which is BLX(2)
8804 Unfortunately, there are two different opcodes for this mnemonic.
8805 So, the insns[].value is not used, and the code here zaps values
8806 into inst.instruction.
8808 ??? How to take advantage of the additional two bits of displacement
8809 available in Thumb32 mode? Need new relocation? */
8814 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8815 if (inst
.operands
[0].isreg
)
8816 /* We have a register, so this is BLX(2). */
8817 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8820 /* No register. This must be BLX(1). */
8821 inst
.instruction
= 0xf000e800;
8823 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8824 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8827 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
8828 inst
.reloc
.pc_rel
= 1;
8838 if (current_it_mask
)
8840 /* Conditional branches inside IT blocks are encoded as unconditional
8843 /* A branch must be the last instruction in an IT block. */
8844 constraint (current_it_mask
!= 0x10, BAD_BRANCH
);
8849 if (cond
!= COND_ALWAYS
)
8850 opcode
= T_MNEM_bcond
;
8852 opcode
= inst
.instruction
;
8854 if (unified_syntax
&& inst
.size_req
== 4)
8856 inst
.instruction
= THUMB_OP32(opcode
);
8857 if (cond
== COND_ALWAYS
)
8858 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
8861 assert (cond
!= 0xF);
8862 inst
.instruction
|= cond
<< 22;
8863 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
8868 inst
.instruction
= THUMB_OP16(opcode
);
8869 if (cond
== COND_ALWAYS
)
8870 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
8873 inst
.instruction
|= cond
<< 8;
8874 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
8876 /* Allow section relaxation. */
8877 if (unified_syntax
&& inst
.size_req
!= 2)
8878 inst
.relax
= opcode
;
8881 inst
.reloc
.pc_rel
= 1;
8887 constraint (inst
.cond
!= COND_ALWAYS
,
8888 _("instruction is always unconditional"));
8889 if (inst
.operands
[0].present
)
8891 constraint (inst
.operands
[0].imm
> 255,
8892 _("immediate value out of range"));
8893 inst
.instruction
|= inst
.operands
[0].imm
;
8898 do_t_branch23 (void)
8900 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8901 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8902 inst
.reloc
.pc_rel
= 1;
8904 /* If the destination of the branch is a defined symbol which does not have
8905 the THUMB_FUNC attribute, then we must be calling a function which has
8906 the (interfacearm) attribute. We look for the Thumb entry point to that
8907 function and change the branch to refer to that function instead. */
8908 if ( inst
.reloc
.exp
.X_op
== O_symbol
8909 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8910 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8911 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8912 inst
.reloc
.exp
.X_add_symbol
=
8913 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
8919 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8920 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8921 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
8922 should cause the alignment to be checked once it is known. This is
8923 because BX PC only works if the instruction is word aligned. */
8929 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8930 if (inst
.operands
[0].reg
== REG_PC
)
8931 as_tsktsk (_("use of r15 in bxj is not really useful"));
8933 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8939 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8940 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8941 inst
.instruction
|= inst
.operands
[1].reg
;
8947 constraint (current_it_mask
, BAD_NOT_IT
);
8948 inst
.instruction
|= inst
.operands
[0].imm
;
8954 constraint (current_it_mask
, BAD_NOT_IT
);
8956 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
8957 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
8959 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
8960 inst
.instruction
= 0xf3af8000;
8961 inst
.instruction
|= imod
<< 9;
8962 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
8963 if (inst
.operands
[1].present
)
8964 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
8968 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
8969 && (inst
.operands
[0].imm
& 4),
8970 _("selected processor does not support 'A' form "
8971 "of this instruction"));
8972 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
8973 _("Thumb does not support the 2-argument "
8974 "form of this instruction"));
8975 inst
.instruction
|= inst
.operands
[0].imm
;
8979 /* THUMB CPY instruction (argument parse). */
8984 if (inst
.size_req
== 4)
8986 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
8987 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8988 inst
.instruction
|= inst
.operands
[1].reg
;
8992 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
8993 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
8994 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9001 constraint (current_it_mask
, BAD_NOT_IT
);
9002 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9003 inst
.instruction
|= inst
.operands
[0].reg
;
9004 inst
.reloc
.pc_rel
= 1;
9005 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9011 inst
.instruction
|= inst
.operands
[0].imm
;
9017 if (!inst
.operands
[1].present
)
9018 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9019 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9020 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9021 inst
.instruction
|= inst
.operands
[2].reg
;
9027 if (unified_syntax
&& inst
.size_req
== 4)
9028 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9030 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9036 unsigned int cond
= inst
.operands
[0].imm
;
9038 constraint (current_it_mask
, BAD_NOT_IT
);
9039 current_it_mask
= (inst
.instruction
& 0xf) | 0x10;
9042 /* If the condition is a negative condition, invert the mask. */
9043 if ((cond
& 0x1) == 0x0)
9045 unsigned int mask
= inst
.instruction
& 0x000f;
9047 if ((mask
& 0x7) == 0)
9048 /* no conversion needed */;
9049 else if ((mask
& 0x3) == 0)
9051 else if ((mask
& 0x1) == 0)
9056 inst
.instruction
&= 0xfff0;
9057 inst
.instruction
|= mask
;
9060 inst
.instruction
|= cond
<< 4;
9066 /* This really doesn't seem worth it. */
9067 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9068 _("expression too complex"));
9069 constraint (inst
.operands
[1].writeback
,
9070 _("Thumb load/store multiple does not support {reglist}^"));
9074 /* See if we can use a 16-bit instruction. */
9075 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9076 && inst
.size_req
!= 4
9077 && inst
.operands
[0].reg
<= 7
9078 && !(inst
.operands
[1].imm
& ~0xff)
9079 && (inst
.instruction
== T_MNEM_stmia
9080 ? inst
.operands
[0].writeback
9081 : (inst
.operands
[0].writeback
9082 == !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))))
9084 if (inst
.instruction
== T_MNEM_stmia
9085 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9086 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9087 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9088 inst
.operands
[0].reg
);
9090 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9091 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9092 inst
.instruction
|= inst
.operands
[1].imm
;
9096 if (inst
.operands
[1].imm
& (1 << 13))
9097 as_warn (_("SP should not be in register list"));
9098 if (inst
.instruction
== T_MNEM_stmia
)
9100 if (inst
.operands
[1].imm
& (1 << 15))
9101 as_warn (_("PC should not be in register list"));
9102 if (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9103 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9104 inst
.operands
[0].reg
);
9108 if (inst
.operands
[1].imm
& (1 << 14)
9109 && inst
.operands
[1].imm
& (1 << 15))
9110 as_warn (_("LR and PC should not both be in register list"));
9111 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9112 && inst
.operands
[0].writeback
)
9113 as_warn (_("base register should not be in register list "
9114 "when written back"));
9116 if (inst
.instruction
< 0xffff)
9117 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9118 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9119 inst
.instruction
|= inst
.operands
[1].imm
;
9120 if (inst
.operands
[0].writeback
)
9121 inst
.instruction
|= WRITE_BACK
;
9126 constraint (inst
.operands
[0].reg
> 7
9127 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9128 if (inst
.instruction
== T_MNEM_stmia
)
9130 if (!inst
.operands
[0].writeback
)
9131 as_warn (_("this instruction will write back the base register"));
9132 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9133 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9134 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9135 inst
.operands
[0].reg
);
9139 if (!inst
.operands
[0].writeback
9140 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9141 as_warn (_("this instruction will write back the base register"));
9142 else if (inst
.operands
[0].writeback
9143 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9144 as_warn (_("this instruction will not write back the base register"));
9147 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9148 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9149 inst
.instruction
|= inst
.operands
[1].imm
;
9156 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9157 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9158 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9159 || inst
.operands
[1].negative
,
9162 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9163 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9164 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9170 if (!inst
.operands
[1].present
)
9172 constraint (inst
.operands
[0].reg
== REG_LR
,
9173 _("r14 not allowed as first register "
9174 "when second register is omitted"));
9175 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9177 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9180 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9181 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9182 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9188 unsigned long opcode
;
9191 opcode
= inst
.instruction
;
9194 if (!inst
.operands
[1].isreg
)
9196 if (opcode
<= 0xffff)
9197 inst
.instruction
= THUMB_OP32 (opcode
);
9198 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9201 if (inst
.operands
[1].isreg
9202 && !inst
.operands
[1].writeback
9203 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9204 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9206 && inst
.size_req
!= 4)
9208 /* Insn may have a 16-bit form. */
9209 Rn
= inst
.operands
[1].reg
;
9210 if (inst
.operands
[1].immisreg
)
9212 inst
.instruction
= THUMB_OP16 (opcode
);
9214 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9217 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9218 && opcode
!= T_MNEM_ldrsb
)
9219 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9220 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9227 if (inst
.reloc
.pc_rel
)
9228 opcode
= T_MNEM_ldr_pc2
;
9230 opcode
= T_MNEM_ldr_pc
;
9234 if (opcode
== T_MNEM_ldr
)
9235 opcode
= T_MNEM_ldr_sp
;
9237 opcode
= T_MNEM_str_sp
;
9239 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9243 inst
.instruction
= inst
.operands
[0].reg
;
9244 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9246 inst
.instruction
|= THUMB_OP16 (opcode
);
9247 if (inst
.size_req
== 2)
9248 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9250 inst
.relax
= opcode
;
9254 /* Definitely a 32-bit variant. */
9255 inst
.instruction
= THUMB_OP32 (opcode
);
9256 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9257 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9261 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9263 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9265 /* Only [Rn,Rm] is acceptable. */
9266 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9267 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9268 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9269 || inst
.operands
[1].negative
,
9270 _("Thumb does not support this addressing mode"));
9271 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9275 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9276 if (!inst
.operands
[1].isreg
)
9277 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9280 constraint (!inst
.operands
[1].preind
9281 || inst
.operands
[1].shifted
9282 || inst
.operands
[1].writeback
,
9283 _("Thumb does not support this addressing mode"));
9284 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9286 constraint (inst
.instruction
& 0x0600,
9287 _("byte or halfword not valid for base register"));
9288 constraint (inst
.operands
[1].reg
== REG_PC
9289 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9290 _("r15 based store not allowed"));
9291 constraint (inst
.operands
[1].immisreg
,
9292 _("invalid base register for register offset"));
9294 if (inst
.operands
[1].reg
== REG_PC
)
9295 inst
.instruction
= T_OPCODE_LDR_PC
;
9296 else if (inst
.instruction
& THUMB_LOAD_BIT
)
9297 inst
.instruction
= T_OPCODE_LDR_SP
;
9299 inst
.instruction
= T_OPCODE_STR_SP
;
9301 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9302 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9306 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
9307 if (!inst
.operands
[1].immisreg
)
9309 /* Immediate offset. */
9310 inst
.instruction
|= inst
.operands
[0].reg
;
9311 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9312 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9316 /* Register offset. */
9317 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
9318 constraint (inst
.operands
[1].negative
,
9319 _("Thumb does not support this addressing mode"));
9322 switch (inst
.instruction
)
9324 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
9325 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
9326 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
9327 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
9328 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
9329 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
9330 case 0x5600 /* ldrsb */:
9331 case 0x5e00 /* ldrsh */: break;
9335 inst
.instruction
|= inst
.operands
[0].reg
;
9336 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9337 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
9343 if (!inst
.operands
[1].present
)
9345 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9346 constraint (inst
.operands
[0].reg
== REG_LR
,
9347 _("r14 not allowed here"));
9349 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9350 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9351 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
9358 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9359 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
9365 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9366 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9367 inst
.instruction
|= inst
.operands
[2].reg
;
9368 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9374 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9375 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9376 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9377 inst
.instruction
|= inst
.operands
[3].reg
;
9385 int r0off
= (inst
.instruction
== T_MNEM_mov
9386 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
9387 unsigned long opcode
;
9389 bfd_boolean low_regs
;
9391 low_regs
= (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7);
9392 opcode
= inst
.instruction
;
9393 if (current_it_mask
)
9394 narrow
= opcode
!= T_MNEM_movs
;
9396 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
9397 if (inst
.size_req
== 4
9398 || inst
.operands
[1].shifted
)
9401 if (!inst
.operands
[1].isreg
)
9403 /* Immediate operand. */
9404 if (current_it_mask
== 0 && opcode
== T_MNEM_mov
)
9406 if (low_regs
&& narrow
)
9408 inst
.instruction
= THUMB_OP16 (opcode
);
9409 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9410 if (inst
.size_req
== 2)
9411 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9413 inst
.relax
= opcode
;
9417 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9418 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9419 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9420 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9425 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9426 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9427 encode_thumb32_shifted_operand (1);
9430 switch (inst
.instruction
)
9433 inst
.instruction
= T_OPCODE_MOV_HR
;
9434 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9435 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9436 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9440 /* We know we have low registers at this point.
9441 Generate ADD Rd, Rs, #0. */
9442 inst
.instruction
= T_OPCODE_ADD_I3
;
9443 inst
.instruction
|= inst
.operands
[0].reg
;
9444 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9450 inst
.instruction
= T_OPCODE_CMP_LR
;
9451 inst
.instruction
|= inst
.operands
[0].reg
;
9452 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9456 inst
.instruction
= T_OPCODE_CMP_HR
;
9457 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9458 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9459 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9466 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9467 if (inst
.operands
[1].isreg
)
9469 if (inst
.operands
[0].reg
< 8 && inst
.operands
[1].reg
< 8)
9471 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
9472 since a MOV instruction produces unpredictable results. */
9473 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9474 inst
.instruction
= T_OPCODE_ADD_I3
;
9476 inst
.instruction
= T_OPCODE_CMP_LR
;
9478 inst
.instruction
|= inst
.operands
[0].reg
;
9479 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9483 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9484 inst
.instruction
= T_OPCODE_MOV_HR
;
9486 inst
.instruction
= T_OPCODE_CMP_HR
;
9492 constraint (inst
.operands
[0].reg
> 7,
9493 _("only lo regs allowed with immediate"));
9494 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9495 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9505 top
= (inst
.instruction
& 0x00800000) != 0;
9506 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
9508 constraint (top
, _(":lower16: not allowed this instruction"));
9509 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
9511 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
9513 constraint (!top
, _(":upper16: not allowed this instruction"));
9514 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
9517 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9518 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9520 imm
= inst
.reloc
.exp
.X_add_number
;
9521 inst
.instruction
|= (imm
& 0xf000) << 4;
9522 inst
.instruction
|= (imm
& 0x0800) << 15;
9523 inst
.instruction
|= (imm
& 0x0700) << 4;
9524 inst
.instruction
|= (imm
& 0x00ff);
9533 int r0off
= (inst
.instruction
== T_MNEM_mvn
9534 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
9537 if (inst
.size_req
== 4
9538 || inst
.instruction
> 0xffff
9539 || inst
.operands
[1].shifted
9540 || inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9542 else if (inst
.instruction
== T_MNEM_cmn
)
9544 else if (THUMB_SETS_FLAGS (inst
.instruction
))
9545 narrow
= (current_it_mask
== 0);
9547 narrow
= (current_it_mask
!= 0);
9549 if (!inst
.operands
[1].isreg
)
9551 /* For an immediate, we always generate a 32-bit opcode;
9552 section relaxation will shrink it later if possible. */
9553 if (inst
.instruction
< 0xffff)
9554 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9555 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9556 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9557 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9561 /* See if we can do this with a 16-bit instruction. */
9564 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9565 inst
.instruction
|= inst
.operands
[0].reg
;
9566 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9570 constraint (inst
.operands
[1].shifted
9571 && inst
.operands
[1].immisreg
,
9572 _("shift must be constant"));
9573 if (inst
.instruction
< 0xffff)
9574 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9575 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9576 encode_thumb32_shifted_operand (1);
9582 constraint (inst
.instruction
> 0xffff
9583 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
9584 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
9585 _("unshifted register required"));
9586 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9589 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9590 inst
.instruction
|= inst
.operands
[0].reg
;
9591 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9600 if (do_vfp_nsyn_mrs () == SUCCESS
)
9603 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
9606 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
9607 _("selected processor does not support "
9608 "requested special purpose register"));
9612 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9613 _("selected processor does not support "
9614 "requested special purpose register %x"));
9615 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9616 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
9617 _("'CPSR' or 'SPSR' expected"));
9620 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9621 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9622 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
9630 if (do_vfp_nsyn_msr () == SUCCESS
)
9633 constraint (!inst
.operands
[1].isreg
,
9634 _("Thumb encoding does not support an immediate here"));
9635 flags
= inst
.operands
[0].imm
;
9638 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9639 _("selected processor does not support "
9640 "requested special purpose register"));
9644 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
9645 _("selected processor does not support "
9646 "requested special purpose register"));
9649 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9650 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
9651 inst
.instruction
|= (flags
& 0xff);
9652 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9658 if (!inst
.operands
[2].present
)
9659 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9661 /* There is no 32-bit MULS and no 16-bit MUL. */
9662 if (unified_syntax
&& inst
.instruction
== T_MNEM_mul
)
9664 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9665 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9666 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9667 inst
.instruction
|= inst
.operands
[2].reg
<< 0;
9671 constraint (!unified_syntax
9672 && inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
9673 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9676 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9677 inst
.instruction
|= inst
.operands
[0].reg
;
9679 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9680 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9681 else if (inst
.operands
[0].reg
== inst
.operands
[2].reg
)
9682 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9684 constraint (1, _("dest must overlap one source register"));
9691 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9692 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9693 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9694 inst
.instruction
|= inst
.operands
[3].reg
;
9696 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9697 as_tsktsk (_("rdhi and rdlo must be different"));
9705 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
9707 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9708 inst
.instruction
|= inst
.operands
[0].imm
;
9712 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9713 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
9718 constraint (inst
.operands
[0].present
,
9719 _("Thumb does not support NOP with hints"));
9720 inst
.instruction
= 0x46c0;
9731 if (THUMB_SETS_FLAGS (inst
.instruction
))
9732 narrow
= (current_it_mask
== 0);
9734 narrow
= (current_it_mask
!= 0);
9735 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9737 if (inst
.size_req
== 4)
9742 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9743 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9744 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9748 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9749 inst
.instruction
|= inst
.operands
[0].reg
;
9750 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9755 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9757 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9759 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9760 inst
.instruction
|= inst
.operands
[0].reg
;
9761 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9768 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9769 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9770 inst
.instruction
|= inst
.operands
[2].reg
;
9771 if (inst
.operands
[3].present
)
9773 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
9774 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9775 _("expression too complex"));
9776 inst
.instruction
|= (val
& 0x1c) << 10;
9777 inst
.instruction
|= (val
& 0x03) << 6;
9784 if (!inst
.operands
[3].present
)
9785 inst
.instruction
&= ~0x00000020;
9792 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9796 do_t_push_pop (void)
9800 constraint (inst
.operands
[0].writeback
,
9801 _("push/pop do not support {reglist}^"));
9802 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9803 _("expression too complex"));
9805 mask
= inst
.operands
[0].imm
;
9806 if ((mask
& ~0xff) == 0)
9807 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9808 else if ((inst
.instruction
== T_MNEM_push
9809 && (mask
& ~0xff) == 1 << REG_LR
)
9810 || (inst
.instruction
== T_MNEM_pop
9811 && (mask
& ~0xff) == 1 << REG_PC
))
9813 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9814 inst
.instruction
|= THUMB_PP_PC_LR
;
9817 else if (unified_syntax
)
9819 if (mask
& (1 << 13))
9820 inst
.error
= _("SP not allowed in register list");
9821 if (inst
.instruction
== T_MNEM_push
)
9823 if (mask
& (1 << 15))
9824 inst
.error
= _("PC not allowed in register list");
9828 if (mask
& (1 << 14)
9829 && mask
& (1 << 15))
9830 inst
.error
= _("LR and PC should not both be in register list");
9832 if ((mask
& (mask
- 1)) == 0)
9834 /* Single register push/pop implemented as str/ldr. */
9835 if (inst
.instruction
== T_MNEM_push
)
9836 inst
.instruction
= 0xf84d0d04; /* str reg, [sp, #-4]! */
9838 inst
.instruction
= 0xf85d0b04; /* ldr reg, [sp], #4 */
9839 mask
= ffs(mask
) - 1;
9843 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9847 inst
.error
= _("invalid register list to push/pop instruction");
9851 inst
.instruction
|= mask
;
9857 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9858 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9864 if (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
9865 && inst
.size_req
!= 4)
9867 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9868 inst
.instruction
|= inst
.operands
[0].reg
;
9869 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9871 else if (unified_syntax
)
9873 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9874 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9875 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9876 inst
.instruction
|= inst
.operands
[1].reg
;
9879 inst
.error
= BAD_HIREG
;
9887 Rd
= inst
.operands
[0].reg
;
9888 Rs
= (inst
.operands
[1].present
9889 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9890 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9892 inst
.instruction
|= Rd
<< 8;
9893 inst
.instruction
|= Rs
<< 16;
9894 if (!inst
.operands
[2].isreg
)
9896 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9897 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9900 encode_thumb32_shifted_operand (2);
9906 constraint (current_it_mask
, BAD_NOT_IT
);
9907 if (inst
.operands
[0].imm
)
9908 inst
.instruction
|= 0x8;
9914 if (!inst
.operands
[1].present
)
9915 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9922 switch (inst
.instruction
)
9925 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
9927 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
9929 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
9931 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
9935 if (THUMB_SETS_FLAGS (inst
.instruction
))
9936 narrow
= (current_it_mask
== 0);
9938 narrow
= (current_it_mask
!= 0);
9939 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9941 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
9943 if (inst
.operands
[2].isreg
9944 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
9945 || inst
.operands
[2].reg
> 7))
9947 if (inst
.size_req
== 4)
9952 if (inst
.operands
[2].isreg
)
9954 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9955 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9956 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9957 inst
.instruction
|= inst
.operands
[2].reg
;
9961 inst
.operands
[1].shifted
= 1;
9962 inst
.operands
[1].shift_kind
= shift_kind
;
9963 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
9964 ? T_MNEM_movs
: T_MNEM_mov
);
9965 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9966 encode_thumb32_shifted_operand (1);
9967 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
9968 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9973 if (inst
.operands
[2].isreg
)
9977 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
9978 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
9979 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
9980 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
9984 inst
.instruction
|= inst
.operands
[0].reg
;
9985 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9991 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
9992 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
9993 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
9996 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
9997 inst
.instruction
|= inst
.operands
[0].reg
;
9998 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10004 constraint (inst
.operands
[0].reg
> 7
10005 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
10006 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10008 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
10010 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
10011 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
10012 _("source1 and dest must be same register"));
10014 switch (inst
.instruction
)
10016 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10017 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10018 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10019 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10023 inst
.instruction
|= inst
.operands
[0].reg
;
10024 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10028 switch (inst
.instruction
)
10030 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10031 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10032 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10033 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
10036 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10037 inst
.instruction
|= inst
.operands
[0].reg
;
10038 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10046 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10047 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10048 inst
.instruction
|= inst
.operands
[2].reg
;
10054 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10055 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10056 _("expression too complex"));
10057 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10058 inst
.instruction
|= (value
& 0xf000) >> 12;
10059 inst
.instruction
|= (value
& 0x0ff0);
10060 inst
.instruction
|= (value
& 0x000f) << 16;
10066 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10067 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10068 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10070 if (inst
.operands
[3].present
)
10072 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10073 _("expression too complex"));
10075 if (inst
.reloc
.exp
.X_add_number
!= 0)
10077 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10078 inst
.instruction
|= 0x00200000; /* sh bit */
10079 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10080 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10082 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10089 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10090 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10091 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10097 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10098 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10099 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10100 || inst
.operands
[2].negative
,
10103 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10104 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10105 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10106 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10112 if (!inst
.operands
[2].present
)
10113 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
10115 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10116 || inst
.operands
[0].reg
== inst
.operands
[2].reg
10117 || inst
.operands
[0].reg
== inst
.operands
[3].reg
10118 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
10121 inst
.instruction
|= inst
.operands
[0].reg
;
10122 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10123 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10124 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10130 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10131 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10132 inst
.instruction
|= inst
.operands
[2].reg
;
10133 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
10139 if (inst
.instruction
<= 0xffff && inst
.size_req
!= 4
10140 && inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
10141 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
10143 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10144 inst
.instruction
|= inst
.operands
[0].reg
;
10145 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10147 else if (unified_syntax
)
10149 if (inst
.instruction
<= 0xffff)
10150 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10151 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10152 inst
.instruction
|= inst
.operands
[1].reg
;
10153 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
10157 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
10158 _("Thumb encoding does not support rotation"));
10159 constraint (1, BAD_HIREG
);
10166 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
10174 half
= (inst
.instruction
& 0x10) != 0;
10175 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
10176 constraint (inst
.operands
[0].immisreg
,
10177 _("instruction requires register index"));
10178 constraint (inst
.operands
[0].imm
== 15,
10179 _("PC is not a valid index register"));
10180 constraint (!half
&& inst
.operands
[0].shifted
,
10181 _("instruction does not allow shifted index"));
10182 inst
.instruction
|= (inst
.operands
[0].reg
<< 16) | inst
.operands
[0].imm
;
10188 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10189 inst
.instruction
|= inst
.operands
[1].imm
;
10190 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10192 if (inst
.operands
[3].present
)
10194 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10195 _("expression too complex"));
10196 if (inst
.reloc
.exp
.X_add_number
!= 0)
10198 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10199 inst
.instruction
|= 0x00200000; /* sh bit */
10201 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10202 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10204 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10211 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10212 inst
.instruction
|= inst
.operands
[1].imm
;
10213 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10216 /* Neon instruction encoder helpers. */
10218 /* Encodings for the different types for various Neon opcodes. */
10220 /* An "invalid" code for the following tables. */
10223 struct neon_tab_entry
10226 unsigned float_or_poly
;
10227 unsigned scalar_or_imm
;
10230 /* Map overloaded Neon opcodes to their respective encodings. */
10231 #define NEON_ENC_TAB \
10232 X(vabd, 0x0000700, 0x1200d00, N_INV), \
10233 X(vmax, 0x0000600, 0x0000f00, N_INV), \
10234 X(vmin, 0x0000610, 0x0200f00, N_INV), \
10235 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
10236 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
10237 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
10238 X(vadd, 0x0000800, 0x0000d00, N_INV), \
10239 X(vsub, 0x1000800, 0x0200d00, N_INV), \
10240 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
10241 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
10242 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
10243 /* Register variants of the following two instructions are encoded as
10244 vcge / vcgt with the operands reversed. */ \
10245 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
10246 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
10247 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
10248 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
10249 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
10250 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
10251 X(vmlal, 0x0800800, N_INV, 0x0800240), \
10252 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
10253 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
10254 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
10255 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
10256 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
10257 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
10258 X(vshl, 0x0000400, N_INV, 0x0800510), \
10259 X(vqshl, 0x0000410, N_INV, 0x0800710), \
10260 X(vand, 0x0000110, N_INV, 0x0800030), \
10261 X(vbic, 0x0100110, N_INV, 0x0800030), \
10262 X(veor, 0x1000110, N_INV, N_INV), \
10263 X(vorn, 0x0300110, N_INV, 0x0800010), \
10264 X(vorr, 0x0200110, N_INV, 0x0800010), \
10265 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
10266 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
10267 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
10268 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
10269 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
10270 X(vst1, 0x0000000, 0x0800000, N_INV), \
10271 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
10272 X(vst2, 0x0000100, 0x0800100, N_INV), \
10273 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
10274 X(vst3, 0x0000200, 0x0800200, N_INV), \
10275 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
10276 X(vst4, 0x0000300, 0x0800300, N_INV), \
10277 X(vmovn, 0x1b20200, N_INV, N_INV), \
10278 X(vtrn, 0x1b20080, N_INV, N_INV), \
10279 X(vqmovn, 0x1b20200, N_INV, N_INV), \
10280 X(vqmovun, 0x1b20240, N_INV, N_INV), \
10281 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
10282 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \
10283 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \
10284 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
10285 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
10286 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
10287 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
10291 #define X(OPC,I,F,S) N_MNEM_##OPC
10296 static const struct neon_tab_entry neon_enc_tab
[] =
10298 #define X(OPC,I,F,S) { (I), (F), (S) }
10303 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10304 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10305 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10306 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10307 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10308 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10309 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10310 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10311 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10312 #define NEON_ENC_SINGLE(X) \
10313 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
10314 #define NEON_ENC_DOUBLE(X) \
10315 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
10317 /* Define shapes for instruction operands. The following mnemonic characters
10318 are used in this table:
10320 F - VFP S<n> register
10321 D - Neon D<n> register
10322 Q - Neon Q<n> register
10326 L - D<n> register list
10328 This table is used to generate various data:
10329 - enumerations of the form NS_DDR to be used as arguments to
10331 - a table classifying shapes into single, double, quad, mixed.
10332 - a table used to drive neon_select_shape.
10335 #define NEON_SHAPE_DEF \
10336 X(3, (D, D, D), DOUBLE), \
10337 X(3, (Q, Q, Q), QUAD), \
10338 X(3, (D, D, I), DOUBLE), \
10339 X(3, (Q, Q, I), QUAD), \
10340 X(3, (D, D, S), DOUBLE), \
10341 X(3, (Q, Q, S), QUAD), \
10342 X(2, (D, D), DOUBLE), \
10343 X(2, (Q, Q), QUAD), \
10344 X(2, (D, S), DOUBLE), \
10345 X(2, (Q, S), QUAD), \
10346 X(2, (D, R), DOUBLE), \
10347 X(2, (Q, R), QUAD), \
10348 X(2, (D, I), DOUBLE), \
10349 X(2, (Q, I), QUAD), \
10350 X(3, (D, L, D), DOUBLE), \
10351 X(2, (D, Q), MIXED), \
10352 X(2, (Q, D), MIXED), \
10353 X(3, (D, Q, I), MIXED), \
10354 X(3, (Q, D, I), MIXED), \
10355 X(3, (Q, D, D), MIXED), \
10356 X(3, (D, Q, Q), MIXED), \
10357 X(3, (Q, Q, D), MIXED), \
10358 X(3, (Q, D, S), MIXED), \
10359 X(3, (D, Q, S), MIXED), \
10360 X(4, (D, D, D, I), DOUBLE), \
10361 X(4, (Q, Q, Q, I), QUAD), \
10362 X(2, (F, F), SINGLE), \
10363 X(3, (F, F, F), SINGLE), \
10364 X(2, (F, I), SINGLE), \
10365 X(2, (F, D), MIXED), \
10366 X(2, (D, F), MIXED), \
10367 X(3, (F, F, I), MIXED), \
10368 X(4, (R, R, F, F), SINGLE), \
10369 X(4, (F, F, R, R), SINGLE), \
10370 X(3, (D, R, R), DOUBLE), \
10371 X(3, (R, R, D), DOUBLE), \
10372 X(2, (S, R), SINGLE), \
10373 X(2, (R, S), SINGLE), \
10374 X(2, (F, R), SINGLE), \
10375 X(2, (R, F), SINGLE)
10377 #define S2(A,B) NS_##A##B
10378 #define S3(A,B,C) NS_##A##B##C
10379 #define S4(A,B,C,D) NS_##A##B##C##D
10381 #define X(N, L, C) S##N L
10394 enum neon_shape_class
10402 #define X(N, L, C) SC_##C
10404 static enum neon_shape_class neon_shape_class
[] =
10422 /* Register widths of above. */
10423 static unsigned neon_shape_el_size
[] =
10434 struct neon_shape_info
10437 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
10440 #define S2(A,B) { SE_##A, SE_##B }
10441 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
10442 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
10444 #define X(N, L, C) { N, S##N L }
10446 static struct neon_shape_info neon_shape_tab
[] =
10456 /* Bit masks used in type checking given instructions.
10457 'N_EQK' means the type must be the same as (or based on in some way) the key
10458 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
10459 set, various other bits can be set as well in order to modify the meaning of
10460 the type constraint. */
10462 enum neon_type_mask
10484 N_KEY
= 0x100000, /* key element (main type specifier). */
10485 N_EQK
= 0x200000, /* given operand has the same type & size as the key. */
10486 N_VFP
= 0x400000, /* VFP mode: operand size must match register width. */
10487 N_DBL
= 0x000001, /* if N_EQK, this operand is twice the size. */
10488 N_HLF
= 0x000002, /* if N_EQK, this operand is half the size. */
10489 N_SGN
= 0x000004, /* if N_EQK, this operand is forced to be signed. */
10490 N_UNS
= 0x000008, /* if N_EQK, this operand is forced to be unsigned. */
10491 N_INT
= 0x000010, /* if N_EQK, this operand is forced to be integer. */
10492 N_FLT
= 0x000020, /* if N_EQK, this operand is forced to be float. */
10493 N_SIZ
= 0x000040, /* if N_EQK, this operand is forced to be size-only. */
10495 N_MAX_NONSPECIAL
= N_F64
10498 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
10500 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
10501 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
10502 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
10503 #define N_SUF_32 (N_SU_32 | N_F32)
10504 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
10505 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
10507 /* Pass this as the first type argument to neon_check_type to ignore types
10509 #define N_IGNORE_TYPE (N_KEY | N_EQK)
10511 /* Select a "shape" for the current instruction (describing register types or
10512 sizes) from a list of alternatives. Return NS_NULL if the current instruction
10513 doesn't fit. For non-polymorphic shapes, checking is usually done as a
10514 function of operand parsing, so this function doesn't need to be called.
10515 Shapes should be listed in order of decreasing length. */
10517 static enum neon_shape
10518 neon_select_shape (enum neon_shape shape
, ...)
10521 enum neon_shape first_shape
= shape
;
10523 /* Fix missing optional operands. FIXME: we don't know at this point how
10524 many arguments we should have, so this makes the assumption that we have
10525 > 1. This is true of all current Neon opcodes, I think, but may not be
10526 true in the future. */
10527 if (!inst
.operands
[1].present
)
10528 inst
.operands
[1] = inst
.operands
[0];
10530 va_start (ap
, shape
);
10532 for (; shape
!= NS_NULL
; shape
= va_arg (ap
, int))
10537 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
10539 if (!inst
.operands
[j
].present
)
10545 switch (neon_shape_tab
[shape
].el
[j
])
10548 if (!(inst
.operands
[j
].isreg
10549 && inst
.operands
[j
].isvec
10550 && inst
.operands
[j
].issingle
10551 && !inst
.operands
[j
].isquad
))
10556 if (!(inst
.operands
[j
].isreg
10557 && inst
.operands
[j
].isvec
10558 && !inst
.operands
[j
].isquad
10559 && !inst
.operands
[j
].issingle
))
10564 if (!(inst
.operands
[j
].isreg
10565 && !inst
.operands
[j
].isvec
))
10570 if (!(inst
.operands
[j
].isreg
10571 && inst
.operands
[j
].isvec
10572 && inst
.operands
[j
].isquad
10573 && !inst
.operands
[j
].issingle
))
10578 if (!(!inst
.operands
[j
].isreg
10579 && !inst
.operands
[j
].isscalar
))
10584 if (!(!inst
.operands
[j
].isreg
10585 && inst
.operands
[j
].isscalar
))
10599 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
10600 first_error (_("invalid instruction shape"));
10605 /* True if SHAPE is predominantly a quadword operation (most of the time, this
10606 means the Q bit should be set). */
10609 neon_quad (enum neon_shape shape
)
10611 return neon_shape_class
[shape
] == SC_QUAD
;
10615 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
10618 /* Allow modification to be made to types which are constrained to be
10619 based on the key element, based on bits set alongside N_EQK. */
10620 if ((typebits
& N_EQK
) != 0)
10622 if ((typebits
& N_HLF
) != 0)
10624 else if ((typebits
& N_DBL
) != 0)
10626 if ((typebits
& N_SGN
) != 0)
10627 *g_type
= NT_signed
;
10628 else if ((typebits
& N_UNS
) != 0)
10629 *g_type
= NT_unsigned
;
10630 else if ((typebits
& N_INT
) != 0)
10631 *g_type
= NT_integer
;
10632 else if ((typebits
& N_FLT
) != 0)
10633 *g_type
= NT_float
;
10634 else if ((typebits
& N_SIZ
) != 0)
10635 *g_type
= NT_untyped
;
10639 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
10640 operand type, i.e. the single type specified in a Neon instruction when it
10641 is the only one given. */
10643 static struct neon_type_el
10644 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
10646 struct neon_type_el dest
= *key
;
10648 assert ((thisarg
& N_EQK
) != 0);
10650 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
10655 /* Convert Neon type and size into compact bitmask representation. */
10657 static enum neon_type_mask
10658 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
10665 case 8: return N_8
;
10666 case 16: return N_16
;
10667 case 32: return N_32
;
10668 case 64: return N_64
;
10676 case 8: return N_I8
;
10677 case 16: return N_I16
;
10678 case 32: return N_I32
;
10679 case 64: return N_I64
;
10687 case 32: return N_F32
;
10688 case 64: return N_F64
;
10696 case 8: return N_P8
;
10697 case 16: return N_P16
;
10705 case 8: return N_S8
;
10706 case 16: return N_S16
;
10707 case 32: return N_S32
;
10708 case 64: return N_S64
;
10716 case 8: return N_U8
;
10717 case 16: return N_U16
;
10718 case 32: return N_U32
;
10719 case 64: return N_U64
;
10730 /* Convert compact Neon bitmask type representation to a type and size. Only
10731 handles the case where a single bit is set in the mask. */
10734 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
10735 enum neon_type_mask mask
)
10737 if ((mask
& N_EQK
) != 0)
10740 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
10742 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
10744 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
10746 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
10751 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
10753 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
10754 *type
= NT_unsigned
;
10755 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
10756 *type
= NT_integer
;
10757 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
10758 *type
= NT_untyped
;
10759 else if ((mask
& (N_P8
| N_P16
)) != 0)
10761 else if ((mask
& (N_F32
| N_F64
)) != 0)
10769 /* Modify a bitmask of allowed types. This is only needed for type
10773 modify_types_allowed (unsigned allowed
, unsigned mods
)
10776 enum neon_el_type type
;
10782 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
10784 if (el_type_of_type_chk (&type
, &size
, allowed
& i
) == SUCCESS
)
10786 neon_modify_type_size (mods
, &type
, &size
);
10787 destmask
|= type_chk_of_el_type (type
, size
);
10794 /* Check type and return type classification.
10795 The manual states (paraphrase): If one datatype is given, it indicates the
10797 - the second operand, if there is one
10798 - the operand, if there is no second operand
10799 - the result, if there are no operands.
10800 This isn't quite good enough though, so we use a concept of a "key" datatype
10801 which is set on a per-instruction basis, which is the one which matters when
10802 only one data type is written.
10803 Note: this function has side-effects (e.g. filling in missing operands). All
10804 Neon instructions should call it before performing bit encoding. */
10806 static struct neon_type_el
10807 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
10810 unsigned i
, pass
, key_el
= 0;
10811 unsigned types
[NEON_MAX_TYPE_ELS
];
10812 enum neon_el_type k_type
= NT_invtype
;
10813 unsigned k_size
= -1u;
10814 struct neon_type_el badtype
= {NT_invtype
, -1};
10815 unsigned key_allowed
= 0;
10817 /* Optional registers in Neon instructions are always (not) in operand 1.
10818 Fill in the missing operand here, if it was omitted. */
10819 if (els
> 1 && !inst
.operands
[1].present
)
10820 inst
.operands
[1] = inst
.operands
[0];
10822 /* Suck up all the varargs. */
10824 for (i
= 0; i
< els
; i
++)
10826 unsigned thisarg
= va_arg (ap
, unsigned);
10827 if (thisarg
== N_IGNORE_TYPE
)
10832 types
[i
] = thisarg
;
10833 if ((thisarg
& N_KEY
) != 0)
10838 if (inst
.vectype
.elems
> 0)
10839 for (i
= 0; i
< els
; i
++)
10840 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
10842 first_error (_("types specified in both the mnemonic and operands"));
10846 /* Duplicate inst.vectype elements here as necessary.
10847 FIXME: No idea if this is exactly the same as the ARM assembler,
10848 particularly when an insn takes one register and one non-register
10850 if (inst
.vectype
.elems
== 1 && els
> 1)
10853 inst
.vectype
.elems
= els
;
10854 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
10855 for (j
= 0; j
< els
; j
++)
10857 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
10860 else if (inst
.vectype
.elems
== 0 && els
> 0)
10863 /* No types were given after the mnemonic, so look for types specified
10864 after each operand. We allow some flexibility here; as long as the
10865 "key" operand has a type, we can infer the others. */
10866 for (j
= 0; j
< els
; j
++)
10867 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
10868 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
10870 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
10872 for (j
= 0; j
< els
; j
++)
10873 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
10874 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
10879 first_error (_("operand types can't be inferred"));
10883 else if (inst
.vectype
.elems
!= els
)
10885 first_error (_("type specifier has the wrong number of parts"));
10889 for (pass
= 0; pass
< 2; pass
++)
10891 for (i
= 0; i
< els
; i
++)
10893 unsigned thisarg
= types
[i
];
10894 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
10895 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
10896 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
10897 unsigned g_size
= inst
.vectype
.el
[i
].size
;
10899 /* Decay more-specific signed & unsigned types to sign-insensitive
10900 integer types if sign-specific variants are unavailable. */
10901 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
10902 && (types_allowed
& N_SU_ALL
) == 0)
10903 g_type
= NT_integer
;
10905 /* If only untyped args are allowed, decay any more specific types to
10906 them. Some instructions only care about signs for some element
10907 sizes, so handle that properly. */
10908 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
10909 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
10910 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
10911 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
10912 g_type
= NT_untyped
;
10916 if ((thisarg
& N_KEY
) != 0)
10920 key_allowed
= thisarg
& ~N_KEY
;
10925 if ((thisarg
& N_VFP
) != 0)
10927 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
10928 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
10930 /* In VFP mode, operands must match register widths. If we
10931 have a key operand, use its width, else use the width of
10932 the current operand. */
10938 if (regwidth
!= match
)
10940 first_error (_("operand size must match register width"));
10945 if ((thisarg
& N_EQK
) == 0)
10947 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
10949 if ((given_type
& types_allowed
) == 0)
10951 first_error (_("bad type in Neon instruction"));
10957 enum neon_el_type mod_k_type
= k_type
;
10958 unsigned mod_k_size
= k_size
;
10959 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
10960 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
10962 first_error (_("inconsistent types in Neon instruction"));
10970 return inst
.vectype
.el
[key_el
];
10973 /* Neon-style VFP instruction forwarding. */
10975 /* Thumb VFP instructions have 0xE in the condition field. */
10978 do_vfp_cond_or_thumb (void)
10981 inst
.instruction
|= 0xe0000000;
10983 inst
.instruction
|= inst
.cond
<< 28;
10986 /* Look up and encode a simple mnemonic, for use as a helper function for the
10987 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
10988 etc. It is assumed that operand parsing has already been done, and that the
10989 operands are in the form expected by the given opcode (this isn't necessarily
10990 the same as the form in which they were parsed, hence some massaging must
10991 take place before this function is called).
10992 Checks current arch version against that in the looked-up opcode. */
10995 do_vfp_nsyn_opcode (const char *opname
)
10997 const struct asm_opcode
*opcode
;
10999 opcode
= hash_find (arm_ops_hsh
, opname
);
11004 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
11005 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
11010 inst
.instruction
= opcode
->tvalue
;
11011 opcode
->tencode ();
11015 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
11016 opcode
->aencode ();
11021 do_vfp_nsyn_add_sub (enum neon_shape rs
)
11023 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
11028 do_vfp_nsyn_opcode ("fadds");
11030 do_vfp_nsyn_opcode ("fsubs");
11035 do_vfp_nsyn_opcode ("faddd");
11037 do_vfp_nsyn_opcode ("fsubd");
11041 /* Check operand types to see if this is a VFP instruction, and if so call
11045 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
11047 enum neon_shape rs
;
11048 struct neon_type_el et
;
11053 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11054 et
= neon_check_type (2, rs
,
11055 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11059 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11060 et
= neon_check_type (3, rs
,
11061 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11068 if (et
.type
!= NT_invtype
)
11080 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
11082 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
11087 do_vfp_nsyn_opcode ("fmacs");
11089 do_vfp_nsyn_opcode ("fmscs");
11094 do_vfp_nsyn_opcode ("fmacd");
11096 do_vfp_nsyn_opcode ("fmscd");
11101 do_vfp_nsyn_mul (enum neon_shape rs
)
11104 do_vfp_nsyn_opcode ("fmuls");
11106 do_vfp_nsyn_opcode ("fmuld");
11110 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
11112 int is_neg
= (inst
.instruction
& 0x80) != 0;
11113 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
11118 do_vfp_nsyn_opcode ("fnegs");
11120 do_vfp_nsyn_opcode ("fabss");
11125 do_vfp_nsyn_opcode ("fnegd");
11127 do_vfp_nsyn_opcode ("fabsd");
11131 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
11132 insns belong to Neon, and are handled elsewhere. */
11135 do_vfp_nsyn_ldm_stm (int is_dbmode
)
11137 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
11141 do_vfp_nsyn_opcode ("fldmdbs");
11143 do_vfp_nsyn_opcode ("fldmias");
11148 do_vfp_nsyn_opcode ("fstmdbs");
11150 do_vfp_nsyn_opcode ("fstmias");
11155 do_vfp_nsyn_sqrt (void)
11157 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11158 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11161 do_vfp_nsyn_opcode ("fsqrts");
11163 do_vfp_nsyn_opcode ("fsqrtd");
11167 do_vfp_nsyn_div (void)
11169 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11170 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11171 N_F32
| N_F64
| N_KEY
| N_VFP
);
11174 do_vfp_nsyn_opcode ("fdivs");
11176 do_vfp_nsyn_opcode ("fdivd");
11180 do_vfp_nsyn_nmul (void)
11182 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11183 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11184 N_F32
| N_F64
| N_KEY
| N_VFP
);
11188 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11189 do_vfp_sp_dyadic ();
11193 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11194 do_vfp_dp_rd_rn_rm ();
11196 do_vfp_cond_or_thumb ();
11200 do_vfp_nsyn_cmp (void)
11202 if (inst
.operands
[1].isreg
)
11204 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11205 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11209 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11210 do_vfp_sp_monadic ();
11214 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11215 do_vfp_dp_rd_rm ();
11220 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
11221 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
11223 switch (inst
.instruction
& 0x0fffffff)
11226 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
11229 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
11237 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11238 do_vfp_sp_compare_z ();
11242 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11246 do_vfp_cond_or_thumb ();
11250 nsyn_insert_sp (void)
11252 inst
.operands
[1] = inst
.operands
[0];
11253 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
11254 inst
.operands
[0].reg
= 13;
11255 inst
.operands
[0].isreg
= 1;
11256 inst
.operands
[0].writeback
= 1;
11257 inst
.operands
[0].present
= 1;
11261 do_vfp_nsyn_push (void)
11264 if (inst
.operands
[1].issingle
)
11265 do_vfp_nsyn_opcode ("fstmdbs");
11267 do_vfp_nsyn_opcode ("fstmdbd");
11271 do_vfp_nsyn_pop (void)
11274 if (inst
.operands
[1].issingle
)
11275 do_vfp_nsyn_opcode ("fldmias");
11277 do_vfp_nsyn_opcode ("fldmiad");
11280 /* Fix up Neon data-processing instructions, ORing in the correct bits for
11281 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
11284 neon_dp_fixup (unsigned i
)
11288 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
11302 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
11306 neon_logbits (unsigned x
)
11308 return ffs (x
) - 4;
11311 #define LOW4(R) ((R) & 0xf)
11312 #define HI1(R) (((R) >> 4) & 1)
11314 /* Encode insns with bit pattern:
11316 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
11317 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
11319 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
11320 different meaning for some instruction. */
11323 neon_three_same (int isquad
, int ubit
, int size
)
11325 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11326 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11327 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
11328 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
11329 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
11330 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
11331 inst
.instruction
|= (isquad
!= 0) << 6;
11332 inst
.instruction
|= (ubit
!= 0) << 24;
11334 inst
.instruction
|= neon_logbits (size
) << 20;
11336 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11339 /* Encode instructions of the form:
11341 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
11342 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
11344 Don't write size if SIZE == -1. */
11347 neon_two_same (int qbit
, int ubit
, int size
)
11349 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11350 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11351 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11352 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11353 inst
.instruction
|= (qbit
!= 0) << 6;
11354 inst
.instruction
|= (ubit
!= 0) << 24;
11357 inst
.instruction
|= neon_logbits (size
) << 18;
11359 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11362 /* Neon instruction encoders, in approximate order of appearance. */
11365 do_neon_dyadic_i_su (void)
11367 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11368 struct neon_type_el et
= neon_check_type (3, rs
,
11369 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
11370 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11374 do_neon_dyadic_i64_su (void)
11376 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11377 struct neon_type_el et
= neon_check_type (3, rs
,
11378 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11379 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11383 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
11386 unsigned size
= et
.size
>> 3;
11387 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11388 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11389 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11390 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11391 inst
.instruction
|= (isquad
!= 0) << 6;
11392 inst
.instruction
|= immbits
<< 16;
11393 inst
.instruction
|= (size
>> 3) << 7;
11394 inst
.instruction
|= (size
& 0x7) << 19;
11396 inst
.instruction
|= (uval
!= 0) << 24;
11398 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11402 do_neon_shl_imm (void)
11404 if (!inst
.operands
[2].isreg
)
11406 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11407 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
11408 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11409 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
11413 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11414 struct neon_type_el et
= neon_check_type (3, rs
,
11415 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11418 /* VSHL/VQSHL 3-register variants have syntax such as:
11420 whereas other 3-register operations encoded by neon_three_same have
11423 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
11425 tmp
= inst
.operands
[2].reg
;
11426 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11427 inst
.operands
[1].reg
= tmp
;
11428 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11429 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11434 do_neon_qshl_imm (void)
11436 if (!inst
.operands
[2].isreg
)
11438 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11439 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
11441 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11442 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
11443 inst
.operands
[2].imm
);
11447 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11448 struct neon_type_el et
= neon_check_type (3, rs
,
11449 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11452 /* See note in do_neon_shl_imm. */
11453 tmp
= inst
.operands
[2].reg
;
11454 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11455 inst
.operands
[1].reg
= tmp
;
11456 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11457 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11462 do_neon_rshl (void)
11464 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11465 struct neon_type_el et
= neon_check_type (3, rs
,
11466 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11469 tmp
= inst
.operands
[2].reg
;
11470 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11471 inst
.operands
[1].reg
= tmp
;
11472 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11476 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
11478 /* Handle .I8 pseudo-instructions. */
11481 /* Unfortunately, this will make everything apart from zero out-of-range.
11482 FIXME is this the intended semantics? There doesn't seem much point in
11483 accepting .I8 if so. */
11484 immediate
|= immediate
<< 8;
11490 if (immediate
== (immediate
& 0x000000ff))
11492 *immbits
= immediate
;
11495 else if (immediate
== (immediate
& 0x0000ff00))
11497 *immbits
= immediate
>> 8;
11500 else if (immediate
== (immediate
& 0x00ff0000))
11502 *immbits
= immediate
>> 16;
11505 else if (immediate
== (immediate
& 0xff000000))
11507 *immbits
= immediate
>> 24;
11510 if ((immediate
& 0xffff) != (immediate
>> 16))
11511 goto bad_immediate
;
11512 immediate
&= 0xffff;
11515 if (immediate
== (immediate
& 0x000000ff))
11517 *immbits
= immediate
;
11520 else if (immediate
== (immediate
& 0x0000ff00))
11522 *immbits
= immediate
>> 8;
11527 first_error (_("immediate value out of range"));
11531 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
11535 neon_bits_same_in_bytes (unsigned imm
)
11537 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
11538 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
11539 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
11540 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
11543 /* For immediate of above form, return 0bABCD. */
11546 neon_squash_bits (unsigned imm
)
11548 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
11549 | ((imm
& 0x01000000) >> 21);
11552 /* Compress quarter-float representation to 0b...000 abcdefgh. */
11555 neon_qfloat_bits (unsigned imm
)
11557 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
11560 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
11561 the instruction. *OP is passed as the initial value of the op field, and
11562 may be set to a different value depending on the constant (i.e.
11563 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
11564 MVN). If the immediate looks like a repeated parttern then also
11565 try smaller element sizes. */
11568 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, unsigned *immbits
,
11569 int *op
, int size
, enum neon_el_type type
)
11571 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
11573 if (size
!= 32 || *op
== 1)
11575 *immbits
= neon_qfloat_bits (immlo
);
11581 if (neon_bits_same_in_bytes (immhi
)
11582 && neon_bits_same_in_bytes (immlo
))
11586 *immbits
= (neon_squash_bits (immhi
) << 4)
11587 | neon_squash_bits (immlo
);
11592 if (immhi
!= immlo
)
11598 if (immlo
== (immlo
& 0x000000ff))
11603 else if (immlo
== (immlo
& 0x0000ff00))
11605 *immbits
= immlo
>> 8;
11608 else if (immlo
== (immlo
& 0x00ff0000))
11610 *immbits
= immlo
>> 16;
11613 else if (immlo
== (immlo
& 0xff000000))
11615 *immbits
= immlo
>> 24;
11618 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
11620 *immbits
= (immlo
>> 8) & 0xff;
11623 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
11625 *immbits
= (immlo
>> 16) & 0xff;
11629 if ((immlo
& 0xffff) != (immlo
>> 16))
11636 if (immlo
== (immlo
& 0x000000ff))
11641 else if (immlo
== (immlo
& 0x0000ff00))
11643 *immbits
= immlo
>> 8;
11647 if ((immlo
& 0xff) != (immlo
>> 8))
11652 if (immlo
== (immlo
& 0x000000ff))
11654 /* Don't allow MVN with 8-bit immediate. */
11664 /* Write immediate bits [7:0] to the following locations:
11666 |28/24|23 19|18 16|15 4|3 0|
11667 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
11669 This function is used by VMOV/VMVN/VORR/VBIC. */
11672 neon_write_immbits (unsigned immbits
)
11674 inst
.instruction
|= immbits
& 0xf;
11675 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
11676 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
11679 /* Invert low-order SIZE bits of XHI:XLO. */
11682 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
11684 unsigned immlo
= xlo
? *xlo
: 0;
11685 unsigned immhi
= xhi
? *xhi
: 0;
11690 immlo
= (~immlo
) & 0xff;
11694 immlo
= (~immlo
) & 0xffff;
11698 immhi
= (~immhi
) & 0xffffffff;
11699 /* fall through. */
11702 immlo
= (~immlo
) & 0xffffffff;
11717 do_neon_logic (void)
11719 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
11721 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11722 neon_check_type (3, rs
, N_IGNORE_TYPE
);
11723 /* U bit and size field were set as part of the bitmask. */
11724 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11725 neon_three_same (neon_quad (rs
), 0, -1);
11729 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
11730 struct neon_type_el et
= neon_check_type (2, rs
,
11731 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
11732 enum neon_opc opcode
= inst
.instruction
& 0x0fffffff;
11736 if (et
.type
== NT_invtype
)
11739 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11741 immbits
= inst
.operands
[1].imm
;
11744 /* .i64 is a pseudo-op, so the immediate must be a repeating
11746 if (immbits
!= (inst
.operands
[1].regisimm
?
11747 inst
.operands
[1].reg
: 0))
11749 /* Set immbits to an invalid constant. */
11750 immbits
= 0xdeadbeef;
11757 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11761 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11765 /* Pseudo-instruction for VBIC. */
11766 neon_invert_size (&immbits
, 0, et
.size
);
11767 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11771 /* Pseudo-instruction for VORR. */
11772 neon_invert_size (&immbits
, 0, et
.size
);
11773 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11783 inst
.instruction
|= neon_quad (rs
) << 6;
11784 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11785 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11786 inst
.instruction
|= cmode
<< 8;
11787 neon_write_immbits (immbits
);
11789 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11794 do_neon_bitfield (void)
11796 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11797 neon_check_type (3, rs
, N_IGNORE_TYPE
);
11798 neon_three_same (neon_quad (rs
), 0, -1);
11802 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
11805 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11806 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
11808 if (et
.type
== NT_float
)
11810 inst
.instruction
= NEON_ENC_FLOAT (inst
.instruction
);
11811 neon_three_same (neon_quad (rs
), 0, -1);
11815 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11816 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
11821 do_neon_dyadic_if_su (void)
11823 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
11827 do_neon_dyadic_if_su_d (void)
11829 /* This version only allow D registers, but that constraint is enforced during
11830 operand parsing so we don't need to do anything extra here. */
11831 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
11835 do_neon_dyadic_if_i_d (void)
11837 /* The "untyped" case can't happen. Do this to stop the "U" bit being
11838 affected if we specify unsigned args. */
11839 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
11842 enum vfp_or_neon_is_neon_bits
11845 NEON_CHECK_ARCH
= 2
11848 /* Call this function if an instruction which may have belonged to the VFP or
11849 Neon instruction sets, but turned out to be a Neon instruction (due to the
11850 operand types involved, etc.). We have to check and/or fix-up a couple of
11853 - Make sure the user hasn't attempted to make a Neon instruction
11855 - Alter the value in the condition code field if necessary.
11856 - Make sure that the arch supports Neon instructions.
11858 Which of these operations take place depends on bits from enum
11859 vfp_or_neon_is_neon_bits.
11861 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
11862 current instruction's condition is COND_ALWAYS, the condition field is
11863 changed to inst.uncond_value. This is necessary because instructions shared
11864 between VFP and Neon may be conditional for the VFP variants only, and the
11865 unconditional Neon version must have, e.g., 0xF in the condition field. */
11868 vfp_or_neon_is_neon (unsigned check
)
11870 /* Conditions are always legal in Thumb mode (IT blocks). */
11871 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
11873 if (inst
.cond
!= COND_ALWAYS
)
11875 first_error (_(BAD_COND
));
11878 if (inst
.uncond_value
!= -1)
11879 inst
.instruction
|= inst
.uncond_value
<< 28;
11882 if ((check
& NEON_CHECK_ARCH
)
11883 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
11885 first_error (_(BAD_FPU
));
11893 do_neon_addsub_if_i (void)
11895 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
11898 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11901 /* The "untyped" case can't happen. Do this to stop the "U" bit being
11902 affected if we specify unsigned args. */
11903 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
11906 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
11908 V<op> A,B (A is operand 0, B is operand 2)
11913 so handle that case specially. */
11916 neon_exchange_operands (void)
11918 void *scratch
= alloca (sizeof (inst
.operands
[0]));
11919 if (inst
.operands
[1].present
)
11921 /* Swap operands[1] and operands[2]. */
11922 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
11923 inst
.operands
[1] = inst
.operands
[2];
11924 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
11928 inst
.operands
[1] = inst
.operands
[2];
11929 inst
.operands
[2] = inst
.operands
[0];
11934 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
11936 if (inst
.operands
[2].isreg
)
11939 neon_exchange_operands ();
11940 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
11944 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11945 struct neon_type_el et
= neon_check_type (2, rs
,
11946 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
11948 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11949 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11950 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11951 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11952 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11953 inst
.instruction
|= neon_quad (rs
) << 6;
11954 inst
.instruction
|= (et
.type
== NT_float
) << 10;
11955 inst
.instruction
|= neon_logbits (et
.size
) << 18;
11957 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11964 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
11968 do_neon_cmp_inv (void)
11970 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
11976 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
11979 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
11980 scalars, which are encoded in 5 bits, M : Rm.
11981 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
11982 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
11986 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
11988 unsigned regno
= NEON_SCALAR_REG (scalar
);
11989 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
11994 if (regno
> 7 || elno
> 3)
11996 return regno
| (elno
<< 3);
11999 if (regno
> 15 || elno
> 1)
12001 return regno
| (elno
<< 4);
12005 first_error (_("scalar out of range for multiply instruction"));
12011 /* Encode multiply / multiply-accumulate scalar instructions. */
12014 neon_mul_mac (struct neon_type_el et
, int ubit
)
12018 /* Give a more helpful error message if we have an invalid type. */
12019 if (et
.type
== NT_invtype
)
12022 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
12023 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12024 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12025 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12026 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12027 inst
.instruction
|= LOW4 (scalar
);
12028 inst
.instruction
|= HI1 (scalar
) << 5;
12029 inst
.instruction
|= (et
.type
== NT_float
) << 8;
12030 inst
.instruction
|= neon_logbits (et
.size
) << 20;
12031 inst
.instruction
|= (ubit
!= 0) << 24;
12033 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12037 do_neon_mac_maybe_scalar (void)
12039 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
12042 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12045 if (inst
.operands
[2].isscalar
)
12047 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
12048 struct neon_type_el et
= neon_check_type (3, rs
,
12049 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
12050 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12051 neon_mul_mac (et
, neon_quad (rs
));
12055 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12056 affected if we specify unsigned args. */
12057 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12064 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12065 struct neon_type_el et
= neon_check_type (3, rs
,
12066 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12067 neon_three_same (neon_quad (rs
), 0, et
.size
);
12070 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
12071 same types as the MAC equivalents. The polynomial type for this instruction
12072 is encoded the same as the integer type. */
12077 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
12080 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12083 if (inst
.operands
[2].isscalar
)
12084 do_neon_mac_maybe_scalar ();
12086 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
12090 do_neon_qdmulh (void)
12092 if (inst
.operands
[2].isscalar
)
12094 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
12095 struct neon_type_el et
= neon_check_type (3, rs
,
12096 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
12097 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12098 neon_mul_mac (et
, neon_quad (rs
));
12102 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12103 struct neon_type_el et
= neon_check_type (3, rs
,
12104 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
12105 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12106 /* The U bit (rounding) comes from bit mask. */
12107 neon_three_same (neon_quad (rs
), 0, et
.size
);
12112 do_neon_fcmp_absolute (void)
12114 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12115 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12116 /* Size field comes from bit mask. */
12117 neon_three_same (neon_quad (rs
), 1, -1);
12121 do_neon_fcmp_absolute_inv (void)
12123 neon_exchange_operands ();
12124 do_neon_fcmp_absolute ();
12128 do_neon_step (void)
12130 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12131 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12132 neon_three_same (neon_quad (rs
), 0, -1);
12136 do_neon_abs_neg (void)
12138 enum neon_shape rs
;
12139 struct neon_type_el et
;
12141 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
12144 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12147 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12148 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
12150 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12151 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12152 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12153 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12154 inst
.instruction
|= neon_quad (rs
) << 6;
12155 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12156 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12158 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12164 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12165 struct neon_type_el et
= neon_check_type (2, rs
,
12166 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12167 int imm
= inst
.operands
[2].imm
;
12168 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12169 _("immediate out of range for insert"));
12170 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12176 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12177 struct neon_type_el et
= neon_check_type (2, rs
,
12178 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12179 int imm
= inst
.operands
[2].imm
;
12180 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12181 _("immediate out of range for insert"));
12182 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
12186 do_neon_qshlu_imm (void)
12188 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12189 struct neon_type_el et
= neon_check_type (2, rs
,
12190 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
12191 int imm
= inst
.operands
[2].imm
;
12192 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12193 _("immediate out of range for shift"));
12194 /* Only encodes the 'U present' variant of the instruction.
12195 In this case, signed types have OP (bit 8) set to 0.
12196 Unsigned types have OP set to 1. */
12197 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
12198 /* The rest of the bits are the same as other immediate shifts. */
12199 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12203 do_neon_qmovn (void)
12205 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12206 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12207 /* Saturating move where operands can be signed or unsigned, and the
12208 destination has the same signedness. */
12209 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12210 if (et
.type
== NT_unsigned
)
12211 inst
.instruction
|= 0xc0;
12213 inst
.instruction
|= 0x80;
12214 neon_two_same (0, 1, et
.size
/ 2);
12218 do_neon_qmovun (void)
12220 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12221 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12222 /* Saturating move with unsigned results. Operands must be signed. */
12223 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12224 neon_two_same (0, 1, et
.size
/ 2);
12228 do_neon_rshift_sat_narrow (void)
12230 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12231 or unsigned. If operands are unsigned, results must also be unsigned. */
12232 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12233 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12234 int imm
= inst
.operands
[2].imm
;
12235 /* This gets the bounds check, size encoding and immediate bits calculation
12239 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
12240 VQMOVN.I<size> <Dd>, <Qm>. */
12243 inst
.operands
[2].present
= 0;
12244 inst
.instruction
= N_MNEM_vqmovn
;
12249 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12250 _("immediate out of range"));
12251 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
12255 do_neon_rshift_sat_narrow_u (void)
12257 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12258 or unsigned. If operands are unsigned, results must also be unsigned. */
12259 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12260 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12261 int imm
= inst
.operands
[2].imm
;
12262 /* This gets the bounds check, size encoding and immediate bits calculation
12266 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
12267 VQMOVUN.I<size> <Dd>, <Qm>. */
12270 inst
.operands
[2].present
= 0;
12271 inst
.instruction
= N_MNEM_vqmovun
;
12276 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12277 _("immediate out of range"));
12278 /* FIXME: The manual is kind of unclear about what value U should have in
12279 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
12281 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
12285 do_neon_movn (void)
12287 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12288 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12289 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12290 neon_two_same (0, 1, et
.size
/ 2);
12294 do_neon_rshift_narrow (void)
12296 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12297 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12298 int imm
= inst
.operands
[2].imm
;
12299 /* This gets the bounds check, size encoding and immediate bits calculation
12303 /* If immediate is zero then we are a pseudo-instruction for
12304 VMOVN.I<size> <Dd>, <Qm> */
12307 inst
.operands
[2].present
= 0;
12308 inst
.instruction
= N_MNEM_vmovn
;
12313 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12314 _("immediate out of range for narrowing operation"));
12315 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
12319 do_neon_shll (void)
12321 /* FIXME: Type checking when lengthening. */
12322 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
12323 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
12324 unsigned imm
= inst
.operands
[2].imm
;
12326 if (imm
== et
.size
)
12328 /* Maximum shift variant. */
12329 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12330 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12331 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12332 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12333 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12334 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12336 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12340 /* A more-specific type check for non-max versions. */
12341 et
= neon_check_type (2, NS_QDI
,
12342 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12343 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12344 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
12348 /* Check the various types for the VCVT instruction, and return which version
12349 the current instruction is. */
12352 neon_cvt_flavour (enum neon_shape rs
)
12354 #define CVT_VAR(C,X,Y) \
12355 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
12356 if (et.type != NT_invtype) \
12358 inst.error = NULL; \
12361 struct neon_type_el et
;
12362 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
12363 || rs
== NS_FF
) ? N_VFP
: 0;
12364 /* The instruction versions which take an immediate take one register
12365 argument, which is extended to the width of the full register. Thus the
12366 "source" and "destination" registers must have the same width. Hack that
12367 here by making the size equal to the key (wider, in this case) operand. */
12368 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
12370 CVT_VAR (0, N_S32
, N_F32
);
12371 CVT_VAR (1, N_U32
, N_F32
);
12372 CVT_VAR (2, N_F32
, N_S32
);
12373 CVT_VAR (3, N_F32
, N_U32
);
12377 /* VFP instructions. */
12378 CVT_VAR (4, N_F32
, N_F64
);
12379 CVT_VAR (5, N_F64
, N_F32
);
12380 CVT_VAR (6, N_S32
, N_F64
| key
);
12381 CVT_VAR (7, N_U32
, N_F64
| key
);
12382 CVT_VAR (8, N_F64
| key
, N_S32
);
12383 CVT_VAR (9, N_F64
| key
, N_U32
);
12384 /* VFP instructions with bitshift. */
12385 CVT_VAR (10, N_F32
| key
, N_S16
);
12386 CVT_VAR (11, N_F32
| key
, N_U16
);
12387 CVT_VAR (12, N_F64
| key
, N_S16
);
12388 CVT_VAR (13, N_F64
| key
, N_U16
);
12389 CVT_VAR (14, N_S16
, N_F32
| key
);
12390 CVT_VAR (15, N_U16
, N_F32
| key
);
12391 CVT_VAR (16, N_S16
, N_F64
| key
);
12392 CVT_VAR (17, N_U16
, N_F64
| key
);
12398 /* Neon-syntax VFP conversions. */
12401 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
12403 const char *opname
= 0;
12405 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
12407 /* Conversions with immediate bitshift. */
12408 const char *enc
[] =
12430 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12432 opname
= enc
[flavour
];
12433 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12434 _("operands 0 and 1 must be the same register"));
12435 inst
.operands
[1] = inst
.operands
[2];
12436 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
12441 /* Conversions without bitshift. */
12442 const char *enc
[] =
12456 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12457 opname
= enc
[flavour
];
12461 do_vfp_nsyn_opcode (opname
);
12465 do_vfp_nsyn_cvtz (void)
12467 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
12468 int flavour
= neon_cvt_flavour (rs
);
12469 const char *enc
[] =
12481 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
12482 do_vfp_nsyn_opcode (enc
[flavour
]);
12488 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
12489 NS_FD
, NS_DF
, NS_FF
, NS_NULL
);
12490 int flavour
= neon_cvt_flavour (rs
);
12492 /* VFP rather than Neon conversions. */
12495 do_vfp_nsyn_cvt (rs
, flavour
);
12504 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12507 /* Fixed-point conversion with #0 immediate is encoded as an
12508 integer conversion. */
12509 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
12511 unsigned immbits
= 32 - inst
.operands
[2].imm
;
12512 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
12513 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12515 inst
.instruction
|= enctab
[flavour
];
12516 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12517 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12518 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12519 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12520 inst
.instruction
|= neon_quad (rs
) << 6;
12521 inst
.instruction
|= 1 << 21;
12522 inst
.instruction
|= immbits
<< 16;
12524 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12532 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
12534 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12536 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12540 inst
.instruction
|= enctab
[flavour
];
12542 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12543 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12544 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12545 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12546 inst
.instruction
|= neon_quad (rs
) << 6;
12547 inst
.instruction
|= 2 << 18;
12549 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12554 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
12555 do_vfp_nsyn_cvt (rs
, flavour
);
12560 neon_move_immediate (void)
12562 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12563 struct neon_type_el et
= neon_check_type (2, rs
,
12564 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12565 unsigned immlo
, immhi
= 0, immbits
;
12568 constraint (et
.type
== NT_invtype
,
12569 _("operand size must be specified for immediate VMOV"));
12571 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
12572 op
= (inst
.instruction
& (1 << 5)) != 0;
12574 immlo
= inst
.operands
[1].imm
;
12575 if (inst
.operands
[1].regisimm
)
12576 immhi
= inst
.operands
[1].reg
;
12578 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
12579 _("immediate has bits set outside the operand size"));
12581 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, &immbits
, &op
,
12582 et
.size
, et
.type
)) == FAIL
)
12584 /* Invert relevant bits only. */
12585 neon_invert_size (&immlo
, &immhi
, et
.size
);
12586 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
12587 with one or the other; those cases are caught by
12588 neon_cmode_for_move_imm. */
12590 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, &immbits
, &op
,
12591 et
.size
, et
.type
)) == FAIL
)
12593 first_error (_("immediate out of range"));
12598 inst
.instruction
&= ~(1 << 5);
12599 inst
.instruction
|= op
<< 5;
12601 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12602 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12603 inst
.instruction
|= neon_quad (rs
) << 6;
12604 inst
.instruction
|= cmode
<< 8;
12606 neon_write_immbits (immbits
);
12612 if (inst
.operands
[1].isreg
)
12614 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12616 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12617 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12618 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12619 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12620 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12621 inst
.instruction
|= neon_quad (rs
) << 6;
12625 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12626 neon_move_immediate ();
12629 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12632 /* Encode instructions of form:
12634 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12635 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm |
12640 neon_mixed_length (struct neon_type_el et
, unsigned size
)
12642 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12643 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12644 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12645 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12646 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12647 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12648 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
12649 inst
.instruction
|= neon_logbits (size
) << 20;
12651 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12655 do_neon_dyadic_long (void)
12657 /* FIXME: Type checking for lengthening op. */
12658 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12659 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12660 neon_mixed_length (et
, et
.size
);
12664 do_neon_abal (void)
12666 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12667 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12668 neon_mixed_length (et
, et
.size
);
12672 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
12674 if (inst
.operands
[2].isscalar
)
12676 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
12677 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
12678 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12679 neon_mul_mac (et
, et
.type
== NT_unsigned
);
12683 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12684 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
12685 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12686 neon_mixed_length (et
, et
.size
);
12691 do_neon_mac_maybe_scalar_long (void)
12693 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
12697 do_neon_dyadic_wide (void)
12699 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
12700 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12701 neon_mixed_length (et
, et
.size
);
12705 do_neon_dyadic_narrow (void)
12707 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12708 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
12709 /* Operand sign is unimportant, and the U bit is part of the opcode,
12710 so force the operand type to integer. */
12711 et
.type
= NT_integer
;
12712 neon_mixed_length (et
, et
.size
/ 2);
12716 do_neon_mul_sat_scalar_long (void)
12718 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
12722 do_neon_vmull (void)
12724 if (inst
.operands
[2].isscalar
)
12725 do_neon_mac_maybe_scalar_long ();
12728 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12729 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
12730 if (et
.type
== NT_poly
)
12731 inst
.instruction
= NEON_ENC_POLY (inst
.instruction
);
12733 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12734 /* For polynomial encoding, size field must be 0b00 and the U bit must be
12735 zero. Should be OK as-is. */
12736 neon_mixed_length (et
, et
.size
);
12743 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
12744 struct neon_type_el et
= neon_check_type (3, rs
,
12745 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12746 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
12747 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12748 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12749 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12750 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12751 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12752 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12753 inst
.instruction
|= neon_quad (rs
) << 6;
12754 inst
.instruction
|= imm
<< 8;
12756 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12762 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12763 struct neon_type_el et
= neon_check_type (2, rs
,
12764 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12765 unsigned op
= (inst
.instruction
>> 7) & 3;
12766 /* N (width of reversed regions) is encoded as part of the bitmask. We
12767 extract it here to check the elements to be reversed are smaller.
12768 Otherwise we'd get a reserved instruction. */
12769 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
12770 assert (elsize
!= 0);
12771 constraint (et
.size
>= elsize
,
12772 _("elements must be smaller than reversal region"));
12773 neon_two_same (neon_quad (rs
), 1, et
.size
);
12779 if (inst
.operands
[1].isscalar
)
12781 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
12782 struct neon_type_el et
= neon_check_type (2, rs
,
12783 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12784 unsigned sizebits
= et
.size
>> 3;
12785 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
12786 int logsize
= neon_logbits (et
.size
);
12787 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
12789 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
12792 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12793 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12794 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12795 inst
.instruction
|= LOW4 (dm
);
12796 inst
.instruction
|= HI1 (dm
) << 5;
12797 inst
.instruction
|= neon_quad (rs
) << 6;
12798 inst
.instruction
|= x
<< 17;
12799 inst
.instruction
|= sizebits
<< 16;
12801 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12805 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
12806 struct neon_type_el et
= neon_check_type (2, rs
,
12807 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
12808 /* Duplicate ARM register to lanes of vector. */
12809 inst
.instruction
= NEON_ENC_ARMREG (inst
.instruction
);
12812 case 8: inst
.instruction
|= 0x400000; break;
12813 case 16: inst
.instruction
|= 0x000020; break;
12814 case 32: inst
.instruction
|= 0x000000; break;
12817 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
12818 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
12819 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
12820 inst
.instruction
|= neon_quad (rs
) << 21;
12821 /* The encoding for this instruction is identical for the ARM and Thumb
12822 variants, except for the condition field. */
12823 do_vfp_cond_or_thumb ();
12827 /* VMOV has particularly many variations. It can be one of:
12828 0. VMOV<c><q> <Qd>, <Qm>
12829 1. VMOV<c><q> <Dd>, <Dm>
12830 (Register operations, which are VORR with Rm = Rn.)
12831 2. VMOV<c><q>.<dt> <Qd>, #<imm>
12832 3. VMOV<c><q>.<dt> <Dd>, #<imm>
12834 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
12835 (ARM register to scalar.)
12836 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
12837 (Two ARM registers to vector.)
12838 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
12839 (Scalar to ARM register.)
12840 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
12841 (Vector to two ARM registers.)
12842 8. VMOV.F32 <Sd>, <Sm>
12843 9. VMOV.F64 <Dd>, <Dm>
12844 (VFP register moves.)
12845 10. VMOV.F32 <Sd>, #imm
12846 11. VMOV.F64 <Dd>, #imm
12847 (VFP float immediate load.)
12848 12. VMOV <Rd>, <Sm>
12849 (VFP single to ARM reg.)
12850 13. VMOV <Sd>, <Rm>
12851 (ARM reg to VFP single.)
12852 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
12853 (Two ARM regs to two VFP singles.)
12854 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
12855 (Two VFP singles to two ARM regs.)
12857 These cases can be disambiguated using neon_select_shape, except cases 1/9
12858 and 3/11 which depend on the operand type too.
12860 All the encoded bits are hardcoded by this function.
12862 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
12863 Cases 5, 7 may be used with VFPv2 and above.
12865 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
12866 can specify a type where it doesn't make sense to, and is ignored).
12872 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
12873 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
12875 struct neon_type_el et
;
12876 const char *ldconst
= 0;
12880 case NS_DD
: /* case 1/9. */
12881 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
12882 /* It is not an error here if no type is given. */
12884 if (et
.type
== NT_float
&& et
.size
== 64)
12886 do_vfp_nsyn_opcode ("fcpyd");
12889 /* fall through. */
12891 case NS_QQ
: /* case 0/1. */
12893 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12895 /* The architecture manual I have doesn't explicitly state which
12896 value the U bit should have for register->register moves, but
12897 the equivalent VORR instruction has U = 0, so do that. */
12898 inst
.instruction
= 0x0200110;
12899 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12900 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12901 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12902 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12903 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12904 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12905 inst
.instruction
|= neon_quad (rs
) << 6;
12907 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12911 case NS_DI
: /* case 3/11. */
12912 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
12914 if (et
.type
== NT_float
&& et
.size
== 64)
12916 /* case 11 (fconstd). */
12917 ldconst
= "fconstd";
12918 goto encode_fconstd
;
12920 /* fall through. */
12922 case NS_QI
: /* case 2/3. */
12923 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12925 inst
.instruction
= 0x0800010;
12926 neon_move_immediate ();
12927 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12930 case NS_SR
: /* case 4. */
12932 unsigned bcdebits
= 0;
12933 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
12934 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
12935 int logsize
= neon_logbits (et
.size
);
12936 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
12937 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
12939 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
12941 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
12942 && et
.size
!= 32, _(BAD_FPU
));
12943 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
12944 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
12948 case 8: bcdebits
= 0x8; break;
12949 case 16: bcdebits
= 0x1; break;
12950 case 32: bcdebits
= 0x0; break;
12954 bcdebits
|= x
<< logsize
;
12956 inst
.instruction
= 0xe000b10;
12957 do_vfp_cond_or_thumb ();
12958 inst
.instruction
|= LOW4 (dn
) << 16;
12959 inst
.instruction
|= HI1 (dn
) << 7;
12960 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12961 inst
.instruction
|= (bcdebits
& 3) << 5;
12962 inst
.instruction
|= (bcdebits
>> 2) << 21;
12966 case NS_DRR
: /* case 5 (fmdrr). */
12967 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
12970 inst
.instruction
= 0xc400b10;
12971 do_vfp_cond_or_thumb ();
12972 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
12973 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
12974 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12975 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12978 case NS_RS
: /* case 6. */
12980 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
12981 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
12982 unsigned logsize
= neon_logbits (et
.size
);
12983 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
12984 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
12985 unsigned abcdebits
= 0;
12987 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
12989 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
12990 && et
.size
!= 32, _(BAD_FPU
));
12991 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
12992 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
12996 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
12997 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
12998 case 32: abcdebits
= 0x00; break;
13002 abcdebits
|= x
<< logsize
;
13003 inst
.instruction
= 0xe100b10;
13004 do_vfp_cond_or_thumb ();
13005 inst
.instruction
|= LOW4 (dn
) << 16;
13006 inst
.instruction
|= HI1 (dn
) << 7;
13007 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
13008 inst
.instruction
|= (abcdebits
& 3) << 5;
13009 inst
.instruction
|= (abcdebits
>> 2) << 21;
13013 case NS_RRD
: /* case 7 (fmrrd). */
13014 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
13017 inst
.instruction
= 0xc500b10;
13018 do_vfp_cond_or_thumb ();
13019 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
13020 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13021 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13022 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13025 case NS_FF
: /* case 8 (fcpys). */
13026 do_vfp_nsyn_opcode ("fcpys");
13029 case NS_FI
: /* case 10 (fconsts). */
13030 ldconst
= "fconsts";
13032 if (is_quarter_float (inst
.operands
[1].imm
))
13034 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
13035 do_vfp_nsyn_opcode (ldconst
);
13038 first_error (_("immediate out of range"));
13041 case NS_RF
: /* case 12 (fmrs). */
13042 do_vfp_nsyn_opcode ("fmrs");
13045 case NS_FR
: /* case 13 (fmsr). */
13046 do_vfp_nsyn_opcode ("fmsr");
13049 /* The encoders for the fmrrs and fmsrr instructions expect three operands
13050 (one of which is a list), but we have parsed four. Do some fiddling to
13051 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
13053 case NS_RRFF
: /* case 14 (fmrrs). */
13054 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
13055 _("VFP registers must be adjacent"));
13056 inst
.operands
[2].imm
= 2;
13057 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
13058 do_vfp_nsyn_opcode ("fmrrs");
13061 case NS_FFRR
: /* case 15 (fmsrr). */
13062 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
13063 _("VFP registers must be adjacent"));
13064 inst
.operands
[1] = inst
.operands
[2];
13065 inst
.operands
[2] = inst
.operands
[3];
13066 inst
.operands
[0].imm
= 2;
13067 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
13068 do_vfp_nsyn_opcode ("fmsrr");
13077 do_neon_rshift_round_imm (void)
13079 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13080 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
13081 int imm
= inst
.operands
[2].imm
;
13083 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
13086 inst
.operands
[2].present
= 0;
13091 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13092 _("immediate out of range for shift"));
13093 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
13098 do_neon_movl (void)
13100 struct neon_type_el et
= neon_check_type (2, NS_QD
,
13101 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13102 unsigned sizebits
= et
.size
>> 3;
13103 inst
.instruction
|= sizebits
<< 19;
13104 neon_two_same (0, et
.type
== NT_unsigned
, -1);
13110 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13111 struct neon_type_el et
= neon_check_type (2, rs
,
13112 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13113 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13114 neon_two_same (neon_quad (rs
), 1, et
.size
);
13118 do_neon_zip_uzp (void)
13120 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13121 struct neon_type_el et
= neon_check_type (2, rs
,
13122 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13123 if (rs
== NS_DD
&& et
.size
== 32)
13125 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
13126 inst
.instruction
= N_MNEM_vtrn
;
13130 neon_two_same (neon_quad (rs
), 1, et
.size
);
13134 do_neon_sat_abs_neg (void)
13136 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13137 struct neon_type_el et
= neon_check_type (2, rs
,
13138 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13139 neon_two_same (neon_quad (rs
), 1, et
.size
);
13143 do_neon_pair_long (void)
13145 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13146 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
13147 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
13148 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
13149 neon_two_same (neon_quad (rs
), 1, et
.size
);
13153 do_neon_recip_est (void)
13155 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13156 struct neon_type_el et
= neon_check_type (2, rs
,
13157 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
13158 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13159 neon_two_same (neon_quad (rs
), 1, et
.size
);
13165 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13166 struct neon_type_el et
= neon_check_type (2, rs
,
13167 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13168 neon_two_same (neon_quad (rs
), 1, et
.size
);
13174 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13175 struct neon_type_el et
= neon_check_type (2, rs
,
13176 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
13177 neon_two_same (neon_quad (rs
), 1, et
.size
);
13183 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13184 struct neon_type_el et
= neon_check_type (2, rs
,
13185 N_EQK
| N_INT
, N_8
| N_KEY
);
13186 neon_two_same (neon_quad (rs
), 1, et
.size
);
13192 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13193 neon_two_same (neon_quad (rs
), 1, -1);
13197 do_neon_tbl_tbx (void)
13199 unsigned listlenbits
;
13200 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
13202 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
13204 first_error (_("bad list length for table lookup"));
13208 listlenbits
= inst
.operands
[1].imm
- 1;
13209 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13210 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13211 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13212 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13213 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13214 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13215 inst
.instruction
|= listlenbits
<< 8;
13217 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13221 do_neon_ldm_stm (void)
13223 /* P, U and L bits are part of bitmask. */
13224 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
13225 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
13227 if (inst
.operands
[1].issingle
)
13229 do_vfp_nsyn_ldm_stm (is_dbmode
);
13233 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
13234 _("writeback (!) must be used for VLDMDB and VSTMDB"));
13236 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
13237 _("register list must contain at least 1 and at most 16 "
13240 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
13241 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
13242 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13243 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
13245 inst
.instruction
|= offsetbits
;
13247 do_vfp_cond_or_thumb ();
13251 do_neon_ldr_str (void)
13253 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
13255 if (inst
.operands
[0].issingle
)
13258 do_vfp_nsyn_opcode ("flds");
13260 do_vfp_nsyn_opcode ("fsts");
13265 do_vfp_nsyn_opcode ("fldd");
13267 do_vfp_nsyn_opcode ("fstd");
13271 /* "interleave" version also handles non-interleaving register VLD1/VST1
13275 do_neon_ld_st_interleave (void)
13277 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
13278 N_8
| N_16
| N_32
| N_64
);
13279 unsigned alignbits
= 0;
13281 /* The bits in this table go:
13282 0: register stride of one (0) or two (1)
13283 1,2: register list length, minus one (1, 2, 3, 4).
13284 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
13285 We use -1 for invalid entries. */
13286 const int typetable
[] =
13288 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
13289 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
13290 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
13291 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
13295 if (et
.type
== NT_invtype
)
13298 if (inst
.operands
[1].immisalign
)
13299 switch (inst
.operands
[1].imm
>> 8)
13301 case 64: alignbits
= 1; break;
13303 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13304 goto bad_alignment
;
13308 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13309 goto bad_alignment
;
13314 first_error (_("bad alignment"));
13318 inst
.instruction
|= alignbits
<< 4;
13319 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13321 /* Bits [4:6] of the immediate in a list specifier encode register stride
13322 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
13323 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
13324 up the right value for "type" in a table based on this value and the given
13325 list style, then stick it back. */
13326 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
13327 | (((inst
.instruction
>> 8) & 3) << 3);
13329 typebits
= typetable
[idx
];
13331 constraint (typebits
== -1, _("bad list type for instruction"));
13333 inst
.instruction
&= ~0xf00;
13334 inst
.instruction
|= typebits
<< 8;
13337 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
13338 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
13339 otherwise. The variable arguments are a list of pairs of legal (size, align)
13340 values, terminated with -1. */
13343 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
13346 int result
= FAIL
, thissize
, thisalign
;
13348 if (!inst
.operands
[1].immisalign
)
13354 va_start (ap
, do_align
);
13358 thissize
= va_arg (ap
, int);
13359 if (thissize
== -1)
13361 thisalign
= va_arg (ap
, int);
13363 if (size
== thissize
&& align
== thisalign
)
13366 while (result
!= SUCCESS
);
13370 if (result
== SUCCESS
)
13373 first_error (_("unsupported alignment for instruction"));
13379 do_neon_ld_st_lane (void)
13381 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13382 int align_good
, do_align
= 0;
13383 int logsize
= neon_logbits (et
.size
);
13384 int align
= inst
.operands
[1].imm
>> 8;
13385 int n
= (inst
.instruction
>> 8) & 3;
13386 int max_el
= 64 / et
.size
;
13388 if (et
.type
== NT_invtype
)
13391 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
13392 _("bad list length"));
13393 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
13394 _("scalar index out of range"));
13395 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
13397 _("stride of 2 unavailable when element size is 8"));
13401 case 0: /* VLD1 / VST1. */
13402 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
13404 if (align_good
== FAIL
)
13408 unsigned alignbits
= 0;
13411 case 16: alignbits
= 0x1; break;
13412 case 32: alignbits
= 0x3; break;
13415 inst
.instruction
|= alignbits
<< 4;
13419 case 1: /* VLD2 / VST2. */
13420 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
13422 if (align_good
== FAIL
)
13425 inst
.instruction
|= 1 << 4;
13428 case 2: /* VLD3 / VST3. */
13429 constraint (inst
.operands
[1].immisalign
,
13430 _("can't use alignment with this instruction"));
13433 case 3: /* VLD4 / VST4. */
13434 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13435 16, 64, 32, 64, 32, 128, -1);
13436 if (align_good
== FAIL
)
13440 unsigned alignbits
= 0;
13443 case 8: alignbits
= 0x1; break;
13444 case 16: alignbits
= 0x1; break;
13445 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
13448 inst
.instruction
|= alignbits
<< 4;
13455 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
13456 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13457 inst
.instruction
|= 1 << (4 + logsize
);
13459 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
13460 inst
.instruction
|= logsize
<< 10;
13463 /* Encode single n-element structure to all lanes VLD<n> instructions. */
13466 do_neon_ld_dup (void)
13468 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13469 int align_good
, do_align
= 0;
13471 if (et
.type
== NT_invtype
)
13474 switch ((inst
.instruction
>> 8) & 3)
13476 case 0: /* VLD1. */
13477 assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
13478 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13479 &do_align
, 16, 16, 32, 32, -1);
13480 if (align_good
== FAIL
)
13482 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
13485 case 2: inst
.instruction
|= 1 << 5; break;
13486 default: first_error (_("bad list length")); return;
13488 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13491 case 1: /* VLD2. */
13492 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13493 &do_align
, 8, 16, 16, 32, 32, 64, -1);
13494 if (align_good
== FAIL
)
13496 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
13497 _("bad list length"));
13498 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13499 inst
.instruction
|= 1 << 5;
13500 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13503 case 2: /* VLD3. */
13504 constraint (inst
.operands
[1].immisalign
,
13505 _("can't use alignment with this instruction"));
13506 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
13507 _("bad list length"));
13508 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13509 inst
.instruction
|= 1 << 5;
13510 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13513 case 3: /* VLD4. */
13515 int align
= inst
.operands
[1].imm
>> 8;
13516 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13517 16, 64, 32, 64, 32, 128, -1);
13518 if (align_good
== FAIL
)
13520 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
13521 _("bad list length"));
13522 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13523 inst
.instruction
|= 1 << 5;
13524 if (et
.size
== 32 && align
== 128)
13525 inst
.instruction
|= 0x3 << 6;
13527 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13534 inst
.instruction
|= do_align
<< 4;
13537 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
13538 apart from bits [11:4]. */
13541 do_neon_ldx_stx (void)
13543 switch (NEON_LANE (inst
.operands
[0].imm
))
13545 case NEON_INTERLEAVE_LANES
:
13546 inst
.instruction
= NEON_ENC_INTERLV (inst
.instruction
);
13547 do_neon_ld_st_interleave ();
13550 case NEON_ALL_LANES
:
13551 inst
.instruction
= NEON_ENC_DUP (inst
.instruction
);
13556 inst
.instruction
= NEON_ENC_LANE (inst
.instruction
);
13557 do_neon_ld_st_lane ();
13560 /* L bit comes from bit mask. */
13561 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13562 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13563 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13565 if (inst
.operands
[1].postind
)
13567 int postreg
= inst
.operands
[1].imm
& 0xf;
13568 constraint (!inst
.operands
[1].immisreg
,
13569 _("post-index must be a register"));
13570 constraint (postreg
== 0xd || postreg
== 0xf,
13571 _("bad register for post-index"));
13572 inst
.instruction
|= postreg
;
13574 else if (inst
.operands
[1].writeback
)
13576 inst
.instruction
|= 0xd;
13579 inst
.instruction
|= 0xf;
13582 inst
.instruction
|= 0xf9000000;
13584 inst
.instruction
|= 0xf4000000;
13588 /* Overall per-instruction processing. */
13590 /* We need to be able to fix up arbitrary expressions in some statements.
13591 This is so that we can handle symbols that are an arbitrary distance from
13592 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
13593 which returns part of an address in a form which will be valid for
13594 a data instruction. We do this by pushing the expression into a symbol
13595 in the expr_section, and creating a fix for that. */
13598 fix_new_arm (fragS
* frag
,
13613 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
13617 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
13622 /* Mark whether the fix is to a THUMB instruction, or an ARM
13624 new_fix
->tc_fix_data
= thumb_mode
;
13627 /* Create a frg for an instruction requiring relaxation. */
13629 output_relax_insn (void)
13635 /* The size of the instruction is unknown, so tie the debug info to the
13636 start of the instruction. */
13637 dwarf2_emit_insn (0);
13639 switch (inst
.reloc
.exp
.X_op
)
13642 sym
= inst
.reloc
.exp
.X_add_symbol
;
13643 offset
= inst
.reloc
.exp
.X_add_number
;
13647 offset
= inst
.reloc
.exp
.X_add_number
;
13650 sym
= make_expr_symbol (&inst
.reloc
.exp
);
13654 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
13655 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
13656 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
13659 /* Write a 32-bit thumb instruction to buf. */
13661 put_thumb32_insn (char * buf
, unsigned long insn
)
13663 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
13664 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
13668 output_inst (const char * str
)
13674 as_bad ("%s -- `%s'", inst
.error
, str
);
13678 output_relax_insn();
13681 if (inst
.size
== 0)
13684 to
= frag_more (inst
.size
);
13686 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
13688 assert (inst
.size
== (2 * THUMB_SIZE
));
13689 put_thumb32_insn (to
, inst
.instruction
);
13691 else if (inst
.size
> INSN_SIZE
)
13693 assert (inst
.size
== (2 * INSN_SIZE
));
13694 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
13695 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
13698 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
13700 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
13701 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
13702 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
13705 dwarf2_emit_insn (inst
.size
);
13708 /* Tag values used in struct asm_opcode's tag field. */
13711 OT_unconditional
, /* Instruction cannot be conditionalized.
13712 The ARM condition field is still 0xE. */
13713 OT_unconditionalF
, /* Instruction cannot be conditionalized
13714 and carries 0xF in its ARM condition field. */
13715 OT_csuffix
, /* Instruction takes a conditional suffix. */
13716 OT_csuffixF
, /* Some forms of the instruction take a conditional
13717 suffix, others place 0xF where the condition field
13719 OT_cinfix3
, /* Instruction takes a conditional infix,
13720 beginning at character index 3. (In
13721 unified mode, it becomes a suffix.) */
13722 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
13723 tsts, cmps, cmns, and teqs. */
13724 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
13725 character index 3, even in unified mode. Used for
13726 legacy instructions where suffix and infix forms
13727 may be ambiguous. */
13728 OT_csuf_or_in3
, /* Instruction takes either a conditional
13729 suffix or an infix at character index 3. */
13730 OT_odd_infix_unc
, /* This is the unconditional variant of an
13731 instruction that takes a conditional infix
13732 at an unusual position. In unified mode,
13733 this variant will accept a suffix. */
13734 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
13735 are the conditional variants of instructions that
13736 take conditional infixes in unusual positions.
13737 The infix appears at character index
13738 (tag - OT_odd_infix_0). These are not accepted
13739 in unified mode. */
13742 /* Subroutine of md_assemble, responsible for looking up the primary
13743 opcode from the mnemonic the user wrote. STR points to the
13744 beginning of the mnemonic.
13746 This is not simply a hash table lookup, because of conditional
13747 variants. Most instructions have conditional variants, which are
13748 expressed with a _conditional affix_ to the mnemonic. If we were
13749 to encode each conditional variant as a literal string in the opcode
13750 table, it would have approximately 20,000 entries.
13752 Most mnemonics take this affix as a suffix, and in unified syntax,
13753 'most' is upgraded to 'all'. However, in the divided syntax, some
13754 instructions take the affix as an infix, notably the s-variants of
13755 the arithmetic instructions. Of those instructions, all but six
13756 have the infix appear after the third character of the mnemonic.
13758 Accordingly, the algorithm for looking up primary opcodes given
13761 1. Look up the identifier in the opcode table.
13762 If we find a match, go to step U.
13764 2. Look up the last two characters of the identifier in the
13765 conditions table. If we find a match, look up the first N-2
13766 characters of the identifier in the opcode table. If we
13767 find a match, go to step CE.
13769 3. Look up the fourth and fifth characters of the identifier in
13770 the conditions table. If we find a match, extract those
13771 characters from the identifier, and look up the remaining
13772 characters in the opcode table. If we find a match, go
13777 U. Examine the tag field of the opcode structure, in case this is
13778 one of the six instructions with its conditional infix in an
13779 unusual place. If it is, the tag tells us where to find the
13780 infix; look it up in the conditions table and set inst.cond
13781 accordingly. Otherwise, this is an unconditional instruction.
13782 Again set inst.cond accordingly. Return the opcode structure.
13784 CE. Examine the tag field to make sure this is an instruction that
13785 should receive a conditional suffix. If it is not, fail.
13786 Otherwise, set inst.cond from the suffix we already looked up,
13787 and return the opcode structure.
13789 CM. Examine the tag field to make sure this is an instruction that
13790 should receive a conditional infix after the third character.
13791 If it is not, fail. Otherwise, undo the edits to the current
13792 line of input and proceed as for case CE. */
13794 static const struct asm_opcode
*
13795 opcode_lookup (char **str
)
13799 const struct asm_opcode
*opcode
;
13800 const struct asm_cond
*cond
;
13802 bfd_boolean neon_supported
;
13804 neon_supported
= ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
);
13806 /* Scan up to the end of the mnemonic, which must end in white space,
13807 '.' (in unified mode, or for Neon instructions), or end of string. */
13808 for (base
= end
= *str
; *end
!= '\0'; end
++)
13809 if (*end
== ' ' || ((unified_syntax
|| neon_supported
) && *end
== '.'))
13815 /* Handle a possible width suffix and/or Neon type suffix. */
13820 /* The .w and .n suffixes are only valid if the unified syntax is in
13822 if (unified_syntax
&& end
[1] == 'w')
13824 else if (unified_syntax
&& end
[1] == 'n')
13829 inst
.vectype
.elems
= 0;
13831 *str
= end
+ offset
;
13833 if (end
[offset
] == '.')
13835 /* See if we have a Neon type suffix (possible in either unified or
13836 non-unified ARM syntax mode). */
13837 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
13840 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
13846 /* Look for unaffixed or special-case affixed mnemonic. */
13847 opcode
= hash_find_n (arm_ops_hsh
, base
, end
- base
);
13851 if (opcode
->tag
< OT_odd_infix_0
)
13853 inst
.cond
= COND_ALWAYS
;
13857 if (unified_syntax
)
13858 as_warn (_("conditional infixes are deprecated in unified syntax"));
13859 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
13860 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
13863 inst
.cond
= cond
->value
;
13867 /* Cannot have a conditional suffix on a mnemonic of less than two
13869 if (end
- base
< 3)
13872 /* Look for suffixed mnemonic. */
13874 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
13875 opcode
= hash_find_n (arm_ops_hsh
, base
, affix
- base
);
13876 if (opcode
&& cond
)
13879 switch (opcode
->tag
)
13881 case OT_cinfix3_legacy
:
13882 /* Ignore conditional suffixes matched on infix only mnemonics. */
13886 case OT_cinfix3_deprecated
:
13887 case OT_odd_infix_unc
:
13888 if (!unified_syntax
)
13890 /* else fall through */
13894 case OT_csuf_or_in3
:
13895 inst
.cond
= cond
->value
;
13898 case OT_unconditional
:
13899 case OT_unconditionalF
:
13902 inst
.cond
= cond
->value
;
13906 /* delayed diagnostic */
13907 inst
.error
= BAD_COND
;
13908 inst
.cond
= COND_ALWAYS
;
13917 /* Cannot have a usual-position infix on a mnemonic of less than
13918 six characters (five would be a suffix). */
13919 if (end
- base
< 6)
13922 /* Look for infixed mnemonic in the usual position. */
13924 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
13928 memcpy (save
, affix
, 2);
13929 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
13930 opcode
= hash_find_n (arm_ops_hsh
, base
, (end
- base
) - 2);
13931 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
13932 memcpy (affix
, save
, 2);
13935 && (opcode
->tag
== OT_cinfix3
13936 || opcode
->tag
== OT_cinfix3_deprecated
13937 || opcode
->tag
== OT_csuf_or_in3
13938 || opcode
->tag
== OT_cinfix3_legacy
))
13942 && (opcode
->tag
== OT_cinfix3
13943 || opcode
->tag
== OT_cinfix3_deprecated
))
13944 as_warn (_("conditional infixes are deprecated in unified syntax"));
13946 inst
.cond
= cond
->value
;
13954 md_assemble (char *str
)
13957 const struct asm_opcode
* opcode
;
13959 /* Align the previous label if needed. */
13960 if (last_label_seen
!= NULL
)
13962 symbol_set_frag (last_label_seen
, frag_now
);
13963 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
13964 S_SET_SEGMENT (last_label_seen
, now_seg
);
13967 memset (&inst
, '\0', sizeof (inst
));
13968 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13970 opcode
= opcode_lookup (&p
);
13973 /* It wasn't an instruction, but it might be a register alias of
13974 the form alias .req reg, or a Neon .dn/.qn directive. */
13975 if (!create_register_alias (str
, p
)
13976 && !create_neon_reg_alias (str
, p
))
13977 as_bad (_("bad instruction `%s'"), str
);
13982 if (opcode
->tag
== OT_cinfix3_deprecated
)
13983 as_warn (_("s suffix on comparison instruction is deprecated"));
13985 /* The value which unconditional instructions should have in place of the
13986 condition field. */
13987 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
13991 arm_feature_set variant
;
13993 variant
= cpu_variant
;
13994 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
13995 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
13996 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
13997 /* Check that this instruction is supported for this CPU. */
13998 if (!opcode
->tvariant
13999 || (thumb_mode
== 1
14000 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
14002 as_bad (_("selected processor does not support `%s'"), str
);
14005 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
14006 && opcode
->tencode
!= do_t_branch
)
14008 as_bad (_("Thumb does not support conditional execution"));
14012 /* Check conditional suffixes. */
14013 if (current_it_mask
)
14016 cond
= current_cc
^ ((current_it_mask
>> 4) & 1) ^ 1;
14017 current_it_mask
<<= 1;
14018 current_it_mask
&= 0x1f;
14019 /* The BKPT instruction is unconditional even in an IT block. */
14021 && cond
!= inst
.cond
&& opcode
->tencode
!= do_t_bkpt
)
14023 as_bad (_("incorrect condition in IT block"));
14027 else if (inst
.cond
!= COND_ALWAYS
&& opcode
->tencode
!= do_t_branch
)
14029 as_bad (_("thumb conditional instrunction not in IT block"));
14033 mapping_state (MAP_THUMB
);
14034 inst
.instruction
= opcode
->tvalue
;
14036 if (!parse_operands (p
, opcode
->operands
))
14037 opcode
->tencode ();
14039 /* Clear current_it_mask at the end of an IT block. */
14040 if (current_it_mask
== 0x10)
14041 current_it_mask
= 0;
14043 if (!(inst
.error
|| inst
.relax
))
14045 assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
14046 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
14047 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
14049 as_bad (_("cannot honor width suffix -- `%s'"), str
);
14053 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
14054 *opcode
->tvariant
);
14055 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
14056 set those bits when Thumb-2 32-bit instructions are seen. ie.
14057 anything other than bl/blx.
14058 This is overly pessimistic for relaxable instructions. */
14059 if ((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
14061 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
14064 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
14066 /* Check that this instruction is supported for this CPU. */
14067 if (!opcode
->avariant
||
14068 !ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
))
14070 as_bad (_("selected processor does not support `%s'"), str
);
14075 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
14079 mapping_state (MAP_ARM
);
14080 inst
.instruction
= opcode
->avalue
;
14081 if (opcode
->tag
== OT_unconditionalF
)
14082 inst
.instruction
|= 0xF << 28;
14084 inst
.instruction
|= inst
.cond
<< 28;
14085 inst
.size
= INSN_SIZE
;
14086 if (!parse_operands (p
, opcode
->operands
))
14087 opcode
->aencode ();
14088 /* Arm mode bx is marked as both v4T and v5 because it's still required
14089 on a hypothetical non-thumb v5 core. */
14090 if (ARM_CPU_HAS_FEATURE (*opcode
->avariant
, arm_ext_v4t
)
14091 || ARM_CPU_HAS_FEATURE (*opcode
->avariant
, arm_ext_v5
))
14092 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
14094 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
14095 *opcode
->avariant
);
14099 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
14106 /* Various frobbings of labels and their addresses. */
14109 arm_start_line_hook (void)
14111 last_label_seen
= NULL
;
14115 arm_frob_label (symbolS
* sym
)
14117 last_label_seen
= sym
;
14119 ARM_SET_THUMB (sym
, thumb_mode
);
14121 #if defined OBJ_COFF || defined OBJ_ELF
14122 ARM_SET_INTERWORK (sym
, support_interwork
);
14125 /* Note - do not allow local symbols (.Lxxx) to be labeled
14126 as Thumb functions. This is because these labels, whilst
14127 they exist inside Thumb code, are not the entry points for
14128 possible ARM->Thumb calls. Also, these labels can be used
14129 as part of a computed goto or switch statement. eg gcc
14130 can generate code that looks like this:
14132 ldr r2, [pc, .Laaa]
14142 The first instruction loads the address of the jump table.
14143 The second instruction converts a table index into a byte offset.
14144 The third instruction gets the jump address out of the table.
14145 The fourth instruction performs the jump.
14147 If the address stored at .Laaa is that of a symbol which has the
14148 Thumb_Func bit set, then the linker will arrange for this address
14149 to have the bottom bit set, which in turn would mean that the
14150 address computation performed by the third instruction would end
14151 up with the bottom bit set. Since the ARM is capable of unaligned
14152 word loads, the instruction would then load the incorrect address
14153 out of the jump table, and chaos would ensue. */
14154 if (label_is_thumb_function_name
14155 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
14156 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
14158 /* When the address of a Thumb function is taken the bottom
14159 bit of that address should be set. This will allow
14160 interworking between Arm and Thumb functions to work
14163 THUMB_SET_FUNC (sym
, 1);
14165 label_is_thumb_function_name
= FALSE
;
14168 dwarf2_emit_label (sym
);
14172 arm_data_in_code (void)
14174 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
14176 *input_line_pointer
= '/';
14177 input_line_pointer
+= 5;
14178 *input_line_pointer
= 0;
14186 arm_canonicalize_symbol_name (char * name
)
14190 if (thumb_mode
&& (len
= strlen (name
)) > 5
14191 && streq (name
+ len
- 5, "/data"))
14192 *(name
+ len
- 5) = 0;
14197 /* Table of all register names defined by default. The user can
14198 define additional names with .req. Note that all register names
14199 should appear in both upper and lowercase variants. Some registers
14200 also have mixed-case names. */
14202 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
14203 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
14204 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
14205 #define REGSET(p,t) \
14206 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
14207 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
14208 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
14209 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
14210 #define REGSETH(p,t) \
14211 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
14212 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
14213 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
14214 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
14215 #define REGSET2(p,t) \
14216 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
14217 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
14218 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
14219 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
14221 static const struct reg_entry reg_names
[] =
14223 /* ARM integer registers. */
14224 REGSET(r
, RN
), REGSET(R
, RN
),
14226 /* ATPCS synonyms. */
14227 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
14228 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
14229 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
14231 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
14232 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
14233 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
14235 /* Well-known aliases. */
14236 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
14237 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
14239 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
14240 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
14242 /* Coprocessor numbers. */
14243 REGSET(p
, CP
), REGSET(P
, CP
),
14245 /* Coprocessor register numbers. The "cr" variants are for backward
14247 REGSET(c
, CN
), REGSET(C
, CN
),
14248 REGSET(cr
, CN
), REGSET(CR
, CN
),
14250 /* FPA registers. */
14251 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
14252 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
14254 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
14255 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
14257 /* VFP SP registers. */
14258 REGSET(s
,VFS
), REGSET(S
,VFS
),
14259 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
14261 /* VFP DP Registers. */
14262 REGSET(d
,VFD
), REGSET(D
,VFD
),
14263 /* Extra Neon DP registers. */
14264 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
14266 /* Neon QP registers. */
14267 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
14269 /* VFP control registers. */
14270 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
14271 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
14273 /* Maverick DSP coprocessor registers. */
14274 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
14275 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
14277 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
14278 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
14279 REGDEF(dspsc
,0,DSPSC
),
14281 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
14282 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
14283 REGDEF(DSPSC
,0,DSPSC
),
14285 /* iWMMXt data registers - p0, c0-15. */
14286 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
14288 /* iWMMXt control registers - p1, c0-3. */
14289 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
14290 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
14291 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
14292 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
14294 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
14295 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
14296 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
14297 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
14298 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
14300 /* XScale accumulator registers. */
14301 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
14307 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
14308 within psr_required_here. */
14309 static const struct asm_psr psrs
[] =
14311 /* Backward compatibility notation. Note that "all" is no longer
14312 truly all possible PSR bits. */
14313 {"all", PSR_c
| PSR_f
},
14317 /* Individual flags. */
14322 /* Combinations of flags. */
14323 {"fs", PSR_f
| PSR_s
},
14324 {"fx", PSR_f
| PSR_x
},
14325 {"fc", PSR_f
| PSR_c
},
14326 {"sf", PSR_s
| PSR_f
},
14327 {"sx", PSR_s
| PSR_x
},
14328 {"sc", PSR_s
| PSR_c
},
14329 {"xf", PSR_x
| PSR_f
},
14330 {"xs", PSR_x
| PSR_s
},
14331 {"xc", PSR_x
| PSR_c
},
14332 {"cf", PSR_c
| PSR_f
},
14333 {"cs", PSR_c
| PSR_s
},
14334 {"cx", PSR_c
| PSR_x
},
14335 {"fsx", PSR_f
| PSR_s
| PSR_x
},
14336 {"fsc", PSR_f
| PSR_s
| PSR_c
},
14337 {"fxs", PSR_f
| PSR_x
| PSR_s
},
14338 {"fxc", PSR_f
| PSR_x
| PSR_c
},
14339 {"fcs", PSR_f
| PSR_c
| PSR_s
},
14340 {"fcx", PSR_f
| PSR_c
| PSR_x
},
14341 {"sfx", PSR_s
| PSR_f
| PSR_x
},
14342 {"sfc", PSR_s
| PSR_f
| PSR_c
},
14343 {"sxf", PSR_s
| PSR_x
| PSR_f
},
14344 {"sxc", PSR_s
| PSR_x
| PSR_c
},
14345 {"scf", PSR_s
| PSR_c
| PSR_f
},
14346 {"scx", PSR_s
| PSR_c
| PSR_x
},
14347 {"xfs", PSR_x
| PSR_f
| PSR_s
},
14348 {"xfc", PSR_x
| PSR_f
| PSR_c
},
14349 {"xsf", PSR_x
| PSR_s
| PSR_f
},
14350 {"xsc", PSR_x
| PSR_s
| PSR_c
},
14351 {"xcf", PSR_x
| PSR_c
| PSR_f
},
14352 {"xcs", PSR_x
| PSR_c
| PSR_s
},
14353 {"cfs", PSR_c
| PSR_f
| PSR_s
},
14354 {"cfx", PSR_c
| PSR_f
| PSR_x
},
14355 {"csf", PSR_c
| PSR_s
| PSR_f
},
14356 {"csx", PSR_c
| PSR_s
| PSR_x
},
14357 {"cxf", PSR_c
| PSR_x
| PSR_f
},
14358 {"cxs", PSR_c
| PSR_x
| PSR_s
},
14359 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
14360 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
14361 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
14362 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
14363 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
14364 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
14365 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
14366 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
14367 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
14368 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
14369 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
14370 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
14371 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
14372 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
14373 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
14374 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
14375 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
14376 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
14377 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
14378 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
14379 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
14380 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
14381 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
14382 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
14385 /* Table of V7M psr names. */
14386 static const struct asm_psr v7m_psrs
[] =
14399 {"basepri_max", 18},
14404 /* Table of all shift-in-operand names. */
14405 static const struct asm_shift_name shift_names
[] =
14407 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
14408 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
14409 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
14410 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
14411 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
14412 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
14415 /* Table of all explicit relocation names. */
14417 static struct reloc_entry reloc_names
[] =
14419 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
14420 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
14421 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
14422 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
14423 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
14424 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
14425 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
14426 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
14427 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
14428 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
14429 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
14433 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
14434 static const struct asm_cond conds
[] =
14438 {"cs", 0x2}, {"hs", 0x2},
14439 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
14453 static struct asm_barrier_opt barrier_opt_names
[] =
14461 /* Table of ARM-format instructions. */
14463 /* Macros for gluing together operand strings. N.B. In all cases
14464 other than OPS0, the trailing OP_stop comes from default
14465 zero-initialization of the unspecified elements of the array. */
14466 #define OPS0() { OP_stop, }
14467 #define OPS1(a) { OP_##a, }
14468 #define OPS2(a,b) { OP_##a,OP_##b, }
14469 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
14470 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
14471 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
14472 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
14474 /* These macros abstract out the exact format of the mnemonic table and
14475 save some repeated characters. */
14477 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
14478 #define TxCE(mnem, op, top, nops, ops, ae, te) \
14479 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
14480 THUMB_VARIANT, do_##ae, do_##te }
14482 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
14483 a T_MNEM_xyz enumerator. */
14484 #define TCE(mnem, aop, top, nops, ops, ae, te) \
14485 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
14486 #define tCE(mnem, aop, top, nops, ops, ae, te) \
14487 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14489 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
14490 infix after the third character. */
14491 #define TxC3(mnem, op, top, nops, ops, ae, te) \
14492 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
14493 THUMB_VARIANT, do_##ae, do_##te }
14494 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
14495 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
14496 THUMB_VARIANT, do_##ae, do_##te }
14497 #define TC3(mnem, aop, top, nops, ops, ae, te) \
14498 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
14499 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
14500 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
14501 #define tC3(mnem, aop, top, nops, ops, ae, te) \
14502 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14503 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
14504 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14506 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
14507 appear in the condition table. */
14508 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
14509 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14510 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
14512 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
14513 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
14514 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
14515 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
14516 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
14517 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
14518 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
14519 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
14520 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
14521 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
14522 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
14523 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
14524 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
14525 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
14526 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
14527 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
14528 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
14529 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
14530 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
14531 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
14533 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
14534 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
14535 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
14536 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
14538 /* Mnemonic that cannot be conditionalized. The ARM condition-code
14539 field is still 0xE. Many of the Thumb variants can be executed
14540 conditionally, so this is checked separately. */
14541 #define TUE(mnem, op, top, nops, ops, ae, te) \
14542 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
14543 THUMB_VARIANT, do_##ae, do_##te }
14545 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
14546 condition code field. */
14547 #define TUF(mnem, op, top, nops, ops, ae, te) \
14548 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
14549 THUMB_VARIANT, do_##ae, do_##te }
14551 /* ARM-only variants of all the above. */
14552 #define CE(mnem, op, nops, ops, ae) \
14553 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14555 #define C3(mnem, op, nops, ops, ae) \
14556 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14558 /* Legacy mnemonics that always have conditional infix after the third
14560 #define CL(mnem, op, nops, ops, ae) \
14561 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14562 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14564 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
14565 #define cCE(mnem, op, nops, ops, ae) \
14566 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14568 /* Legacy coprocessor instructions where conditional infix and conditional
14569 suffix are ambiguous. For consistency this includes all FPA instructions,
14570 not just the potentially ambiguous ones. */
14571 #define cCL(mnem, op, nops, ops, ae) \
14572 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14573 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14575 /* Coprocessor, takes either a suffix or a position-3 infix
14576 (for an FPA corner case). */
14577 #define C3E(mnem, op, nops, ops, ae) \
14578 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
14579 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14581 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
14582 { #m1 #m2 #m3, OPS##nops ops, \
14583 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14584 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14586 #define CM(m1, m2, op, nops, ops, ae) \
14587 xCM_(m1, , m2, op, nops, ops, ae), \
14588 xCM_(m1, eq, m2, op, nops, ops, ae), \
14589 xCM_(m1, ne, m2, op, nops, ops, ae), \
14590 xCM_(m1, cs, m2, op, nops, ops, ae), \
14591 xCM_(m1, hs, m2, op, nops, ops, ae), \
14592 xCM_(m1, cc, m2, op, nops, ops, ae), \
14593 xCM_(m1, ul, m2, op, nops, ops, ae), \
14594 xCM_(m1, lo, m2, op, nops, ops, ae), \
14595 xCM_(m1, mi, m2, op, nops, ops, ae), \
14596 xCM_(m1, pl, m2, op, nops, ops, ae), \
14597 xCM_(m1, vs, m2, op, nops, ops, ae), \
14598 xCM_(m1, vc, m2, op, nops, ops, ae), \
14599 xCM_(m1, hi, m2, op, nops, ops, ae), \
14600 xCM_(m1, ls, m2, op, nops, ops, ae), \
14601 xCM_(m1, ge, m2, op, nops, ops, ae), \
14602 xCM_(m1, lt, m2, op, nops, ops, ae), \
14603 xCM_(m1, gt, m2, op, nops, ops, ae), \
14604 xCM_(m1, le, m2, op, nops, ops, ae), \
14605 xCM_(m1, al, m2, op, nops, ops, ae)
14607 #define UE(mnem, op, nops, ops, ae) \
14608 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14610 #define UF(mnem, op, nops, ops, ae) \
14611 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14613 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
14614 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
14615 use the same encoding function for each. */
14616 #define NUF(mnem, op, nops, ops, enc) \
14617 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
14618 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14620 /* Neon data processing, version which indirects through neon_enc_tab for
14621 the various overloaded versions of opcodes. */
14622 #define nUF(mnem, op, nops, ops, enc) \
14623 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \
14624 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14626 /* Neon insn with conditional suffix for the ARM version, non-overloaded
14628 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
14629 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
14630 THUMB_VARIANT, do_##enc, do_##enc }
14632 #define NCE(mnem, op, nops, ops, enc) \
14633 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14635 #define NCEF(mnem, op, nops, ops, enc) \
14636 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14638 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
14639 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
14640 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \
14641 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14643 #define nCE(mnem, op, nops, ops, enc) \
14644 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14646 #define nCEF(mnem, op, nops, ops, enc) \
14647 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14651 /* Thumb-only, unconditional. */
14652 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
14654 static const struct asm_opcode insns
[] =
14656 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
14657 #define THUMB_VARIANT &arm_ext_v4t
14658 tCE(and, 0000000, and, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14659 tC3(ands
, 0100000, ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14660 tCE(eor
, 0200000, eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14661 tC3(eors
, 0300000, eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14662 tCE(sub
, 0400000, sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14663 tC3(subs
, 0500000, subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14664 tCE(add
, 0800000, add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14665 tC3(adds
, 0900000, adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14666 tCE(adc
, 0a00000
, adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14667 tC3(adcs
, 0b00000, adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14668 tCE(sbc
, 0c00000
, sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14669 tC3(sbcs
, 0d00000
, sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14670 tCE(orr
, 1800000, orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14671 tC3(orrs
, 1900000, orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14672 tCE(bic
, 1c00000
, bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14673 tC3(bics
, 1d00000
, bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14675 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
14676 for setting PSR flag bits. They are obsolete in V6 and do not
14677 have Thumb equivalents. */
14678 tCE(tst
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14679 tC3w(tsts
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14680 CL(tstp
, 110f000
, 2, (RR
, SH
), cmp
),
14681 tCE(cmp
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14682 tC3w(cmps
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14683 CL(cmpp
, 150f000
, 2, (RR
, SH
), cmp
),
14684 tCE(cmn
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14685 tC3w(cmns
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14686 CL(cmnp
, 170f000
, 2, (RR
, SH
), cmp
),
14688 tCE(mov
, 1a00000
, mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14689 tC3(movs
, 1b00000
, movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14690 tCE(mvn
, 1e00000
, mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14691 tC3(mvns
, 1f00000
, mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14693 tCE(ldr
, 4100000, ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14694 tC3(ldrb
, 4500000, ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14695 tCE(str
, 4000000, str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14696 tC3(strb
, 4400000, strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14698 tCE(stm
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14699 tC3(stmia
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14700 tC3(stmea
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14701 tCE(ldm
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14702 tC3(ldmia
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14703 tC3(ldmfd
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14705 TCE(swi
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14706 TCE(svc
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14707 tCE(b
, a000000
, b
, 1, (EXPr
), branch
, t_branch
),
14708 TCE(bl
, b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
14711 tCE(adr
, 28f0000
, adr
, 2, (RR
, EXP
), adr
, t_adr
),
14712 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
14713 tCE(nop
, 1a00000
, nop
, 1, (oI255c
), nop
, t_nop
),
14715 /* Thumb-compatibility pseudo ops. */
14716 tCE(lsl
, 1a00000
, lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14717 tC3(lsls
, 1b00000
, lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14718 tCE(lsr
, 1a00020
, lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14719 tC3(lsrs
, 1b00020
, lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14720 tCE(asr
, 1a00040
, asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14721 tC3(asrs
, 1b00040
, asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14722 tCE(ror
, 1a00060
, ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14723 tC3(rors
, 1b00060
, rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14724 tCE(neg
, 2600000, neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
14725 tC3(negs
, 2700000, negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
14726 tCE(push
, 92d0000
, push
, 1, (REGLST
), push_pop
, t_push_pop
),
14727 tCE(pop
, 8bd0000
, pop
, 1, (REGLST
), push_pop
, t_push_pop
),
14729 #undef THUMB_VARIANT
14730 #define THUMB_VARIANT &arm_ext_v6
14731 TCE(cpy
, 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
14733 /* V1 instructions with no Thumb analogue prior to V6T2. */
14734 #undef THUMB_VARIANT
14735 #define THUMB_VARIANT &arm_ext_v6t2
14736 TCE(rsb
, 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14737 TC3(rsbs
, 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14738 TCE(teq
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14739 TC3w(teqs
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14740 CL(teqp
, 130f000
, 2, (RR
, SH
), cmp
),
14742 TC3(ldrt
, 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14743 TC3(ldrbt
, 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14744 TC3(strt
, 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14745 TC3(strbt
, 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14747 TC3(stmdb
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14748 TC3(stmfd
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14750 TC3(ldmdb
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14751 TC3(ldmea
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14753 /* V1 instructions with no Thumb analogue at all. */
14754 CE(rsc
, 0e00000
, 3, (RR
, oRR
, SH
), arit
),
14755 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
14757 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
14758 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
14759 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
14760 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
14761 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
14762 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
14763 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
14764 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
14767 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
14768 #undef THUMB_VARIANT
14769 #define THUMB_VARIANT &arm_ext_v4t
14770 tCE(mul
, 0000090, mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
14771 tC3(muls
, 0100090, muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
14773 #undef THUMB_VARIANT
14774 #define THUMB_VARIANT &arm_ext_v6t2
14775 TCE(mla
, 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
14776 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
14778 /* Generic coprocessor instructions. */
14779 TCE(cdp
, e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
14780 TCE(ldc
, c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14781 TC3(ldcl
, c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14782 TCE(stc
, c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14783 TC3(stcl
, c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14784 TCE(mcr
, e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14785 TCE(mrc
, e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14788 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
14789 CE(swp
, 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
14790 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
14793 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
14794 TCE(mrs
, 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
14795 TCE(msr
, 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
14798 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
14799 TCE(smull
, 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14800 CM(smull
,s
, 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14801 TCE(umull
, 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14802 CM(umull
,s
, 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14803 TCE(smlal
, 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14804 CM(smlal
,s
, 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14805 TCE(umlal
, 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14806 CM(umlal
,s
, 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14809 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
14810 #undef THUMB_VARIANT
14811 #define THUMB_VARIANT &arm_ext_v4t
14812 tC3(ldrh
, 01000b0
, ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14813 tC3(strh
, 00000b0
, strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14814 tC3(ldrsh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14815 tC3(ldrsb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14816 tCM(ld
,sh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14817 tCM(ld
,sb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14820 #define ARM_VARIANT &arm_ext_v4t_5
14821 /* ARM Architecture 4T. */
14822 /* Note: bx (and blx) are required on V5, even if the processor does
14823 not support Thumb. */
14824 TCE(bx
, 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
14827 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
14828 #undef THUMB_VARIANT
14829 #define THUMB_VARIANT &arm_ext_v5t
14830 /* Note: blx has 2 variants; the .value coded here is for
14831 BLX(2). Only this variant has conditional execution. */
14832 TCE(blx
, 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
14833 TUE(bkpt
, 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
14835 #undef THUMB_VARIANT
14836 #define THUMB_VARIANT &arm_ext_v6t2
14837 TCE(clz
, 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
14838 TUF(ldc2
, c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14839 TUF(ldc2l
, c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14840 TUF(stc2
, c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14841 TUF(stc2l
, c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14842 TUF(cdp2
, e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
14843 TUF(mcr2
, e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14844 TUF(mrc2
, e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14847 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
14848 TCE(smlabb
, 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14849 TCE(smlatb
, 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14850 TCE(smlabt
, 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14851 TCE(smlatt
, 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14853 TCE(smlawb
, 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14854 TCE(smlawt
, 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14856 TCE(smlalbb
, 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14857 TCE(smlaltb
, 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14858 TCE(smlalbt
, 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14859 TCE(smlaltt
, 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14861 TCE(smulbb
, 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14862 TCE(smultb
, 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14863 TCE(smulbt
, 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14864 TCE(smultt
, 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14866 TCE(smulwb
, 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14867 TCE(smulwt
, 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14869 TCE(qadd
, 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14870 TCE(qdadd
, 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14871 TCE(qsub
, 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14872 TCE(qdsub
, 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14875 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
14876 TUF(pld
, 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
14877 TC3(ldrd
, 00000d0
, e9500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
14878 TC3(strd
, 00000f0
, e9400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
14880 TCE(mcrr
, c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14881 TCE(mrrc
, c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14884 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
14885 TCE(bxj
, 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
14888 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
14889 #undef THUMB_VARIANT
14890 #define THUMB_VARIANT &arm_ext_v6
14891 TUF(cpsie
, 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
14892 TUF(cpsid
, 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
14893 tCE(rev
, 6bf0f30
, rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
14894 tCE(rev16
, 6bf0fb0
, rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
14895 tCE(revsh
, 6ff0fb0
, revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
14896 tCE(sxth
, 6bf0070
, sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14897 tCE(uxth
, 6ff0070
, uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14898 tCE(sxtb
, 6af0070
, sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14899 tCE(uxtb
, 6ef0070
, uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14900 TUF(setend
, 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
14902 #undef THUMB_VARIANT
14903 #define THUMB_VARIANT &arm_ext_v6t2
14904 TCE(ldrex
, 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
14905 TUF(mcrr2
, c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14906 TUF(mrrc2
, c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14908 TCE(ssat
, 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
14909 TCE(usat
, 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
14911 /* ARM V6 not included in V7M (eg. integer SIMD). */
14912 #undef THUMB_VARIANT
14913 #define THUMB_VARIANT &arm_ext_v6_notm
14914 TUF(cps
, 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
14915 TCE(pkhbt
, 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
14916 TCE(pkhtb
, 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
14917 TCE(qadd16
, 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14918 TCE(qadd8
, 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14919 TCE(qaddsubx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14920 TCE(qsub16
, 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14921 TCE(qsub8
, 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14922 TCE(qsubaddx
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14923 TCE(sadd16
, 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14924 TCE(sadd8
, 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14925 TCE(saddsubx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14926 TCE(shadd16
, 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14927 TCE(shadd8
, 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14928 TCE(shaddsubx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14929 TCE(shsub16
, 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14930 TCE(shsub8
, 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14931 TCE(shsubaddx
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14932 TCE(ssub16
, 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14933 TCE(ssub8
, 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14934 TCE(ssubaddx
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14935 TCE(uadd16
, 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14936 TCE(uadd8
, 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14937 TCE(uaddsubx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14938 TCE(uhadd16
, 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14939 TCE(uhadd8
, 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14940 TCE(uhaddsubx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14941 TCE(uhsub16
, 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14942 TCE(uhsub8
, 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14943 TCE(uhsubaddx
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14944 TCE(uqadd16
, 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14945 TCE(uqadd8
, 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14946 TCE(uqaddsubx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14947 TCE(uqsub16
, 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14948 TCE(uqsub8
, 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14949 TCE(uqsubaddx
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14950 TCE(usub16
, 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14951 TCE(usub8
, 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14952 TCE(usubaddx
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14953 TUF(rfeia
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
14954 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
14955 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
14956 TUF(rfedb
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
14957 TUF(rfefd
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
14958 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
14959 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
14960 TUF(rfeed
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
14961 TCE(sxtah
, 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14962 TCE(sxtab16
, 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14963 TCE(sxtab
, 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14964 TCE(sxtb16
, 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14965 TCE(uxtah
, 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14966 TCE(uxtab16
, 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14967 TCE(uxtab
, 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14968 TCE(uxtb16
, 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14969 TCE(sel
, 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14970 TCE(smlad
, 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14971 TCE(smladx
, 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14972 TCE(smlald
, 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14973 TCE(smlaldx
, 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14974 TCE(smlsd
, 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14975 TCE(smlsdx
, 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14976 TCE(smlsld
, 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14977 TCE(smlsldx
, 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14978 TCE(smmla
, 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14979 TCE(smmlar
, 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14980 TCE(smmls
, 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14981 TCE(smmlsr
, 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14982 TCE(smmul
, 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14983 TCE(smmulr
, 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14984 TCE(smuad
, 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14985 TCE(smuadx
, 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14986 TCE(smusd
, 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14987 TCE(smusdx
, 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14988 TUF(srsia
, 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
14989 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
14990 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
14991 TUF(srsdb
, 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
14992 TCE(ssat16
, 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
14993 TCE(strex
, 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
14994 TCE(umaal
, 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
14995 TCE(usad8
, 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14996 TCE(usada8
, 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14997 TCE(usat16
, 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
15000 #define ARM_VARIANT &arm_ext_v6k
15001 #undef THUMB_VARIANT
15002 #define THUMB_VARIANT &arm_ext_v6k
15003 tCE(yield
, 320f001
, yield
, 0, (), noargs
, t_hint
),
15004 tCE(wfe
, 320f002
, wfe
, 0, (), noargs
, t_hint
),
15005 tCE(wfi
, 320f003
, wfi
, 0, (), noargs
, t_hint
),
15006 tCE(sev
, 320f004
, sev
, 0, (), noargs
, t_hint
),
15008 #undef THUMB_VARIANT
15009 #define THUMB_VARIANT &arm_ext_v6_notm
15010 TCE(ldrexd
, 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
15011 TCE(strexd
, 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
15013 #undef THUMB_VARIANT
15014 #define THUMB_VARIANT &arm_ext_v6t2
15015 TCE(ldrexb
, 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
15016 TCE(ldrexh
, 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
15017 TCE(strexb
, 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
15018 TCE(strexh
, 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
15019 TUF(clrex
, 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
15022 #define ARM_VARIANT &arm_ext_v6z
15023 TCE(smc
, 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
15026 #define ARM_VARIANT &arm_ext_v6t2
15027 TCE(bfc
, 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
15028 TCE(bfi
, 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
15029 TCE(sbfx
, 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
15030 TCE(ubfx
, 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
15032 TCE(mls
, 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
15033 TCE(movw
, 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
15034 TCE(movt
, 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
15035 TCE(rbit
, 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
15037 TC3(ldrht
, 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15038 TC3(ldrsht
, 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15039 TC3(ldrsbt
, 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15040 TC3(strht
, 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15042 UT(cbnz
, b900
, 2, (RR
, EXP
), t_cbz
),
15043 UT(cbz
, b100
, 2, (RR
, EXP
), t_cbz
),
15044 /* ARM does not really have an IT instruction, so always allow it. */
15046 #define ARM_VARIANT &arm_ext_v1
15047 TUE(it
, 0, bf08
, 1, (COND
), it
, t_it
),
15048 TUE(itt
, 0, bf0c
, 1, (COND
), it
, t_it
),
15049 TUE(ite
, 0, bf04
, 1, (COND
), it
, t_it
),
15050 TUE(ittt
, 0, bf0e
, 1, (COND
), it
, t_it
),
15051 TUE(itet
, 0, bf06
, 1, (COND
), it
, t_it
),
15052 TUE(itte
, 0, bf0a
, 1, (COND
), it
, t_it
),
15053 TUE(itee
, 0, bf02
, 1, (COND
), it
, t_it
),
15054 TUE(itttt
, 0, bf0f
, 1, (COND
), it
, t_it
),
15055 TUE(itett
, 0, bf07
, 1, (COND
), it
, t_it
),
15056 TUE(ittet
, 0, bf0b
, 1, (COND
), it
, t_it
),
15057 TUE(iteet
, 0, bf03
, 1, (COND
), it
, t_it
),
15058 TUE(ittte
, 0, bf0d
, 1, (COND
), it
, t_it
),
15059 TUE(itete
, 0, bf05
, 1, (COND
), it
, t_it
),
15060 TUE(ittee
, 0, bf09
, 1, (COND
), it
, t_it
),
15061 TUE(iteee
, 0, bf01
, 1, (COND
), it
, t_it
),
15063 /* Thumb2 only instructions. */
15065 #define ARM_VARIANT NULL
15067 TCE(addw
, 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
15068 TCE(subw
, 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
15069 TCE(tbb
, 0, e8d0f000
, 1, (TB
), 0, t_tb
),
15070 TCE(tbh
, 0, e8d0f010
, 1, (TB
), 0, t_tb
),
15072 /* Thumb-2 hardware division instructions (R and M profiles only). */
15073 #undef THUMB_VARIANT
15074 #define THUMB_VARIANT &arm_ext_div
15075 TCE(sdiv
, 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
15076 TCE(udiv
, 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
15078 /* ARM V7 instructions. */
15080 #define ARM_VARIANT &arm_ext_v7
15081 #undef THUMB_VARIANT
15082 #define THUMB_VARIANT &arm_ext_v7
15083 TUF(pli
, 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
15084 TCE(dbg
, 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
15085 TUF(dmb
, 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
15086 TUF(dsb
, 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
15087 TUF(isb
, 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
15090 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
15091 cCE(wfs
, e200110
, 1, (RR
), rd
),
15092 cCE(rfs
, e300110
, 1, (RR
), rd
),
15093 cCE(wfc
, e400110
, 1, (RR
), rd
),
15094 cCE(rfc
, e500110
, 1, (RR
), rd
),
15096 cCL(ldfs
, c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15097 cCL(ldfd
, c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15098 cCL(ldfe
, c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15099 cCL(ldfp
, c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15101 cCL(stfs
, c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15102 cCL(stfd
, c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15103 cCL(stfe
, c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15104 cCL(stfp
, c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15106 cCL(mvfs
, e008100
, 2, (RF
, RF_IF
), rd_rm
),
15107 cCL(mvfsp
, e008120
, 2, (RF
, RF_IF
), rd_rm
),
15108 cCL(mvfsm
, e008140
, 2, (RF
, RF_IF
), rd_rm
),
15109 cCL(mvfsz
, e008160
, 2, (RF
, RF_IF
), rd_rm
),
15110 cCL(mvfd
, e008180
, 2, (RF
, RF_IF
), rd_rm
),
15111 cCL(mvfdp
, e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
15112 cCL(mvfdm
, e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
15113 cCL(mvfdz
, e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
15114 cCL(mvfe
, e088100
, 2, (RF
, RF_IF
), rd_rm
),
15115 cCL(mvfep
, e088120
, 2, (RF
, RF_IF
), rd_rm
),
15116 cCL(mvfem
, e088140
, 2, (RF
, RF_IF
), rd_rm
),
15117 cCL(mvfez
, e088160
, 2, (RF
, RF_IF
), rd_rm
),
15119 cCL(mnfs
, e108100
, 2, (RF
, RF_IF
), rd_rm
),
15120 cCL(mnfsp
, e108120
, 2, (RF
, RF_IF
), rd_rm
),
15121 cCL(mnfsm
, e108140
, 2, (RF
, RF_IF
), rd_rm
),
15122 cCL(mnfsz
, e108160
, 2, (RF
, RF_IF
), rd_rm
),
15123 cCL(mnfd
, e108180
, 2, (RF
, RF_IF
), rd_rm
),
15124 cCL(mnfdp
, e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
15125 cCL(mnfdm
, e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
15126 cCL(mnfdz
, e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
15127 cCL(mnfe
, e188100
, 2, (RF
, RF_IF
), rd_rm
),
15128 cCL(mnfep
, e188120
, 2, (RF
, RF_IF
), rd_rm
),
15129 cCL(mnfem
, e188140
, 2, (RF
, RF_IF
), rd_rm
),
15130 cCL(mnfez
, e188160
, 2, (RF
, RF_IF
), rd_rm
),
15132 cCL(abss
, e208100
, 2, (RF
, RF_IF
), rd_rm
),
15133 cCL(abssp
, e208120
, 2, (RF
, RF_IF
), rd_rm
),
15134 cCL(abssm
, e208140
, 2, (RF
, RF_IF
), rd_rm
),
15135 cCL(abssz
, e208160
, 2, (RF
, RF_IF
), rd_rm
),
15136 cCL(absd
, e208180
, 2, (RF
, RF_IF
), rd_rm
),
15137 cCL(absdp
, e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
15138 cCL(absdm
, e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
15139 cCL(absdz
, e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
15140 cCL(abse
, e288100
, 2, (RF
, RF_IF
), rd_rm
),
15141 cCL(absep
, e288120
, 2, (RF
, RF_IF
), rd_rm
),
15142 cCL(absem
, e288140
, 2, (RF
, RF_IF
), rd_rm
),
15143 cCL(absez
, e288160
, 2, (RF
, RF_IF
), rd_rm
),
15145 cCL(rnds
, e308100
, 2, (RF
, RF_IF
), rd_rm
),
15146 cCL(rndsp
, e308120
, 2, (RF
, RF_IF
), rd_rm
),
15147 cCL(rndsm
, e308140
, 2, (RF
, RF_IF
), rd_rm
),
15148 cCL(rndsz
, e308160
, 2, (RF
, RF_IF
), rd_rm
),
15149 cCL(rndd
, e308180
, 2, (RF
, RF_IF
), rd_rm
),
15150 cCL(rnddp
, e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
15151 cCL(rnddm
, e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
15152 cCL(rnddz
, e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
15153 cCL(rnde
, e388100
, 2, (RF
, RF_IF
), rd_rm
),
15154 cCL(rndep
, e388120
, 2, (RF
, RF_IF
), rd_rm
),
15155 cCL(rndem
, e388140
, 2, (RF
, RF_IF
), rd_rm
),
15156 cCL(rndez
, e388160
, 2, (RF
, RF_IF
), rd_rm
),
15158 cCL(sqts
, e408100
, 2, (RF
, RF_IF
), rd_rm
),
15159 cCL(sqtsp
, e408120
, 2, (RF
, RF_IF
), rd_rm
),
15160 cCL(sqtsm
, e408140
, 2, (RF
, RF_IF
), rd_rm
),
15161 cCL(sqtsz
, e408160
, 2, (RF
, RF_IF
), rd_rm
),
15162 cCL(sqtd
, e408180
, 2, (RF
, RF_IF
), rd_rm
),
15163 cCL(sqtdp
, e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
15164 cCL(sqtdm
, e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
15165 cCL(sqtdz
, e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
15166 cCL(sqte
, e488100
, 2, (RF
, RF_IF
), rd_rm
),
15167 cCL(sqtep
, e488120
, 2, (RF
, RF_IF
), rd_rm
),
15168 cCL(sqtem
, e488140
, 2, (RF
, RF_IF
), rd_rm
),
15169 cCL(sqtez
, e488160
, 2, (RF
, RF_IF
), rd_rm
),
15171 cCL(logs
, e508100
, 2, (RF
, RF_IF
), rd_rm
),
15172 cCL(logsp
, e508120
, 2, (RF
, RF_IF
), rd_rm
),
15173 cCL(logsm
, e508140
, 2, (RF
, RF_IF
), rd_rm
),
15174 cCL(logsz
, e508160
, 2, (RF
, RF_IF
), rd_rm
),
15175 cCL(logd
, e508180
, 2, (RF
, RF_IF
), rd_rm
),
15176 cCL(logdp
, e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
15177 cCL(logdm
, e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
15178 cCL(logdz
, e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
15179 cCL(loge
, e588100
, 2, (RF
, RF_IF
), rd_rm
),
15180 cCL(logep
, e588120
, 2, (RF
, RF_IF
), rd_rm
),
15181 cCL(logem
, e588140
, 2, (RF
, RF_IF
), rd_rm
),
15182 cCL(logez
, e588160
, 2, (RF
, RF_IF
), rd_rm
),
15184 cCL(lgns
, e608100
, 2, (RF
, RF_IF
), rd_rm
),
15185 cCL(lgnsp
, e608120
, 2, (RF
, RF_IF
), rd_rm
),
15186 cCL(lgnsm
, e608140
, 2, (RF
, RF_IF
), rd_rm
),
15187 cCL(lgnsz
, e608160
, 2, (RF
, RF_IF
), rd_rm
),
15188 cCL(lgnd
, e608180
, 2, (RF
, RF_IF
), rd_rm
),
15189 cCL(lgndp
, e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
15190 cCL(lgndm
, e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
15191 cCL(lgndz
, e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
15192 cCL(lgne
, e688100
, 2, (RF
, RF_IF
), rd_rm
),
15193 cCL(lgnep
, e688120
, 2, (RF
, RF_IF
), rd_rm
),
15194 cCL(lgnem
, e688140
, 2, (RF
, RF_IF
), rd_rm
),
15195 cCL(lgnez
, e688160
, 2, (RF
, RF_IF
), rd_rm
),
15197 cCL(exps
, e708100
, 2, (RF
, RF_IF
), rd_rm
),
15198 cCL(expsp
, e708120
, 2, (RF
, RF_IF
), rd_rm
),
15199 cCL(expsm
, e708140
, 2, (RF
, RF_IF
), rd_rm
),
15200 cCL(expsz
, e708160
, 2, (RF
, RF_IF
), rd_rm
),
15201 cCL(expd
, e708180
, 2, (RF
, RF_IF
), rd_rm
),
15202 cCL(expdp
, e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
15203 cCL(expdm
, e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
15204 cCL(expdz
, e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
15205 cCL(expe
, e788100
, 2, (RF
, RF_IF
), rd_rm
),
15206 cCL(expep
, e788120
, 2, (RF
, RF_IF
), rd_rm
),
15207 cCL(expem
, e788140
, 2, (RF
, RF_IF
), rd_rm
),
15208 cCL(expdz
, e788160
, 2, (RF
, RF_IF
), rd_rm
),
15210 cCL(sins
, e808100
, 2, (RF
, RF_IF
), rd_rm
),
15211 cCL(sinsp
, e808120
, 2, (RF
, RF_IF
), rd_rm
),
15212 cCL(sinsm
, e808140
, 2, (RF
, RF_IF
), rd_rm
),
15213 cCL(sinsz
, e808160
, 2, (RF
, RF_IF
), rd_rm
),
15214 cCL(sind
, e808180
, 2, (RF
, RF_IF
), rd_rm
),
15215 cCL(sindp
, e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
15216 cCL(sindm
, e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
15217 cCL(sindz
, e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
15218 cCL(sine
, e888100
, 2, (RF
, RF_IF
), rd_rm
),
15219 cCL(sinep
, e888120
, 2, (RF
, RF_IF
), rd_rm
),
15220 cCL(sinem
, e888140
, 2, (RF
, RF_IF
), rd_rm
),
15221 cCL(sinez
, e888160
, 2, (RF
, RF_IF
), rd_rm
),
15223 cCL(coss
, e908100
, 2, (RF
, RF_IF
), rd_rm
),
15224 cCL(cossp
, e908120
, 2, (RF
, RF_IF
), rd_rm
),
15225 cCL(cossm
, e908140
, 2, (RF
, RF_IF
), rd_rm
),
15226 cCL(cossz
, e908160
, 2, (RF
, RF_IF
), rd_rm
),
15227 cCL(cosd
, e908180
, 2, (RF
, RF_IF
), rd_rm
),
15228 cCL(cosdp
, e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
15229 cCL(cosdm
, e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
15230 cCL(cosdz
, e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
15231 cCL(cose
, e988100
, 2, (RF
, RF_IF
), rd_rm
),
15232 cCL(cosep
, e988120
, 2, (RF
, RF_IF
), rd_rm
),
15233 cCL(cosem
, e988140
, 2, (RF
, RF_IF
), rd_rm
),
15234 cCL(cosez
, e988160
, 2, (RF
, RF_IF
), rd_rm
),
15236 cCL(tans
, ea08100
, 2, (RF
, RF_IF
), rd_rm
),
15237 cCL(tansp
, ea08120
, 2, (RF
, RF_IF
), rd_rm
),
15238 cCL(tansm
, ea08140
, 2, (RF
, RF_IF
), rd_rm
),
15239 cCL(tansz
, ea08160
, 2, (RF
, RF_IF
), rd_rm
),
15240 cCL(tand
, ea08180
, 2, (RF
, RF_IF
), rd_rm
),
15241 cCL(tandp
, ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
15242 cCL(tandm
, ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
15243 cCL(tandz
, ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
15244 cCL(tane
, ea88100
, 2, (RF
, RF_IF
), rd_rm
),
15245 cCL(tanep
, ea88120
, 2, (RF
, RF_IF
), rd_rm
),
15246 cCL(tanem
, ea88140
, 2, (RF
, RF_IF
), rd_rm
),
15247 cCL(tanez
, ea88160
, 2, (RF
, RF_IF
), rd_rm
),
15249 cCL(asns
, eb08100
, 2, (RF
, RF_IF
), rd_rm
),
15250 cCL(asnsp
, eb08120
, 2, (RF
, RF_IF
), rd_rm
),
15251 cCL(asnsm
, eb08140
, 2, (RF
, RF_IF
), rd_rm
),
15252 cCL(asnsz
, eb08160
, 2, (RF
, RF_IF
), rd_rm
),
15253 cCL(asnd
, eb08180
, 2, (RF
, RF_IF
), rd_rm
),
15254 cCL(asndp
, eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
15255 cCL(asndm
, eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
15256 cCL(asndz
, eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
15257 cCL(asne
, eb88100
, 2, (RF
, RF_IF
), rd_rm
),
15258 cCL(asnep
, eb88120
, 2, (RF
, RF_IF
), rd_rm
),
15259 cCL(asnem
, eb88140
, 2, (RF
, RF_IF
), rd_rm
),
15260 cCL(asnez
, eb88160
, 2, (RF
, RF_IF
), rd_rm
),
15262 cCL(acss
, ec08100
, 2, (RF
, RF_IF
), rd_rm
),
15263 cCL(acssp
, ec08120
, 2, (RF
, RF_IF
), rd_rm
),
15264 cCL(acssm
, ec08140
, 2, (RF
, RF_IF
), rd_rm
),
15265 cCL(acssz
, ec08160
, 2, (RF
, RF_IF
), rd_rm
),
15266 cCL(acsd
, ec08180
, 2, (RF
, RF_IF
), rd_rm
),
15267 cCL(acsdp
, ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
15268 cCL(acsdm
, ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
15269 cCL(acsdz
, ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
15270 cCL(acse
, ec88100
, 2, (RF
, RF_IF
), rd_rm
),
15271 cCL(acsep
, ec88120
, 2, (RF
, RF_IF
), rd_rm
),
15272 cCL(acsem
, ec88140
, 2, (RF
, RF_IF
), rd_rm
),
15273 cCL(acsez
, ec88160
, 2, (RF
, RF_IF
), rd_rm
),
15275 cCL(atns
, ed08100
, 2, (RF
, RF_IF
), rd_rm
),
15276 cCL(atnsp
, ed08120
, 2, (RF
, RF_IF
), rd_rm
),
15277 cCL(atnsm
, ed08140
, 2, (RF
, RF_IF
), rd_rm
),
15278 cCL(atnsz
, ed08160
, 2, (RF
, RF_IF
), rd_rm
),
15279 cCL(atnd
, ed08180
, 2, (RF
, RF_IF
), rd_rm
),
15280 cCL(atndp
, ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
15281 cCL(atndm
, ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
15282 cCL(atndz
, ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
15283 cCL(atne
, ed88100
, 2, (RF
, RF_IF
), rd_rm
),
15284 cCL(atnep
, ed88120
, 2, (RF
, RF_IF
), rd_rm
),
15285 cCL(atnem
, ed88140
, 2, (RF
, RF_IF
), rd_rm
),
15286 cCL(atnez
, ed88160
, 2, (RF
, RF_IF
), rd_rm
),
15288 cCL(urds
, ee08100
, 2, (RF
, RF_IF
), rd_rm
),
15289 cCL(urdsp
, ee08120
, 2, (RF
, RF_IF
), rd_rm
),
15290 cCL(urdsm
, ee08140
, 2, (RF
, RF_IF
), rd_rm
),
15291 cCL(urdsz
, ee08160
, 2, (RF
, RF_IF
), rd_rm
),
15292 cCL(urdd
, ee08180
, 2, (RF
, RF_IF
), rd_rm
),
15293 cCL(urddp
, ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
15294 cCL(urddm
, ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
15295 cCL(urddz
, ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
15296 cCL(urde
, ee88100
, 2, (RF
, RF_IF
), rd_rm
),
15297 cCL(urdep
, ee88120
, 2, (RF
, RF_IF
), rd_rm
),
15298 cCL(urdem
, ee88140
, 2, (RF
, RF_IF
), rd_rm
),
15299 cCL(urdez
, ee88160
, 2, (RF
, RF_IF
), rd_rm
),
15301 cCL(nrms
, ef08100
, 2, (RF
, RF_IF
), rd_rm
),
15302 cCL(nrmsp
, ef08120
, 2, (RF
, RF_IF
), rd_rm
),
15303 cCL(nrmsm
, ef08140
, 2, (RF
, RF_IF
), rd_rm
),
15304 cCL(nrmsz
, ef08160
, 2, (RF
, RF_IF
), rd_rm
),
15305 cCL(nrmd
, ef08180
, 2, (RF
, RF_IF
), rd_rm
),
15306 cCL(nrmdp
, ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
15307 cCL(nrmdm
, ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
15308 cCL(nrmdz
, ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
15309 cCL(nrme
, ef88100
, 2, (RF
, RF_IF
), rd_rm
),
15310 cCL(nrmep
, ef88120
, 2, (RF
, RF_IF
), rd_rm
),
15311 cCL(nrmem
, ef88140
, 2, (RF
, RF_IF
), rd_rm
),
15312 cCL(nrmez
, ef88160
, 2, (RF
, RF_IF
), rd_rm
),
15314 cCL(adfs
, e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15315 cCL(adfsp
, e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15316 cCL(adfsm
, e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15317 cCL(adfsz
, e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15318 cCL(adfd
, e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15319 cCL(adfdp
, e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15320 cCL(adfdm
, e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15321 cCL(adfdz
, e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15322 cCL(adfe
, e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15323 cCL(adfep
, e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15324 cCL(adfem
, e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15325 cCL(adfez
, e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15327 cCL(sufs
, e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15328 cCL(sufsp
, e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15329 cCL(sufsm
, e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15330 cCL(sufsz
, e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15331 cCL(sufd
, e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15332 cCL(sufdp
, e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15333 cCL(sufdm
, e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15334 cCL(sufdz
, e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15335 cCL(sufe
, e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15336 cCL(sufep
, e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15337 cCL(sufem
, e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15338 cCL(sufez
, e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15340 cCL(rsfs
, e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15341 cCL(rsfsp
, e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15342 cCL(rsfsm
, e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15343 cCL(rsfsz
, e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15344 cCL(rsfd
, e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15345 cCL(rsfdp
, e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15346 cCL(rsfdm
, e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15347 cCL(rsfdz
, e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15348 cCL(rsfe
, e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15349 cCL(rsfep
, e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15350 cCL(rsfem
, e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15351 cCL(rsfez
, e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15353 cCL(mufs
, e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15354 cCL(mufsp
, e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15355 cCL(mufsm
, e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15356 cCL(mufsz
, e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15357 cCL(mufd
, e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15358 cCL(mufdp
, e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15359 cCL(mufdm
, e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15360 cCL(mufdz
, e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15361 cCL(mufe
, e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15362 cCL(mufep
, e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15363 cCL(mufem
, e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15364 cCL(mufez
, e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15366 cCL(dvfs
, e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15367 cCL(dvfsp
, e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15368 cCL(dvfsm
, e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15369 cCL(dvfsz
, e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15370 cCL(dvfd
, e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15371 cCL(dvfdp
, e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15372 cCL(dvfdm
, e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15373 cCL(dvfdz
, e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15374 cCL(dvfe
, e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15375 cCL(dvfep
, e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15376 cCL(dvfem
, e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15377 cCL(dvfez
, e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15379 cCL(rdfs
, e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15380 cCL(rdfsp
, e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15381 cCL(rdfsm
, e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15382 cCL(rdfsz
, e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15383 cCL(rdfd
, e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15384 cCL(rdfdp
, e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15385 cCL(rdfdm
, e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15386 cCL(rdfdz
, e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15387 cCL(rdfe
, e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15388 cCL(rdfep
, e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15389 cCL(rdfem
, e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15390 cCL(rdfez
, e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15392 cCL(pows
, e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15393 cCL(powsp
, e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15394 cCL(powsm
, e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15395 cCL(powsz
, e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15396 cCL(powd
, e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15397 cCL(powdp
, e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15398 cCL(powdm
, e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15399 cCL(powdz
, e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15400 cCL(powe
, e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15401 cCL(powep
, e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15402 cCL(powem
, e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15403 cCL(powez
, e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15405 cCL(rpws
, e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15406 cCL(rpwsp
, e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15407 cCL(rpwsm
, e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15408 cCL(rpwsz
, e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15409 cCL(rpwd
, e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15410 cCL(rpwdp
, e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15411 cCL(rpwdm
, e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15412 cCL(rpwdz
, e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15413 cCL(rpwe
, e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15414 cCL(rpwep
, e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15415 cCL(rpwem
, e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15416 cCL(rpwez
, e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15418 cCL(rmfs
, e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15419 cCL(rmfsp
, e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15420 cCL(rmfsm
, e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15421 cCL(rmfsz
, e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15422 cCL(rmfd
, e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15423 cCL(rmfdp
, e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15424 cCL(rmfdm
, e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15425 cCL(rmfdz
, e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15426 cCL(rmfe
, e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15427 cCL(rmfep
, e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15428 cCL(rmfem
, e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15429 cCL(rmfez
, e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15431 cCL(fmls
, e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15432 cCL(fmlsp
, e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15433 cCL(fmlsm
, e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15434 cCL(fmlsz
, e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15435 cCL(fmld
, e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15436 cCL(fmldp
, e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15437 cCL(fmldm
, e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15438 cCL(fmldz
, e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15439 cCL(fmle
, e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15440 cCL(fmlep
, e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15441 cCL(fmlem
, e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15442 cCL(fmlez
, e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15444 cCL(fdvs
, ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15445 cCL(fdvsp
, ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15446 cCL(fdvsm
, ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15447 cCL(fdvsz
, ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15448 cCL(fdvd
, ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15449 cCL(fdvdp
, ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15450 cCL(fdvdm
, ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15451 cCL(fdvdz
, ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15452 cCL(fdve
, ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15453 cCL(fdvep
, ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15454 cCL(fdvem
, ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15455 cCL(fdvez
, ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15457 cCL(frds
, eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15458 cCL(frdsp
, eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15459 cCL(frdsm
, eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15460 cCL(frdsz
, eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15461 cCL(frdd
, eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15462 cCL(frddp
, eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15463 cCL(frddm
, eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15464 cCL(frddz
, eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15465 cCL(frde
, eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15466 cCL(frdep
, eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15467 cCL(frdem
, eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15468 cCL(frdez
, eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15470 cCL(pols
, ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15471 cCL(polsp
, ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15472 cCL(polsm
, ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15473 cCL(polsz
, ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15474 cCL(pold
, ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15475 cCL(poldp
, ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15476 cCL(poldm
, ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15477 cCL(poldz
, ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15478 cCL(pole
, ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15479 cCL(polep
, ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15480 cCL(polem
, ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15481 cCL(polez
, ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15483 cCE(cmf
, e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15484 C3E(cmfe
, ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15485 cCE(cnf
, eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15486 C3E(cnfe
, ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15488 cCL(flts
, e000110
, 2, (RF
, RR
), rn_rd
),
15489 cCL(fltsp
, e000130
, 2, (RF
, RR
), rn_rd
),
15490 cCL(fltsm
, e000150
, 2, (RF
, RR
), rn_rd
),
15491 cCL(fltsz
, e000170
, 2, (RF
, RR
), rn_rd
),
15492 cCL(fltd
, e000190
, 2, (RF
, RR
), rn_rd
),
15493 cCL(fltdp
, e0001b0
, 2, (RF
, RR
), rn_rd
),
15494 cCL(fltdm
, e0001d0
, 2, (RF
, RR
), rn_rd
),
15495 cCL(fltdz
, e0001f0
, 2, (RF
, RR
), rn_rd
),
15496 cCL(flte
, e080110
, 2, (RF
, RR
), rn_rd
),
15497 cCL(fltep
, e080130
, 2, (RF
, RR
), rn_rd
),
15498 cCL(fltem
, e080150
, 2, (RF
, RR
), rn_rd
),
15499 cCL(fltez
, e080170
, 2, (RF
, RR
), rn_rd
),
15501 /* The implementation of the FIX instruction is broken on some
15502 assemblers, in that it accepts a precision specifier as well as a
15503 rounding specifier, despite the fact that this is meaningless.
15504 To be more compatible, we accept it as well, though of course it
15505 does not set any bits. */
15506 cCE(fix
, e100110
, 2, (RR
, RF
), rd_rm
),
15507 cCL(fixp
, e100130
, 2, (RR
, RF
), rd_rm
),
15508 cCL(fixm
, e100150
, 2, (RR
, RF
), rd_rm
),
15509 cCL(fixz
, e100170
, 2, (RR
, RF
), rd_rm
),
15510 cCL(fixsp
, e100130
, 2, (RR
, RF
), rd_rm
),
15511 cCL(fixsm
, e100150
, 2, (RR
, RF
), rd_rm
),
15512 cCL(fixsz
, e100170
, 2, (RR
, RF
), rd_rm
),
15513 cCL(fixdp
, e100130
, 2, (RR
, RF
), rd_rm
),
15514 cCL(fixdm
, e100150
, 2, (RR
, RF
), rd_rm
),
15515 cCL(fixdz
, e100170
, 2, (RR
, RF
), rd_rm
),
15516 cCL(fixep
, e100130
, 2, (RR
, RF
), rd_rm
),
15517 cCL(fixem
, e100150
, 2, (RR
, RF
), rd_rm
),
15518 cCL(fixez
, e100170
, 2, (RR
, RF
), rd_rm
),
15520 /* Instructions that were new with the real FPA, call them V2. */
15522 #define ARM_VARIANT &fpu_fpa_ext_v2
15523 cCE(lfm
, c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15524 cCL(lfmfd
, c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15525 cCL(lfmea
, d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15526 cCE(sfm
, c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15527 cCL(sfmfd
, d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15528 cCL(sfmea
, c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15531 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
15532 /* Moves and type conversions. */
15533 cCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15534 cCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
15535 cCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
15536 cCE(fmstat
, ef1fa10
, 0, (), noargs
),
15537 cCE(fsitos
, eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15538 cCE(fuitos
, eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15539 cCE(ftosis
, ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15540 cCE(ftosizs
, ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15541 cCE(ftouis
, ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15542 cCE(ftouizs
, ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15543 cCE(fmrx
, ef00a10
, 2, (RR
, RVC
), rd_rn
),
15544 cCE(fmxr
, ee00a10
, 2, (RVC
, RR
), rn_rd
),
15546 /* Memory operations. */
15547 cCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15548 cCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15549 cCE(fldmias
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15550 cCE(fldmfds
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15551 cCE(fldmdbs
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15552 cCE(fldmeas
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15553 cCE(fldmiax
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15554 cCE(fldmfdx
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15555 cCE(fldmdbx
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15556 cCE(fldmeax
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15557 cCE(fstmias
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15558 cCE(fstmeas
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15559 cCE(fstmdbs
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15560 cCE(fstmfds
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15561 cCE(fstmiax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15562 cCE(fstmeax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15563 cCE(fstmdbx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15564 cCE(fstmfdx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15566 /* Monadic operations. */
15567 cCE(fabss
, eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15568 cCE(fnegs
, eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15569 cCE(fsqrts
, eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15571 /* Dyadic operations. */
15572 cCE(fadds
, e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15573 cCE(fsubs
, e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15574 cCE(fmuls
, e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15575 cCE(fdivs
, e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15576 cCE(fmacs
, e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15577 cCE(fmscs
, e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15578 cCE(fnmuls
, e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15579 cCE(fnmacs
, e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15580 cCE(fnmscs
, e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15583 cCE(fcmps
, eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15584 cCE(fcmpzs
, eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
15585 cCE(fcmpes
, eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15586 cCE(fcmpezs
, eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
15589 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
15590 /* Moves and type conversions. */
15591 cCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15592 cCE(fcvtds
, eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15593 cCE(fcvtsd
, eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15594 cCE(fmdhr
, e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15595 cCE(fmdlr
, e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15596 cCE(fmrdh
, e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15597 cCE(fmrdl
, e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15598 cCE(fsitod
, eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15599 cCE(fuitod
, eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15600 cCE(ftosid
, ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15601 cCE(ftosizd
, ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15602 cCE(ftouid
, ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15603 cCE(ftouizd
, ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15605 /* Memory operations. */
15606 cCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15607 cCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15608 cCE(fldmiad
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15609 cCE(fldmfdd
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15610 cCE(fldmdbd
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15611 cCE(fldmead
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15612 cCE(fstmiad
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15613 cCE(fstmead
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15614 cCE(fstmdbd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15615 cCE(fstmfdd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15617 /* Monadic operations. */
15618 cCE(fabsd
, eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15619 cCE(fnegd
, eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15620 cCE(fsqrtd
, eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15622 /* Dyadic operations. */
15623 cCE(faddd
, e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15624 cCE(fsubd
, e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15625 cCE(fmuld
, e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15626 cCE(fdivd
, e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15627 cCE(fmacd
, e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15628 cCE(fmscd
, e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15629 cCE(fnmuld
, e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15630 cCE(fnmacd
, e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15631 cCE(fnmscd
, e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15634 cCE(fcmpd
, eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15635 cCE(fcmpzd
, eb50b40
, 1, (RVD
), vfp_dp_rd
),
15636 cCE(fcmped
, eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15637 cCE(fcmpezd
, eb50bc0
, 1, (RVD
), vfp_dp_rd
),
15640 #define ARM_VARIANT &fpu_vfp_ext_v2
15641 cCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
15642 cCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
15643 cCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
15644 cCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
15646 /* Instructions which may belong to either the Neon or VFP instruction sets.
15647 Individual encoder functions perform additional architecture checks. */
15649 #define ARM_VARIANT &fpu_vfp_ext_v1xd
15650 #undef THUMB_VARIANT
15651 #define THUMB_VARIANT &fpu_vfp_ext_v1xd
15652 /* These mnemonics are unique to VFP. */
15653 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
15654 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
15655 nCE(vnmul
, vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15656 nCE(vnmla
, vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15657 nCE(vnmls
, vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15658 nCE(vcmp
, vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15659 nCE(vcmpe
, vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15660 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
15661 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
15662 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
15664 /* Mnemonics shared by Neon and VFP. */
15665 nCEF(vmul
, vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
15666 nCEF(vmla
, vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15667 nCEF(vmls
, vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15669 nCEF(vadd
, vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15670 nCEF(vsub
, vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15672 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15673 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15675 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15676 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15677 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15678 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15679 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15680 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15681 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15682 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15684 nCEF(vcvt
, vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
15686 /* NOTE: All VMOV encoding is special-cased! */
15687 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
15688 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
15690 #undef THUMB_VARIANT
15691 #define THUMB_VARIANT &fpu_neon_ext_v1
15693 #define ARM_VARIANT &fpu_neon_ext_v1
15694 /* Data processing with three registers of the same length. */
15695 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
15696 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
15697 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
15698 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15699 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15700 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15701 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15702 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15703 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15704 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
15705 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15706 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15707 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15708 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15709 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
15710 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
15711 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
15712 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
15713 /* If not immediate, fall back to neon_dyadic_i64_su.
15714 shl_imm should accept I8 I16 I32 I64,
15715 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
15716 nUF(vshl
, vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
15717 nUF(vshlq
, vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
15718 nUF(vqshl
, vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
15719 nUF(vqshlq
, vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
15720 /* Logic ops, types optional & ignored. */
15721 nUF(vand
, vand
, 2, (RNDQ
, NILO
), neon_logic
),
15722 nUF(vandq
, vand
, 2, (RNQ
, NILO
), neon_logic
),
15723 nUF(vbic
, vbic
, 2, (RNDQ
, NILO
), neon_logic
),
15724 nUF(vbicq
, vbic
, 2, (RNQ
, NILO
), neon_logic
),
15725 nUF(vorr
, vorr
, 2, (RNDQ
, NILO
), neon_logic
),
15726 nUF(vorrq
, vorr
, 2, (RNQ
, NILO
), neon_logic
),
15727 nUF(vorn
, vorn
, 2, (RNDQ
, NILO
), neon_logic
),
15728 nUF(vornq
, vorn
, 2, (RNQ
, NILO
), neon_logic
),
15729 nUF(veor
, veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
15730 nUF(veorq
, veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
15731 /* Bitfield ops, untyped. */
15732 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15733 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15734 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15735 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15736 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15737 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15738 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
15739 nUF(vabd
, vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15740 nUF(vabdq
, vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15741 nUF(vmax
, vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15742 nUF(vmaxq
, vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15743 nUF(vmin
, vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15744 nUF(vminq
, vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15745 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
15746 back to neon_dyadic_if_su. */
15747 nUF(vcge
, vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
15748 nUF(vcgeq
, vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
15749 nUF(vcgt
, vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
15750 nUF(vcgtq
, vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
15751 nUF(vclt
, vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
15752 nUF(vcltq
, vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
15753 nUF(vcle
, vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
15754 nUF(vcleq
, vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
15755 /* Comparison. Type I8 I16 I32 F32. */
15756 nUF(vceq
, vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
15757 nUF(vceqq
, vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
15758 /* As above, D registers only. */
15759 nUF(vpmax
, vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
15760 nUF(vpmin
, vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
15761 /* Int and float variants, signedness unimportant. */
15762 nUF(vmlaq
, vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
15763 nUF(vmlsq
, vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
15764 nUF(vpadd
, vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
15765 /* Add/sub take types I8 I16 I32 I64 F32. */
15766 nUF(vaddq
, vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
15767 nUF(vsubq
, vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
15768 /* vtst takes sizes 8, 16, 32. */
15769 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
15770 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
15771 /* VMUL takes I8 I16 I32 F32 P8. */
15772 nUF(vmulq
, vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
15773 /* VQD{R}MULH takes S16 S32. */
15774 nUF(vqdmulh
, vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
15775 nUF(vqdmulhq
, vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
15776 nUF(vqrdmulh
, vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
15777 nUF(vqrdmulhq
, vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
15778 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
15779 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
15780 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
15781 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
15782 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
15783 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
15784 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
15785 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
15786 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
15787 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
15788 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
15789 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
15791 /* Two address, int/float. Types S8 S16 S32 F32. */
15792 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
15793 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
15795 /* Data processing with two registers and a shift amount. */
15796 /* Right shifts, and variants with rounding.
15797 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
15798 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
15799 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
15800 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
15801 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
15802 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
15803 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
15804 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
15805 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
15806 /* Shift and insert. Sizes accepted 8 16 32 64. */
15807 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
15808 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
15809 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
15810 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
15811 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
15812 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
15813 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
15814 /* Right shift immediate, saturating & narrowing, with rounding variants.
15815 Types accepted S16 S32 S64 U16 U32 U64. */
15816 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
15817 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
15818 /* As above, unsigned. Types accepted S16 S32 S64. */
15819 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
15820 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
15821 /* Right shift narrowing. Types accepted I16 I32 I64. */
15822 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
15823 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
15824 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
15825 nUF(vshll
, vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
15826 /* CVT with optional immediate for fixed-point variant. */
15827 nUF(vcvtq
, vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
15829 nUF(vmvn
, vmvn
, 2, (RNDQ
, RNDQ_IMVNb
), neon_mvn
),
15830 nUF(vmvnq
, vmvn
, 2, (RNQ
, RNDQ_IMVNb
), neon_mvn
),
15832 /* Data processing, three registers of different lengths. */
15833 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
15834 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
15835 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
15836 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
15837 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
15838 /* If not scalar, fall back to neon_dyadic_long.
15839 Vector types as above, scalar types S16 S32 U16 U32. */
15840 nUF(vmlal
, vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
15841 nUF(vmlsl
, vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
15842 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
15843 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
15844 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
15845 /* Dyadic, narrowing insns. Types I16 I32 I64. */
15846 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15847 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15848 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15849 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15850 /* Saturating doubling multiplies. Types S16 S32. */
15851 nUF(vqdmlal
, vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
15852 nUF(vqdmlsl
, vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
15853 nUF(vqdmull
, vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
15854 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
15855 S16 S32 U16 U32. */
15856 nUF(vmull
, vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
15858 /* Extract. Size 8. */
15859 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I7
), neon_ext
),
15860 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I7
), neon_ext
),
15862 /* Two registers, miscellaneous. */
15863 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
15864 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
15865 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
15866 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
15867 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
15868 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
15869 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
15870 /* Vector replicate. Sizes 8 16 32. */
15871 nCE(vdup
, vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
15872 nCE(vdupq
, vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
15873 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
15874 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
15875 /* VMOVN. Types I16 I32 I64. */
15876 nUF(vmovn
, vmovn
, 2, (RND
, RNQ
), neon_movn
),
15877 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
15878 nUF(vqmovn
, vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
15879 /* VQMOVUN. Types S16 S32 S64. */
15880 nUF(vqmovun
, vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
15881 /* VZIP / VUZP. Sizes 8 16 32. */
15882 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
15883 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
15884 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
15885 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
15886 /* VQABS / VQNEG. Types S8 S16 S32. */
15887 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
15888 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
15889 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
15890 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
15891 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
15892 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
15893 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
15894 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
15895 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
15896 /* Reciprocal estimates. Types U32 F32. */
15897 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
15898 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
15899 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
15900 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
15901 /* VCLS. Types S8 S16 S32. */
15902 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
15903 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
15904 /* VCLZ. Types I8 I16 I32. */
15905 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
15906 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
15907 /* VCNT. Size 8. */
15908 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
15909 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
15910 /* Two address, untyped. */
15911 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
15912 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
15913 /* VTRN. Sizes 8 16 32. */
15914 nUF(vtrn
, vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
15915 nUF(vtrnq
, vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
15917 /* Table lookup. Size 8. */
15918 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
15919 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
15921 #undef THUMB_VARIANT
15922 #define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
15924 #define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
15925 /* Neon element/structure load/store. */
15926 nUF(vld1
, vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15927 nUF(vst1
, vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15928 nUF(vld2
, vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15929 nUF(vst2
, vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15930 nUF(vld3
, vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15931 nUF(vst3
, vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15932 nUF(vld4
, vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15933 nUF(vst4
, vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15935 #undef THUMB_VARIANT
15936 #define THUMB_VARIANT &fpu_vfp_ext_v3
15938 #define ARM_VARIANT &fpu_vfp_ext_v3
15939 cCE(fconsts
, eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
15940 cCE(fconstd
, eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
15941 cCE(fshtos
, eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15942 cCE(fshtod
, eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15943 cCE(fsltos
, eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15944 cCE(fsltod
, eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15945 cCE(fuhtos
, ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15946 cCE(fuhtod
, ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15947 cCE(fultos
, ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15948 cCE(fultod
, ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15949 cCE(ftoshs
, ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15950 cCE(ftoshd
, ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15951 cCE(ftosls
, ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15952 cCE(ftosld
, ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15953 cCE(ftouhs
, ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15954 cCE(ftouhd
, ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15955 cCE(ftouls
, ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15956 cCE(ftould
, ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15958 #undef THUMB_VARIANT
15960 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
15961 cCE(mia
, e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15962 cCE(miaph
, e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15963 cCE(miabb
, e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15964 cCE(miabt
, e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15965 cCE(miatb
, e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15966 cCE(miatt
, e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15967 cCE(mar
, c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
15968 cCE(mra
, c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
15971 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
15972 cCE(tandcb
, e13f130
, 1, (RR
), iwmmxt_tandorc
),
15973 cCE(tandch
, e53f130
, 1, (RR
), iwmmxt_tandorc
),
15974 cCE(tandcw
, e93f130
, 1, (RR
), iwmmxt_tandorc
),
15975 cCE(tbcstb
, e400010
, 2, (RIWR
, RR
), rn_rd
),
15976 cCE(tbcsth
, e400050
, 2, (RIWR
, RR
), rn_rd
),
15977 cCE(tbcstw
, e400090
, 2, (RIWR
, RR
), rn_rd
),
15978 cCE(textrcb
, e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
15979 cCE(textrch
, e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
15980 cCE(textrcw
, e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
15981 cCE(textrmub
, e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15982 cCE(textrmuh
, e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15983 cCE(textrmuw
, e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15984 cCE(textrmsb
, e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15985 cCE(textrmsh
, e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15986 cCE(textrmsw
, e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15987 cCE(tinsrb
, e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
15988 cCE(tinsrh
, e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
15989 cCE(tinsrw
, e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
15990 cCE(tmcr
, e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
15991 cCE(tmcrr
, c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
15992 cCE(tmia
, e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15993 cCE(tmiaph
, e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15994 cCE(tmiabb
, e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15995 cCE(tmiabt
, e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15996 cCE(tmiatb
, e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15997 cCE(tmiatt
, e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15998 cCE(tmovmskb
, e100030
, 2, (RR
, RIWR
), rd_rn
),
15999 cCE(tmovmskh
, e500030
, 2, (RR
, RIWR
), rd_rn
),
16000 cCE(tmovmskw
, e900030
, 2, (RR
, RIWR
), rd_rn
),
16001 cCE(tmrc
, e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
16002 cCE(tmrrc
, c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
16003 cCE(torcb
, e13f150
, 1, (RR
), iwmmxt_tandorc
),
16004 cCE(torch
, e53f150
, 1, (RR
), iwmmxt_tandorc
),
16005 cCE(torcw
, e93f150
, 1, (RR
), iwmmxt_tandorc
),
16006 cCE(waccb
, e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16007 cCE(wacch
, e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16008 cCE(waccw
, e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16009 cCE(waddbss
, e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16010 cCE(waddb
, e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16011 cCE(waddbus
, e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16012 cCE(waddhss
, e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16013 cCE(waddh
, e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16014 cCE(waddhus
, e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16015 cCE(waddwss
, eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16016 cCE(waddw
, e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16017 cCE(waddwus
, e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16018 cCE(waligni
, e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
16019 cCE(walignr0
, e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16020 cCE(walignr1
, e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16021 cCE(walignr2
, ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16022 cCE(walignr3
, eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16023 cCE(wand
, e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16024 cCE(wandn
, e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16025 cCE(wavg2b
, e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16026 cCE(wavg2br
, e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16027 cCE(wavg2h
, ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16028 cCE(wavg2hr
, ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16029 cCE(wcmpeqb
, e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16030 cCE(wcmpeqh
, e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16031 cCE(wcmpeqw
, e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16032 cCE(wcmpgtub
, e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16033 cCE(wcmpgtuh
, e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16034 cCE(wcmpgtuw
, e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16035 cCE(wcmpgtsb
, e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16036 cCE(wcmpgtsh
, e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16037 cCE(wcmpgtsw
, eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16038 cCE(wldrb
, c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16039 cCE(wldrh
, c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16040 cCE(wldrw
, c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
16041 cCE(wldrd
, c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
16042 cCE(wmacs
, e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16043 cCE(wmacsz
, e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16044 cCE(wmacu
, e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16045 cCE(wmacuz
, e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16046 cCE(wmadds
, ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16047 cCE(wmaddu
, e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16048 cCE(wmaxsb
, e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16049 cCE(wmaxsh
, e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16050 cCE(wmaxsw
, ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16051 cCE(wmaxub
, e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16052 cCE(wmaxuh
, e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16053 cCE(wmaxuw
, e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16054 cCE(wminsb
, e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16055 cCE(wminsh
, e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16056 cCE(wminsw
, eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16057 cCE(wminub
, e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16058 cCE(wminuh
, e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16059 cCE(wminuw
, e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16060 cCE(wmov
, e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
16061 cCE(wmulsm
, e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16062 cCE(wmulsl
, e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16063 cCE(wmulum
, e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16064 cCE(wmulul
, e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16065 cCE(wor
, e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16066 cCE(wpackhss
, e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16067 cCE(wpackhus
, e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16068 cCE(wpackwss
, eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16069 cCE(wpackwus
, e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16070 cCE(wpackdss
, ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16071 cCE(wpackdus
, ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16072 cCE(wrorh
, e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16073 cCE(wrorhg
, e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16074 cCE(wrorw
, eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16075 cCE(wrorwg
, eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16076 cCE(wrord
, ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16077 cCE(wrordg
, ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16078 cCE(wsadb
, e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16079 cCE(wsadbz
, e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16080 cCE(wsadh
, e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16081 cCE(wsadhz
, e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16082 cCE(wshufh
, e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
16083 cCE(wsllh
, e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16084 cCE(wsllhg
, e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16085 cCE(wsllw
, e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16086 cCE(wsllwg
, e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16087 cCE(wslld
, ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16088 cCE(wslldg
, ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16089 cCE(wsrah
, e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16090 cCE(wsrahg
, e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16091 cCE(wsraw
, e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16092 cCE(wsrawg
, e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16093 cCE(wsrad
, ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16094 cCE(wsradg
, ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16095 cCE(wsrlh
, e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16096 cCE(wsrlhg
, e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16097 cCE(wsrlw
, ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16098 cCE(wsrlwg
, ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16099 cCE(wsrld
, ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16100 cCE(wsrldg
, ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16101 cCE(wstrb
, c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16102 cCE(wstrh
, c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16103 cCE(wstrw
, c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
16104 cCE(wstrd
, c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
16105 cCE(wsubbss
, e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16106 cCE(wsubb
, e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16107 cCE(wsubbus
, e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16108 cCE(wsubhss
, e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16109 cCE(wsubh
, e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16110 cCE(wsubhus
, e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16111 cCE(wsubwss
, eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16112 cCE(wsubw
, e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16113 cCE(wsubwus
, e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16114 cCE(wunpckehub
,e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16115 cCE(wunpckehuh
,e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16116 cCE(wunpckehuw
,e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16117 cCE(wunpckehsb
,e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16118 cCE(wunpckehsh
,e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16119 cCE(wunpckehsw
,ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16120 cCE(wunpckihb
, e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16121 cCE(wunpckihh
, e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16122 cCE(wunpckihw
, e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16123 cCE(wunpckelub
,e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16124 cCE(wunpckeluh
,e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16125 cCE(wunpckeluw
,e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16126 cCE(wunpckelsb
,e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16127 cCE(wunpckelsh
,e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16128 cCE(wunpckelsw
,ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16129 cCE(wunpckilb
, e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16130 cCE(wunpckilh
, e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16131 cCE(wunpckilw
, e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16132 cCE(wxor
, e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16133 cCE(wzero
, e300000
, 1, (RIWR
), iwmmxt_wzero
),
16136 #define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
16137 cCE(torvscb
, e13f190
, 1, (RR
), iwmmxt_tandorc
),
16138 cCE(torvsch
, e53f190
, 1, (RR
), iwmmxt_tandorc
),
16139 cCE(torvscw
, e93f190
, 1, (RR
), iwmmxt_tandorc
),
16140 cCE(wabsb
, e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16141 cCE(wabsh
, e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16142 cCE(wabsw
, ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16143 cCE(wabsdiffb
, e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16144 cCE(wabsdiffh
, e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16145 cCE(wabsdiffw
, e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16146 cCE(waddbhusl
, e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16147 cCE(waddbhusm
, e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16148 cCE(waddhc
, e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16149 cCE(waddwc
, ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16150 cCE(waddsubhx
, ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16151 cCE(wavg4
, e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16152 cCE(wavg4r
, e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16153 cCE(wmaddsn
, ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16154 cCE(wmaddsx
, eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16155 cCE(wmaddun
, ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16156 cCE(wmaddux
, e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16157 cCE(wmerge
, e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
16158 cCE(wmiabb
, e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16159 cCE(wmiabt
, e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16160 cCE(wmiatb
, e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16161 cCE(wmiatt
, e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16162 cCE(wmiabbn
, e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16163 cCE(wmiabtn
, e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16164 cCE(wmiatbn
, e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16165 cCE(wmiattn
, e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16166 cCE(wmiawbb
, e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16167 cCE(wmiawbt
, e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16168 cCE(wmiawtb
, ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16169 cCE(wmiawtt
, eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16170 cCE(wmiawbbn
, ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16171 cCE(wmiawbtn
, ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16172 cCE(wmiawtbn
, ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16173 cCE(wmiawttn
, ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16174 cCE(wmulsmr
, ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16175 cCE(wmulumr
, ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16176 cCE(wmulwumr
, ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16177 cCE(wmulwsmr
, ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16178 cCE(wmulwum
, ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16179 cCE(wmulwsm
, ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16180 cCE(wmulwl
, eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16181 cCE(wqmiabb
, e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16182 cCE(wqmiabt
, e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16183 cCE(wqmiatb
, ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16184 cCE(wqmiatt
, eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16185 cCE(wqmiabbn
, ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16186 cCE(wqmiabtn
, ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16187 cCE(wqmiatbn
, ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16188 cCE(wqmiattn
, ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16189 cCE(wqmulm
, e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16190 cCE(wqmulmr
, e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16191 cCE(wqmulwm
, ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16192 cCE(wqmulwmr
, ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16193 cCE(wsubaddhx
, ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16196 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
16197 cCE(cfldrs
, c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
16198 cCE(cfldrd
, c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
16199 cCE(cfldr32
, c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
16200 cCE(cfldr64
, c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
16201 cCE(cfstrs
, c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
16202 cCE(cfstrd
, c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
16203 cCE(cfstr32
, c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
16204 cCE(cfstr64
, c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
16205 cCE(cfmvsr
, e000450
, 2, (RMF
, RR
), rn_rd
),
16206 cCE(cfmvrs
, e100450
, 2, (RR
, RMF
), rd_rn
),
16207 cCE(cfmvdlr
, e000410
, 2, (RMD
, RR
), rn_rd
),
16208 cCE(cfmvrdl
, e100410
, 2, (RR
, RMD
), rd_rn
),
16209 cCE(cfmvdhr
, e000430
, 2, (RMD
, RR
), rn_rd
),
16210 cCE(cfmvrdh
, e100430
, 2, (RR
, RMD
), rd_rn
),
16211 cCE(cfmv64lr
, e000510
, 2, (RMDX
, RR
), rn_rd
),
16212 cCE(cfmvr64l
, e100510
, 2, (RR
, RMDX
), rd_rn
),
16213 cCE(cfmv64hr
, e000530
, 2, (RMDX
, RR
), rn_rd
),
16214 cCE(cfmvr64h
, e100530
, 2, (RR
, RMDX
), rd_rn
),
16215 cCE(cfmval32
, e200440
, 2, (RMAX
, RMFX
), rd_rn
),
16216 cCE(cfmv32al
, e100440
, 2, (RMFX
, RMAX
), rd_rn
),
16217 cCE(cfmvam32
, e200460
, 2, (RMAX
, RMFX
), rd_rn
),
16218 cCE(cfmv32am
, e100460
, 2, (RMFX
, RMAX
), rd_rn
),
16219 cCE(cfmvah32
, e200480
, 2, (RMAX
, RMFX
), rd_rn
),
16220 cCE(cfmv32ah
, e100480
, 2, (RMFX
, RMAX
), rd_rn
),
16221 cCE(cfmva32
, e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
16222 cCE(cfmv32a
, e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
16223 cCE(cfmva64
, e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
16224 cCE(cfmv64a
, e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
16225 cCE(cfmvsc32
, e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
16226 cCE(cfmv32sc
, e1004e0
, 2, (RMDX
, RMDS
), rd
),
16227 cCE(cfcpys
, e000400
, 2, (RMF
, RMF
), rd_rn
),
16228 cCE(cfcpyd
, e000420
, 2, (RMD
, RMD
), rd_rn
),
16229 cCE(cfcvtsd
, e000460
, 2, (RMD
, RMF
), rd_rn
),
16230 cCE(cfcvtds
, e000440
, 2, (RMF
, RMD
), rd_rn
),
16231 cCE(cfcvt32s
, e000480
, 2, (RMF
, RMFX
), rd_rn
),
16232 cCE(cfcvt32d
, e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
16233 cCE(cfcvt64s
, e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
16234 cCE(cfcvt64d
, e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
16235 cCE(cfcvts32
, e100580
, 2, (RMFX
, RMF
), rd_rn
),
16236 cCE(cfcvtd32
, e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
16237 cCE(cftruncs32
,e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
16238 cCE(cftruncd32
,e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
16239 cCE(cfrshl32
, e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
16240 cCE(cfrshl64
, e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
16241 cCE(cfsh32
, e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
16242 cCE(cfsh64
, e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
16243 cCE(cfcmps
, e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
16244 cCE(cfcmpd
, e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
16245 cCE(cfcmp32
, e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
16246 cCE(cfcmp64
, e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
16247 cCE(cfabss
, e300400
, 2, (RMF
, RMF
), rd_rn
),
16248 cCE(cfabsd
, e300420
, 2, (RMD
, RMD
), rd_rn
),
16249 cCE(cfnegs
, e300440
, 2, (RMF
, RMF
), rd_rn
),
16250 cCE(cfnegd
, e300460
, 2, (RMD
, RMD
), rd_rn
),
16251 cCE(cfadds
, e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16252 cCE(cfaddd
, e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16253 cCE(cfsubs
, e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16254 cCE(cfsubd
, e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16255 cCE(cfmuls
, e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16256 cCE(cfmuld
, e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16257 cCE(cfabs32
, e300500
, 2, (RMFX
, RMFX
), rd_rn
),
16258 cCE(cfabs64
, e300520
, 2, (RMDX
, RMDX
), rd_rn
),
16259 cCE(cfneg32
, e300540
, 2, (RMFX
, RMFX
), rd_rn
),
16260 cCE(cfneg64
, e300560
, 2, (RMDX
, RMDX
), rd_rn
),
16261 cCE(cfadd32
, e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16262 cCE(cfadd64
, e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16263 cCE(cfsub32
, e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16264 cCE(cfsub64
, e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16265 cCE(cfmul32
, e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16266 cCE(cfmul64
, e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16267 cCE(cfmac32
, e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16268 cCE(cfmsc32
, e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16269 cCE(cfmadd32
, e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
16270 cCE(cfmsub32
, e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
16271 cCE(cfmadda32
, e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
16272 cCE(cfmsuba32
, e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
16275 #undef THUMB_VARIANT
16302 /* MD interface: bits in the object file. */
16304 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
16305 for use in the a.out file, and stores them in the array pointed to by buf.
16306 This knows about the endian-ness of the target machine and does
16307 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
16308 2 (short) and 4 (long) Floating numbers are put out as a series of
16309 LITTLENUMS (shorts, here at least). */
16312 md_number_to_chars (char * buf
, valueT val
, int n
)
16314 if (target_big_endian
)
16315 number_to_chars_bigendian (buf
, val
, n
);
16317 number_to_chars_littleendian (buf
, val
, n
);
16321 md_chars_to_number (char * buf
, int n
)
16324 unsigned char * where
= (unsigned char *) buf
;
16326 if (target_big_endian
)
16331 result
|= (*where
++ & 255);
16339 result
|= (where
[n
] & 255);
16346 /* MD interface: Sections. */
16348 /* Estimate the size of a frag before relaxing. Assume everything fits in
16352 md_estimate_size_before_relax (fragS
* fragp
,
16353 segT segtype ATTRIBUTE_UNUSED
)
16359 /* Convert a machine dependent frag. */
16362 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
16364 unsigned long insn
;
16365 unsigned long old_op
;
16373 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16375 old_op
= bfd_get_16(abfd
, buf
);
16376 if (fragp
->fr_symbol
) {
16377 exp
.X_op
= O_symbol
;
16378 exp
.X_add_symbol
= fragp
->fr_symbol
;
16380 exp
.X_op
= O_constant
;
16382 exp
.X_add_number
= fragp
->fr_offset
;
16383 opcode
= fragp
->fr_subtype
;
16386 case T_MNEM_ldr_pc
:
16387 case T_MNEM_ldr_pc2
:
16388 case T_MNEM_ldr_sp
:
16389 case T_MNEM_str_sp
:
16396 if (fragp
->fr_var
== 4)
16398 insn
= THUMB_OP32(opcode
);
16399 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
16401 insn
|= (old_op
& 0x700) << 4;
16405 insn
|= (old_op
& 7) << 12;
16406 insn
|= (old_op
& 0x38) << 13;
16408 insn
|= 0x00000c00;
16409 put_thumb32_insn (buf
, insn
);
16410 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
16414 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
16416 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
16419 if (fragp
->fr_var
== 4)
16421 insn
= THUMB_OP32 (opcode
);
16422 insn
|= (old_op
& 0xf0) << 4;
16423 put_thumb32_insn (buf
, insn
);
16424 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
16428 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16429 exp
.X_add_number
-= 4;
16437 if (fragp
->fr_var
== 4)
16439 int r0off
= (opcode
== T_MNEM_mov
16440 || opcode
== T_MNEM_movs
) ? 0 : 8;
16441 insn
= THUMB_OP32 (opcode
);
16442 insn
= (insn
& 0xe1ffffff) | 0x10000000;
16443 insn
|= (old_op
& 0x700) << r0off
;
16444 put_thumb32_insn (buf
, insn
);
16445 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16449 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
16454 if (fragp
->fr_var
== 4)
16456 insn
= THUMB_OP32(opcode
);
16457 put_thumb32_insn (buf
, insn
);
16458 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
16461 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
16465 if (fragp
->fr_var
== 4)
16467 insn
= THUMB_OP32(opcode
);
16468 insn
|= (old_op
& 0xf00) << 14;
16469 put_thumb32_insn (buf
, insn
);
16470 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
16473 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
16476 case T_MNEM_add_sp
:
16477 case T_MNEM_add_pc
:
16478 case T_MNEM_inc_sp
:
16479 case T_MNEM_dec_sp
:
16480 if (fragp
->fr_var
== 4)
16482 /* ??? Choose between add and addw. */
16483 insn
= THUMB_OP32 (opcode
);
16484 insn
|= (old_op
& 0xf0) << 4;
16485 put_thumb32_insn (buf
, insn
);
16486 if (opcode
== T_MNEM_add_pc
)
16487 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
16489 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16492 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16500 if (fragp
->fr_var
== 4)
16502 insn
= THUMB_OP32 (opcode
);
16503 insn
|= (old_op
& 0xf0) << 4;
16504 insn
|= (old_op
& 0xf) << 16;
16505 put_thumb32_insn (buf
, insn
);
16506 if (insn
& (1 << 20))
16507 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16509 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16512 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16518 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
16520 fixp
->fx_file
= fragp
->fr_file
;
16521 fixp
->fx_line
= fragp
->fr_line
;
16522 fragp
->fr_fix
+= fragp
->fr_var
;
16525 /* Return the size of a relaxable immediate operand instruction.
16526 SHIFT and SIZE specify the form of the allowable immediate. */
16528 relax_immediate (fragS
*fragp
, int size
, int shift
)
16534 /* ??? Should be able to do better than this. */
16535 if (fragp
->fr_symbol
)
16538 low
= (1 << shift
) - 1;
16539 mask
= (1 << (shift
+ size
)) - (1 << shift
);
16540 offset
= fragp
->fr_offset
;
16541 /* Force misaligned offsets to 32-bit variant. */
16544 if (offset
& ~mask
)
16549 /* Get the address of a symbol during relaxation. */
16551 relaxed_symbol_addr(fragS
*fragp
, long stretch
)
16557 sym
= fragp
->fr_symbol
;
16558 sym_frag
= symbol_get_frag (sym
);
16559 know (S_GET_SEGMENT (sym
) != absolute_section
16560 || sym_frag
== &zero_address_frag
);
16561 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
16563 /* If frag has yet to be reached on this pass, assume it will
16564 move by STRETCH just as we did. If this is not so, it will
16565 be because some frag between grows, and that will force
16569 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
16575 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
16578 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
16583 /* Assume worst case for symbols not known to be in the same section. */
16584 if (!S_IS_DEFINED(fragp
->fr_symbol
)
16585 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16588 val
= relaxed_symbol_addr(fragp
, stretch
);
16589 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16590 addr
= (addr
+ 4) & ~3;
16591 /* Force misaligned targets to 32-bit variant. */
16595 if (val
< 0 || val
> 1020)
16600 /* Return the size of a relaxable add/sub immediate instruction. */
16602 relax_addsub (fragS
*fragp
, asection
*sec
)
16607 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16608 op
= bfd_get_16(sec
->owner
, buf
);
16609 if ((op
& 0xf) == ((op
>> 4) & 0xf))
16610 return relax_immediate (fragp
, 8, 0);
16612 return relax_immediate (fragp
, 3, 0);
16616 /* Return the size of a relaxable branch instruction. BITS is the
16617 size of the offset field in the narrow instruction. */
16620 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
16626 /* Assume worst case for symbols not known to be in the same section. */
16627 if (!S_IS_DEFINED(fragp
->fr_symbol
)
16628 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16631 val
= relaxed_symbol_addr(fragp
, stretch
);
16632 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16635 /* Offset is a signed value *2 */
16637 if (val
>= limit
|| val
< -limit
)
16643 /* Relax a machine dependent frag. This returns the amount by which
16644 the current size of the frag should change. */
16647 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
16652 oldsize
= fragp
->fr_var
;
16653 switch (fragp
->fr_subtype
)
16655 case T_MNEM_ldr_pc2
:
16656 newsize
= relax_adr(fragp
, sec
, stretch
);
16658 case T_MNEM_ldr_pc
:
16659 case T_MNEM_ldr_sp
:
16660 case T_MNEM_str_sp
:
16661 newsize
= relax_immediate(fragp
, 8, 2);
16665 newsize
= relax_immediate(fragp
, 5, 2);
16669 newsize
= relax_immediate(fragp
, 5, 1);
16673 newsize
= relax_immediate(fragp
, 5, 0);
16676 newsize
= relax_adr(fragp
, sec
, stretch
);
16682 newsize
= relax_immediate(fragp
, 8, 0);
16685 newsize
= relax_branch(fragp
, sec
, 11, stretch
);
16688 newsize
= relax_branch(fragp
, sec
, 8, stretch
);
16690 case T_MNEM_add_sp
:
16691 case T_MNEM_add_pc
:
16692 newsize
= relax_immediate (fragp
, 8, 2);
16694 case T_MNEM_inc_sp
:
16695 case T_MNEM_dec_sp
:
16696 newsize
= relax_immediate (fragp
, 7, 2);
16702 newsize
= relax_addsub (fragp
, sec
);
16708 fragp
->fr_var
= newsize
;
16709 /* Freeze wide instructions that are at or before the same location as
16710 in the previous pass. This avoids infinite loops.
16711 Don't freeze them unconditionally because targets may be artificialy
16712 misaligned by the expansion of preceeding frags. */
16713 if (stretch
<= 0 && newsize
> 2)
16715 md_convert_frag (sec
->owner
, sec
, fragp
);
16719 return newsize
- oldsize
;
16722 /* Round up a section size to the appropriate boundary. */
16725 md_section_align (segT segment ATTRIBUTE_UNUSED
,
16728 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
16729 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
16731 /* For a.out, force the section size to be aligned. If we don't do
16732 this, BFD will align it for us, but it will not write out the
16733 final bytes of the section. This may be a bug in BFD, but it is
16734 easier to fix it here since that is how the other a.out targets
16738 align
= bfd_get_section_alignment (stdoutput
, segment
);
16739 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
16746 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
16747 of an rs_align_code fragment. */
16750 arm_handle_align (fragS
* fragP
)
16752 static char const arm_noop
[4] = { 0x00, 0x00, 0xa0, 0xe1 };
16753 static char const thumb_noop
[2] = { 0xc0, 0x46 };
16754 static char const arm_bigend_noop
[4] = { 0xe1, 0xa0, 0x00, 0x00 };
16755 static char const thumb_bigend_noop
[2] = { 0x46, 0xc0 };
16757 int bytes
, fix
, noop_size
;
16761 if (fragP
->fr_type
!= rs_align_code
)
16764 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
16765 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
16768 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
16769 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
16771 if (fragP
->tc_frag_data
)
16773 if (target_big_endian
)
16774 noop
= thumb_bigend_noop
;
16777 noop_size
= sizeof (thumb_noop
);
16781 if (target_big_endian
)
16782 noop
= arm_bigend_noop
;
16785 noop_size
= sizeof (arm_noop
);
16788 if (bytes
& (noop_size
- 1))
16790 fix
= bytes
& (noop_size
- 1);
16791 memset (p
, 0, fix
);
16796 while (bytes
>= noop_size
)
16798 memcpy (p
, noop
, noop_size
);
16800 bytes
-= noop_size
;
16804 fragP
->fr_fix
+= fix
;
16805 fragP
->fr_var
= noop_size
;
16808 /* Called from md_do_align. Used to create an alignment
16809 frag in a code section. */
16812 arm_frag_align_code (int n
, int max
)
16816 /* We assume that there will never be a requirement
16817 to support alignments greater than 32 bytes. */
16818 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
16819 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
16821 p
= frag_var (rs_align_code
,
16822 MAX_MEM_FOR_RS_ALIGN_CODE
,
16824 (relax_substateT
) max
,
16831 /* Perform target specific initialisation of a frag. */
16834 arm_init_frag (fragS
* fragP
)
16836 /* Record whether this frag is in an ARM or a THUMB area. */
16837 fragP
->tc_frag_data
= thumb_mode
;
16841 /* When we change sections we need to issue a new mapping symbol. */
16844 arm_elf_change_section (void)
16847 segment_info_type
*seginfo
;
16849 /* Link an unlinked unwind index table section to the .text section. */
16850 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
16851 && elf_linked_to_section (now_seg
) == NULL
)
16852 elf_linked_to_section (now_seg
) = text_section
;
16854 if (!SEG_NORMAL (now_seg
))
16857 flags
= bfd_get_section_flags (stdoutput
, now_seg
);
16859 /* We can ignore sections that only contain debug info. */
16860 if ((flags
& SEC_ALLOC
) == 0)
16863 seginfo
= seg_info (now_seg
);
16864 mapstate
= seginfo
->tc_segment_info_data
.mapstate
;
16865 marked_pr_dependency
= seginfo
->tc_segment_info_data
.marked_pr_dependency
;
16869 arm_elf_section_type (const char * str
, size_t len
)
16871 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
16872 return SHT_ARM_EXIDX
;
16877 /* Code to deal with unwinding tables. */
16879 static void add_unwind_adjustsp (offsetT
);
16881 /* Cenerate and deferred unwind frame offset. */
16884 flush_pending_unwind (void)
16888 offset
= unwind
.pending_offset
;
16889 unwind
.pending_offset
= 0;
16891 add_unwind_adjustsp (offset
);
16894 /* Add an opcode to this list for this function. Two-byte opcodes should
16895 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
16899 add_unwind_opcode (valueT op
, int length
)
16901 /* Add any deferred stack adjustment. */
16902 if (unwind
.pending_offset
)
16903 flush_pending_unwind ();
16905 unwind
.sp_restored
= 0;
16907 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
16909 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
16910 if (unwind
.opcodes
)
16911 unwind
.opcodes
= xrealloc (unwind
.opcodes
,
16912 unwind
.opcode_alloc
);
16914 unwind
.opcodes
= xmalloc (unwind
.opcode_alloc
);
16919 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
16921 unwind
.opcode_count
++;
16925 /* Add unwind opcodes to adjust the stack pointer. */
16928 add_unwind_adjustsp (offsetT offset
)
16932 if (offset
> 0x200)
16934 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
16939 /* Long form: 0xb2, uleb128. */
16940 /* This might not fit in a word so add the individual bytes,
16941 remembering the list is built in reverse order. */
16942 o
= (valueT
) ((offset
- 0x204) >> 2);
16944 add_unwind_opcode (0, 1);
16946 /* Calculate the uleb128 encoding of the offset. */
16950 bytes
[n
] = o
& 0x7f;
16956 /* Add the insn. */
16958 add_unwind_opcode (bytes
[n
- 1], 1);
16959 add_unwind_opcode (0xb2, 1);
16961 else if (offset
> 0x100)
16963 /* Two short opcodes. */
16964 add_unwind_opcode (0x3f, 1);
16965 op
= (offset
- 0x104) >> 2;
16966 add_unwind_opcode (op
, 1);
16968 else if (offset
> 0)
16970 /* Short opcode. */
16971 op
= (offset
- 4) >> 2;
16972 add_unwind_opcode (op
, 1);
16974 else if (offset
< 0)
16977 while (offset
> 0x100)
16979 add_unwind_opcode (0x7f, 1);
16982 op
= ((offset
- 4) >> 2) | 0x40;
16983 add_unwind_opcode (op
, 1);
16987 /* Finish the list of unwind opcodes for this function. */
16989 finish_unwind_opcodes (void)
16993 if (unwind
.fp_used
)
16995 /* Adjust sp as necessary. */
16996 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
16997 flush_pending_unwind ();
16999 /* After restoring sp from the frame pointer. */
17000 op
= 0x90 | unwind
.fp_reg
;
17001 add_unwind_opcode (op
, 1);
17004 flush_pending_unwind ();
17008 /* Start an exception table entry. If idx is nonzero this is an index table
17012 start_unwind_section (const segT text_seg
, int idx
)
17014 const char * text_name
;
17015 const char * prefix
;
17016 const char * prefix_once
;
17017 const char * group_name
;
17021 size_t sec_name_len
;
17028 prefix
= ELF_STRING_ARM_unwind
;
17029 prefix_once
= ELF_STRING_ARM_unwind_once
;
17030 type
= SHT_ARM_EXIDX
;
17034 prefix
= ELF_STRING_ARM_unwind_info
;
17035 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
17036 type
= SHT_PROGBITS
;
17039 text_name
= segment_name (text_seg
);
17040 if (streq (text_name
, ".text"))
17043 if (strncmp (text_name
, ".gnu.linkonce.t.",
17044 strlen (".gnu.linkonce.t.")) == 0)
17046 prefix
= prefix_once
;
17047 text_name
+= strlen (".gnu.linkonce.t.");
17050 prefix_len
= strlen (prefix
);
17051 text_len
= strlen (text_name
);
17052 sec_name_len
= prefix_len
+ text_len
;
17053 sec_name
= xmalloc (sec_name_len
+ 1);
17054 memcpy (sec_name
, prefix
, prefix_len
);
17055 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
17056 sec_name
[prefix_len
+ text_len
] = '\0';
17062 /* Handle COMDAT group. */
17063 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
17065 group_name
= elf_group_name (text_seg
);
17066 if (group_name
== NULL
)
17068 as_bad ("Group section `%s' has no group signature",
17069 segment_name (text_seg
));
17070 ignore_rest_of_line ();
17073 flags
|= SHF_GROUP
;
17077 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
17079 /* Set the setion link for index tables. */
17081 elf_linked_to_section (now_seg
) = text_seg
;
17085 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
17086 personality routine data. Returns zero, or the index table value for
17087 and inline entry. */
17090 create_unwind_entry (int have_data
)
17095 /* The current word of data. */
17097 /* The number of bytes left in this word. */
17100 finish_unwind_opcodes ();
17102 /* Remember the current text section. */
17103 unwind
.saved_seg
= now_seg
;
17104 unwind
.saved_subseg
= now_subseg
;
17106 start_unwind_section (now_seg
, 0);
17108 if (unwind
.personality_routine
== NULL
)
17110 if (unwind
.personality_index
== -2)
17113 as_bad (_("handerdata in cantunwind frame"));
17114 return 1; /* EXIDX_CANTUNWIND. */
17117 /* Use a default personality routine if none is specified. */
17118 if (unwind
.personality_index
== -1)
17120 if (unwind
.opcode_count
> 3)
17121 unwind
.personality_index
= 1;
17123 unwind
.personality_index
= 0;
17126 /* Space for the personality routine entry. */
17127 if (unwind
.personality_index
== 0)
17129 if (unwind
.opcode_count
> 3)
17130 as_bad (_("too many unwind opcodes for personality routine 0"));
17134 /* All the data is inline in the index table. */
17137 while (unwind
.opcode_count
> 0)
17139 unwind
.opcode_count
--;
17140 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
17144 /* Pad with "finish" opcodes. */
17146 data
= (data
<< 8) | 0xb0;
17153 /* We get two opcodes "free" in the first word. */
17154 size
= unwind
.opcode_count
- 2;
17157 /* An extra byte is required for the opcode count. */
17158 size
= unwind
.opcode_count
+ 1;
17160 size
= (size
+ 3) >> 2;
17162 as_bad (_("too many unwind opcodes"));
17164 frag_align (2, 0, 0);
17165 record_alignment (now_seg
, 2);
17166 unwind
.table_entry
= expr_build_dot ();
17168 /* Allocate the table entry. */
17169 ptr
= frag_more ((size
<< 2) + 4);
17170 where
= frag_now_fix () - ((size
<< 2) + 4);
17172 switch (unwind
.personality_index
)
17175 /* ??? Should this be a PLT generating relocation? */
17176 /* Custom personality routine. */
17177 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
17178 BFD_RELOC_ARM_PREL31
);
17183 /* Set the first byte to the number of additional words. */
17188 /* ABI defined personality routines. */
17190 /* Three opcodes bytes are packed into the first word. */
17197 /* The size and first two opcode bytes go in the first word. */
17198 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
17203 /* Should never happen. */
17207 /* Pack the opcodes into words (MSB first), reversing the list at the same
17209 while (unwind
.opcode_count
> 0)
17213 md_number_to_chars (ptr
, data
, 4);
17218 unwind
.opcode_count
--;
17220 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
17223 /* Finish off the last word. */
17226 /* Pad with "finish" opcodes. */
17228 data
= (data
<< 8) | 0xb0;
17230 md_number_to_chars (ptr
, data
, 4);
17235 /* Add an empty descriptor if there is no user-specified data. */
17236 ptr
= frag_more (4);
17237 md_number_to_chars (ptr
, 0, 4);
17244 /* Initialize the DWARF-2 unwind information for this procedure. */
17247 tc_arm_frame_initial_instructions (void)
17249 cfi_add_CFA_def_cfa (REG_SP
, 0);
17251 #endif /* OBJ_ELF */
17253 /* Convert REGNAME to a DWARF-2 register number. */
17256 tc_arm_regname_to_dw2regnum (char *regname
)
17258 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
17268 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
17272 expr
.X_op
= O_secrel
;
17273 expr
.X_add_symbol
= symbol
;
17274 expr
.X_add_number
= 0;
17275 emit_expr (&expr
, size
);
17279 /* MD interface: Symbol and relocation handling. */
17281 /* Return the address within the segment that a PC-relative fixup is
17282 relative to. For ARM, PC-relative fixups applied to instructions
17283 are generally relative to the location of the fixup plus 8 bytes.
17284 Thumb branches are offset by 4, and Thumb loads relative to PC
17285 require special handling. */
17288 md_pcrel_from_section (fixS
* fixP
, segT seg
)
17290 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
17292 /* If this is pc-relative and we are going to emit a relocation
17293 then we just want to put out any pipeline compensation that the linker
17294 will need. Otherwise we want to use the calculated base.
17295 For WinCE we skip the bias for externals as well, since this
17296 is how the MS ARM-CE assembler behaves and we want to be compatible. */
17298 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
17299 || (arm_force_relocation (fixP
)
17301 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
17306 switch (fixP
->fx_r_type
)
17308 /* PC relative addressing on the Thumb is slightly odd as the
17309 bottom two bits of the PC are forced to zero for the
17310 calculation. This happens *after* application of the
17311 pipeline offset. However, Thumb adrl already adjusts for
17312 this, so we need not do it again. */
17313 case BFD_RELOC_ARM_THUMB_ADD
:
17316 case BFD_RELOC_ARM_THUMB_OFFSET
:
17317 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
17318 case BFD_RELOC_ARM_T32_ADD_PC12
:
17319 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
17320 return (base
+ 4) & ~3;
17322 /* Thumb branches are simply offset by +4. */
17323 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
17324 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
17325 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
17326 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
17327 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
17328 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
17329 case BFD_RELOC_THUMB_PCREL_BLX
:
17332 /* ARM mode branches are offset by +8. However, the Windows CE
17333 loader expects the relocation not to take this into account. */
17334 case BFD_RELOC_ARM_PCREL_BRANCH
:
17335 case BFD_RELOC_ARM_PCREL_CALL
:
17336 case BFD_RELOC_ARM_PCREL_JUMP
:
17337 case BFD_RELOC_ARM_PCREL_BLX
:
17338 case BFD_RELOC_ARM_PLT32
:
17340 /* When handling fixups immediately, because we have already
17341 discovered the value of a symbol, or the address of the frag involved
17342 we must account for the offset by +8, as the OS loader will never see the reloc.
17343 see fixup_segment() in write.c
17344 The S_IS_EXTERNAL test handles the case of global symbols.
17345 Those need the calculated base, not just the pipe compensation the linker will need. */
17347 && fixP
->fx_addsy
!= NULL
17348 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
17349 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
17356 /* ARM mode loads relative to PC are also offset by +8. Unlike
17357 branches, the Windows CE loader *does* expect the relocation
17358 to take this into account. */
17359 case BFD_RELOC_ARM_OFFSET_IMM
:
17360 case BFD_RELOC_ARM_OFFSET_IMM8
:
17361 case BFD_RELOC_ARM_HWLITERAL
:
17362 case BFD_RELOC_ARM_LITERAL
:
17363 case BFD_RELOC_ARM_CP_OFF_IMM
:
17367 /* Other PC-relative relocations are un-offset. */
17373 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
17374 Otherwise we have no need to default values of symbols. */
17377 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
17380 if (name
[0] == '_' && name
[1] == 'G'
17381 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
17385 if (symbol_find (name
))
17386 as_bad ("GOT already in the symbol table");
17388 GOT_symbol
= symbol_new (name
, undefined_section
,
17389 (valueT
) 0, & zero_address_frag
);
17399 /* Subroutine of md_apply_fix. Check to see if an immediate can be
17400 computed as two separate immediate values, added together. We
17401 already know that this value cannot be computed by just one ARM
17404 static unsigned int
17405 validate_immediate_twopart (unsigned int val
,
17406 unsigned int * highpart
)
17411 for (i
= 0; i
< 32; i
+= 2)
17412 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
17418 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
17420 else if (a
& 0xff0000)
17422 if (a
& 0xff000000)
17424 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
17428 assert (a
& 0xff000000);
17429 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
17432 return (a
& 0xff) | (i
<< 7);
17439 validate_offset_imm (unsigned int val
, int hwse
)
17441 if ((hwse
&& val
> 255) || val
> 4095)
17446 /* Subroutine of md_apply_fix. Do those data_ops which can take a
17447 negative immediate constant by altering the instruction. A bit of
17452 by inverting the second operand, and
17455 by negating the second operand. */
17458 negate_data_op (unsigned long * instruction
,
17459 unsigned long value
)
17462 unsigned long negated
, inverted
;
17464 negated
= encode_arm_immediate (-value
);
17465 inverted
= encode_arm_immediate (~value
);
17467 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
17470 /* First negates. */
17471 case OPCODE_SUB
: /* ADD <-> SUB */
17472 new_inst
= OPCODE_ADD
;
17477 new_inst
= OPCODE_SUB
;
17481 case OPCODE_CMP
: /* CMP <-> CMN */
17482 new_inst
= OPCODE_CMN
;
17487 new_inst
= OPCODE_CMP
;
17491 /* Now Inverted ops. */
17492 case OPCODE_MOV
: /* MOV <-> MVN */
17493 new_inst
= OPCODE_MVN
;
17498 new_inst
= OPCODE_MOV
;
17502 case OPCODE_AND
: /* AND <-> BIC */
17503 new_inst
= OPCODE_BIC
;
17508 new_inst
= OPCODE_AND
;
17512 case OPCODE_ADC
: /* ADC <-> SBC */
17513 new_inst
= OPCODE_SBC
;
17518 new_inst
= OPCODE_ADC
;
17522 /* We cannot do anything. */
17527 if (value
== (unsigned) FAIL
)
17530 *instruction
&= OPCODE_MASK
;
17531 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
17535 /* Like negate_data_op, but for Thumb-2. */
17537 static unsigned int
17538 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
17542 unsigned int negated
, inverted
;
17544 negated
= encode_thumb32_immediate (-value
);
17545 inverted
= encode_thumb32_immediate (~value
);
17547 rd
= (*instruction
>> 8) & 0xf;
17548 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
17551 /* ADD <-> SUB. Includes CMP <-> CMN. */
17552 case T2_OPCODE_SUB
:
17553 new_inst
= T2_OPCODE_ADD
;
17557 case T2_OPCODE_ADD
:
17558 new_inst
= T2_OPCODE_SUB
;
17562 /* ORR <-> ORN. Includes MOV <-> MVN. */
17563 case T2_OPCODE_ORR
:
17564 new_inst
= T2_OPCODE_ORN
;
17568 case T2_OPCODE_ORN
:
17569 new_inst
= T2_OPCODE_ORR
;
17573 /* AND <-> BIC. TST has no inverted equivalent. */
17574 case T2_OPCODE_AND
:
17575 new_inst
= T2_OPCODE_BIC
;
17582 case T2_OPCODE_BIC
:
17583 new_inst
= T2_OPCODE_AND
;
17588 case T2_OPCODE_ADC
:
17589 new_inst
= T2_OPCODE_SBC
;
17593 case T2_OPCODE_SBC
:
17594 new_inst
= T2_OPCODE_ADC
;
17598 /* We cannot do anything. */
17603 if (value
== (unsigned int)FAIL
)
17606 *instruction
&= T2_OPCODE_MASK
;
17607 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
17611 /* Read a 32-bit thumb instruction from buf. */
17612 static unsigned long
17613 get_thumb32_insn (char * buf
)
17615 unsigned long insn
;
17616 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
17617 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17623 /* We usually want to set the low bit on the address of thumb function
17624 symbols. In particular .word foo - . should have the low bit set.
17625 Generic code tries to fold the difference of two symbols to
17626 a constant. Prevent this and force a relocation when the first symbols
17627 is a thumb function. */
17629 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
17631 if (op
== O_subtract
17632 && l
->X_op
== O_symbol
17633 && r
->X_op
== O_symbol
17634 && THUMB_IS_FUNC (l
->X_add_symbol
))
17636 l
->X_op
= O_subtract
;
17637 l
->X_op_symbol
= r
->X_add_symbol
;
17638 l
->X_add_number
-= r
->X_add_number
;
17641 /* Process as normal. */
17646 md_apply_fix (fixS
* fixP
,
17650 offsetT value
= * valP
;
17652 unsigned int newimm
;
17653 unsigned long temp
;
17655 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
17657 assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
17659 /* Note whether this will delete the relocation. */
17661 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
17664 /* On a 64-bit host, silently truncate 'value' to 32 bits for
17665 consistency with the behavior on 32-bit hosts. Remember value
17667 value
&= 0xffffffff;
17668 value
^= 0x80000000;
17669 value
-= 0x80000000;
17672 fixP
->fx_addnumber
= value
;
17674 /* Same treatment for fixP->fx_offset. */
17675 fixP
->fx_offset
&= 0xffffffff;
17676 fixP
->fx_offset
^= 0x80000000;
17677 fixP
->fx_offset
-= 0x80000000;
17679 switch (fixP
->fx_r_type
)
17681 case BFD_RELOC_NONE
:
17682 /* This will need to go in the object file. */
17686 case BFD_RELOC_ARM_IMMEDIATE
:
17687 /* We claim that this fixup has been processed here,
17688 even if in fact we generate an error because we do
17689 not have a reloc for it, so tc_gen_reloc will reject it. */
17693 && ! S_IS_DEFINED (fixP
->fx_addsy
))
17695 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17696 _("undefined symbol %s used as an immediate value"),
17697 S_GET_NAME (fixP
->fx_addsy
));
17701 newimm
= encode_arm_immediate (value
);
17702 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17704 /* If the instruction will fail, see if we can fix things up by
17705 changing the opcode. */
17706 if (newimm
== (unsigned int) FAIL
17707 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
17709 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17710 _("invalid constant (%lx) after fixup"),
17711 (unsigned long) value
);
17715 newimm
|= (temp
& 0xfffff000);
17716 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
17719 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
17721 unsigned int highpart
= 0;
17722 unsigned int newinsn
= 0xe1a00000; /* nop. */
17724 newimm
= encode_arm_immediate (value
);
17725 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17727 /* If the instruction will fail, see if we can fix things up by
17728 changing the opcode. */
17729 if (newimm
== (unsigned int) FAIL
17730 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
17732 /* No ? OK - try using two ADD instructions to generate
17734 newimm
= validate_immediate_twopart (value
, & highpart
);
17736 /* Yes - then make sure that the second instruction is
17738 if (newimm
!= (unsigned int) FAIL
)
17740 /* Still No ? Try using a negated value. */
17741 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
17742 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
17743 /* Otherwise - give up. */
17746 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17747 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
17752 /* Replace the first operand in the 2nd instruction (which
17753 is the PC) with the destination register. We have
17754 already added in the PC in the first instruction and we
17755 do not want to do it again. */
17756 newinsn
&= ~ 0xf0000;
17757 newinsn
|= ((newinsn
& 0x0f000) << 4);
17760 newimm
|= (temp
& 0xfffff000);
17761 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
17763 highpart
|= (newinsn
& 0xfffff000);
17764 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
17768 case BFD_RELOC_ARM_OFFSET_IMM
:
17769 if (!fixP
->fx_done
&& seg
->use_rela_p
)
17772 case BFD_RELOC_ARM_LITERAL
:
17778 if (validate_offset_imm (value
, 0) == FAIL
)
17780 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
17781 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17782 _("invalid literal constant: pool needs to be closer"));
17784 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17785 _("bad immediate value for offset (%ld)"),
17790 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17791 newval
&= 0xff7ff000;
17792 newval
|= value
| (sign
? INDEX_UP
: 0);
17793 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17796 case BFD_RELOC_ARM_OFFSET_IMM8
:
17797 case BFD_RELOC_ARM_HWLITERAL
:
17803 if (validate_offset_imm (value
, 1) == FAIL
)
17805 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
17806 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17807 _("invalid literal constant: pool needs to be closer"));
17809 as_bad (_("bad immediate value for half-word offset (%ld)"),
17814 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17815 newval
&= 0xff7ff0f0;
17816 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
17817 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17820 case BFD_RELOC_ARM_T32_OFFSET_U8
:
17821 if (value
< 0 || value
> 1020 || value
% 4 != 0)
17822 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17823 _("bad immediate value for offset (%ld)"), (long) value
);
17826 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
17828 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
17831 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
17832 /* This is a complicated relocation used for all varieties of Thumb32
17833 load/store instruction with immediate offset:
17835 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
17836 *4, optional writeback(W)
17837 (doubleword load/store)
17839 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
17840 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
17841 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
17842 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
17843 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
17845 Uppercase letters indicate bits that are already encoded at
17846 this point. Lowercase letters are our problem. For the
17847 second block of instructions, the secondary opcode nybble
17848 (bits 8..11) is present, and bit 23 is zero, even if this is
17849 a PC-relative operation. */
17850 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17852 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
17854 if ((newval
& 0xf0000000) == 0xe0000000)
17856 /* Doubleword load/store: 8-bit offset, scaled by 4. */
17858 newval
|= (1 << 23);
17861 if (value
% 4 != 0)
17863 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17864 _("offset not a multiple of 4"));
17870 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17871 _("offset out of range"));
17876 else if ((newval
& 0x000f0000) == 0x000f0000)
17878 /* PC-relative, 12-bit offset. */
17880 newval
|= (1 << 23);
17885 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17886 _("offset out of range"));
17891 else if ((newval
& 0x00000100) == 0x00000100)
17893 /* Writeback: 8-bit, +/- offset. */
17895 newval
|= (1 << 9);
17900 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17901 _("offset out of range"));
17906 else if ((newval
& 0x00000f00) == 0x00000e00)
17908 /* T-instruction: positive 8-bit offset. */
17909 if (value
< 0 || value
> 0xff)
17911 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17912 _("offset out of range"));
17920 /* Positive 12-bit or negative 8-bit offset. */
17924 newval
|= (1 << 23);
17934 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17935 _("offset out of range"));
17942 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
17943 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
17946 case BFD_RELOC_ARM_SHIFT_IMM
:
17947 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17948 if (((unsigned long) value
) > 32
17950 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
17952 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17953 _("shift expression is too large"));
17958 /* Shifts of zero must be done as lsl. */
17960 else if (value
== 32)
17962 newval
&= 0xfffff07f;
17963 newval
|= (value
& 0x1f) << 7;
17964 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17967 case BFD_RELOC_ARM_T32_IMMEDIATE
:
17968 case BFD_RELOC_ARM_T32_ADD_IMM
:
17969 case BFD_RELOC_ARM_T32_IMM12
:
17970 case BFD_RELOC_ARM_T32_ADD_PC12
:
17971 /* We claim that this fixup has been processed here,
17972 even if in fact we generate an error because we do
17973 not have a reloc for it, so tc_gen_reloc will reject it. */
17977 && ! S_IS_DEFINED (fixP
->fx_addsy
))
17979 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17980 _("undefined symbol %s used as an immediate value"),
17981 S_GET_NAME (fixP
->fx_addsy
));
17985 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17987 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
17990 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
17991 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
17993 newimm
= encode_thumb32_immediate (value
);
17994 if (newimm
== (unsigned int) FAIL
)
17995 newimm
= thumb32_negate_data_op (&newval
, value
);
17997 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
17998 && newimm
== (unsigned int) FAIL
)
18000 /* Turn add/sum into addw/subw. */
18001 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
18002 newval
= (newval
& 0xfeffffff) | 0x02000000;
18004 /* 12 bit immediate for addw/subw. */
18008 newval
^= 0x00a00000;
18011 newimm
= (unsigned int) FAIL
;
18016 if (newimm
== (unsigned int)FAIL
)
18018 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18019 _("invalid constant (%lx) after fixup"),
18020 (unsigned long) value
);
18024 newval
|= (newimm
& 0x800) << 15;
18025 newval
|= (newimm
& 0x700) << 4;
18026 newval
|= (newimm
& 0x0ff);
18028 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
18029 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
18032 case BFD_RELOC_ARM_SMC
:
18033 if (((unsigned long) value
) > 0xffff)
18034 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18035 _("invalid smc expression"));
18036 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18037 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
18038 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18041 case BFD_RELOC_ARM_SWI
:
18042 if (fixP
->tc_fix_data
!= 0)
18044 if (((unsigned long) value
) > 0xff)
18045 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18046 _("invalid swi expression"));
18047 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18049 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18053 if (((unsigned long) value
) > 0x00ffffff)
18054 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18055 _("invalid swi expression"));
18056 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18058 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18062 case BFD_RELOC_ARM_MULTI
:
18063 if (((unsigned long) value
) > 0xffff)
18064 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18065 _("invalid expression in load/store multiple"));
18066 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
18067 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18071 case BFD_RELOC_ARM_PCREL_CALL
:
18072 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18073 if ((newval
& 0xf0000000) == 0xf0000000)
18077 goto arm_branch_common
;
18079 case BFD_RELOC_ARM_PCREL_JUMP
:
18080 case BFD_RELOC_ARM_PLT32
:
18082 case BFD_RELOC_ARM_PCREL_BRANCH
:
18084 goto arm_branch_common
;
18086 case BFD_RELOC_ARM_PCREL_BLX
:
18089 /* We are going to store value (shifted right by two) in the
18090 instruction, in a 24 bit, signed field. Bits 26 through 32 either
18091 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
18092 also be be clear. */
18094 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18095 _("misaligned branch destination"));
18096 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
18097 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
18098 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18099 _("branch out of range"));
18101 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18103 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18104 newval
|= (value
>> 2) & 0x00ffffff;
18105 /* Set the H bit on BLX instructions. */
18109 newval
|= 0x01000000;
18111 newval
&= ~0x01000000;
18113 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18117 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
18118 /* CBZ can only branch forward. */
18120 /* Attempts to use CBZ to branch to the next instruction
18121 (which, strictly speaking, are prohibited) will be turned into
18124 FIXME: It may be better to remove the instruction completely and
18125 perform relaxation. */
18128 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18129 newval
= 0xbf00; /* NOP encoding T1 */
18130 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18135 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18136 _("branch out of range"));
18138 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18140 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18141 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
18142 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18147 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
18148 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
18149 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18150 _("branch out of range"));
18152 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18154 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18155 newval
|= (value
& 0x1ff) >> 1;
18156 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18160 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
18161 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
18162 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18163 _("branch out of range"));
18165 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18167 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18168 newval
|= (value
& 0xfff) >> 1;
18169 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18173 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
18174 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
18175 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18176 _("conditional branch out of range"));
18178 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18181 addressT S
, J1
, J2
, lo
, hi
;
18183 S
= (value
& 0x00100000) >> 20;
18184 J2
= (value
& 0x00080000) >> 19;
18185 J1
= (value
& 0x00040000) >> 18;
18186 hi
= (value
& 0x0003f000) >> 12;
18187 lo
= (value
& 0x00000ffe) >> 1;
18189 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18190 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18191 newval
|= (S
<< 10) | hi
;
18192 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
18193 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18194 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18198 case BFD_RELOC_THUMB_PCREL_BLX
:
18199 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
18200 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
18201 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18202 _("branch out of range"));
18204 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
18205 /* For a BLX instruction, make sure that the relocation is rounded up
18206 to a word boundary. This follows the semantics of the instruction
18207 which specifies that bit 1 of the target address will come from bit
18208 1 of the base address. */
18209 value
= (value
+ 1) & ~ 1;
18211 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18215 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18216 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18217 newval
|= (value
& 0x7fffff) >> 12;
18218 newval2
|= (value
& 0xfff) >> 1;
18219 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18220 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18224 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
18225 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
18226 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18227 _("branch out of range"));
18229 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18232 addressT S
, I1
, I2
, lo
, hi
;
18234 S
= (value
& 0x01000000) >> 24;
18235 I1
= (value
& 0x00800000) >> 23;
18236 I2
= (value
& 0x00400000) >> 22;
18237 hi
= (value
& 0x003ff000) >> 12;
18238 lo
= (value
& 0x00000ffe) >> 1;
18243 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18244 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18245 newval
|= (S
<< 10) | hi
;
18246 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
18247 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18248 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18253 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18254 md_number_to_chars (buf
, value
, 1);
18258 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18259 md_number_to_chars (buf
, value
, 2);
18263 case BFD_RELOC_ARM_TLS_GD32
:
18264 case BFD_RELOC_ARM_TLS_LE32
:
18265 case BFD_RELOC_ARM_TLS_IE32
:
18266 case BFD_RELOC_ARM_TLS_LDM32
:
18267 case BFD_RELOC_ARM_TLS_LDO32
:
18268 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
18271 case BFD_RELOC_ARM_GOT32
:
18272 case BFD_RELOC_ARM_GOTOFF
:
18273 case BFD_RELOC_ARM_TARGET2
:
18274 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18275 md_number_to_chars (buf
, 0, 4);
18279 case BFD_RELOC_RVA
:
18281 case BFD_RELOC_ARM_TARGET1
:
18282 case BFD_RELOC_ARM_ROSEGREL32
:
18283 case BFD_RELOC_ARM_SBREL32
:
18284 case BFD_RELOC_32_PCREL
:
18286 case BFD_RELOC_32_SECREL
:
18288 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18290 /* For WinCE we only do this for pcrel fixups. */
18291 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
18293 md_number_to_chars (buf
, value
, 4);
18297 case BFD_RELOC_ARM_PREL31
:
18298 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18300 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
18301 if ((value
^ (value
>> 1)) & 0x40000000)
18303 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18304 _("rel31 relocation overflow"));
18306 newval
|= value
& 0x7fffffff;
18307 md_number_to_chars (buf
, newval
, 4);
18312 case BFD_RELOC_ARM_CP_OFF_IMM
:
18313 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
18314 if (value
< -1023 || value
> 1023 || (value
& 3))
18315 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18316 _("co-processor offset out of range"));
18321 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18322 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18323 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18325 newval
= get_thumb32_insn (buf
);
18326 newval
&= 0xff7fff00;
18327 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
18328 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18329 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18330 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18332 put_thumb32_insn (buf
, newval
);
18335 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
18336 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
18337 if (value
< -255 || value
> 255)
18338 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18339 _("co-processor offset out of range"));
18341 goto cp_off_common
;
18343 case BFD_RELOC_ARM_THUMB_OFFSET
:
18344 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18345 /* Exactly what ranges, and where the offset is inserted depends
18346 on the type of instruction, we can establish this from the
18348 switch (newval
>> 12)
18350 case 4: /* PC load. */
18351 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
18352 forced to zero for these loads; md_pcrel_from has already
18353 compensated for this. */
18355 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18356 _("invalid offset, target not word aligned (0x%08lX)"),
18357 (((unsigned long) fixP
->fx_frag
->fr_address
18358 + (unsigned long) fixP
->fx_where
) & ~3)
18359 + (unsigned long) value
);
18361 if (value
& ~0x3fc)
18362 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18363 _("invalid offset, value too big (0x%08lX)"),
18366 newval
|= value
>> 2;
18369 case 9: /* SP load/store. */
18370 if (value
& ~0x3fc)
18371 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18372 _("invalid offset, value too big (0x%08lX)"),
18374 newval
|= value
>> 2;
18377 case 6: /* Word load/store. */
18379 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18380 _("invalid offset, value too big (0x%08lX)"),
18382 newval
|= value
<< 4; /* 6 - 2. */
18385 case 7: /* Byte load/store. */
18387 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18388 _("invalid offset, value too big (0x%08lX)"),
18390 newval
|= value
<< 6;
18393 case 8: /* Halfword load/store. */
18395 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18396 _("invalid offset, value too big (0x%08lX)"),
18398 newval
|= value
<< 5; /* 6 - 1. */
18402 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18403 "Unable to process relocation for thumb opcode: %lx",
18404 (unsigned long) newval
);
18407 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18410 case BFD_RELOC_ARM_THUMB_ADD
:
18411 /* This is a complicated relocation, since we use it for all of
18412 the following immediate relocations:
18416 9bit ADD/SUB SP word-aligned
18417 10bit ADD PC/SP word-aligned
18419 The type of instruction being processed is encoded in the
18426 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18428 int rd
= (newval
>> 4) & 0xf;
18429 int rs
= newval
& 0xf;
18430 int subtract
= !!(newval
& 0x8000);
18432 /* Check for HI regs, only very restricted cases allowed:
18433 Adjusting SP, and using PC or SP to get an address. */
18434 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
18435 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
18436 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18437 _("invalid Hi register with immediate"));
18439 /* If value is negative, choose the opposite instruction. */
18443 subtract
= !subtract
;
18445 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18446 _("immediate value out of range"));
18451 if (value
& ~0x1fc)
18452 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18453 _("invalid immediate for stack address calculation"));
18454 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
18455 newval
|= value
>> 2;
18457 else if (rs
== REG_PC
|| rs
== REG_SP
)
18459 if (subtract
|| value
& ~0x3fc)
18460 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18461 _("invalid immediate for address calculation (value = 0x%08lX)"),
18462 (unsigned long) value
);
18463 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
18465 newval
|= value
>> 2;
18470 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18471 _("immediate value out of range"));
18472 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
18473 newval
|= (rd
<< 8) | value
;
18478 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18479 _("immediate value out of range"));
18480 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
18481 newval
|= rd
| (rs
<< 3) | (value
<< 6);
18484 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18487 case BFD_RELOC_ARM_THUMB_IMM
:
18488 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18489 if (value
< 0 || value
> 255)
18490 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18491 _("invalid immediate: %ld is too large"),
18494 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18497 case BFD_RELOC_ARM_THUMB_SHIFT
:
18498 /* 5bit shift value (0..32). LSL cannot take 32. */
18499 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
18500 temp
= newval
& 0xf800;
18501 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
18502 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18503 _("invalid shift value: %ld"), (long) value
);
18504 /* Shifts of zero must be encoded as LSL. */
18506 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
18507 /* Shifts of 32 are encoded as zero. */
18508 else if (value
== 32)
18510 newval
|= value
<< 6;
18511 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18514 case BFD_RELOC_VTABLE_INHERIT
:
18515 case BFD_RELOC_VTABLE_ENTRY
:
18519 case BFD_RELOC_ARM_MOVW
:
18520 case BFD_RELOC_ARM_MOVT
:
18521 case BFD_RELOC_ARM_THUMB_MOVW
:
18522 case BFD_RELOC_ARM_THUMB_MOVT
:
18523 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18525 /* REL format relocations are limited to a 16-bit addend. */
18526 if (!fixP
->fx_done
)
18528 if (value
< -0x1000 || value
> 0xffff)
18529 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18530 _("offset too big"));
18532 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
18533 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18538 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
18539 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18541 newval
= get_thumb32_insn (buf
);
18542 newval
&= 0xfbf08f00;
18543 newval
|= (value
& 0xf000) << 4;
18544 newval
|= (value
& 0x0800) << 15;
18545 newval
|= (value
& 0x0700) << 4;
18546 newval
|= (value
& 0x00ff);
18547 put_thumb32_insn (buf
, newval
);
18551 newval
= md_chars_to_number (buf
, 4);
18552 newval
&= 0xfff0f000;
18553 newval
|= value
& 0x0fff;
18554 newval
|= (value
& 0xf000) << 4;
18555 md_number_to_chars (buf
, newval
, 4);
18560 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
18561 case BFD_RELOC_ARM_ALU_PC_G0
:
18562 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
18563 case BFD_RELOC_ARM_ALU_PC_G1
:
18564 case BFD_RELOC_ARM_ALU_PC_G2
:
18565 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
18566 case BFD_RELOC_ARM_ALU_SB_G0
:
18567 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
18568 case BFD_RELOC_ARM_ALU_SB_G1
:
18569 case BFD_RELOC_ARM_ALU_SB_G2
:
18570 assert (!fixP
->fx_done
);
18571 if (!seg
->use_rela_p
)
18574 bfd_vma encoded_addend
;
18575 bfd_vma addend_abs
= abs (value
);
18577 /* Check that the absolute value of the addend can be
18578 expressed as an 8-bit constant plus a rotation. */
18579 encoded_addend
= encode_arm_immediate (addend_abs
);
18580 if (encoded_addend
== (unsigned int) FAIL
)
18581 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18582 _("the offset 0x%08lX is not representable"),
18585 /* Extract the instruction. */
18586 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18588 /* If the addend is positive, use an ADD instruction.
18589 Otherwise use a SUB. Take care not to destroy the S bit. */
18590 insn
&= 0xff1fffff;
18596 /* Place the encoded addend into the first 12 bits of the
18598 insn
&= 0xfffff000;
18599 insn
|= encoded_addend
;
18601 /* Update the instruction. */
18602 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18606 case BFD_RELOC_ARM_LDR_PC_G0
:
18607 case BFD_RELOC_ARM_LDR_PC_G1
:
18608 case BFD_RELOC_ARM_LDR_PC_G2
:
18609 case BFD_RELOC_ARM_LDR_SB_G0
:
18610 case BFD_RELOC_ARM_LDR_SB_G1
:
18611 case BFD_RELOC_ARM_LDR_SB_G2
:
18612 assert (!fixP
->fx_done
);
18613 if (!seg
->use_rela_p
)
18616 bfd_vma addend_abs
= abs (value
);
18618 /* Check that the absolute value of the addend can be
18619 encoded in 12 bits. */
18620 if (addend_abs
>= 0x1000)
18621 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18622 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
18625 /* Extract the instruction. */
18626 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18628 /* If the addend is negative, clear bit 23 of the instruction.
18629 Otherwise set it. */
18631 insn
&= ~(1 << 23);
18635 /* Place the absolute value of the addend into the first 12 bits
18636 of the instruction. */
18637 insn
&= 0xfffff000;
18638 insn
|= addend_abs
;
18640 /* Update the instruction. */
18641 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18645 case BFD_RELOC_ARM_LDRS_PC_G0
:
18646 case BFD_RELOC_ARM_LDRS_PC_G1
:
18647 case BFD_RELOC_ARM_LDRS_PC_G2
:
18648 case BFD_RELOC_ARM_LDRS_SB_G0
:
18649 case BFD_RELOC_ARM_LDRS_SB_G1
:
18650 case BFD_RELOC_ARM_LDRS_SB_G2
:
18651 assert (!fixP
->fx_done
);
18652 if (!seg
->use_rela_p
)
18655 bfd_vma addend_abs
= abs (value
);
18657 /* Check that the absolute value of the addend can be
18658 encoded in 8 bits. */
18659 if (addend_abs
>= 0x100)
18660 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18661 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
18664 /* Extract the instruction. */
18665 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18667 /* If the addend is negative, clear bit 23 of the instruction.
18668 Otherwise set it. */
18670 insn
&= ~(1 << 23);
18674 /* Place the first four bits of the absolute value of the addend
18675 into the first 4 bits of the instruction, and the remaining
18676 four into bits 8 .. 11. */
18677 insn
&= 0xfffff0f0;
18678 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
18680 /* Update the instruction. */
18681 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18685 case BFD_RELOC_ARM_LDC_PC_G0
:
18686 case BFD_RELOC_ARM_LDC_PC_G1
:
18687 case BFD_RELOC_ARM_LDC_PC_G2
:
18688 case BFD_RELOC_ARM_LDC_SB_G0
:
18689 case BFD_RELOC_ARM_LDC_SB_G1
:
18690 case BFD_RELOC_ARM_LDC_SB_G2
:
18691 assert (!fixP
->fx_done
);
18692 if (!seg
->use_rela_p
)
18695 bfd_vma addend_abs
= abs (value
);
18697 /* Check that the absolute value of the addend is a multiple of
18698 four and, when divided by four, fits in 8 bits. */
18699 if (addend_abs
& 0x3)
18700 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18701 _("bad offset 0x%08lX (must be word-aligned)"),
18704 if ((addend_abs
>> 2) > 0xff)
18705 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18706 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
18709 /* Extract the instruction. */
18710 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18712 /* If the addend is negative, clear bit 23 of the instruction.
18713 Otherwise set it. */
18715 insn
&= ~(1 << 23);
18719 /* Place the addend (divided by four) into the first eight
18720 bits of the instruction. */
18721 insn
&= 0xfffffff0;
18722 insn
|= addend_abs
>> 2;
18724 /* Update the instruction. */
18725 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18729 case BFD_RELOC_UNUSED
:
18731 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18732 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
18736 /* Translate internal representation of relocation info to BFD target
18740 tc_gen_reloc (asection
*section
, fixS
*fixp
)
18743 bfd_reloc_code_real_type code
;
18745 reloc
= xmalloc (sizeof (arelent
));
18747 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
18748 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18749 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18751 if (fixp
->fx_pcrel
)
18753 if (section
->use_rela_p
)
18754 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
18756 fixp
->fx_offset
= reloc
->address
;
18758 reloc
->addend
= fixp
->fx_offset
;
18760 switch (fixp
->fx_r_type
)
18763 if (fixp
->fx_pcrel
)
18765 code
= BFD_RELOC_8_PCREL
;
18770 if (fixp
->fx_pcrel
)
18772 code
= BFD_RELOC_16_PCREL
;
18777 if (fixp
->fx_pcrel
)
18779 code
= BFD_RELOC_32_PCREL
;
18783 case BFD_RELOC_ARM_MOVW
:
18784 if (fixp
->fx_pcrel
)
18786 code
= BFD_RELOC_ARM_MOVW_PCREL
;
18790 case BFD_RELOC_ARM_MOVT
:
18791 if (fixp
->fx_pcrel
)
18793 code
= BFD_RELOC_ARM_MOVT_PCREL
;
18797 case BFD_RELOC_ARM_THUMB_MOVW
:
18798 if (fixp
->fx_pcrel
)
18800 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
18804 case BFD_RELOC_ARM_THUMB_MOVT
:
18805 if (fixp
->fx_pcrel
)
18807 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
18811 case BFD_RELOC_NONE
:
18812 case BFD_RELOC_ARM_PCREL_BRANCH
:
18813 case BFD_RELOC_ARM_PCREL_BLX
:
18814 case BFD_RELOC_RVA
:
18815 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
18816 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
18817 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
18818 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
18819 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
18820 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
18821 case BFD_RELOC_THUMB_PCREL_BLX
:
18822 case BFD_RELOC_VTABLE_ENTRY
:
18823 case BFD_RELOC_VTABLE_INHERIT
:
18825 case BFD_RELOC_32_SECREL
:
18827 code
= fixp
->fx_r_type
;
18830 case BFD_RELOC_ARM_LITERAL
:
18831 case BFD_RELOC_ARM_HWLITERAL
:
18832 /* If this is called then the a literal has
18833 been referenced across a section boundary. */
18834 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18835 _("literal referenced across section boundary"));
18839 case BFD_RELOC_ARM_GOT32
:
18840 case BFD_RELOC_ARM_GOTOFF
:
18841 case BFD_RELOC_ARM_PLT32
:
18842 case BFD_RELOC_ARM_TARGET1
:
18843 case BFD_RELOC_ARM_ROSEGREL32
:
18844 case BFD_RELOC_ARM_SBREL32
:
18845 case BFD_RELOC_ARM_PREL31
:
18846 case BFD_RELOC_ARM_TARGET2
:
18847 case BFD_RELOC_ARM_TLS_LE32
:
18848 case BFD_RELOC_ARM_TLS_LDO32
:
18849 case BFD_RELOC_ARM_PCREL_CALL
:
18850 case BFD_RELOC_ARM_PCREL_JUMP
:
18851 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
18852 case BFD_RELOC_ARM_ALU_PC_G0
:
18853 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
18854 case BFD_RELOC_ARM_ALU_PC_G1
:
18855 case BFD_RELOC_ARM_ALU_PC_G2
:
18856 case BFD_RELOC_ARM_LDR_PC_G0
:
18857 case BFD_RELOC_ARM_LDR_PC_G1
:
18858 case BFD_RELOC_ARM_LDR_PC_G2
:
18859 case BFD_RELOC_ARM_LDRS_PC_G0
:
18860 case BFD_RELOC_ARM_LDRS_PC_G1
:
18861 case BFD_RELOC_ARM_LDRS_PC_G2
:
18862 case BFD_RELOC_ARM_LDC_PC_G0
:
18863 case BFD_RELOC_ARM_LDC_PC_G1
:
18864 case BFD_RELOC_ARM_LDC_PC_G2
:
18865 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
18866 case BFD_RELOC_ARM_ALU_SB_G0
:
18867 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
18868 case BFD_RELOC_ARM_ALU_SB_G1
:
18869 case BFD_RELOC_ARM_ALU_SB_G2
:
18870 case BFD_RELOC_ARM_LDR_SB_G0
:
18871 case BFD_RELOC_ARM_LDR_SB_G1
:
18872 case BFD_RELOC_ARM_LDR_SB_G2
:
18873 case BFD_RELOC_ARM_LDRS_SB_G0
:
18874 case BFD_RELOC_ARM_LDRS_SB_G1
:
18875 case BFD_RELOC_ARM_LDRS_SB_G2
:
18876 case BFD_RELOC_ARM_LDC_SB_G0
:
18877 case BFD_RELOC_ARM_LDC_SB_G1
:
18878 case BFD_RELOC_ARM_LDC_SB_G2
:
18879 code
= fixp
->fx_r_type
;
18882 case BFD_RELOC_ARM_TLS_GD32
:
18883 case BFD_RELOC_ARM_TLS_IE32
:
18884 case BFD_RELOC_ARM_TLS_LDM32
:
18885 /* BFD will include the symbol's address in the addend.
18886 But we don't want that, so subtract it out again here. */
18887 if (!S_IS_COMMON (fixp
->fx_addsy
))
18888 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
18889 code
= fixp
->fx_r_type
;
18893 case BFD_RELOC_ARM_IMMEDIATE
:
18894 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18895 _("internal relocation (type: IMMEDIATE) not fixed up"));
18898 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
18899 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18900 _("ADRL used for a symbol not defined in the same file"));
18903 case BFD_RELOC_ARM_OFFSET_IMM
:
18904 if (section
->use_rela_p
)
18906 code
= fixp
->fx_r_type
;
18910 if (fixp
->fx_addsy
!= NULL
18911 && !S_IS_DEFINED (fixp
->fx_addsy
)
18912 && S_IS_LOCAL (fixp
->fx_addsy
))
18914 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18915 _("undefined local label `%s'"),
18916 S_GET_NAME (fixp
->fx_addsy
));
18920 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18921 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
18928 switch (fixp
->fx_r_type
)
18930 case BFD_RELOC_NONE
: type
= "NONE"; break;
18931 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
18932 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
18933 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
18934 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
18935 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
18936 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
18937 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
18938 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
18939 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
18940 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
18941 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
18942 default: type
= _("<unknown>"); break;
18944 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18945 _("cannot represent %s relocation in this object file format"),
18952 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
18954 && fixp
->fx_addsy
== GOT_symbol
)
18956 code
= BFD_RELOC_ARM_GOTPC
;
18957 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
18961 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18963 if (reloc
->howto
== NULL
)
18965 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18966 _("cannot represent %s relocation in this object file format"),
18967 bfd_get_reloc_code_name (code
));
18971 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
18972 vtable entry to be used in the relocation's section offset. */
18973 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18974 reloc
->address
= fixp
->fx_offset
;
18979 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
18982 cons_fix_new_arm (fragS
* frag
,
18987 bfd_reloc_code_real_type type
;
18991 FIXME: @@ Should look at CPU word size. */
18995 type
= BFD_RELOC_8
;
18998 type
= BFD_RELOC_16
;
19002 type
= BFD_RELOC_32
;
19005 type
= BFD_RELOC_64
;
19010 if (exp
->X_op
== O_secrel
)
19012 exp
->X_op
= O_symbol
;
19013 type
= BFD_RELOC_32_SECREL
;
19017 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
19020 #if defined OBJ_COFF || defined OBJ_ELF
19022 arm_validate_fix (fixS
* fixP
)
19024 /* If the destination of the branch is a defined symbol which does not have
19025 the THUMB_FUNC attribute, then we must be calling a function which has
19026 the (interfacearm) attribute. We look for the Thumb entry point to that
19027 function and change the branch to refer to that function instead. */
19028 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
19029 && fixP
->fx_addsy
!= NULL
19030 && S_IS_DEFINED (fixP
->fx_addsy
)
19031 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
19033 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
19039 arm_force_relocation (struct fix
* fixp
)
19041 #if defined (OBJ_COFF) && defined (TE_PE)
19042 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
19046 /* Resolve these relocations even if the symbol is extern or weak. */
19047 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
19048 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
19049 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
19050 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
19051 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
19052 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
19053 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
19056 /* Always leave these relocations for the linker. */
19057 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
19058 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
19059 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
19062 /* Always generate relocations against function symbols. */
19063 if (fixp
->fx_r_type
== BFD_RELOC_32
19065 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
19068 return generic_force_reloc (fixp
);
19071 #if defined (OBJ_ELF) || defined (OBJ_COFF)
19072 /* Relocations against function names must be left unadjusted,
19073 so that the linker can use this information to generate interworking
19074 stubs. The MIPS version of this function
19075 also prevents relocations that are mips-16 specific, but I do not
19076 know why it does this.
19079 There is one other problem that ought to be addressed here, but
19080 which currently is not: Taking the address of a label (rather
19081 than a function) and then later jumping to that address. Such
19082 addresses also ought to have their bottom bit set (assuming that
19083 they reside in Thumb code), but at the moment they will not. */
19086 arm_fix_adjustable (fixS
* fixP
)
19088 if (fixP
->fx_addsy
== NULL
)
19091 /* Preserve relocations against symbols with function type. */
19092 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
19095 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
19096 && fixP
->fx_subsy
== NULL
)
19099 /* We need the symbol name for the VTABLE entries. */
19100 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
19101 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
19104 /* Don't allow symbols to be discarded on GOT related relocs. */
19105 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
19106 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
19107 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
19108 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
19109 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
19110 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
19111 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
19112 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
19113 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
19116 /* Similarly for group relocations. */
19117 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
19118 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
19119 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
19124 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
19129 elf32_arm_target_format (void)
19132 return (target_big_endian
19133 ? "elf32-bigarm-symbian"
19134 : "elf32-littlearm-symbian");
19135 #elif defined (TE_VXWORKS)
19136 return (target_big_endian
19137 ? "elf32-bigarm-vxworks"
19138 : "elf32-littlearm-vxworks");
19140 if (target_big_endian
)
19141 return "elf32-bigarm";
19143 return "elf32-littlearm";
19148 armelf_frob_symbol (symbolS
* symp
,
19151 elf_frob_symbol (symp
, puntp
);
19155 /* MD interface: Finalization. */
19157 /* A good place to do this, although this was probably not intended
19158 for this kind of use. We need to dump the literal pool before
19159 references are made to a null symbol pointer. */
19164 literal_pool
* pool
;
19166 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
19168 /* Put it at the end of the relevent section. */
19169 subseg_set (pool
->section
, pool
->sub_section
);
19171 arm_elf_change_section ();
19177 /* Adjust the symbol table. This marks Thumb symbols as distinct from
19181 arm_adjust_symtab (void)
19186 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
19188 if (ARM_IS_THUMB (sym
))
19190 if (THUMB_IS_FUNC (sym
))
19192 /* Mark the symbol as a Thumb function. */
19193 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
19194 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
19195 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
19197 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
19198 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
19200 as_bad (_("%s: unexpected function type: %d"),
19201 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
19203 else switch (S_GET_STORAGE_CLASS (sym
))
19206 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
19209 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
19212 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
19220 if (ARM_IS_INTERWORK (sym
))
19221 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
19228 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
19230 if (ARM_IS_THUMB (sym
))
19232 elf_symbol_type
* elf_sym
;
19234 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
19235 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
19237 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
19238 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
19240 /* If it's a .thumb_func, declare it as so,
19241 otherwise tag label as .code 16. */
19242 if (THUMB_IS_FUNC (sym
))
19243 elf_sym
->internal_elf_sym
.st_info
=
19244 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
19245 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
19246 elf_sym
->internal_elf_sym
.st_info
=
19247 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
19254 /* MD interface: Initialization. */
19257 set_constant_flonums (void)
19261 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
19262 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
19266 /* Auto-select Thumb mode if it's the only available instruction set for the
19267 given architecture. */
19270 autoselect_thumb_from_cpu_variant (void)
19272 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
19273 opcode_select (16);
19282 if ( (arm_ops_hsh
= hash_new ()) == NULL
19283 || (arm_cond_hsh
= hash_new ()) == NULL
19284 || (arm_shift_hsh
= hash_new ()) == NULL
19285 || (arm_psr_hsh
= hash_new ()) == NULL
19286 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
19287 || (arm_reg_hsh
= hash_new ()) == NULL
19288 || (arm_reloc_hsh
= hash_new ()) == NULL
19289 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
19290 as_fatal (_("virtual memory exhausted"));
19292 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
19293 hash_insert (arm_ops_hsh
, insns
[i
].template, (PTR
) (insns
+ i
));
19294 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
19295 hash_insert (arm_cond_hsh
, conds
[i
].template, (PTR
) (conds
+ i
));
19296 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
19297 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (PTR
) (shift_names
+ i
));
19298 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
19299 hash_insert (arm_psr_hsh
, psrs
[i
].template, (PTR
) (psrs
+ i
));
19300 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
19301 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template, (PTR
) (v7m_psrs
+ i
));
19302 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
19303 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (PTR
) (reg_names
+ i
));
19305 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
19307 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template,
19308 (PTR
) (barrier_opt_names
+ i
));
19310 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
19311 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (PTR
) (reloc_names
+ i
));
19314 set_constant_flonums ();
19316 /* Set the cpu variant based on the command-line options. We prefer
19317 -mcpu= over -march= if both are set (as for GCC); and we prefer
19318 -mfpu= over any other way of setting the floating point unit.
19319 Use of legacy options with new options are faulted. */
19322 if (mcpu_cpu_opt
|| march_cpu_opt
)
19323 as_bad (_("use of old and new-style options to set CPU type"));
19325 mcpu_cpu_opt
= legacy_cpu
;
19327 else if (!mcpu_cpu_opt
)
19328 mcpu_cpu_opt
= march_cpu_opt
;
19333 as_bad (_("use of old and new-style options to set FPU type"));
19335 mfpu_opt
= legacy_fpu
;
19337 else if (!mfpu_opt
)
19339 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
19340 /* Some environments specify a default FPU. If they don't, infer it
19341 from the processor. */
19343 mfpu_opt
= mcpu_fpu_opt
;
19345 mfpu_opt
= march_fpu_opt
;
19347 mfpu_opt
= &fpu_default
;
19353 if (mcpu_cpu_opt
!= NULL
)
19354 mfpu_opt
= &fpu_default
;
19355 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
19356 mfpu_opt
= &fpu_arch_vfp_v2
;
19358 mfpu_opt
= &fpu_arch_fpa
;
19364 mcpu_cpu_opt
= &cpu_default
;
19365 selected_cpu
= cpu_default
;
19369 selected_cpu
= *mcpu_cpu_opt
;
19371 mcpu_cpu_opt
= &arm_arch_any
;
19374 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
19376 autoselect_thumb_from_cpu_variant ();
19378 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
19380 #if defined OBJ_COFF || defined OBJ_ELF
19382 unsigned int flags
= 0;
19384 #if defined OBJ_ELF
19385 flags
= meabi_flags
;
19387 switch (meabi_flags
)
19389 case EF_ARM_EABI_UNKNOWN
:
19391 /* Set the flags in the private structure. */
19392 if (uses_apcs_26
) flags
|= F_APCS26
;
19393 if (support_interwork
) flags
|= F_INTERWORK
;
19394 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
19395 if (pic_code
) flags
|= F_PIC
;
19396 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
19397 flags
|= F_SOFT_FLOAT
;
19399 switch (mfloat_abi_opt
)
19401 case ARM_FLOAT_ABI_SOFT
:
19402 case ARM_FLOAT_ABI_SOFTFP
:
19403 flags
|= F_SOFT_FLOAT
;
19406 case ARM_FLOAT_ABI_HARD
:
19407 if (flags
& F_SOFT_FLOAT
)
19408 as_bad (_("hard-float conflicts with specified fpu"));
19412 /* Using pure-endian doubles (even if soft-float). */
19413 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
19414 flags
|= F_VFP_FLOAT
;
19416 #if defined OBJ_ELF
19417 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
19418 flags
|= EF_ARM_MAVERICK_FLOAT
;
19421 case EF_ARM_EABI_VER4
:
19422 case EF_ARM_EABI_VER5
:
19423 /* No additional flags to set. */
19430 bfd_set_private_flags (stdoutput
, flags
);
19432 /* We have run out flags in the COFF header to encode the
19433 status of ATPCS support, so instead we create a dummy,
19434 empty, debug section called .arm.atpcs. */
19439 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
19443 bfd_set_section_flags
19444 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
19445 bfd_set_section_size (stdoutput
, sec
, 0);
19446 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
19452 /* Record the CPU type as well. */
19453 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
19454 mach
= bfd_mach_arm_iWMMXt2
;
19455 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
19456 mach
= bfd_mach_arm_iWMMXt
;
19457 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
19458 mach
= bfd_mach_arm_XScale
;
19459 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
19460 mach
= bfd_mach_arm_ep9312
;
19461 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
19462 mach
= bfd_mach_arm_5TE
;
19463 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
19465 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19466 mach
= bfd_mach_arm_5T
;
19468 mach
= bfd_mach_arm_5
;
19470 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
19472 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19473 mach
= bfd_mach_arm_4T
;
19475 mach
= bfd_mach_arm_4
;
19477 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
19478 mach
= bfd_mach_arm_3M
;
19479 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
19480 mach
= bfd_mach_arm_3
;
19481 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
19482 mach
= bfd_mach_arm_2a
;
19483 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
19484 mach
= bfd_mach_arm_2
;
19486 mach
= bfd_mach_arm_unknown
;
19488 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
19491 /* Command line processing. */
19494 Invocation line includes a switch not recognized by the base assembler.
19495 See if it's a processor-specific option.
19497 This routine is somewhat complicated by the need for backwards
19498 compatibility (since older releases of gcc can't be changed).
19499 The new options try to make the interface as compatible as
19502 New options (supported) are:
19504 -mcpu=<cpu name> Assemble for selected processor
19505 -march=<architecture name> Assemble for selected architecture
19506 -mfpu=<fpu architecture> Assemble for selected FPU.
19507 -EB/-mbig-endian Big-endian
19508 -EL/-mlittle-endian Little-endian
19509 -k Generate PIC code
19510 -mthumb Start in Thumb mode
19511 -mthumb-interwork Code supports ARM/Thumb interworking
19513 For now we will also provide support for:
19515 -mapcs-32 32-bit Program counter
19516 -mapcs-26 26-bit Program counter
19517 -macps-float Floats passed in FP registers
19518 -mapcs-reentrant Reentrant code
19520 (sometime these will probably be replaced with -mapcs=<list of options>
19521 and -matpcs=<list of options>)
19523 The remaining options are only supported for back-wards compatibility.
19524 Cpu variants, the arm part is optional:
19525 -m[arm]1 Currently not supported.
19526 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
19527 -m[arm]3 Arm 3 processor
19528 -m[arm]6[xx], Arm 6 processors
19529 -m[arm]7[xx][t][[d]m] Arm 7 processors
19530 -m[arm]8[10] Arm 8 processors
19531 -m[arm]9[20][tdmi] Arm 9 processors
19532 -mstrongarm[110[0]] StrongARM processors
19533 -mxscale XScale processors
19534 -m[arm]v[2345[t[e]]] Arm architectures
19535 -mall All (except the ARM1)
19537 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
19538 -mfpe-old (No float load/store multiples)
19539 -mvfpxd VFP Single precision
19541 -mno-fpu Disable all floating point instructions
19543 The following CPU names are recognized:
19544 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
19545 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
19546 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
19547 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
19548 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
19549 arm10t arm10e, arm1020t, arm1020e, arm10200e,
19550 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
19554 const char * md_shortopts
= "m:k";
19556 #ifdef ARM_BI_ENDIAN
19557 #define OPTION_EB (OPTION_MD_BASE + 0)
19558 #define OPTION_EL (OPTION_MD_BASE + 1)
19560 #if TARGET_BYTES_BIG_ENDIAN
19561 #define OPTION_EB (OPTION_MD_BASE + 0)
19563 #define OPTION_EL (OPTION_MD_BASE + 1)
19567 struct option md_longopts
[] =
19570 {"EB", no_argument
, NULL
, OPTION_EB
},
19573 {"EL", no_argument
, NULL
, OPTION_EL
},
19575 {NULL
, no_argument
, NULL
, 0}
19578 size_t md_longopts_size
= sizeof (md_longopts
);
19580 struct arm_option_table
19582 char *option
; /* Option name to match. */
19583 char *help
; /* Help information. */
19584 int *var
; /* Variable to change. */
19585 int value
; /* What to change it to. */
19586 char *deprecated
; /* If non-null, print this message. */
19589 struct arm_option_table arm_opts
[] =
19591 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
19592 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
19593 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
19594 &support_interwork
, 1, NULL
},
19595 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
19596 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
19597 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
19599 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
19600 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
19601 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
19602 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
19605 /* These are recognized by the assembler, but have no affect on code. */
19606 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
19607 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
19608 {NULL
, NULL
, NULL
, 0, NULL
}
19611 struct arm_legacy_option_table
19613 char *option
; /* Option name to match. */
19614 const arm_feature_set
**var
; /* Variable to change. */
19615 const arm_feature_set value
; /* What to change it to. */
19616 char *deprecated
; /* If non-null, print this message. */
19619 const struct arm_legacy_option_table arm_legacy_opts
[] =
19621 /* DON'T add any new processors to this list -- we want the whole list
19622 to go away... Add them to the processors table instead. */
19623 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19624 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19625 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19626 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19627 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19628 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19629 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19630 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19631 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19632 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19633 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19634 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19635 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19636 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19637 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19638 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19639 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19640 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19641 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19642 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19643 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19644 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19645 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19646 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19647 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19648 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19649 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19650 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19651 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19652 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19653 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19654 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19655 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19656 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19657 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19658 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19659 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19660 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19661 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19662 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19663 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19664 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19665 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19666 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19667 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19668 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19669 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19670 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19671 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19672 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19673 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19674 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19675 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19676 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19677 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19678 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19679 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19680 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19681 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19682 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19683 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19684 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19685 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19686 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19687 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19688 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19689 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19690 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19691 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
19692 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
19693 N_("use -mcpu=strongarm110")},
19694 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
19695 N_("use -mcpu=strongarm1100")},
19696 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
19697 N_("use -mcpu=strongarm1110")},
19698 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
19699 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
19700 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
19702 /* Architecture variants -- don't add any more to this list either. */
19703 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19704 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19705 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19706 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19707 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19708 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19709 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19710 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19711 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19712 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19713 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
19714 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
19715 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
19716 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
19717 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
19718 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
19719 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
19720 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
19722 /* Floating point variants -- don't add any more to this list either. */
19723 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
19724 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
19725 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
19726 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
19727 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
19729 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
19732 struct arm_cpu_option_table
19735 const arm_feature_set value
;
19736 /* For some CPUs we assume an FPU unless the user explicitly sets
19738 const arm_feature_set default_fpu
;
19739 /* The canonical name of the CPU, or NULL to use NAME converted to upper
19741 const char *canonical_name
;
19744 /* This list should, at a minimum, contain all the cpu names
19745 recognized by GCC. */
19746 static const struct arm_cpu_option_table arm_cpus
[] =
19748 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
19749 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
19750 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
19751 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
19752 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
19753 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19754 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19755 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19756 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19757 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19758 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19759 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
19760 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19761 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
19762 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19763 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
19764 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19765 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19766 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19767 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19768 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19769 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19770 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19771 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19772 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19773 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19774 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19775 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19776 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19777 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19778 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19779 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19780 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19781 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19782 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19783 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19784 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19785 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19786 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19787 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
19788 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19789 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19790 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19791 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19792 /* For V5 or later processors we default to using VFP; but the user
19793 should really set the FPU type explicitly. */
19794 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
19795 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19796 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
19797 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
19798 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
19799 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
19800 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
19801 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19802 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
19803 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
19804 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19805 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19806 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
19807 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
19808 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19809 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
19810 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
19811 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19812 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19813 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
19814 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
19815 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
19816 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
19817 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
19818 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
19819 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
19820 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
19821 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
19822 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
19823 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
19824 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
19825 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE(0, FPU_VFP_V3
19826 | FPU_NEON_EXT_V1
),
19828 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
19829 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
19830 /* ??? XSCALE is really an architecture. */
19831 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
19832 /* ??? iwmmxt is not a processor. */
19833 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
19834 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
19835 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
19837 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
19838 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
19841 struct arm_arch_option_table
19844 const arm_feature_set value
;
19845 const arm_feature_set default_fpu
;
19848 /* This list should, at a minimum, contain all the architecture names
19849 recognized by GCC. */
19850 static const struct arm_arch_option_table arm_archs
[] =
19852 {"all", ARM_ANY
, FPU_ARCH_FPA
},
19853 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
19854 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
19855 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
19856 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
19857 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
19858 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
19859 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
19860 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
19861 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
19862 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
19863 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
19864 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
19865 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
19866 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
19867 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
19868 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
19869 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
19870 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
19871 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
19872 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
19873 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
19874 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
19875 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
19876 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
19877 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
19878 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
19879 /* The official spelling of the ARMv7 profile variants is the dashed form.
19880 Accept the non-dashed form for compatibility with old toolchains. */
19881 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
19882 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
19883 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
19884 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
19885 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
19886 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
19887 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
19888 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
19889 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
19890 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
19893 /* ISA extensions in the co-processor space. */
19894 struct arm_option_cpu_value_table
19897 const arm_feature_set value
;
19900 static const struct arm_option_cpu_value_table arm_extensions
[] =
19902 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
19903 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
19904 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
19905 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
19906 {NULL
, ARM_ARCH_NONE
}
19909 /* This list should, at a minimum, contain all the fpu names
19910 recognized by GCC. */
19911 static const struct arm_option_cpu_value_table arm_fpus
[] =
19913 {"softfpa", FPU_NONE
},
19914 {"fpe", FPU_ARCH_FPE
},
19915 {"fpe2", FPU_ARCH_FPE
},
19916 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
19917 {"fpa", FPU_ARCH_FPA
},
19918 {"fpa10", FPU_ARCH_FPA
},
19919 {"fpa11", FPU_ARCH_FPA
},
19920 {"arm7500fe", FPU_ARCH_FPA
},
19921 {"softvfp", FPU_ARCH_VFP
},
19922 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
19923 {"vfp", FPU_ARCH_VFP_V2
},
19924 {"vfp9", FPU_ARCH_VFP_V2
},
19925 {"vfp3", FPU_ARCH_VFP_V3
},
19926 {"vfp10", FPU_ARCH_VFP_V2
},
19927 {"vfp10-r0", FPU_ARCH_VFP_V1
},
19928 {"vfpxd", FPU_ARCH_VFP_V1xD
},
19929 {"arm1020t", FPU_ARCH_VFP_V1
},
19930 {"arm1020e", FPU_ARCH_VFP_V2
},
19931 {"arm1136jfs", FPU_ARCH_VFP_V2
},
19932 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
19933 {"maverick", FPU_ARCH_MAVERICK
},
19934 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
19935 {NULL
, ARM_ARCH_NONE
}
19938 struct arm_option_value_table
19944 static const struct arm_option_value_table arm_float_abis
[] =
19946 {"hard", ARM_FLOAT_ABI_HARD
},
19947 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
19948 {"soft", ARM_FLOAT_ABI_SOFT
},
19953 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
19954 static const struct arm_option_value_table arm_eabis
[] =
19956 {"gnu", EF_ARM_EABI_UNKNOWN
},
19957 {"4", EF_ARM_EABI_VER4
},
19958 {"5", EF_ARM_EABI_VER5
},
19963 struct arm_long_option_table
19965 char * option
; /* Substring to match. */
19966 char * help
; /* Help information. */
19967 int (* func
) (char * subopt
); /* Function to decode sub-option. */
19968 char * deprecated
; /* If non-null, print this message. */
19972 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
19974 arm_feature_set
*ext_set
= xmalloc (sizeof (arm_feature_set
));
19976 /* Copy the feature set, so that we can modify it. */
19977 *ext_set
= **opt_p
;
19980 while (str
!= NULL
&& *str
!= 0)
19982 const struct arm_option_cpu_value_table
* opt
;
19988 as_bad (_("invalid architectural extension"));
19993 ext
= strchr (str
, '+');
19996 optlen
= ext
- str
;
19998 optlen
= strlen (str
);
20002 as_bad (_("missing architectural extension"));
20006 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
20007 if (strncmp (opt
->name
, str
, optlen
) == 0)
20009 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
20013 if (opt
->name
== NULL
)
20015 as_bad (_("unknown architectural extnsion `%s'"), str
);
20026 arm_parse_cpu (char * str
)
20028 const struct arm_cpu_option_table
* opt
;
20029 char * ext
= strchr (str
, '+');
20033 optlen
= ext
- str
;
20035 optlen
= strlen (str
);
20039 as_bad (_("missing cpu name `%s'"), str
);
20043 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
20044 if (strncmp (opt
->name
, str
, optlen
) == 0)
20046 mcpu_cpu_opt
= &opt
->value
;
20047 mcpu_fpu_opt
= &opt
->default_fpu
;
20048 if (opt
->canonical_name
)
20049 strcpy(selected_cpu_name
, opt
->canonical_name
);
20053 for (i
= 0; i
< optlen
; i
++)
20054 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20055 selected_cpu_name
[i
] = 0;
20059 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
20064 as_bad (_("unknown cpu `%s'"), str
);
20069 arm_parse_arch (char * str
)
20071 const struct arm_arch_option_table
*opt
;
20072 char *ext
= strchr (str
, '+');
20076 optlen
= ext
- str
;
20078 optlen
= strlen (str
);
20082 as_bad (_("missing architecture name `%s'"), str
);
20086 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
20087 if (streq (opt
->name
, str
))
20089 march_cpu_opt
= &opt
->value
;
20090 march_fpu_opt
= &opt
->default_fpu
;
20091 strcpy(selected_cpu_name
, opt
->name
);
20094 return arm_parse_extension (ext
, &march_cpu_opt
);
20099 as_bad (_("unknown architecture `%s'\n"), str
);
20104 arm_parse_fpu (char * str
)
20106 const struct arm_option_cpu_value_table
* opt
;
20108 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
20109 if (streq (opt
->name
, str
))
20111 mfpu_opt
= &opt
->value
;
20115 as_bad (_("unknown floating point format `%s'\n"), str
);
20120 arm_parse_float_abi (char * str
)
20122 const struct arm_option_value_table
* opt
;
20124 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
20125 if (streq (opt
->name
, str
))
20127 mfloat_abi_opt
= opt
->value
;
20131 as_bad (_("unknown floating point abi `%s'\n"), str
);
20137 arm_parse_eabi (char * str
)
20139 const struct arm_option_value_table
*opt
;
20141 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
20142 if (streq (opt
->name
, str
))
20144 meabi_flags
= opt
->value
;
20147 as_bad (_("unknown EABI `%s'\n"), str
);
20152 struct arm_long_option_table arm_long_opts
[] =
20154 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
20155 arm_parse_cpu
, NULL
},
20156 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
20157 arm_parse_arch
, NULL
},
20158 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
20159 arm_parse_fpu
, NULL
},
20160 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
20161 arm_parse_float_abi
, NULL
},
20163 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
20164 arm_parse_eabi
, NULL
},
20166 {NULL
, NULL
, 0, NULL
}
20170 md_parse_option (int c
, char * arg
)
20172 struct arm_option_table
*opt
;
20173 const struct arm_legacy_option_table
*fopt
;
20174 struct arm_long_option_table
*lopt
;
20180 target_big_endian
= 1;
20186 target_big_endian
= 0;
20191 /* Listing option. Just ignore these, we don't support additional
20196 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
20198 if (c
== opt
->option
[0]
20199 && ((arg
== NULL
&& opt
->option
[1] == 0)
20200 || streq (arg
, opt
->option
+ 1)))
20202 #if WARN_DEPRECATED
20203 /* If the option is deprecated, tell the user. */
20204 if (opt
->deprecated
!= NULL
)
20205 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
20206 arg
? arg
: "", _(opt
->deprecated
));
20209 if (opt
->var
!= NULL
)
20210 *opt
->var
= opt
->value
;
20216 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
20218 if (c
== fopt
->option
[0]
20219 && ((arg
== NULL
&& fopt
->option
[1] == 0)
20220 || streq (arg
, fopt
->option
+ 1)))
20222 #if WARN_DEPRECATED
20223 /* If the option is deprecated, tell the user. */
20224 if (fopt
->deprecated
!= NULL
)
20225 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
20226 arg
? arg
: "", _(fopt
->deprecated
));
20229 if (fopt
->var
!= NULL
)
20230 *fopt
->var
= &fopt
->value
;
20236 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
20238 /* These options are expected to have an argument. */
20239 if (c
== lopt
->option
[0]
20241 && strncmp (arg
, lopt
->option
+ 1,
20242 strlen (lopt
->option
+ 1)) == 0)
20244 #if WARN_DEPRECATED
20245 /* If the option is deprecated, tell the user. */
20246 if (lopt
->deprecated
!= NULL
)
20247 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
20248 _(lopt
->deprecated
));
20251 /* Call the sup-option parser. */
20252 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
20263 md_show_usage (FILE * fp
)
20265 struct arm_option_table
*opt
;
20266 struct arm_long_option_table
*lopt
;
20268 fprintf (fp
, _(" ARM-specific assembler options:\n"));
20270 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
20271 if (opt
->help
!= NULL
)
20272 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
20274 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
20275 if (lopt
->help
!= NULL
)
20276 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
20280 -EB assemble code for a big-endian cpu\n"));
20285 -EL assemble code for a little-endian cpu\n"));
20294 arm_feature_set flags
;
20295 } cpu_arch_ver_table
;
20297 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
20298 least features first. */
20299 static const cpu_arch_ver_table cpu_arch_ver
[] =
20304 {4, ARM_ARCH_V5TE
},
20305 {5, ARM_ARCH_V5TEJ
},
20309 {9, ARM_ARCH_V6T2
},
20310 {10, ARM_ARCH_V7A
},
20311 {10, ARM_ARCH_V7R
},
20312 {10, ARM_ARCH_V7M
},
20316 /* Set the public EABI object attributes. */
20318 aeabi_set_public_attributes (void)
20321 arm_feature_set flags
;
20322 arm_feature_set tmp
;
20323 const cpu_arch_ver_table
*p
;
20325 /* Choose the architecture based on the capabilities of the requested cpu
20326 (if any) and/or the instructions actually used. */
20327 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
20328 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
20329 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
20330 /*Allow the user to override the reported architecture. */
20333 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
20334 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
20339 for (p
= cpu_arch_ver
; p
->val
; p
++)
20341 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
20344 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
20348 /* Tag_CPU_name. */
20349 if (selected_cpu_name
[0])
20353 p
= selected_cpu_name
;
20354 if (strncmp(p
, "armv", 4) == 0)
20359 for (i
= 0; p
[i
]; i
++)
20360 p
[i
] = TOUPPER (p
[i
]);
20362 elf32_arm_add_eabi_attr_string (stdoutput
, 5, p
);
20364 /* Tag_CPU_arch. */
20365 elf32_arm_add_eabi_attr_int (stdoutput
, 6, arch
);
20366 /* Tag_CPU_arch_profile. */
20367 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
20368 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'A');
20369 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
20370 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'R');
20371 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
))
20372 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'M');
20373 /* Tag_ARM_ISA_use. */
20374 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_full
))
20375 elf32_arm_add_eabi_attr_int (stdoutput
, 8, 1);
20376 /* Tag_THUMB_ISA_use. */
20377 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_full
))
20378 elf32_arm_add_eabi_attr_int (stdoutput
, 9,
20379 ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
) ? 2 : 1);
20380 /* Tag_VFP_arch. */
20381 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v3
)
20382 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v3
))
20383 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 3);
20384 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v2
)
20385 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v2
))
20386 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 2);
20387 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1
)
20388 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1
)
20389 || ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1xd
)
20390 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1xd
))
20391 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 1);
20392 /* Tag_WMMX_arch. */
20393 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_cext_iwmmxt
)
20394 || ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_cext_iwmmxt
))
20395 elf32_arm_add_eabi_attr_int (stdoutput
, 11, 1);
20396 /* Tag_NEON_arch. */
20397 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_neon_ext_v1
)
20398 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_neon_ext_v1
))
20399 elf32_arm_add_eabi_attr_int (stdoutput
, 12, 1);
20402 /* Add the .ARM.attributes section. */
20411 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
20414 aeabi_set_public_attributes ();
20415 size
= elf32_arm_eabi_attr_size (stdoutput
);
20416 s
= subseg_new (".ARM.attributes", 0);
20417 bfd_set_section_flags (stdoutput
, s
, SEC_READONLY
| SEC_DATA
);
20418 addr
= frag_now_fix ();
20419 p
= frag_more (size
);
20420 elf32_arm_set_eabi_attr_contents (stdoutput
, (bfd_byte
*)p
, size
);
20422 #endif /* OBJ_ELF */
20425 /* Parse a .cpu directive. */
20428 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
20430 const struct arm_cpu_option_table
*opt
;
20434 name
= input_line_pointer
;
20435 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20436 input_line_pointer
++;
20437 saved_char
= *input_line_pointer
;
20438 *input_line_pointer
= 0;
20440 /* Skip the first "all" entry. */
20441 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
20442 if (streq (opt
->name
, name
))
20444 mcpu_cpu_opt
= &opt
->value
;
20445 selected_cpu
= opt
->value
;
20446 if (opt
->canonical_name
)
20447 strcpy(selected_cpu_name
, opt
->canonical_name
);
20451 for (i
= 0; opt
->name
[i
]; i
++)
20452 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20453 selected_cpu_name
[i
] = 0;
20455 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20456 *input_line_pointer
= saved_char
;
20457 demand_empty_rest_of_line ();
20460 as_bad (_("unknown cpu `%s'"), name
);
20461 *input_line_pointer
= saved_char
;
20462 ignore_rest_of_line ();
20466 /* Parse a .arch directive. */
20469 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
20471 const struct arm_arch_option_table
*opt
;
20475 name
= input_line_pointer
;
20476 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20477 input_line_pointer
++;
20478 saved_char
= *input_line_pointer
;
20479 *input_line_pointer
= 0;
20481 /* Skip the first "all" entry. */
20482 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
20483 if (streq (opt
->name
, name
))
20485 mcpu_cpu_opt
= &opt
->value
;
20486 selected_cpu
= opt
->value
;
20487 strcpy(selected_cpu_name
, opt
->name
);
20488 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20489 *input_line_pointer
= saved_char
;
20490 demand_empty_rest_of_line ();
20494 as_bad (_("unknown architecture `%s'\n"), name
);
20495 *input_line_pointer
= saved_char
;
20496 ignore_rest_of_line ();
20500 /* Parse a .object_arch directive. */
20503 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
20505 const struct arm_arch_option_table
*opt
;
20509 name
= input_line_pointer
;
20510 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20511 input_line_pointer
++;
20512 saved_char
= *input_line_pointer
;
20513 *input_line_pointer
= 0;
20515 /* Skip the first "all" entry. */
20516 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
20517 if (streq (opt
->name
, name
))
20519 object_arch
= &opt
->value
;
20520 *input_line_pointer
= saved_char
;
20521 demand_empty_rest_of_line ();
20525 as_bad (_("unknown architecture `%s'\n"), name
);
20526 *input_line_pointer
= saved_char
;
20527 ignore_rest_of_line ();
20531 /* Parse a .fpu directive. */
20534 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
20536 const struct arm_option_cpu_value_table
*opt
;
20540 name
= input_line_pointer
;
20541 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20542 input_line_pointer
++;
20543 saved_char
= *input_line_pointer
;
20544 *input_line_pointer
= 0;
20546 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
20547 if (streq (opt
->name
, name
))
20549 mfpu_opt
= &opt
->value
;
20550 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20551 *input_line_pointer
= saved_char
;
20552 demand_empty_rest_of_line ();
20556 as_bad (_("unknown floating point format `%s'\n"), name
);
20557 *input_line_pointer
= saved_char
;
20558 ignore_rest_of_line ();
20561 /* Copy symbol information. */
20563 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
20565 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);