1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
45 #define WARN_DEPRECATED 1
48 /* Must be at least the size of the largest unwind opcode (currently two). */
49 #define ARM_OPCODE_CHUNK_SIZE 8
51 /* This structure holds the unwinding state. */
56 symbolS
* table_entry
;
57 symbolS
* personality_routine
;
58 int personality_index
;
59 /* The segment containing the function. */
62 /* Opcodes generated from this function. */
63 unsigned char * opcodes
;
66 /* The number of bytes pushed to the stack. */
68 /* We don't add stack adjustment opcodes immediately so that we can merge
69 multiple adjustments. We can also omit the final adjustment
70 when using a frame pointer. */
71 offsetT pending_offset
;
72 /* These two fields are set by both unwind_movsp and unwind_setfp. They
73 hold the reg+offset to use when restoring sp from a frame pointer. */
76 /* Nonzero if an unwind_setfp directive has been seen. */
78 /* Nonzero if the last opcode restores sp from fp_reg. */
79 unsigned sp_restored
:1;
82 /* Bit N indicates that an R_ARM_NONE relocation has been output for
83 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
84 emitted only once per section, to save unnecessary bloat. */
85 static unsigned int marked_pr_dependency
= 0;
89 /* Results from operand parsing worker functions. */
93 PARSE_OPERAND_SUCCESS
,
95 PARSE_OPERAND_FAIL_NO_BACKTRACK
96 } parse_operand_result
;
101 ARM_FLOAT_ABI_SOFTFP
,
105 /* Types of processor to assemble for. */
107 #if defined __XSCALE__
108 #define CPU_DEFAULT ARM_ARCH_XSCALE
110 #if defined __thumb__
111 #define CPU_DEFAULT ARM_ARCH_V5T
118 # define FPU_DEFAULT FPU_ARCH_FPA
119 # elif defined (TE_NetBSD)
121 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
123 /* Legacy a.out format. */
124 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
126 # elif defined (TE_VXWORKS)
127 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
129 /* For backwards compatibility, default to FPA. */
130 # define FPU_DEFAULT FPU_ARCH_FPA
132 #endif /* ifndef FPU_DEFAULT */
134 #define streq(a, b) (strcmp (a, b) == 0)
136 static arm_feature_set cpu_variant
;
137 static arm_feature_set arm_arch_used
;
138 static arm_feature_set thumb_arch_used
;
140 /* Flags stored in private area of BFD structure. */
141 static int uses_apcs_26
= FALSE
;
142 static int atpcs
= FALSE
;
143 static int support_interwork
= FALSE
;
144 static int uses_apcs_float
= FALSE
;
145 static int pic_code
= FALSE
;
146 static int fix_v4bx
= FALSE
;
148 /* Variables that we set while parsing command-line options. Once all
149 options have been read we re-process these values to set the real
151 static const arm_feature_set
*legacy_cpu
= NULL
;
152 static const arm_feature_set
*legacy_fpu
= NULL
;
154 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
155 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
156 static const arm_feature_set
*march_cpu_opt
= NULL
;
157 static const arm_feature_set
*march_fpu_opt
= NULL
;
158 static const arm_feature_set
*mfpu_opt
= NULL
;
159 static const arm_feature_set
*object_arch
= NULL
;
161 /* Constants for known architecture features. */
162 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
163 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
164 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
165 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
166 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
167 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
168 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
169 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
170 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
173 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
176 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
177 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
178 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
179 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
180 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
181 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
182 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
183 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
184 static const arm_feature_set arm_ext_v4t_5
=
185 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
186 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
187 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
188 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
189 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
190 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
191 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
192 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
193 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
194 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
195 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
196 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
197 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
198 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
199 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
200 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
201 static const arm_feature_set arm_ext_m
=
202 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_V7M
, 0);
204 static const arm_feature_set arm_arch_any
= ARM_ANY
;
205 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
206 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
207 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
209 static const arm_feature_set arm_cext_iwmmxt2
=
210 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
211 static const arm_feature_set arm_cext_iwmmxt
=
212 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
213 static const arm_feature_set arm_cext_xscale
=
214 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
215 static const arm_feature_set arm_cext_maverick
=
216 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
217 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
218 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
219 static const arm_feature_set fpu_vfp_ext_v1xd
=
220 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
221 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
222 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
223 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
224 static const arm_feature_set fpu_vfp_ext_d32
=
225 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
226 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
227 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
228 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
229 static const arm_feature_set fpu_neon_fp16
= ARM_FEATURE (0, FPU_NEON_FP16
);
231 static int mfloat_abi_opt
= -1;
232 /* Record user cpu selection for object attributes. */
233 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
234 /* Must be long enough to hold any of the names in arm_cpus. */
235 static char selected_cpu_name
[16];
238 static int meabi_flags
= EABI_DEFAULT
;
240 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
246 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
251 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
252 symbolS
* GOT_symbol
;
255 /* 0: assemble for ARM,
256 1: assemble for Thumb,
257 2: assemble for Thumb even though target CPU does not support thumb
259 static int thumb_mode
= 0;
261 /* If unified_syntax is true, we are processing the new unified
262 ARM/Thumb syntax. Important differences from the old ARM mode:
264 - Immediate operands do not require a # prefix.
265 - Conditional affixes always appear at the end of the
266 instruction. (For backward compatibility, those instructions
267 that formerly had them in the middle, continue to accept them
269 - The IT instruction may appear, and if it does is validated
270 against subsequent conditional affixes. It does not generate
273 Important differences from the old Thumb mode:
275 - Immediate operands do not require a # prefix.
276 - Most of the V6T2 instructions are only available in unified mode.
277 - The .N and .W suffixes are recognized and honored (it is an error
278 if they cannot be honored).
279 - All instructions set the flags if and only if they have an 's' affix.
280 - Conditional affixes may be used. They are validated against
281 preceding IT instructions. Unlike ARM mode, you cannot use a
282 conditional affix except in the scope of an IT instruction. */
284 static bfd_boolean unified_syntax
= FALSE
;
299 enum neon_el_type type
;
303 #define NEON_MAX_TYPE_ELS 4
307 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
314 unsigned long instruction
;
318 /* "uncond_value" is set to the value in place of the conditional field in
319 unconditional versions of the instruction, or -1 if nothing is
322 struct neon_type vectype
;
323 /* Set to the opcode if the instruction needs relaxation.
324 Zero if the instruction is not relaxed. */
328 bfd_reloc_code_real_type type
;
337 struct neon_type_el vectype
;
338 unsigned present
: 1; /* Operand present. */
339 unsigned isreg
: 1; /* Operand was a register. */
340 unsigned immisreg
: 1; /* .imm field is a second register. */
341 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
342 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
343 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
344 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
345 instructions. This allows us to disambiguate ARM <-> vector insns. */
346 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
347 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
348 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
349 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
350 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
351 unsigned writeback
: 1; /* Operand has trailing ! */
352 unsigned preind
: 1; /* Preindexed address. */
353 unsigned postind
: 1; /* Postindexed address. */
354 unsigned negative
: 1; /* Index register was negated. */
355 unsigned shifted
: 1; /* Shift applied to operation. */
356 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
360 static struct arm_it inst
;
362 #define NUM_FLOAT_VALS 8
364 const char * fp_const
[] =
366 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
369 /* Number of littlenums required to hold an extended precision number. */
370 #define MAX_LITTLENUMS 6
372 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
382 #define CP_T_X 0x00008000
383 #define CP_T_Y 0x00400000
385 #define CONDS_BIT 0x00100000
386 #define LOAD_BIT 0x00100000
388 #define DOUBLE_LOAD_FLAG 0x00000001
392 const char * template;
396 #define COND_ALWAYS 0xE
400 const char *template;
404 struct asm_barrier_opt
406 const char *template;
410 /* The bit that distinguishes CPSR and SPSR. */
411 #define SPSR_BIT (1 << 22)
413 /* The individual PSR flag bits. */
414 #define PSR_c (1 << 16)
415 #define PSR_x (1 << 17)
416 #define PSR_s (1 << 18)
417 #define PSR_f (1 << 19)
422 bfd_reloc_code_real_type reloc
;
427 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
428 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
433 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
436 /* Bits for DEFINED field in neon_typed_alias. */
437 #define NTA_HASTYPE 1
438 #define NTA_HASINDEX 2
440 struct neon_typed_alias
442 unsigned char defined
;
444 struct neon_type_el eltype
;
447 /* ARM register categories. This includes coprocessor numbers and various
448 architecture extensions' registers. */
474 /* Structure for a hash table entry for a register.
475 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
476 information which states whether a vector type or index is specified (for a
477 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
481 unsigned char number
;
483 unsigned char builtin
;
484 struct neon_typed_alias
*neon
;
487 /* Diagnostics used when we don't get a register of the expected type. */
488 const char *const reg_expected_msgs
[] =
490 N_("ARM register expected"),
491 N_("bad or missing co-processor number"),
492 N_("co-processor register expected"),
493 N_("FPA register expected"),
494 N_("VFP single precision register expected"),
495 N_("VFP/Neon double precision register expected"),
496 N_("Neon quad precision register expected"),
497 N_("VFP single or double precision register expected"),
498 N_("Neon double or quad precision register expected"),
499 N_("VFP single, double or Neon quad precision register expected"),
500 N_("VFP system register expected"),
501 N_("Maverick MVF register expected"),
502 N_("Maverick MVD register expected"),
503 N_("Maverick MVFX register expected"),
504 N_("Maverick MVDX register expected"),
505 N_("Maverick MVAX register expected"),
506 N_("Maverick DSPSC register expected"),
507 N_("iWMMXt data register expected"),
508 N_("iWMMXt control register expected"),
509 N_("iWMMXt scalar register expected"),
510 N_("XScale accumulator register expected"),
513 /* Some well known registers that we refer to directly elsewhere. */
518 /* ARM instructions take 4bytes in the object file, Thumb instructions
524 /* Basic string to match. */
525 const char *template;
527 /* Parameters to instruction. */
528 unsigned char operands
[8];
530 /* Conditional tag - see opcode_lookup. */
531 unsigned int tag
: 4;
533 /* Basic instruction code. */
534 unsigned int avalue
: 28;
536 /* Thumb-format instruction code. */
539 /* Which architecture variant provides this instruction. */
540 const arm_feature_set
*avariant
;
541 const arm_feature_set
*tvariant
;
543 /* Function to call to encode instruction in ARM format. */
544 void (* aencode
) (void);
546 /* Function to call to encode instruction in Thumb format. */
547 void (* tencode
) (void);
550 /* Defines for various bits that we will want to toggle. */
551 #define INST_IMMEDIATE 0x02000000
552 #define OFFSET_REG 0x02000000
553 #define HWOFFSET_IMM 0x00400000
554 #define SHIFT_BY_REG 0x00000010
555 #define PRE_INDEX 0x01000000
556 #define INDEX_UP 0x00800000
557 #define WRITE_BACK 0x00200000
558 #define LDM_TYPE_2_OR_3 0x00400000
559 #define CPSI_MMOD 0x00020000
561 #define LITERAL_MASK 0xf000f000
562 #define OPCODE_MASK 0xfe1fffff
563 #define V4_STR_BIT 0x00000020
565 #define T2_SUBS_PC_LR 0xf3de8f00
567 #define DATA_OP_SHIFT 21
569 #define T2_OPCODE_MASK 0xfe1fffff
570 #define T2_DATA_OP_SHIFT 21
572 /* Codes to distinguish the arithmetic instructions. */
583 #define OPCODE_CMP 10
584 #define OPCODE_CMN 11
585 #define OPCODE_ORR 12
586 #define OPCODE_MOV 13
587 #define OPCODE_BIC 14
588 #define OPCODE_MVN 15
590 #define T2_OPCODE_AND 0
591 #define T2_OPCODE_BIC 1
592 #define T2_OPCODE_ORR 2
593 #define T2_OPCODE_ORN 3
594 #define T2_OPCODE_EOR 4
595 #define T2_OPCODE_ADD 8
596 #define T2_OPCODE_ADC 10
597 #define T2_OPCODE_SBC 11
598 #define T2_OPCODE_SUB 13
599 #define T2_OPCODE_RSB 14
601 #define T_OPCODE_MUL 0x4340
602 #define T_OPCODE_TST 0x4200
603 #define T_OPCODE_CMN 0x42c0
604 #define T_OPCODE_NEG 0x4240
605 #define T_OPCODE_MVN 0x43c0
607 #define T_OPCODE_ADD_R3 0x1800
608 #define T_OPCODE_SUB_R3 0x1a00
609 #define T_OPCODE_ADD_HI 0x4400
610 #define T_OPCODE_ADD_ST 0xb000
611 #define T_OPCODE_SUB_ST 0xb080
612 #define T_OPCODE_ADD_SP 0xa800
613 #define T_OPCODE_ADD_PC 0xa000
614 #define T_OPCODE_ADD_I8 0x3000
615 #define T_OPCODE_SUB_I8 0x3800
616 #define T_OPCODE_ADD_I3 0x1c00
617 #define T_OPCODE_SUB_I3 0x1e00
619 #define T_OPCODE_ASR_R 0x4100
620 #define T_OPCODE_LSL_R 0x4080
621 #define T_OPCODE_LSR_R 0x40c0
622 #define T_OPCODE_ROR_R 0x41c0
623 #define T_OPCODE_ASR_I 0x1000
624 #define T_OPCODE_LSL_I 0x0000
625 #define T_OPCODE_LSR_I 0x0800
627 #define T_OPCODE_MOV_I8 0x2000
628 #define T_OPCODE_CMP_I8 0x2800
629 #define T_OPCODE_CMP_LR 0x4280
630 #define T_OPCODE_MOV_HR 0x4600
631 #define T_OPCODE_CMP_HR 0x4500
633 #define T_OPCODE_LDR_PC 0x4800
634 #define T_OPCODE_LDR_SP 0x9800
635 #define T_OPCODE_STR_SP 0x9000
636 #define T_OPCODE_LDR_IW 0x6800
637 #define T_OPCODE_STR_IW 0x6000
638 #define T_OPCODE_LDR_IH 0x8800
639 #define T_OPCODE_STR_IH 0x8000
640 #define T_OPCODE_LDR_IB 0x7800
641 #define T_OPCODE_STR_IB 0x7000
642 #define T_OPCODE_LDR_RW 0x5800
643 #define T_OPCODE_STR_RW 0x5000
644 #define T_OPCODE_LDR_RH 0x5a00
645 #define T_OPCODE_STR_RH 0x5200
646 #define T_OPCODE_LDR_RB 0x5c00
647 #define T_OPCODE_STR_RB 0x5400
649 #define T_OPCODE_PUSH 0xb400
650 #define T_OPCODE_POP 0xbc00
652 #define T_OPCODE_BRANCH 0xe000
654 #define THUMB_SIZE 2 /* Size of thumb instruction. */
655 #define THUMB_PP_PC_LR 0x0100
656 #define THUMB_LOAD_BIT 0x0800
657 #define THUMB2_LOAD_BIT 0x00100000
659 #define BAD_ARGS _("bad arguments to instruction")
660 #define BAD_PC _("r15 not allowed here")
661 #define BAD_COND _("instruction cannot be conditional")
662 #define BAD_OVERLAP _("registers may not be the same")
663 #define BAD_HIREG _("lo register required")
664 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
665 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
666 #define BAD_BRANCH _("branch must be last instruction in IT block")
667 #define BAD_NOT_IT _("instruction not allowed in IT block")
668 #define BAD_FPU _("selected FPU does not support instruction")
670 static struct hash_control
*arm_ops_hsh
;
671 static struct hash_control
*arm_cond_hsh
;
672 static struct hash_control
*arm_shift_hsh
;
673 static struct hash_control
*arm_psr_hsh
;
674 static struct hash_control
*arm_v7m_psr_hsh
;
675 static struct hash_control
*arm_reg_hsh
;
676 static struct hash_control
*arm_reloc_hsh
;
677 static struct hash_control
*arm_barrier_opt_hsh
;
679 /* Stuff needed to resolve the label ambiguity
688 symbolS
* last_label_seen
;
689 static int label_is_thumb_function_name
= FALSE
;
691 /* Literal pool structure. Held on a per-section
692 and per-sub-section basis. */
694 #define MAX_LITERAL_POOL_SIZE 1024
695 typedef struct literal_pool
697 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
698 unsigned int next_free_entry
;
703 struct literal_pool
* next
;
706 /* Pointer to a linked list of literal pools. */
707 literal_pool
* list_of_pools
= NULL
;
709 /* State variables for IT block handling. */
710 static bfd_boolean current_it_mask
= 0;
711 static int current_cc
;
715 /* This array holds the chars that always start a comment. If the
716 pre-processor is disabled, these aren't very useful. */
717 const char comment_chars
[] = "@";
719 /* This array holds the chars that only start a comment at the beginning of
720 a line. If the line seems to have the form '# 123 filename'
721 .line and .file directives will appear in the pre-processed output. */
722 /* Note that input_file.c hand checks for '#' at the beginning of the
723 first line of the input file. This is because the compiler outputs
724 #NO_APP at the beginning of its output. */
725 /* Also note that comments like this one will always work. */
726 const char line_comment_chars
[] = "#";
728 const char line_separator_chars
[] = ";";
730 /* Chars that can be used to separate mant
731 from exp in floating point numbers. */
732 const char EXP_CHARS
[] = "eE";
734 /* Chars that mean this number is a floating point constant. */
738 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
740 /* Prefix characters that indicate the start of an immediate
742 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
744 /* Separator character handling. */
746 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
749 skip_past_char (char ** str
, char c
)
759 #define skip_past_comma(str) skip_past_char (str, ',')
761 /* Arithmetic expressions (possibly involving symbols). */
763 /* Return TRUE if anything in the expression is a bignum. */
766 walk_no_bignums (symbolS
* sp
)
768 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
771 if (symbol_get_value_expression (sp
)->X_add_symbol
)
773 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
774 || (symbol_get_value_expression (sp
)->X_op_symbol
775 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
781 static int in_my_get_expression
= 0;
783 /* Third argument to my_get_expression. */
784 #define GE_NO_PREFIX 0
785 #define GE_IMM_PREFIX 1
786 #define GE_OPT_PREFIX 2
787 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
788 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
789 #define GE_OPT_PREFIX_BIG 3
792 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
797 /* In unified syntax, all prefixes are optional. */
799 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
804 case GE_NO_PREFIX
: break;
806 if (!is_immediate_prefix (**str
))
808 inst
.error
= _("immediate expression requires a # prefix");
814 case GE_OPT_PREFIX_BIG
:
815 if (is_immediate_prefix (**str
))
821 memset (ep
, 0, sizeof (expressionS
));
823 save_in
= input_line_pointer
;
824 input_line_pointer
= *str
;
825 in_my_get_expression
= 1;
826 seg
= expression (ep
);
827 in_my_get_expression
= 0;
829 if (ep
->X_op
== O_illegal
)
831 /* We found a bad expression in md_operand(). */
832 *str
= input_line_pointer
;
833 input_line_pointer
= save_in
;
834 if (inst
.error
== NULL
)
835 inst
.error
= _("bad expression");
840 if (seg
!= absolute_section
841 && seg
!= text_section
842 && seg
!= data_section
843 && seg
!= bss_section
844 && seg
!= undefined_section
)
846 inst
.error
= _("bad segment");
847 *str
= input_line_pointer
;
848 input_line_pointer
= save_in
;
853 /* Get rid of any bignums now, so that we don't generate an error for which
854 we can't establish a line number later on. Big numbers are never valid
855 in instructions, which is where this routine is always called. */
856 if (prefix_mode
!= GE_OPT_PREFIX_BIG
857 && (ep
->X_op
== O_big
859 && (walk_no_bignums (ep
->X_add_symbol
)
861 && walk_no_bignums (ep
->X_op_symbol
))))))
863 inst
.error
= _("invalid constant");
864 *str
= input_line_pointer
;
865 input_line_pointer
= save_in
;
869 *str
= input_line_pointer
;
870 input_line_pointer
= save_in
;
874 /* Turn a string in input_line_pointer into a floating point constant
875 of type TYPE, and store the appropriate bytes in *LITP. The number
876 of LITTLENUMS emitted is stored in *SIZEP. An error message is
877 returned, or NULL on OK.
879 Note that fp constants aren't represent in the normal way on the ARM.
880 In big endian mode, things are as expected. However, in little endian
881 mode fp constants are big-endian word-wise, and little-endian byte-wise
882 within the words. For example, (double) 1.1 in big endian mode is
883 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
884 the byte sequence 99 99 f1 3f 9a 99 99 99.
886 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
889 md_atof (int type
, char * litP
, int * sizeP
)
892 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
924 return _("Unrecognized or unsupported floating point constant");
927 t
= atof_ieee (input_line_pointer
, type
, words
);
929 input_line_pointer
= t
;
930 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
932 if (target_big_endian
)
934 for (i
= 0; i
< prec
; i
++)
936 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
937 litP
+= sizeof (LITTLENUM_TYPE
);
942 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
943 for (i
= prec
- 1; i
>= 0; i
--)
945 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
946 litP
+= sizeof (LITTLENUM_TYPE
);
949 /* For a 4 byte float the order of elements in `words' is 1 0.
950 For an 8 byte float the order is 1 0 3 2. */
951 for (i
= 0; i
< prec
; i
+= 2)
953 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
954 sizeof (LITTLENUM_TYPE
));
955 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
956 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
957 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
964 /* We handle all bad expressions here, so that we can report the faulty
965 instruction in the error message. */
967 md_operand (expressionS
* expr
)
969 if (in_my_get_expression
)
970 expr
->X_op
= O_illegal
;
973 /* Immediate values. */
975 /* Generic immediate-value read function for use in directives.
976 Accepts anything that 'expression' can fold to a constant.
977 *val receives the number. */
980 immediate_for_directive (int *val
)
983 exp
.X_op
= O_illegal
;
985 if (is_immediate_prefix (*input_line_pointer
))
987 input_line_pointer
++;
991 if (exp
.X_op
!= O_constant
)
993 as_bad (_("expected #constant"));
994 ignore_rest_of_line ();
997 *val
= exp
.X_add_number
;
1002 /* Register parsing. */
1004 /* Generic register parser. CCP points to what should be the
1005 beginning of a register name. If it is indeed a valid register
1006 name, advance CCP over it and return the reg_entry structure;
1007 otherwise return NULL. Does not issue diagnostics. */
1009 static struct reg_entry
*
1010 arm_reg_parse_multi (char **ccp
)
1014 struct reg_entry
*reg
;
1016 #ifdef REGISTER_PREFIX
1017 if (*start
!= REGISTER_PREFIX
)
1021 #ifdef OPTIONAL_REGISTER_PREFIX
1022 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1027 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1032 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1034 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1044 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1045 enum arm_reg_type type
)
1047 /* Alternative syntaxes are accepted for a few register classes. */
1054 /* Generic coprocessor register names are allowed for these. */
1055 if (reg
&& reg
->type
== REG_TYPE_CN
)
1060 /* For backward compatibility, a bare number is valid here. */
1062 unsigned long processor
= strtoul (start
, ccp
, 10);
1063 if (*ccp
!= start
&& processor
<= 15)
1067 case REG_TYPE_MMXWC
:
1068 /* WC includes WCG. ??? I'm not sure this is true for all
1069 instructions that take WC registers. */
1070 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1081 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1082 return value is the register number or FAIL. */
1085 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1088 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1091 /* Do not allow a scalar (reg+index) to parse as a register. */
1092 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1095 if (reg
&& reg
->type
== type
)
1098 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1105 /* Parse a Neon type specifier. *STR should point at the leading '.'
1106 character. Does no verification at this stage that the type fits the opcode
1113 Can all be legally parsed by this function.
1115 Fills in neon_type struct pointer with parsed information, and updates STR
1116 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1117 type, FAIL if not. */
1120 parse_neon_type (struct neon_type
*type
, char **str
)
1127 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1129 enum neon_el_type thistype
= NT_untyped
;
1130 unsigned thissize
= -1u;
1137 /* Just a size without an explicit type. */
1141 switch (TOLOWER (*ptr
))
1143 case 'i': thistype
= NT_integer
; break;
1144 case 'f': thistype
= NT_float
; break;
1145 case 'p': thistype
= NT_poly
; break;
1146 case 's': thistype
= NT_signed
; break;
1147 case 'u': thistype
= NT_unsigned
; break;
1149 thistype
= NT_float
;
1154 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1160 /* .f is an abbreviation for .f32. */
1161 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1166 thissize
= strtoul (ptr
, &ptr
, 10);
1168 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1171 as_bad (_("bad size %d in type specifier"), thissize
);
1179 type
->el
[type
->elems
].type
= thistype
;
1180 type
->el
[type
->elems
].size
= thissize
;
1185 /* Empty/missing type is not a successful parse. */
1186 if (type
->elems
== 0)
1194 /* Errors may be set multiple times during parsing or bit encoding
1195 (particularly in the Neon bits), but usually the earliest error which is set
1196 will be the most meaningful. Avoid overwriting it with later (cascading)
1197 errors by calling this function. */
1200 first_error (const char *err
)
1206 /* Parse a single type, e.g. ".s32", leading period included. */
1208 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1211 struct neon_type optype
;
1215 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1217 if (optype
.elems
== 1)
1218 *vectype
= optype
.el
[0];
1221 first_error (_("only one type should be specified for operand"));
1227 first_error (_("vector type expected"));
1239 /* Special meanings for indices (which have a range of 0-7), which will fit into
1242 #define NEON_ALL_LANES 15
1243 #define NEON_INTERLEAVE_LANES 14
1245 /* Parse either a register or a scalar, with an optional type. Return the
1246 register number, and optionally fill in the actual type of the register
1247 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1248 type/index information in *TYPEINFO. */
1251 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1252 enum arm_reg_type
*rtype
,
1253 struct neon_typed_alias
*typeinfo
)
1256 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1257 struct neon_typed_alias atype
;
1258 struct neon_type_el parsetype
;
1262 atype
.eltype
.type
= NT_invtype
;
1263 atype
.eltype
.size
= -1;
1265 /* Try alternate syntax for some types of register. Note these are mutually
1266 exclusive with the Neon syntax extensions. */
1269 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1277 /* Undo polymorphism when a set of register types may be accepted. */
1278 if ((type
== REG_TYPE_NDQ
1279 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1280 || (type
== REG_TYPE_VFSD
1281 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1282 || (type
== REG_TYPE_NSDQ
1283 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1284 || reg
->type
== REG_TYPE_NQ
))
1285 || (type
== REG_TYPE_MMXWC
1286 && (reg
->type
== REG_TYPE_MMXWCG
)))
1289 if (type
!= reg
->type
)
1295 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1297 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1299 first_error (_("can't redefine type for operand"));
1302 atype
.defined
|= NTA_HASTYPE
;
1303 atype
.eltype
= parsetype
;
1306 if (skip_past_char (&str
, '[') == SUCCESS
)
1308 if (type
!= REG_TYPE_VFD
)
1310 first_error (_("only D registers may be indexed"));
1314 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1316 first_error (_("can't change index for operand"));
1320 atype
.defined
|= NTA_HASINDEX
;
1322 if (skip_past_char (&str
, ']') == SUCCESS
)
1323 atype
.index
= NEON_ALL_LANES
;
1328 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1330 if (exp
.X_op
!= O_constant
)
1332 first_error (_("constant expression required"));
1336 if (skip_past_char (&str
, ']') == FAIL
)
1339 atype
.index
= exp
.X_add_number
;
1354 /* Like arm_reg_parse, but allow allow the following extra features:
1355 - If RTYPE is non-zero, return the (possibly restricted) type of the
1356 register (e.g. Neon double or quad reg when either has been requested).
1357 - If this is a Neon vector type with additional type information, fill
1358 in the struct pointed to by VECTYPE (if non-NULL).
1359 This function will fault on encountering a scalar. */
1362 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1363 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1365 struct neon_typed_alias atype
;
1367 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1372 /* Do not allow a scalar (reg+index) to parse as a register. */
1373 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1375 first_error (_("register operand expected, but got scalar"));
1380 *vectype
= atype
.eltype
;
1387 #define NEON_SCALAR_REG(X) ((X) >> 4)
1388 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1390 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1391 have enough information to be able to do a good job bounds-checking. So, we
1392 just do easy checks here, and do further checks later. */
1395 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1399 struct neon_typed_alias atype
;
1401 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1403 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1406 if (atype
.index
== NEON_ALL_LANES
)
1408 first_error (_("scalar must have an index"));
1411 else if (atype
.index
>= 64 / elsize
)
1413 first_error (_("scalar index out of range"));
1418 *type
= atype
.eltype
;
1422 return reg
* 16 + atype
.index
;
1425 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1427 parse_reg_list (char ** strp
)
1429 char * str
= * strp
;
1433 /* We come back here if we get ranges concatenated by '+' or '|'. */
1448 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1450 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1460 first_error (_("bad range in register list"));
1464 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1466 if (range
& (1 << i
))
1468 (_("Warning: duplicated register (r%d) in register list"),
1476 if (range
& (1 << reg
))
1477 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1479 else if (reg
<= cur_reg
)
1480 as_tsktsk (_("Warning: register range not in ascending order"));
1485 while (skip_past_comma (&str
) != FAIL
1486 || (in_range
= 1, *str
++ == '-'));
1491 first_error (_("missing `}'"));
1499 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1502 if (expr
.X_op
== O_constant
)
1504 if (expr
.X_add_number
1505 != (expr
.X_add_number
& 0x0000ffff))
1507 inst
.error
= _("invalid register mask");
1511 if ((range
& expr
.X_add_number
) != 0)
1513 int regno
= range
& expr
.X_add_number
;
1516 regno
= (1 << regno
) - 1;
1518 (_("Warning: duplicated register (r%d) in register list"),
1522 range
|= expr
.X_add_number
;
1526 if (inst
.reloc
.type
!= 0)
1528 inst
.error
= _("expression too complex");
1532 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1533 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1534 inst
.reloc
.pc_rel
= 0;
1538 if (*str
== '|' || *str
== '+')
1544 while (another_range
);
1550 /* Types of registers in a list. */
1559 /* Parse a VFP register list. If the string is invalid return FAIL.
1560 Otherwise return the number of registers, and set PBASE to the first
1561 register. Parses registers of type ETYPE.
1562 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1563 - Q registers can be used to specify pairs of D registers
1564 - { } can be omitted from around a singleton register list
1565 FIXME: This is not implemented, as it would require backtracking in
1568 This could be done (the meaning isn't really ambiguous), but doesn't
1569 fit in well with the current parsing framework.
1570 - 32 D registers may be used (also true for VFPv3).
1571 FIXME: Types are ignored in these register lists, which is probably a
1575 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1580 enum arm_reg_type regtype
= 0;
1584 unsigned long mask
= 0;
1589 inst
.error
= _("expecting {");
1598 regtype
= REG_TYPE_VFS
;
1603 regtype
= REG_TYPE_VFD
;
1606 case REGLIST_NEON_D
:
1607 regtype
= REG_TYPE_NDQ
;
1611 if (etype
!= REGLIST_VFP_S
)
1613 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1614 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1618 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1621 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1628 base_reg
= max_regs
;
1632 int setmask
= 1, addregs
= 1;
1634 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1636 if (new_base
== FAIL
)
1638 first_error (_(reg_expected_msgs
[regtype
]));
1642 if (new_base
>= max_regs
)
1644 first_error (_("register out of range in list"));
1648 /* Note: a value of 2 * n is returned for the register Q<n>. */
1649 if (regtype
== REG_TYPE_NQ
)
1655 if (new_base
< base_reg
)
1656 base_reg
= new_base
;
1658 if (mask
& (setmask
<< new_base
))
1660 first_error (_("invalid register list"));
1664 if ((mask
>> new_base
) != 0 && ! warned
)
1666 as_tsktsk (_("register list not in ascending order"));
1670 mask
|= setmask
<< new_base
;
1673 if (*str
== '-') /* We have the start of a range expression */
1679 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1682 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1686 if (high_range
>= max_regs
)
1688 first_error (_("register out of range in list"));
1692 if (regtype
== REG_TYPE_NQ
)
1693 high_range
= high_range
+ 1;
1695 if (high_range
<= new_base
)
1697 inst
.error
= _("register range not in ascending order");
1701 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1703 if (mask
& (setmask
<< new_base
))
1705 inst
.error
= _("invalid register list");
1709 mask
|= setmask
<< new_base
;
1714 while (skip_past_comma (&str
) != FAIL
);
1718 /* Sanity check -- should have raised a parse error above. */
1719 if (count
== 0 || count
> max_regs
)
1724 /* Final test -- the registers must be consecutive. */
1726 for (i
= 0; i
< count
; i
++)
1728 if ((mask
& (1u << i
)) == 0)
1730 inst
.error
= _("non-contiguous register range");
1740 /* True if two alias types are the same. */
1743 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1751 if (a
->defined
!= b
->defined
)
1754 if ((a
->defined
& NTA_HASTYPE
) != 0
1755 && (a
->eltype
.type
!= b
->eltype
.type
1756 || a
->eltype
.size
!= b
->eltype
.size
))
1759 if ((a
->defined
& NTA_HASINDEX
) != 0
1760 && (a
->index
!= b
->index
))
1766 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1767 The base register is put in *PBASE.
1768 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1770 The register stride (minus one) is put in bit 4 of the return value.
1771 Bits [6:5] encode the list length (minus one).
1772 The type of the list elements is put in *ELTYPE, if non-NULL. */
1774 #define NEON_LANE(X) ((X) & 0xf)
1775 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1776 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1779 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1780 struct neon_type_el
*eltype
)
1787 int leading_brace
= 0;
1788 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1790 const char *const incr_error
= "register stride must be 1 or 2";
1791 const char *const type_error
= "mismatched element/structure types in list";
1792 struct neon_typed_alias firsttype
;
1794 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1799 struct neon_typed_alias atype
;
1800 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1804 first_error (_(reg_expected_msgs
[rtype
]));
1811 if (rtype
== REG_TYPE_NQ
)
1818 else if (reg_incr
== -1)
1820 reg_incr
= getreg
- base_reg
;
1821 if (reg_incr
< 1 || reg_incr
> 2)
1823 first_error (_(incr_error
));
1827 else if (getreg
!= base_reg
+ reg_incr
* count
)
1829 first_error (_(incr_error
));
1833 if (!neon_alias_types_same (&atype
, &firsttype
))
1835 first_error (_(type_error
));
1839 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1843 struct neon_typed_alias htype
;
1844 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1846 lane
= NEON_INTERLEAVE_LANES
;
1847 else if (lane
!= NEON_INTERLEAVE_LANES
)
1849 first_error (_(type_error
));
1854 else if (reg_incr
!= 1)
1856 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1860 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1863 first_error (_(reg_expected_msgs
[rtype
]));
1866 if (!neon_alias_types_same (&htype
, &firsttype
))
1868 first_error (_(type_error
));
1871 count
+= hireg
+ dregs
- getreg
;
1875 /* If we're using Q registers, we can't use [] or [n] syntax. */
1876 if (rtype
== REG_TYPE_NQ
)
1882 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1886 else if (lane
!= atype
.index
)
1888 first_error (_(type_error
));
1892 else if (lane
== -1)
1893 lane
= NEON_INTERLEAVE_LANES
;
1894 else if (lane
!= NEON_INTERLEAVE_LANES
)
1896 first_error (_(type_error
));
1901 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1903 /* No lane set by [x]. We must be interleaving structures. */
1905 lane
= NEON_INTERLEAVE_LANES
;
1908 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
1909 || (count
> 1 && reg_incr
== -1))
1911 first_error (_("error parsing element/structure list"));
1915 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
1917 first_error (_("expected }"));
1925 *eltype
= firsttype
.eltype
;
1930 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
1933 /* Parse an explicit relocation suffix on an expression. This is
1934 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1935 arm_reloc_hsh contains no entries, so this function can only
1936 succeed if there is no () after the word. Returns -1 on error,
1937 BFD_RELOC_UNUSED if there wasn't any suffix. */
1939 parse_reloc (char **str
)
1941 struct reloc_entry
*r
;
1945 return BFD_RELOC_UNUSED
;
1950 while (*q
&& *q
!= ')' && *q
!= ',')
1955 if ((r
= hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
1962 /* Directives: register aliases. */
1964 static struct reg_entry
*
1965 insert_reg_alias (char *str
, int number
, int type
)
1967 struct reg_entry
*new;
1970 if ((new = hash_find (arm_reg_hsh
, str
)) != 0)
1973 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
1975 /* Only warn about a redefinition if it's not defined as the
1977 else if (new->number
!= number
|| new->type
!= type
)
1978 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1983 name
= xstrdup (str
);
1984 new = xmalloc (sizeof (struct reg_entry
));
1987 new->number
= number
;
1989 new->builtin
= FALSE
;
1992 if (hash_insert (arm_reg_hsh
, name
, (void *) new))
1999 insert_neon_reg_alias (char *str
, int number
, int type
,
2000 struct neon_typed_alias
*atype
)
2002 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2006 first_error (_("attempt to redefine typed alias"));
2012 reg
->neon
= xmalloc (sizeof (struct neon_typed_alias
));
2013 *reg
->neon
= *atype
;
2017 /* Look for the .req directive. This is of the form:
2019 new_register_name .req existing_register_name
2021 If we find one, or if it looks sufficiently like one that we want to
2022 handle any error here, return TRUE. Otherwise return FALSE. */
2025 create_register_alias (char * newname
, char *p
)
2027 struct reg_entry
*old
;
2028 char *oldname
, *nbuf
;
2031 /* The input scrubber ensures that whitespace after the mnemonic is
2032 collapsed to single spaces. */
2034 if (strncmp (oldname
, " .req ", 6) != 0)
2038 if (*oldname
== '\0')
2041 old
= hash_find (arm_reg_hsh
, oldname
);
2044 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2048 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2049 the desired alias name, and p points to its end. If not, then
2050 the desired alias name is in the global original_case_string. */
2051 #ifdef TC_CASE_SENSITIVE
2054 newname
= original_case_string
;
2055 nlen
= strlen (newname
);
2058 nbuf
= alloca (nlen
+ 1);
2059 memcpy (nbuf
, newname
, nlen
);
2062 /* Create aliases under the new name as stated; an all-lowercase
2063 version of the new name; and an all-uppercase version of the new
2065 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2067 for (p
= nbuf
; *p
; p
++)
2070 if (strncmp (nbuf
, newname
, nlen
))
2072 /* If this attempt to create an additional alias fails, do not bother
2073 trying to create the all-lower case alias. We will fail and issue
2074 a second, duplicate error message. This situation arises when the
2075 programmer does something like:
2078 The second .req creates the "Foo" alias but then fails to create
2079 the artificial FOO alias because it has already been created by the
2081 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2085 for (p
= nbuf
; *p
; p
++)
2088 if (strncmp (nbuf
, newname
, nlen
))
2089 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2095 /* Create a Neon typed/indexed register alias using directives, e.g.:
2100 These typed registers can be used instead of the types specified after the
2101 Neon mnemonic, so long as all operands given have types. Types can also be
2102 specified directly, e.g.:
2103 vadd d0.s32, d1.s32, d2.s32 */
2106 create_neon_reg_alias (char *newname
, char *p
)
2108 enum arm_reg_type basetype
;
2109 struct reg_entry
*basereg
;
2110 struct reg_entry mybasereg
;
2111 struct neon_type ntype
;
2112 struct neon_typed_alias typeinfo
;
2113 char *namebuf
, *nameend
;
2116 typeinfo
.defined
= 0;
2117 typeinfo
.eltype
.type
= NT_invtype
;
2118 typeinfo
.eltype
.size
= -1;
2119 typeinfo
.index
= -1;
2123 if (strncmp (p
, " .dn ", 5) == 0)
2124 basetype
= REG_TYPE_VFD
;
2125 else if (strncmp (p
, " .qn ", 5) == 0)
2126 basetype
= REG_TYPE_NQ
;
2135 basereg
= arm_reg_parse_multi (&p
);
2137 if (basereg
&& basereg
->type
!= basetype
)
2139 as_bad (_("bad type for register"));
2143 if (basereg
== NULL
)
2146 /* Try parsing as an integer. */
2147 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2148 if (exp
.X_op
!= O_constant
)
2150 as_bad (_("expression must be constant"));
2153 basereg
= &mybasereg
;
2154 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2160 typeinfo
= *basereg
->neon
;
2162 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2164 /* We got a type. */
2165 if (typeinfo
.defined
& NTA_HASTYPE
)
2167 as_bad (_("can't redefine the type of a register alias"));
2171 typeinfo
.defined
|= NTA_HASTYPE
;
2172 if (ntype
.elems
!= 1)
2174 as_bad (_("you must specify a single type only"));
2177 typeinfo
.eltype
= ntype
.el
[0];
2180 if (skip_past_char (&p
, '[') == SUCCESS
)
2183 /* We got a scalar index. */
2185 if (typeinfo
.defined
& NTA_HASINDEX
)
2187 as_bad (_("can't redefine the index of a scalar alias"));
2191 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2193 if (exp
.X_op
!= O_constant
)
2195 as_bad (_("scalar index must be constant"));
2199 typeinfo
.defined
|= NTA_HASINDEX
;
2200 typeinfo
.index
= exp
.X_add_number
;
2202 if (skip_past_char (&p
, ']') == FAIL
)
2204 as_bad (_("expecting ]"));
2209 namelen
= nameend
- newname
;
2210 namebuf
= alloca (namelen
+ 1);
2211 strncpy (namebuf
, newname
, namelen
);
2212 namebuf
[namelen
] = '\0';
2214 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2215 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2217 /* Insert name in all uppercase. */
2218 for (p
= namebuf
; *p
; p
++)
2221 if (strncmp (namebuf
, newname
, namelen
))
2222 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2223 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2225 /* Insert name in all lowercase. */
2226 for (p
= namebuf
; *p
; p
++)
2229 if (strncmp (namebuf
, newname
, namelen
))
2230 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2231 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2236 /* Should never be called, as .req goes between the alias and the
2237 register name, not at the beginning of the line. */
2239 s_req (int a ATTRIBUTE_UNUSED
)
2241 as_bad (_("invalid syntax for .req directive"));
2245 s_dn (int a ATTRIBUTE_UNUSED
)
2247 as_bad (_("invalid syntax for .dn directive"));
2251 s_qn (int a ATTRIBUTE_UNUSED
)
2253 as_bad (_("invalid syntax for .qn directive"));
2256 /* The .unreq directive deletes an alias which was previously defined
2257 by .req. For example:
2263 s_unreq (int a ATTRIBUTE_UNUSED
)
2268 name
= input_line_pointer
;
2270 while (*input_line_pointer
!= 0
2271 && *input_line_pointer
!= ' '
2272 && *input_line_pointer
!= '\n')
2273 ++input_line_pointer
;
2275 saved_char
= *input_line_pointer
;
2276 *input_line_pointer
= 0;
2279 as_bad (_("invalid syntax for .unreq directive"));
2282 struct reg_entry
*reg
= hash_find (arm_reg_hsh
, name
);
2285 as_bad (_("unknown register alias '%s'"), name
);
2286 else if (reg
->builtin
)
2287 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2294 hash_delete (arm_reg_hsh
, name
, FALSE
);
2295 free ((char *) reg
->name
);
2300 /* Also locate the all upper case and all lower case versions.
2301 Do not complain if we cannot find one or the other as it
2302 was probably deleted above. */
2304 nbuf
= strdup (name
);
2305 for (p
= nbuf
; *p
; p
++)
2307 reg
= hash_find (arm_reg_hsh
, nbuf
);
2310 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2311 free ((char *) reg
->name
);
2317 for (p
= nbuf
; *p
; p
++)
2319 reg
= hash_find (arm_reg_hsh
, nbuf
);
2322 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2323 free ((char *) reg
->name
);
2333 *input_line_pointer
= saved_char
;
2334 demand_empty_rest_of_line ();
2337 /* Directives: Instruction set selection. */
2340 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2341 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2342 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2343 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2345 static enum mstate mapstate
= MAP_UNDEFINED
;
2348 mapping_state (enum mstate state
)
2351 const char * symname
;
2354 if (mapstate
== state
)
2355 /* The mapping symbol has already been emitted.
2356 There is nothing else to do. */
2365 type
= BSF_NO_FLAGS
;
2369 type
= BSF_NO_FLAGS
;
2373 type
= BSF_NO_FLAGS
;
2381 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2383 symbolP
= symbol_new (symname
, now_seg
, (valueT
) frag_now_fix (), frag_now
);
2384 symbol_table_insert (symbolP
);
2385 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2390 THUMB_SET_FUNC (symbolP
, 0);
2391 ARM_SET_THUMB (symbolP
, 0);
2392 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2396 THUMB_SET_FUNC (symbolP
, 1);
2397 ARM_SET_THUMB (symbolP
, 1);
2398 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2407 #define mapping_state(x) /* nothing */
2410 /* Find the real, Thumb encoded start of a Thumb function. */
2413 find_real_start (symbolS
* symbolP
)
2416 const char * name
= S_GET_NAME (symbolP
);
2417 symbolS
* new_target
;
2419 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2420 #define STUB_NAME ".real_start_of"
2425 /* The compiler may generate BL instructions to local labels because
2426 it needs to perform a branch to a far away location. These labels
2427 do not have a corresponding ".real_start_of" label. We check
2428 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2429 the ".real_start_of" convention for nonlocal branches. */
2430 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2433 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2434 new_target
= symbol_find (real_start
);
2436 if (new_target
== NULL
)
2438 as_warn (_("Failed to find real start of function: %s\n"), name
);
2439 new_target
= symbolP
;
2446 opcode_select (int width
)
2453 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2454 as_bad (_("selected processor does not support THUMB opcodes"));
2457 /* No need to force the alignment, since we will have been
2458 coming from ARM mode, which is word-aligned. */
2459 record_alignment (now_seg
, 1);
2461 mapping_state (MAP_THUMB
);
2467 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2468 as_bad (_("selected processor does not support ARM opcodes"));
2473 frag_align (2, 0, 0);
2475 record_alignment (now_seg
, 1);
2477 mapping_state (MAP_ARM
);
2481 as_bad (_("invalid instruction size selected (%d)"), width
);
2486 s_arm (int ignore ATTRIBUTE_UNUSED
)
2489 demand_empty_rest_of_line ();
2493 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2496 demand_empty_rest_of_line ();
2500 s_code (int unused ATTRIBUTE_UNUSED
)
2504 temp
= get_absolute_expression ();
2509 opcode_select (temp
);
2513 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2518 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2520 /* If we are not already in thumb mode go into it, EVEN if
2521 the target processor does not support thumb instructions.
2522 This is used by gcc/config/arm/lib1funcs.asm for example
2523 to compile interworking support functions even if the
2524 target processor should not support interworking. */
2528 record_alignment (now_seg
, 1);
2531 demand_empty_rest_of_line ();
2535 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2539 /* The following label is the name/address of the start of a Thumb function.
2540 We need to know this for the interworking support. */
2541 label_is_thumb_function_name
= TRUE
;
2544 /* Perform a .set directive, but also mark the alias as
2545 being a thumb function. */
2548 s_thumb_set (int equiv
)
2550 /* XXX the following is a duplicate of the code for s_set() in read.c
2551 We cannot just call that code as we need to get at the symbol that
2558 /* Especial apologies for the random logic:
2559 This just grew, and could be parsed much more simply!
2561 name
= input_line_pointer
;
2562 delim
= get_symbol_end ();
2563 end_name
= input_line_pointer
;
2566 if (*input_line_pointer
!= ',')
2569 as_bad (_("expected comma after name \"%s\""), name
);
2571 ignore_rest_of_line ();
2575 input_line_pointer
++;
2578 if (name
[0] == '.' && name
[1] == '\0')
2580 /* XXX - this should not happen to .thumb_set. */
2584 if ((symbolP
= symbol_find (name
)) == NULL
2585 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2588 /* When doing symbol listings, play games with dummy fragments living
2589 outside the normal fragment chain to record the file and line info
2591 if (listing
& LISTING_SYMBOLS
)
2593 extern struct list_info_struct
* listing_tail
;
2594 fragS
* dummy_frag
= xmalloc (sizeof (fragS
));
2596 memset (dummy_frag
, 0, sizeof (fragS
));
2597 dummy_frag
->fr_type
= rs_fill
;
2598 dummy_frag
->line
= listing_tail
;
2599 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2600 dummy_frag
->fr_symbol
= symbolP
;
2604 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2607 /* "set" symbols are local unless otherwise specified. */
2608 SF_SET_LOCAL (symbolP
);
2609 #endif /* OBJ_COFF */
2610 } /* Make a new symbol. */
2612 symbol_table_insert (symbolP
);
2617 && S_IS_DEFINED (symbolP
)
2618 && S_GET_SEGMENT (symbolP
) != reg_section
)
2619 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2621 pseudo_set (symbolP
);
2623 demand_empty_rest_of_line ();
2625 /* XXX Now we come to the Thumb specific bit of code. */
2627 THUMB_SET_FUNC (symbolP
, 1);
2628 ARM_SET_THUMB (symbolP
, 1);
2629 #if defined OBJ_ELF || defined OBJ_COFF
2630 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2634 /* Directives: Mode selection. */
2636 /* .syntax [unified|divided] - choose the new unified syntax
2637 (same for Arm and Thumb encoding, modulo slight differences in what
2638 can be represented) or the old divergent syntax for each mode. */
2640 s_syntax (int unused ATTRIBUTE_UNUSED
)
2644 name
= input_line_pointer
;
2645 delim
= get_symbol_end ();
2647 if (!strcasecmp (name
, "unified"))
2648 unified_syntax
= TRUE
;
2649 else if (!strcasecmp (name
, "divided"))
2650 unified_syntax
= FALSE
;
2653 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2656 *input_line_pointer
= delim
;
2657 demand_empty_rest_of_line ();
2660 /* Directives: sectioning and alignment. */
2662 /* Same as s_align_ptwo but align 0 => align 2. */
2665 s_align (int unused ATTRIBUTE_UNUSED
)
2670 long max_alignment
= 15;
2672 temp
= get_absolute_expression ();
2673 if (temp
> max_alignment
)
2674 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2677 as_bad (_("alignment negative. 0 assumed."));
2681 if (*input_line_pointer
== ',')
2683 input_line_pointer
++;
2684 temp_fill
= get_absolute_expression ();
2696 /* Only make a frag if we HAVE to. */
2697 if (temp
&& !need_pass_2
)
2699 if (!fill_p
&& subseg_text_p (now_seg
))
2700 frag_align_code (temp
, 0);
2702 frag_align (temp
, (int) temp_fill
, 0);
2704 demand_empty_rest_of_line ();
2706 record_alignment (now_seg
, temp
);
2710 s_bss (int ignore ATTRIBUTE_UNUSED
)
2712 /* We don't support putting frags in the BSS segment, we fake it by
2713 marking in_bss, then looking at s_skip for clues. */
2714 subseg_set (bss_section
, 0);
2715 demand_empty_rest_of_line ();
2716 mapping_state (MAP_DATA
);
2720 s_even (int ignore ATTRIBUTE_UNUSED
)
2722 /* Never make frag if expect extra pass. */
2724 frag_align (1, 0, 0);
2726 record_alignment (now_seg
, 1);
2728 demand_empty_rest_of_line ();
2731 /* Directives: Literal pools. */
2733 static literal_pool
*
2734 find_literal_pool (void)
2736 literal_pool
* pool
;
2738 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2740 if (pool
->section
== now_seg
2741 && pool
->sub_section
== now_subseg
)
2748 static literal_pool
*
2749 find_or_make_literal_pool (void)
2751 /* Next literal pool ID number. */
2752 static unsigned int latest_pool_num
= 1;
2753 literal_pool
* pool
;
2755 pool
= find_literal_pool ();
2759 /* Create a new pool. */
2760 pool
= xmalloc (sizeof (* pool
));
2764 pool
->next_free_entry
= 0;
2765 pool
->section
= now_seg
;
2766 pool
->sub_section
= now_subseg
;
2767 pool
->next
= list_of_pools
;
2768 pool
->symbol
= NULL
;
2770 /* Add it to the list. */
2771 list_of_pools
= pool
;
2774 /* New pools, and emptied pools, will have a NULL symbol. */
2775 if (pool
->symbol
== NULL
)
2777 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2778 (valueT
) 0, &zero_address_frag
);
2779 pool
->id
= latest_pool_num
++;
2786 /* Add the literal in the global 'inst'
2787 structure to the relevant literal pool. */
2790 add_to_lit_pool (void)
2792 literal_pool
* pool
;
2795 pool
= find_or_make_literal_pool ();
2797 /* Check if this literal value is already in the pool. */
2798 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2800 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2801 && (inst
.reloc
.exp
.X_op
== O_constant
)
2802 && (pool
->literals
[entry
].X_add_number
2803 == inst
.reloc
.exp
.X_add_number
)
2804 && (pool
->literals
[entry
].X_unsigned
2805 == inst
.reloc
.exp
.X_unsigned
))
2808 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2809 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2810 && (pool
->literals
[entry
].X_add_number
2811 == inst
.reloc
.exp
.X_add_number
)
2812 && (pool
->literals
[entry
].X_add_symbol
2813 == inst
.reloc
.exp
.X_add_symbol
)
2814 && (pool
->literals
[entry
].X_op_symbol
2815 == inst
.reloc
.exp
.X_op_symbol
))
2819 /* Do we need to create a new entry? */
2820 if (entry
== pool
->next_free_entry
)
2822 if (entry
>= MAX_LITERAL_POOL_SIZE
)
2824 inst
.error
= _("literal pool overflow");
2828 pool
->literals
[entry
] = inst
.reloc
.exp
;
2829 pool
->next_free_entry
+= 1;
2832 inst
.reloc
.exp
.X_op
= O_symbol
;
2833 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
2834 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
2839 /* Can't use symbol_new here, so have to create a symbol and then at
2840 a later date assign it a value. Thats what these functions do. */
2843 symbol_locate (symbolS
* symbolP
,
2844 const char * name
, /* It is copied, the caller can modify. */
2845 segT segment
, /* Segment identifier (SEG_<something>). */
2846 valueT valu
, /* Symbol value. */
2847 fragS
* frag
) /* Associated fragment. */
2849 unsigned int name_length
;
2850 char * preserved_copy_of_name
;
2852 name_length
= strlen (name
) + 1; /* +1 for \0. */
2853 obstack_grow (¬es
, name
, name_length
);
2854 preserved_copy_of_name
= obstack_finish (¬es
);
2856 #ifdef tc_canonicalize_symbol_name
2857 preserved_copy_of_name
=
2858 tc_canonicalize_symbol_name (preserved_copy_of_name
);
2861 S_SET_NAME (symbolP
, preserved_copy_of_name
);
2863 S_SET_SEGMENT (symbolP
, segment
);
2864 S_SET_VALUE (symbolP
, valu
);
2865 symbol_clear_list_pointers (symbolP
);
2867 symbol_set_frag (symbolP
, frag
);
2869 /* Link to end of symbol chain. */
2871 extern int symbol_table_frozen
;
2873 if (symbol_table_frozen
)
2877 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
2879 obj_symbol_new_hook (symbolP
);
2881 #ifdef tc_symbol_new_hook
2882 tc_symbol_new_hook (symbolP
);
2886 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
2887 #endif /* DEBUG_SYMS */
2892 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
2895 literal_pool
* pool
;
2898 pool
= find_literal_pool ();
2900 || pool
->symbol
== NULL
2901 || pool
->next_free_entry
== 0)
2904 mapping_state (MAP_DATA
);
2906 /* Align pool as you have word accesses.
2907 Only make a frag if we have to. */
2909 frag_align (2, 0, 0);
2911 record_alignment (now_seg
, 2);
2913 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
2915 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
2916 (valueT
) frag_now_fix (), frag_now
);
2917 symbol_table_insert (pool
->symbol
);
2919 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
2921 #if defined OBJ_COFF || defined OBJ_ELF
2922 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
2925 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2926 /* First output the expression in the instruction to the pool. */
2927 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
2929 /* Mark the pool as empty. */
2930 pool
->next_free_entry
= 0;
2931 pool
->symbol
= NULL
;
2935 /* Forward declarations for functions below, in the MD interface
2937 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
2938 static valueT
create_unwind_entry (int);
2939 static void start_unwind_section (const segT
, int);
2940 static void add_unwind_opcode (valueT
, int);
2941 static void flush_pending_unwind (void);
2943 /* Directives: Data. */
2946 s_arm_elf_cons (int nbytes
)
2950 #ifdef md_flush_pending_output
2951 md_flush_pending_output ();
2954 if (is_it_end_of_statement ())
2956 demand_empty_rest_of_line ();
2960 #ifdef md_cons_align
2961 md_cons_align (nbytes
);
2964 mapping_state (MAP_DATA
);
2968 char *base
= input_line_pointer
;
2972 if (exp
.X_op
!= O_symbol
)
2973 emit_expr (&exp
, (unsigned int) nbytes
);
2976 char *before_reloc
= input_line_pointer
;
2977 reloc
= parse_reloc (&input_line_pointer
);
2980 as_bad (_("unrecognized relocation suffix"));
2981 ignore_rest_of_line ();
2984 else if (reloc
== BFD_RELOC_UNUSED
)
2985 emit_expr (&exp
, (unsigned int) nbytes
);
2988 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
2989 int size
= bfd_get_reloc_size (howto
);
2991 if (reloc
== BFD_RELOC_ARM_PLT32
)
2993 as_bad (_("(plt) is only valid on branch targets"));
2994 reloc
= BFD_RELOC_UNUSED
;
2999 as_bad (_("%s relocations do not fit in %d bytes"),
3000 howto
->name
, nbytes
);
3003 /* We've parsed an expression stopping at O_symbol.
3004 But there may be more expression left now that we
3005 have parsed the relocation marker. Parse it again.
3006 XXX Surely there is a cleaner way to do this. */
3007 char *p
= input_line_pointer
;
3009 char *save_buf
= alloca (input_line_pointer
- base
);
3010 memcpy (save_buf
, base
, input_line_pointer
- base
);
3011 memmove (base
+ (input_line_pointer
- before_reloc
),
3012 base
, before_reloc
- base
);
3014 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3016 memcpy (base
, save_buf
, p
- base
);
3018 offset
= nbytes
- size
;
3019 p
= frag_more ((int) nbytes
);
3020 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3021 size
, &exp
, 0, reloc
);
3026 while (*input_line_pointer
++ == ',');
3028 /* Put terminator back into stream. */
3029 input_line_pointer
--;
3030 demand_empty_rest_of_line ();
3034 /* Parse a .rel31 directive. */
3037 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3044 if (*input_line_pointer
== '1')
3045 highbit
= 0x80000000;
3046 else if (*input_line_pointer
!= '0')
3047 as_bad (_("expected 0 or 1"));
3049 input_line_pointer
++;
3050 if (*input_line_pointer
!= ',')
3051 as_bad (_("missing comma"));
3052 input_line_pointer
++;
3054 #ifdef md_flush_pending_output
3055 md_flush_pending_output ();
3058 #ifdef md_cons_align
3062 mapping_state (MAP_DATA
);
3067 md_number_to_chars (p
, highbit
, 4);
3068 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3069 BFD_RELOC_ARM_PREL31
);
3071 demand_empty_rest_of_line ();
3074 /* Directives: AEABI stack-unwind tables. */
3076 /* Parse an unwind_fnstart directive. Simply records the current location. */
3079 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3081 demand_empty_rest_of_line ();
3082 /* Mark the start of the function. */
3083 unwind
.proc_start
= expr_build_dot ();
3085 /* Reset the rest of the unwind info. */
3086 unwind
.opcode_count
= 0;
3087 unwind
.table_entry
= NULL
;
3088 unwind
.personality_routine
= NULL
;
3089 unwind
.personality_index
= -1;
3090 unwind
.frame_size
= 0;
3091 unwind
.fp_offset
= 0;
3094 unwind
.sp_restored
= 0;
3098 /* Parse a handlerdata directive. Creates the exception handling table entry
3099 for the function. */
3102 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3104 demand_empty_rest_of_line ();
3105 if (unwind
.table_entry
)
3106 as_bad (_("duplicate .handlerdata directive"));
3108 create_unwind_entry (1);
3111 /* Parse an unwind_fnend directive. Generates the index table entry. */
3114 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3120 demand_empty_rest_of_line ();
3122 /* Add eh table entry. */
3123 if (unwind
.table_entry
== NULL
)
3124 val
= create_unwind_entry (0);
3128 /* Add index table entry. This is two words. */
3129 start_unwind_section (unwind
.saved_seg
, 1);
3130 frag_align (2, 0, 0);
3131 record_alignment (now_seg
, 2);
3133 ptr
= frag_more (8);
3134 where
= frag_now_fix () - 8;
3136 /* Self relative offset of the function start. */
3137 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3138 BFD_RELOC_ARM_PREL31
);
3140 /* Indicate dependency on EHABI-defined personality routines to the
3141 linker, if it hasn't been done already. */
3142 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3143 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3145 static const char *const name
[] =
3147 "__aeabi_unwind_cpp_pr0",
3148 "__aeabi_unwind_cpp_pr1",
3149 "__aeabi_unwind_cpp_pr2"
3151 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3152 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3153 marked_pr_dependency
|= 1 << unwind
.personality_index
;
3154 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3155 = marked_pr_dependency
;
3159 /* Inline exception table entry. */
3160 md_number_to_chars (ptr
+ 4, val
, 4);
3162 /* Self relative offset of the table entry. */
3163 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3164 BFD_RELOC_ARM_PREL31
);
3166 /* Restore the original section. */
3167 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3171 /* Parse an unwind_cantunwind directive. */
3174 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3176 demand_empty_rest_of_line ();
3177 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3178 as_bad (_("personality routine specified for cantunwind frame"));
3180 unwind
.personality_index
= -2;
3184 /* Parse a personalityindex directive. */
3187 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3191 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3192 as_bad (_("duplicate .personalityindex directive"));
3196 if (exp
.X_op
!= O_constant
3197 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3199 as_bad (_("bad personality routine number"));
3200 ignore_rest_of_line ();
3204 unwind
.personality_index
= exp
.X_add_number
;
3206 demand_empty_rest_of_line ();
3210 /* Parse a personality directive. */
3213 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3217 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3218 as_bad (_("duplicate .personality directive"));
3220 name
= input_line_pointer
;
3221 c
= get_symbol_end ();
3222 p
= input_line_pointer
;
3223 unwind
.personality_routine
= symbol_find_or_make (name
);
3225 demand_empty_rest_of_line ();
3229 /* Parse a directive saving core registers. */
3232 s_arm_unwind_save_core (void)
3238 range
= parse_reg_list (&input_line_pointer
);
3241 as_bad (_("expected register list"));
3242 ignore_rest_of_line ();
3246 demand_empty_rest_of_line ();
3248 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3249 into .unwind_save {..., sp...}. We aren't bothered about the value of
3250 ip because it is clobbered by calls. */
3251 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3252 && (range
& 0x3000) == 0x1000)
3254 unwind
.opcode_count
--;
3255 unwind
.sp_restored
= 0;
3256 range
= (range
| 0x2000) & ~0x1000;
3257 unwind
.pending_offset
= 0;
3263 /* See if we can use the short opcodes. These pop a block of up to 8
3264 registers starting with r4, plus maybe r14. */
3265 for (n
= 0; n
< 8; n
++)
3267 /* Break at the first non-saved register. */
3268 if ((range
& (1 << (n
+ 4))) == 0)
3271 /* See if there are any other bits set. */
3272 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3274 /* Use the long form. */
3275 op
= 0x8000 | ((range
>> 4) & 0xfff);
3276 add_unwind_opcode (op
, 2);
3280 /* Use the short form. */
3282 op
= 0xa8; /* Pop r14. */
3284 op
= 0xa0; /* Do not pop r14. */
3286 add_unwind_opcode (op
, 1);
3293 op
= 0xb100 | (range
& 0xf);
3294 add_unwind_opcode (op
, 2);
3297 /* Record the number of bytes pushed. */
3298 for (n
= 0; n
< 16; n
++)
3300 if (range
& (1 << n
))
3301 unwind
.frame_size
+= 4;
3306 /* Parse a directive saving FPA registers. */
3309 s_arm_unwind_save_fpa (int reg
)
3315 /* Get Number of registers to transfer. */
3316 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3319 exp
.X_op
= O_illegal
;
3321 if (exp
.X_op
!= O_constant
)
3323 as_bad (_("expected , <constant>"));
3324 ignore_rest_of_line ();
3328 num_regs
= exp
.X_add_number
;
3330 if (num_regs
< 1 || num_regs
> 4)
3332 as_bad (_("number of registers must be in the range [1:4]"));
3333 ignore_rest_of_line ();
3337 demand_empty_rest_of_line ();
3342 op
= 0xb4 | (num_regs
- 1);
3343 add_unwind_opcode (op
, 1);
3348 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3349 add_unwind_opcode (op
, 2);
3351 unwind
.frame_size
+= num_regs
* 12;
3355 /* Parse a directive saving VFP registers for ARMv6 and above. */
3358 s_arm_unwind_save_vfp_armv6 (void)
3363 int num_vfpv3_regs
= 0;
3364 int num_regs_below_16
;
3366 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3369 as_bad (_("expected register list"));
3370 ignore_rest_of_line ();
3374 demand_empty_rest_of_line ();
3376 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3377 than FSTMX/FLDMX-style ones). */
3379 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3381 num_vfpv3_regs
= count
;
3382 else if (start
+ count
> 16)
3383 num_vfpv3_regs
= start
+ count
- 16;
3385 if (num_vfpv3_regs
> 0)
3387 int start_offset
= start
> 16 ? start
- 16 : 0;
3388 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3389 add_unwind_opcode (op
, 2);
3392 /* Generate opcode for registers numbered in the range 0 .. 15. */
3393 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3394 assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3395 if (num_regs_below_16
> 0)
3397 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3398 add_unwind_opcode (op
, 2);
3401 unwind
.frame_size
+= count
* 8;
3405 /* Parse a directive saving VFP registers for pre-ARMv6. */
3408 s_arm_unwind_save_vfp (void)
3414 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3417 as_bad (_("expected register list"));
3418 ignore_rest_of_line ();
3422 demand_empty_rest_of_line ();
3427 op
= 0xb8 | (count
- 1);
3428 add_unwind_opcode (op
, 1);
3433 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3434 add_unwind_opcode (op
, 2);
3436 unwind
.frame_size
+= count
* 8 + 4;
3440 /* Parse a directive saving iWMMXt data registers. */
3443 s_arm_unwind_save_mmxwr (void)
3451 if (*input_line_pointer
== '{')
3452 input_line_pointer
++;
3456 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3460 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3465 as_tsktsk (_("register list not in ascending order"));
3468 if (*input_line_pointer
== '-')
3470 input_line_pointer
++;
3471 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3474 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3477 else if (reg
>= hi_reg
)
3479 as_bad (_("bad register range"));
3482 for (; reg
< hi_reg
; reg
++)
3486 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3488 if (*input_line_pointer
== '}')
3489 input_line_pointer
++;
3491 demand_empty_rest_of_line ();
3493 /* Generate any deferred opcodes because we're going to be looking at
3495 flush_pending_unwind ();
3497 for (i
= 0; i
< 16; i
++)
3499 if (mask
& (1 << i
))
3500 unwind
.frame_size
+= 8;
3503 /* Attempt to combine with a previous opcode. We do this because gcc
3504 likes to output separate unwind directives for a single block of
3506 if (unwind
.opcode_count
> 0)
3508 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3509 if ((i
& 0xf8) == 0xc0)
3512 /* Only merge if the blocks are contiguous. */
3515 if ((mask
& 0xfe00) == (1 << 9))
3517 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3518 unwind
.opcode_count
--;
3521 else if (i
== 6 && unwind
.opcode_count
>= 2)
3523 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3527 op
= 0xffff << (reg
- 1);
3529 && ((mask
& op
) == (1u << (reg
- 1))))
3531 op
= (1 << (reg
+ i
+ 1)) - 1;
3532 op
&= ~((1 << reg
) - 1);
3534 unwind
.opcode_count
-= 2;
3541 /* We want to generate opcodes in the order the registers have been
3542 saved, ie. descending order. */
3543 for (reg
= 15; reg
>= -1; reg
--)
3545 /* Save registers in blocks. */
3547 || !(mask
& (1 << reg
)))
3549 /* We found an unsaved reg. Generate opcodes to save the
3556 op
= 0xc0 | (hi_reg
- 10);
3557 add_unwind_opcode (op
, 1);
3562 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3563 add_unwind_opcode (op
, 2);
3572 ignore_rest_of_line ();
3576 s_arm_unwind_save_mmxwcg (void)
3583 if (*input_line_pointer
== '{')
3584 input_line_pointer
++;
3588 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3592 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3598 as_tsktsk (_("register list not in ascending order"));
3601 if (*input_line_pointer
== '-')
3603 input_line_pointer
++;
3604 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3607 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3610 else if (reg
>= hi_reg
)
3612 as_bad (_("bad register range"));
3615 for (; reg
< hi_reg
; reg
++)
3619 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3621 if (*input_line_pointer
== '}')
3622 input_line_pointer
++;
3624 demand_empty_rest_of_line ();
3626 /* Generate any deferred opcodes because we're going to be looking at
3628 flush_pending_unwind ();
3630 for (reg
= 0; reg
< 16; reg
++)
3632 if (mask
& (1 << reg
))
3633 unwind
.frame_size
+= 4;
3636 add_unwind_opcode (op
, 2);
3639 ignore_rest_of_line ();
3643 /* Parse an unwind_save directive.
3644 If the argument is non-zero, this is a .vsave directive. */
3647 s_arm_unwind_save (int arch_v6
)
3650 struct reg_entry
*reg
;
3651 bfd_boolean had_brace
= FALSE
;
3653 /* Figure out what sort of save we have. */
3654 peek
= input_line_pointer
;
3662 reg
= arm_reg_parse_multi (&peek
);
3666 as_bad (_("register expected"));
3667 ignore_rest_of_line ();
3676 as_bad (_("FPA .unwind_save does not take a register list"));
3677 ignore_rest_of_line ();
3680 input_line_pointer
= peek
;
3681 s_arm_unwind_save_fpa (reg
->number
);
3684 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
3687 s_arm_unwind_save_vfp_armv6 ();
3689 s_arm_unwind_save_vfp ();
3691 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
3692 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
3695 as_bad (_(".unwind_save does not support this kind of register"));
3696 ignore_rest_of_line ();
3701 /* Parse an unwind_movsp directive. */
3704 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
3710 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3713 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
3714 ignore_rest_of_line ();
3718 /* Optional constant. */
3719 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3721 if (immediate_for_directive (&offset
) == FAIL
)
3727 demand_empty_rest_of_line ();
3729 if (reg
== REG_SP
|| reg
== REG_PC
)
3731 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
3735 if (unwind
.fp_reg
!= REG_SP
)
3736 as_bad (_("unexpected .unwind_movsp directive"));
3738 /* Generate opcode to restore the value. */
3740 add_unwind_opcode (op
, 1);
3742 /* Record the information for later. */
3743 unwind
.fp_reg
= reg
;
3744 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3745 unwind
.sp_restored
= 1;
3748 /* Parse an unwind_pad directive. */
3751 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
3755 if (immediate_for_directive (&offset
) == FAIL
)
3760 as_bad (_("stack increment must be multiple of 4"));
3761 ignore_rest_of_line ();
3765 /* Don't generate any opcodes, just record the details for later. */
3766 unwind
.frame_size
+= offset
;
3767 unwind
.pending_offset
+= offset
;
3769 demand_empty_rest_of_line ();
3772 /* Parse an unwind_setfp directive. */
3775 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
3781 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3782 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3785 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3787 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
3789 as_bad (_("expected <reg>, <reg>"));
3790 ignore_rest_of_line ();
3794 /* Optional constant. */
3795 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3797 if (immediate_for_directive (&offset
) == FAIL
)
3803 demand_empty_rest_of_line ();
3805 if (sp_reg
!= 13 && sp_reg
!= unwind
.fp_reg
)
3807 as_bad (_("register must be either sp or set by a previous"
3808 "unwind_movsp directive"));
3812 /* Don't generate any opcodes, just record the information for later. */
3813 unwind
.fp_reg
= fp_reg
;
3816 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3818 unwind
.fp_offset
-= offset
;
3821 /* Parse an unwind_raw directive. */
3824 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
3827 /* This is an arbitrary limit. */
3828 unsigned char op
[16];
3832 if (exp
.X_op
== O_constant
3833 && skip_past_comma (&input_line_pointer
) != FAIL
)
3835 unwind
.frame_size
+= exp
.X_add_number
;
3839 exp
.X_op
= O_illegal
;
3841 if (exp
.X_op
!= O_constant
)
3843 as_bad (_("expected <offset>, <opcode>"));
3844 ignore_rest_of_line ();
3850 /* Parse the opcode. */
3855 as_bad (_("unwind opcode too long"));
3856 ignore_rest_of_line ();
3858 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
3860 as_bad (_("invalid unwind opcode"));
3861 ignore_rest_of_line ();
3864 op
[count
++] = exp
.X_add_number
;
3866 /* Parse the next byte. */
3867 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3873 /* Add the opcode bytes in reverse order. */
3875 add_unwind_opcode (op
[count
], 1);
3877 demand_empty_rest_of_line ();
3881 /* Parse a .eabi_attribute directive. */
3884 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
3886 s_vendor_attribute (OBJ_ATTR_PROC
);
3888 #endif /* OBJ_ELF */
3890 static void s_arm_arch (int);
3891 static void s_arm_object_arch (int);
3892 static void s_arm_cpu (int);
3893 static void s_arm_fpu (int);
3898 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
3905 if (exp
.X_op
== O_symbol
)
3906 exp
.X_op
= O_secrel
;
3908 emit_expr (&exp
, 4);
3910 while (*input_line_pointer
++ == ',');
3912 input_line_pointer
--;
3913 demand_empty_rest_of_line ();
3917 /* This table describes all the machine specific pseudo-ops the assembler
3918 has to support. The fields are:
3919 pseudo-op name without dot
3920 function to call to execute this pseudo-op
3921 Integer arg to pass to the function. */
3923 const pseudo_typeS md_pseudo_table
[] =
3925 /* Never called because '.req' does not start a line. */
3926 { "req", s_req
, 0 },
3927 /* Following two are likewise never called. */
3930 { "unreq", s_unreq
, 0 },
3931 { "bss", s_bss
, 0 },
3932 { "align", s_align
, 0 },
3933 { "arm", s_arm
, 0 },
3934 { "thumb", s_thumb
, 0 },
3935 { "code", s_code
, 0 },
3936 { "force_thumb", s_force_thumb
, 0 },
3937 { "thumb_func", s_thumb_func
, 0 },
3938 { "thumb_set", s_thumb_set
, 0 },
3939 { "even", s_even
, 0 },
3940 { "ltorg", s_ltorg
, 0 },
3941 { "pool", s_ltorg
, 0 },
3942 { "syntax", s_syntax
, 0 },
3943 { "cpu", s_arm_cpu
, 0 },
3944 { "arch", s_arm_arch
, 0 },
3945 { "object_arch", s_arm_object_arch
, 0 },
3946 { "fpu", s_arm_fpu
, 0 },
3948 { "word", s_arm_elf_cons
, 4 },
3949 { "long", s_arm_elf_cons
, 4 },
3950 { "rel31", s_arm_rel31
, 0 },
3951 { "fnstart", s_arm_unwind_fnstart
, 0 },
3952 { "fnend", s_arm_unwind_fnend
, 0 },
3953 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
3954 { "personality", s_arm_unwind_personality
, 0 },
3955 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
3956 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
3957 { "save", s_arm_unwind_save
, 0 },
3958 { "vsave", s_arm_unwind_save
, 1 },
3959 { "movsp", s_arm_unwind_movsp
, 0 },
3960 { "pad", s_arm_unwind_pad
, 0 },
3961 { "setfp", s_arm_unwind_setfp
, 0 },
3962 { "unwind_raw", s_arm_unwind_raw
, 0 },
3963 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
3967 /* These are used for dwarf. */
3971 /* These are used for dwarf2. */
3972 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
3973 { "loc", dwarf2_directive_loc
, 0 },
3974 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
3976 { "extend", float_cons
, 'x' },
3977 { "ldouble", float_cons
, 'x' },
3978 { "packed", float_cons
, 'p' },
3980 {"secrel32", pe_directive_secrel
, 0},
3985 /* Parser functions used exclusively in instruction operands. */
3987 /* Generic immediate-value read function for use in insn parsing.
3988 STR points to the beginning of the immediate (the leading #);
3989 VAL receives the value; if the value is outside [MIN, MAX]
3990 issue an error. PREFIX_OPT is true if the immediate prefix is
3994 parse_immediate (char **str
, int *val
, int min
, int max
,
3995 bfd_boolean prefix_opt
)
3998 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
3999 if (exp
.X_op
!= O_constant
)
4001 inst
.error
= _("constant expression required");
4005 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4007 inst
.error
= _("immediate value out of range");
4011 *val
= exp
.X_add_number
;
4015 /* Less-generic immediate-value read function with the possibility of loading a
4016 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4017 instructions. Puts the result directly in inst.operands[i]. */
4020 parse_big_immediate (char **str
, int i
)
4025 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4027 if (exp
.X_op
== O_constant
)
4029 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4030 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4031 O_constant. We have to be careful not to break compilation for
4032 32-bit X_add_number, though. */
4033 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4035 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4036 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4037 inst
.operands
[i
].regisimm
= 1;
4040 else if (exp
.X_op
== O_big
4041 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4042 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4044 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4045 /* Bignums have their least significant bits in
4046 generic_bignum[0]. Make sure we put 32 bits in imm and
4047 32 bits in reg, in a (hopefully) portable way. */
4048 assert (parts
!= 0);
4049 inst
.operands
[i
].imm
= 0;
4050 for (j
= 0; j
< parts
; j
++, idx
++)
4051 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4052 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4053 inst
.operands
[i
].reg
= 0;
4054 for (j
= 0; j
< parts
; j
++, idx
++)
4055 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4056 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4057 inst
.operands
[i
].regisimm
= 1;
4067 /* Returns the pseudo-register number of an FPA immediate constant,
4068 or FAIL if there isn't a valid constant here. */
4071 parse_fpa_immediate (char ** str
)
4073 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4079 /* First try and match exact strings, this is to guarantee
4080 that some formats will work even for cross assembly. */
4082 for (i
= 0; fp_const
[i
]; i
++)
4084 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4088 *str
+= strlen (fp_const
[i
]);
4089 if (is_end_of_line
[(unsigned char) **str
])
4095 /* Just because we didn't get a match doesn't mean that the constant
4096 isn't valid, just that it is in a format that we don't
4097 automatically recognize. Try parsing it with the standard
4098 expression routines. */
4100 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4102 /* Look for a raw floating point number. */
4103 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4104 && is_end_of_line
[(unsigned char) *save_in
])
4106 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4108 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4110 if (words
[j
] != fp_values
[i
][j
])
4114 if (j
== MAX_LITTLENUMS
)
4122 /* Try and parse a more complex expression, this will probably fail
4123 unless the code uses a floating point prefix (eg "0f"). */
4124 save_in
= input_line_pointer
;
4125 input_line_pointer
= *str
;
4126 if (expression (&exp
) == absolute_section
4127 && exp
.X_op
== O_big
4128 && exp
.X_add_number
< 0)
4130 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4132 if (gen_to_words (words
, 5, (long) 15) == 0)
4134 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4136 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4138 if (words
[j
] != fp_values
[i
][j
])
4142 if (j
== MAX_LITTLENUMS
)
4144 *str
= input_line_pointer
;
4145 input_line_pointer
= save_in
;
4152 *str
= input_line_pointer
;
4153 input_line_pointer
= save_in
;
4154 inst
.error
= _("invalid FPA immediate expression");
4158 /* Returns 1 if a number has "quarter-precision" float format
4159 0baBbbbbbc defgh000 00000000 00000000. */
4162 is_quarter_float (unsigned imm
)
4164 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4165 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4168 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4169 0baBbbbbbc defgh000 00000000 00000000.
4170 The zero and minus-zero cases need special handling, since they can't be
4171 encoded in the "quarter-precision" float format, but can nonetheless be
4172 loaded as integer constants. */
4175 parse_qfloat_immediate (char **ccp
, int *immed
)
4179 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4180 int found_fpchar
= 0;
4182 skip_past_char (&str
, '#');
4184 /* We must not accidentally parse an integer as a floating-point number. Make
4185 sure that the value we parse is not an integer by checking for special
4186 characters '.' or 'e'.
4187 FIXME: This is a horrible hack, but doing better is tricky because type
4188 information isn't in a very usable state at parse time. */
4190 skip_whitespace (fpnum
);
4192 if (strncmp (fpnum
, "0x", 2) == 0)
4196 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4197 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4207 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4209 unsigned fpword
= 0;
4212 /* Our FP word must be 32 bits (single-precision FP). */
4213 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4215 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4219 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4232 /* Shift operands. */
4235 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4238 struct asm_shift_name
4241 enum shift_kind kind
;
4244 /* Third argument to parse_shift. */
4245 enum parse_shift_mode
4247 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4248 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4249 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4250 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4251 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4254 /* Parse a <shift> specifier on an ARM data processing instruction.
4255 This has three forms:
4257 (LSL|LSR|ASL|ASR|ROR) Rs
4258 (LSL|LSR|ASL|ASR|ROR) #imm
4261 Note that ASL is assimilated to LSL in the instruction encoding, and
4262 RRX to ROR #0 (which cannot be written as such). */
4265 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4267 const struct asm_shift_name
*shift_name
;
4268 enum shift_kind shift
;
4273 for (p
= *str
; ISALPHA (*p
); p
++)
4278 inst
.error
= _("shift expression expected");
4282 shift_name
= hash_find_n (arm_shift_hsh
, *str
, p
- *str
);
4284 if (shift_name
== NULL
)
4286 inst
.error
= _("shift expression expected");
4290 shift
= shift_name
->kind
;
4294 case NO_SHIFT_RESTRICT
:
4295 case SHIFT_IMMEDIATE
: break;
4297 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4298 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4300 inst
.error
= _("'LSL' or 'ASR' required");
4305 case SHIFT_LSL_IMMEDIATE
:
4306 if (shift
!= SHIFT_LSL
)
4308 inst
.error
= _("'LSL' required");
4313 case SHIFT_ASR_IMMEDIATE
:
4314 if (shift
!= SHIFT_ASR
)
4316 inst
.error
= _("'ASR' required");
4324 if (shift
!= SHIFT_RRX
)
4326 /* Whitespace can appear here if the next thing is a bare digit. */
4327 skip_whitespace (p
);
4329 if (mode
== NO_SHIFT_RESTRICT
4330 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4332 inst
.operands
[i
].imm
= reg
;
4333 inst
.operands
[i
].immisreg
= 1;
4335 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4338 inst
.operands
[i
].shift_kind
= shift
;
4339 inst
.operands
[i
].shifted
= 1;
4344 /* Parse a <shifter_operand> for an ARM data processing instruction:
4347 #<immediate>, <rotate>
4351 where <shift> is defined by parse_shift above, and <rotate> is a
4352 multiple of 2 between 0 and 30. Validation of immediate operands
4353 is deferred to md_apply_fix. */
4356 parse_shifter_operand (char **str
, int i
)
4361 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4363 inst
.operands
[i
].reg
= value
;
4364 inst
.operands
[i
].isreg
= 1;
4366 /* parse_shift will override this if appropriate */
4367 inst
.reloc
.exp
.X_op
= O_constant
;
4368 inst
.reloc
.exp
.X_add_number
= 0;
4370 if (skip_past_comma (str
) == FAIL
)
4373 /* Shift operation on register. */
4374 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4377 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4380 if (skip_past_comma (str
) == SUCCESS
)
4382 /* #x, y -- ie explicit rotation by Y. */
4383 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
4386 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4388 inst
.error
= _("constant expression expected");
4392 value
= expr
.X_add_number
;
4393 if (value
< 0 || value
> 30 || value
% 2 != 0)
4395 inst
.error
= _("invalid rotation");
4398 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4400 inst
.error
= _("invalid constant");
4404 /* Convert to decoded value. md_apply_fix will put it back. */
4405 inst
.reloc
.exp
.X_add_number
4406 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4407 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4410 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4411 inst
.reloc
.pc_rel
= 0;
4415 /* Group relocation information. Each entry in the table contains the
4416 textual name of the relocation as may appear in assembler source
4417 and must end with a colon.
4418 Along with this textual name are the relocation codes to be used if
4419 the corresponding instruction is an ALU instruction (ADD or SUB only),
4420 an LDR, an LDRS, or an LDC. */
4422 struct group_reloc_table_entry
4433 /* Varieties of non-ALU group relocation. */
4440 static struct group_reloc_table_entry group_reloc_table
[] =
4441 { /* Program counter relative: */
4443 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4448 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4449 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4450 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4451 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4453 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4458 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4459 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4460 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4461 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4463 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4464 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4465 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4466 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4467 /* Section base relative */
4469 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4474 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4475 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4476 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4477 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4479 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4484 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4485 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4486 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4487 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4489 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4490 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4491 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4492 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4494 /* Given the address of a pointer pointing to the textual name of a group
4495 relocation as may appear in assembler source, attempt to find its details
4496 in group_reloc_table. The pointer will be updated to the character after
4497 the trailing colon. On failure, FAIL will be returned; SUCCESS
4498 otherwise. On success, *entry will be updated to point at the relevant
4499 group_reloc_table entry. */
4502 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4505 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4507 int length
= strlen (group_reloc_table
[i
].name
);
4509 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4510 && (*str
)[length
] == ':')
4512 *out
= &group_reloc_table
[i
];
4513 *str
+= (length
+ 1);
4521 /* Parse a <shifter_operand> for an ARM data processing instruction
4522 (as for parse_shifter_operand) where group relocations are allowed:
4525 #<immediate>, <rotate>
4526 #:<group_reloc>:<expression>
4530 where <group_reloc> is one of the strings defined in group_reloc_table.
4531 The hashes are optional.
4533 Everything else is as for parse_shifter_operand. */
4535 static parse_operand_result
4536 parse_shifter_operand_group_reloc (char **str
, int i
)
4538 /* Determine if we have the sequence of characters #: or just :
4539 coming next. If we do, then we check for a group relocation.
4540 If we don't, punt the whole lot to parse_shifter_operand. */
4542 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4543 || (*str
)[0] == ':')
4545 struct group_reloc_table_entry
*entry
;
4547 if ((*str
)[0] == '#')
4552 /* Try to parse a group relocation. Anything else is an error. */
4553 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4555 inst
.error
= _("unknown group relocation");
4556 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4559 /* We now have the group relocation table entry corresponding to
4560 the name in the assembler source. Next, we parse the expression. */
4561 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4562 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4564 /* Record the relocation type (always the ALU variant here). */
4565 inst
.reloc
.type
= entry
->alu_code
;
4566 assert (inst
.reloc
.type
!= 0);
4568 return PARSE_OPERAND_SUCCESS
;
4571 return parse_shifter_operand (str
, i
) == SUCCESS
4572 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4574 /* Never reached. */
4577 /* Parse all forms of an ARM address expression. Information is written
4578 to inst.operands[i] and/or inst.reloc.
4580 Preindexed addressing (.preind=1):
4582 [Rn, #offset] .reg=Rn .reloc.exp=offset
4583 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4584 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4585 .shift_kind=shift .reloc.exp=shift_imm
4587 These three may have a trailing ! which causes .writeback to be set also.
4589 Postindexed addressing (.postind=1, .writeback=1):
4591 [Rn], #offset .reg=Rn .reloc.exp=offset
4592 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4593 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4594 .shift_kind=shift .reloc.exp=shift_imm
4596 Unindexed addressing (.preind=0, .postind=0):
4598 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4602 [Rn]{!} shorthand for [Rn,#0]{!}
4603 =immediate .isreg=0 .reloc.exp=immediate
4604 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4606 It is the caller's responsibility to check for addressing modes not
4607 supported by the instruction, and to set inst.reloc.type. */
4609 static parse_operand_result
4610 parse_address_main (char **str
, int i
, int group_relocations
,
4611 group_reloc_type group_type
)
4616 if (skip_past_char (&p
, '[') == FAIL
)
4618 if (skip_past_char (&p
, '=') == FAIL
)
4620 /* bare address - translate to PC-relative offset */
4621 inst
.reloc
.pc_rel
= 1;
4622 inst
.operands
[i
].reg
= REG_PC
;
4623 inst
.operands
[i
].isreg
= 1;
4624 inst
.operands
[i
].preind
= 1;
4626 /* else a load-constant pseudo op, no special treatment needed here */
4628 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4629 return PARSE_OPERAND_FAIL
;
4632 return PARSE_OPERAND_SUCCESS
;
4635 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4637 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4638 return PARSE_OPERAND_FAIL
;
4640 inst
.operands
[i
].reg
= reg
;
4641 inst
.operands
[i
].isreg
= 1;
4643 if (skip_past_comma (&p
) == SUCCESS
)
4645 inst
.operands
[i
].preind
= 1;
4648 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4650 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4652 inst
.operands
[i
].imm
= reg
;
4653 inst
.operands
[i
].immisreg
= 1;
4655 if (skip_past_comma (&p
) == SUCCESS
)
4656 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4657 return PARSE_OPERAND_FAIL
;
4659 else if (skip_past_char (&p
, ':') == SUCCESS
)
4661 /* FIXME: '@' should be used here, but it's filtered out by generic
4662 code before we get to see it here. This may be subject to
4665 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4666 if (exp
.X_op
!= O_constant
)
4668 inst
.error
= _("alignment must be constant");
4669 return PARSE_OPERAND_FAIL
;
4671 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4672 inst
.operands
[i
].immisalign
= 1;
4673 /* Alignments are not pre-indexes. */
4674 inst
.operands
[i
].preind
= 0;
4678 if (inst
.operands
[i
].negative
)
4680 inst
.operands
[i
].negative
= 0;
4684 if (group_relocations
4685 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
4687 struct group_reloc_table_entry
*entry
;
4689 /* Skip over the #: or : sequence. */
4695 /* Try to parse a group relocation. Anything else is an
4697 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
4699 inst
.error
= _("unknown group relocation");
4700 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4703 /* We now have the group relocation table entry corresponding to
4704 the name in the assembler source. Next, we parse the
4706 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4707 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4709 /* Record the relocation type. */
4713 inst
.reloc
.type
= entry
->ldr_code
;
4717 inst
.reloc
.type
= entry
->ldrs_code
;
4721 inst
.reloc
.type
= entry
->ldc_code
;
4728 if (inst
.reloc
.type
== 0)
4730 inst
.error
= _("this group relocation is not allowed on this instruction");
4731 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4735 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4736 return PARSE_OPERAND_FAIL
;
4740 if (skip_past_char (&p
, ']') == FAIL
)
4742 inst
.error
= _("']' expected");
4743 return PARSE_OPERAND_FAIL
;
4746 if (skip_past_char (&p
, '!') == SUCCESS
)
4747 inst
.operands
[i
].writeback
= 1;
4749 else if (skip_past_comma (&p
) == SUCCESS
)
4751 if (skip_past_char (&p
, '{') == SUCCESS
)
4753 /* [Rn], {expr} - unindexed, with option */
4754 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
4755 0, 255, TRUE
) == FAIL
)
4756 return PARSE_OPERAND_FAIL
;
4758 if (skip_past_char (&p
, '}') == FAIL
)
4760 inst
.error
= _("'}' expected at end of 'option' field");
4761 return PARSE_OPERAND_FAIL
;
4763 if (inst
.operands
[i
].preind
)
4765 inst
.error
= _("cannot combine index with option");
4766 return PARSE_OPERAND_FAIL
;
4769 return PARSE_OPERAND_SUCCESS
;
4773 inst
.operands
[i
].postind
= 1;
4774 inst
.operands
[i
].writeback
= 1;
4776 if (inst
.operands
[i
].preind
)
4778 inst
.error
= _("cannot combine pre- and post-indexing");
4779 return PARSE_OPERAND_FAIL
;
4783 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4785 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4787 /* We might be using the immediate for alignment already. If we
4788 are, OR the register number into the low-order bits. */
4789 if (inst
.operands
[i
].immisalign
)
4790 inst
.operands
[i
].imm
|= reg
;
4792 inst
.operands
[i
].imm
= reg
;
4793 inst
.operands
[i
].immisreg
= 1;
4795 if (skip_past_comma (&p
) == SUCCESS
)
4796 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4797 return PARSE_OPERAND_FAIL
;
4801 if (inst
.operands
[i
].negative
)
4803 inst
.operands
[i
].negative
= 0;
4806 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4807 return PARSE_OPERAND_FAIL
;
4812 /* If at this point neither .preind nor .postind is set, we have a
4813 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
4814 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
4816 inst
.operands
[i
].preind
= 1;
4817 inst
.reloc
.exp
.X_op
= O_constant
;
4818 inst
.reloc
.exp
.X_add_number
= 0;
4821 return PARSE_OPERAND_SUCCESS
;
4825 parse_address (char **str
, int i
)
4827 return parse_address_main (str
, i
, 0, 0) == PARSE_OPERAND_SUCCESS
4831 static parse_operand_result
4832 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
4834 return parse_address_main (str
, i
, 1, type
);
4837 /* Parse an operand for a MOVW or MOVT instruction. */
4839 parse_half (char **str
)
4844 skip_past_char (&p
, '#');
4845 if (strncasecmp (p
, ":lower16:", 9) == 0)
4846 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
4847 else if (strncasecmp (p
, ":upper16:", 9) == 0)
4848 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
4850 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4853 skip_whitespace (p
);
4856 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4859 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4861 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4863 inst
.error
= _("constant expression expected");
4866 if (inst
.reloc
.exp
.X_add_number
< 0
4867 || inst
.reloc
.exp
.X_add_number
> 0xffff)
4869 inst
.error
= _("immediate value out of range");
4877 /* Miscellaneous. */
4879 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
4880 or a bitmask suitable to be or-ed into the ARM msr instruction. */
4882 parse_psr (char **str
)
4885 unsigned long psr_field
;
4886 const struct asm_psr
*psr
;
4889 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
4890 feature for ease of use and backwards compatibility. */
4892 if (strncasecmp (p
, "SPSR", 4) == 0)
4893 psr_field
= SPSR_BIT
;
4894 else if (strncasecmp (p
, "CPSR", 4) == 0)
4901 while (ISALNUM (*p
) || *p
== '_');
4903 psr
= hash_find_n (arm_v7m_psr_hsh
, start
, p
- start
);
4914 /* A suffix follows. */
4920 while (ISALNUM (*p
) || *p
== '_');
4922 psr
= hash_find_n (arm_psr_hsh
, start
, p
- start
);
4926 psr_field
|= psr
->field
;
4931 goto error
; /* Garbage after "[CS]PSR". */
4933 psr_field
|= (PSR_c
| PSR_f
);
4939 inst
.error
= _("flag for {c}psr instruction expected");
4943 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
4944 value suitable for splatting into the AIF field of the instruction. */
4947 parse_cps_flags (char **str
)
4956 case '\0': case ',':
4959 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
4960 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
4961 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
4964 inst
.error
= _("unrecognized CPS flag");
4969 if (saw_a_flag
== 0)
4971 inst
.error
= _("missing CPS flags");
4979 /* Parse an endian specifier ("BE" or "LE", case insensitive);
4980 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
4983 parse_endian_specifier (char **str
)
4988 if (strncasecmp (s
, "BE", 2))
4990 else if (strncasecmp (s
, "LE", 2))
4994 inst
.error
= _("valid endian specifiers are be or le");
4998 if (ISALNUM (s
[2]) || s
[2] == '_')
5000 inst
.error
= _("valid endian specifiers are be or le");
5005 return little_endian
;
5008 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5009 value suitable for poking into the rotate field of an sxt or sxta
5010 instruction, or FAIL on error. */
5013 parse_ror (char **str
)
5018 if (strncasecmp (s
, "ROR", 3) == 0)
5022 inst
.error
= _("missing rotation field after comma");
5026 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5031 case 0: *str
= s
; return 0x0;
5032 case 8: *str
= s
; return 0x1;
5033 case 16: *str
= s
; return 0x2;
5034 case 24: *str
= s
; return 0x3;
5037 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5042 /* Parse a conditional code (from conds[] below). The value returned is in the
5043 range 0 .. 14, or FAIL. */
5045 parse_cond (char **str
)
5048 const struct asm_cond
*c
;
5050 /* Condition codes are always 2 characters, so matching up to
5051 3 characters is sufficient. */
5056 while (ISALPHA (*q
) && n
< 3)
5058 cond
[n
] = TOLOWER(*q
);
5063 c
= hash_find_n (arm_cond_hsh
, cond
, n
);
5066 inst
.error
= _("condition required");
5074 /* Parse an option for a barrier instruction. Returns the encoding for the
5077 parse_barrier (char **str
)
5080 const struct asm_barrier_opt
*o
;
5083 while (ISALPHA (*q
))
5086 o
= hash_find_n (arm_barrier_opt_hsh
, p
, q
- p
);
5094 /* Parse the operands of a table branch instruction. Similar to a memory
5097 parse_tb (char **str
)
5102 if (skip_past_char (&p
, '[') == FAIL
)
5104 inst
.error
= _("'[' expected");
5108 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5110 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5113 inst
.operands
[0].reg
= reg
;
5115 if (skip_past_comma (&p
) == FAIL
)
5117 inst
.error
= _("',' expected");
5121 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5123 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5126 inst
.operands
[0].imm
= reg
;
5128 if (skip_past_comma (&p
) == SUCCESS
)
5130 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5132 if (inst
.reloc
.exp
.X_add_number
!= 1)
5134 inst
.error
= _("invalid shift");
5137 inst
.operands
[0].shifted
= 1;
5140 if (skip_past_char (&p
, ']') == FAIL
)
5142 inst
.error
= _("']' expected");
5149 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5150 information on the types the operands can take and how they are encoded.
5151 Up to four operands may be read; this function handles setting the
5152 ".present" field for each read operand itself.
5153 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5154 else returns FAIL. */
5157 parse_neon_mov (char **str
, int *which_operand
)
5159 int i
= *which_operand
, val
;
5160 enum arm_reg_type rtype
;
5162 struct neon_type_el optype
;
5164 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5166 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5167 inst
.operands
[i
].reg
= val
;
5168 inst
.operands
[i
].isscalar
= 1;
5169 inst
.operands
[i
].vectype
= optype
;
5170 inst
.operands
[i
++].present
= 1;
5172 if (skip_past_comma (&ptr
) == FAIL
)
5175 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5178 inst
.operands
[i
].reg
= val
;
5179 inst
.operands
[i
].isreg
= 1;
5180 inst
.operands
[i
].present
= 1;
5182 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5185 /* Cases 0, 1, 2, 3, 5 (D only). */
5186 if (skip_past_comma (&ptr
) == FAIL
)
5189 inst
.operands
[i
].reg
= val
;
5190 inst
.operands
[i
].isreg
= 1;
5191 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5192 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5193 inst
.operands
[i
].isvec
= 1;
5194 inst
.operands
[i
].vectype
= optype
;
5195 inst
.operands
[i
++].present
= 1;
5197 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5199 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5200 Case 13: VMOV <Sd>, <Rm> */
5201 inst
.operands
[i
].reg
= val
;
5202 inst
.operands
[i
].isreg
= 1;
5203 inst
.operands
[i
].present
= 1;
5205 if (rtype
== REG_TYPE_NQ
)
5207 first_error (_("can't use Neon quad register here"));
5210 else if (rtype
!= REG_TYPE_VFS
)
5213 if (skip_past_comma (&ptr
) == FAIL
)
5215 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5217 inst
.operands
[i
].reg
= val
;
5218 inst
.operands
[i
].isreg
= 1;
5219 inst
.operands
[i
].present
= 1;
5222 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5225 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5226 Case 1: VMOV<c><q> <Dd>, <Dm>
5227 Case 8: VMOV.F32 <Sd>, <Sm>
5228 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5230 inst
.operands
[i
].reg
= val
;
5231 inst
.operands
[i
].isreg
= 1;
5232 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5233 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5234 inst
.operands
[i
].isvec
= 1;
5235 inst
.operands
[i
].vectype
= optype
;
5236 inst
.operands
[i
].present
= 1;
5238 if (skip_past_comma (&ptr
) == SUCCESS
)
5243 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5246 inst
.operands
[i
].reg
= val
;
5247 inst
.operands
[i
].isreg
= 1;
5248 inst
.operands
[i
++].present
= 1;
5250 if (skip_past_comma (&ptr
) == FAIL
)
5253 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5256 inst
.operands
[i
].reg
= val
;
5257 inst
.operands
[i
].isreg
= 1;
5258 inst
.operands
[i
++].present
= 1;
5261 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5262 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5263 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5264 Case 10: VMOV.F32 <Sd>, #<imm>
5265 Case 11: VMOV.F64 <Dd>, #<imm> */
5266 inst
.operands
[i
].immisfloat
= 1;
5267 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5268 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5269 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5273 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5277 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5280 inst
.operands
[i
].reg
= val
;
5281 inst
.operands
[i
].isreg
= 1;
5282 inst
.operands
[i
++].present
= 1;
5284 if (skip_past_comma (&ptr
) == FAIL
)
5287 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5289 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5290 inst
.operands
[i
].reg
= val
;
5291 inst
.operands
[i
].isscalar
= 1;
5292 inst
.operands
[i
].present
= 1;
5293 inst
.operands
[i
].vectype
= optype
;
5295 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5297 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5298 inst
.operands
[i
].reg
= val
;
5299 inst
.operands
[i
].isreg
= 1;
5300 inst
.operands
[i
++].present
= 1;
5302 if (skip_past_comma (&ptr
) == FAIL
)
5305 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5308 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5312 inst
.operands
[i
].reg
= val
;
5313 inst
.operands
[i
].isreg
= 1;
5314 inst
.operands
[i
].isvec
= 1;
5315 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5316 inst
.operands
[i
].vectype
= optype
;
5317 inst
.operands
[i
].present
= 1;
5319 if (rtype
== REG_TYPE_VFS
)
5323 if (skip_past_comma (&ptr
) == FAIL
)
5325 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5328 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5331 inst
.operands
[i
].reg
= val
;
5332 inst
.operands
[i
].isreg
= 1;
5333 inst
.operands
[i
].isvec
= 1;
5334 inst
.operands
[i
].issingle
= 1;
5335 inst
.operands
[i
].vectype
= optype
;
5336 inst
.operands
[i
].present
= 1;
5339 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5343 inst
.operands
[i
].reg
= val
;
5344 inst
.operands
[i
].isreg
= 1;
5345 inst
.operands
[i
].isvec
= 1;
5346 inst
.operands
[i
].issingle
= 1;
5347 inst
.operands
[i
].vectype
= optype
;
5348 inst
.operands
[i
++].present
= 1;
5353 first_error (_("parse error"));
5357 /* Successfully parsed the operands. Update args. */
5363 first_error (_("expected comma"));
5367 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5371 /* Matcher codes for parse_operands. */
5372 enum operand_parse_code
5374 OP_stop
, /* end of line */
5376 OP_RR
, /* ARM register */
5377 OP_RRnpc
, /* ARM register, not r15 */
5378 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5379 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5380 OP_RCP
, /* Coprocessor number */
5381 OP_RCN
, /* Coprocessor register */
5382 OP_RF
, /* FPA register */
5383 OP_RVS
, /* VFP single precision register */
5384 OP_RVD
, /* VFP double precision register (0..15) */
5385 OP_RND
, /* Neon double precision register (0..31) */
5386 OP_RNQ
, /* Neon quad precision register */
5387 OP_RVSD
, /* VFP single or double precision register */
5388 OP_RNDQ
, /* Neon double or quad precision register */
5389 OP_RNSDQ
, /* Neon single, double or quad precision register */
5390 OP_RNSC
, /* Neon scalar D[X] */
5391 OP_RVC
, /* VFP control register */
5392 OP_RMF
, /* Maverick F register */
5393 OP_RMD
, /* Maverick D register */
5394 OP_RMFX
, /* Maverick FX register */
5395 OP_RMDX
, /* Maverick DX register */
5396 OP_RMAX
, /* Maverick AX register */
5397 OP_RMDS
, /* Maverick DSPSC register */
5398 OP_RIWR
, /* iWMMXt wR register */
5399 OP_RIWC
, /* iWMMXt wC register */
5400 OP_RIWG
, /* iWMMXt wCG register */
5401 OP_RXA
, /* XScale accumulator register */
5403 OP_REGLST
, /* ARM register list */
5404 OP_VRSLST
, /* VFP single-precision register list */
5405 OP_VRDLST
, /* VFP double-precision register list */
5406 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5407 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5408 OP_NSTRLST
, /* Neon element/structure list */
5410 OP_NILO
, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5411 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5412 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5413 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5414 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5415 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5416 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5417 OP_VMOV
, /* Neon VMOV operands. */
5418 OP_RNDQ_IMVNb
,/* Neon D or Q reg, or immediate good for VMVN. */
5419 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5420 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5422 OP_I0
, /* immediate zero */
5423 OP_I7
, /* immediate value 0 .. 7 */
5424 OP_I15
, /* 0 .. 15 */
5425 OP_I16
, /* 1 .. 16 */
5426 OP_I16z
, /* 0 .. 16 */
5427 OP_I31
, /* 0 .. 31 */
5428 OP_I31w
, /* 0 .. 31, optional trailing ! */
5429 OP_I32
, /* 1 .. 32 */
5430 OP_I32z
, /* 0 .. 32 */
5431 OP_I63
, /* 0 .. 63 */
5432 OP_I63s
, /* -64 .. 63 */
5433 OP_I64
, /* 1 .. 64 */
5434 OP_I64z
, /* 0 .. 64 */
5435 OP_I255
, /* 0 .. 255 */
5437 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5438 OP_I7b
, /* 0 .. 7 */
5439 OP_I15b
, /* 0 .. 15 */
5440 OP_I31b
, /* 0 .. 31 */
5442 OP_SH
, /* shifter operand */
5443 OP_SHG
, /* shifter operand with possible group relocation */
5444 OP_ADDR
, /* Memory address expression (any mode) */
5445 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5446 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5447 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5448 OP_EXP
, /* arbitrary expression */
5449 OP_EXPi
, /* same, with optional immediate prefix */
5450 OP_EXPr
, /* same, with optional relocation suffix */
5451 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5453 OP_CPSF
, /* CPS flags */
5454 OP_ENDI
, /* Endianness specifier */
5455 OP_PSR
, /* CPSR/SPSR mask for msr */
5456 OP_COND
, /* conditional code */
5457 OP_TB
, /* Table branch. */
5459 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5460 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5462 OP_RRnpc_I0
, /* ARM register or literal 0 */
5463 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5464 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5465 OP_RF_IF
, /* FPA register or immediate */
5466 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5467 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5469 /* Optional operands. */
5470 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5471 OP_oI31b
, /* 0 .. 31 */
5472 OP_oI32b
, /* 1 .. 32 */
5473 OP_oIffffb
, /* 0 .. 65535 */
5474 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5476 OP_oRR
, /* ARM register */
5477 OP_oRRnpc
, /* ARM register, not the PC */
5478 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5479 OP_oRND
, /* Optional Neon double precision register */
5480 OP_oRNQ
, /* Optional Neon quad precision register */
5481 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5482 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5483 OP_oSHll
, /* LSL immediate */
5484 OP_oSHar
, /* ASR immediate */
5485 OP_oSHllar
, /* LSL or ASR immediate */
5486 OP_oROR
, /* ROR 0/8/16/24 */
5487 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5489 OP_FIRST_OPTIONAL
= OP_oI7b
5492 /* Generic instruction operand parser. This does no encoding and no
5493 semantic validation; it merely squirrels values away in the inst
5494 structure. Returns SUCCESS or FAIL depending on whether the
5495 specified grammar matched. */
5497 parse_operands (char *str
, const unsigned char *pattern
)
5499 unsigned const char *upat
= pattern
;
5500 char *backtrack_pos
= 0;
5501 const char *backtrack_error
= 0;
5502 int i
, val
, backtrack_index
= 0;
5503 enum arm_reg_type rtype
;
5504 parse_operand_result result
;
5506 #define po_char_or_fail(chr) do { \
5507 if (skip_past_char (&str, chr) == FAIL) \
5511 #define po_reg_or_fail(regtype) do { \
5512 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5513 &inst.operands[i].vectype); \
5516 first_error (_(reg_expected_msgs[regtype])); \
5519 inst.operands[i].reg = val; \
5520 inst.operands[i].isreg = 1; \
5521 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5522 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5523 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5524 || rtype == REG_TYPE_VFD \
5525 || rtype == REG_TYPE_NQ); \
5528 #define po_reg_or_goto(regtype, label) do { \
5529 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5530 &inst.operands[i].vectype); \
5534 inst.operands[i].reg = val; \
5535 inst.operands[i].isreg = 1; \
5536 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5537 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5538 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5539 || rtype == REG_TYPE_VFD \
5540 || rtype == REG_TYPE_NQ); \
5543 #define po_imm_or_fail(min, max, popt) do { \
5544 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5546 inst.operands[i].imm = val; \
5549 #define po_scalar_or_goto(elsz, label) do { \
5550 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \
5553 inst.operands[i].reg = val; \
5554 inst.operands[i].isscalar = 1; \
5557 #define po_misc_or_fail(expr) do { \
5562 #define po_misc_or_fail_no_backtrack(expr) do { \
5564 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
5565 backtrack_pos = 0; \
5566 if (result != PARSE_OPERAND_SUCCESS) \
5570 skip_whitespace (str
);
5572 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5574 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5576 /* Remember where we are in case we need to backtrack. */
5577 assert (!backtrack_pos
);
5578 backtrack_pos
= str
;
5579 backtrack_error
= inst
.error
;
5580 backtrack_index
= i
;
5583 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
5584 po_char_or_fail (',');
5592 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5593 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5594 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5595 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5596 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5597 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5599 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5601 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
5603 /* Also accept generic coprocessor regs for unknown registers. */
5605 po_reg_or_fail (REG_TYPE_CN
);
5607 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5608 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5609 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5610 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5611 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5612 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5613 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5614 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5615 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5616 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5618 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
5620 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
5621 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
5623 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
5625 /* Neon scalar. Using an element size of 8 means that some invalid
5626 scalars are accepted here, so deal with those in later code. */
5627 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
5629 /* WARNING: We can expand to two operands here. This has the potential
5630 to totally confuse the backtracking mechanism! It will be OK at
5631 least as long as we don't try to use optional args as well,
5635 po_reg_or_goto (REG_TYPE_NDQ
, try_imm
);
5636 inst
.operands
[i
].present
= 1;
5638 skip_past_comma (&str
);
5639 po_reg_or_goto (REG_TYPE_NDQ
, one_reg_only
);
5642 /* Optional register operand was omitted. Unfortunately, it's in
5643 operands[i-1] and we need it to be in inst.operands[i]. Fix that
5644 here (this is a bit grotty). */
5645 inst
.operands
[i
] = inst
.operands
[i
-1];
5646 inst
.operands
[i
-1].present
= 0;
5649 /* There's a possibility of getting a 64-bit immediate here, so
5650 we need special handling. */
5651 if (parse_big_immediate (&str
, i
) == FAIL
)
5653 inst
.error
= _("immediate value is out of range");
5661 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
5664 po_imm_or_fail (0, 0, TRUE
);
5669 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
5674 po_scalar_or_goto (8, try_rr
);
5677 po_reg_or_fail (REG_TYPE_RN
);
5683 po_scalar_or_goto (8, try_nsdq
);
5686 po_reg_or_fail (REG_TYPE_NSDQ
);
5692 po_scalar_or_goto (8, try_ndq
);
5695 po_reg_or_fail (REG_TYPE_NDQ
);
5701 po_scalar_or_goto (8, try_vfd
);
5704 po_reg_or_fail (REG_TYPE_VFD
);
5709 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
5710 not careful then bad things might happen. */
5711 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
5716 po_reg_or_goto (REG_TYPE_NDQ
, try_mvnimm
);
5719 /* There's a possibility of getting a 64-bit immediate here, so
5720 we need special handling. */
5721 if (parse_big_immediate (&str
, i
) == FAIL
)
5723 inst
.error
= _("immediate value is out of range");
5731 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
5734 po_imm_or_fail (0, 63, TRUE
);
5739 po_char_or_fail ('[');
5740 po_reg_or_fail (REG_TYPE_RN
);
5741 po_char_or_fail (']');
5746 po_reg_or_fail (REG_TYPE_RN
);
5747 if (skip_past_char (&str
, '!') == SUCCESS
)
5748 inst
.operands
[i
].writeback
= 1;
5752 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
5753 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
5754 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
5755 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
5756 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
5757 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
5758 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
5759 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
5760 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
5761 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
5762 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
5763 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
5765 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
5767 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
5768 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
5770 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
5771 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
5772 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
5774 /* Immediate variants */
5776 po_char_or_fail ('{');
5777 po_imm_or_fail (0, 255, TRUE
);
5778 po_char_or_fail ('}');
5782 /* The expression parser chokes on a trailing !, so we have
5783 to find it first and zap it. */
5786 while (*s
&& *s
!= ',')
5791 inst
.operands
[i
].writeback
= 1;
5793 po_imm_or_fail (0, 31, TRUE
);
5801 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5806 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5811 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5813 if (inst
.reloc
.exp
.X_op
== O_symbol
)
5815 val
= parse_reloc (&str
);
5818 inst
.error
= _("unrecognized relocation suffix");
5821 else if (val
!= BFD_RELOC_UNUSED
)
5823 inst
.operands
[i
].imm
= val
;
5824 inst
.operands
[i
].hasreloc
= 1;
5829 /* Operand for MOVW or MOVT. */
5831 po_misc_or_fail (parse_half (&str
));
5834 /* Register or expression */
5835 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
5836 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
5838 /* Register or immediate */
5839 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
5840 I0
: po_imm_or_fail (0, 0, FALSE
); break;
5842 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
5844 if (!is_immediate_prefix (*str
))
5847 val
= parse_fpa_immediate (&str
);
5850 /* FPA immediates are encoded as registers 8-15.
5851 parse_fpa_immediate has already applied the offset. */
5852 inst
.operands
[i
].reg
= val
;
5853 inst
.operands
[i
].isreg
= 1;
5856 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
5857 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
5859 /* Two kinds of register */
5862 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5864 || (rege
->type
!= REG_TYPE_MMXWR
5865 && rege
->type
!= REG_TYPE_MMXWC
5866 && rege
->type
!= REG_TYPE_MMXWCG
))
5868 inst
.error
= _("iWMMXt data or control register expected");
5871 inst
.operands
[i
].reg
= rege
->number
;
5872 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
5878 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5880 || (rege
->type
!= REG_TYPE_MMXWC
5881 && rege
->type
!= REG_TYPE_MMXWCG
))
5883 inst
.error
= _("iWMMXt control register expected");
5886 inst
.operands
[i
].reg
= rege
->number
;
5887 inst
.operands
[i
].isreg
= 1;
5892 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
5893 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
5894 case OP_oROR
: val
= parse_ror (&str
); break;
5895 case OP_PSR
: val
= parse_psr (&str
); break;
5896 case OP_COND
: val
= parse_cond (&str
); break;
5897 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
5900 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
5901 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
5904 val
= parse_psr (&str
);
5908 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
5911 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
5913 if (strncasecmp (str
, "APSR_", 5) == 0)
5920 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
5921 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
5922 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
5923 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
5924 default: found
= 16;
5928 inst
.operands
[i
].isvec
= 1;
5935 po_misc_or_fail (parse_tb (&str
));
5938 /* Register lists */
5940 val
= parse_reg_list (&str
);
5943 inst
.operands
[1].writeback
= 1;
5949 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
5953 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
5957 /* Allow Q registers too. */
5958 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5963 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5965 inst
.operands
[i
].issingle
= 1;
5970 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5975 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
5976 &inst
.operands
[i
].vectype
);
5979 /* Addressing modes */
5981 po_misc_or_fail (parse_address (&str
, i
));
5985 po_misc_or_fail_no_backtrack (
5986 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
5990 po_misc_or_fail_no_backtrack (
5991 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
5995 po_misc_or_fail_no_backtrack (
5996 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6000 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6004 po_misc_or_fail_no_backtrack (
6005 parse_shifter_operand_group_reloc (&str
, i
));
6009 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6013 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6017 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6021 as_fatal (_("unhandled operand code %d"), upat
[i
]);
6024 /* Various value-based sanity checks and shared operations. We
6025 do not signal immediate failures for the register constraints;
6026 this allows a syntax error to take precedence. */
6035 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6036 inst
.error
= BAD_PC
;
6054 inst
.operands
[i
].imm
= val
;
6061 /* If we get here, this operand was successfully parsed. */
6062 inst
.operands
[i
].present
= 1;
6066 inst
.error
= BAD_ARGS
;
6071 /* The parse routine should already have set inst.error, but set a
6072 default here just in case. */
6074 inst
.error
= _("syntax error");
6078 /* Do not backtrack over a trailing optional argument that
6079 absorbed some text. We will only fail again, with the
6080 'garbage following instruction' error message, which is
6081 probably less helpful than the current one. */
6082 if (backtrack_index
== i
&& backtrack_pos
!= str
6083 && upat
[i
+1] == OP_stop
)
6086 inst
.error
= _("syntax error");
6090 /* Try again, skipping the optional argument at backtrack_pos. */
6091 str
= backtrack_pos
;
6092 inst
.error
= backtrack_error
;
6093 inst
.operands
[backtrack_index
].present
= 0;
6094 i
= backtrack_index
;
6098 /* Check that we have parsed all the arguments. */
6099 if (*str
!= '\0' && !inst
.error
)
6100 inst
.error
= _("garbage following instruction");
6102 return inst
.error
? FAIL
: SUCCESS
;
6105 #undef po_char_or_fail
6106 #undef po_reg_or_fail
6107 #undef po_reg_or_goto
6108 #undef po_imm_or_fail
6109 #undef po_scalar_or_fail
6111 /* Shorthand macro for instruction encoding functions issuing errors. */
6112 #define constraint(expr, err) do { \
6120 /* Functions for operand encoding. ARM, then Thumb. */
6122 #define rotate_left(v, n) (v << n | v >> (32 - n))
6124 /* If VAL can be encoded in the immediate field of an ARM instruction,
6125 return the encoded form. Otherwise, return FAIL. */
6128 encode_arm_immediate (unsigned int val
)
6132 for (i
= 0; i
< 32; i
+= 2)
6133 if ((a
= rotate_left (val
, i
)) <= 0xff)
6134 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6139 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6140 return the encoded form. Otherwise, return FAIL. */
6142 encode_thumb32_immediate (unsigned int val
)
6149 for (i
= 1; i
<= 24; i
++)
6152 if ((val
& ~(0xff << i
)) == 0)
6153 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6157 if (val
== ((a
<< 16) | a
))
6159 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6163 if (val
== ((a
<< 16) | a
))
6164 return 0x200 | (a
>> 8);
6168 /* Encode a VFP SP or DP register number into inst.instruction. */
6171 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6173 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6176 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6179 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6182 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6187 first_error (_("D register out of range for selected VFP version"));
6195 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6199 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6203 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6207 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6211 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6215 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6223 /* Encode a <shift> in an ARM-format instruction. The immediate,
6224 if any, is handled by md_apply_fix. */
6226 encode_arm_shift (int i
)
6228 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6229 inst
.instruction
|= SHIFT_ROR
<< 5;
6232 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6233 if (inst
.operands
[i
].immisreg
)
6235 inst
.instruction
|= SHIFT_BY_REG
;
6236 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6239 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6244 encode_arm_shifter_operand (int i
)
6246 if (inst
.operands
[i
].isreg
)
6248 inst
.instruction
|= inst
.operands
[i
].reg
;
6249 encode_arm_shift (i
);
6252 inst
.instruction
|= INST_IMMEDIATE
;
6255 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6257 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6259 assert (inst
.operands
[i
].isreg
);
6260 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6262 if (inst
.operands
[i
].preind
)
6266 inst
.error
= _("instruction does not accept preindexed addressing");
6269 inst
.instruction
|= PRE_INDEX
;
6270 if (inst
.operands
[i
].writeback
)
6271 inst
.instruction
|= WRITE_BACK
;
6274 else if (inst
.operands
[i
].postind
)
6276 assert (inst
.operands
[i
].writeback
);
6278 inst
.instruction
|= WRITE_BACK
;
6280 else /* unindexed - only for coprocessor */
6282 inst
.error
= _("instruction does not accept unindexed addressing");
6286 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6287 && (((inst
.instruction
& 0x000f0000) >> 16)
6288 == ((inst
.instruction
& 0x0000f000) >> 12)))
6289 as_warn ((inst
.instruction
& LOAD_BIT
)
6290 ? _("destination register same as write-back base")
6291 : _("source register same as write-back base"));
6294 /* inst.operands[i] was set up by parse_address. Encode it into an
6295 ARM-format mode 2 load or store instruction. If is_t is true,
6296 reject forms that cannot be used with a T instruction (i.e. not
6299 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6301 encode_arm_addr_mode_common (i
, is_t
);
6303 if (inst
.operands
[i
].immisreg
)
6305 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6306 inst
.instruction
|= inst
.operands
[i
].imm
;
6307 if (!inst
.operands
[i
].negative
)
6308 inst
.instruction
|= INDEX_UP
;
6309 if (inst
.operands
[i
].shifted
)
6311 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6312 inst
.instruction
|= SHIFT_ROR
<< 5;
6315 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6316 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6320 else /* immediate offset in inst.reloc */
6322 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6323 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6327 /* inst.operands[i] was set up by parse_address. Encode it into an
6328 ARM-format mode 3 load or store instruction. Reject forms that
6329 cannot be used with such instructions. If is_t is true, reject
6330 forms that cannot be used with a T instruction (i.e. not
6333 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6335 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6337 inst
.error
= _("instruction does not accept scaled register index");
6341 encode_arm_addr_mode_common (i
, is_t
);
6343 if (inst
.operands
[i
].immisreg
)
6345 inst
.instruction
|= inst
.operands
[i
].imm
;
6346 if (!inst
.operands
[i
].negative
)
6347 inst
.instruction
|= INDEX_UP
;
6349 else /* immediate offset in inst.reloc */
6351 inst
.instruction
|= HWOFFSET_IMM
;
6352 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6353 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6357 /* inst.operands[i] was set up by parse_address. Encode it into an
6358 ARM-format instruction. Reject all forms which cannot be encoded
6359 into a coprocessor load/store instruction. If wb_ok is false,
6360 reject use of writeback; if unind_ok is false, reject use of
6361 unindexed addressing. If reloc_override is not 0, use it instead
6362 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6363 (in which case it is preserved). */
6366 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6368 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6370 assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6372 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6374 assert (!inst
.operands
[i
].writeback
);
6377 inst
.error
= _("instruction does not support unindexed addressing");
6380 inst
.instruction
|= inst
.operands
[i
].imm
;
6381 inst
.instruction
|= INDEX_UP
;
6385 if (inst
.operands
[i
].preind
)
6386 inst
.instruction
|= PRE_INDEX
;
6388 if (inst
.operands
[i
].writeback
)
6390 if (inst
.operands
[i
].reg
== REG_PC
)
6392 inst
.error
= _("pc may not be used with write-back");
6397 inst
.error
= _("instruction does not support writeback");
6400 inst
.instruction
|= WRITE_BACK
;
6404 inst
.reloc
.type
= reloc_override
;
6405 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6406 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6407 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6410 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6412 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6418 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6419 Determine whether it can be performed with a move instruction; if
6420 it can, convert inst.instruction to that move instruction and
6421 return 1; if it can't, convert inst.instruction to a literal-pool
6422 load and return 0. If this is not a valid thing to do in the
6423 current context, set inst.error and return 1.
6425 inst.operands[i] describes the destination register. */
6428 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6433 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6437 if ((inst
.instruction
& tbit
) == 0)
6439 inst
.error
= _("invalid pseudo operation");
6442 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6444 inst
.error
= _("constant expression expected");
6447 if (inst
.reloc
.exp
.X_op
== O_constant
)
6451 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6453 /* This can be done with a mov(1) instruction. */
6454 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6455 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6461 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6464 /* This can be done with a mov instruction. */
6465 inst
.instruction
&= LITERAL_MASK
;
6466 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6467 inst
.instruction
|= value
& 0xfff;
6471 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6474 /* This can be done with a mvn instruction. */
6475 inst
.instruction
&= LITERAL_MASK
;
6476 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6477 inst
.instruction
|= value
& 0xfff;
6483 if (add_to_lit_pool () == FAIL
)
6485 inst
.error
= _("literal pool insertion failed");
6488 inst
.operands
[1].reg
= REG_PC
;
6489 inst
.operands
[1].isreg
= 1;
6490 inst
.operands
[1].preind
= 1;
6491 inst
.reloc
.pc_rel
= 1;
6492 inst
.reloc
.type
= (thumb_p
6493 ? BFD_RELOC_ARM_THUMB_OFFSET
6495 ? BFD_RELOC_ARM_HWLITERAL
6496 : BFD_RELOC_ARM_LITERAL
));
6500 /* Functions for instruction encoding, sorted by sub-architecture.
6501 First some generics; their names are taken from the conventional
6502 bit positions for register arguments in ARM format instructions. */
6512 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6518 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6519 inst
.instruction
|= inst
.operands
[1].reg
;
6525 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6526 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6532 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6533 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6539 unsigned Rn
= inst
.operands
[2].reg
;
6540 /* Enforce restrictions on SWP instruction. */
6541 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6542 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6543 _("Rn must not overlap other operands"));
6544 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6545 inst
.instruction
|= inst
.operands
[1].reg
;
6546 inst
.instruction
|= Rn
<< 16;
6552 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6553 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6554 inst
.instruction
|= inst
.operands
[2].reg
;
6560 inst
.instruction
|= inst
.operands
[0].reg
;
6561 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6562 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6568 inst
.instruction
|= inst
.operands
[0].imm
;
6574 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6575 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6578 /* ARM instructions, in alphabetical order by function name (except
6579 that wrapper functions appear immediately after the function they
6582 /* This is a pseudo-op of the form "adr rd, label" to be converted
6583 into a relative address of the form "add rd, pc, #label-.-8". */
6588 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6590 /* Frag hacking will turn this into a sub instruction if the offset turns
6591 out to be negative. */
6592 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6593 inst
.reloc
.pc_rel
= 1;
6594 inst
.reloc
.exp
.X_add_number
-= 8;
6597 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6598 into a relative address of the form:
6599 add rd, pc, #low(label-.-8)"
6600 add rd, rd, #high(label-.-8)" */
6605 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6607 /* Frag hacking will turn this into a sub instruction if the offset turns
6608 out to be negative. */
6609 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
6610 inst
.reloc
.pc_rel
= 1;
6611 inst
.size
= INSN_SIZE
* 2;
6612 inst
.reloc
.exp
.X_add_number
-= 8;
6618 if (!inst
.operands
[1].present
)
6619 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
6620 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6621 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6622 encode_arm_shifter_operand (2);
6628 if (inst
.operands
[0].present
)
6630 constraint ((inst
.instruction
& 0xf0) != 0x40
6631 && inst
.operands
[0].imm
!= 0xf,
6632 _("bad barrier type"));
6633 inst
.instruction
|= inst
.operands
[0].imm
;
6636 inst
.instruction
|= 0xf;
6642 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
6643 constraint (msb
> 32, _("bit-field extends past end of register"));
6644 /* The instruction encoding stores the LSB and MSB,
6645 not the LSB and width. */
6646 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6647 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
6648 inst
.instruction
|= (msb
- 1) << 16;
6656 /* #0 in second position is alternative syntax for bfc, which is
6657 the same instruction but with REG_PC in the Rm field. */
6658 if (!inst
.operands
[1].isreg
)
6659 inst
.operands
[1].reg
= REG_PC
;
6661 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
6662 constraint (msb
> 32, _("bit-field extends past end of register"));
6663 /* The instruction encoding stores the LSB and MSB,
6664 not the LSB and width. */
6665 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6666 inst
.instruction
|= inst
.operands
[1].reg
;
6667 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6668 inst
.instruction
|= (msb
- 1) << 16;
6674 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
6675 _("bit-field extends past end of register"));
6676 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6677 inst
.instruction
|= inst
.operands
[1].reg
;
6678 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6679 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
6682 /* ARM V5 breakpoint instruction (argument parse)
6683 BKPT <16 bit unsigned immediate>
6684 Instruction is not conditional.
6685 The bit pattern given in insns[] has the COND_ALWAYS condition,
6686 and it is an error if the caller tried to override that. */
6691 /* Top 12 of 16 bits to bits 19:8. */
6692 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
6694 /* Bottom 4 of 16 bits to bits 3:0. */
6695 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
6699 encode_branch (int default_reloc
)
6701 if (inst
.operands
[0].hasreloc
)
6703 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
6704 _("the only suffix valid here is '(plt)'"));
6705 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
6709 inst
.reloc
.type
= default_reloc
;
6711 inst
.reloc
.pc_rel
= 1;
6718 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6719 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6722 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6729 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6731 if (inst
.cond
== COND_ALWAYS
)
6732 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6734 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6738 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6741 /* ARM V5 branch-link-exchange instruction (argument parse)
6742 BLX <target_addr> ie BLX(1)
6743 BLX{<condition>} <Rm> ie BLX(2)
6744 Unfortunately, there are two different opcodes for this mnemonic.
6745 So, the insns[].value is not used, and the code here zaps values
6746 into inst.instruction.
6747 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
6752 if (inst
.operands
[0].isreg
)
6754 /* Arg is a register; the opcode provided by insns[] is correct.
6755 It is not illegal to do "blx pc", just useless. */
6756 if (inst
.operands
[0].reg
== REG_PC
)
6757 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
6759 inst
.instruction
|= inst
.operands
[0].reg
;
6763 /* Arg is an address; this instruction cannot be executed
6764 conditionally, and the opcode must be adjusted. */
6765 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
6766 inst
.instruction
= 0xfa000000;
6768 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6769 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6772 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
6779 bfd_boolean want_reloc
;
6781 if (inst
.operands
[0].reg
== REG_PC
)
6782 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
6784 inst
.instruction
|= inst
.operands
[0].reg
;
6785 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
6786 it is for ARMv4t or earlier. */
6787 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
6788 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
6792 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
6797 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
6801 /* ARM v5TEJ. Jump to Jazelle code. */
6806 if (inst
.operands
[0].reg
== REG_PC
)
6807 as_tsktsk (_("use of r15 in bxj is not really useful"));
6809 inst
.instruction
|= inst
.operands
[0].reg
;
6812 /* Co-processor data operation:
6813 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
6814 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
6818 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6819 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
6820 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6821 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6822 inst
.instruction
|= inst
.operands
[4].reg
;
6823 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6829 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6830 encode_arm_shifter_operand (1);
6833 /* Transfer between coprocessor and ARM registers.
6834 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
6839 No special properties. */
6844 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6845 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
6846 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6847 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6848 inst
.instruction
|= inst
.operands
[4].reg
;
6849 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6852 /* Transfer between coprocessor register and pair of ARM registers.
6853 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6858 Two XScale instructions are special cases of these:
6860 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
6861 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
6863 Result unpredictable if Rd or Rn is R15. */
6868 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6869 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
6870 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6871 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6872 inst
.instruction
|= inst
.operands
[4].reg
;
6878 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
6879 if (inst
.operands
[1].present
)
6881 inst
.instruction
|= CPSI_MMOD
;
6882 inst
.instruction
|= inst
.operands
[1].imm
;
6889 inst
.instruction
|= inst
.operands
[0].imm
;
6895 /* There is no IT instruction in ARM mode. We
6896 process it but do not generate code for it. */
6903 int base_reg
= inst
.operands
[0].reg
;
6904 int range
= inst
.operands
[1].imm
;
6906 inst
.instruction
|= base_reg
<< 16;
6907 inst
.instruction
|= range
;
6909 if (inst
.operands
[1].writeback
)
6910 inst
.instruction
|= LDM_TYPE_2_OR_3
;
6912 if (inst
.operands
[0].writeback
)
6914 inst
.instruction
|= WRITE_BACK
;
6915 /* Check for unpredictable uses of writeback. */
6916 if (inst
.instruction
& LOAD_BIT
)
6918 /* Not allowed in LDM type 2. */
6919 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
6920 && ((range
& (1 << REG_PC
)) == 0))
6921 as_warn (_("writeback of base register is UNPREDICTABLE"));
6922 /* Only allowed if base reg not in list for other types. */
6923 else if (range
& (1 << base_reg
))
6924 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
6928 /* Not allowed for type 2. */
6929 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
6930 as_warn (_("writeback of base register is UNPREDICTABLE"));
6931 /* Only allowed if base reg not in list, or first in list. */
6932 else if ((range
& (1 << base_reg
))
6933 && (range
& ((1 << base_reg
) - 1)))
6934 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
6939 /* ARMv5TE load-consecutive (argument parse)
6948 constraint (inst
.operands
[0].reg
% 2 != 0,
6949 _("first destination register must be even"));
6950 constraint (inst
.operands
[1].present
6951 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
6952 _("can only load two consecutive registers"));
6953 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
6954 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
6956 if (!inst
.operands
[1].present
)
6957 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
6959 if (inst
.instruction
& LOAD_BIT
)
6961 /* encode_arm_addr_mode_3 will diagnose overlap between the base
6962 register and the first register written; we have to diagnose
6963 overlap between the base and the second register written here. */
6965 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
6966 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
6967 as_warn (_("base register written back, and overlaps "
6968 "second destination register"));
6970 /* For an index-register load, the index register must not overlap the
6971 destination (even if not write-back). */
6972 else if (inst
.operands
[2].immisreg
6973 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
6974 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
6975 as_warn (_("index register overlaps destination register"));
6978 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6979 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
6985 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
6986 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
6987 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
6988 || inst
.operands
[1].negative
6989 /* This can arise if the programmer has written
6991 or if they have mistakenly used a register name as the last
6994 It is very difficult to distinguish between these two cases
6995 because "rX" might actually be a label. ie the register
6996 name has been occluded by a symbol of the same name. So we
6997 just generate a general 'bad addressing mode' type error
6998 message and leave it up to the programmer to discover the
6999 true cause and fix their mistake. */
7000 || (inst
.operands
[1].reg
== REG_PC
),
7003 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7004 || inst
.reloc
.exp
.X_add_number
!= 0,
7005 _("offset must be zero in ARM encoding"));
7007 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7008 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7009 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7015 constraint (inst
.operands
[0].reg
% 2 != 0,
7016 _("even register required"));
7017 constraint (inst
.operands
[1].present
7018 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7019 _("can only load two consecutive registers"));
7020 /* If op 1 were present and equal to PC, this function wouldn't
7021 have been called in the first place. */
7022 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7024 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7025 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7031 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7032 if (!inst
.operands
[1].isreg
)
7033 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7035 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7041 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7043 if (inst
.operands
[1].preind
)
7045 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7046 || inst
.reloc
.exp
.X_add_number
!= 0,
7047 _("this instruction requires a post-indexed address"));
7049 inst
.operands
[1].preind
= 0;
7050 inst
.operands
[1].postind
= 1;
7051 inst
.operands
[1].writeback
= 1;
7053 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7054 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7057 /* Halfword and signed-byte load/store operations. */
7062 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7063 if (!inst
.operands
[1].isreg
)
7064 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7066 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7072 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7074 if (inst
.operands
[1].preind
)
7076 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7077 || inst
.reloc
.exp
.X_add_number
!= 0,
7078 _("this instruction requires a post-indexed address"));
7080 inst
.operands
[1].preind
= 0;
7081 inst
.operands
[1].postind
= 1;
7082 inst
.operands
[1].writeback
= 1;
7084 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7085 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7088 /* Co-processor register load/store.
7089 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7093 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7094 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7095 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7101 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7102 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7103 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7104 && !(inst
.instruction
& 0x00400000))
7105 as_tsktsk (_("Rd and Rm should be different in mla"));
7107 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7108 inst
.instruction
|= inst
.operands
[1].reg
;
7109 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7110 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7116 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7117 encode_arm_shifter_operand (1);
7120 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7127 top
= (inst
.instruction
& 0x00400000) != 0;
7128 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7129 _(":lower16: not allowed this instruction"));
7130 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7131 _(":upper16: not allowed instruction"));
7132 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7133 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7135 imm
= inst
.reloc
.exp
.X_add_number
;
7136 /* The value is in two pieces: 0:11, 16:19. */
7137 inst
.instruction
|= (imm
& 0x00000fff);
7138 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7142 static void do_vfp_nsyn_opcode (const char *);
7145 do_vfp_nsyn_mrs (void)
7147 if (inst
.operands
[0].isvec
)
7149 if (inst
.operands
[1].reg
!= 1)
7150 first_error (_("operand 1 must be FPSCR"));
7151 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7152 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7153 do_vfp_nsyn_opcode ("fmstat");
7155 else if (inst
.operands
[1].isvec
)
7156 do_vfp_nsyn_opcode ("fmrx");
7164 do_vfp_nsyn_msr (void)
7166 if (inst
.operands
[0].isvec
)
7167 do_vfp_nsyn_opcode ("fmxr");
7177 if (do_vfp_nsyn_mrs () == SUCCESS
)
7180 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7181 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7183 _("'CPSR' or 'SPSR' expected"));
7184 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7185 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7188 /* Two possible forms:
7189 "{C|S}PSR_<field>, Rm",
7190 "{C|S}PSR_f, #expression". */
7195 if (do_vfp_nsyn_msr () == SUCCESS
)
7198 inst
.instruction
|= inst
.operands
[0].imm
;
7199 if (inst
.operands
[1].isreg
)
7200 inst
.instruction
|= inst
.operands
[1].reg
;
7203 inst
.instruction
|= INST_IMMEDIATE
;
7204 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7205 inst
.reloc
.pc_rel
= 0;
7212 if (!inst
.operands
[2].present
)
7213 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7214 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7215 inst
.instruction
|= inst
.operands
[1].reg
;
7216 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7218 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7219 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7220 as_tsktsk (_("Rd and Rm should be different in mul"));
7223 /* Long Multiply Parser
7224 UMULL RdLo, RdHi, Rm, Rs
7225 SMULL RdLo, RdHi, Rm, Rs
7226 UMLAL RdLo, RdHi, Rm, Rs
7227 SMLAL RdLo, RdHi, Rm, Rs. */
7232 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7233 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7234 inst
.instruction
|= inst
.operands
[2].reg
;
7235 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7237 /* rdhi and rdlo must be different. */
7238 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7239 as_tsktsk (_("rdhi and rdlo must be different"));
7241 /* rdhi, rdlo and rm must all be different before armv6. */
7242 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7243 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7244 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7245 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7251 if (inst
.operands
[0].present
)
7253 /* Architectural NOP hints are CPSR sets with no bits selected. */
7254 inst
.instruction
&= 0xf0000000;
7255 inst
.instruction
|= 0x0320f000 + inst
.operands
[0].imm
;
7259 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7260 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7261 Condition defaults to COND_ALWAYS.
7262 Error if Rd, Rn or Rm are R15. */
7267 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7268 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7269 inst
.instruction
|= inst
.operands
[2].reg
;
7270 if (inst
.operands
[3].present
)
7271 encode_arm_shift (3);
7274 /* ARM V6 PKHTB (Argument Parse). */
7279 if (!inst
.operands
[3].present
)
7281 /* If the shift specifier is omitted, turn the instruction
7282 into pkhbt rd, rm, rn. */
7283 inst
.instruction
&= 0xfff00010;
7284 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7285 inst
.instruction
|= inst
.operands
[1].reg
;
7286 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7290 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7291 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7292 inst
.instruction
|= inst
.operands
[2].reg
;
7293 encode_arm_shift (3);
7297 /* ARMv5TE: Preload-Cache
7301 Syntactically, like LDR with B=1, W=0, L=1. */
7306 constraint (!inst
.operands
[0].isreg
,
7307 _("'[' expected after PLD mnemonic"));
7308 constraint (inst
.operands
[0].postind
,
7309 _("post-indexed expression used in preload instruction"));
7310 constraint (inst
.operands
[0].writeback
,
7311 _("writeback used in preload instruction"));
7312 constraint (!inst
.operands
[0].preind
,
7313 _("unindexed addressing used in preload instruction"));
7314 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7317 /* ARMv7: PLI <addr_mode> */
7321 constraint (!inst
.operands
[0].isreg
,
7322 _("'[' expected after PLI mnemonic"));
7323 constraint (inst
.operands
[0].postind
,
7324 _("post-indexed expression used in preload instruction"));
7325 constraint (inst
.operands
[0].writeback
,
7326 _("writeback used in preload instruction"));
7327 constraint (!inst
.operands
[0].preind
,
7328 _("unindexed addressing used in preload instruction"));
7329 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7330 inst
.instruction
&= ~PRE_INDEX
;
7336 inst
.operands
[1] = inst
.operands
[0];
7337 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7338 inst
.operands
[0].isreg
= 1;
7339 inst
.operands
[0].writeback
= 1;
7340 inst
.operands
[0].reg
= REG_SP
;
7344 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7345 word at the specified address and the following word
7347 Unconditionally executed.
7348 Error if Rn is R15. */
7353 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7354 if (inst
.operands
[0].writeback
)
7355 inst
.instruction
|= WRITE_BACK
;
7358 /* ARM V6 ssat (argument parse). */
7363 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7364 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7365 inst
.instruction
|= inst
.operands
[2].reg
;
7367 if (inst
.operands
[3].present
)
7368 encode_arm_shift (3);
7371 /* ARM V6 usat (argument parse). */
7376 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7377 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7378 inst
.instruction
|= inst
.operands
[2].reg
;
7380 if (inst
.operands
[3].present
)
7381 encode_arm_shift (3);
7384 /* ARM V6 ssat16 (argument parse). */
7389 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7390 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7391 inst
.instruction
|= inst
.operands
[2].reg
;
7397 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7398 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7399 inst
.instruction
|= inst
.operands
[2].reg
;
7402 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7403 preserving the other bits.
7405 setend <endian_specifier>, where <endian_specifier> is either
7411 if (inst
.operands
[0].imm
)
7412 inst
.instruction
|= 0x200;
7418 unsigned int Rm
= (inst
.operands
[1].present
7419 ? inst
.operands
[1].reg
7420 : inst
.operands
[0].reg
);
7422 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7423 inst
.instruction
|= Rm
;
7424 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7426 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7427 inst
.instruction
|= SHIFT_BY_REG
;
7430 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7436 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7437 inst
.reloc
.pc_rel
= 0;
7443 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7444 inst
.reloc
.pc_rel
= 0;
7447 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7448 SMLAxy{cond} Rd,Rm,Rs,Rn
7449 SMLAWy{cond} Rd,Rm,Rs,Rn
7450 Error if any register is R15. */
7455 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7456 inst
.instruction
|= inst
.operands
[1].reg
;
7457 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7458 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7461 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7462 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7463 Error if any register is R15.
7464 Warning if Rdlo == Rdhi. */
7469 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7470 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7471 inst
.instruction
|= inst
.operands
[2].reg
;
7472 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7474 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7475 as_tsktsk (_("rdhi and rdlo must be different"));
7478 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7479 SMULxy{cond} Rd,Rm,Rs
7480 Error if any register is R15. */
7485 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7486 inst
.instruction
|= inst
.operands
[1].reg
;
7487 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7490 /* ARM V6 srs (argument parse). The variable fields in the encoding are
7491 the same for both ARM and Thumb-2. */
7498 if (inst
.operands
[0].present
)
7500 reg
= inst
.operands
[0].reg
;
7501 constraint (reg
!= 13, _("SRS base register must be r13"));
7506 inst
.instruction
|= reg
<< 16;
7507 inst
.instruction
|= inst
.operands
[1].imm
;
7508 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
7509 inst
.instruction
|= WRITE_BACK
;
7512 /* ARM V6 strex (argument parse). */
7517 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7518 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7519 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7520 || inst
.operands
[2].negative
7521 /* See comment in do_ldrex(). */
7522 || (inst
.operands
[2].reg
== REG_PC
),
7525 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7526 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
7528 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7529 || inst
.reloc
.exp
.X_add_number
!= 0,
7530 _("offset must be zero in ARM encoding"));
7532 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7533 inst
.instruction
|= inst
.operands
[1].reg
;
7534 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7535 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7541 constraint (inst
.operands
[1].reg
% 2 != 0,
7542 _("even register required"));
7543 constraint (inst
.operands
[2].present
7544 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
7545 _("can only store two consecutive registers"));
7546 /* If op 2 were present and equal to PC, this function wouldn't
7547 have been called in the first place. */
7548 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
7550 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7551 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
7552 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
7555 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7556 inst
.instruction
|= inst
.operands
[1].reg
;
7557 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7560 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7561 extends it to 32-bits, and adds the result to a value in another
7562 register. You can specify a rotation by 0, 8, 16, or 24 bits
7563 before extracting the 16-bit value.
7564 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7565 Condition defaults to COND_ALWAYS.
7566 Error if any register uses R15. */
7571 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7572 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7573 inst
.instruction
|= inst
.operands
[2].reg
;
7574 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
7579 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
7580 Condition defaults to COND_ALWAYS.
7581 Error if any register uses R15. */
7586 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7587 inst
.instruction
|= inst
.operands
[1].reg
;
7588 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
7591 /* VFP instructions. In a logical order: SP variant first, monad
7592 before dyad, arithmetic then move then load/store. */
7595 do_vfp_sp_monadic (void)
7597 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7598 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7602 do_vfp_sp_dyadic (void)
7604 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7605 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7606 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7610 do_vfp_sp_compare_z (void)
7612 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7616 do_vfp_dp_sp_cvt (void)
7618 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7619 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7623 do_vfp_sp_dp_cvt (void)
7625 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7626 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7630 do_vfp_reg_from_sp (void)
7632 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7633 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7637 do_vfp_reg2_from_sp2 (void)
7639 constraint (inst
.operands
[2].imm
!= 2,
7640 _("only two consecutive VFP SP registers allowed here"));
7641 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7642 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7643 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7647 do_vfp_sp_from_reg (void)
7649 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
7650 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7654 do_vfp_sp2_from_reg2 (void)
7656 constraint (inst
.operands
[0].imm
!= 2,
7657 _("only two consecutive VFP SP registers allowed here"));
7658 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
7659 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7660 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7664 do_vfp_sp_ldst (void)
7666 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7667 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7671 do_vfp_dp_ldst (void)
7673 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7674 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7679 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
7681 if (inst
.operands
[0].writeback
)
7682 inst
.instruction
|= WRITE_BACK
;
7684 constraint (ldstm_type
!= VFP_LDSTMIA
,
7685 _("this addressing mode requires base-register writeback"));
7686 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7687 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
7688 inst
.instruction
|= inst
.operands
[1].imm
;
7692 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
7696 if (inst
.operands
[0].writeback
)
7697 inst
.instruction
|= WRITE_BACK
;
7699 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
7700 _("this addressing mode requires base-register writeback"));
7702 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7703 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7705 count
= inst
.operands
[1].imm
<< 1;
7706 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
7709 inst
.instruction
|= count
;
7713 do_vfp_sp_ldstmia (void)
7715 vfp_sp_ldstm (VFP_LDSTMIA
);
7719 do_vfp_sp_ldstmdb (void)
7721 vfp_sp_ldstm (VFP_LDSTMDB
);
7725 do_vfp_dp_ldstmia (void)
7727 vfp_dp_ldstm (VFP_LDSTMIA
);
7731 do_vfp_dp_ldstmdb (void)
7733 vfp_dp_ldstm (VFP_LDSTMDB
);
7737 do_vfp_xp_ldstmia (void)
7739 vfp_dp_ldstm (VFP_LDSTMIAX
);
7743 do_vfp_xp_ldstmdb (void)
7745 vfp_dp_ldstm (VFP_LDSTMDBX
);
7749 do_vfp_dp_rd_rm (void)
7751 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7752 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7756 do_vfp_dp_rn_rd (void)
7758 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
7759 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7763 do_vfp_dp_rd_rn (void)
7765 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7766 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7770 do_vfp_dp_rd_rn_rm (void)
7772 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7773 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7774 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
7780 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7784 do_vfp_dp_rm_rd_rn (void)
7786 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
7787 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7788 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
7791 /* VFPv3 instructions. */
7793 do_vfp_sp_const (void)
7795 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7796 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
7797 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
7801 do_vfp_dp_const (void)
7803 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7804 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
7805 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
7809 vfp_conv (int srcsize
)
7811 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
7812 inst
.instruction
|= (immbits
& 1) << 5;
7813 inst
.instruction
|= (immbits
>> 1);
7817 do_vfp_sp_conv_16 (void)
7819 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7824 do_vfp_dp_conv_16 (void)
7826 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7831 do_vfp_sp_conv_32 (void)
7833 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7838 do_vfp_dp_conv_32 (void)
7840 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7844 /* FPA instructions. Also in a logical order. */
7849 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7850 inst
.instruction
|= inst
.operands
[1].reg
;
7854 do_fpa_ldmstm (void)
7856 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7857 switch (inst
.operands
[1].imm
)
7859 case 1: inst
.instruction
|= CP_T_X
; break;
7860 case 2: inst
.instruction
|= CP_T_Y
; break;
7861 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
7866 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
7868 /* The instruction specified "ea" or "fd", so we can only accept
7869 [Rn]{!}. The instruction does not really support stacking or
7870 unstacking, so we have to emulate these by setting appropriate
7871 bits and offsets. */
7872 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7873 || inst
.reloc
.exp
.X_add_number
!= 0,
7874 _("this instruction does not support indexing"));
7876 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
7877 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
7879 if (!(inst
.instruction
& INDEX_UP
))
7880 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
7882 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
7884 inst
.operands
[2].preind
= 0;
7885 inst
.operands
[2].postind
= 1;
7889 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7892 /* iWMMXt instructions: strictly in alphabetical order. */
7895 do_iwmmxt_tandorc (void)
7897 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
7901 do_iwmmxt_textrc (void)
7903 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7904 inst
.instruction
|= inst
.operands
[1].imm
;
7908 do_iwmmxt_textrm (void)
7910 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7911 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7912 inst
.instruction
|= inst
.operands
[2].imm
;
7916 do_iwmmxt_tinsr (void)
7918 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7919 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7920 inst
.instruction
|= inst
.operands
[2].imm
;
7924 do_iwmmxt_tmia (void)
7926 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
7927 inst
.instruction
|= inst
.operands
[1].reg
;
7928 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7932 do_iwmmxt_waligni (void)
7934 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7935 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7936 inst
.instruction
|= inst
.operands
[2].reg
;
7937 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
7941 do_iwmmxt_wmerge (void)
7943 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7944 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7945 inst
.instruction
|= inst
.operands
[2].reg
;
7946 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
7950 do_iwmmxt_wmov (void)
7952 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
7953 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7954 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7955 inst
.instruction
|= inst
.operands
[1].reg
;
7959 do_iwmmxt_wldstbh (void)
7962 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7964 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
7966 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
7967 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
7971 do_iwmmxt_wldstw (void)
7973 /* RIWR_RIWC clears .isreg for a control register. */
7974 if (!inst
.operands
[0].isreg
)
7976 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7977 inst
.instruction
|= 0xf0000000;
7980 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7981 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7985 do_iwmmxt_wldstd (void)
7987 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7988 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
7989 && inst
.operands
[1].immisreg
)
7991 inst
.instruction
&= ~0x1a000ff;
7992 inst
.instruction
|= (0xf << 28);
7993 if (inst
.operands
[1].preind
)
7994 inst
.instruction
|= PRE_INDEX
;
7995 if (!inst
.operands
[1].negative
)
7996 inst
.instruction
|= INDEX_UP
;
7997 if (inst
.operands
[1].writeback
)
7998 inst
.instruction
|= WRITE_BACK
;
7999 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8000 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8001 inst
.instruction
|= inst
.operands
[1].imm
;
8004 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8008 do_iwmmxt_wshufh (void)
8010 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8011 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8012 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8013 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8017 do_iwmmxt_wzero (void)
8019 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8020 inst
.instruction
|= inst
.operands
[0].reg
;
8021 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8022 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8026 do_iwmmxt_wrwrwr_or_imm5 (void)
8028 if (inst
.operands
[2].isreg
)
8031 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8032 _("immediate operand requires iWMMXt2"));
8034 if (inst
.operands
[2].imm
== 0)
8036 switch ((inst
.instruction
>> 20) & 0xf)
8042 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8043 inst
.operands
[2].imm
= 16;
8044 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8050 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8051 inst
.operands
[2].imm
= 32;
8052 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8059 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8061 wrn
= (inst
.instruction
>> 16) & 0xf;
8062 inst
.instruction
&= 0xff0fff0f;
8063 inst
.instruction
|= wrn
;
8064 /* Bail out here; the instruction is now assembled. */
8069 /* Map 32 -> 0, etc. */
8070 inst
.operands
[2].imm
&= 0x1f;
8071 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8075 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8076 operations first, then control, shift, and load/store. */
8078 /* Insns like "foo X,Y,Z". */
8081 do_mav_triple (void)
8083 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8084 inst
.instruction
|= inst
.operands
[1].reg
;
8085 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8088 /* Insns like "foo W,X,Y,Z".
8089 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8094 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8095 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8096 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8097 inst
.instruction
|= inst
.operands
[3].reg
;
8100 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8104 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8107 /* Maverick shift immediate instructions.
8108 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8109 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8114 int imm
= inst
.operands
[2].imm
;
8116 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8117 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8119 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8120 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8121 Bit 4 should be 0. */
8122 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8124 inst
.instruction
|= imm
;
8127 /* XScale instructions. Also sorted arithmetic before move. */
8129 /* Xscale multiply-accumulate (argument parse)
8132 MIAxycc acc0,Rm,Rs. */
8137 inst
.instruction
|= inst
.operands
[1].reg
;
8138 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8141 /* Xscale move-accumulator-register (argument parse)
8143 MARcc acc0,RdLo,RdHi. */
8148 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8149 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8152 /* Xscale move-register-accumulator (argument parse)
8154 MRAcc RdLo,RdHi,acc0. */
8159 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8160 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8161 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8164 /* Encoding functions relevant only to Thumb. */
8166 /* inst.operands[i] is a shifted-register operand; encode
8167 it into inst.instruction in the format used by Thumb32. */
8170 encode_thumb32_shifted_operand (int i
)
8172 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8173 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8175 constraint (inst
.operands
[i
].immisreg
,
8176 _("shift by register not allowed in thumb mode"));
8177 inst
.instruction
|= inst
.operands
[i
].reg
;
8178 if (shift
== SHIFT_RRX
)
8179 inst
.instruction
|= SHIFT_ROR
<< 4;
8182 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8183 _("expression too complex"));
8185 constraint (value
> 32
8186 || (value
== 32 && (shift
== SHIFT_LSL
8187 || shift
== SHIFT_ROR
)),
8188 _("shift expression is too large"));
8192 else if (value
== 32)
8195 inst
.instruction
|= shift
<< 4;
8196 inst
.instruction
|= (value
& 0x1c) << 10;
8197 inst
.instruction
|= (value
& 0x03) << 6;
8202 /* inst.operands[i] was set up by parse_address. Encode it into a
8203 Thumb32 format load or store instruction. Reject forms that cannot
8204 be used with such instructions. If is_t is true, reject forms that
8205 cannot be used with a T instruction; if is_d is true, reject forms
8206 that cannot be used with a D instruction. */
8209 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8211 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8213 constraint (!inst
.operands
[i
].isreg
,
8214 _("Instruction does not support =N addresses"));
8216 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8217 if (inst
.operands
[i
].immisreg
)
8219 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
8220 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8221 constraint (inst
.operands
[i
].negative
,
8222 _("Thumb does not support negative register indexing"));
8223 constraint (inst
.operands
[i
].postind
,
8224 _("Thumb does not support register post-indexing"));
8225 constraint (inst
.operands
[i
].writeback
,
8226 _("Thumb does not support register indexing with writeback"));
8227 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8228 _("Thumb supports only LSL in shifted register indexing"));
8230 inst
.instruction
|= inst
.operands
[i
].imm
;
8231 if (inst
.operands
[i
].shifted
)
8233 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8234 _("expression too complex"));
8235 constraint (inst
.reloc
.exp
.X_add_number
< 0
8236 || inst
.reloc
.exp
.X_add_number
> 3,
8237 _("shift out of range"));
8238 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8240 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8242 else if (inst
.operands
[i
].preind
)
8244 constraint (is_pc
&& inst
.operands
[i
].writeback
,
8245 _("cannot use writeback with PC-relative addressing"));
8246 constraint (is_t
&& inst
.operands
[i
].writeback
,
8247 _("cannot use writeback with this instruction"));
8251 inst
.instruction
|= 0x01000000;
8252 if (inst
.operands
[i
].writeback
)
8253 inst
.instruction
|= 0x00200000;
8257 inst
.instruction
|= 0x00000c00;
8258 if (inst
.operands
[i
].writeback
)
8259 inst
.instruction
|= 0x00000100;
8261 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8263 else if (inst
.operands
[i
].postind
)
8265 assert (inst
.operands
[i
].writeback
);
8266 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8267 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8270 inst
.instruction
|= 0x00200000;
8272 inst
.instruction
|= 0x00000900;
8273 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8275 else /* unindexed - only for coprocessor */
8276 inst
.error
= _("instruction does not accept unindexed addressing");
8279 /* Table of Thumb instructions which exist in both 16- and 32-bit
8280 encodings (the latter only in post-V6T2 cores). The index is the
8281 value used in the insns table below. When there is more than one
8282 possible 16-bit encoding for the instruction, this table always
8284 Also contains several pseudo-instructions used during relaxation. */
8285 #define T16_32_TAB \
8286 X(adc, 4140, eb400000), \
8287 X(adcs, 4140, eb500000), \
8288 X(add, 1c00, eb000000), \
8289 X(adds, 1c00, eb100000), \
8290 X(addi, 0000, f1000000), \
8291 X(addis, 0000, f1100000), \
8292 X(add_pc,000f, f20f0000), \
8293 X(add_sp,000d, f10d0000), \
8294 X(adr, 000f, f20f0000), \
8295 X(and, 4000, ea000000), \
8296 X(ands, 4000, ea100000), \
8297 X(asr, 1000, fa40f000), \
8298 X(asrs, 1000, fa50f000), \
8299 X(b, e000, f000b000), \
8300 X(bcond, d000, f0008000), \
8301 X(bic, 4380, ea200000), \
8302 X(bics, 4380, ea300000), \
8303 X(cmn, 42c0, eb100f00), \
8304 X(cmp, 2800, ebb00f00), \
8305 X(cpsie, b660, f3af8400), \
8306 X(cpsid, b670, f3af8600), \
8307 X(cpy, 4600, ea4f0000), \
8308 X(dec_sp,80dd, f1ad0d00), \
8309 X(eor, 4040, ea800000), \
8310 X(eors, 4040, ea900000), \
8311 X(inc_sp,00dd, f10d0d00), \
8312 X(ldmia, c800, e8900000), \
8313 X(ldr, 6800, f8500000), \
8314 X(ldrb, 7800, f8100000), \
8315 X(ldrh, 8800, f8300000), \
8316 X(ldrsb, 5600, f9100000), \
8317 X(ldrsh, 5e00, f9300000), \
8318 X(ldr_pc,4800, f85f0000), \
8319 X(ldr_pc2,4800, f85f0000), \
8320 X(ldr_sp,9800, f85d0000), \
8321 X(lsl, 0000, fa00f000), \
8322 X(lsls, 0000, fa10f000), \
8323 X(lsr, 0800, fa20f000), \
8324 X(lsrs, 0800, fa30f000), \
8325 X(mov, 2000, ea4f0000), \
8326 X(movs, 2000, ea5f0000), \
8327 X(mul, 4340, fb00f000), \
8328 X(muls, 4340, ffffffff), /* no 32b muls */ \
8329 X(mvn, 43c0, ea6f0000), \
8330 X(mvns, 43c0, ea7f0000), \
8331 X(neg, 4240, f1c00000), /* rsb #0 */ \
8332 X(negs, 4240, f1d00000), /* rsbs #0 */ \
8333 X(orr, 4300, ea400000), \
8334 X(orrs, 4300, ea500000), \
8335 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8336 X(push, b400, e92d0000), /* stmdb sp!,... */ \
8337 X(rev, ba00, fa90f080), \
8338 X(rev16, ba40, fa90f090), \
8339 X(revsh, bac0, fa90f0b0), \
8340 X(ror, 41c0, fa60f000), \
8341 X(rors, 41c0, fa70f000), \
8342 X(sbc, 4180, eb600000), \
8343 X(sbcs, 4180, eb700000), \
8344 X(stmia, c000, e8800000), \
8345 X(str, 6000, f8400000), \
8346 X(strb, 7000, f8000000), \
8347 X(strh, 8000, f8200000), \
8348 X(str_sp,9000, f84d0000), \
8349 X(sub, 1e00, eba00000), \
8350 X(subs, 1e00, ebb00000), \
8351 X(subi, 8000, f1a00000), \
8352 X(subis, 8000, f1b00000), \
8353 X(sxtb, b240, fa4ff080), \
8354 X(sxth, b200, fa0ff080), \
8355 X(tst, 4200, ea100f00), \
8356 X(uxtb, b2c0, fa5ff080), \
8357 X(uxth, b280, fa1ff080), \
8358 X(nop, bf00, f3af8000), \
8359 X(yield, bf10, f3af8001), \
8360 X(wfe, bf20, f3af8002), \
8361 X(wfi, bf30, f3af8003), \
8362 X(sev, bf40, f3af9004), /* typo, 8004? */
8364 /* To catch errors in encoding functions, the codes are all offset by
8365 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8366 as 16-bit instructions. */
8367 #define X(a,b,c) T_MNEM_##a
8368 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8371 #define X(a,b,c) 0x##b
8372 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8373 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8376 #define X(a,b,c) 0x##c
8377 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8378 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8379 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8383 /* Thumb instruction encoders, in alphabetical order. */
8387 do_t_add_sub_w (void)
8391 Rd
= inst
.operands
[0].reg
;
8392 Rn
= inst
.operands
[1].reg
;
8394 constraint (Rd
== 15, _("PC not allowed as destination"));
8395 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8396 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8399 /* Parse an add or subtract instruction. We get here with inst.instruction
8400 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8407 Rd
= inst
.operands
[0].reg
;
8408 Rs
= (inst
.operands
[1].present
8409 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8410 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8418 flags
= (inst
.instruction
== T_MNEM_adds
8419 || inst
.instruction
== T_MNEM_subs
);
8421 narrow
= (current_it_mask
== 0);
8423 narrow
= (current_it_mask
!= 0);
8424 if (!inst
.operands
[2].isreg
)
8428 add
= (inst
.instruction
== T_MNEM_add
8429 || inst
.instruction
== T_MNEM_adds
);
8431 if (inst
.size_req
!= 4)
8433 /* Attempt to use a narrow opcode, with relaxation if
8435 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8436 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8437 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8438 opcode
= T_MNEM_add_sp
;
8439 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8440 opcode
= T_MNEM_add_pc
;
8441 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8444 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8446 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8450 inst
.instruction
= THUMB_OP16(opcode
);
8451 inst
.instruction
|= (Rd
<< 4) | Rs
;
8452 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8453 if (inst
.size_req
!= 2)
8454 inst
.relax
= opcode
;
8457 constraint (inst
.size_req
== 2, BAD_HIREG
);
8459 if (inst
.size_req
== 4
8460 || (inst
.size_req
!= 2 && !opcode
))
8464 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
8465 _("only SUBS PC, LR, #const allowed"));
8466 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8467 _("expression too complex"));
8468 constraint (inst
.reloc
.exp
.X_add_number
< 0
8469 || inst
.reloc
.exp
.X_add_number
> 0xff,
8470 _("immediate value out of range"));
8471 inst
.instruction
= T2_SUBS_PC_LR
8472 | inst
.reloc
.exp
.X_add_number
;
8473 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8476 else if (Rs
== REG_PC
)
8478 /* Always use addw/subw. */
8479 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
8480 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8484 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8485 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
8488 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8490 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
8492 inst
.instruction
|= Rd
<< 8;
8493 inst
.instruction
|= Rs
<< 16;
8498 Rn
= inst
.operands
[2].reg
;
8499 /* See if we can do this with a 16-bit instruction. */
8500 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
8502 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8507 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
8508 || inst
.instruction
== T_MNEM_add
)
8511 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8515 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
8517 /* Thumb-1 cores (except v6-M) require at least one high
8518 register in a narrow non flag setting add. */
8519 if (Rd
> 7 || Rn
> 7
8520 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
8521 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
8528 inst
.instruction
= T_OPCODE_ADD_HI
;
8529 inst
.instruction
|= (Rd
& 8) << 4;
8530 inst
.instruction
|= (Rd
& 7);
8531 inst
.instruction
|= Rn
<< 3;
8536 /* If we get here, it can't be done in 16 bits. */
8537 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
8538 _("shift must be constant"));
8539 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8540 inst
.instruction
|= Rd
<< 8;
8541 inst
.instruction
|= Rs
<< 16;
8542 encode_thumb32_shifted_operand (2);
8547 constraint (inst
.instruction
== T_MNEM_adds
8548 || inst
.instruction
== T_MNEM_subs
,
8551 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
8553 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
8554 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
8557 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8559 inst
.instruction
|= (Rd
<< 4) | Rs
;
8560 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8564 Rn
= inst
.operands
[2].reg
;
8565 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
8567 /* We now have Rd, Rs, and Rn set to registers. */
8568 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8570 /* Can't do this for SUB. */
8571 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
8572 inst
.instruction
= T_OPCODE_ADD_HI
;
8573 inst
.instruction
|= (Rd
& 8) << 4;
8574 inst
.instruction
|= (Rd
& 7);
8576 inst
.instruction
|= Rn
<< 3;
8578 inst
.instruction
|= Rs
<< 3;
8580 constraint (1, _("dest must overlap one source register"));
8584 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8585 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
8586 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8594 if (unified_syntax
&& inst
.size_req
== 0 && inst
.operands
[0].reg
<= 7)
8596 /* Defer to section relaxation. */
8597 inst
.relax
= inst
.instruction
;
8598 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8599 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8601 else if (unified_syntax
&& inst
.size_req
!= 2)
8603 /* Generate a 32-bit opcode. */
8604 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8605 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8606 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
8607 inst
.reloc
.pc_rel
= 1;
8611 /* Generate a 16-bit opcode. */
8612 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8613 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8614 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
8615 inst
.reloc
.pc_rel
= 1;
8617 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8621 /* Arithmetic instructions for which there is just one 16-bit
8622 instruction encoding, and it allows only two low registers.
8623 For maximal compatibility with ARM syntax, we allow three register
8624 operands even when Thumb-32 instructions are not available, as long
8625 as the first two are identical. For instance, both "sbc r0,r1" and
8626 "sbc r0,r0,r1" are allowed. */
8632 Rd
= inst
.operands
[0].reg
;
8633 Rs
= (inst
.operands
[1].present
8634 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8635 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8636 Rn
= inst
.operands
[2].reg
;
8640 if (!inst
.operands
[2].isreg
)
8642 /* For an immediate, we always generate a 32-bit opcode;
8643 section relaxation will shrink it later if possible. */
8644 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8645 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8646 inst
.instruction
|= Rd
<< 8;
8647 inst
.instruction
|= Rs
<< 16;
8648 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8654 /* See if we can do this with a 16-bit instruction. */
8655 if (THUMB_SETS_FLAGS (inst
.instruction
))
8656 narrow
= current_it_mask
== 0;
8658 narrow
= current_it_mask
!= 0;
8660 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8662 if (inst
.operands
[2].shifted
)
8664 if (inst
.size_req
== 4)
8670 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8671 inst
.instruction
|= Rd
;
8672 inst
.instruction
|= Rn
<< 3;
8676 /* If we get here, it can't be done in 16 bits. */
8677 constraint (inst
.operands
[2].shifted
8678 && inst
.operands
[2].immisreg
,
8679 _("shift must be constant"));
8680 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8681 inst
.instruction
|= Rd
<< 8;
8682 inst
.instruction
|= Rs
<< 16;
8683 encode_thumb32_shifted_operand (2);
8688 /* On its face this is a lie - the instruction does set the
8689 flags. However, the only supported mnemonic in this mode
8691 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8693 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8694 _("unshifted register required"));
8695 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8696 constraint (Rd
!= Rs
,
8697 _("dest and source1 must be the same register"));
8699 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8700 inst
.instruction
|= Rd
;
8701 inst
.instruction
|= Rn
<< 3;
8705 /* Similarly, but for instructions where the arithmetic operation is
8706 commutative, so we can allow either of them to be different from
8707 the destination operand in a 16-bit instruction. For instance, all
8708 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
8715 Rd
= inst
.operands
[0].reg
;
8716 Rs
= (inst
.operands
[1].present
8717 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8718 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8719 Rn
= inst
.operands
[2].reg
;
8723 if (!inst
.operands
[2].isreg
)
8725 /* For an immediate, we always generate a 32-bit opcode;
8726 section relaxation will shrink it later if possible. */
8727 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8728 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8729 inst
.instruction
|= Rd
<< 8;
8730 inst
.instruction
|= Rs
<< 16;
8731 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8737 /* See if we can do this with a 16-bit instruction. */
8738 if (THUMB_SETS_FLAGS (inst
.instruction
))
8739 narrow
= current_it_mask
== 0;
8741 narrow
= current_it_mask
!= 0;
8743 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8745 if (inst
.operands
[2].shifted
)
8747 if (inst
.size_req
== 4)
8754 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8755 inst
.instruction
|= Rd
;
8756 inst
.instruction
|= Rn
<< 3;
8761 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8762 inst
.instruction
|= Rd
;
8763 inst
.instruction
|= Rs
<< 3;
8768 /* If we get here, it can't be done in 16 bits. */
8769 constraint (inst
.operands
[2].shifted
8770 && inst
.operands
[2].immisreg
,
8771 _("shift must be constant"));
8772 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8773 inst
.instruction
|= Rd
<< 8;
8774 inst
.instruction
|= Rs
<< 16;
8775 encode_thumb32_shifted_operand (2);
8780 /* On its face this is a lie - the instruction does set the
8781 flags. However, the only supported mnemonic in this mode
8783 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8785 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8786 _("unshifted register required"));
8787 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8789 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8790 inst
.instruction
|= Rd
;
8793 inst
.instruction
|= Rn
<< 3;
8795 inst
.instruction
|= Rs
<< 3;
8797 constraint (1, _("dest must overlap one source register"));
8804 if (inst
.operands
[0].present
)
8806 constraint ((inst
.instruction
& 0xf0) != 0x40
8807 && inst
.operands
[0].imm
!= 0xf,
8808 _("bad barrier type"));
8809 inst
.instruction
|= inst
.operands
[0].imm
;
8812 inst
.instruction
|= 0xf;
8818 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8819 constraint (msb
> 32, _("bit-field extends past end of register"));
8820 /* The instruction encoding stores the LSB and MSB,
8821 not the LSB and width. */
8822 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8823 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
8824 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
8825 inst
.instruction
|= msb
- 1;
8833 /* #0 in second position is alternative syntax for bfc, which is
8834 the same instruction but with REG_PC in the Rm field. */
8835 if (!inst
.operands
[1].isreg
)
8836 inst
.operands
[1].reg
= REG_PC
;
8838 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8839 constraint (msb
> 32, _("bit-field extends past end of register"));
8840 /* The instruction encoding stores the LSB and MSB,
8841 not the LSB and width. */
8842 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8843 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8844 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8845 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8846 inst
.instruction
|= msb
- 1;
8852 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8853 _("bit-field extends past end of register"));
8854 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8855 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8856 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8857 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8858 inst
.instruction
|= inst
.operands
[3].imm
- 1;
8861 /* ARM V5 Thumb BLX (argument parse)
8862 BLX <target_addr> which is BLX(1)
8863 BLX <Rm> which is BLX(2)
8864 Unfortunately, there are two different opcodes for this mnemonic.
8865 So, the insns[].value is not used, and the code here zaps values
8866 into inst.instruction.
8868 ??? How to take advantage of the additional two bits of displacement
8869 available in Thumb32 mode? Need new relocation? */
8874 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8875 if (inst
.operands
[0].isreg
)
8876 /* We have a register, so this is BLX(2). */
8877 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8880 /* No register. This must be BLX(1). */
8881 inst
.instruction
= 0xf000e800;
8883 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8884 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8887 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
8888 inst
.reloc
.pc_rel
= 1;
8898 if (current_it_mask
)
8900 /* Conditional branches inside IT blocks are encoded as unconditional
8903 /* A branch must be the last instruction in an IT block. */
8904 constraint (current_it_mask
!= 0x10, BAD_BRANCH
);
8909 if (cond
!= COND_ALWAYS
)
8910 opcode
= T_MNEM_bcond
;
8912 opcode
= inst
.instruction
;
8914 if (unified_syntax
&& inst
.size_req
== 4)
8916 inst
.instruction
= THUMB_OP32(opcode
);
8917 if (cond
== COND_ALWAYS
)
8918 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
8921 assert (cond
!= 0xF);
8922 inst
.instruction
|= cond
<< 22;
8923 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
8928 inst
.instruction
= THUMB_OP16(opcode
);
8929 if (cond
== COND_ALWAYS
)
8930 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
8933 inst
.instruction
|= cond
<< 8;
8934 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
8936 /* Allow section relaxation. */
8937 if (unified_syntax
&& inst
.size_req
!= 2)
8938 inst
.relax
= opcode
;
8941 inst
.reloc
.pc_rel
= 1;
8947 constraint (inst
.cond
!= COND_ALWAYS
,
8948 _("instruction is always unconditional"));
8949 if (inst
.operands
[0].present
)
8951 constraint (inst
.operands
[0].imm
> 255,
8952 _("immediate value out of range"));
8953 inst
.instruction
|= inst
.operands
[0].imm
;
8958 do_t_branch23 (void)
8960 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8961 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8962 inst
.reloc
.pc_rel
= 1;
8964 /* If the destination of the branch is a defined symbol which does not have
8965 the THUMB_FUNC attribute, then we must be calling a function which has
8966 the (interfacearm) attribute. We look for the Thumb entry point to that
8967 function and change the branch to refer to that function instead. */
8968 if ( inst
.reloc
.exp
.X_op
== O_symbol
8969 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8970 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8971 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8972 inst
.reloc
.exp
.X_add_symbol
=
8973 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
8979 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8980 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8981 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
8982 should cause the alignment to be checked once it is known. This is
8983 because BX PC only works if the instruction is word aligned. */
8989 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8990 if (inst
.operands
[0].reg
== REG_PC
)
8991 as_tsktsk (_("use of r15 in bxj is not really useful"));
8993 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8999 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9000 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9001 inst
.instruction
|= inst
.operands
[1].reg
;
9007 constraint (current_it_mask
, BAD_NOT_IT
);
9008 inst
.instruction
|= inst
.operands
[0].imm
;
9014 constraint (current_it_mask
, BAD_NOT_IT
);
9016 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9017 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9019 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9020 inst
.instruction
= 0xf3af8000;
9021 inst
.instruction
|= imod
<< 9;
9022 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9023 if (inst
.operands
[1].present
)
9024 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9028 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9029 && (inst
.operands
[0].imm
& 4),
9030 _("selected processor does not support 'A' form "
9031 "of this instruction"));
9032 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9033 _("Thumb does not support the 2-argument "
9034 "form of this instruction"));
9035 inst
.instruction
|= inst
.operands
[0].imm
;
9039 /* THUMB CPY instruction (argument parse). */
9044 if (inst
.size_req
== 4)
9046 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9047 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9048 inst
.instruction
|= inst
.operands
[1].reg
;
9052 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9053 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9054 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9061 constraint (current_it_mask
, BAD_NOT_IT
);
9062 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9063 inst
.instruction
|= inst
.operands
[0].reg
;
9064 inst
.reloc
.pc_rel
= 1;
9065 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9071 inst
.instruction
|= inst
.operands
[0].imm
;
9077 if (!inst
.operands
[1].present
)
9078 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9079 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9080 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9081 inst
.instruction
|= inst
.operands
[2].reg
;
9087 if (unified_syntax
&& inst
.size_req
== 4)
9088 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9090 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9096 unsigned int cond
= inst
.operands
[0].imm
;
9098 constraint (current_it_mask
, BAD_NOT_IT
);
9099 current_it_mask
= (inst
.instruction
& 0xf) | 0x10;
9102 /* If the condition is a negative condition, invert the mask. */
9103 if ((cond
& 0x1) == 0x0)
9105 unsigned int mask
= inst
.instruction
& 0x000f;
9107 if ((mask
& 0x7) == 0)
9108 /* no conversion needed */;
9109 else if ((mask
& 0x3) == 0)
9111 else if ((mask
& 0x1) == 0)
9116 inst
.instruction
&= 0xfff0;
9117 inst
.instruction
|= mask
;
9120 inst
.instruction
|= cond
<< 4;
9123 /* Helper function used for both push/pop and ldm/stm. */
9125 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9129 load
= (inst
.instruction
& (1 << 20)) != 0;
9131 if (mask
& (1 << 13))
9132 inst
.error
= _("SP not allowed in register list");
9135 if (mask
& (1 << 14)
9136 && mask
& (1 << 15))
9137 inst
.error
= _("LR and PC should not both be in register list");
9139 if ((mask
& (1 << base
)) != 0
9141 as_warn (_("base register should not be in register list "
9142 "when written back"));
9146 if (mask
& (1 << 15))
9147 inst
.error
= _("PC not allowed in register list");
9149 if (mask
& (1 << base
))
9150 as_warn (_("value stored for r%d is UNPREDICTABLE"), base
);
9153 if ((mask
& (mask
- 1)) == 0)
9155 /* Single register transfers implemented as str/ldr. */
9158 if (inst
.instruction
& (1 << 23))
9159 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9161 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9165 if (inst
.instruction
& (1 << 23))
9166 inst
.instruction
= 0x00800000; /* ia -> [base] */
9168 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9171 inst
.instruction
|= 0xf8400000;
9173 inst
.instruction
|= 0x00100000;
9175 mask
= ffs (mask
) - 1;
9179 inst
.instruction
|= WRITE_BACK
;
9181 inst
.instruction
|= mask
;
9182 inst
.instruction
|= base
<< 16;
9188 /* This really doesn't seem worth it. */
9189 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9190 _("expression too complex"));
9191 constraint (inst
.operands
[1].writeback
,
9192 _("Thumb load/store multiple does not support {reglist}^"));
9200 /* See if we can use a 16-bit instruction. */
9201 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9202 && inst
.size_req
!= 4
9203 && !(inst
.operands
[1].imm
& ~0xff))
9205 mask
= 1 << inst
.operands
[0].reg
;
9207 if (inst
.operands
[0].reg
<= 7
9208 && (inst
.instruction
== T_MNEM_stmia
9209 ? inst
.operands
[0].writeback
9210 : (inst
.operands
[0].writeback
9211 == !(inst
.operands
[1].imm
& mask
))))
9213 if (inst
.instruction
== T_MNEM_stmia
9214 && (inst
.operands
[1].imm
& mask
)
9215 && (inst
.operands
[1].imm
& (mask
- 1)))
9216 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9217 inst
.operands
[0].reg
);
9219 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9220 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9221 inst
.instruction
|= inst
.operands
[1].imm
;
9224 else if (inst
.operands
[0] .reg
== REG_SP
9225 && inst
.operands
[0].writeback
)
9227 inst
.instruction
= THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9228 ? T_MNEM_push
: T_MNEM_pop
);
9229 inst
.instruction
|= inst
.operands
[1].imm
;
9236 if (inst
.instruction
< 0xffff)
9237 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9239 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
9240 inst
.operands
[0].writeback
);
9245 constraint (inst
.operands
[0].reg
> 7
9246 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9247 constraint (inst
.instruction
!= T_MNEM_ldmia
9248 && inst
.instruction
!= T_MNEM_stmia
,
9249 _("Thumb-2 instruction only valid in unified syntax"));
9250 if (inst
.instruction
== T_MNEM_stmia
)
9252 if (!inst
.operands
[0].writeback
)
9253 as_warn (_("this instruction will write back the base register"));
9254 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9255 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9256 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9257 inst
.operands
[0].reg
);
9261 if (!inst
.operands
[0].writeback
9262 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9263 as_warn (_("this instruction will write back the base register"));
9264 else if (inst
.operands
[0].writeback
9265 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9266 as_warn (_("this instruction will not write back the base register"));
9269 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9270 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9271 inst
.instruction
|= inst
.operands
[1].imm
;
9278 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9279 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9280 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9281 || inst
.operands
[1].negative
,
9284 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9285 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9286 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9292 if (!inst
.operands
[1].present
)
9294 constraint (inst
.operands
[0].reg
== REG_LR
,
9295 _("r14 not allowed as first register "
9296 "when second register is omitted"));
9297 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9299 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9302 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9303 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9304 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9310 unsigned long opcode
;
9313 opcode
= inst
.instruction
;
9316 if (!inst
.operands
[1].isreg
)
9318 if (opcode
<= 0xffff)
9319 inst
.instruction
= THUMB_OP32 (opcode
);
9320 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9323 if (inst
.operands
[1].isreg
9324 && !inst
.operands
[1].writeback
9325 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9326 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9328 && inst
.size_req
!= 4)
9330 /* Insn may have a 16-bit form. */
9331 Rn
= inst
.operands
[1].reg
;
9332 if (inst
.operands
[1].immisreg
)
9334 inst
.instruction
= THUMB_OP16 (opcode
);
9336 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9339 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9340 && opcode
!= T_MNEM_ldrsb
)
9341 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9342 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9349 if (inst
.reloc
.pc_rel
)
9350 opcode
= T_MNEM_ldr_pc2
;
9352 opcode
= T_MNEM_ldr_pc
;
9356 if (opcode
== T_MNEM_ldr
)
9357 opcode
= T_MNEM_ldr_sp
;
9359 opcode
= T_MNEM_str_sp
;
9361 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9365 inst
.instruction
= inst
.operands
[0].reg
;
9366 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9368 inst
.instruction
|= THUMB_OP16 (opcode
);
9369 if (inst
.size_req
== 2)
9370 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9372 inst
.relax
= opcode
;
9376 /* Definitely a 32-bit variant. */
9377 inst
.instruction
= THUMB_OP32 (opcode
);
9378 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9379 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9383 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9385 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9387 /* Only [Rn,Rm] is acceptable. */
9388 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9389 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9390 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9391 || inst
.operands
[1].negative
,
9392 _("Thumb does not support this addressing mode"));
9393 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9397 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9398 if (!inst
.operands
[1].isreg
)
9399 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9402 constraint (!inst
.operands
[1].preind
9403 || inst
.operands
[1].shifted
9404 || inst
.operands
[1].writeback
,
9405 _("Thumb does not support this addressing mode"));
9406 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9408 constraint (inst
.instruction
& 0x0600,
9409 _("byte or halfword not valid for base register"));
9410 constraint (inst
.operands
[1].reg
== REG_PC
9411 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9412 _("r15 based store not allowed"));
9413 constraint (inst
.operands
[1].immisreg
,
9414 _("invalid base register for register offset"));
9416 if (inst
.operands
[1].reg
== REG_PC
)
9417 inst
.instruction
= T_OPCODE_LDR_PC
;
9418 else if (inst
.instruction
& THUMB_LOAD_BIT
)
9419 inst
.instruction
= T_OPCODE_LDR_SP
;
9421 inst
.instruction
= T_OPCODE_STR_SP
;
9423 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9424 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9428 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
9429 if (!inst
.operands
[1].immisreg
)
9431 /* Immediate offset. */
9432 inst
.instruction
|= inst
.operands
[0].reg
;
9433 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9434 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9438 /* Register offset. */
9439 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
9440 constraint (inst
.operands
[1].negative
,
9441 _("Thumb does not support this addressing mode"));
9444 switch (inst
.instruction
)
9446 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
9447 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
9448 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
9449 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
9450 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
9451 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
9452 case 0x5600 /* ldrsb */:
9453 case 0x5e00 /* ldrsh */: break;
9457 inst
.instruction
|= inst
.operands
[0].reg
;
9458 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9459 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
9465 if (!inst
.operands
[1].present
)
9467 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9468 constraint (inst
.operands
[0].reg
== REG_LR
,
9469 _("r14 not allowed here"));
9471 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9472 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9473 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
9479 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9480 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
9486 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9487 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9488 inst
.instruction
|= inst
.operands
[2].reg
;
9489 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9495 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9496 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9497 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9498 inst
.instruction
|= inst
.operands
[3].reg
;
9506 int r0off
= (inst
.instruction
== T_MNEM_mov
9507 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
9508 unsigned long opcode
;
9510 bfd_boolean low_regs
;
9512 low_regs
= (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7);
9513 opcode
= inst
.instruction
;
9514 if (current_it_mask
)
9515 narrow
= opcode
!= T_MNEM_movs
;
9517 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
9518 if (inst
.size_req
== 4
9519 || inst
.operands
[1].shifted
)
9522 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
9523 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
9524 && !inst
.operands
[1].shifted
9525 && inst
.operands
[0].reg
== REG_PC
9526 && inst
.operands
[1].reg
== REG_LR
)
9528 inst
.instruction
= T2_SUBS_PC_LR
;
9532 if (!inst
.operands
[1].isreg
)
9534 /* Immediate operand. */
9535 if (current_it_mask
== 0 && opcode
== T_MNEM_mov
)
9537 if (low_regs
&& narrow
)
9539 inst
.instruction
= THUMB_OP16 (opcode
);
9540 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9541 if (inst
.size_req
== 2)
9542 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9544 inst
.relax
= opcode
;
9548 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9549 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9550 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9551 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9554 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
9555 && (inst
.instruction
== T_MNEM_mov
9556 || inst
.instruction
== T_MNEM_movs
))
9558 /* Register shifts are encoded as separate shift instructions. */
9559 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
9561 if (current_it_mask
)
9566 if (inst
.size_req
== 4)
9569 if (!low_regs
|| inst
.operands
[1].imm
> 7)
9572 if (inst
.operands
[0].reg
!= inst
.operands
[1].reg
)
9575 switch (inst
.operands
[1].shift_kind
)
9578 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
9581 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
9584 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
9587 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
9593 inst
.instruction
= opcode
;
9596 inst
.instruction
|= inst
.operands
[0].reg
;
9597 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
9602 inst
.instruction
|= CONDS_BIT
;
9604 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9605 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9606 inst
.instruction
|= inst
.operands
[1].imm
;
9611 /* Some mov with immediate shift have narrow variants.
9612 Register shifts are handled above. */
9613 if (low_regs
&& inst
.operands
[1].shifted
9614 && (inst
.instruction
== T_MNEM_mov
9615 || inst
.instruction
== T_MNEM_movs
))
9617 if (current_it_mask
)
9618 narrow
= (inst
.instruction
== T_MNEM_mov
);
9620 narrow
= (inst
.instruction
== T_MNEM_movs
);
9625 switch (inst
.operands
[1].shift_kind
)
9627 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
9628 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
9629 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
9630 default: narrow
= FALSE
; break;
9636 inst
.instruction
|= inst
.operands
[0].reg
;
9637 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9638 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
9642 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9643 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9644 encode_thumb32_shifted_operand (1);
9648 switch (inst
.instruction
)
9651 inst
.instruction
= T_OPCODE_MOV_HR
;
9652 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9653 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9654 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9658 /* We know we have low registers at this point.
9659 Generate ADD Rd, Rs, #0. */
9660 inst
.instruction
= T_OPCODE_ADD_I3
;
9661 inst
.instruction
|= inst
.operands
[0].reg
;
9662 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9668 inst
.instruction
= T_OPCODE_CMP_LR
;
9669 inst
.instruction
|= inst
.operands
[0].reg
;
9670 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9674 inst
.instruction
= T_OPCODE_CMP_HR
;
9675 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9676 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9677 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9684 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9685 if (inst
.operands
[1].isreg
)
9687 if (inst
.operands
[0].reg
< 8 && inst
.operands
[1].reg
< 8)
9689 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
9690 since a MOV instruction produces unpredictable results. */
9691 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9692 inst
.instruction
= T_OPCODE_ADD_I3
;
9694 inst
.instruction
= T_OPCODE_CMP_LR
;
9696 inst
.instruction
|= inst
.operands
[0].reg
;
9697 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9701 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9702 inst
.instruction
= T_OPCODE_MOV_HR
;
9704 inst
.instruction
= T_OPCODE_CMP_HR
;
9710 constraint (inst
.operands
[0].reg
> 7,
9711 _("only lo regs allowed with immediate"));
9712 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9713 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9723 top
= (inst
.instruction
& 0x00800000) != 0;
9724 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
9726 constraint (top
, _(":lower16: not allowed this instruction"));
9727 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
9729 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
9731 constraint (!top
, _(":upper16: not allowed this instruction"));
9732 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
9735 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9736 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9738 imm
= inst
.reloc
.exp
.X_add_number
;
9739 inst
.instruction
|= (imm
& 0xf000) << 4;
9740 inst
.instruction
|= (imm
& 0x0800) << 15;
9741 inst
.instruction
|= (imm
& 0x0700) << 4;
9742 inst
.instruction
|= (imm
& 0x00ff);
9751 int r0off
= (inst
.instruction
== T_MNEM_mvn
9752 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
9755 if (inst
.size_req
== 4
9756 || inst
.instruction
> 0xffff
9757 || inst
.operands
[1].shifted
9758 || inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9760 else if (inst
.instruction
== T_MNEM_cmn
)
9762 else if (THUMB_SETS_FLAGS (inst
.instruction
))
9763 narrow
= (current_it_mask
== 0);
9765 narrow
= (current_it_mask
!= 0);
9767 if (!inst
.operands
[1].isreg
)
9769 /* For an immediate, we always generate a 32-bit opcode;
9770 section relaxation will shrink it later if possible. */
9771 if (inst
.instruction
< 0xffff)
9772 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9773 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9774 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9775 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9779 /* See if we can do this with a 16-bit instruction. */
9782 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9783 inst
.instruction
|= inst
.operands
[0].reg
;
9784 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9788 constraint (inst
.operands
[1].shifted
9789 && inst
.operands
[1].immisreg
,
9790 _("shift must be constant"));
9791 if (inst
.instruction
< 0xffff)
9792 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9793 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9794 encode_thumb32_shifted_operand (1);
9800 constraint (inst
.instruction
> 0xffff
9801 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
9802 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
9803 _("unshifted register required"));
9804 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9807 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9808 inst
.instruction
|= inst
.operands
[0].reg
;
9809 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9818 if (do_vfp_nsyn_mrs () == SUCCESS
)
9821 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
9824 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
9825 _("selected processor does not support "
9826 "requested special purpose register"));
9830 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9831 _("selected processor does not support "
9832 "requested special purpose register"));
9833 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9834 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
9835 _("'CPSR' or 'SPSR' expected"));
9838 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9839 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9840 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
9848 if (do_vfp_nsyn_msr () == SUCCESS
)
9851 constraint (!inst
.operands
[1].isreg
,
9852 _("Thumb encoding does not support an immediate here"));
9853 flags
= inst
.operands
[0].imm
;
9856 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9857 _("selected processor does not support "
9858 "requested special purpose register"));
9862 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
9863 _("selected processor does not support "
9864 "requested special purpose register"));
9867 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9868 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
9869 inst
.instruction
|= (flags
& 0xff);
9870 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9876 if (!inst
.operands
[2].present
)
9877 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9879 /* There is no 32-bit MULS and no 16-bit MUL. */
9880 if (unified_syntax
&& inst
.instruction
== T_MNEM_mul
)
9882 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9883 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9884 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9885 inst
.instruction
|= inst
.operands
[2].reg
<< 0;
9889 constraint (!unified_syntax
9890 && inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
9891 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9894 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9895 inst
.instruction
|= inst
.operands
[0].reg
;
9897 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9898 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9899 else if (inst
.operands
[0].reg
== inst
.operands
[2].reg
)
9900 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9902 constraint (1, _("dest must overlap one source register"));
9909 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9910 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9911 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9912 inst
.instruction
|= inst
.operands
[3].reg
;
9914 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9915 as_tsktsk (_("rdhi and rdlo must be different"));
9923 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
9925 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9926 inst
.instruction
|= inst
.operands
[0].imm
;
9930 /* PR9722: Check for Thumb2 availability before
9931 generating a thumb2 nop instruction. */
9932 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
9934 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9935 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
9938 inst
.instruction
= 0x46c0;
9943 constraint (inst
.operands
[0].present
,
9944 _("Thumb does not support NOP with hints"));
9945 inst
.instruction
= 0x46c0;
9956 if (THUMB_SETS_FLAGS (inst
.instruction
))
9957 narrow
= (current_it_mask
== 0);
9959 narrow
= (current_it_mask
!= 0);
9960 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9962 if (inst
.size_req
== 4)
9967 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9968 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9969 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9973 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9974 inst
.instruction
|= inst
.operands
[0].reg
;
9975 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9980 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9982 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9984 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9985 inst
.instruction
|= inst
.operands
[0].reg
;
9986 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9993 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9994 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9995 inst
.instruction
|= inst
.operands
[2].reg
;
9996 if (inst
.operands
[3].present
)
9998 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
9999 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10000 _("expression too complex"));
10001 inst
.instruction
|= (val
& 0x1c) << 10;
10002 inst
.instruction
|= (val
& 0x03) << 6;
10009 if (!inst
.operands
[3].present
)
10010 inst
.instruction
&= ~0x00000020;
10017 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10021 do_t_push_pop (void)
10025 constraint (inst
.operands
[0].writeback
,
10026 _("push/pop do not support {reglist}^"));
10027 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10028 _("expression too complex"));
10030 mask
= inst
.operands
[0].imm
;
10031 if ((mask
& ~0xff) == 0)
10032 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
10033 else if ((inst
.instruction
== T_MNEM_push
10034 && (mask
& ~0xff) == 1 << REG_LR
)
10035 || (inst
.instruction
== T_MNEM_pop
10036 && (mask
& ~0xff) == 1 << REG_PC
))
10038 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10039 inst
.instruction
|= THUMB_PP_PC_LR
;
10040 inst
.instruction
|= mask
& 0xff;
10042 else if (unified_syntax
)
10044 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10045 encode_thumb2_ldmstm (13, mask
, TRUE
);
10049 inst
.error
= _("invalid register list to push/pop instruction");
10057 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10058 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10059 inst
.instruction
|= inst
.operands
[1].reg
;
10065 if (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
10066 && inst
.size_req
!= 4)
10068 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10069 inst
.instruction
|= inst
.operands
[0].reg
;
10070 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10072 else if (unified_syntax
)
10074 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10075 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10076 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10077 inst
.instruction
|= inst
.operands
[1].reg
;
10080 inst
.error
= BAD_HIREG
;
10088 Rd
= inst
.operands
[0].reg
;
10089 Rs
= (inst
.operands
[1].present
10090 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10091 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10093 inst
.instruction
|= Rd
<< 8;
10094 inst
.instruction
|= Rs
<< 16;
10095 if (!inst
.operands
[2].isreg
)
10097 bfd_boolean narrow
;
10099 if ((inst
.instruction
& 0x00100000) != 0)
10100 narrow
= (current_it_mask
== 0);
10102 narrow
= (current_it_mask
!= 0);
10104 if (Rd
> 7 || Rs
> 7)
10107 if (inst
.size_req
== 4 || !unified_syntax
)
10110 if (inst
.reloc
.exp
.X_op
!= O_constant
10111 || inst
.reloc
.exp
.X_add_number
!= 0)
10114 /* Turn rsb #0 into 16-bit neg. We should probably do this via
10115 relaxation, but it doesn't seem worth the hassle. */
10118 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10119 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
10120 inst
.instruction
|= Rs
<< 3;
10121 inst
.instruction
|= Rd
;
10125 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10126 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10130 encode_thumb32_shifted_operand (2);
10136 constraint (current_it_mask
, BAD_NOT_IT
);
10137 if (inst
.operands
[0].imm
)
10138 inst
.instruction
|= 0x8;
10144 if (!inst
.operands
[1].present
)
10145 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
10147 if (unified_syntax
)
10149 bfd_boolean narrow
;
10152 switch (inst
.instruction
)
10155 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
10157 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
10159 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
10161 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
10165 if (THUMB_SETS_FLAGS (inst
.instruction
))
10166 narrow
= (current_it_mask
== 0);
10168 narrow
= (current_it_mask
!= 0);
10169 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10171 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
10173 if (inst
.operands
[2].isreg
10174 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
10175 || inst
.operands
[2].reg
> 7))
10177 if (inst
.size_req
== 4)
10182 if (inst
.operands
[2].isreg
)
10184 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10185 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10186 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10187 inst
.instruction
|= inst
.operands
[2].reg
;
10191 inst
.operands
[1].shifted
= 1;
10192 inst
.operands
[1].shift_kind
= shift_kind
;
10193 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
10194 ? T_MNEM_movs
: T_MNEM_mov
);
10195 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10196 encode_thumb32_shifted_operand (1);
10197 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
10198 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10203 if (inst
.operands
[2].isreg
)
10205 switch (shift_kind
)
10207 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10208 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10209 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10210 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10214 inst
.instruction
|= inst
.operands
[0].reg
;
10215 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10219 switch (shift_kind
)
10221 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10222 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10223 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10226 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10227 inst
.instruction
|= inst
.operands
[0].reg
;
10228 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10234 constraint (inst
.operands
[0].reg
> 7
10235 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
10236 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10238 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
10240 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
10241 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
10242 _("source1 and dest must be same register"));
10244 switch (inst
.instruction
)
10246 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10247 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10248 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10249 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10253 inst
.instruction
|= inst
.operands
[0].reg
;
10254 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10258 switch (inst
.instruction
)
10260 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10261 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10262 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10263 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
10266 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10267 inst
.instruction
|= inst
.operands
[0].reg
;
10268 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10276 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10277 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10278 inst
.instruction
|= inst
.operands
[2].reg
;
10284 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10285 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10286 _("expression too complex"));
10287 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10288 inst
.instruction
|= (value
& 0xf000) >> 12;
10289 inst
.instruction
|= (value
& 0x0ff0);
10290 inst
.instruction
|= (value
& 0x000f) << 16;
10296 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10297 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10298 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10300 if (inst
.operands
[3].present
)
10302 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10303 _("expression too complex"));
10305 if (inst
.reloc
.exp
.X_add_number
!= 0)
10307 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10308 inst
.instruction
|= 0x00200000; /* sh bit */
10309 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10310 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10312 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10319 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10320 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10321 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10327 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10328 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10329 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10330 || inst
.operands
[2].negative
,
10333 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10334 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10335 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10336 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10342 if (!inst
.operands
[2].present
)
10343 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
10345 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10346 || inst
.operands
[0].reg
== inst
.operands
[2].reg
10347 || inst
.operands
[0].reg
== inst
.operands
[3].reg
10348 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
10351 inst
.instruction
|= inst
.operands
[0].reg
;
10352 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10353 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10354 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10360 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10361 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10362 inst
.instruction
|= inst
.operands
[2].reg
;
10363 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
10369 if (inst
.instruction
<= 0xffff && inst
.size_req
!= 4
10370 && inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
10371 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
10373 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10374 inst
.instruction
|= inst
.operands
[0].reg
;
10375 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10377 else if (unified_syntax
)
10379 if (inst
.instruction
<= 0xffff)
10380 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10381 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10382 inst
.instruction
|= inst
.operands
[1].reg
;
10383 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
10387 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
10388 _("Thumb encoding does not support rotation"));
10389 constraint (1, BAD_HIREG
);
10396 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
10404 half
= (inst
.instruction
& 0x10) != 0;
10405 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
10406 constraint (inst
.operands
[0].immisreg
,
10407 _("instruction requires register index"));
10408 constraint (inst
.operands
[0].imm
== 15,
10409 _("PC is not a valid index register"));
10410 constraint (!half
&& inst
.operands
[0].shifted
,
10411 _("instruction does not allow shifted index"));
10412 inst
.instruction
|= (inst
.operands
[0].reg
<< 16) | inst
.operands
[0].imm
;
10418 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10419 inst
.instruction
|= inst
.operands
[1].imm
;
10420 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10422 if (inst
.operands
[3].present
)
10424 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10425 _("expression too complex"));
10426 if (inst
.reloc
.exp
.X_add_number
!= 0)
10428 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10429 inst
.instruction
|= 0x00200000; /* sh bit */
10431 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10432 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10434 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10441 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10442 inst
.instruction
|= inst
.operands
[1].imm
;
10443 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10446 /* Neon instruction encoder helpers. */
10448 /* Encodings for the different types for various Neon opcodes. */
10450 /* An "invalid" code for the following tables. */
10453 struct neon_tab_entry
10456 unsigned float_or_poly
;
10457 unsigned scalar_or_imm
;
10460 /* Map overloaded Neon opcodes to their respective encodings. */
10461 #define NEON_ENC_TAB \
10462 X(vabd, 0x0000700, 0x1200d00, N_INV), \
10463 X(vmax, 0x0000600, 0x0000f00, N_INV), \
10464 X(vmin, 0x0000610, 0x0200f00, N_INV), \
10465 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
10466 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
10467 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
10468 X(vadd, 0x0000800, 0x0000d00, N_INV), \
10469 X(vsub, 0x1000800, 0x0200d00, N_INV), \
10470 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
10471 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
10472 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
10473 /* Register variants of the following two instructions are encoded as
10474 vcge / vcgt with the operands reversed. */ \
10475 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
10476 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
10477 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
10478 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
10479 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
10480 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
10481 X(vmlal, 0x0800800, N_INV, 0x0800240), \
10482 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
10483 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
10484 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
10485 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
10486 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
10487 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
10488 X(vshl, 0x0000400, N_INV, 0x0800510), \
10489 X(vqshl, 0x0000410, N_INV, 0x0800710), \
10490 X(vand, 0x0000110, N_INV, 0x0800030), \
10491 X(vbic, 0x0100110, N_INV, 0x0800030), \
10492 X(veor, 0x1000110, N_INV, N_INV), \
10493 X(vorn, 0x0300110, N_INV, 0x0800010), \
10494 X(vorr, 0x0200110, N_INV, 0x0800010), \
10495 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
10496 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
10497 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
10498 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
10499 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
10500 X(vst1, 0x0000000, 0x0800000, N_INV), \
10501 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
10502 X(vst2, 0x0000100, 0x0800100, N_INV), \
10503 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
10504 X(vst3, 0x0000200, 0x0800200, N_INV), \
10505 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
10506 X(vst4, 0x0000300, 0x0800300, N_INV), \
10507 X(vmovn, 0x1b20200, N_INV, N_INV), \
10508 X(vtrn, 0x1b20080, N_INV, N_INV), \
10509 X(vqmovn, 0x1b20200, N_INV, N_INV), \
10510 X(vqmovun, 0x1b20240, N_INV, N_INV), \
10511 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
10512 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \
10513 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \
10514 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
10515 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
10516 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
10517 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
10521 #define X(OPC,I,F,S) N_MNEM_##OPC
10526 static const struct neon_tab_entry neon_enc_tab
[] =
10528 #define X(OPC,I,F,S) { (I), (F), (S) }
10533 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10534 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10535 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10536 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10537 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10538 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10539 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10540 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10541 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10542 #define NEON_ENC_SINGLE(X) \
10543 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
10544 #define NEON_ENC_DOUBLE(X) \
10545 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
10547 /* Define shapes for instruction operands. The following mnemonic characters
10548 are used in this table:
10550 F - VFP S<n> register
10551 D - Neon D<n> register
10552 Q - Neon Q<n> register
10556 L - D<n> register list
10558 This table is used to generate various data:
10559 - enumerations of the form NS_DDR to be used as arguments to
10561 - a table classifying shapes into single, double, quad, mixed.
10562 - a table used to drive neon_select_shape. */
10564 #define NEON_SHAPE_DEF \
10565 X(3, (D, D, D), DOUBLE), \
10566 X(3, (Q, Q, Q), QUAD), \
10567 X(3, (D, D, I), DOUBLE), \
10568 X(3, (Q, Q, I), QUAD), \
10569 X(3, (D, D, S), DOUBLE), \
10570 X(3, (Q, Q, S), QUAD), \
10571 X(2, (D, D), DOUBLE), \
10572 X(2, (Q, Q), QUAD), \
10573 X(2, (D, S), DOUBLE), \
10574 X(2, (Q, S), QUAD), \
10575 X(2, (D, R), DOUBLE), \
10576 X(2, (Q, R), QUAD), \
10577 X(2, (D, I), DOUBLE), \
10578 X(2, (Q, I), QUAD), \
10579 X(3, (D, L, D), DOUBLE), \
10580 X(2, (D, Q), MIXED), \
10581 X(2, (Q, D), MIXED), \
10582 X(3, (D, Q, I), MIXED), \
10583 X(3, (Q, D, I), MIXED), \
10584 X(3, (Q, D, D), MIXED), \
10585 X(3, (D, Q, Q), MIXED), \
10586 X(3, (Q, Q, D), MIXED), \
10587 X(3, (Q, D, S), MIXED), \
10588 X(3, (D, Q, S), MIXED), \
10589 X(4, (D, D, D, I), DOUBLE), \
10590 X(4, (Q, Q, Q, I), QUAD), \
10591 X(2, (F, F), SINGLE), \
10592 X(3, (F, F, F), SINGLE), \
10593 X(2, (F, I), SINGLE), \
10594 X(2, (F, D), MIXED), \
10595 X(2, (D, F), MIXED), \
10596 X(3, (F, F, I), MIXED), \
10597 X(4, (R, R, F, F), SINGLE), \
10598 X(4, (F, F, R, R), SINGLE), \
10599 X(3, (D, R, R), DOUBLE), \
10600 X(3, (R, R, D), DOUBLE), \
10601 X(2, (S, R), SINGLE), \
10602 X(2, (R, S), SINGLE), \
10603 X(2, (F, R), SINGLE), \
10604 X(2, (R, F), SINGLE)
10606 #define S2(A,B) NS_##A##B
10607 #define S3(A,B,C) NS_##A##B##C
10608 #define S4(A,B,C,D) NS_##A##B##C##D
10610 #define X(N, L, C) S##N L
10623 enum neon_shape_class
10631 #define X(N, L, C) SC_##C
10633 static enum neon_shape_class neon_shape_class
[] =
10651 /* Register widths of above. */
10652 static unsigned neon_shape_el_size
[] =
10663 struct neon_shape_info
10666 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
10669 #define S2(A,B) { SE_##A, SE_##B }
10670 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
10671 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
10673 #define X(N, L, C) { N, S##N L }
10675 static struct neon_shape_info neon_shape_tab
[] =
10685 /* Bit masks used in type checking given instructions.
10686 'N_EQK' means the type must be the same as (or based on in some way) the key
10687 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
10688 set, various other bits can be set as well in order to modify the meaning of
10689 the type constraint. */
10691 enum neon_type_mask
10714 N_KEY
= 0x1000000, /* key element (main type specifier). */
10715 N_EQK
= 0x2000000, /* given operand has the same type & size as the key. */
10716 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
10717 N_DBL
= 0x0000001, /* if N_EQK, this operand is twice the size. */
10718 N_HLF
= 0x0000002, /* if N_EQK, this operand is half the size. */
10719 N_SGN
= 0x0000004, /* if N_EQK, this operand is forced to be signed. */
10720 N_UNS
= 0x0000008, /* if N_EQK, this operand is forced to be unsigned. */
10721 N_INT
= 0x0000010, /* if N_EQK, this operand is forced to be integer. */
10722 N_FLT
= 0x0000020, /* if N_EQK, this operand is forced to be float. */
10723 N_SIZ
= 0x0000040, /* if N_EQK, this operand is forced to be size-only. */
10725 N_MAX_NONSPECIAL
= N_F64
10728 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
10730 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
10731 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
10732 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
10733 #define N_SUF_32 (N_SU_32 | N_F32)
10734 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
10735 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
10737 /* Pass this as the first type argument to neon_check_type to ignore types
10739 #define N_IGNORE_TYPE (N_KEY | N_EQK)
10741 /* Select a "shape" for the current instruction (describing register types or
10742 sizes) from a list of alternatives. Return NS_NULL if the current instruction
10743 doesn't fit. For non-polymorphic shapes, checking is usually done as a
10744 function of operand parsing, so this function doesn't need to be called.
10745 Shapes should be listed in order of decreasing length. */
10747 static enum neon_shape
10748 neon_select_shape (enum neon_shape shape
, ...)
10751 enum neon_shape first_shape
= shape
;
10753 /* Fix missing optional operands. FIXME: we don't know at this point how
10754 many arguments we should have, so this makes the assumption that we have
10755 > 1. This is true of all current Neon opcodes, I think, but may not be
10756 true in the future. */
10757 if (!inst
.operands
[1].present
)
10758 inst
.operands
[1] = inst
.operands
[0];
10760 va_start (ap
, shape
);
10762 for (; shape
!= NS_NULL
; shape
= va_arg (ap
, int))
10767 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
10769 if (!inst
.operands
[j
].present
)
10775 switch (neon_shape_tab
[shape
].el
[j
])
10778 if (!(inst
.operands
[j
].isreg
10779 && inst
.operands
[j
].isvec
10780 && inst
.operands
[j
].issingle
10781 && !inst
.operands
[j
].isquad
))
10786 if (!(inst
.operands
[j
].isreg
10787 && inst
.operands
[j
].isvec
10788 && !inst
.operands
[j
].isquad
10789 && !inst
.operands
[j
].issingle
))
10794 if (!(inst
.operands
[j
].isreg
10795 && !inst
.operands
[j
].isvec
))
10800 if (!(inst
.operands
[j
].isreg
10801 && inst
.operands
[j
].isvec
10802 && inst
.operands
[j
].isquad
10803 && !inst
.operands
[j
].issingle
))
10808 if (!(!inst
.operands
[j
].isreg
10809 && !inst
.operands
[j
].isscalar
))
10814 if (!(!inst
.operands
[j
].isreg
10815 && inst
.operands
[j
].isscalar
))
10829 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
10830 first_error (_("invalid instruction shape"));
10835 /* True if SHAPE is predominantly a quadword operation (most of the time, this
10836 means the Q bit should be set). */
10839 neon_quad (enum neon_shape shape
)
10841 return neon_shape_class
[shape
] == SC_QUAD
;
10845 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
10848 /* Allow modification to be made to types which are constrained to be
10849 based on the key element, based on bits set alongside N_EQK. */
10850 if ((typebits
& N_EQK
) != 0)
10852 if ((typebits
& N_HLF
) != 0)
10854 else if ((typebits
& N_DBL
) != 0)
10856 if ((typebits
& N_SGN
) != 0)
10857 *g_type
= NT_signed
;
10858 else if ((typebits
& N_UNS
) != 0)
10859 *g_type
= NT_unsigned
;
10860 else if ((typebits
& N_INT
) != 0)
10861 *g_type
= NT_integer
;
10862 else if ((typebits
& N_FLT
) != 0)
10863 *g_type
= NT_float
;
10864 else if ((typebits
& N_SIZ
) != 0)
10865 *g_type
= NT_untyped
;
10869 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
10870 operand type, i.e. the single type specified in a Neon instruction when it
10871 is the only one given. */
10873 static struct neon_type_el
10874 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
10876 struct neon_type_el dest
= *key
;
10878 assert ((thisarg
& N_EQK
) != 0);
10880 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
10885 /* Convert Neon type and size into compact bitmask representation. */
10887 static enum neon_type_mask
10888 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
10895 case 8: return N_8
;
10896 case 16: return N_16
;
10897 case 32: return N_32
;
10898 case 64: return N_64
;
10906 case 8: return N_I8
;
10907 case 16: return N_I16
;
10908 case 32: return N_I32
;
10909 case 64: return N_I64
;
10917 case 16: return N_F16
;
10918 case 32: return N_F32
;
10919 case 64: return N_F64
;
10927 case 8: return N_P8
;
10928 case 16: return N_P16
;
10936 case 8: return N_S8
;
10937 case 16: return N_S16
;
10938 case 32: return N_S32
;
10939 case 64: return N_S64
;
10947 case 8: return N_U8
;
10948 case 16: return N_U16
;
10949 case 32: return N_U32
;
10950 case 64: return N_U64
;
10961 /* Convert compact Neon bitmask type representation to a type and size. Only
10962 handles the case where a single bit is set in the mask. */
10965 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
10966 enum neon_type_mask mask
)
10968 if ((mask
& N_EQK
) != 0)
10971 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
10973 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
10975 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
10977 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
10982 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
10984 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
10985 *type
= NT_unsigned
;
10986 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
10987 *type
= NT_integer
;
10988 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
10989 *type
= NT_untyped
;
10990 else if ((mask
& (N_P8
| N_P16
)) != 0)
10992 else if ((mask
& (N_F32
| N_F64
)) != 0)
11000 /* Modify a bitmask of allowed types. This is only needed for type
11004 modify_types_allowed (unsigned allowed
, unsigned mods
)
11007 enum neon_el_type type
;
11013 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
11015 if (el_type_of_type_chk (&type
, &size
, allowed
& i
) == SUCCESS
)
11017 neon_modify_type_size (mods
, &type
, &size
);
11018 destmask
|= type_chk_of_el_type (type
, size
);
11025 /* Check type and return type classification.
11026 The manual states (paraphrase): If one datatype is given, it indicates the
11028 - the second operand, if there is one
11029 - the operand, if there is no second operand
11030 - the result, if there are no operands.
11031 This isn't quite good enough though, so we use a concept of a "key" datatype
11032 which is set on a per-instruction basis, which is the one which matters when
11033 only one data type is written.
11034 Note: this function has side-effects (e.g. filling in missing operands). All
11035 Neon instructions should call it before performing bit encoding. */
11037 static struct neon_type_el
11038 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
11041 unsigned i
, pass
, key_el
= 0;
11042 unsigned types
[NEON_MAX_TYPE_ELS
];
11043 enum neon_el_type k_type
= NT_invtype
;
11044 unsigned k_size
= -1u;
11045 struct neon_type_el badtype
= {NT_invtype
, -1};
11046 unsigned key_allowed
= 0;
11048 /* Optional registers in Neon instructions are always (not) in operand 1.
11049 Fill in the missing operand here, if it was omitted. */
11050 if (els
> 1 && !inst
.operands
[1].present
)
11051 inst
.operands
[1] = inst
.operands
[0];
11053 /* Suck up all the varargs. */
11055 for (i
= 0; i
< els
; i
++)
11057 unsigned thisarg
= va_arg (ap
, unsigned);
11058 if (thisarg
== N_IGNORE_TYPE
)
11063 types
[i
] = thisarg
;
11064 if ((thisarg
& N_KEY
) != 0)
11069 if (inst
.vectype
.elems
> 0)
11070 for (i
= 0; i
< els
; i
++)
11071 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
11073 first_error (_("types specified in both the mnemonic and operands"));
11077 /* Duplicate inst.vectype elements here as necessary.
11078 FIXME: No idea if this is exactly the same as the ARM assembler,
11079 particularly when an insn takes one register and one non-register
11081 if (inst
.vectype
.elems
== 1 && els
> 1)
11084 inst
.vectype
.elems
= els
;
11085 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
11086 for (j
= 0; j
< els
; j
++)
11088 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11091 else if (inst
.vectype
.elems
== 0 && els
> 0)
11094 /* No types were given after the mnemonic, so look for types specified
11095 after each operand. We allow some flexibility here; as long as the
11096 "key" operand has a type, we can infer the others. */
11097 for (j
= 0; j
< els
; j
++)
11098 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
11099 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
11101 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
11103 for (j
= 0; j
< els
; j
++)
11104 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
11105 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11110 first_error (_("operand types can't be inferred"));
11114 else if (inst
.vectype
.elems
!= els
)
11116 first_error (_("type specifier has the wrong number of parts"));
11120 for (pass
= 0; pass
< 2; pass
++)
11122 for (i
= 0; i
< els
; i
++)
11124 unsigned thisarg
= types
[i
];
11125 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
11126 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
11127 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
11128 unsigned g_size
= inst
.vectype
.el
[i
].size
;
11130 /* Decay more-specific signed & unsigned types to sign-insensitive
11131 integer types if sign-specific variants are unavailable. */
11132 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
11133 && (types_allowed
& N_SU_ALL
) == 0)
11134 g_type
= NT_integer
;
11136 /* If only untyped args are allowed, decay any more specific types to
11137 them. Some instructions only care about signs for some element
11138 sizes, so handle that properly. */
11139 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
11140 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
11141 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
11142 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
11143 g_type
= NT_untyped
;
11147 if ((thisarg
& N_KEY
) != 0)
11151 key_allowed
= thisarg
& ~N_KEY
;
11156 if ((thisarg
& N_VFP
) != 0)
11158 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
11159 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
11161 /* In VFP mode, operands must match register widths. If we
11162 have a key operand, use its width, else use the width of
11163 the current operand. */
11169 if (regwidth
!= match
)
11171 first_error (_("operand size must match register width"));
11176 if ((thisarg
& N_EQK
) == 0)
11178 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
11180 if ((given_type
& types_allowed
) == 0)
11182 first_error (_("bad type in Neon instruction"));
11188 enum neon_el_type mod_k_type
= k_type
;
11189 unsigned mod_k_size
= k_size
;
11190 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
11191 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
11193 first_error (_("inconsistent types in Neon instruction"));
11201 return inst
.vectype
.el
[key_el
];
11204 /* Neon-style VFP instruction forwarding. */
11206 /* Thumb VFP instructions have 0xE in the condition field. */
11209 do_vfp_cond_or_thumb (void)
11212 inst
.instruction
|= 0xe0000000;
11214 inst
.instruction
|= inst
.cond
<< 28;
11217 /* Look up and encode a simple mnemonic, for use as a helper function for the
11218 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
11219 etc. It is assumed that operand parsing has already been done, and that the
11220 operands are in the form expected by the given opcode (this isn't necessarily
11221 the same as the form in which they were parsed, hence some massaging must
11222 take place before this function is called).
11223 Checks current arch version against that in the looked-up opcode. */
11226 do_vfp_nsyn_opcode (const char *opname
)
11228 const struct asm_opcode
*opcode
;
11230 opcode
= hash_find (arm_ops_hsh
, opname
);
11235 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
11236 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
11241 inst
.instruction
= opcode
->tvalue
;
11242 opcode
->tencode ();
11246 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
11247 opcode
->aencode ();
11252 do_vfp_nsyn_add_sub (enum neon_shape rs
)
11254 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
11259 do_vfp_nsyn_opcode ("fadds");
11261 do_vfp_nsyn_opcode ("fsubs");
11266 do_vfp_nsyn_opcode ("faddd");
11268 do_vfp_nsyn_opcode ("fsubd");
11272 /* Check operand types to see if this is a VFP instruction, and if so call
11276 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
11278 enum neon_shape rs
;
11279 struct neon_type_el et
;
11284 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11285 et
= neon_check_type (2, rs
,
11286 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11290 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11291 et
= neon_check_type (3, rs
,
11292 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11299 if (et
.type
!= NT_invtype
)
11311 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
11313 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
11318 do_vfp_nsyn_opcode ("fmacs");
11320 do_vfp_nsyn_opcode ("fmscs");
11325 do_vfp_nsyn_opcode ("fmacd");
11327 do_vfp_nsyn_opcode ("fmscd");
11332 do_vfp_nsyn_mul (enum neon_shape rs
)
11335 do_vfp_nsyn_opcode ("fmuls");
11337 do_vfp_nsyn_opcode ("fmuld");
11341 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
11343 int is_neg
= (inst
.instruction
& 0x80) != 0;
11344 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
11349 do_vfp_nsyn_opcode ("fnegs");
11351 do_vfp_nsyn_opcode ("fabss");
11356 do_vfp_nsyn_opcode ("fnegd");
11358 do_vfp_nsyn_opcode ("fabsd");
11362 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
11363 insns belong to Neon, and are handled elsewhere. */
11366 do_vfp_nsyn_ldm_stm (int is_dbmode
)
11368 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
11372 do_vfp_nsyn_opcode ("fldmdbs");
11374 do_vfp_nsyn_opcode ("fldmias");
11379 do_vfp_nsyn_opcode ("fstmdbs");
11381 do_vfp_nsyn_opcode ("fstmias");
11386 do_vfp_nsyn_sqrt (void)
11388 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11389 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11392 do_vfp_nsyn_opcode ("fsqrts");
11394 do_vfp_nsyn_opcode ("fsqrtd");
11398 do_vfp_nsyn_div (void)
11400 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11401 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11402 N_F32
| N_F64
| N_KEY
| N_VFP
);
11405 do_vfp_nsyn_opcode ("fdivs");
11407 do_vfp_nsyn_opcode ("fdivd");
11411 do_vfp_nsyn_nmul (void)
11413 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11414 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11415 N_F32
| N_F64
| N_KEY
| N_VFP
);
11419 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11420 do_vfp_sp_dyadic ();
11424 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11425 do_vfp_dp_rd_rn_rm ();
11427 do_vfp_cond_or_thumb ();
11431 do_vfp_nsyn_cmp (void)
11433 if (inst
.operands
[1].isreg
)
11435 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11436 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11440 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11441 do_vfp_sp_monadic ();
11445 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11446 do_vfp_dp_rd_rm ();
11451 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
11452 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
11454 switch (inst
.instruction
& 0x0fffffff)
11457 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
11460 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
11468 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11469 do_vfp_sp_compare_z ();
11473 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11477 do_vfp_cond_or_thumb ();
11481 nsyn_insert_sp (void)
11483 inst
.operands
[1] = inst
.operands
[0];
11484 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
11485 inst
.operands
[0].reg
= 13;
11486 inst
.operands
[0].isreg
= 1;
11487 inst
.operands
[0].writeback
= 1;
11488 inst
.operands
[0].present
= 1;
11492 do_vfp_nsyn_push (void)
11495 if (inst
.operands
[1].issingle
)
11496 do_vfp_nsyn_opcode ("fstmdbs");
11498 do_vfp_nsyn_opcode ("fstmdbd");
11502 do_vfp_nsyn_pop (void)
11505 if (inst
.operands
[1].issingle
)
11506 do_vfp_nsyn_opcode ("fldmias");
11508 do_vfp_nsyn_opcode ("fldmiad");
11511 /* Fix up Neon data-processing instructions, ORing in the correct bits for
11512 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
11515 neon_dp_fixup (unsigned i
)
11519 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
11533 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
11537 neon_logbits (unsigned x
)
11539 return ffs (x
) - 4;
11542 #define LOW4(R) ((R) & 0xf)
11543 #define HI1(R) (((R) >> 4) & 1)
11545 /* Encode insns with bit pattern:
11547 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
11548 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
11550 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
11551 different meaning for some instruction. */
11554 neon_three_same (int isquad
, int ubit
, int size
)
11556 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11557 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11558 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
11559 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
11560 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
11561 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
11562 inst
.instruction
|= (isquad
!= 0) << 6;
11563 inst
.instruction
|= (ubit
!= 0) << 24;
11565 inst
.instruction
|= neon_logbits (size
) << 20;
11567 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11570 /* Encode instructions of the form:
11572 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
11573 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
11575 Don't write size if SIZE == -1. */
11578 neon_two_same (int qbit
, int ubit
, int size
)
11580 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11581 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11582 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11583 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11584 inst
.instruction
|= (qbit
!= 0) << 6;
11585 inst
.instruction
|= (ubit
!= 0) << 24;
11588 inst
.instruction
|= neon_logbits (size
) << 18;
11590 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11593 /* Neon instruction encoders, in approximate order of appearance. */
11596 do_neon_dyadic_i_su (void)
11598 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11599 struct neon_type_el et
= neon_check_type (3, rs
,
11600 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
11601 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11605 do_neon_dyadic_i64_su (void)
11607 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11608 struct neon_type_el et
= neon_check_type (3, rs
,
11609 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11610 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11614 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
11617 unsigned size
= et
.size
>> 3;
11618 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11619 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11620 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11621 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11622 inst
.instruction
|= (isquad
!= 0) << 6;
11623 inst
.instruction
|= immbits
<< 16;
11624 inst
.instruction
|= (size
>> 3) << 7;
11625 inst
.instruction
|= (size
& 0x7) << 19;
11627 inst
.instruction
|= (uval
!= 0) << 24;
11629 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11633 do_neon_shl_imm (void)
11635 if (!inst
.operands
[2].isreg
)
11637 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11638 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
11639 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11640 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
11644 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11645 struct neon_type_el et
= neon_check_type (3, rs
,
11646 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11649 /* VSHL/VQSHL 3-register variants have syntax such as:
11651 whereas other 3-register operations encoded by neon_three_same have
11654 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
11656 tmp
= inst
.operands
[2].reg
;
11657 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11658 inst
.operands
[1].reg
= tmp
;
11659 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11660 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11665 do_neon_qshl_imm (void)
11667 if (!inst
.operands
[2].isreg
)
11669 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11670 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
11672 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11673 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
11674 inst
.operands
[2].imm
);
11678 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11679 struct neon_type_el et
= neon_check_type (3, rs
,
11680 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11683 /* See note in do_neon_shl_imm. */
11684 tmp
= inst
.operands
[2].reg
;
11685 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11686 inst
.operands
[1].reg
= tmp
;
11687 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11688 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11693 do_neon_rshl (void)
11695 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11696 struct neon_type_el et
= neon_check_type (3, rs
,
11697 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11700 tmp
= inst
.operands
[2].reg
;
11701 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11702 inst
.operands
[1].reg
= tmp
;
11703 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11707 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
11709 /* Handle .I8 pseudo-instructions. */
11712 /* Unfortunately, this will make everything apart from zero out-of-range.
11713 FIXME is this the intended semantics? There doesn't seem much point in
11714 accepting .I8 if so. */
11715 immediate
|= immediate
<< 8;
11721 if (immediate
== (immediate
& 0x000000ff))
11723 *immbits
= immediate
;
11726 else if (immediate
== (immediate
& 0x0000ff00))
11728 *immbits
= immediate
>> 8;
11731 else if (immediate
== (immediate
& 0x00ff0000))
11733 *immbits
= immediate
>> 16;
11736 else if (immediate
== (immediate
& 0xff000000))
11738 *immbits
= immediate
>> 24;
11741 if ((immediate
& 0xffff) != (immediate
>> 16))
11742 goto bad_immediate
;
11743 immediate
&= 0xffff;
11746 if (immediate
== (immediate
& 0x000000ff))
11748 *immbits
= immediate
;
11751 else if (immediate
== (immediate
& 0x0000ff00))
11753 *immbits
= immediate
>> 8;
11758 first_error (_("immediate value out of range"));
11762 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
11766 neon_bits_same_in_bytes (unsigned imm
)
11768 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
11769 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
11770 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
11771 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
11774 /* For immediate of above form, return 0bABCD. */
11777 neon_squash_bits (unsigned imm
)
11779 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
11780 | ((imm
& 0x01000000) >> 21);
11783 /* Compress quarter-float representation to 0b...000 abcdefgh. */
11786 neon_qfloat_bits (unsigned imm
)
11788 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
11791 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
11792 the instruction. *OP is passed as the initial value of the op field, and
11793 may be set to a different value depending on the constant (i.e.
11794 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
11795 MVN). If the immediate looks like a repeated pattern then also
11796 try smaller element sizes. */
11799 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
11800 unsigned *immbits
, int *op
, int size
,
11801 enum neon_el_type type
)
11803 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
11805 if (type
== NT_float
&& !float_p
)
11808 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
11810 if (size
!= 32 || *op
== 1)
11812 *immbits
= neon_qfloat_bits (immlo
);
11818 if (neon_bits_same_in_bytes (immhi
)
11819 && neon_bits_same_in_bytes (immlo
))
11823 *immbits
= (neon_squash_bits (immhi
) << 4)
11824 | neon_squash_bits (immlo
);
11829 if (immhi
!= immlo
)
11835 if (immlo
== (immlo
& 0x000000ff))
11840 else if (immlo
== (immlo
& 0x0000ff00))
11842 *immbits
= immlo
>> 8;
11845 else if (immlo
== (immlo
& 0x00ff0000))
11847 *immbits
= immlo
>> 16;
11850 else if (immlo
== (immlo
& 0xff000000))
11852 *immbits
= immlo
>> 24;
11855 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
11857 *immbits
= (immlo
>> 8) & 0xff;
11860 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
11862 *immbits
= (immlo
>> 16) & 0xff;
11866 if ((immlo
& 0xffff) != (immlo
>> 16))
11873 if (immlo
== (immlo
& 0x000000ff))
11878 else if (immlo
== (immlo
& 0x0000ff00))
11880 *immbits
= immlo
>> 8;
11884 if ((immlo
& 0xff) != (immlo
>> 8))
11889 if (immlo
== (immlo
& 0x000000ff))
11891 /* Don't allow MVN with 8-bit immediate. */
11901 /* Write immediate bits [7:0] to the following locations:
11903 |28/24|23 19|18 16|15 4|3 0|
11904 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
11906 This function is used by VMOV/VMVN/VORR/VBIC. */
11909 neon_write_immbits (unsigned immbits
)
11911 inst
.instruction
|= immbits
& 0xf;
11912 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
11913 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
11916 /* Invert low-order SIZE bits of XHI:XLO. */
11919 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
11921 unsigned immlo
= xlo
? *xlo
: 0;
11922 unsigned immhi
= xhi
? *xhi
: 0;
11927 immlo
= (~immlo
) & 0xff;
11931 immlo
= (~immlo
) & 0xffff;
11935 immhi
= (~immhi
) & 0xffffffff;
11936 /* fall through. */
11939 immlo
= (~immlo
) & 0xffffffff;
11954 do_neon_logic (void)
11956 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
11958 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11959 neon_check_type (3, rs
, N_IGNORE_TYPE
);
11960 /* U bit and size field were set as part of the bitmask. */
11961 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11962 neon_three_same (neon_quad (rs
), 0, -1);
11966 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
11967 struct neon_type_el et
= neon_check_type (2, rs
,
11968 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
11969 enum neon_opc opcode
= inst
.instruction
& 0x0fffffff;
11973 if (et
.type
== NT_invtype
)
11976 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11978 immbits
= inst
.operands
[1].imm
;
11981 /* .i64 is a pseudo-op, so the immediate must be a repeating
11983 if (immbits
!= (inst
.operands
[1].regisimm
?
11984 inst
.operands
[1].reg
: 0))
11986 /* Set immbits to an invalid constant. */
11987 immbits
= 0xdeadbeef;
11994 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11998 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12002 /* Pseudo-instruction for VBIC. */
12003 neon_invert_size (&immbits
, 0, et
.size
);
12004 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12008 /* Pseudo-instruction for VORR. */
12009 neon_invert_size (&immbits
, 0, et
.size
);
12010 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12020 inst
.instruction
|= neon_quad (rs
) << 6;
12021 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12022 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12023 inst
.instruction
|= cmode
<< 8;
12024 neon_write_immbits (immbits
);
12026 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12031 do_neon_bitfield (void)
12033 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12034 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12035 neon_three_same (neon_quad (rs
), 0, -1);
12039 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
12042 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12043 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
12045 if (et
.type
== NT_float
)
12047 inst
.instruction
= NEON_ENC_FLOAT (inst
.instruction
);
12048 neon_three_same (neon_quad (rs
), 0, -1);
12052 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12053 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
12058 do_neon_dyadic_if_su (void)
12060 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12064 do_neon_dyadic_if_su_d (void)
12066 /* This version only allow D registers, but that constraint is enforced during
12067 operand parsing so we don't need to do anything extra here. */
12068 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12072 do_neon_dyadic_if_i_d (void)
12074 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12075 affected if we specify unsigned args. */
12076 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12079 enum vfp_or_neon_is_neon_bits
12082 NEON_CHECK_ARCH
= 2
12085 /* Call this function if an instruction which may have belonged to the VFP or
12086 Neon instruction sets, but turned out to be a Neon instruction (due to the
12087 operand types involved, etc.). We have to check and/or fix-up a couple of
12090 - Make sure the user hasn't attempted to make a Neon instruction
12092 - Alter the value in the condition code field if necessary.
12093 - Make sure that the arch supports Neon instructions.
12095 Which of these operations take place depends on bits from enum
12096 vfp_or_neon_is_neon_bits.
12098 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
12099 current instruction's condition is COND_ALWAYS, the condition field is
12100 changed to inst.uncond_value. This is necessary because instructions shared
12101 between VFP and Neon may be conditional for the VFP variants only, and the
12102 unconditional Neon version must have, e.g., 0xF in the condition field. */
12105 vfp_or_neon_is_neon (unsigned check
)
12107 /* Conditions are always legal in Thumb mode (IT blocks). */
12108 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
12110 if (inst
.cond
!= COND_ALWAYS
)
12112 first_error (_(BAD_COND
));
12115 if (inst
.uncond_value
!= -1)
12116 inst
.instruction
|= inst
.uncond_value
<< 28;
12119 if ((check
& NEON_CHECK_ARCH
)
12120 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
12122 first_error (_(BAD_FPU
));
12130 do_neon_addsub_if_i (void)
12132 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
12135 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12138 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12139 affected if we specify unsigned args. */
12140 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
12143 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
12145 V<op> A,B (A is operand 0, B is operand 2)
12150 so handle that case specially. */
12153 neon_exchange_operands (void)
12155 void *scratch
= alloca (sizeof (inst
.operands
[0]));
12156 if (inst
.operands
[1].present
)
12158 /* Swap operands[1] and operands[2]. */
12159 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
12160 inst
.operands
[1] = inst
.operands
[2];
12161 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
12165 inst
.operands
[1] = inst
.operands
[2];
12166 inst
.operands
[2] = inst
.operands
[0];
12171 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
12173 if (inst
.operands
[2].isreg
)
12176 neon_exchange_operands ();
12177 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
12181 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12182 struct neon_type_el et
= neon_check_type (2, rs
,
12183 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
12185 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12186 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12187 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12188 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12189 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12190 inst
.instruction
|= neon_quad (rs
) << 6;
12191 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12192 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12194 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12201 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
12205 do_neon_cmp_inv (void)
12207 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
12213 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
12216 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
12217 scalars, which are encoded in 5 bits, M : Rm.
12218 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
12219 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
12223 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
12225 unsigned regno
= NEON_SCALAR_REG (scalar
);
12226 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
12231 if (regno
> 7 || elno
> 3)
12233 return regno
| (elno
<< 3);
12236 if (regno
> 15 || elno
> 1)
12238 return regno
| (elno
<< 4);
12242 first_error (_("scalar out of range for multiply instruction"));
12248 /* Encode multiply / multiply-accumulate scalar instructions. */
12251 neon_mul_mac (struct neon_type_el et
, int ubit
)
12255 /* Give a more helpful error message if we have an invalid type. */
12256 if (et
.type
== NT_invtype
)
12259 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
12260 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12261 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12262 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12263 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12264 inst
.instruction
|= LOW4 (scalar
);
12265 inst
.instruction
|= HI1 (scalar
) << 5;
12266 inst
.instruction
|= (et
.type
== NT_float
) << 8;
12267 inst
.instruction
|= neon_logbits (et
.size
) << 20;
12268 inst
.instruction
|= (ubit
!= 0) << 24;
12270 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12274 do_neon_mac_maybe_scalar (void)
12276 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
12279 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12282 if (inst
.operands
[2].isscalar
)
12284 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
12285 struct neon_type_el et
= neon_check_type (3, rs
,
12286 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
12287 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12288 neon_mul_mac (et
, neon_quad (rs
));
12292 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12293 affected if we specify unsigned args. */
12294 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12301 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12302 struct neon_type_el et
= neon_check_type (3, rs
,
12303 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12304 neon_three_same (neon_quad (rs
), 0, et
.size
);
12307 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
12308 same types as the MAC equivalents. The polynomial type for this instruction
12309 is encoded the same as the integer type. */
12314 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
12317 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12320 if (inst
.operands
[2].isscalar
)
12321 do_neon_mac_maybe_scalar ();
12323 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
12327 do_neon_qdmulh (void)
12329 if (inst
.operands
[2].isscalar
)
12331 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
12332 struct neon_type_el et
= neon_check_type (3, rs
,
12333 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
12334 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12335 neon_mul_mac (et
, neon_quad (rs
));
12339 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12340 struct neon_type_el et
= neon_check_type (3, rs
,
12341 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
12342 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12343 /* The U bit (rounding) comes from bit mask. */
12344 neon_three_same (neon_quad (rs
), 0, et
.size
);
12349 do_neon_fcmp_absolute (void)
12351 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12352 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12353 /* Size field comes from bit mask. */
12354 neon_three_same (neon_quad (rs
), 1, -1);
12358 do_neon_fcmp_absolute_inv (void)
12360 neon_exchange_operands ();
12361 do_neon_fcmp_absolute ();
12365 do_neon_step (void)
12367 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12368 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12369 neon_three_same (neon_quad (rs
), 0, -1);
12373 do_neon_abs_neg (void)
12375 enum neon_shape rs
;
12376 struct neon_type_el et
;
12378 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
12381 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12384 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12385 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
12387 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12388 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12389 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12390 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12391 inst
.instruction
|= neon_quad (rs
) << 6;
12392 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12393 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12395 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12401 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12402 struct neon_type_el et
= neon_check_type (2, rs
,
12403 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12404 int imm
= inst
.operands
[2].imm
;
12405 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12406 _("immediate out of range for insert"));
12407 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12413 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12414 struct neon_type_el et
= neon_check_type (2, rs
,
12415 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12416 int imm
= inst
.operands
[2].imm
;
12417 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12418 _("immediate out of range for insert"));
12419 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
12423 do_neon_qshlu_imm (void)
12425 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12426 struct neon_type_el et
= neon_check_type (2, rs
,
12427 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
12428 int imm
= inst
.operands
[2].imm
;
12429 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12430 _("immediate out of range for shift"));
12431 /* Only encodes the 'U present' variant of the instruction.
12432 In this case, signed types have OP (bit 8) set to 0.
12433 Unsigned types have OP set to 1. */
12434 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
12435 /* The rest of the bits are the same as other immediate shifts. */
12436 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12440 do_neon_qmovn (void)
12442 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12443 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12444 /* Saturating move where operands can be signed or unsigned, and the
12445 destination has the same signedness. */
12446 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12447 if (et
.type
== NT_unsigned
)
12448 inst
.instruction
|= 0xc0;
12450 inst
.instruction
|= 0x80;
12451 neon_two_same (0, 1, et
.size
/ 2);
12455 do_neon_qmovun (void)
12457 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12458 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12459 /* Saturating move with unsigned results. Operands must be signed. */
12460 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12461 neon_two_same (0, 1, et
.size
/ 2);
12465 do_neon_rshift_sat_narrow (void)
12467 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12468 or unsigned. If operands are unsigned, results must also be unsigned. */
12469 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12470 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12471 int imm
= inst
.operands
[2].imm
;
12472 /* This gets the bounds check, size encoding and immediate bits calculation
12476 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
12477 VQMOVN.I<size> <Dd>, <Qm>. */
12480 inst
.operands
[2].present
= 0;
12481 inst
.instruction
= N_MNEM_vqmovn
;
12486 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12487 _("immediate out of range"));
12488 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
12492 do_neon_rshift_sat_narrow_u (void)
12494 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12495 or unsigned. If operands are unsigned, results must also be unsigned. */
12496 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12497 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12498 int imm
= inst
.operands
[2].imm
;
12499 /* This gets the bounds check, size encoding and immediate bits calculation
12503 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
12504 VQMOVUN.I<size> <Dd>, <Qm>. */
12507 inst
.operands
[2].present
= 0;
12508 inst
.instruction
= N_MNEM_vqmovun
;
12513 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12514 _("immediate out of range"));
12515 /* FIXME: The manual is kind of unclear about what value U should have in
12516 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
12518 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
12522 do_neon_movn (void)
12524 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12525 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12526 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12527 neon_two_same (0, 1, et
.size
/ 2);
12531 do_neon_rshift_narrow (void)
12533 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12534 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12535 int imm
= inst
.operands
[2].imm
;
12536 /* This gets the bounds check, size encoding and immediate bits calculation
12540 /* If immediate is zero then we are a pseudo-instruction for
12541 VMOVN.I<size> <Dd>, <Qm> */
12544 inst
.operands
[2].present
= 0;
12545 inst
.instruction
= N_MNEM_vmovn
;
12550 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12551 _("immediate out of range for narrowing operation"));
12552 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
12556 do_neon_shll (void)
12558 /* FIXME: Type checking when lengthening. */
12559 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
12560 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
12561 unsigned imm
= inst
.operands
[2].imm
;
12563 if (imm
== et
.size
)
12565 /* Maximum shift variant. */
12566 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12567 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12568 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12569 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12570 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12571 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12573 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12577 /* A more-specific type check for non-max versions. */
12578 et
= neon_check_type (2, NS_QDI
,
12579 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12580 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12581 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
12585 /* Check the various types for the VCVT instruction, and return which version
12586 the current instruction is. */
12589 neon_cvt_flavour (enum neon_shape rs
)
12591 #define CVT_VAR(C,X,Y) \
12592 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
12593 if (et.type != NT_invtype) \
12595 inst.error = NULL; \
12598 struct neon_type_el et
;
12599 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
12600 || rs
== NS_FF
) ? N_VFP
: 0;
12601 /* The instruction versions which take an immediate take one register
12602 argument, which is extended to the width of the full register. Thus the
12603 "source" and "destination" registers must have the same width. Hack that
12604 here by making the size equal to the key (wider, in this case) operand. */
12605 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
12607 CVT_VAR (0, N_S32
, N_F32
);
12608 CVT_VAR (1, N_U32
, N_F32
);
12609 CVT_VAR (2, N_F32
, N_S32
);
12610 CVT_VAR (3, N_F32
, N_U32
);
12611 /* Half-precision conversions. */
12612 CVT_VAR (4, N_F32
, N_F16
);
12613 CVT_VAR (5, N_F16
, N_F32
);
12617 /* VFP instructions. */
12618 CVT_VAR (6, N_F32
, N_F64
);
12619 CVT_VAR (7, N_F64
, N_F32
);
12620 CVT_VAR (8, N_S32
, N_F64
| key
);
12621 CVT_VAR (9, N_U32
, N_F64
| key
);
12622 CVT_VAR (10, N_F64
| key
, N_S32
);
12623 CVT_VAR (11, N_F64
| key
, N_U32
);
12624 /* VFP instructions with bitshift. */
12625 CVT_VAR (12, N_F32
| key
, N_S16
);
12626 CVT_VAR (13, N_F32
| key
, N_U16
);
12627 CVT_VAR (14, N_F64
| key
, N_S16
);
12628 CVT_VAR (15, N_F64
| key
, N_U16
);
12629 CVT_VAR (16, N_S16
, N_F32
| key
);
12630 CVT_VAR (17, N_U16
, N_F32
| key
);
12631 CVT_VAR (18, N_S16
, N_F64
| key
);
12632 CVT_VAR (19, N_U16
, N_F64
| key
);
12638 /* Neon-syntax VFP conversions. */
12641 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
12643 const char *opname
= 0;
12645 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
12647 /* Conversions with immediate bitshift. */
12648 const char *enc
[] =
12672 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12674 opname
= enc
[flavour
];
12675 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12676 _("operands 0 and 1 must be the same register"));
12677 inst
.operands
[1] = inst
.operands
[2];
12678 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
12683 /* Conversions without bitshift. */
12684 const char *enc
[] =
12700 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12701 opname
= enc
[flavour
];
12705 do_vfp_nsyn_opcode (opname
);
12709 do_vfp_nsyn_cvtz (void)
12711 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
12712 int flavour
= neon_cvt_flavour (rs
);
12713 const char *enc
[] =
12727 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
12728 do_vfp_nsyn_opcode (enc
[flavour
]);
12733 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
12734 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
12735 int flavour
= neon_cvt_flavour (rs
);
12737 /* VFP rather than Neon conversions. */
12740 do_vfp_nsyn_cvt (rs
, flavour
);
12750 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
12752 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12755 /* Fixed-point conversion with #0 immediate is encoded as an
12756 integer conversion. */
12757 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
12759 immbits
= 32 - inst
.operands
[2].imm
;
12760 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12762 inst
.instruction
|= enctab
[flavour
];
12763 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12764 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12765 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12766 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12767 inst
.instruction
|= neon_quad (rs
) << 6;
12768 inst
.instruction
|= 1 << 21;
12769 inst
.instruction
|= immbits
<< 16;
12771 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12779 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
12781 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12783 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12787 inst
.instruction
|= enctab
[flavour
];
12789 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12790 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12791 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12792 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12793 inst
.instruction
|= neon_quad (rs
) << 6;
12794 inst
.instruction
|= 2 << 18;
12796 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12800 /* Half-precision conversions for Advanced SIMD -- neon. */
12805 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
12807 as_bad (_("operand size must match register width"));
12812 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
12814 as_bad (_("operand size must match register width"));
12819 inst
.instruction
= 0x3b60600;
12821 inst
.instruction
= 0x3b60700;
12823 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12824 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12825 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12826 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12827 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12831 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
12832 do_vfp_nsyn_cvt (rs
, flavour
);
12837 do_neon_cvtb (void)
12839 inst
.instruction
= 0xeb20a40;
12841 /* The sizes are attached to the mnemonic. */
12842 if (inst
.vectype
.el
[0].type
!= NT_invtype
12843 && inst
.vectype
.el
[0].size
== 16)
12844 inst
.instruction
|= 0x00010000;
12846 /* Programmer's syntax: the sizes are attached to the operands. */
12847 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
12848 && inst
.operands
[0].vectype
.size
== 16)
12849 inst
.instruction
|= 0x00010000;
12851 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
12852 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
12853 do_vfp_cond_or_thumb ();
12858 do_neon_cvtt (void)
12861 inst
.instruction
|= 0x80;
12865 neon_move_immediate (void)
12867 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12868 struct neon_type_el et
= neon_check_type (2, rs
,
12869 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12870 unsigned immlo
, immhi
= 0, immbits
;
12871 int op
, cmode
, float_p
;
12873 constraint (et
.type
== NT_invtype
,
12874 _("operand size must be specified for immediate VMOV"));
12876 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
12877 op
= (inst
.instruction
& (1 << 5)) != 0;
12879 immlo
= inst
.operands
[1].imm
;
12880 if (inst
.operands
[1].regisimm
)
12881 immhi
= inst
.operands
[1].reg
;
12883 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
12884 _("immediate has bits set outside the operand size"));
12886 float_p
= inst
.operands
[1].immisfloat
;
12888 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
12889 et
.size
, et
.type
)) == FAIL
)
12891 /* Invert relevant bits only. */
12892 neon_invert_size (&immlo
, &immhi
, et
.size
);
12893 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
12894 with one or the other; those cases are caught by
12895 neon_cmode_for_move_imm. */
12897 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
12898 &op
, et
.size
, et
.type
)) == FAIL
)
12900 first_error (_("immediate out of range"));
12905 inst
.instruction
&= ~(1 << 5);
12906 inst
.instruction
|= op
<< 5;
12908 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12909 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12910 inst
.instruction
|= neon_quad (rs
) << 6;
12911 inst
.instruction
|= cmode
<< 8;
12913 neon_write_immbits (immbits
);
12919 if (inst
.operands
[1].isreg
)
12921 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12923 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12924 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12925 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12926 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12927 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12928 inst
.instruction
|= neon_quad (rs
) << 6;
12932 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12933 neon_move_immediate ();
12936 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12939 /* Encode instructions of form:
12941 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12942 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
12945 neon_mixed_length (struct neon_type_el et
, unsigned size
)
12947 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12948 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12949 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12950 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12951 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12952 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12953 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
12954 inst
.instruction
|= neon_logbits (size
) << 20;
12956 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12960 do_neon_dyadic_long (void)
12962 /* FIXME: Type checking for lengthening op. */
12963 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12964 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12965 neon_mixed_length (et
, et
.size
);
12969 do_neon_abal (void)
12971 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12972 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12973 neon_mixed_length (et
, et
.size
);
12977 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
12979 if (inst
.operands
[2].isscalar
)
12981 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
12982 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
12983 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12984 neon_mul_mac (et
, et
.type
== NT_unsigned
);
12988 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12989 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
12990 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12991 neon_mixed_length (et
, et
.size
);
12996 do_neon_mac_maybe_scalar_long (void)
12998 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
13002 do_neon_dyadic_wide (void)
13004 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
13005 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13006 neon_mixed_length (et
, et
.size
);
13010 do_neon_dyadic_narrow (void)
13012 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13013 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
13014 /* Operand sign is unimportant, and the U bit is part of the opcode,
13015 so force the operand type to integer. */
13016 et
.type
= NT_integer
;
13017 neon_mixed_length (et
, et
.size
/ 2);
13021 do_neon_mul_sat_scalar_long (void)
13023 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
13027 do_neon_vmull (void)
13029 if (inst
.operands
[2].isscalar
)
13030 do_neon_mac_maybe_scalar_long ();
13033 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13034 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
13035 if (et
.type
== NT_poly
)
13036 inst
.instruction
= NEON_ENC_POLY (inst
.instruction
);
13038 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13039 /* For polynomial encoding, size field must be 0b00 and the U bit must be
13040 zero. Should be OK as-is. */
13041 neon_mixed_length (et
, et
.size
);
13048 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
13049 struct neon_type_el et
= neon_check_type (3, rs
,
13050 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13051 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
13053 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
13054 _("shift out of range"));
13055 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13056 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13057 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13058 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13059 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13060 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13061 inst
.instruction
|= neon_quad (rs
) << 6;
13062 inst
.instruction
|= imm
<< 8;
13064 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13070 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13071 struct neon_type_el et
= neon_check_type (2, rs
,
13072 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13073 unsigned op
= (inst
.instruction
>> 7) & 3;
13074 /* N (width of reversed regions) is encoded as part of the bitmask. We
13075 extract it here to check the elements to be reversed are smaller.
13076 Otherwise we'd get a reserved instruction. */
13077 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
13078 assert (elsize
!= 0);
13079 constraint (et
.size
>= elsize
,
13080 _("elements must be smaller than reversal region"));
13081 neon_two_same (neon_quad (rs
), 1, et
.size
);
13087 if (inst
.operands
[1].isscalar
)
13089 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
13090 struct neon_type_el et
= neon_check_type (2, rs
,
13091 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13092 unsigned sizebits
= et
.size
>> 3;
13093 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
13094 int logsize
= neon_logbits (et
.size
);
13095 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
13097 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
13100 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13101 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13102 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13103 inst
.instruction
|= LOW4 (dm
);
13104 inst
.instruction
|= HI1 (dm
) << 5;
13105 inst
.instruction
|= neon_quad (rs
) << 6;
13106 inst
.instruction
|= x
<< 17;
13107 inst
.instruction
|= sizebits
<< 16;
13109 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13113 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
13114 struct neon_type_el et
= neon_check_type (2, rs
,
13115 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13116 /* Duplicate ARM register to lanes of vector. */
13117 inst
.instruction
= NEON_ENC_ARMREG (inst
.instruction
);
13120 case 8: inst
.instruction
|= 0x400000; break;
13121 case 16: inst
.instruction
|= 0x000020; break;
13122 case 32: inst
.instruction
|= 0x000000; break;
13125 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13126 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
13127 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
13128 inst
.instruction
|= neon_quad (rs
) << 21;
13129 /* The encoding for this instruction is identical for the ARM and Thumb
13130 variants, except for the condition field. */
13131 do_vfp_cond_or_thumb ();
13135 /* VMOV has particularly many variations. It can be one of:
13136 0. VMOV<c><q> <Qd>, <Qm>
13137 1. VMOV<c><q> <Dd>, <Dm>
13138 (Register operations, which are VORR with Rm = Rn.)
13139 2. VMOV<c><q>.<dt> <Qd>, #<imm>
13140 3. VMOV<c><q>.<dt> <Dd>, #<imm>
13142 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
13143 (ARM register to scalar.)
13144 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
13145 (Two ARM registers to vector.)
13146 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
13147 (Scalar to ARM register.)
13148 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
13149 (Vector to two ARM registers.)
13150 8. VMOV.F32 <Sd>, <Sm>
13151 9. VMOV.F64 <Dd>, <Dm>
13152 (VFP register moves.)
13153 10. VMOV.F32 <Sd>, #imm
13154 11. VMOV.F64 <Dd>, #imm
13155 (VFP float immediate load.)
13156 12. VMOV <Rd>, <Sm>
13157 (VFP single to ARM reg.)
13158 13. VMOV <Sd>, <Rm>
13159 (ARM reg to VFP single.)
13160 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
13161 (Two ARM regs to two VFP singles.)
13162 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
13163 (Two VFP singles to two ARM regs.)
13165 These cases can be disambiguated using neon_select_shape, except cases 1/9
13166 and 3/11 which depend on the operand type too.
13168 All the encoded bits are hardcoded by this function.
13170 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
13171 Cases 5, 7 may be used with VFPv2 and above.
13173 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
13174 can specify a type where it doesn't make sense to, and is ignored). */
13179 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
13180 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
13182 struct neon_type_el et
;
13183 const char *ldconst
= 0;
13187 case NS_DD
: /* case 1/9. */
13188 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
13189 /* It is not an error here if no type is given. */
13191 if (et
.type
== NT_float
&& et
.size
== 64)
13193 do_vfp_nsyn_opcode ("fcpyd");
13196 /* fall through. */
13198 case NS_QQ
: /* case 0/1. */
13200 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13202 /* The architecture manual I have doesn't explicitly state which
13203 value the U bit should have for register->register moves, but
13204 the equivalent VORR instruction has U = 0, so do that. */
13205 inst
.instruction
= 0x0200110;
13206 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13207 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13208 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13209 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13210 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13211 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13212 inst
.instruction
|= neon_quad (rs
) << 6;
13214 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13218 case NS_DI
: /* case 3/11. */
13219 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
13221 if (et
.type
== NT_float
&& et
.size
== 64)
13223 /* case 11 (fconstd). */
13224 ldconst
= "fconstd";
13225 goto encode_fconstd
;
13227 /* fall through. */
13229 case NS_QI
: /* case 2/3. */
13230 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13232 inst
.instruction
= 0x0800010;
13233 neon_move_immediate ();
13234 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13237 case NS_SR
: /* case 4. */
13239 unsigned bcdebits
= 0;
13240 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
13241 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13242 int logsize
= neon_logbits (et
.size
);
13243 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
13244 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
13246 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
13248 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
13249 && et
.size
!= 32, _(BAD_FPU
));
13250 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
13251 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
13255 case 8: bcdebits
= 0x8; break;
13256 case 16: bcdebits
= 0x1; break;
13257 case 32: bcdebits
= 0x0; break;
13261 bcdebits
|= x
<< logsize
;
13263 inst
.instruction
= 0xe000b10;
13264 do_vfp_cond_or_thumb ();
13265 inst
.instruction
|= LOW4 (dn
) << 16;
13266 inst
.instruction
|= HI1 (dn
) << 7;
13267 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13268 inst
.instruction
|= (bcdebits
& 3) << 5;
13269 inst
.instruction
|= (bcdebits
>> 2) << 21;
13273 case NS_DRR
: /* case 5 (fmdrr). */
13274 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
13277 inst
.instruction
= 0xc400b10;
13278 do_vfp_cond_or_thumb ();
13279 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
13280 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
13281 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13282 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13285 case NS_RS
: /* case 6. */
13287 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
13288 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
13289 unsigned logsize
= neon_logbits (et
.size
);
13290 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
13291 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
13292 unsigned abcdebits
= 0;
13294 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
13296 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
13297 && et
.size
!= 32, _(BAD_FPU
));
13298 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
13299 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
13303 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
13304 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
13305 case 32: abcdebits
= 0x00; break;
13309 abcdebits
|= x
<< logsize
;
13310 inst
.instruction
= 0xe100b10;
13311 do_vfp_cond_or_thumb ();
13312 inst
.instruction
|= LOW4 (dn
) << 16;
13313 inst
.instruction
|= HI1 (dn
) << 7;
13314 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
13315 inst
.instruction
|= (abcdebits
& 3) << 5;
13316 inst
.instruction
|= (abcdebits
>> 2) << 21;
13320 case NS_RRD
: /* case 7 (fmrrd). */
13321 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
13324 inst
.instruction
= 0xc500b10;
13325 do_vfp_cond_or_thumb ();
13326 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
13327 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13328 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13329 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13332 case NS_FF
: /* case 8 (fcpys). */
13333 do_vfp_nsyn_opcode ("fcpys");
13336 case NS_FI
: /* case 10 (fconsts). */
13337 ldconst
= "fconsts";
13339 if (is_quarter_float (inst
.operands
[1].imm
))
13341 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
13342 do_vfp_nsyn_opcode (ldconst
);
13345 first_error (_("immediate out of range"));
13348 case NS_RF
: /* case 12 (fmrs). */
13349 do_vfp_nsyn_opcode ("fmrs");
13352 case NS_FR
: /* case 13 (fmsr). */
13353 do_vfp_nsyn_opcode ("fmsr");
13356 /* The encoders for the fmrrs and fmsrr instructions expect three operands
13357 (one of which is a list), but we have parsed four. Do some fiddling to
13358 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
13360 case NS_RRFF
: /* case 14 (fmrrs). */
13361 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
13362 _("VFP registers must be adjacent"));
13363 inst
.operands
[2].imm
= 2;
13364 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
13365 do_vfp_nsyn_opcode ("fmrrs");
13368 case NS_FFRR
: /* case 15 (fmsrr). */
13369 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
13370 _("VFP registers must be adjacent"));
13371 inst
.operands
[1] = inst
.operands
[2];
13372 inst
.operands
[2] = inst
.operands
[3];
13373 inst
.operands
[0].imm
= 2;
13374 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
13375 do_vfp_nsyn_opcode ("fmsrr");
13384 do_neon_rshift_round_imm (void)
13386 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13387 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
13388 int imm
= inst
.operands
[2].imm
;
13390 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
13393 inst
.operands
[2].present
= 0;
13398 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13399 _("immediate out of range for shift"));
13400 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
13405 do_neon_movl (void)
13407 struct neon_type_el et
= neon_check_type (2, NS_QD
,
13408 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13409 unsigned sizebits
= et
.size
>> 3;
13410 inst
.instruction
|= sizebits
<< 19;
13411 neon_two_same (0, et
.type
== NT_unsigned
, -1);
13417 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13418 struct neon_type_el et
= neon_check_type (2, rs
,
13419 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13420 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13421 neon_two_same (neon_quad (rs
), 1, et
.size
);
13425 do_neon_zip_uzp (void)
13427 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13428 struct neon_type_el et
= neon_check_type (2, rs
,
13429 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13430 if (rs
== NS_DD
&& et
.size
== 32)
13432 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
13433 inst
.instruction
= N_MNEM_vtrn
;
13437 neon_two_same (neon_quad (rs
), 1, et
.size
);
13441 do_neon_sat_abs_neg (void)
13443 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13444 struct neon_type_el et
= neon_check_type (2, rs
,
13445 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13446 neon_two_same (neon_quad (rs
), 1, et
.size
);
13450 do_neon_pair_long (void)
13452 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13453 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
13454 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
13455 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
13456 neon_two_same (neon_quad (rs
), 1, et
.size
);
13460 do_neon_recip_est (void)
13462 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13463 struct neon_type_el et
= neon_check_type (2, rs
,
13464 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
13465 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13466 neon_two_same (neon_quad (rs
), 1, et
.size
);
13472 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13473 struct neon_type_el et
= neon_check_type (2, rs
,
13474 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13475 neon_two_same (neon_quad (rs
), 1, et
.size
);
13481 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13482 struct neon_type_el et
= neon_check_type (2, rs
,
13483 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
13484 neon_two_same (neon_quad (rs
), 1, et
.size
);
13490 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13491 struct neon_type_el et
= neon_check_type (2, rs
,
13492 N_EQK
| N_INT
, N_8
| N_KEY
);
13493 neon_two_same (neon_quad (rs
), 1, et
.size
);
13499 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13500 neon_two_same (neon_quad (rs
), 1, -1);
13504 do_neon_tbl_tbx (void)
13506 unsigned listlenbits
;
13507 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
13509 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
13511 first_error (_("bad list length for table lookup"));
13515 listlenbits
= inst
.operands
[1].imm
- 1;
13516 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13517 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13518 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13519 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13520 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13521 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13522 inst
.instruction
|= listlenbits
<< 8;
13524 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13528 do_neon_ldm_stm (void)
13530 /* P, U and L bits are part of bitmask. */
13531 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
13532 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
13534 if (inst
.operands
[1].issingle
)
13536 do_vfp_nsyn_ldm_stm (is_dbmode
);
13540 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
13541 _("writeback (!) must be used for VLDMDB and VSTMDB"));
13543 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
13544 _("register list must contain at least 1 and at most 16 "
13547 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
13548 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
13549 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13550 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
13552 inst
.instruction
|= offsetbits
;
13554 do_vfp_cond_or_thumb ();
13558 do_neon_ldr_str (void)
13560 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
13562 if (inst
.operands
[0].issingle
)
13565 do_vfp_nsyn_opcode ("flds");
13567 do_vfp_nsyn_opcode ("fsts");
13572 do_vfp_nsyn_opcode ("fldd");
13574 do_vfp_nsyn_opcode ("fstd");
13578 /* "interleave" version also handles non-interleaving register VLD1/VST1
13582 do_neon_ld_st_interleave (void)
13584 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
13585 N_8
| N_16
| N_32
| N_64
);
13586 unsigned alignbits
= 0;
13588 /* The bits in this table go:
13589 0: register stride of one (0) or two (1)
13590 1,2: register list length, minus one (1, 2, 3, 4).
13591 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
13592 We use -1 for invalid entries. */
13593 const int typetable
[] =
13595 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
13596 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
13597 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
13598 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
13602 if (et
.type
== NT_invtype
)
13605 if (inst
.operands
[1].immisalign
)
13606 switch (inst
.operands
[1].imm
>> 8)
13608 case 64: alignbits
= 1; break;
13610 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13611 goto bad_alignment
;
13615 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13616 goto bad_alignment
;
13621 first_error (_("bad alignment"));
13625 inst
.instruction
|= alignbits
<< 4;
13626 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13628 /* Bits [4:6] of the immediate in a list specifier encode register stride
13629 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
13630 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
13631 up the right value for "type" in a table based on this value and the given
13632 list style, then stick it back. */
13633 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
13634 | (((inst
.instruction
>> 8) & 3) << 3);
13636 typebits
= typetable
[idx
];
13638 constraint (typebits
== -1, _("bad list type for instruction"));
13640 inst
.instruction
&= ~0xf00;
13641 inst
.instruction
|= typebits
<< 8;
13644 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
13645 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
13646 otherwise. The variable arguments are a list of pairs of legal (size, align)
13647 values, terminated with -1. */
13650 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
13653 int result
= FAIL
, thissize
, thisalign
;
13655 if (!inst
.operands
[1].immisalign
)
13661 va_start (ap
, do_align
);
13665 thissize
= va_arg (ap
, int);
13666 if (thissize
== -1)
13668 thisalign
= va_arg (ap
, int);
13670 if (size
== thissize
&& align
== thisalign
)
13673 while (result
!= SUCCESS
);
13677 if (result
== SUCCESS
)
13680 first_error (_("unsupported alignment for instruction"));
13686 do_neon_ld_st_lane (void)
13688 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13689 int align_good
, do_align
= 0;
13690 int logsize
= neon_logbits (et
.size
);
13691 int align
= inst
.operands
[1].imm
>> 8;
13692 int n
= (inst
.instruction
>> 8) & 3;
13693 int max_el
= 64 / et
.size
;
13695 if (et
.type
== NT_invtype
)
13698 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
13699 _("bad list length"));
13700 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
13701 _("scalar index out of range"));
13702 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
13704 _("stride of 2 unavailable when element size is 8"));
13708 case 0: /* VLD1 / VST1. */
13709 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
13711 if (align_good
== FAIL
)
13715 unsigned alignbits
= 0;
13718 case 16: alignbits
= 0x1; break;
13719 case 32: alignbits
= 0x3; break;
13722 inst
.instruction
|= alignbits
<< 4;
13726 case 1: /* VLD2 / VST2. */
13727 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
13729 if (align_good
== FAIL
)
13732 inst
.instruction
|= 1 << 4;
13735 case 2: /* VLD3 / VST3. */
13736 constraint (inst
.operands
[1].immisalign
,
13737 _("can't use alignment with this instruction"));
13740 case 3: /* VLD4 / VST4. */
13741 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13742 16, 64, 32, 64, 32, 128, -1);
13743 if (align_good
== FAIL
)
13747 unsigned alignbits
= 0;
13750 case 8: alignbits
= 0x1; break;
13751 case 16: alignbits
= 0x1; break;
13752 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
13755 inst
.instruction
|= alignbits
<< 4;
13762 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
13763 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13764 inst
.instruction
|= 1 << (4 + logsize
);
13766 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
13767 inst
.instruction
|= logsize
<< 10;
13770 /* Encode single n-element structure to all lanes VLD<n> instructions. */
13773 do_neon_ld_dup (void)
13775 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13776 int align_good
, do_align
= 0;
13778 if (et
.type
== NT_invtype
)
13781 switch ((inst
.instruction
>> 8) & 3)
13783 case 0: /* VLD1. */
13784 assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
13785 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13786 &do_align
, 16, 16, 32, 32, -1);
13787 if (align_good
== FAIL
)
13789 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
13792 case 2: inst
.instruction
|= 1 << 5; break;
13793 default: first_error (_("bad list length")); return;
13795 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13798 case 1: /* VLD2. */
13799 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13800 &do_align
, 8, 16, 16, 32, 32, 64, -1);
13801 if (align_good
== FAIL
)
13803 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
13804 _("bad list length"));
13805 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13806 inst
.instruction
|= 1 << 5;
13807 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13810 case 2: /* VLD3. */
13811 constraint (inst
.operands
[1].immisalign
,
13812 _("can't use alignment with this instruction"));
13813 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
13814 _("bad list length"));
13815 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13816 inst
.instruction
|= 1 << 5;
13817 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13820 case 3: /* VLD4. */
13822 int align
= inst
.operands
[1].imm
>> 8;
13823 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13824 16, 64, 32, 64, 32, 128, -1);
13825 if (align_good
== FAIL
)
13827 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
13828 _("bad list length"));
13829 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13830 inst
.instruction
|= 1 << 5;
13831 if (et
.size
== 32 && align
== 128)
13832 inst
.instruction
|= 0x3 << 6;
13834 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13841 inst
.instruction
|= do_align
<< 4;
13844 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
13845 apart from bits [11:4]. */
13848 do_neon_ldx_stx (void)
13850 switch (NEON_LANE (inst
.operands
[0].imm
))
13852 case NEON_INTERLEAVE_LANES
:
13853 inst
.instruction
= NEON_ENC_INTERLV (inst
.instruction
);
13854 do_neon_ld_st_interleave ();
13857 case NEON_ALL_LANES
:
13858 inst
.instruction
= NEON_ENC_DUP (inst
.instruction
);
13863 inst
.instruction
= NEON_ENC_LANE (inst
.instruction
);
13864 do_neon_ld_st_lane ();
13867 /* L bit comes from bit mask. */
13868 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13869 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13870 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13872 if (inst
.operands
[1].postind
)
13874 int postreg
= inst
.operands
[1].imm
& 0xf;
13875 constraint (!inst
.operands
[1].immisreg
,
13876 _("post-index must be a register"));
13877 constraint (postreg
== 0xd || postreg
== 0xf,
13878 _("bad register for post-index"));
13879 inst
.instruction
|= postreg
;
13881 else if (inst
.operands
[1].writeback
)
13883 inst
.instruction
|= 0xd;
13886 inst
.instruction
|= 0xf;
13889 inst
.instruction
|= 0xf9000000;
13891 inst
.instruction
|= 0xf4000000;
13894 /* Overall per-instruction processing. */
13896 /* We need to be able to fix up arbitrary expressions in some statements.
13897 This is so that we can handle symbols that are an arbitrary distance from
13898 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
13899 which returns part of an address in a form which will be valid for
13900 a data instruction. We do this by pushing the expression into a symbol
13901 in the expr_section, and creating a fix for that. */
13904 fix_new_arm (fragS
* frag
,
13919 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
13923 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
13928 /* Mark whether the fix is to a THUMB instruction, or an ARM
13930 new_fix
->tc_fix_data
= thumb_mode
;
13933 /* Create a frg for an instruction requiring relaxation. */
13935 output_relax_insn (void)
13941 /* The size of the instruction is unknown, so tie the debug info to the
13942 start of the instruction. */
13943 dwarf2_emit_insn (0);
13945 switch (inst
.reloc
.exp
.X_op
)
13948 sym
= inst
.reloc
.exp
.X_add_symbol
;
13949 offset
= inst
.reloc
.exp
.X_add_number
;
13953 offset
= inst
.reloc
.exp
.X_add_number
;
13956 sym
= make_expr_symbol (&inst
.reloc
.exp
);
13960 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
13961 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
13962 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
13965 /* Write a 32-bit thumb instruction to buf. */
13967 put_thumb32_insn (char * buf
, unsigned long insn
)
13969 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
13970 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
13974 output_inst (const char * str
)
13980 as_bad ("%s -- `%s'", inst
.error
, str
);
13985 output_relax_insn ();
13988 if (inst
.size
== 0)
13991 to
= frag_more (inst
.size
);
13993 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
13995 assert (inst
.size
== (2 * THUMB_SIZE
));
13996 put_thumb32_insn (to
, inst
.instruction
);
13998 else if (inst
.size
> INSN_SIZE
)
14000 assert (inst
.size
== (2 * INSN_SIZE
));
14001 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
14002 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
14005 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
14007 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
14008 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
14009 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
14012 dwarf2_emit_insn (inst
.size
);
14015 /* Tag values used in struct asm_opcode's tag field. */
14018 OT_unconditional
, /* Instruction cannot be conditionalized.
14019 The ARM condition field is still 0xE. */
14020 OT_unconditionalF
, /* Instruction cannot be conditionalized
14021 and carries 0xF in its ARM condition field. */
14022 OT_csuffix
, /* Instruction takes a conditional suffix. */
14023 OT_csuffixF
, /* Some forms of the instruction take a conditional
14024 suffix, others place 0xF where the condition field
14026 OT_cinfix3
, /* Instruction takes a conditional infix,
14027 beginning at character index 3. (In
14028 unified mode, it becomes a suffix.) */
14029 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
14030 tsts, cmps, cmns, and teqs. */
14031 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
14032 character index 3, even in unified mode. Used for
14033 legacy instructions where suffix and infix forms
14034 may be ambiguous. */
14035 OT_csuf_or_in3
, /* Instruction takes either a conditional
14036 suffix or an infix at character index 3. */
14037 OT_odd_infix_unc
, /* This is the unconditional variant of an
14038 instruction that takes a conditional infix
14039 at an unusual position. In unified mode,
14040 this variant will accept a suffix. */
14041 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
14042 are the conditional variants of instructions that
14043 take conditional infixes in unusual positions.
14044 The infix appears at character index
14045 (tag - OT_odd_infix_0). These are not accepted
14046 in unified mode. */
14049 /* Subroutine of md_assemble, responsible for looking up the primary
14050 opcode from the mnemonic the user wrote. STR points to the
14051 beginning of the mnemonic.
14053 This is not simply a hash table lookup, because of conditional
14054 variants. Most instructions have conditional variants, which are
14055 expressed with a _conditional affix_ to the mnemonic. If we were
14056 to encode each conditional variant as a literal string in the opcode
14057 table, it would have approximately 20,000 entries.
14059 Most mnemonics take this affix as a suffix, and in unified syntax,
14060 'most' is upgraded to 'all'. However, in the divided syntax, some
14061 instructions take the affix as an infix, notably the s-variants of
14062 the arithmetic instructions. Of those instructions, all but six
14063 have the infix appear after the third character of the mnemonic.
14065 Accordingly, the algorithm for looking up primary opcodes given
14068 1. Look up the identifier in the opcode table.
14069 If we find a match, go to step U.
14071 2. Look up the last two characters of the identifier in the
14072 conditions table. If we find a match, look up the first N-2
14073 characters of the identifier in the opcode table. If we
14074 find a match, go to step CE.
14076 3. Look up the fourth and fifth characters of the identifier in
14077 the conditions table. If we find a match, extract those
14078 characters from the identifier, and look up the remaining
14079 characters in the opcode table. If we find a match, go
14084 U. Examine the tag field of the opcode structure, in case this is
14085 one of the six instructions with its conditional infix in an
14086 unusual place. If it is, the tag tells us where to find the
14087 infix; look it up in the conditions table and set inst.cond
14088 accordingly. Otherwise, this is an unconditional instruction.
14089 Again set inst.cond accordingly. Return the opcode structure.
14091 CE. Examine the tag field to make sure this is an instruction that
14092 should receive a conditional suffix. If it is not, fail.
14093 Otherwise, set inst.cond from the suffix we already looked up,
14094 and return the opcode structure.
14096 CM. Examine the tag field to make sure this is an instruction that
14097 should receive a conditional infix after the third character.
14098 If it is not, fail. Otherwise, undo the edits to the current
14099 line of input and proceed as for case CE. */
14101 static const struct asm_opcode
*
14102 opcode_lookup (char **str
)
14106 const struct asm_opcode
*opcode
;
14107 const struct asm_cond
*cond
;
14109 bfd_boolean neon_supported
;
14111 neon_supported
= ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
);
14113 /* Scan up to the end of the mnemonic, which must end in white space,
14114 '.' (in unified mode, or for Neon instructions), or end of string. */
14115 for (base
= end
= *str
; *end
!= '\0'; end
++)
14116 if (*end
== ' ' || ((unified_syntax
|| neon_supported
) && *end
== '.'))
14122 /* Handle a possible width suffix and/or Neon type suffix. */
14127 /* The .w and .n suffixes are only valid if the unified syntax is in
14129 if (unified_syntax
&& end
[1] == 'w')
14131 else if (unified_syntax
&& end
[1] == 'n')
14136 inst
.vectype
.elems
= 0;
14138 *str
= end
+ offset
;
14140 if (end
[offset
] == '.')
14142 /* See if we have a Neon type suffix (possible in either unified or
14143 non-unified ARM syntax mode). */
14144 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
14147 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
14153 /* Look for unaffixed or special-case affixed mnemonic. */
14154 opcode
= hash_find_n (arm_ops_hsh
, base
, end
- base
);
14158 if (opcode
->tag
< OT_odd_infix_0
)
14160 inst
.cond
= COND_ALWAYS
;
14164 if (unified_syntax
)
14165 as_warn (_("conditional infixes are deprecated in unified syntax"));
14166 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
14167 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14170 inst
.cond
= cond
->value
;
14174 /* Cannot have a conditional suffix on a mnemonic of less than two
14176 if (end
- base
< 3)
14179 /* Look for suffixed mnemonic. */
14181 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14182 opcode
= hash_find_n (arm_ops_hsh
, base
, affix
- base
);
14183 if (opcode
&& cond
)
14186 switch (opcode
->tag
)
14188 case OT_cinfix3_legacy
:
14189 /* Ignore conditional suffixes matched on infix only mnemonics. */
14193 case OT_cinfix3_deprecated
:
14194 case OT_odd_infix_unc
:
14195 if (!unified_syntax
)
14197 /* else fall through */
14201 case OT_csuf_or_in3
:
14202 inst
.cond
= cond
->value
;
14205 case OT_unconditional
:
14206 case OT_unconditionalF
:
14209 inst
.cond
= cond
->value
;
14213 /* delayed diagnostic */
14214 inst
.error
= BAD_COND
;
14215 inst
.cond
= COND_ALWAYS
;
14224 /* Cannot have a usual-position infix on a mnemonic of less than
14225 six characters (five would be a suffix). */
14226 if (end
- base
< 6)
14229 /* Look for infixed mnemonic in the usual position. */
14231 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14235 memcpy (save
, affix
, 2);
14236 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
14237 opcode
= hash_find_n (arm_ops_hsh
, base
, (end
- base
) - 2);
14238 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
14239 memcpy (affix
, save
, 2);
14242 && (opcode
->tag
== OT_cinfix3
14243 || opcode
->tag
== OT_cinfix3_deprecated
14244 || opcode
->tag
== OT_csuf_or_in3
14245 || opcode
->tag
== OT_cinfix3_legacy
))
14249 && (opcode
->tag
== OT_cinfix3
14250 || opcode
->tag
== OT_cinfix3_deprecated
))
14251 as_warn (_("conditional infixes are deprecated in unified syntax"));
14253 inst
.cond
= cond
->value
;
14261 md_assemble (char *str
)
14264 const struct asm_opcode
* opcode
;
14266 /* Align the previous label if needed. */
14267 if (last_label_seen
!= NULL
)
14269 symbol_set_frag (last_label_seen
, frag_now
);
14270 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
14271 S_SET_SEGMENT (last_label_seen
, now_seg
);
14274 memset (&inst
, '\0', sizeof (inst
));
14275 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
14277 opcode
= opcode_lookup (&p
);
14280 /* It wasn't an instruction, but it might be a register alias of
14281 the form alias .req reg, or a Neon .dn/.qn directive. */
14282 if (!create_register_alias (str
, p
)
14283 && !create_neon_reg_alias (str
, p
))
14284 as_bad (_("bad instruction `%s'"), str
);
14289 if (opcode
->tag
== OT_cinfix3_deprecated
)
14290 as_warn (_("s suffix on comparison instruction is deprecated"));
14292 /* The value which unconditional instructions should have in place of the
14293 condition field. */
14294 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
14298 arm_feature_set variant
;
14300 variant
= cpu_variant
;
14301 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
14302 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
14303 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
14304 /* Check that this instruction is supported for this CPU. */
14305 if (!opcode
->tvariant
14306 || (thumb_mode
== 1
14307 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
14309 as_bad (_("selected processor does not support `%s'"), str
);
14312 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
14313 && opcode
->tencode
!= do_t_branch
)
14315 as_bad (_("Thumb does not support conditional execution"));
14319 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
) && !inst
.size_req
)
14321 /* Implicit require narrow instructions on Thumb-1. This avoids
14322 relaxation accidentally introducing Thumb-2 instructions. */
14323 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
14324 && !ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
))
14328 /* Check conditional suffixes. */
14329 if (current_it_mask
)
14332 cond
= current_cc
^ ((current_it_mask
>> 4) & 1) ^ 1;
14333 current_it_mask
<<= 1;
14334 current_it_mask
&= 0x1f;
14335 /* The BKPT instruction is unconditional even in an IT block. */
14337 && cond
!= inst
.cond
&& opcode
->tencode
!= do_t_bkpt
)
14339 as_bad (_("incorrect condition in IT block"));
14343 else if (inst
.cond
!= COND_ALWAYS
&& opcode
->tencode
!= do_t_branch
)
14345 as_bad (_("thumb conditional instruction not in IT block"));
14349 mapping_state (MAP_THUMB
);
14350 inst
.instruction
= opcode
->tvalue
;
14352 if (!parse_operands (p
, opcode
->operands
))
14353 opcode
->tencode ();
14355 /* Clear current_it_mask at the end of an IT block. */
14356 if (current_it_mask
== 0x10)
14357 current_it_mask
= 0;
14359 if (!(inst
.error
|| inst
.relax
))
14361 assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
14362 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
14363 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
14365 as_bad (_("cannot honor width suffix -- `%s'"), str
);
14370 /* Something has gone badly wrong if we try to relax a fixed size
14372 assert (inst
.size_req
== 0 || !inst
.relax
);
14374 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
14375 *opcode
->tvariant
);
14376 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
14377 set those bits when Thumb-2 32-bit instructions are seen. ie.
14378 anything other than bl/blx and v6-M instructions.
14379 This is overly pessimistic for relaxable instructions. */
14380 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
14382 && !ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
))
14383 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
14386 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
14390 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
14391 is_bx
= (opcode
->aencode
== do_bx
);
14393 /* Check that this instruction is supported for this CPU. */
14394 if (!(is_bx
&& fix_v4bx
)
14395 && !(opcode
->avariant
&&
14396 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
14398 as_bad (_("selected processor does not support `%s'"), str
);
14403 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
14407 mapping_state (MAP_ARM
);
14408 inst
.instruction
= opcode
->avalue
;
14409 if (opcode
->tag
== OT_unconditionalF
)
14410 inst
.instruction
|= 0xF << 28;
14412 inst
.instruction
|= inst
.cond
<< 28;
14413 inst
.size
= INSN_SIZE
;
14414 if (!parse_operands (p
, opcode
->operands
))
14415 opcode
->aencode ();
14416 /* Arm mode bx is marked as both v4T and v5 because it's still required
14417 on a hypothetical non-thumb v5 core. */
14419 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
14421 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
14422 *opcode
->avariant
);
14426 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
14433 /* Various frobbings of labels and their addresses. */
14436 arm_start_line_hook (void)
14438 last_label_seen
= NULL
;
14442 arm_frob_label (symbolS
* sym
)
14444 last_label_seen
= sym
;
14446 ARM_SET_THUMB (sym
, thumb_mode
);
14448 #if defined OBJ_COFF || defined OBJ_ELF
14449 ARM_SET_INTERWORK (sym
, support_interwork
);
14452 /* Note - do not allow local symbols (.Lxxx) to be labelled
14453 as Thumb functions. This is because these labels, whilst
14454 they exist inside Thumb code, are not the entry points for
14455 possible ARM->Thumb calls. Also, these labels can be used
14456 as part of a computed goto or switch statement. eg gcc
14457 can generate code that looks like this:
14459 ldr r2, [pc, .Laaa]
14469 The first instruction loads the address of the jump table.
14470 The second instruction converts a table index into a byte offset.
14471 The third instruction gets the jump address out of the table.
14472 The fourth instruction performs the jump.
14474 If the address stored at .Laaa is that of a symbol which has the
14475 Thumb_Func bit set, then the linker will arrange for this address
14476 to have the bottom bit set, which in turn would mean that the
14477 address computation performed by the third instruction would end
14478 up with the bottom bit set. Since the ARM is capable of unaligned
14479 word loads, the instruction would then load the incorrect address
14480 out of the jump table, and chaos would ensue. */
14481 if (label_is_thumb_function_name
14482 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
14483 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
14485 /* When the address of a Thumb function is taken the bottom
14486 bit of that address should be set. This will allow
14487 interworking between Arm and Thumb functions to work
14490 THUMB_SET_FUNC (sym
, 1);
14492 label_is_thumb_function_name
= FALSE
;
14495 dwarf2_emit_label (sym
);
14499 arm_data_in_code (void)
14501 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
14503 *input_line_pointer
= '/';
14504 input_line_pointer
+= 5;
14505 *input_line_pointer
= 0;
14513 arm_canonicalize_symbol_name (char * name
)
14517 if (thumb_mode
&& (len
= strlen (name
)) > 5
14518 && streq (name
+ len
- 5, "/data"))
14519 *(name
+ len
- 5) = 0;
14524 /* Table of all register names defined by default. The user can
14525 define additional names with .req. Note that all register names
14526 should appear in both upper and lowercase variants. Some registers
14527 also have mixed-case names. */
14529 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
14530 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
14531 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
14532 #define REGSET(p,t) \
14533 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
14534 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
14535 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
14536 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
14537 #define REGSETH(p,t) \
14538 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
14539 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
14540 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
14541 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
14542 #define REGSET2(p,t) \
14543 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
14544 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
14545 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
14546 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
14548 static const struct reg_entry reg_names
[] =
14550 /* ARM integer registers. */
14551 REGSET(r
, RN
), REGSET(R
, RN
),
14553 /* ATPCS synonyms. */
14554 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
14555 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
14556 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
14558 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
14559 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
14560 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
14562 /* Well-known aliases. */
14563 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
14564 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
14566 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
14567 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
14569 /* Coprocessor numbers. */
14570 REGSET(p
, CP
), REGSET(P
, CP
),
14572 /* Coprocessor register numbers. The "cr" variants are for backward
14574 REGSET(c
, CN
), REGSET(C
, CN
),
14575 REGSET(cr
, CN
), REGSET(CR
, CN
),
14577 /* FPA registers. */
14578 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
14579 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
14581 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
14582 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
14584 /* VFP SP registers. */
14585 REGSET(s
,VFS
), REGSET(S
,VFS
),
14586 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
14588 /* VFP DP Registers. */
14589 REGSET(d
,VFD
), REGSET(D
,VFD
),
14590 /* Extra Neon DP registers. */
14591 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
14593 /* Neon QP registers. */
14594 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
14596 /* VFP control registers. */
14597 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
14598 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
14599 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
14600 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
14601 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
14602 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
14604 /* Maverick DSP coprocessor registers. */
14605 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
14606 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
14608 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
14609 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
14610 REGDEF(dspsc
,0,DSPSC
),
14612 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
14613 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
14614 REGDEF(DSPSC
,0,DSPSC
),
14616 /* iWMMXt data registers - p0, c0-15. */
14617 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
14619 /* iWMMXt control registers - p1, c0-3. */
14620 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
14621 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
14622 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
14623 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
14625 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
14626 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
14627 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
14628 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
14629 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
14631 /* XScale accumulator registers. */
14632 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
14638 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
14639 within psr_required_here. */
14640 static const struct asm_psr psrs
[] =
14642 /* Backward compatibility notation. Note that "all" is no longer
14643 truly all possible PSR bits. */
14644 {"all", PSR_c
| PSR_f
},
14648 /* Individual flags. */
14653 /* Combinations of flags. */
14654 {"fs", PSR_f
| PSR_s
},
14655 {"fx", PSR_f
| PSR_x
},
14656 {"fc", PSR_f
| PSR_c
},
14657 {"sf", PSR_s
| PSR_f
},
14658 {"sx", PSR_s
| PSR_x
},
14659 {"sc", PSR_s
| PSR_c
},
14660 {"xf", PSR_x
| PSR_f
},
14661 {"xs", PSR_x
| PSR_s
},
14662 {"xc", PSR_x
| PSR_c
},
14663 {"cf", PSR_c
| PSR_f
},
14664 {"cs", PSR_c
| PSR_s
},
14665 {"cx", PSR_c
| PSR_x
},
14666 {"fsx", PSR_f
| PSR_s
| PSR_x
},
14667 {"fsc", PSR_f
| PSR_s
| PSR_c
},
14668 {"fxs", PSR_f
| PSR_x
| PSR_s
},
14669 {"fxc", PSR_f
| PSR_x
| PSR_c
},
14670 {"fcs", PSR_f
| PSR_c
| PSR_s
},
14671 {"fcx", PSR_f
| PSR_c
| PSR_x
},
14672 {"sfx", PSR_s
| PSR_f
| PSR_x
},
14673 {"sfc", PSR_s
| PSR_f
| PSR_c
},
14674 {"sxf", PSR_s
| PSR_x
| PSR_f
},
14675 {"sxc", PSR_s
| PSR_x
| PSR_c
},
14676 {"scf", PSR_s
| PSR_c
| PSR_f
},
14677 {"scx", PSR_s
| PSR_c
| PSR_x
},
14678 {"xfs", PSR_x
| PSR_f
| PSR_s
},
14679 {"xfc", PSR_x
| PSR_f
| PSR_c
},
14680 {"xsf", PSR_x
| PSR_s
| PSR_f
},
14681 {"xsc", PSR_x
| PSR_s
| PSR_c
},
14682 {"xcf", PSR_x
| PSR_c
| PSR_f
},
14683 {"xcs", PSR_x
| PSR_c
| PSR_s
},
14684 {"cfs", PSR_c
| PSR_f
| PSR_s
},
14685 {"cfx", PSR_c
| PSR_f
| PSR_x
},
14686 {"csf", PSR_c
| PSR_s
| PSR_f
},
14687 {"csx", PSR_c
| PSR_s
| PSR_x
},
14688 {"cxf", PSR_c
| PSR_x
| PSR_f
},
14689 {"cxs", PSR_c
| PSR_x
| PSR_s
},
14690 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
14691 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
14692 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
14693 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
14694 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
14695 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
14696 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
14697 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
14698 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
14699 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
14700 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
14701 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
14702 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
14703 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
14704 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
14705 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
14706 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
14707 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
14708 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
14709 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
14710 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
14711 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
14712 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
14713 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
14716 /* Table of V7M psr names. */
14717 static const struct asm_psr v7m_psrs
[] =
14719 {"apsr", 0 }, {"APSR", 0 },
14720 {"iapsr", 1 }, {"IAPSR", 1 },
14721 {"eapsr", 2 }, {"EAPSR", 2 },
14722 {"psr", 3 }, {"PSR", 3 },
14723 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
14724 {"ipsr", 5 }, {"IPSR", 5 },
14725 {"epsr", 6 }, {"EPSR", 6 },
14726 {"iepsr", 7 }, {"IEPSR", 7 },
14727 {"msp", 8 }, {"MSP", 8 },
14728 {"psp", 9 }, {"PSP", 9 },
14729 {"primask", 16}, {"PRIMASK", 16},
14730 {"basepri", 17}, {"BASEPRI", 17},
14731 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
14732 {"faultmask", 19}, {"FAULTMASK", 19},
14733 {"control", 20}, {"CONTROL", 20}
14736 /* Table of all shift-in-operand names. */
14737 static const struct asm_shift_name shift_names
[] =
14739 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
14740 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
14741 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
14742 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
14743 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
14744 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
14747 /* Table of all explicit relocation names. */
14749 static struct reloc_entry reloc_names
[] =
14751 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
14752 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
14753 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
14754 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
14755 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
14756 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
14757 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
14758 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
14759 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
14760 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
14761 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
14765 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
14766 static const struct asm_cond conds
[] =
14770 {"cs", 0x2}, {"hs", 0x2},
14771 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
14785 static struct asm_barrier_opt barrier_opt_names
[] =
14793 /* Table of ARM-format instructions. */
14795 /* Macros for gluing together operand strings. N.B. In all cases
14796 other than OPS0, the trailing OP_stop comes from default
14797 zero-initialization of the unspecified elements of the array. */
14798 #define OPS0() { OP_stop, }
14799 #define OPS1(a) { OP_##a, }
14800 #define OPS2(a,b) { OP_##a,OP_##b, }
14801 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
14802 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
14803 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
14804 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
14806 /* These macros abstract out the exact format of the mnemonic table and
14807 save some repeated characters. */
14809 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
14810 #define TxCE(mnem, op, top, nops, ops, ae, te) \
14811 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
14812 THUMB_VARIANT, do_##ae, do_##te }
14814 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
14815 a T_MNEM_xyz enumerator. */
14816 #define TCE(mnem, aop, top, nops, ops, ae, te) \
14817 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
14818 #define tCE(mnem, aop, top, nops, ops, ae, te) \
14819 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14821 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
14822 infix after the third character. */
14823 #define TxC3(mnem, op, top, nops, ops, ae, te) \
14824 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
14825 THUMB_VARIANT, do_##ae, do_##te }
14826 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
14827 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
14828 THUMB_VARIANT, do_##ae, do_##te }
14829 #define TC3(mnem, aop, top, nops, ops, ae, te) \
14830 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
14831 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
14832 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
14833 #define tC3(mnem, aop, top, nops, ops, ae, te) \
14834 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14835 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
14836 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14838 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
14839 appear in the condition table. */
14840 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
14841 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14842 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
14844 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
14845 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
14846 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
14847 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
14848 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
14849 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
14850 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
14851 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
14852 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
14853 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
14854 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
14855 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
14856 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
14857 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
14858 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
14859 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
14860 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
14861 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
14862 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
14863 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
14865 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
14866 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
14867 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
14868 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
14870 /* Mnemonic that cannot be conditionalized. The ARM condition-code
14871 field is still 0xE. Many of the Thumb variants can be executed
14872 conditionally, so this is checked separately. */
14873 #define TUE(mnem, op, top, nops, ops, ae, te) \
14874 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
14875 THUMB_VARIANT, do_##ae, do_##te }
14877 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
14878 condition code field. */
14879 #define TUF(mnem, op, top, nops, ops, ae, te) \
14880 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
14881 THUMB_VARIANT, do_##ae, do_##te }
14883 /* ARM-only variants of all the above. */
14884 #define CE(mnem, op, nops, ops, ae) \
14885 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14887 #define C3(mnem, op, nops, ops, ae) \
14888 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14890 /* Legacy mnemonics that always have conditional infix after the third
14892 #define CL(mnem, op, nops, ops, ae) \
14893 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14894 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14896 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
14897 #define cCE(mnem, op, nops, ops, ae) \
14898 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14900 /* Legacy coprocessor instructions where conditional infix and conditional
14901 suffix are ambiguous. For consistency this includes all FPA instructions,
14902 not just the potentially ambiguous ones. */
14903 #define cCL(mnem, op, nops, ops, ae) \
14904 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14905 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14907 /* Coprocessor, takes either a suffix or a position-3 infix
14908 (for an FPA corner case). */
14909 #define C3E(mnem, op, nops, ops, ae) \
14910 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
14911 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14913 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
14914 { #m1 #m2 #m3, OPS##nops ops, \
14915 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14916 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14918 #define CM(m1, m2, op, nops, ops, ae) \
14919 xCM_(m1, , m2, op, nops, ops, ae), \
14920 xCM_(m1, eq, m2, op, nops, ops, ae), \
14921 xCM_(m1, ne, m2, op, nops, ops, ae), \
14922 xCM_(m1, cs, m2, op, nops, ops, ae), \
14923 xCM_(m1, hs, m2, op, nops, ops, ae), \
14924 xCM_(m1, cc, m2, op, nops, ops, ae), \
14925 xCM_(m1, ul, m2, op, nops, ops, ae), \
14926 xCM_(m1, lo, m2, op, nops, ops, ae), \
14927 xCM_(m1, mi, m2, op, nops, ops, ae), \
14928 xCM_(m1, pl, m2, op, nops, ops, ae), \
14929 xCM_(m1, vs, m2, op, nops, ops, ae), \
14930 xCM_(m1, vc, m2, op, nops, ops, ae), \
14931 xCM_(m1, hi, m2, op, nops, ops, ae), \
14932 xCM_(m1, ls, m2, op, nops, ops, ae), \
14933 xCM_(m1, ge, m2, op, nops, ops, ae), \
14934 xCM_(m1, lt, m2, op, nops, ops, ae), \
14935 xCM_(m1, gt, m2, op, nops, ops, ae), \
14936 xCM_(m1, le, m2, op, nops, ops, ae), \
14937 xCM_(m1, al, m2, op, nops, ops, ae)
14939 #define UE(mnem, op, nops, ops, ae) \
14940 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14942 #define UF(mnem, op, nops, ops, ae) \
14943 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14945 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
14946 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
14947 use the same encoding function for each. */
14948 #define NUF(mnem, op, nops, ops, enc) \
14949 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
14950 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14952 /* Neon data processing, version which indirects through neon_enc_tab for
14953 the various overloaded versions of opcodes. */
14954 #define nUF(mnem, op, nops, ops, enc) \
14955 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \
14956 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14958 /* Neon insn with conditional suffix for the ARM version, non-overloaded
14960 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
14961 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
14962 THUMB_VARIANT, do_##enc, do_##enc }
14964 #define NCE(mnem, op, nops, ops, enc) \
14965 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14967 #define NCEF(mnem, op, nops, ops, enc) \
14968 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14970 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
14971 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
14972 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \
14973 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14975 #define nCE(mnem, op, nops, ops, enc) \
14976 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14978 #define nCEF(mnem, op, nops, ops, enc) \
14979 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14983 /* Thumb-only, unconditional. */
14984 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
14986 static const struct asm_opcode insns
[] =
14988 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
14989 #define THUMB_VARIANT &arm_ext_v4t
14990 tCE(and, 0000000, and, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14991 tC3(ands
, 0100000, ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14992 tCE(eor
, 0200000, eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14993 tC3(eors
, 0300000, eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14994 tCE(sub
, 0400000, sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14995 tC3(subs
, 0500000, subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14996 tCE(add
, 0800000, add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14997 tC3(adds
, 0900000, adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14998 tCE(adc
, 0a00000
, adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14999 tC3(adcs
, 0b00000, adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15000 tCE(sbc
, 0c00000
, sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
15001 tC3(sbcs
, 0d00000
, sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
15002 tCE(orr
, 1800000, orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15003 tC3(orrs
, 1900000, orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15004 tCE(bic
, 1c00000
, bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
15005 tC3(bics
, 1d00000
, bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
15007 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
15008 for setting PSR flag bits. They are obsolete in V6 and do not
15009 have Thumb equivalents. */
15010 tCE(tst
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15011 tC3w(tsts
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15012 CL(tstp
, 110f000
, 2, (RR
, SH
), cmp
),
15013 tCE(cmp
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
15014 tC3w(cmps
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
15015 CL(cmpp
, 150f000
, 2, (RR
, SH
), cmp
),
15016 tCE(cmn
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15017 tC3w(cmns
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15018 CL(cmnp
, 170f000
, 2, (RR
, SH
), cmp
),
15020 tCE(mov
, 1a00000
, mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
15021 tC3(movs
, 1b00000
, movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
15022 tCE(mvn
, 1e00000
, mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
15023 tC3(mvns
, 1f00000
, mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
15025 tCE(ldr
, 4100000, ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
15026 tC3(ldrb
, 4500000, ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
15027 tCE(str
, 4000000, str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
15028 tC3(strb
, 4400000, strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
15030 tCE(stm
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15031 tC3(stmia
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15032 tC3(stmea
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15033 tCE(ldm
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15034 tC3(ldmia
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15035 tC3(ldmfd
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15037 TCE(swi
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
15038 TCE(svc
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
15039 tCE(b
, a000000
, b
, 1, (EXPr
), branch
, t_branch
),
15040 TCE(bl
, b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
15043 tCE(adr
, 28f0000
, adr
, 2, (RR
, EXP
), adr
, t_adr
),
15044 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
15045 tCE(nop
, 1a00000
, nop
, 1, (oI255c
), nop
, t_nop
),
15047 /* Thumb-compatibility pseudo ops. */
15048 tCE(lsl
, 1a00000
, lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15049 tC3(lsls
, 1b00000
, lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15050 tCE(lsr
, 1a00020
, lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15051 tC3(lsrs
, 1b00020
, lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15052 tCE(asr
, 1a00040
, asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15053 tC3(asrs
, 1b00040
, asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15054 tCE(ror
, 1a00060
, ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15055 tC3(rors
, 1b00060
, rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15056 tCE(neg
, 2600000, neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
15057 tC3(negs
, 2700000, negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
15058 tCE(push
, 92d0000
, push
, 1, (REGLST
), push_pop
, t_push_pop
),
15059 tCE(pop
, 8bd0000
, pop
, 1, (REGLST
), push_pop
, t_push_pop
),
15061 /* These may simplify to neg. */
15062 TCE(rsb
, 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
15063 TC3(rsbs
, 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
15065 #undef THUMB_VARIANT
15066 #define THUMB_VARIANT &arm_ext_v6
15067 TCE(cpy
, 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
15069 /* V1 instructions with no Thumb analogue prior to V6T2. */
15070 #undef THUMB_VARIANT
15071 #define THUMB_VARIANT &arm_ext_v6t2
15072 TCE(teq
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15073 TC3w(teqs
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15074 CL(teqp
, 130f000
, 2, (RR
, SH
), cmp
),
15076 TC3(ldrt
, 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
15077 TC3(ldrbt
, 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
15078 TC3(strt
, 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
15079 TC3(strbt
, 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
15081 TC3(stmdb
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15082 TC3(stmfd
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15084 TC3(ldmdb
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15085 TC3(ldmea
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15087 /* V1 instructions with no Thumb analogue at all. */
15088 CE(rsc
, 0e00000
, 3, (RR
, oRR
, SH
), arit
),
15089 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
15091 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
15092 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
15093 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
15094 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
15095 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
15096 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
15097 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
15098 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
15101 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
15102 #undef THUMB_VARIANT
15103 #define THUMB_VARIANT &arm_ext_v4t
15104 tCE(mul
, 0000090, mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
15105 tC3(muls
, 0100090, muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
15107 #undef THUMB_VARIANT
15108 #define THUMB_VARIANT &arm_ext_v6t2
15109 TCE(mla
, 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
15110 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
15112 /* Generic coprocessor instructions. */
15113 TCE(cdp
, e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
15114 TCE(ldc
, c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15115 TC3(ldcl
, c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15116 TCE(stc
, c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15117 TC3(stcl
, c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15118 TCE(mcr
, e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15119 TCE(mrc
, e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15122 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
15123 CE(swp
, 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
15124 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
15127 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
15128 #undef THUMB_VARIANT
15129 #define THUMB_VARIANT &arm_ext_msr
15130 TCE(mrs
, 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
15131 TCE(msr
, 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
15134 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
15135 #undef THUMB_VARIANT
15136 #define THUMB_VARIANT &arm_ext_v6t2
15137 TCE(smull
, 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15138 CM(smull
,s
, 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15139 TCE(umull
, 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15140 CM(umull
,s
, 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15141 TCE(smlal
, 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15142 CM(smlal
,s
, 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15143 TCE(umlal
, 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15144 CM(umlal
,s
, 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15147 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
15148 #undef THUMB_VARIANT
15149 #define THUMB_VARIANT &arm_ext_v4t
15150 tC3(ldrh
, 01000b0
, ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15151 tC3(strh
, 00000b0
, strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15152 tC3(ldrsh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15153 tC3(ldrsb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15154 tCM(ld
,sh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15155 tCM(ld
,sb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15158 #define ARM_VARIANT &arm_ext_v4t_5
15159 /* ARM Architecture 4T. */
15160 /* Note: bx (and blx) are required on V5, even if the processor does
15161 not support Thumb. */
15162 TCE(bx
, 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
15165 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
15166 #undef THUMB_VARIANT
15167 #define THUMB_VARIANT &arm_ext_v5t
15168 /* Note: blx has 2 variants; the .value coded here is for
15169 BLX(2). Only this variant has conditional execution. */
15170 TCE(blx
, 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
15171 TUE(bkpt
, 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
15173 #undef THUMB_VARIANT
15174 #define THUMB_VARIANT &arm_ext_v6t2
15175 TCE(clz
, 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
15176 TUF(ldc2
, c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15177 TUF(ldc2l
, c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15178 TUF(stc2
, c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15179 TUF(stc2l
, c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15180 TUF(cdp2
, e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
15181 TUF(mcr2
, e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15182 TUF(mrc2
, e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15185 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
15186 TCE(smlabb
, 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15187 TCE(smlatb
, 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15188 TCE(smlabt
, 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15189 TCE(smlatt
, 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15191 TCE(smlawb
, 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15192 TCE(smlawt
, 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15194 TCE(smlalbb
, 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15195 TCE(smlaltb
, 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15196 TCE(smlalbt
, 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15197 TCE(smlaltt
, 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15199 TCE(smulbb
, 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15200 TCE(smultb
, 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15201 TCE(smulbt
, 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15202 TCE(smultt
, 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15204 TCE(smulwb
, 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15205 TCE(smulwt
, 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15207 TCE(qadd
, 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15208 TCE(qdadd
, 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15209 TCE(qsub
, 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15210 TCE(qdsub
, 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15213 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
15214 TUF(pld
, 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
15215 TC3(ldrd
, 00000d0
, e8500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
15216 TC3(strd
, 00000f0
, e8400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
15218 TCE(mcrr
, c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15219 TCE(mrrc
, c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15222 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
15223 TCE(bxj
, 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
15226 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
15227 #undef THUMB_VARIANT
15228 #define THUMB_VARIANT &arm_ext_v6
15229 TUF(cpsie
, 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
15230 TUF(cpsid
, 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
15231 tCE(rev
, 6bf0f30
, rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15232 tCE(rev16
, 6bf0fb0
, rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15233 tCE(revsh
, 6ff0fb0
, revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15234 tCE(sxth
, 6bf0070
, sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15235 tCE(uxth
, 6ff0070
, uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15236 tCE(sxtb
, 6af0070
, sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15237 tCE(uxtb
, 6ef0070
, uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15238 TUF(setend
, 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
15240 #undef THUMB_VARIANT
15241 #define THUMB_VARIANT &arm_ext_v6t2
15242 TCE(ldrex
, 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
15243 TCE(strex
, 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
15244 TUF(mcrr2
, c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15245 TUF(mrrc2
, c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15247 TCE(ssat
, 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
15248 TCE(usat
, 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
15250 /* ARM V6 not included in V7M (eg. integer SIMD). */
15251 #undef THUMB_VARIANT
15252 #define THUMB_VARIANT &arm_ext_v6_notm
15253 TUF(cps
, 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
15254 TCE(pkhbt
, 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
15255 TCE(pkhtb
, 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
15256 TCE(qadd16
, 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15257 TCE(qadd8
, 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15258 TCE(qaddsubx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15259 TCE(qsub16
, 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15260 TCE(qsub8
, 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15261 TCE(qsubaddx
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15262 TCE(sadd16
, 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15263 TCE(sadd8
, 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15264 TCE(saddsubx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15265 TCE(shadd16
, 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15266 TCE(shadd8
, 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15267 TCE(shaddsubx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15268 TCE(shsub16
, 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15269 TCE(shsub8
, 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15270 TCE(shsubaddx
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15271 TCE(ssub16
, 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15272 TCE(ssub8
, 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15273 TCE(ssubaddx
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15274 TCE(uadd16
, 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15275 TCE(uadd8
, 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15276 TCE(uaddsubx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15277 TCE(uhadd16
, 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15278 TCE(uhadd8
, 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15279 TCE(uhaddsubx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15280 TCE(uhsub16
, 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15281 TCE(uhsub8
, 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15282 TCE(uhsubaddx
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15283 TCE(uqadd16
, 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15284 TCE(uqadd8
, 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15285 TCE(uqaddsubx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15286 TCE(uqsub16
, 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15287 TCE(uqsub8
, 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15288 TCE(uqsubaddx
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15289 TCE(usub16
, 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15290 TCE(usub8
, 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15291 TCE(usubaddx
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15292 TUF(rfeia
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
15293 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
15294 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
15295 TUF(rfedb
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
15296 TUF(rfefd
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
15297 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
15298 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
15299 TUF(rfeed
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
15300 TCE(sxtah
, 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15301 TCE(sxtab16
, 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15302 TCE(sxtab
, 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15303 TCE(sxtb16
, 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15304 TCE(uxtah
, 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15305 TCE(uxtab16
, 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15306 TCE(uxtab
, 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15307 TCE(uxtb16
, 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15308 TCE(sel
, 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15309 TCE(smlad
, 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15310 TCE(smladx
, 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15311 TCE(smlald
, 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15312 TCE(smlaldx
, 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15313 TCE(smlsd
, 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15314 TCE(smlsdx
, 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15315 TCE(smlsld
, 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15316 TCE(smlsldx
, 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15317 TCE(smmla
, 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15318 TCE(smmlar
, 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15319 TCE(smmls
, 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15320 TCE(smmlsr
, 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15321 TCE(smmul
, 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15322 TCE(smmulr
, 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15323 TCE(smuad
, 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15324 TCE(smuadx
, 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15325 TCE(smusd
, 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15326 TCE(smusdx
, 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15327 TUF(srsia
, 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
15328 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
15329 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
15330 TUF(srsdb
, 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
15331 TCE(ssat16
, 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
15332 TCE(umaal
, 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
15333 TCE(usad8
, 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15334 TCE(usada8
, 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15335 TCE(usat16
, 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
15338 #define ARM_VARIANT &arm_ext_v6k
15339 #undef THUMB_VARIANT
15340 #define THUMB_VARIANT &arm_ext_v6k
15341 tCE(yield
, 320f001
, yield
, 0, (), noargs
, t_hint
),
15342 tCE(wfe
, 320f002
, wfe
, 0, (), noargs
, t_hint
),
15343 tCE(wfi
, 320f003
, wfi
, 0, (), noargs
, t_hint
),
15344 tCE(sev
, 320f004
, sev
, 0, (), noargs
, t_hint
),
15346 #undef THUMB_VARIANT
15347 #define THUMB_VARIANT &arm_ext_v6_notm
15348 TCE(ldrexd
, 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
15349 TCE(strexd
, 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
15351 #undef THUMB_VARIANT
15352 #define THUMB_VARIANT &arm_ext_v6t2
15353 TCE(ldrexb
, 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
15354 TCE(ldrexh
, 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
15355 TCE(strexb
, 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
15356 TCE(strexh
, 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
15357 TUF(clrex
, 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
15360 #define ARM_VARIANT &arm_ext_v6z
15361 TCE(smc
, 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
15364 #define ARM_VARIANT &arm_ext_v6t2
15365 TCE(bfc
, 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
15366 TCE(bfi
, 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
15367 TCE(sbfx
, 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
15368 TCE(ubfx
, 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
15370 TCE(mls
, 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
15371 TCE(movw
, 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
15372 TCE(movt
, 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
15373 TCE(rbit
, 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
15375 TC3(ldrht
, 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15376 TC3(ldrsht
, 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15377 TC3(ldrsbt
, 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15378 TC3(strht
, 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15380 UT(cbnz
, b900
, 2, (RR
, EXP
), t_cbz
),
15381 UT(cbz
, b100
, 2, (RR
, EXP
), t_cbz
),
15382 /* ARM does not really have an IT instruction, so always allow it. */
15384 #define ARM_VARIANT &arm_ext_v1
15385 TUE(it
, 0, bf08
, 1, (COND
), it
, t_it
),
15386 TUE(itt
, 0, bf0c
, 1, (COND
), it
, t_it
),
15387 TUE(ite
, 0, bf04
, 1, (COND
), it
, t_it
),
15388 TUE(ittt
, 0, bf0e
, 1, (COND
), it
, t_it
),
15389 TUE(itet
, 0, bf06
, 1, (COND
), it
, t_it
),
15390 TUE(itte
, 0, bf0a
, 1, (COND
), it
, t_it
),
15391 TUE(itee
, 0, bf02
, 1, (COND
), it
, t_it
),
15392 TUE(itttt
, 0, bf0f
, 1, (COND
), it
, t_it
),
15393 TUE(itett
, 0, bf07
, 1, (COND
), it
, t_it
),
15394 TUE(ittet
, 0, bf0b
, 1, (COND
), it
, t_it
),
15395 TUE(iteet
, 0, bf03
, 1, (COND
), it
, t_it
),
15396 TUE(ittte
, 0, bf0d
, 1, (COND
), it
, t_it
),
15397 TUE(itete
, 0, bf05
, 1, (COND
), it
, t_it
),
15398 TUE(ittee
, 0, bf09
, 1, (COND
), it
, t_it
),
15399 TUE(iteee
, 0, bf01
, 1, (COND
), it
, t_it
),
15401 /* Thumb2 only instructions. */
15403 #define ARM_VARIANT NULL
15405 TCE(addw
, 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
15406 TCE(subw
, 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
15407 TCE(tbb
, 0, e8d0f000
, 1, (TB
), 0, t_tb
),
15408 TCE(tbh
, 0, e8d0f010
, 1, (TB
), 0, t_tb
),
15410 /* Thumb-2 hardware division instructions (R and M profiles only). */
15411 #undef THUMB_VARIANT
15412 #define THUMB_VARIANT &arm_ext_div
15413 TCE(sdiv
, 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
15414 TCE(udiv
, 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
15416 /* ARM V6M/V7 instructions. */
15418 #define ARM_VARIANT &arm_ext_barrier
15419 #undef THUMB_VARIANT
15420 #define THUMB_VARIANT &arm_ext_barrier
15421 TUF(dmb
, 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
15422 TUF(dsb
, 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
15423 TUF(isb
, 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
15425 /* ARM V7 instructions. */
15427 #define ARM_VARIANT &arm_ext_v7
15428 #undef THUMB_VARIANT
15429 #define THUMB_VARIANT &arm_ext_v7
15430 TUF(pli
, 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
15431 TCE(dbg
, 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
15434 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
15435 cCE(wfs
, e200110
, 1, (RR
), rd
),
15436 cCE(rfs
, e300110
, 1, (RR
), rd
),
15437 cCE(wfc
, e400110
, 1, (RR
), rd
),
15438 cCE(rfc
, e500110
, 1, (RR
), rd
),
15440 cCL(ldfs
, c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15441 cCL(ldfd
, c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15442 cCL(ldfe
, c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15443 cCL(ldfp
, c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15445 cCL(stfs
, c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15446 cCL(stfd
, c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15447 cCL(stfe
, c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15448 cCL(stfp
, c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15450 cCL(mvfs
, e008100
, 2, (RF
, RF_IF
), rd_rm
),
15451 cCL(mvfsp
, e008120
, 2, (RF
, RF_IF
), rd_rm
),
15452 cCL(mvfsm
, e008140
, 2, (RF
, RF_IF
), rd_rm
),
15453 cCL(mvfsz
, e008160
, 2, (RF
, RF_IF
), rd_rm
),
15454 cCL(mvfd
, e008180
, 2, (RF
, RF_IF
), rd_rm
),
15455 cCL(mvfdp
, e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
15456 cCL(mvfdm
, e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
15457 cCL(mvfdz
, e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
15458 cCL(mvfe
, e088100
, 2, (RF
, RF_IF
), rd_rm
),
15459 cCL(mvfep
, e088120
, 2, (RF
, RF_IF
), rd_rm
),
15460 cCL(mvfem
, e088140
, 2, (RF
, RF_IF
), rd_rm
),
15461 cCL(mvfez
, e088160
, 2, (RF
, RF_IF
), rd_rm
),
15463 cCL(mnfs
, e108100
, 2, (RF
, RF_IF
), rd_rm
),
15464 cCL(mnfsp
, e108120
, 2, (RF
, RF_IF
), rd_rm
),
15465 cCL(mnfsm
, e108140
, 2, (RF
, RF_IF
), rd_rm
),
15466 cCL(mnfsz
, e108160
, 2, (RF
, RF_IF
), rd_rm
),
15467 cCL(mnfd
, e108180
, 2, (RF
, RF_IF
), rd_rm
),
15468 cCL(mnfdp
, e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
15469 cCL(mnfdm
, e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
15470 cCL(mnfdz
, e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
15471 cCL(mnfe
, e188100
, 2, (RF
, RF_IF
), rd_rm
),
15472 cCL(mnfep
, e188120
, 2, (RF
, RF_IF
), rd_rm
),
15473 cCL(mnfem
, e188140
, 2, (RF
, RF_IF
), rd_rm
),
15474 cCL(mnfez
, e188160
, 2, (RF
, RF_IF
), rd_rm
),
15476 cCL(abss
, e208100
, 2, (RF
, RF_IF
), rd_rm
),
15477 cCL(abssp
, e208120
, 2, (RF
, RF_IF
), rd_rm
),
15478 cCL(abssm
, e208140
, 2, (RF
, RF_IF
), rd_rm
),
15479 cCL(abssz
, e208160
, 2, (RF
, RF_IF
), rd_rm
),
15480 cCL(absd
, e208180
, 2, (RF
, RF_IF
), rd_rm
),
15481 cCL(absdp
, e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
15482 cCL(absdm
, e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
15483 cCL(absdz
, e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
15484 cCL(abse
, e288100
, 2, (RF
, RF_IF
), rd_rm
),
15485 cCL(absep
, e288120
, 2, (RF
, RF_IF
), rd_rm
),
15486 cCL(absem
, e288140
, 2, (RF
, RF_IF
), rd_rm
),
15487 cCL(absez
, e288160
, 2, (RF
, RF_IF
), rd_rm
),
15489 cCL(rnds
, e308100
, 2, (RF
, RF_IF
), rd_rm
),
15490 cCL(rndsp
, e308120
, 2, (RF
, RF_IF
), rd_rm
),
15491 cCL(rndsm
, e308140
, 2, (RF
, RF_IF
), rd_rm
),
15492 cCL(rndsz
, e308160
, 2, (RF
, RF_IF
), rd_rm
),
15493 cCL(rndd
, e308180
, 2, (RF
, RF_IF
), rd_rm
),
15494 cCL(rnddp
, e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
15495 cCL(rnddm
, e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
15496 cCL(rnddz
, e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
15497 cCL(rnde
, e388100
, 2, (RF
, RF_IF
), rd_rm
),
15498 cCL(rndep
, e388120
, 2, (RF
, RF_IF
), rd_rm
),
15499 cCL(rndem
, e388140
, 2, (RF
, RF_IF
), rd_rm
),
15500 cCL(rndez
, e388160
, 2, (RF
, RF_IF
), rd_rm
),
15502 cCL(sqts
, e408100
, 2, (RF
, RF_IF
), rd_rm
),
15503 cCL(sqtsp
, e408120
, 2, (RF
, RF_IF
), rd_rm
),
15504 cCL(sqtsm
, e408140
, 2, (RF
, RF_IF
), rd_rm
),
15505 cCL(sqtsz
, e408160
, 2, (RF
, RF_IF
), rd_rm
),
15506 cCL(sqtd
, e408180
, 2, (RF
, RF_IF
), rd_rm
),
15507 cCL(sqtdp
, e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
15508 cCL(sqtdm
, e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
15509 cCL(sqtdz
, e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
15510 cCL(sqte
, e488100
, 2, (RF
, RF_IF
), rd_rm
),
15511 cCL(sqtep
, e488120
, 2, (RF
, RF_IF
), rd_rm
),
15512 cCL(sqtem
, e488140
, 2, (RF
, RF_IF
), rd_rm
),
15513 cCL(sqtez
, e488160
, 2, (RF
, RF_IF
), rd_rm
),
15515 cCL(logs
, e508100
, 2, (RF
, RF_IF
), rd_rm
),
15516 cCL(logsp
, e508120
, 2, (RF
, RF_IF
), rd_rm
),
15517 cCL(logsm
, e508140
, 2, (RF
, RF_IF
), rd_rm
),
15518 cCL(logsz
, e508160
, 2, (RF
, RF_IF
), rd_rm
),
15519 cCL(logd
, e508180
, 2, (RF
, RF_IF
), rd_rm
),
15520 cCL(logdp
, e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
15521 cCL(logdm
, e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
15522 cCL(logdz
, e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
15523 cCL(loge
, e588100
, 2, (RF
, RF_IF
), rd_rm
),
15524 cCL(logep
, e588120
, 2, (RF
, RF_IF
), rd_rm
),
15525 cCL(logem
, e588140
, 2, (RF
, RF_IF
), rd_rm
),
15526 cCL(logez
, e588160
, 2, (RF
, RF_IF
), rd_rm
),
15528 cCL(lgns
, e608100
, 2, (RF
, RF_IF
), rd_rm
),
15529 cCL(lgnsp
, e608120
, 2, (RF
, RF_IF
), rd_rm
),
15530 cCL(lgnsm
, e608140
, 2, (RF
, RF_IF
), rd_rm
),
15531 cCL(lgnsz
, e608160
, 2, (RF
, RF_IF
), rd_rm
),
15532 cCL(lgnd
, e608180
, 2, (RF
, RF_IF
), rd_rm
),
15533 cCL(lgndp
, e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
15534 cCL(lgndm
, e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
15535 cCL(lgndz
, e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
15536 cCL(lgne
, e688100
, 2, (RF
, RF_IF
), rd_rm
),
15537 cCL(lgnep
, e688120
, 2, (RF
, RF_IF
), rd_rm
),
15538 cCL(lgnem
, e688140
, 2, (RF
, RF_IF
), rd_rm
),
15539 cCL(lgnez
, e688160
, 2, (RF
, RF_IF
), rd_rm
),
15541 cCL(exps
, e708100
, 2, (RF
, RF_IF
), rd_rm
),
15542 cCL(expsp
, e708120
, 2, (RF
, RF_IF
), rd_rm
),
15543 cCL(expsm
, e708140
, 2, (RF
, RF_IF
), rd_rm
),
15544 cCL(expsz
, e708160
, 2, (RF
, RF_IF
), rd_rm
),
15545 cCL(expd
, e708180
, 2, (RF
, RF_IF
), rd_rm
),
15546 cCL(expdp
, e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
15547 cCL(expdm
, e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
15548 cCL(expdz
, e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
15549 cCL(expe
, e788100
, 2, (RF
, RF_IF
), rd_rm
),
15550 cCL(expep
, e788120
, 2, (RF
, RF_IF
), rd_rm
),
15551 cCL(expem
, e788140
, 2, (RF
, RF_IF
), rd_rm
),
15552 cCL(expdz
, e788160
, 2, (RF
, RF_IF
), rd_rm
),
15554 cCL(sins
, e808100
, 2, (RF
, RF_IF
), rd_rm
),
15555 cCL(sinsp
, e808120
, 2, (RF
, RF_IF
), rd_rm
),
15556 cCL(sinsm
, e808140
, 2, (RF
, RF_IF
), rd_rm
),
15557 cCL(sinsz
, e808160
, 2, (RF
, RF_IF
), rd_rm
),
15558 cCL(sind
, e808180
, 2, (RF
, RF_IF
), rd_rm
),
15559 cCL(sindp
, e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
15560 cCL(sindm
, e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
15561 cCL(sindz
, e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
15562 cCL(sine
, e888100
, 2, (RF
, RF_IF
), rd_rm
),
15563 cCL(sinep
, e888120
, 2, (RF
, RF_IF
), rd_rm
),
15564 cCL(sinem
, e888140
, 2, (RF
, RF_IF
), rd_rm
),
15565 cCL(sinez
, e888160
, 2, (RF
, RF_IF
), rd_rm
),
15567 cCL(coss
, e908100
, 2, (RF
, RF_IF
), rd_rm
),
15568 cCL(cossp
, e908120
, 2, (RF
, RF_IF
), rd_rm
),
15569 cCL(cossm
, e908140
, 2, (RF
, RF_IF
), rd_rm
),
15570 cCL(cossz
, e908160
, 2, (RF
, RF_IF
), rd_rm
),
15571 cCL(cosd
, e908180
, 2, (RF
, RF_IF
), rd_rm
),
15572 cCL(cosdp
, e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
15573 cCL(cosdm
, e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
15574 cCL(cosdz
, e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
15575 cCL(cose
, e988100
, 2, (RF
, RF_IF
), rd_rm
),
15576 cCL(cosep
, e988120
, 2, (RF
, RF_IF
), rd_rm
),
15577 cCL(cosem
, e988140
, 2, (RF
, RF_IF
), rd_rm
),
15578 cCL(cosez
, e988160
, 2, (RF
, RF_IF
), rd_rm
),
15580 cCL(tans
, ea08100
, 2, (RF
, RF_IF
), rd_rm
),
15581 cCL(tansp
, ea08120
, 2, (RF
, RF_IF
), rd_rm
),
15582 cCL(tansm
, ea08140
, 2, (RF
, RF_IF
), rd_rm
),
15583 cCL(tansz
, ea08160
, 2, (RF
, RF_IF
), rd_rm
),
15584 cCL(tand
, ea08180
, 2, (RF
, RF_IF
), rd_rm
),
15585 cCL(tandp
, ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
15586 cCL(tandm
, ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
15587 cCL(tandz
, ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
15588 cCL(tane
, ea88100
, 2, (RF
, RF_IF
), rd_rm
),
15589 cCL(tanep
, ea88120
, 2, (RF
, RF_IF
), rd_rm
),
15590 cCL(tanem
, ea88140
, 2, (RF
, RF_IF
), rd_rm
),
15591 cCL(tanez
, ea88160
, 2, (RF
, RF_IF
), rd_rm
),
15593 cCL(asns
, eb08100
, 2, (RF
, RF_IF
), rd_rm
),
15594 cCL(asnsp
, eb08120
, 2, (RF
, RF_IF
), rd_rm
),
15595 cCL(asnsm
, eb08140
, 2, (RF
, RF_IF
), rd_rm
),
15596 cCL(asnsz
, eb08160
, 2, (RF
, RF_IF
), rd_rm
),
15597 cCL(asnd
, eb08180
, 2, (RF
, RF_IF
), rd_rm
),
15598 cCL(asndp
, eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
15599 cCL(asndm
, eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
15600 cCL(asndz
, eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
15601 cCL(asne
, eb88100
, 2, (RF
, RF_IF
), rd_rm
),
15602 cCL(asnep
, eb88120
, 2, (RF
, RF_IF
), rd_rm
),
15603 cCL(asnem
, eb88140
, 2, (RF
, RF_IF
), rd_rm
),
15604 cCL(asnez
, eb88160
, 2, (RF
, RF_IF
), rd_rm
),
15606 cCL(acss
, ec08100
, 2, (RF
, RF_IF
), rd_rm
),
15607 cCL(acssp
, ec08120
, 2, (RF
, RF_IF
), rd_rm
),
15608 cCL(acssm
, ec08140
, 2, (RF
, RF_IF
), rd_rm
),
15609 cCL(acssz
, ec08160
, 2, (RF
, RF_IF
), rd_rm
),
15610 cCL(acsd
, ec08180
, 2, (RF
, RF_IF
), rd_rm
),
15611 cCL(acsdp
, ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
15612 cCL(acsdm
, ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
15613 cCL(acsdz
, ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
15614 cCL(acse
, ec88100
, 2, (RF
, RF_IF
), rd_rm
),
15615 cCL(acsep
, ec88120
, 2, (RF
, RF_IF
), rd_rm
),
15616 cCL(acsem
, ec88140
, 2, (RF
, RF_IF
), rd_rm
),
15617 cCL(acsez
, ec88160
, 2, (RF
, RF_IF
), rd_rm
),
15619 cCL(atns
, ed08100
, 2, (RF
, RF_IF
), rd_rm
),
15620 cCL(atnsp
, ed08120
, 2, (RF
, RF_IF
), rd_rm
),
15621 cCL(atnsm
, ed08140
, 2, (RF
, RF_IF
), rd_rm
),
15622 cCL(atnsz
, ed08160
, 2, (RF
, RF_IF
), rd_rm
),
15623 cCL(atnd
, ed08180
, 2, (RF
, RF_IF
), rd_rm
),
15624 cCL(atndp
, ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
15625 cCL(atndm
, ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
15626 cCL(atndz
, ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
15627 cCL(atne
, ed88100
, 2, (RF
, RF_IF
), rd_rm
),
15628 cCL(atnep
, ed88120
, 2, (RF
, RF_IF
), rd_rm
),
15629 cCL(atnem
, ed88140
, 2, (RF
, RF_IF
), rd_rm
),
15630 cCL(atnez
, ed88160
, 2, (RF
, RF_IF
), rd_rm
),
15632 cCL(urds
, ee08100
, 2, (RF
, RF_IF
), rd_rm
),
15633 cCL(urdsp
, ee08120
, 2, (RF
, RF_IF
), rd_rm
),
15634 cCL(urdsm
, ee08140
, 2, (RF
, RF_IF
), rd_rm
),
15635 cCL(urdsz
, ee08160
, 2, (RF
, RF_IF
), rd_rm
),
15636 cCL(urdd
, ee08180
, 2, (RF
, RF_IF
), rd_rm
),
15637 cCL(urddp
, ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
15638 cCL(urddm
, ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
15639 cCL(urddz
, ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
15640 cCL(urde
, ee88100
, 2, (RF
, RF_IF
), rd_rm
),
15641 cCL(urdep
, ee88120
, 2, (RF
, RF_IF
), rd_rm
),
15642 cCL(urdem
, ee88140
, 2, (RF
, RF_IF
), rd_rm
),
15643 cCL(urdez
, ee88160
, 2, (RF
, RF_IF
), rd_rm
),
15645 cCL(nrms
, ef08100
, 2, (RF
, RF_IF
), rd_rm
),
15646 cCL(nrmsp
, ef08120
, 2, (RF
, RF_IF
), rd_rm
),
15647 cCL(nrmsm
, ef08140
, 2, (RF
, RF_IF
), rd_rm
),
15648 cCL(nrmsz
, ef08160
, 2, (RF
, RF_IF
), rd_rm
),
15649 cCL(nrmd
, ef08180
, 2, (RF
, RF_IF
), rd_rm
),
15650 cCL(nrmdp
, ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
15651 cCL(nrmdm
, ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
15652 cCL(nrmdz
, ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
15653 cCL(nrme
, ef88100
, 2, (RF
, RF_IF
), rd_rm
),
15654 cCL(nrmep
, ef88120
, 2, (RF
, RF_IF
), rd_rm
),
15655 cCL(nrmem
, ef88140
, 2, (RF
, RF_IF
), rd_rm
),
15656 cCL(nrmez
, ef88160
, 2, (RF
, RF_IF
), rd_rm
),
15658 cCL(adfs
, e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15659 cCL(adfsp
, e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15660 cCL(adfsm
, e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15661 cCL(adfsz
, e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15662 cCL(adfd
, e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15663 cCL(adfdp
, e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15664 cCL(adfdm
, e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15665 cCL(adfdz
, e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15666 cCL(adfe
, e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15667 cCL(adfep
, e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15668 cCL(adfem
, e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15669 cCL(adfez
, e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15671 cCL(sufs
, e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15672 cCL(sufsp
, e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15673 cCL(sufsm
, e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15674 cCL(sufsz
, e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15675 cCL(sufd
, e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15676 cCL(sufdp
, e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15677 cCL(sufdm
, e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15678 cCL(sufdz
, e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15679 cCL(sufe
, e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15680 cCL(sufep
, e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15681 cCL(sufem
, e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15682 cCL(sufez
, e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15684 cCL(rsfs
, e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15685 cCL(rsfsp
, e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15686 cCL(rsfsm
, e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15687 cCL(rsfsz
, e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15688 cCL(rsfd
, e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15689 cCL(rsfdp
, e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15690 cCL(rsfdm
, e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15691 cCL(rsfdz
, e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15692 cCL(rsfe
, e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15693 cCL(rsfep
, e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15694 cCL(rsfem
, e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15695 cCL(rsfez
, e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15697 cCL(mufs
, e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15698 cCL(mufsp
, e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15699 cCL(mufsm
, e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15700 cCL(mufsz
, e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15701 cCL(mufd
, e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15702 cCL(mufdp
, e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15703 cCL(mufdm
, e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15704 cCL(mufdz
, e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15705 cCL(mufe
, e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15706 cCL(mufep
, e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15707 cCL(mufem
, e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15708 cCL(mufez
, e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15710 cCL(dvfs
, e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15711 cCL(dvfsp
, e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15712 cCL(dvfsm
, e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15713 cCL(dvfsz
, e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15714 cCL(dvfd
, e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15715 cCL(dvfdp
, e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15716 cCL(dvfdm
, e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15717 cCL(dvfdz
, e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15718 cCL(dvfe
, e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15719 cCL(dvfep
, e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15720 cCL(dvfem
, e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15721 cCL(dvfez
, e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15723 cCL(rdfs
, e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15724 cCL(rdfsp
, e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15725 cCL(rdfsm
, e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15726 cCL(rdfsz
, e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15727 cCL(rdfd
, e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15728 cCL(rdfdp
, e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15729 cCL(rdfdm
, e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15730 cCL(rdfdz
, e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15731 cCL(rdfe
, e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15732 cCL(rdfep
, e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15733 cCL(rdfem
, e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15734 cCL(rdfez
, e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15736 cCL(pows
, e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15737 cCL(powsp
, e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15738 cCL(powsm
, e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15739 cCL(powsz
, e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15740 cCL(powd
, e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15741 cCL(powdp
, e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15742 cCL(powdm
, e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15743 cCL(powdz
, e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15744 cCL(powe
, e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15745 cCL(powep
, e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15746 cCL(powem
, e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15747 cCL(powez
, e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15749 cCL(rpws
, e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15750 cCL(rpwsp
, e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15751 cCL(rpwsm
, e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15752 cCL(rpwsz
, e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15753 cCL(rpwd
, e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15754 cCL(rpwdp
, e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15755 cCL(rpwdm
, e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15756 cCL(rpwdz
, e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15757 cCL(rpwe
, e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15758 cCL(rpwep
, e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15759 cCL(rpwem
, e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15760 cCL(rpwez
, e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15762 cCL(rmfs
, e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15763 cCL(rmfsp
, e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15764 cCL(rmfsm
, e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15765 cCL(rmfsz
, e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15766 cCL(rmfd
, e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15767 cCL(rmfdp
, e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15768 cCL(rmfdm
, e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15769 cCL(rmfdz
, e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15770 cCL(rmfe
, e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15771 cCL(rmfep
, e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15772 cCL(rmfem
, e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15773 cCL(rmfez
, e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15775 cCL(fmls
, e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15776 cCL(fmlsp
, e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15777 cCL(fmlsm
, e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15778 cCL(fmlsz
, e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15779 cCL(fmld
, e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15780 cCL(fmldp
, e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15781 cCL(fmldm
, e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15782 cCL(fmldz
, e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15783 cCL(fmle
, e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15784 cCL(fmlep
, e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15785 cCL(fmlem
, e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15786 cCL(fmlez
, e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15788 cCL(fdvs
, ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15789 cCL(fdvsp
, ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15790 cCL(fdvsm
, ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15791 cCL(fdvsz
, ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15792 cCL(fdvd
, ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15793 cCL(fdvdp
, ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15794 cCL(fdvdm
, ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15795 cCL(fdvdz
, ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15796 cCL(fdve
, ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15797 cCL(fdvep
, ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15798 cCL(fdvem
, ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15799 cCL(fdvez
, ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15801 cCL(frds
, eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15802 cCL(frdsp
, eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15803 cCL(frdsm
, eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15804 cCL(frdsz
, eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15805 cCL(frdd
, eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15806 cCL(frddp
, eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15807 cCL(frddm
, eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15808 cCL(frddz
, eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15809 cCL(frde
, eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15810 cCL(frdep
, eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15811 cCL(frdem
, eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15812 cCL(frdez
, eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15814 cCL(pols
, ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15815 cCL(polsp
, ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15816 cCL(polsm
, ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15817 cCL(polsz
, ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15818 cCL(pold
, ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15819 cCL(poldp
, ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15820 cCL(poldm
, ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15821 cCL(poldz
, ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15822 cCL(pole
, ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15823 cCL(polep
, ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15824 cCL(polem
, ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15825 cCL(polez
, ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15827 cCE(cmf
, e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15828 C3E(cmfe
, ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15829 cCE(cnf
, eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15830 C3E(cnfe
, ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15832 cCL(flts
, e000110
, 2, (RF
, RR
), rn_rd
),
15833 cCL(fltsp
, e000130
, 2, (RF
, RR
), rn_rd
),
15834 cCL(fltsm
, e000150
, 2, (RF
, RR
), rn_rd
),
15835 cCL(fltsz
, e000170
, 2, (RF
, RR
), rn_rd
),
15836 cCL(fltd
, e000190
, 2, (RF
, RR
), rn_rd
),
15837 cCL(fltdp
, e0001b0
, 2, (RF
, RR
), rn_rd
),
15838 cCL(fltdm
, e0001d0
, 2, (RF
, RR
), rn_rd
),
15839 cCL(fltdz
, e0001f0
, 2, (RF
, RR
), rn_rd
),
15840 cCL(flte
, e080110
, 2, (RF
, RR
), rn_rd
),
15841 cCL(fltep
, e080130
, 2, (RF
, RR
), rn_rd
),
15842 cCL(fltem
, e080150
, 2, (RF
, RR
), rn_rd
),
15843 cCL(fltez
, e080170
, 2, (RF
, RR
), rn_rd
),
15845 /* The implementation of the FIX instruction is broken on some
15846 assemblers, in that it accepts a precision specifier as well as a
15847 rounding specifier, despite the fact that this is meaningless.
15848 To be more compatible, we accept it as well, though of course it
15849 does not set any bits. */
15850 cCE(fix
, e100110
, 2, (RR
, RF
), rd_rm
),
15851 cCL(fixp
, e100130
, 2, (RR
, RF
), rd_rm
),
15852 cCL(fixm
, e100150
, 2, (RR
, RF
), rd_rm
),
15853 cCL(fixz
, e100170
, 2, (RR
, RF
), rd_rm
),
15854 cCL(fixsp
, e100130
, 2, (RR
, RF
), rd_rm
),
15855 cCL(fixsm
, e100150
, 2, (RR
, RF
), rd_rm
),
15856 cCL(fixsz
, e100170
, 2, (RR
, RF
), rd_rm
),
15857 cCL(fixdp
, e100130
, 2, (RR
, RF
), rd_rm
),
15858 cCL(fixdm
, e100150
, 2, (RR
, RF
), rd_rm
),
15859 cCL(fixdz
, e100170
, 2, (RR
, RF
), rd_rm
),
15860 cCL(fixep
, e100130
, 2, (RR
, RF
), rd_rm
),
15861 cCL(fixem
, e100150
, 2, (RR
, RF
), rd_rm
),
15862 cCL(fixez
, e100170
, 2, (RR
, RF
), rd_rm
),
15864 /* Instructions that were new with the real FPA, call them V2. */
15866 #define ARM_VARIANT &fpu_fpa_ext_v2
15867 cCE(lfm
, c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15868 cCL(lfmfd
, c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15869 cCL(lfmea
, d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15870 cCE(sfm
, c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15871 cCL(sfmfd
, d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15872 cCL(sfmea
, c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15875 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
15876 /* Moves and type conversions. */
15877 cCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15878 cCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
15879 cCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
15880 cCE(fmstat
, ef1fa10
, 0, (), noargs
),
15881 cCE(fsitos
, eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15882 cCE(fuitos
, eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15883 cCE(ftosis
, ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15884 cCE(ftosizs
, ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15885 cCE(ftouis
, ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15886 cCE(ftouizs
, ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15887 cCE(fmrx
, ef00a10
, 2, (RR
, RVC
), rd_rn
),
15888 cCE(fmxr
, ee00a10
, 2, (RVC
, RR
), rn_rd
),
15890 /* Memory operations. */
15891 cCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15892 cCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15893 cCE(fldmias
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15894 cCE(fldmfds
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15895 cCE(fldmdbs
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15896 cCE(fldmeas
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15897 cCE(fldmiax
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15898 cCE(fldmfdx
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15899 cCE(fldmdbx
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15900 cCE(fldmeax
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15901 cCE(fstmias
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15902 cCE(fstmeas
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15903 cCE(fstmdbs
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15904 cCE(fstmfds
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15905 cCE(fstmiax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15906 cCE(fstmeax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15907 cCE(fstmdbx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15908 cCE(fstmfdx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15910 /* Monadic operations. */
15911 cCE(fabss
, eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15912 cCE(fnegs
, eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15913 cCE(fsqrts
, eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15915 /* Dyadic operations. */
15916 cCE(fadds
, e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15917 cCE(fsubs
, e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15918 cCE(fmuls
, e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15919 cCE(fdivs
, e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15920 cCE(fmacs
, e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15921 cCE(fmscs
, e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15922 cCE(fnmuls
, e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15923 cCE(fnmacs
, e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15924 cCE(fnmscs
, e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15927 cCE(fcmps
, eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15928 cCE(fcmpzs
, eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
15929 cCE(fcmpes
, eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15930 cCE(fcmpezs
, eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
15933 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
15934 /* Moves and type conversions. */
15935 cCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15936 cCE(fcvtds
, eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15937 cCE(fcvtsd
, eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15938 cCE(fmdhr
, e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15939 cCE(fmdlr
, e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15940 cCE(fmrdh
, e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15941 cCE(fmrdl
, e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15942 cCE(fsitod
, eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15943 cCE(fuitod
, eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15944 cCE(ftosid
, ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15945 cCE(ftosizd
, ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15946 cCE(ftouid
, ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15947 cCE(ftouizd
, ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15949 /* Memory operations. */
15950 cCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15951 cCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15952 cCE(fldmiad
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15953 cCE(fldmfdd
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15954 cCE(fldmdbd
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15955 cCE(fldmead
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15956 cCE(fstmiad
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15957 cCE(fstmead
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15958 cCE(fstmdbd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15959 cCE(fstmfdd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15961 /* Monadic operations. */
15962 cCE(fabsd
, eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15963 cCE(fnegd
, eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15964 cCE(fsqrtd
, eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15966 /* Dyadic operations. */
15967 cCE(faddd
, e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15968 cCE(fsubd
, e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15969 cCE(fmuld
, e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15970 cCE(fdivd
, e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15971 cCE(fmacd
, e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15972 cCE(fmscd
, e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15973 cCE(fnmuld
, e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15974 cCE(fnmacd
, e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15975 cCE(fnmscd
, e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15978 cCE(fcmpd
, eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15979 cCE(fcmpzd
, eb50b40
, 1, (RVD
), vfp_dp_rd
),
15980 cCE(fcmped
, eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15981 cCE(fcmpezd
, eb50bc0
, 1, (RVD
), vfp_dp_rd
),
15984 #define ARM_VARIANT &fpu_vfp_ext_v2
15985 cCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
15986 cCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
15987 cCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
15988 cCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
15990 /* Instructions which may belong to either the Neon or VFP instruction sets.
15991 Individual encoder functions perform additional architecture checks. */
15993 #define ARM_VARIANT &fpu_vfp_ext_v1xd
15994 #undef THUMB_VARIANT
15995 #define THUMB_VARIANT &fpu_vfp_ext_v1xd
15996 /* These mnemonics are unique to VFP. */
15997 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
15998 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
15999 nCE(vnmul
, vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
16000 nCE(vnmla
, vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
16001 nCE(vnmls
, vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
16002 nCE(vcmp
, vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
16003 nCE(vcmpe
, vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
16004 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
16005 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
16006 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
16008 /* Mnemonics shared by Neon and VFP. */
16009 nCEF(vmul
, vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
16010 nCEF(vmla
, vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
16011 nCEF(vmls
, vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
16013 nCEF(vadd
, vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
16014 nCEF(vsub
, vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
16016 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
16017 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
16019 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16020 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16021 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16022 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16023 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16024 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16025 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
16026 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
16028 nCEF(vcvt
, vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
16029 nCEF(vcvtb
, vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
16030 nCEF(vcvtt
, vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
16033 /* NOTE: All VMOV encoding is special-cased! */
16034 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
16035 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
16037 #undef THUMB_VARIANT
16038 #define THUMB_VARIANT &fpu_neon_ext_v1
16040 #define ARM_VARIANT &fpu_neon_ext_v1
16041 /* Data processing with three registers of the same length. */
16042 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
16043 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
16044 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
16045 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
16046 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
16047 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
16048 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
16049 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
16050 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
16051 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
16052 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
16053 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
16054 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
16055 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
16056 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
16057 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
16058 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
16059 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
16060 /* If not immediate, fall back to neon_dyadic_i64_su.
16061 shl_imm should accept I8 I16 I32 I64,
16062 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
16063 nUF(vshl
, vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
16064 nUF(vshlq
, vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
16065 nUF(vqshl
, vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
16066 nUF(vqshlq
, vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
16067 /* Logic ops, types optional & ignored. */
16068 nUF(vand
, vand
, 2, (RNDQ
, NILO
), neon_logic
),
16069 nUF(vandq
, vand
, 2, (RNQ
, NILO
), neon_logic
),
16070 nUF(vbic
, vbic
, 2, (RNDQ
, NILO
), neon_logic
),
16071 nUF(vbicq
, vbic
, 2, (RNQ
, NILO
), neon_logic
),
16072 nUF(vorr
, vorr
, 2, (RNDQ
, NILO
), neon_logic
),
16073 nUF(vorrq
, vorr
, 2, (RNQ
, NILO
), neon_logic
),
16074 nUF(vorn
, vorn
, 2, (RNDQ
, NILO
), neon_logic
),
16075 nUF(vornq
, vorn
, 2, (RNQ
, NILO
), neon_logic
),
16076 nUF(veor
, veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
16077 nUF(veorq
, veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
16078 /* Bitfield ops, untyped. */
16079 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
16080 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
16081 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
16082 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
16083 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
16084 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
16085 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
16086 nUF(vabd
, vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
16087 nUF(vabdq
, vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
16088 nUF(vmax
, vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
16089 nUF(vmaxq
, vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
16090 nUF(vmin
, vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
16091 nUF(vminq
, vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
16092 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
16093 back to neon_dyadic_if_su. */
16094 nUF(vcge
, vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
16095 nUF(vcgeq
, vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
16096 nUF(vcgt
, vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
16097 nUF(vcgtq
, vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
16098 nUF(vclt
, vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
16099 nUF(vcltq
, vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
16100 nUF(vcle
, vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
16101 nUF(vcleq
, vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
16102 /* Comparison. Type I8 I16 I32 F32. */
16103 nUF(vceq
, vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
16104 nUF(vceqq
, vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
16105 /* As above, D registers only. */
16106 nUF(vpmax
, vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
16107 nUF(vpmin
, vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
16108 /* Int and float variants, signedness unimportant. */
16109 nUF(vmlaq
, vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
16110 nUF(vmlsq
, vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
16111 nUF(vpadd
, vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
16112 /* Add/sub take types I8 I16 I32 I64 F32. */
16113 nUF(vaddq
, vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
16114 nUF(vsubq
, vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
16115 /* vtst takes sizes 8, 16, 32. */
16116 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
16117 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
16118 /* VMUL takes I8 I16 I32 F32 P8. */
16119 nUF(vmulq
, vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
16120 /* VQD{R}MULH takes S16 S32. */
16121 nUF(vqdmulh
, vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
16122 nUF(vqdmulhq
, vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
16123 nUF(vqrdmulh
, vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
16124 nUF(vqrdmulhq
, vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
16125 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
16126 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
16127 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
16128 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
16129 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
16130 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
16131 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
16132 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
16133 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
16134 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
16135 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
16136 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
16138 /* Two address, int/float. Types S8 S16 S32 F32. */
16139 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
16140 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
16142 /* Data processing with two registers and a shift amount. */
16143 /* Right shifts, and variants with rounding.
16144 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
16145 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
16146 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
16147 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
16148 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
16149 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
16150 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
16151 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
16152 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
16153 /* Shift and insert. Sizes accepted 8 16 32 64. */
16154 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
16155 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
16156 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
16157 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
16158 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
16159 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
16160 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
16161 /* Right shift immediate, saturating & narrowing, with rounding variants.
16162 Types accepted S16 S32 S64 U16 U32 U64. */
16163 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
16164 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
16165 /* As above, unsigned. Types accepted S16 S32 S64. */
16166 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
16167 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
16168 /* Right shift narrowing. Types accepted I16 I32 I64. */
16169 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
16170 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
16171 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
16172 nUF(vshll
, vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
16173 /* CVT with optional immediate for fixed-point variant. */
16174 nUF(vcvtq
, vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
16176 nUF(vmvn
, vmvn
, 2, (RNDQ
, RNDQ_IMVNb
), neon_mvn
),
16177 nUF(vmvnq
, vmvn
, 2, (RNQ
, RNDQ_IMVNb
), neon_mvn
),
16179 /* Data processing, three registers of different lengths. */
16180 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
16181 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
16182 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16183 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16184 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16185 /* If not scalar, fall back to neon_dyadic_long.
16186 Vector types as above, scalar types S16 S32 U16 U32. */
16187 nUF(vmlal
, vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
16188 nUF(vmlsl
, vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
16189 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
16190 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
16191 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
16192 /* Dyadic, narrowing insns. Types I16 I32 I64. */
16193 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16194 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16195 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16196 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16197 /* Saturating doubling multiplies. Types S16 S32. */
16198 nUF(vqdmlal
, vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16199 nUF(vqdmlsl
, vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16200 nUF(vqdmull
, vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16201 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
16202 S16 S32 U16 U32. */
16203 nUF(vmull
, vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
16205 /* Extract. Size 8. */
16206 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
16207 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
16209 /* Two registers, miscellaneous. */
16210 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
16211 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
16212 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
16213 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
16214 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
16215 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
16216 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
16217 /* Vector replicate. Sizes 8 16 32. */
16218 nCE(vdup
, vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
16219 nCE(vdupq
, vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
16220 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
16221 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
16222 /* VMOVN. Types I16 I32 I64. */
16223 nUF(vmovn
, vmovn
, 2, (RND
, RNQ
), neon_movn
),
16224 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
16225 nUF(vqmovn
, vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
16226 /* VQMOVUN. Types S16 S32 S64. */
16227 nUF(vqmovun
, vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
16228 /* VZIP / VUZP. Sizes 8 16 32. */
16229 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
16230 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
16231 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
16232 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
16233 /* VQABS / VQNEG. Types S8 S16 S32. */
16234 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
16235 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
16236 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
16237 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
16238 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
16239 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
16240 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
16241 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
16242 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
16243 /* Reciprocal estimates. Types U32 F32. */
16244 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
16245 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
16246 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
16247 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
16248 /* VCLS. Types S8 S16 S32. */
16249 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
16250 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
16251 /* VCLZ. Types I8 I16 I32. */
16252 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
16253 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
16254 /* VCNT. Size 8. */
16255 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
16256 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
16257 /* Two address, untyped. */
16258 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
16259 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
16260 /* VTRN. Sizes 8 16 32. */
16261 nUF(vtrn
, vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
16262 nUF(vtrnq
, vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
16264 /* Table lookup. Size 8. */
16265 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
16266 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
16268 #undef THUMB_VARIANT
16269 #define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
16271 #define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
16272 /* Neon element/structure load/store. */
16273 nUF(vld1
, vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16274 nUF(vst1
, vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16275 nUF(vld2
, vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16276 nUF(vst2
, vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16277 nUF(vld3
, vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16278 nUF(vst3
, vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16279 nUF(vld4
, vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16280 nUF(vst4
, vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16282 #undef THUMB_VARIANT
16283 #define THUMB_VARIANT &fpu_vfp_ext_v3
16285 #define ARM_VARIANT &fpu_vfp_ext_v3
16286 cCE(fconsts
, eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
16287 cCE(fconstd
, eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
16288 cCE(fshtos
, eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16289 cCE(fshtod
, eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16290 cCE(fsltos
, eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16291 cCE(fsltod
, eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16292 cCE(fuhtos
, ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16293 cCE(fuhtod
, ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16294 cCE(fultos
, ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16295 cCE(fultod
, ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16296 cCE(ftoshs
, ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16297 cCE(ftoshd
, ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16298 cCE(ftosls
, ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16299 cCE(ftosld
, ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16300 cCE(ftouhs
, ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16301 cCE(ftouhd
, ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16302 cCE(ftouls
, ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16303 cCE(ftould
, ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16305 #undef THUMB_VARIANT
16307 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
16308 cCE(mia
, e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16309 cCE(miaph
, e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16310 cCE(miabb
, e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16311 cCE(miabt
, e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16312 cCE(miatb
, e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16313 cCE(miatt
, e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16314 cCE(mar
, c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
16315 cCE(mra
, c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
16318 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
16319 cCE(tandcb
, e13f130
, 1, (RR
), iwmmxt_tandorc
),
16320 cCE(tandch
, e53f130
, 1, (RR
), iwmmxt_tandorc
),
16321 cCE(tandcw
, e93f130
, 1, (RR
), iwmmxt_tandorc
),
16322 cCE(tbcstb
, e400010
, 2, (RIWR
, RR
), rn_rd
),
16323 cCE(tbcsth
, e400050
, 2, (RIWR
, RR
), rn_rd
),
16324 cCE(tbcstw
, e400090
, 2, (RIWR
, RR
), rn_rd
),
16325 cCE(textrcb
, e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
16326 cCE(textrch
, e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
16327 cCE(textrcw
, e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
16328 cCE(textrmub
, e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16329 cCE(textrmuh
, e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16330 cCE(textrmuw
, e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16331 cCE(textrmsb
, e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16332 cCE(textrmsh
, e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16333 cCE(textrmsw
, e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16334 cCE(tinsrb
, e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16335 cCE(tinsrh
, e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16336 cCE(tinsrw
, e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16337 cCE(tmcr
, e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
16338 cCE(tmcrr
, c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
16339 cCE(tmia
, e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16340 cCE(tmiaph
, e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16341 cCE(tmiabb
, e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16342 cCE(tmiabt
, e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16343 cCE(tmiatb
, e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16344 cCE(tmiatt
, e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16345 cCE(tmovmskb
, e100030
, 2, (RR
, RIWR
), rd_rn
),
16346 cCE(tmovmskh
, e500030
, 2, (RR
, RIWR
), rd_rn
),
16347 cCE(tmovmskw
, e900030
, 2, (RR
, RIWR
), rd_rn
),
16348 cCE(tmrc
, e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
16349 cCE(tmrrc
, c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
16350 cCE(torcb
, e13f150
, 1, (RR
), iwmmxt_tandorc
),
16351 cCE(torch
, e53f150
, 1, (RR
), iwmmxt_tandorc
),
16352 cCE(torcw
, e93f150
, 1, (RR
), iwmmxt_tandorc
),
16353 cCE(waccb
, e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16354 cCE(wacch
, e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16355 cCE(waccw
, e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16356 cCE(waddbss
, e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16357 cCE(waddb
, e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16358 cCE(waddbus
, e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16359 cCE(waddhss
, e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16360 cCE(waddh
, e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16361 cCE(waddhus
, e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16362 cCE(waddwss
, eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16363 cCE(waddw
, e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16364 cCE(waddwus
, e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16365 cCE(waligni
, e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
16366 cCE(walignr0
, e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16367 cCE(walignr1
, e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16368 cCE(walignr2
, ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16369 cCE(walignr3
, eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16370 cCE(wand
, e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16371 cCE(wandn
, e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16372 cCE(wavg2b
, e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16373 cCE(wavg2br
, e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16374 cCE(wavg2h
, ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16375 cCE(wavg2hr
, ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16376 cCE(wcmpeqb
, e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16377 cCE(wcmpeqh
, e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16378 cCE(wcmpeqw
, e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16379 cCE(wcmpgtub
, e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16380 cCE(wcmpgtuh
, e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16381 cCE(wcmpgtuw
, e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16382 cCE(wcmpgtsb
, e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16383 cCE(wcmpgtsh
, e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16384 cCE(wcmpgtsw
, eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16385 cCE(wldrb
, c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16386 cCE(wldrh
, c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16387 cCE(wldrw
, c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
16388 cCE(wldrd
, c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
16389 cCE(wmacs
, e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16390 cCE(wmacsz
, e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16391 cCE(wmacu
, e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16392 cCE(wmacuz
, e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16393 cCE(wmadds
, ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16394 cCE(wmaddu
, e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16395 cCE(wmaxsb
, e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16396 cCE(wmaxsh
, e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16397 cCE(wmaxsw
, ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16398 cCE(wmaxub
, e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16399 cCE(wmaxuh
, e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16400 cCE(wmaxuw
, e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16401 cCE(wminsb
, e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16402 cCE(wminsh
, e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16403 cCE(wminsw
, eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16404 cCE(wminub
, e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16405 cCE(wminuh
, e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16406 cCE(wminuw
, e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16407 cCE(wmov
, e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
16408 cCE(wmulsm
, e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16409 cCE(wmulsl
, e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16410 cCE(wmulum
, e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16411 cCE(wmulul
, e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16412 cCE(wor
, e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16413 cCE(wpackhss
, e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16414 cCE(wpackhus
, e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16415 cCE(wpackwss
, eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16416 cCE(wpackwus
, e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16417 cCE(wpackdss
, ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16418 cCE(wpackdus
, ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16419 cCE(wrorh
, e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16420 cCE(wrorhg
, e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16421 cCE(wrorw
, eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16422 cCE(wrorwg
, eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16423 cCE(wrord
, ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16424 cCE(wrordg
, ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16425 cCE(wsadb
, e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16426 cCE(wsadbz
, e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16427 cCE(wsadh
, e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16428 cCE(wsadhz
, e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16429 cCE(wshufh
, e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
16430 cCE(wsllh
, e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16431 cCE(wsllhg
, e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16432 cCE(wsllw
, e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16433 cCE(wsllwg
, e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16434 cCE(wslld
, ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16435 cCE(wslldg
, ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16436 cCE(wsrah
, e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16437 cCE(wsrahg
, e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16438 cCE(wsraw
, e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16439 cCE(wsrawg
, e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16440 cCE(wsrad
, ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16441 cCE(wsradg
, ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16442 cCE(wsrlh
, e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16443 cCE(wsrlhg
, e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16444 cCE(wsrlw
, ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16445 cCE(wsrlwg
, ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16446 cCE(wsrld
, ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16447 cCE(wsrldg
, ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16448 cCE(wstrb
, c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16449 cCE(wstrh
, c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16450 cCE(wstrw
, c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
16451 cCE(wstrd
, c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
16452 cCE(wsubbss
, e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16453 cCE(wsubb
, e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16454 cCE(wsubbus
, e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16455 cCE(wsubhss
, e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16456 cCE(wsubh
, e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16457 cCE(wsubhus
, e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16458 cCE(wsubwss
, eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16459 cCE(wsubw
, e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16460 cCE(wsubwus
, e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16461 cCE(wunpckehub
,e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16462 cCE(wunpckehuh
,e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16463 cCE(wunpckehuw
,e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16464 cCE(wunpckehsb
,e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16465 cCE(wunpckehsh
,e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16466 cCE(wunpckehsw
,ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16467 cCE(wunpckihb
, e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16468 cCE(wunpckihh
, e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16469 cCE(wunpckihw
, e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16470 cCE(wunpckelub
,e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16471 cCE(wunpckeluh
,e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16472 cCE(wunpckeluw
,e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16473 cCE(wunpckelsb
,e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16474 cCE(wunpckelsh
,e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16475 cCE(wunpckelsw
,ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16476 cCE(wunpckilb
, e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16477 cCE(wunpckilh
, e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16478 cCE(wunpckilw
, e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16479 cCE(wxor
, e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16480 cCE(wzero
, e300000
, 1, (RIWR
), iwmmxt_wzero
),
16483 #define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
16484 cCE(torvscb
, e13f190
, 1, (RR
), iwmmxt_tandorc
),
16485 cCE(torvsch
, e53f190
, 1, (RR
), iwmmxt_tandorc
),
16486 cCE(torvscw
, e93f190
, 1, (RR
), iwmmxt_tandorc
),
16487 cCE(wabsb
, e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16488 cCE(wabsh
, e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16489 cCE(wabsw
, ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16490 cCE(wabsdiffb
, e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16491 cCE(wabsdiffh
, e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16492 cCE(wabsdiffw
, e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16493 cCE(waddbhusl
, e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16494 cCE(waddbhusm
, e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16495 cCE(waddhc
, e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16496 cCE(waddwc
, ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16497 cCE(waddsubhx
, ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16498 cCE(wavg4
, e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16499 cCE(wavg4r
, e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16500 cCE(wmaddsn
, ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16501 cCE(wmaddsx
, eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16502 cCE(wmaddun
, ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16503 cCE(wmaddux
, e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16504 cCE(wmerge
, e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
16505 cCE(wmiabb
, e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16506 cCE(wmiabt
, e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16507 cCE(wmiatb
, e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16508 cCE(wmiatt
, e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16509 cCE(wmiabbn
, e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16510 cCE(wmiabtn
, e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16511 cCE(wmiatbn
, e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16512 cCE(wmiattn
, e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16513 cCE(wmiawbb
, e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16514 cCE(wmiawbt
, e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16515 cCE(wmiawtb
, ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16516 cCE(wmiawtt
, eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16517 cCE(wmiawbbn
, ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16518 cCE(wmiawbtn
, ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16519 cCE(wmiawtbn
, ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16520 cCE(wmiawttn
, ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16521 cCE(wmulsmr
, ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16522 cCE(wmulumr
, ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16523 cCE(wmulwumr
, ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16524 cCE(wmulwsmr
, ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16525 cCE(wmulwum
, ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16526 cCE(wmulwsm
, ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16527 cCE(wmulwl
, eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16528 cCE(wqmiabb
, e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16529 cCE(wqmiabt
, e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16530 cCE(wqmiatb
, ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16531 cCE(wqmiatt
, eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16532 cCE(wqmiabbn
, ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16533 cCE(wqmiabtn
, ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16534 cCE(wqmiatbn
, ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16535 cCE(wqmiattn
, ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16536 cCE(wqmulm
, e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16537 cCE(wqmulmr
, e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16538 cCE(wqmulwm
, ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16539 cCE(wqmulwmr
, ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16540 cCE(wsubaddhx
, ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16543 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
16544 cCE(cfldrs
, c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
16545 cCE(cfldrd
, c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
16546 cCE(cfldr32
, c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
16547 cCE(cfldr64
, c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
16548 cCE(cfstrs
, c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
16549 cCE(cfstrd
, c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
16550 cCE(cfstr32
, c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
16551 cCE(cfstr64
, c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
16552 cCE(cfmvsr
, e000450
, 2, (RMF
, RR
), rn_rd
),
16553 cCE(cfmvrs
, e100450
, 2, (RR
, RMF
), rd_rn
),
16554 cCE(cfmvdlr
, e000410
, 2, (RMD
, RR
), rn_rd
),
16555 cCE(cfmvrdl
, e100410
, 2, (RR
, RMD
), rd_rn
),
16556 cCE(cfmvdhr
, e000430
, 2, (RMD
, RR
), rn_rd
),
16557 cCE(cfmvrdh
, e100430
, 2, (RR
, RMD
), rd_rn
),
16558 cCE(cfmv64lr
, e000510
, 2, (RMDX
, RR
), rn_rd
),
16559 cCE(cfmvr64l
, e100510
, 2, (RR
, RMDX
), rd_rn
),
16560 cCE(cfmv64hr
, e000530
, 2, (RMDX
, RR
), rn_rd
),
16561 cCE(cfmvr64h
, e100530
, 2, (RR
, RMDX
), rd_rn
),
16562 cCE(cfmval32
, e200440
, 2, (RMAX
, RMFX
), rd_rn
),
16563 cCE(cfmv32al
, e100440
, 2, (RMFX
, RMAX
), rd_rn
),
16564 cCE(cfmvam32
, e200460
, 2, (RMAX
, RMFX
), rd_rn
),
16565 cCE(cfmv32am
, e100460
, 2, (RMFX
, RMAX
), rd_rn
),
16566 cCE(cfmvah32
, e200480
, 2, (RMAX
, RMFX
), rd_rn
),
16567 cCE(cfmv32ah
, e100480
, 2, (RMFX
, RMAX
), rd_rn
),
16568 cCE(cfmva32
, e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
16569 cCE(cfmv32a
, e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
16570 cCE(cfmva64
, e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
16571 cCE(cfmv64a
, e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
16572 cCE(cfmvsc32
, e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
16573 cCE(cfmv32sc
, e1004e0
, 2, (RMDX
, RMDS
), rd
),
16574 cCE(cfcpys
, e000400
, 2, (RMF
, RMF
), rd_rn
),
16575 cCE(cfcpyd
, e000420
, 2, (RMD
, RMD
), rd_rn
),
16576 cCE(cfcvtsd
, e000460
, 2, (RMD
, RMF
), rd_rn
),
16577 cCE(cfcvtds
, e000440
, 2, (RMF
, RMD
), rd_rn
),
16578 cCE(cfcvt32s
, e000480
, 2, (RMF
, RMFX
), rd_rn
),
16579 cCE(cfcvt32d
, e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
16580 cCE(cfcvt64s
, e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
16581 cCE(cfcvt64d
, e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
16582 cCE(cfcvts32
, e100580
, 2, (RMFX
, RMF
), rd_rn
),
16583 cCE(cfcvtd32
, e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
16584 cCE(cftruncs32
,e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
16585 cCE(cftruncd32
,e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
16586 cCE(cfrshl32
, e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
16587 cCE(cfrshl64
, e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
16588 cCE(cfsh32
, e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
16589 cCE(cfsh64
, e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
16590 cCE(cfcmps
, e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
16591 cCE(cfcmpd
, e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
16592 cCE(cfcmp32
, e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
16593 cCE(cfcmp64
, e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
16594 cCE(cfabss
, e300400
, 2, (RMF
, RMF
), rd_rn
),
16595 cCE(cfabsd
, e300420
, 2, (RMD
, RMD
), rd_rn
),
16596 cCE(cfnegs
, e300440
, 2, (RMF
, RMF
), rd_rn
),
16597 cCE(cfnegd
, e300460
, 2, (RMD
, RMD
), rd_rn
),
16598 cCE(cfadds
, e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16599 cCE(cfaddd
, e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16600 cCE(cfsubs
, e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16601 cCE(cfsubd
, e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16602 cCE(cfmuls
, e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16603 cCE(cfmuld
, e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16604 cCE(cfabs32
, e300500
, 2, (RMFX
, RMFX
), rd_rn
),
16605 cCE(cfabs64
, e300520
, 2, (RMDX
, RMDX
), rd_rn
),
16606 cCE(cfneg32
, e300540
, 2, (RMFX
, RMFX
), rd_rn
),
16607 cCE(cfneg64
, e300560
, 2, (RMDX
, RMDX
), rd_rn
),
16608 cCE(cfadd32
, e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16609 cCE(cfadd64
, e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16610 cCE(cfsub32
, e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16611 cCE(cfsub64
, e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16612 cCE(cfmul32
, e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16613 cCE(cfmul64
, e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16614 cCE(cfmac32
, e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16615 cCE(cfmsc32
, e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16616 cCE(cfmadd32
, e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
16617 cCE(cfmsub32
, e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
16618 cCE(cfmadda32
, e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
16619 cCE(cfmsuba32
, e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
16622 #undef THUMB_VARIANT
16649 /* MD interface: bits in the object file. */
16651 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
16652 for use in the a.out file, and stores them in the array pointed to by buf.
16653 This knows about the endian-ness of the target machine and does
16654 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
16655 2 (short) and 4 (long) Floating numbers are put out as a series of
16656 LITTLENUMS (shorts, here at least). */
16659 md_number_to_chars (char * buf
, valueT val
, int n
)
16661 if (target_big_endian
)
16662 number_to_chars_bigendian (buf
, val
, n
);
16664 number_to_chars_littleendian (buf
, val
, n
);
16668 md_chars_to_number (char * buf
, int n
)
16671 unsigned char * where
= (unsigned char *) buf
;
16673 if (target_big_endian
)
16678 result
|= (*where
++ & 255);
16686 result
|= (where
[n
] & 255);
16693 /* MD interface: Sections. */
16695 /* Estimate the size of a frag before relaxing. Assume everything fits in
16699 md_estimate_size_before_relax (fragS
* fragp
,
16700 segT segtype ATTRIBUTE_UNUSED
)
16706 /* Convert a machine dependent frag. */
16709 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
16711 unsigned long insn
;
16712 unsigned long old_op
;
16720 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16722 old_op
= bfd_get_16(abfd
, buf
);
16723 if (fragp
->fr_symbol
)
16725 exp
.X_op
= O_symbol
;
16726 exp
.X_add_symbol
= fragp
->fr_symbol
;
16730 exp
.X_op
= O_constant
;
16732 exp
.X_add_number
= fragp
->fr_offset
;
16733 opcode
= fragp
->fr_subtype
;
16736 case T_MNEM_ldr_pc
:
16737 case T_MNEM_ldr_pc2
:
16738 case T_MNEM_ldr_sp
:
16739 case T_MNEM_str_sp
:
16746 if (fragp
->fr_var
== 4)
16748 insn
= THUMB_OP32 (opcode
);
16749 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
16751 insn
|= (old_op
& 0x700) << 4;
16755 insn
|= (old_op
& 7) << 12;
16756 insn
|= (old_op
& 0x38) << 13;
16758 insn
|= 0x00000c00;
16759 put_thumb32_insn (buf
, insn
);
16760 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
16764 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
16766 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
16769 if (fragp
->fr_var
== 4)
16771 insn
= THUMB_OP32 (opcode
);
16772 insn
|= (old_op
& 0xf0) << 4;
16773 put_thumb32_insn (buf
, insn
);
16774 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
16778 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16779 exp
.X_add_number
-= 4;
16787 if (fragp
->fr_var
== 4)
16789 int r0off
= (opcode
== T_MNEM_mov
16790 || opcode
== T_MNEM_movs
) ? 0 : 8;
16791 insn
= THUMB_OP32 (opcode
);
16792 insn
= (insn
& 0xe1ffffff) | 0x10000000;
16793 insn
|= (old_op
& 0x700) << r0off
;
16794 put_thumb32_insn (buf
, insn
);
16795 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16799 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
16804 if (fragp
->fr_var
== 4)
16806 insn
= THUMB_OP32(opcode
);
16807 put_thumb32_insn (buf
, insn
);
16808 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
16811 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
16815 if (fragp
->fr_var
== 4)
16817 insn
= THUMB_OP32(opcode
);
16818 insn
|= (old_op
& 0xf00) << 14;
16819 put_thumb32_insn (buf
, insn
);
16820 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
16823 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
16826 case T_MNEM_add_sp
:
16827 case T_MNEM_add_pc
:
16828 case T_MNEM_inc_sp
:
16829 case T_MNEM_dec_sp
:
16830 if (fragp
->fr_var
== 4)
16832 /* ??? Choose between add and addw. */
16833 insn
= THUMB_OP32 (opcode
);
16834 insn
|= (old_op
& 0xf0) << 4;
16835 put_thumb32_insn (buf
, insn
);
16836 if (opcode
== T_MNEM_add_pc
)
16837 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
16839 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16842 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16850 if (fragp
->fr_var
== 4)
16852 insn
= THUMB_OP32 (opcode
);
16853 insn
|= (old_op
& 0xf0) << 4;
16854 insn
|= (old_op
& 0xf) << 16;
16855 put_thumb32_insn (buf
, insn
);
16856 if (insn
& (1 << 20))
16857 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16859 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16862 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16868 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
16870 fixp
->fx_file
= fragp
->fr_file
;
16871 fixp
->fx_line
= fragp
->fr_line
;
16872 fragp
->fr_fix
+= fragp
->fr_var
;
16875 /* Return the size of a relaxable immediate operand instruction.
16876 SHIFT and SIZE specify the form of the allowable immediate. */
16878 relax_immediate (fragS
*fragp
, int size
, int shift
)
16884 /* ??? Should be able to do better than this. */
16885 if (fragp
->fr_symbol
)
16888 low
= (1 << shift
) - 1;
16889 mask
= (1 << (shift
+ size
)) - (1 << shift
);
16890 offset
= fragp
->fr_offset
;
16891 /* Force misaligned offsets to 32-bit variant. */
16894 if (offset
& ~mask
)
16899 /* Get the address of a symbol during relaxation. */
16901 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
16907 sym
= fragp
->fr_symbol
;
16908 sym_frag
= symbol_get_frag (sym
);
16909 know (S_GET_SEGMENT (sym
) != absolute_section
16910 || sym_frag
== &zero_address_frag
);
16911 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
16913 /* If frag has yet to be reached on this pass, assume it will
16914 move by STRETCH just as we did. If this is not so, it will
16915 be because some frag between grows, and that will force
16919 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
16923 /* Adjust stretch for any alignment frag. Note that if have
16924 been expanding the earlier code, the symbol may be
16925 defined in what appears to be an earlier frag. FIXME:
16926 This doesn't handle the fr_subtype field, which specifies
16927 a maximum number of bytes to skip when doing an
16929 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
16931 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
16934 stretch
= - ((- stretch
)
16935 & ~ ((1 << (int) f
->fr_offset
) - 1));
16937 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
16949 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
16952 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
16957 /* Assume worst case for symbols not known to be in the same section. */
16958 if (!S_IS_DEFINED (fragp
->fr_symbol
)
16959 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16962 val
= relaxed_symbol_addr (fragp
, stretch
);
16963 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16964 addr
= (addr
+ 4) & ~3;
16965 /* Force misaligned targets to 32-bit variant. */
16969 if (val
< 0 || val
> 1020)
16974 /* Return the size of a relaxable add/sub immediate instruction. */
16976 relax_addsub (fragS
*fragp
, asection
*sec
)
16981 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16982 op
= bfd_get_16(sec
->owner
, buf
);
16983 if ((op
& 0xf) == ((op
>> 4) & 0xf))
16984 return relax_immediate (fragp
, 8, 0);
16986 return relax_immediate (fragp
, 3, 0);
16990 /* Return the size of a relaxable branch instruction. BITS is the
16991 size of the offset field in the narrow instruction. */
16994 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
17000 /* Assume worst case for symbols not known to be in the same section. */
17001 if (!S_IS_DEFINED (fragp
->fr_symbol
)
17002 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
17005 val
= relaxed_symbol_addr (fragp
, stretch
);
17006 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17009 /* Offset is a signed value *2 */
17011 if (val
>= limit
|| val
< -limit
)
17017 /* Relax a machine dependent frag. This returns the amount by which
17018 the current size of the frag should change. */
17021 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
17026 oldsize
= fragp
->fr_var
;
17027 switch (fragp
->fr_subtype
)
17029 case T_MNEM_ldr_pc2
:
17030 newsize
= relax_adr (fragp
, sec
, stretch
);
17032 case T_MNEM_ldr_pc
:
17033 case T_MNEM_ldr_sp
:
17034 case T_MNEM_str_sp
:
17035 newsize
= relax_immediate (fragp
, 8, 2);
17039 newsize
= relax_immediate (fragp
, 5, 2);
17043 newsize
= relax_immediate (fragp
, 5, 1);
17047 newsize
= relax_immediate (fragp
, 5, 0);
17050 newsize
= relax_adr (fragp
, sec
, stretch
);
17056 newsize
= relax_immediate (fragp
, 8, 0);
17059 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
17062 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
17064 case T_MNEM_add_sp
:
17065 case T_MNEM_add_pc
:
17066 newsize
= relax_immediate (fragp
, 8, 2);
17068 case T_MNEM_inc_sp
:
17069 case T_MNEM_dec_sp
:
17070 newsize
= relax_immediate (fragp
, 7, 2);
17076 newsize
= relax_addsub (fragp
, sec
);
17082 fragp
->fr_var
= newsize
;
17083 /* Freeze wide instructions that are at or before the same location as
17084 in the previous pass. This avoids infinite loops.
17085 Don't freeze them unconditionally because targets may be artificially
17086 misaligned by the expansion of preceding frags. */
17087 if (stretch
<= 0 && newsize
> 2)
17089 md_convert_frag (sec
->owner
, sec
, fragp
);
17093 return newsize
- oldsize
;
17096 /* Round up a section size to the appropriate boundary. */
17099 md_section_align (segT segment ATTRIBUTE_UNUSED
,
17102 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
17103 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
17105 /* For a.out, force the section size to be aligned. If we don't do
17106 this, BFD will align it for us, but it will not write out the
17107 final bytes of the section. This may be a bug in BFD, but it is
17108 easier to fix it here since that is how the other a.out targets
17112 align
= bfd_get_section_alignment (stdoutput
, segment
);
17113 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
17120 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
17121 of an rs_align_code fragment. */
17124 arm_handle_align (fragS
* fragP
)
17126 static char const arm_noop
[4] = { 0x00, 0x00, 0xa0, 0xe1 };
17127 static char const thumb_noop
[2] = { 0xc0, 0x46 };
17128 static char const arm_bigend_noop
[4] = { 0xe1, 0xa0, 0x00, 0x00 };
17129 static char const thumb_bigend_noop
[2] = { 0x46, 0xc0 };
17131 int bytes
, fix
, noop_size
;
17135 if (fragP
->fr_type
!= rs_align_code
)
17138 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
17139 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
17142 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
17143 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
17145 if (fragP
->tc_frag_data
)
17147 if (target_big_endian
)
17148 noop
= thumb_bigend_noop
;
17151 noop_size
= sizeof (thumb_noop
);
17155 if (target_big_endian
)
17156 noop
= arm_bigend_noop
;
17159 noop_size
= sizeof (arm_noop
);
17162 if (bytes
& (noop_size
- 1))
17164 fix
= bytes
& (noop_size
- 1);
17165 memset (p
, 0, fix
);
17170 while (bytes
>= noop_size
)
17172 memcpy (p
, noop
, noop_size
);
17174 bytes
-= noop_size
;
17178 fragP
->fr_fix
+= fix
;
17179 fragP
->fr_var
= noop_size
;
17182 /* Called from md_do_align. Used to create an alignment
17183 frag in a code section. */
17186 arm_frag_align_code (int n
, int max
)
17190 /* We assume that there will never be a requirement
17191 to support alignments greater than 32 bytes. */
17192 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
17193 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
17195 p
= frag_var (rs_align_code
,
17196 MAX_MEM_FOR_RS_ALIGN_CODE
,
17198 (relax_substateT
) max
,
17205 /* Perform target specific initialisation of a frag. */
17208 arm_init_frag (fragS
* fragP
)
17210 /* Record whether this frag is in an ARM or a THUMB area. */
17211 fragP
->tc_frag_data
= thumb_mode
;
17215 /* When we change sections we need to issue a new mapping symbol. */
17218 arm_elf_change_section (void)
17221 segment_info_type
*seginfo
;
17223 /* Link an unlinked unwind index table section to the .text section. */
17224 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
17225 && elf_linked_to_section (now_seg
) == NULL
)
17226 elf_linked_to_section (now_seg
) = text_section
;
17228 if (!SEG_NORMAL (now_seg
))
17231 flags
= bfd_get_section_flags (stdoutput
, now_seg
);
17233 /* We can ignore sections that only contain debug info. */
17234 if ((flags
& SEC_ALLOC
) == 0)
17237 seginfo
= seg_info (now_seg
);
17238 mapstate
= seginfo
->tc_segment_info_data
.mapstate
;
17239 marked_pr_dependency
= seginfo
->tc_segment_info_data
.marked_pr_dependency
;
17243 arm_elf_section_type (const char * str
, size_t len
)
17245 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
17246 return SHT_ARM_EXIDX
;
17251 /* Code to deal with unwinding tables. */
17253 static void add_unwind_adjustsp (offsetT
);
17255 /* Generate any deferred unwind frame offset. */
17258 flush_pending_unwind (void)
17262 offset
= unwind
.pending_offset
;
17263 unwind
.pending_offset
= 0;
17265 add_unwind_adjustsp (offset
);
17268 /* Add an opcode to this list for this function. Two-byte opcodes should
17269 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
17273 add_unwind_opcode (valueT op
, int length
)
17275 /* Add any deferred stack adjustment. */
17276 if (unwind
.pending_offset
)
17277 flush_pending_unwind ();
17279 unwind
.sp_restored
= 0;
17281 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
17283 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
17284 if (unwind
.opcodes
)
17285 unwind
.opcodes
= xrealloc (unwind
.opcodes
,
17286 unwind
.opcode_alloc
);
17288 unwind
.opcodes
= xmalloc (unwind
.opcode_alloc
);
17293 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
17295 unwind
.opcode_count
++;
17299 /* Add unwind opcodes to adjust the stack pointer. */
17302 add_unwind_adjustsp (offsetT offset
)
17306 if (offset
> 0x200)
17308 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
17313 /* Long form: 0xb2, uleb128. */
17314 /* This might not fit in a word so add the individual bytes,
17315 remembering the list is built in reverse order. */
17316 o
= (valueT
) ((offset
- 0x204) >> 2);
17318 add_unwind_opcode (0, 1);
17320 /* Calculate the uleb128 encoding of the offset. */
17324 bytes
[n
] = o
& 0x7f;
17330 /* Add the insn. */
17332 add_unwind_opcode (bytes
[n
- 1], 1);
17333 add_unwind_opcode (0xb2, 1);
17335 else if (offset
> 0x100)
17337 /* Two short opcodes. */
17338 add_unwind_opcode (0x3f, 1);
17339 op
= (offset
- 0x104) >> 2;
17340 add_unwind_opcode (op
, 1);
17342 else if (offset
> 0)
17344 /* Short opcode. */
17345 op
= (offset
- 4) >> 2;
17346 add_unwind_opcode (op
, 1);
17348 else if (offset
< 0)
17351 while (offset
> 0x100)
17353 add_unwind_opcode (0x7f, 1);
17356 op
= ((offset
- 4) >> 2) | 0x40;
17357 add_unwind_opcode (op
, 1);
17361 /* Finish the list of unwind opcodes for this function. */
17363 finish_unwind_opcodes (void)
17367 if (unwind
.fp_used
)
17369 /* Adjust sp as necessary. */
17370 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
17371 flush_pending_unwind ();
17373 /* After restoring sp from the frame pointer. */
17374 op
= 0x90 | unwind
.fp_reg
;
17375 add_unwind_opcode (op
, 1);
17378 flush_pending_unwind ();
17382 /* Start an exception table entry. If idx is nonzero this is an index table
17386 start_unwind_section (const segT text_seg
, int idx
)
17388 const char * text_name
;
17389 const char * prefix
;
17390 const char * prefix_once
;
17391 const char * group_name
;
17395 size_t sec_name_len
;
17402 prefix
= ELF_STRING_ARM_unwind
;
17403 prefix_once
= ELF_STRING_ARM_unwind_once
;
17404 type
= SHT_ARM_EXIDX
;
17408 prefix
= ELF_STRING_ARM_unwind_info
;
17409 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
17410 type
= SHT_PROGBITS
;
17413 text_name
= segment_name (text_seg
);
17414 if (streq (text_name
, ".text"))
17417 if (strncmp (text_name
, ".gnu.linkonce.t.",
17418 strlen (".gnu.linkonce.t.")) == 0)
17420 prefix
= prefix_once
;
17421 text_name
+= strlen (".gnu.linkonce.t.");
17424 prefix_len
= strlen (prefix
);
17425 text_len
= strlen (text_name
);
17426 sec_name_len
= prefix_len
+ text_len
;
17427 sec_name
= xmalloc (sec_name_len
+ 1);
17428 memcpy (sec_name
, prefix
, prefix_len
);
17429 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
17430 sec_name
[prefix_len
+ text_len
] = '\0';
17436 /* Handle COMDAT group. */
17437 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
17439 group_name
= elf_group_name (text_seg
);
17440 if (group_name
== NULL
)
17442 as_bad (_("Group section `%s' has no group signature"),
17443 segment_name (text_seg
));
17444 ignore_rest_of_line ();
17447 flags
|= SHF_GROUP
;
17451 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
17453 /* Set the section link for index tables. */
17455 elf_linked_to_section (now_seg
) = text_seg
;
17459 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
17460 personality routine data. Returns zero, or the index table value for
17461 and inline entry. */
17464 create_unwind_entry (int have_data
)
17469 /* The current word of data. */
17471 /* The number of bytes left in this word. */
17474 finish_unwind_opcodes ();
17476 /* Remember the current text section. */
17477 unwind
.saved_seg
= now_seg
;
17478 unwind
.saved_subseg
= now_subseg
;
17480 start_unwind_section (now_seg
, 0);
17482 if (unwind
.personality_routine
== NULL
)
17484 if (unwind
.personality_index
== -2)
17487 as_bad (_("handlerdata in cantunwind frame"));
17488 return 1; /* EXIDX_CANTUNWIND. */
17491 /* Use a default personality routine if none is specified. */
17492 if (unwind
.personality_index
== -1)
17494 if (unwind
.opcode_count
> 3)
17495 unwind
.personality_index
= 1;
17497 unwind
.personality_index
= 0;
17500 /* Space for the personality routine entry. */
17501 if (unwind
.personality_index
== 0)
17503 if (unwind
.opcode_count
> 3)
17504 as_bad (_("too many unwind opcodes for personality routine 0"));
17508 /* All the data is inline in the index table. */
17511 while (unwind
.opcode_count
> 0)
17513 unwind
.opcode_count
--;
17514 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
17518 /* Pad with "finish" opcodes. */
17520 data
= (data
<< 8) | 0xb0;
17527 /* We get two opcodes "free" in the first word. */
17528 size
= unwind
.opcode_count
- 2;
17531 /* An extra byte is required for the opcode count. */
17532 size
= unwind
.opcode_count
+ 1;
17534 size
= (size
+ 3) >> 2;
17536 as_bad (_("too many unwind opcodes"));
17538 frag_align (2, 0, 0);
17539 record_alignment (now_seg
, 2);
17540 unwind
.table_entry
= expr_build_dot ();
17542 /* Allocate the table entry. */
17543 ptr
= frag_more ((size
<< 2) + 4);
17544 where
= frag_now_fix () - ((size
<< 2) + 4);
17546 switch (unwind
.personality_index
)
17549 /* ??? Should this be a PLT generating relocation? */
17550 /* Custom personality routine. */
17551 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
17552 BFD_RELOC_ARM_PREL31
);
17557 /* Set the first byte to the number of additional words. */
17562 /* ABI defined personality routines. */
17564 /* Three opcodes bytes are packed into the first word. */
17571 /* The size and first two opcode bytes go in the first word. */
17572 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
17577 /* Should never happen. */
17581 /* Pack the opcodes into words (MSB first), reversing the list at the same
17583 while (unwind
.opcode_count
> 0)
17587 md_number_to_chars (ptr
, data
, 4);
17592 unwind
.opcode_count
--;
17594 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
17597 /* Finish off the last word. */
17600 /* Pad with "finish" opcodes. */
17602 data
= (data
<< 8) | 0xb0;
17604 md_number_to_chars (ptr
, data
, 4);
17609 /* Add an empty descriptor if there is no user-specified data. */
17610 ptr
= frag_more (4);
17611 md_number_to_chars (ptr
, 0, 4);
17618 /* Initialize the DWARF-2 unwind information for this procedure. */
17621 tc_arm_frame_initial_instructions (void)
17623 cfi_add_CFA_def_cfa (REG_SP
, 0);
17625 #endif /* OBJ_ELF */
17627 /* Convert REGNAME to a DWARF-2 register number. */
17630 tc_arm_regname_to_dw2regnum (char *regname
)
17632 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
17642 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
17646 expr
.X_op
= O_secrel
;
17647 expr
.X_add_symbol
= symbol
;
17648 expr
.X_add_number
= 0;
17649 emit_expr (&expr
, size
);
17653 /* MD interface: Symbol and relocation handling. */
17655 /* Return the address within the segment that a PC-relative fixup is
17656 relative to. For ARM, PC-relative fixups applied to instructions
17657 are generally relative to the location of the fixup plus 8 bytes.
17658 Thumb branches are offset by 4, and Thumb loads relative to PC
17659 require special handling. */
17662 md_pcrel_from_section (fixS
* fixP
, segT seg
)
17664 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
17666 /* If this is pc-relative and we are going to emit a relocation
17667 then we just want to put out any pipeline compensation that the linker
17668 will need. Otherwise we want to use the calculated base.
17669 For WinCE we skip the bias for externals as well, since this
17670 is how the MS ARM-CE assembler behaves and we want to be compatible. */
17672 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
17673 || (arm_force_relocation (fixP
)
17675 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
17680 switch (fixP
->fx_r_type
)
17682 /* PC relative addressing on the Thumb is slightly odd as the
17683 bottom two bits of the PC are forced to zero for the
17684 calculation. This happens *after* application of the
17685 pipeline offset. However, Thumb adrl already adjusts for
17686 this, so we need not do it again. */
17687 case BFD_RELOC_ARM_THUMB_ADD
:
17690 case BFD_RELOC_ARM_THUMB_OFFSET
:
17691 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
17692 case BFD_RELOC_ARM_T32_ADD_PC12
:
17693 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
17694 return (base
+ 4) & ~3;
17696 /* Thumb branches are simply offset by +4. */
17697 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
17698 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
17699 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
17700 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
17701 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
17702 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
17703 case BFD_RELOC_THUMB_PCREL_BLX
:
17706 /* ARM mode branches are offset by +8. However, the Windows CE
17707 loader expects the relocation not to take this into account. */
17708 case BFD_RELOC_ARM_PCREL_BRANCH
:
17709 case BFD_RELOC_ARM_PCREL_CALL
:
17710 case BFD_RELOC_ARM_PCREL_JUMP
:
17711 case BFD_RELOC_ARM_PCREL_BLX
:
17712 case BFD_RELOC_ARM_PLT32
:
17714 /* When handling fixups immediately, because we have already
17715 discovered the value of a symbol, or the address of the frag involved
17716 we must account for the offset by +8, as the OS loader will never see the reloc.
17717 see fixup_segment() in write.c
17718 The S_IS_EXTERNAL test handles the case of global symbols.
17719 Those need the calculated base, not just the pipe compensation the linker will need. */
17721 && fixP
->fx_addsy
!= NULL
17722 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
17723 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
17730 /* ARM mode loads relative to PC are also offset by +8. Unlike
17731 branches, the Windows CE loader *does* expect the relocation
17732 to take this into account. */
17733 case BFD_RELOC_ARM_OFFSET_IMM
:
17734 case BFD_RELOC_ARM_OFFSET_IMM8
:
17735 case BFD_RELOC_ARM_HWLITERAL
:
17736 case BFD_RELOC_ARM_LITERAL
:
17737 case BFD_RELOC_ARM_CP_OFF_IMM
:
17741 /* Other PC-relative relocations are un-offset. */
17747 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
17748 Otherwise we have no need to default values of symbols. */
17751 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
17754 if (name
[0] == '_' && name
[1] == 'G'
17755 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
17759 if (symbol_find (name
))
17760 as_bad (_("GOT already in the symbol table"));
17762 GOT_symbol
= symbol_new (name
, undefined_section
,
17763 (valueT
) 0, & zero_address_frag
);
17773 /* Subroutine of md_apply_fix. Check to see if an immediate can be
17774 computed as two separate immediate values, added together. We
17775 already know that this value cannot be computed by just one ARM
17778 static unsigned int
17779 validate_immediate_twopart (unsigned int val
,
17780 unsigned int * highpart
)
17785 for (i
= 0; i
< 32; i
+= 2)
17786 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
17792 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
17794 else if (a
& 0xff0000)
17796 if (a
& 0xff000000)
17798 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
17802 assert (a
& 0xff000000);
17803 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
17806 return (a
& 0xff) | (i
<< 7);
17813 validate_offset_imm (unsigned int val
, int hwse
)
17815 if ((hwse
&& val
> 255) || val
> 4095)
17820 /* Subroutine of md_apply_fix. Do those data_ops which can take a
17821 negative immediate constant by altering the instruction. A bit of
17826 by inverting the second operand, and
17829 by negating the second operand. */
17832 negate_data_op (unsigned long * instruction
,
17833 unsigned long value
)
17836 unsigned long negated
, inverted
;
17838 negated
= encode_arm_immediate (-value
);
17839 inverted
= encode_arm_immediate (~value
);
17841 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
17844 /* First negates. */
17845 case OPCODE_SUB
: /* ADD <-> SUB */
17846 new_inst
= OPCODE_ADD
;
17851 new_inst
= OPCODE_SUB
;
17855 case OPCODE_CMP
: /* CMP <-> CMN */
17856 new_inst
= OPCODE_CMN
;
17861 new_inst
= OPCODE_CMP
;
17865 /* Now Inverted ops. */
17866 case OPCODE_MOV
: /* MOV <-> MVN */
17867 new_inst
= OPCODE_MVN
;
17872 new_inst
= OPCODE_MOV
;
17876 case OPCODE_AND
: /* AND <-> BIC */
17877 new_inst
= OPCODE_BIC
;
17882 new_inst
= OPCODE_AND
;
17886 case OPCODE_ADC
: /* ADC <-> SBC */
17887 new_inst
= OPCODE_SBC
;
17892 new_inst
= OPCODE_ADC
;
17896 /* We cannot do anything. */
17901 if (value
== (unsigned) FAIL
)
17904 *instruction
&= OPCODE_MASK
;
17905 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
17909 /* Like negate_data_op, but for Thumb-2. */
17911 static unsigned int
17912 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
17916 unsigned int negated
, inverted
;
17918 negated
= encode_thumb32_immediate (-value
);
17919 inverted
= encode_thumb32_immediate (~value
);
17921 rd
= (*instruction
>> 8) & 0xf;
17922 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
17925 /* ADD <-> SUB. Includes CMP <-> CMN. */
17926 case T2_OPCODE_SUB
:
17927 new_inst
= T2_OPCODE_ADD
;
17931 case T2_OPCODE_ADD
:
17932 new_inst
= T2_OPCODE_SUB
;
17936 /* ORR <-> ORN. Includes MOV <-> MVN. */
17937 case T2_OPCODE_ORR
:
17938 new_inst
= T2_OPCODE_ORN
;
17942 case T2_OPCODE_ORN
:
17943 new_inst
= T2_OPCODE_ORR
;
17947 /* AND <-> BIC. TST has no inverted equivalent. */
17948 case T2_OPCODE_AND
:
17949 new_inst
= T2_OPCODE_BIC
;
17956 case T2_OPCODE_BIC
:
17957 new_inst
= T2_OPCODE_AND
;
17962 case T2_OPCODE_ADC
:
17963 new_inst
= T2_OPCODE_SBC
;
17967 case T2_OPCODE_SBC
:
17968 new_inst
= T2_OPCODE_ADC
;
17972 /* We cannot do anything. */
17977 if (value
== (unsigned int)FAIL
)
17980 *instruction
&= T2_OPCODE_MASK
;
17981 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
17985 /* Read a 32-bit thumb instruction from buf. */
17986 static unsigned long
17987 get_thumb32_insn (char * buf
)
17989 unsigned long insn
;
17990 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
17991 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17997 /* We usually want to set the low bit on the address of thumb function
17998 symbols. In particular .word foo - . should have the low bit set.
17999 Generic code tries to fold the difference of two symbols to
18000 a constant. Prevent this and force a relocation when the first symbols
18001 is a thumb function. */
18003 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
18005 if (op
== O_subtract
18006 && l
->X_op
== O_symbol
18007 && r
->X_op
== O_symbol
18008 && THUMB_IS_FUNC (l
->X_add_symbol
))
18010 l
->X_op
= O_subtract
;
18011 l
->X_op_symbol
= r
->X_add_symbol
;
18012 l
->X_add_number
-= r
->X_add_number
;
18015 /* Process as normal. */
18020 md_apply_fix (fixS
* fixP
,
18024 offsetT value
= * valP
;
18026 unsigned int newimm
;
18027 unsigned long temp
;
18029 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
18031 assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
18033 /* Note whether this will delete the relocation. */
18035 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
18038 /* On a 64-bit host, silently truncate 'value' to 32 bits for
18039 consistency with the behaviour on 32-bit hosts. Remember value
18041 value
&= 0xffffffff;
18042 value
^= 0x80000000;
18043 value
-= 0x80000000;
18046 fixP
->fx_addnumber
= value
;
18048 /* Same treatment for fixP->fx_offset. */
18049 fixP
->fx_offset
&= 0xffffffff;
18050 fixP
->fx_offset
^= 0x80000000;
18051 fixP
->fx_offset
-= 0x80000000;
18053 switch (fixP
->fx_r_type
)
18055 case BFD_RELOC_NONE
:
18056 /* This will need to go in the object file. */
18060 case BFD_RELOC_ARM_IMMEDIATE
:
18061 /* We claim that this fixup has been processed here,
18062 even if in fact we generate an error because we do
18063 not have a reloc for it, so tc_gen_reloc will reject it. */
18067 && ! S_IS_DEFINED (fixP
->fx_addsy
))
18069 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18070 _("undefined symbol %s used as an immediate value"),
18071 S_GET_NAME (fixP
->fx_addsy
));
18075 newimm
= encode_arm_immediate (value
);
18076 temp
= md_chars_to_number (buf
, INSN_SIZE
);
18078 /* If the instruction will fail, see if we can fix things up by
18079 changing the opcode. */
18080 if (newimm
== (unsigned int) FAIL
18081 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
18083 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18084 _("invalid constant (%lx) after fixup"),
18085 (unsigned long) value
);
18089 newimm
|= (temp
& 0xfffff000);
18090 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
18093 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
18095 unsigned int highpart
= 0;
18096 unsigned int newinsn
= 0xe1a00000; /* nop. */
18098 newimm
= encode_arm_immediate (value
);
18099 temp
= md_chars_to_number (buf
, INSN_SIZE
);
18101 /* If the instruction will fail, see if we can fix things up by
18102 changing the opcode. */
18103 if (newimm
== (unsigned int) FAIL
18104 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
18106 /* No ? OK - try using two ADD instructions to generate
18108 newimm
= validate_immediate_twopart (value
, & highpart
);
18110 /* Yes - then make sure that the second instruction is
18112 if (newimm
!= (unsigned int) FAIL
)
18114 /* Still No ? Try using a negated value. */
18115 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
18116 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
18117 /* Otherwise - give up. */
18120 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18121 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
18126 /* Replace the first operand in the 2nd instruction (which
18127 is the PC) with the destination register. We have
18128 already added in the PC in the first instruction and we
18129 do not want to do it again. */
18130 newinsn
&= ~ 0xf0000;
18131 newinsn
|= ((newinsn
& 0x0f000) << 4);
18134 newimm
|= (temp
& 0xfffff000);
18135 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
18137 highpart
|= (newinsn
& 0xfffff000);
18138 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
18142 case BFD_RELOC_ARM_OFFSET_IMM
:
18143 if (!fixP
->fx_done
&& seg
->use_rela_p
)
18146 case BFD_RELOC_ARM_LITERAL
:
18152 if (validate_offset_imm (value
, 0) == FAIL
)
18154 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
18155 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18156 _("invalid literal constant: pool needs to be closer"));
18158 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18159 _("bad immediate value for offset (%ld)"),
18164 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18165 newval
&= 0xff7ff000;
18166 newval
|= value
| (sign
? INDEX_UP
: 0);
18167 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18170 case BFD_RELOC_ARM_OFFSET_IMM8
:
18171 case BFD_RELOC_ARM_HWLITERAL
:
18177 if (validate_offset_imm (value
, 1) == FAIL
)
18179 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
18180 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18181 _("invalid literal constant: pool needs to be closer"));
18183 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
18188 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18189 newval
&= 0xff7ff0f0;
18190 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
18191 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18194 case BFD_RELOC_ARM_T32_OFFSET_U8
:
18195 if (value
< 0 || value
> 1020 || value
% 4 != 0)
18196 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18197 _("bad immediate value for offset (%ld)"), (long) value
);
18200 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
18202 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
18205 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
18206 /* This is a complicated relocation used for all varieties of Thumb32
18207 load/store instruction with immediate offset:
18209 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
18210 *4, optional writeback(W)
18211 (doubleword load/store)
18213 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
18214 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
18215 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
18216 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
18217 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
18219 Uppercase letters indicate bits that are already encoded at
18220 this point. Lowercase letters are our problem. For the
18221 second block of instructions, the secondary opcode nybble
18222 (bits 8..11) is present, and bit 23 is zero, even if this is
18223 a PC-relative operation. */
18224 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18226 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
18228 if ((newval
& 0xf0000000) == 0xe0000000)
18230 /* Doubleword load/store: 8-bit offset, scaled by 4. */
18232 newval
|= (1 << 23);
18235 if (value
% 4 != 0)
18237 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18238 _("offset not a multiple of 4"));
18244 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18245 _("offset out of range"));
18250 else if ((newval
& 0x000f0000) == 0x000f0000)
18252 /* PC-relative, 12-bit offset. */
18254 newval
|= (1 << 23);
18259 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18260 _("offset out of range"));
18265 else if ((newval
& 0x00000100) == 0x00000100)
18267 /* Writeback: 8-bit, +/- offset. */
18269 newval
|= (1 << 9);
18274 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18275 _("offset out of range"));
18280 else if ((newval
& 0x00000f00) == 0x00000e00)
18282 /* T-instruction: positive 8-bit offset. */
18283 if (value
< 0 || value
> 0xff)
18285 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18286 _("offset out of range"));
18294 /* Positive 12-bit or negative 8-bit offset. */
18298 newval
|= (1 << 23);
18308 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18309 _("offset out of range"));
18316 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
18317 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
18320 case BFD_RELOC_ARM_SHIFT_IMM
:
18321 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18322 if (((unsigned long) value
) > 32
18324 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
18326 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18327 _("shift expression is too large"));
18332 /* Shifts of zero must be done as lsl. */
18334 else if (value
== 32)
18336 newval
&= 0xfffff07f;
18337 newval
|= (value
& 0x1f) << 7;
18338 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18341 case BFD_RELOC_ARM_T32_IMMEDIATE
:
18342 case BFD_RELOC_ARM_T32_ADD_IMM
:
18343 case BFD_RELOC_ARM_T32_IMM12
:
18344 case BFD_RELOC_ARM_T32_ADD_PC12
:
18345 /* We claim that this fixup has been processed here,
18346 even if in fact we generate an error because we do
18347 not have a reloc for it, so tc_gen_reloc will reject it. */
18351 && ! S_IS_DEFINED (fixP
->fx_addsy
))
18353 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18354 _("undefined symbol %s used as an immediate value"),
18355 S_GET_NAME (fixP
->fx_addsy
));
18359 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18361 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
18364 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
18365 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
18367 newimm
= encode_thumb32_immediate (value
);
18368 if (newimm
== (unsigned int) FAIL
)
18369 newimm
= thumb32_negate_data_op (&newval
, value
);
18371 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
18372 && newimm
== (unsigned int) FAIL
)
18374 /* Turn add/sum into addw/subw. */
18375 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
18376 newval
= (newval
& 0xfeffffff) | 0x02000000;
18378 /* 12 bit immediate for addw/subw. */
18382 newval
^= 0x00a00000;
18385 newimm
= (unsigned int) FAIL
;
18390 if (newimm
== (unsigned int)FAIL
)
18392 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18393 _("invalid constant (%lx) after fixup"),
18394 (unsigned long) value
);
18398 newval
|= (newimm
& 0x800) << 15;
18399 newval
|= (newimm
& 0x700) << 4;
18400 newval
|= (newimm
& 0x0ff);
18402 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
18403 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
18406 case BFD_RELOC_ARM_SMC
:
18407 if (((unsigned long) value
) > 0xffff)
18408 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18409 _("invalid smc expression"));
18410 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18411 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
18412 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18415 case BFD_RELOC_ARM_SWI
:
18416 if (fixP
->tc_fix_data
!= 0)
18418 if (((unsigned long) value
) > 0xff)
18419 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18420 _("invalid swi expression"));
18421 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18423 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18427 if (((unsigned long) value
) > 0x00ffffff)
18428 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18429 _("invalid swi expression"));
18430 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18432 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18436 case BFD_RELOC_ARM_MULTI
:
18437 if (((unsigned long) value
) > 0xffff)
18438 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18439 _("invalid expression in load/store multiple"));
18440 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
18441 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18445 case BFD_RELOC_ARM_PCREL_CALL
:
18446 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18447 if ((newval
& 0xf0000000) == 0xf0000000)
18451 goto arm_branch_common
;
18453 case BFD_RELOC_ARM_PCREL_JUMP
:
18454 case BFD_RELOC_ARM_PLT32
:
18456 case BFD_RELOC_ARM_PCREL_BRANCH
:
18458 goto arm_branch_common
;
18460 case BFD_RELOC_ARM_PCREL_BLX
:
18463 /* We are going to store value (shifted right by two) in the
18464 instruction, in a 24 bit, signed field. Bits 26 through 32 either
18465 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
18466 also be be clear. */
18468 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18469 _("misaligned branch destination"));
18470 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
18471 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
18472 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18473 _("branch out of range"));
18475 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18477 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18478 newval
|= (value
>> 2) & 0x00ffffff;
18479 /* Set the H bit on BLX instructions. */
18483 newval
|= 0x01000000;
18485 newval
&= ~0x01000000;
18487 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18491 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
18492 /* CBZ can only branch forward. */
18494 /* Attempts to use CBZ to branch to the next instruction
18495 (which, strictly speaking, are prohibited) will be turned into
18498 FIXME: It may be better to remove the instruction completely and
18499 perform relaxation. */
18502 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18503 newval
= 0xbf00; /* NOP encoding T1 */
18504 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18509 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18510 _("branch out of range"));
18512 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18514 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18515 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
18516 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18521 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
18522 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
18523 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18524 _("branch out of range"));
18526 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18528 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18529 newval
|= (value
& 0x1ff) >> 1;
18530 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18534 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
18535 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
18536 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18537 _("branch out of range"));
18539 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18541 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18542 newval
|= (value
& 0xfff) >> 1;
18543 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18547 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
18548 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
18549 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18550 _("conditional branch out of range"));
18552 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18555 addressT S
, J1
, J2
, lo
, hi
;
18557 S
= (value
& 0x00100000) >> 20;
18558 J2
= (value
& 0x00080000) >> 19;
18559 J1
= (value
& 0x00040000) >> 18;
18560 hi
= (value
& 0x0003f000) >> 12;
18561 lo
= (value
& 0x00000ffe) >> 1;
18563 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18564 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18565 newval
|= (S
<< 10) | hi
;
18566 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
18567 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18568 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18572 case BFD_RELOC_THUMB_PCREL_BLX
:
18573 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
18574 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
18575 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18576 _("branch out of range"));
18578 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
18579 /* For a BLX instruction, make sure that the relocation is rounded up
18580 to a word boundary. This follows the semantics of the instruction
18581 which specifies that bit 1 of the target address will come from bit
18582 1 of the base address. */
18583 value
= (value
+ 1) & ~ 1;
18585 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18589 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18590 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18591 newval
|= (value
& 0x7fffff) >> 12;
18592 newval2
|= (value
& 0xfff) >> 1;
18593 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18594 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18598 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
18599 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
18600 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18601 _("branch out of range"));
18603 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18606 addressT S
, I1
, I2
, lo
, hi
;
18608 S
= (value
& 0x01000000) >> 24;
18609 I1
= (value
& 0x00800000) >> 23;
18610 I2
= (value
& 0x00400000) >> 22;
18611 hi
= (value
& 0x003ff000) >> 12;
18612 lo
= (value
& 0x00000ffe) >> 1;
18617 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18618 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18619 newval
|= (S
<< 10) | hi
;
18620 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
18621 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18622 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18627 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18628 md_number_to_chars (buf
, value
, 1);
18632 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18633 md_number_to_chars (buf
, value
, 2);
18637 case BFD_RELOC_ARM_TLS_GD32
:
18638 case BFD_RELOC_ARM_TLS_LE32
:
18639 case BFD_RELOC_ARM_TLS_IE32
:
18640 case BFD_RELOC_ARM_TLS_LDM32
:
18641 case BFD_RELOC_ARM_TLS_LDO32
:
18642 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
18645 case BFD_RELOC_ARM_GOT32
:
18646 case BFD_RELOC_ARM_GOTOFF
:
18647 case BFD_RELOC_ARM_TARGET2
:
18648 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18649 md_number_to_chars (buf
, 0, 4);
18653 case BFD_RELOC_RVA
:
18655 case BFD_RELOC_ARM_TARGET1
:
18656 case BFD_RELOC_ARM_ROSEGREL32
:
18657 case BFD_RELOC_ARM_SBREL32
:
18658 case BFD_RELOC_32_PCREL
:
18660 case BFD_RELOC_32_SECREL
:
18662 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18664 /* For WinCE we only do this for pcrel fixups. */
18665 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
18667 md_number_to_chars (buf
, value
, 4);
18671 case BFD_RELOC_ARM_PREL31
:
18672 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18674 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
18675 if ((value
^ (value
>> 1)) & 0x40000000)
18677 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18678 _("rel31 relocation overflow"));
18680 newval
|= value
& 0x7fffffff;
18681 md_number_to_chars (buf
, newval
, 4);
18686 case BFD_RELOC_ARM_CP_OFF_IMM
:
18687 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
18688 if (value
< -1023 || value
> 1023 || (value
& 3))
18689 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18690 _("co-processor offset out of range"));
18695 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18696 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18697 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18699 newval
= get_thumb32_insn (buf
);
18700 newval
&= 0xff7fff00;
18701 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
18702 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18703 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18704 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18706 put_thumb32_insn (buf
, newval
);
18709 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
18710 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
18711 if (value
< -255 || value
> 255)
18712 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18713 _("co-processor offset out of range"));
18715 goto cp_off_common
;
18717 case BFD_RELOC_ARM_THUMB_OFFSET
:
18718 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18719 /* Exactly what ranges, and where the offset is inserted depends
18720 on the type of instruction, we can establish this from the
18722 switch (newval
>> 12)
18724 case 4: /* PC load. */
18725 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
18726 forced to zero for these loads; md_pcrel_from has already
18727 compensated for this. */
18729 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18730 _("invalid offset, target not word aligned (0x%08lX)"),
18731 (((unsigned long) fixP
->fx_frag
->fr_address
18732 + (unsigned long) fixP
->fx_where
) & ~3)
18733 + (unsigned long) value
);
18735 if (value
& ~0x3fc)
18736 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18737 _("invalid offset, value too big (0x%08lX)"),
18740 newval
|= value
>> 2;
18743 case 9: /* SP load/store. */
18744 if (value
& ~0x3fc)
18745 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18746 _("invalid offset, value too big (0x%08lX)"),
18748 newval
|= value
>> 2;
18751 case 6: /* Word load/store. */
18753 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18754 _("invalid offset, value too big (0x%08lX)"),
18756 newval
|= value
<< 4; /* 6 - 2. */
18759 case 7: /* Byte load/store. */
18761 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18762 _("invalid offset, value too big (0x%08lX)"),
18764 newval
|= value
<< 6;
18767 case 8: /* Halfword load/store. */
18769 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18770 _("invalid offset, value too big (0x%08lX)"),
18772 newval
|= value
<< 5; /* 6 - 1. */
18776 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18777 "Unable to process relocation for thumb opcode: %lx",
18778 (unsigned long) newval
);
18781 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18784 case BFD_RELOC_ARM_THUMB_ADD
:
18785 /* This is a complicated relocation, since we use it for all of
18786 the following immediate relocations:
18790 9bit ADD/SUB SP word-aligned
18791 10bit ADD PC/SP word-aligned
18793 The type of instruction being processed is encoded in the
18800 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18802 int rd
= (newval
>> 4) & 0xf;
18803 int rs
= newval
& 0xf;
18804 int subtract
= !!(newval
& 0x8000);
18806 /* Check for HI regs, only very restricted cases allowed:
18807 Adjusting SP, and using PC or SP to get an address. */
18808 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
18809 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
18810 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18811 _("invalid Hi register with immediate"));
18813 /* If value is negative, choose the opposite instruction. */
18817 subtract
= !subtract
;
18819 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18820 _("immediate value out of range"));
18825 if (value
& ~0x1fc)
18826 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18827 _("invalid immediate for stack address calculation"));
18828 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
18829 newval
|= value
>> 2;
18831 else if (rs
== REG_PC
|| rs
== REG_SP
)
18833 if (subtract
|| value
& ~0x3fc)
18834 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18835 _("invalid immediate for address calculation (value = 0x%08lX)"),
18836 (unsigned long) value
);
18837 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
18839 newval
|= value
>> 2;
18844 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18845 _("immediate value out of range"));
18846 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
18847 newval
|= (rd
<< 8) | value
;
18852 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18853 _("immediate value out of range"));
18854 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
18855 newval
|= rd
| (rs
<< 3) | (value
<< 6);
18858 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18861 case BFD_RELOC_ARM_THUMB_IMM
:
18862 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18863 if (value
< 0 || value
> 255)
18864 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18865 _("invalid immediate: %ld is out of range"),
18868 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18871 case BFD_RELOC_ARM_THUMB_SHIFT
:
18872 /* 5bit shift value (0..32). LSL cannot take 32. */
18873 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
18874 temp
= newval
& 0xf800;
18875 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
18876 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18877 _("invalid shift value: %ld"), (long) value
);
18878 /* Shifts of zero must be encoded as LSL. */
18880 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
18881 /* Shifts of 32 are encoded as zero. */
18882 else if (value
== 32)
18884 newval
|= value
<< 6;
18885 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18888 case BFD_RELOC_VTABLE_INHERIT
:
18889 case BFD_RELOC_VTABLE_ENTRY
:
18893 case BFD_RELOC_ARM_MOVW
:
18894 case BFD_RELOC_ARM_MOVT
:
18895 case BFD_RELOC_ARM_THUMB_MOVW
:
18896 case BFD_RELOC_ARM_THUMB_MOVT
:
18897 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18899 /* REL format relocations are limited to a 16-bit addend. */
18900 if (!fixP
->fx_done
)
18902 if (value
< -0x8000 || value
> 0x7fff)
18903 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18904 _("offset out of range"));
18906 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
18907 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18912 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
18913 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18915 newval
= get_thumb32_insn (buf
);
18916 newval
&= 0xfbf08f00;
18917 newval
|= (value
& 0xf000) << 4;
18918 newval
|= (value
& 0x0800) << 15;
18919 newval
|= (value
& 0x0700) << 4;
18920 newval
|= (value
& 0x00ff);
18921 put_thumb32_insn (buf
, newval
);
18925 newval
= md_chars_to_number (buf
, 4);
18926 newval
&= 0xfff0f000;
18927 newval
|= value
& 0x0fff;
18928 newval
|= (value
& 0xf000) << 4;
18929 md_number_to_chars (buf
, newval
, 4);
18934 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
18935 case BFD_RELOC_ARM_ALU_PC_G0
:
18936 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
18937 case BFD_RELOC_ARM_ALU_PC_G1
:
18938 case BFD_RELOC_ARM_ALU_PC_G2
:
18939 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
18940 case BFD_RELOC_ARM_ALU_SB_G0
:
18941 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
18942 case BFD_RELOC_ARM_ALU_SB_G1
:
18943 case BFD_RELOC_ARM_ALU_SB_G2
:
18944 assert (!fixP
->fx_done
);
18945 if (!seg
->use_rela_p
)
18948 bfd_vma encoded_addend
;
18949 bfd_vma addend_abs
= abs (value
);
18951 /* Check that the absolute value of the addend can be
18952 expressed as an 8-bit constant plus a rotation. */
18953 encoded_addend
= encode_arm_immediate (addend_abs
);
18954 if (encoded_addend
== (unsigned int) FAIL
)
18955 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18956 _("the offset 0x%08lX is not representable"),
18957 (unsigned long) addend_abs
);
18959 /* Extract the instruction. */
18960 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18962 /* If the addend is positive, use an ADD instruction.
18963 Otherwise use a SUB. Take care not to destroy the S bit. */
18964 insn
&= 0xff1fffff;
18970 /* Place the encoded addend into the first 12 bits of the
18972 insn
&= 0xfffff000;
18973 insn
|= encoded_addend
;
18975 /* Update the instruction. */
18976 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18980 case BFD_RELOC_ARM_LDR_PC_G0
:
18981 case BFD_RELOC_ARM_LDR_PC_G1
:
18982 case BFD_RELOC_ARM_LDR_PC_G2
:
18983 case BFD_RELOC_ARM_LDR_SB_G0
:
18984 case BFD_RELOC_ARM_LDR_SB_G1
:
18985 case BFD_RELOC_ARM_LDR_SB_G2
:
18986 assert (!fixP
->fx_done
);
18987 if (!seg
->use_rela_p
)
18990 bfd_vma addend_abs
= abs (value
);
18992 /* Check that the absolute value of the addend can be
18993 encoded in 12 bits. */
18994 if (addend_abs
>= 0x1000)
18995 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18996 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
18997 (unsigned long) addend_abs
);
18999 /* Extract the instruction. */
19000 insn
= md_chars_to_number (buf
, INSN_SIZE
);
19002 /* If the addend is negative, clear bit 23 of the instruction.
19003 Otherwise set it. */
19005 insn
&= ~(1 << 23);
19009 /* Place the absolute value of the addend into the first 12 bits
19010 of the instruction. */
19011 insn
&= 0xfffff000;
19012 insn
|= addend_abs
;
19014 /* Update the instruction. */
19015 md_number_to_chars (buf
, insn
, INSN_SIZE
);
19019 case BFD_RELOC_ARM_LDRS_PC_G0
:
19020 case BFD_RELOC_ARM_LDRS_PC_G1
:
19021 case BFD_RELOC_ARM_LDRS_PC_G2
:
19022 case BFD_RELOC_ARM_LDRS_SB_G0
:
19023 case BFD_RELOC_ARM_LDRS_SB_G1
:
19024 case BFD_RELOC_ARM_LDRS_SB_G2
:
19025 assert (!fixP
->fx_done
);
19026 if (!seg
->use_rela_p
)
19029 bfd_vma addend_abs
= abs (value
);
19031 /* Check that the absolute value of the addend can be
19032 encoded in 8 bits. */
19033 if (addend_abs
>= 0x100)
19034 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19035 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
19036 (unsigned long) addend_abs
);
19038 /* Extract the instruction. */
19039 insn
= md_chars_to_number (buf
, INSN_SIZE
);
19041 /* If the addend is negative, clear bit 23 of the instruction.
19042 Otherwise set it. */
19044 insn
&= ~(1 << 23);
19048 /* Place the first four bits of the absolute value of the addend
19049 into the first 4 bits of the instruction, and the remaining
19050 four into bits 8 .. 11. */
19051 insn
&= 0xfffff0f0;
19052 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
19054 /* Update the instruction. */
19055 md_number_to_chars (buf
, insn
, INSN_SIZE
);
19059 case BFD_RELOC_ARM_LDC_PC_G0
:
19060 case BFD_RELOC_ARM_LDC_PC_G1
:
19061 case BFD_RELOC_ARM_LDC_PC_G2
:
19062 case BFD_RELOC_ARM_LDC_SB_G0
:
19063 case BFD_RELOC_ARM_LDC_SB_G1
:
19064 case BFD_RELOC_ARM_LDC_SB_G2
:
19065 assert (!fixP
->fx_done
);
19066 if (!seg
->use_rela_p
)
19069 bfd_vma addend_abs
= abs (value
);
19071 /* Check that the absolute value of the addend is a multiple of
19072 four and, when divided by four, fits in 8 bits. */
19073 if (addend_abs
& 0x3)
19074 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19075 _("bad offset 0x%08lX (must be word-aligned)"),
19076 (unsigned long) addend_abs
);
19078 if ((addend_abs
>> 2) > 0xff)
19079 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19080 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
19081 (unsigned long) addend_abs
);
19083 /* Extract the instruction. */
19084 insn
= md_chars_to_number (buf
, INSN_SIZE
);
19086 /* If the addend is negative, clear bit 23 of the instruction.
19087 Otherwise set it. */
19089 insn
&= ~(1 << 23);
19093 /* Place the addend (divided by four) into the first eight
19094 bits of the instruction. */
19095 insn
&= 0xfffffff0;
19096 insn
|= addend_abs
>> 2;
19098 /* Update the instruction. */
19099 md_number_to_chars (buf
, insn
, INSN_SIZE
);
19103 case BFD_RELOC_ARM_V4BX
:
19104 /* This will need to go in the object file. */
19108 case BFD_RELOC_UNUSED
:
19110 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19111 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
19115 /* Translate internal representation of relocation info to BFD target
19119 tc_gen_reloc (asection
*section
, fixS
*fixp
)
19122 bfd_reloc_code_real_type code
;
19124 reloc
= xmalloc (sizeof (arelent
));
19126 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
19127 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
19128 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
19130 if (fixp
->fx_pcrel
)
19132 if (section
->use_rela_p
)
19133 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
19135 fixp
->fx_offset
= reloc
->address
;
19137 reloc
->addend
= fixp
->fx_offset
;
19139 switch (fixp
->fx_r_type
)
19142 if (fixp
->fx_pcrel
)
19144 code
= BFD_RELOC_8_PCREL
;
19149 if (fixp
->fx_pcrel
)
19151 code
= BFD_RELOC_16_PCREL
;
19156 if (fixp
->fx_pcrel
)
19158 code
= BFD_RELOC_32_PCREL
;
19162 case BFD_RELOC_ARM_MOVW
:
19163 if (fixp
->fx_pcrel
)
19165 code
= BFD_RELOC_ARM_MOVW_PCREL
;
19169 case BFD_RELOC_ARM_MOVT
:
19170 if (fixp
->fx_pcrel
)
19172 code
= BFD_RELOC_ARM_MOVT_PCREL
;
19176 case BFD_RELOC_ARM_THUMB_MOVW
:
19177 if (fixp
->fx_pcrel
)
19179 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
19183 case BFD_RELOC_ARM_THUMB_MOVT
:
19184 if (fixp
->fx_pcrel
)
19186 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
19190 case BFD_RELOC_NONE
:
19191 case BFD_RELOC_ARM_PCREL_BRANCH
:
19192 case BFD_RELOC_ARM_PCREL_BLX
:
19193 case BFD_RELOC_RVA
:
19194 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19195 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19196 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19197 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19198 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19199 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19200 case BFD_RELOC_THUMB_PCREL_BLX
:
19201 case BFD_RELOC_VTABLE_ENTRY
:
19202 case BFD_RELOC_VTABLE_INHERIT
:
19204 case BFD_RELOC_32_SECREL
:
19206 code
= fixp
->fx_r_type
;
19209 case BFD_RELOC_ARM_LITERAL
:
19210 case BFD_RELOC_ARM_HWLITERAL
:
19211 /* If this is called then the a literal has
19212 been referenced across a section boundary. */
19213 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19214 _("literal referenced across section boundary"));
19218 case BFD_RELOC_ARM_GOT32
:
19219 case BFD_RELOC_ARM_GOTOFF
:
19220 case BFD_RELOC_ARM_PLT32
:
19221 case BFD_RELOC_ARM_TARGET1
:
19222 case BFD_RELOC_ARM_ROSEGREL32
:
19223 case BFD_RELOC_ARM_SBREL32
:
19224 case BFD_RELOC_ARM_PREL31
:
19225 case BFD_RELOC_ARM_TARGET2
:
19226 case BFD_RELOC_ARM_TLS_LE32
:
19227 case BFD_RELOC_ARM_TLS_LDO32
:
19228 case BFD_RELOC_ARM_PCREL_CALL
:
19229 case BFD_RELOC_ARM_PCREL_JUMP
:
19230 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
19231 case BFD_RELOC_ARM_ALU_PC_G0
:
19232 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
19233 case BFD_RELOC_ARM_ALU_PC_G1
:
19234 case BFD_RELOC_ARM_ALU_PC_G2
:
19235 case BFD_RELOC_ARM_LDR_PC_G0
:
19236 case BFD_RELOC_ARM_LDR_PC_G1
:
19237 case BFD_RELOC_ARM_LDR_PC_G2
:
19238 case BFD_RELOC_ARM_LDRS_PC_G0
:
19239 case BFD_RELOC_ARM_LDRS_PC_G1
:
19240 case BFD_RELOC_ARM_LDRS_PC_G2
:
19241 case BFD_RELOC_ARM_LDC_PC_G0
:
19242 case BFD_RELOC_ARM_LDC_PC_G1
:
19243 case BFD_RELOC_ARM_LDC_PC_G2
:
19244 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
19245 case BFD_RELOC_ARM_ALU_SB_G0
:
19246 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
19247 case BFD_RELOC_ARM_ALU_SB_G1
:
19248 case BFD_RELOC_ARM_ALU_SB_G2
:
19249 case BFD_RELOC_ARM_LDR_SB_G0
:
19250 case BFD_RELOC_ARM_LDR_SB_G1
:
19251 case BFD_RELOC_ARM_LDR_SB_G2
:
19252 case BFD_RELOC_ARM_LDRS_SB_G0
:
19253 case BFD_RELOC_ARM_LDRS_SB_G1
:
19254 case BFD_RELOC_ARM_LDRS_SB_G2
:
19255 case BFD_RELOC_ARM_LDC_SB_G0
:
19256 case BFD_RELOC_ARM_LDC_SB_G1
:
19257 case BFD_RELOC_ARM_LDC_SB_G2
:
19258 case BFD_RELOC_ARM_V4BX
:
19259 code
= fixp
->fx_r_type
;
19262 case BFD_RELOC_ARM_TLS_GD32
:
19263 case BFD_RELOC_ARM_TLS_IE32
:
19264 case BFD_RELOC_ARM_TLS_LDM32
:
19265 /* BFD will include the symbol's address in the addend.
19266 But we don't want that, so subtract it out again here. */
19267 if (!S_IS_COMMON (fixp
->fx_addsy
))
19268 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
19269 code
= fixp
->fx_r_type
;
19273 case BFD_RELOC_ARM_IMMEDIATE
:
19274 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19275 _("internal relocation (type: IMMEDIATE) not fixed up"));
19278 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
19279 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19280 _("ADRL used for a symbol not defined in the same file"));
19283 case BFD_RELOC_ARM_OFFSET_IMM
:
19284 if (section
->use_rela_p
)
19286 code
= fixp
->fx_r_type
;
19290 if (fixp
->fx_addsy
!= NULL
19291 && !S_IS_DEFINED (fixp
->fx_addsy
)
19292 && S_IS_LOCAL (fixp
->fx_addsy
))
19294 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19295 _("undefined local label `%s'"),
19296 S_GET_NAME (fixp
->fx_addsy
));
19300 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19301 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
19308 switch (fixp
->fx_r_type
)
19310 case BFD_RELOC_NONE
: type
= "NONE"; break;
19311 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
19312 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
19313 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
19314 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
19315 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
19316 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
19317 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
19318 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
19319 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
19320 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
19321 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
19322 default: type
= _("<unknown>"); break;
19324 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19325 _("cannot represent %s relocation in this object file format"),
19332 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
19334 && fixp
->fx_addsy
== GOT_symbol
)
19336 code
= BFD_RELOC_ARM_GOTPC
;
19337 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
19341 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
19343 if (reloc
->howto
== NULL
)
19345 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19346 _("cannot represent %s relocation in this object file format"),
19347 bfd_get_reloc_code_name (code
));
19351 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
19352 vtable entry to be used in the relocation's section offset. */
19353 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
19354 reloc
->address
= fixp
->fx_offset
;
19359 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
19362 cons_fix_new_arm (fragS
* frag
,
19367 bfd_reloc_code_real_type type
;
19371 FIXME: @@ Should look at CPU word size. */
19375 type
= BFD_RELOC_8
;
19378 type
= BFD_RELOC_16
;
19382 type
= BFD_RELOC_32
;
19385 type
= BFD_RELOC_64
;
19390 if (exp
->X_op
== O_secrel
)
19392 exp
->X_op
= O_symbol
;
19393 type
= BFD_RELOC_32_SECREL
;
19397 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
19400 #if defined OBJ_COFF || defined OBJ_ELF
19402 arm_validate_fix (fixS
* fixP
)
19404 /* If the destination of the branch is a defined symbol which does not have
19405 the THUMB_FUNC attribute, then we must be calling a function which has
19406 the (interfacearm) attribute. We look for the Thumb entry point to that
19407 function and change the branch to refer to that function instead. */
19408 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
19409 && fixP
->fx_addsy
!= NULL
19410 && S_IS_DEFINED (fixP
->fx_addsy
)
19411 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
19413 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
19419 arm_force_relocation (struct fix
* fixp
)
19421 #if defined (OBJ_COFF) && defined (TE_PE)
19422 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
19426 /* Resolve these relocations even if the symbol is extern or weak. */
19427 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
19428 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
19429 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
19430 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
19431 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
19432 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
19433 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
19436 /* Always leave these relocations for the linker. */
19437 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
19438 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
19439 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
19442 /* Always generate relocations against function symbols. */
19443 if (fixp
->fx_r_type
== BFD_RELOC_32
19445 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
19448 return generic_force_reloc (fixp
);
19451 #if defined (OBJ_ELF) || defined (OBJ_COFF)
19452 /* Relocations against function names must be left unadjusted,
19453 so that the linker can use this information to generate interworking
19454 stubs. The MIPS version of this function
19455 also prevents relocations that are mips-16 specific, but I do not
19456 know why it does this.
19459 There is one other problem that ought to be addressed here, but
19460 which currently is not: Taking the address of a label (rather
19461 than a function) and then later jumping to that address. Such
19462 addresses also ought to have their bottom bit set (assuming that
19463 they reside in Thumb code), but at the moment they will not. */
19466 arm_fix_adjustable (fixS
* fixP
)
19468 if (fixP
->fx_addsy
== NULL
)
19471 /* Preserve relocations against symbols with function type. */
19472 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
19475 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
19476 && fixP
->fx_subsy
== NULL
)
19479 /* We need the symbol name for the VTABLE entries. */
19480 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
19481 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
19484 /* Don't allow symbols to be discarded on GOT related relocs. */
19485 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
19486 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
19487 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
19488 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
19489 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
19490 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
19491 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
19492 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
19493 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
19496 /* Similarly for group relocations. */
19497 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
19498 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
19499 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
19502 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
19503 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
19504 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
19505 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
19506 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
19507 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
19508 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
19509 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
19510 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
19515 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
19520 elf32_arm_target_format (void)
19523 return (target_big_endian
19524 ? "elf32-bigarm-symbian"
19525 : "elf32-littlearm-symbian");
19526 #elif defined (TE_VXWORKS)
19527 return (target_big_endian
19528 ? "elf32-bigarm-vxworks"
19529 : "elf32-littlearm-vxworks");
19531 if (target_big_endian
)
19532 return "elf32-bigarm";
19534 return "elf32-littlearm";
19539 armelf_frob_symbol (symbolS
* symp
,
19542 elf_frob_symbol (symp
, puntp
);
19546 /* MD interface: Finalization. */
19548 /* A good place to do this, although this was probably not intended
19549 for this kind of use. We need to dump the literal pool before
19550 references are made to a null symbol pointer. */
19555 literal_pool
* pool
;
19557 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
19559 /* Put it at the end of the relevant section. */
19560 subseg_set (pool
->section
, pool
->sub_section
);
19562 arm_elf_change_section ();
19568 /* Adjust the symbol table. This marks Thumb symbols as distinct from
19572 arm_adjust_symtab (void)
19577 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
19579 if (ARM_IS_THUMB (sym
))
19581 if (THUMB_IS_FUNC (sym
))
19583 /* Mark the symbol as a Thumb function. */
19584 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
19585 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
19586 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
19588 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
19589 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
19591 as_bad (_("%s: unexpected function type: %d"),
19592 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
19594 else switch (S_GET_STORAGE_CLASS (sym
))
19597 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
19600 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
19603 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
19611 if (ARM_IS_INTERWORK (sym
))
19612 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
19619 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
19621 if (ARM_IS_THUMB (sym
))
19623 elf_symbol_type
* elf_sym
;
19625 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
19626 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
19628 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
19629 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
19631 /* If it's a .thumb_func, declare it as so,
19632 otherwise tag label as .code 16. */
19633 if (THUMB_IS_FUNC (sym
))
19634 elf_sym
->internal_elf_sym
.st_info
=
19635 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
19636 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
19637 elf_sym
->internal_elf_sym
.st_info
=
19638 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
19645 /* MD interface: Initialization. */
19648 set_constant_flonums (void)
19652 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
19653 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
19657 /* Auto-select Thumb mode if it's the only available instruction set for the
19658 given architecture. */
19661 autoselect_thumb_from_cpu_variant (void)
19663 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
19664 opcode_select (16);
19673 if ( (arm_ops_hsh
= hash_new ()) == NULL
19674 || (arm_cond_hsh
= hash_new ()) == NULL
19675 || (arm_shift_hsh
= hash_new ()) == NULL
19676 || (arm_psr_hsh
= hash_new ()) == NULL
19677 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
19678 || (arm_reg_hsh
= hash_new ()) == NULL
19679 || (arm_reloc_hsh
= hash_new ()) == NULL
19680 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
19681 as_fatal (_("virtual memory exhausted"));
19683 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
19684 hash_insert (arm_ops_hsh
, insns
[i
].template, (void *) (insns
+ i
));
19685 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
19686 hash_insert (arm_cond_hsh
, conds
[i
].template, (void *) (conds
+ i
));
19687 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
19688 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
19689 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
19690 hash_insert (arm_psr_hsh
, psrs
[i
].template, (void *) (psrs
+ i
));
19691 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
19692 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template, (void *) (v7m_psrs
+ i
));
19693 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
19694 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
19696 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
19698 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template,
19699 (void *) (barrier_opt_names
+ i
));
19701 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
19702 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
19705 set_constant_flonums ();
19707 /* Set the cpu variant based on the command-line options. We prefer
19708 -mcpu= over -march= if both are set (as for GCC); and we prefer
19709 -mfpu= over any other way of setting the floating point unit.
19710 Use of legacy options with new options are faulted. */
19713 if (mcpu_cpu_opt
|| march_cpu_opt
)
19714 as_bad (_("use of old and new-style options to set CPU type"));
19716 mcpu_cpu_opt
= legacy_cpu
;
19718 else if (!mcpu_cpu_opt
)
19719 mcpu_cpu_opt
= march_cpu_opt
;
19724 as_bad (_("use of old and new-style options to set FPU type"));
19726 mfpu_opt
= legacy_fpu
;
19728 else if (!mfpu_opt
)
19730 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
19731 /* Some environments specify a default FPU. If they don't, infer it
19732 from the processor. */
19734 mfpu_opt
= mcpu_fpu_opt
;
19736 mfpu_opt
= march_fpu_opt
;
19738 mfpu_opt
= &fpu_default
;
19744 if (mcpu_cpu_opt
!= NULL
)
19745 mfpu_opt
= &fpu_default
;
19746 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
19747 mfpu_opt
= &fpu_arch_vfp_v2
;
19749 mfpu_opt
= &fpu_arch_fpa
;
19755 mcpu_cpu_opt
= &cpu_default
;
19756 selected_cpu
= cpu_default
;
19760 selected_cpu
= *mcpu_cpu_opt
;
19762 mcpu_cpu_opt
= &arm_arch_any
;
19765 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
19767 autoselect_thumb_from_cpu_variant ();
19769 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
19771 #if defined OBJ_COFF || defined OBJ_ELF
19773 unsigned int flags
= 0;
19775 #if defined OBJ_ELF
19776 flags
= meabi_flags
;
19778 switch (meabi_flags
)
19780 case EF_ARM_EABI_UNKNOWN
:
19782 /* Set the flags in the private structure. */
19783 if (uses_apcs_26
) flags
|= F_APCS26
;
19784 if (support_interwork
) flags
|= F_INTERWORK
;
19785 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
19786 if (pic_code
) flags
|= F_PIC
;
19787 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
19788 flags
|= F_SOFT_FLOAT
;
19790 switch (mfloat_abi_opt
)
19792 case ARM_FLOAT_ABI_SOFT
:
19793 case ARM_FLOAT_ABI_SOFTFP
:
19794 flags
|= F_SOFT_FLOAT
;
19797 case ARM_FLOAT_ABI_HARD
:
19798 if (flags
& F_SOFT_FLOAT
)
19799 as_bad (_("hard-float conflicts with specified fpu"));
19803 /* Using pure-endian doubles (even if soft-float). */
19804 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
19805 flags
|= F_VFP_FLOAT
;
19807 #if defined OBJ_ELF
19808 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
19809 flags
|= EF_ARM_MAVERICK_FLOAT
;
19812 case EF_ARM_EABI_VER4
:
19813 case EF_ARM_EABI_VER5
:
19814 /* No additional flags to set. */
19821 bfd_set_private_flags (stdoutput
, flags
);
19823 /* We have run out flags in the COFF header to encode the
19824 status of ATPCS support, so instead we create a dummy,
19825 empty, debug section called .arm.atpcs. */
19830 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
19834 bfd_set_section_flags
19835 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
19836 bfd_set_section_size (stdoutput
, sec
, 0);
19837 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
19843 /* Record the CPU type as well. */
19844 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
19845 mach
= bfd_mach_arm_iWMMXt2
;
19846 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
19847 mach
= bfd_mach_arm_iWMMXt
;
19848 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
19849 mach
= bfd_mach_arm_XScale
;
19850 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
19851 mach
= bfd_mach_arm_ep9312
;
19852 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
19853 mach
= bfd_mach_arm_5TE
;
19854 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
19856 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19857 mach
= bfd_mach_arm_5T
;
19859 mach
= bfd_mach_arm_5
;
19861 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
19863 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19864 mach
= bfd_mach_arm_4T
;
19866 mach
= bfd_mach_arm_4
;
19868 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
19869 mach
= bfd_mach_arm_3M
;
19870 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
19871 mach
= bfd_mach_arm_3
;
19872 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
19873 mach
= bfd_mach_arm_2a
;
19874 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
19875 mach
= bfd_mach_arm_2
;
19877 mach
= bfd_mach_arm_unknown
;
19879 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
19882 /* Command line processing. */
19885 Invocation line includes a switch not recognized by the base assembler.
19886 See if it's a processor-specific option.
19888 This routine is somewhat complicated by the need for backwards
19889 compatibility (since older releases of gcc can't be changed).
19890 The new options try to make the interface as compatible as
19893 New options (supported) are:
19895 -mcpu=<cpu name> Assemble for selected processor
19896 -march=<architecture name> Assemble for selected architecture
19897 -mfpu=<fpu architecture> Assemble for selected FPU.
19898 -EB/-mbig-endian Big-endian
19899 -EL/-mlittle-endian Little-endian
19900 -k Generate PIC code
19901 -mthumb Start in Thumb mode
19902 -mthumb-interwork Code supports ARM/Thumb interworking
19904 For now we will also provide support for:
19906 -mapcs-32 32-bit Program counter
19907 -mapcs-26 26-bit Program counter
19908 -macps-float Floats passed in FP registers
19909 -mapcs-reentrant Reentrant code
19911 (sometime these will probably be replaced with -mapcs=<list of options>
19912 and -matpcs=<list of options>)
19914 The remaining options are only supported for back-wards compatibility.
19915 Cpu variants, the arm part is optional:
19916 -m[arm]1 Currently not supported.
19917 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
19918 -m[arm]3 Arm 3 processor
19919 -m[arm]6[xx], Arm 6 processors
19920 -m[arm]7[xx][t][[d]m] Arm 7 processors
19921 -m[arm]8[10] Arm 8 processors
19922 -m[arm]9[20][tdmi] Arm 9 processors
19923 -mstrongarm[110[0]] StrongARM processors
19924 -mxscale XScale processors
19925 -m[arm]v[2345[t[e]]] Arm architectures
19926 -mall All (except the ARM1)
19928 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
19929 -mfpe-old (No float load/store multiples)
19930 -mvfpxd VFP Single precision
19932 -mno-fpu Disable all floating point instructions
19934 The following CPU names are recognized:
19935 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
19936 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
19937 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
19938 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
19939 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
19940 arm10t arm10e, arm1020t, arm1020e, arm10200e,
19941 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
19945 const char * md_shortopts
= "m:k";
19947 #ifdef ARM_BI_ENDIAN
19948 #define OPTION_EB (OPTION_MD_BASE + 0)
19949 #define OPTION_EL (OPTION_MD_BASE + 1)
19951 #if TARGET_BYTES_BIG_ENDIAN
19952 #define OPTION_EB (OPTION_MD_BASE + 0)
19954 #define OPTION_EL (OPTION_MD_BASE + 1)
19957 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
19959 struct option md_longopts
[] =
19962 {"EB", no_argument
, NULL
, OPTION_EB
},
19965 {"EL", no_argument
, NULL
, OPTION_EL
},
19967 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
19968 {NULL
, no_argument
, NULL
, 0}
19971 size_t md_longopts_size
= sizeof (md_longopts
);
19973 struct arm_option_table
19975 char *option
; /* Option name to match. */
19976 char *help
; /* Help information. */
19977 int *var
; /* Variable to change. */
19978 int value
; /* What to change it to. */
19979 char *deprecated
; /* If non-null, print this message. */
19982 struct arm_option_table arm_opts
[] =
19984 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
19985 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
19986 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
19987 &support_interwork
, 1, NULL
},
19988 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
19989 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
19990 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
19992 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
19993 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
19994 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
19995 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
19998 /* These are recognized by the assembler, but have no affect on code. */
19999 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
20000 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
20001 {NULL
, NULL
, NULL
, 0, NULL
}
20004 struct arm_legacy_option_table
20006 char *option
; /* Option name to match. */
20007 const arm_feature_set
**var
; /* Variable to change. */
20008 const arm_feature_set value
; /* What to change it to. */
20009 char *deprecated
; /* If non-null, print this message. */
20012 const struct arm_legacy_option_table arm_legacy_opts
[] =
20014 /* DON'T add any new processors to this list -- we want the whole list
20015 to go away... Add them to the processors table instead. */
20016 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
20017 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
20018 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
20019 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
20020 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
20021 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
20022 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
20023 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
20024 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
20025 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
20026 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
20027 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
20028 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
20029 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
20030 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
20031 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
20032 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
20033 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
20034 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
20035 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
20036 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
20037 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
20038 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
20039 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
20040 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
20041 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
20042 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
20043 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
20044 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
20045 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
20046 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
20047 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
20048 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
20049 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
20050 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
20051 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
20052 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
20053 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
20054 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
20055 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
20056 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
20057 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
20058 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
20059 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
20060 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
20061 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
20062 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
20063 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
20064 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
20065 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
20066 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
20067 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
20068 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
20069 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
20070 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
20071 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
20072 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
20073 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
20074 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
20075 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
20076 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
20077 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
20078 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
20079 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
20080 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
20081 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
20082 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
20083 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
20084 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
20085 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
20086 N_("use -mcpu=strongarm110")},
20087 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
20088 N_("use -mcpu=strongarm1100")},
20089 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
20090 N_("use -mcpu=strongarm1110")},
20091 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
20092 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
20093 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
20095 /* Architecture variants -- don't add any more to this list either. */
20096 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
20097 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
20098 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
20099 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
20100 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
20101 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
20102 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
20103 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
20104 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
20105 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
20106 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
20107 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
20108 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
20109 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
20110 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
20111 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
20112 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
20113 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
20115 /* Floating point variants -- don't add any more to this list either. */
20116 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
20117 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
20118 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
20119 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
20120 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
20122 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
20125 struct arm_cpu_option_table
20128 const arm_feature_set value
;
20129 /* For some CPUs we assume an FPU unless the user explicitly sets
20131 const arm_feature_set default_fpu
;
20132 /* The canonical name of the CPU, or NULL to use NAME converted to upper
20134 const char *canonical_name
;
20137 /* This list should, at a minimum, contain all the cpu names
20138 recognized by GCC. */
20139 static const struct arm_cpu_option_table arm_cpus
[] =
20141 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
20142 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
20143 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
20144 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
20145 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
20146 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20147 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20148 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20149 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20150 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20151 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20152 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20153 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20154 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20155 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20156 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20157 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20158 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20159 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20160 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20161 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20162 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20163 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20164 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20165 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20166 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20167 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20168 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20169 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20170 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20171 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20172 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20173 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20174 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20175 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20176 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20177 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20178 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20179 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20180 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
20181 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20182 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20183 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20184 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20185 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20186 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20187 /* For V5 or later processors we default to using VFP; but the user
20188 should really set the FPU type explicitly. */
20189 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20190 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20191 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
20192 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
20193 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
20194 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20195 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
20196 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20197 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20198 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
20199 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20200 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20201 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20202 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20203 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20204 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
20205 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20206 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20207 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20208 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
20209 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
20210 {"fa626te", ARM_ARCH_V5TE
, FPU_NONE
, NULL
},
20211 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20212 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
20213 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
20214 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
20215 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
20216 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
20217 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
20218 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
20219 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
20220 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
20221 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
20222 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE(0, FPU_VFP_V3
20223 | FPU_NEON_EXT_V1
),
20225 {"cortex-a9", ARM_ARCH_V7A
, ARM_FEATURE(0, FPU_VFP_V3
20226 | FPU_NEON_EXT_V1
),
20228 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
20229 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
20230 {"cortex-m1", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
20231 /* ??? XSCALE is really an architecture. */
20232 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
20233 /* ??? iwmmxt is not a processor. */
20234 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
20235 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
20236 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
20238 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
20239 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
20242 struct arm_arch_option_table
20245 const arm_feature_set value
;
20246 const arm_feature_set default_fpu
;
20249 /* This list should, at a minimum, contain all the architecture names
20250 recognized by GCC. */
20251 static const struct arm_arch_option_table arm_archs
[] =
20253 {"all", ARM_ANY
, FPU_ARCH_FPA
},
20254 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
20255 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
20256 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
20257 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
20258 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
20259 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
20260 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
20261 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
20262 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
20263 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
20264 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
20265 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
20266 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
20267 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
20268 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
20269 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
20270 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
20271 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
20272 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
20273 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
20274 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
20275 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
20276 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
20277 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
20278 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
20279 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
20280 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
20281 /* The official spelling of the ARMv7 profile variants is the dashed form.
20282 Accept the non-dashed form for compatibility with old toolchains. */
20283 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
20284 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
20285 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
20286 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
20287 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
20288 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
20289 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
20290 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
20291 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
20292 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
20295 /* ISA extensions in the co-processor space. */
20296 struct arm_option_cpu_value_table
20299 const arm_feature_set value
;
20302 static const struct arm_option_cpu_value_table arm_extensions
[] =
20304 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
20305 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
20306 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
20307 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
20308 {NULL
, ARM_ARCH_NONE
}
20311 /* This list should, at a minimum, contain all the fpu names
20312 recognized by GCC. */
20313 static const struct arm_option_cpu_value_table arm_fpus
[] =
20315 {"softfpa", FPU_NONE
},
20316 {"fpe", FPU_ARCH_FPE
},
20317 {"fpe2", FPU_ARCH_FPE
},
20318 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
20319 {"fpa", FPU_ARCH_FPA
},
20320 {"fpa10", FPU_ARCH_FPA
},
20321 {"fpa11", FPU_ARCH_FPA
},
20322 {"arm7500fe", FPU_ARCH_FPA
},
20323 {"softvfp", FPU_ARCH_VFP
},
20324 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
20325 {"vfp", FPU_ARCH_VFP_V2
},
20326 {"vfp9", FPU_ARCH_VFP_V2
},
20327 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
20328 {"vfp10", FPU_ARCH_VFP_V2
},
20329 {"vfp10-r0", FPU_ARCH_VFP_V1
},
20330 {"vfpxd", FPU_ARCH_VFP_V1xD
},
20331 {"vfpv2", FPU_ARCH_VFP_V2
},
20332 {"vfpv3", FPU_ARCH_VFP_V3
},
20333 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
20334 {"arm1020t", FPU_ARCH_VFP_V1
},
20335 {"arm1020e", FPU_ARCH_VFP_V2
},
20336 {"arm1136jfs", FPU_ARCH_VFP_V2
},
20337 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
20338 {"maverick", FPU_ARCH_MAVERICK
},
20339 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
20340 {"neon-fp16", FPU_ARCH_NEON_FP16
},
20341 {NULL
, ARM_ARCH_NONE
}
20344 struct arm_option_value_table
20350 static const struct arm_option_value_table arm_float_abis
[] =
20352 {"hard", ARM_FLOAT_ABI_HARD
},
20353 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
20354 {"soft", ARM_FLOAT_ABI_SOFT
},
20359 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
20360 static const struct arm_option_value_table arm_eabis
[] =
20362 {"gnu", EF_ARM_EABI_UNKNOWN
},
20363 {"4", EF_ARM_EABI_VER4
},
20364 {"5", EF_ARM_EABI_VER5
},
20369 struct arm_long_option_table
20371 char * option
; /* Substring to match. */
20372 char * help
; /* Help information. */
20373 int (* func
) (char * subopt
); /* Function to decode sub-option. */
20374 char * deprecated
; /* If non-null, print this message. */
20378 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
20380 arm_feature_set
*ext_set
= xmalloc (sizeof (arm_feature_set
));
20382 /* Copy the feature set, so that we can modify it. */
20383 *ext_set
= **opt_p
;
20386 while (str
!= NULL
&& *str
!= 0)
20388 const struct arm_option_cpu_value_table
* opt
;
20394 as_bad (_("invalid architectural extension"));
20399 ext
= strchr (str
, '+');
20402 optlen
= ext
- str
;
20404 optlen
= strlen (str
);
20408 as_bad (_("missing architectural extension"));
20412 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
20413 if (strncmp (opt
->name
, str
, optlen
) == 0)
20415 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
20419 if (opt
->name
== NULL
)
20421 as_bad (_("unknown architectural extension `%s'"), str
);
20432 arm_parse_cpu (char * str
)
20434 const struct arm_cpu_option_table
* opt
;
20435 char * ext
= strchr (str
, '+');
20439 optlen
= ext
- str
;
20441 optlen
= strlen (str
);
20445 as_bad (_("missing cpu name `%s'"), str
);
20449 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
20450 if (strncmp (opt
->name
, str
, optlen
) == 0)
20452 mcpu_cpu_opt
= &opt
->value
;
20453 mcpu_fpu_opt
= &opt
->default_fpu
;
20454 if (opt
->canonical_name
)
20455 strcpy (selected_cpu_name
, opt
->canonical_name
);
20459 for (i
= 0; i
< optlen
; i
++)
20460 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20461 selected_cpu_name
[i
] = 0;
20465 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
20470 as_bad (_("unknown cpu `%s'"), str
);
20475 arm_parse_arch (char * str
)
20477 const struct arm_arch_option_table
*opt
;
20478 char *ext
= strchr (str
, '+');
20482 optlen
= ext
- str
;
20484 optlen
= strlen (str
);
20488 as_bad (_("missing architecture name `%s'"), str
);
20492 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
20493 if (streq (opt
->name
, str
))
20495 march_cpu_opt
= &opt
->value
;
20496 march_fpu_opt
= &opt
->default_fpu
;
20497 strcpy (selected_cpu_name
, opt
->name
);
20500 return arm_parse_extension (ext
, &march_cpu_opt
);
20505 as_bad (_("unknown architecture `%s'\n"), str
);
20510 arm_parse_fpu (char * str
)
20512 const struct arm_option_cpu_value_table
* opt
;
20514 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
20515 if (streq (opt
->name
, str
))
20517 mfpu_opt
= &opt
->value
;
20521 as_bad (_("unknown floating point format `%s'\n"), str
);
20526 arm_parse_float_abi (char * str
)
20528 const struct arm_option_value_table
* opt
;
20530 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
20531 if (streq (opt
->name
, str
))
20533 mfloat_abi_opt
= opt
->value
;
20537 as_bad (_("unknown floating point abi `%s'\n"), str
);
20543 arm_parse_eabi (char * str
)
20545 const struct arm_option_value_table
*opt
;
20547 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
20548 if (streq (opt
->name
, str
))
20550 meabi_flags
= opt
->value
;
20553 as_bad (_("unknown EABI `%s'\n"), str
);
20558 struct arm_long_option_table arm_long_opts
[] =
20560 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
20561 arm_parse_cpu
, NULL
},
20562 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
20563 arm_parse_arch
, NULL
},
20564 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
20565 arm_parse_fpu
, NULL
},
20566 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
20567 arm_parse_float_abi
, NULL
},
20569 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
20570 arm_parse_eabi
, NULL
},
20572 {NULL
, NULL
, 0, NULL
}
20576 md_parse_option (int c
, char * arg
)
20578 struct arm_option_table
*opt
;
20579 const struct arm_legacy_option_table
*fopt
;
20580 struct arm_long_option_table
*lopt
;
20586 target_big_endian
= 1;
20592 target_big_endian
= 0;
20596 case OPTION_FIX_V4BX
:
20601 /* Listing option. Just ignore these, we don't support additional
20606 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
20608 if (c
== opt
->option
[0]
20609 && ((arg
== NULL
&& opt
->option
[1] == 0)
20610 || streq (arg
, opt
->option
+ 1)))
20612 #if WARN_DEPRECATED
20613 /* If the option is deprecated, tell the user. */
20614 if (opt
->deprecated
!= NULL
)
20615 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
20616 arg
? arg
: "", _(opt
->deprecated
));
20619 if (opt
->var
!= NULL
)
20620 *opt
->var
= opt
->value
;
20626 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
20628 if (c
== fopt
->option
[0]
20629 && ((arg
== NULL
&& fopt
->option
[1] == 0)
20630 || streq (arg
, fopt
->option
+ 1)))
20632 #if WARN_DEPRECATED
20633 /* If the option is deprecated, tell the user. */
20634 if (fopt
->deprecated
!= NULL
)
20635 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
20636 arg
? arg
: "", _(fopt
->deprecated
));
20639 if (fopt
->var
!= NULL
)
20640 *fopt
->var
= &fopt
->value
;
20646 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
20648 /* These options are expected to have an argument. */
20649 if (c
== lopt
->option
[0]
20651 && strncmp (arg
, lopt
->option
+ 1,
20652 strlen (lopt
->option
+ 1)) == 0)
20654 #if WARN_DEPRECATED
20655 /* If the option is deprecated, tell the user. */
20656 if (lopt
->deprecated
!= NULL
)
20657 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
20658 _(lopt
->deprecated
));
20661 /* Call the sup-option parser. */
20662 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
20673 md_show_usage (FILE * fp
)
20675 struct arm_option_table
*opt
;
20676 struct arm_long_option_table
*lopt
;
20678 fprintf (fp
, _(" ARM-specific assembler options:\n"));
20680 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
20681 if (opt
->help
!= NULL
)
20682 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
20684 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
20685 if (lopt
->help
!= NULL
)
20686 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
20690 -EB assemble code for a big-endian cpu\n"));
20695 -EL assemble code for a little-endian cpu\n"));
20699 --fix-v4bx Allow BX in ARMv4 code\n"));
20707 arm_feature_set flags
;
20708 } cpu_arch_ver_table
;
20710 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
20711 least features first. */
20712 static const cpu_arch_ver_table cpu_arch_ver
[] =
20717 {4, ARM_ARCH_V5TE
},
20718 {5, ARM_ARCH_V5TEJ
},
20723 {8, ARM_ARCH_V6T2
},
20724 {10, ARM_ARCH_V7A
},
20725 {10, ARM_ARCH_V7R
},
20726 {10, ARM_ARCH_V7M
},
20730 /* Set the public EABI object attributes. */
20732 aeabi_set_public_attributes (void)
20735 arm_feature_set flags
;
20736 arm_feature_set tmp
;
20737 const cpu_arch_ver_table
*p
;
20739 /* Choose the architecture based on the capabilities of the requested cpu
20740 (if any) and/or the instructions actually used. */
20741 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
20742 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
20743 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
20744 /*Allow the user to override the reported architecture. */
20747 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
20748 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
20753 for (p
= cpu_arch_ver
; p
->val
; p
++)
20755 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
20758 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
20762 /* Tag_CPU_name. */
20763 if (selected_cpu_name
[0])
20767 p
= selected_cpu_name
;
20768 if (strncmp (p
, "armv", 4) == 0)
20773 for (i
= 0; p
[i
]; i
++)
20774 p
[i
] = TOUPPER (p
[i
]);
20776 bfd_elf_add_proc_attr_string (stdoutput
, 5, p
);
20778 /* Tag_CPU_arch. */
20779 bfd_elf_add_proc_attr_int (stdoutput
, 6, arch
);
20780 /* Tag_CPU_arch_profile. */
20781 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
20782 bfd_elf_add_proc_attr_int (stdoutput
, 7, 'A');
20783 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
20784 bfd_elf_add_proc_attr_int (stdoutput
, 7, 'R');
20785 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
20786 bfd_elf_add_proc_attr_int (stdoutput
, 7, 'M');
20787 /* Tag_ARM_ISA_use. */
20788 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_full
))
20789 bfd_elf_add_proc_attr_int (stdoutput
, 8, 1);
20790 /* Tag_THUMB_ISA_use. */
20791 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_full
))
20792 bfd_elf_add_proc_attr_int (stdoutput
, 9,
20793 ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
) ? 2 : 1);
20794 /* Tag_VFP_arch. */
20795 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_d32
)
20796 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_d32
))
20797 bfd_elf_add_proc_attr_int (stdoutput
, 10, 4);
20798 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v3
)
20799 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v3
))
20800 bfd_elf_add_proc_attr_int (stdoutput
, 10, 3);
20801 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v2
)
20802 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v2
))
20803 bfd_elf_add_proc_attr_int (stdoutput
, 10, 2);
20804 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1
)
20805 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1
)
20806 || ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1xd
)
20807 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1xd
))
20808 bfd_elf_add_proc_attr_int (stdoutput
, 10, 1);
20809 /* Tag_WMMX_arch. */
20810 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_cext_iwmmxt
)
20811 || ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_cext_iwmmxt
))
20812 bfd_elf_add_proc_attr_int (stdoutput
, 11, 1);
20813 /* Tag_NEON_arch. */
20814 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
20815 bfd_elf_add_proc_attr_int (stdoutput
, 12, 1);
20816 /* Tag_NEON_FP16_arch. */
20817 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_fp16
))
20818 bfd_elf_add_proc_attr_int (stdoutput
, 36, 1);
20821 /* Add the default contents for the .ARM.attributes section. */
20825 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
20828 aeabi_set_public_attributes ();
20830 #endif /* OBJ_ELF */
20833 /* Parse a .cpu directive. */
20836 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
20838 const struct arm_cpu_option_table
*opt
;
20842 name
= input_line_pointer
;
20843 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20844 input_line_pointer
++;
20845 saved_char
= *input_line_pointer
;
20846 *input_line_pointer
= 0;
20848 /* Skip the first "all" entry. */
20849 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
20850 if (streq (opt
->name
, name
))
20852 mcpu_cpu_opt
= &opt
->value
;
20853 selected_cpu
= opt
->value
;
20854 if (opt
->canonical_name
)
20855 strcpy (selected_cpu_name
, opt
->canonical_name
);
20859 for (i
= 0; opt
->name
[i
]; i
++)
20860 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20861 selected_cpu_name
[i
] = 0;
20863 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20864 *input_line_pointer
= saved_char
;
20865 demand_empty_rest_of_line ();
20868 as_bad (_("unknown cpu `%s'"), name
);
20869 *input_line_pointer
= saved_char
;
20870 ignore_rest_of_line ();
20874 /* Parse a .arch directive. */
20877 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
20879 const struct arm_arch_option_table
*opt
;
20883 name
= input_line_pointer
;
20884 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20885 input_line_pointer
++;
20886 saved_char
= *input_line_pointer
;
20887 *input_line_pointer
= 0;
20889 /* Skip the first "all" entry. */
20890 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
20891 if (streq (opt
->name
, name
))
20893 mcpu_cpu_opt
= &opt
->value
;
20894 selected_cpu
= opt
->value
;
20895 strcpy (selected_cpu_name
, opt
->name
);
20896 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20897 *input_line_pointer
= saved_char
;
20898 demand_empty_rest_of_line ();
20902 as_bad (_("unknown architecture `%s'\n"), name
);
20903 *input_line_pointer
= saved_char
;
20904 ignore_rest_of_line ();
20908 /* Parse a .object_arch directive. */
20911 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
20913 const struct arm_arch_option_table
*opt
;
20917 name
= input_line_pointer
;
20918 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20919 input_line_pointer
++;
20920 saved_char
= *input_line_pointer
;
20921 *input_line_pointer
= 0;
20923 /* Skip the first "all" entry. */
20924 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
20925 if (streq (opt
->name
, name
))
20927 object_arch
= &opt
->value
;
20928 *input_line_pointer
= saved_char
;
20929 demand_empty_rest_of_line ();
20933 as_bad (_("unknown architecture `%s'\n"), name
);
20934 *input_line_pointer
= saved_char
;
20935 ignore_rest_of_line ();
20939 /* Parse a .fpu directive. */
20942 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
20944 const struct arm_option_cpu_value_table
*opt
;
20948 name
= input_line_pointer
;
20949 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20950 input_line_pointer
++;
20951 saved_char
= *input_line_pointer
;
20952 *input_line_pointer
= 0;
20954 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
20955 if (streq (opt
->name
, name
))
20957 mfpu_opt
= &opt
->value
;
20958 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20959 *input_line_pointer
= saved_char
;
20960 demand_empty_rest_of_line ();
20964 as_bad (_("unknown floating point format `%s'\n"), name
);
20965 *input_line_pointer
= saved_char
;
20966 ignore_rest_of_line ();
20969 /* Copy symbol information. */
20971 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
20973 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);