1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
45 #define WARN_DEPRECATED 1
48 /* Must be at least the size of the largest unwind opcode (currently two). */
49 #define ARM_OPCODE_CHUNK_SIZE 8
51 /* This structure holds the unwinding state. */
56 symbolS
* table_entry
;
57 symbolS
* personality_routine
;
58 int personality_index
;
59 /* The segment containing the function. */
62 /* Opcodes generated from this function. */
63 unsigned char * opcodes
;
66 /* The number of bytes pushed to the stack. */
68 /* We don't add stack adjustment opcodes immediately so that we can merge
69 multiple adjustments. We can also omit the final adjustment
70 when using a frame pointer. */
71 offsetT pending_offset
;
72 /* These two fields are set by both unwind_movsp and unwind_setfp. They
73 hold the reg+offset to use when restoring sp from a frame pointer. */
76 /* Nonzero if an unwind_setfp directive has been seen. */
78 /* Nonzero if the last opcode restores sp from fp_reg. */
79 unsigned sp_restored
:1;
82 /* Bit N indicates that an R_ARM_NONE relocation has been output for
83 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
84 emitted only once per section, to save unnecessary bloat. */
85 static unsigned int marked_pr_dependency
= 0;
89 /* Results from operand parsing worker functions. */
93 PARSE_OPERAND_SUCCESS
,
95 PARSE_OPERAND_FAIL_NO_BACKTRACK
96 } parse_operand_result
;
101 ARM_FLOAT_ABI_SOFTFP
,
105 /* Types of processor to assemble for. */
107 #if defined __XSCALE__
108 #define CPU_DEFAULT ARM_ARCH_XSCALE
110 #if defined __thumb__
111 #define CPU_DEFAULT ARM_ARCH_V5T
118 # define FPU_DEFAULT FPU_ARCH_FPA
119 # elif defined (TE_NetBSD)
121 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
123 /* Legacy a.out format. */
124 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
126 # elif defined (TE_VXWORKS)
127 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
129 /* For backwards compatibility, default to FPA. */
130 # define FPU_DEFAULT FPU_ARCH_FPA
132 #endif /* ifndef FPU_DEFAULT */
134 #define streq(a, b) (strcmp (a, b) == 0)
136 static arm_feature_set cpu_variant
;
137 static arm_feature_set arm_arch_used
;
138 static arm_feature_set thumb_arch_used
;
140 /* Flags stored in private area of BFD structure. */
141 static int uses_apcs_26
= FALSE
;
142 static int atpcs
= FALSE
;
143 static int support_interwork
= FALSE
;
144 static int uses_apcs_float
= FALSE
;
145 static int pic_code
= FALSE
;
147 /* Variables that we set while parsing command-line options. Once all
148 options have been read we re-process these values to set the real
150 static const arm_feature_set
*legacy_cpu
= NULL
;
151 static const arm_feature_set
*legacy_fpu
= NULL
;
153 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
154 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
155 static const arm_feature_set
*march_cpu_opt
= NULL
;
156 static const arm_feature_set
*march_fpu_opt
= NULL
;
157 static const arm_feature_set
*mfpu_opt
= NULL
;
159 /* Constants for known architecture features. */
160 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
161 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
162 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
163 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
164 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
165 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
166 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
167 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
168 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
171 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
174 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
175 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
176 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
177 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
178 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
179 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
180 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
181 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
182 static const arm_feature_set arm_ext_v4t_5
=
183 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
184 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
185 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
186 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
187 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
188 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
189 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
190 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
191 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
192 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
199 static const arm_feature_set arm_arch_any
= ARM_ANY
;
200 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
201 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
202 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
204 static const arm_feature_set arm_cext_iwmmxt2
=
205 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
206 static const arm_feature_set arm_cext_iwmmxt
=
207 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
208 static const arm_feature_set arm_cext_xscale
=
209 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
210 static const arm_feature_set arm_cext_maverick
=
211 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
212 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
213 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
214 static const arm_feature_set fpu_vfp_ext_v1xd
=
215 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
216 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
217 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
218 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
219 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
220 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
221 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
223 static int mfloat_abi_opt
= -1;
224 /* Record user cpu selection for object attributes. */
225 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
226 /* Must be long enough to hold any of the names in arm_cpus. */
227 static char selected_cpu_name
[16];
230 static int meabi_flags
= EABI_DEFAULT
;
232 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
237 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
238 symbolS
* GOT_symbol
;
241 /* 0: assemble for ARM,
242 1: assemble for Thumb,
243 2: assemble for Thumb even though target CPU does not support thumb
245 static int thumb_mode
= 0;
247 /* If unified_syntax is true, we are processing the new unified
248 ARM/Thumb syntax. Important differences from the old ARM mode:
250 - Immediate operands do not require a # prefix.
251 - Conditional affixes always appear at the end of the
252 instruction. (For backward compatibility, those instructions
253 that formerly had them in the middle, continue to accept them
255 - The IT instruction may appear, and if it does is validated
256 against subsequent conditional affixes. It does not generate
259 Important differences from the old Thumb mode:
261 - Immediate operands do not require a # prefix.
262 - Most of the V6T2 instructions are only available in unified mode.
263 - The .N and .W suffixes are recognized and honored (it is an error
264 if they cannot be honored).
265 - All instructions set the flags if and only if they have an 's' affix.
266 - Conditional affixes may be used. They are validated against
267 preceding IT instructions. Unlike ARM mode, you cannot use a
268 conditional affix except in the scope of an IT instruction. */
270 static bfd_boolean unified_syntax
= FALSE
;
285 enum neon_el_type type
;
289 #define NEON_MAX_TYPE_ELS 4
293 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
300 unsigned long instruction
;
304 /* "uncond_value" is set to the value in place of the conditional field in
305 unconditional versions of the instruction, or -1 if nothing is
308 struct neon_type vectype
;
309 /* Set to the opcode if the instruction needs relaxation.
310 Zero if the instruction is not relaxed. */
314 bfd_reloc_code_real_type type
;
323 struct neon_type_el vectype
;
324 unsigned present
: 1; /* Operand present. */
325 unsigned isreg
: 1; /* Operand was a register. */
326 unsigned immisreg
: 1; /* .imm field is a second register. */
327 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
328 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
329 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
330 instructions. This allows us to disambiguate ARM <-> vector insns. */
331 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
332 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
333 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
334 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
335 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
336 unsigned writeback
: 1; /* Operand has trailing ! */
337 unsigned preind
: 1; /* Preindexed address. */
338 unsigned postind
: 1; /* Postindexed address. */
339 unsigned negative
: 1; /* Index register was negated. */
340 unsigned shifted
: 1; /* Shift applied to operation. */
341 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
345 static struct arm_it inst
;
347 #define NUM_FLOAT_VALS 8
349 const char * fp_const
[] =
351 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
354 /* Number of littlenums required to hold an extended precision number. */
355 #define MAX_LITTLENUMS 6
357 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
367 #define CP_T_X 0x00008000
368 #define CP_T_Y 0x00400000
370 #define CONDS_BIT 0x00100000
371 #define LOAD_BIT 0x00100000
373 #define DOUBLE_LOAD_FLAG 0x00000001
377 const char * template;
381 #define COND_ALWAYS 0xE
385 const char *template;
389 struct asm_barrier_opt
391 const char *template;
395 /* The bit that distinguishes CPSR and SPSR. */
396 #define SPSR_BIT (1 << 22)
398 /* The individual PSR flag bits. */
399 #define PSR_c (1 << 16)
400 #define PSR_x (1 << 17)
401 #define PSR_s (1 << 18)
402 #define PSR_f (1 << 19)
407 bfd_reloc_code_real_type reloc
;
412 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
413 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
418 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
421 /* Bits for DEFINED field in neon_typed_alias. */
422 #define NTA_HASTYPE 1
423 #define NTA_HASINDEX 2
425 struct neon_typed_alias
427 unsigned char defined
;
429 struct neon_type_el eltype
;
432 /* ARM register categories. This includes coprocessor numbers and various
433 architecture extensions' registers. */
459 /* Structure for a hash table entry for a register.
460 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
461 information which states whether a vector type or index is specified (for a
462 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
466 unsigned char number
;
468 unsigned char builtin
;
469 struct neon_typed_alias
*neon
;
472 /* Diagnostics used when we don't get a register of the expected type. */
473 const char *const reg_expected_msgs
[] =
475 N_("ARM register expected"),
476 N_("bad or missing co-processor number"),
477 N_("co-processor register expected"),
478 N_("FPA register expected"),
479 N_("VFP single precision register expected"),
480 N_("VFP/Neon double precision register expected"),
481 N_("Neon quad precision register expected"),
482 N_("VFP single or double precision register expected"),
483 N_("Neon double or quad precision register expected"),
484 N_("VFP single, double or Neon quad precision register expected"),
485 N_("VFP system register expected"),
486 N_("Maverick MVF register expected"),
487 N_("Maverick MVD register expected"),
488 N_("Maverick MVFX register expected"),
489 N_("Maverick MVDX register expected"),
490 N_("Maverick MVAX register expected"),
491 N_("Maverick DSPSC register expected"),
492 N_("iWMMXt data register expected"),
493 N_("iWMMXt control register expected"),
494 N_("iWMMXt scalar register expected"),
495 N_("XScale accumulator register expected"),
498 /* Some well known registers that we refer to directly elsewhere. */
503 /* ARM instructions take 4bytes in the object file, Thumb instructions
509 /* Basic string to match. */
510 const char *template;
512 /* Parameters to instruction. */
513 unsigned char operands
[8];
515 /* Conditional tag - see opcode_lookup. */
516 unsigned int tag
: 4;
518 /* Basic instruction code. */
519 unsigned int avalue
: 28;
521 /* Thumb-format instruction code. */
524 /* Which architecture variant provides this instruction. */
525 const arm_feature_set
*avariant
;
526 const arm_feature_set
*tvariant
;
528 /* Function to call to encode instruction in ARM format. */
529 void (* aencode
) (void);
531 /* Function to call to encode instruction in Thumb format. */
532 void (* tencode
) (void);
535 /* Defines for various bits that we will want to toggle. */
536 #define INST_IMMEDIATE 0x02000000
537 #define OFFSET_REG 0x02000000
538 #define HWOFFSET_IMM 0x00400000
539 #define SHIFT_BY_REG 0x00000010
540 #define PRE_INDEX 0x01000000
541 #define INDEX_UP 0x00800000
542 #define WRITE_BACK 0x00200000
543 #define LDM_TYPE_2_OR_3 0x00400000
545 #define LITERAL_MASK 0xf000f000
546 #define OPCODE_MASK 0xfe1fffff
547 #define V4_STR_BIT 0x00000020
549 #define DATA_OP_SHIFT 21
551 #define T2_OPCODE_MASK 0xfe1fffff
552 #define T2_DATA_OP_SHIFT 21
554 /* Codes to distinguish the arithmetic instructions. */
565 #define OPCODE_CMP 10
566 #define OPCODE_CMN 11
567 #define OPCODE_ORR 12
568 #define OPCODE_MOV 13
569 #define OPCODE_BIC 14
570 #define OPCODE_MVN 15
572 #define T2_OPCODE_AND 0
573 #define T2_OPCODE_BIC 1
574 #define T2_OPCODE_ORR 2
575 #define T2_OPCODE_ORN 3
576 #define T2_OPCODE_EOR 4
577 #define T2_OPCODE_ADD 8
578 #define T2_OPCODE_ADC 10
579 #define T2_OPCODE_SBC 11
580 #define T2_OPCODE_SUB 13
581 #define T2_OPCODE_RSB 14
583 #define T_OPCODE_MUL 0x4340
584 #define T_OPCODE_TST 0x4200
585 #define T_OPCODE_CMN 0x42c0
586 #define T_OPCODE_NEG 0x4240
587 #define T_OPCODE_MVN 0x43c0
589 #define T_OPCODE_ADD_R3 0x1800
590 #define T_OPCODE_SUB_R3 0x1a00
591 #define T_OPCODE_ADD_HI 0x4400
592 #define T_OPCODE_ADD_ST 0xb000
593 #define T_OPCODE_SUB_ST 0xb080
594 #define T_OPCODE_ADD_SP 0xa800
595 #define T_OPCODE_ADD_PC 0xa000
596 #define T_OPCODE_ADD_I8 0x3000
597 #define T_OPCODE_SUB_I8 0x3800
598 #define T_OPCODE_ADD_I3 0x1c00
599 #define T_OPCODE_SUB_I3 0x1e00
601 #define T_OPCODE_ASR_R 0x4100
602 #define T_OPCODE_LSL_R 0x4080
603 #define T_OPCODE_LSR_R 0x40c0
604 #define T_OPCODE_ROR_R 0x41c0
605 #define T_OPCODE_ASR_I 0x1000
606 #define T_OPCODE_LSL_I 0x0000
607 #define T_OPCODE_LSR_I 0x0800
609 #define T_OPCODE_MOV_I8 0x2000
610 #define T_OPCODE_CMP_I8 0x2800
611 #define T_OPCODE_CMP_LR 0x4280
612 #define T_OPCODE_MOV_HR 0x4600
613 #define T_OPCODE_CMP_HR 0x4500
615 #define T_OPCODE_LDR_PC 0x4800
616 #define T_OPCODE_LDR_SP 0x9800
617 #define T_OPCODE_STR_SP 0x9000
618 #define T_OPCODE_LDR_IW 0x6800
619 #define T_OPCODE_STR_IW 0x6000
620 #define T_OPCODE_LDR_IH 0x8800
621 #define T_OPCODE_STR_IH 0x8000
622 #define T_OPCODE_LDR_IB 0x7800
623 #define T_OPCODE_STR_IB 0x7000
624 #define T_OPCODE_LDR_RW 0x5800
625 #define T_OPCODE_STR_RW 0x5000
626 #define T_OPCODE_LDR_RH 0x5a00
627 #define T_OPCODE_STR_RH 0x5200
628 #define T_OPCODE_LDR_RB 0x5c00
629 #define T_OPCODE_STR_RB 0x5400
631 #define T_OPCODE_PUSH 0xb400
632 #define T_OPCODE_POP 0xbc00
634 #define T_OPCODE_BRANCH 0xe000
636 #define THUMB_SIZE 2 /* Size of thumb instruction. */
637 #define THUMB_PP_PC_LR 0x0100
638 #define THUMB_LOAD_BIT 0x0800
639 #define THUMB2_LOAD_BIT 0x00100000
641 #define BAD_ARGS _("bad arguments to instruction")
642 #define BAD_PC _("r15 not allowed here")
643 #define BAD_COND _("instruction cannot be conditional")
644 #define BAD_OVERLAP _("registers may not be the same")
645 #define BAD_HIREG _("lo register required")
646 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
647 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
648 #define BAD_BRANCH _("branch must be last instruction in IT block")
649 #define BAD_NOT_IT _("instruction not allowed in IT block")
650 #define BAD_FPU _("selected FPU does not support instruction")
652 static struct hash_control
*arm_ops_hsh
;
653 static struct hash_control
*arm_cond_hsh
;
654 static struct hash_control
*arm_shift_hsh
;
655 static struct hash_control
*arm_psr_hsh
;
656 static struct hash_control
*arm_v7m_psr_hsh
;
657 static struct hash_control
*arm_reg_hsh
;
658 static struct hash_control
*arm_reloc_hsh
;
659 static struct hash_control
*arm_barrier_opt_hsh
;
661 /* Stuff needed to resolve the label ambiguity
671 symbolS
* last_label_seen
;
672 static int label_is_thumb_function_name
= FALSE
;
674 /* Literal pool structure. Held on a per-section
675 and per-sub-section basis. */
677 #define MAX_LITERAL_POOL_SIZE 1024
678 typedef struct literal_pool
680 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
681 unsigned int next_free_entry
;
686 struct literal_pool
* next
;
689 /* Pointer to a linked list of literal pools. */
690 literal_pool
* list_of_pools
= NULL
;
692 /* State variables for IT block handling. */
693 static bfd_boolean current_it_mask
= 0;
694 static int current_cc
;
699 /* This array holds the chars that always start a comment. If the
700 pre-processor is disabled, these aren't very useful. */
701 const char comment_chars
[] = "@";
703 /* This array holds the chars that only start a comment at the beginning of
704 a line. If the line seems to have the form '# 123 filename'
705 .line and .file directives will appear in the pre-processed output. */
706 /* Note that input_file.c hand checks for '#' at the beginning of the
707 first line of the input file. This is because the compiler outputs
708 #NO_APP at the beginning of its output. */
709 /* Also note that comments like this one will always work. */
710 const char line_comment_chars
[] = "#";
712 const char line_separator_chars
[] = ";";
714 /* Chars that can be used to separate mant
715 from exp in floating point numbers. */
716 const char EXP_CHARS
[] = "eE";
718 /* Chars that mean this number is a floating point constant. */
722 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
724 /* Prefix characters that indicate the start of an immediate
726 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
728 /* Separator character handling. */
730 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
733 skip_past_char (char ** str
, char c
)
743 #define skip_past_comma(str) skip_past_char (str, ',')
745 /* Arithmetic expressions (possibly involving symbols). */
747 /* Return TRUE if anything in the expression is a bignum. */
750 walk_no_bignums (symbolS
* sp
)
752 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
755 if (symbol_get_value_expression (sp
)->X_add_symbol
)
757 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
758 || (symbol_get_value_expression (sp
)->X_op_symbol
759 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
765 static int in_my_get_expression
= 0;
767 /* Third argument to my_get_expression. */
768 #define GE_NO_PREFIX 0
769 #define GE_IMM_PREFIX 1
770 #define GE_OPT_PREFIX 2
771 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
772 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
773 #define GE_OPT_PREFIX_BIG 3
776 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
781 /* In unified syntax, all prefixes are optional. */
783 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
788 case GE_NO_PREFIX
: break;
790 if (!is_immediate_prefix (**str
))
792 inst
.error
= _("immediate expression requires a # prefix");
798 case GE_OPT_PREFIX_BIG
:
799 if (is_immediate_prefix (**str
))
805 memset (ep
, 0, sizeof (expressionS
));
807 save_in
= input_line_pointer
;
808 input_line_pointer
= *str
;
809 in_my_get_expression
= 1;
810 seg
= expression (ep
);
811 in_my_get_expression
= 0;
813 if (ep
->X_op
== O_illegal
)
815 /* We found a bad expression in md_operand(). */
816 *str
= input_line_pointer
;
817 input_line_pointer
= save_in
;
818 if (inst
.error
== NULL
)
819 inst
.error
= _("bad expression");
824 if (seg
!= absolute_section
825 && seg
!= text_section
826 && seg
!= data_section
827 && seg
!= bss_section
828 && seg
!= undefined_section
)
830 inst
.error
= _("bad segment");
831 *str
= input_line_pointer
;
832 input_line_pointer
= save_in
;
837 /* Get rid of any bignums now, so that we don't generate an error for which
838 we can't establish a line number later on. Big numbers are never valid
839 in instructions, which is where this routine is always called. */
840 if (prefix_mode
!= GE_OPT_PREFIX_BIG
841 && (ep
->X_op
== O_big
843 && (walk_no_bignums (ep
->X_add_symbol
)
845 && walk_no_bignums (ep
->X_op_symbol
))))))
847 inst
.error
= _("invalid constant");
848 *str
= input_line_pointer
;
849 input_line_pointer
= save_in
;
853 *str
= input_line_pointer
;
854 input_line_pointer
= save_in
;
858 /* Turn a string in input_line_pointer into a floating point constant
859 of type TYPE, and store the appropriate bytes in *LITP. The number
860 of LITTLENUMS emitted is stored in *SIZEP. An error message is
861 returned, or NULL on OK.
863 Note that fp constants aren't represent in the normal way on the ARM.
864 In big endian mode, things are as expected. However, in little endian
865 mode fp constants are big-endian word-wise, and little-endian byte-wise
866 within the words. For example, (double) 1.1 in big endian mode is
867 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
868 the byte sequence 99 99 f1 3f 9a 99 99 99.
870 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
873 md_atof (int type
, char * litP
, int * sizeP
)
876 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
908 return _("bad call to MD_ATOF()");
911 t
= atof_ieee (input_line_pointer
, type
, words
);
913 input_line_pointer
= t
;
916 if (target_big_endian
)
918 for (i
= 0; i
< prec
; i
++)
920 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
926 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
927 for (i
= prec
- 1; i
>= 0; i
--)
929 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
933 /* For a 4 byte float the order of elements in `words' is 1 0.
934 For an 8 byte float the order is 1 0 3 2. */
935 for (i
= 0; i
< prec
; i
+= 2)
937 md_number_to_chars (litP
, (valueT
) words
[i
+ 1], 2);
938 md_number_to_chars (litP
+ 2, (valueT
) words
[i
], 2);
946 /* We handle all bad expressions here, so that we can report the faulty
947 instruction in the error message. */
949 md_operand (expressionS
* expr
)
951 if (in_my_get_expression
)
952 expr
->X_op
= O_illegal
;
955 /* Immediate values. */
957 /* Generic immediate-value read function for use in directives.
958 Accepts anything that 'expression' can fold to a constant.
959 *val receives the number. */
962 immediate_for_directive (int *val
)
965 exp
.X_op
= O_illegal
;
967 if (is_immediate_prefix (*input_line_pointer
))
969 input_line_pointer
++;
973 if (exp
.X_op
!= O_constant
)
975 as_bad (_("expected #constant"));
976 ignore_rest_of_line ();
979 *val
= exp
.X_add_number
;
984 /* Register parsing. */
986 /* Generic register parser. CCP points to what should be the
987 beginning of a register name. If it is indeed a valid register
988 name, advance CCP over it and return the reg_entry structure;
989 otherwise return NULL. Does not issue diagnostics. */
991 static struct reg_entry
*
992 arm_reg_parse_multi (char **ccp
)
996 struct reg_entry
*reg
;
998 #ifdef REGISTER_PREFIX
999 if (*start
!= REGISTER_PREFIX
)
1003 #ifdef OPTIONAL_REGISTER_PREFIX
1004 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1009 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1014 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1016 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1026 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1027 enum arm_reg_type type
)
1029 /* Alternative syntaxes are accepted for a few register classes. */
1036 /* Generic coprocessor register names are allowed for these. */
1037 if (reg
&& reg
->type
== REG_TYPE_CN
)
1042 /* For backward compatibility, a bare number is valid here. */
1044 unsigned long processor
= strtoul (start
, ccp
, 10);
1045 if (*ccp
!= start
&& processor
<= 15)
1049 case REG_TYPE_MMXWC
:
1050 /* WC includes WCG. ??? I'm not sure this is true for all
1051 instructions that take WC registers. */
1052 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1063 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1064 return value is the register number or FAIL. */
1067 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1070 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1073 /* Do not allow a scalar (reg+index) to parse as a register. */
1074 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1077 if (reg
&& reg
->type
== type
)
1080 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1087 /* Parse a Neon type specifier. *STR should point at the leading '.'
1088 character. Does no verification at this stage that the type fits the opcode
1095 Can all be legally parsed by this function.
1097 Fills in neon_type struct pointer with parsed information, and updates STR
1098 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1099 type, FAIL if not. */
1102 parse_neon_type (struct neon_type
*type
, char **str
)
1109 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1111 enum neon_el_type thistype
= NT_untyped
;
1112 unsigned thissize
= -1u;
1119 /* Just a size without an explicit type. */
1123 switch (TOLOWER (*ptr
))
1125 case 'i': thistype
= NT_integer
; break;
1126 case 'f': thistype
= NT_float
; break;
1127 case 'p': thistype
= NT_poly
; break;
1128 case 's': thistype
= NT_signed
; break;
1129 case 'u': thistype
= NT_unsigned
; break;
1131 thistype
= NT_float
;
1136 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1142 /* .f is an abbreviation for .f32. */
1143 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1148 thissize
= strtoul (ptr
, &ptr
, 10);
1150 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1153 as_bad (_("bad size %d in type specifier"), thissize
);
1161 type
->el
[type
->elems
].type
= thistype
;
1162 type
->el
[type
->elems
].size
= thissize
;
1167 /* Empty/missing type is not a successful parse. */
1168 if (type
->elems
== 0)
1176 /* Errors may be set multiple times during parsing or bit encoding
1177 (particularly in the Neon bits), but usually the earliest error which is set
1178 will be the most meaningful. Avoid overwriting it with later (cascading)
1179 errors by calling this function. */
1182 first_error (const char *err
)
1188 /* Parse a single type, e.g. ".s32", leading period included. */
1190 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1193 struct neon_type optype
;
1197 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1199 if (optype
.elems
== 1)
1200 *vectype
= optype
.el
[0];
1203 first_error (_("only one type should be specified for operand"));
1209 first_error (_("vector type expected"));
1221 /* Special meanings for indices (which have a range of 0-7), which will fit into
1224 #define NEON_ALL_LANES 15
1225 #define NEON_INTERLEAVE_LANES 14
1227 /* Parse either a register or a scalar, with an optional type. Return the
1228 register number, and optionally fill in the actual type of the register
1229 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1230 type/index information in *TYPEINFO. */
1233 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1234 enum arm_reg_type
*rtype
,
1235 struct neon_typed_alias
*typeinfo
)
1238 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1239 struct neon_typed_alias atype
;
1240 struct neon_type_el parsetype
;
1244 atype
.eltype
.type
= NT_invtype
;
1245 atype
.eltype
.size
= -1;
1247 /* Try alternate syntax for some types of register. Note these are mutually
1248 exclusive with the Neon syntax extensions. */
1251 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1259 /* Undo polymorphism when a set of register types may be accepted. */
1260 if ((type
== REG_TYPE_NDQ
1261 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1262 || (type
== REG_TYPE_VFSD
1263 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1264 || (type
== REG_TYPE_NSDQ
1265 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1266 || reg
->type
== REG_TYPE_NQ
))
1267 || (type
== REG_TYPE_MMXWC
1268 && (reg
->type
== REG_TYPE_MMXWCG
)))
1271 if (type
!= reg
->type
)
1277 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1279 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1281 first_error (_("can't redefine type for operand"));
1284 atype
.defined
|= NTA_HASTYPE
;
1285 atype
.eltype
= parsetype
;
1288 if (skip_past_char (&str
, '[') == SUCCESS
)
1290 if (type
!= REG_TYPE_VFD
)
1292 first_error (_("only D registers may be indexed"));
1296 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1298 first_error (_("can't change index for operand"));
1302 atype
.defined
|= NTA_HASINDEX
;
1304 if (skip_past_char (&str
, ']') == SUCCESS
)
1305 atype
.index
= NEON_ALL_LANES
;
1310 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1312 if (exp
.X_op
!= O_constant
)
1314 first_error (_("constant expression required"));
1318 if (skip_past_char (&str
, ']') == FAIL
)
1321 atype
.index
= exp
.X_add_number
;
1336 /* Like arm_reg_parse, but allow allow the following extra features:
1337 - If RTYPE is non-zero, return the (possibly restricted) type of the
1338 register (e.g. Neon double or quad reg when either has been requested).
1339 - If this is a Neon vector type with additional type information, fill
1340 in the struct pointed to by VECTYPE (if non-NULL).
1341 This function will fault on encountering a scalar.
1345 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1346 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1348 struct neon_typed_alias atype
;
1350 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1355 /* Do not allow a scalar (reg+index) to parse as a register. */
1356 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1358 first_error (_("register operand expected, but got scalar"));
1363 *vectype
= atype
.eltype
;
1370 #define NEON_SCALAR_REG(X) ((X) >> 4)
1371 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1373 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1374 have enough information to be able to do a good job bounds-checking. So, we
1375 just do easy checks here, and do further checks later. */
1378 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1382 struct neon_typed_alias atype
;
1384 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1386 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1389 if (atype
.index
== NEON_ALL_LANES
)
1391 first_error (_("scalar must have an index"));
1394 else if (atype
.index
>= 64 / elsize
)
1396 first_error (_("scalar index out of range"));
1401 *type
= atype
.eltype
;
1405 return reg
* 16 + atype
.index
;
1408 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1410 parse_reg_list (char ** strp
)
1412 char * str
= * strp
;
1416 /* We come back here if we get ranges concatenated by '+' or '|'. */
1431 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1433 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1443 first_error (_("bad range in register list"));
1447 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1449 if (range
& (1 << i
))
1451 (_("Warning: duplicated register (r%d) in register list"),
1459 if (range
& (1 << reg
))
1460 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1462 else if (reg
<= cur_reg
)
1463 as_tsktsk (_("Warning: register range not in ascending order"));
1468 while (skip_past_comma (&str
) != FAIL
1469 || (in_range
= 1, *str
++ == '-'));
1474 first_error (_("missing `}'"));
1482 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1485 if (expr
.X_op
== O_constant
)
1487 if (expr
.X_add_number
1488 != (expr
.X_add_number
& 0x0000ffff))
1490 inst
.error
= _("invalid register mask");
1494 if ((range
& expr
.X_add_number
) != 0)
1496 int regno
= range
& expr
.X_add_number
;
1499 regno
= (1 << regno
) - 1;
1501 (_("Warning: duplicated register (r%d) in register list"),
1505 range
|= expr
.X_add_number
;
1509 if (inst
.reloc
.type
!= 0)
1511 inst
.error
= _("expression too complex");
1515 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1516 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1517 inst
.reloc
.pc_rel
= 0;
1521 if (*str
== '|' || *str
== '+')
1527 while (another_range
);
1533 /* Types of registers in a list. */
1542 /* Parse a VFP register list. If the string is invalid return FAIL.
1543 Otherwise return the number of registers, and set PBASE to the first
1544 register. Parses registers of type ETYPE.
1545 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1546 - Q registers can be used to specify pairs of D registers
1547 - { } can be omitted from around a singleton register list
1548 FIXME: This is not implemented, as it would require backtracking in
1551 This could be done (the meaning isn't really ambiguous), but doesn't
1552 fit in well with the current parsing framework.
1553 - 32 D registers may be used (also true for VFPv3).
1554 FIXME: Types are ignored in these register lists, which is probably a
1558 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1563 enum arm_reg_type regtype
= 0;
1567 unsigned long mask
= 0;
1572 inst
.error
= _("expecting {");
1581 regtype
= REG_TYPE_VFS
;
1586 regtype
= REG_TYPE_VFD
;
1589 case REGLIST_NEON_D
:
1590 regtype
= REG_TYPE_NDQ
;
1594 if (etype
!= REGLIST_VFP_S
)
1596 /* VFPv3 allows 32 D registers. */
1597 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
1601 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1604 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1611 base_reg
= max_regs
;
1615 int setmask
= 1, addregs
= 1;
1617 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1619 if (new_base
== FAIL
)
1621 first_error (_(reg_expected_msgs
[regtype
]));
1625 if (new_base
>= max_regs
)
1627 first_error (_("register out of range in list"));
1631 /* Note: a value of 2 * n is returned for the register Q<n>. */
1632 if (regtype
== REG_TYPE_NQ
)
1638 if (new_base
< base_reg
)
1639 base_reg
= new_base
;
1641 if (mask
& (setmask
<< new_base
))
1643 first_error (_("invalid register list"));
1647 if ((mask
>> new_base
) != 0 && ! warned
)
1649 as_tsktsk (_("register list not in ascending order"));
1653 mask
|= setmask
<< new_base
;
1656 if (*str
== '-') /* We have the start of a range expression */
1662 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1665 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1669 if (high_range
>= max_regs
)
1671 first_error (_("register out of range in list"));
1675 if (regtype
== REG_TYPE_NQ
)
1676 high_range
= high_range
+ 1;
1678 if (high_range
<= new_base
)
1680 inst
.error
= _("register range not in ascending order");
1684 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1686 if (mask
& (setmask
<< new_base
))
1688 inst
.error
= _("invalid register list");
1692 mask
|= setmask
<< new_base
;
1697 while (skip_past_comma (&str
) != FAIL
);
1701 /* Sanity check -- should have raised a parse error above. */
1702 if (count
== 0 || count
> max_regs
)
1707 /* Final test -- the registers must be consecutive. */
1709 for (i
= 0; i
< count
; i
++)
1711 if ((mask
& (1u << i
)) == 0)
1713 inst
.error
= _("non-contiguous register range");
1723 /* True if two alias types are the same. */
1726 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1734 if (a
->defined
!= b
->defined
)
1737 if ((a
->defined
& NTA_HASTYPE
) != 0
1738 && (a
->eltype
.type
!= b
->eltype
.type
1739 || a
->eltype
.size
!= b
->eltype
.size
))
1742 if ((a
->defined
& NTA_HASINDEX
) != 0
1743 && (a
->index
!= b
->index
))
1749 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1750 The base register is put in *PBASE.
1751 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1753 The register stride (minus one) is put in bit 4 of the return value.
1754 Bits [6:5] encode the list length (minus one).
1755 The type of the list elements is put in *ELTYPE, if non-NULL. */
1757 #define NEON_LANE(X) ((X) & 0xf)
1758 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1759 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1762 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1763 struct neon_type_el
*eltype
)
1770 int leading_brace
= 0;
1771 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1773 const char *const incr_error
= "register stride must be 1 or 2";
1774 const char *const type_error
= "mismatched element/structure types in list";
1775 struct neon_typed_alias firsttype
;
1777 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1782 struct neon_typed_alias atype
;
1783 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1787 first_error (_(reg_expected_msgs
[rtype
]));
1794 if (rtype
== REG_TYPE_NQ
)
1801 else if (reg_incr
== -1)
1803 reg_incr
= getreg
- base_reg
;
1804 if (reg_incr
< 1 || reg_incr
> 2)
1806 first_error (_(incr_error
));
1810 else if (getreg
!= base_reg
+ reg_incr
* count
)
1812 first_error (_(incr_error
));
1816 if (!neon_alias_types_same (&atype
, &firsttype
))
1818 first_error (_(type_error
));
1822 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1826 struct neon_typed_alias htype
;
1827 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1829 lane
= NEON_INTERLEAVE_LANES
;
1830 else if (lane
!= NEON_INTERLEAVE_LANES
)
1832 first_error (_(type_error
));
1837 else if (reg_incr
!= 1)
1839 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1843 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1846 first_error (_(reg_expected_msgs
[rtype
]));
1849 if (!neon_alias_types_same (&htype
, &firsttype
))
1851 first_error (_(type_error
));
1854 count
+= hireg
+ dregs
- getreg
;
1858 /* If we're using Q registers, we can't use [] or [n] syntax. */
1859 if (rtype
== REG_TYPE_NQ
)
1865 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1869 else if (lane
!= atype
.index
)
1871 first_error (_(type_error
));
1875 else if (lane
== -1)
1876 lane
= NEON_INTERLEAVE_LANES
;
1877 else if (lane
!= NEON_INTERLEAVE_LANES
)
1879 first_error (_(type_error
));
1884 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1886 /* No lane set by [x]. We must be interleaving structures. */
1888 lane
= NEON_INTERLEAVE_LANES
;
1891 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
1892 || (count
> 1 && reg_incr
== -1))
1894 first_error (_("error parsing element/structure list"));
1898 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
1900 first_error (_("expected }"));
1908 *eltype
= firsttype
.eltype
;
1913 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
1916 /* Parse an explicit relocation suffix on an expression. This is
1917 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1918 arm_reloc_hsh contains no entries, so this function can only
1919 succeed if there is no () after the word. Returns -1 on error,
1920 BFD_RELOC_UNUSED if there wasn't any suffix. */
1922 parse_reloc (char **str
)
1924 struct reloc_entry
*r
;
1928 return BFD_RELOC_UNUSED
;
1933 while (*q
&& *q
!= ')' && *q
!= ',')
1938 if ((r
= hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
1945 /* Directives: register aliases. */
1947 static struct reg_entry
*
1948 insert_reg_alias (char *str
, int number
, int type
)
1950 struct reg_entry
*new;
1953 if ((new = hash_find (arm_reg_hsh
, str
)) != 0)
1956 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
1958 /* Only warn about a redefinition if it's not defined as the
1960 else if (new->number
!= number
|| new->type
!= type
)
1961 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1966 name
= xstrdup (str
);
1967 new = xmalloc (sizeof (struct reg_entry
));
1970 new->number
= number
;
1972 new->builtin
= FALSE
;
1975 if (hash_insert (arm_reg_hsh
, name
, (PTR
) new))
1982 insert_neon_reg_alias (char *str
, int number
, int type
,
1983 struct neon_typed_alias
*atype
)
1985 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
1989 first_error (_("attempt to redefine typed alias"));
1995 reg
->neon
= xmalloc (sizeof (struct neon_typed_alias
));
1996 *reg
->neon
= *atype
;
2000 /* Look for the .req directive. This is of the form:
2002 new_register_name .req existing_register_name
2004 If we find one, or if it looks sufficiently like one that we want to
2005 handle any error here, return non-zero. Otherwise return zero. */
2008 create_register_alias (char * newname
, char *p
)
2010 struct reg_entry
*old
;
2011 char *oldname
, *nbuf
;
2014 /* The input scrubber ensures that whitespace after the mnemonic is
2015 collapsed to single spaces. */
2017 if (strncmp (oldname
, " .req ", 6) != 0)
2021 if (*oldname
== '\0')
2024 old
= hash_find (arm_reg_hsh
, oldname
);
2027 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2031 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2032 the desired alias name, and p points to its end. If not, then
2033 the desired alias name is in the global original_case_string. */
2034 #ifdef TC_CASE_SENSITIVE
2037 newname
= original_case_string
;
2038 nlen
= strlen (newname
);
2041 nbuf
= alloca (nlen
+ 1);
2042 memcpy (nbuf
, newname
, nlen
);
2045 /* Create aliases under the new name as stated; an all-lowercase
2046 version of the new name; and an all-uppercase version of the new
2048 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2050 for (p
= nbuf
; *p
; p
++)
2053 if (strncmp (nbuf
, newname
, nlen
))
2054 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2056 for (p
= nbuf
; *p
; p
++)
2059 if (strncmp (nbuf
, newname
, nlen
))
2060 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2065 /* Create a Neon typed/indexed register alias using directives, e.g.:
2070 These typed registers can be used instead of the types specified after the
2071 Neon mnemonic, so long as all operands given have types. Types can also be
2072 specified directly, e.g.:
2073 vadd d0.s32, d1.s32, d2.s32
2077 create_neon_reg_alias (char *newname
, char *p
)
2079 enum arm_reg_type basetype
;
2080 struct reg_entry
*basereg
;
2081 struct reg_entry mybasereg
;
2082 struct neon_type ntype
;
2083 struct neon_typed_alias typeinfo
;
2084 char *namebuf
, *nameend
;
2087 typeinfo
.defined
= 0;
2088 typeinfo
.eltype
.type
= NT_invtype
;
2089 typeinfo
.eltype
.size
= -1;
2090 typeinfo
.index
= -1;
2094 if (strncmp (p
, " .dn ", 5) == 0)
2095 basetype
= REG_TYPE_VFD
;
2096 else if (strncmp (p
, " .qn ", 5) == 0)
2097 basetype
= REG_TYPE_NQ
;
2106 basereg
= arm_reg_parse_multi (&p
);
2108 if (basereg
&& basereg
->type
!= basetype
)
2110 as_bad (_("bad type for register"));
2114 if (basereg
== NULL
)
2117 /* Try parsing as an integer. */
2118 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2119 if (exp
.X_op
!= O_constant
)
2121 as_bad (_("expression must be constant"));
2124 basereg
= &mybasereg
;
2125 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2131 typeinfo
= *basereg
->neon
;
2133 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2135 /* We got a type. */
2136 if (typeinfo
.defined
& NTA_HASTYPE
)
2138 as_bad (_("can't redefine the type of a register alias"));
2142 typeinfo
.defined
|= NTA_HASTYPE
;
2143 if (ntype
.elems
!= 1)
2145 as_bad (_("you must specify a single type only"));
2148 typeinfo
.eltype
= ntype
.el
[0];
2151 if (skip_past_char (&p
, '[') == SUCCESS
)
2154 /* We got a scalar index. */
2156 if (typeinfo
.defined
& NTA_HASINDEX
)
2158 as_bad (_("can't redefine the index of a scalar alias"));
2162 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2164 if (exp
.X_op
!= O_constant
)
2166 as_bad (_("scalar index must be constant"));
2170 typeinfo
.defined
|= NTA_HASINDEX
;
2171 typeinfo
.index
= exp
.X_add_number
;
2173 if (skip_past_char (&p
, ']') == FAIL
)
2175 as_bad (_("expecting ]"));
2180 namelen
= nameend
- newname
;
2181 namebuf
= alloca (namelen
+ 1);
2182 strncpy (namebuf
, newname
, namelen
);
2183 namebuf
[namelen
] = '\0';
2185 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2186 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2188 /* Insert name in all uppercase. */
2189 for (p
= namebuf
; *p
; p
++)
2192 if (strncmp (namebuf
, newname
, namelen
))
2193 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2194 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2196 /* Insert name in all lowercase. */
2197 for (p
= namebuf
; *p
; p
++)
2200 if (strncmp (namebuf
, newname
, namelen
))
2201 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2202 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2207 /* Should never be called, as .req goes between the alias and the
2208 register name, not at the beginning of the line. */
2210 s_req (int a ATTRIBUTE_UNUSED
)
2212 as_bad (_("invalid syntax for .req directive"));
2216 s_dn (int a ATTRIBUTE_UNUSED
)
2218 as_bad (_("invalid syntax for .dn directive"));
2222 s_qn (int a ATTRIBUTE_UNUSED
)
2224 as_bad (_("invalid syntax for .qn directive"));
2227 /* The .unreq directive deletes an alias which was previously defined
2228 by .req. For example:
2234 s_unreq (int a ATTRIBUTE_UNUSED
)
2239 name
= input_line_pointer
;
2241 while (*input_line_pointer
!= 0
2242 && *input_line_pointer
!= ' '
2243 && *input_line_pointer
!= '\n')
2244 ++input_line_pointer
;
2246 saved_char
= *input_line_pointer
;
2247 *input_line_pointer
= 0;
2250 as_bad (_("invalid syntax for .unreq directive"));
2253 struct reg_entry
*reg
= hash_find (arm_reg_hsh
, name
);
2256 as_bad (_("unknown register alias '%s'"), name
);
2257 else if (reg
->builtin
)
2258 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2262 hash_delete (arm_reg_hsh
, name
);
2263 free ((char *) reg
->name
);
2270 *input_line_pointer
= saved_char
;
2271 demand_empty_rest_of_line ();
2274 /* Directives: Instruction set selection. */
2277 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2278 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2279 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2280 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2282 static enum mstate mapstate
= MAP_UNDEFINED
;
2285 mapping_state (enum mstate state
)
2288 const char * symname
;
2291 if (mapstate
== state
)
2292 /* The mapping symbol has already been emitted.
2293 There is nothing else to do. */
2302 type
= BSF_NO_FLAGS
;
2306 type
= BSF_NO_FLAGS
;
2310 type
= BSF_NO_FLAGS
;
2318 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2320 symbolP
= symbol_new (symname
, now_seg
, (valueT
) frag_now_fix (), frag_now
);
2321 symbol_table_insert (symbolP
);
2322 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2327 THUMB_SET_FUNC (symbolP
, 0);
2328 ARM_SET_THUMB (symbolP
, 0);
2329 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2333 THUMB_SET_FUNC (symbolP
, 1);
2334 ARM_SET_THUMB (symbolP
, 1);
2335 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2344 #define mapping_state(x) /* nothing */
2347 /* Find the real, Thumb encoded start of a Thumb function. */
2350 find_real_start (symbolS
* symbolP
)
2353 const char * name
= S_GET_NAME (symbolP
);
2354 symbolS
* new_target
;
2356 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2357 #define STUB_NAME ".real_start_of"
2362 /* The compiler may generate BL instructions to local labels because
2363 it needs to perform a branch to a far away location. These labels
2364 do not have a corresponding ".real_start_of" label. We check
2365 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2366 the ".real_start_of" convention for nonlocal branches. */
2367 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2370 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2371 new_target
= symbol_find (real_start
);
2373 if (new_target
== NULL
)
2375 as_warn ("Failed to find real start of function: %s\n", name
);
2376 new_target
= symbolP
;
2383 opcode_select (int width
)
2390 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2391 as_bad (_("selected processor does not support THUMB opcodes"));
2394 /* No need to force the alignment, since we will have been
2395 coming from ARM mode, which is word-aligned. */
2396 record_alignment (now_seg
, 1);
2398 mapping_state (MAP_THUMB
);
2404 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2405 as_bad (_("selected processor does not support ARM opcodes"));
2410 frag_align (2, 0, 0);
2412 record_alignment (now_seg
, 1);
2414 mapping_state (MAP_ARM
);
2418 as_bad (_("invalid instruction size selected (%d)"), width
);
2423 s_arm (int ignore ATTRIBUTE_UNUSED
)
2426 demand_empty_rest_of_line ();
2430 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2433 demand_empty_rest_of_line ();
2437 s_code (int unused ATTRIBUTE_UNUSED
)
2441 temp
= get_absolute_expression ();
2446 opcode_select (temp
);
2450 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2455 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2457 /* If we are not already in thumb mode go into it, EVEN if
2458 the target processor does not support thumb instructions.
2459 This is used by gcc/config/arm/lib1funcs.asm for example
2460 to compile interworking support functions even if the
2461 target processor should not support interworking. */
2465 record_alignment (now_seg
, 1);
2468 demand_empty_rest_of_line ();
2472 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2476 /* The following label is the name/address of the start of a Thumb function.
2477 We need to know this for the interworking support. */
2478 label_is_thumb_function_name
= TRUE
;
2481 /* Perform a .set directive, but also mark the alias as
2482 being a thumb function. */
2485 s_thumb_set (int equiv
)
2487 /* XXX the following is a duplicate of the code for s_set() in read.c
2488 We cannot just call that code as we need to get at the symbol that
2495 /* Especial apologies for the random logic:
2496 This just grew, and could be parsed much more simply!
2498 name
= input_line_pointer
;
2499 delim
= get_symbol_end ();
2500 end_name
= input_line_pointer
;
2503 if (*input_line_pointer
!= ',')
2506 as_bad (_("expected comma after name \"%s\""), name
);
2508 ignore_rest_of_line ();
2512 input_line_pointer
++;
2515 if (name
[0] == '.' && name
[1] == '\0')
2517 /* XXX - this should not happen to .thumb_set. */
2521 if ((symbolP
= symbol_find (name
)) == NULL
2522 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2525 /* When doing symbol listings, play games with dummy fragments living
2526 outside the normal fragment chain to record the file and line info
2528 if (listing
& LISTING_SYMBOLS
)
2530 extern struct list_info_struct
* listing_tail
;
2531 fragS
* dummy_frag
= xmalloc (sizeof (fragS
));
2533 memset (dummy_frag
, 0, sizeof (fragS
));
2534 dummy_frag
->fr_type
= rs_fill
;
2535 dummy_frag
->line
= listing_tail
;
2536 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2537 dummy_frag
->fr_symbol
= symbolP
;
2541 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2544 /* "set" symbols are local unless otherwise specified. */
2545 SF_SET_LOCAL (symbolP
);
2546 #endif /* OBJ_COFF */
2547 } /* Make a new symbol. */
2549 symbol_table_insert (symbolP
);
2554 && S_IS_DEFINED (symbolP
)
2555 && S_GET_SEGMENT (symbolP
) != reg_section
)
2556 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2558 pseudo_set (symbolP
);
2560 demand_empty_rest_of_line ();
2562 /* XXX Now we come to the Thumb specific bit of code. */
2564 THUMB_SET_FUNC (symbolP
, 1);
2565 ARM_SET_THUMB (symbolP
, 1);
2566 #if defined OBJ_ELF || defined OBJ_COFF
2567 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2571 /* Directives: Mode selection. */
2573 /* .syntax [unified|divided] - choose the new unified syntax
2574 (same for Arm and Thumb encoding, modulo slight differences in what
2575 can be represented) or the old divergent syntax for each mode. */
2577 s_syntax (int unused ATTRIBUTE_UNUSED
)
2581 name
= input_line_pointer
;
2582 delim
= get_symbol_end ();
2584 if (!strcasecmp (name
, "unified"))
2585 unified_syntax
= TRUE
;
2586 else if (!strcasecmp (name
, "divided"))
2587 unified_syntax
= FALSE
;
2590 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2593 *input_line_pointer
= delim
;
2594 demand_empty_rest_of_line ();
2597 /* Directives: sectioning and alignment. */
2599 /* Same as s_align_ptwo but align 0 => align 2. */
2602 s_align (int unused ATTRIBUTE_UNUSED
)
2606 long max_alignment
= 15;
2608 temp
= get_absolute_expression ();
2609 if (temp
> max_alignment
)
2610 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2613 as_bad (_("alignment negative. 0 assumed."));
2617 if (*input_line_pointer
== ',')
2619 input_line_pointer
++;
2620 temp_fill
= get_absolute_expression ();
2628 /* Only make a frag if we HAVE to. */
2629 if (temp
&& !need_pass_2
)
2630 frag_align (temp
, (int) temp_fill
, 0);
2631 demand_empty_rest_of_line ();
2633 record_alignment (now_seg
, temp
);
2637 s_bss (int ignore ATTRIBUTE_UNUSED
)
2639 /* We don't support putting frags in the BSS segment, we fake it by
2640 marking in_bss, then looking at s_skip for clues. */
2641 subseg_set (bss_section
, 0);
2642 demand_empty_rest_of_line ();
2643 mapping_state (MAP_DATA
);
2647 s_even (int ignore ATTRIBUTE_UNUSED
)
2649 /* Never make frag if expect extra pass. */
2651 frag_align (1, 0, 0);
2653 record_alignment (now_seg
, 1);
2655 demand_empty_rest_of_line ();
2658 /* Directives: Literal pools. */
2660 static literal_pool
*
2661 find_literal_pool (void)
2663 literal_pool
* pool
;
2665 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2667 if (pool
->section
== now_seg
2668 && pool
->sub_section
== now_subseg
)
2675 static literal_pool
*
2676 find_or_make_literal_pool (void)
2678 /* Next literal pool ID number. */
2679 static unsigned int latest_pool_num
= 1;
2680 literal_pool
* pool
;
2682 pool
= find_literal_pool ();
2686 /* Create a new pool. */
2687 pool
= xmalloc (sizeof (* pool
));
2691 pool
->next_free_entry
= 0;
2692 pool
->section
= now_seg
;
2693 pool
->sub_section
= now_subseg
;
2694 pool
->next
= list_of_pools
;
2695 pool
->symbol
= NULL
;
2697 /* Add it to the list. */
2698 list_of_pools
= pool
;
2701 /* New pools, and emptied pools, will have a NULL symbol. */
2702 if (pool
->symbol
== NULL
)
2704 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2705 (valueT
) 0, &zero_address_frag
);
2706 pool
->id
= latest_pool_num
++;
2713 /* Add the literal in the global 'inst'
2714 structure to the relevent literal pool. */
2717 add_to_lit_pool (void)
2719 literal_pool
* pool
;
2722 pool
= find_or_make_literal_pool ();
2724 /* Check if this literal value is already in the pool. */
2725 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2727 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2728 && (inst
.reloc
.exp
.X_op
== O_constant
)
2729 && (pool
->literals
[entry
].X_add_number
2730 == inst
.reloc
.exp
.X_add_number
)
2731 && (pool
->literals
[entry
].X_unsigned
2732 == inst
.reloc
.exp
.X_unsigned
))
2735 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2736 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2737 && (pool
->literals
[entry
].X_add_number
2738 == inst
.reloc
.exp
.X_add_number
)
2739 && (pool
->literals
[entry
].X_add_symbol
2740 == inst
.reloc
.exp
.X_add_symbol
)
2741 && (pool
->literals
[entry
].X_op_symbol
2742 == inst
.reloc
.exp
.X_op_symbol
))
2746 /* Do we need to create a new entry? */
2747 if (entry
== pool
->next_free_entry
)
2749 if (entry
>= MAX_LITERAL_POOL_SIZE
)
2751 inst
.error
= _("literal pool overflow");
2755 pool
->literals
[entry
] = inst
.reloc
.exp
;
2756 pool
->next_free_entry
+= 1;
2759 inst
.reloc
.exp
.X_op
= O_symbol
;
2760 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
2761 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
2766 /* Can't use symbol_new here, so have to create a symbol and then at
2767 a later date assign it a value. Thats what these functions do. */
2770 symbol_locate (symbolS
* symbolP
,
2771 const char * name
, /* It is copied, the caller can modify. */
2772 segT segment
, /* Segment identifier (SEG_<something>). */
2773 valueT valu
, /* Symbol value. */
2774 fragS
* frag
) /* Associated fragment. */
2776 unsigned int name_length
;
2777 char * preserved_copy_of_name
;
2779 name_length
= strlen (name
) + 1; /* +1 for \0. */
2780 obstack_grow (¬es
, name
, name_length
);
2781 preserved_copy_of_name
= obstack_finish (¬es
);
2783 #ifdef tc_canonicalize_symbol_name
2784 preserved_copy_of_name
=
2785 tc_canonicalize_symbol_name (preserved_copy_of_name
);
2788 S_SET_NAME (symbolP
, preserved_copy_of_name
);
2790 S_SET_SEGMENT (symbolP
, segment
);
2791 S_SET_VALUE (symbolP
, valu
);
2792 symbol_clear_list_pointers (symbolP
);
2794 symbol_set_frag (symbolP
, frag
);
2796 /* Link to end of symbol chain. */
2798 extern int symbol_table_frozen
;
2800 if (symbol_table_frozen
)
2804 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
2806 obj_symbol_new_hook (symbolP
);
2808 #ifdef tc_symbol_new_hook
2809 tc_symbol_new_hook (symbolP
);
2813 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
2814 #endif /* DEBUG_SYMS */
2819 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
2822 literal_pool
* pool
;
2825 pool
= find_literal_pool ();
2827 || pool
->symbol
== NULL
2828 || pool
->next_free_entry
== 0)
2831 mapping_state (MAP_DATA
);
2833 /* Align pool as you have word accesses.
2834 Only make a frag if we have to. */
2836 frag_align (2, 0, 0);
2838 record_alignment (now_seg
, 2);
2840 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
2842 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
2843 (valueT
) frag_now_fix (), frag_now
);
2844 symbol_table_insert (pool
->symbol
);
2846 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
2848 #if defined OBJ_COFF || defined OBJ_ELF
2849 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
2852 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2853 /* First output the expression in the instruction to the pool. */
2854 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
2856 /* Mark the pool as empty. */
2857 pool
->next_free_entry
= 0;
2858 pool
->symbol
= NULL
;
2862 /* Forward declarations for functions below, in the MD interface
2864 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
2865 static valueT
create_unwind_entry (int);
2866 static void start_unwind_section (const segT
, int);
2867 static void add_unwind_opcode (valueT
, int);
2868 static void flush_pending_unwind (void);
2870 /* Directives: Data. */
2873 s_arm_elf_cons (int nbytes
)
2877 #ifdef md_flush_pending_output
2878 md_flush_pending_output ();
2881 if (is_it_end_of_statement ())
2883 demand_empty_rest_of_line ();
2887 #ifdef md_cons_align
2888 md_cons_align (nbytes
);
2891 mapping_state (MAP_DATA
);
2895 char *base
= input_line_pointer
;
2899 if (exp
.X_op
!= O_symbol
)
2900 emit_expr (&exp
, (unsigned int) nbytes
);
2903 char *before_reloc
= input_line_pointer
;
2904 reloc
= parse_reloc (&input_line_pointer
);
2907 as_bad (_("unrecognized relocation suffix"));
2908 ignore_rest_of_line ();
2911 else if (reloc
== BFD_RELOC_UNUSED
)
2912 emit_expr (&exp
, (unsigned int) nbytes
);
2915 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
2916 int size
= bfd_get_reloc_size (howto
);
2918 if (reloc
== BFD_RELOC_ARM_PLT32
)
2920 as_bad (_("(plt) is only valid on branch targets"));
2921 reloc
= BFD_RELOC_UNUSED
;
2926 as_bad (_("%s relocations do not fit in %d bytes"),
2927 howto
->name
, nbytes
);
2930 /* We've parsed an expression stopping at O_symbol.
2931 But there may be more expression left now that we
2932 have parsed the relocation marker. Parse it again.
2933 XXX Surely there is a cleaner way to do this. */
2934 char *p
= input_line_pointer
;
2936 char *save_buf
= alloca (input_line_pointer
- base
);
2937 memcpy (save_buf
, base
, input_line_pointer
- base
);
2938 memmove (base
+ (input_line_pointer
- before_reloc
),
2939 base
, before_reloc
- base
);
2941 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
2943 memcpy (base
, save_buf
, p
- base
);
2945 offset
= nbytes
- size
;
2946 p
= frag_more ((int) nbytes
);
2947 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
2948 size
, &exp
, 0, reloc
);
2953 while (*input_line_pointer
++ == ',');
2955 /* Put terminator back into stream. */
2956 input_line_pointer
--;
2957 demand_empty_rest_of_line ();
2961 /* Parse a .rel31 directive. */
2964 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
2971 if (*input_line_pointer
== '1')
2972 highbit
= 0x80000000;
2973 else if (*input_line_pointer
!= '0')
2974 as_bad (_("expected 0 or 1"));
2976 input_line_pointer
++;
2977 if (*input_line_pointer
!= ',')
2978 as_bad (_("missing comma"));
2979 input_line_pointer
++;
2981 #ifdef md_flush_pending_output
2982 md_flush_pending_output ();
2985 #ifdef md_cons_align
2989 mapping_state (MAP_DATA
);
2994 md_number_to_chars (p
, highbit
, 4);
2995 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
2996 BFD_RELOC_ARM_PREL31
);
2998 demand_empty_rest_of_line ();
3001 /* Directives: AEABI stack-unwind tables. */
3003 /* Parse an unwind_fnstart directive. Simply records the current location. */
3006 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3008 demand_empty_rest_of_line ();
3009 /* Mark the start of the function. */
3010 unwind
.proc_start
= expr_build_dot ();
3012 /* Reset the rest of the unwind info. */
3013 unwind
.opcode_count
= 0;
3014 unwind
.table_entry
= NULL
;
3015 unwind
.personality_routine
= NULL
;
3016 unwind
.personality_index
= -1;
3017 unwind
.frame_size
= 0;
3018 unwind
.fp_offset
= 0;
3021 unwind
.sp_restored
= 0;
3025 /* Parse a handlerdata directive. Creates the exception handling table entry
3026 for the function. */
3029 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3031 demand_empty_rest_of_line ();
3032 if (unwind
.table_entry
)
3033 as_bad (_("dupicate .handlerdata directive"));
3035 create_unwind_entry (1);
3038 /* Parse an unwind_fnend directive. Generates the index table entry. */
3041 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3047 demand_empty_rest_of_line ();
3049 /* Add eh table entry. */
3050 if (unwind
.table_entry
== NULL
)
3051 val
= create_unwind_entry (0);
3055 /* Add index table entry. This is two words. */
3056 start_unwind_section (unwind
.saved_seg
, 1);
3057 frag_align (2, 0, 0);
3058 record_alignment (now_seg
, 2);
3060 ptr
= frag_more (8);
3061 where
= frag_now_fix () - 8;
3063 /* Self relative offset of the function start. */
3064 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3065 BFD_RELOC_ARM_PREL31
);
3067 /* Indicate dependency on EHABI-defined personality routines to the
3068 linker, if it hasn't been done already. */
3069 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3070 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3072 static const char *const name
[] = {
3073 "__aeabi_unwind_cpp_pr0",
3074 "__aeabi_unwind_cpp_pr1",
3075 "__aeabi_unwind_cpp_pr2"
3077 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3078 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3079 marked_pr_dependency
|= 1 << unwind
.personality_index
;
3080 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3081 = marked_pr_dependency
;
3085 /* Inline exception table entry. */
3086 md_number_to_chars (ptr
+ 4, val
, 4);
3088 /* Self relative offset of the table entry. */
3089 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3090 BFD_RELOC_ARM_PREL31
);
3092 /* Restore the original section. */
3093 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3097 /* Parse an unwind_cantunwind directive. */
3100 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3102 demand_empty_rest_of_line ();
3103 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3104 as_bad (_("personality routine specified for cantunwind frame"));
3106 unwind
.personality_index
= -2;
3110 /* Parse a personalityindex directive. */
3113 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3117 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3118 as_bad (_("duplicate .personalityindex directive"));
3122 if (exp
.X_op
!= O_constant
3123 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3125 as_bad (_("bad personality routine number"));
3126 ignore_rest_of_line ();
3130 unwind
.personality_index
= exp
.X_add_number
;
3132 demand_empty_rest_of_line ();
3136 /* Parse a personality directive. */
3139 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3143 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3144 as_bad (_("duplicate .personality directive"));
3146 name
= input_line_pointer
;
3147 c
= get_symbol_end ();
3148 p
= input_line_pointer
;
3149 unwind
.personality_routine
= symbol_find_or_make (name
);
3151 demand_empty_rest_of_line ();
3155 /* Parse a directive saving core registers. */
3158 s_arm_unwind_save_core (void)
3164 range
= parse_reg_list (&input_line_pointer
);
3167 as_bad (_("expected register list"));
3168 ignore_rest_of_line ();
3172 demand_empty_rest_of_line ();
3174 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3175 into .unwind_save {..., sp...}. We aren't bothered about the value of
3176 ip because it is clobbered by calls. */
3177 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3178 && (range
& 0x3000) == 0x1000)
3180 unwind
.opcode_count
--;
3181 unwind
.sp_restored
= 0;
3182 range
= (range
| 0x2000) & ~0x1000;
3183 unwind
.pending_offset
= 0;
3189 /* See if we can use the short opcodes. These pop a block of up to 8
3190 registers starting with r4, plus maybe r14. */
3191 for (n
= 0; n
< 8; n
++)
3193 /* Break at the first non-saved register. */
3194 if ((range
& (1 << (n
+ 4))) == 0)
3197 /* See if there are any other bits set. */
3198 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3200 /* Use the long form. */
3201 op
= 0x8000 | ((range
>> 4) & 0xfff);
3202 add_unwind_opcode (op
, 2);
3206 /* Use the short form. */
3208 op
= 0xa8; /* Pop r14. */
3210 op
= 0xa0; /* Do not pop r14. */
3212 add_unwind_opcode (op
, 1);
3219 op
= 0xb100 | (range
& 0xf);
3220 add_unwind_opcode (op
, 2);
3223 /* Record the number of bytes pushed. */
3224 for (n
= 0; n
< 16; n
++)
3226 if (range
& (1 << n
))
3227 unwind
.frame_size
+= 4;
3232 /* Parse a directive saving FPA registers. */
3235 s_arm_unwind_save_fpa (int reg
)
3241 /* Get Number of registers to transfer. */
3242 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3245 exp
.X_op
= O_illegal
;
3247 if (exp
.X_op
!= O_constant
)
3249 as_bad (_("expected , <constant>"));
3250 ignore_rest_of_line ();
3254 num_regs
= exp
.X_add_number
;
3256 if (num_regs
< 1 || num_regs
> 4)
3258 as_bad (_("number of registers must be in the range [1:4]"));
3259 ignore_rest_of_line ();
3263 demand_empty_rest_of_line ();
3268 op
= 0xb4 | (num_regs
- 1);
3269 add_unwind_opcode (op
, 1);
3274 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3275 add_unwind_opcode (op
, 2);
3277 unwind
.frame_size
+= num_regs
* 12;
3281 /* Parse a directive saving VFP registers for ARMv6 and above. */
3284 s_arm_unwind_save_vfp_armv6 (void)
3289 int num_vfpv3_regs
= 0;
3290 int num_regs_below_16
;
3292 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3295 as_bad (_("expected register list"));
3296 ignore_rest_of_line ();
3300 demand_empty_rest_of_line ();
3302 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3303 than FSTMX/FLDMX-style ones). */
3305 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3307 num_vfpv3_regs
= count
;
3308 else if (start
+ count
> 16)
3309 num_vfpv3_regs
= start
+ count
- 16;
3311 if (num_vfpv3_regs
> 0)
3313 int start_offset
= start
> 16 ? start
- 16 : 0;
3314 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3315 add_unwind_opcode (op
, 2);
3318 /* Generate opcode for registers numbered in the range 0 .. 15. */
3319 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3320 assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3321 if (num_regs_below_16
> 0)
3323 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3324 add_unwind_opcode (op
, 2);
3327 unwind
.frame_size
+= count
* 8;
3331 /* Parse a directive saving VFP registers for pre-ARMv6. */
3334 s_arm_unwind_save_vfp (void)
3340 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3343 as_bad (_("expected register list"));
3344 ignore_rest_of_line ();
3348 demand_empty_rest_of_line ();
3353 op
= 0xb8 | (count
- 1);
3354 add_unwind_opcode (op
, 1);
3359 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3360 add_unwind_opcode (op
, 2);
3362 unwind
.frame_size
+= count
* 8 + 4;
3366 /* Parse a directive saving iWMMXt data registers. */
3369 s_arm_unwind_save_mmxwr (void)
3377 if (*input_line_pointer
== '{')
3378 input_line_pointer
++;
3382 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3386 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3391 as_tsktsk (_("register list not in ascending order"));
3394 if (*input_line_pointer
== '-')
3396 input_line_pointer
++;
3397 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3400 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3403 else if (reg
>= hi_reg
)
3405 as_bad (_("bad register range"));
3408 for (; reg
< hi_reg
; reg
++)
3412 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3414 if (*input_line_pointer
== '}')
3415 input_line_pointer
++;
3417 demand_empty_rest_of_line ();
3419 /* Generate any deferred opcodes because we're going to be looking at
3421 flush_pending_unwind ();
3423 for (i
= 0; i
< 16; i
++)
3425 if (mask
& (1 << i
))
3426 unwind
.frame_size
+= 8;
3429 /* Attempt to combine with a previous opcode. We do this because gcc
3430 likes to output separate unwind directives for a single block of
3432 if (unwind
.opcode_count
> 0)
3434 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3435 if ((i
& 0xf8) == 0xc0)
3438 /* Only merge if the blocks are contiguous. */
3441 if ((mask
& 0xfe00) == (1 << 9))
3443 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3444 unwind
.opcode_count
--;
3447 else if (i
== 6 && unwind
.opcode_count
>= 2)
3449 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3453 op
= 0xffff << (reg
- 1);
3455 && ((mask
& op
) == (1u << (reg
- 1))))
3457 op
= (1 << (reg
+ i
+ 1)) - 1;
3458 op
&= ~((1 << reg
) - 1);
3460 unwind
.opcode_count
-= 2;
3467 /* We want to generate opcodes in the order the registers have been
3468 saved, ie. descending order. */
3469 for (reg
= 15; reg
>= -1; reg
--)
3471 /* Save registers in blocks. */
3473 || !(mask
& (1 << reg
)))
3475 /* We found an unsaved reg. Generate opcodes to save the
3476 preceeding block. */
3482 op
= 0xc0 | (hi_reg
- 10);
3483 add_unwind_opcode (op
, 1);
3488 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3489 add_unwind_opcode (op
, 2);
3498 ignore_rest_of_line ();
3502 s_arm_unwind_save_mmxwcg (void)
3509 if (*input_line_pointer
== '{')
3510 input_line_pointer
++;
3514 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3518 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3524 as_tsktsk (_("register list not in ascending order"));
3527 if (*input_line_pointer
== '-')
3529 input_line_pointer
++;
3530 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3533 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3536 else if (reg
>= hi_reg
)
3538 as_bad (_("bad register range"));
3541 for (; reg
< hi_reg
; reg
++)
3545 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3547 if (*input_line_pointer
== '}')
3548 input_line_pointer
++;
3550 demand_empty_rest_of_line ();
3552 /* Generate any deferred opcodes because we're going to be looking at
3554 flush_pending_unwind ();
3556 for (reg
= 0; reg
< 16; reg
++)
3558 if (mask
& (1 << reg
))
3559 unwind
.frame_size
+= 4;
3562 add_unwind_opcode (op
, 2);
3565 ignore_rest_of_line ();
3569 /* Parse an unwind_save directive.
3570 If the argument is non-zero, this is a .vsave directive. */
3573 s_arm_unwind_save (int arch_v6
)
3576 struct reg_entry
*reg
;
3577 bfd_boolean had_brace
= FALSE
;
3579 /* Figure out what sort of save we have. */
3580 peek
= input_line_pointer
;
3588 reg
= arm_reg_parse_multi (&peek
);
3592 as_bad (_("register expected"));
3593 ignore_rest_of_line ();
3602 as_bad (_("FPA .unwind_save does not take a register list"));
3603 ignore_rest_of_line ();
3606 s_arm_unwind_save_fpa (reg
->number
);
3609 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
3612 s_arm_unwind_save_vfp_armv6 ();
3614 s_arm_unwind_save_vfp ();
3616 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
3617 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
3620 as_bad (_(".unwind_save does not support this kind of register"));
3621 ignore_rest_of_line ();
3626 /* Parse an unwind_movsp directive. */
3629 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
3635 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3638 as_bad (_(reg_expected_msgs
[REG_TYPE_RN
]));
3639 ignore_rest_of_line ();
3643 /* Optional constant. */
3644 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3646 if (immediate_for_directive (&offset
) == FAIL
)
3652 demand_empty_rest_of_line ();
3654 if (reg
== REG_SP
|| reg
== REG_PC
)
3656 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
3660 if (unwind
.fp_reg
!= REG_SP
)
3661 as_bad (_("unexpected .unwind_movsp directive"));
3663 /* Generate opcode to restore the value. */
3665 add_unwind_opcode (op
, 1);
3667 /* Record the information for later. */
3668 unwind
.fp_reg
= reg
;
3669 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3670 unwind
.sp_restored
= 1;
3673 /* Parse an unwind_pad directive. */
3676 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
3680 if (immediate_for_directive (&offset
) == FAIL
)
3685 as_bad (_("stack increment must be multiple of 4"));
3686 ignore_rest_of_line ();
3690 /* Don't generate any opcodes, just record the details for later. */
3691 unwind
.frame_size
+= offset
;
3692 unwind
.pending_offset
+= offset
;
3694 demand_empty_rest_of_line ();
3697 /* Parse an unwind_setfp directive. */
3700 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
3706 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3707 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3710 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3712 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
3714 as_bad (_("expected <reg>, <reg>"));
3715 ignore_rest_of_line ();
3719 /* Optional constant. */
3720 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3722 if (immediate_for_directive (&offset
) == FAIL
)
3728 demand_empty_rest_of_line ();
3730 if (sp_reg
!= 13 && sp_reg
!= unwind
.fp_reg
)
3732 as_bad (_("register must be either sp or set by a previous"
3733 "unwind_movsp directive"));
3737 /* Don't generate any opcodes, just record the information for later. */
3738 unwind
.fp_reg
= fp_reg
;
3741 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3743 unwind
.fp_offset
-= offset
;
3746 /* Parse an unwind_raw directive. */
3749 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
3752 /* This is an arbitrary limit. */
3753 unsigned char op
[16];
3757 if (exp
.X_op
== O_constant
3758 && skip_past_comma (&input_line_pointer
) != FAIL
)
3760 unwind
.frame_size
+= exp
.X_add_number
;
3764 exp
.X_op
= O_illegal
;
3766 if (exp
.X_op
!= O_constant
)
3768 as_bad (_("expected <offset>, <opcode>"));
3769 ignore_rest_of_line ();
3775 /* Parse the opcode. */
3780 as_bad (_("unwind opcode too long"));
3781 ignore_rest_of_line ();
3783 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
3785 as_bad (_("invalid unwind opcode"));
3786 ignore_rest_of_line ();
3789 op
[count
++] = exp
.X_add_number
;
3791 /* Parse the next byte. */
3792 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3798 /* Add the opcode bytes in reverse order. */
3800 add_unwind_opcode (op
[count
], 1);
3802 demand_empty_rest_of_line ();
3806 /* Parse a .eabi_attribute directive. */
3809 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
3812 bfd_boolean is_string
;
3819 if (exp
.X_op
!= O_constant
)
3822 tag
= exp
.X_add_number
;
3823 if (tag
== 4 || tag
== 5 || tag
== 32 || (tag
> 32 && (tag
& 1) != 0))
3828 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3830 if (tag
== 32 || !is_string
)
3833 if (exp
.X_op
!= O_constant
)
3835 as_bad (_("expected numeric constant"));
3836 ignore_rest_of_line ();
3839 i
= exp
.X_add_number
;
3841 if (tag
== Tag_compatibility
3842 && skip_past_comma (&input_line_pointer
) == FAIL
)
3844 as_bad (_("expected comma"));
3845 ignore_rest_of_line ();
3850 skip_whitespace(input_line_pointer
);
3851 if (*input_line_pointer
!= '"')
3853 input_line_pointer
++;
3854 s
= input_line_pointer
;
3855 while (*input_line_pointer
&& *input_line_pointer
!= '"')
3856 input_line_pointer
++;
3857 if (*input_line_pointer
!= '"')
3859 saved_char
= *input_line_pointer
;
3860 *input_line_pointer
= 0;
3868 if (tag
== Tag_compatibility
)
3869 elf32_arm_add_eabi_attr_compat (stdoutput
, i
, s
);
3871 elf32_arm_add_eabi_attr_string (stdoutput
, tag
, s
);
3873 elf32_arm_add_eabi_attr_int (stdoutput
, tag
, i
);
3877 *input_line_pointer
= saved_char
;
3878 input_line_pointer
++;
3880 demand_empty_rest_of_line ();
3883 as_bad (_("bad string constant"));
3884 ignore_rest_of_line ();
3887 as_bad (_("expected <tag> , <value>"));
3888 ignore_rest_of_line ();
3890 #endif /* OBJ_ELF */
3892 static void s_arm_arch (int);
3893 static void s_arm_cpu (int);
3894 static void s_arm_fpu (int);
3899 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
3906 if (exp
.X_op
== O_symbol
)
3907 exp
.X_op
= O_secrel
;
3909 emit_expr (&exp
, 4);
3911 while (*input_line_pointer
++ == ',');
3913 input_line_pointer
--;
3914 demand_empty_rest_of_line ();
3918 /* This table describes all the machine specific pseudo-ops the assembler
3919 has to support. The fields are:
3920 pseudo-op name without dot
3921 function to call to execute this pseudo-op
3922 Integer arg to pass to the function. */
3924 const pseudo_typeS md_pseudo_table
[] =
3926 /* Never called because '.req' does not start a line. */
3927 { "req", s_req
, 0 },
3928 /* Following two are likewise never called. */
3931 { "unreq", s_unreq
, 0 },
3932 { "bss", s_bss
, 0 },
3933 { "align", s_align
, 0 },
3934 { "arm", s_arm
, 0 },
3935 { "thumb", s_thumb
, 0 },
3936 { "code", s_code
, 0 },
3937 { "force_thumb", s_force_thumb
, 0 },
3938 { "thumb_func", s_thumb_func
, 0 },
3939 { "thumb_set", s_thumb_set
, 0 },
3940 { "even", s_even
, 0 },
3941 { "ltorg", s_ltorg
, 0 },
3942 { "pool", s_ltorg
, 0 },
3943 { "syntax", s_syntax
, 0 },
3944 { "cpu", s_arm_cpu
, 0 },
3945 { "arch", s_arm_arch
, 0 },
3946 { "fpu", s_arm_fpu
, 0 },
3948 { "word", s_arm_elf_cons
, 4 },
3949 { "long", s_arm_elf_cons
, 4 },
3950 { "rel31", s_arm_rel31
, 0 },
3951 { "fnstart", s_arm_unwind_fnstart
, 0 },
3952 { "fnend", s_arm_unwind_fnend
, 0 },
3953 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
3954 { "personality", s_arm_unwind_personality
, 0 },
3955 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
3956 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
3957 { "save", s_arm_unwind_save
, 0 },
3958 { "vsave", s_arm_unwind_save
, 1 },
3959 { "movsp", s_arm_unwind_movsp
, 0 },
3960 { "pad", s_arm_unwind_pad
, 0 },
3961 { "setfp", s_arm_unwind_setfp
, 0 },
3962 { "unwind_raw", s_arm_unwind_raw
, 0 },
3963 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
3967 /* These are used for dwarf. */
3971 /* These are used for dwarf2. */
3972 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
3973 { "loc", dwarf2_directive_loc
, 0 },
3974 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
3976 { "extend", float_cons
, 'x' },
3977 { "ldouble", float_cons
, 'x' },
3978 { "packed", float_cons
, 'p' },
3980 {"secrel32", pe_directive_secrel
, 0},
3985 /* Parser functions used exclusively in instruction operands. */
3987 /* Generic immediate-value read function for use in insn parsing.
3988 STR points to the beginning of the immediate (the leading #);
3989 VAL receives the value; if the value is outside [MIN, MAX]
3990 issue an error. PREFIX_OPT is true if the immediate prefix is
3994 parse_immediate (char **str
, int *val
, int min
, int max
,
3995 bfd_boolean prefix_opt
)
3998 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
3999 if (exp
.X_op
!= O_constant
)
4001 inst
.error
= _("constant expression required");
4005 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4007 inst
.error
= _("immediate value out of range");
4011 *val
= exp
.X_add_number
;
4015 /* Less-generic immediate-value read function with the possibility of loading a
4016 big (64-bit) immediate, as required by Neon VMOV and VMVN immediate
4017 instructions. Puts the result directly in inst.operands[i]. */
4020 parse_big_immediate (char **str
, int i
)
4025 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4027 if (exp
.X_op
== O_constant
)
4028 inst
.operands
[i
].imm
= exp
.X_add_number
;
4029 else if (exp
.X_op
== O_big
4030 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4031 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4033 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4034 /* Bignums have their least significant bits in
4035 generic_bignum[0]. Make sure we put 32 bits in imm and
4036 32 bits in reg, in a (hopefully) portable way. */
4037 assert (parts
!= 0);
4038 inst
.operands
[i
].imm
= 0;
4039 for (j
= 0; j
< parts
; j
++, idx
++)
4040 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4041 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4042 inst
.operands
[i
].reg
= 0;
4043 for (j
= 0; j
< parts
; j
++, idx
++)
4044 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4045 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4046 inst
.operands
[i
].regisimm
= 1;
4056 /* Returns the pseudo-register number of an FPA immediate constant,
4057 or FAIL if there isn't a valid constant here. */
4060 parse_fpa_immediate (char ** str
)
4062 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4068 /* First try and match exact strings, this is to guarantee
4069 that some formats will work even for cross assembly. */
4071 for (i
= 0; fp_const
[i
]; i
++)
4073 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4077 *str
+= strlen (fp_const
[i
]);
4078 if (is_end_of_line
[(unsigned char) **str
])
4084 /* Just because we didn't get a match doesn't mean that the constant
4085 isn't valid, just that it is in a format that we don't
4086 automatically recognize. Try parsing it with the standard
4087 expression routines. */
4089 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4091 /* Look for a raw floating point number. */
4092 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4093 && is_end_of_line
[(unsigned char) *save_in
])
4095 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4097 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4099 if (words
[j
] != fp_values
[i
][j
])
4103 if (j
== MAX_LITTLENUMS
)
4111 /* Try and parse a more complex expression, this will probably fail
4112 unless the code uses a floating point prefix (eg "0f"). */
4113 save_in
= input_line_pointer
;
4114 input_line_pointer
= *str
;
4115 if (expression (&exp
) == absolute_section
4116 && exp
.X_op
== O_big
4117 && exp
.X_add_number
< 0)
4119 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4121 if (gen_to_words (words
, 5, (long) 15) == 0)
4123 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4125 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4127 if (words
[j
] != fp_values
[i
][j
])
4131 if (j
== MAX_LITTLENUMS
)
4133 *str
= input_line_pointer
;
4134 input_line_pointer
= save_in
;
4141 *str
= input_line_pointer
;
4142 input_line_pointer
= save_in
;
4143 inst
.error
= _("invalid FPA immediate expression");
4147 /* Returns 1 if a number has "quarter-precision" float format
4148 0baBbbbbbc defgh000 00000000 00000000. */
4151 is_quarter_float (unsigned imm
)
4153 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4154 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4157 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4158 0baBbbbbbc defgh000 00000000 00000000.
4159 The minus-zero case needs special handling, since it can't be encoded in the
4160 "quarter-precision" float format, but can nonetheless be loaded as an integer
4164 parse_qfloat_immediate (char **ccp
, int *immed
)
4167 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4169 skip_past_char (&str
, '#');
4171 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4173 unsigned fpword
= 0;
4176 /* Our FP word must be 32 bits (single-precision FP). */
4177 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4179 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4183 if (is_quarter_float (fpword
) || fpword
== 0x80000000)
4196 /* Shift operands. */
4199 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4202 struct asm_shift_name
4205 enum shift_kind kind
;
4208 /* Third argument to parse_shift. */
4209 enum parse_shift_mode
4211 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4212 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4213 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4214 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4215 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4218 /* Parse a <shift> specifier on an ARM data processing instruction.
4219 This has three forms:
4221 (LSL|LSR|ASL|ASR|ROR) Rs
4222 (LSL|LSR|ASL|ASR|ROR) #imm
4225 Note that ASL is assimilated to LSL in the instruction encoding, and
4226 RRX to ROR #0 (which cannot be written as such). */
4229 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4231 const struct asm_shift_name
*shift_name
;
4232 enum shift_kind shift
;
4237 for (p
= *str
; ISALPHA (*p
); p
++)
4242 inst
.error
= _("shift expression expected");
4246 shift_name
= hash_find_n (arm_shift_hsh
, *str
, p
- *str
);
4248 if (shift_name
== NULL
)
4250 inst
.error
= _("shift expression expected");
4254 shift
= shift_name
->kind
;
4258 case NO_SHIFT_RESTRICT
:
4259 case SHIFT_IMMEDIATE
: break;
4261 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4262 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4264 inst
.error
= _("'LSL' or 'ASR' required");
4269 case SHIFT_LSL_IMMEDIATE
:
4270 if (shift
!= SHIFT_LSL
)
4272 inst
.error
= _("'LSL' required");
4277 case SHIFT_ASR_IMMEDIATE
:
4278 if (shift
!= SHIFT_ASR
)
4280 inst
.error
= _("'ASR' required");
4288 if (shift
!= SHIFT_RRX
)
4290 /* Whitespace can appear here if the next thing is a bare digit. */
4291 skip_whitespace (p
);
4293 if (mode
== NO_SHIFT_RESTRICT
4294 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4296 inst
.operands
[i
].imm
= reg
;
4297 inst
.operands
[i
].immisreg
= 1;
4299 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4302 inst
.operands
[i
].shift_kind
= shift
;
4303 inst
.operands
[i
].shifted
= 1;
4308 /* Parse a <shifter_operand> for an ARM data processing instruction:
4311 #<immediate>, <rotate>
4315 where <shift> is defined by parse_shift above, and <rotate> is a
4316 multiple of 2 between 0 and 30. Validation of immediate operands
4317 is deferred to md_apply_fix. */
4320 parse_shifter_operand (char **str
, int i
)
4325 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4327 inst
.operands
[i
].reg
= value
;
4328 inst
.operands
[i
].isreg
= 1;
4330 /* parse_shift will override this if appropriate */
4331 inst
.reloc
.exp
.X_op
= O_constant
;
4332 inst
.reloc
.exp
.X_add_number
= 0;
4334 if (skip_past_comma (str
) == FAIL
)
4337 /* Shift operation on register. */
4338 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4341 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4344 if (skip_past_comma (str
) == SUCCESS
)
4346 /* #x, y -- ie explicit rotation by Y. */
4347 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
4350 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4352 inst
.error
= _("constant expression expected");
4356 value
= expr
.X_add_number
;
4357 if (value
< 0 || value
> 30 || value
% 2 != 0)
4359 inst
.error
= _("invalid rotation");
4362 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4364 inst
.error
= _("invalid constant");
4368 /* Convert to decoded value. md_apply_fix will put it back. */
4369 inst
.reloc
.exp
.X_add_number
4370 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4371 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4374 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4375 inst
.reloc
.pc_rel
= 0;
4379 /* Group relocation information. Each entry in the table contains the
4380 textual name of the relocation as may appear in assembler source
4381 and must end with a colon.
4382 Along with this textual name are the relocation codes to be used if
4383 the corresponding instruction is an ALU instruction (ADD or SUB only),
4384 an LDR, an LDRS, or an LDC. */
4386 struct group_reloc_table_entry
4397 /* Varieties of non-ALU group relocation. */
4404 static struct group_reloc_table_entry group_reloc_table
[] =
4405 { /* Program counter relative: */
4407 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4412 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4413 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4414 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4415 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4417 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4422 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4423 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4424 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4425 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4427 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4428 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4429 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4430 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4431 /* Section base relative */
4433 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4438 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4439 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4440 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4441 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4443 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4448 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4449 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4450 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4451 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4453 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4454 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4455 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4456 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4458 /* Given the address of a pointer pointing to the textual name of a group
4459 relocation as may appear in assembler source, attempt to find its details
4460 in group_reloc_table. The pointer will be updated to the character after
4461 the trailing colon. On failure, FAIL will be returned; SUCCESS
4462 otherwise. On success, *entry will be updated to point at the relevant
4463 group_reloc_table entry. */
4466 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4469 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4471 int length
= strlen (group_reloc_table
[i
].name
);
4473 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0 &&
4474 (*str
)[length
] == ':')
4476 *out
= &group_reloc_table
[i
];
4477 *str
+= (length
+ 1);
4485 /* Parse a <shifter_operand> for an ARM data processing instruction
4486 (as for parse_shifter_operand) where group relocations are allowed:
4489 #<immediate>, <rotate>
4490 #:<group_reloc>:<expression>
4494 where <group_reloc> is one of the strings defined in group_reloc_table.
4495 The hashes are optional.
4497 Everything else is as for parse_shifter_operand. */
4499 static parse_operand_result
4500 parse_shifter_operand_group_reloc (char **str
, int i
)
4502 /* Determine if we have the sequence of characters #: or just :
4503 coming next. If we do, then we check for a group relocation.
4504 If we don't, punt the whole lot to parse_shifter_operand. */
4506 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4507 || (*str
)[0] == ':')
4509 struct group_reloc_table_entry
*entry
;
4511 if ((*str
)[0] == '#')
4516 /* Try to parse a group relocation. Anything else is an error. */
4517 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4519 inst
.error
= _("unknown group relocation");
4520 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4523 /* We now have the group relocation table entry corresponding to
4524 the name in the assembler source. Next, we parse the expression. */
4525 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4526 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4528 /* Record the relocation type (always the ALU variant here). */
4529 inst
.reloc
.type
= entry
->alu_code
;
4530 assert (inst
.reloc
.type
!= 0);
4532 return PARSE_OPERAND_SUCCESS
;
4535 return parse_shifter_operand (str
, i
) == SUCCESS
4536 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4538 /* Never reached. */
4541 /* Parse all forms of an ARM address expression. Information is written
4542 to inst.operands[i] and/or inst.reloc.
4544 Preindexed addressing (.preind=1):
4546 [Rn, #offset] .reg=Rn .reloc.exp=offset
4547 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4548 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4549 .shift_kind=shift .reloc.exp=shift_imm
4551 These three may have a trailing ! which causes .writeback to be set also.
4553 Postindexed addressing (.postind=1, .writeback=1):
4555 [Rn], #offset .reg=Rn .reloc.exp=offset
4556 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4557 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4558 .shift_kind=shift .reloc.exp=shift_imm
4560 Unindexed addressing (.preind=0, .postind=0):
4562 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4566 [Rn]{!} shorthand for [Rn,#0]{!}
4567 =immediate .isreg=0 .reloc.exp=immediate
4568 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4570 It is the caller's responsibility to check for addressing modes not
4571 supported by the instruction, and to set inst.reloc.type. */
4573 static parse_operand_result
4574 parse_address_main (char **str
, int i
, int group_relocations
,
4575 group_reloc_type group_type
)
4580 if (skip_past_char (&p
, '[') == FAIL
)
4582 if (skip_past_char (&p
, '=') == FAIL
)
4584 /* bare address - translate to PC-relative offset */
4585 inst
.reloc
.pc_rel
= 1;
4586 inst
.operands
[i
].reg
= REG_PC
;
4587 inst
.operands
[i
].isreg
= 1;
4588 inst
.operands
[i
].preind
= 1;
4590 /* else a load-constant pseudo op, no special treatment needed here */
4592 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4593 return PARSE_OPERAND_FAIL
;
4596 return PARSE_OPERAND_SUCCESS
;
4599 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4601 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4602 return PARSE_OPERAND_FAIL
;
4604 inst
.operands
[i
].reg
= reg
;
4605 inst
.operands
[i
].isreg
= 1;
4607 if (skip_past_comma (&p
) == SUCCESS
)
4609 inst
.operands
[i
].preind
= 1;
4612 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4614 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4616 inst
.operands
[i
].imm
= reg
;
4617 inst
.operands
[i
].immisreg
= 1;
4619 if (skip_past_comma (&p
) == SUCCESS
)
4620 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4621 return PARSE_OPERAND_FAIL
;
4623 else if (skip_past_char (&p
, ':') == SUCCESS
)
4625 /* FIXME: '@' should be used here, but it's filtered out by generic
4626 code before we get to see it here. This may be subject to
4629 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4630 if (exp
.X_op
!= O_constant
)
4632 inst
.error
= _("alignment must be constant");
4633 return PARSE_OPERAND_FAIL
;
4635 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4636 inst
.operands
[i
].immisalign
= 1;
4637 /* Alignments are not pre-indexes. */
4638 inst
.operands
[i
].preind
= 0;
4642 if (inst
.operands
[i
].negative
)
4644 inst
.operands
[i
].negative
= 0;
4648 if (group_relocations
&&
4649 ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
4652 struct group_reloc_table_entry
*entry
;
4654 /* Skip over the #: or : sequence. */
4660 /* Try to parse a group relocation. Anything else is an
4662 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
4664 inst
.error
= _("unknown group relocation");
4665 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4668 /* We now have the group relocation table entry corresponding to
4669 the name in the assembler source. Next, we parse the
4671 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4672 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4674 /* Record the relocation type. */
4678 inst
.reloc
.type
= entry
->ldr_code
;
4682 inst
.reloc
.type
= entry
->ldrs_code
;
4686 inst
.reloc
.type
= entry
->ldc_code
;
4693 if (inst
.reloc
.type
== 0)
4695 inst
.error
= _("this group relocation is not allowed on this instruction");
4696 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4700 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4701 return PARSE_OPERAND_FAIL
;
4705 if (skip_past_char (&p
, ']') == FAIL
)
4707 inst
.error
= _("']' expected");
4708 return PARSE_OPERAND_FAIL
;
4711 if (skip_past_char (&p
, '!') == SUCCESS
)
4712 inst
.operands
[i
].writeback
= 1;
4714 else if (skip_past_comma (&p
) == SUCCESS
)
4716 if (skip_past_char (&p
, '{') == SUCCESS
)
4718 /* [Rn], {expr} - unindexed, with option */
4719 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
4720 0, 255, TRUE
) == FAIL
)
4721 return PARSE_OPERAND_FAIL
;
4723 if (skip_past_char (&p
, '}') == FAIL
)
4725 inst
.error
= _("'}' expected at end of 'option' field");
4726 return PARSE_OPERAND_FAIL
;
4728 if (inst
.operands
[i
].preind
)
4730 inst
.error
= _("cannot combine index with option");
4731 return PARSE_OPERAND_FAIL
;
4734 return PARSE_OPERAND_SUCCESS
;
4738 inst
.operands
[i
].postind
= 1;
4739 inst
.operands
[i
].writeback
= 1;
4741 if (inst
.operands
[i
].preind
)
4743 inst
.error
= _("cannot combine pre- and post-indexing");
4744 return PARSE_OPERAND_FAIL
;
4748 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4750 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4752 /* We might be using the immediate for alignment already. If we
4753 are, OR the register number into the low-order bits. */
4754 if (inst
.operands
[i
].immisalign
)
4755 inst
.operands
[i
].imm
|= reg
;
4757 inst
.operands
[i
].imm
= reg
;
4758 inst
.operands
[i
].immisreg
= 1;
4760 if (skip_past_comma (&p
) == SUCCESS
)
4761 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4762 return PARSE_OPERAND_FAIL
;
4766 if (inst
.operands
[i
].negative
)
4768 inst
.operands
[i
].negative
= 0;
4771 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4772 return PARSE_OPERAND_FAIL
;
4777 /* If at this point neither .preind nor .postind is set, we have a
4778 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
4779 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
4781 inst
.operands
[i
].preind
= 1;
4782 inst
.reloc
.exp
.X_op
= O_constant
;
4783 inst
.reloc
.exp
.X_add_number
= 0;
4786 return PARSE_OPERAND_SUCCESS
;
4790 parse_address (char **str
, int i
)
4792 return parse_address_main (str
, i
, 0, 0) == PARSE_OPERAND_SUCCESS
4796 static parse_operand_result
4797 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
4799 return parse_address_main (str
, i
, 1, type
);
4802 /* Parse an operand for a MOVW or MOVT instruction. */
4804 parse_half (char **str
)
4809 skip_past_char (&p
, '#');
4810 if (strncasecmp (p
, ":lower16:", 9) == 0)
4811 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
4812 else if (strncasecmp (p
, ":upper16:", 9) == 0)
4813 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
4815 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4821 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4824 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4826 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4828 inst
.error
= _("constant expression expected");
4831 if (inst
.reloc
.exp
.X_add_number
< 0
4832 || inst
.reloc
.exp
.X_add_number
> 0xffff)
4834 inst
.error
= _("immediate value out of range");
4842 /* Miscellaneous. */
4844 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
4845 or a bitmask suitable to be or-ed into the ARM msr instruction. */
4847 parse_psr (char **str
)
4850 unsigned long psr_field
;
4851 const struct asm_psr
*psr
;
4854 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
4855 feature for ease of use and backwards compatibility. */
4857 if (strncasecmp (p
, "SPSR", 4) == 0)
4858 psr_field
= SPSR_BIT
;
4859 else if (strncasecmp (p
, "CPSR", 4) == 0)
4866 while (ISALNUM (*p
) || *p
== '_');
4868 psr
= hash_find_n (arm_v7m_psr_hsh
, start
, p
- start
);
4879 /* A suffix follows. */
4885 while (ISALNUM (*p
) || *p
== '_');
4887 psr
= hash_find_n (arm_psr_hsh
, start
, p
- start
);
4891 psr_field
|= psr
->field
;
4896 goto error
; /* Garbage after "[CS]PSR". */
4898 psr_field
|= (PSR_c
| PSR_f
);
4904 inst
.error
= _("flag for {c}psr instruction expected");
4908 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
4909 value suitable for splatting into the AIF field of the instruction. */
4912 parse_cps_flags (char **str
)
4921 case '\0': case ',':
4924 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
4925 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
4926 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
4929 inst
.error
= _("unrecognized CPS flag");
4934 if (saw_a_flag
== 0)
4936 inst
.error
= _("missing CPS flags");
4944 /* Parse an endian specifier ("BE" or "LE", case insensitive);
4945 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
4948 parse_endian_specifier (char **str
)
4953 if (strncasecmp (s
, "BE", 2))
4955 else if (strncasecmp (s
, "LE", 2))
4959 inst
.error
= _("valid endian specifiers are be or le");
4963 if (ISALNUM (s
[2]) || s
[2] == '_')
4965 inst
.error
= _("valid endian specifiers are be or le");
4970 return little_endian
;
4973 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
4974 value suitable for poking into the rotate field of an sxt or sxta
4975 instruction, or FAIL on error. */
4978 parse_ror (char **str
)
4983 if (strncasecmp (s
, "ROR", 3) == 0)
4987 inst
.error
= _("missing rotation field after comma");
4991 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
4996 case 0: *str
= s
; return 0x0;
4997 case 8: *str
= s
; return 0x1;
4998 case 16: *str
= s
; return 0x2;
4999 case 24: *str
= s
; return 0x3;
5002 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5007 /* Parse a conditional code (from conds[] below). The value returned is in the
5008 range 0 .. 14, or FAIL. */
5010 parse_cond (char **str
)
5013 const struct asm_cond
*c
;
5016 while (ISALPHA (*q
))
5019 c
= hash_find_n (arm_cond_hsh
, p
, q
- p
);
5022 inst
.error
= _("condition required");
5030 /* Parse an option for a barrier instruction. Returns the encoding for the
5033 parse_barrier (char **str
)
5036 const struct asm_barrier_opt
*o
;
5039 while (ISALPHA (*q
))
5042 o
= hash_find_n (arm_barrier_opt_hsh
, p
, q
- p
);
5050 /* Parse the operands of a table branch instruction. Similar to a memory
5053 parse_tb (char **str
)
5058 if (skip_past_char (&p
, '[') == FAIL
)
5060 inst
.error
= _("'[' expected");
5064 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5066 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5069 inst
.operands
[0].reg
= reg
;
5071 if (skip_past_comma (&p
) == FAIL
)
5073 inst
.error
= _("',' expected");
5077 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5079 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5082 inst
.operands
[0].imm
= reg
;
5084 if (skip_past_comma (&p
) == SUCCESS
)
5086 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5088 if (inst
.reloc
.exp
.X_add_number
!= 1)
5090 inst
.error
= _("invalid shift");
5093 inst
.operands
[0].shifted
= 1;
5096 if (skip_past_char (&p
, ']') == FAIL
)
5098 inst
.error
= _("']' expected");
5105 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5106 information on the types the operands can take and how they are encoded.
5107 Up to four operands may be read; this function handles setting the
5108 ".present" field for each read operand itself.
5109 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5110 else returns FAIL. */
5113 parse_neon_mov (char **str
, int *which_operand
)
5115 int i
= *which_operand
, val
;
5116 enum arm_reg_type rtype
;
5118 struct neon_type_el optype
;
5120 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5122 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5123 inst
.operands
[i
].reg
= val
;
5124 inst
.operands
[i
].isscalar
= 1;
5125 inst
.operands
[i
].vectype
= optype
;
5126 inst
.operands
[i
++].present
= 1;
5128 if (skip_past_comma (&ptr
) == FAIL
)
5131 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5134 inst
.operands
[i
].reg
= val
;
5135 inst
.operands
[i
].isreg
= 1;
5136 inst
.operands
[i
].present
= 1;
5138 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5141 /* Cases 0, 1, 2, 3, 5 (D only). */
5142 if (skip_past_comma (&ptr
) == FAIL
)
5145 inst
.operands
[i
].reg
= val
;
5146 inst
.operands
[i
].isreg
= 1;
5147 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5148 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5149 inst
.operands
[i
].isvec
= 1;
5150 inst
.operands
[i
].vectype
= optype
;
5151 inst
.operands
[i
++].present
= 1;
5153 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5155 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5156 Case 13: VMOV <Sd>, <Rm> */
5157 inst
.operands
[i
].reg
= val
;
5158 inst
.operands
[i
].isreg
= 1;
5159 inst
.operands
[i
].present
= 1;
5161 if (rtype
== REG_TYPE_NQ
)
5163 first_error (_("can't use Neon quad register here"));
5166 else if (rtype
!= REG_TYPE_VFS
)
5169 if (skip_past_comma (&ptr
) == FAIL
)
5171 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5173 inst
.operands
[i
].reg
= val
;
5174 inst
.operands
[i
].isreg
= 1;
5175 inst
.operands
[i
].present
= 1;
5178 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5179 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5180 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5181 Case 10: VMOV.F32 <Sd>, #<imm>
5182 Case 11: VMOV.F64 <Dd>, #<imm> */
5184 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5185 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5186 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5188 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5191 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5192 Case 1: VMOV<c><q> <Dd>, <Dm>
5193 Case 8: VMOV.F32 <Sd>, <Sm>
5194 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5196 inst
.operands
[i
].reg
= val
;
5197 inst
.operands
[i
].isreg
= 1;
5198 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5199 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5200 inst
.operands
[i
].isvec
= 1;
5201 inst
.operands
[i
].vectype
= optype
;
5202 inst
.operands
[i
].present
= 1;
5204 if (skip_past_comma (&ptr
) == SUCCESS
)
5209 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5212 inst
.operands
[i
].reg
= val
;
5213 inst
.operands
[i
].isreg
= 1;
5214 inst
.operands
[i
++].present
= 1;
5216 if (skip_past_comma (&ptr
) == FAIL
)
5219 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5222 inst
.operands
[i
].reg
= val
;
5223 inst
.operands
[i
].isreg
= 1;
5224 inst
.operands
[i
++].present
= 1;
5229 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5233 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5236 inst
.operands
[i
].reg
= val
;
5237 inst
.operands
[i
].isreg
= 1;
5238 inst
.operands
[i
++].present
= 1;
5240 if (skip_past_comma (&ptr
) == FAIL
)
5243 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5245 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5246 inst
.operands
[i
].reg
= val
;
5247 inst
.operands
[i
].isscalar
= 1;
5248 inst
.operands
[i
].present
= 1;
5249 inst
.operands
[i
].vectype
= optype
;
5251 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5253 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5254 inst
.operands
[i
].reg
= val
;
5255 inst
.operands
[i
].isreg
= 1;
5256 inst
.operands
[i
++].present
= 1;
5258 if (skip_past_comma (&ptr
) == FAIL
)
5261 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5264 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5268 inst
.operands
[i
].reg
= val
;
5269 inst
.operands
[i
].isreg
= 1;
5270 inst
.operands
[i
].isvec
= 1;
5271 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5272 inst
.operands
[i
].vectype
= optype
;
5273 inst
.operands
[i
].present
= 1;
5275 if (rtype
== REG_TYPE_VFS
)
5279 if (skip_past_comma (&ptr
) == FAIL
)
5281 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5284 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5287 inst
.operands
[i
].reg
= val
;
5288 inst
.operands
[i
].isreg
= 1;
5289 inst
.operands
[i
].isvec
= 1;
5290 inst
.operands
[i
].issingle
= 1;
5291 inst
.operands
[i
].vectype
= optype
;
5292 inst
.operands
[i
].present
= 1;
5295 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5299 inst
.operands
[i
].reg
= val
;
5300 inst
.operands
[i
].isreg
= 1;
5301 inst
.operands
[i
].isvec
= 1;
5302 inst
.operands
[i
].issingle
= 1;
5303 inst
.operands
[i
].vectype
= optype
;
5304 inst
.operands
[i
++].present
= 1;
5309 first_error (_("parse error"));
5313 /* Successfully parsed the operands. Update args. */
5319 first_error (_("expected comma"));
5323 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5327 /* Matcher codes for parse_operands. */
5328 enum operand_parse_code
5330 OP_stop
, /* end of line */
5332 OP_RR
, /* ARM register */
5333 OP_RRnpc
, /* ARM register, not r15 */
5334 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5335 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5336 OP_RCP
, /* Coprocessor number */
5337 OP_RCN
, /* Coprocessor register */
5338 OP_RF
, /* FPA register */
5339 OP_RVS
, /* VFP single precision register */
5340 OP_RVD
, /* VFP double precision register (0..15) */
5341 OP_RND
, /* Neon double precision register (0..31) */
5342 OP_RNQ
, /* Neon quad precision register */
5343 OP_RVSD
, /* VFP single or double precision register */
5344 OP_RNDQ
, /* Neon double or quad precision register */
5345 OP_RNSDQ
, /* Neon single, double or quad precision register */
5346 OP_RNSC
, /* Neon scalar D[X] */
5347 OP_RVC
, /* VFP control register */
5348 OP_RMF
, /* Maverick F register */
5349 OP_RMD
, /* Maverick D register */
5350 OP_RMFX
, /* Maverick FX register */
5351 OP_RMDX
, /* Maverick DX register */
5352 OP_RMAX
, /* Maverick AX register */
5353 OP_RMDS
, /* Maverick DSPSC register */
5354 OP_RIWR
, /* iWMMXt wR register */
5355 OP_RIWC
, /* iWMMXt wC register */
5356 OP_RIWG
, /* iWMMXt wCG register */
5357 OP_RXA
, /* XScale accumulator register */
5359 OP_REGLST
, /* ARM register list */
5360 OP_VRSLST
, /* VFP single-precision register list */
5361 OP_VRDLST
, /* VFP double-precision register list */
5362 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5363 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5364 OP_NSTRLST
, /* Neon element/structure list */
5366 OP_NILO
, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5367 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5368 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5369 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5370 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5371 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5372 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5373 OP_VMOV
, /* Neon VMOV operands. */
5374 OP_RNDQ_IMVNb
,/* Neon D or Q reg, or immediate good for VMVN. */
5375 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5376 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5378 OP_I0
, /* immediate zero */
5379 OP_I7
, /* immediate value 0 .. 7 */
5380 OP_I15
, /* 0 .. 15 */
5381 OP_I16
, /* 1 .. 16 */
5382 OP_I16z
, /* 0 .. 16 */
5383 OP_I31
, /* 0 .. 31 */
5384 OP_I31w
, /* 0 .. 31, optional trailing ! */
5385 OP_I32
, /* 1 .. 32 */
5386 OP_I32z
, /* 0 .. 32 */
5387 OP_I63
, /* 0 .. 63 */
5388 OP_I63s
, /* -64 .. 63 */
5389 OP_I64
, /* 1 .. 64 */
5390 OP_I64z
, /* 0 .. 64 */
5391 OP_I255
, /* 0 .. 255 */
5393 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5394 OP_I7b
, /* 0 .. 7 */
5395 OP_I15b
, /* 0 .. 15 */
5396 OP_I31b
, /* 0 .. 31 */
5398 OP_SH
, /* shifter operand */
5399 OP_SHG
, /* shifter operand with possible group relocation */
5400 OP_ADDR
, /* Memory address expression (any mode) */
5401 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5402 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5403 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5404 OP_EXP
, /* arbitrary expression */
5405 OP_EXPi
, /* same, with optional immediate prefix */
5406 OP_EXPr
, /* same, with optional relocation suffix */
5407 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5409 OP_CPSF
, /* CPS flags */
5410 OP_ENDI
, /* Endianness specifier */
5411 OP_PSR
, /* CPSR/SPSR mask for msr */
5412 OP_COND
, /* conditional code */
5413 OP_TB
, /* Table branch. */
5415 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5416 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5418 OP_RRnpc_I0
, /* ARM register or literal 0 */
5419 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5420 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5421 OP_RF_IF
, /* FPA register or immediate */
5422 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5423 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5425 /* Optional operands. */
5426 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5427 OP_oI31b
, /* 0 .. 31 */
5428 OP_oI32b
, /* 1 .. 32 */
5429 OP_oIffffb
, /* 0 .. 65535 */
5430 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5432 OP_oRR
, /* ARM register */
5433 OP_oRRnpc
, /* ARM register, not the PC */
5434 OP_oRND
, /* Optional Neon double precision register */
5435 OP_oRNQ
, /* Optional Neon quad precision register */
5436 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5437 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5438 OP_oSHll
, /* LSL immediate */
5439 OP_oSHar
, /* ASR immediate */
5440 OP_oSHllar
, /* LSL or ASR immediate */
5441 OP_oROR
, /* ROR 0/8/16/24 */
5442 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5444 OP_FIRST_OPTIONAL
= OP_oI7b
5447 /* Generic instruction operand parser. This does no encoding and no
5448 semantic validation; it merely squirrels values away in the inst
5449 structure. Returns SUCCESS or FAIL depending on whether the
5450 specified grammar matched. */
5452 parse_operands (char *str
, const unsigned char *pattern
)
5454 unsigned const char *upat
= pattern
;
5455 char *backtrack_pos
= 0;
5456 const char *backtrack_error
= 0;
5457 int i
, val
, backtrack_index
= 0;
5458 enum arm_reg_type rtype
;
5459 parse_operand_result result
;
5461 #define po_char_or_fail(chr) do { \
5462 if (skip_past_char (&str, chr) == FAIL) \
5466 #define po_reg_or_fail(regtype) do { \
5467 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5468 &inst.operands[i].vectype); \
5471 first_error (_(reg_expected_msgs[regtype])); \
5474 inst.operands[i].reg = val; \
5475 inst.operands[i].isreg = 1; \
5476 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5477 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5478 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5479 || rtype == REG_TYPE_VFD \
5480 || rtype == REG_TYPE_NQ); \
5483 #define po_reg_or_goto(regtype, label) do { \
5484 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5485 &inst.operands[i].vectype); \
5489 inst.operands[i].reg = val; \
5490 inst.operands[i].isreg = 1; \
5491 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5492 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5493 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5494 || rtype == REG_TYPE_VFD \
5495 || rtype == REG_TYPE_NQ); \
5498 #define po_imm_or_fail(min, max, popt) do { \
5499 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5501 inst.operands[i].imm = val; \
5504 #define po_scalar_or_goto(elsz, label) do { \
5505 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \
5508 inst.operands[i].reg = val; \
5509 inst.operands[i].isscalar = 1; \
5512 #define po_misc_or_fail(expr) do { \
5517 #define po_misc_or_fail_no_backtrack(expr) do { \
5519 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
5520 backtrack_pos = 0; \
5521 if (result != PARSE_OPERAND_SUCCESS) \
5525 skip_whitespace (str
);
5527 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5529 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5531 /* Remember where we are in case we need to backtrack. */
5532 assert (!backtrack_pos
);
5533 backtrack_pos
= str
;
5534 backtrack_error
= inst
.error
;
5535 backtrack_index
= i
;
5539 po_char_or_fail (',');
5547 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5548 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5549 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5550 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5551 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5552 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5554 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5555 case OP_RVC
: po_reg_or_fail (REG_TYPE_VFC
); break;
5556 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5557 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5558 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5559 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5560 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5561 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5562 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5563 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5564 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5565 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5567 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
5569 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
5570 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
5572 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
5574 /* Neon scalar. Using an element size of 8 means that some invalid
5575 scalars are accepted here, so deal with those in later code. */
5576 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
5578 /* WARNING: We can expand to two operands here. This has the potential
5579 to totally confuse the backtracking mechanism! It will be OK at
5580 least as long as we don't try to use optional args as well,
5584 po_reg_or_goto (REG_TYPE_NDQ
, try_imm
);
5585 inst
.operands
[i
].present
= 1;
5587 skip_past_comma (&str
);
5588 po_reg_or_goto (REG_TYPE_NDQ
, one_reg_only
);
5591 /* Optional register operand was omitted. Unfortunately, it's in
5592 operands[i-1] and we need it to be in inst.operands[i]. Fix that
5593 here (this is a bit grotty). */
5594 inst
.operands
[i
] = inst
.operands
[i
-1];
5595 inst
.operands
[i
-1].present
= 0;
5598 /* Immediate gets verified properly later, so accept any now. */
5599 po_imm_or_fail (INT_MIN
, INT_MAX
, TRUE
);
5605 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
5608 po_imm_or_fail (0, 0, TRUE
);
5613 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
5618 po_scalar_or_goto (8, try_rr
);
5621 po_reg_or_fail (REG_TYPE_RN
);
5627 po_scalar_or_goto (8, try_nsdq
);
5630 po_reg_or_fail (REG_TYPE_NSDQ
);
5636 po_scalar_or_goto (8, try_ndq
);
5639 po_reg_or_fail (REG_TYPE_NDQ
);
5645 po_scalar_or_goto (8, try_vfd
);
5648 po_reg_or_fail (REG_TYPE_VFD
);
5653 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
5654 not careful then bad things might happen. */
5655 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
5660 po_reg_or_goto (REG_TYPE_NDQ
, try_mvnimm
);
5663 /* There's a possibility of getting a 64-bit immediate here, so
5664 we need special handling. */
5665 if (parse_big_immediate (&str
, i
) == FAIL
)
5667 inst
.error
= _("immediate value is out of range");
5675 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
5678 po_imm_or_fail (0, 63, TRUE
);
5683 po_char_or_fail ('[');
5684 po_reg_or_fail (REG_TYPE_RN
);
5685 po_char_or_fail (']');
5689 po_reg_or_fail (REG_TYPE_RN
);
5690 if (skip_past_char (&str
, '!') == SUCCESS
)
5691 inst
.operands
[i
].writeback
= 1;
5695 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
5696 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
5697 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
5698 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
5699 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
5700 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
5701 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
5702 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
5703 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
5704 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
5705 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
5706 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
5708 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
5710 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
5711 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
5713 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
5714 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
5715 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
5717 /* Immediate variants */
5719 po_char_or_fail ('{');
5720 po_imm_or_fail (0, 255, TRUE
);
5721 po_char_or_fail ('}');
5725 /* The expression parser chokes on a trailing !, so we have
5726 to find it first and zap it. */
5729 while (*s
&& *s
!= ',')
5734 inst
.operands
[i
].writeback
= 1;
5736 po_imm_or_fail (0, 31, TRUE
);
5744 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5749 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5754 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5756 if (inst
.reloc
.exp
.X_op
== O_symbol
)
5758 val
= parse_reloc (&str
);
5761 inst
.error
= _("unrecognized relocation suffix");
5764 else if (val
!= BFD_RELOC_UNUSED
)
5766 inst
.operands
[i
].imm
= val
;
5767 inst
.operands
[i
].hasreloc
= 1;
5772 /* Operand for MOVW or MOVT. */
5774 po_misc_or_fail (parse_half (&str
));
5777 /* Register or expression */
5778 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
5779 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
5781 /* Register or immediate */
5782 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
5783 I0
: po_imm_or_fail (0, 0, FALSE
); break;
5785 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
5787 if (!is_immediate_prefix (*str
))
5790 val
= parse_fpa_immediate (&str
);
5793 /* FPA immediates are encoded as registers 8-15.
5794 parse_fpa_immediate has already applied the offset. */
5795 inst
.operands
[i
].reg
= val
;
5796 inst
.operands
[i
].isreg
= 1;
5799 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
5800 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
5802 /* Two kinds of register */
5805 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5807 || (rege
->type
!= REG_TYPE_MMXWR
5808 && rege
->type
!= REG_TYPE_MMXWC
5809 && rege
->type
!= REG_TYPE_MMXWCG
))
5811 inst
.error
= _("iWMMXt data or control register expected");
5814 inst
.operands
[i
].reg
= rege
->number
;
5815 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
5821 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5823 || (rege
->type
!= REG_TYPE_MMXWC
5824 && rege
->type
!= REG_TYPE_MMXWCG
))
5826 inst
.error
= _("iWMMXt control register expected");
5829 inst
.operands
[i
].reg
= rege
->number
;
5830 inst
.operands
[i
].isreg
= 1;
5835 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
5836 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
5837 case OP_oROR
: val
= parse_ror (&str
); break;
5838 case OP_PSR
: val
= parse_psr (&str
); break;
5839 case OP_COND
: val
= parse_cond (&str
); break;
5840 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
5843 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
5844 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
5847 val
= parse_psr (&str
);
5851 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
5854 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
5856 if (strncasecmp (str
, "APSR_", 5) == 0)
5863 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
5864 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
5865 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
5866 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
5867 default: found
= 16;
5871 inst
.operands
[i
].isvec
= 1;
5878 po_misc_or_fail (parse_tb (&str
));
5881 /* Register lists */
5883 val
= parse_reg_list (&str
);
5886 inst
.operands
[1].writeback
= 1;
5892 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
5896 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
5900 /* Allow Q registers too. */
5901 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5906 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5908 inst
.operands
[i
].issingle
= 1;
5913 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5918 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
5919 &inst
.operands
[i
].vectype
);
5922 /* Addressing modes */
5924 po_misc_or_fail (parse_address (&str
, i
));
5928 po_misc_or_fail_no_backtrack (
5929 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
5933 po_misc_or_fail_no_backtrack (
5934 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
5938 po_misc_or_fail_no_backtrack (
5939 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
5943 po_misc_or_fail (parse_shifter_operand (&str
, i
));
5947 po_misc_or_fail_no_backtrack (
5948 parse_shifter_operand_group_reloc (&str
, i
));
5952 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
5956 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
5960 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
5964 as_fatal ("unhandled operand code %d", upat
[i
]);
5967 /* Various value-based sanity checks and shared operations. We
5968 do not signal immediate failures for the register constraints;
5969 this allows a syntax error to take precedence. */
5977 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
5978 inst
.error
= BAD_PC
;
5996 inst
.operands
[i
].imm
= val
;
6003 /* If we get here, this operand was successfully parsed. */
6004 inst
.operands
[i
].present
= 1;
6008 inst
.error
= BAD_ARGS
;
6013 /* The parse routine should already have set inst.error, but set a
6014 defaut here just in case. */
6016 inst
.error
= _("syntax error");
6020 /* Do not backtrack over a trailing optional argument that
6021 absorbed some text. We will only fail again, with the
6022 'garbage following instruction' error message, which is
6023 probably less helpful than the current one. */
6024 if (backtrack_index
== i
&& backtrack_pos
!= str
6025 && upat
[i
+1] == OP_stop
)
6028 inst
.error
= _("syntax error");
6032 /* Try again, skipping the optional argument at backtrack_pos. */
6033 str
= backtrack_pos
;
6034 inst
.error
= backtrack_error
;
6035 inst
.operands
[backtrack_index
].present
= 0;
6036 i
= backtrack_index
;
6040 /* Check that we have parsed all the arguments. */
6041 if (*str
!= '\0' && !inst
.error
)
6042 inst
.error
= _("garbage following instruction");
6044 return inst
.error
? FAIL
: SUCCESS
;
6047 #undef po_char_or_fail
6048 #undef po_reg_or_fail
6049 #undef po_reg_or_goto
6050 #undef po_imm_or_fail
6051 #undef po_scalar_or_fail
6053 /* Shorthand macro for instruction encoding functions issuing errors. */
6054 #define constraint(expr, err) do { \
6062 /* Functions for operand encoding. ARM, then Thumb. */
6064 #define rotate_left(v, n) (v << n | v >> (32 - n))
6066 /* If VAL can be encoded in the immediate field of an ARM instruction,
6067 return the encoded form. Otherwise, return FAIL. */
6070 encode_arm_immediate (unsigned int val
)
6074 for (i
= 0; i
< 32; i
+= 2)
6075 if ((a
= rotate_left (val
, i
)) <= 0xff)
6076 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6081 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6082 return the encoded form. Otherwise, return FAIL. */
6084 encode_thumb32_immediate (unsigned int val
)
6091 for (i
= 1; i
<= 24; i
++)
6094 if ((val
& ~(0xff << i
)) == 0)
6095 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6099 if (val
== ((a
<< 16) | a
))
6101 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6105 if (val
== ((a
<< 16) | a
))
6106 return 0x200 | (a
>> 8);
6110 /* Encode a VFP SP or DP register number into inst.instruction. */
6113 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6115 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6118 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
6121 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6124 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6129 first_error (_("D register out of range for selected VFP version"));
6137 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6141 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6145 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6149 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6153 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6157 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6165 /* Encode a <shift> in an ARM-format instruction. The immediate,
6166 if any, is handled by md_apply_fix. */
6168 encode_arm_shift (int i
)
6170 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6171 inst
.instruction
|= SHIFT_ROR
<< 5;
6174 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6175 if (inst
.operands
[i
].immisreg
)
6177 inst
.instruction
|= SHIFT_BY_REG
;
6178 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6181 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6186 encode_arm_shifter_operand (int i
)
6188 if (inst
.operands
[i
].isreg
)
6190 inst
.instruction
|= inst
.operands
[i
].reg
;
6191 encode_arm_shift (i
);
6194 inst
.instruction
|= INST_IMMEDIATE
;
6197 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6199 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6201 assert (inst
.operands
[i
].isreg
);
6202 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6204 if (inst
.operands
[i
].preind
)
6208 inst
.error
= _("instruction does not accept preindexed addressing");
6211 inst
.instruction
|= PRE_INDEX
;
6212 if (inst
.operands
[i
].writeback
)
6213 inst
.instruction
|= WRITE_BACK
;
6216 else if (inst
.operands
[i
].postind
)
6218 assert (inst
.operands
[i
].writeback
);
6220 inst
.instruction
|= WRITE_BACK
;
6222 else /* unindexed - only for coprocessor */
6224 inst
.error
= _("instruction does not accept unindexed addressing");
6228 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6229 && (((inst
.instruction
& 0x000f0000) >> 16)
6230 == ((inst
.instruction
& 0x0000f000) >> 12)))
6231 as_warn ((inst
.instruction
& LOAD_BIT
)
6232 ? _("destination register same as write-back base")
6233 : _("source register same as write-back base"));
6236 /* inst.operands[i] was set up by parse_address. Encode it into an
6237 ARM-format mode 2 load or store instruction. If is_t is true,
6238 reject forms that cannot be used with a T instruction (i.e. not
6241 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6243 encode_arm_addr_mode_common (i
, is_t
);
6245 if (inst
.operands
[i
].immisreg
)
6247 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6248 inst
.instruction
|= inst
.operands
[i
].imm
;
6249 if (!inst
.operands
[i
].negative
)
6250 inst
.instruction
|= INDEX_UP
;
6251 if (inst
.operands
[i
].shifted
)
6253 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6254 inst
.instruction
|= SHIFT_ROR
<< 5;
6257 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6258 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6262 else /* immediate offset in inst.reloc */
6264 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6265 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6269 /* inst.operands[i] was set up by parse_address. Encode it into an
6270 ARM-format mode 3 load or store instruction. Reject forms that
6271 cannot be used with such instructions. If is_t is true, reject
6272 forms that cannot be used with a T instruction (i.e. not
6275 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6277 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6279 inst
.error
= _("instruction does not accept scaled register index");
6283 encode_arm_addr_mode_common (i
, is_t
);
6285 if (inst
.operands
[i
].immisreg
)
6287 inst
.instruction
|= inst
.operands
[i
].imm
;
6288 if (!inst
.operands
[i
].negative
)
6289 inst
.instruction
|= INDEX_UP
;
6291 else /* immediate offset in inst.reloc */
6293 inst
.instruction
|= HWOFFSET_IMM
;
6294 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6295 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6299 /* inst.operands[i] was set up by parse_address. Encode it into an
6300 ARM-format instruction. Reject all forms which cannot be encoded
6301 into a coprocessor load/store instruction. If wb_ok is false,
6302 reject use of writeback; if unind_ok is false, reject use of
6303 unindexed addressing. If reloc_override is not 0, use it instead
6304 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6305 (in which case it is preserved). */
6308 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6310 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6312 assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6314 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6316 assert (!inst
.operands
[i
].writeback
);
6319 inst
.error
= _("instruction does not support unindexed addressing");
6322 inst
.instruction
|= inst
.operands
[i
].imm
;
6323 inst
.instruction
|= INDEX_UP
;
6327 if (inst
.operands
[i
].preind
)
6328 inst
.instruction
|= PRE_INDEX
;
6330 if (inst
.operands
[i
].writeback
)
6332 if (inst
.operands
[i
].reg
== REG_PC
)
6334 inst
.error
= _("pc may not be used with write-back");
6339 inst
.error
= _("instruction does not support writeback");
6342 inst
.instruction
|= WRITE_BACK
;
6346 inst
.reloc
.type
= reloc_override
;
6347 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6348 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6349 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6352 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6354 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6360 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6361 Determine whether it can be performed with a move instruction; if
6362 it can, convert inst.instruction to that move instruction and
6363 return 1; if it can't, convert inst.instruction to a literal-pool
6364 load and return 0. If this is not a valid thing to do in the
6365 current context, set inst.error and return 1.
6367 inst.operands[i] describes the destination register. */
6370 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6375 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6379 if ((inst
.instruction
& tbit
) == 0)
6381 inst
.error
= _("invalid pseudo operation");
6384 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6386 inst
.error
= _("constant expression expected");
6389 if (inst
.reloc
.exp
.X_op
== O_constant
)
6393 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6395 /* This can be done with a mov(1) instruction. */
6396 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6397 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6403 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6406 /* This can be done with a mov instruction. */
6407 inst
.instruction
&= LITERAL_MASK
;
6408 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6409 inst
.instruction
|= value
& 0xfff;
6413 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6416 /* This can be done with a mvn instruction. */
6417 inst
.instruction
&= LITERAL_MASK
;
6418 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6419 inst
.instruction
|= value
& 0xfff;
6425 if (add_to_lit_pool () == FAIL
)
6427 inst
.error
= _("literal pool insertion failed");
6430 inst
.operands
[1].reg
= REG_PC
;
6431 inst
.operands
[1].isreg
= 1;
6432 inst
.operands
[1].preind
= 1;
6433 inst
.reloc
.pc_rel
= 1;
6434 inst
.reloc
.type
= (thumb_p
6435 ? BFD_RELOC_ARM_THUMB_OFFSET
6437 ? BFD_RELOC_ARM_HWLITERAL
6438 : BFD_RELOC_ARM_LITERAL
));
6442 /* Functions for instruction encoding, sorted by subarchitecture.
6443 First some generics; their names are taken from the conventional
6444 bit positions for register arguments in ARM format instructions. */
6454 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6460 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6461 inst
.instruction
|= inst
.operands
[1].reg
;
6467 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6468 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6474 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6475 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6481 unsigned Rn
= inst
.operands
[2].reg
;
6482 /* Enforce restrictions on SWP instruction. */
6483 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6484 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6485 _("Rn must not overlap other operands"));
6486 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6487 inst
.instruction
|= inst
.operands
[1].reg
;
6488 inst
.instruction
|= Rn
<< 16;
6494 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6495 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6496 inst
.instruction
|= inst
.operands
[2].reg
;
6502 inst
.instruction
|= inst
.operands
[0].reg
;
6503 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6504 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6510 inst
.instruction
|= inst
.operands
[0].imm
;
6516 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6517 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6520 /* ARM instructions, in alphabetical order by function name (except
6521 that wrapper functions appear immediately after the function they
6524 /* This is a pseudo-op of the form "adr rd, label" to be converted
6525 into a relative address of the form "add rd, pc, #label-.-8". */
6530 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6532 /* Frag hacking will turn this into a sub instruction if the offset turns
6533 out to be negative. */
6534 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6535 inst
.reloc
.pc_rel
= 1;
6536 inst
.reloc
.exp
.X_add_number
-= 8;
6539 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6540 into a relative address of the form:
6541 add rd, pc, #low(label-.-8)"
6542 add rd, rd, #high(label-.-8)" */
6547 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6549 /* Frag hacking will turn this into a sub instruction if the offset turns
6550 out to be negative. */
6551 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
6552 inst
.reloc
.pc_rel
= 1;
6553 inst
.size
= INSN_SIZE
* 2;
6554 inst
.reloc
.exp
.X_add_number
-= 8;
6560 if (!inst
.operands
[1].present
)
6561 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
6562 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6563 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6564 encode_arm_shifter_operand (2);
6570 if (inst
.operands
[0].present
)
6572 constraint ((inst
.instruction
& 0xf0) != 0x40
6573 && inst
.operands
[0].imm
!= 0xf,
6574 "bad barrier type");
6575 inst
.instruction
|= inst
.operands
[0].imm
;
6578 inst
.instruction
|= 0xf;
6584 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
6585 constraint (msb
> 32, _("bit-field extends past end of register"));
6586 /* The instruction encoding stores the LSB and MSB,
6587 not the LSB and width. */
6588 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6589 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
6590 inst
.instruction
|= (msb
- 1) << 16;
6598 /* #0 in second position is alternative syntax for bfc, which is
6599 the same instruction but with REG_PC in the Rm field. */
6600 if (!inst
.operands
[1].isreg
)
6601 inst
.operands
[1].reg
= REG_PC
;
6603 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
6604 constraint (msb
> 32, _("bit-field extends past end of register"));
6605 /* The instruction encoding stores the LSB and MSB,
6606 not the LSB and width. */
6607 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6608 inst
.instruction
|= inst
.operands
[1].reg
;
6609 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6610 inst
.instruction
|= (msb
- 1) << 16;
6616 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
6617 _("bit-field extends past end of register"));
6618 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6619 inst
.instruction
|= inst
.operands
[1].reg
;
6620 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6621 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
6624 /* ARM V5 breakpoint instruction (argument parse)
6625 BKPT <16 bit unsigned immediate>
6626 Instruction is not conditional.
6627 The bit pattern given in insns[] has the COND_ALWAYS condition,
6628 and it is an error if the caller tried to override that. */
6633 /* Top 12 of 16 bits to bits 19:8. */
6634 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
6636 /* Bottom 4 of 16 bits to bits 3:0. */
6637 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
6641 encode_branch (int default_reloc
)
6643 if (inst
.operands
[0].hasreloc
)
6645 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
6646 _("the only suffix valid here is '(plt)'"));
6647 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
6651 inst
.reloc
.type
= default_reloc
;
6653 inst
.reloc
.pc_rel
= 1;
6660 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6661 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6664 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6671 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6673 if (inst
.cond
== COND_ALWAYS
)
6674 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6676 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6680 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6683 /* ARM V5 branch-link-exchange instruction (argument parse)
6684 BLX <target_addr> ie BLX(1)
6685 BLX{<condition>} <Rm> ie BLX(2)
6686 Unfortunately, there are two different opcodes for this mnemonic.
6687 So, the insns[].value is not used, and the code here zaps values
6688 into inst.instruction.
6689 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
6694 if (inst
.operands
[0].isreg
)
6696 /* Arg is a register; the opcode provided by insns[] is correct.
6697 It is not illegal to do "blx pc", just useless. */
6698 if (inst
.operands
[0].reg
== REG_PC
)
6699 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
6701 inst
.instruction
|= inst
.operands
[0].reg
;
6705 /* Arg is an address; this instruction cannot be executed
6706 conditionally, and the opcode must be adjusted. */
6707 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
6708 inst
.instruction
= 0xfa000000;
6710 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6711 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6714 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
6721 if (inst
.operands
[0].reg
== REG_PC
)
6722 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
6724 inst
.instruction
|= inst
.operands
[0].reg
;
6728 /* ARM v5TEJ. Jump to Jazelle code. */
6733 if (inst
.operands
[0].reg
== REG_PC
)
6734 as_tsktsk (_("use of r15 in bxj is not really useful"));
6736 inst
.instruction
|= inst
.operands
[0].reg
;
6739 /* Co-processor data operation:
6740 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
6741 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
6745 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6746 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
6747 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6748 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6749 inst
.instruction
|= inst
.operands
[4].reg
;
6750 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6756 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6757 encode_arm_shifter_operand (1);
6760 /* Transfer between coprocessor and ARM registers.
6761 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
6766 No special properties. */
6771 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6772 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
6773 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6774 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6775 inst
.instruction
|= inst
.operands
[4].reg
;
6776 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6779 /* Transfer between coprocessor register and pair of ARM registers.
6780 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6785 Two XScale instructions are special cases of these:
6787 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
6788 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
6790 Result unpredicatable if Rd or Rn is R15. */
6795 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6796 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
6797 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6798 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6799 inst
.instruction
|= inst
.operands
[4].reg
;
6805 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
6806 inst
.instruction
|= inst
.operands
[1].imm
;
6812 inst
.instruction
|= inst
.operands
[0].imm
;
6818 /* There is no IT instruction in ARM mode. We
6819 process it but do not generate code for it. */
6826 int base_reg
= inst
.operands
[0].reg
;
6827 int range
= inst
.operands
[1].imm
;
6829 inst
.instruction
|= base_reg
<< 16;
6830 inst
.instruction
|= range
;
6832 if (inst
.operands
[1].writeback
)
6833 inst
.instruction
|= LDM_TYPE_2_OR_3
;
6835 if (inst
.operands
[0].writeback
)
6837 inst
.instruction
|= WRITE_BACK
;
6838 /* Check for unpredictable uses of writeback. */
6839 if (inst
.instruction
& LOAD_BIT
)
6841 /* Not allowed in LDM type 2. */
6842 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
6843 && ((range
& (1 << REG_PC
)) == 0))
6844 as_warn (_("writeback of base register is UNPREDICTABLE"));
6845 /* Only allowed if base reg not in list for other types. */
6846 else if (range
& (1 << base_reg
))
6847 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
6851 /* Not allowed for type 2. */
6852 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
6853 as_warn (_("writeback of base register is UNPREDICTABLE"));
6854 /* Only allowed if base reg not in list, or first in list. */
6855 else if ((range
& (1 << base_reg
))
6856 && (range
& ((1 << base_reg
) - 1)))
6857 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
6862 /* ARMv5TE load-consecutive (argument parse)
6871 constraint (inst
.operands
[0].reg
% 2 != 0,
6872 _("first destination register must be even"));
6873 constraint (inst
.operands
[1].present
6874 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
6875 _("can only load two consecutive registers"));
6876 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
6877 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
6879 if (!inst
.operands
[1].present
)
6880 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
6882 if (inst
.instruction
& LOAD_BIT
)
6884 /* encode_arm_addr_mode_3 will diagnose overlap between the base
6885 register and the first register written; we have to diagnose
6886 overlap between the base and the second register written here. */
6888 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
6889 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
6890 as_warn (_("base register written back, and overlaps "
6891 "second destination register"));
6893 /* For an index-register load, the index register must not overlap the
6894 destination (even if not write-back). */
6895 else if (inst
.operands
[2].immisreg
6896 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
6897 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
6898 as_warn (_("index register overlaps destination register"));
6901 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6902 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
6908 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
6909 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
6910 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
6911 || inst
.operands
[1].negative
6912 /* This can arise if the programmer has written
6914 or if they have mistakenly used a register name as the last
6917 It is very difficult to distinguish between these two cases
6918 because "rX" might actually be a label. ie the register
6919 name has been occluded by a symbol of the same name. So we
6920 just generate a general 'bad addressing mode' type error
6921 message and leave it up to the programmer to discover the
6922 true cause and fix their mistake. */
6923 || (inst
.operands
[1].reg
== REG_PC
),
6926 constraint (inst
.reloc
.exp
.X_op
!= O_constant
6927 || inst
.reloc
.exp
.X_add_number
!= 0,
6928 _("offset must be zero in ARM encoding"));
6930 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6931 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6932 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6938 constraint (inst
.operands
[0].reg
% 2 != 0,
6939 _("even register required"));
6940 constraint (inst
.operands
[1].present
6941 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
6942 _("can only load two consecutive registers"));
6943 /* If op 1 were present and equal to PC, this function wouldn't
6944 have been called in the first place. */
6945 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
6947 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6948 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6954 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6955 if (!inst
.operands
[1].isreg
)
6956 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
6958 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
6964 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
6966 if (inst
.operands
[1].preind
)
6968 constraint (inst
.reloc
.exp
.X_op
!= O_constant
||
6969 inst
.reloc
.exp
.X_add_number
!= 0,
6970 _("this instruction requires a post-indexed address"));
6972 inst
.operands
[1].preind
= 0;
6973 inst
.operands
[1].postind
= 1;
6974 inst
.operands
[1].writeback
= 1;
6976 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6977 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
6980 /* Halfword and signed-byte load/store operations. */
6985 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6986 if (!inst
.operands
[1].isreg
)
6987 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
6989 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
6995 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
6997 if (inst
.operands
[1].preind
)
6999 constraint (inst
.reloc
.exp
.X_op
!= O_constant
||
7000 inst
.reloc
.exp
.X_add_number
!= 0,
7001 _("this instruction requires a post-indexed address"));
7003 inst
.operands
[1].preind
= 0;
7004 inst
.operands
[1].postind
= 1;
7005 inst
.operands
[1].writeback
= 1;
7007 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7008 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7011 /* Co-processor register load/store.
7012 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7016 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7017 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7018 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7024 /* This restriction does not apply to mls (nor to mla in v6, but
7025 that's hard to detect at present). */
7026 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7027 && !(inst
.instruction
& 0x00400000))
7028 as_tsktsk (_("rd and rm should be different in mla"));
7030 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7031 inst
.instruction
|= inst
.operands
[1].reg
;
7032 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7033 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7040 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7041 encode_arm_shifter_operand (1);
7044 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7051 top
= (inst
.instruction
& 0x00400000) != 0;
7052 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7053 _(":lower16: not allowed this instruction"));
7054 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7055 _(":upper16: not allowed instruction"));
7056 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7057 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7059 imm
= inst
.reloc
.exp
.X_add_number
;
7060 /* The value is in two pieces: 0:11, 16:19. */
7061 inst
.instruction
|= (imm
& 0x00000fff);
7062 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7066 static void do_vfp_nsyn_opcode (const char *);
7069 do_vfp_nsyn_mrs (void)
7071 if (inst
.operands
[0].isvec
)
7073 if (inst
.operands
[1].reg
!= 1)
7074 first_error (_("operand 1 must be FPSCR"));
7075 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7076 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7077 do_vfp_nsyn_opcode ("fmstat");
7079 else if (inst
.operands
[1].isvec
)
7080 do_vfp_nsyn_opcode ("fmrx");
7088 do_vfp_nsyn_msr (void)
7090 if (inst
.operands
[0].isvec
)
7091 do_vfp_nsyn_opcode ("fmxr");
7101 if (do_vfp_nsyn_mrs () == SUCCESS
)
7104 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7105 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7107 _("'CPSR' or 'SPSR' expected"));
7108 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7109 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7112 /* Two possible forms:
7113 "{C|S}PSR_<field>, Rm",
7114 "{C|S}PSR_f, #expression". */
7119 if (do_vfp_nsyn_msr () == SUCCESS
)
7122 inst
.instruction
|= inst
.operands
[0].imm
;
7123 if (inst
.operands
[1].isreg
)
7124 inst
.instruction
|= inst
.operands
[1].reg
;
7127 inst
.instruction
|= INST_IMMEDIATE
;
7128 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7129 inst
.reloc
.pc_rel
= 0;
7136 if (!inst
.operands
[2].present
)
7137 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7138 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7139 inst
.instruction
|= inst
.operands
[1].reg
;
7140 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7142 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7143 as_tsktsk (_("rd and rm should be different in mul"));
7146 /* Long Multiply Parser
7147 UMULL RdLo, RdHi, Rm, Rs
7148 SMULL RdLo, RdHi, Rm, Rs
7149 UMLAL RdLo, RdHi, Rm, Rs
7150 SMLAL RdLo, RdHi, Rm, Rs. */
7155 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7156 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7157 inst
.instruction
|= inst
.operands
[2].reg
;
7158 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7160 /* rdhi, rdlo and rm must all be different. */
7161 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7162 || inst
.operands
[0].reg
== inst
.operands
[2].reg
7163 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7164 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7170 if (inst
.operands
[0].present
)
7172 /* Architectural NOP hints are CPSR sets with no bits selected. */
7173 inst
.instruction
&= 0xf0000000;
7174 inst
.instruction
|= 0x0320f000 + inst
.operands
[0].imm
;
7178 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7179 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7180 Condition defaults to COND_ALWAYS.
7181 Error if Rd, Rn or Rm are R15. */
7186 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7187 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7188 inst
.instruction
|= inst
.operands
[2].reg
;
7189 if (inst
.operands
[3].present
)
7190 encode_arm_shift (3);
7193 /* ARM V6 PKHTB (Argument Parse). */
7198 if (!inst
.operands
[3].present
)
7200 /* If the shift specifier is omitted, turn the instruction
7201 into pkhbt rd, rm, rn. */
7202 inst
.instruction
&= 0xfff00010;
7203 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7204 inst
.instruction
|= inst
.operands
[1].reg
;
7205 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7209 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7210 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7211 inst
.instruction
|= inst
.operands
[2].reg
;
7212 encode_arm_shift (3);
7216 /* ARMv5TE: Preload-Cache
7220 Syntactically, like LDR with B=1, W=0, L=1. */
7225 constraint (!inst
.operands
[0].isreg
,
7226 _("'[' expected after PLD mnemonic"));
7227 constraint (inst
.operands
[0].postind
,
7228 _("post-indexed expression used in preload instruction"));
7229 constraint (inst
.operands
[0].writeback
,
7230 _("writeback used in preload instruction"));
7231 constraint (!inst
.operands
[0].preind
,
7232 _("unindexed addressing used in preload instruction"));
7233 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7236 /* ARMv7: PLI <addr_mode> */
7240 constraint (!inst
.operands
[0].isreg
,
7241 _("'[' expected after PLI mnemonic"));
7242 constraint (inst
.operands
[0].postind
,
7243 _("post-indexed expression used in preload instruction"));
7244 constraint (inst
.operands
[0].writeback
,
7245 _("writeback used in preload instruction"));
7246 constraint (!inst
.operands
[0].preind
,
7247 _("unindexed addressing used in preload instruction"));
7248 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7249 inst
.instruction
&= ~PRE_INDEX
;
7255 inst
.operands
[1] = inst
.operands
[0];
7256 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7257 inst
.operands
[0].isreg
= 1;
7258 inst
.operands
[0].writeback
= 1;
7259 inst
.operands
[0].reg
= REG_SP
;
7263 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7264 word at the specified address and the following word
7266 Unconditionally executed.
7267 Error if Rn is R15. */
7272 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7273 if (inst
.operands
[0].writeback
)
7274 inst
.instruction
|= WRITE_BACK
;
7277 /* ARM V6 ssat (argument parse). */
7282 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7283 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7284 inst
.instruction
|= inst
.operands
[2].reg
;
7286 if (inst
.operands
[3].present
)
7287 encode_arm_shift (3);
7290 /* ARM V6 usat (argument parse). */
7295 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7296 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7297 inst
.instruction
|= inst
.operands
[2].reg
;
7299 if (inst
.operands
[3].present
)
7300 encode_arm_shift (3);
7303 /* ARM V6 ssat16 (argument parse). */
7308 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7309 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7310 inst
.instruction
|= inst
.operands
[2].reg
;
7316 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7317 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7318 inst
.instruction
|= inst
.operands
[2].reg
;
7321 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7322 preserving the other bits.
7324 setend <endian_specifier>, where <endian_specifier> is either
7330 if (inst
.operands
[0].imm
)
7331 inst
.instruction
|= 0x200;
7337 unsigned int Rm
= (inst
.operands
[1].present
7338 ? inst
.operands
[1].reg
7339 : inst
.operands
[0].reg
);
7341 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7342 inst
.instruction
|= Rm
;
7343 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7345 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7346 inst
.instruction
|= SHIFT_BY_REG
;
7349 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7355 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7356 inst
.reloc
.pc_rel
= 0;
7362 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7363 inst
.reloc
.pc_rel
= 0;
7366 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7367 SMLAxy{cond} Rd,Rm,Rs,Rn
7368 SMLAWy{cond} Rd,Rm,Rs,Rn
7369 Error if any register is R15. */
7374 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7375 inst
.instruction
|= inst
.operands
[1].reg
;
7376 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7377 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7380 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7381 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7382 Error if any register is R15.
7383 Warning if Rdlo == Rdhi. */
7388 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7389 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7390 inst
.instruction
|= inst
.operands
[2].reg
;
7391 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7393 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7394 as_tsktsk (_("rdhi and rdlo must be different"));
7397 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7398 SMULxy{cond} Rd,Rm,Rs
7399 Error if any register is R15. */
7404 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7405 inst
.instruction
|= inst
.operands
[1].reg
;
7406 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7409 /* ARM V6 srs (argument parse). */
7414 inst
.instruction
|= inst
.operands
[0].imm
;
7415 if (inst
.operands
[0].writeback
)
7416 inst
.instruction
|= WRITE_BACK
;
7419 /* ARM V6 strex (argument parse). */
7424 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7425 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7426 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7427 || inst
.operands
[2].negative
7428 /* See comment in do_ldrex(). */
7429 || (inst
.operands
[2].reg
== REG_PC
),
7432 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7433 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
7435 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7436 || inst
.reloc
.exp
.X_add_number
!= 0,
7437 _("offset must be zero in ARM encoding"));
7439 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7440 inst
.instruction
|= inst
.operands
[1].reg
;
7441 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7442 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7448 constraint (inst
.operands
[1].reg
% 2 != 0,
7449 _("even register required"));
7450 constraint (inst
.operands
[2].present
7451 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
7452 _("can only store two consecutive registers"));
7453 /* If op 2 were present and equal to PC, this function wouldn't
7454 have been called in the first place. */
7455 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
7457 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7458 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
7459 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
7462 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7463 inst
.instruction
|= inst
.operands
[1].reg
;
7464 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7467 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7468 extends it to 32-bits, and adds the result to a value in another
7469 register. You can specify a rotation by 0, 8, 16, or 24 bits
7470 before extracting the 16-bit value.
7471 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7472 Condition defaults to COND_ALWAYS.
7473 Error if any register uses R15. */
7478 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7479 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7480 inst
.instruction
|= inst
.operands
[2].reg
;
7481 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
7486 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
7487 Condition defaults to COND_ALWAYS.
7488 Error if any register uses R15. */
7493 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7494 inst
.instruction
|= inst
.operands
[1].reg
;
7495 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
7498 /* VFP instructions. In a logical order: SP variant first, monad
7499 before dyad, arithmetic then move then load/store. */
7502 do_vfp_sp_monadic (void)
7504 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7505 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7509 do_vfp_sp_dyadic (void)
7511 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7512 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7513 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7517 do_vfp_sp_compare_z (void)
7519 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7523 do_vfp_dp_sp_cvt (void)
7525 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7526 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7530 do_vfp_sp_dp_cvt (void)
7532 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7533 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7537 do_vfp_reg_from_sp (void)
7539 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7540 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7544 do_vfp_reg2_from_sp2 (void)
7546 constraint (inst
.operands
[2].imm
!= 2,
7547 _("only two consecutive VFP SP registers allowed here"));
7548 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7549 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7550 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7554 do_vfp_sp_from_reg (void)
7556 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
7557 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7561 do_vfp_sp2_from_reg2 (void)
7563 constraint (inst
.operands
[0].imm
!= 2,
7564 _("only two consecutive VFP SP registers allowed here"));
7565 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
7566 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7567 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7571 do_vfp_sp_ldst (void)
7573 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7574 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7578 do_vfp_dp_ldst (void)
7580 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7581 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7586 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
7588 if (inst
.operands
[0].writeback
)
7589 inst
.instruction
|= WRITE_BACK
;
7591 constraint (ldstm_type
!= VFP_LDSTMIA
,
7592 _("this addressing mode requires base-register writeback"));
7593 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7594 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
7595 inst
.instruction
|= inst
.operands
[1].imm
;
7599 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
7603 if (inst
.operands
[0].writeback
)
7604 inst
.instruction
|= WRITE_BACK
;
7606 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
7607 _("this addressing mode requires base-register writeback"));
7609 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7610 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7612 count
= inst
.operands
[1].imm
<< 1;
7613 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
7616 inst
.instruction
|= count
;
7620 do_vfp_sp_ldstmia (void)
7622 vfp_sp_ldstm (VFP_LDSTMIA
);
7626 do_vfp_sp_ldstmdb (void)
7628 vfp_sp_ldstm (VFP_LDSTMDB
);
7632 do_vfp_dp_ldstmia (void)
7634 vfp_dp_ldstm (VFP_LDSTMIA
);
7638 do_vfp_dp_ldstmdb (void)
7640 vfp_dp_ldstm (VFP_LDSTMDB
);
7644 do_vfp_xp_ldstmia (void)
7646 vfp_dp_ldstm (VFP_LDSTMIAX
);
7650 do_vfp_xp_ldstmdb (void)
7652 vfp_dp_ldstm (VFP_LDSTMDBX
);
7656 do_vfp_dp_rd_rm (void)
7658 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7659 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7663 do_vfp_dp_rn_rd (void)
7665 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
7666 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7670 do_vfp_dp_rd_rn (void)
7672 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7673 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7677 do_vfp_dp_rd_rn_rm (void)
7679 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7680 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7681 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
7687 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7691 do_vfp_dp_rm_rd_rn (void)
7693 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
7694 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7695 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
7698 /* VFPv3 instructions. */
7700 do_vfp_sp_const (void)
7702 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7703 inst
.instruction
|= (inst
.operands
[1].imm
& 15) << 16;
7704 inst
.instruction
|= (inst
.operands
[1].imm
>> 4);
7708 do_vfp_dp_const (void)
7710 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7711 inst
.instruction
|= (inst
.operands
[1].imm
& 15) << 16;
7712 inst
.instruction
|= (inst
.operands
[1].imm
>> 4);
7716 vfp_conv (int srcsize
)
7718 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
7719 inst
.instruction
|= (immbits
& 1) << 5;
7720 inst
.instruction
|= (immbits
>> 1);
7724 do_vfp_sp_conv_16 (void)
7726 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7731 do_vfp_dp_conv_16 (void)
7733 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7738 do_vfp_sp_conv_32 (void)
7740 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7745 do_vfp_dp_conv_32 (void)
7747 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7752 /* FPA instructions. Also in a logical order. */
7757 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7758 inst
.instruction
|= inst
.operands
[1].reg
;
7762 do_fpa_ldmstm (void)
7764 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7765 switch (inst
.operands
[1].imm
)
7767 case 1: inst
.instruction
|= CP_T_X
; break;
7768 case 2: inst
.instruction
|= CP_T_Y
; break;
7769 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
7774 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
7776 /* The instruction specified "ea" or "fd", so we can only accept
7777 [Rn]{!}. The instruction does not really support stacking or
7778 unstacking, so we have to emulate these by setting appropriate
7779 bits and offsets. */
7780 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7781 || inst
.reloc
.exp
.X_add_number
!= 0,
7782 _("this instruction does not support indexing"));
7784 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
7785 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
7787 if (!(inst
.instruction
& INDEX_UP
))
7788 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
7790 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
7792 inst
.operands
[2].preind
= 0;
7793 inst
.operands
[2].postind
= 1;
7797 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7801 /* iWMMXt instructions: strictly in alphabetical order. */
7804 do_iwmmxt_tandorc (void)
7806 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
7810 do_iwmmxt_textrc (void)
7812 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7813 inst
.instruction
|= inst
.operands
[1].imm
;
7817 do_iwmmxt_textrm (void)
7819 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7820 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7821 inst
.instruction
|= inst
.operands
[2].imm
;
7825 do_iwmmxt_tinsr (void)
7827 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7828 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7829 inst
.instruction
|= inst
.operands
[2].imm
;
7833 do_iwmmxt_tmia (void)
7835 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
7836 inst
.instruction
|= inst
.operands
[1].reg
;
7837 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7841 do_iwmmxt_waligni (void)
7843 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7844 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7845 inst
.instruction
|= inst
.operands
[2].reg
;
7846 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
7850 do_iwmmxt_wmerge (void)
7852 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7853 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7854 inst
.instruction
|= inst
.operands
[2].reg
;
7855 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
7859 do_iwmmxt_wmov (void)
7861 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
7862 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7863 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7864 inst
.instruction
|= inst
.operands
[1].reg
;
7868 do_iwmmxt_wldstbh (void)
7871 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7873 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
7875 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
7876 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
7880 do_iwmmxt_wldstw (void)
7882 /* RIWR_RIWC clears .isreg for a control register. */
7883 if (!inst
.operands
[0].isreg
)
7885 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7886 inst
.instruction
|= 0xf0000000;
7889 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7890 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7894 do_iwmmxt_wldstd (void)
7896 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7897 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
7898 && inst
.operands
[1].immisreg
)
7900 inst
.instruction
&= ~0x1a000ff;
7901 inst
.instruction
|= (0xf << 28);
7902 if (inst
.operands
[1].preind
)
7903 inst
.instruction
|= PRE_INDEX
;
7904 if (!inst
.operands
[1].negative
)
7905 inst
.instruction
|= INDEX_UP
;
7906 if (inst
.operands
[1].writeback
)
7907 inst
.instruction
|= WRITE_BACK
;
7908 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7909 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
7910 inst
.instruction
|= inst
.operands
[1].imm
;
7913 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
7917 do_iwmmxt_wshufh (void)
7919 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7920 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7921 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
7922 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
7926 do_iwmmxt_wzero (void)
7928 /* WZERO reg is an alias for WANDN reg, reg, reg. */
7929 inst
.instruction
|= inst
.operands
[0].reg
;
7930 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7931 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7935 do_iwmmxt_wrwrwr_or_imm5 (void)
7937 if (inst
.operands
[2].isreg
)
7940 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
7941 _("immediate operand requires iWMMXt2"));
7943 if (inst
.operands
[2].imm
== 0)
7945 switch ((inst
.instruction
>> 20) & 0xf)
7951 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
7952 inst
.operands
[2].imm
= 16;
7953 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
7959 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
7960 inst
.operands
[2].imm
= 32;
7961 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
7968 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
7970 wrn
= (inst
.instruction
>> 16) & 0xf;
7971 inst
.instruction
&= 0xff0fff0f;
7972 inst
.instruction
|= wrn
;
7973 /* Bail out here; the instruction is now assembled. */
7978 /* Map 32 -> 0, etc. */
7979 inst
.operands
[2].imm
&= 0x1f;
7980 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
7984 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
7985 operations first, then control, shift, and load/store. */
7987 /* Insns like "foo X,Y,Z". */
7990 do_mav_triple (void)
7992 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7993 inst
.instruction
|= inst
.operands
[1].reg
;
7994 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7997 /* Insns like "foo W,X,Y,Z".
7998 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8003 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8004 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8005 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8006 inst
.instruction
|= inst
.operands
[3].reg
;
8009 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8013 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8016 /* Maverick shift immediate instructions.
8017 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8018 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8023 int imm
= inst
.operands
[2].imm
;
8025 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8026 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8028 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8029 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8030 Bit 4 should be 0. */
8031 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8033 inst
.instruction
|= imm
;
8036 /* XScale instructions. Also sorted arithmetic before move. */
8038 /* Xscale multiply-accumulate (argument parse)
8041 MIAxycc acc0,Rm,Rs. */
8046 inst
.instruction
|= inst
.operands
[1].reg
;
8047 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8050 /* Xscale move-accumulator-register (argument parse)
8052 MARcc acc0,RdLo,RdHi. */
8057 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8058 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8061 /* Xscale move-register-accumulator (argument parse)
8063 MRAcc RdLo,RdHi,acc0. */
8068 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8069 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8070 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8073 /* Encoding functions relevant only to Thumb. */
8075 /* inst.operands[i] is a shifted-register operand; encode
8076 it into inst.instruction in the format used by Thumb32. */
8079 encode_thumb32_shifted_operand (int i
)
8081 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8082 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8084 constraint (inst
.operands
[i
].immisreg
,
8085 _("shift by register not allowed in thumb mode"));
8086 inst
.instruction
|= inst
.operands
[i
].reg
;
8087 if (shift
== SHIFT_RRX
)
8088 inst
.instruction
|= SHIFT_ROR
<< 4;
8091 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8092 _("expression too complex"));
8094 constraint (value
> 32
8095 || (value
== 32 && (shift
== SHIFT_LSL
8096 || shift
== SHIFT_ROR
)),
8097 _("shift expression is too large"));
8101 else if (value
== 32)
8104 inst
.instruction
|= shift
<< 4;
8105 inst
.instruction
|= (value
& 0x1c) << 10;
8106 inst
.instruction
|= (value
& 0x03) << 6;
8111 /* inst.operands[i] was set up by parse_address. Encode it into a
8112 Thumb32 format load or store instruction. Reject forms that cannot
8113 be used with such instructions. If is_t is true, reject forms that
8114 cannot be used with a T instruction; if is_d is true, reject forms
8115 that cannot be used with a D instruction. */
8118 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8120 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8122 constraint (!inst
.operands
[i
].isreg
,
8123 _("Instruction does not support =N addresses"));
8125 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8126 if (inst
.operands
[i
].immisreg
)
8128 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
8129 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8130 constraint (inst
.operands
[i
].negative
,
8131 _("Thumb does not support negative register indexing"));
8132 constraint (inst
.operands
[i
].postind
,
8133 _("Thumb does not support register post-indexing"));
8134 constraint (inst
.operands
[i
].writeback
,
8135 _("Thumb does not support register indexing with writeback"));
8136 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8137 _("Thumb supports only LSL in shifted register indexing"));
8139 inst
.instruction
|= inst
.operands
[i
].imm
;
8140 if (inst
.operands
[i
].shifted
)
8142 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8143 _("expression too complex"));
8144 constraint (inst
.reloc
.exp
.X_add_number
< 0
8145 || inst
.reloc
.exp
.X_add_number
> 3,
8146 _("shift out of range"));
8147 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8149 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8151 else if (inst
.operands
[i
].preind
)
8153 constraint (is_pc
&& inst
.operands
[i
].writeback
,
8154 _("cannot use writeback with PC-relative addressing"));
8155 constraint (is_t
&& inst
.operands
[i
].writeback
,
8156 _("cannot use writeback with this instruction"));
8160 inst
.instruction
|= 0x01000000;
8161 if (inst
.operands
[i
].writeback
)
8162 inst
.instruction
|= 0x00200000;
8166 inst
.instruction
|= 0x00000c00;
8167 if (inst
.operands
[i
].writeback
)
8168 inst
.instruction
|= 0x00000100;
8170 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8172 else if (inst
.operands
[i
].postind
)
8174 assert (inst
.operands
[i
].writeback
);
8175 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8176 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8179 inst
.instruction
|= 0x00200000;
8181 inst
.instruction
|= 0x00000900;
8182 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8184 else /* unindexed - only for coprocessor */
8185 inst
.error
= _("instruction does not accept unindexed addressing");
8188 /* Table of Thumb instructions which exist in both 16- and 32-bit
8189 encodings (the latter only in post-V6T2 cores). The index is the
8190 value used in the insns table below. When there is more than one
8191 possible 16-bit encoding for the instruction, this table always
8193 Also contains several pseudo-instructions used during relaxation. */
8194 #define T16_32_TAB \
8195 X(adc, 4140, eb400000), \
8196 X(adcs, 4140, eb500000), \
8197 X(add, 1c00, eb000000), \
8198 X(adds, 1c00, eb100000), \
8199 X(addi, 0000, f1000000), \
8200 X(addis, 0000, f1100000), \
8201 X(add_pc,000f, f20f0000), \
8202 X(add_sp,000d, f10d0000), \
8203 X(adr, 000f, f20f0000), \
8204 X(and, 4000, ea000000), \
8205 X(ands, 4000, ea100000), \
8206 X(asr, 1000, fa40f000), \
8207 X(asrs, 1000, fa50f000), \
8208 X(b, e000, f000b000), \
8209 X(bcond, d000, f0008000), \
8210 X(bic, 4380, ea200000), \
8211 X(bics, 4380, ea300000), \
8212 X(cmn, 42c0, eb100f00), \
8213 X(cmp, 2800, ebb00f00), \
8214 X(cpsie, b660, f3af8400), \
8215 X(cpsid, b670, f3af8600), \
8216 X(cpy, 4600, ea4f0000), \
8217 X(dec_sp,80dd, f1bd0d00), \
8218 X(eor, 4040, ea800000), \
8219 X(eors, 4040, ea900000), \
8220 X(inc_sp,00dd, f10d0d00), \
8221 X(ldmia, c800, e8900000), \
8222 X(ldr, 6800, f8500000), \
8223 X(ldrb, 7800, f8100000), \
8224 X(ldrh, 8800, f8300000), \
8225 X(ldrsb, 5600, f9100000), \
8226 X(ldrsh, 5e00, f9300000), \
8227 X(ldr_pc,4800, f85f0000), \
8228 X(ldr_pc2,4800, f85f0000), \
8229 X(ldr_sp,9800, f85d0000), \
8230 X(lsl, 0000, fa00f000), \
8231 X(lsls, 0000, fa10f000), \
8232 X(lsr, 0800, fa20f000), \
8233 X(lsrs, 0800, fa30f000), \
8234 X(mov, 2000, ea4f0000), \
8235 X(movs, 2000, ea5f0000), \
8236 X(mul, 4340, fb00f000), \
8237 X(muls, 4340, ffffffff), /* no 32b muls */ \
8238 X(mvn, 43c0, ea6f0000), \
8239 X(mvns, 43c0, ea7f0000), \
8240 X(neg, 4240, f1c00000), /* rsb #0 */ \
8241 X(negs, 4240, f1d00000), /* rsbs #0 */ \
8242 X(orr, 4300, ea400000), \
8243 X(orrs, 4300, ea500000), \
8244 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8245 X(push, b400, e92d0000), /* stmdb sp!,... */ \
8246 X(rev, ba00, fa90f080), \
8247 X(rev16, ba40, fa90f090), \
8248 X(revsh, bac0, fa90f0b0), \
8249 X(ror, 41c0, fa60f000), \
8250 X(rors, 41c0, fa70f000), \
8251 X(sbc, 4180, eb600000), \
8252 X(sbcs, 4180, eb700000), \
8253 X(stmia, c000, e8800000), \
8254 X(str, 6000, f8400000), \
8255 X(strb, 7000, f8000000), \
8256 X(strh, 8000, f8200000), \
8257 X(str_sp,9000, f84d0000), \
8258 X(sub, 1e00, eba00000), \
8259 X(subs, 1e00, ebb00000), \
8260 X(subi, 8000, f1a00000), \
8261 X(subis, 8000, f1b00000), \
8262 X(sxtb, b240, fa4ff080), \
8263 X(sxth, b200, fa0ff080), \
8264 X(tst, 4200, ea100f00), \
8265 X(uxtb, b2c0, fa5ff080), \
8266 X(uxth, b280, fa1ff080), \
8267 X(nop, bf00, f3af8000), \
8268 X(yield, bf10, f3af8001), \
8269 X(wfe, bf20, f3af8002), \
8270 X(wfi, bf30, f3af8003), \
8271 X(sev, bf40, f3af9004), /* typo, 8004? */
8273 /* To catch errors in encoding functions, the codes are all offset by
8274 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8275 as 16-bit instructions. */
8276 #define X(a,b,c) T_MNEM_##a
8277 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8280 #define X(a,b,c) 0x##b
8281 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8282 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8285 #define X(a,b,c) 0x##c
8286 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8287 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8288 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8292 /* Thumb instruction encoders, in alphabetical order. */
8296 do_t_add_sub_w (void)
8300 Rd
= inst
.operands
[0].reg
;
8301 Rn
= inst
.operands
[1].reg
;
8303 constraint (Rd
== 15, _("PC not allowed as destination"));
8304 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8305 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8308 /* Parse an add or subtract instruction. We get here with inst.instruction
8309 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8316 Rd
= inst
.operands
[0].reg
;
8317 Rs
= (inst
.operands
[1].present
8318 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8319 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8327 flags
= (inst
.instruction
== T_MNEM_adds
8328 || inst
.instruction
== T_MNEM_subs
);
8330 narrow
= (current_it_mask
== 0);
8332 narrow
= (current_it_mask
!= 0);
8333 if (!inst
.operands
[2].isreg
)
8337 add
= (inst
.instruction
== T_MNEM_add
8338 || inst
.instruction
== T_MNEM_adds
);
8340 if (inst
.size_req
!= 4)
8342 /* Attempt to use a narrow opcode, with relaxation if
8344 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8345 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8346 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8347 opcode
= T_MNEM_add_sp
;
8348 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8349 opcode
= T_MNEM_add_pc
;
8350 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8353 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8355 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8359 inst
.instruction
= THUMB_OP16(opcode
);
8360 inst
.instruction
|= (Rd
<< 4) | Rs
;
8361 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8362 if (inst
.size_req
!= 2)
8363 inst
.relax
= opcode
;
8366 constraint (inst
.size_req
== 2, BAD_HIREG
);
8368 if (inst
.size_req
== 4
8369 || (inst
.size_req
!= 2 && !opcode
))
8373 /* Always use addw/subw. */
8374 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
8375 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8379 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8380 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
8383 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8385 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
8387 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8388 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8393 Rn
= inst
.operands
[2].reg
;
8394 /* See if we can do this with a 16-bit instruction. */
8395 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
8397 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8402 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
8403 || inst
.instruction
== T_MNEM_add
)
8406 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8410 if (inst
.instruction
== T_MNEM_add
)
8414 inst
.instruction
= T_OPCODE_ADD_HI
;
8415 inst
.instruction
|= (Rd
& 8) << 4;
8416 inst
.instruction
|= (Rd
& 7);
8417 inst
.instruction
|= Rn
<< 3;
8420 /* ... because addition is commutative! */
8423 inst
.instruction
= T_OPCODE_ADD_HI
;
8424 inst
.instruction
|= (Rd
& 8) << 4;
8425 inst
.instruction
|= (Rd
& 7);
8426 inst
.instruction
|= Rs
<< 3;
8431 /* If we get here, it can't be done in 16 bits. */
8432 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
8433 _("shift must be constant"));
8434 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8435 inst
.instruction
|= Rd
<< 8;
8436 inst
.instruction
|= Rs
<< 16;
8437 encode_thumb32_shifted_operand (2);
8442 constraint (inst
.instruction
== T_MNEM_adds
8443 || inst
.instruction
== T_MNEM_subs
,
8446 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
8448 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
8449 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
8452 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8454 inst
.instruction
|= (Rd
<< 4) | Rs
;
8455 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8459 Rn
= inst
.operands
[2].reg
;
8460 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
8462 /* We now have Rd, Rs, and Rn set to registers. */
8463 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8465 /* Can't do this for SUB. */
8466 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
8467 inst
.instruction
= T_OPCODE_ADD_HI
;
8468 inst
.instruction
|= (Rd
& 8) << 4;
8469 inst
.instruction
|= (Rd
& 7);
8471 inst
.instruction
|= Rn
<< 3;
8473 inst
.instruction
|= Rs
<< 3;
8475 constraint (1, _("dest must overlap one source register"));
8479 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8480 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
8481 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8489 if (unified_syntax
&& inst
.size_req
== 0 && inst
.operands
[0].reg
<= 7)
8491 /* Defer to section relaxation. */
8492 inst
.relax
= inst
.instruction
;
8493 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8494 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8496 else if (unified_syntax
&& inst
.size_req
!= 2)
8498 /* Generate a 32-bit opcode. */
8499 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8500 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8501 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
8502 inst
.reloc
.pc_rel
= 1;
8506 /* Generate a 16-bit opcode. */
8507 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8508 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8509 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
8510 inst
.reloc
.pc_rel
= 1;
8512 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8516 /* Arithmetic instructions for which there is just one 16-bit
8517 instruction encoding, and it allows only two low registers.
8518 For maximal compatibility with ARM syntax, we allow three register
8519 operands even when Thumb-32 instructions are not available, as long
8520 as the first two are identical. For instance, both "sbc r0,r1" and
8521 "sbc r0,r0,r1" are allowed. */
8527 Rd
= inst
.operands
[0].reg
;
8528 Rs
= (inst
.operands
[1].present
8529 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8530 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8531 Rn
= inst
.operands
[2].reg
;
8535 if (!inst
.operands
[2].isreg
)
8537 /* For an immediate, we always generate a 32-bit opcode;
8538 section relaxation will shrink it later if possible. */
8539 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8540 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8541 inst
.instruction
|= Rd
<< 8;
8542 inst
.instruction
|= Rs
<< 16;
8543 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8549 /* See if we can do this with a 16-bit instruction. */
8550 if (THUMB_SETS_FLAGS (inst
.instruction
))
8551 narrow
= current_it_mask
== 0;
8553 narrow
= current_it_mask
!= 0;
8555 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8557 if (inst
.operands
[2].shifted
)
8559 if (inst
.size_req
== 4)
8565 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8566 inst
.instruction
|= Rd
;
8567 inst
.instruction
|= Rn
<< 3;
8571 /* If we get here, it can't be done in 16 bits. */
8572 constraint (inst
.operands
[2].shifted
8573 && inst
.operands
[2].immisreg
,
8574 _("shift must be constant"));
8575 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8576 inst
.instruction
|= Rd
<< 8;
8577 inst
.instruction
|= Rs
<< 16;
8578 encode_thumb32_shifted_operand (2);
8583 /* On its face this is a lie - the instruction does set the
8584 flags. However, the only supported mnemonic in this mode
8586 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8588 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8589 _("unshifted register required"));
8590 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8591 constraint (Rd
!= Rs
,
8592 _("dest and source1 must be the same register"));
8594 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8595 inst
.instruction
|= Rd
;
8596 inst
.instruction
|= Rn
<< 3;
8600 /* Similarly, but for instructions where the arithmetic operation is
8601 commutative, so we can allow either of them to be different from
8602 the destination operand in a 16-bit instruction. For instance, all
8603 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
8610 Rd
= inst
.operands
[0].reg
;
8611 Rs
= (inst
.operands
[1].present
8612 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8613 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8614 Rn
= inst
.operands
[2].reg
;
8618 if (!inst
.operands
[2].isreg
)
8620 /* For an immediate, we always generate a 32-bit opcode;
8621 section relaxation will shrink it later if possible. */
8622 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8623 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8624 inst
.instruction
|= Rd
<< 8;
8625 inst
.instruction
|= Rs
<< 16;
8626 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8632 /* See if we can do this with a 16-bit instruction. */
8633 if (THUMB_SETS_FLAGS (inst
.instruction
))
8634 narrow
= current_it_mask
== 0;
8636 narrow
= current_it_mask
!= 0;
8638 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8640 if (inst
.operands
[2].shifted
)
8642 if (inst
.size_req
== 4)
8649 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8650 inst
.instruction
|= Rd
;
8651 inst
.instruction
|= Rn
<< 3;
8656 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8657 inst
.instruction
|= Rd
;
8658 inst
.instruction
|= Rs
<< 3;
8663 /* If we get here, it can't be done in 16 bits. */
8664 constraint (inst
.operands
[2].shifted
8665 && inst
.operands
[2].immisreg
,
8666 _("shift must be constant"));
8667 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8668 inst
.instruction
|= Rd
<< 8;
8669 inst
.instruction
|= Rs
<< 16;
8670 encode_thumb32_shifted_operand (2);
8675 /* On its face this is a lie - the instruction does set the
8676 flags. However, the only supported mnemonic in this mode
8678 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8680 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8681 _("unshifted register required"));
8682 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8684 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8685 inst
.instruction
|= Rd
;
8688 inst
.instruction
|= Rn
<< 3;
8690 inst
.instruction
|= Rs
<< 3;
8692 constraint (1, _("dest must overlap one source register"));
8699 if (inst
.operands
[0].present
)
8701 constraint ((inst
.instruction
& 0xf0) != 0x40
8702 && inst
.operands
[0].imm
!= 0xf,
8703 "bad barrier type");
8704 inst
.instruction
|= inst
.operands
[0].imm
;
8707 inst
.instruction
|= 0xf;
8713 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8714 constraint (msb
> 32, _("bit-field extends past end of register"));
8715 /* The instruction encoding stores the LSB and MSB,
8716 not the LSB and width. */
8717 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8718 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
8719 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
8720 inst
.instruction
|= msb
- 1;
8728 /* #0 in second position is alternative syntax for bfc, which is
8729 the same instruction but with REG_PC in the Rm field. */
8730 if (!inst
.operands
[1].isreg
)
8731 inst
.operands
[1].reg
= REG_PC
;
8733 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8734 constraint (msb
> 32, _("bit-field extends past end of register"));
8735 /* The instruction encoding stores the LSB and MSB,
8736 not the LSB and width. */
8737 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8738 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8739 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8740 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8741 inst
.instruction
|= msb
- 1;
8747 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8748 _("bit-field extends past end of register"));
8749 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8750 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8751 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8752 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8753 inst
.instruction
|= inst
.operands
[3].imm
- 1;
8756 /* ARM V5 Thumb BLX (argument parse)
8757 BLX <target_addr> which is BLX(1)
8758 BLX <Rm> which is BLX(2)
8759 Unfortunately, there are two different opcodes for this mnemonic.
8760 So, the insns[].value is not used, and the code here zaps values
8761 into inst.instruction.
8763 ??? How to take advantage of the additional two bits of displacement
8764 available in Thumb32 mode? Need new relocation? */
8769 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8770 if (inst
.operands
[0].isreg
)
8771 /* We have a register, so this is BLX(2). */
8772 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8775 /* No register. This must be BLX(1). */
8776 inst
.instruction
= 0xf000e800;
8778 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8779 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8782 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
8783 inst
.reloc
.pc_rel
= 1;
8793 if (current_it_mask
)
8795 /* Conditional branches inside IT blocks are encoded as unconditional
8798 /* A branch must be the last instruction in an IT block. */
8799 constraint (current_it_mask
!= 0x10, BAD_BRANCH
);
8804 if (cond
!= COND_ALWAYS
)
8805 opcode
= T_MNEM_bcond
;
8807 opcode
= inst
.instruction
;
8809 if (unified_syntax
&& inst
.size_req
== 4)
8811 inst
.instruction
= THUMB_OP32(opcode
);
8812 if (cond
== COND_ALWAYS
)
8813 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
8816 assert (cond
!= 0xF);
8817 inst
.instruction
|= cond
<< 22;
8818 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
8823 inst
.instruction
= THUMB_OP16(opcode
);
8824 if (cond
== COND_ALWAYS
)
8825 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
8828 inst
.instruction
|= cond
<< 8;
8829 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
8831 /* Allow section relaxation. */
8832 if (unified_syntax
&& inst
.size_req
!= 2)
8833 inst
.relax
= opcode
;
8836 inst
.reloc
.pc_rel
= 1;
8842 constraint (inst
.cond
!= COND_ALWAYS
,
8843 _("instruction is always unconditional"));
8844 if (inst
.operands
[0].present
)
8846 constraint (inst
.operands
[0].imm
> 255,
8847 _("immediate value out of range"));
8848 inst
.instruction
|= inst
.operands
[0].imm
;
8853 do_t_branch23 (void)
8855 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8856 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8857 inst
.reloc
.pc_rel
= 1;
8859 /* If the destination of the branch is a defined symbol which does not have
8860 the THUMB_FUNC attribute, then we must be calling a function which has
8861 the (interfacearm) attribute. We look for the Thumb entry point to that
8862 function and change the branch to refer to that function instead. */
8863 if ( inst
.reloc
.exp
.X_op
== O_symbol
8864 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8865 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8866 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8867 inst
.reloc
.exp
.X_add_symbol
=
8868 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
8874 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8875 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8876 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
8877 should cause the alignment to be checked once it is known. This is
8878 because BX PC only works if the instruction is word aligned. */
8884 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8885 if (inst
.operands
[0].reg
== REG_PC
)
8886 as_tsktsk (_("use of r15 in bxj is not really useful"));
8888 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8894 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8895 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8896 inst
.instruction
|= inst
.operands
[1].reg
;
8902 constraint (current_it_mask
, BAD_NOT_IT
);
8903 inst
.instruction
|= inst
.operands
[0].imm
;
8909 constraint (current_it_mask
, BAD_NOT_IT
);
8911 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
8912 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
8914 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
8915 inst
.instruction
= 0xf3af8000;
8916 inst
.instruction
|= imod
<< 9;
8917 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
8918 if (inst
.operands
[1].present
)
8919 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
8923 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
8924 && (inst
.operands
[0].imm
& 4),
8925 _("selected processor does not support 'A' form "
8926 "of this instruction"));
8927 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
8928 _("Thumb does not support the 2-argument "
8929 "form of this instruction"));
8930 inst
.instruction
|= inst
.operands
[0].imm
;
8934 /* THUMB CPY instruction (argument parse). */
8939 if (inst
.size_req
== 4)
8941 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
8942 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8943 inst
.instruction
|= inst
.operands
[1].reg
;
8947 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
8948 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
8949 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
8956 constraint (current_it_mask
, BAD_NOT_IT
);
8957 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
8958 inst
.instruction
|= inst
.operands
[0].reg
;
8959 inst
.reloc
.pc_rel
= 1;
8960 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
8966 inst
.instruction
|= inst
.operands
[0].imm
;
8972 if (!inst
.operands
[1].present
)
8973 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8974 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8975 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8976 inst
.instruction
|= inst
.operands
[2].reg
;
8982 if (unified_syntax
&& inst
.size_req
== 4)
8983 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8985 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8991 unsigned int cond
= inst
.operands
[0].imm
;
8993 constraint (current_it_mask
, BAD_NOT_IT
);
8994 current_it_mask
= (inst
.instruction
& 0xf) | 0x10;
8997 /* If the condition is a negative condition, invert the mask. */
8998 if ((cond
& 0x1) == 0x0)
9000 unsigned int mask
= inst
.instruction
& 0x000f;
9002 if ((mask
& 0x7) == 0)
9003 /* no conversion needed */;
9004 else if ((mask
& 0x3) == 0)
9006 else if ((mask
& 0x1) == 0)
9011 inst
.instruction
&= 0xfff0;
9012 inst
.instruction
|= mask
;
9015 inst
.instruction
|= cond
<< 4;
9021 /* This really doesn't seem worth it. */
9022 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9023 _("expression too complex"));
9024 constraint (inst
.operands
[1].writeback
,
9025 _("Thumb load/store multiple does not support {reglist}^"));
9029 /* See if we can use a 16-bit instruction. */
9030 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9031 && inst
.size_req
!= 4
9032 && inst
.operands
[0].reg
<= 7
9033 && !(inst
.operands
[1].imm
& ~0xff)
9034 && (inst
.instruction
== T_MNEM_stmia
9035 ? inst
.operands
[0].writeback
9036 : (inst
.operands
[0].writeback
9037 == !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))))
9039 if (inst
.instruction
== T_MNEM_stmia
9040 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9041 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9042 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9043 inst
.operands
[0].reg
);
9045 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9046 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9047 inst
.instruction
|= inst
.operands
[1].imm
;
9051 if (inst
.operands
[1].imm
& (1 << 13))
9052 as_warn (_("SP should not be in register list"));
9053 if (inst
.instruction
== T_MNEM_stmia
)
9055 if (inst
.operands
[1].imm
& (1 << 15))
9056 as_warn (_("PC should not be in register list"));
9057 if (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9058 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9059 inst
.operands
[0].reg
);
9063 if (inst
.operands
[1].imm
& (1 << 14)
9064 && inst
.operands
[1].imm
& (1 << 15))
9065 as_warn (_("LR and PC should not both be in register list"));
9066 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9067 && inst
.operands
[0].writeback
)
9068 as_warn (_("base register should not be in register list "
9069 "when written back"));
9071 if (inst
.instruction
< 0xffff)
9072 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9073 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9074 inst
.instruction
|= inst
.operands
[1].imm
;
9075 if (inst
.operands
[0].writeback
)
9076 inst
.instruction
|= WRITE_BACK
;
9081 constraint (inst
.operands
[0].reg
> 7
9082 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9083 if (inst
.instruction
== T_MNEM_stmia
)
9085 if (!inst
.operands
[0].writeback
)
9086 as_warn (_("this instruction will write back the base register"));
9087 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9088 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9089 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9090 inst
.operands
[0].reg
);
9094 if (!inst
.operands
[0].writeback
9095 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9096 as_warn (_("this instruction will write back the base register"));
9097 else if (inst
.operands
[0].writeback
9098 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9099 as_warn (_("this instruction will not write back the base register"));
9102 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9103 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9104 inst
.instruction
|= inst
.operands
[1].imm
;
9111 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9112 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9113 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9114 || inst
.operands
[1].negative
,
9117 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9118 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9119 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9125 if (!inst
.operands
[1].present
)
9127 constraint (inst
.operands
[0].reg
== REG_LR
,
9128 _("r14 not allowed as first register "
9129 "when second register is omitted"));
9130 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9132 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9135 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9136 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9137 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9143 unsigned long opcode
;
9146 opcode
= inst
.instruction
;
9149 if (!inst
.operands
[1].isreg
)
9151 if (opcode
<= 0xffff)
9152 inst
.instruction
= THUMB_OP32 (opcode
);
9153 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9156 if (inst
.operands
[1].isreg
9157 && !inst
.operands
[1].writeback
9158 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9159 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9161 && inst
.size_req
!= 4)
9163 /* Insn may have a 16-bit form. */
9164 Rn
= inst
.operands
[1].reg
;
9165 if (inst
.operands
[1].immisreg
)
9167 inst
.instruction
= THUMB_OP16 (opcode
);
9169 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9172 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9173 && opcode
!= T_MNEM_ldrsb
)
9174 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9175 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9182 if (inst
.reloc
.pc_rel
)
9183 opcode
= T_MNEM_ldr_pc2
;
9185 opcode
= T_MNEM_ldr_pc
;
9189 if (opcode
== T_MNEM_ldr
)
9190 opcode
= T_MNEM_ldr_sp
;
9192 opcode
= T_MNEM_str_sp
;
9194 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9198 inst
.instruction
= inst
.operands
[0].reg
;
9199 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9201 inst
.instruction
|= THUMB_OP16 (opcode
);
9202 if (inst
.size_req
== 2)
9203 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9205 inst
.relax
= opcode
;
9209 /* Definitely a 32-bit variant. */
9210 inst
.instruction
= THUMB_OP32 (opcode
);
9211 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9212 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9216 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9218 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9220 /* Only [Rn,Rm] is acceptable. */
9221 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9222 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9223 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9224 || inst
.operands
[1].negative
,
9225 _("Thumb does not support this addressing mode"));
9226 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9230 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9231 if (!inst
.operands
[1].isreg
)
9232 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9235 constraint (!inst
.operands
[1].preind
9236 || inst
.operands
[1].shifted
9237 || inst
.operands
[1].writeback
,
9238 _("Thumb does not support this addressing mode"));
9239 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9241 constraint (inst
.instruction
& 0x0600,
9242 _("byte or halfword not valid for base register"));
9243 constraint (inst
.operands
[1].reg
== REG_PC
9244 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9245 _("r15 based store not allowed"));
9246 constraint (inst
.operands
[1].immisreg
,
9247 _("invalid base register for register offset"));
9249 if (inst
.operands
[1].reg
== REG_PC
)
9250 inst
.instruction
= T_OPCODE_LDR_PC
;
9251 else if (inst
.instruction
& THUMB_LOAD_BIT
)
9252 inst
.instruction
= T_OPCODE_LDR_SP
;
9254 inst
.instruction
= T_OPCODE_STR_SP
;
9256 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9257 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9261 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
9262 if (!inst
.operands
[1].immisreg
)
9264 /* Immediate offset. */
9265 inst
.instruction
|= inst
.operands
[0].reg
;
9266 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9267 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9271 /* Register offset. */
9272 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
9273 constraint (inst
.operands
[1].negative
,
9274 _("Thumb does not support this addressing mode"));
9277 switch (inst
.instruction
)
9279 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
9280 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
9281 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
9282 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
9283 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
9284 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
9285 case 0x5600 /* ldrsb */:
9286 case 0x5e00 /* ldrsh */: break;
9290 inst
.instruction
|= inst
.operands
[0].reg
;
9291 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9292 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
9298 if (!inst
.operands
[1].present
)
9300 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9301 constraint (inst
.operands
[0].reg
== REG_LR
,
9302 _("r14 not allowed here"));
9304 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9305 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9306 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
9313 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9314 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
9320 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9321 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9322 inst
.instruction
|= inst
.operands
[2].reg
;
9323 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9329 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9330 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9331 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9332 inst
.instruction
|= inst
.operands
[3].reg
;
9340 int r0off
= (inst
.instruction
== T_MNEM_mov
9341 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
9342 unsigned long opcode
;
9344 bfd_boolean low_regs
;
9346 low_regs
= (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7);
9347 opcode
= inst
.instruction
;
9348 if (current_it_mask
)
9349 narrow
= opcode
!= T_MNEM_movs
;
9351 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
9352 if (inst
.size_req
== 4
9353 || inst
.operands
[1].shifted
)
9356 if (!inst
.operands
[1].isreg
)
9358 /* Immediate operand. */
9359 if (current_it_mask
== 0 && opcode
== T_MNEM_mov
)
9361 if (low_regs
&& narrow
)
9363 inst
.instruction
= THUMB_OP16 (opcode
);
9364 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9365 if (inst
.size_req
== 2)
9366 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9368 inst
.relax
= opcode
;
9372 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9373 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9374 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9375 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9380 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9381 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9382 encode_thumb32_shifted_operand (1);
9385 switch (inst
.instruction
)
9388 inst
.instruction
= T_OPCODE_MOV_HR
;
9389 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9390 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9391 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9395 /* We know we have low registers at this point.
9396 Generate ADD Rd, Rs, #0. */
9397 inst
.instruction
= T_OPCODE_ADD_I3
;
9398 inst
.instruction
|= inst
.operands
[0].reg
;
9399 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9405 inst
.instruction
= T_OPCODE_CMP_LR
;
9406 inst
.instruction
|= inst
.operands
[0].reg
;
9407 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9411 inst
.instruction
= T_OPCODE_CMP_HR
;
9412 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9413 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9414 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9421 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9422 if (inst
.operands
[1].isreg
)
9424 if (inst
.operands
[0].reg
< 8 && inst
.operands
[1].reg
< 8)
9426 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
9427 since a MOV instruction produces unpredictable results. */
9428 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9429 inst
.instruction
= T_OPCODE_ADD_I3
;
9431 inst
.instruction
= T_OPCODE_CMP_LR
;
9433 inst
.instruction
|= inst
.operands
[0].reg
;
9434 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9438 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9439 inst
.instruction
= T_OPCODE_MOV_HR
;
9441 inst
.instruction
= T_OPCODE_CMP_HR
;
9447 constraint (inst
.operands
[0].reg
> 7,
9448 _("only lo regs allowed with immediate"));
9449 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9450 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9460 top
= (inst
.instruction
& 0x00800000) != 0;
9461 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
9463 constraint (top
, _(":lower16: not allowed this instruction"));
9464 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
9466 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
9468 constraint (!top
, _(":upper16: not allowed this instruction"));
9469 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
9472 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9473 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9475 imm
= inst
.reloc
.exp
.X_add_number
;
9476 inst
.instruction
|= (imm
& 0xf000) << 4;
9477 inst
.instruction
|= (imm
& 0x0800) << 15;
9478 inst
.instruction
|= (imm
& 0x0700) << 4;
9479 inst
.instruction
|= (imm
& 0x00ff);
9488 int r0off
= (inst
.instruction
== T_MNEM_mvn
9489 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
9492 if (inst
.size_req
== 4
9493 || inst
.instruction
> 0xffff
9494 || inst
.operands
[1].shifted
9495 || inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9497 else if (inst
.instruction
== T_MNEM_cmn
)
9499 else if (THUMB_SETS_FLAGS (inst
.instruction
))
9500 narrow
= (current_it_mask
== 0);
9502 narrow
= (current_it_mask
!= 0);
9504 if (!inst
.operands
[1].isreg
)
9506 /* For an immediate, we always generate a 32-bit opcode;
9507 section relaxation will shrink it later if possible. */
9508 if (inst
.instruction
< 0xffff)
9509 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9510 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9511 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9512 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9516 /* See if we can do this with a 16-bit instruction. */
9519 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9520 inst
.instruction
|= inst
.operands
[0].reg
;
9521 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9525 constraint (inst
.operands
[1].shifted
9526 && inst
.operands
[1].immisreg
,
9527 _("shift must be constant"));
9528 if (inst
.instruction
< 0xffff)
9529 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9530 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9531 encode_thumb32_shifted_operand (1);
9537 constraint (inst
.instruction
> 0xffff
9538 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
9539 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
9540 _("unshifted register required"));
9541 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9544 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9545 inst
.instruction
|= inst
.operands
[0].reg
;
9546 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9555 if (do_vfp_nsyn_mrs () == SUCCESS
)
9558 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
9561 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
9562 _("selected processor does not support "
9563 "requested special purpose register"));
9567 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9568 _("selected processor does not support "
9569 "requested special purpose register %x"));
9570 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9571 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
9572 _("'CPSR' or 'SPSR' expected"));
9575 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9576 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9577 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
9585 if (do_vfp_nsyn_msr () == SUCCESS
)
9588 constraint (!inst
.operands
[1].isreg
,
9589 _("Thumb encoding does not support an immediate here"));
9590 flags
= inst
.operands
[0].imm
;
9593 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9594 _("selected processor does not support "
9595 "requested special purpose register"));
9599 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
9600 _("selected processor does not support "
9601 "requested special purpose register"));
9604 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9605 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
9606 inst
.instruction
|= (flags
& 0xff);
9607 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9613 if (!inst
.operands
[2].present
)
9614 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9616 /* There is no 32-bit MULS and no 16-bit MUL. */
9617 if (unified_syntax
&& inst
.instruction
== T_MNEM_mul
)
9619 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9620 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9621 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9622 inst
.instruction
|= inst
.operands
[2].reg
<< 0;
9626 constraint (!unified_syntax
9627 && inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
9628 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9631 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9632 inst
.instruction
|= inst
.operands
[0].reg
;
9634 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9635 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9636 else if (inst
.operands
[0].reg
== inst
.operands
[2].reg
)
9637 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9639 constraint (1, _("dest must overlap one source register"));
9646 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9647 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9648 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9649 inst
.instruction
|= inst
.operands
[3].reg
;
9651 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9652 as_tsktsk (_("rdhi and rdlo must be different"));
9660 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
9662 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9663 inst
.instruction
|= inst
.operands
[0].imm
;
9667 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9668 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
9673 constraint (inst
.operands
[0].present
,
9674 _("Thumb does not support NOP with hints"));
9675 inst
.instruction
= 0x46c0;
9686 if (THUMB_SETS_FLAGS (inst
.instruction
))
9687 narrow
= (current_it_mask
== 0);
9689 narrow
= (current_it_mask
!= 0);
9690 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9692 if (inst
.size_req
== 4)
9697 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9698 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9699 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9703 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9704 inst
.instruction
|= inst
.operands
[0].reg
;
9705 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9710 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9712 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9714 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9715 inst
.instruction
|= inst
.operands
[0].reg
;
9716 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9723 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9724 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9725 inst
.instruction
|= inst
.operands
[2].reg
;
9726 if (inst
.operands
[3].present
)
9728 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
9729 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9730 _("expression too complex"));
9731 inst
.instruction
|= (val
& 0x1c) << 10;
9732 inst
.instruction
|= (val
& 0x03) << 6;
9739 if (!inst
.operands
[3].present
)
9740 inst
.instruction
&= ~0x00000020;
9747 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9751 do_t_push_pop (void)
9755 constraint (inst
.operands
[0].writeback
,
9756 _("push/pop do not support {reglist}^"));
9757 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9758 _("expression too complex"));
9760 mask
= inst
.operands
[0].imm
;
9761 if ((mask
& ~0xff) == 0)
9762 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9763 else if ((inst
.instruction
== T_MNEM_push
9764 && (mask
& ~0xff) == 1 << REG_LR
)
9765 || (inst
.instruction
== T_MNEM_pop
9766 && (mask
& ~0xff) == 1 << REG_PC
))
9768 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9769 inst
.instruction
|= THUMB_PP_PC_LR
;
9772 else if (unified_syntax
)
9774 if (mask
& (1 << 13))
9775 inst
.error
= _("SP not allowed in register list");
9776 if (inst
.instruction
== T_MNEM_push
)
9778 if (mask
& (1 << 15))
9779 inst
.error
= _("PC not allowed in register list");
9783 if (mask
& (1 << 14)
9784 && mask
& (1 << 15))
9785 inst
.error
= _("LR and PC should not both be in register list");
9787 if ((mask
& (mask
- 1)) == 0)
9789 /* Single register push/pop implemented as str/ldr. */
9790 if (inst
.instruction
== T_MNEM_push
)
9791 inst
.instruction
= 0xf84d0d04; /* str reg, [sp, #-4]! */
9793 inst
.instruction
= 0xf85d0b04; /* ldr reg, [sp], #4 */
9794 mask
= ffs(mask
) - 1;
9798 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9802 inst
.error
= _("invalid register list to push/pop instruction");
9806 inst
.instruction
|= mask
;
9812 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9813 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9819 if (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
9820 && inst
.size_req
!= 4)
9822 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9823 inst
.instruction
|= inst
.operands
[0].reg
;
9824 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9826 else if (unified_syntax
)
9828 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9829 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9830 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9831 inst
.instruction
|= inst
.operands
[1].reg
;
9834 inst
.error
= BAD_HIREG
;
9842 Rd
= inst
.operands
[0].reg
;
9843 Rs
= (inst
.operands
[1].present
9844 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9845 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9847 inst
.instruction
|= Rd
<< 8;
9848 inst
.instruction
|= Rs
<< 16;
9849 if (!inst
.operands
[2].isreg
)
9851 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9852 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9855 encode_thumb32_shifted_operand (2);
9861 constraint (current_it_mask
, BAD_NOT_IT
);
9862 if (inst
.operands
[0].imm
)
9863 inst
.instruction
|= 0x8;
9869 if (!inst
.operands
[1].present
)
9870 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9877 switch (inst
.instruction
)
9880 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
9882 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
9884 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
9886 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
9890 if (THUMB_SETS_FLAGS (inst
.instruction
))
9891 narrow
= (current_it_mask
== 0);
9893 narrow
= (current_it_mask
!= 0);
9894 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9896 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
9898 if (inst
.operands
[2].isreg
9899 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
9900 || inst
.operands
[2].reg
> 7))
9902 if (inst
.size_req
== 4)
9907 if (inst
.operands
[2].isreg
)
9909 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9910 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9911 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9912 inst
.instruction
|= inst
.operands
[2].reg
;
9916 inst
.operands
[1].shifted
= 1;
9917 inst
.operands
[1].shift_kind
= shift_kind
;
9918 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
9919 ? T_MNEM_movs
: T_MNEM_mov
);
9920 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9921 encode_thumb32_shifted_operand (1);
9922 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
9923 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9928 if (inst
.operands
[2].isreg
)
9932 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
9933 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
9934 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
9935 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
9939 inst
.instruction
|= inst
.operands
[0].reg
;
9940 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9946 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
9947 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
9948 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
9951 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
9952 inst
.instruction
|= inst
.operands
[0].reg
;
9953 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9959 constraint (inst
.operands
[0].reg
> 7
9960 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
9961 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9963 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
9965 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
9966 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
9967 _("source1 and dest must be same register"));
9969 switch (inst
.instruction
)
9971 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
9972 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
9973 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
9974 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
9978 inst
.instruction
|= inst
.operands
[0].reg
;
9979 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9983 switch (inst
.instruction
)
9985 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
9986 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
9987 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
9988 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
9991 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
9992 inst
.instruction
|= inst
.operands
[0].reg
;
9993 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10001 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10002 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10003 inst
.instruction
|= inst
.operands
[2].reg
;
10009 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10010 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10011 _("expression too complex"));
10012 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10013 inst
.instruction
|= (value
& 0xf000) >> 12;
10014 inst
.instruction
|= (value
& 0x0ff0);
10015 inst
.instruction
|= (value
& 0x000f) << 16;
10021 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10022 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10023 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10025 if (inst
.operands
[3].present
)
10027 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10028 _("expression too complex"));
10030 if (inst
.reloc
.exp
.X_add_number
!= 0)
10032 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10033 inst
.instruction
|= 0x00200000; /* sh bit */
10034 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10035 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10037 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10044 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10045 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10046 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10052 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10053 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10054 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10055 || inst
.operands
[2].negative
,
10058 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10059 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10060 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10061 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10067 if (!inst
.operands
[2].present
)
10068 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
10070 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10071 || inst
.operands
[0].reg
== inst
.operands
[2].reg
10072 || inst
.operands
[0].reg
== inst
.operands
[3].reg
10073 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
10076 inst
.instruction
|= inst
.operands
[0].reg
;
10077 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10078 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10079 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10085 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10086 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10087 inst
.instruction
|= inst
.operands
[2].reg
;
10088 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
10094 if (inst
.instruction
<= 0xffff && inst
.size_req
!= 4
10095 && inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
10096 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
10098 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10099 inst
.instruction
|= inst
.operands
[0].reg
;
10100 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10102 else if (unified_syntax
)
10104 if (inst
.instruction
<= 0xffff)
10105 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10106 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10107 inst
.instruction
|= inst
.operands
[1].reg
;
10108 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
10112 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
10113 _("Thumb encoding does not support rotation"));
10114 constraint (1, BAD_HIREG
);
10121 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
10129 half
= (inst
.instruction
& 0x10) != 0;
10130 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
10131 constraint (inst
.operands
[0].immisreg
,
10132 _("instruction requires register index"));
10133 constraint (inst
.operands
[0].imm
== 15,
10134 _("PC is not a valid index register"));
10135 constraint (!half
&& inst
.operands
[0].shifted
,
10136 _("instruction does not allow shifted index"));
10137 inst
.instruction
|= (inst
.operands
[0].reg
<< 16) | inst
.operands
[0].imm
;
10143 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10144 inst
.instruction
|= inst
.operands
[1].imm
;
10145 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10147 if (inst
.operands
[3].present
)
10149 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10150 _("expression too complex"));
10151 if (inst
.reloc
.exp
.X_add_number
!= 0)
10153 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10154 inst
.instruction
|= 0x00200000; /* sh bit */
10156 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10157 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10159 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10166 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10167 inst
.instruction
|= inst
.operands
[1].imm
;
10168 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10171 /* Neon instruction encoder helpers. */
10173 /* Encodings for the different types for various Neon opcodes. */
10175 /* An "invalid" code for the following tables. */
10178 struct neon_tab_entry
10181 unsigned float_or_poly
;
10182 unsigned scalar_or_imm
;
10185 /* Map overloaded Neon opcodes to their respective encodings. */
10186 #define NEON_ENC_TAB \
10187 X(vabd, 0x0000700, 0x1200d00, N_INV), \
10188 X(vmax, 0x0000600, 0x0000f00, N_INV), \
10189 X(vmin, 0x0000610, 0x0200f00, N_INV), \
10190 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
10191 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
10192 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
10193 X(vadd, 0x0000800, 0x0000d00, N_INV), \
10194 X(vsub, 0x1000800, 0x0200d00, N_INV), \
10195 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
10196 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
10197 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
10198 /* Register variants of the following two instructions are encoded as
10199 vcge / vcgt with the operands reversed. */ \
10200 X(vclt, 0x0000310, 0x1000e00, 0x1b10200), \
10201 X(vcle, 0x0000300, 0x1200e00, 0x1b10180), \
10202 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
10203 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
10204 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
10205 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
10206 X(vmlal, 0x0800800, N_INV, 0x0800240), \
10207 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
10208 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
10209 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
10210 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
10211 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
10212 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
10213 X(vshl, 0x0000400, N_INV, 0x0800510), \
10214 X(vqshl, 0x0000410, N_INV, 0x0800710), \
10215 X(vand, 0x0000110, N_INV, 0x0800030), \
10216 X(vbic, 0x0100110, N_INV, 0x0800030), \
10217 X(veor, 0x1000110, N_INV, N_INV), \
10218 X(vorn, 0x0300110, N_INV, 0x0800010), \
10219 X(vorr, 0x0200110, N_INV, 0x0800010), \
10220 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
10221 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
10222 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
10223 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
10224 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
10225 X(vst1, 0x0000000, 0x0800000, N_INV), \
10226 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
10227 X(vst2, 0x0000100, 0x0800100, N_INV), \
10228 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
10229 X(vst3, 0x0000200, 0x0800200, N_INV), \
10230 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
10231 X(vst4, 0x0000300, 0x0800300, N_INV), \
10232 X(vmovn, 0x1b20200, N_INV, N_INV), \
10233 X(vtrn, 0x1b20080, N_INV, N_INV), \
10234 X(vqmovn, 0x1b20200, N_INV, N_INV), \
10235 X(vqmovun, 0x1b20240, N_INV, N_INV), \
10236 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
10237 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \
10238 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \
10239 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
10240 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
10241 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
10242 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
10246 #define X(OPC,I,F,S) N_MNEM_##OPC
10251 static const struct neon_tab_entry neon_enc_tab
[] =
10253 #define X(OPC,I,F,S) { (I), (F), (S) }
10258 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10259 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10260 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10261 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10262 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10263 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10264 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10265 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10266 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10267 #define NEON_ENC_SINGLE(X) \
10268 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
10269 #define NEON_ENC_DOUBLE(X) \
10270 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
10272 /* Define shapes for instruction operands. The following mnemonic characters
10273 are used in this table:
10275 F - VFP S<n> register
10276 D - Neon D<n> register
10277 Q - Neon Q<n> register
10281 L - D<n> register list
10283 This table is used to generate various data:
10284 - enumerations of the form NS_DDR to be used as arguments to
10286 - a table classifying shapes into single, double, quad, mixed.
10287 - a table used to drive neon_select_shape.
10290 #define NEON_SHAPE_DEF \
10291 X(3, (D, D, D), DOUBLE), \
10292 X(3, (Q, Q, Q), QUAD), \
10293 X(3, (D, D, I), DOUBLE), \
10294 X(3, (Q, Q, I), QUAD), \
10295 X(3, (D, D, S), DOUBLE), \
10296 X(3, (Q, Q, S), QUAD), \
10297 X(2, (D, D), DOUBLE), \
10298 X(2, (Q, Q), QUAD), \
10299 X(2, (D, S), DOUBLE), \
10300 X(2, (Q, S), QUAD), \
10301 X(2, (D, R), DOUBLE), \
10302 X(2, (Q, R), QUAD), \
10303 X(2, (D, I), DOUBLE), \
10304 X(2, (Q, I), QUAD), \
10305 X(3, (D, L, D), DOUBLE), \
10306 X(2, (D, Q), MIXED), \
10307 X(2, (Q, D), MIXED), \
10308 X(3, (D, Q, I), MIXED), \
10309 X(3, (Q, D, I), MIXED), \
10310 X(3, (Q, D, D), MIXED), \
10311 X(3, (D, Q, Q), MIXED), \
10312 X(3, (Q, Q, D), MIXED), \
10313 X(3, (Q, D, S), MIXED), \
10314 X(3, (D, Q, S), MIXED), \
10315 X(4, (D, D, D, I), DOUBLE), \
10316 X(4, (Q, Q, Q, I), QUAD), \
10317 X(2, (F, F), SINGLE), \
10318 X(3, (F, F, F), SINGLE), \
10319 X(2, (F, I), SINGLE), \
10320 X(2, (F, D), MIXED), \
10321 X(2, (D, F), MIXED), \
10322 X(3, (F, F, I), MIXED), \
10323 X(4, (R, R, F, F), SINGLE), \
10324 X(4, (F, F, R, R), SINGLE), \
10325 X(3, (D, R, R), DOUBLE), \
10326 X(3, (R, R, D), DOUBLE), \
10327 X(2, (S, R), SINGLE), \
10328 X(2, (R, S), SINGLE), \
10329 X(2, (F, R), SINGLE), \
10330 X(2, (R, F), SINGLE)
10332 #define S2(A,B) NS_##A##B
10333 #define S3(A,B,C) NS_##A##B##C
10334 #define S4(A,B,C,D) NS_##A##B##C##D
10336 #define X(N, L, C) S##N L
10349 enum neon_shape_class
10357 #define X(N, L, C) SC_##C
10359 static enum neon_shape_class neon_shape_class
[] =
10377 /* Register widths of above. */
10378 static unsigned neon_shape_el_size
[] =
10389 struct neon_shape_info
10392 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
10395 #define S2(A,B) { SE_##A, SE_##B }
10396 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
10397 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
10399 #define X(N, L, C) { N, S##N L }
10401 static struct neon_shape_info neon_shape_tab
[] =
10411 /* Bit masks used in type checking given instructions.
10412 'N_EQK' means the type must be the same as (or based on in some way) the key
10413 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
10414 set, various other bits can be set as well in order to modify the meaning of
10415 the type constraint. */
10417 enum neon_type_mask
10439 N_KEY
= 0x100000, /* key element (main type specifier). */
10440 N_EQK
= 0x200000, /* given operand has the same type & size as the key. */
10441 N_VFP
= 0x400000, /* VFP mode: operand size must match register width. */
10442 N_DBL
= 0x000001, /* if N_EQK, this operand is twice the size. */
10443 N_HLF
= 0x000002, /* if N_EQK, this operand is half the size. */
10444 N_SGN
= 0x000004, /* if N_EQK, this operand is forced to be signed. */
10445 N_UNS
= 0x000008, /* if N_EQK, this operand is forced to be unsigned. */
10446 N_INT
= 0x000010, /* if N_EQK, this operand is forced to be integer. */
10447 N_FLT
= 0x000020, /* if N_EQK, this operand is forced to be float. */
10448 N_SIZ
= 0x000040, /* if N_EQK, this operand is forced to be size-only. */
10450 N_MAX_NONSPECIAL
= N_F64
10453 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
10455 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
10456 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
10457 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
10458 #define N_SUF_32 (N_SU_32 | N_F32)
10459 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
10460 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
10462 /* Pass this as the first type argument to neon_check_type to ignore types
10464 #define N_IGNORE_TYPE (N_KEY | N_EQK)
10466 /* Select a "shape" for the current instruction (describing register types or
10467 sizes) from a list of alternatives. Return NS_NULL if the current instruction
10468 doesn't fit. For non-polymorphic shapes, checking is usually done as a
10469 function of operand parsing, so this function doesn't need to be called.
10470 Shapes should be listed in order of decreasing length. */
10472 static enum neon_shape
10473 neon_select_shape (enum neon_shape shape
, ...)
10476 enum neon_shape first_shape
= shape
;
10478 /* Fix missing optional operands. FIXME: we don't know at this point how
10479 many arguments we should have, so this makes the assumption that we have
10480 > 1. This is true of all current Neon opcodes, I think, but may not be
10481 true in the future. */
10482 if (!inst
.operands
[1].present
)
10483 inst
.operands
[1] = inst
.operands
[0];
10485 va_start (ap
, shape
);
10487 for (; shape
!= NS_NULL
; shape
= va_arg (ap
, int))
10492 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
10494 if (!inst
.operands
[j
].present
)
10500 switch (neon_shape_tab
[shape
].el
[j
])
10503 if (!(inst
.operands
[j
].isreg
10504 && inst
.operands
[j
].isvec
10505 && inst
.operands
[j
].issingle
10506 && !inst
.operands
[j
].isquad
))
10511 if (!(inst
.operands
[j
].isreg
10512 && inst
.operands
[j
].isvec
10513 && !inst
.operands
[j
].isquad
10514 && !inst
.operands
[j
].issingle
))
10519 if (!(inst
.operands
[j
].isreg
10520 && !inst
.operands
[j
].isvec
))
10525 if (!(inst
.operands
[j
].isreg
10526 && inst
.operands
[j
].isvec
10527 && inst
.operands
[j
].isquad
10528 && !inst
.operands
[j
].issingle
))
10533 if (!(!inst
.operands
[j
].isreg
10534 && !inst
.operands
[j
].isscalar
))
10539 if (!(!inst
.operands
[j
].isreg
10540 && inst
.operands
[j
].isscalar
))
10554 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
10555 first_error (_("invalid instruction shape"));
10560 /* True if SHAPE is predominantly a quadword operation (most of the time, this
10561 means the Q bit should be set). */
10564 neon_quad (enum neon_shape shape
)
10566 return neon_shape_class
[shape
] == SC_QUAD
;
10570 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
10573 /* Allow modification to be made to types which are constrained to be
10574 based on the key element, based on bits set alongside N_EQK. */
10575 if ((typebits
& N_EQK
) != 0)
10577 if ((typebits
& N_HLF
) != 0)
10579 else if ((typebits
& N_DBL
) != 0)
10581 if ((typebits
& N_SGN
) != 0)
10582 *g_type
= NT_signed
;
10583 else if ((typebits
& N_UNS
) != 0)
10584 *g_type
= NT_unsigned
;
10585 else if ((typebits
& N_INT
) != 0)
10586 *g_type
= NT_integer
;
10587 else if ((typebits
& N_FLT
) != 0)
10588 *g_type
= NT_float
;
10589 else if ((typebits
& N_SIZ
) != 0)
10590 *g_type
= NT_untyped
;
10594 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
10595 operand type, i.e. the single type specified in a Neon instruction when it
10596 is the only one given. */
10598 static struct neon_type_el
10599 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
10601 struct neon_type_el dest
= *key
;
10603 assert ((thisarg
& N_EQK
) != 0);
10605 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
10610 /* Convert Neon type and size into compact bitmask representation. */
10612 static enum neon_type_mask
10613 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
10620 case 8: return N_8
;
10621 case 16: return N_16
;
10622 case 32: return N_32
;
10623 case 64: return N_64
;
10631 case 8: return N_I8
;
10632 case 16: return N_I16
;
10633 case 32: return N_I32
;
10634 case 64: return N_I64
;
10642 case 32: return N_F32
;
10643 case 64: return N_F64
;
10651 case 8: return N_P8
;
10652 case 16: return N_P16
;
10660 case 8: return N_S8
;
10661 case 16: return N_S16
;
10662 case 32: return N_S32
;
10663 case 64: return N_S64
;
10671 case 8: return N_U8
;
10672 case 16: return N_U16
;
10673 case 32: return N_U32
;
10674 case 64: return N_U64
;
10685 /* Convert compact Neon bitmask type representation to a type and size. Only
10686 handles the case where a single bit is set in the mask. */
10689 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
10690 enum neon_type_mask mask
)
10692 if ((mask
& N_EQK
) != 0)
10695 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
10697 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
10699 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
10701 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
10706 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
10708 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
10709 *type
= NT_unsigned
;
10710 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
10711 *type
= NT_integer
;
10712 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
10713 *type
= NT_untyped
;
10714 else if ((mask
& (N_P8
| N_P16
)) != 0)
10716 else if ((mask
& (N_F32
| N_F64
)) != 0)
10724 /* Modify a bitmask of allowed types. This is only needed for type
10728 modify_types_allowed (unsigned allowed
, unsigned mods
)
10731 enum neon_el_type type
;
10737 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
10739 if (el_type_of_type_chk (&type
, &size
, allowed
& i
) == SUCCESS
)
10741 neon_modify_type_size (mods
, &type
, &size
);
10742 destmask
|= type_chk_of_el_type (type
, size
);
10749 /* Check type and return type classification.
10750 The manual states (paraphrase): If one datatype is given, it indicates the
10752 - the second operand, if there is one
10753 - the operand, if there is no second operand
10754 - the result, if there are no operands.
10755 This isn't quite good enough though, so we use a concept of a "key" datatype
10756 which is set on a per-instruction basis, which is the one which matters when
10757 only one data type is written.
10758 Note: this function has side-effects (e.g. filling in missing operands). All
10759 Neon instructions should call it before performing bit encoding. */
10761 static struct neon_type_el
10762 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
10765 unsigned i
, pass
, key_el
= 0;
10766 unsigned types
[NEON_MAX_TYPE_ELS
];
10767 enum neon_el_type k_type
= NT_invtype
;
10768 unsigned k_size
= -1u;
10769 struct neon_type_el badtype
= {NT_invtype
, -1};
10770 unsigned key_allowed
= 0;
10772 /* Optional registers in Neon instructions are always (not) in operand 1.
10773 Fill in the missing operand here, if it was omitted. */
10774 if (els
> 1 && !inst
.operands
[1].present
)
10775 inst
.operands
[1] = inst
.operands
[0];
10777 /* Suck up all the varargs. */
10779 for (i
= 0; i
< els
; i
++)
10781 unsigned thisarg
= va_arg (ap
, unsigned);
10782 if (thisarg
== N_IGNORE_TYPE
)
10787 types
[i
] = thisarg
;
10788 if ((thisarg
& N_KEY
) != 0)
10793 if (inst
.vectype
.elems
> 0)
10794 for (i
= 0; i
< els
; i
++)
10795 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
10797 first_error (_("types specified in both the mnemonic and operands"));
10801 /* Duplicate inst.vectype elements here as necessary.
10802 FIXME: No idea if this is exactly the same as the ARM assembler,
10803 particularly when an insn takes one register and one non-register
10805 if (inst
.vectype
.elems
== 1 && els
> 1)
10808 inst
.vectype
.elems
= els
;
10809 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
10810 for (j
= 0; j
< els
; j
++)
10812 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
10815 else if (inst
.vectype
.elems
== 0 && els
> 0)
10818 /* No types were given after the mnemonic, so look for types specified
10819 after each operand. We allow some flexibility here; as long as the
10820 "key" operand has a type, we can infer the others. */
10821 for (j
= 0; j
< els
; j
++)
10822 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
10823 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
10825 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
10827 for (j
= 0; j
< els
; j
++)
10828 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
10829 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
10834 first_error (_("operand types can't be inferred"));
10838 else if (inst
.vectype
.elems
!= els
)
10840 first_error (_("type specifier has the wrong number of parts"));
10844 for (pass
= 0; pass
< 2; pass
++)
10846 for (i
= 0; i
< els
; i
++)
10848 unsigned thisarg
= types
[i
];
10849 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
10850 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
10851 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
10852 unsigned g_size
= inst
.vectype
.el
[i
].size
;
10854 /* Decay more-specific signed & unsigned types to sign-insensitive
10855 integer types if sign-specific variants are unavailable. */
10856 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
10857 && (types_allowed
& N_SU_ALL
) == 0)
10858 g_type
= NT_integer
;
10860 /* If only untyped args are allowed, decay any more specific types to
10861 them. Some instructions only care about signs for some element
10862 sizes, so handle that properly. */
10863 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
10864 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
10865 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
10866 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
10867 g_type
= NT_untyped
;
10871 if ((thisarg
& N_KEY
) != 0)
10875 key_allowed
= thisarg
& ~N_KEY
;
10880 if ((thisarg
& N_VFP
) != 0)
10882 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
10883 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
10885 /* In VFP mode, operands must match register widths. If we
10886 have a key operand, use its width, else use the width of
10887 the current operand. */
10893 if (regwidth
!= match
)
10895 first_error (_("operand size must match register width"));
10900 if ((thisarg
& N_EQK
) == 0)
10902 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
10904 if ((given_type
& types_allowed
) == 0)
10906 first_error (_("bad type in Neon instruction"));
10912 enum neon_el_type mod_k_type
= k_type
;
10913 unsigned mod_k_size
= k_size
;
10914 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
10915 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
10917 first_error (_("inconsistent types in Neon instruction"));
10925 return inst
.vectype
.el
[key_el
];
10928 /* Neon-style VFP instruction forwarding. */
10930 /* Thumb VFP instructions have 0xE in the condition field. */
10933 do_vfp_cond_or_thumb (void)
10936 inst
.instruction
|= 0xe0000000;
10938 inst
.instruction
|= inst
.cond
<< 28;
10941 /* Look up and encode a simple mnemonic, for use as a helper function for the
10942 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
10943 etc. It is assumed that operand parsing has already been done, and that the
10944 operands are in the form expected by the given opcode (this isn't necessarily
10945 the same as the form in which they were parsed, hence some massaging must
10946 take place before this function is called).
10947 Checks current arch version against that in the looked-up opcode. */
10950 do_vfp_nsyn_opcode (const char *opname
)
10952 const struct asm_opcode
*opcode
;
10954 opcode
= hash_find (arm_ops_hsh
, opname
);
10959 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
10960 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
10965 inst
.instruction
= opcode
->tvalue
;
10966 opcode
->tencode ();
10970 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
10971 opcode
->aencode ();
10976 do_vfp_nsyn_add_sub (enum neon_shape rs
)
10978 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
10983 do_vfp_nsyn_opcode ("fadds");
10985 do_vfp_nsyn_opcode ("fsubs");
10990 do_vfp_nsyn_opcode ("faddd");
10992 do_vfp_nsyn_opcode ("fsubd");
10996 /* Check operand types to see if this is a VFP instruction, and if so call
11000 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
11002 enum neon_shape rs
;
11003 struct neon_type_el et
;
11008 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11009 et
= neon_check_type (2, rs
,
11010 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11014 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11015 et
= neon_check_type (3, rs
,
11016 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11023 if (et
.type
!= NT_invtype
)
11035 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
11037 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
11042 do_vfp_nsyn_opcode ("fmacs");
11044 do_vfp_nsyn_opcode ("fmscs");
11049 do_vfp_nsyn_opcode ("fmacd");
11051 do_vfp_nsyn_opcode ("fmscd");
11056 do_vfp_nsyn_mul (enum neon_shape rs
)
11059 do_vfp_nsyn_opcode ("fmuls");
11061 do_vfp_nsyn_opcode ("fmuld");
11065 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
11067 int is_neg
= (inst
.instruction
& 0x80) != 0;
11068 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
11073 do_vfp_nsyn_opcode ("fnegs");
11075 do_vfp_nsyn_opcode ("fabss");
11080 do_vfp_nsyn_opcode ("fnegd");
11082 do_vfp_nsyn_opcode ("fabsd");
11086 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
11087 insns belong to Neon, and are handled elsewhere. */
11090 do_vfp_nsyn_ldm_stm (int is_dbmode
)
11092 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
11096 do_vfp_nsyn_opcode ("fldmdbs");
11098 do_vfp_nsyn_opcode ("fldmias");
11103 do_vfp_nsyn_opcode ("fstmdbs");
11105 do_vfp_nsyn_opcode ("fstmias");
11110 do_vfp_nsyn_sqrt (void)
11112 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11113 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11116 do_vfp_nsyn_opcode ("fsqrts");
11118 do_vfp_nsyn_opcode ("fsqrtd");
11122 do_vfp_nsyn_div (void)
11124 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11125 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11126 N_F32
| N_F64
| N_KEY
| N_VFP
);
11129 do_vfp_nsyn_opcode ("fdivs");
11131 do_vfp_nsyn_opcode ("fdivd");
11135 do_vfp_nsyn_nmul (void)
11137 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11138 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11139 N_F32
| N_F64
| N_KEY
| N_VFP
);
11143 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11144 do_vfp_sp_dyadic ();
11148 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11149 do_vfp_dp_rd_rn_rm ();
11151 do_vfp_cond_or_thumb ();
11155 do_vfp_nsyn_cmp (void)
11157 if (inst
.operands
[1].isreg
)
11159 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11160 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11164 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11165 do_vfp_sp_monadic ();
11169 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11170 do_vfp_dp_rd_rm ();
11175 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
11176 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
11178 switch (inst
.instruction
& 0x0fffffff)
11181 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
11184 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
11192 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11193 do_vfp_sp_compare_z ();
11197 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11201 do_vfp_cond_or_thumb ();
11205 nsyn_insert_sp (void)
11207 inst
.operands
[1] = inst
.operands
[0];
11208 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
11209 inst
.operands
[0].reg
= 13;
11210 inst
.operands
[0].isreg
= 1;
11211 inst
.operands
[0].writeback
= 1;
11212 inst
.operands
[0].present
= 1;
11216 do_vfp_nsyn_push (void)
11219 if (inst
.operands
[1].issingle
)
11220 do_vfp_nsyn_opcode ("fstmdbs");
11222 do_vfp_nsyn_opcode ("fstmdbd");
11226 do_vfp_nsyn_pop (void)
11229 if (inst
.operands
[1].issingle
)
11230 do_vfp_nsyn_opcode ("fldmdbs");
11232 do_vfp_nsyn_opcode ("fldmdbd");
11235 /* Fix up Neon data-processing instructions, ORing in the correct bits for
11236 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
11239 neon_dp_fixup (unsigned i
)
11243 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
11257 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
11261 neon_logbits (unsigned x
)
11263 return ffs (x
) - 4;
11266 #define LOW4(R) ((R) & 0xf)
11267 #define HI1(R) (((R) >> 4) & 1)
11269 /* Encode insns with bit pattern:
11271 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
11272 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
11274 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
11275 different meaning for some instruction. */
11278 neon_three_same (int isquad
, int ubit
, int size
)
11280 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11281 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11282 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
11283 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
11284 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
11285 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
11286 inst
.instruction
|= (isquad
!= 0) << 6;
11287 inst
.instruction
|= (ubit
!= 0) << 24;
11289 inst
.instruction
|= neon_logbits (size
) << 20;
11291 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11294 /* Encode instructions of the form:
11296 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
11297 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
11299 Don't write size if SIZE == -1. */
11302 neon_two_same (int qbit
, int ubit
, int size
)
11304 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11305 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11306 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11307 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11308 inst
.instruction
|= (qbit
!= 0) << 6;
11309 inst
.instruction
|= (ubit
!= 0) << 24;
11312 inst
.instruction
|= neon_logbits (size
) << 18;
11314 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11317 /* Neon instruction encoders, in approximate order of appearance. */
11320 do_neon_dyadic_i_su (void)
11322 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11323 struct neon_type_el et
= neon_check_type (3, rs
,
11324 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
11325 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11329 do_neon_dyadic_i64_su (void)
11331 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11332 struct neon_type_el et
= neon_check_type (3, rs
,
11333 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11334 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11338 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
11341 unsigned size
= et
.size
>> 3;
11342 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11343 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11344 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11345 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11346 inst
.instruction
|= (isquad
!= 0) << 6;
11347 inst
.instruction
|= immbits
<< 16;
11348 inst
.instruction
|= (size
>> 3) << 7;
11349 inst
.instruction
|= (size
& 0x7) << 19;
11351 inst
.instruction
|= (uval
!= 0) << 24;
11353 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11357 do_neon_shl_imm (void)
11359 if (!inst
.operands
[2].isreg
)
11361 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11362 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
11363 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11364 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
11368 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11369 struct neon_type_el et
= neon_check_type (3, rs
,
11370 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11371 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11372 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11377 do_neon_qshl_imm (void)
11379 if (!inst
.operands
[2].isreg
)
11381 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11382 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
11383 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11384 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
11385 inst
.operands
[2].imm
);
11389 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11390 struct neon_type_el et
= neon_check_type (3, rs
,
11391 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11392 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11393 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11398 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
11400 /* Handle .I8 and .I64 as pseudo-instructions. */
11404 /* Unfortunately, this will make everything apart from zero out-of-range.
11405 FIXME is this the intended semantics? There doesn't seem much point in
11406 accepting .I8 if so. */
11407 immediate
|= immediate
<< 8;
11411 /* Similarly, anything other than zero will be replicated in bits [63:32],
11412 which probably isn't want we want if we specified .I64. */
11413 if (immediate
!= 0)
11414 goto bad_immediate
;
11420 if (immediate
== (immediate
& 0x000000ff))
11422 *immbits
= immediate
;
11423 return (size
== 16) ? 0x9 : 0x1;
11425 else if (immediate
== (immediate
& 0x0000ff00))
11427 *immbits
= immediate
>> 8;
11428 return (size
== 16) ? 0xb : 0x3;
11430 else if (immediate
== (immediate
& 0x00ff0000))
11432 *immbits
= immediate
>> 16;
11435 else if (immediate
== (immediate
& 0xff000000))
11437 *immbits
= immediate
>> 24;
11442 first_error (_("immediate value out of range"));
11446 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
11450 neon_bits_same_in_bytes (unsigned imm
)
11452 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
11453 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
11454 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
11455 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
11458 /* For immediate of above form, return 0bABCD. */
11461 neon_squash_bits (unsigned imm
)
11463 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
11464 | ((imm
& 0x01000000) >> 21);
11467 /* Compress quarter-float representation to 0b...000 abcdefgh. */
11470 neon_qfloat_bits (unsigned imm
)
11472 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
11475 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
11476 the instruction. *OP is passed as the initial value of the op field, and
11477 may be set to a different value depending on the constant (i.e.
11478 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
11482 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, unsigned *immbits
,
11483 int *op
, int size
, enum neon_el_type type
)
11485 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
11487 if (size
!= 32 || *op
== 1)
11489 *immbits
= neon_qfloat_bits (immlo
);
11492 else if (size
== 64 && neon_bits_same_in_bytes (immhi
)
11493 && neon_bits_same_in_bytes (immlo
))
11495 /* Check this one first so we don't have to bother with immhi in later
11499 *immbits
= (neon_squash_bits (immhi
) << 4) | neon_squash_bits (immlo
);
11503 else if (immhi
!= 0)
11505 else if (immlo
== (immlo
& 0x000000ff))
11507 /* 64-bit case was already handled. Don't allow MVN with 8-bit
11509 if ((size
!= 8 && size
!= 16 && size
!= 32)
11510 || (size
== 8 && *op
== 1))
11513 return (size
== 8) ? 0xe : (size
== 16) ? 0x8 : 0x0;
11515 else if (immlo
== (immlo
& 0x0000ff00))
11517 if (size
!= 16 && size
!= 32)
11519 *immbits
= immlo
>> 8;
11520 return (size
== 16) ? 0xa : 0x2;
11522 else if (immlo
== (immlo
& 0x00ff0000))
11526 *immbits
= immlo
>> 16;
11529 else if (immlo
== (immlo
& 0xff000000))
11533 *immbits
= immlo
>> 24;
11536 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
11540 *immbits
= (immlo
>> 8) & 0xff;
11543 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
11547 *immbits
= (immlo
>> 16) & 0xff;
11554 /* Write immediate bits [7:0] to the following locations:
11556 |28/24|23 19|18 16|15 4|3 0|
11557 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
11559 This function is used by VMOV/VMVN/VORR/VBIC. */
11562 neon_write_immbits (unsigned immbits
)
11564 inst
.instruction
|= immbits
& 0xf;
11565 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
11566 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
11569 /* Invert low-order SIZE bits of XHI:XLO. */
11572 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
11574 unsigned immlo
= xlo
? *xlo
: 0;
11575 unsigned immhi
= xhi
? *xhi
: 0;
11580 immlo
= (~immlo
) & 0xff;
11584 immlo
= (~immlo
) & 0xffff;
11588 immhi
= (~immhi
) & 0xffffffff;
11589 /* fall through. */
11592 immlo
= (~immlo
) & 0xffffffff;
11607 do_neon_logic (void)
11609 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
11611 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11612 neon_check_type (3, rs
, N_IGNORE_TYPE
);
11613 /* U bit and size field were set as part of the bitmask. */
11614 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11615 neon_three_same (neon_quad (rs
), 0, -1);
11619 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
11620 struct neon_type_el et
= neon_check_type (2, rs
,
11621 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
11622 enum neon_opc opcode
= inst
.instruction
& 0x0fffffff;
11626 if (et
.type
== NT_invtype
)
11629 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11634 cmode
= neon_cmode_for_logic_imm (inst
.operands
[1].imm
, &immbits
,
11639 cmode
= neon_cmode_for_logic_imm (inst
.operands
[1].imm
, &immbits
,
11644 /* Pseudo-instruction for VBIC. */
11645 immbits
= inst
.operands
[1].imm
;
11646 neon_invert_size (&immbits
, 0, et
.size
);
11647 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11651 /* Pseudo-instruction for VORR. */
11652 immbits
= inst
.operands
[1].imm
;
11653 neon_invert_size (&immbits
, 0, et
.size
);
11654 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11664 inst
.instruction
|= neon_quad (rs
) << 6;
11665 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11666 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11667 inst
.instruction
|= cmode
<< 8;
11668 neon_write_immbits (immbits
);
11670 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11675 do_neon_bitfield (void)
11677 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11678 neon_check_type (3, rs
, N_IGNORE_TYPE
);
11679 neon_three_same (neon_quad (rs
), 0, -1);
11683 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
11686 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11687 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
11689 if (et
.type
== NT_float
)
11691 inst
.instruction
= NEON_ENC_FLOAT (inst
.instruction
);
11692 neon_three_same (neon_quad (rs
), 0, -1);
11696 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11697 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
11702 do_neon_dyadic_if_su (void)
11704 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
11708 do_neon_dyadic_if_su_d (void)
11710 /* This version only allow D registers, but that constraint is enforced during
11711 operand parsing so we don't need to do anything extra here. */
11712 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
11716 do_neon_dyadic_if_i_d (void)
11718 /* The "untyped" case can't happen. Do this to stop the "U" bit being
11719 affected if we specify unsigned args. */
11720 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
11723 enum vfp_or_neon_is_neon_bits
11726 NEON_CHECK_ARCH
= 2
11729 /* Call this function if an instruction which may have belonged to the VFP or
11730 Neon instruction sets, but turned out to be a Neon instruction (due to the
11731 operand types involved, etc.). We have to check and/or fix-up a couple of
11734 - Make sure the user hasn't attempted to make a Neon instruction
11736 - Alter the value in the condition code field if necessary.
11737 - Make sure that the arch supports Neon instructions.
11739 Which of these operations take place depends on bits from enum
11740 vfp_or_neon_is_neon_bits.
11742 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
11743 current instruction's condition is COND_ALWAYS, the condition field is
11744 changed to inst.uncond_value. This is necessary because instructions shared
11745 between VFP and Neon may be conditional for the VFP variants only, and the
11746 unconditional Neon version must have, e.g., 0xF in the condition field. */
11749 vfp_or_neon_is_neon (unsigned check
)
11751 /* Conditions are always legal in Thumb mode (IT blocks). */
11752 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
11754 if (inst
.cond
!= COND_ALWAYS
)
11756 first_error (_(BAD_COND
));
11759 if (inst
.uncond_value
!= -1)
11760 inst
.instruction
|= inst
.uncond_value
<< 28;
11763 if ((check
& NEON_CHECK_ARCH
)
11764 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
11766 first_error (_(BAD_FPU
));
11774 do_neon_addsub_if_i (void)
11776 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
11779 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11782 /* The "untyped" case can't happen. Do this to stop the "U" bit being
11783 affected if we specify unsigned args. */
11784 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
11787 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
11789 V<op> A,B (A is operand 0, B is operand 2)
11794 so handle that case specially. */
11797 neon_exchange_operands (void)
11799 void *scratch
= alloca (sizeof (inst
.operands
[0]));
11800 if (inst
.operands
[1].present
)
11802 /* Swap operands[1] and operands[2]. */
11803 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
11804 inst
.operands
[1] = inst
.operands
[2];
11805 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
11809 inst
.operands
[1] = inst
.operands
[2];
11810 inst
.operands
[2] = inst
.operands
[0];
11815 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
11817 if (inst
.operands
[2].isreg
)
11820 neon_exchange_operands ();
11821 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
11825 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11826 struct neon_type_el et
= neon_check_type (2, rs
,
11827 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
11829 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11830 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11831 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11832 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11833 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11834 inst
.instruction
|= neon_quad (rs
) << 6;
11835 inst
.instruction
|= (et
.type
== NT_float
) << 10;
11836 inst
.instruction
|= neon_logbits (et
.size
) << 18;
11838 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11845 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
11849 do_neon_cmp_inv (void)
11851 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
11857 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
11860 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
11861 scalars, which are encoded in 5 bits, M : Rm.
11862 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
11863 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
11867 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
11869 unsigned regno
= NEON_SCALAR_REG (scalar
);
11870 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
11875 if (regno
> 7 || elno
> 3)
11877 return regno
| (elno
<< 3);
11880 if (regno
> 15 || elno
> 1)
11882 return regno
| (elno
<< 4);
11886 first_error (_("scalar out of range for multiply instruction"));
11892 /* Encode multiply / multiply-accumulate scalar instructions. */
11895 neon_mul_mac (struct neon_type_el et
, int ubit
)
11899 /* Give a more helpful error message if we have an invalid type. */
11900 if (et
.type
== NT_invtype
)
11903 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
11904 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11905 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11906 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
11907 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
11908 inst
.instruction
|= LOW4 (scalar
);
11909 inst
.instruction
|= HI1 (scalar
) << 5;
11910 inst
.instruction
|= (et
.type
== NT_float
) << 8;
11911 inst
.instruction
|= neon_logbits (et
.size
) << 20;
11912 inst
.instruction
|= (ubit
!= 0) << 24;
11914 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11918 do_neon_mac_maybe_scalar (void)
11920 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
11923 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11926 if (inst
.operands
[2].isscalar
)
11928 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
11929 struct neon_type_el et
= neon_check_type (3, rs
,
11930 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
11931 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
11932 neon_mul_mac (et
, neon_quad (rs
));
11936 /* The "untyped" case can't happen. Do this to stop the "U" bit being
11937 affected if we specify unsigned args. */
11938 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
11945 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11946 struct neon_type_el et
= neon_check_type (3, rs
,
11947 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
11948 neon_three_same (neon_quad (rs
), 0, et
.size
);
11951 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
11952 same types as the MAC equivalents. The polynomial type for this instruction
11953 is encoded the same as the integer type. */
11958 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
11961 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11964 if (inst
.operands
[2].isscalar
)
11965 do_neon_mac_maybe_scalar ();
11967 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
11971 do_neon_qdmulh (void)
11973 if (inst
.operands
[2].isscalar
)
11975 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
11976 struct neon_type_el et
= neon_check_type (3, rs
,
11977 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
11978 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
11979 neon_mul_mac (et
, neon_quad (rs
));
11983 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11984 struct neon_type_el et
= neon_check_type (3, rs
,
11985 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
11986 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11987 /* The U bit (rounding) comes from bit mask. */
11988 neon_three_same (neon_quad (rs
), 0, et
.size
);
11993 do_neon_fcmp_absolute (void)
11995 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11996 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
11997 /* Size field comes from bit mask. */
11998 neon_three_same (neon_quad (rs
), 1, -1);
12002 do_neon_fcmp_absolute_inv (void)
12004 neon_exchange_operands ();
12005 do_neon_fcmp_absolute ();
12009 do_neon_step (void)
12011 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12012 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12013 neon_three_same (neon_quad (rs
), 0, -1);
12017 do_neon_abs_neg (void)
12019 enum neon_shape rs
;
12020 struct neon_type_el et
;
12022 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
12025 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12028 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12029 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
12031 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12032 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12033 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12034 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12035 inst
.instruction
|= neon_quad (rs
) << 6;
12036 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12037 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12039 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12045 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12046 struct neon_type_el et
= neon_check_type (2, rs
,
12047 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12048 int imm
= inst
.operands
[2].imm
;
12049 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12050 _("immediate out of range for insert"));
12051 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12057 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12058 struct neon_type_el et
= neon_check_type (2, rs
,
12059 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12060 int imm
= inst
.operands
[2].imm
;
12061 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12062 _("immediate out of range for insert"));
12063 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
12067 do_neon_qshlu_imm (void)
12069 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12070 struct neon_type_el et
= neon_check_type (2, rs
,
12071 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
12072 int imm
= inst
.operands
[2].imm
;
12073 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12074 _("immediate out of range for shift"));
12075 /* Only encodes the 'U present' variant of the instruction.
12076 In this case, signed types have OP (bit 8) set to 0.
12077 Unsigned types have OP set to 1. */
12078 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
12079 /* The rest of the bits are the same as other immediate shifts. */
12080 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12084 do_neon_qmovn (void)
12086 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12087 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12088 /* Saturating move where operands can be signed or unsigned, and the
12089 destination has the same signedness. */
12090 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12091 if (et
.type
== NT_unsigned
)
12092 inst
.instruction
|= 0xc0;
12094 inst
.instruction
|= 0x80;
12095 neon_two_same (0, 1, et
.size
/ 2);
12099 do_neon_qmovun (void)
12101 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12102 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12103 /* Saturating move with unsigned results. Operands must be signed. */
12104 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12105 neon_two_same (0, 1, et
.size
/ 2);
12109 do_neon_rshift_sat_narrow (void)
12111 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12112 or unsigned. If operands are unsigned, results must also be unsigned. */
12113 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12114 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12115 int imm
= inst
.operands
[2].imm
;
12116 /* This gets the bounds check, size encoding and immediate bits calculation
12120 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
12121 VQMOVN.I<size> <Dd>, <Qm>. */
12124 inst
.operands
[2].present
= 0;
12125 inst
.instruction
= N_MNEM_vqmovn
;
12130 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12131 _("immediate out of range"));
12132 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
12136 do_neon_rshift_sat_narrow_u (void)
12138 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12139 or unsigned. If operands are unsigned, results must also be unsigned. */
12140 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12141 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12142 int imm
= inst
.operands
[2].imm
;
12143 /* This gets the bounds check, size encoding and immediate bits calculation
12147 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
12148 VQMOVUN.I<size> <Dd>, <Qm>. */
12151 inst
.operands
[2].present
= 0;
12152 inst
.instruction
= N_MNEM_vqmovun
;
12157 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12158 _("immediate out of range"));
12159 /* FIXME: The manual is kind of unclear about what value U should have in
12160 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
12162 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
12166 do_neon_movn (void)
12168 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12169 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12170 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12171 neon_two_same (0, 1, et
.size
/ 2);
12175 do_neon_rshift_narrow (void)
12177 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12178 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12179 int imm
= inst
.operands
[2].imm
;
12180 /* This gets the bounds check, size encoding and immediate bits calculation
12184 /* If immediate is zero then we are a pseudo-instruction for
12185 VMOVN.I<size> <Dd>, <Qm> */
12188 inst
.operands
[2].present
= 0;
12189 inst
.instruction
= N_MNEM_vmovn
;
12194 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12195 _("immediate out of range for narrowing operation"));
12196 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
12200 do_neon_shll (void)
12202 /* FIXME: Type checking when lengthening. */
12203 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
12204 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
12205 unsigned imm
= inst
.operands
[2].imm
;
12207 if (imm
== et
.size
)
12209 /* Maximum shift variant. */
12210 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12211 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12212 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12213 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12214 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12215 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12217 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12221 /* A more-specific type check for non-max versions. */
12222 et
= neon_check_type (2, NS_QDI
,
12223 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12224 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12225 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
12229 /* Check the various types for the VCVT instruction, and return which version
12230 the current instruction is. */
12233 neon_cvt_flavour (enum neon_shape rs
)
12235 #define CVT_VAR(C,X,Y) \
12236 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
12237 if (et.type != NT_invtype) \
12239 inst.error = NULL; \
12242 struct neon_type_el et
;
12243 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
12244 || rs
== NS_FF
) ? N_VFP
: 0;
12245 /* The instruction versions which take an immediate take one register
12246 argument, which is extended to the width of the full register. Thus the
12247 "source" and "destination" registers must have the same width. Hack that
12248 here by making the size equal to the key (wider, in this case) operand. */
12249 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
12251 CVT_VAR (0, N_S32
, N_F32
);
12252 CVT_VAR (1, N_U32
, N_F32
);
12253 CVT_VAR (2, N_F32
, N_S32
);
12254 CVT_VAR (3, N_F32
, N_U32
);
12258 /* VFP instructions. */
12259 CVT_VAR (4, N_F32
, N_F64
);
12260 CVT_VAR (5, N_F64
, N_F32
);
12261 CVT_VAR (6, N_S32
, N_F64
| key
);
12262 CVT_VAR (7, N_U32
, N_F64
| key
);
12263 CVT_VAR (8, N_F64
| key
, N_S32
);
12264 CVT_VAR (9, N_F64
| key
, N_U32
);
12265 /* VFP instructions with bitshift. */
12266 CVT_VAR (10, N_F32
| key
, N_S16
);
12267 CVT_VAR (11, N_F32
| key
, N_U16
);
12268 CVT_VAR (12, N_F64
| key
, N_S16
);
12269 CVT_VAR (13, N_F64
| key
, N_U16
);
12270 CVT_VAR (14, N_S16
, N_F32
| key
);
12271 CVT_VAR (15, N_U16
, N_F32
| key
);
12272 CVT_VAR (16, N_S16
, N_F64
| key
);
12273 CVT_VAR (17, N_U16
, N_F64
| key
);
12279 /* Neon-syntax VFP conversions. */
12282 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
12284 const char *opname
= 0;
12286 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
12288 /* Conversions with immediate bitshift. */
12289 const char *enc
[] =
12311 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12313 opname
= enc
[flavour
];
12314 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12315 _("operands 0 and 1 must be the same register"));
12316 inst
.operands
[1] = inst
.operands
[2];
12317 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
12322 /* Conversions without bitshift. */
12323 const char *enc
[] =
12337 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12338 opname
= enc
[flavour
];
12342 do_vfp_nsyn_opcode (opname
);
12346 do_vfp_nsyn_cvtz (void)
12348 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
12349 int flavour
= neon_cvt_flavour (rs
);
12350 const char *enc
[] =
12362 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
12363 do_vfp_nsyn_opcode (enc
[flavour
]);
12369 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
12370 NS_FD
, NS_DF
, NS_FF
, NS_NULL
);
12371 int flavour
= neon_cvt_flavour (rs
);
12373 /* VFP rather than Neon conversions. */
12376 do_vfp_nsyn_cvt (rs
, flavour
);
12385 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12388 /* Fixed-point conversion with #0 immediate is encoded as an
12389 integer conversion. */
12390 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
12392 unsigned immbits
= 32 - inst
.operands
[2].imm
;
12393 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
12394 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12396 inst
.instruction
|= enctab
[flavour
];
12397 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12398 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12399 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12400 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12401 inst
.instruction
|= neon_quad (rs
) << 6;
12402 inst
.instruction
|= 1 << 21;
12403 inst
.instruction
|= immbits
<< 16;
12405 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12413 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
12415 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12417 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12421 inst
.instruction
|= enctab
[flavour
];
12423 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12424 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12425 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12426 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12427 inst
.instruction
|= neon_quad (rs
) << 6;
12428 inst
.instruction
|= 2 << 18;
12430 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12435 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
12436 do_vfp_nsyn_cvt (rs
, flavour
);
12441 neon_move_immediate (void)
12443 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12444 struct neon_type_el et
= neon_check_type (2, rs
,
12445 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12446 unsigned immlo
, immhi
= 0, immbits
;
12449 constraint (et
.type
== NT_invtype
,
12450 _("operand size must be specified for immediate VMOV"));
12452 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
12453 op
= (inst
.instruction
& (1 << 5)) != 0;
12455 immlo
= inst
.operands
[1].imm
;
12456 if (inst
.operands
[1].regisimm
)
12457 immhi
= inst
.operands
[1].reg
;
12459 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
12460 _("immediate has bits set outside the operand size"));
12462 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, &immbits
, &op
,
12463 et
.size
, et
.type
)) == FAIL
)
12465 /* Invert relevant bits only. */
12466 neon_invert_size (&immlo
, &immhi
, et
.size
);
12467 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
12468 with one or the other; those cases are caught by
12469 neon_cmode_for_move_imm. */
12471 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, &immbits
, &op
,
12472 et
.size
, et
.type
)) == FAIL
)
12474 first_error (_("immediate out of range"));
12479 inst
.instruction
&= ~(1 << 5);
12480 inst
.instruction
|= op
<< 5;
12482 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12483 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12484 inst
.instruction
|= neon_quad (rs
) << 6;
12485 inst
.instruction
|= cmode
<< 8;
12487 neon_write_immbits (immbits
);
12493 if (inst
.operands
[1].isreg
)
12495 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12497 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12498 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12499 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12500 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12501 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12502 inst
.instruction
|= neon_quad (rs
) << 6;
12506 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12507 neon_move_immediate ();
12510 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12513 /* Encode instructions of form:
12515 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12516 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm |
12521 neon_mixed_length (struct neon_type_el et
, unsigned size
)
12523 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12524 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12525 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12526 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12527 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12528 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12529 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
12530 inst
.instruction
|= neon_logbits (size
) << 20;
12532 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12536 do_neon_dyadic_long (void)
12538 /* FIXME: Type checking for lengthening op. */
12539 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12540 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12541 neon_mixed_length (et
, et
.size
);
12545 do_neon_abal (void)
12547 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12548 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12549 neon_mixed_length (et
, et
.size
);
12553 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
12555 if (inst
.operands
[2].isscalar
)
12557 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
12558 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
12559 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12560 neon_mul_mac (et
, et
.type
== NT_unsigned
);
12564 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12565 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
12566 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12567 neon_mixed_length (et
, et
.size
);
12572 do_neon_mac_maybe_scalar_long (void)
12574 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
12578 do_neon_dyadic_wide (void)
12580 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
12581 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12582 neon_mixed_length (et
, et
.size
);
12586 do_neon_dyadic_narrow (void)
12588 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12589 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
12590 /* Operand sign is unimportant, and the U bit is part of the opcode,
12591 so force the operand type to integer. */
12592 et
.type
= NT_integer
;
12593 neon_mixed_length (et
, et
.size
/ 2);
12597 do_neon_mul_sat_scalar_long (void)
12599 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
12603 do_neon_vmull (void)
12605 if (inst
.operands
[2].isscalar
)
12606 do_neon_mac_maybe_scalar_long ();
12609 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12610 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
12611 if (et
.type
== NT_poly
)
12612 inst
.instruction
= NEON_ENC_POLY (inst
.instruction
);
12614 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12615 /* For polynomial encoding, size field must be 0b00 and the U bit must be
12616 zero. Should be OK as-is. */
12617 neon_mixed_length (et
, et
.size
);
12624 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
12625 struct neon_type_el et
= neon_check_type (3, rs
,
12626 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12627 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
12628 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12629 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12630 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12631 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12632 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12633 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12634 inst
.instruction
|= neon_quad (rs
) << 6;
12635 inst
.instruction
|= imm
<< 8;
12637 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12643 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12644 struct neon_type_el et
= neon_check_type (2, rs
,
12645 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12646 unsigned op
= (inst
.instruction
>> 7) & 3;
12647 /* N (width of reversed regions) is encoded as part of the bitmask. We
12648 extract it here to check the elements to be reversed are smaller.
12649 Otherwise we'd get a reserved instruction. */
12650 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
12651 assert (elsize
!= 0);
12652 constraint (et
.size
>= elsize
,
12653 _("elements must be smaller than reversal region"));
12654 neon_two_same (neon_quad (rs
), 1, et
.size
);
12660 if (inst
.operands
[1].isscalar
)
12662 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
12663 struct neon_type_el et
= neon_check_type (2, rs
,
12664 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12665 unsigned sizebits
= et
.size
>> 3;
12666 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
12667 int logsize
= neon_logbits (et
.size
);
12668 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
12670 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
12673 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12674 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12675 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12676 inst
.instruction
|= LOW4 (dm
);
12677 inst
.instruction
|= HI1 (dm
) << 5;
12678 inst
.instruction
|= neon_quad (rs
) << 6;
12679 inst
.instruction
|= x
<< 17;
12680 inst
.instruction
|= sizebits
<< 16;
12682 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12686 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
12687 struct neon_type_el et
= neon_check_type (2, rs
,
12688 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
12689 /* Duplicate ARM register to lanes of vector. */
12690 inst
.instruction
= NEON_ENC_ARMREG (inst
.instruction
);
12693 case 8: inst
.instruction
|= 0x400000; break;
12694 case 16: inst
.instruction
|= 0x000020; break;
12695 case 32: inst
.instruction
|= 0x000000; break;
12698 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
12699 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
12700 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
12701 inst
.instruction
|= neon_quad (rs
) << 21;
12702 /* The encoding for this instruction is identical for the ARM and Thumb
12703 variants, except for the condition field. */
12704 do_vfp_cond_or_thumb ();
12708 /* VMOV has particularly many variations. It can be one of:
12709 0. VMOV<c><q> <Qd>, <Qm>
12710 1. VMOV<c><q> <Dd>, <Dm>
12711 (Register operations, which are VORR with Rm = Rn.)
12712 2. VMOV<c><q>.<dt> <Qd>, #<imm>
12713 3. VMOV<c><q>.<dt> <Dd>, #<imm>
12715 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
12716 (ARM register to scalar.)
12717 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
12718 (Two ARM registers to vector.)
12719 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
12720 (Scalar to ARM register.)
12721 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
12722 (Vector to two ARM registers.)
12723 8. VMOV.F32 <Sd>, <Sm>
12724 9. VMOV.F64 <Dd>, <Dm>
12725 (VFP register moves.)
12726 10. VMOV.F32 <Sd>, #imm
12727 11. VMOV.F64 <Dd>, #imm
12728 (VFP float immediate load.)
12729 12. VMOV <Rd>, <Sm>
12730 (VFP single to ARM reg.)
12731 13. VMOV <Sd>, <Rm>
12732 (ARM reg to VFP single.)
12733 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
12734 (Two ARM regs to two VFP singles.)
12735 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
12736 (Two VFP singles to two ARM regs.)
12738 These cases can be disambiguated using neon_select_shape, except cases 1/9
12739 and 3/11 which depend on the operand type too.
12741 All the encoded bits are hardcoded by this function.
12743 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
12744 Cases 5, 7 may be used with VFPv2 and above.
12746 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
12747 can specify a type where it doesn't make sense to, and is ignored).
12753 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
12754 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
12756 struct neon_type_el et
;
12757 const char *ldconst
= 0;
12761 case NS_DD
: /* case 1/9. */
12762 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
12763 /* It is not an error here if no type is given. */
12765 if (et
.type
== NT_float
&& et
.size
== 64)
12767 do_vfp_nsyn_opcode ("fcpyd");
12770 /* fall through. */
12772 case NS_QQ
: /* case 0/1. */
12774 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12776 /* The architecture manual I have doesn't explicitly state which
12777 value the U bit should have for register->register moves, but
12778 the equivalent VORR instruction has U = 0, so do that. */
12779 inst
.instruction
= 0x0200110;
12780 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12781 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12782 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12783 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12784 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12785 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12786 inst
.instruction
|= neon_quad (rs
) << 6;
12788 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12792 case NS_DI
: /* case 3/11. */
12793 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
12795 if (et
.type
== NT_float
&& et
.size
== 64)
12797 /* case 11 (fconstd). */
12798 ldconst
= "fconstd";
12799 goto encode_fconstd
;
12801 /* fall through. */
12803 case NS_QI
: /* case 2/3. */
12804 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12806 inst
.instruction
= 0x0800010;
12807 neon_move_immediate ();
12808 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12811 case NS_SR
: /* case 4. */
12813 unsigned bcdebits
= 0;
12814 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
12815 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
12816 int logsize
= neon_logbits (et
.size
);
12817 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
12818 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
12820 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
12822 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
12823 && et
.size
!= 32, _(BAD_FPU
));
12824 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
12825 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
12829 case 8: bcdebits
= 0x8; break;
12830 case 16: bcdebits
= 0x1; break;
12831 case 32: bcdebits
= 0x0; break;
12835 bcdebits
|= x
<< logsize
;
12837 inst
.instruction
= 0xe000b10;
12838 do_vfp_cond_or_thumb ();
12839 inst
.instruction
|= LOW4 (dn
) << 16;
12840 inst
.instruction
|= HI1 (dn
) << 7;
12841 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12842 inst
.instruction
|= (bcdebits
& 3) << 5;
12843 inst
.instruction
|= (bcdebits
>> 2) << 21;
12847 case NS_DRR
: /* case 5 (fmdrr). */
12848 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
12851 inst
.instruction
= 0xc400b10;
12852 do_vfp_cond_or_thumb ();
12853 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
12854 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
12855 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12856 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12859 case NS_RS
: /* case 6. */
12861 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
12862 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
12863 unsigned logsize
= neon_logbits (et
.size
);
12864 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
12865 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
12866 unsigned abcdebits
= 0;
12868 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
12870 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
12871 && et
.size
!= 32, _(BAD_FPU
));
12872 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
12873 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
12877 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
12878 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
12879 case 32: abcdebits
= 0x00; break;
12883 abcdebits
|= x
<< logsize
;
12884 inst
.instruction
= 0xe100b10;
12885 do_vfp_cond_or_thumb ();
12886 inst
.instruction
|= LOW4 (dn
) << 16;
12887 inst
.instruction
|= HI1 (dn
) << 7;
12888 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12889 inst
.instruction
|= (abcdebits
& 3) << 5;
12890 inst
.instruction
|= (abcdebits
>> 2) << 21;
12894 case NS_RRD
: /* case 7 (fmrrd). */
12895 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
12898 inst
.instruction
= 0xc500b10;
12899 do_vfp_cond_or_thumb ();
12900 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12901 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12902 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12903 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12906 case NS_FF
: /* case 8 (fcpys). */
12907 do_vfp_nsyn_opcode ("fcpys");
12910 case NS_FI
: /* case 10 (fconsts). */
12911 ldconst
= "fconsts";
12913 if (is_quarter_float (inst
.operands
[1].imm
))
12915 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
12916 do_vfp_nsyn_opcode (ldconst
);
12919 first_error (_("immediate out of range"));
12922 case NS_RF
: /* case 12 (fmrs). */
12923 do_vfp_nsyn_opcode ("fmrs");
12926 case NS_FR
: /* case 13 (fmsr). */
12927 do_vfp_nsyn_opcode ("fmsr");
12930 /* The encoders for the fmrrs and fmsrr instructions expect three operands
12931 (one of which is a list), but we have parsed four. Do some fiddling to
12932 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
12934 case NS_RRFF
: /* case 14 (fmrrs). */
12935 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
12936 _("VFP registers must be adjacent"));
12937 inst
.operands
[2].imm
= 2;
12938 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
12939 do_vfp_nsyn_opcode ("fmrrs");
12942 case NS_FFRR
: /* case 15 (fmsrr). */
12943 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
12944 _("VFP registers must be adjacent"));
12945 inst
.operands
[1] = inst
.operands
[2];
12946 inst
.operands
[2] = inst
.operands
[3];
12947 inst
.operands
[0].imm
= 2;
12948 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
12949 do_vfp_nsyn_opcode ("fmsrr");
12958 do_neon_rshift_round_imm (void)
12960 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12961 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12962 int imm
= inst
.operands
[2].imm
;
12964 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
12967 inst
.operands
[2].present
= 0;
12972 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12973 _("immediate out of range for shift"));
12974 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12979 do_neon_movl (void)
12981 struct neon_type_el et
= neon_check_type (2, NS_QD
,
12982 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12983 unsigned sizebits
= et
.size
>> 3;
12984 inst
.instruction
|= sizebits
<< 19;
12985 neon_two_same (0, et
.type
== NT_unsigned
, -1);
12991 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12992 struct neon_type_el et
= neon_check_type (2, rs
,
12993 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12994 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12995 neon_two_same (neon_quad (rs
), 1, et
.size
);
12999 do_neon_zip_uzp (void)
13001 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13002 struct neon_type_el et
= neon_check_type (2, rs
,
13003 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13004 if (rs
== NS_DD
&& et
.size
== 32)
13006 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
13007 inst
.instruction
= N_MNEM_vtrn
;
13011 neon_two_same (neon_quad (rs
), 1, et
.size
);
13015 do_neon_sat_abs_neg (void)
13017 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13018 struct neon_type_el et
= neon_check_type (2, rs
,
13019 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13020 neon_two_same (neon_quad (rs
), 1, et
.size
);
13024 do_neon_pair_long (void)
13026 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13027 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
13028 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
13029 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
13030 neon_two_same (neon_quad (rs
), 1, et
.size
);
13034 do_neon_recip_est (void)
13036 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13037 struct neon_type_el et
= neon_check_type (2, rs
,
13038 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
13039 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13040 neon_two_same (neon_quad (rs
), 1, et
.size
);
13046 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13047 struct neon_type_el et
= neon_check_type (2, rs
,
13048 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13049 neon_two_same (neon_quad (rs
), 1, et
.size
);
13055 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13056 struct neon_type_el et
= neon_check_type (2, rs
,
13057 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
13058 neon_two_same (neon_quad (rs
), 1, et
.size
);
13064 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13065 struct neon_type_el et
= neon_check_type (2, rs
,
13066 N_EQK
| N_INT
, N_8
| N_KEY
);
13067 neon_two_same (neon_quad (rs
), 1, et
.size
);
13073 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13074 neon_two_same (neon_quad (rs
), 1, -1);
13078 do_neon_tbl_tbx (void)
13080 unsigned listlenbits
;
13081 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
13083 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
13085 first_error (_("bad list length for table lookup"));
13089 listlenbits
= inst
.operands
[1].imm
- 1;
13090 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13091 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13092 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13093 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13094 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13095 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13096 inst
.instruction
|= listlenbits
<< 8;
13098 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13102 do_neon_ldm_stm (void)
13104 /* P, U and L bits are part of bitmask. */
13105 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
13106 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
13108 if (inst
.operands
[1].issingle
)
13110 do_vfp_nsyn_ldm_stm (is_dbmode
);
13114 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
13115 _("writeback (!) must be used for VLDMDB and VSTMDB"));
13117 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
13118 _("register list must contain at least 1 and at most 16 "
13121 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
13122 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
13123 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13124 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
13126 inst
.instruction
|= offsetbits
;
13128 do_vfp_cond_or_thumb ();
13132 do_neon_ldr_str (void)
13134 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
13136 if (inst
.operands
[0].issingle
)
13139 do_vfp_nsyn_opcode ("flds");
13141 do_vfp_nsyn_opcode ("fsts");
13146 do_vfp_nsyn_opcode ("fldd");
13148 do_vfp_nsyn_opcode ("fstd");
13152 /* "interleave" version also handles non-interleaving register VLD1/VST1
13156 do_neon_ld_st_interleave (void)
13158 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
13159 N_8
| N_16
| N_32
| N_64
);
13160 unsigned alignbits
= 0;
13162 /* The bits in this table go:
13163 0: register stride of one (0) or two (1)
13164 1,2: register list length, minus one (1, 2, 3, 4).
13165 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
13166 We use -1 for invalid entries. */
13167 const int typetable
[] =
13169 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
13170 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
13171 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
13172 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
13176 if (et
.type
== NT_invtype
)
13179 if (inst
.operands
[1].immisalign
)
13180 switch (inst
.operands
[1].imm
>> 8)
13182 case 64: alignbits
= 1; break;
13184 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13185 goto bad_alignment
;
13189 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13190 goto bad_alignment
;
13195 first_error (_("bad alignment"));
13199 inst
.instruction
|= alignbits
<< 4;
13200 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13202 /* Bits [4:6] of the immediate in a list specifier encode register stride
13203 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
13204 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
13205 up the right value for "type" in a table based on this value and the given
13206 list style, then stick it back. */
13207 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
13208 | (((inst
.instruction
>> 8) & 3) << 3);
13210 typebits
= typetable
[idx
];
13212 constraint (typebits
== -1, _("bad list type for instruction"));
13214 inst
.instruction
&= ~0xf00;
13215 inst
.instruction
|= typebits
<< 8;
13218 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
13219 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
13220 otherwise. The variable arguments are a list of pairs of legal (size, align)
13221 values, terminated with -1. */
13224 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
13227 int result
= FAIL
, thissize
, thisalign
;
13229 if (!inst
.operands
[1].immisalign
)
13235 va_start (ap
, do_align
);
13239 thissize
= va_arg (ap
, int);
13240 if (thissize
== -1)
13242 thisalign
= va_arg (ap
, int);
13244 if (size
== thissize
&& align
== thisalign
)
13247 while (result
!= SUCCESS
);
13251 if (result
== SUCCESS
)
13254 first_error (_("unsupported alignment for instruction"));
13260 do_neon_ld_st_lane (void)
13262 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13263 int align_good
, do_align
= 0;
13264 int logsize
= neon_logbits (et
.size
);
13265 int align
= inst
.operands
[1].imm
>> 8;
13266 int n
= (inst
.instruction
>> 8) & 3;
13267 int max_el
= 64 / et
.size
;
13269 if (et
.type
== NT_invtype
)
13272 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
13273 _("bad list length"));
13274 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
13275 _("scalar index out of range"));
13276 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
13278 _("stride of 2 unavailable when element size is 8"));
13282 case 0: /* VLD1 / VST1. */
13283 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
13285 if (align_good
== FAIL
)
13289 unsigned alignbits
= 0;
13292 case 16: alignbits
= 0x1; break;
13293 case 32: alignbits
= 0x3; break;
13296 inst
.instruction
|= alignbits
<< 4;
13300 case 1: /* VLD2 / VST2. */
13301 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
13303 if (align_good
== FAIL
)
13306 inst
.instruction
|= 1 << 4;
13309 case 2: /* VLD3 / VST3. */
13310 constraint (inst
.operands
[1].immisalign
,
13311 _("can't use alignment with this instruction"));
13314 case 3: /* VLD4 / VST4. */
13315 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13316 16, 64, 32, 64, 32, 128, -1);
13317 if (align_good
== FAIL
)
13321 unsigned alignbits
= 0;
13324 case 8: alignbits
= 0x1; break;
13325 case 16: alignbits
= 0x1; break;
13326 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
13329 inst
.instruction
|= alignbits
<< 4;
13336 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
13337 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13338 inst
.instruction
|= 1 << (4 + logsize
);
13340 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
13341 inst
.instruction
|= logsize
<< 10;
13344 /* Encode single n-element structure to all lanes VLD<n> instructions. */
13347 do_neon_ld_dup (void)
13349 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13350 int align_good
, do_align
= 0;
13352 if (et
.type
== NT_invtype
)
13355 switch ((inst
.instruction
>> 8) & 3)
13357 case 0: /* VLD1. */
13358 assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
13359 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13360 &do_align
, 16, 16, 32, 32, -1);
13361 if (align_good
== FAIL
)
13363 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
13366 case 2: inst
.instruction
|= 1 << 5; break;
13367 default: first_error (_("bad list length")); return;
13369 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13372 case 1: /* VLD2. */
13373 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13374 &do_align
, 8, 16, 16, 32, 32, 64, -1);
13375 if (align_good
== FAIL
)
13377 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
13378 _("bad list length"));
13379 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13380 inst
.instruction
|= 1 << 5;
13381 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13384 case 2: /* VLD3. */
13385 constraint (inst
.operands
[1].immisalign
,
13386 _("can't use alignment with this instruction"));
13387 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
13388 _("bad list length"));
13389 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13390 inst
.instruction
|= 1 << 5;
13391 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13394 case 3: /* VLD4. */
13396 int align
= inst
.operands
[1].imm
>> 8;
13397 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13398 16, 64, 32, 64, 32, 128, -1);
13399 if (align_good
== FAIL
)
13401 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
13402 _("bad list length"));
13403 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13404 inst
.instruction
|= 1 << 5;
13405 if (et
.size
== 32 && align
== 128)
13406 inst
.instruction
|= 0x3 << 6;
13408 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13415 inst
.instruction
|= do_align
<< 4;
13418 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
13419 apart from bits [11:4]. */
13422 do_neon_ldx_stx (void)
13424 switch (NEON_LANE (inst
.operands
[0].imm
))
13426 case NEON_INTERLEAVE_LANES
:
13427 inst
.instruction
= NEON_ENC_INTERLV (inst
.instruction
);
13428 do_neon_ld_st_interleave ();
13431 case NEON_ALL_LANES
:
13432 inst
.instruction
= NEON_ENC_DUP (inst
.instruction
);
13437 inst
.instruction
= NEON_ENC_LANE (inst
.instruction
);
13438 do_neon_ld_st_lane ();
13441 /* L bit comes from bit mask. */
13442 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13443 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13444 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13446 if (inst
.operands
[1].postind
)
13448 int postreg
= inst
.operands
[1].imm
& 0xf;
13449 constraint (!inst
.operands
[1].immisreg
,
13450 _("post-index must be a register"));
13451 constraint (postreg
== 0xd || postreg
== 0xf,
13452 _("bad register for post-index"));
13453 inst
.instruction
|= postreg
;
13455 else if (inst
.operands
[1].writeback
)
13457 inst
.instruction
|= 0xd;
13460 inst
.instruction
|= 0xf;
13463 inst
.instruction
|= 0xf9000000;
13465 inst
.instruction
|= 0xf4000000;
13469 /* Overall per-instruction processing. */
13471 /* We need to be able to fix up arbitrary expressions in some statements.
13472 This is so that we can handle symbols that are an arbitrary distance from
13473 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
13474 which returns part of an address in a form which will be valid for
13475 a data instruction. We do this by pushing the expression into a symbol
13476 in the expr_section, and creating a fix for that. */
13479 fix_new_arm (fragS
* frag
,
13494 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
13498 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
13503 /* Mark whether the fix is to a THUMB instruction, or an ARM
13505 new_fix
->tc_fix_data
= thumb_mode
;
13508 /* Create a frg for an instruction requiring relaxation. */
13510 output_relax_insn (void)
13516 /* The size of the instruction is unknown, so tie the debug info to the
13517 start of the instruction. */
13518 dwarf2_emit_insn (0);
13520 switch (inst
.reloc
.exp
.X_op
)
13523 sym
= inst
.reloc
.exp
.X_add_symbol
;
13524 offset
= inst
.reloc
.exp
.X_add_number
;
13528 offset
= inst
.reloc
.exp
.X_add_number
;
13531 sym
= make_expr_symbol (&inst
.reloc
.exp
);
13535 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
13536 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
13537 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
13540 /* Write a 32-bit thumb instruction to buf. */
13542 put_thumb32_insn (char * buf
, unsigned long insn
)
13544 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
13545 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
13549 output_inst (const char * str
)
13555 as_bad ("%s -- `%s'", inst
.error
, str
);
13559 output_relax_insn();
13562 if (inst
.size
== 0)
13565 to
= frag_more (inst
.size
);
13567 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
13569 assert (inst
.size
== (2 * THUMB_SIZE
));
13570 put_thumb32_insn (to
, inst
.instruction
);
13572 else if (inst
.size
> INSN_SIZE
)
13574 assert (inst
.size
== (2 * INSN_SIZE
));
13575 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
13576 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
13579 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
13581 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
13582 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
13583 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
13586 dwarf2_emit_insn (inst
.size
);
13589 /* Tag values used in struct asm_opcode's tag field. */
13592 OT_unconditional
, /* Instruction cannot be conditionalized.
13593 The ARM condition field is still 0xE. */
13594 OT_unconditionalF
, /* Instruction cannot be conditionalized
13595 and carries 0xF in its ARM condition field. */
13596 OT_csuffix
, /* Instruction takes a conditional suffix. */
13597 OT_csuffixF
, /* Some forms of the instruction take a conditional
13598 suffix, others place 0xF where the condition field
13600 OT_cinfix3
, /* Instruction takes a conditional infix,
13601 beginning at character index 3. (In
13602 unified mode, it becomes a suffix.) */
13603 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
13604 tsts, cmps, cmns, and teqs. */
13605 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
13606 character index 3, even in unified mode. Used for
13607 legacy instructions where suffix and infix forms
13608 may be ambiguous. */
13609 OT_csuf_or_in3
, /* Instruction takes either a conditional
13610 suffix or an infix at character index 3. */
13611 OT_odd_infix_unc
, /* This is the unconditional variant of an
13612 instruction that takes a conditional infix
13613 at an unusual position. In unified mode,
13614 this variant will accept a suffix. */
13615 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
13616 are the conditional variants of instructions that
13617 take conditional infixes in unusual positions.
13618 The infix appears at character index
13619 (tag - OT_odd_infix_0). These are not accepted
13620 in unified mode. */
13623 /* Subroutine of md_assemble, responsible for looking up the primary
13624 opcode from the mnemonic the user wrote. STR points to the
13625 beginning of the mnemonic.
13627 This is not simply a hash table lookup, because of conditional
13628 variants. Most instructions have conditional variants, which are
13629 expressed with a _conditional affix_ to the mnemonic. If we were
13630 to encode each conditional variant as a literal string in the opcode
13631 table, it would have approximately 20,000 entries.
13633 Most mnemonics take this affix as a suffix, and in unified syntax,
13634 'most' is upgraded to 'all'. However, in the divided syntax, some
13635 instructions take the affix as an infix, notably the s-variants of
13636 the arithmetic instructions. Of those instructions, all but six
13637 have the infix appear after the third character of the mnemonic.
13639 Accordingly, the algorithm for looking up primary opcodes given
13642 1. Look up the identifier in the opcode table.
13643 If we find a match, go to step U.
13645 2. Look up the last two characters of the identifier in the
13646 conditions table. If we find a match, look up the first N-2
13647 characters of the identifier in the opcode table. If we
13648 find a match, go to step CE.
13650 3. Look up the fourth and fifth characters of the identifier in
13651 the conditions table. If we find a match, extract those
13652 characters from the identifier, and look up the remaining
13653 characters in the opcode table. If we find a match, go
13658 U. Examine the tag field of the opcode structure, in case this is
13659 one of the six instructions with its conditional infix in an
13660 unusual place. If it is, the tag tells us where to find the
13661 infix; look it up in the conditions table and set inst.cond
13662 accordingly. Otherwise, this is an unconditional instruction.
13663 Again set inst.cond accordingly. Return the opcode structure.
13665 CE. Examine the tag field to make sure this is an instruction that
13666 should receive a conditional suffix. If it is not, fail.
13667 Otherwise, set inst.cond from the suffix we already looked up,
13668 and return the opcode structure.
13670 CM. Examine the tag field to make sure this is an instruction that
13671 should receive a conditional infix after the third character.
13672 If it is not, fail. Otherwise, undo the edits to the current
13673 line of input and proceed as for case CE. */
13675 static const struct asm_opcode
*
13676 opcode_lookup (char **str
)
13680 const struct asm_opcode
*opcode
;
13681 const struct asm_cond
*cond
;
13683 bfd_boolean neon_supported
;
13685 neon_supported
= ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
);
13687 /* Scan up to the end of the mnemonic, which must end in white space,
13688 '.' (in unified mode, or for Neon instructions), or end of string. */
13689 for (base
= end
= *str
; *end
!= '\0'; end
++)
13690 if (*end
== ' ' || ((unified_syntax
|| neon_supported
) && *end
== '.'))
13696 /* Handle a possible width suffix and/or Neon type suffix. */
13701 /* The .w and .n suffixes are only valid if the unified syntax is in
13703 if (unified_syntax
&& end
[1] == 'w')
13705 else if (unified_syntax
&& end
[1] == 'n')
13710 inst
.vectype
.elems
= 0;
13712 *str
= end
+ offset
;
13714 if (end
[offset
] == '.')
13716 /* See if we have a Neon type suffix (possible in either unified or
13717 non-unified ARM syntax mode). */
13718 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
13721 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
13727 /* Look for unaffixed or special-case affixed mnemonic. */
13728 opcode
= hash_find_n (arm_ops_hsh
, base
, end
- base
);
13732 if (opcode
->tag
< OT_odd_infix_0
)
13734 inst
.cond
= COND_ALWAYS
;
13738 if (unified_syntax
)
13739 as_warn (_("conditional infixes are deprecated in unified syntax"));
13740 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
13741 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
13744 inst
.cond
= cond
->value
;
13748 /* Cannot have a conditional suffix on a mnemonic of less than two
13750 if (end
- base
< 3)
13753 /* Look for suffixed mnemonic. */
13755 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
13756 opcode
= hash_find_n (arm_ops_hsh
, base
, affix
- base
);
13757 if (opcode
&& cond
)
13760 switch (opcode
->tag
)
13762 case OT_cinfix3_legacy
:
13763 /* Ignore conditional suffixes matched on infix only mnemonics. */
13767 case OT_cinfix3_deprecated
:
13768 case OT_odd_infix_unc
:
13769 if (!unified_syntax
)
13771 /* else fall through */
13775 case OT_csuf_or_in3
:
13776 inst
.cond
= cond
->value
;
13779 case OT_unconditional
:
13780 case OT_unconditionalF
:
13783 inst
.cond
= cond
->value
;
13787 /* delayed diagnostic */
13788 inst
.error
= BAD_COND
;
13789 inst
.cond
= COND_ALWAYS
;
13798 /* Cannot have a usual-position infix on a mnemonic of less than
13799 six characters (five would be a suffix). */
13800 if (end
- base
< 6)
13803 /* Look for infixed mnemonic in the usual position. */
13805 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
13809 memcpy (save
, affix
, 2);
13810 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
13811 opcode
= hash_find_n (arm_ops_hsh
, base
, (end
- base
) - 2);
13812 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
13813 memcpy (affix
, save
, 2);
13816 && (opcode
->tag
== OT_cinfix3
13817 || opcode
->tag
== OT_cinfix3_deprecated
13818 || opcode
->tag
== OT_csuf_or_in3
13819 || opcode
->tag
== OT_cinfix3_legacy
))
13823 && (opcode
->tag
== OT_cinfix3
13824 || opcode
->tag
== OT_cinfix3_deprecated
))
13825 as_warn (_("conditional infixes are deprecated in unified syntax"));
13827 inst
.cond
= cond
->value
;
13835 md_assemble (char *str
)
13838 const struct asm_opcode
* opcode
;
13840 /* Align the previous label if needed. */
13841 if (last_label_seen
!= NULL
)
13843 symbol_set_frag (last_label_seen
, frag_now
);
13844 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
13845 S_SET_SEGMENT (last_label_seen
, now_seg
);
13848 memset (&inst
, '\0', sizeof (inst
));
13849 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13851 opcode
= opcode_lookup (&p
);
13854 /* It wasn't an instruction, but it might be a register alias of
13855 the form alias .req reg, or a Neon .dn/.qn directive. */
13856 if (!create_register_alias (str
, p
)
13857 && !create_neon_reg_alias (str
, p
))
13858 as_bad (_("bad instruction `%s'"), str
);
13863 if (opcode
->tag
== OT_cinfix3_deprecated
)
13864 as_warn (_("s suffix on comparison instruction is deprecated"));
13866 /* The value which unconditional instructions should have in place of the
13867 condition field. */
13868 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
13872 arm_feature_set variant
;
13874 variant
= cpu_variant
;
13875 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
13876 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
13877 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
13878 /* Check that this instruction is supported for this CPU. */
13879 if (!opcode
->tvariant
13880 || (thumb_mode
== 1
13881 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
13883 as_bad (_("selected processor does not support `%s'"), str
);
13886 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
13887 && opcode
->tencode
!= do_t_branch
)
13889 as_bad (_("Thumb does not support conditional execution"));
13893 /* Check conditional suffixes. */
13894 if (current_it_mask
)
13897 cond
= current_cc
^ ((current_it_mask
>> 4) & 1) ^ 1;
13898 current_it_mask
<<= 1;
13899 current_it_mask
&= 0x1f;
13900 /* The BKPT instruction is unconditional even in an IT block. */
13902 && cond
!= inst
.cond
&& opcode
->tencode
!= do_t_bkpt
)
13904 as_bad (_("incorrect condition in IT block"));
13908 else if (inst
.cond
!= COND_ALWAYS
&& opcode
->tencode
!= do_t_branch
)
13910 as_bad (_("thumb conditional instrunction not in IT block"));
13914 mapping_state (MAP_THUMB
);
13915 inst
.instruction
= opcode
->tvalue
;
13917 if (!parse_operands (p
, opcode
->operands
))
13918 opcode
->tencode ();
13920 /* Clear current_it_mask at the end of an IT block. */
13921 if (current_it_mask
== 0x10)
13922 current_it_mask
= 0;
13924 if (!(inst
.error
|| inst
.relax
))
13926 assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
13927 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
13928 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
13930 as_bad (_("cannot honor width suffix -- `%s'"), str
);
13934 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13935 *opcode
->tvariant
);
13936 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
13937 set those bits when Thumb-2 32-bit instructions are seen. ie.
13938 anything other than bl/blx.
13939 This is overly pessimistic for relaxable instructions. */
13940 if ((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
13942 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13945 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
13947 /* Check that this instruction is supported for this CPU. */
13948 if (!opcode
->avariant
||
13949 !ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
))
13951 as_bad (_("selected processor does not support `%s'"), str
);
13956 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
13960 mapping_state (MAP_ARM
);
13961 inst
.instruction
= opcode
->avalue
;
13962 if (opcode
->tag
== OT_unconditionalF
)
13963 inst
.instruction
|= 0xF << 28;
13965 inst
.instruction
|= inst
.cond
<< 28;
13966 inst
.size
= INSN_SIZE
;
13967 if (!parse_operands (p
, opcode
->operands
))
13968 opcode
->aencode ();
13969 /* Arm mode bx is marked as both v4T and v5 because it's still required
13970 on a hypothetical non-thumb v5 core. */
13971 if (ARM_CPU_HAS_FEATURE (*opcode
->avariant
, arm_ext_v4t
)
13972 || ARM_CPU_HAS_FEATURE (*opcode
->avariant
, arm_ext_v5
))
13973 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
13975 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
13976 *opcode
->avariant
);
13980 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
13987 /* Various frobbings of labels and their addresses. */
13990 arm_start_line_hook (void)
13992 last_label_seen
= NULL
;
13996 arm_frob_label (symbolS
* sym
)
13998 last_label_seen
= sym
;
14000 ARM_SET_THUMB (sym
, thumb_mode
);
14002 #if defined OBJ_COFF || defined OBJ_ELF
14003 ARM_SET_INTERWORK (sym
, support_interwork
);
14006 /* Note - do not allow local symbols (.Lxxx) to be labeled
14007 as Thumb functions. This is because these labels, whilst
14008 they exist inside Thumb code, are not the entry points for
14009 possible ARM->Thumb calls. Also, these labels can be used
14010 as part of a computed goto or switch statement. eg gcc
14011 can generate code that looks like this:
14013 ldr r2, [pc, .Laaa]
14023 The first instruction loads the address of the jump table.
14024 The second instruction converts a table index into a byte offset.
14025 The third instruction gets the jump address out of the table.
14026 The fourth instruction performs the jump.
14028 If the address stored at .Laaa is that of a symbol which has the
14029 Thumb_Func bit set, then the linker will arrange for this address
14030 to have the bottom bit set, which in turn would mean that the
14031 address computation performed by the third instruction would end
14032 up with the bottom bit set. Since the ARM is capable of unaligned
14033 word loads, the instruction would then load the incorrect address
14034 out of the jump table, and chaos would ensue. */
14035 if (label_is_thumb_function_name
14036 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
14037 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
14039 /* When the address of a Thumb function is taken the bottom
14040 bit of that address should be set. This will allow
14041 interworking between Arm and Thumb functions to work
14044 THUMB_SET_FUNC (sym
, 1);
14046 label_is_thumb_function_name
= FALSE
;
14049 dwarf2_emit_label (sym
);
14053 arm_data_in_code (void)
14055 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
14057 *input_line_pointer
= '/';
14058 input_line_pointer
+= 5;
14059 *input_line_pointer
= 0;
14067 arm_canonicalize_symbol_name (char * name
)
14071 if (thumb_mode
&& (len
= strlen (name
)) > 5
14072 && streq (name
+ len
- 5, "/data"))
14073 *(name
+ len
- 5) = 0;
14078 /* Table of all register names defined by default. The user can
14079 define additional names with .req. Note that all register names
14080 should appear in both upper and lowercase variants. Some registers
14081 also have mixed-case names. */
14083 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
14084 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
14085 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
14086 #define REGSET(p,t) \
14087 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
14088 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
14089 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
14090 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
14091 #define REGSETH(p,t) \
14092 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
14093 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
14094 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
14095 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
14096 #define REGSET2(p,t) \
14097 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
14098 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
14099 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
14100 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
14102 static const struct reg_entry reg_names
[] =
14104 /* ARM integer registers. */
14105 REGSET(r
, RN
), REGSET(R
, RN
),
14107 /* ATPCS synonyms. */
14108 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
14109 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
14110 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
14112 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
14113 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
14114 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
14116 /* Well-known aliases. */
14117 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
14118 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
14120 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
14121 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
14123 /* Coprocessor numbers. */
14124 REGSET(p
, CP
), REGSET(P
, CP
),
14126 /* Coprocessor register numbers. The "cr" variants are for backward
14128 REGSET(c
, CN
), REGSET(C
, CN
),
14129 REGSET(cr
, CN
), REGSET(CR
, CN
),
14131 /* FPA registers. */
14132 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
14133 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
14135 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
14136 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
14138 /* VFP SP registers. */
14139 REGSET(s
,VFS
), REGSET(S
,VFS
),
14140 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
14142 /* VFP DP Registers. */
14143 REGSET(d
,VFD
), REGSET(D
,VFD
),
14144 /* Extra Neon DP registers. */
14145 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
14147 /* Neon QP registers. */
14148 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
14150 /* VFP control registers. */
14151 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
14152 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
14154 /* Maverick DSP coprocessor registers. */
14155 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
14156 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
14158 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
14159 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
14160 REGDEF(dspsc
,0,DSPSC
),
14162 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
14163 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
14164 REGDEF(DSPSC
,0,DSPSC
),
14166 /* iWMMXt data registers - p0, c0-15. */
14167 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
14169 /* iWMMXt control registers - p1, c0-3. */
14170 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
14171 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
14172 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
14173 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
14175 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
14176 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
14177 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
14178 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
14179 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
14181 /* XScale accumulator registers. */
14182 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
14188 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
14189 within psr_required_here. */
14190 static const struct asm_psr psrs
[] =
14192 /* Backward compatibility notation. Note that "all" is no longer
14193 truly all possible PSR bits. */
14194 {"all", PSR_c
| PSR_f
},
14198 /* Individual flags. */
14203 /* Combinations of flags. */
14204 {"fs", PSR_f
| PSR_s
},
14205 {"fx", PSR_f
| PSR_x
},
14206 {"fc", PSR_f
| PSR_c
},
14207 {"sf", PSR_s
| PSR_f
},
14208 {"sx", PSR_s
| PSR_x
},
14209 {"sc", PSR_s
| PSR_c
},
14210 {"xf", PSR_x
| PSR_f
},
14211 {"xs", PSR_x
| PSR_s
},
14212 {"xc", PSR_x
| PSR_c
},
14213 {"cf", PSR_c
| PSR_f
},
14214 {"cs", PSR_c
| PSR_s
},
14215 {"cx", PSR_c
| PSR_x
},
14216 {"fsx", PSR_f
| PSR_s
| PSR_x
},
14217 {"fsc", PSR_f
| PSR_s
| PSR_c
},
14218 {"fxs", PSR_f
| PSR_x
| PSR_s
},
14219 {"fxc", PSR_f
| PSR_x
| PSR_c
},
14220 {"fcs", PSR_f
| PSR_c
| PSR_s
},
14221 {"fcx", PSR_f
| PSR_c
| PSR_x
},
14222 {"sfx", PSR_s
| PSR_f
| PSR_x
},
14223 {"sfc", PSR_s
| PSR_f
| PSR_c
},
14224 {"sxf", PSR_s
| PSR_x
| PSR_f
},
14225 {"sxc", PSR_s
| PSR_x
| PSR_c
},
14226 {"scf", PSR_s
| PSR_c
| PSR_f
},
14227 {"scx", PSR_s
| PSR_c
| PSR_x
},
14228 {"xfs", PSR_x
| PSR_f
| PSR_s
},
14229 {"xfc", PSR_x
| PSR_f
| PSR_c
},
14230 {"xsf", PSR_x
| PSR_s
| PSR_f
},
14231 {"xsc", PSR_x
| PSR_s
| PSR_c
},
14232 {"xcf", PSR_x
| PSR_c
| PSR_f
},
14233 {"xcs", PSR_x
| PSR_c
| PSR_s
},
14234 {"cfs", PSR_c
| PSR_f
| PSR_s
},
14235 {"cfx", PSR_c
| PSR_f
| PSR_x
},
14236 {"csf", PSR_c
| PSR_s
| PSR_f
},
14237 {"csx", PSR_c
| PSR_s
| PSR_x
},
14238 {"cxf", PSR_c
| PSR_x
| PSR_f
},
14239 {"cxs", PSR_c
| PSR_x
| PSR_s
},
14240 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
14241 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
14242 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
14243 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
14244 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
14245 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
14246 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
14247 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
14248 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
14249 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
14250 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
14251 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
14252 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
14253 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
14254 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
14255 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
14256 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
14257 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
14258 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
14259 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
14260 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
14261 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
14262 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
14263 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
14266 /* Table of V7M psr names. */
14267 static const struct asm_psr v7m_psrs
[] =
14280 {"basepri_max", 18},
14285 /* Table of all shift-in-operand names. */
14286 static const struct asm_shift_name shift_names
[] =
14288 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
14289 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
14290 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
14291 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
14292 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
14293 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
14296 /* Table of all explicit relocation names. */
14298 static struct reloc_entry reloc_names
[] =
14300 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
14301 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
14302 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
14303 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
14304 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
14305 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
14306 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
14307 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
14308 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
14309 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
14310 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
14314 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
14315 static const struct asm_cond conds
[] =
14319 {"cs", 0x2}, {"hs", 0x2},
14320 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
14334 static struct asm_barrier_opt barrier_opt_names
[] =
14342 /* Table of ARM-format instructions. */
14344 /* Macros for gluing together operand strings. N.B. In all cases
14345 other than OPS0, the trailing OP_stop comes from default
14346 zero-initialization of the unspecified elements of the array. */
14347 #define OPS0() { OP_stop, }
14348 #define OPS1(a) { OP_##a, }
14349 #define OPS2(a,b) { OP_##a,OP_##b, }
14350 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
14351 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
14352 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
14353 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
14355 /* These macros abstract out the exact format of the mnemonic table and
14356 save some repeated characters. */
14358 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
14359 #define TxCE(mnem, op, top, nops, ops, ae, te) \
14360 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
14361 THUMB_VARIANT, do_##ae, do_##te }
14363 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
14364 a T_MNEM_xyz enumerator. */
14365 #define TCE(mnem, aop, top, nops, ops, ae, te) \
14366 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
14367 #define tCE(mnem, aop, top, nops, ops, ae, te) \
14368 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14370 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
14371 infix after the third character. */
14372 #define TxC3(mnem, op, top, nops, ops, ae, te) \
14373 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
14374 THUMB_VARIANT, do_##ae, do_##te }
14375 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
14376 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
14377 THUMB_VARIANT, do_##ae, do_##te }
14378 #define TC3(mnem, aop, top, nops, ops, ae, te) \
14379 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
14380 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
14381 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
14382 #define tC3(mnem, aop, top, nops, ops, ae, te) \
14383 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14384 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
14385 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14387 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
14388 appear in the condition table. */
14389 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
14390 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14391 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
14393 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
14394 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
14395 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
14396 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
14397 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
14398 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
14399 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
14400 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
14401 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
14402 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
14403 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
14404 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
14405 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
14406 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
14407 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
14408 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
14409 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
14410 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
14411 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
14412 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
14414 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
14415 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
14416 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
14417 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
14419 /* Mnemonic that cannot be conditionalized. The ARM condition-code
14420 field is still 0xE. Many of the Thumb variants can be executed
14421 conditionally, so this is checked separately. */
14422 #define TUE(mnem, op, top, nops, ops, ae, te) \
14423 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
14424 THUMB_VARIANT, do_##ae, do_##te }
14426 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
14427 condition code field. */
14428 #define TUF(mnem, op, top, nops, ops, ae, te) \
14429 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
14430 THUMB_VARIANT, do_##ae, do_##te }
14432 /* ARM-only variants of all the above. */
14433 #define CE(mnem, op, nops, ops, ae) \
14434 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14436 #define C3(mnem, op, nops, ops, ae) \
14437 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14439 /* Legacy mnemonics that always have conditional infix after the third
14441 #define CL(mnem, op, nops, ops, ae) \
14442 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14443 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14445 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
14446 #define cCE(mnem, op, nops, ops, ae) \
14447 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14449 /* Legacy coprocessor instructions where conditional infix and conditional
14450 suffix are ambiguous. For consistency this includes all FPA instructions,
14451 not just the potentially ambiguous ones. */
14452 #define cCL(mnem, op, nops, ops, ae) \
14453 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14454 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14456 /* Coprocessor, takes either a suffix or a position-3 infix
14457 (for an FPA corner case). */
14458 #define C3E(mnem, op, nops, ops, ae) \
14459 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
14460 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14462 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
14463 { #m1 #m2 #m3, OPS##nops ops, \
14464 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14465 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14467 #define CM(m1, m2, op, nops, ops, ae) \
14468 xCM_(m1, , m2, op, nops, ops, ae), \
14469 xCM_(m1, eq, m2, op, nops, ops, ae), \
14470 xCM_(m1, ne, m2, op, nops, ops, ae), \
14471 xCM_(m1, cs, m2, op, nops, ops, ae), \
14472 xCM_(m1, hs, m2, op, nops, ops, ae), \
14473 xCM_(m1, cc, m2, op, nops, ops, ae), \
14474 xCM_(m1, ul, m2, op, nops, ops, ae), \
14475 xCM_(m1, lo, m2, op, nops, ops, ae), \
14476 xCM_(m1, mi, m2, op, nops, ops, ae), \
14477 xCM_(m1, pl, m2, op, nops, ops, ae), \
14478 xCM_(m1, vs, m2, op, nops, ops, ae), \
14479 xCM_(m1, vc, m2, op, nops, ops, ae), \
14480 xCM_(m1, hi, m2, op, nops, ops, ae), \
14481 xCM_(m1, ls, m2, op, nops, ops, ae), \
14482 xCM_(m1, ge, m2, op, nops, ops, ae), \
14483 xCM_(m1, lt, m2, op, nops, ops, ae), \
14484 xCM_(m1, gt, m2, op, nops, ops, ae), \
14485 xCM_(m1, le, m2, op, nops, ops, ae), \
14486 xCM_(m1, al, m2, op, nops, ops, ae)
14488 #define UE(mnem, op, nops, ops, ae) \
14489 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14491 #define UF(mnem, op, nops, ops, ae) \
14492 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14494 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
14495 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
14496 use the same encoding function for each. */
14497 #define NUF(mnem, op, nops, ops, enc) \
14498 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
14499 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14501 /* Neon data processing, version which indirects through neon_enc_tab for
14502 the various overloaded versions of opcodes. */
14503 #define nUF(mnem, op, nops, ops, enc) \
14504 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \
14505 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14507 /* Neon insn with conditional suffix for the ARM version, non-overloaded
14509 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
14510 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
14511 THUMB_VARIANT, do_##enc, do_##enc }
14513 #define NCE(mnem, op, nops, ops, enc) \
14514 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14516 #define NCEF(mnem, op, nops, ops, enc) \
14517 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14519 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
14520 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
14521 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \
14522 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14524 #define nCE(mnem, op, nops, ops, enc) \
14525 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14527 #define nCEF(mnem, op, nops, ops, enc) \
14528 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14532 /* Thumb-only, unconditional. */
14533 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
14535 static const struct asm_opcode insns
[] =
14537 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
14538 #define THUMB_VARIANT &arm_ext_v4t
14539 tCE(and, 0000000, and, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14540 tC3(ands
, 0100000, ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14541 tCE(eor
, 0200000, eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14542 tC3(eors
, 0300000, eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14543 tCE(sub
, 0400000, sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14544 tC3(subs
, 0500000, subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14545 tCE(add
, 0800000, add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14546 tC3(adds
, 0900000, adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14547 tCE(adc
, 0a00000
, adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14548 tC3(adcs
, 0b00000, adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14549 tCE(sbc
, 0c00000
, sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14550 tC3(sbcs
, 0d00000
, sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14551 tCE(orr
, 1800000, orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14552 tC3(orrs
, 1900000, orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14553 tCE(bic
, 1c00000
, bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14554 tC3(bics
, 1d00000
, bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14556 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
14557 for setting PSR flag bits. They are obsolete in V6 and do not
14558 have Thumb equivalents. */
14559 tCE(tst
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14560 tC3w(tsts
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14561 CL(tstp
, 110f000
, 2, (RR
, SH
), cmp
),
14562 tCE(cmp
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14563 tC3w(cmps
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14564 CL(cmpp
, 150f000
, 2, (RR
, SH
), cmp
),
14565 tCE(cmn
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14566 tC3w(cmns
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14567 CL(cmnp
, 170f000
, 2, (RR
, SH
), cmp
),
14569 tCE(mov
, 1a00000
, mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14570 tC3(movs
, 1b00000
, movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14571 tCE(mvn
, 1e00000
, mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14572 tC3(mvns
, 1f00000
, mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14574 tCE(ldr
, 4100000, ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14575 tC3(ldrb
, 4500000, ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14576 tCE(str
, 4000000, str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14577 tC3(strb
, 4400000, strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14579 tCE(stm
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14580 tC3(stmia
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14581 tC3(stmea
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14582 tCE(ldm
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14583 tC3(ldmia
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14584 tC3(ldmfd
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14586 TCE(swi
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14587 TCE(svc
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14588 tCE(b
, a000000
, b
, 1, (EXPr
), branch
, t_branch
),
14589 TCE(bl
, b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
14592 tCE(adr
, 28f0000
, adr
, 2, (RR
, EXP
), adr
, t_adr
),
14593 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
14594 tCE(nop
, 1a00000
, nop
, 1, (oI255c
), nop
, t_nop
),
14596 /* Thumb-compatibility pseudo ops. */
14597 tCE(lsl
, 1a00000
, lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14598 tC3(lsls
, 1b00000
, lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14599 tCE(lsr
, 1a00020
, lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14600 tC3(lsrs
, 1b00020
, lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14601 tCE(asr
, 1a00040
, asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14602 tC3(asrs
, 1b00040
, asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14603 tCE(ror
, 1a00060
, ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14604 tC3(rors
, 1b00060
, rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14605 tCE(neg
, 2600000, neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
14606 tC3(negs
, 2700000, negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
14607 tCE(push
, 92d0000
, push
, 1, (REGLST
), push_pop
, t_push_pop
),
14608 tCE(pop
, 8bd0000
, pop
, 1, (REGLST
), push_pop
, t_push_pop
),
14610 #undef THUMB_VARIANT
14611 #define THUMB_VARIANT &arm_ext_v6
14612 TCE(cpy
, 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
14614 /* V1 instructions with no Thumb analogue prior to V6T2. */
14615 #undef THUMB_VARIANT
14616 #define THUMB_VARIANT &arm_ext_v6t2
14617 TCE(rsb
, 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14618 TC3(rsbs
, 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14619 TCE(teq
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14620 TC3w(teqs
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14621 CL(teqp
, 130f000
, 2, (RR
, SH
), cmp
),
14623 TC3(ldrt
, 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14624 TC3(ldrbt
, 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14625 TC3(strt
, 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14626 TC3(strbt
, 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14628 TC3(stmdb
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14629 TC3(stmfd
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14631 TC3(ldmdb
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14632 TC3(ldmea
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14634 /* V1 instructions with no Thumb analogue at all. */
14635 CE(rsc
, 0e00000
, 3, (RR
, oRR
, SH
), arit
),
14636 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
14638 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
14639 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
14640 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
14641 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
14642 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
14643 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
14644 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
14645 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
14648 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
14649 #undef THUMB_VARIANT
14650 #define THUMB_VARIANT &arm_ext_v4t
14651 tCE(mul
, 0000090, mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
14652 tC3(muls
, 0100090, muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
14654 #undef THUMB_VARIANT
14655 #define THUMB_VARIANT &arm_ext_v6t2
14656 TCE(mla
, 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
14657 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
14659 /* Generic coprocessor instructions. */
14660 TCE(cdp
, e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
14661 TCE(ldc
, c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14662 TC3(ldcl
, c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14663 TCE(stc
, c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14664 TC3(stcl
, c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14665 TCE(mcr
, e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14666 TCE(mrc
, e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14669 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
14670 CE(swp
, 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
14671 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
14674 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
14675 TCE(mrs
, 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
14676 TCE(msr
, 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
14679 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
14680 TCE(smull
, 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14681 CM(smull
,s
, 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14682 TCE(umull
, 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14683 CM(umull
,s
, 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14684 TCE(smlal
, 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14685 CM(smlal
,s
, 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14686 TCE(umlal
, 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14687 CM(umlal
,s
, 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14690 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
14691 #undef THUMB_VARIANT
14692 #define THUMB_VARIANT &arm_ext_v4t
14693 tC3(ldrh
, 01000b0
, ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14694 tC3(strh
, 00000b0
, strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14695 tC3(ldrsh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14696 tC3(ldrsb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14697 tCM(ld
,sh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14698 tCM(ld
,sb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14701 #define ARM_VARIANT &arm_ext_v4t_5
14702 /* ARM Architecture 4T. */
14703 /* Note: bx (and blx) are required on V5, even if the processor does
14704 not support Thumb. */
14705 TCE(bx
, 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
14708 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
14709 #undef THUMB_VARIANT
14710 #define THUMB_VARIANT &arm_ext_v5t
14711 /* Note: blx has 2 variants; the .value coded here is for
14712 BLX(2). Only this variant has conditional execution. */
14713 TCE(blx
, 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
14714 TUE(bkpt
, 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
14716 #undef THUMB_VARIANT
14717 #define THUMB_VARIANT &arm_ext_v6t2
14718 TCE(clz
, 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
14719 TUF(ldc2
, c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14720 TUF(ldc2l
, c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14721 TUF(stc2
, c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14722 TUF(stc2l
, c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14723 TUF(cdp2
, e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
14724 TUF(mcr2
, e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14725 TUF(mrc2
, e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14728 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
14729 TCE(smlabb
, 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14730 TCE(smlatb
, 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14731 TCE(smlabt
, 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14732 TCE(smlatt
, 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14734 TCE(smlawb
, 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14735 TCE(smlawt
, 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14737 TCE(smlalbb
, 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14738 TCE(smlaltb
, 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14739 TCE(smlalbt
, 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14740 TCE(smlaltt
, 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14742 TCE(smulbb
, 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14743 TCE(smultb
, 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14744 TCE(smulbt
, 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14745 TCE(smultt
, 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14747 TCE(smulwb
, 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14748 TCE(smulwt
, 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14750 TCE(qadd
, 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14751 TCE(qdadd
, 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14752 TCE(qsub
, 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14753 TCE(qdsub
, 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14756 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
14757 TUF(pld
, 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
14758 TC3(ldrd
, 00000d0
, e9500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
14759 TC3(strd
, 00000f0
, e9400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
14761 TCE(mcrr
, c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14762 TCE(mrrc
, c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14765 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
14766 TCE(bxj
, 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
14769 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
14770 #undef THUMB_VARIANT
14771 #define THUMB_VARIANT &arm_ext_v6
14772 TUF(cpsie
, 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
14773 TUF(cpsid
, 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
14774 tCE(rev
, 6bf0f30
, rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
14775 tCE(rev16
, 6bf0fb0
, rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
14776 tCE(revsh
, 6ff0fb0
, revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
14777 tCE(sxth
, 6bf0070
, sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14778 tCE(uxth
, 6ff0070
, uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14779 tCE(sxtb
, 6af0070
, sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14780 tCE(uxtb
, 6ef0070
, uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14781 TUF(setend
, 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
14783 #undef THUMB_VARIANT
14784 #define THUMB_VARIANT &arm_ext_v6t2
14785 TCE(ldrex
, 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
14786 TUF(mcrr2
, c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14787 TUF(mrrc2
, c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14789 TCE(ssat
, 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
14790 TCE(usat
, 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
14792 /* ARM V6 not included in V7M (eg. integer SIMD). */
14793 #undef THUMB_VARIANT
14794 #define THUMB_VARIANT &arm_ext_v6_notm
14795 TUF(cps
, 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
14796 TCE(pkhbt
, 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
14797 TCE(pkhtb
, 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
14798 TCE(qadd16
, 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14799 TCE(qadd8
, 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14800 TCE(qaddsubx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14801 TCE(qsub16
, 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14802 TCE(qsub8
, 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14803 TCE(qsubaddx
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14804 TCE(sadd16
, 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14805 TCE(sadd8
, 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14806 TCE(saddsubx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14807 TCE(shadd16
, 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14808 TCE(shadd8
, 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14809 TCE(shaddsubx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14810 TCE(shsub16
, 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14811 TCE(shsub8
, 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14812 TCE(shsubaddx
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14813 TCE(ssub16
, 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14814 TCE(ssub8
, 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14815 TCE(ssubaddx
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14816 TCE(uadd16
, 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14817 TCE(uadd8
, 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14818 TCE(uaddsubx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14819 TCE(uhadd16
, 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14820 TCE(uhadd8
, 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14821 TCE(uhaddsubx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14822 TCE(uhsub16
, 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14823 TCE(uhsub8
, 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14824 TCE(uhsubaddx
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14825 TCE(uqadd16
, 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14826 TCE(uqadd8
, 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14827 TCE(uqaddsubx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14828 TCE(uqsub16
, 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14829 TCE(uqsub8
, 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14830 TCE(uqsubaddx
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14831 TCE(usub16
, 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14832 TCE(usub8
, 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14833 TCE(usubaddx
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14834 TUF(rfeia
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
14835 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
14836 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
14837 TUF(rfedb
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
14838 TUF(rfefd
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
14839 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
14840 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
14841 TUF(rfeed
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
14842 TCE(sxtah
, 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14843 TCE(sxtab16
, 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14844 TCE(sxtab
, 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14845 TCE(sxtb16
, 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14846 TCE(uxtah
, 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14847 TCE(uxtab16
, 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14848 TCE(uxtab
, 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14849 TCE(uxtb16
, 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14850 TCE(sel
, 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14851 TCE(smlad
, 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14852 TCE(smladx
, 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14853 TCE(smlald
, 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14854 TCE(smlaldx
, 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14855 TCE(smlsd
, 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14856 TCE(smlsdx
, 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14857 TCE(smlsld
, 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14858 TCE(smlsldx
, 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14859 TCE(smmla
, 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14860 TCE(smmlar
, 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14861 TCE(smmls
, 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14862 TCE(smmlsr
, 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14863 TCE(smmul
, 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14864 TCE(smmulr
, 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14865 TCE(smuad
, 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14866 TCE(smuadx
, 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14867 TCE(smusd
, 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14868 TCE(smusdx
, 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14869 TUF(srsia
, 8cd0500
, e980c000
, 1, (I31w
), srs
, srs
),
14870 UF(srsib
, 9cd0500
, 1, (I31w
), srs
),
14871 UF(srsda
, 84d0500
, 1, (I31w
), srs
),
14872 TUF(srsdb
, 94d0500
, e800c000
, 1, (I31w
), srs
, srs
),
14873 TCE(ssat16
, 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
14874 TCE(strex
, 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
14875 TCE(umaal
, 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
14876 TCE(usad8
, 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14877 TCE(usada8
, 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14878 TCE(usat16
, 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
14881 #define ARM_VARIANT &arm_ext_v6k
14882 #undef THUMB_VARIANT
14883 #define THUMB_VARIANT &arm_ext_v6k
14884 tCE(yield
, 320f001
, yield
, 0, (), noargs
, t_hint
),
14885 tCE(wfe
, 320f002
, wfe
, 0, (), noargs
, t_hint
),
14886 tCE(wfi
, 320f003
, wfi
, 0, (), noargs
, t_hint
),
14887 tCE(sev
, 320f004
, sev
, 0, (), noargs
, t_hint
),
14889 #undef THUMB_VARIANT
14890 #define THUMB_VARIANT &arm_ext_v6_notm
14891 TCE(ldrexd
, 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
14892 TCE(strexd
, 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
14894 #undef THUMB_VARIANT
14895 #define THUMB_VARIANT &arm_ext_v6t2
14896 TCE(ldrexb
, 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
14897 TCE(ldrexh
, 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
14898 TCE(strexb
, 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
14899 TCE(strexh
, 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
14900 TUF(clrex
, 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
14903 #define ARM_VARIANT &arm_ext_v6z
14904 TCE(smc
, 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
14907 #define ARM_VARIANT &arm_ext_v6t2
14908 TCE(bfc
, 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
14909 TCE(bfi
, 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
14910 TCE(sbfx
, 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
14911 TCE(ubfx
, 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
14913 TCE(mls
, 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
14914 TCE(movw
, 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
14915 TCE(movt
, 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
14916 TCE(rbit
, 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
14918 TC3(ldrht
, 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
14919 TC3(ldrsht
, 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
14920 TC3(ldrsbt
, 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
14921 TC3(strht
, 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
14923 UT(cbnz
, b900
, 2, (RR
, EXP
), t_czb
),
14924 UT(cbz
, b100
, 2, (RR
, EXP
), t_czb
),
14925 /* ARM does not really have an IT instruction, so always allow it. */
14927 #define ARM_VARIANT &arm_ext_v1
14928 TUE(it
, 0, bf08
, 1, (COND
), it
, t_it
),
14929 TUE(itt
, 0, bf0c
, 1, (COND
), it
, t_it
),
14930 TUE(ite
, 0, bf04
, 1, (COND
), it
, t_it
),
14931 TUE(ittt
, 0, bf0e
, 1, (COND
), it
, t_it
),
14932 TUE(itet
, 0, bf06
, 1, (COND
), it
, t_it
),
14933 TUE(itte
, 0, bf0a
, 1, (COND
), it
, t_it
),
14934 TUE(itee
, 0, bf02
, 1, (COND
), it
, t_it
),
14935 TUE(itttt
, 0, bf0f
, 1, (COND
), it
, t_it
),
14936 TUE(itett
, 0, bf07
, 1, (COND
), it
, t_it
),
14937 TUE(ittet
, 0, bf0b
, 1, (COND
), it
, t_it
),
14938 TUE(iteet
, 0, bf03
, 1, (COND
), it
, t_it
),
14939 TUE(ittte
, 0, bf0d
, 1, (COND
), it
, t_it
),
14940 TUE(itete
, 0, bf05
, 1, (COND
), it
, t_it
),
14941 TUE(ittee
, 0, bf09
, 1, (COND
), it
, t_it
),
14942 TUE(iteee
, 0, bf01
, 1, (COND
), it
, t_it
),
14944 /* Thumb2 only instructions. */
14946 #define ARM_VARIANT NULL
14948 TCE(addw
, 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
14949 TCE(subw
, 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
14950 TCE(tbb
, 0, e8d0f000
, 1, (TB
), 0, t_tb
),
14951 TCE(tbh
, 0, e8d0f010
, 1, (TB
), 0, t_tb
),
14953 /* Thumb-2 hardware division instructions (R and M profiles only). */
14954 #undef THUMB_VARIANT
14955 #define THUMB_VARIANT &arm_ext_div
14956 TCE(sdiv
, 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
14957 TCE(udiv
, 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
14959 /* ARM V7 instructions. */
14961 #define ARM_VARIANT &arm_ext_v7
14962 #undef THUMB_VARIANT
14963 #define THUMB_VARIANT &arm_ext_v7
14964 TUF(pli
, 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
14965 TCE(dbg
, 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
14966 TUF(dmb
, 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
14967 TUF(dsb
, 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
14968 TUF(isb
, 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
14971 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
14972 cCE(wfs
, e200110
, 1, (RR
), rd
),
14973 cCE(rfs
, e300110
, 1, (RR
), rd
),
14974 cCE(wfc
, e400110
, 1, (RR
), rd
),
14975 cCE(rfc
, e500110
, 1, (RR
), rd
),
14977 cCL(ldfs
, c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14978 cCL(ldfd
, c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14979 cCL(ldfe
, c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14980 cCL(ldfp
, c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14982 cCL(stfs
, c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14983 cCL(stfd
, c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14984 cCL(stfe
, c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14985 cCL(stfp
, c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14987 cCL(mvfs
, e008100
, 2, (RF
, RF_IF
), rd_rm
),
14988 cCL(mvfsp
, e008120
, 2, (RF
, RF_IF
), rd_rm
),
14989 cCL(mvfsm
, e008140
, 2, (RF
, RF_IF
), rd_rm
),
14990 cCL(mvfsz
, e008160
, 2, (RF
, RF_IF
), rd_rm
),
14991 cCL(mvfd
, e008180
, 2, (RF
, RF_IF
), rd_rm
),
14992 cCL(mvfdp
, e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
14993 cCL(mvfdm
, e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
14994 cCL(mvfdz
, e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
14995 cCL(mvfe
, e088100
, 2, (RF
, RF_IF
), rd_rm
),
14996 cCL(mvfep
, e088120
, 2, (RF
, RF_IF
), rd_rm
),
14997 cCL(mvfem
, e088140
, 2, (RF
, RF_IF
), rd_rm
),
14998 cCL(mvfez
, e088160
, 2, (RF
, RF_IF
), rd_rm
),
15000 cCL(mnfs
, e108100
, 2, (RF
, RF_IF
), rd_rm
),
15001 cCL(mnfsp
, e108120
, 2, (RF
, RF_IF
), rd_rm
),
15002 cCL(mnfsm
, e108140
, 2, (RF
, RF_IF
), rd_rm
),
15003 cCL(mnfsz
, e108160
, 2, (RF
, RF_IF
), rd_rm
),
15004 cCL(mnfd
, e108180
, 2, (RF
, RF_IF
), rd_rm
),
15005 cCL(mnfdp
, e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
15006 cCL(mnfdm
, e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
15007 cCL(mnfdz
, e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
15008 cCL(mnfe
, e188100
, 2, (RF
, RF_IF
), rd_rm
),
15009 cCL(mnfep
, e188120
, 2, (RF
, RF_IF
), rd_rm
),
15010 cCL(mnfem
, e188140
, 2, (RF
, RF_IF
), rd_rm
),
15011 cCL(mnfez
, e188160
, 2, (RF
, RF_IF
), rd_rm
),
15013 cCL(abss
, e208100
, 2, (RF
, RF_IF
), rd_rm
),
15014 cCL(abssp
, e208120
, 2, (RF
, RF_IF
), rd_rm
),
15015 cCL(abssm
, e208140
, 2, (RF
, RF_IF
), rd_rm
),
15016 cCL(abssz
, e208160
, 2, (RF
, RF_IF
), rd_rm
),
15017 cCL(absd
, e208180
, 2, (RF
, RF_IF
), rd_rm
),
15018 cCL(absdp
, e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
15019 cCL(absdm
, e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
15020 cCL(absdz
, e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
15021 cCL(abse
, e288100
, 2, (RF
, RF_IF
), rd_rm
),
15022 cCL(absep
, e288120
, 2, (RF
, RF_IF
), rd_rm
),
15023 cCL(absem
, e288140
, 2, (RF
, RF_IF
), rd_rm
),
15024 cCL(absez
, e288160
, 2, (RF
, RF_IF
), rd_rm
),
15026 cCL(rnds
, e308100
, 2, (RF
, RF_IF
), rd_rm
),
15027 cCL(rndsp
, e308120
, 2, (RF
, RF_IF
), rd_rm
),
15028 cCL(rndsm
, e308140
, 2, (RF
, RF_IF
), rd_rm
),
15029 cCL(rndsz
, e308160
, 2, (RF
, RF_IF
), rd_rm
),
15030 cCL(rndd
, e308180
, 2, (RF
, RF_IF
), rd_rm
),
15031 cCL(rnddp
, e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
15032 cCL(rnddm
, e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
15033 cCL(rnddz
, e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
15034 cCL(rnde
, e388100
, 2, (RF
, RF_IF
), rd_rm
),
15035 cCL(rndep
, e388120
, 2, (RF
, RF_IF
), rd_rm
),
15036 cCL(rndem
, e388140
, 2, (RF
, RF_IF
), rd_rm
),
15037 cCL(rndez
, e388160
, 2, (RF
, RF_IF
), rd_rm
),
15039 cCL(sqts
, e408100
, 2, (RF
, RF_IF
), rd_rm
),
15040 cCL(sqtsp
, e408120
, 2, (RF
, RF_IF
), rd_rm
),
15041 cCL(sqtsm
, e408140
, 2, (RF
, RF_IF
), rd_rm
),
15042 cCL(sqtsz
, e408160
, 2, (RF
, RF_IF
), rd_rm
),
15043 cCL(sqtd
, e408180
, 2, (RF
, RF_IF
), rd_rm
),
15044 cCL(sqtdp
, e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
15045 cCL(sqtdm
, e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
15046 cCL(sqtdz
, e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
15047 cCL(sqte
, e488100
, 2, (RF
, RF_IF
), rd_rm
),
15048 cCL(sqtep
, e488120
, 2, (RF
, RF_IF
), rd_rm
),
15049 cCL(sqtem
, e488140
, 2, (RF
, RF_IF
), rd_rm
),
15050 cCL(sqtez
, e488160
, 2, (RF
, RF_IF
), rd_rm
),
15052 cCL(logs
, e508100
, 2, (RF
, RF_IF
), rd_rm
),
15053 cCL(logsp
, e508120
, 2, (RF
, RF_IF
), rd_rm
),
15054 cCL(logsm
, e508140
, 2, (RF
, RF_IF
), rd_rm
),
15055 cCL(logsz
, e508160
, 2, (RF
, RF_IF
), rd_rm
),
15056 cCL(logd
, e508180
, 2, (RF
, RF_IF
), rd_rm
),
15057 cCL(logdp
, e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
15058 cCL(logdm
, e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
15059 cCL(logdz
, e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
15060 cCL(loge
, e588100
, 2, (RF
, RF_IF
), rd_rm
),
15061 cCL(logep
, e588120
, 2, (RF
, RF_IF
), rd_rm
),
15062 cCL(logem
, e588140
, 2, (RF
, RF_IF
), rd_rm
),
15063 cCL(logez
, e588160
, 2, (RF
, RF_IF
), rd_rm
),
15065 cCL(lgns
, e608100
, 2, (RF
, RF_IF
), rd_rm
),
15066 cCL(lgnsp
, e608120
, 2, (RF
, RF_IF
), rd_rm
),
15067 cCL(lgnsm
, e608140
, 2, (RF
, RF_IF
), rd_rm
),
15068 cCL(lgnsz
, e608160
, 2, (RF
, RF_IF
), rd_rm
),
15069 cCL(lgnd
, e608180
, 2, (RF
, RF_IF
), rd_rm
),
15070 cCL(lgndp
, e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
15071 cCL(lgndm
, e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
15072 cCL(lgndz
, e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
15073 cCL(lgne
, e688100
, 2, (RF
, RF_IF
), rd_rm
),
15074 cCL(lgnep
, e688120
, 2, (RF
, RF_IF
), rd_rm
),
15075 cCL(lgnem
, e688140
, 2, (RF
, RF_IF
), rd_rm
),
15076 cCL(lgnez
, e688160
, 2, (RF
, RF_IF
), rd_rm
),
15078 cCL(exps
, e708100
, 2, (RF
, RF_IF
), rd_rm
),
15079 cCL(expsp
, e708120
, 2, (RF
, RF_IF
), rd_rm
),
15080 cCL(expsm
, e708140
, 2, (RF
, RF_IF
), rd_rm
),
15081 cCL(expsz
, e708160
, 2, (RF
, RF_IF
), rd_rm
),
15082 cCL(expd
, e708180
, 2, (RF
, RF_IF
), rd_rm
),
15083 cCL(expdp
, e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
15084 cCL(expdm
, e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
15085 cCL(expdz
, e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
15086 cCL(expe
, e788100
, 2, (RF
, RF_IF
), rd_rm
),
15087 cCL(expep
, e788120
, 2, (RF
, RF_IF
), rd_rm
),
15088 cCL(expem
, e788140
, 2, (RF
, RF_IF
), rd_rm
),
15089 cCL(expdz
, e788160
, 2, (RF
, RF_IF
), rd_rm
),
15091 cCL(sins
, e808100
, 2, (RF
, RF_IF
), rd_rm
),
15092 cCL(sinsp
, e808120
, 2, (RF
, RF_IF
), rd_rm
),
15093 cCL(sinsm
, e808140
, 2, (RF
, RF_IF
), rd_rm
),
15094 cCL(sinsz
, e808160
, 2, (RF
, RF_IF
), rd_rm
),
15095 cCL(sind
, e808180
, 2, (RF
, RF_IF
), rd_rm
),
15096 cCL(sindp
, e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
15097 cCL(sindm
, e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
15098 cCL(sindz
, e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
15099 cCL(sine
, e888100
, 2, (RF
, RF_IF
), rd_rm
),
15100 cCL(sinep
, e888120
, 2, (RF
, RF_IF
), rd_rm
),
15101 cCL(sinem
, e888140
, 2, (RF
, RF_IF
), rd_rm
),
15102 cCL(sinez
, e888160
, 2, (RF
, RF_IF
), rd_rm
),
15104 cCL(coss
, e908100
, 2, (RF
, RF_IF
), rd_rm
),
15105 cCL(cossp
, e908120
, 2, (RF
, RF_IF
), rd_rm
),
15106 cCL(cossm
, e908140
, 2, (RF
, RF_IF
), rd_rm
),
15107 cCL(cossz
, e908160
, 2, (RF
, RF_IF
), rd_rm
),
15108 cCL(cosd
, e908180
, 2, (RF
, RF_IF
), rd_rm
),
15109 cCL(cosdp
, e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
15110 cCL(cosdm
, e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
15111 cCL(cosdz
, e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
15112 cCL(cose
, e988100
, 2, (RF
, RF_IF
), rd_rm
),
15113 cCL(cosep
, e988120
, 2, (RF
, RF_IF
), rd_rm
),
15114 cCL(cosem
, e988140
, 2, (RF
, RF_IF
), rd_rm
),
15115 cCL(cosez
, e988160
, 2, (RF
, RF_IF
), rd_rm
),
15117 cCL(tans
, ea08100
, 2, (RF
, RF_IF
), rd_rm
),
15118 cCL(tansp
, ea08120
, 2, (RF
, RF_IF
), rd_rm
),
15119 cCL(tansm
, ea08140
, 2, (RF
, RF_IF
), rd_rm
),
15120 cCL(tansz
, ea08160
, 2, (RF
, RF_IF
), rd_rm
),
15121 cCL(tand
, ea08180
, 2, (RF
, RF_IF
), rd_rm
),
15122 cCL(tandp
, ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
15123 cCL(tandm
, ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
15124 cCL(tandz
, ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
15125 cCL(tane
, ea88100
, 2, (RF
, RF_IF
), rd_rm
),
15126 cCL(tanep
, ea88120
, 2, (RF
, RF_IF
), rd_rm
),
15127 cCL(tanem
, ea88140
, 2, (RF
, RF_IF
), rd_rm
),
15128 cCL(tanez
, ea88160
, 2, (RF
, RF_IF
), rd_rm
),
15130 cCL(asns
, eb08100
, 2, (RF
, RF_IF
), rd_rm
),
15131 cCL(asnsp
, eb08120
, 2, (RF
, RF_IF
), rd_rm
),
15132 cCL(asnsm
, eb08140
, 2, (RF
, RF_IF
), rd_rm
),
15133 cCL(asnsz
, eb08160
, 2, (RF
, RF_IF
), rd_rm
),
15134 cCL(asnd
, eb08180
, 2, (RF
, RF_IF
), rd_rm
),
15135 cCL(asndp
, eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
15136 cCL(asndm
, eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
15137 cCL(asndz
, eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
15138 cCL(asne
, eb88100
, 2, (RF
, RF_IF
), rd_rm
),
15139 cCL(asnep
, eb88120
, 2, (RF
, RF_IF
), rd_rm
),
15140 cCL(asnem
, eb88140
, 2, (RF
, RF_IF
), rd_rm
),
15141 cCL(asnez
, eb88160
, 2, (RF
, RF_IF
), rd_rm
),
15143 cCL(acss
, ec08100
, 2, (RF
, RF_IF
), rd_rm
),
15144 cCL(acssp
, ec08120
, 2, (RF
, RF_IF
), rd_rm
),
15145 cCL(acssm
, ec08140
, 2, (RF
, RF_IF
), rd_rm
),
15146 cCL(acssz
, ec08160
, 2, (RF
, RF_IF
), rd_rm
),
15147 cCL(acsd
, ec08180
, 2, (RF
, RF_IF
), rd_rm
),
15148 cCL(acsdp
, ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
15149 cCL(acsdm
, ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
15150 cCL(acsdz
, ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
15151 cCL(acse
, ec88100
, 2, (RF
, RF_IF
), rd_rm
),
15152 cCL(acsep
, ec88120
, 2, (RF
, RF_IF
), rd_rm
),
15153 cCL(acsem
, ec88140
, 2, (RF
, RF_IF
), rd_rm
),
15154 cCL(acsez
, ec88160
, 2, (RF
, RF_IF
), rd_rm
),
15156 cCL(atns
, ed08100
, 2, (RF
, RF_IF
), rd_rm
),
15157 cCL(atnsp
, ed08120
, 2, (RF
, RF_IF
), rd_rm
),
15158 cCL(atnsm
, ed08140
, 2, (RF
, RF_IF
), rd_rm
),
15159 cCL(atnsz
, ed08160
, 2, (RF
, RF_IF
), rd_rm
),
15160 cCL(atnd
, ed08180
, 2, (RF
, RF_IF
), rd_rm
),
15161 cCL(atndp
, ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
15162 cCL(atndm
, ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
15163 cCL(atndz
, ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
15164 cCL(atne
, ed88100
, 2, (RF
, RF_IF
), rd_rm
),
15165 cCL(atnep
, ed88120
, 2, (RF
, RF_IF
), rd_rm
),
15166 cCL(atnem
, ed88140
, 2, (RF
, RF_IF
), rd_rm
),
15167 cCL(atnez
, ed88160
, 2, (RF
, RF_IF
), rd_rm
),
15169 cCL(urds
, ee08100
, 2, (RF
, RF_IF
), rd_rm
),
15170 cCL(urdsp
, ee08120
, 2, (RF
, RF_IF
), rd_rm
),
15171 cCL(urdsm
, ee08140
, 2, (RF
, RF_IF
), rd_rm
),
15172 cCL(urdsz
, ee08160
, 2, (RF
, RF_IF
), rd_rm
),
15173 cCL(urdd
, ee08180
, 2, (RF
, RF_IF
), rd_rm
),
15174 cCL(urddp
, ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
15175 cCL(urddm
, ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
15176 cCL(urddz
, ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
15177 cCL(urde
, ee88100
, 2, (RF
, RF_IF
), rd_rm
),
15178 cCL(urdep
, ee88120
, 2, (RF
, RF_IF
), rd_rm
),
15179 cCL(urdem
, ee88140
, 2, (RF
, RF_IF
), rd_rm
),
15180 cCL(urdez
, ee88160
, 2, (RF
, RF_IF
), rd_rm
),
15182 cCL(nrms
, ef08100
, 2, (RF
, RF_IF
), rd_rm
),
15183 cCL(nrmsp
, ef08120
, 2, (RF
, RF_IF
), rd_rm
),
15184 cCL(nrmsm
, ef08140
, 2, (RF
, RF_IF
), rd_rm
),
15185 cCL(nrmsz
, ef08160
, 2, (RF
, RF_IF
), rd_rm
),
15186 cCL(nrmd
, ef08180
, 2, (RF
, RF_IF
), rd_rm
),
15187 cCL(nrmdp
, ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
15188 cCL(nrmdm
, ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
15189 cCL(nrmdz
, ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
15190 cCL(nrme
, ef88100
, 2, (RF
, RF_IF
), rd_rm
),
15191 cCL(nrmep
, ef88120
, 2, (RF
, RF_IF
), rd_rm
),
15192 cCL(nrmem
, ef88140
, 2, (RF
, RF_IF
), rd_rm
),
15193 cCL(nrmez
, ef88160
, 2, (RF
, RF_IF
), rd_rm
),
15195 cCL(adfs
, e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15196 cCL(adfsp
, e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15197 cCL(adfsm
, e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15198 cCL(adfsz
, e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15199 cCL(adfd
, e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15200 cCL(adfdp
, e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15201 cCL(adfdm
, e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15202 cCL(adfdz
, e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15203 cCL(adfe
, e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15204 cCL(adfep
, e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15205 cCL(adfem
, e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15206 cCL(adfez
, e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15208 cCL(sufs
, e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15209 cCL(sufsp
, e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15210 cCL(sufsm
, e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15211 cCL(sufsz
, e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15212 cCL(sufd
, e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15213 cCL(sufdp
, e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15214 cCL(sufdm
, e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15215 cCL(sufdz
, e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15216 cCL(sufe
, e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15217 cCL(sufep
, e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15218 cCL(sufem
, e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15219 cCL(sufez
, e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15221 cCL(rsfs
, e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15222 cCL(rsfsp
, e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15223 cCL(rsfsm
, e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15224 cCL(rsfsz
, e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15225 cCL(rsfd
, e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15226 cCL(rsfdp
, e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15227 cCL(rsfdm
, e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15228 cCL(rsfdz
, e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15229 cCL(rsfe
, e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15230 cCL(rsfep
, e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15231 cCL(rsfem
, e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15232 cCL(rsfez
, e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15234 cCL(mufs
, e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15235 cCL(mufsp
, e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15236 cCL(mufsm
, e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15237 cCL(mufsz
, e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15238 cCL(mufd
, e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15239 cCL(mufdp
, e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15240 cCL(mufdm
, e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15241 cCL(mufdz
, e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15242 cCL(mufe
, e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15243 cCL(mufep
, e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15244 cCL(mufem
, e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15245 cCL(mufez
, e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15247 cCL(dvfs
, e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15248 cCL(dvfsp
, e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15249 cCL(dvfsm
, e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15250 cCL(dvfsz
, e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15251 cCL(dvfd
, e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15252 cCL(dvfdp
, e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15253 cCL(dvfdm
, e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15254 cCL(dvfdz
, e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15255 cCL(dvfe
, e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15256 cCL(dvfep
, e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15257 cCL(dvfem
, e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15258 cCL(dvfez
, e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15260 cCL(rdfs
, e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15261 cCL(rdfsp
, e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15262 cCL(rdfsm
, e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15263 cCL(rdfsz
, e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15264 cCL(rdfd
, e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15265 cCL(rdfdp
, e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15266 cCL(rdfdm
, e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15267 cCL(rdfdz
, e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15268 cCL(rdfe
, e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15269 cCL(rdfep
, e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15270 cCL(rdfem
, e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15271 cCL(rdfez
, e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15273 cCL(pows
, e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15274 cCL(powsp
, e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15275 cCL(powsm
, e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15276 cCL(powsz
, e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15277 cCL(powd
, e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15278 cCL(powdp
, e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15279 cCL(powdm
, e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15280 cCL(powdz
, e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15281 cCL(powe
, e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15282 cCL(powep
, e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15283 cCL(powem
, e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15284 cCL(powez
, e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15286 cCL(rpws
, e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15287 cCL(rpwsp
, e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15288 cCL(rpwsm
, e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15289 cCL(rpwsz
, e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15290 cCL(rpwd
, e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15291 cCL(rpwdp
, e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15292 cCL(rpwdm
, e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15293 cCL(rpwdz
, e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15294 cCL(rpwe
, e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15295 cCL(rpwep
, e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15296 cCL(rpwem
, e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15297 cCL(rpwez
, e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15299 cCL(rmfs
, e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15300 cCL(rmfsp
, e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15301 cCL(rmfsm
, e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15302 cCL(rmfsz
, e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15303 cCL(rmfd
, e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15304 cCL(rmfdp
, e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15305 cCL(rmfdm
, e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15306 cCL(rmfdz
, e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15307 cCL(rmfe
, e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15308 cCL(rmfep
, e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15309 cCL(rmfem
, e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15310 cCL(rmfez
, e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15312 cCL(fmls
, e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15313 cCL(fmlsp
, e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15314 cCL(fmlsm
, e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15315 cCL(fmlsz
, e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15316 cCL(fmld
, e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15317 cCL(fmldp
, e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15318 cCL(fmldm
, e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15319 cCL(fmldz
, e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15320 cCL(fmle
, e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15321 cCL(fmlep
, e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15322 cCL(fmlem
, e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15323 cCL(fmlez
, e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15325 cCL(fdvs
, ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15326 cCL(fdvsp
, ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15327 cCL(fdvsm
, ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15328 cCL(fdvsz
, ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15329 cCL(fdvd
, ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15330 cCL(fdvdp
, ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15331 cCL(fdvdm
, ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15332 cCL(fdvdz
, ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15333 cCL(fdve
, ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15334 cCL(fdvep
, ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15335 cCL(fdvem
, ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15336 cCL(fdvez
, ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15338 cCL(frds
, eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15339 cCL(frdsp
, eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15340 cCL(frdsm
, eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15341 cCL(frdsz
, eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15342 cCL(frdd
, eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15343 cCL(frddp
, eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15344 cCL(frddm
, eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15345 cCL(frddz
, eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15346 cCL(frde
, eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15347 cCL(frdep
, eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15348 cCL(frdem
, eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15349 cCL(frdez
, eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15351 cCL(pols
, ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15352 cCL(polsp
, ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15353 cCL(polsm
, ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15354 cCL(polsz
, ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15355 cCL(pold
, ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15356 cCL(poldp
, ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15357 cCL(poldm
, ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15358 cCL(poldz
, ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15359 cCL(pole
, ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15360 cCL(polep
, ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15361 cCL(polem
, ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15362 cCL(polez
, ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15364 cCE(cmf
, e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15365 C3E(cmfe
, ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15366 cCE(cnf
, eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15367 C3E(cnfe
, ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15369 cCL(flts
, e000110
, 2, (RF
, RR
), rn_rd
),
15370 cCL(fltsp
, e000130
, 2, (RF
, RR
), rn_rd
),
15371 cCL(fltsm
, e000150
, 2, (RF
, RR
), rn_rd
),
15372 cCL(fltsz
, e000170
, 2, (RF
, RR
), rn_rd
),
15373 cCL(fltd
, e000190
, 2, (RF
, RR
), rn_rd
),
15374 cCL(fltdp
, e0001b0
, 2, (RF
, RR
), rn_rd
),
15375 cCL(fltdm
, e0001d0
, 2, (RF
, RR
), rn_rd
),
15376 cCL(fltdz
, e0001f0
, 2, (RF
, RR
), rn_rd
),
15377 cCL(flte
, e080110
, 2, (RF
, RR
), rn_rd
),
15378 cCL(fltep
, e080130
, 2, (RF
, RR
), rn_rd
),
15379 cCL(fltem
, e080150
, 2, (RF
, RR
), rn_rd
),
15380 cCL(fltez
, e080170
, 2, (RF
, RR
), rn_rd
),
15382 /* The implementation of the FIX instruction is broken on some
15383 assemblers, in that it accepts a precision specifier as well as a
15384 rounding specifier, despite the fact that this is meaningless.
15385 To be more compatible, we accept it as well, though of course it
15386 does not set any bits. */
15387 cCE(fix
, e100110
, 2, (RR
, RF
), rd_rm
),
15388 cCL(fixp
, e100130
, 2, (RR
, RF
), rd_rm
),
15389 cCL(fixm
, e100150
, 2, (RR
, RF
), rd_rm
),
15390 cCL(fixz
, e100170
, 2, (RR
, RF
), rd_rm
),
15391 cCL(fixsp
, e100130
, 2, (RR
, RF
), rd_rm
),
15392 cCL(fixsm
, e100150
, 2, (RR
, RF
), rd_rm
),
15393 cCL(fixsz
, e100170
, 2, (RR
, RF
), rd_rm
),
15394 cCL(fixdp
, e100130
, 2, (RR
, RF
), rd_rm
),
15395 cCL(fixdm
, e100150
, 2, (RR
, RF
), rd_rm
),
15396 cCL(fixdz
, e100170
, 2, (RR
, RF
), rd_rm
),
15397 cCL(fixep
, e100130
, 2, (RR
, RF
), rd_rm
),
15398 cCL(fixem
, e100150
, 2, (RR
, RF
), rd_rm
),
15399 cCL(fixez
, e100170
, 2, (RR
, RF
), rd_rm
),
15401 /* Instructions that were new with the real FPA, call them V2. */
15403 #define ARM_VARIANT &fpu_fpa_ext_v2
15404 cCE(lfm
, c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15405 cCL(lfmfd
, c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15406 cCL(lfmea
, d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15407 cCE(sfm
, c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15408 cCL(sfmfd
, d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15409 cCL(sfmea
, c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15412 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
15413 /* Moves and type conversions. */
15414 cCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15415 cCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
15416 cCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
15417 cCE(fmstat
, ef1fa10
, 0, (), noargs
),
15418 cCE(fsitos
, eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15419 cCE(fuitos
, eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15420 cCE(ftosis
, ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15421 cCE(ftosizs
, ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15422 cCE(ftouis
, ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15423 cCE(ftouizs
, ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15424 cCE(fmrx
, ef00a10
, 2, (RR
, RVC
), rd_rn
),
15425 cCE(fmxr
, ee00a10
, 2, (RVC
, RR
), rn_rd
),
15427 /* Memory operations. */
15428 cCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15429 cCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15430 cCE(fldmias
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15431 cCE(fldmfds
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15432 cCE(fldmdbs
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15433 cCE(fldmeas
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15434 cCE(fldmiax
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15435 cCE(fldmfdx
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15436 cCE(fldmdbx
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15437 cCE(fldmeax
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15438 cCE(fstmias
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15439 cCE(fstmeas
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15440 cCE(fstmdbs
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15441 cCE(fstmfds
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15442 cCE(fstmiax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15443 cCE(fstmeax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15444 cCE(fstmdbx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15445 cCE(fstmfdx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15447 /* Monadic operations. */
15448 cCE(fabss
, eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15449 cCE(fnegs
, eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15450 cCE(fsqrts
, eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15452 /* Dyadic operations. */
15453 cCE(fadds
, e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15454 cCE(fsubs
, e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15455 cCE(fmuls
, e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15456 cCE(fdivs
, e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15457 cCE(fmacs
, e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15458 cCE(fmscs
, e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15459 cCE(fnmuls
, e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15460 cCE(fnmacs
, e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15461 cCE(fnmscs
, e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15464 cCE(fcmps
, eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15465 cCE(fcmpzs
, eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
15466 cCE(fcmpes
, eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15467 cCE(fcmpezs
, eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
15470 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
15471 /* Moves and type conversions. */
15472 cCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15473 cCE(fcvtds
, eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15474 cCE(fcvtsd
, eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15475 cCE(fmdhr
, e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15476 cCE(fmdlr
, e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15477 cCE(fmrdh
, e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15478 cCE(fmrdl
, e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15479 cCE(fsitod
, eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15480 cCE(fuitod
, eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15481 cCE(ftosid
, ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15482 cCE(ftosizd
, ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15483 cCE(ftouid
, ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15484 cCE(ftouizd
, ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15486 /* Memory operations. */
15487 cCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15488 cCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15489 cCE(fldmiad
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15490 cCE(fldmfdd
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15491 cCE(fldmdbd
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15492 cCE(fldmead
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15493 cCE(fstmiad
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15494 cCE(fstmead
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15495 cCE(fstmdbd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15496 cCE(fstmfdd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15498 /* Monadic operations. */
15499 cCE(fabsd
, eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15500 cCE(fnegd
, eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15501 cCE(fsqrtd
, eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15503 /* Dyadic operations. */
15504 cCE(faddd
, e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15505 cCE(fsubd
, e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15506 cCE(fmuld
, e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15507 cCE(fdivd
, e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15508 cCE(fmacd
, e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15509 cCE(fmscd
, e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15510 cCE(fnmuld
, e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15511 cCE(fnmacd
, e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15512 cCE(fnmscd
, e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15515 cCE(fcmpd
, eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15516 cCE(fcmpzd
, eb50b40
, 1, (RVD
), vfp_dp_rd
),
15517 cCE(fcmped
, eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15518 cCE(fcmpezd
, eb50bc0
, 1, (RVD
), vfp_dp_rd
),
15521 #define ARM_VARIANT &fpu_vfp_ext_v2
15522 cCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
15523 cCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
15524 cCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
15525 cCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
15527 /* Instructions which may belong to either the Neon or VFP instruction sets.
15528 Individual encoder functions perform additional architecture checks. */
15530 #define ARM_VARIANT &fpu_vfp_ext_v1xd
15531 #undef THUMB_VARIANT
15532 #define THUMB_VARIANT &fpu_vfp_ext_v1xd
15533 /* These mnemonics are unique to VFP. */
15534 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
15535 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
15536 nCE(vnmul
, vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15537 nCE(vnmla
, vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15538 nCE(vnmls
, vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15539 nCE(vcmp
, vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15540 nCE(vcmpe
, vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15541 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
15542 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
15543 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
15545 /* Mnemonics shared by Neon and VFP. */
15546 nCEF(vmul
, vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
15547 nCEF(vmla
, vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15548 nCEF(vmls
, vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15550 nCEF(vadd
, vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15551 nCEF(vsub
, vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15553 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15554 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15556 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15557 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15558 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15559 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15560 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15561 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15562 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15563 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15565 nCEF(vcvt
, vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
15567 /* NOTE: All VMOV encoding is special-cased! */
15568 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
15569 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
15571 #undef THUMB_VARIANT
15572 #define THUMB_VARIANT &fpu_neon_ext_v1
15574 #define ARM_VARIANT &fpu_neon_ext_v1
15575 /* Data processing with three registers of the same length. */
15576 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
15577 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
15578 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
15579 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15580 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15581 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15582 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15583 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15584 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15585 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
15586 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15587 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15588 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15589 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15590 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15591 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15592 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15593 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15594 /* If not immediate, fall back to neon_dyadic_i64_su.
15595 shl_imm should accept I8 I16 I32 I64,
15596 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
15597 nUF(vshl
, vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
15598 nUF(vshlq
, vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
15599 nUF(vqshl
, vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
15600 nUF(vqshlq
, vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
15601 /* Logic ops, types optional & ignored. */
15602 nUF(vand
, vand
, 2, (RNDQ
, NILO
), neon_logic
),
15603 nUF(vandq
, vand
, 2, (RNQ
, NILO
), neon_logic
),
15604 nUF(vbic
, vbic
, 2, (RNDQ
, NILO
), neon_logic
),
15605 nUF(vbicq
, vbic
, 2, (RNQ
, NILO
), neon_logic
),
15606 nUF(vorr
, vorr
, 2, (RNDQ
, NILO
), neon_logic
),
15607 nUF(vorrq
, vorr
, 2, (RNQ
, NILO
), neon_logic
),
15608 nUF(vorn
, vorn
, 2, (RNDQ
, NILO
), neon_logic
),
15609 nUF(vornq
, vorn
, 2, (RNQ
, NILO
), neon_logic
),
15610 nUF(veor
, veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
15611 nUF(veorq
, veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
15612 /* Bitfield ops, untyped. */
15613 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15614 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15615 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15616 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15617 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15618 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15619 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
15620 nUF(vabd
, vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15621 nUF(vabdq
, vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15622 nUF(vmax
, vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15623 nUF(vmaxq
, vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15624 nUF(vmin
, vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15625 nUF(vminq
, vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15626 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
15627 back to neon_dyadic_if_su. */
15628 nUF(vcge
, vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
15629 nUF(vcgeq
, vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
15630 nUF(vcgt
, vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
15631 nUF(vcgtq
, vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
15632 nUF(vclt
, vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
15633 nUF(vcltq
, vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
15634 nUF(vcle
, vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
15635 nUF(vcleq
, vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
15636 /* Comparison. Type I8 I16 I32 F32. */
15637 nUF(vceq
, vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
15638 nUF(vceqq
, vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
15639 /* As above, D registers only. */
15640 nUF(vpmax
, vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
15641 nUF(vpmin
, vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
15642 /* Int and float variants, signedness unimportant. */
15643 nUF(vmlaq
, vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
15644 nUF(vmlsq
, vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
15645 nUF(vpadd
, vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
15646 /* Add/sub take types I8 I16 I32 I64 F32. */
15647 nUF(vaddq
, vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
15648 nUF(vsubq
, vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
15649 /* vtst takes sizes 8, 16, 32. */
15650 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
15651 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
15652 /* VMUL takes I8 I16 I32 F32 P8. */
15653 nUF(vmulq
, vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
15654 /* VQD{R}MULH takes S16 S32. */
15655 nUF(vqdmulh
, vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
15656 nUF(vqdmulhq
, vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
15657 nUF(vqrdmulh
, vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
15658 nUF(vqrdmulhq
, vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
15659 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
15660 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
15661 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
15662 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
15663 NUF(vaclt
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
15664 NUF(vacltq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
15665 NUF(vacle
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
15666 NUF(vacleq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
15667 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
15668 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
15669 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
15670 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
15672 /* Two address, int/float. Types S8 S16 S32 F32. */
15673 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
15674 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
15676 /* Data processing with two registers and a shift amount. */
15677 /* Right shifts, and variants with rounding.
15678 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
15679 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
15680 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
15681 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
15682 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
15683 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
15684 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
15685 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
15686 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
15687 /* Shift and insert. Sizes accepted 8 16 32 64. */
15688 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
15689 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
15690 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
15691 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
15692 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
15693 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
15694 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
15695 /* Right shift immediate, saturating & narrowing, with rounding variants.
15696 Types accepted S16 S32 S64 U16 U32 U64. */
15697 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
15698 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
15699 /* As above, unsigned. Types accepted S16 S32 S64. */
15700 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
15701 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
15702 /* Right shift narrowing. Types accepted I16 I32 I64. */
15703 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
15704 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
15705 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
15706 nUF(vshll
, vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
15707 /* CVT with optional immediate for fixed-point variant. */
15708 nUF(vcvtq
, vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
15710 nUF(vmvn
, vmvn
, 2, (RNDQ
, RNDQ_IMVNb
), neon_mvn
),
15711 nUF(vmvnq
, vmvn
, 2, (RNQ
, RNDQ_IMVNb
), neon_mvn
),
15713 /* Data processing, three registers of different lengths. */
15714 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
15715 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
15716 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
15717 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
15718 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
15719 /* If not scalar, fall back to neon_dyadic_long.
15720 Vector types as above, scalar types S16 S32 U16 U32. */
15721 nUF(vmlal
, vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
15722 nUF(vmlsl
, vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
15723 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
15724 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
15725 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
15726 /* Dyadic, narrowing insns. Types I16 I32 I64. */
15727 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15728 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15729 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15730 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15731 /* Saturating doubling multiplies. Types S16 S32. */
15732 nUF(vqdmlal
, vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
15733 nUF(vqdmlsl
, vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
15734 nUF(vqdmull
, vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
15735 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
15736 S16 S32 U16 U32. */
15737 nUF(vmull
, vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
15739 /* Extract. Size 8. */
15740 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I7
), neon_ext
),
15741 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I7
), neon_ext
),
15743 /* Two registers, miscellaneous. */
15744 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
15745 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
15746 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
15747 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
15748 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
15749 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
15750 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
15751 /* Vector replicate. Sizes 8 16 32. */
15752 nCE(vdup
, vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
15753 nCE(vdupq
, vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
15754 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
15755 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
15756 /* VMOVN. Types I16 I32 I64. */
15757 nUF(vmovn
, vmovn
, 2, (RND
, RNQ
), neon_movn
),
15758 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
15759 nUF(vqmovn
, vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
15760 /* VQMOVUN. Types S16 S32 S64. */
15761 nUF(vqmovun
, vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
15762 /* VZIP / VUZP. Sizes 8 16 32. */
15763 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
15764 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
15765 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
15766 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
15767 /* VQABS / VQNEG. Types S8 S16 S32. */
15768 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
15769 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
15770 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
15771 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
15772 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
15773 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
15774 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
15775 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
15776 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
15777 /* Reciprocal estimates. Types U32 F32. */
15778 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
15779 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
15780 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
15781 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
15782 /* VCLS. Types S8 S16 S32. */
15783 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
15784 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
15785 /* VCLZ. Types I8 I16 I32. */
15786 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
15787 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
15788 /* VCNT. Size 8. */
15789 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
15790 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
15791 /* Two address, untyped. */
15792 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
15793 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
15794 /* VTRN. Sizes 8 16 32. */
15795 nUF(vtrn
, vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
15796 nUF(vtrnq
, vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
15798 /* Table lookup. Size 8. */
15799 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
15800 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
15802 #undef THUMB_VARIANT
15803 #define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
15805 #define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
15806 /* Neon element/structure load/store. */
15807 nUF(vld1
, vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15808 nUF(vst1
, vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15809 nUF(vld2
, vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15810 nUF(vst2
, vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15811 nUF(vld3
, vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15812 nUF(vst3
, vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15813 nUF(vld4
, vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15814 nUF(vst4
, vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15816 #undef THUMB_VARIANT
15817 #define THUMB_VARIANT &fpu_vfp_ext_v3
15819 #define ARM_VARIANT &fpu_vfp_ext_v3
15820 cCE(fconsts
, eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
15821 cCE(fconstd
, eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
15822 cCE(fshtos
, eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15823 cCE(fshtod
, eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15824 cCE(fsltos
, eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15825 cCE(fsltod
, eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15826 cCE(fuhtos
, ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15827 cCE(fuhtod
, ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15828 cCE(fultos
, ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15829 cCE(fultod
, ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15830 cCE(ftoshs
, ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15831 cCE(ftoshd
, ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15832 cCE(ftosls
, ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15833 cCE(ftosld
, ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15834 cCE(ftouhs
, ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15835 cCE(ftouhd
, ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15836 cCE(ftouls
, ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15837 cCE(ftould
, ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15839 #undef THUMB_VARIANT
15841 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
15842 cCE(mia
, e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15843 cCE(miaph
, e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15844 cCE(miabb
, e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15845 cCE(miabt
, e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15846 cCE(miatb
, e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15847 cCE(miatt
, e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15848 cCE(mar
, c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
15849 cCE(mra
, c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
15852 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
15853 cCE(tandcb
, e13f130
, 1, (RR
), iwmmxt_tandorc
),
15854 cCE(tandch
, e53f130
, 1, (RR
), iwmmxt_tandorc
),
15855 cCE(tandcw
, e93f130
, 1, (RR
), iwmmxt_tandorc
),
15856 cCE(tbcstb
, e400010
, 2, (RIWR
, RR
), rn_rd
),
15857 cCE(tbcsth
, e400050
, 2, (RIWR
, RR
), rn_rd
),
15858 cCE(tbcstw
, e400090
, 2, (RIWR
, RR
), rn_rd
),
15859 cCE(textrcb
, e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
15860 cCE(textrch
, e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
15861 cCE(textrcw
, e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
15862 cCE(textrmub
, e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15863 cCE(textrmuh
, e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15864 cCE(textrmuw
, e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15865 cCE(textrmsb
, e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15866 cCE(textrmsh
, e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15867 cCE(textrmsw
, e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15868 cCE(tinsrb
, e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
15869 cCE(tinsrh
, e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
15870 cCE(tinsrw
, e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
15871 cCE(tmcr
, e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
15872 cCE(tmcrr
, c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
15873 cCE(tmia
, e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15874 cCE(tmiaph
, e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15875 cCE(tmiabb
, e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15876 cCE(tmiabt
, e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15877 cCE(tmiatb
, e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15878 cCE(tmiatt
, e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15879 cCE(tmovmskb
, e100030
, 2, (RR
, RIWR
), rd_rn
),
15880 cCE(tmovmskh
, e500030
, 2, (RR
, RIWR
), rd_rn
),
15881 cCE(tmovmskw
, e900030
, 2, (RR
, RIWR
), rd_rn
),
15882 cCE(tmrc
, e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
15883 cCE(tmrrc
, c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
15884 cCE(torcb
, e13f150
, 1, (RR
), iwmmxt_tandorc
),
15885 cCE(torch
, e53f150
, 1, (RR
), iwmmxt_tandorc
),
15886 cCE(torcw
, e93f150
, 1, (RR
), iwmmxt_tandorc
),
15887 cCE(waccb
, e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
15888 cCE(wacch
, e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
15889 cCE(waccw
, e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
15890 cCE(waddbss
, e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15891 cCE(waddb
, e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15892 cCE(waddbus
, e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15893 cCE(waddhss
, e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15894 cCE(waddh
, e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15895 cCE(waddhus
, e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15896 cCE(waddwss
, eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15897 cCE(waddw
, e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15898 cCE(waddwus
, e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15899 cCE(waligni
, e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
15900 cCE(walignr0
, e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15901 cCE(walignr1
, e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15902 cCE(walignr2
, ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15903 cCE(walignr3
, eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15904 cCE(wand
, e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15905 cCE(wandn
, e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15906 cCE(wavg2b
, e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15907 cCE(wavg2br
, e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15908 cCE(wavg2h
, ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15909 cCE(wavg2hr
, ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15910 cCE(wcmpeqb
, e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15911 cCE(wcmpeqh
, e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15912 cCE(wcmpeqw
, e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15913 cCE(wcmpgtub
, e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15914 cCE(wcmpgtuh
, e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15915 cCE(wcmpgtuw
, e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15916 cCE(wcmpgtsb
, e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15917 cCE(wcmpgtsh
, e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15918 cCE(wcmpgtsw
, eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15919 cCE(wldrb
, c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
15920 cCE(wldrh
, c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
15921 cCE(wldrw
, c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
15922 cCE(wldrd
, c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
15923 cCE(wmacs
, e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15924 cCE(wmacsz
, e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15925 cCE(wmacu
, e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15926 cCE(wmacuz
, e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15927 cCE(wmadds
, ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15928 cCE(wmaddu
, e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15929 cCE(wmaxsb
, e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15930 cCE(wmaxsh
, e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15931 cCE(wmaxsw
, ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15932 cCE(wmaxub
, e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15933 cCE(wmaxuh
, e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15934 cCE(wmaxuw
, e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15935 cCE(wminsb
, e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15936 cCE(wminsh
, e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15937 cCE(wminsw
, eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15938 cCE(wminub
, e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15939 cCE(wminuh
, e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15940 cCE(wminuw
, e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15941 cCE(wmov
, e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
15942 cCE(wmulsm
, e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15943 cCE(wmulsl
, e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15944 cCE(wmulum
, e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15945 cCE(wmulul
, e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15946 cCE(wor
, e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15947 cCE(wpackhss
, e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15948 cCE(wpackhus
, e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15949 cCE(wpackwss
, eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15950 cCE(wpackwus
, e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15951 cCE(wpackdss
, ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15952 cCE(wpackdus
, ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15953 cCE(wrorh
, e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
15954 cCE(wrorhg
, e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15955 cCE(wrorw
, eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
15956 cCE(wrorwg
, eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15957 cCE(wrord
, ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
15958 cCE(wrordg
, ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15959 cCE(wsadb
, e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15960 cCE(wsadbz
, e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15961 cCE(wsadh
, e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15962 cCE(wsadhz
, e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15963 cCE(wshufh
, e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
15964 cCE(wsllh
, e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
15965 cCE(wsllhg
, e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15966 cCE(wsllw
, e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
15967 cCE(wsllwg
, e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15968 cCE(wslld
, ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
15969 cCE(wslldg
, ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15970 cCE(wsrah
, e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
15971 cCE(wsrahg
, e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15972 cCE(wsraw
, e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
15973 cCE(wsrawg
, e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15974 cCE(wsrad
, ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
15975 cCE(wsradg
, ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15976 cCE(wsrlh
, e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
15977 cCE(wsrlhg
, e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15978 cCE(wsrlw
, ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
15979 cCE(wsrlwg
, ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15980 cCE(wsrld
, ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
15981 cCE(wsrldg
, ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15982 cCE(wstrb
, c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
15983 cCE(wstrh
, c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
15984 cCE(wstrw
, c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
15985 cCE(wstrd
, c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
15986 cCE(wsubbss
, e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15987 cCE(wsubb
, e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15988 cCE(wsubbus
, e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15989 cCE(wsubhss
, e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15990 cCE(wsubh
, e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15991 cCE(wsubhus
, e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15992 cCE(wsubwss
, eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15993 cCE(wsubw
, e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15994 cCE(wsubwus
, e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15995 cCE(wunpckehub
,e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15996 cCE(wunpckehuh
,e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15997 cCE(wunpckehuw
,e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15998 cCE(wunpckehsb
,e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15999 cCE(wunpckehsh
,e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16000 cCE(wunpckehsw
,ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16001 cCE(wunpckihb
, e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16002 cCE(wunpckihh
, e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16003 cCE(wunpckihw
, e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16004 cCE(wunpckelub
,e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16005 cCE(wunpckeluh
,e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16006 cCE(wunpckeluw
,e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16007 cCE(wunpckelsb
,e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16008 cCE(wunpckelsh
,e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16009 cCE(wunpckelsw
,ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16010 cCE(wunpckilb
, e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16011 cCE(wunpckilh
, e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16012 cCE(wunpckilw
, e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16013 cCE(wxor
, e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16014 cCE(wzero
, e300000
, 1, (RIWR
), iwmmxt_wzero
),
16017 #define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
16018 cCE(torvscb
, e13f190
, 1, (RR
), iwmmxt_tandorc
),
16019 cCE(torvsch
, e53f190
, 1, (RR
), iwmmxt_tandorc
),
16020 cCE(torvscw
, e93f190
, 1, (RR
), iwmmxt_tandorc
),
16021 cCE(wabsb
, e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16022 cCE(wabsh
, e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16023 cCE(wabsw
, ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16024 cCE(wabsdiffb
, e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16025 cCE(wabsdiffh
, e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16026 cCE(wabsdiffw
, e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16027 cCE(waddbhusl
, e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16028 cCE(waddbhusm
, e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16029 cCE(waddhc
, e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16030 cCE(waddwc
, ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16031 cCE(waddsubhx
, ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16032 cCE(wavg4
, e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16033 cCE(wavg4r
, e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16034 cCE(wmaddsn
, ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16035 cCE(wmaddsx
, eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16036 cCE(wmaddun
, ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16037 cCE(wmaddux
, e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16038 cCE(wmerge
, e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
16039 cCE(wmiabb
, e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16040 cCE(wmiabt
, e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16041 cCE(wmiatb
, e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16042 cCE(wmiatt
, e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16043 cCE(wmiabbn
, e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16044 cCE(wmiabtn
, e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16045 cCE(wmiatbn
, e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16046 cCE(wmiattn
, e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16047 cCE(wmiawbb
, e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16048 cCE(wmiawbt
, e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16049 cCE(wmiawtb
, ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16050 cCE(wmiawtt
, eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16051 cCE(wmiawbbn
, ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16052 cCE(wmiawbtn
, ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16053 cCE(wmiawtbn
, ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16054 cCE(wmiawttn
, ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16055 cCE(wmulsmr
, ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16056 cCE(wmulumr
, ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16057 cCE(wmulwumr
, ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16058 cCE(wmulwsmr
, ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16059 cCE(wmulwum
, ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16060 cCE(wmulwsm
, ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16061 cCE(wmulwl
, eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16062 cCE(wqmiabb
, e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16063 cCE(wqmiabt
, e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16064 cCE(wqmiatb
, ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16065 cCE(wqmiatt
, eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16066 cCE(wqmiabbn
, ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16067 cCE(wqmiabtn
, ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16068 cCE(wqmiatbn
, ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16069 cCE(wqmiattn
, ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16070 cCE(wqmulm
, e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16071 cCE(wqmulmr
, e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16072 cCE(wqmulwm
, ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16073 cCE(wqmulwmr
, ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16074 cCE(wsubaddhx
, ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16077 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
16078 cCE(cfldrs
, c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
16079 cCE(cfldrd
, c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
16080 cCE(cfldr32
, c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
16081 cCE(cfldr64
, c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
16082 cCE(cfstrs
, c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
16083 cCE(cfstrd
, c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
16084 cCE(cfstr32
, c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
16085 cCE(cfstr64
, c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
16086 cCE(cfmvsr
, e000450
, 2, (RMF
, RR
), rn_rd
),
16087 cCE(cfmvrs
, e100450
, 2, (RR
, RMF
), rd_rn
),
16088 cCE(cfmvdlr
, e000410
, 2, (RMD
, RR
), rn_rd
),
16089 cCE(cfmvrdl
, e100410
, 2, (RR
, RMD
), rd_rn
),
16090 cCE(cfmvdhr
, e000430
, 2, (RMD
, RR
), rn_rd
),
16091 cCE(cfmvrdh
, e100430
, 2, (RR
, RMD
), rd_rn
),
16092 cCE(cfmv64lr
, e000510
, 2, (RMDX
, RR
), rn_rd
),
16093 cCE(cfmvr64l
, e100510
, 2, (RR
, RMDX
), rd_rn
),
16094 cCE(cfmv64hr
, e000530
, 2, (RMDX
, RR
), rn_rd
),
16095 cCE(cfmvr64h
, e100530
, 2, (RR
, RMDX
), rd_rn
),
16096 cCE(cfmval32
, e200440
, 2, (RMAX
, RMFX
), rd_rn
),
16097 cCE(cfmv32al
, e100440
, 2, (RMFX
, RMAX
), rd_rn
),
16098 cCE(cfmvam32
, e200460
, 2, (RMAX
, RMFX
), rd_rn
),
16099 cCE(cfmv32am
, e100460
, 2, (RMFX
, RMAX
), rd_rn
),
16100 cCE(cfmvah32
, e200480
, 2, (RMAX
, RMFX
), rd_rn
),
16101 cCE(cfmv32ah
, e100480
, 2, (RMFX
, RMAX
), rd_rn
),
16102 cCE(cfmva32
, e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
16103 cCE(cfmv32a
, e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
16104 cCE(cfmva64
, e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
16105 cCE(cfmv64a
, e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
16106 cCE(cfmvsc32
, e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
16107 cCE(cfmv32sc
, e1004e0
, 2, (RMDX
, RMDS
), rd
),
16108 cCE(cfcpys
, e000400
, 2, (RMF
, RMF
), rd_rn
),
16109 cCE(cfcpyd
, e000420
, 2, (RMD
, RMD
), rd_rn
),
16110 cCE(cfcvtsd
, e000460
, 2, (RMD
, RMF
), rd_rn
),
16111 cCE(cfcvtds
, e000440
, 2, (RMF
, RMD
), rd_rn
),
16112 cCE(cfcvt32s
, e000480
, 2, (RMF
, RMFX
), rd_rn
),
16113 cCE(cfcvt32d
, e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
16114 cCE(cfcvt64s
, e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
16115 cCE(cfcvt64d
, e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
16116 cCE(cfcvts32
, e100580
, 2, (RMFX
, RMF
), rd_rn
),
16117 cCE(cfcvtd32
, e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
16118 cCE(cftruncs32
,e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
16119 cCE(cftruncd32
,e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
16120 cCE(cfrshl32
, e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
16121 cCE(cfrshl64
, e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
16122 cCE(cfsh32
, e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
16123 cCE(cfsh64
, e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
16124 cCE(cfcmps
, e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
16125 cCE(cfcmpd
, e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
16126 cCE(cfcmp32
, e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
16127 cCE(cfcmp64
, e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
16128 cCE(cfabss
, e300400
, 2, (RMF
, RMF
), rd_rn
),
16129 cCE(cfabsd
, e300420
, 2, (RMD
, RMD
), rd_rn
),
16130 cCE(cfnegs
, e300440
, 2, (RMF
, RMF
), rd_rn
),
16131 cCE(cfnegd
, e300460
, 2, (RMD
, RMD
), rd_rn
),
16132 cCE(cfadds
, e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16133 cCE(cfaddd
, e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16134 cCE(cfsubs
, e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16135 cCE(cfsubd
, e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16136 cCE(cfmuls
, e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16137 cCE(cfmuld
, e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16138 cCE(cfabs32
, e300500
, 2, (RMFX
, RMFX
), rd_rn
),
16139 cCE(cfabs64
, e300520
, 2, (RMDX
, RMDX
), rd_rn
),
16140 cCE(cfneg32
, e300540
, 2, (RMFX
, RMFX
), rd_rn
),
16141 cCE(cfneg64
, e300560
, 2, (RMDX
, RMDX
), rd_rn
),
16142 cCE(cfadd32
, e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16143 cCE(cfadd64
, e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16144 cCE(cfsub32
, e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16145 cCE(cfsub64
, e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16146 cCE(cfmul32
, e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16147 cCE(cfmul64
, e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16148 cCE(cfmac32
, e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16149 cCE(cfmsc32
, e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16150 cCE(cfmadd32
, e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
16151 cCE(cfmsub32
, e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
16152 cCE(cfmadda32
, e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
16153 cCE(cfmsuba32
, e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
16156 #undef THUMB_VARIANT
16183 /* MD interface: bits in the object file. */
16185 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
16186 for use in the a.out file, and stores them in the array pointed to by buf.
16187 This knows about the endian-ness of the target machine and does
16188 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
16189 2 (short) and 4 (long) Floating numbers are put out as a series of
16190 LITTLENUMS (shorts, here at least). */
16193 md_number_to_chars (char * buf
, valueT val
, int n
)
16195 if (target_big_endian
)
16196 number_to_chars_bigendian (buf
, val
, n
);
16198 number_to_chars_littleendian (buf
, val
, n
);
16202 md_chars_to_number (char * buf
, int n
)
16205 unsigned char * where
= (unsigned char *) buf
;
16207 if (target_big_endian
)
16212 result
|= (*where
++ & 255);
16220 result
|= (where
[n
] & 255);
16227 /* MD interface: Sections. */
16229 /* Estimate the size of a frag before relaxing. Assume everything fits in
16233 md_estimate_size_before_relax (fragS
* fragp
,
16234 segT segtype ATTRIBUTE_UNUSED
)
16240 /* Convert a machine dependent frag. */
16243 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
16245 unsigned long insn
;
16246 unsigned long old_op
;
16254 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16256 old_op
= bfd_get_16(abfd
, buf
);
16257 if (fragp
->fr_symbol
) {
16258 exp
.X_op
= O_symbol
;
16259 exp
.X_add_symbol
= fragp
->fr_symbol
;
16261 exp
.X_op
= O_constant
;
16263 exp
.X_add_number
= fragp
->fr_offset
;
16264 opcode
= fragp
->fr_subtype
;
16267 case T_MNEM_ldr_pc
:
16268 case T_MNEM_ldr_pc2
:
16269 case T_MNEM_ldr_sp
:
16270 case T_MNEM_str_sp
:
16277 if (fragp
->fr_var
== 4)
16279 insn
= THUMB_OP32(opcode
);
16280 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
16282 insn
|= (old_op
& 0x700) << 4;
16286 insn
|= (old_op
& 7) << 12;
16287 insn
|= (old_op
& 0x38) << 13;
16289 insn
|= 0x00000c00;
16290 put_thumb32_insn (buf
, insn
);
16291 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
16295 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
16297 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
16300 if (fragp
->fr_var
== 4)
16302 insn
= THUMB_OP32 (opcode
);
16303 insn
|= (old_op
& 0xf0) << 4;
16304 put_thumb32_insn (buf
, insn
);
16305 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
16309 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16310 exp
.X_add_number
-= 4;
16318 if (fragp
->fr_var
== 4)
16320 int r0off
= (opcode
== T_MNEM_mov
16321 || opcode
== T_MNEM_movs
) ? 0 : 8;
16322 insn
= THUMB_OP32 (opcode
);
16323 insn
= (insn
& 0xe1ffffff) | 0x10000000;
16324 insn
|= (old_op
& 0x700) << r0off
;
16325 put_thumb32_insn (buf
, insn
);
16326 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16330 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
16335 if (fragp
->fr_var
== 4)
16337 insn
= THUMB_OP32(opcode
);
16338 put_thumb32_insn (buf
, insn
);
16339 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
16342 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
16346 if (fragp
->fr_var
== 4)
16348 insn
= THUMB_OP32(opcode
);
16349 insn
|= (old_op
& 0xf00) << 14;
16350 put_thumb32_insn (buf
, insn
);
16351 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
16354 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
16357 case T_MNEM_add_sp
:
16358 case T_MNEM_add_pc
:
16359 case T_MNEM_inc_sp
:
16360 case T_MNEM_dec_sp
:
16361 if (fragp
->fr_var
== 4)
16363 /* ??? Choose between add and addw. */
16364 insn
= THUMB_OP32 (opcode
);
16365 insn
|= (old_op
& 0xf0) << 4;
16366 put_thumb32_insn (buf
, insn
);
16367 if (opcode
== T_MNEM_add_pc
)
16368 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
16370 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16373 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16381 if (fragp
->fr_var
== 4)
16383 insn
= THUMB_OP32 (opcode
);
16384 insn
|= (old_op
& 0xf0) << 4;
16385 insn
|= (old_op
& 0xf) << 16;
16386 put_thumb32_insn (buf
, insn
);
16387 if (insn
& (1 << 20))
16388 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16390 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16393 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16399 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
16401 fixp
->fx_file
= fragp
->fr_file
;
16402 fixp
->fx_line
= fragp
->fr_line
;
16403 fragp
->fr_fix
+= fragp
->fr_var
;
16406 /* Return the size of a relaxable immediate operand instruction.
16407 SHIFT and SIZE specify the form of the allowable immediate. */
16409 relax_immediate (fragS
*fragp
, int size
, int shift
)
16415 /* ??? Should be able to do better than this. */
16416 if (fragp
->fr_symbol
)
16419 low
= (1 << shift
) - 1;
16420 mask
= (1 << (shift
+ size
)) - (1 << shift
);
16421 offset
= fragp
->fr_offset
;
16422 /* Force misaligned offsets to 32-bit variant. */
16425 if (offset
& ~mask
)
16430 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
16433 relax_adr (fragS
*fragp
, asection
*sec
)
16438 /* Assume worst case for symbols not known to be in the same section. */
16439 if (!S_IS_DEFINED(fragp
->fr_symbol
)
16440 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16443 val
= S_GET_VALUE(fragp
->fr_symbol
) + fragp
->fr_offset
;
16444 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16445 addr
= (addr
+ 4) & ~3;
16446 /* Fix the insn as the 4-byte version if the target address is not
16447 sufficiently aligned. This is prevents an infinite loop when two
16448 instructions have contradictory range/alignment requirements. */
16452 if (val
< 0 || val
> 1020)
16457 /* Return the size of a relaxable add/sub immediate instruction. */
16459 relax_addsub (fragS
*fragp
, asection
*sec
)
16464 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16465 op
= bfd_get_16(sec
->owner
, buf
);
16466 if ((op
& 0xf) == ((op
>> 4) & 0xf))
16467 return relax_immediate (fragp
, 8, 0);
16469 return relax_immediate (fragp
, 3, 0);
16473 /* Return the size of a relaxable branch instruction. BITS is the
16474 size of the offset field in the narrow instruction. */
16477 relax_branch (fragS
*fragp
, asection
*sec
, int bits
)
16483 /* Assume worst case for symbols not known to be in the same section. */
16484 if (!S_IS_DEFINED(fragp
->fr_symbol
)
16485 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16488 val
= S_GET_VALUE(fragp
->fr_symbol
) + fragp
->fr_offset
;
16489 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16492 /* Offset is a signed value *2 */
16494 if (val
>= limit
|| val
< -limit
)
16500 /* Relax a machine dependent frag. This returns the amount by which
16501 the current size of the frag should change. */
16504 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
16509 oldsize
= fragp
->fr_var
;
16510 switch (fragp
->fr_subtype
)
16512 case T_MNEM_ldr_pc2
:
16513 newsize
= relax_adr(fragp
, sec
);
16515 case T_MNEM_ldr_pc
:
16516 case T_MNEM_ldr_sp
:
16517 case T_MNEM_str_sp
:
16518 newsize
= relax_immediate(fragp
, 8, 2);
16522 newsize
= relax_immediate(fragp
, 5, 2);
16526 newsize
= relax_immediate(fragp
, 5, 1);
16530 newsize
= relax_immediate(fragp
, 5, 0);
16533 newsize
= relax_adr(fragp
, sec
);
16539 newsize
= relax_immediate(fragp
, 8, 0);
16542 newsize
= relax_branch(fragp
, sec
, 11);
16545 newsize
= relax_branch(fragp
, sec
, 8);
16547 case T_MNEM_add_sp
:
16548 case T_MNEM_add_pc
:
16549 newsize
= relax_immediate (fragp
, 8, 2);
16551 case T_MNEM_inc_sp
:
16552 case T_MNEM_dec_sp
:
16553 newsize
= relax_immediate (fragp
, 7, 2);
16559 newsize
= relax_addsub (fragp
, sec
);
16566 fragp
->fr_var
= -newsize
;
16567 md_convert_frag (sec
->owner
, sec
, fragp
);
16569 return -(newsize
+ oldsize
);
16571 fragp
->fr_var
= newsize
;
16572 return newsize
- oldsize
;
16575 /* Round up a section size to the appropriate boundary. */
16578 md_section_align (segT segment ATTRIBUTE_UNUSED
,
16581 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
16582 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
16584 /* For a.out, force the section size to be aligned. If we don't do
16585 this, BFD will align it for us, but it will not write out the
16586 final bytes of the section. This may be a bug in BFD, but it is
16587 easier to fix it here since that is how the other a.out targets
16591 align
= bfd_get_section_alignment (stdoutput
, segment
);
16592 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
16599 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
16600 of an rs_align_code fragment. */
16603 arm_handle_align (fragS
* fragP
)
16605 static char const arm_noop
[4] = { 0x00, 0x00, 0xa0, 0xe1 };
16606 static char const thumb_noop
[2] = { 0xc0, 0x46 };
16607 static char const arm_bigend_noop
[4] = { 0xe1, 0xa0, 0x00, 0x00 };
16608 static char const thumb_bigend_noop
[2] = { 0x46, 0xc0 };
16610 int bytes
, fix
, noop_size
;
16614 if (fragP
->fr_type
!= rs_align_code
)
16617 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
16618 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
16621 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
16622 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
16624 if (fragP
->tc_frag_data
)
16626 if (target_big_endian
)
16627 noop
= thumb_bigend_noop
;
16630 noop_size
= sizeof (thumb_noop
);
16634 if (target_big_endian
)
16635 noop
= arm_bigend_noop
;
16638 noop_size
= sizeof (arm_noop
);
16641 if (bytes
& (noop_size
- 1))
16643 fix
= bytes
& (noop_size
- 1);
16644 memset (p
, 0, fix
);
16649 while (bytes
>= noop_size
)
16651 memcpy (p
, noop
, noop_size
);
16653 bytes
-= noop_size
;
16657 fragP
->fr_fix
+= fix
;
16658 fragP
->fr_var
= noop_size
;
16661 /* Called from md_do_align. Used to create an alignment
16662 frag in a code section. */
16665 arm_frag_align_code (int n
, int max
)
16669 /* We assume that there will never be a requirement
16670 to support alignments greater than 32 bytes. */
16671 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
16672 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
16674 p
= frag_var (rs_align_code
,
16675 MAX_MEM_FOR_RS_ALIGN_CODE
,
16677 (relax_substateT
) max
,
16684 /* Perform target specific initialisation of a frag. */
16687 arm_init_frag (fragS
* fragP
)
16689 /* Record whether this frag is in an ARM or a THUMB area. */
16690 fragP
->tc_frag_data
= thumb_mode
;
16694 /* When we change sections we need to issue a new mapping symbol. */
16697 arm_elf_change_section (void)
16700 segment_info_type
*seginfo
;
16702 /* Link an unlinked unwind index table section to the .text section. */
16703 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
16704 && elf_linked_to_section (now_seg
) == NULL
)
16705 elf_linked_to_section (now_seg
) = text_section
;
16707 if (!SEG_NORMAL (now_seg
))
16710 flags
= bfd_get_section_flags (stdoutput
, now_seg
);
16712 /* We can ignore sections that only contain debug info. */
16713 if ((flags
& SEC_ALLOC
) == 0)
16716 seginfo
= seg_info (now_seg
);
16717 mapstate
= seginfo
->tc_segment_info_data
.mapstate
;
16718 marked_pr_dependency
= seginfo
->tc_segment_info_data
.marked_pr_dependency
;
16722 arm_elf_section_type (const char * str
, size_t len
)
16724 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
16725 return SHT_ARM_EXIDX
;
16730 /* Code to deal with unwinding tables. */
16732 static void add_unwind_adjustsp (offsetT
);
16734 /* Cenerate and deferred unwind frame offset. */
16737 flush_pending_unwind (void)
16741 offset
= unwind
.pending_offset
;
16742 unwind
.pending_offset
= 0;
16744 add_unwind_adjustsp (offset
);
16747 /* Add an opcode to this list for this function. Two-byte opcodes should
16748 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
16752 add_unwind_opcode (valueT op
, int length
)
16754 /* Add any deferred stack adjustment. */
16755 if (unwind
.pending_offset
)
16756 flush_pending_unwind ();
16758 unwind
.sp_restored
= 0;
16760 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
16762 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
16763 if (unwind
.opcodes
)
16764 unwind
.opcodes
= xrealloc (unwind
.opcodes
,
16765 unwind
.opcode_alloc
);
16767 unwind
.opcodes
= xmalloc (unwind
.opcode_alloc
);
16772 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
16774 unwind
.opcode_count
++;
16778 /* Add unwind opcodes to adjust the stack pointer. */
16781 add_unwind_adjustsp (offsetT offset
)
16785 if (offset
> 0x200)
16787 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
16792 /* Long form: 0xb2, uleb128. */
16793 /* This might not fit in a word so add the individual bytes,
16794 remembering the list is built in reverse order. */
16795 o
= (valueT
) ((offset
- 0x204) >> 2);
16797 add_unwind_opcode (0, 1);
16799 /* Calculate the uleb128 encoding of the offset. */
16803 bytes
[n
] = o
& 0x7f;
16809 /* Add the insn. */
16811 add_unwind_opcode (bytes
[n
- 1], 1);
16812 add_unwind_opcode (0xb2, 1);
16814 else if (offset
> 0x100)
16816 /* Two short opcodes. */
16817 add_unwind_opcode (0x3f, 1);
16818 op
= (offset
- 0x104) >> 2;
16819 add_unwind_opcode (op
, 1);
16821 else if (offset
> 0)
16823 /* Short opcode. */
16824 op
= (offset
- 4) >> 2;
16825 add_unwind_opcode (op
, 1);
16827 else if (offset
< 0)
16830 while (offset
> 0x100)
16832 add_unwind_opcode (0x7f, 1);
16835 op
= ((offset
- 4) >> 2) | 0x40;
16836 add_unwind_opcode (op
, 1);
16840 /* Finish the list of unwind opcodes for this function. */
16842 finish_unwind_opcodes (void)
16846 if (unwind
.fp_used
)
16848 /* Adjust sp as necessary. */
16849 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
16850 flush_pending_unwind ();
16852 /* After restoring sp from the frame pointer. */
16853 op
= 0x90 | unwind
.fp_reg
;
16854 add_unwind_opcode (op
, 1);
16857 flush_pending_unwind ();
16861 /* Start an exception table entry. If idx is nonzero this is an index table
16865 start_unwind_section (const segT text_seg
, int idx
)
16867 const char * text_name
;
16868 const char * prefix
;
16869 const char * prefix_once
;
16870 const char * group_name
;
16874 size_t sec_name_len
;
16881 prefix
= ELF_STRING_ARM_unwind
;
16882 prefix_once
= ELF_STRING_ARM_unwind_once
;
16883 type
= SHT_ARM_EXIDX
;
16887 prefix
= ELF_STRING_ARM_unwind_info
;
16888 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
16889 type
= SHT_PROGBITS
;
16892 text_name
= segment_name (text_seg
);
16893 if (streq (text_name
, ".text"))
16896 if (strncmp (text_name
, ".gnu.linkonce.t.",
16897 strlen (".gnu.linkonce.t.")) == 0)
16899 prefix
= prefix_once
;
16900 text_name
+= strlen (".gnu.linkonce.t.");
16903 prefix_len
= strlen (prefix
);
16904 text_len
= strlen (text_name
);
16905 sec_name_len
= prefix_len
+ text_len
;
16906 sec_name
= xmalloc (sec_name_len
+ 1);
16907 memcpy (sec_name
, prefix
, prefix_len
);
16908 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
16909 sec_name
[prefix_len
+ text_len
] = '\0';
16915 /* Handle COMDAT group. */
16916 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
16918 group_name
= elf_group_name (text_seg
);
16919 if (group_name
== NULL
)
16921 as_bad ("Group section `%s' has no group signature",
16922 segment_name (text_seg
));
16923 ignore_rest_of_line ();
16926 flags
|= SHF_GROUP
;
16930 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
16932 /* Set the setion link for index tables. */
16934 elf_linked_to_section (now_seg
) = text_seg
;
16938 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
16939 personality routine data. Returns zero, or the index table value for
16940 and inline entry. */
16943 create_unwind_entry (int have_data
)
16948 /* The current word of data. */
16950 /* The number of bytes left in this word. */
16953 finish_unwind_opcodes ();
16955 /* Remember the current text section. */
16956 unwind
.saved_seg
= now_seg
;
16957 unwind
.saved_subseg
= now_subseg
;
16959 start_unwind_section (now_seg
, 0);
16961 if (unwind
.personality_routine
== NULL
)
16963 if (unwind
.personality_index
== -2)
16966 as_bad (_("handerdata in cantunwind frame"));
16967 return 1; /* EXIDX_CANTUNWIND. */
16970 /* Use a default personality routine if none is specified. */
16971 if (unwind
.personality_index
== -1)
16973 if (unwind
.opcode_count
> 3)
16974 unwind
.personality_index
= 1;
16976 unwind
.personality_index
= 0;
16979 /* Space for the personality routine entry. */
16980 if (unwind
.personality_index
== 0)
16982 if (unwind
.opcode_count
> 3)
16983 as_bad (_("too many unwind opcodes for personality routine 0"));
16987 /* All the data is inline in the index table. */
16990 while (unwind
.opcode_count
> 0)
16992 unwind
.opcode_count
--;
16993 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
16997 /* Pad with "finish" opcodes. */
16999 data
= (data
<< 8) | 0xb0;
17006 /* We get two opcodes "free" in the first word. */
17007 size
= unwind
.opcode_count
- 2;
17010 /* An extra byte is required for the opcode count. */
17011 size
= unwind
.opcode_count
+ 1;
17013 size
= (size
+ 3) >> 2;
17015 as_bad (_("too many unwind opcodes"));
17017 frag_align (2, 0, 0);
17018 record_alignment (now_seg
, 2);
17019 unwind
.table_entry
= expr_build_dot ();
17021 /* Allocate the table entry. */
17022 ptr
= frag_more ((size
<< 2) + 4);
17023 where
= frag_now_fix () - ((size
<< 2) + 4);
17025 switch (unwind
.personality_index
)
17028 /* ??? Should this be a PLT generating relocation? */
17029 /* Custom personality routine. */
17030 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
17031 BFD_RELOC_ARM_PREL31
);
17036 /* Set the first byte to the number of additional words. */
17041 /* ABI defined personality routines. */
17043 /* Three opcodes bytes are packed into the first word. */
17050 /* The size and first two opcode bytes go in the first word. */
17051 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
17056 /* Should never happen. */
17060 /* Pack the opcodes into words (MSB first), reversing the list at the same
17062 while (unwind
.opcode_count
> 0)
17066 md_number_to_chars (ptr
, data
, 4);
17071 unwind
.opcode_count
--;
17073 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
17076 /* Finish off the last word. */
17079 /* Pad with "finish" opcodes. */
17081 data
= (data
<< 8) | 0xb0;
17083 md_number_to_chars (ptr
, data
, 4);
17088 /* Add an empty descriptor if there is no user-specified data. */
17089 ptr
= frag_more (4);
17090 md_number_to_chars (ptr
, 0, 4);
17097 /* Initialize the DWARF-2 unwind information for this procedure. */
17100 tc_arm_frame_initial_instructions (void)
17102 cfi_add_CFA_def_cfa (REG_SP
, 0);
17104 #endif /* OBJ_ELF */
17106 /* Convert REGNAME to a DWARF-2 register number. */
17109 tc_arm_regname_to_dw2regnum (char *regname
)
17111 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
17121 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
17125 expr
.X_op
= O_secrel
;
17126 expr
.X_add_symbol
= symbol
;
17127 expr
.X_add_number
= 0;
17128 emit_expr (&expr
, size
);
17132 /* MD interface: Symbol and relocation handling. */
17134 /* Return the address within the segment that a PC-relative fixup is
17135 relative to. For ARM, PC-relative fixups applied to instructions
17136 are generally relative to the location of the fixup plus 8 bytes.
17137 Thumb branches are offset by 4, and Thumb loads relative to PC
17138 require special handling. */
17141 md_pcrel_from_section (fixS
* fixP
, segT seg
)
17143 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
17145 /* If this is pc-relative and we are going to emit a relocation
17146 then we just want to put out any pipeline compensation that the linker
17147 will need. Otherwise we want to use the calculated base.
17148 For WinCE we skip the bias for externals as well, since this
17149 is how the MS ARM-CE assembler behaves and we want to be compatible. */
17151 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
17152 || (arm_force_relocation (fixP
)
17154 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
17159 switch (fixP
->fx_r_type
)
17161 /* PC relative addressing on the Thumb is slightly odd as the
17162 bottom two bits of the PC are forced to zero for the
17163 calculation. This happens *after* application of the
17164 pipeline offset. However, Thumb adrl already adjusts for
17165 this, so we need not do it again. */
17166 case BFD_RELOC_ARM_THUMB_ADD
:
17169 case BFD_RELOC_ARM_THUMB_OFFSET
:
17170 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
17171 case BFD_RELOC_ARM_T32_ADD_PC12
:
17172 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
17173 return (base
+ 4) & ~3;
17175 /* Thumb branches are simply offset by +4. */
17176 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
17177 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
17178 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
17179 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
17180 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
17181 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
17182 case BFD_RELOC_THUMB_PCREL_BLX
:
17185 /* ARM mode branches are offset by +8. However, the Windows CE
17186 loader expects the relocation not to take this into account. */
17187 case BFD_RELOC_ARM_PCREL_BRANCH
:
17188 case BFD_RELOC_ARM_PCREL_CALL
:
17189 case BFD_RELOC_ARM_PCREL_JUMP
:
17190 case BFD_RELOC_ARM_PCREL_BLX
:
17191 case BFD_RELOC_ARM_PLT32
:
17193 /* When handling fixups immediately, because we have already
17194 discovered the value of a symbol, or the address of the frag involved
17195 we must account for the offset by +8, as the OS loader will never see the reloc.
17196 see fixup_segment() in write.c
17197 The S_IS_EXTERNAL test handles the case of global symbols.
17198 Those need the calculated base, not just the pipe compensation the linker will need. */
17200 && fixP
->fx_addsy
!= NULL
17201 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
17202 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
17209 /* ARM mode loads relative to PC are also offset by +8. Unlike
17210 branches, the Windows CE loader *does* expect the relocation
17211 to take this into account. */
17212 case BFD_RELOC_ARM_OFFSET_IMM
:
17213 case BFD_RELOC_ARM_OFFSET_IMM8
:
17214 case BFD_RELOC_ARM_HWLITERAL
:
17215 case BFD_RELOC_ARM_LITERAL
:
17216 case BFD_RELOC_ARM_CP_OFF_IMM
:
17220 /* Other PC-relative relocations are un-offset. */
17226 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
17227 Otherwise we have no need to default values of symbols. */
17230 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
17233 if (name
[0] == '_' && name
[1] == 'G'
17234 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
17238 if (symbol_find (name
))
17239 as_bad ("GOT already in the symbol table");
17241 GOT_symbol
= symbol_new (name
, undefined_section
,
17242 (valueT
) 0, & zero_address_frag
);
17252 /* Subroutine of md_apply_fix. Check to see if an immediate can be
17253 computed as two separate immediate values, added together. We
17254 already know that this value cannot be computed by just one ARM
17257 static unsigned int
17258 validate_immediate_twopart (unsigned int val
,
17259 unsigned int * highpart
)
17264 for (i
= 0; i
< 32; i
+= 2)
17265 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
17271 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
17273 else if (a
& 0xff0000)
17275 if (a
& 0xff000000)
17277 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
17281 assert (a
& 0xff000000);
17282 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
17285 return (a
& 0xff) | (i
<< 7);
17292 validate_offset_imm (unsigned int val
, int hwse
)
17294 if ((hwse
&& val
> 255) || val
> 4095)
17299 /* Subroutine of md_apply_fix. Do those data_ops which can take a
17300 negative immediate constant by altering the instruction. A bit of
17305 by inverting the second operand, and
17308 by negating the second operand. */
17311 negate_data_op (unsigned long * instruction
,
17312 unsigned long value
)
17315 unsigned long negated
, inverted
;
17317 negated
= encode_arm_immediate (-value
);
17318 inverted
= encode_arm_immediate (~value
);
17320 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
17323 /* First negates. */
17324 case OPCODE_SUB
: /* ADD <-> SUB */
17325 new_inst
= OPCODE_ADD
;
17330 new_inst
= OPCODE_SUB
;
17334 case OPCODE_CMP
: /* CMP <-> CMN */
17335 new_inst
= OPCODE_CMN
;
17340 new_inst
= OPCODE_CMP
;
17344 /* Now Inverted ops. */
17345 case OPCODE_MOV
: /* MOV <-> MVN */
17346 new_inst
= OPCODE_MVN
;
17351 new_inst
= OPCODE_MOV
;
17355 case OPCODE_AND
: /* AND <-> BIC */
17356 new_inst
= OPCODE_BIC
;
17361 new_inst
= OPCODE_AND
;
17365 case OPCODE_ADC
: /* ADC <-> SBC */
17366 new_inst
= OPCODE_SBC
;
17371 new_inst
= OPCODE_ADC
;
17375 /* We cannot do anything. */
17380 if (value
== (unsigned) FAIL
)
17383 *instruction
&= OPCODE_MASK
;
17384 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
17388 /* Like negate_data_op, but for Thumb-2. */
17390 static unsigned int
17391 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
17395 unsigned int negated
, inverted
;
17397 negated
= encode_thumb32_immediate (-value
);
17398 inverted
= encode_thumb32_immediate (~value
);
17400 rd
= (*instruction
>> 8) & 0xf;
17401 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
17404 /* ADD <-> SUB. Includes CMP <-> CMN. */
17405 case T2_OPCODE_SUB
:
17406 new_inst
= T2_OPCODE_ADD
;
17410 case T2_OPCODE_ADD
:
17411 new_inst
= T2_OPCODE_SUB
;
17415 /* ORR <-> ORN. Includes MOV <-> MVN. */
17416 case T2_OPCODE_ORR
:
17417 new_inst
= T2_OPCODE_ORN
;
17421 case T2_OPCODE_ORN
:
17422 new_inst
= T2_OPCODE_ORR
;
17426 /* AND <-> BIC. TST has no inverted equivalent. */
17427 case T2_OPCODE_AND
:
17428 new_inst
= T2_OPCODE_BIC
;
17435 case T2_OPCODE_BIC
:
17436 new_inst
= T2_OPCODE_AND
;
17441 case T2_OPCODE_ADC
:
17442 new_inst
= T2_OPCODE_SBC
;
17446 case T2_OPCODE_SBC
:
17447 new_inst
= T2_OPCODE_ADC
;
17451 /* We cannot do anything. */
17456 if (value
== (unsigned int)FAIL
)
17459 *instruction
&= T2_OPCODE_MASK
;
17460 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
17464 /* Read a 32-bit thumb instruction from buf. */
17465 static unsigned long
17466 get_thumb32_insn (char * buf
)
17468 unsigned long insn
;
17469 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
17470 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17476 /* We usually want to set the low bit on the address of thumb function
17477 symbols. In particular .word foo - . should have the low bit set.
17478 Generic code tries to fold the difference of two symbols to
17479 a constant. Prevent this and force a relocation when the first symbols
17480 is a thumb function. */
17482 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
17484 if (op
== O_subtract
17485 && l
->X_op
== O_symbol
17486 && r
->X_op
== O_symbol
17487 && THUMB_IS_FUNC (l
->X_add_symbol
))
17489 l
->X_op
= O_subtract
;
17490 l
->X_op_symbol
= r
->X_add_symbol
;
17491 l
->X_add_number
-= r
->X_add_number
;
17494 /* Process as normal. */
17499 md_apply_fix (fixS
* fixP
,
17503 offsetT value
= * valP
;
17505 unsigned int newimm
;
17506 unsigned long temp
;
17508 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
17510 assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
17512 /* Note whether this will delete the relocation. */
17514 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
17517 /* On a 64-bit host, silently truncate 'value' to 32 bits for
17518 consistency with the behavior on 32-bit hosts. Remember value
17520 value
&= 0xffffffff;
17521 value
^= 0x80000000;
17522 value
-= 0x80000000;
17525 fixP
->fx_addnumber
= value
;
17527 /* Same treatment for fixP->fx_offset. */
17528 fixP
->fx_offset
&= 0xffffffff;
17529 fixP
->fx_offset
^= 0x80000000;
17530 fixP
->fx_offset
-= 0x80000000;
17532 switch (fixP
->fx_r_type
)
17534 case BFD_RELOC_NONE
:
17535 /* This will need to go in the object file. */
17539 case BFD_RELOC_ARM_IMMEDIATE
:
17540 /* We claim that this fixup has been processed here,
17541 even if in fact we generate an error because we do
17542 not have a reloc for it, so tc_gen_reloc will reject it. */
17546 && ! S_IS_DEFINED (fixP
->fx_addsy
))
17548 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17549 _("undefined symbol %s used as an immediate value"),
17550 S_GET_NAME (fixP
->fx_addsy
));
17554 newimm
= encode_arm_immediate (value
);
17555 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17557 /* If the instruction will fail, see if we can fix things up by
17558 changing the opcode. */
17559 if (newimm
== (unsigned int) FAIL
17560 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
17562 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17563 _("invalid constant (%lx) after fixup"),
17564 (unsigned long) value
);
17568 newimm
|= (temp
& 0xfffff000);
17569 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
17572 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
17574 unsigned int highpart
= 0;
17575 unsigned int newinsn
= 0xe1a00000; /* nop. */
17577 newimm
= encode_arm_immediate (value
);
17578 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17580 /* If the instruction will fail, see if we can fix things up by
17581 changing the opcode. */
17582 if (newimm
== (unsigned int) FAIL
17583 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
17585 /* No ? OK - try using two ADD instructions to generate
17587 newimm
= validate_immediate_twopart (value
, & highpart
);
17589 /* Yes - then make sure that the second instruction is
17591 if (newimm
!= (unsigned int) FAIL
)
17593 /* Still No ? Try using a negated value. */
17594 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
17595 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
17596 /* Otherwise - give up. */
17599 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17600 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
17605 /* Replace the first operand in the 2nd instruction (which
17606 is the PC) with the destination register. We have
17607 already added in the PC in the first instruction and we
17608 do not want to do it again. */
17609 newinsn
&= ~ 0xf0000;
17610 newinsn
|= ((newinsn
& 0x0f000) << 4);
17613 newimm
|= (temp
& 0xfffff000);
17614 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
17616 highpart
|= (newinsn
& 0xfffff000);
17617 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
17621 case BFD_RELOC_ARM_OFFSET_IMM
:
17622 if (!fixP
->fx_done
&& seg
->use_rela_p
)
17625 case BFD_RELOC_ARM_LITERAL
:
17631 if (validate_offset_imm (value
, 0) == FAIL
)
17633 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
17634 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17635 _("invalid literal constant: pool needs to be closer"));
17637 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17638 _("bad immediate value for offset (%ld)"),
17643 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17644 newval
&= 0xff7ff000;
17645 newval
|= value
| (sign
? INDEX_UP
: 0);
17646 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17649 case BFD_RELOC_ARM_OFFSET_IMM8
:
17650 case BFD_RELOC_ARM_HWLITERAL
:
17656 if (validate_offset_imm (value
, 1) == FAIL
)
17658 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
17659 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17660 _("invalid literal constant: pool needs to be closer"));
17662 as_bad (_("bad immediate value for half-word offset (%ld)"),
17667 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17668 newval
&= 0xff7ff0f0;
17669 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
17670 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17673 case BFD_RELOC_ARM_T32_OFFSET_U8
:
17674 if (value
< 0 || value
> 1020 || value
% 4 != 0)
17675 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17676 _("bad immediate value for offset (%ld)"), (long) value
);
17679 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
17681 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
17684 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
17685 /* This is a complicated relocation used for all varieties of Thumb32
17686 load/store instruction with immediate offset:
17688 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
17689 *4, optional writeback(W)
17690 (doubleword load/store)
17692 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
17693 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
17694 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
17695 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
17696 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
17698 Uppercase letters indicate bits that are already encoded at
17699 this point. Lowercase letters are our problem. For the
17700 second block of instructions, the secondary opcode nybble
17701 (bits 8..11) is present, and bit 23 is zero, even if this is
17702 a PC-relative operation. */
17703 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17705 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
17707 if ((newval
& 0xf0000000) == 0xe0000000)
17709 /* Doubleword load/store: 8-bit offset, scaled by 4. */
17711 newval
|= (1 << 23);
17714 if (value
% 4 != 0)
17716 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17717 _("offset not a multiple of 4"));
17723 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17724 _("offset out of range"));
17729 else if ((newval
& 0x000f0000) == 0x000f0000)
17731 /* PC-relative, 12-bit offset. */
17733 newval
|= (1 << 23);
17738 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17739 _("offset out of range"));
17744 else if ((newval
& 0x00000100) == 0x00000100)
17746 /* Writeback: 8-bit, +/- offset. */
17748 newval
|= (1 << 9);
17753 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17754 _("offset out of range"));
17759 else if ((newval
& 0x00000f00) == 0x00000e00)
17761 /* T-instruction: positive 8-bit offset. */
17762 if (value
< 0 || value
> 0xff)
17764 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17765 _("offset out of range"));
17773 /* Positive 12-bit or negative 8-bit offset. */
17777 newval
|= (1 << 23);
17787 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17788 _("offset out of range"));
17795 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
17796 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
17799 case BFD_RELOC_ARM_SHIFT_IMM
:
17800 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17801 if (((unsigned long) value
) > 32
17803 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
17805 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17806 _("shift expression is too large"));
17811 /* Shifts of zero must be done as lsl. */
17813 else if (value
== 32)
17815 newval
&= 0xfffff07f;
17816 newval
|= (value
& 0x1f) << 7;
17817 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17820 case BFD_RELOC_ARM_T32_IMMEDIATE
:
17821 case BFD_RELOC_ARM_T32_ADD_IMM
:
17822 case BFD_RELOC_ARM_T32_IMM12
:
17823 case BFD_RELOC_ARM_T32_ADD_PC12
:
17824 /* We claim that this fixup has been processed here,
17825 even if in fact we generate an error because we do
17826 not have a reloc for it, so tc_gen_reloc will reject it. */
17830 && ! S_IS_DEFINED (fixP
->fx_addsy
))
17832 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17833 _("undefined symbol %s used as an immediate value"),
17834 S_GET_NAME (fixP
->fx_addsy
));
17838 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17840 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
17843 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
17844 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
17846 newimm
= encode_thumb32_immediate (value
);
17847 if (newimm
== (unsigned int) FAIL
)
17848 newimm
= thumb32_negate_data_op (&newval
, value
);
17850 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
17851 && newimm
== (unsigned int) FAIL
)
17853 /* Turn add/sum into addw/subw. */
17854 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
17855 newval
= (newval
& 0xfeffffff) | 0x02000000;
17857 /* 12 bit immediate for addw/subw. */
17861 newval
^= 0x00a00000;
17864 newimm
= (unsigned int) FAIL
;
17869 if (newimm
== (unsigned int)FAIL
)
17871 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17872 _("invalid constant (%lx) after fixup"),
17873 (unsigned long) value
);
17877 newval
|= (newimm
& 0x800) << 15;
17878 newval
|= (newimm
& 0x700) << 4;
17879 newval
|= (newimm
& 0x0ff);
17881 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
17882 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
17885 case BFD_RELOC_ARM_SMC
:
17886 if (((unsigned long) value
) > 0xffff)
17887 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17888 _("invalid smc expression"));
17889 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17890 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
17891 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17894 case BFD_RELOC_ARM_SWI
:
17895 if (fixP
->tc_fix_data
!= 0)
17897 if (((unsigned long) value
) > 0xff)
17898 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17899 _("invalid swi expression"));
17900 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17902 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17906 if (((unsigned long) value
) > 0x00ffffff)
17907 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17908 _("invalid swi expression"));
17909 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17911 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17915 case BFD_RELOC_ARM_MULTI
:
17916 if (((unsigned long) value
) > 0xffff)
17917 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17918 _("invalid expression in load/store multiple"));
17919 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
17920 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17924 case BFD_RELOC_ARM_PCREL_CALL
:
17925 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17926 if ((newval
& 0xf0000000) == 0xf0000000)
17930 goto arm_branch_common
;
17932 case BFD_RELOC_ARM_PCREL_JUMP
:
17933 case BFD_RELOC_ARM_PLT32
:
17935 case BFD_RELOC_ARM_PCREL_BRANCH
:
17937 goto arm_branch_common
;
17939 case BFD_RELOC_ARM_PCREL_BLX
:
17942 /* We are going to store value (shifted right by two) in the
17943 instruction, in a 24 bit, signed field. Bits 26 through 32 either
17944 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
17945 also be be clear. */
17947 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17948 _("misaligned branch destination"));
17949 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
17950 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
17951 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17952 _("branch out of range"));
17954 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17956 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17957 newval
|= (value
>> 2) & 0x00ffffff;
17958 /* Set the H bit on BLX instructions. */
17962 newval
|= 0x01000000;
17964 newval
&= ~0x01000000;
17966 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17970 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CZB */
17971 /* CZB can only branch forward. */
17973 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17974 _("branch out of range"));
17976 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17978 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17979 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
17980 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17984 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
17985 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
17986 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17987 _("branch out of range"));
17989 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17991 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17992 newval
|= (value
& 0x1ff) >> 1;
17993 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17997 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
17998 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
17999 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18000 _("branch out of range"));
18002 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18004 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18005 newval
|= (value
& 0xfff) >> 1;
18006 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18010 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
18011 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
18012 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18013 _("conditional branch out of range"));
18015 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18018 addressT S
, J1
, J2
, lo
, hi
;
18020 S
= (value
& 0x00100000) >> 20;
18021 J2
= (value
& 0x00080000) >> 19;
18022 J1
= (value
& 0x00040000) >> 18;
18023 hi
= (value
& 0x0003f000) >> 12;
18024 lo
= (value
& 0x00000ffe) >> 1;
18026 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18027 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18028 newval
|= (S
<< 10) | hi
;
18029 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
18030 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18031 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18035 case BFD_RELOC_THUMB_PCREL_BLX
:
18036 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
18037 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
18038 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18039 _("branch out of range"));
18041 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
18042 /* For a BLX instruction, make sure that the relocation is rounded up
18043 to a word boundary. This follows the semantics of the instruction
18044 which specifies that bit 1 of the target address will come from bit
18045 1 of the base address. */
18046 value
= (value
+ 1) & ~ 1;
18048 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18052 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18053 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18054 newval
|= (value
& 0x7fffff) >> 12;
18055 newval2
|= (value
& 0xfff) >> 1;
18056 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18057 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18061 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
18062 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
18063 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18064 _("branch out of range"));
18066 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18069 addressT S
, I1
, I2
, lo
, hi
;
18071 S
= (value
& 0x01000000) >> 24;
18072 I1
= (value
& 0x00800000) >> 23;
18073 I2
= (value
& 0x00400000) >> 22;
18074 hi
= (value
& 0x003ff000) >> 12;
18075 lo
= (value
& 0x00000ffe) >> 1;
18080 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18081 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18082 newval
|= (S
<< 10) | hi
;
18083 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
18084 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18085 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18090 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18091 md_number_to_chars (buf
, value
, 1);
18095 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18096 md_number_to_chars (buf
, value
, 2);
18100 case BFD_RELOC_ARM_TLS_GD32
:
18101 case BFD_RELOC_ARM_TLS_LE32
:
18102 case BFD_RELOC_ARM_TLS_IE32
:
18103 case BFD_RELOC_ARM_TLS_LDM32
:
18104 case BFD_RELOC_ARM_TLS_LDO32
:
18105 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
18108 case BFD_RELOC_ARM_GOT32
:
18109 case BFD_RELOC_ARM_GOTOFF
:
18110 case BFD_RELOC_ARM_TARGET2
:
18111 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18112 md_number_to_chars (buf
, 0, 4);
18116 case BFD_RELOC_RVA
:
18118 case BFD_RELOC_ARM_TARGET1
:
18119 case BFD_RELOC_ARM_ROSEGREL32
:
18120 case BFD_RELOC_ARM_SBREL32
:
18121 case BFD_RELOC_32_PCREL
:
18123 case BFD_RELOC_32_SECREL
:
18125 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18127 /* For WinCE we only do this for pcrel fixups. */
18128 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
18130 md_number_to_chars (buf
, value
, 4);
18134 case BFD_RELOC_ARM_PREL31
:
18135 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18137 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
18138 if ((value
^ (value
>> 1)) & 0x40000000)
18140 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18141 _("rel31 relocation overflow"));
18143 newval
|= value
& 0x7fffffff;
18144 md_number_to_chars (buf
, newval
, 4);
18149 case BFD_RELOC_ARM_CP_OFF_IMM
:
18150 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
18151 if (value
< -1023 || value
> 1023 || (value
& 3))
18152 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18153 _("co-processor offset out of range"));
18158 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18159 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18160 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18162 newval
= get_thumb32_insn (buf
);
18163 newval
&= 0xff7fff00;
18164 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
18165 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18166 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18167 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18169 put_thumb32_insn (buf
, newval
);
18172 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
18173 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
18174 if (value
< -255 || value
> 255)
18175 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18176 _("co-processor offset out of range"));
18178 goto cp_off_common
;
18180 case BFD_RELOC_ARM_THUMB_OFFSET
:
18181 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18182 /* Exactly what ranges, and where the offset is inserted depends
18183 on the type of instruction, we can establish this from the
18185 switch (newval
>> 12)
18187 case 4: /* PC load. */
18188 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
18189 forced to zero for these loads; md_pcrel_from has already
18190 compensated for this. */
18192 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18193 _("invalid offset, target not word aligned (0x%08lX)"),
18194 (((unsigned long) fixP
->fx_frag
->fr_address
18195 + (unsigned long) fixP
->fx_where
) & ~3)
18196 + (unsigned long) value
);
18198 if (value
& ~0x3fc)
18199 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18200 _("invalid offset, value too big (0x%08lX)"),
18203 newval
|= value
>> 2;
18206 case 9: /* SP load/store. */
18207 if (value
& ~0x3fc)
18208 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18209 _("invalid offset, value too big (0x%08lX)"),
18211 newval
|= value
>> 2;
18214 case 6: /* Word load/store. */
18216 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18217 _("invalid offset, value too big (0x%08lX)"),
18219 newval
|= value
<< 4; /* 6 - 2. */
18222 case 7: /* Byte load/store. */
18224 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18225 _("invalid offset, value too big (0x%08lX)"),
18227 newval
|= value
<< 6;
18230 case 8: /* Halfword load/store. */
18232 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18233 _("invalid offset, value too big (0x%08lX)"),
18235 newval
|= value
<< 5; /* 6 - 1. */
18239 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18240 "Unable to process relocation for thumb opcode: %lx",
18241 (unsigned long) newval
);
18244 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18247 case BFD_RELOC_ARM_THUMB_ADD
:
18248 /* This is a complicated relocation, since we use it for all of
18249 the following immediate relocations:
18253 9bit ADD/SUB SP word-aligned
18254 10bit ADD PC/SP word-aligned
18256 The type of instruction being processed is encoded in the
18263 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18265 int rd
= (newval
>> 4) & 0xf;
18266 int rs
= newval
& 0xf;
18267 int subtract
= !!(newval
& 0x8000);
18269 /* Check for HI regs, only very restricted cases allowed:
18270 Adjusting SP, and using PC or SP to get an address. */
18271 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
18272 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
18273 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18274 _("invalid Hi register with immediate"));
18276 /* If value is negative, choose the opposite instruction. */
18280 subtract
= !subtract
;
18282 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18283 _("immediate value out of range"));
18288 if (value
& ~0x1fc)
18289 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18290 _("invalid immediate for stack address calculation"));
18291 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
18292 newval
|= value
>> 2;
18294 else if (rs
== REG_PC
|| rs
== REG_SP
)
18296 if (subtract
|| value
& ~0x3fc)
18297 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18298 _("invalid immediate for address calculation (value = 0x%08lX)"),
18299 (unsigned long) value
);
18300 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
18302 newval
|= value
>> 2;
18307 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18308 _("immediate value out of range"));
18309 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
18310 newval
|= (rd
<< 8) | value
;
18315 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18316 _("immediate value out of range"));
18317 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
18318 newval
|= rd
| (rs
<< 3) | (value
<< 6);
18321 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18324 case BFD_RELOC_ARM_THUMB_IMM
:
18325 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18326 if (value
< 0 || value
> 255)
18327 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18328 _("invalid immediate: %ld is too large"),
18331 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18334 case BFD_RELOC_ARM_THUMB_SHIFT
:
18335 /* 5bit shift value (0..32). LSL cannot take 32. */
18336 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
18337 temp
= newval
& 0xf800;
18338 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
18339 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18340 _("invalid shift value: %ld"), (long) value
);
18341 /* Shifts of zero must be encoded as LSL. */
18343 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
18344 /* Shifts of 32 are encoded as zero. */
18345 else if (value
== 32)
18347 newval
|= value
<< 6;
18348 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18351 case BFD_RELOC_VTABLE_INHERIT
:
18352 case BFD_RELOC_VTABLE_ENTRY
:
18356 case BFD_RELOC_ARM_MOVW
:
18357 case BFD_RELOC_ARM_MOVT
:
18358 case BFD_RELOC_ARM_THUMB_MOVW
:
18359 case BFD_RELOC_ARM_THUMB_MOVT
:
18360 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18362 /* REL format relocations are limited to a 16-bit addend. */
18363 if (!fixP
->fx_done
)
18365 if (value
< -0x1000 || value
> 0xffff)
18366 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18367 _("offset too big"));
18369 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
18370 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18375 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
18376 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18378 newval
= get_thumb32_insn (buf
);
18379 newval
&= 0xfbf08f00;
18380 newval
|= (value
& 0xf000) << 4;
18381 newval
|= (value
& 0x0800) << 15;
18382 newval
|= (value
& 0x0700) << 4;
18383 newval
|= (value
& 0x00ff);
18384 put_thumb32_insn (buf
, newval
);
18388 newval
= md_chars_to_number (buf
, 4);
18389 newval
&= 0xfff0f000;
18390 newval
|= value
& 0x0fff;
18391 newval
|= (value
& 0xf000) << 4;
18392 md_number_to_chars (buf
, newval
, 4);
18397 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
18398 case BFD_RELOC_ARM_ALU_PC_G0
:
18399 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
18400 case BFD_RELOC_ARM_ALU_PC_G1
:
18401 case BFD_RELOC_ARM_ALU_PC_G2
:
18402 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
18403 case BFD_RELOC_ARM_ALU_SB_G0
:
18404 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
18405 case BFD_RELOC_ARM_ALU_SB_G1
:
18406 case BFD_RELOC_ARM_ALU_SB_G2
:
18407 assert (!fixP
->fx_done
);
18408 if (!seg
->use_rela_p
)
18411 bfd_vma encoded_addend
;
18412 bfd_vma addend_abs
= abs (value
);
18414 /* Check that the absolute value of the addend can be
18415 expressed as an 8-bit constant plus a rotation. */
18416 encoded_addend
= encode_arm_immediate (addend_abs
);
18417 if (encoded_addend
== (unsigned int) FAIL
)
18418 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18419 _("the offset 0x%08lX is not representable"),
18422 /* Extract the instruction. */
18423 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18425 /* If the addend is positive, use an ADD instruction.
18426 Otherwise use a SUB. Take care not to destroy the S bit. */
18427 insn
&= 0xff1fffff;
18433 /* Place the encoded addend into the first 12 bits of the
18435 insn
&= 0xfffff000;
18436 insn
|= encoded_addend
;
18438 /* Update the instruction. */
18439 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18443 case BFD_RELOC_ARM_LDR_PC_G0
:
18444 case BFD_RELOC_ARM_LDR_PC_G1
:
18445 case BFD_RELOC_ARM_LDR_PC_G2
:
18446 case BFD_RELOC_ARM_LDR_SB_G0
:
18447 case BFD_RELOC_ARM_LDR_SB_G1
:
18448 case BFD_RELOC_ARM_LDR_SB_G2
:
18449 assert (!fixP
->fx_done
);
18450 if (!seg
->use_rela_p
)
18453 bfd_vma addend_abs
= abs (value
);
18455 /* Check that the absolute value of the addend can be
18456 encoded in 12 bits. */
18457 if (addend_abs
>= 0x1000)
18458 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18459 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
18462 /* Extract the instruction. */
18463 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18465 /* If the addend is negative, clear bit 23 of the instruction.
18466 Otherwise set it. */
18468 insn
&= ~(1 << 23);
18472 /* Place the absolute value of the addend into the first 12 bits
18473 of the instruction. */
18474 insn
&= 0xfffff000;
18475 insn
|= addend_abs
;
18477 /* Update the instruction. */
18478 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18482 case BFD_RELOC_ARM_LDRS_PC_G0
:
18483 case BFD_RELOC_ARM_LDRS_PC_G1
:
18484 case BFD_RELOC_ARM_LDRS_PC_G2
:
18485 case BFD_RELOC_ARM_LDRS_SB_G0
:
18486 case BFD_RELOC_ARM_LDRS_SB_G1
:
18487 case BFD_RELOC_ARM_LDRS_SB_G2
:
18488 assert (!fixP
->fx_done
);
18489 if (!seg
->use_rela_p
)
18492 bfd_vma addend_abs
= abs (value
);
18494 /* Check that the absolute value of the addend can be
18495 encoded in 8 bits. */
18496 if (addend_abs
>= 0x100)
18497 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18498 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
18501 /* Extract the instruction. */
18502 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18504 /* If the addend is negative, clear bit 23 of the instruction.
18505 Otherwise set it. */
18507 insn
&= ~(1 << 23);
18511 /* Place the first four bits of the absolute value of the addend
18512 into the first 4 bits of the instruction, and the remaining
18513 four into bits 8 .. 11. */
18514 insn
&= 0xfffff0f0;
18515 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
18517 /* Update the instruction. */
18518 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18522 case BFD_RELOC_ARM_LDC_PC_G0
:
18523 case BFD_RELOC_ARM_LDC_PC_G1
:
18524 case BFD_RELOC_ARM_LDC_PC_G2
:
18525 case BFD_RELOC_ARM_LDC_SB_G0
:
18526 case BFD_RELOC_ARM_LDC_SB_G1
:
18527 case BFD_RELOC_ARM_LDC_SB_G2
:
18528 assert (!fixP
->fx_done
);
18529 if (!seg
->use_rela_p
)
18532 bfd_vma addend_abs
= abs (value
);
18534 /* Check that the absolute value of the addend is a multiple of
18535 four and, when divided by four, fits in 8 bits. */
18536 if (addend_abs
& 0x3)
18537 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18538 _("bad offset 0x%08lX (must be word-aligned)"),
18541 if ((addend_abs
>> 2) > 0xff)
18542 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18543 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
18546 /* Extract the instruction. */
18547 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18549 /* If the addend is negative, clear bit 23 of the instruction.
18550 Otherwise set it. */
18552 insn
&= ~(1 << 23);
18556 /* Place the addend (divided by four) into the first eight
18557 bits of the instruction. */
18558 insn
&= 0xfffffff0;
18559 insn
|= addend_abs
>> 2;
18561 /* Update the instruction. */
18562 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18566 case BFD_RELOC_UNUSED
:
18568 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18569 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
18573 /* Translate internal representation of relocation info to BFD target
18577 tc_gen_reloc (asection
*section
, fixS
*fixp
)
18580 bfd_reloc_code_real_type code
;
18582 reloc
= xmalloc (sizeof (arelent
));
18584 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
18585 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18586 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18588 if (fixp
->fx_pcrel
)
18590 if (section
->use_rela_p
)
18591 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
18593 fixp
->fx_offset
= reloc
->address
;
18595 reloc
->addend
= fixp
->fx_offset
;
18597 switch (fixp
->fx_r_type
)
18600 if (fixp
->fx_pcrel
)
18602 code
= BFD_RELOC_8_PCREL
;
18607 if (fixp
->fx_pcrel
)
18609 code
= BFD_RELOC_16_PCREL
;
18614 if (fixp
->fx_pcrel
)
18616 code
= BFD_RELOC_32_PCREL
;
18620 case BFD_RELOC_ARM_MOVW
:
18621 if (fixp
->fx_pcrel
)
18623 code
= BFD_RELOC_ARM_MOVW_PCREL
;
18627 case BFD_RELOC_ARM_MOVT
:
18628 if (fixp
->fx_pcrel
)
18630 code
= BFD_RELOC_ARM_MOVT_PCREL
;
18634 case BFD_RELOC_ARM_THUMB_MOVW
:
18635 if (fixp
->fx_pcrel
)
18637 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
18641 case BFD_RELOC_ARM_THUMB_MOVT
:
18642 if (fixp
->fx_pcrel
)
18644 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
18648 case BFD_RELOC_NONE
:
18649 case BFD_RELOC_ARM_PCREL_BRANCH
:
18650 case BFD_RELOC_ARM_PCREL_BLX
:
18651 case BFD_RELOC_RVA
:
18652 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
18653 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
18654 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
18655 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
18656 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
18657 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
18658 case BFD_RELOC_THUMB_PCREL_BLX
:
18659 case BFD_RELOC_VTABLE_ENTRY
:
18660 case BFD_RELOC_VTABLE_INHERIT
:
18662 case BFD_RELOC_32_SECREL
:
18664 code
= fixp
->fx_r_type
;
18667 case BFD_RELOC_ARM_LITERAL
:
18668 case BFD_RELOC_ARM_HWLITERAL
:
18669 /* If this is called then the a literal has
18670 been referenced across a section boundary. */
18671 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18672 _("literal referenced across section boundary"));
18676 case BFD_RELOC_ARM_GOT32
:
18677 case BFD_RELOC_ARM_GOTOFF
:
18678 case BFD_RELOC_ARM_PLT32
:
18679 case BFD_RELOC_ARM_TARGET1
:
18680 case BFD_RELOC_ARM_ROSEGREL32
:
18681 case BFD_RELOC_ARM_SBREL32
:
18682 case BFD_RELOC_ARM_PREL31
:
18683 case BFD_RELOC_ARM_TARGET2
:
18684 case BFD_RELOC_ARM_TLS_LE32
:
18685 case BFD_RELOC_ARM_TLS_LDO32
:
18686 case BFD_RELOC_ARM_PCREL_CALL
:
18687 case BFD_RELOC_ARM_PCREL_JUMP
:
18688 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
18689 case BFD_RELOC_ARM_ALU_PC_G0
:
18690 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
18691 case BFD_RELOC_ARM_ALU_PC_G1
:
18692 case BFD_RELOC_ARM_ALU_PC_G2
:
18693 case BFD_RELOC_ARM_LDR_PC_G0
:
18694 case BFD_RELOC_ARM_LDR_PC_G1
:
18695 case BFD_RELOC_ARM_LDR_PC_G2
:
18696 case BFD_RELOC_ARM_LDRS_PC_G0
:
18697 case BFD_RELOC_ARM_LDRS_PC_G1
:
18698 case BFD_RELOC_ARM_LDRS_PC_G2
:
18699 case BFD_RELOC_ARM_LDC_PC_G0
:
18700 case BFD_RELOC_ARM_LDC_PC_G1
:
18701 case BFD_RELOC_ARM_LDC_PC_G2
:
18702 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
18703 case BFD_RELOC_ARM_ALU_SB_G0
:
18704 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
18705 case BFD_RELOC_ARM_ALU_SB_G1
:
18706 case BFD_RELOC_ARM_ALU_SB_G2
:
18707 case BFD_RELOC_ARM_LDR_SB_G0
:
18708 case BFD_RELOC_ARM_LDR_SB_G1
:
18709 case BFD_RELOC_ARM_LDR_SB_G2
:
18710 case BFD_RELOC_ARM_LDRS_SB_G0
:
18711 case BFD_RELOC_ARM_LDRS_SB_G1
:
18712 case BFD_RELOC_ARM_LDRS_SB_G2
:
18713 case BFD_RELOC_ARM_LDC_SB_G0
:
18714 case BFD_RELOC_ARM_LDC_SB_G1
:
18715 case BFD_RELOC_ARM_LDC_SB_G2
:
18716 code
= fixp
->fx_r_type
;
18719 case BFD_RELOC_ARM_TLS_GD32
:
18720 case BFD_RELOC_ARM_TLS_IE32
:
18721 case BFD_RELOC_ARM_TLS_LDM32
:
18722 /* BFD will include the symbol's address in the addend.
18723 But we don't want that, so subtract it out again here. */
18724 if (!S_IS_COMMON (fixp
->fx_addsy
))
18725 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
18726 code
= fixp
->fx_r_type
;
18730 case BFD_RELOC_ARM_IMMEDIATE
:
18731 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18732 _("internal relocation (type: IMMEDIATE) not fixed up"));
18735 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
18736 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18737 _("ADRL used for a symbol not defined in the same file"));
18740 case BFD_RELOC_ARM_OFFSET_IMM
:
18741 if (section
->use_rela_p
)
18743 code
= fixp
->fx_r_type
;
18747 if (fixp
->fx_addsy
!= NULL
18748 && !S_IS_DEFINED (fixp
->fx_addsy
)
18749 && S_IS_LOCAL (fixp
->fx_addsy
))
18751 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18752 _("undefined local label `%s'"),
18753 S_GET_NAME (fixp
->fx_addsy
));
18757 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18758 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
18765 switch (fixp
->fx_r_type
)
18767 case BFD_RELOC_NONE
: type
= "NONE"; break;
18768 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
18769 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
18770 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
18771 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
18772 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
18773 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
18774 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
18775 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
18776 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
18777 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
18778 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
18779 default: type
= _("<unknown>"); break;
18781 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18782 _("cannot represent %s relocation in this object file format"),
18789 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
18791 && fixp
->fx_addsy
== GOT_symbol
)
18793 code
= BFD_RELOC_ARM_GOTPC
;
18794 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
18798 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18800 if (reloc
->howto
== NULL
)
18802 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18803 _("cannot represent %s relocation in this object file format"),
18804 bfd_get_reloc_code_name (code
));
18808 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
18809 vtable entry to be used in the relocation's section offset. */
18810 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18811 reloc
->address
= fixp
->fx_offset
;
18816 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
18819 cons_fix_new_arm (fragS
* frag
,
18824 bfd_reloc_code_real_type type
;
18828 FIXME: @@ Should look at CPU word size. */
18832 type
= BFD_RELOC_8
;
18835 type
= BFD_RELOC_16
;
18839 type
= BFD_RELOC_32
;
18842 type
= BFD_RELOC_64
;
18847 if (exp
->X_op
== O_secrel
)
18849 exp
->X_op
= O_symbol
;
18850 type
= BFD_RELOC_32_SECREL
;
18854 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
18857 #if defined OBJ_COFF || defined OBJ_ELF
18859 arm_validate_fix (fixS
* fixP
)
18861 /* If the destination of the branch is a defined symbol which does not have
18862 the THUMB_FUNC attribute, then we must be calling a function which has
18863 the (interfacearm) attribute. We look for the Thumb entry point to that
18864 function and change the branch to refer to that function instead. */
18865 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
18866 && fixP
->fx_addsy
!= NULL
18867 && S_IS_DEFINED (fixP
->fx_addsy
)
18868 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
18870 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
18876 arm_force_relocation (struct fix
* fixp
)
18878 #if defined (OBJ_COFF) && defined (TE_PE)
18879 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
18883 /* Resolve these relocations even if the symbol is extern or weak. */
18884 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
18885 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
18886 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
18887 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
18888 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
18889 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
18890 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
18893 /* Always leave these relocations for the linker. */
18894 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
18895 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
18896 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
18899 return generic_force_reloc (fixp
);
18904 arm_fix_adjustable (fixS
* fixP
)
18906 /* This is a little hack to help the gas/arm/adrl.s test. It prevents
18907 local labels from being added to the output symbol table when they
18908 are used with the ADRL pseudo op. The ADRL relocation should always
18909 be resolved before the binbary is emitted, so it is safe to say that
18910 it is adjustable. */
18911 if (fixP
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
)
18914 /* This is a hack for the gas/all/redef2.s test. This test causes symbols
18915 to be cloned, and without this test relocs would still be generated
18916 against the original, pre-cloned symbol. Such symbols would not appear
18917 in the symbol table however, and so a valid reloc could not be
18918 generated. So check to see if the fixup is against a symbol which has
18919 been removed from the symbol chain, and if it is, then allow it to be
18920 adjusted into a reloc against a section symbol. */
18921 if (fixP
->fx_addsy
!= NULL
18922 && ! S_IS_LOCAL (fixP
->fx_addsy
)
18923 && symbol_next (fixP
->fx_addsy
) == NULL
18924 && symbol_next (fixP
->fx_addsy
) == symbol_previous (fixP
->fx_addsy
))
18932 /* Relocations against function names must be left unadjusted,
18933 so that the linker can use this information to generate interworking
18934 stubs. The MIPS version of this function
18935 also prevents relocations that are mips-16 specific, but I do not
18936 know why it does this.
18939 There is one other problem that ought to be addressed here, but
18940 which currently is not: Taking the address of a label (rather
18941 than a function) and then later jumping to that address. Such
18942 addresses also ought to have their bottom bit set (assuming that
18943 they reside in Thumb code), but at the moment they will not. */
18946 arm_fix_adjustable (fixS
* fixP
)
18948 if (fixP
->fx_addsy
== NULL
)
18951 /* Preserve relocations against symbols with function type. */
18952 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
18955 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
18956 && fixP
->fx_subsy
== NULL
)
18959 /* We need the symbol name for the VTABLE entries. */
18960 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
18961 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18964 /* Don't allow symbols to be discarded on GOT related relocs. */
18965 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
18966 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
18967 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
18968 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
18969 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
18970 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
18971 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
18972 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
18973 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
18976 /* Similarly for group relocations. */
18977 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
18978 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
18979 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
18986 elf32_arm_target_format (void)
18989 return (target_big_endian
18990 ? "elf32-bigarm-symbian"
18991 : "elf32-littlearm-symbian");
18992 #elif defined (TE_VXWORKS)
18993 return (target_big_endian
18994 ? "elf32-bigarm-vxworks"
18995 : "elf32-littlearm-vxworks");
18997 if (target_big_endian
)
18998 return "elf32-bigarm";
19000 return "elf32-littlearm";
19005 armelf_frob_symbol (symbolS
* symp
,
19008 elf_frob_symbol (symp
, puntp
);
19012 /* MD interface: Finalization. */
19014 /* A good place to do this, although this was probably not intended
19015 for this kind of use. We need to dump the literal pool before
19016 references are made to a null symbol pointer. */
19021 literal_pool
* pool
;
19023 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
19025 /* Put it at the end of the relevent section. */
19026 subseg_set (pool
->section
, pool
->sub_section
);
19028 arm_elf_change_section ();
19034 /* Adjust the symbol table. This marks Thumb symbols as distinct from
19038 arm_adjust_symtab (void)
19043 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
19045 if (ARM_IS_THUMB (sym
))
19047 if (THUMB_IS_FUNC (sym
))
19049 /* Mark the symbol as a Thumb function. */
19050 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
19051 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
19052 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
19054 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
19055 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
19057 as_bad (_("%s: unexpected function type: %d"),
19058 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
19060 else switch (S_GET_STORAGE_CLASS (sym
))
19063 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
19066 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
19069 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
19077 if (ARM_IS_INTERWORK (sym
))
19078 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
19085 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
19087 if (ARM_IS_THUMB (sym
))
19089 elf_symbol_type
* elf_sym
;
19091 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
19092 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
19094 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
19095 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
19097 /* If it's a .thumb_func, declare it as so,
19098 otherwise tag label as .code 16. */
19099 if (THUMB_IS_FUNC (sym
))
19100 elf_sym
->internal_elf_sym
.st_info
=
19101 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
19103 elf_sym
->internal_elf_sym
.st_info
=
19104 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
19111 /* MD interface: Initialization. */
19114 set_constant_flonums (void)
19118 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
19119 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
19123 /* Auto-select Thumb mode if it's the only available instruction set for the
19124 given architecture. */
19127 autoselect_thumb_from_cpu_variant (void)
19129 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
19130 opcode_select (16);
19139 if ( (arm_ops_hsh
= hash_new ()) == NULL
19140 || (arm_cond_hsh
= hash_new ()) == NULL
19141 || (arm_shift_hsh
= hash_new ()) == NULL
19142 || (arm_psr_hsh
= hash_new ()) == NULL
19143 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
19144 || (arm_reg_hsh
= hash_new ()) == NULL
19145 || (arm_reloc_hsh
= hash_new ()) == NULL
19146 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
19147 as_fatal (_("virtual memory exhausted"));
19149 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
19150 hash_insert (arm_ops_hsh
, insns
[i
].template, (PTR
) (insns
+ i
));
19151 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
19152 hash_insert (arm_cond_hsh
, conds
[i
].template, (PTR
) (conds
+ i
));
19153 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
19154 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (PTR
) (shift_names
+ i
));
19155 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
19156 hash_insert (arm_psr_hsh
, psrs
[i
].template, (PTR
) (psrs
+ i
));
19157 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
19158 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template, (PTR
) (v7m_psrs
+ i
));
19159 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
19160 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (PTR
) (reg_names
+ i
));
19162 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
19164 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template,
19165 (PTR
) (barrier_opt_names
+ i
));
19167 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
19168 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (PTR
) (reloc_names
+ i
));
19171 set_constant_flonums ();
19173 /* Set the cpu variant based on the command-line options. We prefer
19174 -mcpu= over -march= if both are set (as for GCC); and we prefer
19175 -mfpu= over any other way of setting the floating point unit.
19176 Use of legacy options with new options are faulted. */
19179 if (mcpu_cpu_opt
|| march_cpu_opt
)
19180 as_bad (_("use of old and new-style options to set CPU type"));
19182 mcpu_cpu_opt
= legacy_cpu
;
19184 else if (!mcpu_cpu_opt
)
19185 mcpu_cpu_opt
= march_cpu_opt
;
19190 as_bad (_("use of old and new-style options to set FPU type"));
19192 mfpu_opt
= legacy_fpu
;
19194 else if (!mfpu_opt
)
19196 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
19197 /* Some environments specify a default FPU. If they don't, infer it
19198 from the processor. */
19200 mfpu_opt
= mcpu_fpu_opt
;
19202 mfpu_opt
= march_fpu_opt
;
19204 mfpu_opt
= &fpu_default
;
19211 mfpu_opt
= &fpu_default
;
19212 else if (ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
19213 mfpu_opt
= &fpu_arch_vfp_v2
;
19215 mfpu_opt
= &fpu_arch_fpa
;
19221 mcpu_cpu_opt
= &cpu_default
;
19222 selected_cpu
= cpu_default
;
19226 selected_cpu
= *mcpu_cpu_opt
;
19228 mcpu_cpu_opt
= &arm_arch_any
;
19231 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
19233 autoselect_thumb_from_cpu_variant ();
19235 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
19237 #if defined OBJ_COFF || defined OBJ_ELF
19239 unsigned int flags
= 0;
19241 #if defined OBJ_ELF
19242 flags
= meabi_flags
;
19244 switch (meabi_flags
)
19246 case EF_ARM_EABI_UNKNOWN
:
19248 /* Set the flags in the private structure. */
19249 if (uses_apcs_26
) flags
|= F_APCS26
;
19250 if (support_interwork
) flags
|= F_INTERWORK
;
19251 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
19252 if (pic_code
) flags
|= F_PIC
;
19253 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
19254 flags
|= F_SOFT_FLOAT
;
19256 switch (mfloat_abi_opt
)
19258 case ARM_FLOAT_ABI_SOFT
:
19259 case ARM_FLOAT_ABI_SOFTFP
:
19260 flags
|= F_SOFT_FLOAT
;
19263 case ARM_FLOAT_ABI_HARD
:
19264 if (flags
& F_SOFT_FLOAT
)
19265 as_bad (_("hard-float conflicts with specified fpu"));
19269 /* Using pure-endian doubles (even if soft-float). */
19270 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
19271 flags
|= F_VFP_FLOAT
;
19273 #if defined OBJ_ELF
19274 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
19275 flags
|= EF_ARM_MAVERICK_FLOAT
;
19278 case EF_ARM_EABI_VER4
:
19279 case EF_ARM_EABI_VER5
:
19280 /* No additional flags to set. */
19287 bfd_set_private_flags (stdoutput
, flags
);
19289 /* We have run out flags in the COFF header to encode the
19290 status of ATPCS support, so instead we create a dummy,
19291 empty, debug section called .arm.atpcs. */
19296 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
19300 bfd_set_section_flags
19301 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
19302 bfd_set_section_size (stdoutput
, sec
, 0);
19303 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
19309 /* Record the CPU type as well. */
19310 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
19311 mach
= bfd_mach_arm_iWMMXt2
;
19312 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
19313 mach
= bfd_mach_arm_iWMMXt
;
19314 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
19315 mach
= bfd_mach_arm_XScale
;
19316 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
19317 mach
= bfd_mach_arm_ep9312
;
19318 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
19319 mach
= bfd_mach_arm_5TE
;
19320 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
19322 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19323 mach
= bfd_mach_arm_5T
;
19325 mach
= bfd_mach_arm_5
;
19327 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
19329 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19330 mach
= bfd_mach_arm_4T
;
19332 mach
= bfd_mach_arm_4
;
19334 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
19335 mach
= bfd_mach_arm_3M
;
19336 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
19337 mach
= bfd_mach_arm_3
;
19338 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
19339 mach
= bfd_mach_arm_2a
;
19340 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
19341 mach
= bfd_mach_arm_2
;
19343 mach
= bfd_mach_arm_unknown
;
19345 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
19348 /* Command line processing. */
19351 Invocation line includes a switch not recognized by the base assembler.
19352 See if it's a processor-specific option.
19354 This routine is somewhat complicated by the need for backwards
19355 compatibility (since older releases of gcc can't be changed).
19356 The new options try to make the interface as compatible as
19359 New options (supported) are:
19361 -mcpu=<cpu name> Assemble for selected processor
19362 -march=<architecture name> Assemble for selected architecture
19363 -mfpu=<fpu architecture> Assemble for selected FPU.
19364 -EB/-mbig-endian Big-endian
19365 -EL/-mlittle-endian Little-endian
19366 -k Generate PIC code
19367 -mthumb Start in Thumb mode
19368 -mthumb-interwork Code supports ARM/Thumb interworking
19370 For now we will also provide support for:
19372 -mapcs-32 32-bit Program counter
19373 -mapcs-26 26-bit Program counter
19374 -macps-float Floats passed in FP registers
19375 -mapcs-reentrant Reentrant code
19377 (sometime these will probably be replaced with -mapcs=<list of options>
19378 and -matpcs=<list of options>)
19380 The remaining options are only supported for back-wards compatibility.
19381 Cpu variants, the arm part is optional:
19382 -m[arm]1 Currently not supported.
19383 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
19384 -m[arm]3 Arm 3 processor
19385 -m[arm]6[xx], Arm 6 processors
19386 -m[arm]7[xx][t][[d]m] Arm 7 processors
19387 -m[arm]8[10] Arm 8 processors
19388 -m[arm]9[20][tdmi] Arm 9 processors
19389 -mstrongarm[110[0]] StrongARM processors
19390 -mxscale XScale processors
19391 -m[arm]v[2345[t[e]]] Arm architectures
19392 -mall All (except the ARM1)
19394 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
19395 -mfpe-old (No float load/store multiples)
19396 -mvfpxd VFP Single precision
19398 -mno-fpu Disable all floating point instructions
19400 The following CPU names are recognized:
19401 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
19402 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
19403 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
19404 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
19405 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
19406 arm10t arm10e, arm1020t, arm1020e, arm10200e,
19407 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
19411 const char * md_shortopts
= "m:k";
19413 #ifdef ARM_BI_ENDIAN
19414 #define OPTION_EB (OPTION_MD_BASE + 0)
19415 #define OPTION_EL (OPTION_MD_BASE + 1)
19417 #if TARGET_BYTES_BIG_ENDIAN
19418 #define OPTION_EB (OPTION_MD_BASE + 0)
19420 #define OPTION_EL (OPTION_MD_BASE + 1)
19424 struct option md_longopts
[] =
19427 {"EB", no_argument
, NULL
, OPTION_EB
},
19430 {"EL", no_argument
, NULL
, OPTION_EL
},
19432 {NULL
, no_argument
, NULL
, 0}
19435 size_t md_longopts_size
= sizeof (md_longopts
);
19437 struct arm_option_table
19439 char *option
; /* Option name to match. */
19440 char *help
; /* Help information. */
19441 int *var
; /* Variable to change. */
19442 int value
; /* What to change it to. */
19443 char *deprecated
; /* If non-null, print this message. */
19446 struct arm_option_table arm_opts
[] =
19448 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
19449 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
19450 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
19451 &support_interwork
, 1, NULL
},
19452 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
19453 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
19454 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
19456 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
19457 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
19458 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
19459 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
19462 /* These are recognized by the assembler, but have no affect on code. */
19463 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
19464 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
19465 {NULL
, NULL
, NULL
, 0, NULL
}
19468 struct arm_legacy_option_table
19470 char *option
; /* Option name to match. */
19471 const arm_feature_set
**var
; /* Variable to change. */
19472 const arm_feature_set value
; /* What to change it to. */
19473 char *deprecated
; /* If non-null, print this message. */
19476 const struct arm_legacy_option_table arm_legacy_opts
[] =
19478 /* DON'T add any new processors to this list -- we want the whole list
19479 to go away... Add them to the processors table instead. */
19480 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19481 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19482 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19483 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19484 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19485 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19486 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19487 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19488 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19489 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19490 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19491 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19492 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19493 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19494 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19495 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19496 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19497 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19498 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19499 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19500 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19501 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19502 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19503 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19504 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19505 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19506 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19507 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19508 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19509 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19510 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19511 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19512 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19513 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19514 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19515 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19516 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19517 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19518 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19519 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19520 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19521 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19522 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19523 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19524 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19525 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19526 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19527 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19528 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19529 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19530 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19531 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19532 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19533 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19534 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19535 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19536 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19537 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19538 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19539 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19540 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19541 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19542 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19543 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19544 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19545 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19546 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19547 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19548 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
19549 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
19550 N_("use -mcpu=strongarm110")},
19551 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
19552 N_("use -mcpu=strongarm1100")},
19553 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
19554 N_("use -mcpu=strongarm1110")},
19555 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
19556 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
19557 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
19559 /* Architecture variants -- don't add any more to this list either. */
19560 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19561 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19562 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19563 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19564 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19565 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19566 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19567 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19568 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19569 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19570 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
19571 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
19572 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
19573 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
19574 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
19575 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
19576 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
19577 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
19579 /* Floating point variants -- don't add any more to this list either. */
19580 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
19581 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
19582 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
19583 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
19584 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
19586 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
19589 struct arm_cpu_option_table
19592 const arm_feature_set value
;
19593 /* For some CPUs we assume an FPU unless the user explicitly sets
19595 const arm_feature_set default_fpu
;
19596 /* The canonical name of the CPU, or NULL to use NAME converted to upper
19598 const char *canonical_name
;
19601 /* This list should, at a minimum, contain all the cpu names
19602 recognized by GCC. */
19603 static const struct arm_cpu_option_table arm_cpus
[] =
19605 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
19606 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
19607 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
19608 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
19609 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
19610 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19611 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19612 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19613 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19614 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19615 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19616 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
19617 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19618 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
19619 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19620 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
19621 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19622 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19623 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19624 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19625 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19626 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19627 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19628 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19629 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19630 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19631 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19632 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19633 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19634 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19635 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19636 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19637 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19638 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19639 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19640 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19641 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19642 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19643 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19644 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
19645 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19646 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19647 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19648 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19649 /* For V5 or later processors we default to using VFP; but the user
19650 should really set the FPU type explicitly. */
19651 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
19652 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19653 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
19654 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
19655 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
19656 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
19657 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
19658 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19659 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
19660 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
19661 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19662 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19663 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
19664 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
19665 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19666 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
19667 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
19668 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19669 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19670 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
19671 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
19672 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
19673 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
19674 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
19675 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
19676 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
19677 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
19678 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
19679 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
19680 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
19681 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
19682 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE(0, FPU_VFP_V3
19683 | FPU_NEON_EXT_V1
),
19685 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
19686 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
19687 /* ??? XSCALE is really an architecture. */
19688 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
19689 /* ??? iwmmxt is not a processor. */
19690 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
19691 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
19692 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
19694 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
19695 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
19698 struct arm_arch_option_table
19701 const arm_feature_set value
;
19702 const arm_feature_set default_fpu
;
19705 /* This list should, at a minimum, contain all the architecture names
19706 recognized by GCC. */
19707 static const struct arm_arch_option_table arm_archs
[] =
19709 {"all", ARM_ANY
, FPU_ARCH_FPA
},
19710 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
19711 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
19712 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
19713 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
19714 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
19715 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
19716 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
19717 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
19718 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
19719 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
19720 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
19721 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
19722 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
19723 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
19724 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
19725 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
19726 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
19727 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
19728 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
19729 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
19730 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
19731 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
19732 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
19733 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
19734 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
19735 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
19736 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
19737 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
19738 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
19739 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
19740 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
19741 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
19742 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
19745 /* ISA extensions in the co-processor space. */
19746 struct arm_option_cpu_value_table
19749 const arm_feature_set value
;
19752 static const struct arm_option_cpu_value_table arm_extensions
[] =
19754 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
19755 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
19756 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
19757 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
19758 {NULL
, ARM_ARCH_NONE
}
19761 /* This list should, at a minimum, contain all the fpu names
19762 recognized by GCC. */
19763 static const struct arm_option_cpu_value_table arm_fpus
[] =
19765 {"softfpa", FPU_NONE
},
19766 {"fpe", FPU_ARCH_FPE
},
19767 {"fpe2", FPU_ARCH_FPE
},
19768 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
19769 {"fpa", FPU_ARCH_FPA
},
19770 {"fpa10", FPU_ARCH_FPA
},
19771 {"fpa11", FPU_ARCH_FPA
},
19772 {"arm7500fe", FPU_ARCH_FPA
},
19773 {"softvfp", FPU_ARCH_VFP
},
19774 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
19775 {"vfp", FPU_ARCH_VFP_V2
},
19776 {"vfp9", FPU_ARCH_VFP_V2
},
19777 {"vfp3", FPU_ARCH_VFP_V3
},
19778 {"vfp10", FPU_ARCH_VFP_V2
},
19779 {"vfp10-r0", FPU_ARCH_VFP_V1
},
19780 {"vfpxd", FPU_ARCH_VFP_V1xD
},
19781 {"arm1020t", FPU_ARCH_VFP_V1
},
19782 {"arm1020e", FPU_ARCH_VFP_V2
},
19783 {"arm1136jfs", FPU_ARCH_VFP_V2
},
19784 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
19785 {"maverick", FPU_ARCH_MAVERICK
},
19786 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
19787 {NULL
, ARM_ARCH_NONE
}
19790 struct arm_option_value_table
19796 static const struct arm_option_value_table arm_float_abis
[] =
19798 {"hard", ARM_FLOAT_ABI_HARD
},
19799 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
19800 {"soft", ARM_FLOAT_ABI_SOFT
},
19805 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
19806 static const struct arm_option_value_table arm_eabis
[] =
19808 {"gnu", EF_ARM_EABI_UNKNOWN
},
19809 {"4", EF_ARM_EABI_VER4
},
19810 {"5", EF_ARM_EABI_VER5
},
19815 struct arm_long_option_table
19817 char * option
; /* Substring to match. */
19818 char * help
; /* Help information. */
19819 int (* func
) (char * subopt
); /* Function to decode sub-option. */
19820 char * deprecated
; /* If non-null, print this message. */
19824 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
19826 arm_feature_set
*ext_set
= xmalloc (sizeof (arm_feature_set
));
19828 /* Copy the feature set, so that we can modify it. */
19829 *ext_set
= **opt_p
;
19832 while (str
!= NULL
&& *str
!= 0)
19834 const struct arm_option_cpu_value_table
* opt
;
19840 as_bad (_("invalid architectural extension"));
19845 ext
= strchr (str
, '+');
19848 optlen
= ext
- str
;
19850 optlen
= strlen (str
);
19854 as_bad (_("missing architectural extension"));
19858 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
19859 if (strncmp (opt
->name
, str
, optlen
) == 0)
19861 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
19865 if (opt
->name
== NULL
)
19867 as_bad (_("unknown architectural extnsion `%s'"), str
);
19878 arm_parse_cpu (char * str
)
19880 const struct arm_cpu_option_table
* opt
;
19881 char * ext
= strchr (str
, '+');
19885 optlen
= ext
- str
;
19887 optlen
= strlen (str
);
19891 as_bad (_("missing cpu name `%s'"), str
);
19895 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
19896 if (strncmp (opt
->name
, str
, optlen
) == 0)
19898 mcpu_cpu_opt
= &opt
->value
;
19899 mcpu_fpu_opt
= &opt
->default_fpu
;
19900 if (opt
->canonical_name
)
19901 strcpy(selected_cpu_name
, opt
->canonical_name
);
19905 for (i
= 0; i
< optlen
; i
++)
19906 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
19907 selected_cpu_name
[i
] = 0;
19911 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
19916 as_bad (_("unknown cpu `%s'"), str
);
19921 arm_parse_arch (char * str
)
19923 const struct arm_arch_option_table
*opt
;
19924 char *ext
= strchr (str
, '+');
19928 optlen
= ext
- str
;
19930 optlen
= strlen (str
);
19934 as_bad (_("missing architecture name `%s'"), str
);
19938 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
19939 if (streq (opt
->name
, str
))
19941 march_cpu_opt
= &opt
->value
;
19942 march_fpu_opt
= &opt
->default_fpu
;
19943 strcpy(selected_cpu_name
, opt
->name
);
19946 return arm_parse_extension (ext
, &march_cpu_opt
);
19951 as_bad (_("unknown architecture `%s'\n"), str
);
19956 arm_parse_fpu (char * str
)
19958 const struct arm_option_cpu_value_table
* opt
;
19960 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
19961 if (streq (opt
->name
, str
))
19963 mfpu_opt
= &opt
->value
;
19967 as_bad (_("unknown floating point format `%s'\n"), str
);
19972 arm_parse_float_abi (char * str
)
19974 const struct arm_option_value_table
* opt
;
19976 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
19977 if (streq (opt
->name
, str
))
19979 mfloat_abi_opt
= opt
->value
;
19983 as_bad (_("unknown floating point abi `%s'\n"), str
);
19989 arm_parse_eabi (char * str
)
19991 const struct arm_option_value_table
*opt
;
19993 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
19994 if (streq (opt
->name
, str
))
19996 meabi_flags
= opt
->value
;
19999 as_bad (_("unknown EABI `%s'\n"), str
);
20004 struct arm_long_option_table arm_long_opts
[] =
20006 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
20007 arm_parse_cpu
, NULL
},
20008 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
20009 arm_parse_arch
, NULL
},
20010 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
20011 arm_parse_fpu
, NULL
},
20012 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
20013 arm_parse_float_abi
, NULL
},
20015 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
20016 arm_parse_eabi
, NULL
},
20018 {NULL
, NULL
, 0, NULL
}
20022 md_parse_option (int c
, char * arg
)
20024 struct arm_option_table
*opt
;
20025 const struct arm_legacy_option_table
*fopt
;
20026 struct arm_long_option_table
*lopt
;
20032 target_big_endian
= 1;
20038 target_big_endian
= 0;
20043 /* Listing option. Just ignore these, we don't support additional
20048 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
20050 if (c
== opt
->option
[0]
20051 && ((arg
== NULL
&& opt
->option
[1] == 0)
20052 || streq (arg
, opt
->option
+ 1)))
20054 #if WARN_DEPRECATED
20055 /* If the option is deprecated, tell the user. */
20056 if (opt
->deprecated
!= NULL
)
20057 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
20058 arg
? arg
: "", _(opt
->deprecated
));
20061 if (opt
->var
!= NULL
)
20062 *opt
->var
= opt
->value
;
20068 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
20070 if (c
== fopt
->option
[0]
20071 && ((arg
== NULL
&& fopt
->option
[1] == 0)
20072 || streq (arg
, fopt
->option
+ 1)))
20074 #if WARN_DEPRECATED
20075 /* If the option is deprecated, tell the user. */
20076 if (fopt
->deprecated
!= NULL
)
20077 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
20078 arg
? arg
: "", _(fopt
->deprecated
));
20081 if (fopt
->var
!= NULL
)
20082 *fopt
->var
= &fopt
->value
;
20088 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
20090 /* These options are expected to have an argument. */
20091 if (c
== lopt
->option
[0]
20093 && strncmp (arg
, lopt
->option
+ 1,
20094 strlen (lopt
->option
+ 1)) == 0)
20096 #if WARN_DEPRECATED
20097 /* If the option is deprecated, tell the user. */
20098 if (lopt
->deprecated
!= NULL
)
20099 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
20100 _(lopt
->deprecated
));
20103 /* Call the sup-option parser. */
20104 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
20115 md_show_usage (FILE * fp
)
20117 struct arm_option_table
*opt
;
20118 struct arm_long_option_table
*lopt
;
20120 fprintf (fp
, _(" ARM-specific assembler options:\n"));
20122 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
20123 if (opt
->help
!= NULL
)
20124 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
20126 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
20127 if (lopt
->help
!= NULL
)
20128 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
20132 -EB assemble code for a big-endian cpu\n"));
20137 -EL assemble code for a little-endian cpu\n"));
20146 arm_feature_set flags
;
20147 } cpu_arch_ver_table
;
20149 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
20150 least features first. */
20151 static const cpu_arch_ver_table cpu_arch_ver
[] =
20156 {4, ARM_ARCH_V5TE
},
20157 {5, ARM_ARCH_V5TEJ
},
20161 {9, ARM_ARCH_V6T2
},
20162 {10, ARM_ARCH_V7A
},
20163 {10, ARM_ARCH_V7R
},
20164 {10, ARM_ARCH_V7M
},
20168 /* Set the public EABI object attributes. */
20170 aeabi_set_public_attributes (void)
20173 arm_feature_set flags
;
20174 arm_feature_set tmp
;
20175 const cpu_arch_ver_table
*p
;
20177 /* Choose the architecture based on the capabilities of the requested cpu
20178 (if any) and/or the instructions actually used. */
20179 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
20180 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
20181 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
20185 for (p
= cpu_arch_ver
; p
->val
; p
++)
20187 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
20190 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
20194 /* Tag_CPU_name. */
20195 if (selected_cpu_name
[0])
20199 p
= selected_cpu_name
;
20200 if (strncmp(p
, "armv", 4) == 0)
20205 for (i
= 0; p
[i
]; i
++)
20206 p
[i
] = TOUPPER (p
[i
]);
20208 elf32_arm_add_eabi_attr_string (stdoutput
, 5, p
);
20210 /* Tag_CPU_arch. */
20211 elf32_arm_add_eabi_attr_int (stdoutput
, 6, arch
);
20212 /* Tag_CPU_arch_profile. */
20213 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
20214 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'A');
20215 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
20216 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'R');
20217 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
))
20218 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'M');
20219 /* Tag_ARM_ISA_use. */
20220 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_full
))
20221 elf32_arm_add_eabi_attr_int (stdoutput
, 8, 1);
20222 /* Tag_THUMB_ISA_use. */
20223 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_full
))
20224 elf32_arm_add_eabi_attr_int (stdoutput
, 9,
20225 ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
) ? 2 : 1);
20226 /* Tag_VFP_arch. */
20227 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v3
)
20228 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v3
))
20229 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 3);
20230 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v2
)
20231 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v2
))
20232 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 2);
20233 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1
)
20234 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1
)
20235 || ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1xd
)
20236 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1xd
))
20237 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 1);
20238 /* Tag_WMMX_arch. */
20239 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_cext_iwmmxt
)
20240 || ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_cext_iwmmxt
))
20241 elf32_arm_add_eabi_attr_int (stdoutput
, 11, 1);
20242 /* Tag_NEON_arch. */
20243 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_neon_ext_v1
)
20244 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_neon_ext_v1
))
20245 elf32_arm_add_eabi_attr_int (stdoutput
, 12, 1);
20248 /* Add the .ARM.attributes section. */
20257 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
20260 aeabi_set_public_attributes ();
20261 size
= elf32_arm_eabi_attr_size (stdoutput
);
20262 s
= subseg_new (".ARM.attributes", 0);
20263 bfd_set_section_flags (stdoutput
, s
, SEC_READONLY
| SEC_DATA
);
20264 addr
= frag_now_fix ();
20265 p
= frag_more (size
);
20266 elf32_arm_set_eabi_attr_contents (stdoutput
, (bfd_byte
*)p
, size
);
20268 #endif /* OBJ_ELF */
20271 /* Parse a .cpu directive. */
20274 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
20276 const struct arm_cpu_option_table
*opt
;
20280 name
= input_line_pointer
;
20281 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20282 input_line_pointer
++;
20283 saved_char
= *input_line_pointer
;
20284 *input_line_pointer
= 0;
20286 /* Skip the first "all" entry. */
20287 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
20288 if (streq (opt
->name
, name
))
20290 mcpu_cpu_opt
= &opt
->value
;
20291 selected_cpu
= opt
->value
;
20292 if (opt
->canonical_name
)
20293 strcpy(selected_cpu_name
, opt
->canonical_name
);
20297 for (i
= 0; opt
->name
[i
]; i
++)
20298 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20299 selected_cpu_name
[i
] = 0;
20301 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20302 *input_line_pointer
= saved_char
;
20303 demand_empty_rest_of_line ();
20306 as_bad (_("unknown cpu `%s'"), name
);
20307 *input_line_pointer
= saved_char
;
20308 ignore_rest_of_line ();
20312 /* Parse a .arch directive. */
20315 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
20317 const struct arm_arch_option_table
*opt
;
20321 name
= input_line_pointer
;
20322 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20323 input_line_pointer
++;
20324 saved_char
= *input_line_pointer
;
20325 *input_line_pointer
= 0;
20327 /* Skip the first "all" entry. */
20328 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
20329 if (streq (opt
->name
, name
))
20331 mcpu_cpu_opt
= &opt
->value
;
20332 selected_cpu
= opt
->value
;
20333 strcpy(selected_cpu_name
, opt
->name
);
20334 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20335 *input_line_pointer
= saved_char
;
20336 demand_empty_rest_of_line ();
20340 as_bad (_("unknown architecture `%s'\n"), name
);
20341 *input_line_pointer
= saved_char
;
20342 ignore_rest_of_line ();
20346 /* Parse a .fpu directive. */
20349 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
20351 const struct arm_option_cpu_value_table
*opt
;
20355 name
= input_line_pointer
;
20356 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20357 input_line_pointer
++;
20358 saved_char
= *input_line_pointer
;
20359 *input_line_pointer
= 0;
20361 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
20362 if (streq (opt
->name
, name
))
20364 mfpu_opt
= &opt
->value
;
20365 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20366 *input_line_pointer
= saved_char
;
20367 demand_empty_rest_of_line ();
20371 as_bad (_("unknown floating point format `%s'\n"), name
);
20372 *input_line_pointer
= saved_char
;
20373 ignore_rest_of_line ();