1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
);
189 static const arm_feature_set arm_ext_v6_notm
=
190 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
191 static const arm_feature_set arm_ext_v6_dsp
=
192 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
193 static const arm_feature_set arm_ext_barrier
=
194 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
195 static const arm_feature_set arm_ext_msr
=
196 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
197 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
198 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
199 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
200 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
201 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
202 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
203 static const arm_feature_set arm_ext_m
=
204 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
);
205 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
206 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
207 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
208 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
209 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
210 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
212 static const arm_feature_set arm_arch_any
= ARM_ANY
;
213 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1, -1);
214 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
215 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
216 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
218 static const arm_feature_set arm_cext_iwmmxt2
=
219 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
220 static const arm_feature_set arm_cext_iwmmxt
=
221 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
222 static const arm_feature_set arm_cext_xscale
=
223 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
224 static const arm_feature_set arm_cext_maverick
=
225 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
226 static const arm_feature_set fpu_fpa_ext_v1
=
227 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
228 static const arm_feature_set fpu_fpa_ext_v2
=
229 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
230 static const arm_feature_set fpu_vfp_ext_v1xd
=
231 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
232 static const arm_feature_set fpu_vfp_ext_v1
=
233 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
234 static const arm_feature_set fpu_vfp_ext_v2
=
235 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
236 static const arm_feature_set fpu_vfp_ext_v3xd
=
237 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
238 static const arm_feature_set fpu_vfp_ext_v3
=
239 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
240 static const arm_feature_set fpu_vfp_ext_d32
=
241 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
242 static const arm_feature_set fpu_neon_ext_v1
=
243 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
244 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
245 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
246 static const arm_feature_set fpu_vfp_fp16
=
247 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
248 static const arm_feature_set fpu_neon_ext_fma
=
249 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
250 static const arm_feature_set fpu_vfp_ext_fma
=
251 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
252 static const arm_feature_set fpu_vfp_ext_armv8
=
253 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
254 static const arm_feature_set fpu_vfp_ext_armv8xd
=
255 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
256 static const arm_feature_set fpu_neon_ext_armv8
=
257 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
258 static const arm_feature_set fpu_crypto_ext_armv8
=
259 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
260 static const arm_feature_set crc_ext_armv8
=
261 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
262 static const arm_feature_set fpu_neon_ext_v8_1
=
263 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
| FPU_NEON_EXT_RDMA
);
265 static int mfloat_abi_opt
= -1;
266 /* Record user cpu selection for object attributes. */
267 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
268 /* Must be long enough to hold any of the names in arm_cpus. */
269 static char selected_cpu_name
[16];
271 extern FLONUM_TYPE generic_floating_point_number
;
273 /* Return if no cpu was selected on command-line. */
275 no_cpu_selected (void)
277 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
282 static int meabi_flags
= EABI_DEFAULT
;
284 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
287 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
292 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
297 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
298 symbolS
* GOT_symbol
;
301 /* 0: assemble for ARM,
302 1: assemble for Thumb,
303 2: assemble for Thumb even though target CPU does not support thumb
305 static int thumb_mode
= 0;
306 /* A value distinct from the possible values for thumb_mode that we
307 can use to record whether thumb_mode has been copied into the
308 tc_frag_data field of a frag. */
309 #define MODE_RECORDED (1 << 4)
311 /* Specifies the intrinsic IT insn behavior mode. */
312 enum implicit_it_mode
314 IMPLICIT_IT_MODE_NEVER
= 0x00,
315 IMPLICIT_IT_MODE_ARM
= 0x01,
316 IMPLICIT_IT_MODE_THUMB
= 0x02,
317 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
319 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
321 /* If unified_syntax is true, we are processing the new unified
322 ARM/Thumb syntax. Important differences from the old ARM mode:
324 - Immediate operands do not require a # prefix.
325 - Conditional affixes always appear at the end of the
326 instruction. (For backward compatibility, those instructions
327 that formerly had them in the middle, continue to accept them
329 - The IT instruction may appear, and if it does is validated
330 against subsequent conditional affixes. It does not generate
333 Important differences from the old Thumb mode:
335 - Immediate operands do not require a # prefix.
336 - Most of the V6T2 instructions are only available in unified mode.
337 - The .N and .W suffixes are recognized and honored (it is an error
338 if they cannot be honored).
339 - All instructions set the flags if and only if they have an 's' affix.
340 - Conditional affixes may be used. They are validated against
341 preceding IT instructions. Unlike ARM mode, you cannot use a
342 conditional affix except in the scope of an IT instruction. */
344 static bfd_boolean unified_syntax
= FALSE
;
346 /* An immediate operand can start with #, and ld*, st*, pld operands
347 can contain [ and ]. We need to tell APP not to elide whitespace
348 before a [, which can appear as the first operand for pld.
349 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
350 const char arm_symbol_chars
[] = "#[]{}";
365 enum neon_el_type type
;
369 #define NEON_MAX_TYPE_ELS 4
373 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
377 enum it_instruction_type
382 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
383 if inside, should be the last one. */
384 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
385 i.e. BKPT and NOP. */
386 IT_INSN
/* The IT insn has been parsed. */
389 /* The maximum number of operands we need. */
390 #define ARM_IT_MAX_OPERANDS 6
395 unsigned long instruction
;
399 /* "uncond_value" is set to the value in place of the conditional field in
400 unconditional versions of the instruction, or -1 if nothing is
403 struct neon_type vectype
;
404 /* This does not indicate an actual NEON instruction, only that
405 the mnemonic accepts neon-style type suffixes. */
407 /* Set to the opcode if the instruction needs relaxation.
408 Zero if the instruction is not relaxed. */
412 bfd_reloc_code_real_type type
;
417 enum it_instruction_type it_insn_type
;
423 struct neon_type_el vectype
;
424 unsigned present
: 1; /* Operand present. */
425 unsigned isreg
: 1; /* Operand was a register. */
426 unsigned immisreg
: 1; /* .imm field is a second register. */
427 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
428 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
429 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
430 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
431 instructions. This allows us to disambiguate ARM <-> vector insns. */
432 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
433 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
434 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
435 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
436 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
437 unsigned writeback
: 1; /* Operand has trailing ! */
438 unsigned preind
: 1; /* Preindexed address. */
439 unsigned postind
: 1; /* Postindexed address. */
440 unsigned negative
: 1; /* Index register was negated. */
441 unsigned shifted
: 1; /* Shift applied to operation. */
442 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
443 } operands
[ARM_IT_MAX_OPERANDS
];
446 static struct arm_it inst
;
448 #define NUM_FLOAT_VALS 8
450 const char * fp_const
[] =
452 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
455 /* Number of littlenums required to hold an extended precision number. */
456 #define MAX_LITTLENUMS 6
458 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
468 #define CP_T_X 0x00008000
469 #define CP_T_Y 0x00400000
471 #define CONDS_BIT 0x00100000
472 #define LOAD_BIT 0x00100000
474 #define DOUBLE_LOAD_FLAG 0x00000001
478 const char * template_name
;
482 #define COND_ALWAYS 0xE
486 const char * template_name
;
490 struct asm_barrier_opt
492 const char * template_name
;
494 const arm_feature_set arch
;
497 /* The bit that distinguishes CPSR and SPSR. */
498 #define SPSR_BIT (1 << 22)
500 /* The individual PSR flag bits. */
501 #define PSR_c (1 << 16)
502 #define PSR_x (1 << 17)
503 #define PSR_s (1 << 18)
504 #define PSR_f (1 << 19)
509 bfd_reloc_code_real_type reloc
;
514 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
515 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
520 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
523 /* Bits for DEFINED field in neon_typed_alias. */
524 #define NTA_HASTYPE 1
525 #define NTA_HASINDEX 2
527 struct neon_typed_alias
529 unsigned char defined
;
531 struct neon_type_el eltype
;
534 /* ARM register categories. This includes coprocessor numbers and various
535 architecture extensions' registers. */
562 /* Structure for a hash table entry for a register.
563 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
564 information which states whether a vector type or index is specified (for a
565 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
571 unsigned char builtin
;
572 struct neon_typed_alias
* neon
;
575 /* Diagnostics used when we don't get a register of the expected type. */
576 const char * const reg_expected_msgs
[] =
578 N_("ARM register expected"),
579 N_("bad or missing co-processor number"),
580 N_("co-processor register expected"),
581 N_("FPA register expected"),
582 N_("VFP single precision register expected"),
583 N_("VFP/Neon double precision register expected"),
584 N_("Neon quad precision register expected"),
585 N_("VFP single or double precision register expected"),
586 N_("Neon double or quad precision register expected"),
587 N_("VFP single, double or Neon quad precision register expected"),
588 N_("VFP system register expected"),
589 N_("Maverick MVF register expected"),
590 N_("Maverick MVD register expected"),
591 N_("Maverick MVFX register expected"),
592 N_("Maverick MVDX register expected"),
593 N_("Maverick MVAX register expected"),
594 N_("Maverick DSPSC register expected"),
595 N_("iWMMXt data register expected"),
596 N_("iWMMXt control register expected"),
597 N_("iWMMXt scalar register expected"),
598 N_("XScale accumulator register expected"),
601 /* Some well known registers that we refer to directly elsewhere. */
607 /* ARM instructions take 4bytes in the object file, Thumb instructions
613 /* Basic string to match. */
614 const char * template_name
;
616 /* Parameters to instruction. */
617 unsigned int operands
[8];
619 /* Conditional tag - see opcode_lookup. */
620 unsigned int tag
: 4;
622 /* Basic instruction code. */
623 unsigned int avalue
: 28;
625 /* Thumb-format instruction code. */
628 /* Which architecture variant provides this instruction. */
629 const arm_feature_set
* avariant
;
630 const arm_feature_set
* tvariant
;
632 /* Function to call to encode instruction in ARM format. */
633 void (* aencode
) (void);
635 /* Function to call to encode instruction in Thumb format. */
636 void (* tencode
) (void);
639 /* Defines for various bits that we will want to toggle. */
640 #define INST_IMMEDIATE 0x02000000
641 #define OFFSET_REG 0x02000000
642 #define HWOFFSET_IMM 0x00400000
643 #define SHIFT_BY_REG 0x00000010
644 #define PRE_INDEX 0x01000000
645 #define INDEX_UP 0x00800000
646 #define WRITE_BACK 0x00200000
647 #define LDM_TYPE_2_OR_3 0x00400000
648 #define CPSI_MMOD 0x00020000
650 #define LITERAL_MASK 0xf000f000
651 #define OPCODE_MASK 0xfe1fffff
652 #define V4_STR_BIT 0x00000020
653 #define VLDR_VMOV_SAME 0x0040f000
655 #define T2_SUBS_PC_LR 0xf3de8f00
657 #define DATA_OP_SHIFT 21
659 #define T2_OPCODE_MASK 0xfe1fffff
660 #define T2_DATA_OP_SHIFT 21
662 #define A_COND_MASK 0xf0000000
663 #define A_PUSH_POP_OP_MASK 0x0fff0000
665 /* Opcodes for pushing/poping registers to/from the stack. */
666 #define A1_OPCODE_PUSH 0x092d0000
667 #define A2_OPCODE_PUSH 0x052d0004
668 #define A2_OPCODE_POP 0x049d0004
670 /* Codes to distinguish the arithmetic instructions. */
681 #define OPCODE_CMP 10
682 #define OPCODE_CMN 11
683 #define OPCODE_ORR 12
684 #define OPCODE_MOV 13
685 #define OPCODE_BIC 14
686 #define OPCODE_MVN 15
688 #define T2_OPCODE_AND 0
689 #define T2_OPCODE_BIC 1
690 #define T2_OPCODE_ORR 2
691 #define T2_OPCODE_ORN 3
692 #define T2_OPCODE_EOR 4
693 #define T2_OPCODE_ADD 8
694 #define T2_OPCODE_ADC 10
695 #define T2_OPCODE_SBC 11
696 #define T2_OPCODE_SUB 13
697 #define T2_OPCODE_RSB 14
699 #define T_OPCODE_MUL 0x4340
700 #define T_OPCODE_TST 0x4200
701 #define T_OPCODE_CMN 0x42c0
702 #define T_OPCODE_NEG 0x4240
703 #define T_OPCODE_MVN 0x43c0
705 #define T_OPCODE_ADD_R3 0x1800
706 #define T_OPCODE_SUB_R3 0x1a00
707 #define T_OPCODE_ADD_HI 0x4400
708 #define T_OPCODE_ADD_ST 0xb000
709 #define T_OPCODE_SUB_ST 0xb080
710 #define T_OPCODE_ADD_SP 0xa800
711 #define T_OPCODE_ADD_PC 0xa000
712 #define T_OPCODE_ADD_I8 0x3000
713 #define T_OPCODE_SUB_I8 0x3800
714 #define T_OPCODE_ADD_I3 0x1c00
715 #define T_OPCODE_SUB_I3 0x1e00
717 #define T_OPCODE_ASR_R 0x4100
718 #define T_OPCODE_LSL_R 0x4080
719 #define T_OPCODE_LSR_R 0x40c0
720 #define T_OPCODE_ROR_R 0x41c0
721 #define T_OPCODE_ASR_I 0x1000
722 #define T_OPCODE_LSL_I 0x0000
723 #define T_OPCODE_LSR_I 0x0800
725 #define T_OPCODE_MOV_I8 0x2000
726 #define T_OPCODE_CMP_I8 0x2800
727 #define T_OPCODE_CMP_LR 0x4280
728 #define T_OPCODE_MOV_HR 0x4600
729 #define T_OPCODE_CMP_HR 0x4500
731 #define T_OPCODE_LDR_PC 0x4800
732 #define T_OPCODE_LDR_SP 0x9800
733 #define T_OPCODE_STR_SP 0x9000
734 #define T_OPCODE_LDR_IW 0x6800
735 #define T_OPCODE_STR_IW 0x6000
736 #define T_OPCODE_LDR_IH 0x8800
737 #define T_OPCODE_STR_IH 0x8000
738 #define T_OPCODE_LDR_IB 0x7800
739 #define T_OPCODE_STR_IB 0x7000
740 #define T_OPCODE_LDR_RW 0x5800
741 #define T_OPCODE_STR_RW 0x5000
742 #define T_OPCODE_LDR_RH 0x5a00
743 #define T_OPCODE_STR_RH 0x5200
744 #define T_OPCODE_LDR_RB 0x5c00
745 #define T_OPCODE_STR_RB 0x5400
747 #define T_OPCODE_PUSH 0xb400
748 #define T_OPCODE_POP 0xbc00
750 #define T_OPCODE_BRANCH 0xe000
752 #define THUMB_SIZE 2 /* Size of thumb instruction. */
753 #define THUMB_PP_PC_LR 0x0100
754 #define THUMB_LOAD_BIT 0x0800
755 #define THUMB2_LOAD_BIT 0x00100000
757 #define BAD_ARGS _("bad arguments to instruction")
758 #define BAD_SP _("r13 not allowed here")
759 #define BAD_PC _("r15 not allowed here")
760 #define BAD_COND _("instruction cannot be conditional")
761 #define BAD_OVERLAP _("registers may not be the same")
762 #define BAD_HIREG _("lo register required")
763 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
764 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
765 #define BAD_BRANCH _("branch must be last instruction in IT block")
766 #define BAD_NOT_IT _("instruction not allowed in IT block")
767 #define BAD_FPU _("selected FPU does not support instruction")
768 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
769 #define BAD_IT_COND _("incorrect condition in IT block")
770 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
771 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
772 #define BAD_PC_ADDRESSING \
773 _("cannot use register index with PC-relative addressing")
774 #define BAD_PC_WRITEBACK \
775 _("cannot use writeback with PC-relative addressing")
776 #define BAD_RANGE _("branch out of range")
777 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
779 static struct hash_control
* arm_ops_hsh
;
780 static struct hash_control
* arm_cond_hsh
;
781 static struct hash_control
* arm_shift_hsh
;
782 static struct hash_control
* arm_psr_hsh
;
783 static struct hash_control
* arm_v7m_psr_hsh
;
784 static struct hash_control
* arm_reg_hsh
;
785 static struct hash_control
* arm_reloc_hsh
;
786 static struct hash_control
* arm_barrier_opt_hsh
;
788 /* Stuff needed to resolve the label ambiguity
797 symbolS
* last_label_seen
;
798 static int label_is_thumb_function_name
= FALSE
;
800 /* Literal pool structure. Held on a per-section
801 and per-sub-section basis. */
803 #define MAX_LITERAL_POOL_SIZE 1024
804 typedef struct literal_pool
806 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
807 unsigned int next_free_entry
;
813 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
815 struct literal_pool
* next
;
816 unsigned int alignment
;
819 /* Pointer to a linked list of literal pools. */
820 literal_pool
* list_of_pools
= NULL
;
822 typedef enum asmfunc_states
825 WAITING_ASMFUNC_NAME
,
829 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
832 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
834 static struct current_it now_it
;
838 now_it_compatible (int cond
)
840 return (cond
& ~1) == (now_it
.cc
& ~1);
844 conditional_insn (void)
846 return inst
.cond
!= COND_ALWAYS
;
849 static int in_it_block (void);
851 static int handle_it_state (void);
853 static void force_automatic_it_block_close (void);
855 static void it_fsm_post_encode (void);
857 #define set_it_insn_type(type) \
860 inst.it_insn_type = type; \
861 if (handle_it_state () == FAIL) \
866 #define set_it_insn_type_nonvoid(type, failret) \
869 inst.it_insn_type = type; \
870 if (handle_it_state () == FAIL) \
875 #define set_it_insn_type_last() \
878 if (inst.cond == COND_ALWAYS) \
879 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
881 set_it_insn_type (INSIDE_IT_LAST_INSN); \
887 /* This array holds the chars that always start a comment. If the
888 pre-processor is disabled, these aren't very useful. */
889 char arm_comment_chars
[] = "@";
891 /* This array holds the chars that only start a comment at the beginning of
892 a line. If the line seems to have the form '# 123 filename'
893 .line and .file directives will appear in the pre-processed output. */
894 /* Note that input_file.c hand checks for '#' at the beginning of the
895 first line of the input file. This is because the compiler outputs
896 #NO_APP at the beginning of its output. */
897 /* Also note that comments like this one will always work. */
898 const char line_comment_chars
[] = "#";
900 char arm_line_separator_chars
[] = ";";
902 /* Chars that can be used to separate mant
903 from exp in floating point numbers. */
904 const char EXP_CHARS
[] = "eE";
906 /* Chars that mean this number is a floating point constant. */
910 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
912 /* Prefix characters that indicate the start of an immediate
914 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
916 /* Separator character handling. */
918 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
921 skip_past_char (char ** str
, char c
)
923 /* PR gas/14987: Allow for whitespace before the expected character. */
924 skip_whitespace (*str
);
935 #define skip_past_comma(str) skip_past_char (str, ',')
937 /* Arithmetic expressions (possibly involving symbols). */
939 /* Return TRUE if anything in the expression is a bignum. */
942 walk_no_bignums (symbolS
* sp
)
944 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
947 if (symbol_get_value_expression (sp
)->X_add_symbol
)
949 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
950 || (symbol_get_value_expression (sp
)->X_op_symbol
951 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
957 static int in_my_get_expression
= 0;
959 /* Third argument to my_get_expression. */
960 #define GE_NO_PREFIX 0
961 #define GE_IMM_PREFIX 1
962 #define GE_OPT_PREFIX 2
963 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
964 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
965 #define GE_OPT_PREFIX_BIG 3
968 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
973 /* In unified syntax, all prefixes are optional. */
975 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
980 case GE_NO_PREFIX
: break;
982 if (!is_immediate_prefix (**str
))
984 inst
.error
= _("immediate expression requires a # prefix");
990 case GE_OPT_PREFIX_BIG
:
991 if (is_immediate_prefix (**str
))
997 memset (ep
, 0, sizeof (expressionS
));
999 save_in
= input_line_pointer
;
1000 input_line_pointer
= *str
;
1001 in_my_get_expression
= 1;
1002 seg
= expression (ep
);
1003 in_my_get_expression
= 0;
1005 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1007 /* We found a bad or missing expression in md_operand(). */
1008 *str
= input_line_pointer
;
1009 input_line_pointer
= save_in
;
1010 if (inst
.error
== NULL
)
1011 inst
.error
= (ep
->X_op
== O_absent
1012 ? _("missing expression") :_("bad expression"));
1017 if (seg
!= absolute_section
1018 && seg
!= text_section
1019 && seg
!= data_section
1020 && seg
!= bss_section
1021 && seg
!= undefined_section
)
1023 inst
.error
= _("bad segment");
1024 *str
= input_line_pointer
;
1025 input_line_pointer
= save_in
;
1032 /* Get rid of any bignums now, so that we don't generate an error for which
1033 we can't establish a line number later on. Big numbers are never valid
1034 in instructions, which is where this routine is always called. */
1035 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1036 && (ep
->X_op
== O_big
1037 || (ep
->X_add_symbol
1038 && (walk_no_bignums (ep
->X_add_symbol
)
1040 && walk_no_bignums (ep
->X_op_symbol
))))))
1042 inst
.error
= _("invalid constant");
1043 *str
= input_line_pointer
;
1044 input_line_pointer
= save_in
;
1048 *str
= input_line_pointer
;
1049 input_line_pointer
= save_in
;
1053 /* Turn a string in input_line_pointer into a floating point constant
1054 of type TYPE, and store the appropriate bytes in *LITP. The number
1055 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1056 returned, or NULL on OK.
1058 Note that fp constants aren't represent in the normal way on the ARM.
1059 In big endian mode, things are as expected. However, in little endian
1060 mode fp constants are big-endian word-wise, and little-endian byte-wise
1061 within the words. For example, (double) 1.1 in big endian mode is
1062 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1063 the byte sequence 99 99 f1 3f 9a 99 99 99.
1065 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1068 md_atof (int type
, char * litP
, int * sizeP
)
1071 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1103 return _("Unrecognized or unsupported floating point constant");
1106 t
= atof_ieee (input_line_pointer
, type
, words
);
1108 input_line_pointer
= t
;
1109 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1111 if (target_big_endian
)
1113 for (i
= 0; i
< prec
; i
++)
1115 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1116 litP
+= sizeof (LITTLENUM_TYPE
);
1121 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1122 for (i
= prec
- 1; i
>= 0; i
--)
1124 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1125 litP
+= sizeof (LITTLENUM_TYPE
);
1128 /* For a 4 byte float the order of elements in `words' is 1 0.
1129 For an 8 byte float the order is 1 0 3 2. */
1130 for (i
= 0; i
< prec
; i
+= 2)
1132 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1133 sizeof (LITTLENUM_TYPE
));
1134 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1135 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1136 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1143 /* We handle all bad expressions here, so that we can report the faulty
1144 instruction in the error message. */
1146 md_operand (expressionS
* exp
)
1148 if (in_my_get_expression
)
1149 exp
->X_op
= O_illegal
;
1152 /* Immediate values. */
1154 /* Generic immediate-value read function for use in directives.
1155 Accepts anything that 'expression' can fold to a constant.
1156 *val receives the number. */
1159 immediate_for_directive (int *val
)
1162 exp
.X_op
= O_illegal
;
1164 if (is_immediate_prefix (*input_line_pointer
))
1166 input_line_pointer
++;
1170 if (exp
.X_op
!= O_constant
)
1172 as_bad (_("expected #constant"));
1173 ignore_rest_of_line ();
1176 *val
= exp
.X_add_number
;
1181 /* Register parsing. */
1183 /* Generic register parser. CCP points to what should be the
1184 beginning of a register name. If it is indeed a valid register
1185 name, advance CCP over it and return the reg_entry structure;
1186 otherwise return NULL. Does not issue diagnostics. */
1188 static struct reg_entry
*
1189 arm_reg_parse_multi (char **ccp
)
1193 struct reg_entry
*reg
;
1195 skip_whitespace (start
);
1197 #ifdef REGISTER_PREFIX
1198 if (*start
!= REGISTER_PREFIX
)
1202 #ifdef OPTIONAL_REGISTER_PREFIX
1203 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1208 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1213 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1215 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1225 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1226 enum arm_reg_type type
)
1228 /* Alternative syntaxes are accepted for a few register classes. */
1235 /* Generic coprocessor register names are allowed for these. */
1236 if (reg
&& reg
->type
== REG_TYPE_CN
)
1241 /* For backward compatibility, a bare number is valid here. */
1243 unsigned long processor
= strtoul (start
, ccp
, 10);
1244 if (*ccp
!= start
&& processor
<= 15)
1248 case REG_TYPE_MMXWC
:
1249 /* WC includes WCG. ??? I'm not sure this is true for all
1250 instructions that take WC registers. */
1251 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1262 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1263 return value is the register number or FAIL. */
1266 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1269 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1272 /* Do not allow a scalar (reg+index) to parse as a register. */
1273 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1276 if (reg
&& reg
->type
== type
)
1279 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1286 /* Parse a Neon type specifier. *STR should point at the leading '.'
1287 character. Does no verification at this stage that the type fits the opcode
1294 Can all be legally parsed by this function.
1296 Fills in neon_type struct pointer with parsed information, and updates STR
1297 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1298 type, FAIL if not. */
1301 parse_neon_type (struct neon_type
*type
, char **str
)
1308 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1310 enum neon_el_type thistype
= NT_untyped
;
1311 unsigned thissize
= -1u;
1318 /* Just a size without an explicit type. */
1322 switch (TOLOWER (*ptr
))
1324 case 'i': thistype
= NT_integer
; break;
1325 case 'f': thistype
= NT_float
; break;
1326 case 'p': thistype
= NT_poly
; break;
1327 case 's': thistype
= NT_signed
; break;
1328 case 'u': thistype
= NT_unsigned
; break;
1330 thistype
= NT_float
;
1335 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1341 /* .f is an abbreviation for .f32. */
1342 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1347 thissize
= strtoul (ptr
, &ptr
, 10);
1349 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1352 as_bad (_("bad size %d in type specifier"), thissize
);
1360 type
->el
[type
->elems
].type
= thistype
;
1361 type
->el
[type
->elems
].size
= thissize
;
1366 /* Empty/missing type is not a successful parse. */
1367 if (type
->elems
== 0)
1375 /* Errors may be set multiple times during parsing or bit encoding
1376 (particularly in the Neon bits), but usually the earliest error which is set
1377 will be the most meaningful. Avoid overwriting it with later (cascading)
1378 errors by calling this function. */
1381 first_error (const char *err
)
1387 /* Parse a single type, e.g. ".s32", leading period included. */
1389 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1392 struct neon_type optype
;
1396 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1398 if (optype
.elems
== 1)
1399 *vectype
= optype
.el
[0];
1402 first_error (_("only one type should be specified for operand"));
1408 first_error (_("vector type expected"));
1420 /* Special meanings for indices (which have a range of 0-7), which will fit into
1423 #define NEON_ALL_LANES 15
1424 #define NEON_INTERLEAVE_LANES 14
1426 /* Parse either a register or a scalar, with an optional type. Return the
1427 register number, and optionally fill in the actual type of the register
1428 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1429 type/index information in *TYPEINFO. */
1432 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1433 enum arm_reg_type
*rtype
,
1434 struct neon_typed_alias
*typeinfo
)
1437 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1438 struct neon_typed_alias atype
;
1439 struct neon_type_el parsetype
;
1443 atype
.eltype
.type
= NT_invtype
;
1444 atype
.eltype
.size
= -1;
1446 /* Try alternate syntax for some types of register. Note these are mutually
1447 exclusive with the Neon syntax extensions. */
1450 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1458 /* Undo polymorphism when a set of register types may be accepted. */
1459 if ((type
== REG_TYPE_NDQ
1460 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1461 || (type
== REG_TYPE_VFSD
1462 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1463 || (type
== REG_TYPE_NSDQ
1464 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1465 || reg
->type
== REG_TYPE_NQ
))
1466 || (type
== REG_TYPE_MMXWC
1467 && (reg
->type
== REG_TYPE_MMXWCG
)))
1468 type
= (enum arm_reg_type
) reg
->type
;
1470 if (type
!= reg
->type
)
1476 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1478 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1480 first_error (_("can't redefine type for operand"));
1483 atype
.defined
|= NTA_HASTYPE
;
1484 atype
.eltype
= parsetype
;
1487 if (skip_past_char (&str
, '[') == SUCCESS
)
1489 if (type
!= REG_TYPE_VFD
)
1491 first_error (_("only D registers may be indexed"));
1495 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1497 first_error (_("can't change index for operand"));
1501 atype
.defined
|= NTA_HASINDEX
;
1503 if (skip_past_char (&str
, ']') == SUCCESS
)
1504 atype
.index
= NEON_ALL_LANES
;
1509 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1511 if (exp
.X_op
!= O_constant
)
1513 first_error (_("constant expression required"));
1517 if (skip_past_char (&str
, ']') == FAIL
)
1520 atype
.index
= exp
.X_add_number
;
1535 /* Like arm_reg_parse, but allow allow the following extra features:
1536 - If RTYPE is non-zero, return the (possibly restricted) type of the
1537 register (e.g. Neon double or quad reg when either has been requested).
1538 - If this is a Neon vector type with additional type information, fill
1539 in the struct pointed to by VECTYPE (if non-NULL).
1540 This function will fault on encountering a scalar. */
1543 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1544 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1546 struct neon_typed_alias atype
;
1548 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1553 /* Do not allow regname(... to parse as a register. */
1557 /* Do not allow a scalar (reg+index) to parse as a register. */
1558 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1560 first_error (_("register operand expected, but got scalar"));
1565 *vectype
= atype
.eltype
;
1572 #define NEON_SCALAR_REG(X) ((X) >> 4)
1573 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1575 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1576 have enough information to be able to do a good job bounds-checking. So, we
1577 just do easy checks here, and do further checks later. */
1580 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1584 struct neon_typed_alias atype
;
1586 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1588 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1591 if (atype
.index
== NEON_ALL_LANES
)
1593 first_error (_("scalar must have an index"));
1596 else if (atype
.index
>= 64 / elsize
)
1598 first_error (_("scalar index out of range"));
1603 *type
= atype
.eltype
;
1607 return reg
* 16 + atype
.index
;
1610 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1613 parse_reg_list (char ** strp
)
1615 char * str
= * strp
;
1619 /* We come back here if we get ranges concatenated by '+' or '|'. */
1622 skip_whitespace (str
);
1636 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1638 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1648 first_error (_("bad range in register list"));
1652 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1654 if (range
& (1 << i
))
1656 (_("Warning: duplicated register (r%d) in register list"),
1664 if (range
& (1 << reg
))
1665 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1667 else if (reg
<= cur_reg
)
1668 as_tsktsk (_("Warning: register range not in ascending order"));
1673 while (skip_past_comma (&str
) != FAIL
1674 || (in_range
= 1, *str
++ == '-'));
1677 if (skip_past_char (&str
, '}') == FAIL
)
1679 first_error (_("missing `}'"));
1687 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1690 if (exp
.X_op
== O_constant
)
1692 if (exp
.X_add_number
1693 != (exp
.X_add_number
& 0x0000ffff))
1695 inst
.error
= _("invalid register mask");
1699 if ((range
& exp
.X_add_number
) != 0)
1701 int regno
= range
& exp
.X_add_number
;
1704 regno
= (1 << regno
) - 1;
1706 (_("Warning: duplicated register (r%d) in register list"),
1710 range
|= exp
.X_add_number
;
1714 if (inst
.reloc
.type
!= 0)
1716 inst
.error
= _("expression too complex");
1720 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1721 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1722 inst
.reloc
.pc_rel
= 0;
1726 if (*str
== '|' || *str
== '+')
1732 while (another_range
);
1738 /* Types of registers in a list. */
1747 /* Parse a VFP register list. If the string is invalid return FAIL.
1748 Otherwise return the number of registers, and set PBASE to the first
1749 register. Parses registers of type ETYPE.
1750 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1751 - Q registers can be used to specify pairs of D registers
1752 - { } can be omitted from around a singleton register list
1753 FIXME: This is not implemented, as it would require backtracking in
1756 This could be done (the meaning isn't really ambiguous), but doesn't
1757 fit in well with the current parsing framework.
1758 - 32 D registers may be used (also true for VFPv3).
1759 FIXME: Types are ignored in these register lists, which is probably a
1763 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1768 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1772 unsigned long mask
= 0;
1775 if (skip_past_char (&str
, '{') == FAIL
)
1777 inst
.error
= _("expecting {");
1784 regtype
= REG_TYPE_VFS
;
1789 regtype
= REG_TYPE_VFD
;
1792 case REGLIST_NEON_D
:
1793 regtype
= REG_TYPE_NDQ
;
1797 if (etype
!= REGLIST_VFP_S
)
1799 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1800 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1804 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1807 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1814 base_reg
= max_regs
;
1818 int setmask
= 1, addregs
= 1;
1820 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1822 if (new_base
== FAIL
)
1824 first_error (_(reg_expected_msgs
[regtype
]));
1828 if (new_base
>= max_regs
)
1830 first_error (_("register out of range in list"));
1834 /* Note: a value of 2 * n is returned for the register Q<n>. */
1835 if (regtype
== REG_TYPE_NQ
)
1841 if (new_base
< base_reg
)
1842 base_reg
= new_base
;
1844 if (mask
& (setmask
<< new_base
))
1846 first_error (_("invalid register list"));
1850 if ((mask
>> new_base
) != 0 && ! warned
)
1852 as_tsktsk (_("register list not in ascending order"));
1856 mask
|= setmask
<< new_base
;
1859 if (*str
== '-') /* We have the start of a range expression */
1865 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1868 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1872 if (high_range
>= max_regs
)
1874 first_error (_("register out of range in list"));
1878 if (regtype
== REG_TYPE_NQ
)
1879 high_range
= high_range
+ 1;
1881 if (high_range
<= new_base
)
1883 inst
.error
= _("register range not in ascending order");
1887 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1889 if (mask
& (setmask
<< new_base
))
1891 inst
.error
= _("invalid register list");
1895 mask
|= setmask
<< new_base
;
1900 while (skip_past_comma (&str
) != FAIL
);
1904 /* Sanity check -- should have raised a parse error above. */
1905 if (count
== 0 || count
> max_regs
)
1910 /* Final test -- the registers must be consecutive. */
1912 for (i
= 0; i
< count
; i
++)
1914 if ((mask
& (1u << i
)) == 0)
1916 inst
.error
= _("non-contiguous register range");
1926 /* True if two alias types are the same. */
1929 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1937 if (a
->defined
!= b
->defined
)
1940 if ((a
->defined
& NTA_HASTYPE
) != 0
1941 && (a
->eltype
.type
!= b
->eltype
.type
1942 || a
->eltype
.size
!= b
->eltype
.size
))
1945 if ((a
->defined
& NTA_HASINDEX
) != 0
1946 && (a
->index
!= b
->index
))
1952 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1953 The base register is put in *PBASE.
1954 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1956 The register stride (minus one) is put in bit 4 of the return value.
1957 Bits [6:5] encode the list length (minus one).
1958 The type of the list elements is put in *ELTYPE, if non-NULL. */
1960 #define NEON_LANE(X) ((X) & 0xf)
1961 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1962 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1965 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1966 struct neon_type_el
*eltype
)
1973 int leading_brace
= 0;
1974 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1975 const char *const incr_error
= _("register stride must be 1 or 2");
1976 const char *const type_error
= _("mismatched element/structure types in list");
1977 struct neon_typed_alias firsttype
;
1979 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1984 struct neon_typed_alias atype
;
1985 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1989 first_error (_(reg_expected_msgs
[rtype
]));
1996 if (rtype
== REG_TYPE_NQ
)
2002 else if (reg_incr
== -1)
2004 reg_incr
= getreg
- base_reg
;
2005 if (reg_incr
< 1 || reg_incr
> 2)
2007 first_error (_(incr_error
));
2011 else if (getreg
!= base_reg
+ reg_incr
* count
)
2013 first_error (_(incr_error
));
2017 if (! neon_alias_types_same (&atype
, &firsttype
))
2019 first_error (_(type_error
));
2023 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2027 struct neon_typed_alias htype
;
2028 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2030 lane
= NEON_INTERLEAVE_LANES
;
2031 else if (lane
!= NEON_INTERLEAVE_LANES
)
2033 first_error (_(type_error
));
2038 else if (reg_incr
!= 1)
2040 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2044 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2047 first_error (_(reg_expected_msgs
[rtype
]));
2050 if (! neon_alias_types_same (&htype
, &firsttype
))
2052 first_error (_(type_error
));
2055 count
+= hireg
+ dregs
- getreg
;
2059 /* If we're using Q registers, we can't use [] or [n] syntax. */
2060 if (rtype
== REG_TYPE_NQ
)
2066 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2070 else if (lane
!= atype
.index
)
2072 first_error (_(type_error
));
2076 else if (lane
== -1)
2077 lane
= NEON_INTERLEAVE_LANES
;
2078 else if (lane
!= NEON_INTERLEAVE_LANES
)
2080 first_error (_(type_error
));
2085 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2087 /* No lane set by [x]. We must be interleaving structures. */
2089 lane
= NEON_INTERLEAVE_LANES
;
2092 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2093 || (count
> 1 && reg_incr
== -1))
2095 first_error (_("error parsing element/structure list"));
2099 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2101 first_error (_("expected }"));
2109 *eltype
= firsttype
.eltype
;
2114 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2117 /* Parse an explicit relocation suffix on an expression. This is
2118 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2119 arm_reloc_hsh contains no entries, so this function can only
2120 succeed if there is no () after the word. Returns -1 on error,
2121 BFD_RELOC_UNUSED if there wasn't any suffix. */
2124 parse_reloc (char **str
)
2126 struct reloc_entry
*r
;
2130 return BFD_RELOC_UNUSED
;
2135 while (*q
&& *q
!= ')' && *q
!= ',')
2140 if ((r
= (struct reloc_entry
*)
2141 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2148 /* Directives: register aliases. */
2150 static struct reg_entry
*
2151 insert_reg_alias (char *str
, unsigned number
, int type
)
2153 struct reg_entry
*new_reg
;
2156 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2158 if (new_reg
->builtin
)
2159 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2161 /* Only warn about a redefinition if it's not defined as the
2163 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2164 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2169 name
= xstrdup (str
);
2170 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2172 new_reg
->name
= name
;
2173 new_reg
->number
= number
;
2174 new_reg
->type
= type
;
2175 new_reg
->builtin
= FALSE
;
2176 new_reg
->neon
= NULL
;
2178 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2185 insert_neon_reg_alias (char *str
, int number
, int type
,
2186 struct neon_typed_alias
*atype
)
2188 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2192 first_error (_("attempt to redefine typed alias"));
2198 reg
->neon
= (struct neon_typed_alias
*)
2199 xmalloc (sizeof (struct neon_typed_alias
));
2200 *reg
->neon
= *atype
;
2204 /* Look for the .req directive. This is of the form:
2206 new_register_name .req existing_register_name
2208 If we find one, or if it looks sufficiently like one that we want to
2209 handle any error here, return TRUE. Otherwise return FALSE. */
2212 create_register_alias (char * newname
, char *p
)
2214 struct reg_entry
*old
;
2215 char *oldname
, *nbuf
;
2218 /* The input scrubber ensures that whitespace after the mnemonic is
2219 collapsed to single spaces. */
2221 if (strncmp (oldname
, " .req ", 6) != 0)
2225 if (*oldname
== '\0')
2228 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2231 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2235 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2236 the desired alias name, and p points to its end. If not, then
2237 the desired alias name is in the global original_case_string. */
2238 #ifdef TC_CASE_SENSITIVE
2241 newname
= original_case_string
;
2242 nlen
= strlen (newname
);
2245 nbuf
= (char *) alloca (nlen
+ 1);
2246 memcpy (nbuf
, newname
, nlen
);
2249 /* Create aliases under the new name as stated; an all-lowercase
2250 version of the new name; and an all-uppercase version of the new
2252 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2254 for (p
= nbuf
; *p
; p
++)
2257 if (strncmp (nbuf
, newname
, nlen
))
2259 /* If this attempt to create an additional alias fails, do not bother
2260 trying to create the all-lower case alias. We will fail and issue
2261 a second, duplicate error message. This situation arises when the
2262 programmer does something like:
2265 The second .req creates the "Foo" alias but then fails to create
2266 the artificial FOO alias because it has already been created by the
2268 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2272 for (p
= nbuf
; *p
; p
++)
2275 if (strncmp (nbuf
, newname
, nlen
))
2276 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2282 /* Create a Neon typed/indexed register alias using directives, e.g.:
2287 These typed registers can be used instead of the types specified after the
2288 Neon mnemonic, so long as all operands given have types. Types can also be
2289 specified directly, e.g.:
2290 vadd d0.s32, d1.s32, d2.s32 */
2293 create_neon_reg_alias (char *newname
, char *p
)
2295 enum arm_reg_type basetype
;
2296 struct reg_entry
*basereg
;
2297 struct reg_entry mybasereg
;
2298 struct neon_type ntype
;
2299 struct neon_typed_alias typeinfo
;
2300 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2303 typeinfo
.defined
= 0;
2304 typeinfo
.eltype
.type
= NT_invtype
;
2305 typeinfo
.eltype
.size
= -1;
2306 typeinfo
.index
= -1;
2310 if (strncmp (p
, " .dn ", 5) == 0)
2311 basetype
= REG_TYPE_VFD
;
2312 else if (strncmp (p
, " .qn ", 5) == 0)
2313 basetype
= REG_TYPE_NQ
;
2322 basereg
= arm_reg_parse_multi (&p
);
2324 if (basereg
&& basereg
->type
!= basetype
)
2326 as_bad (_("bad type for register"));
2330 if (basereg
== NULL
)
2333 /* Try parsing as an integer. */
2334 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2335 if (exp
.X_op
!= O_constant
)
2337 as_bad (_("expression must be constant"));
2340 basereg
= &mybasereg
;
2341 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2347 typeinfo
= *basereg
->neon
;
2349 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2351 /* We got a type. */
2352 if (typeinfo
.defined
& NTA_HASTYPE
)
2354 as_bad (_("can't redefine the type of a register alias"));
2358 typeinfo
.defined
|= NTA_HASTYPE
;
2359 if (ntype
.elems
!= 1)
2361 as_bad (_("you must specify a single type only"));
2364 typeinfo
.eltype
= ntype
.el
[0];
2367 if (skip_past_char (&p
, '[') == SUCCESS
)
2370 /* We got a scalar index. */
2372 if (typeinfo
.defined
& NTA_HASINDEX
)
2374 as_bad (_("can't redefine the index of a scalar alias"));
2378 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2380 if (exp
.X_op
!= O_constant
)
2382 as_bad (_("scalar index must be constant"));
2386 typeinfo
.defined
|= NTA_HASINDEX
;
2387 typeinfo
.index
= exp
.X_add_number
;
2389 if (skip_past_char (&p
, ']') == FAIL
)
2391 as_bad (_("expecting ]"));
2396 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2397 the desired alias name, and p points to its end. If not, then
2398 the desired alias name is in the global original_case_string. */
2399 #ifdef TC_CASE_SENSITIVE
2400 namelen
= nameend
- newname
;
2402 newname
= original_case_string
;
2403 namelen
= strlen (newname
);
2406 namebuf
= (char *) alloca (namelen
+ 1);
2407 strncpy (namebuf
, newname
, namelen
);
2408 namebuf
[namelen
] = '\0';
2410 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2411 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2413 /* Insert name in all uppercase. */
2414 for (p
= namebuf
; *p
; p
++)
2417 if (strncmp (namebuf
, newname
, namelen
))
2418 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2419 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2421 /* Insert name in all lowercase. */
2422 for (p
= namebuf
; *p
; p
++)
2425 if (strncmp (namebuf
, newname
, namelen
))
2426 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2427 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2432 /* Should never be called, as .req goes between the alias and the
2433 register name, not at the beginning of the line. */
2436 s_req (int a ATTRIBUTE_UNUSED
)
2438 as_bad (_("invalid syntax for .req directive"));
2442 s_dn (int a ATTRIBUTE_UNUSED
)
2444 as_bad (_("invalid syntax for .dn directive"));
2448 s_qn (int a ATTRIBUTE_UNUSED
)
2450 as_bad (_("invalid syntax for .qn directive"));
2453 /* The .unreq directive deletes an alias which was previously defined
2454 by .req. For example:
2460 s_unreq (int a ATTRIBUTE_UNUSED
)
2465 name
= input_line_pointer
;
2467 while (*input_line_pointer
!= 0
2468 && *input_line_pointer
!= ' '
2469 && *input_line_pointer
!= '\n')
2470 ++input_line_pointer
;
2472 saved_char
= *input_line_pointer
;
2473 *input_line_pointer
= 0;
2476 as_bad (_("invalid syntax for .unreq directive"));
2479 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2483 as_bad (_("unknown register alias '%s'"), name
);
2484 else if (reg
->builtin
)
2485 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2492 hash_delete (arm_reg_hsh
, name
, FALSE
);
2493 free ((char *) reg
->name
);
2498 /* Also locate the all upper case and all lower case versions.
2499 Do not complain if we cannot find one or the other as it
2500 was probably deleted above. */
2502 nbuf
= strdup (name
);
2503 for (p
= nbuf
; *p
; p
++)
2505 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2508 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2509 free ((char *) reg
->name
);
2515 for (p
= nbuf
; *p
; p
++)
2517 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2520 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2521 free ((char *) reg
->name
);
2531 *input_line_pointer
= saved_char
;
2532 demand_empty_rest_of_line ();
2535 /* Directives: Instruction set selection. */
2538 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2539 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2540 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2541 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2543 /* Create a new mapping symbol for the transition to STATE. */
2546 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2549 const char * symname
;
2556 type
= BSF_NO_FLAGS
;
2560 type
= BSF_NO_FLAGS
;
2564 type
= BSF_NO_FLAGS
;
2570 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2571 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2576 THUMB_SET_FUNC (symbolP
, 0);
2577 ARM_SET_THUMB (symbolP
, 0);
2578 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2582 THUMB_SET_FUNC (symbolP
, 1);
2583 ARM_SET_THUMB (symbolP
, 1);
2584 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2592 /* Save the mapping symbols for future reference. Also check that
2593 we do not place two mapping symbols at the same offset within a
2594 frag. We'll handle overlap between frags in
2595 check_mapping_symbols.
2597 If .fill or other data filling directive generates zero sized data,
2598 the mapping symbol for the following code will have the same value
2599 as the one generated for the data filling directive. In this case,
2600 we replace the old symbol with the new one at the same address. */
2603 if (frag
->tc_frag_data
.first_map
!= NULL
)
2605 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2606 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2608 frag
->tc_frag_data
.first_map
= symbolP
;
2610 if (frag
->tc_frag_data
.last_map
!= NULL
)
2612 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2613 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2614 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2616 frag
->tc_frag_data
.last_map
= symbolP
;
2619 /* We must sometimes convert a region marked as code to data during
2620 code alignment, if an odd number of bytes have to be padded. The
2621 code mapping symbol is pushed to an aligned address. */
2624 insert_data_mapping_symbol (enum mstate state
,
2625 valueT value
, fragS
*frag
, offsetT bytes
)
2627 /* If there was already a mapping symbol, remove it. */
2628 if (frag
->tc_frag_data
.last_map
!= NULL
2629 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2631 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2635 know (frag
->tc_frag_data
.first_map
== symp
);
2636 frag
->tc_frag_data
.first_map
= NULL
;
2638 frag
->tc_frag_data
.last_map
= NULL
;
2639 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2642 make_mapping_symbol (MAP_DATA
, value
, frag
);
2643 make_mapping_symbol (state
, value
+ bytes
, frag
);
2646 static void mapping_state_2 (enum mstate state
, int max_chars
);
2648 /* Set the mapping state to STATE. Only call this when about to
2649 emit some STATE bytes to the file. */
2651 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2653 mapping_state (enum mstate state
)
2655 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2657 if (mapstate
== state
)
2658 /* The mapping symbol has already been emitted.
2659 There is nothing else to do. */
2662 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2664 All ARM instructions require 4-byte alignment.
2665 (Almost) all Thumb instructions require 2-byte alignment.
2667 When emitting instructions into any section, mark the section
2670 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2671 but themselves require 2-byte alignment; this applies to some
2672 PC- relative forms. However, these cases will invovle implicit
2673 literal pool generation or an explicit .align >=2, both of
2674 which will cause the section to me marked with sufficient
2675 alignment. Thus, we don't handle those cases here. */
2676 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2678 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2679 /* This case will be evaluated later. */
2682 mapping_state_2 (state
, 0);
2685 /* Same as mapping_state, but MAX_CHARS bytes have already been
2686 allocated. Put the mapping symbol that far back. */
2689 mapping_state_2 (enum mstate state
, int max_chars
)
2691 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2693 if (!SEG_NORMAL (now_seg
))
2696 if (mapstate
== state
)
2697 /* The mapping symbol has already been emitted.
2698 There is nothing else to do. */
2701 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2702 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2704 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2705 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2708 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2711 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2712 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2716 #define mapping_state(x) ((void)0)
2717 #define mapping_state_2(x, y) ((void)0)
2720 /* Find the real, Thumb encoded start of a Thumb function. */
2724 find_real_start (symbolS
* symbolP
)
2727 const char * name
= S_GET_NAME (symbolP
);
2728 symbolS
* new_target
;
2730 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2731 #define STUB_NAME ".real_start_of"
2736 /* The compiler may generate BL instructions to local labels because
2737 it needs to perform a branch to a far away location. These labels
2738 do not have a corresponding ".real_start_of" label. We check
2739 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2740 the ".real_start_of" convention for nonlocal branches. */
2741 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2744 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2745 new_target
= symbol_find (real_start
);
2747 if (new_target
== NULL
)
2749 as_warn (_("Failed to find real start of function: %s\n"), name
);
2750 new_target
= symbolP
;
2758 opcode_select (int width
)
2765 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2766 as_bad (_("selected processor does not support THUMB opcodes"));
2769 /* No need to force the alignment, since we will have been
2770 coming from ARM mode, which is word-aligned. */
2771 record_alignment (now_seg
, 1);
2778 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2779 as_bad (_("selected processor does not support ARM opcodes"));
2784 frag_align (2, 0, 0);
2786 record_alignment (now_seg
, 1);
2791 as_bad (_("invalid instruction size selected (%d)"), width
);
2796 s_arm (int ignore ATTRIBUTE_UNUSED
)
2799 demand_empty_rest_of_line ();
2803 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2806 demand_empty_rest_of_line ();
2810 s_code (int unused ATTRIBUTE_UNUSED
)
2814 temp
= get_absolute_expression ();
2819 opcode_select (temp
);
2823 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2828 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2830 /* If we are not already in thumb mode go into it, EVEN if
2831 the target processor does not support thumb instructions.
2832 This is used by gcc/config/arm/lib1funcs.asm for example
2833 to compile interworking support functions even if the
2834 target processor should not support interworking. */
2838 record_alignment (now_seg
, 1);
2841 demand_empty_rest_of_line ();
2845 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2849 /* The following label is the name/address of the start of a Thumb function.
2850 We need to know this for the interworking support. */
2851 label_is_thumb_function_name
= TRUE
;
2854 /* Perform a .set directive, but also mark the alias as
2855 being a thumb function. */
2858 s_thumb_set (int equiv
)
2860 /* XXX the following is a duplicate of the code for s_set() in read.c
2861 We cannot just call that code as we need to get at the symbol that
2868 /* Especial apologies for the random logic:
2869 This just grew, and could be parsed much more simply!
2871 name
= input_line_pointer
;
2872 delim
= get_symbol_end ();
2873 end_name
= input_line_pointer
;
2876 if (*input_line_pointer
!= ',')
2879 as_bad (_("expected comma after name \"%s\""), name
);
2881 ignore_rest_of_line ();
2885 input_line_pointer
++;
2888 if (name
[0] == '.' && name
[1] == '\0')
2890 /* XXX - this should not happen to .thumb_set. */
2894 if ((symbolP
= symbol_find (name
)) == NULL
2895 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2898 /* When doing symbol listings, play games with dummy fragments living
2899 outside the normal fragment chain to record the file and line info
2901 if (listing
& LISTING_SYMBOLS
)
2903 extern struct list_info_struct
* listing_tail
;
2904 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2906 memset (dummy_frag
, 0, sizeof (fragS
));
2907 dummy_frag
->fr_type
= rs_fill
;
2908 dummy_frag
->line
= listing_tail
;
2909 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2910 dummy_frag
->fr_symbol
= symbolP
;
2914 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2917 /* "set" symbols are local unless otherwise specified. */
2918 SF_SET_LOCAL (symbolP
);
2919 #endif /* OBJ_COFF */
2920 } /* Make a new symbol. */
2922 symbol_table_insert (symbolP
);
2927 && S_IS_DEFINED (symbolP
)
2928 && S_GET_SEGMENT (symbolP
) != reg_section
)
2929 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2931 pseudo_set (symbolP
);
2933 demand_empty_rest_of_line ();
2935 /* XXX Now we come to the Thumb specific bit of code. */
2937 THUMB_SET_FUNC (symbolP
, 1);
2938 ARM_SET_THUMB (symbolP
, 1);
2939 #if defined OBJ_ELF || defined OBJ_COFF
2940 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2944 /* Directives: Mode selection. */
2946 /* .syntax [unified|divided] - choose the new unified syntax
2947 (same for Arm and Thumb encoding, modulo slight differences in what
2948 can be represented) or the old divergent syntax for each mode. */
2950 s_syntax (int unused ATTRIBUTE_UNUSED
)
2954 name
= input_line_pointer
;
2955 delim
= get_symbol_end ();
2957 if (!strcasecmp (name
, "unified"))
2958 unified_syntax
= TRUE
;
2959 else if (!strcasecmp (name
, "divided"))
2960 unified_syntax
= FALSE
;
2963 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2966 *input_line_pointer
= delim
;
2967 demand_empty_rest_of_line ();
2970 /* Directives: sectioning and alignment. */
2973 s_bss (int ignore ATTRIBUTE_UNUSED
)
2975 /* We don't support putting frags in the BSS segment, we fake it by
2976 marking in_bss, then looking at s_skip for clues. */
2977 subseg_set (bss_section
, 0);
2978 demand_empty_rest_of_line ();
2980 #ifdef md_elf_section_change_hook
2981 md_elf_section_change_hook ();
2986 s_even (int ignore ATTRIBUTE_UNUSED
)
2988 /* Never make frag if expect extra pass. */
2990 frag_align (1, 0, 0);
2992 record_alignment (now_seg
, 1);
2994 demand_empty_rest_of_line ();
2997 /* Directives: CodeComposer Studio. */
2999 /* .ref (for CodeComposer Studio syntax only). */
3001 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3003 if (codecomposer_syntax
)
3004 ignore_rest_of_line ();
3006 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3009 /* If name is not NULL, then it is used for marking the beginning of a
3010 function, wherease if it is NULL then it means the function end. */
3012 asmfunc_debug (const char * name
)
3014 static const char * last_name
= NULL
;
3018 gas_assert (last_name
== NULL
);
3021 if (debug_type
== DEBUG_STABS
)
3022 stabs_generate_asm_func (name
, name
);
3026 gas_assert (last_name
!= NULL
);
3028 if (debug_type
== DEBUG_STABS
)
3029 stabs_generate_asm_endfunc (last_name
, last_name
);
3036 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3038 if (codecomposer_syntax
)
3040 switch (asmfunc_state
)
3042 case OUTSIDE_ASMFUNC
:
3043 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3046 case WAITING_ASMFUNC_NAME
:
3047 as_bad (_(".asmfunc repeated."));
3050 case WAITING_ENDASMFUNC
:
3051 as_bad (_(".asmfunc without function."));
3054 demand_empty_rest_of_line ();
3057 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3061 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3063 if (codecomposer_syntax
)
3065 switch (asmfunc_state
)
3067 case OUTSIDE_ASMFUNC
:
3068 as_bad (_(".endasmfunc without a .asmfunc."));
3071 case WAITING_ASMFUNC_NAME
:
3072 as_bad (_(".endasmfunc without function."));
3075 case WAITING_ENDASMFUNC
:
3076 asmfunc_state
= OUTSIDE_ASMFUNC
;
3077 asmfunc_debug (NULL
);
3080 demand_empty_rest_of_line ();
3083 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3087 s_ccs_def (int name
)
3089 if (codecomposer_syntax
)
3092 as_bad (_(".def pseudo-op only available with -mccs flag."));
3095 /* Directives: Literal pools. */
3097 static literal_pool
*
3098 find_literal_pool (void)
3100 literal_pool
* pool
;
3102 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3104 if (pool
->section
== now_seg
3105 && pool
->sub_section
== now_subseg
)
3112 static literal_pool
*
3113 find_or_make_literal_pool (void)
3115 /* Next literal pool ID number. */
3116 static unsigned int latest_pool_num
= 1;
3117 literal_pool
* pool
;
3119 pool
= find_literal_pool ();
3123 /* Create a new pool. */
3124 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
3128 pool
->next_free_entry
= 0;
3129 pool
->section
= now_seg
;
3130 pool
->sub_section
= now_subseg
;
3131 pool
->next
= list_of_pools
;
3132 pool
->symbol
= NULL
;
3133 pool
->alignment
= 2;
3135 /* Add it to the list. */
3136 list_of_pools
= pool
;
3139 /* New pools, and emptied pools, will have a NULL symbol. */
3140 if (pool
->symbol
== NULL
)
3142 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3143 (valueT
) 0, &zero_address_frag
);
3144 pool
->id
= latest_pool_num
++;
3151 /* Add the literal in the global 'inst'
3152 structure to the relevant literal pool. */
3155 add_to_lit_pool (unsigned int nbytes
)
3157 #define PADDING_SLOT 0x1
3158 #define LIT_ENTRY_SIZE_MASK 0xFF
3159 literal_pool
* pool
;
3160 unsigned int entry
, pool_size
= 0;
3161 bfd_boolean padding_slot_p
= FALSE
;
3167 imm1
= inst
.operands
[1].imm
;
3168 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3169 : inst
.reloc
.exp
.X_unsigned
? 0
3170 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3171 if (target_big_endian
)
3174 imm2
= inst
.operands
[1].imm
;
3178 pool
= find_or_make_literal_pool ();
3180 /* Check if this literal value is already in the pool. */
3181 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3185 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3186 && (inst
.reloc
.exp
.X_op
== O_constant
)
3187 && (pool
->literals
[entry
].X_add_number
3188 == inst
.reloc
.exp
.X_add_number
)
3189 && (pool
->literals
[entry
].X_md
== nbytes
)
3190 && (pool
->literals
[entry
].X_unsigned
3191 == inst
.reloc
.exp
.X_unsigned
))
3194 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3195 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3196 && (pool
->literals
[entry
].X_add_number
3197 == inst
.reloc
.exp
.X_add_number
)
3198 && (pool
->literals
[entry
].X_add_symbol
3199 == inst
.reloc
.exp
.X_add_symbol
)
3200 && (pool
->literals
[entry
].X_op_symbol
3201 == inst
.reloc
.exp
.X_op_symbol
)
3202 && (pool
->literals
[entry
].X_md
== nbytes
))
3205 else if ((nbytes
== 8)
3206 && !(pool_size
& 0x7)
3207 && ((entry
+ 1) != pool
->next_free_entry
)
3208 && (pool
->literals
[entry
].X_op
== O_constant
)
3209 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3210 && (pool
->literals
[entry
].X_unsigned
3211 == inst
.reloc
.exp
.X_unsigned
)
3212 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3213 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3214 && (pool
->literals
[entry
+ 1].X_unsigned
3215 == inst
.reloc
.exp
.X_unsigned
))
3218 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3219 if (padding_slot_p
&& (nbytes
== 4))
3225 /* Do we need to create a new entry? */
3226 if (entry
== pool
->next_free_entry
)
3228 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3230 inst
.error
= _("literal pool overflow");
3236 /* For 8-byte entries, we align to an 8-byte boundary,
3237 and split it into two 4-byte entries, because on 32-bit
3238 host, 8-byte constants are treated as big num, thus
3239 saved in "generic_bignum" which will be overwritten
3240 by later assignments.
3242 We also need to make sure there is enough space for
3245 We also check to make sure the literal operand is a
3247 if (!(inst
.reloc
.exp
.X_op
== O_constant
3248 || inst
.reloc
.exp
.X_op
== O_big
))
3250 inst
.error
= _("invalid type for literal pool");
3253 else if (pool_size
& 0x7)
3255 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3257 inst
.error
= _("literal pool overflow");
3261 pool
->literals
[entry
] = inst
.reloc
.exp
;
3262 pool
->literals
[entry
].X_add_number
= 0;
3263 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3264 pool
->next_free_entry
+= 1;
3267 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3269 inst
.error
= _("literal pool overflow");
3273 pool
->literals
[entry
] = inst
.reloc
.exp
;
3274 pool
->literals
[entry
].X_op
= O_constant
;
3275 pool
->literals
[entry
].X_add_number
= imm1
;
3276 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3277 pool
->literals
[entry
++].X_md
= 4;
3278 pool
->literals
[entry
] = inst
.reloc
.exp
;
3279 pool
->literals
[entry
].X_op
= O_constant
;
3280 pool
->literals
[entry
].X_add_number
= imm2
;
3281 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3282 pool
->literals
[entry
].X_md
= 4;
3283 pool
->alignment
= 3;
3284 pool
->next_free_entry
+= 1;
3288 pool
->literals
[entry
] = inst
.reloc
.exp
;
3289 pool
->literals
[entry
].X_md
= 4;
3293 /* PR ld/12974: Record the location of the first source line to reference
3294 this entry in the literal pool. If it turns out during linking that the
3295 symbol does not exist we will be able to give an accurate line number for
3296 the (first use of the) missing reference. */
3297 if (debug_type
== DEBUG_DWARF2
)
3298 dwarf2_where (pool
->locs
+ entry
);
3300 pool
->next_free_entry
+= 1;
3302 else if (padding_slot_p
)
3304 pool
->literals
[entry
] = inst
.reloc
.exp
;
3305 pool
->literals
[entry
].X_md
= nbytes
;
3308 inst
.reloc
.exp
.X_op
= O_symbol
;
3309 inst
.reloc
.exp
.X_add_number
= pool_size
;
3310 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3316 tc_start_label_without_colon (char unused1 ATTRIBUTE_UNUSED
, const char * rest
)
3318 bfd_boolean ret
= TRUE
;
3320 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3322 const char *label
= rest
;
3324 while (!is_end_of_line
[(int) label
[-1]])
3329 as_bad (_("Invalid label '%s'"), label
);
3333 asmfunc_debug (label
);
3335 asmfunc_state
= WAITING_ENDASMFUNC
;
3341 /* Can't use symbol_new here, so have to create a symbol and then at
3342 a later date assign it a value. Thats what these functions do. */
3345 symbol_locate (symbolS
* symbolP
,
3346 const char * name
, /* It is copied, the caller can modify. */
3347 segT segment
, /* Segment identifier (SEG_<something>). */
3348 valueT valu
, /* Symbol value. */
3349 fragS
* frag
) /* Associated fragment. */
3352 char * preserved_copy_of_name
;
3354 name_length
= strlen (name
) + 1; /* +1 for \0. */
3355 obstack_grow (¬es
, name
, name_length
);
3356 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3358 #ifdef tc_canonicalize_symbol_name
3359 preserved_copy_of_name
=
3360 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3363 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3365 S_SET_SEGMENT (symbolP
, segment
);
3366 S_SET_VALUE (symbolP
, valu
);
3367 symbol_clear_list_pointers (symbolP
);
3369 symbol_set_frag (symbolP
, frag
);
3371 /* Link to end of symbol chain. */
3373 extern int symbol_table_frozen
;
3375 if (symbol_table_frozen
)
3379 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3381 obj_symbol_new_hook (symbolP
);
3383 #ifdef tc_symbol_new_hook
3384 tc_symbol_new_hook (symbolP
);
3388 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3389 #endif /* DEBUG_SYMS */
3393 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3396 literal_pool
* pool
;
3399 pool
= find_literal_pool ();
3401 || pool
->symbol
== NULL
3402 || pool
->next_free_entry
== 0)
3405 /* Align pool as you have word accesses.
3406 Only make a frag if we have to. */
3408 frag_align (pool
->alignment
, 0, 0);
3410 record_alignment (now_seg
, 2);
3413 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3414 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3416 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3418 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3419 (valueT
) frag_now_fix (), frag_now
);
3420 symbol_table_insert (pool
->symbol
);
3422 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3424 #if defined OBJ_COFF || defined OBJ_ELF
3425 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3428 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3431 if (debug_type
== DEBUG_DWARF2
)
3432 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3434 /* First output the expression in the instruction to the pool. */
3435 emit_expr (&(pool
->literals
[entry
]),
3436 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3439 /* Mark the pool as empty. */
3440 pool
->next_free_entry
= 0;
3441 pool
->symbol
= NULL
;
3445 /* Forward declarations for functions below, in the MD interface
3447 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3448 static valueT
create_unwind_entry (int);
3449 static void start_unwind_section (const segT
, int);
3450 static void add_unwind_opcode (valueT
, int);
3451 static void flush_pending_unwind (void);
3453 /* Directives: Data. */
3456 s_arm_elf_cons (int nbytes
)
3460 #ifdef md_flush_pending_output
3461 md_flush_pending_output ();
3464 if (is_it_end_of_statement ())
3466 demand_empty_rest_of_line ();
3470 #ifdef md_cons_align
3471 md_cons_align (nbytes
);
3474 mapping_state (MAP_DATA
);
3478 char *base
= input_line_pointer
;
3482 if (exp
.X_op
!= O_symbol
)
3483 emit_expr (&exp
, (unsigned int) nbytes
);
3486 char *before_reloc
= input_line_pointer
;
3487 reloc
= parse_reloc (&input_line_pointer
);
3490 as_bad (_("unrecognized relocation suffix"));
3491 ignore_rest_of_line ();
3494 else if (reloc
== BFD_RELOC_UNUSED
)
3495 emit_expr (&exp
, (unsigned int) nbytes
);
3498 reloc_howto_type
*howto
= (reloc_howto_type
*)
3499 bfd_reloc_type_lookup (stdoutput
,
3500 (bfd_reloc_code_real_type
) reloc
);
3501 int size
= bfd_get_reloc_size (howto
);
3503 if (reloc
== BFD_RELOC_ARM_PLT32
)
3505 as_bad (_("(plt) is only valid on branch targets"));
3506 reloc
= BFD_RELOC_UNUSED
;
3511 as_bad (_("%s relocations do not fit in %d bytes"),
3512 howto
->name
, nbytes
);
3515 /* We've parsed an expression stopping at O_symbol.
3516 But there may be more expression left now that we
3517 have parsed the relocation marker. Parse it again.
3518 XXX Surely there is a cleaner way to do this. */
3519 char *p
= input_line_pointer
;
3521 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3522 memcpy (save_buf
, base
, input_line_pointer
- base
);
3523 memmove (base
+ (input_line_pointer
- before_reloc
),
3524 base
, before_reloc
- base
);
3526 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3528 memcpy (base
, save_buf
, p
- base
);
3530 offset
= nbytes
- size
;
3531 p
= frag_more (nbytes
);
3532 memset (p
, 0, nbytes
);
3533 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3534 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3539 while (*input_line_pointer
++ == ',');
3541 /* Put terminator back into stream. */
3542 input_line_pointer
--;
3543 demand_empty_rest_of_line ();
3546 /* Emit an expression containing a 32-bit thumb instruction.
3547 Implementation based on put_thumb32_insn. */
3550 emit_thumb32_expr (expressionS
* exp
)
3552 expressionS exp_high
= *exp
;
3554 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3555 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3556 exp
->X_add_number
&= 0xffff;
3557 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3560 /* Guess the instruction size based on the opcode. */
3563 thumb_insn_size (int opcode
)
3565 if ((unsigned int) opcode
< 0xe800u
)
3567 else if ((unsigned int) opcode
>= 0xe8000000u
)
3574 emit_insn (expressionS
*exp
, int nbytes
)
3578 if (exp
->X_op
== O_constant
)
3583 size
= thumb_insn_size (exp
->X_add_number
);
3587 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3589 as_bad (_(".inst.n operand too big. "\
3590 "Use .inst.w instead"));
3595 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3596 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3598 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3600 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3601 emit_thumb32_expr (exp
);
3603 emit_expr (exp
, (unsigned int) size
);
3605 it_fsm_post_encode ();
3609 as_bad (_("cannot determine Thumb instruction size. " \
3610 "Use .inst.n/.inst.w instead"));
3613 as_bad (_("constant expression required"));
3618 /* Like s_arm_elf_cons but do not use md_cons_align and
3619 set the mapping state to MAP_ARM/MAP_THUMB. */
3622 s_arm_elf_inst (int nbytes
)
3624 if (is_it_end_of_statement ())
3626 demand_empty_rest_of_line ();
3630 /* Calling mapping_state () here will not change ARM/THUMB,
3631 but will ensure not to be in DATA state. */
3634 mapping_state (MAP_THUMB
);
3639 as_bad (_("width suffixes are invalid in ARM mode"));
3640 ignore_rest_of_line ();
3646 mapping_state (MAP_ARM
);
3655 if (! emit_insn (& exp
, nbytes
))
3657 ignore_rest_of_line ();
3661 while (*input_line_pointer
++ == ',');
3663 /* Put terminator back into stream. */
3664 input_line_pointer
--;
3665 demand_empty_rest_of_line ();
3668 /* Parse a .rel31 directive. */
3671 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3678 if (*input_line_pointer
== '1')
3679 highbit
= 0x80000000;
3680 else if (*input_line_pointer
!= '0')
3681 as_bad (_("expected 0 or 1"));
3683 input_line_pointer
++;
3684 if (*input_line_pointer
!= ',')
3685 as_bad (_("missing comma"));
3686 input_line_pointer
++;
3688 #ifdef md_flush_pending_output
3689 md_flush_pending_output ();
3692 #ifdef md_cons_align
3696 mapping_state (MAP_DATA
);
3701 md_number_to_chars (p
, highbit
, 4);
3702 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3703 BFD_RELOC_ARM_PREL31
);
3705 demand_empty_rest_of_line ();
3708 /* Directives: AEABI stack-unwind tables. */
3710 /* Parse an unwind_fnstart directive. Simply records the current location. */
3713 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3715 demand_empty_rest_of_line ();
3716 if (unwind
.proc_start
)
3718 as_bad (_("duplicate .fnstart directive"));
3722 /* Mark the start of the function. */
3723 unwind
.proc_start
= expr_build_dot ();
3725 /* Reset the rest of the unwind info. */
3726 unwind
.opcode_count
= 0;
3727 unwind
.table_entry
= NULL
;
3728 unwind
.personality_routine
= NULL
;
3729 unwind
.personality_index
= -1;
3730 unwind
.frame_size
= 0;
3731 unwind
.fp_offset
= 0;
3732 unwind
.fp_reg
= REG_SP
;
3734 unwind
.sp_restored
= 0;
3738 /* Parse a handlerdata directive. Creates the exception handling table entry
3739 for the function. */
3742 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3744 demand_empty_rest_of_line ();
3745 if (!unwind
.proc_start
)
3746 as_bad (MISSING_FNSTART
);
3748 if (unwind
.table_entry
)
3749 as_bad (_("duplicate .handlerdata directive"));
3751 create_unwind_entry (1);
3754 /* Parse an unwind_fnend directive. Generates the index table entry. */
3757 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3762 unsigned int marked_pr_dependency
;
3764 demand_empty_rest_of_line ();
3766 if (!unwind
.proc_start
)
3768 as_bad (_(".fnend directive without .fnstart"));
3772 /* Add eh table entry. */
3773 if (unwind
.table_entry
== NULL
)
3774 val
= create_unwind_entry (0);
3778 /* Add index table entry. This is two words. */
3779 start_unwind_section (unwind
.saved_seg
, 1);
3780 frag_align (2, 0, 0);
3781 record_alignment (now_seg
, 2);
3783 ptr
= frag_more (8);
3785 where
= frag_now_fix () - 8;
3787 /* Self relative offset of the function start. */
3788 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3789 BFD_RELOC_ARM_PREL31
);
3791 /* Indicate dependency on EHABI-defined personality routines to the
3792 linker, if it hasn't been done already. */
3793 marked_pr_dependency
3794 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3795 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3796 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3798 static const char *const name
[] =
3800 "__aeabi_unwind_cpp_pr0",
3801 "__aeabi_unwind_cpp_pr1",
3802 "__aeabi_unwind_cpp_pr2"
3804 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3805 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3806 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3807 |= 1 << unwind
.personality_index
;
3811 /* Inline exception table entry. */
3812 md_number_to_chars (ptr
+ 4, val
, 4);
3814 /* Self relative offset of the table entry. */
3815 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3816 BFD_RELOC_ARM_PREL31
);
3818 /* Restore the original section. */
3819 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3821 unwind
.proc_start
= NULL
;
3825 /* Parse an unwind_cantunwind directive. */
3828 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3830 demand_empty_rest_of_line ();
3831 if (!unwind
.proc_start
)
3832 as_bad (MISSING_FNSTART
);
3834 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3835 as_bad (_("personality routine specified for cantunwind frame"));
3837 unwind
.personality_index
= -2;
3841 /* Parse a personalityindex directive. */
3844 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3848 if (!unwind
.proc_start
)
3849 as_bad (MISSING_FNSTART
);
3851 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3852 as_bad (_("duplicate .personalityindex directive"));
3856 if (exp
.X_op
!= O_constant
3857 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3859 as_bad (_("bad personality routine number"));
3860 ignore_rest_of_line ();
3864 unwind
.personality_index
= exp
.X_add_number
;
3866 demand_empty_rest_of_line ();
3870 /* Parse a personality directive. */
3873 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3877 if (!unwind
.proc_start
)
3878 as_bad (MISSING_FNSTART
);
3880 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3881 as_bad (_("duplicate .personality directive"));
3883 name
= input_line_pointer
;
3884 c
= get_symbol_end ();
3885 p
= input_line_pointer
;
3886 unwind
.personality_routine
= symbol_find_or_make (name
);
3888 demand_empty_rest_of_line ();
3892 /* Parse a directive saving core registers. */
3895 s_arm_unwind_save_core (void)
3901 range
= parse_reg_list (&input_line_pointer
);
3904 as_bad (_("expected register list"));
3905 ignore_rest_of_line ();
3909 demand_empty_rest_of_line ();
3911 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3912 into .unwind_save {..., sp...}. We aren't bothered about the value of
3913 ip because it is clobbered by calls. */
3914 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3915 && (range
& 0x3000) == 0x1000)
3917 unwind
.opcode_count
--;
3918 unwind
.sp_restored
= 0;
3919 range
= (range
| 0x2000) & ~0x1000;
3920 unwind
.pending_offset
= 0;
3926 /* See if we can use the short opcodes. These pop a block of up to 8
3927 registers starting with r4, plus maybe r14. */
3928 for (n
= 0; n
< 8; n
++)
3930 /* Break at the first non-saved register. */
3931 if ((range
& (1 << (n
+ 4))) == 0)
3934 /* See if there are any other bits set. */
3935 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3937 /* Use the long form. */
3938 op
= 0x8000 | ((range
>> 4) & 0xfff);
3939 add_unwind_opcode (op
, 2);
3943 /* Use the short form. */
3945 op
= 0xa8; /* Pop r14. */
3947 op
= 0xa0; /* Do not pop r14. */
3949 add_unwind_opcode (op
, 1);
3956 op
= 0xb100 | (range
& 0xf);
3957 add_unwind_opcode (op
, 2);
3960 /* Record the number of bytes pushed. */
3961 for (n
= 0; n
< 16; n
++)
3963 if (range
& (1 << n
))
3964 unwind
.frame_size
+= 4;
3969 /* Parse a directive saving FPA registers. */
3972 s_arm_unwind_save_fpa (int reg
)
3978 /* Get Number of registers to transfer. */
3979 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3982 exp
.X_op
= O_illegal
;
3984 if (exp
.X_op
!= O_constant
)
3986 as_bad (_("expected , <constant>"));
3987 ignore_rest_of_line ();
3991 num_regs
= exp
.X_add_number
;
3993 if (num_regs
< 1 || num_regs
> 4)
3995 as_bad (_("number of registers must be in the range [1:4]"));
3996 ignore_rest_of_line ();
4000 demand_empty_rest_of_line ();
4005 op
= 0xb4 | (num_regs
- 1);
4006 add_unwind_opcode (op
, 1);
4011 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4012 add_unwind_opcode (op
, 2);
4014 unwind
.frame_size
+= num_regs
* 12;
4018 /* Parse a directive saving VFP registers for ARMv6 and above. */
4021 s_arm_unwind_save_vfp_armv6 (void)
4026 int num_vfpv3_regs
= 0;
4027 int num_regs_below_16
;
4029 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4032 as_bad (_("expected register list"));
4033 ignore_rest_of_line ();
4037 demand_empty_rest_of_line ();
4039 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4040 than FSTMX/FLDMX-style ones). */
4042 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4044 num_vfpv3_regs
= count
;
4045 else if (start
+ count
> 16)
4046 num_vfpv3_regs
= start
+ count
- 16;
4048 if (num_vfpv3_regs
> 0)
4050 int start_offset
= start
> 16 ? start
- 16 : 0;
4051 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4052 add_unwind_opcode (op
, 2);
4055 /* Generate opcode for registers numbered in the range 0 .. 15. */
4056 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4057 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4058 if (num_regs_below_16
> 0)
4060 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4061 add_unwind_opcode (op
, 2);
4064 unwind
.frame_size
+= count
* 8;
4068 /* Parse a directive saving VFP registers for pre-ARMv6. */
4071 s_arm_unwind_save_vfp (void)
4077 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4080 as_bad (_("expected register list"));
4081 ignore_rest_of_line ();
4085 demand_empty_rest_of_line ();
4090 op
= 0xb8 | (count
- 1);
4091 add_unwind_opcode (op
, 1);
4096 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4097 add_unwind_opcode (op
, 2);
4099 unwind
.frame_size
+= count
* 8 + 4;
4103 /* Parse a directive saving iWMMXt data registers. */
4106 s_arm_unwind_save_mmxwr (void)
4114 if (*input_line_pointer
== '{')
4115 input_line_pointer
++;
4119 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4123 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4128 as_tsktsk (_("register list not in ascending order"));
4131 if (*input_line_pointer
== '-')
4133 input_line_pointer
++;
4134 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4137 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4140 else if (reg
>= hi_reg
)
4142 as_bad (_("bad register range"));
4145 for (; reg
< hi_reg
; reg
++)
4149 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4151 skip_past_char (&input_line_pointer
, '}');
4153 demand_empty_rest_of_line ();
4155 /* Generate any deferred opcodes because we're going to be looking at
4157 flush_pending_unwind ();
4159 for (i
= 0; i
< 16; i
++)
4161 if (mask
& (1 << i
))
4162 unwind
.frame_size
+= 8;
4165 /* Attempt to combine with a previous opcode. We do this because gcc
4166 likes to output separate unwind directives for a single block of
4168 if (unwind
.opcode_count
> 0)
4170 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4171 if ((i
& 0xf8) == 0xc0)
4174 /* Only merge if the blocks are contiguous. */
4177 if ((mask
& 0xfe00) == (1 << 9))
4179 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4180 unwind
.opcode_count
--;
4183 else if (i
== 6 && unwind
.opcode_count
>= 2)
4185 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4189 op
= 0xffff << (reg
- 1);
4191 && ((mask
& op
) == (1u << (reg
- 1))))
4193 op
= (1 << (reg
+ i
+ 1)) - 1;
4194 op
&= ~((1 << reg
) - 1);
4196 unwind
.opcode_count
-= 2;
4203 /* We want to generate opcodes in the order the registers have been
4204 saved, ie. descending order. */
4205 for (reg
= 15; reg
>= -1; reg
--)
4207 /* Save registers in blocks. */
4209 || !(mask
& (1 << reg
)))
4211 /* We found an unsaved reg. Generate opcodes to save the
4218 op
= 0xc0 | (hi_reg
- 10);
4219 add_unwind_opcode (op
, 1);
4224 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4225 add_unwind_opcode (op
, 2);
4234 ignore_rest_of_line ();
4238 s_arm_unwind_save_mmxwcg (void)
4245 if (*input_line_pointer
== '{')
4246 input_line_pointer
++;
4248 skip_whitespace (input_line_pointer
);
4252 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4256 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4262 as_tsktsk (_("register list not in ascending order"));
4265 if (*input_line_pointer
== '-')
4267 input_line_pointer
++;
4268 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4271 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4274 else if (reg
>= hi_reg
)
4276 as_bad (_("bad register range"));
4279 for (; reg
< hi_reg
; reg
++)
4283 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4285 skip_past_char (&input_line_pointer
, '}');
4287 demand_empty_rest_of_line ();
4289 /* Generate any deferred opcodes because we're going to be looking at
4291 flush_pending_unwind ();
4293 for (reg
= 0; reg
< 16; reg
++)
4295 if (mask
& (1 << reg
))
4296 unwind
.frame_size
+= 4;
4299 add_unwind_opcode (op
, 2);
4302 ignore_rest_of_line ();
4306 /* Parse an unwind_save directive.
4307 If the argument is non-zero, this is a .vsave directive. */
4310 s_arm_unwind_save (int arch_v6
)
4313 struct reg_entry
*reg
;
4314 bfd_boolean had_brace
= FALSE
;
4316 if (!unwind
.proc_start
)
4317 as_bad (MISSING_FNSTART
);
4319 /* Figure out what sort of save we have. */
4320 peek
= input_line_pointer
;
4328 reg
= arm_reg_parse_multi (&peek
);
4332 as_bad (_("register expected"));
4333 ignore_rest_of_line ();
4342 as_bad (_("FPA .unwind_save does not take a register list"));
4343 ignore_rest_of_line ();
4346 input_line_pointer
= peek
;
4347 s_arm_unwind_save_fpa (reg
->number
);
4351 s_arm_unwind_save_core ();
4356 s_arm_unwind_save_vfp_armv6 ();
4358 s_arm_unwind_save_vfp ();
4361 case REG_TYPE_MMXWR
:
4362 s_arm_unwind_save_mmxwr ();
4365 case REG_TYPE_MMXWCG
:
4366 s_arm_unwind_save_mmxwcg ();
4370 as_bad (_(".unwind_save does not support this kind of register"));
4371 ignore_rest_of_line ();
4376 /* Parse an unwind_movsp directive. */
4379 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4385 if (!unwind
.proc_start
)
4386 as_bad (MISSING_FNSTART
);
4388 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4391 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4392 ignore_rest_of_line ();
4396 /* Optional constant. */
4397 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4399 if (immediate_for_directive (&offset
) == FAIL
)
4405 demand_empty_rest_of_line ();
4407 if (reg
== REG_SP
|| reg
== REG_PC
)
4409 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4413 if (unwind
.fp_reg
!= REG_SP
)
4414 as_bad (_("unexpected .unwind_movsp directive"));
4416 /* Generate opcode to restore the value. */
4418 add_unwind_opcode (op
, 1);
4420 /* Record the information for later. */
4421 unwind
.fp_reg
= reg
;
4422 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4423 unwind
.sp_restored
= 1;
4426 /* Parse an unwind_pad directive. */
4429 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4433 if (!unwind
.proc_start
)
4434 as_bad (MISSING_FNSTART
);
4436 if (immediate_for_directive (&offset
) == FAIL
)
4441 as_bad (_("stack increment must be multiple of 4"));
4442 ignore_rest_of_line ();
4446 /* Don't generate any opcodes, just record the details for later. */
4447 unwind
.frame_size
+= offset
;
4448 unwind
.pending_offset
+= offset
;
4450 demand_empty_rest_of_line ();
4453 /* Parse an unwind_setfp directive. */
4456 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4462 if (!unwind
.proc_start
)
4463 as_bad (MISSING_FNSTART
);
4465 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4466 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4469 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4471 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4473 as_bad (_("expected <reg>, <reg>"));
4474 ignore_rest_of_line ();
4478 /* Optional constant. */
4479 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4481 if (immediate_for_directive (&offset
) == FAIL
)
4487 demand_empty_rest_of_line ();
4489 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4491 as_bad (_("register must be either sp or set by a previous"
4492 "unwind_movsp directive"));
4496 /* Don't generate any opcodes, just record the information for later. */
4497 unwind
.fp_reg
= fp_reg
;
4499 if (sp_reg
== REG_SP
)
4500 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4502 unwind
.fp_offset
-= offset
;
4505 /* Parse an unwind_raw directive. */
4508 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4511 /* This is an arbitrary limit. */
4512 unsigned char op
[16];
4515 if (!unwind
.proc_start
)
4516 as_bad (MISSING_FNSTART
);
4519 if (exp
.X_op
== O_constant
4520 && skip_past_comma (&input_line_pointer
) != FAIL
)
4522 unwind
.frame_size
+= exp
.X_add_number
;
4526 exp
.X_op
= O_illegal
;
4528 if (exp
.X_op
!= O_constant
)
4530 as_bad (_("expected <offset>, <opcode>"));
4531 ignore_rest_of_line ();
4537 /* Parse the opcode. */
4542 as_bad (_("unwind opcode too long"));
4543 ignore_rest_of_line ();
4545 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4547 as_bad (_("invalid unwind opcode"));
4548 ignore_rest_of_line ();
4551 op
[count
++] = exp
.X_add_number
;
4553 /* Parse the next byte. */
4554 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4560 /* Add the opcode bytes in reverse order. */
4562 add_unwind_opcode (op
[count
], 1);
4564 demand_empty_rest_of_line ();
4568 /* Parse a .eabi_attribute directive. */
4571 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4573 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4575 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4576 attributes_set_explicitly
[tag
] = 1;
4579 /* Emit a tls fix for the symbol. */
4582 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4586 #ifdef md_flush_pending_output
4587 md_flush_pending_output ();
4590 #ifdef md_cons_align
4594 /* Since we're just labelling the code, there's no need to define a
4597 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4598 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4599 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4600 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4602 #endif /* OBJ_ELF */
4604 static void s_arm_arch (int);
4605 static void s_arm_object_arch (int);
4606 static void s_arm_cpu (int);
4607 static void s_arm_fpu (int);
4608 static void s_arm_arch_extension (int);
4613 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4620 if (exp
.X_op
== O_symbol
)
4621 exp
.X_op
= O_secrel
;
4623 emit_expr (&exp
, 4);
4625 while (*input_line_pointer
++ == ',');
4627 input_line_pointer
--;
4628 demand_empty_rest_of_line ();
4632 /* This table describes all the machine specific pseudo-ops the assembler
4633 has to support. The fields are:
4634 pseudo-op name without dot
4635 function to call to execute this pseudo-op
4636 Integer arg to pass to the function. */
4638 const pseudo_typeS md_pseudo_table
[] =
4640 /* Never called because '.req' does not start a line. */
4641 { "req", s_req
, 0 },
4642 /* Following two are likewise never called. */
4645 { "unreq", s_unreq
, 0 },
4646 { "bss", s_bss
, 0 },
4647 { "align", s_align_ptwo
, 2 },
4648 { "arm", s_arm
, 0 },
4649 { "thumb", s_thumb
, 0 },
4650 { "code", s_code
, 0 },
4651 { "force_thumb", s_force_thumb
, 0 },
4652 { "thumb_func", s_thumb_func
, 0 },
4653 { "thumb_set", s_thumb_set
, 0 },
4654 { "even", s_even
, 0 },
4655 { "ltorg", s_ltorg
, 0 },
4656 { "pool", s_ltorg
, 0 },
4657 { "syntax", s_syntax
, 0 },
4658 { "cpu", s_arm_cpu
, 0 },
4659 { "arch", s_arm_arch
, 0 },
4660 { "object_arch", s_arm_object_arch
, 0 },
4661 { "fpu", s_arm_fpu
, 0 },
4662 { "arch_extension", s_arm_arch_extension
, 0 },
4664 { "word", s_arm_elf_cons
, 4 },
4665 { "long", s_arm_elf_cons
, 4 },
4666 { "inst.n", s_arm_elf_inst
, 2 },
4667 { "inst.w", s_arm_elf_inst
, 4 },
4668 { "inst", s_arm_elf_inst
, 0 },
4669 { "rel31", s_arm_rel31
, 0 },
4670 { "fnstart", s_arm_unwind_fnstart
, 0 },
4671 { "fnend", s_arm_unwind_fnend
, 0 },
4672 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4673 { "personality", s_arm_unwind_personality
, 0 },
4674 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4675 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4676 { "save", s_arm_unwind_save
, 0 },
4677 { "vsave", s_arm_unwind_save
, 1 },
4678 { "movsp", s_arm_unwind_movsp
, 0 },
4679 { "pad", s_arm_unwind_pad
, 0 },
4680 { "setfp", s_arm_unwind_setfp
, 0 },
4681 { "unwind_raw", s_arm_unwind_raw
, 0 },
4682 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4683 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4687 /* These are used for dwarf. */
4691 /* These are used for dwarf2. */
4692 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4693 { "loc", dwarf2_directive_loc
, 0 },
4694 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4696 { "extend", float_cons
, 'x' },
4697 { "ldouble", float_cons
, 'x' },
4698 { "packed", float_cons
, 'p' },
4700 {"secrel32", pe_directive_secrel
, 0},
4703 /* These are for compatibility with CodeComposer Studio. */
4704 {"ref", s_ccs_ref
, 0},
4705 {"def", s_ccs_def
, 0},
4706 {"asmfunc", s_ccs_asmfunc
, 0},
4707 {"endasmfunc", s_ccs_endasmfunc
, 0},
4712 /* Parser functions used exclusively in instruction operands. */
4714 /* Generic immediate-value read function for use in insn parsing.
4715 STR points to the beginning of the immediate (the leading #);
4716 VAL receives the value; if the value is outside [MIN, MAX]
4717 issue an error. PREFIX_OPT is true if the immediate prefix is
4721 parse_immediate (char **str
, int *val
, int min
, int max
,
4722 bfd_boolean prefix_opt
)
4725 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4726 if (exp
.X_op
!= O_constant
)
4728 inst
.error
= _("constant expression required");
4732 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4734 inst
.error
= _("immediate value out of range");
4738 *val
= exp
.X_add_number
;
4742 /* Less-generic immediate-value read function with the possibility of loading a
4743 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4744 instructions. Puts the result directly in inst.operands[i]. */
4747 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4748 bfd_boolean allow_symbol_p
)
4751 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4754 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4756 if (exp_p
->X_op
== O_constant
)
4758 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4759 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4760 O_constant. We have to be careful not to break compilation for
4761 32-bit X_add_number, though. */
4762 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4764 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4765 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4767 inst
.operands
[i
].regisimm
= 1;
4770 else if (exp_p
->X_op
== O_big
4771 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4773 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4775 /* Bignums have their least significant bits in
4776 generic_bignum[0]. Make sure we put 32 bits in imm and
4777 32 bits in reg, in a (hopefully) portable way. */
4778 gas_assert (parts
!= 0);
4780 /* Make sure that the number is not too big.
4781 PR 11972: Bignums can now be sign-extended to the
4782 size of a .octa so check that the out of range bits
4783 are all zero or all one. */
4784 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4786 LITTLENUM_TYPE m
= -1;
4788 if (generic_bignum
[parts
* 2] != 0
4789 && generic_bignum
[parts
* 2] != m
)
4792 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4793 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4797 inst
.operands
[i
].imm
= 0;
4798 for (j
= 0; j
< parts
; j
++, idx
++)
4799 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4800 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4801 inst
.operands
[i
].reg
= 0;
4802 for (j
= 0; j
< parts
; j
++, idx
++)
4803 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4804 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4805 inst
.operands
[i
].regisimm
= 1;
4807 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4815 /* Returns the pseudo-register number of an FPA immediate constant,
4816 or FAIL if there isn't a valid constant here. */
4819 parse_fpa_immediate (char ** str
)
4821 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4827 /* First try and match exact strings, this is to guarantee
4828 that some formats will work even for cross assembly. */
4830 for (i
= 0; fp_const
[i
]; i
++)
4832 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4836 *str
+= strlen (fp_const
[i
]);
4837 if (is_end_of_line
[(unsigned char) **str
])
4843 /* Just because we didn't get a match doesn't mean that the constant
4844 isn't valid, just that it is in a format that we don't
4845 automatically recognize. Try parsing it with the standard
4846 expression routines. */
4848 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4850 /* Look for a raw floating point number. */
4851 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4852 && is_end_of_line
[(unsigned char) *save_in
])
4854 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4856 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4858 if (words
[j
] != fp_values
[i
][j
])
4862 if (j
== MAX_LITTLENUMS
)
4870 /* Try and parse a more complex expression, this will probably fail
4871 unless the code uses a floating point prefix (eg "0f"). */
4872 save_in
= input_line_pointer
;
4873 input_line_pointer
= *str
;
4874 if (expression (&exp
) == absolute_section
4875 && exp
.X_op
== O_big
4876 && exp
.X_add_number
< 0)
4878 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4880 #define X_PRECISION 5
4881 #define E_PRECISION 15L
4882 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4884 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4886 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4888 if (words
[j
] != fp_values
[i
][j
])
4892 if (j
== MAX_LITTLENUMS
)
4894 *str
= input_line_pointer
;
4895 input_line_pointer
= save_in
;
4902 *str
= input_line_pointer
;
4903 input_line_pointer
= save_in
;
4904 inst
.error
= _("invalid FPA immediate expression");
4908 /* Returns 1 if a number has "quarter-precision" float format
4909 0baBbbbbbc defgh000 00000000 00000000. */
4912 is_quarter_float (unsigned imm
)
4914 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4915 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4919 /* Detect the presence of a floating point or integer zero constant,
4923 parse_ifimm_zero (char **in
)
4927 if (!is_immediate_prefix (**in
))
4932 /* Accept #0x0 as a synonym for #0. */
4933 if (strncmp (*in
, "0x", 2) == 0)
4936 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4941 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4942 &generic_floating_point_number
);
4945 && generic_floating_point_number
.sign
== '+'
4946 && (generic_floating_point_number
.low
4947 > generic_floating_point_number
.leader
))
4953 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4954 0baBbbbbbc defgh000 00000000 00000000.
4955 The zero and minus-zero cases need special handling, since they can't be
4956 encoded in the "quarter-precision" float format, but can nonetheless be
4957 loaded as integer constants. */
4960 parse_qfloat_immediate (char **ccp
, int *immed
)
4964 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4965 int found_fpchar
= 0;
4967 skip_past_char (&str
, '#');
4969 /* We must not accidentally parse an integer as a floating-point number. Make
4970 sure that the value we parse is not an integer by checking for special
4971 characters '.' or 'e'.
4972 FIXME: This is a horrible hack, but doing better is tricky because type
4973 information isn't in a very usable state at parse time. */
4975 skip_whitespace (fpnum
);
4977 if (strncmp (fpnum
, "0x", 2) == 0)
4981 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4982 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4992 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4994 unsigned fpword
= 0;
4997 /* Our FP word must be 32 bits (single-precision FP). */
4998 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5000 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5004 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5017 /* Shift operands. */
5020 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5023 struct asm_shift_name
5026 enum shift_kind kind
;
5029 /* Third argument to parse_shift. */
5030 enum parse_shift_mode
5032 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5033 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5034 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5035 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5036 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5039 /* Parse a <shift> specifier on an ARM data processing instruction.
5040 This has three forms:
5042 (LSL|LSR|ASL|ASR|ROR) Rs
5043 (LSL|LSR|ASL|ASR|ROR) #imm
5046 Note that ASL is assimilated to LSL in the instruction encoding, and
5047 RRX to ROR #0 (which cannot be written as such). */
5050 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5052 const struct asm_shift_name
*shift_name
;
5053 enum shift_kind shift
;
5058 for (p
= *str
; ISALPHA (*p
); p
++)
5063 inst
.error
= _("shift expression expected");
5067 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5070 if (shift_name
== NULL
)
5072 inst
.error
= _("shift expression expected");
5076 shift
= shift_name
->kind
;
5080 case NO_SHIFT_RESTRICT
:
5081 case SHIFT_IMMEDIATE
: break;
5083 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5084 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5086 inst
.error
= _("'LSL' or 'ASR' required");
5091 case SHIFT_LSL_IMMEDIATE
:
5092 if (shift
!= SHIFT_LSL
)
5094 inst
.error
= _("'LSL' required");
5099 case SHIFT_ASR_IMMEDIATE
:
5100 if (shift
!= SHIFT_ASR
)
5102 inst
.error
= _("'ASR' required");
5110 if (shift
!= SHIFT_RRX
)
5112 /* Whitespace can appear here if the next thing is a bare digit. */
5113 skip_whitespace (p
);
5115 if (mode
== NO_SHIFT_RESTRICT
5116 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5118 inst
.operands
[i
].imm
= reg
;
5119 inst
.operands
[i
].immisreg
= 1;
5121 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5124 inst
.operands
[i
].shift_kind
= shift
;
5125 inst
.operands
[i
].shifted
= 1;
5130 /* Parse a <shifter_operand> for an ARM data processing instruction:
5133 #<immediate>, <rotate>
5137 where <shift> is defined by parse_shift above, and <rotate> is a
5138 multiple of 2 between 0 and 30. Validation of immediate operands
5139 is deferred to md_apply_fix. */
5142 parse_shifter_operand (char **str
, int i
)
5147 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5149 inst
.operands
[i
].reg
= value
;
5150 inst
.operands
[i
].isreg
= 1;
5152 /* parse_shift will override this if appropriate */
5153 inst
.reloc
.exp
.X_op
= O_constant
;
5154 inst
.reloc
.exp
.X_add_number
= 0;
5156 if (skip_past_comma (str
) == FAIL
)
5159 /* Shift operation on register. */
5160 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5163 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5166 if (skip_past_comma (str
) == SUCCESS
)
5168 /* #x, y -- ie explicit rotation by Y. */
5169 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5172 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5174 inst
.error
= _("constant expression expected");
5178 value
= exp
.X_add_number
;
5179 if (value
< 0 || value
> 30 || value
% 2 != 0)
5181 inst
.error
= _("invalid rotation");
5184 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5186 inst
.error
= _("invalid constant");
5190 /* Encode as specified. */
5191 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5195 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5196 inst
.reloc
.pc_rel
= 0;
5200 /* Group relocation information. Each entry in the table contains the
5201 textual name of the relocation as may appear in assembler source
5202 and must end with a colon.
5203 Along with this textual name are the relocation codes to be used if
5204 the corresponding instruction is an ALU instruction (ADD or SUB only),
5205 an LDR, an LDRS, or an LDC. */
5207 struct group_reloc_table_entry
5218 /* Varieties of non-ALU group relocation. */
5225 static struct group_reloc_table_entry group_reloc_table
[] =
5226 { /* Program counter relative: */
5228 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5233 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5234 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5235 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5236 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5238 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5243 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5244 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5245 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5246 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5248 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5249 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5250 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5251 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5252 /* Section base relative */
5254 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5259 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5260 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5261 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5262 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5264 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5269 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5270 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5271 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5272 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5274 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5275 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5276 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5277 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
5279 /* Given the address of a pointer pointing to the textual name of a group
5280 relocation as may appear in assembler source, attempt to find its details
5281 in group_reloc_table. The pointer will be updated to the character after
5282 the trailing colon. On failure, FAIL will be returned; SUCCESS
5283 otherwise. On success, *entry will be updated to point at the relevant
5284 group_reloc_table entry. */
5287 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5290 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5292 int length
= strlen (group_reloc_table
[i
].name
);
5294 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5295 && (*str
)[length
] == ':')
5297 *out
= &group_reloc_table
[i
];
5298 *str
+= (length
+ 1);
5306 /* Parse a <shifter_operand> for an ARM data processing instruction
5307 (as for parse_shifter_operand) where group relocations are allowed:
5310 #<immediate>, <rotate>
5311 #:<group_reloc>:<expression>
5315 where <group_reloc> is one of the strings defined in group_reloc_table.
5316 The hashes are optional.
5318 Everything else is as for parse_shifter_operand. */
5320 static parse_operand_result
5321 parse_shifter_operand_group_reloc (char **str
, int i
)
5323 /* Determine if we have the sequence of characters #: or just :
5324 coming next. If we do, then we check for a group relocation.
5325 If we don't, punt the whole lot to parse_shifter_operand. */
5327 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5328 || (*str
)[0] == ':')
5330 struct group_reloc_table_entry
*entry
;
5332 if ((*str
)[0] == '#')
5337 /* Try to parse a group relocation. Anything else is an error. */
5338 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5340 inst
.error
= _("unknown group relocation");
5341 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5344 /* We now have the group relocation table entry corresponding to
5345 the name in the assembler source. Next, we parse the expression. */
5346 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5347 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5349 /* Record the relocation type (always the ALU variant here). */
5350 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5351 gas_assert (inst
.reloc
.type
!= 0);
5353 return PARSE_OPERAND_SUCCESS
;
5356 return parse_shifter_operand (str
, i
) == SUCCESS
5357 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5359 /* Never reached. */
5362 /* Parse a Neon alignment expression. Information is written to
5363 inst.operands[i]. We assume the initial ':' has been skipped.
5365 align .imm = align << 8, .immisalign=1, .preind=0 */
5366 static parse_operand_result
5367 parse_neon_alignment (char **str
, int i
)
5372 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5374 if (exp
.X_op
!= O_constant
)
5376 inst
.error
= _("alignment must be constant");
5377 return PARSE_OPERAND_FAIL
;
5380 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5381 inst
.operands
[i
].immisalign
= 1;
5382 /* Alignments are not pre-indexes. */
5383 inst
.operands
[i
].preind
= 0;
5386 return PARSE_OPERAND_SUCCESS
;
5389 /* Parse all forms of an ARM address expression. Information is written
5390 to inst.operands[i] and/or inst.reloc.
5392 Preindexed addressing (.preind=1):
5394 [Rn, #offset] .reg=Rn .reloc.exp=offset
5395 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5396 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5397 .shift_kind=shift .reloc.exp=shift_imm
5399 These three may have a trailing ! which causes .writeback to be set also.
5401 Postindexed addressing (.postind=1, .writeback=1):
5403 [Rn], #offset .reg=Rn .reloc.exp=offset
5404 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5405 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5406 .shift_kind=shift .reloc.exp=shift_imm
5408 Unindexed addressing (.preind=0, .postind=0):
5410 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5414 [Rn]{!} shorthand for [Rn,#0]{!}
5415 =immediate .isreg=0 .reloc.exp=immediate
5416 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5418 It is the caller's responsibility to check for addressing modes not
5419 supported by the instruction, and to set inst.reloc.type. */
5421 static parse_operand_result
5422 parse_address_main (char **str
, int i
, int group_relocations
,
5423 group_reloc_type group_type
)
5428 if (skip_past_char (&p
, '[') == FAIL
)
5430 if (skip_past_char (&p
, '=') == FAIL
)
5432 /* Bare address - translate to PC-relative offset. */
5433 inst
.reloc
.pc_rel
= 1;
5434 inst
.operands
[i
].reg
= REG_PC
;
5435 inst
.operands
[i
].isreg
= 1;
5436 inst
.operands
[i
].preind
= 1;
5438 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5439 return PARSE_OPERAND_FAIL
;
5441 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5442 /*allow_symbol_p=*/TRUE
))
5443 return PARSE_OPERAND_FAIL
;
5446 return PARSE_OPERAND_SUCCESS
;
5449 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5450 skip_whitespace (p
);
5452 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5454 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5455 return PARSE_OPERAND_FAIL
;
5457 inst
.operands
[i
].reg
= reg
;
5458 inst
.operands
[i
].isreg
= 1;
5460 if (skip_past_comma (&p
) == SUCCESS
)
5462 inst
.operands
[i
].preind
= 1;
5465 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5467 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5469 inst
.operands
[i
].imm
= reg
;
5470 inst
.operands
[i
].immisreg
= 1;
5472 if (skip_past_comma (&p
) == SUCCESS
)
5473 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5474 return PARSE_OPERAND_FAIL
;
5476 else if (skip_past_char (&p
, ':') == SUCCESS
)
5478 /* FIXME: '@' should be used here, but it's filtered out by generic
5479 code before we get to see it here. This may be subject to
5481 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5483 if (result
!= PARSE_OPERAND_SUCCESS
)
5488 if (inst
.operands
[i
].negative
)
5490 inst
.operands
[i
].negative
= 0;
5494 if (group_relocations
5495 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5497 struct group_reloc_table_entry
*entry
;
5499 /* Skip over the #: or : sequence. */
5505 /* Try to parse a group relocation. Anything else is an
5507 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5509 inst
.error
= _("unknown group relocation");
5510 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5513 /* We now have the group relocation table entry corresponding to
5514 the name in the assembler source. Next, we parse the
5516 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5517 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5519 /* Record the relocation type. */
5523 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5527 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5531 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5538 if (inst
.reloc
.type
== 0)
5540 inst
.error
= _("this group relocation is not allowed on this instruction");
5541 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5547 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5548 return PARSE_OPERAND_FAIL
;
5549 /* If the offset is 0, find out if it's a +0 or -0. */
5550 if (inst
.reloc
.exp
.X_op
== O_constant
5551 && inst
.reloc
.exp
.X_add_number
== 0)
5553 skip_whitespace (q
);
5557 skip_whitespace (q
);
5560 inst
.operands
[i
].negative
= 1;
5565 else if (skip_past_char (&p
, ':') == SUCCESS
)
5567 /* FIXME: '@' should be used here, but it's filtered out by generic code
5568 before we get to see it here. This may be subject to change. */
5569 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5571 if (result
!= PARSE_OPERAND_SUCCESS
)
5575 if (skip_past_char (&p
, ']') == FAIL
)
5577 inst
.error
= _("']' expected");
5578 return PARSE_OPERAND_FAIL
;
5581 if (skip_past_char (&p
, '!') == SUCCESS
)
5582 inst
.operands
[i
].writeback
= 1;
5584 else if (skip_past_comma (&p
) == SUCCESS
)
5586 if (skip_past_char (&p
, '{') == SUCCESS
)
5588 /* [Rn], {expr} - unindexed, with option */
5589 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5590 0, 255, TRUE
) == FAIL
)
5591 return PARSE_OPERAND_FAIL
;
5593 if (skip_past_char (&p
, '}') == FAIL
)
5595 inst
.error
= _("'}' expected at end of 'option' field");
5596 return PARSE_OPERAND_FAIL
;
5598 if (inst
.operands
[i
].preind
)
5600 inst
.error
= _("cannot combine index with option");
5601 return PARSE_OPERAND_FAIL
;
5604 return PARSE_OPERAND_SUCCESS
;
5608 inst
.operands
[i
].postind
= 1;
5609 inst
.operands
[i
].writeback
= 1;
5611 if (inst
.operands
[i
].preind
)
5613 inst
.error
= _("cannot combine pre- and post-indexing");
5614 return PARSE_OPERAND_FAIL
;
5618 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5620 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5622 /* We might be using the immediate for alignment already. If we
5623 are, OR the register number into the low-order bits. */
5624 if (inst
.operands
[i
].immisalign
)
5625 inst
.operands
[i
].imm
|= reg
;
5627 inst
.operands
[i
].imm
= reg
;
5628 inst
.operands
[i
].immisreg
= 1;
5630 if (skip_past_comma (&p
) == SUCCESS
)
5631 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5632 return PARSE_OPERAND_FAIL
;
5637 if (inst
.operands
[i
].negative
)
5639 inst
.operands
[i
].negative
= 0;
5642 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5643 return PARSE_OPERAND_FAIL
;
5644 /* If the offset is 0, find out if it's a +0 or -0. */
5645 if (inst
.reloc
.exp
.X_op
== O_constant
5646 && inst
.reloc
.exp
.X_add_number
== 0)
5648 skip_whitespace (q
);
5652 skip_whitespace (q
);
5655 inst
.operands
[i
].negative
= 1;
5661 /* If at this point neither .preind nor .postind is set, we have a
5662 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5663 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5665 inst
.operands
[i
].preind
= 1;
5666 inst
.reloc
.exp
.X_op
= O_constant
;
5667 inst
.reloc
.exp
.X_add_number
= 0;
5670 return PARSE_OPERAND_SUCCESS
;
5674 parse_address (char **str
, int i
)
5676 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5680 static parse_operand_result
5681 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5683 return parse_address_main (str
, i
, 1, type
);
5686 /* Parse an operand for a MOVW or MOVT instruction. */
5688 parse_half (char **str
)
5693 skip_past_char (&p
, '#');
5694 if (strncasecmp (p
, ":lower16:", 9) == 0)
5695 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5696 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5697 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5699 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5702 skip_whitespace (p
);
5705 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5708 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5710 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5712 inst
.error
= _("constant expression expected");
5715 if (inst
.reloc
.exp
.X_add_number
< 0
5716 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5718 inst
.error
= _("immediate value out of range");
5726 /* Miscellaneous. */
5728 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5729 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5731 parse_psr (char **str
, bfd_boolean lhs
)
5734 unsigned long psr_field
;
5735 const struct asm_psr
*psr
;
5737 bfd_boolean is_apsr
= FALSE
;
5738 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5740 /* PR gas/12698: If the user has specified -march=all then m_profile will
5741 be TRUE, but we want to ignore it in this case as we are building for any
5742 CPU type, including non-m variants. */
5743 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5746 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5747 feature for ease of use and backwards compatibility. */
5749 if (strncasecmp (p
, "SPSR", 4) == 0)
5752 goto unsupported_psr
;
5754 psr_field
= SPSR_BIT
;
5756 else if (strncasecmp (p
, "CPSR", 4) == 0)
5759 goto unsupported_psr
;
5763 else if (strncasecmp (p
, "APSR", 4) == 0)
5765 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5766 and ARMv7-R architecture CPUs. */
5775 while (ISALNUM (*p
) || *p
== '_');
5777 if (strncasecmp (start
, "iapsr", 5) == 0
5778 || strncasecmp (start
, "eapsr", 5) == 0
5779 || strncasecmp (start
, "xpsr", 4) == 0
5780 || strncasecmp (start
, "psr", 3) == 0)
5781 p
= start
+ strcspn (start
, "rR") + 1;
5783 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5789 /* If APSR is being written, a bitfield may be specified. Note that
5790 APSR itself is handled above. */
5791 if (psr
->field
<= 3)
5793 psr_field
= psr
->field
;
5799 /* M-profile MSR instructions have the mask field set to "10", except
5800 *PSR variants which modify APSR, which may use a different mask (and
5801 have been handled already). Do that by setting the PSR_f field
5803 return psr
->field
| (lhs
? PSR_f
: 0);
5806 goto unsupported_psr
;
5812 /* A suffix follows. */
5818 while (ISALNUM (*p
) || *p
== '_');
5822 /* APSR uses a notation for bits, rather than fields. */
5823 unsigned int nzcvq_bits
= 0;
5824 unsigned int g_bit
= 0;
5827 for (bit
= start
; bit
!= p
; bit
++)
5829 switch (TOLOWER (*bit
))
5832 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5836 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5840 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5844 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5848 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5852 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5856 inst
.error
= _("unexpected bit specified after APSR");
5861 if (nzcvq_bits
== 0x1f)
5866 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5868 inst
.error
= _("selected processor does not "
5869 "support DSP extension");
5876 if ((nzcvq_bits
& 0x20) != 0
5877 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5878 || (g_bit
& 0x2) != 0)
5880 inst
.error
= _("bad bitmask specified after APSR");
5886 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5891 psr_field
|= psr
->field
;
5897 goto error
; /* Garbage after "[CS]PSR". */
5899 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5900 is deprecated, but allow it anyway. */
5904 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5907 else if (!m_profile
)
5908 /* These bits are never right for M-profile devices: don't set them
5909 (only code paths which read/write APSR reach here). */
5910 psr_field
|= (PSR_c
| PSR_f
);
5916 inst
.error
= _("selected processor does not support requested special "
5917 "purpose register");
5921 inst
.error
= _("flag for {c}psr instruction expected");
5925 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5926 value suitable for splatting into the AIF field of the instruction. */
5929 parse_cps_flags (char **str
)
5938 case '\0': case ',':
5941 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5942 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5943 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5946 inst
.error
= _("unrecognized CPS flag");
5951 if (saw_a_flag
== 0)
5953 inst
.error
= _("missing CPS flags");
5961 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5962 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5965 parse_endian_specifier (char **str
)
5970 if (strncasecmp (s
, "BE", 2))
5972 else if (strncasecmp (s
, "LE", 2))
5976 inst
.error
= _("valid endian specifiers are be or le");
5980 if (ISALNUM (s
[2]) || s
[2] == '_')
5982 inst
.error
= _("valid endian specifiers are be or le");
5987 return little_endian
;
5990 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5991 value suitable for poking into the rotate field of an sxt or sxta
5992 instruction, or FAIL on error. */
5995 parse_ror (char **str
)
6000 if (strncasecmp (s
, "ROR", 3) == 0)
6004 inst
.error
= _("missing rotation field after comma");
6008 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6013 case 0: *str
= s
; return 0x0;
6014 case 8: *str
= s
; return 0x1;
6015 case 16: *str
= s
; return 0x2;
6016 case 24: *str
= s
; return 0x3;
6019 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6024 /* Parse a conditional code (from conds[] below). The value returned is in the
6025 range 0 .. 14, or FAIL. */
6027 parse_cond (char **str
)
6030 const struct asm_cond
*c
;
6032 /* Condition codes are always 2 characters, so matching up to
6033 3 characters is sufficient. */
6038 while (ISALPHA (*q
) && n
< 3)
6040 cond
[n
] = TOLOWER (*q
);
6045 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6048 inst
.error
= _("condition required");
6056 /* If the given feature available in the selected CPU, mark it as used.
6057 Returns TRUE iff feature is available. */
6059 mark_feature_used (const arm_feature_set
*feature
)
6061 /* Ensure the option is valid on the current architecture. */
6062 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6065 /* Add the appropriate architecture feature for the barrier option used.
6068 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6070 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6075 /* Parse an option for a barrier instruction. Returns the encoding for the
6078 parse_barrier (char **str
)
6081 const struct asm_barrier_opt
*o
;
6084 while (ISALPHA (*q
))
6087 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6092 if (!mark_feature_used (&o
->arch
))
6099 /* Parse the operands of a table branch instruction. Similar to a memory
6102 parse_tb (char **str
)
6107 if (skip_past_char (&p
, '[') == FAIL
)
6109 inst
.error
= _("'[' expected");
6113 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6115 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6118 inst
.operands
[0].reg
= reg
;
6120 if (skip_past_comma (&p
) == FAIL
)
6122 inst
.error
= _("',' expected");
6126 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6128 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6131 inst
.operands
[0].imm
= reg
;
6133 if (skip_past_comma (&p
) == SUCCESS
)
6135 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6137 if (inst
.reloc
.exp
.X_add_number
!= 1)
6139 inst
.error
= _("invalid shift");
6142 inst
.operands
[0].shifted
= 1;
6145 if (skip_past_char (&p
, ']') == FAIL
)
6147 inst
.error
= _("']' expected");
6154 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6155 information on the types the operands can take and how they are encoded.
6156 Up to four operands may be read; this function handles setting the
6157 ".present" field for each read operand itself.
6158 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6159 else returns FAIL. */
6162 parse_neon_mov (char **str
, int *which_operand
)
6164 int i
= *which_operand
, val
;
6165 enum arm_reg_type rtype
;
6167 struct neon_type_el optype
;
6169 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6171 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6172 inst
.operands
[i
].reg
= val
;
6173 inst
.operands
[i
].isscalar
= 1;
6174 inst
.operands
[i
].vectype
= optype
;
6175 inst
.operands
[i
++].present
= 1;
6177 if (skip_past_comma (&ptr
) == FAIL
)
6180 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6183 inst
.operands
[i
].reg
= val
;
6184 inst
.operands
[i
].isreg
= 1;
6185 inst
.operands
[i
].present
= 1;
6187 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6190 /* Cases 0, 1, 2, 3, 5 (D only). */
6191 if (skip_past_comma (&ptr
) == FAIL
)
6194 inst
.operands
[i
].reg
= val
;
6195 inst
.operands
[i
].isreg
= 1;
6196 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6197 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6198 inst
.operands
[i
].isvec
= 1;
6199 inst
.operands
[i
].vectype
= optype
;
6200 inst
.operands
[i
++].present
= 1;
6202 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6204 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6205 Case 13: VMOV <Sd>, <Rm> */
6206 inst
.operands
[i
].reg
= val
;
6207 inst
.operands
[i
].isreg
= 1;
6208 inst
.operands
[i
].present
= 1;
6210 if (rtype
== REG_TYPE_NQ
)
6212 first_error (_("can't use Neon quad register here"));
6215 else if (rtype
!= REG_TYPE_VFS
)
6218 if (skip_past_comma (&ptr
) == FAIL
)
6220 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6222 inst
.operands
[i
].reg
= val
;
6223 inst
.operands
[i
].isreg
= 1;
6224 inst
.operands
[i
].present
= 1;
6227 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6230 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6231 Case 1: VMOV<c><q> <Dd>, <Dm>
6232 Case 8: VMOV.F32 <Sd>, <Sm>
6233 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6235 inst
.operands
[i
].reg
= val
;
6236 inst
.operands
[i
].isreg
= 1;
6237 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6238 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6239 inst
.operands
[i
].isvec
= 1;
6240 inst
.operands
[i
].vectype
= optype
;
6241 inst
.operands
[i
].present
= 1;
6243 if (skip_past_comma (&ptr
) == SUCCESS
)
6248 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6251 inst
.operands
[i
].reg
= val
;
6252 inst
.operands
[i
].isreg
= 1;
6253 inst
.operands
[i
++].present
= 1;
6255 if (skip_past_comma (&ptr
) == FAIL
)
6258 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6261 inst
.operands
[i
].reg
= val
;
6262 inst
.operands
[i
].isreg
= 1;
6263 inst
.operands
[i
].present
= 1;
6266 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6267 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6268 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6269 Case 10: VMOV.F32 <Sd>, #<imm>
6270 Case 11: VMOV.F64 <Dd>, #<imm> */
6271 inst
.operands
[i
].immisfloat
= 1;
6272 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6274 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6275 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6279 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6283 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6286 inst
.operands
[i
].reg
= val
;
6287 inst
.operands
[i
].isreg
= 1;
6288 inst
.operands
[i
++].present
= 1;
6290 if (skip_past_comma (&ptr
) == FAIL
)
6293 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6295 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6296 inst
.operands
[i
].reg
= val
;
6297 inst
.operands
[i
].isscalar
= 1;
6298 inst
.operands
[i
].present
= 1;
6299 inst
.operands
[i
].vectype
= optype
;
6301 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6303 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6304 inst
.operands
[i
].reg
= val
;
6305 inst
.operands
[i
].isreg
= 1;
6306 inst
.operands
[i
++].present
= 1;
6308 if (skip_past_comma (&ptr
) == FAIL
)
6311 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6314 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6318 inst
.operands
[i
].reg
= val
;
6319 inst
.operands
[i
].isreg
= 1;
6320 inst
.operands
[i
].isvec
= 1;
6321 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6322 inst
.operands
[i
].vectype
= optype
;
6323 inst
.operands
[i
].present
= 1;
6325 if (rtype
== REG_TYPE_VFS
)
6329 if (skip_past_comma (&ptr
) == FAIL
)
6331 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6334 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6337 inst
.operands
[i
].reg
= val
;
6338 inst
.operands
[i
].isreg
= 1;
6339 inst
.operands
[i
].isvec
= 1;
6340 inst
.operands
[i
].issingle
= 1;
6341 inst
.operands
[i
].vectype
= optype
;
6342 inst
.operands
[i
].present
= 1;
6345 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6349 inst
.operands
[i
].reg
= val
;
6350 inst
.operands
[i
].isreg
= 1;
6351 inst
.operands
[i
].isvec
= 1;
6352 inst
.operands
[i
].issingle
= 1;
6353 inst
.operands
[i
].vectype
= optype
;
6354 inst
.operands
[i
].present
= 1;
6359 first_error (_("parse error"));
6363 /* Successfully parsed the operands. Update args. */
6369 first_error (_("expected comma"));
6373 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6377 /* Use this macro when the operand constraints are different
6378 for ARM and THUMB (e.g. ldrd). */
6379 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6380 ((arm_operand) | ((thumb_operand) << 16))
6382 /* Matcher codes for parse_operands. */
6383 enum operand_parse_code
6385 OP_stop
, /* end of line */
6387 OP_RR
, /* ARM register */
6388 OP_RRnpc
, /* ARM register, not r15 */
6389 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6390 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6391 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6392 optional trailing ! */
6393 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6394 OP_RCP
, /* Coprocessor number */
6395 OP_RCN
, /* Coprocessor register */
6396 OP_RF
, /* FPA register */
6397 OP_RVS
, /* VFP single precision register */
6398 OP_RVD
, /* VFP double precision register (0..15) */
6399 OP_RND
, /* Neon double precision register (0..31) */
6400 OP_RNQ
, /* Neon quad precision register */
6401 OP_RVSD
, /* VFP single or double precision register */
6402 OP_RNDQ
, /* Neon double or quad precision register */
6403 OP_RNSDQ
, /* Neon single, double or quad precision register */
6404 OP_RNSC
, /* Neon scalar D[X] */
6405 OP_RVC
, /* VFP control register */
6406 OP_RMF
, /* Maverick F register */
6407 OP_RMD
, /* Maverick D register */
6408 OP_RMFX
, /* Maverick FX register */
6409 OP_RMDX
, /* Maverick DX register */
6410 OP_RMAX
, /* Maverick AX register */
6411 OP_RMDS
, /* Maverick DSPSC register */
6412 OP_RIWR
, /* iWMMXt wR register */
6413 OP_RIWC
, /* iWMMXt wC register */
6414 OP_RIWG
, /* iWMMXt wCG register */
6415 OP_RXA
, /* XScale accumulator register */
6417 OP_REGLST
, /* ARM register list */
6418 OP_VRSLST
, /* VFP single-precision register list */
6419 OP_VRDLST
, /* VFP double-precision register list */
6420 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6421 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6422 OP_NSTRLST
, /* Neon element/structure list */
6424 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6425 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6426 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6427 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6428 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6429 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6430 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6431 OP_VMOV
, /* Neon VMOV operands. */
6432 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6433 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6434 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6436 OP_I0
, /* immediate zero */
6437 OP_I7
, /* immediate value 0 .. 7 */
6438 OP_I15
, /* 0 .. 15 */
6439 OP_I16
, /* 1 .. 16 */
6440 OP_I16z
, /* 0 .. 16 */
6441 OP_I31
, /* 0 .. 31 */
6442 OP_I31w
, /* 0 .. 31, optional trailing ! */
6443 OP_I32
, /* 1 .. 32 */
6444 OP_I32z
, /* 0 .. 32 */
6445 OP_I63
, /* 0 .. 63 */
6446 OP_I63s
, /* -64 .. 63 */
6447 OP_I64
, /* 1 .. 64 */
6448 OP_I64z
, /* 0 .. 64 */
6449 OP_I255
, /* 0 .. 255 */
6451 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6452 OP_I7b
, /* 0 .. 7 */
6453 OP_I15b
, /* 0 .. 15 */
6454 OP_I31b
, /* 0 .. 31 */
6456 OP_SH
, /* shifter operand */
6457 OP_SHG
, /* shifter operand with possible group relocation */
6458 OP_ADDR
, /* Memory address expression (any mode) */
6459 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6460 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6461 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6462 OP_EXP
, /* arbitrary expression */
6463 OP_EXPi
, /* same, with optional immediate prefix */
6464 OP_EXPr
, /* same, with optional relocation suffix */
6465 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6467 OP_CPSF
, /* CPS flags */
6468 OP_ENDI
, /* Endianness specifier */
6469 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6470 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6471 OP_COND
, /* conditional code */
6472 OP_TB
, /* Table branch. */
6474 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6476 OP_RRnpc_I0
, /* ARM register or literal 0 */
6477 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6478 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6479 OP_RF_IF
, /* FPA register or immediate */
6480 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6481 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6483 /* Optional operands. */
6484 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6485 OP_oI31b
, /* 0 .. 31 */
6486 OP_oI32b
, /* 1 .. 32 */
6487 OP_oI32z
, /* 0 .. 32 */
6488 OP_oIffffb
, /* 0 .. 65535 */
6489 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6491 OP_oRR
, /* ARM register */
6492 OP_oRRnpc
, /* ARM register, not the PC */
6493 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6494 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6495 OP_oRND
, /* Optional Neon double precision register */
6496 OP_oRNQ
, /* Optional Neon quad precision register */
6497 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6498 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6499 OP_oSHll
, /* LSL immediate */
6500 OP_oSHar
, /* ASR immediate */
6501 OP_oSHllar
, /* LSL or ASR immediate */
6502 OP_oROR
, /* ROR 0/8/16/24 */
6503 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6505 /* Some pre-defined mixed (ARM/THUMB) operands. */
6506 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6507 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6508 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6510 OP_FIRST_OPTIONAL
= OP_oI7b
6513 /* Generic instruction operand parser. This does no encoding and no
6514 semantic validation; it merely squirrels values away in the inst
6515 structure. Returns SUCCESS or FAIL depending on whether the
6516 specified grammar matched. */
6518 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6520 unsigned const int *upat
= pattern
;
6521 char *backtrack_pos
= 0;
6522 const char *backtrack_error
= 0;
6523 int i
, val
= 0, backtrack_index
= 0;
6524 enum arm_reg_type rtype
;
6525 parse_operand_result result
;
6526 unsigned int op_parse_code
;
6528 #define po_char_or_fail(chr) \
6531 if (skip_past_char (&str, chr) == FAIL) \
6536 #define po_reg_or_fail(regtype) \
6539 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6540 & inst.operands[i].vectype); \
6543 first_error (_(reg_expected_msgs[regtype])); \
6546 inst.operands[i].reg = val; \
6547 inst.operands[i].isreg = 1; \
6548 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6549 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6550 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6551 || rtype == REG_TYPE_VFD \
6552 || rtype == REG_TYPE_NQ); \
6556 #define po_reg_or_goto(regtype, label) \
6559 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6560 & inst.operands[i].vectype); \
6564 inst.operands[i].reg = val; \
6565 inst.operands[i].isreg = 1; \
6566 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6567 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6568 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6569 || rtype == REG_TYPE_VFD \
6570 || rtype == REG_TYPE_NQ); \
6574 #define po_imm_or_fail(min, max, popt) \
6577 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6579 inst.operands[i].imm = val; \
6583 #define po_scalar_or_goto(elsz, label) \
6586 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6589 inst.operands[i].reg = val; \
6590 inst.operands[i].isscalar = 1; \
6594 #define po_misc_or_fail(expr) \
6602 #define po_misc_or_fail_no_backtrack(expr) \
6606 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6607 backtrack_pos = 0; \
6608 if (result != PARSE_OPERAND_SUCCESS) \
6613 #define po_barrier_or_imm(str) \
6616 val = parse_barrier (&str); \
6617 if (val == FAIL && ! ISALPHA (*str)) \
6620 /* ISB can only take SY as an option. */ \
6621 || ((inst.instruction & 0xf0) == 0x60 \
6624 inst.error = _("invalid barrier type"); \
6625 backtrack_pos = 0; \
6631 skip_whitespace (str
);
6633 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6635 op_parse_code
= upat
[i
];
6636 if (op_parse_code
>= 1<<16)
6637 op_parse_code
= thumb
? (op_parse_code
>> 16)
6638 : (op_parse_code
& ((1<<16)-1));
6640 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6642 /* Remember where we are in case we need to backtrack. */
6643 gas_assert (!backtrack_pos
);
6644 backtrack_pos
= str
;
6645 backtrack_error
= inst
.error
;
6646 backtrack_index
= i
;
6649 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6650 po_char_or_fail (',');
6652 switch (op_parse_code
)
6660 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6661 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6662 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6663 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6664 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6665 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6667 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6669 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6671 /* Also accept generic coprocessor regs for unknown registers. */
6673 po_reg_or_fail (REG_TYPE_CN
);
6675 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6676 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6677 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6678 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6679 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6680 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6681 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6682 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6683 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6684 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6686 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6688 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6689 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6691 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6693 /* Neon scalar. Using an element size of 8 means that some invalid
6694 scalars are accepted here, so deal with those in later code. */
6695 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6699 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6702 po_imm_or_fail (0, 0, TRUE
);
6707 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6712 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6715 if (parse_ifimm_zero (&str
))
6716 inst
.operands
[i
].imm
= 0;
6720 = _("only floating point zero is allowed as immediate value");
6728 po_scalar_or_goto (8, try_rr
);
6731 po_reg_or_fail (REG_TYPE_RN
);
6737 po_scalar_or_goto (8, try_nsdq
);
6740 po_reg_or_fail (REG_TYPE_NSDQ
);
6746 po_scalar_or_goto (8, try_ndq
);
6749 po_reg_or_fail (REG_TYPE_NDQ
);
6755 po_scalar_or_goto (8, try_vfd
);
6758 po_reg_or_fail (REG_TYPE_VFD
);
6763 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6764 not careful then bad things might happen. */
6765 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6770 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6773 /* There's a possibility of getting a 64-bit immediate here, so
6774 we need special handling. */
6775 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6778 inst
.error
= _("immediate value is out of range");
6786 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6789 po_imm_or_fail (0, 63, TRUE
);
6794 po_char_or_fail ('[');
6795 po_reg_or_fail (REG_TYPE_RN
);
6796 po_char_or_fail (']');
6802 po_reg_or_fail (REG_TYPE_RN
);
6803 if (skip_past_char (&str
, '!') == SUCCESS
)
6804 inst
.operands
[i
].writeback
= 1;
6808 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6809 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6810 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6811 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6812 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6813 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6814 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6815 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6816 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6817 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6818 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6819 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6821 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6823 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6824 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6826 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6827 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6828 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6829 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6831 /* Immediate variants */
6833 po_char_or_fail ('{');
6834 po_imm_or_fail (0, 255, TRUE
);
6835 po_char_or_fail ('}');
6839 /* The expression parser chokes on a trailing !, so we have
6840 to find it first and zap it. */
6843 while (*s
&& *s
!= ',')
6848 inst
.operands
[i
].writeback
= 1;
6850 po_imm_or_fail (0, 31, TRUE
);
6858 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6863 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6868 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6870 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6872 val
= parse_reloc (&str
);
6875 inst
.error
= _("unrecognized relocation suffix");
6878 else if (val
!= BFD_RELOC_UNUSED
)
6880 inst
.operands
[i
].imm
= val
;
6881 inst
.operands
[i
].hasreloc
= 1;
6886 /* Operand for MOVW or MOVT. */
6888 po_misc_or_fail (parse_half (&str
));
6891 /* Register or expression. */
6892 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6893 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6895 /* Register or immediate. */
6896 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6897 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6899 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6901 if (!is_immediate_prefix (*str
))
6904 val
= parse_fpa_immediate (&str
);
6907 /* FPA immediates are encoded as registers 8-15.
6908 parse_fpa_immediate has already applied the offset. */
6909 inst
.operands
[i
].reg
= val
;
6910 inst
.operands
[i
].isreg
= 1;
6913 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6914 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6916 /* Two kinds of register. */
6919 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6921 || (rege
->type
!= REG_TYPE_MMXWR
6922 && rege
->type
!= REG_TYPE_MMXWC
6923 && rege
->type
!= REG_TYPE_MMXWCG
))
6925 inst
.error
= _("iWMMXt data or control register expected");
6928 inst
.operands
[i
].reg
= rege
->number
;
6929 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6935 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6937 || (rege
->type
!= REG_TYPE_MMXWC
6938 && rege
->type
!= REG_TYPE_MMXWCG
))
6940 inst
.error
= _("iWMMXt control register expected");
6943 inst
.operands
[i
].reg
= rege
->number
;
6944 inst
.operands
[i
].isreg
= 1;
6949 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6950 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6951 case OP_oROR
: val
= parse_ror (&str
); break;
6952 case OP_COND
: val
= parse_cond (&str
); break;
6953 case OP_oBARRIER_I15
:
6954 po_barrier_or_imm (str
); break;
6956 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6962 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
6963 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
6965 inst
.error
= _("Banked registers are not available with this "
6971 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
6975 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6978 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6980 if (strncasecmp (str
, "APSR_", 5) == 0)
6987 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6988 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6989 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6990 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6991 default: found
= 16;
6995 inst
.operands
[i
].isvec
= 1;
6996 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6997 inst
.operands
[i
].reg
= REG_PC
;
7004 po_misc_or_fail (parse_tb (&str
));
7007 /* Register lists. */
7009 val
= parse_reg_list (&str
);
7012 inst
.operands
[i
].writeback
= 1;
7018 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7022 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7026 /* Allow Q registers too. */
7027 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7032 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7034 inst
.operands
[i
].issingle
= 1;
7039 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7044 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7045 &inst
.operands
[i
].vectype
);
7048 /* Addressing modes */
7050 po_misc_or_fail (parse_address (&str
, i
));
7054 po_misc_or_fail_no_backtrack (
7055 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7059 po_misc_or_fail_no_backtrack (
7060 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7064 po_misc_or_fail_no_backtrack (
7065 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7069 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7073 po_misc_or_fail_no_backtrack (
7074 parse_shifter_operand_group_reloc (&str
, i
));
7078 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7082 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7086 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7090 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7093 /* Various value-based sanity checks and shared operations. We
7094 do not signal immediate failures for the register constraints;
7095 this allows a syntax error to take precedence. */
7096 switch (op_parse_code
)
7104 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7105 inst
.error
= BAD_PC
;
7110 if (inst
.operands
[i
].isreg
)
7112 if (inst
.operands
[i
].reg
== REG_PC
)
7113 inst
.error
= BAD_PC
;
7114 else if (inst
.operands
[i
].reg
== REG_SP
)
7115 inst
.error
= BAD_SP
;
7120 if (inst
.operands
[i
].isreg
7121 && inst
.operands
[i
].reg
== REG_PC
7122 && (inst
.operands
[i
].writeback
|| thumb
))
7123 inst
.error
= BAD_PC
;
7132 case OP_oBARRIER_I15
:
7141 inst
.operands
[i
].imm
= val
;
7148 /* If we get here, this operand was successfully parsed. */
7149 inst
.operands
[i
].present
= 1;
7153 inst
.error
= BAD_ARGS
;
7158 /* The parse routine should already have set inst.error, but set a
7159 default here just in case. */
7161 inst
.error
= _("syntax error");
7165 /* Do not backtrack over a trailing optional argument that
7166 absorbed some text. We will only fail again, with the
7167 'garbage following instruction' error message, which is
7168 probably less helpful than the current one. */
7169 if (backtrack_index
== i
&& backtrack_pos
!= str
7170 && upat
[i
+1] == OP_stop
)
7173 inst
.error
= _("syntax error");
7177 /* Try again, skipping the optional argument at backtrack_pos. */
7178 str
= backtrack_pos
;
7179 inst
.error
= backtrack_error
;
7180 inst
.operands
[backtrack_index
].present
= 0;
7181 i
= backtrack_index
;
7185 /* Check that we have parsed all the arguments. */
7186 if (*str
!= '\0' && !inst
.error
)
7187 inst
.error
= _("garbage following instruction");
7189 return inst
.error
? FAIL
: SUCCESS
;
7192 #undef po_char_or_fail
7193 #undef po_reg_or_fail
7194 #undef po_reg_or_goto
7195 #undef po_imm_or_fail
7196 #undef po_scalar_or_fail
7197 #undef po_barrier_or_imm
7199 /* Shorthand macro for instruction encoding functions issuing errors. */
7200 #define constraint(expr, err) \
7211 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7212 instructions are unpredictable if these registers are used. This
7213 is the BadReg predicate in ARM's Thumb-2 documentation. */
7214 #define reject_bad_reg(reg) \
7216 if (reg == REG_SP || reg == REG_PC) \
7218 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7223 /* If REG is R13 (the stack pointer), warn that its use is
7225 #define warn_deprecated_sp(reg) \
7227 if (warn_on_deprecated && reg == REG_SP) \
7228 as_tsktsk (_("use of r13 is deprecated")); \
7231 /* Functions for operand encoding. ARM, then Thumb. */
7233 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7235 /* If VAL can be encoded in the immediate field of an ARM instruction,
7236 return the encoded form. Otherwise, return FAIL. */
7239 encode_arm_immediate (unsigned int val
)
7243 for (i
= 0; i
< 32; i
+= 2)
7244 if ((a
= rotate_left (val
, i
)) <= 0xff)
7245 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7250 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7251 return the encoded form. Otherwise, return FAIL. */
7253 encode_thumb32_immediate (unsigned int val
)
7260 for (i
= 1; i
<= 24; i
++)
7263 if ((val
& ~(0xff << i
)) == 0)
7264 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7268 if (val
== ((a
<< 16) | a
))
7270 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7274 if (val
== ((a
<< 16) | a
))
7275 return 0x200 | (a
>> 8);
7279 /* Encode a VFP SP or DP register number into inst.instruction. */
7282 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7284 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7287 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7290 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7293 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7298 first_error (_("D register out of range for selected VFP version"));
7306 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7310 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7314 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7318 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7322 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7326 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7334 /* Encode a <shift> in an ARM-format instruction. The immediate,
7335 if any, is handled by md_apply_fix. */
7337 encode_arm_shift (int i
)
7339 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7340 inst
.instruction
|= SHIFT_ROR
<< 5;
7343 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7344 if (inst
.operands
[i
].immisreg
)
7346 inst
.instruction
|= SHIFT_BY_REG
;
7347 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7350 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7355 encode_arm_shifter_operand (int i
)
7357 if (inst
.operands
[i
].isreg
)
7359 inst
.instruction
|= inst
.operands
[i
].reg
;
7360 encode_arm_shift (i
);
7364 inst
.instruction
|= INST_IMMEDIATE
;
7365 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7366 inst
.instruction
|= inst
.operands
[i
].imm
;
7370 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7372 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7375 Generate an error if the operand is not a register. */
7376 constraint (!inst
.operands
[i
].isreg
,
7377 _("Instruction does not support =N addresses"));
7379 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7381 if (inst
.operands
[i
].preind
)
7385 inst
.error
= _("instruction does not accept preindexed addressing");
7388 inst
.instruction
|= PRE_INDEX
;
7389 if (inst
.operands
[i
].writeback
)
7390 inst
.instruction
|= WRITE_BACK
;
7393 else if (inst
.operands
[i
].postind
)
7395 gas_assert (inst
.operands
[i
].writeback
);
7397 inst
.instruction
|= WRITE_BACK
;
7399 else /* unindexed - only for coprocessor */
7401 inst
.error
= _("instruction does not accept unindexed addressing");
7405 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7406 && (((inst
.instruction
& 0x000f0000) >> 16)
7407 == ((inst
.instruction
& 0x0000f000) >> 12)))
7408 as_warn ((inst
.instruction
& LOAD_BIT
)
7409 ? _("destination register same as write-back base")
7410 : _("source register same as write-back base"));
7413 /* inst.operands[i] was set up by parse_address. Encode it into an
7414 ARM-format mode 2 load or store instruction. If is_t is true,
7415 reject forms that cannot be used with a T instruction (i.e. not
7418 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7420 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7422 encode_arm_addr_mode_common (i
, is_t
);
7424 if (inst
.operands
[i
].immisreg
)
7426 constraint ((inst
.operands
[i
].imm
== REG_PC
7427 || (is_pc
&& inst
.operands
[i
].writeback
)),
7429 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7430 inst
.instruction
|= inst
.operands
[i
].imm
;
7431 if (!inst
.operands
[i
].negative
)
7432 inst
.instruction
|= INDEX_UP
;
7433 if (inst
.operands
[i
].shifted
)
7435 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7436 inst
.instruction
|= SHIFT_ROR
<< 5;
7439 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7440 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7444 else /* immediate offset in inst.reloc */
7446 if (is_pc
&& !inst
.reloc
.pc_rel
)
7448 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7450 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7451 cannot use PC in addressing.
7452 PC cannot be used in writeback addressing, either. */
7453 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7456 /* Use of PC in str is deprecated for ARMv7. */
7457 if (warn_on_deprecated
7459 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7460 as_tsktsk (_("use of PC in this instruction is deprecated"));
7463 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7465 /* Prefer + for zero encoded value. */
7466 if (!inst
.operands
[i
].negative
)
7467 inst
.instruction
|= INDEX_UP
;
7468 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7473 /* inst.operands[i] was set up by parse_address. Encode it into an
7474 ARM-format mode 3 load or store instruction. Reject forms that
7475 cannot be used with such instructions. If is_t is true, reject
7476 forms that cannot be used with a T instruction (i.e. not
7479 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7481 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7483 inst
.error
= _("instruction does not accept scaled register index");
7487 encode_arm_addr_mode_common (i
, is_t
);
7489 if (inst
.operands
[i
].immisreg
)
7491 constraint ((inst
.operands
[i
].imm
== REG_PC
7492 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7494 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7496 inst
.instruction
|= inst
.operands
[i
].imm
;
7497 if (!inst
.operands
[i
].negative
)
7498 inst
.instruction
|= INDEX_UP
;
7500 else /* immediate offset in inst.reloc */
7502 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7503 && inst
.operands
[i
].writeback
),
7505 inst
.instruction
|= HWOFFSET_IMM
;
7506 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7508 /* Prefer + for zero encoded value. */
7509 if (!inst
.operands
[i
].negative
)
7510 inst
.instruction
|= INDEX_UP
;
7512 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7517 /* Write immediate bits [7:0] to the following locations:
7519 |28/24|23 19|18 16|15 4|3 0|
7520 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7522 This function is used by VMOV/VMVN/VORR/VBIC. */
7525 neon_write_immbits (unsigned immbits
)
7527 inst
.instruction
|= immbits
& 0xf;
7528 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7529 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7532 /* Invert low-order SIZE bits of XHI:XLO. */
7535 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7537 unsigned immlo
= xlo
? *xlo
: 0;
7538 unsigned immhi
= xhi
? *xhi
: 0;
7543 immlo
= (~immlo
) & 0xff;
7547 immlo
= (~immlo
) & 0xffff;
7551 immhi
= (~immhi
) & 0xffffffff;
7555 immlo
= (~immlo
) & 0xffffffff;
7569 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7573 neon_bits_same_in_bytes (unsigned imm
)
7575 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7576 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7577 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7578 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7581 /* For immediate of above form, return 0bABCD. */
7584 neon_squash_bits (unsigned imm
)
7586 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7587 | ((imm
& 0x01000000) >> 21);
7590 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7593 neon_qfloat_bits (unsigned imm
)
7595 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7598 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7599 the instruction. *OP is passed as the initial value of the op field, and
7600 may be set to a different value depending on the constant (i.e.
7601 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7602 MVN). If the immediate looks like a repeated pattern then also
7603 try smaller element sizes. */
7606 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7607 unsigned *immbits
, int *op
, int size
,
7608 enum neon_el_type type
)
7610 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7612 if (type
== NT_float
&& !float_p
)
7615 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7617 if (size
!= 32 || *op
== 1)
7619 *immbits
= neon_qfloat_bits (immlo
);
7625 if (neon_bits_same_in_bytes (immhi
)
7626 && neon_bits_same_in_bytes (immlo
))
7630 *immbits
= (neon_squash_bits (immhi
) << 4)
7631 | neon_squash_bits (immlo
);
7642 if (immlo
== (immlo
& 0x000000ff))
7647 else if (immlo
== (immlo
& 0x0000ff00))
7649 *immbits
= immlo
>> 8;
7652 else if (immlo
== (immlo
& 0x00ff0000))
7654 *immbits
= immlo
>> 16;
7657 else if (immlo
== (immlo
& 0xff000000))
7659 *immbits
= immlo
>> 24;
7662 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7664 *immbits
= (immlo
>> 8) & 0xff;
7667 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7669 *immbits
= (immlo
>> 16) & 0xff;
7673 if ((immlo
& 0xffff) != (immlo
>> 16))
7680 if (immlo
== (immlo
& 0x000000ff))
7685 else if (immlo
== (immlo
& 0x0000ff00))
7687 *immbits
= immlo
>> 8;
7691 if ((immlo
& 0xff) != (immlo
>> 8))
7696 if (immlo
== (immlo
& 0x000000ff))
7698 /* Don't allow MVN with 8-bit immediate. */
7708 #if defined BFD_HOST_64_BIT
7709 /* Returns TRUE if double precision value V may be cast
7710 to single precision without loss of accuracy. */
7713 is_double_a_single (bfd_int64_t v
)
7715 int exp
= (int)((v
>> 52) & 0x7FF);
7716 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7718 return (exp
== 0 || exp
== 0x7FF
7719 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7720 && (mantissa
& 0x1FFFFFFFl
) == 0;
7723 /* Returns a double precision value casted to single precision
7724 (ignoring the least significant bits in exponent and mantissa). */
7727 double_to_single (bfd_int64_t v
)
7729 int sign
= (int) ((v
>> 63) & 1l);
7730 int exp
= (int) ((v
>> 52) & 0x7FF);
7731 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7737 exp
= exp
- 1023 + 127;
7746 /* No denormalized numbers. */
7752 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7754 #endif /* BFD_HOST_64_BIT */
7763 static void do_vfp_nsyn_opcode (const char *);
7765 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7766 Determine whether it can be performed with a move instruction; if
7767 it can, convert inst.instruction to that move instruction and
7768 return TRUE; if it can't, convert inst.instruction to a literal-pool
7769 load and return FALSE. If this is not a valid thing to do in the
7770 current context, set inst.error and return TRUE.
7772 inst.operands[i] describes the destination register. */
7775 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7778 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7779 bfd_boolean arm_p
= (t
== CONST_ARM
);
7782 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7786 if ((inst
.instruction
& tbit
) == 0)
7788 inst
.error
= _("invalid pseudo operation");
7792 if (inst
.reloc
.exp
.X_op
!= O_constant
7793 && inst
.reloc
.exp
.X_op
!= O_symbol
7794 && inst
.reloc
.exp
.X_op
!= O_big
)
7796 inst
.error
= _("constant expression expected");
7800 if (inst
.reloc
.exp
.X_op
== O_constant
7801 || inst
.reloc
.exp
.X_op
== O_big
)
7803 #if defined BFD_HOST_64_BIT
7808 if (inst
.reloc
.exp
.X_op
== O_big
)
7810 LITTLENUM_TYPE w
[X_PRECISION
];
7813 if (inst
.reloc
.exp
.X_add_number
== -1)
7815 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7817 /* FIXME: Should we check words w[2..5] ? */
7822 #if defined BFD_HOST_64_BIT
7824 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
7825 << LITTLENUM_NUMBER_OF_BITS
)
7826 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
7827 << LITTLENUM_NUMBER_OF_BITS
)
7828 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
7829 << LITTLENUM_NUMBER_OF_BITS
)
7830 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
7832 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
7833 | (l
[0] & LITTLENUM_MASK
);
7837 v
= inst
.reloc
.exp
.X_add_number
;
7839 if (!inst
.operands
[i
].issingle
)
7843 if ((v
& ~0xFF) == 0)
7845 /* This can be done with a mov(1) instruction. */
7846 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7847 inst
.instruction
|= v
;
7851 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)
7852 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
7854 /* Check if on thumb2 it can be done with a mov.w or mvn.w instruction. */
7855 unsigned int newimm
;
7856 bfd_boolean isNegated
;
7858 newimm
= encode_thumb32_immediate (v
);
7859 if (newimm
!= (unsigned int) FAIL
)
7863 newimm
= encode_thumb32_immediate (~ v
);
7864 if (newimm
!= (unsigned int) FAIL
)
7868 if (newimm
!= (unsigned int) FAIL
)
7870 inst
.instruction
= 0xf04f0000 | (inst
.operands
[i
].reg
<< 8);
7871 inst
.instruction
|= (isNegated
?0x200000:0);
7872 inst
.instruction
|= (newimm
& 0x800) << 15;
7873 inst
.instruction
|= (newimm
& 0x700) << 4;
7874 inst
.instruction
|= (newimm
& 0x0ff);
7877 else if ((v
& ~0xFFFF) == 0 || (v
& ~0xFFFF0000) == 0)
7879 /* The number may be loaded with a movw/movt instruction. */
7882 if ((inst
.reloc
.exp
.X_add_number
& ~0xFFFF) == 0)
7884 inst
.instruction
= 0xf2400000;
7889 inst
.instruction
= 0xf2c00000;
7893 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
7894 inst
.instruction
|= (imm
& 0xf000) << 4;
7895 inst
.instruction
|= (imm
& 0x0800) << 15;
7896 inst
.instruction
|= (imm
& 0x0700) << 4;
7897 inst
.instruction
|= (imm
& 0x00ff);
7904 int value
= encode_arm_immediate (v
);
7908 /* This can be done with a mov instruction. */
7909 inst
.instruction
&= LITERAL_MASK
;
7910 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7911 inst
.instruction
|= value
& 0xfff;
7915 value
= encode_arm_immediate (~ v
);
7918 /* This can be done with a mvn instruction. */
7919 inst
.instruction
&= LITERAL_MASK
;
7920 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7921 inst
.instruction
|= value
& 0xfff;
7925 else if (t
== CONST_VEC
)
7928 unsigned immbits
= 0;
7929 unsigned immlo
= inst
.operands
[1].imm
;
7930 unsigned immhi
= inst
.operands
[1].regisimm
7931 ? inst
.operands
[1].reg
7932 : inst
.reloc
.exp
.X_unsigned
7934 : ((bfd_int64_t
)((int) immlo
)) >> 32;
7935 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
7936 &op
, 64, NT_invtype
);
7940 neon_invert_size (&immlo
, &immhi
, 64);
7942 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
7943 &op
, 64, NT_invtype
);
7948 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
7954 /* Fill other bits in vmov encoding for both thumb and arm. */
7956 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
7958 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
7959 neon_write_immbits (immbits
);
7967 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
7968 if (inst
.operands
[i
].issingle
7969 && is_quarter_float (inst
.operands
[1].imm
)
7970 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
7972 inst
.operands
[1].imm
=
7973 neon_qfloat_bits (v
);
7974 do_vfp_nsyn_opcode ("fconsts");
7978 /* If our host does not support a 64-bit type then we cannot perform
7979 the following optimization. This mean that there will be a
7980 discrepancy between the output produced by an assembler built for
7981 a 32-bit-only host and the output produced from a 64-bit host, but
7982 this cannot be helped. */
7983 #if defined BFD_HOST_64_BIT
7984 else if (!inst
.operands
[1].issingle
7985 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
7987 if (is_double_a_single (v
)
7988 && is_quarter_float (double_to_single (v
)))
7990 inst
.operands
[1].imm
=
7991 neon_qfloat_bits (double_to_single (v
));
7992 do_vfp_nsyn_opcode ("fconstd");
8000 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8001 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8004 inst
.operands
[1].reg
= REG_PC
;
8005 inst
.operands
[1].isreg
= 1;
8006 inst
.operands
[1].preind
= 1;
8007 inst
.reloc
.pc_rel
= 1;
8008 inst
.reloc
.type
= (thumb_p
8009 ? BFD_RELOC_ARM_THUMB_OFFSET
8011 ? BFD_RELOC_ARM_HWLITERAL
8012 : BFD_RELOC_ARM_LITERAL
));
8016 /* inst.operands[i] was set up by parse_address. Encode it into an
8017 ARM-format instruction. Reject all forms which cannot be encoded
8018 into a coprocessor load/store instruction. If wb_ok is false,
8019 reject use of writeback; if unind_ok is false, reject use of
8020 unindexed addressing. If reloc_override is not 0, use it instead
8021 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8022 (in which case it is preserved). */
8025 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8027 if (!inst
.operands
[i
].isreg
)
8030 if (! inst
.operands
[0].isvec
)
8032 inst
.error
= _("invalid co-processor operand");
8035 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8039 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8041 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8043 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8045 gas_assert (!inst
.operands
[i
].writeback
);
8048 inst
.error
= _("instruction does not support unindexed addressing");
8051 inst
.instruction
|= inst
.operands
[i
].imm
;
8052 inst
.instruction
|= INDEX_UP
;
8056 if (inst
.operands
[i
].preind
)
8057 inst
.instruction
|= PRE_INDEX
;
8059 if (inst
.operands
[i
].writeback
)
8061 if (inst
.operands
[i
].reg
== REG_PC
)
8063 inst
.error
= _("pc may not be used with write-back");
8068 inst
.error
= _("instruction does not support writeback");
8071 inst
.instruction
|= WRITE_BACK
;
8075 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8076 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8077 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8078 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8081 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8083 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8086 /* Prefer + for zero encoded value. */
8087 if (!inst
.operands
[i
].negative
)
8088 inst
.instruction
|= INDEX_UP
;
8093 /* Functions for instruction encoding, sorted by sub-architecture.
8094 First some generics; their names are taken from the conventional
8095 bit positions for register arguments in ARM format instructions. */
8105 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8111 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8112 inst
.instruction
|= inst
.operands
[1].reg
;
8118 inst
.instruction
|= inst
.operands
[0].reg
;
8119 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8125 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8126 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8132 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8133 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8137 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8139 if (ARM_CPU_IS_ANY (cpu_variant
))
8141 as_tsktsk ("%s", msg
);
8144 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8156 unsigned Rn
= inst
.operands
[2].reg
;
8157 /* Enforce restrictions on SWP instruction. */
8158 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8160 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8161 _("Rn must not overlap other operands"));
8163 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8165 if (!check_obsolete (&arm_ext_v8
,
8166 _("swp{b} use is obsoleted for ARMv8 and later"))
8167 && warn_on_deprecated
8168 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8169 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8172 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8173 inst
.instruction
|= inst
.operands
[1].reg
;
8174 inst
.instruction
|= Rn
<< 16;
8180 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8181 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8182 inst
.instruction
|= inst
.operands
[2].reg
;
8188 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8189 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8190 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8191 || inst
.reloc
.exp
.X_add_number
!= 0),
8193 inst
.instruction
|= inst
.operands
[0].reg
;
8194 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8195 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8201 inst
.instruction
|= inst
.operands
[0].imm
;
8207 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8208 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8211 /* ARM instructions, in alphabetical order by function name (except
8212 that wrapper functions appear immediately after the function they
8215 /* This is a pseudo-op of the form "adr rd, label" to be converted
8216 into a relative address of the form "add rd, pc, #label-.-8". */
8221 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8223 /* Frag hacking will turn this into a sub instruction if the offset turns
8224 out to be negative. */
8225 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8226 inst
.reloc
.pc_rel
= 1;
8227 inst
.reloc
.exp
.X_add_number
-= 8;
8230 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8231 into a relative address of the form:
8232 add rd, pc, #low(label-.-8)"
8233 add rd, rd, #high(label-.-8)" */
8238 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8240 /* Frag hacking will turn this into a sub instruction if the offset turns
8241 out to be negative. */
8242 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8243 inst
.reloc
.pc_rel
= 1;
8244 inst
.size
= INSN_SIZE
* 2;
8245 inst
.reloc
.exp
.X_add_number
-= 8;
8251 if (!inst
.operands
[1].present
)
8252 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8253 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8254 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8255 encode_arm_shifter_operand (2);
8261 if (inst
.operands
[0].present
)
8262 inst
.instruction
|= inst
.operands
[0].imm
;
8264 inst
.instruction
|= 0xf;
8270 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8271 constraint (msb
> 32, _("bit-field extends past end of register"));
8272 /* The instruction encoding stores the LSB and MSB,
8273 not the LSB and width. */
8274 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8275 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8276 inst
.instruction
|= (msb
- 1) << 16;
8284 /* #0 in second position is alternative syntax for bfc, which is
8285 the same instruction but with REG_PC in the Rm field. */
8286 if (!inst
.operands
[1].isreg
)
8287 inst
.operands
[1].reg
= REG_PC
;
8289 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8290 constraint (msb
> 32, _("bit-field extends past end of register"));
8291 /* The instruction encoding stores the LSB and MSB,
8292 not the LSB and width. */
8293 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8294 inst
.instruction
|= inst
.operands
[1].reg
;
8295 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8296 inst
.instruction
|= (msb
- 1) << 16;
8302 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8303 _("bit-field extends past end of register"));
8304 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8305 inst
.instruction
|= inst
.operands
[1].reg
;
8306 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8307 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8310 /* ARM V5 breakpoint instruction (argument parse)
8311 BKPT <16 bit unsigned immediate>
8312 Instruction is not conditional.
8313 The bit pattern given in insns[] has the COND_ALWAYS condition,
8314 and it is an error if the caller tried to override that. */
8319 /* Top 12 of 16 bits to bits 19:8. */
8320 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8322 /* Bottom 4 of 16 bits to bits 3:0. */
8323 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8327 encode_branch (int default_reloc
)
8329 if (inst
.operands
[0].hasreloc
)
8331 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8332 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8333 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8334 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8335 ? BFD_RELOC_ARM_PLT32
8336 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8339 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8340 inst
.reloc
.pc_rel
= 1;
8347 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8348 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8351 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8358 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8360 if (inst
.cond
== COND_ALWAYS
)
8361 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8363 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8367 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8370 /* ARM V5 branch-link-exchange instruction (argument parse)
8371 BLX <target_addr> ie BLX(1)
8372 BLX{<condition>} <Rm> ie BLX(2)
8373 Unfortunately, there are two different opcodes for this mnemonic.
8374 So, the insns[].value is not used, and the code here zaps values
8375 into inst.instruction.
8376 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8381 if (inst
.operands
[0].isreg
)
8383 /* Arg is a register; the opcode provided by insns[] is correct.
8384 It is not illegal to do "blx pc", just useless. */
8385 if (inst
.operands
[0].reg
== REG_PC
)
8386 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8388 inst
.instruction
|= inst
.operands
[0].reg
;
8392 /* Arg is an address; this instruction cannot be executed
8393 conditionally, and the opcode must be adjusted.
8394 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8395 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8396 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8397 inst
.instruction
= 0xfa000000;
8398 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8405 bfd_boolean want_reloc
;
8407 if (inst
.operands
[0].reg
== REG_PC
)
8408 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8410 inst
.instruction
|= inst
.operands
[0].reg
;
8411 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8412 it is for ARMv4t or earlier. */
8413 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8414 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8418 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8423 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8427 /* ARM v5TEJ. Jump to Jazelle code. */
8432 if (inst
.operands
[0].reg
== REG_PC
)
8433 as_tsktsk (_("use of r15 in bxj is not really useful"));
8435 inst
.instruction
|= inst
.operands
[0].reg
;
8438 /* Co-processor data operation:
8439 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8440 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8444 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8445 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8446 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8447 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8448 inst
.instruction
|= inst
.operands
[4].reg
;
8449 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8455 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8456 encode_arm_shifter_operand (1);
8459 /* Transfer between coprocessor and ARM registers.
8460 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8465 No special properties. */
8467 struct deprecated_coproc_regs_s
8474 arm_feature_set deprecated
;
8475 arm_feature_set obsoleted
;
8476 const char *dep_msg
;
8477 const char *obs_msg
;
8480 #define DEPR_ACCESS_V8 \
8481 N_("This coprocessor register access is deprecated in ARMv8")
8483 /* Table of all deprecated coprocessor registers. */
8484 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8486 {15, 0, 7, 10, 5, /* CP15DMB. */
8487 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8488 DEPR_ACCESS_V8
, NULL
},
8489 {15, 0, 7, 10, 4, /* CP15DSB. */
8490 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8491 DEPR_ACCESS_V8
, NULL
},
8492 {15, 0, 7, 5, 4, /* CP15ISB. */
8493 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8494 DEPR_ACCESS_V8
, NULL
},
8495 {14, 6, 1, 0, 0, /* TEEHBR. */
8496 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8497 DEPR_ACCESS_V8
, NULL
},
8498 {14, 6, 0, 0, 0, /* TEECR. */
8499 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8500 DEPR_ACCESS_V8
, NULL
},
8503 #undef DEPR_ACCESS_V8
8505 static const size_t deprecated_coproc_reg_count
=
8506 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8514 Rd
= inst
.operands
[2].reg
;
8517 if (inst
.instruction
== 0xee000010
8518 || inst
.instruction
== 0xfe000010)
8520 reject_bad_reg (Rd
);
8523 constraint (Rd
== REG_SP
, BAD_SP
);
8528 if (inst
.instruction
== 0xe000010)
8529 constraint (Rd
== REG_PC
, BAD_PC
);
8532 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8534 const struct deprecated_coproc_regs_s
*r
=
8535 deprecated_coproc_regs
+ i
;
8537 if (inst
.operands
[0].reg
== r
->cp
8538 && inst
.operands
[1].imm
== r
->opc1
8539 && inst
.operands
[3].reg
== r
->crn
8540 && inst
.operands
[4].reg
== r
->crm
8541 && inst
.operands
[5].imm
== r
->opc2
)
8543 if (! ARM_CPU_IS_ANY (cpu_variant
)
8544 && warn_on_deprecated
8545 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8546 as_tsktsk ("%s", r
->dep_msg
);
8550 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8551 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8552 inst
.instruction
|= Rd
<< 12;
8553 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8554 inst
.instruction
|= inst
.operands
[4].reg
;
8555 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8558 /* Transfer between coprocessor register and pair of ARM registers.
8559 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8564 Two XScale instructions are special cases of these:
8566 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8567 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8569 Result unpredictable if Rd or Rn is R15. */
8576 Rd
= inst
.operands
[2].reg
;
8577 Rn
= inst
.operands
[3].reg
;
8581 reject_bad_reg (Rd
);
8582 reject_bad_reg (Rn
);
8586 constraint (Rd
== REG_PC
, BAD_PC
);
8587 constraint (Rn
== REG_PC
, BAD_PC
);
8590 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8591 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8592 inst
.instruction
|= Rd
<< 12;
8593 inst
.instruction
|= Rn
<< 16;
8594 inst
.instruction
|= inst
.operands
[4].reg
;
8600 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8601 if (inst
.operands
[1].present
)
8603 inst
.instruction
|= CPSI_MMOD
;
8604 inst
.instruction
|= inst
.operands
[1].imm
;
8611 inst
.instruction
|= inst
.operands
[0].imm
;
8617 unsigned Rd
, Rn
, Rm
;
8619 Rd
= inst
.operands
[0].reg
;
8620 Rn
= (inst
.operands
[1].present
8621 ? inst
.operands
[1].reg
: Rd
);
8622 Rm
= inst
.operands
[2].reg
;
8624 constraint ((Rd
== REG_PC
), BAD_PC
);
8625 constraint ((Rn
== REG_PC
), BAD_PC
);
8626 constraint ((Rm
== REG_PC
), BAD_PC
);
8628 inst
.instruction
|= Rd
<< 16;
8629 inst
.instruction
|= Rn
<< 0;
8630 inst
.instruction
|= Rm
<< 8;
8636 /* There is no IT instruction in ARM mode. We
8637 process it to do the validation as if in
8638 thumb mode, just in case the code gets
8639 assembled for thumb using the unified syntax. */
8644 set_it_insn_type (IT_INSN
);
8645 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8646 now_it
.cc
= inst
.operands
[0].imm
;
8650 /* If there is only one register in the register list,
8651 then return its register number. Otherwise return -1. */
8653 only_one_reg_in_list (int range
)
8655 int i
= ffs (range
) - 1;
8656 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8660 encode_ldmstm(int from_push_pop_mnem
)
8662 int base_reg
= inst
.operands
[0].reg
;
8663 int range
= inst
.operands
[1].imm
;
8666 inst
.instruction
|= base_reg
<< 16;
8667 inst
.instruction
|= range
;
8669 if (inst
.operands
[1].writeback
)
8670 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8672 if (inst
.operands
[0].writeback
)
8674 inst
.instruction
|= WRITE_BACK
;
8675 /* Check for unpredictable uses of writeback. */
8676 if (inst
.instruction
& LOAD_BIT
)
8678 /* Not allowed in LDM type 2. */
8679 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8680 && ((range
& (1 << REG_PC
)) == 0))
8681 as_warn (_("writeback of base register is UNPREDICTABLE"));
8682 /* Only allowed if base reg not in list for other types. */
8683 else if (range
& (1 << base_reg
))
8684 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8688 /* Not allowed for type 2. */
8689 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8690 as_warn (_("writeback of base register is UNPREDICTABLE"));
8691 /* Only allowed if base reg not in list, or first in list. */
8692 else if ((range
& (1 << base_reg
))
8693 && (range
& ((1 << base_reg
) - 1)))
8694 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8698 /* If PUSH/POP has only one register, then use the A2 encoding. */
8699 one_reg
= only_one_reg_in_list (range
);
8700 if (from_push_pop_mnem
&& one_reg
>= 0)
8702 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8704 inst
.instruction
&= A_COND_MASK
;
8705 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8706 inst
.instruction
|= one_reg
<< 12;
8713 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8716 /* ARMv5TE load-consecutive (argument parse)
8725 constraint (inst
.operands
[0].reg
% 2 != 0,
8726 _("first transfer register must be even"));
8727 constraint (inst
.operands
[1].present
8728 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8729 _("can only transfer two consecutive registers"));
8730 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8731 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8733 if (!inst
.operands
[1].present
)
8734 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8736 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8737 register and the first register written; we have to diagnose
8738 overlap between the base and the second register written here. */
8740 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8741 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8742 as_warn (_("base register written back, and overlaps "
8743 "second transfer register"));
8745 if (!(inst
.instruction
& V4_STR_BIT
))
8747 /* For an index-register load, the index register must not overlap the
8748 destination (even if not write-back). */
8749 if (inst
.operands
[2].immisreg
8750 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8751 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8752 as_warn (_("index register overlaps transfer register"));
8754 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8755 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8761 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8762 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8763 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8764 || inst
.operands
[1].negative
8765 /* This can arise if the programmer has written
8767 or if they have mistakenly used a register name as the last
8770 It is very difficult to distinguish between these two cases
8771 because "rX" might actually be a label. ie the register
8772 name has been occluded by a symbol of the same name. So we
8773 just generate a general 'bad addressing mode' type error
8774 message and leave it up to the programmer to discover the
8775 true cause and fix their mistake. */
8776 || (inst
.operands
[1].reg
== REG_PC
),
8779 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8780 || inst
.reloc
.exp
.X_add_number
!= 0,
8781 _("offset must be zero in ARM encoding"));
8783 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8785 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8786 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8787 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8793 constraint (inst
.operands
[0].reg
% 2 != 0,
8794 _("even register required"));
8795 constraint (inst
.operands
[1].present
8796 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8797 _("can only load two consecutive registers"));
8798 /* If op 1 were present and equal to PC, this function wouldn't
8799 have been called in the first place. */
8800 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8802 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8803 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8806 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8807 which is not a multiple of four is UNPREDICTABLE. */
8809 check_ldr_r15_aligned (void)
8811 constraint (!(inst
.operands
[1].immisreg
)
8812 && (inst
.operands
[0].reg
== REG_PC
8813 && inst
.operands
[1].reg
== REG_PC
8814 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8815 _("ldr to register 15 must be 4-byte alligned"));
8821 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8822 if (!inst
.operands
[1].isreg
)
8823 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8825 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8826 check_ldr_r15_aligned ();
8832 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8834 if (inst
.operands
[1].preind
)
8836 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8837 || inst
.reloc
.exp
.X_add_number
!= 0,
8838 _("this instruction requires a post-indexed address"));
8840 inst
.operands
[1].preind
= 0;
8841 inst
.operands
[1].postind
= 1;
8842 inst
.operands
[1].writeback
= 1;
8844 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8845 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8848 /* Halfword and signed-byte load/store operations. */
8853 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8854 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8855 if (!inst
.operands
[1].isreg
)
8856 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
8858 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
8864 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8866 if (inst
.operands
[1].preind
)
8868 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8869 || inst
.reloc
.exp
.X_add_number
!= 0,
8870 _("this instruction requires a post-indexed address"));
8872 inst
.operands
[1].preind
= 0;
8873 inst
.operands
[1].postind
= 1;
8874 inst
.operands
[1].writeback
= 1;
8876 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8877 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
8880 /* Co-processor register load/store.
8881 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8885 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8886 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8887 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8893 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8894 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8895 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
8896 && !(inst
.instruction
& 0x00400000))
8897 as_tsktsk (_("Rd and Rm should be different in mla"));
8899 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8900 inst
.instruction
|= inst
.operands
[1].reg
;
8901 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8902 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8908 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8909 encode_arm_shifter_operand (1);
8912 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8919 top
= (inst
.instruction
& 0x00400000) != 0;
8920 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
8921 _(":lower16: not allowed this instruction"));
8922 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
8923 _(":upper16: not allowed instruction"));
8924 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8925 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
8927 imm
= inst
.reloc
.exp
.X_add_number
;
8928 /* The value is in two pieces: 0:11, 16:19. */
8929 inst
.instruction
|= (imm
& 0x00000fff);
8930 inst
.instruction
|= (imm
& 0x0000f000) << 4;
8935 do_vfp_nsyn_mrs (void)
8937 if (inst
.operands
[0].isvec
)
8939 if (inst
.operands
[1].reg
!= 1)
8940 first_error (_("operand 1 must be FPSCR"));
8941 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
8942 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
8943 do_vfp_nsyn_opcode ("fmstat");
8945 else if (inst
.operands
[1].isvec
)
8946 do_vfp_nsyn_opcode ("fmrx");
8954 do_vfp_nsyn_msr (void)
8956 if (inst
.operands
[0].isvec
)
8957 do_vfp_nsyn_opcode ("fmxr");
8967 unsigned Rt
= inst
.operands
[0].reg
;
8969 if (thumb_mode
&& Rt
== REG_SP
)
8971 inst
.error
= BAD_SP
;
8975 /* APSR_ sets isvec. All other refs to PC are illegal. */
8976 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
8978 inst
.error
= BAD_PC
;
8982 /* If we get through parsing the register name, we just insert the number
8983 generated into the instruction without further validation. */
8984 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
8985 inst
.instruction
|= (Rt
<< 12);
8991 unsigned Rt
= inst
.operands
[1].reg
;
8994 reject_bad_reg (Rt
);
8995 else if (Rt
== REG_PC
)
8997 inst
.error
= BAD_PC
;
9001 /* If we get through parsing the register name, we just insert the number
9002 generated into the instruction without further validation. */
9003 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9004 inst
.instruction
|= (Rt
<< 12);
9012 if (do_vfp_nsyn_mrs () == SUCCESS
)
9015 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9016 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9018 if (inst
.operands
[1].isreg
)
9020 br
= inst
.operands
[1].reg
;
9021 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9022 as_bad (_("bad register for mrs"));
9026 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9027 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9029 _("'APSR', 'CPSR' or 'SPSR' expected"));
9030 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9033 inst
.instruction
|= br
;
9036 /* Two possible forms:
9037 "{C|S}PSR_<field>, Rm",
9038 "{C|S}PSR_f, #expression". */
9043 if (do_vfp_nsyn_msr () == SUCCESS
)
9046 inst
.instruction
|= inst
.operands
[0].imm
;
9047 if (inst
.operands
[1].isreg
)
9048 inst
.instruction
|= inst
.operands
[1].reg
;
9051 inst
.instruction
|= INST_IMMEDIATE
;
9052 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9053 inst
.reloc
.pc_rel
= 0;
9060 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9062 if (!inst
.operands
[2].present
)
9063 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9064 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9065 inst
.instruction
|= inst
.operands
[1].reg
;
9066 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9068 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9069 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9070 as_tsktsk (_("Rd and Rm should be different in mul"));
9073 /* Long Multiply Parser
9074 UMULL RdLo, RdHi, Rm, Rs
9075 SMULL RdLo, RdHi, Rm, Rs
9076 UMLAL RdLo, RdHi, Rm, Rs
9077 SMLAL RdLo, RdHi, Rm, Rs. */
9082 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9083 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9084 inst
.instruction
|= inst
.operands
[2].reg
;
9085 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9087 /* rdhi and rdlo must be different. */
9088 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9089 as_tsktsk (_("rdhi and rdlo must be different"));
9091 /* rdhi, rdlo and rm must all be different before armv6. */
9092 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9093 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9094 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9095 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9101 if (inst
.operands
[0].present
9102 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9104 /* Architectural NOP hints are CPSR sets with no bits selected. */
9105 inst
.instruction
&= 0xf0000000;
9106 inst
.instruction
|= 0x0320f000;
9107 if (inst
.operands
[0].present
)
9108 inst
.instruction
|= inst
.operands
[0].imm
;
9112 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9113 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9114 Condition defaults to COND_ALWAYS.
9115 Error if Rd, Rn or Rm are R15. */
9120 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9121 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9122 inst
.instruction
|= inst
.operands
[2].reg
;
9123 if (inst
.operands
[3].present
)
9124 encode_arm_shift (3);
9127 /* ARM V6 PKHTB (Argument Parse). */
9132 if (!inst
.operands
[3].present
)
9134 /* If the shift specifier is omitted, turn the instruction
9135 into pkhbt rd, rm, rn. */
9136 inst
.instruction
&= 0xfff00010;
9137 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9138 inst
.instruction
|= inst
.operands
[1].reg
;
9139 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9143 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9144 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9145 inst
.instruction
|= inst
.operands
[2].reg
;
9146 encode_arm_shift (3);
9150 /* ARMv5TE: Preload-Cache
9151 MP Extensions: Preload for write
9155 Syntactically, like LDR with B=1, W=0, L=1. */
9160 constraint (!inst
.operands
[0].isreg
,
9161 _("'[' expected after PLD mnemonic"));
9162 constraint (inst
.operands
[0].postind
,
9163 _("post-indexed expression used in preload instruction"));
9164 constraint (inst
.operands
[0].writeback
,
9165 _("writeback used in preload instruction"));
9166 constraint (!inst
.operands
[0].preind
,
9167 _("unindexed addressing used in preload instruction"));
9168 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9171 /* ARMv7: PLI <addr_mode> */
9175 constraint (!inst
.operands
[0].isreg
,
9176 _("'[' expected after PLI mnemonic"));
9177 constraint (inst
.operands
[0].postind
,
9178 _("post-indexed expression used in preload instruction"));
9179 constraint (inst
.operands
[0].writeback
,
9180 _("writeback used in preload instruction"));
9181 constraint (!inst
.operands
[0].preind
,
9182 _("unindexed addressing used in preload instruction"));
9183 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9184 inst
.instruction
&= ~PRE_INDEX
;
9190 constraint (inst
.operands
[0].writeback
,
9191 _("push/pop do not support {reglist}^"));
9192 inst
.operands
[1] = inst
.operands
[0];
9193 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9194 inst
.operands
[0].isreg
= 1;
9195 inst
.operands
[0].writeback
= 1;
9196 inst
.operands
[0].reg
= REG_SP
;
9197 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9200 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9201 word at the specified address and the following word
9203 Unconditionally executed.
9204 Error if Rn is R15. */
9209 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9210 if (inst
.operands
[0].writeback
)
9211 inst
.instruction
|= WRITE_BACK
;
9214 /* ARM V6 ssat (argument parse). */
9219 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9220 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9221 inst
.instruction
|= inst
.operands
[2].reg
;
9223 if (inst
.operands
[3].present
)
9224 encode_arm_shift (3);
9227 /* ARM V6 usat (argument parse). */
9232 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9233 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9234 inst
.instruction
|= inst
.operands
[2].reg
;
9236 if (inst
.operands
[3].present
)
9237 encode_arm_shift (3);
9240 /* ARM V6 ssat16 (argument parse). */
9245 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9246 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9247 inst
.instruction
|= inst
.operands
[2].reg
;
9253 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9254 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9255 inst
.instruction
|= inst
.operands
[2].reg
;
9258 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9259 preserving the other bits.
9261 setend <endian_specifier>, where <endian_specifier> is either
9267 if (warn_on_deprecated
9268 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9269 as_tsktsk (_("setend use is deprecated for ARMv8"));
9271 if (inst
.operands
[0].imm
)
9272 inst
.instruction
|= 0x200;
9278 unsigned int Rm
= (inst
.operands
[1].present
9279 ? inst
.operands
[1].reg
9280 : inst
.operands
[0].reg
);
9282 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9283 inst
.instruction
|= Rm
;
9284 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9286 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9287 inst
.instruction
|= SHIFT_BY_REG
;
9288 /* PR 12854: Error on extraneous shifts. */
9289 constraint (inst
.operands
[2].shifted
,
9290 _("extraneous shift as part of operand to shift insn"));
9293 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9299 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9300 inst
.reloc
.pc_rel
= 0;
9306 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9307 inst
.reloc
.pc_rel
= 0;
9313 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9314 inst
.reloc
.pc_rel
= 0;
9320 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9321 _("selected processor does not support SETPAN instruction"));
9323 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9329 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9330 _("selected processor does not support SETPAN instruction"));
9332 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9335 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9336 SMLAxy{cond} Rd,Rm,Rs,Rn
9337 SMLAWy{cond} Rd,Rm,Rs,Rn
9338 Error if any register is R15. */
9343 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9344 inst
.instruction
|= inst
.operands
[1].reg
;
9345 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9346 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9349 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9350 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9351 Error if any register is R15.
9352 Warning if Rdlo == Rdhi. */
9357 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9358 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9359 inst
.instruction
|= inst
.operands
[2].reg
;
9360 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9362 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9363 as_tsktsk (_("rdhi and rdlo must be different"));
9366 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9367 SMULxy{cond} Rd,Rm,Rs
9368 Error if any register is R15. */
9373 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9374 inst
.instruction
|= inst
.operands
[1].reg
;
9375 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9378 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9379 the same for both ARM and Thumb-2. */
9386 if (inst
.operands
[0].present
)
9388 reg
= inst
.operands
[0].reg
;
9389 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9394 inst
.instruction
|= reg
<< 16;
9395 inst
.instruction
|= inst
.operands
[1].imm
;
9396 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9397 inst
.instruction
|= WRITE_BACK
;
9400 /* ARM V6 strex (argument parse). */
9405 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9406 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9407 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9408 || inst
.operands
[2].negative
9409 /* See comment in do_ldrex(). */
9410 || (inst
.operands
[2].reg
== REG_PC
),
9413 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9414 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9416 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9417 || inst
.reloc
.exp
.X_add_number
!= 0,
9418 _("offset must be zero in ARM encoding"));
9420 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9421 inst
.instruction
|= inst
.operands
[1].reg
;
9422 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9423 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9429 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9430 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9431 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9432 || inst
.operands
[2].negative
,
9435 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9436 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9444 constraint (inst
.operands
[1].reg
% 2 != 0,
9445 _("even register required"));
9446 constraint (inst
.operands
[2].present
9447 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9448 _("can only store two consecutive registers"));
9449 /* If op 2 were present and equal to PC, this function wouldn't
9450 have been called in the first place. */
9451 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9453 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9454 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9455 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9458 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9459 inst
.instruction
|= inst
.operands
[1].reg
;
9460 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9467 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9468 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9476 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9477 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9482 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9483 extends it to 32-bits, and adds the result to a value in another
9484 register. You can specify a rotation by 0, 8, 16, or 24 bits
9485 before extracting the 16-bit value.
9486 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9487 Condition defaults to COND_ALWAYS.
9488 Error if any register uses R15. */
9493 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9494 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9495 inst
.instruction
|= inst
.operands
[2].reg
;
9496 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9501 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9502 Condition defaults to COND_ALWAYS.
9503 Error if any register uses R15. */
9508 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9509 inst
.instruction
|= inst
.operands
[1].reg
;
9510 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9513 /* VFP instructions. In a logical order: SP variant first, monad
9514 before dyad, arithmetic then move then load/store. */
9517 do_vfp_sp_monadic (void)
9519 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9520 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9524 do_vfp_sp_dyadic (void)
9526 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9527 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9528 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9532 do_vfp_sp_compare_z (void)
9534 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9538 do_vfp_dp_sp_cvt (void)
9540 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9541 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9545 do_vfp_sp_dp_cvt (void)
9547 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9548 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9552 do_vfp_reg_from_sp (void)
9554 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9555 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9559 do_vfp_reg2_from_sp2 (void)
9561 constraint (inst
.operands
[2].imm
!= 2,
9562 _("only two consecutive VFP SP registers allowed here"));
9563 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9564 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9565 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9569 do_vfp_sp_from_reg (void)
9571 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9572 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9576 do_vfp_sp2_from_reg2 (void)
9578 constraint (inst
.operands
[0].imm
!= 2,
9579 _("only two consecutive VFP SP registers allowed here"));
9580 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9581 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9582 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9586 do_vfp_sp_ldst (void)
9588 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9589 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9593 do_vfp_dp_ldst (void)
9595 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9596 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9601 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9603 if (inst
.operands
[0].writeback
)
9604 inst
.instruction
|= WRITE_BACK
;
9606 constraint (ldstm_type
!= VFP_LDSTMIA
,
9607 _("this addressing mode requires base-register writeback"));
9608 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9609 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9610 inst
.instruction
|= inst
.operands
[1].imm
;
9614 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9618 if (inst
.operands
[0].writeback
)
9619 inst
.instruction
|= WRITE_BACK
;
9621 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9622 _("this addressing mode requires base-register writeback"));
9624 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9625 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9627 count
= inst
.operands
[1].imm
<< 1;
9628 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9631 inst
.instruction
|= count
;
9635 do_vfp_sp_ldstmia (void)
9637 vfp_sp_ldstm (VFP_LDSTMIA
);
9641 do_vfp_sp_ldstmdb (void)
9643 vfp_sp_ldstm (VFP_LDSTMDB
);
9647 do_vfp_dp_ldstmia (void)
9649 vfp_dp_ldstm (VFP_LDSTMIA
);
9653 do_vfp_dp_ldstmdb (void)
9655 vfp_dp_ldstm (VFP_LDSTMDB
);
9659 do_vfp_xp_ldstmia (void)
9661 vfp_dp_ldstm (VFP_LDSTMIAX
);
9665 do_vfp_xp_ldstmdb (void)
9667 vfp_dp_ldstm (VFP_LDSTMDBX
);
9671 do_vfp_dp_rd_rm (void)
9673 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9674 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9678 do_vfp_dp_rn_rd (void)
9680 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9681 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9685 do_vfp_dp_rd_rn (void)
9687 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9688 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9692 do_vfp_dp_rd_rn_rm (void)
9694 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9695 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9696 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9702 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9706 do_vfp_dp_rm_rd_rn (void)
9708 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9709 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9710 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9713 /* VFPv3 instructions. */
9715 do_vfp_sp_const (void)
9717 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9718 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9719 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9723 do_vfp_dp_const (void)
9725 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9726 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9727 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9731 vfp_conv (int srcsize
)
9733 int immbits
= srcsize
- inst
.operands
[1].imm
;
9735 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9737 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9738 i.e. immbits must be in range 0 - 16. */
9739 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9742 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9744 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9745 i.e. immbits must be in range 0 - 31. */
9746 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9750 inst
.instruction
|= (immbits
& 1) << 5;
9751 inst
.instruction
|= (immbits
>> 1);
9755 do_vfp_sp_conv_16 (void)
9757 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9762 do_vfp_dp_conv_16 (void)
9764 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9769 do_vfp_sp_conv_32 (void)
9771 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9776 do_vfp_dp_conv_32 (void)
9778 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9782 /* FPA instructions. Also in a logical order. */
9787 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9788 inst
.instruction
|= inst
.operands
[1].reg
;
9792 do_fpa_ldmstm (void)
9794 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9795 switch (inst
.operands
[1].imm
)
9797 case 1: inst
.instruction
|= CP_T_X
; break;
9798 case 2: inst
.instruction
|= CP_T_Y
; break;
9799 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9804 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9806 /* The instruction specified "ea" or "fd", so we can only accept
9807 [Rn]{!}. The instruction does not really support stacking or
9808 unstacking, so we have to emulate these by setting appropriate
9809 bits and offsets. */
9810 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9811 || inst
.reloc
.exp
.X_add_number
!= 0,
9812 _("this instruction does not support indexing"));
9814 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9815 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9817 if (!(inst
.instruction
& INDEX_UP
))
9818 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9820 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9822 inst
.operands
[2].preind
= 0;
9823 inst
.operands
[2].postind
= 1;
9827 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9830 /* iWMMXt instructions: strictly in alphabetical order. */
9833 do_iwmmxt_tandorc (void)
9835 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9839 do_iwmmxt_textrc (void)
9841 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9842 inst
.instruction
|= inst
.operands
[1].imm
;
9846 do_iwmmxt_textrm (void)
9848 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9849 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9850 inst
.instruction
|= inst
.operands
[2].imm
;
9854 do_iwmmxt_tinsr (void)
9856 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9857 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9858 inst
.instruction
|= inst
.operands
[2].imm
;
9862 do_iwmmxt_tmia (void)
9864 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9865 inst
.instruction
|= inst
.operands
[1].reg
;
9866 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9870 do_iwmmxt_waligni (void)
9872 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9873 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9874 inst
.instruction
|= inst
.operands
[2].reg
;
9875 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
9879 do_iwmmxt_wmerge (void)
9881 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9882 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9883 inst
.instruction
|= inst
.operands
[2].reg
;
9884 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
9888 do_iwmmxt_wmov (void)
9890 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9891 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9892 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9893 inst
.instruction
|= inst
.operands
[1].reg
;
9897 do_iwmmxt_wldstbh (void)
9900 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9902 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
9904 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
9905 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
9909 do_iwmmxt_wldstw (void)
9911 /* RIWR_RIWC clears .isreg for a control register. */
9912 if (!inst
.operands
[0].isreg
)
9914 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9915 inst
.instruction
|= 0xf0000000;
9918 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9919 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9923 do_iwmmxt_wldstd (void)
9925 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9926 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
9927 && inst
.operands
[1].immisreg
)
9929 inst
.instruction
&= ~0x1a000ff;
9930 inst
.instruction
|= (0xfU
<< 28);
9931 if (inst
.operands
[1].preind
)
9932 inst
.instruction
|= PRE_INDEX
;
9933 if (!inst
.operands
[1].negative
)
9934 inst
.instruction
|= INDEX_UP
;
9935 if (inst
.operands
[1].writeback
)
9936 inst
.instruction
|= WRITE_BACK
;
9937 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9938 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9939 inst
.instruction
|= inst
.operands
[1].imm
;
9942 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
9946 do_iwmmxt_wshufh (void)
9948 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9949 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9950 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
9951 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
9955 do_iwmmxt_wzero (void)
9957 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9958 inst
.instruction
|= inst
.operands
[0].reg
;
9959 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9960 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9964 do_iwmmxt_wrwrwr_or_imm5 (void)
9966 if (inst
.operands
[2].isreg
)
9969 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
9970 _("immediate operand requires iWMMXt2"));
9972 if (inst
.operands
[2].imm
== 0)
9974 switch ((inst
.instruction
>> 20) & 0xf)
9980 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9981 inst
.operands
[2].imm
= 16;
9982 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
9988 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9989 inst
.operands
[2].imm
= 32;
9990 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
9997 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9999 wrn
= (inst
.instruction
>> 16) & 0xf;
10000 inst
.instruction
&= 0xff0fff0f;
10001 inst
.instruction
|= wrn
;
10002 /* Bail out here; the instruction is now assembled. */
10007 /* Map 32 -> 0, etc. */
10008 inst
.operands
[2].imm
&= 0x1f;
10009 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10013 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10014 operations first, then control, shift, and load/store. */
10016 /* Insns like "foo X,Y,Z". */
10019 do_mav_triple (void)
10021 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10022 inst
.instruction
|= inst
.operands
[1].reg
;
10023 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10026 /* Insns like "foo W,X,Y,Z".
10027 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10032 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10033 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10034 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10035 inst
.instruction
|= inst
.operands
[3].reg
;
10038 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10040 do_mav_dspsc (void)
10042 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10045 /* Maverick shift immediate instructions.
10046 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10047 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10050 do_mav_shift (void)
10052 int imm
= inst
.operands
[2].imm
;
10054 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10055 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10057 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10058 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10059 Bit 4 should be 0. */
10060 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10062 inst
.instruction
|= imm
;
10065 /* XScale instructions. Also sorted arithmetic before move. */
10067 /* Xscale multiply-accumulate (argument parse)
10070 MIAxycc acc0,Rm,Rs. */
10075 inst
.instruction
|= inst
.operands
[1].reg
;
10076 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10079 /* Xscale move-accumulator-register (argument parse)
10081 MARcc acc0,RdLo,RdHi. */
10086 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10087 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10090 /* Xscale move-register-accumulator (argument parse)
10092 MRAcc RdLo,RdHi,acc0. */
10097 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10098 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10099 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10102 /* Encoding functions relevant only to Thumb. */
10104 /* inst.operands[i] is a shifted-register operand; encode
10105 it into inst.instruction in the format used by Thumb32. */
10108 encode_thumb32_shifted_operand (int i
)
10110 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10111 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10113 constraint (inst
.operands
[i
].immisreg
,
10114 _("shift by register not allowed in thumb mode"));
10115 inst
.instruction
|= inst
.operands
[i
].reg
;
10116 if (shift
== SHIFT_RRX
)
10117 inst
.instruction
|= SHIFT_ROR
<< 4;
10120 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10121 _("expression too complex"));
10123 constraint (value
> 32
10124 || (value
== 32 && (shift
== SHIFT_LSL
10125 || shift
== SHIFT_ROR
)),
10126 _("shift expression is too large"));
10130 else if (value
== 32)
10133 inst
.instruction
|= shift
<< 4;
10134 inst
.instruction
|= (value
& 0x1c) << 10;
10135 inst
.instruction
|= (value
& 0x03) << 6;
10140 /* inst.operands[i] was set up by parse_address. Encode it into a
10141 Thumb32 format load or store instruction. Reject forms that cannot
10142 be used with such instructions. If is_t is true, reject forms that
10143 cannot be used with a T instruction; if is_d is true, reject forms
10144 that cannot be used with a D instruction. If it is a store insn,
10145 reject PC in Rn. */
10148 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10150 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10152 constraint (!inst
.operands
[i
].isreg
,
10153 _("Instruction does not support =N addresses"));
10155 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10156 if (inst
.operands
[i
].immisreg
)
10158 constraint (is_pc
, BAD_PC_ADDRESSING
);
10159 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10160 constraint (inst
.operands
[i
].negative
,
10161 _("Thumb does not support negative register indexing"));
10162 constraint (inst
.operands
[i
].postind
,
10163 _("Thumb does not support register post-indexing"));
10164 constraint (inst
.operands
[i
].writeback
,
10165 _("Thumb does not support register indexing with writeback"));
10166 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10167 _("Thumb supports only LSL in shifted register indexing"));
10169 inst
.instruction
|= inst
.operands
[i
].imm
;
10170 if (inst
.operands
[i
].shifted
)
10172 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10173 _("expression too complex"));
10174 constraint (inst
.reloc
.exp
.X_add_number
< 0
10175 || inst
.reloc
.exp
.X_add_number
> 3,
10176 _("shift out of range"));
10177 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10179 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10181 else if (inst
.operands
[i
].preind
)
10183 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10184 constraint (is_t
&& inst
.operands
[i
].writeback
,
10185 _("cannot use writeback with this instruction"));
10186 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10187 BAD_PC_ADDRESSING
);
10191 inst
.instruction
|= 0x01000000;
10192 if (inst
.operands
[i
].writeback
)
10193 inst
.instruction
|= 0x00200000;
10197 inst
.instruction
|= 0x00000c00;
10198 if (inst
.operands
[i
].writeback
)
10199 inst
.instruction
|= 0x00000100;
10201 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10203 else if (inst
.operands
[i
].postind
)
10205 gas_assert (inst
.operands
[i
].writeback
);
10206 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10207 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10210 inst
.instruction
|= 0x00200000;
10212 inst
.instruction
|= 0x00000900;
10213 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10215 else /* unindexed - only for coprocessor */
10216 inst
.error
= _("instruction does not accept unindexed addressing");
10219 /* Table of Thumb instructions which exist in both 16- and 32-bit
10220 encodings (the latter only in post-V6T2 cores). The index is the
10221 value used in the insns table below. When there is more than one
10222 possible 16-bit encoding for the instruction, this table always
10224 Also contains several pseudo-instructions used during relaxation. */
10225 #define T16_32_TAB \
10226 X(_adc, 4140, eb400000), \
10227 X(_adcs, 4140, eb500000), \
10228 X(_add, 1c00, eb000000), \
10229 X(_adds, 1c00, eb100000), \
10230 X(_addi, 0000, f1000000), \
10231 X(_addis, 0000, f1100000), \
10232 X(_add_pc,000f, f20f0000), \
10233 X(_add_sp,000d, f10d0000), \
10234 X(_adr, 000f, f20f0000), \
10235 X(_and, 4000, ea000000), \
10236 X(_ands, 4000, ea100000), \
10237 X(_asr, 1000, fa40f000), \
10238 X(_asrs, 1000, fa50f000), \
10239 X(_b, e000, f000b000), \
10240 X(_bcond, d000, f0008000), \
10241 X(_bic, 4380, ea200000), \
10242 X(_bics, 4380, ea300000), \
10243 X(_cmn, 42c0, eb100f00), \
10244 X(_cmp, 2800, ebb00f00), \
10245 X(_cpsie, b660, f3af8400), \
10246 X(_cpsid, b670, f3af8600), \
10247 X(_cpy, 4600, ea4f0000), \
10248 X(_dec_sp,80dd, f1ad0d00), \
10249 X(_eor, 4040, ea800000), \
10250 X(_eors, 4040, ea900000), \
10251 X(_inc_sp,00dd, f10d0d00), \
10252 X(_ldmia, c800, e8900000), \
10253 X(_ldr, 6800, f8500000), \
10254 X(_ldrb, 7800, f8100000), \
10255 X(_ldrh, 8800, f8300000), \
10256 X(_ldrsb, 5600, f9100000), \
10257 X(_ldrsh, 5e00, f9300000), \
10258 X(_ldr_pc,4800, f85f0000), \
10259 X(_ldr_pc2,4800, f85f0000), \
10260 X(_ldr_sp,9800, f85d0000), \
10261 X(_lsl, 0000, fa00f000), \
10262 X(_lsls, 0000, fa10f000), \
10263 X(_lsr, 0800, fa20f000), \
10264 X(_lsrs, 0800, fa30f000), \
10265 X(_mov, 2000, ea4f0000), \
10266 X(_movs, 2000, ea5f0000), \
10267 X(_mul, 4340, fb00f000), \
10268 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10269 X(_mvn, 43c0, ea6f0000), \
10270 X(_mvns, 43c0, ea7f0000), \
10271 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10272 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10273 X(_orr, 4300, ea400000), \
10274 X(_orrs, 4300, ea500000), \
10275 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10276 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10277 X(_rev, ba00, fa90f080), \
10278 X(_rev16, ba40, fa90f090), \
10279 X(_revsh, bac0, fa90f0b0), \
10280 X(_ror, 41c0, fa60f000), \
10281 X(_rors, 41c0, fa70f000), \
10282 X(_sbc, 4180, eb600000), \
10283 X(_sbcs, 4180, eb700000), \
10284 X(_stmia, c000, e8800000), \
10285 X(_str, 6000, f8400000), \
10286 X(_strb, 7000, f8000000), \
10287 X(_strh, 8000, f8200000), \
10288 X(_str_sp,9000, f84d0000), \
10289 X(_sub, 1e00, eba00000), \
10290 X(_subs, 1e00, ebb00000), \
10291 X(_subi, 8000, f1a00000), \
10292 X(_subis, 8000, f1b00000), \
10293 X(_sxtb, b240, fa4ff080), \
10294 X(_sxth, b200, fa0ff080), \
10295 X(_tst, 4200, ea100f00), \
10296 X(_uxtb, b2c0, fa5ff080), \
10297 X(_uxth, b280, fa1ff080), \
10298 X(_nop, bf00, f3af8000), \
10299 X(_yield, bf10, f3af8001), \
10300 X(_wfe, bf20, f3af8002), \
10301 X(_wfi, bf30, f3af8003), \
10302 X(_sev, bf40, f3af8004), \
10303 X(_sevl, bf50, f3af8005), \
10304 X(_udf, de00, f7f0a000)
10306 /* To catch errors in encoding functions, the codes are all offset by
10307 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10308 as 16-bit instructions. */
10309 #define X(a,b,c) T_MNEM##a
10310 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10313 #define X(a,b,c) 0x##b
10314 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10315 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10318 #define X(a,b,c) 0x##c
10319 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10320 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10321 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10325 /* Thumb instruction encoders, in alphabetical order. */
10327 /* ADDW or SUBW. */
10330 do_t_add_sub_w (void)
10334 Rd
= inst
.operands
[0].reg
;
10335 Rn
= inst
.operands
[1].reg
;
10337 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10338 is the SP-{plus,minus}-immediate form of the instruction. */
10340 constraint (Rd
== REG_PC
, BAD_PC
);
10342 reject_bad_reg (Rd
);
10344 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10345 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10348 /* Parse an add or subtract instruction. We get here with inst.instruction
10349 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
10352 do_t_add_sub (void)
10356 Rd
= inst
.operands
[0].reg
;
10357 Rs
= (inst
.operands
[1].present
10358 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10359 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10362 set_it_insn_type_last ();
10364 if (unified_syntax
)
10367 bfd_boolean narrow
;
10370 flags
= (inst
.instruction
== T_MNEM_adds
10371 || inst
.instruction
== T_MNEM_subs
);
10373 narrow
= !in_it_block ();
10375 narrow
= in_it_block ();
10376 if (!inst
.operands
[2].isreg
)
10380 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10382 add
= (inst
.instruction
== T_MNEM_add
10383 || inst
.instruction
== T_MNEM_adds
);
10385 if (inst
.size_req
!= 4)
10387 /* Attempt to use a narrow opcode, with relaxation if
10389 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10390 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10391 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10392 opcode
= T_MNEM_add_sp
;
10393 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10394 opcode
= T_MNEM_add_pc
;
10395 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10398 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10400 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10404 inst
.instruction
= THUMB_OP16(opcode
);
10405 inst
.instruction
|= (Rd
<< 4) | Rs
;
10406 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10407 if (inst
.size_req
!= 2)
10408 inst
.relax
= opcode
;
10411 constraint (inst
.size_req
== 2, BAD_HIREG
);
10413 if (inst
.size_req
== 4
10414 || (inst
.size_req
!= 2 && !opcode
))
10418 constraint (add
, BAD_PC
);
10419 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10420 _("only SUBS PC, LR, #const allowed"));
10421 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10422 _("expression too complex"));
10423 constraint (inst
.reloc
.exp
.X_add_number
< 0
10424 || inst
.reloc
.exp
.X_add_number
> 0xff,
10425 _("immediate value out of range"));
10426 inst
.instruction
= T2_SUBS_PC_LR
10427 | inst
.reloc
.exp
.X_add_number
;
10428 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10431 else if (Rs
== REG_PC
)
10433 /* Always use addw/subw. */
10434 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10435 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10439 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10440 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10443 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10445 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10447 inst
.instruction
|= Rd
<< 8;
10448 inst
.instruction
|= Rs
<< 16;
10453 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10454 unsigned int shift
= inst
.operands
[2].shift_kind
;
10456 Rn
= inst
.operands
[2].reg
;
10457 /* See if we can do this with a 16-bit instruction. */
10458 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10460 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10465 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10466 || inst
.instruction
== T_MNEM_add
)
10468 : T_OPCODE_SUB_R3
);
10469 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10473 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10475 /* Thumb-1 cores (except v6-M) require at least one high
10476 register in a narrow non flag setting add. */
10477 if (Rd
> 7 || Rn
> 7
10478 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10479 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10486 inst
.instruction
= T_OPCODE_ADD_HI
;
10487 inst
.instruction
|= (Rd
& 8) << 4;
10488 inst
.instruction
|= (Rd
& 7);
10489 inst
.instruction
|= Rn
<< 3;
10495 constraint (Rd
== REG_PC
, BAD_PC
);
10496 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10497 constraint (Rs
== REG_PC
, BAD_PC
);
10498 reject_bad_reg (Rn
);
10500 /* If we get here, it can't be done in 16 bits. */
10501 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10502 _("shift must be constant"));
10503 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10504 inst
.instruction
|= Rd
<< 8;
10505 inst
.instruction
|= Rs
<< 16;
10506 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10507 _("shift value over 3 not allowed in thumb mode"));
10508 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10509 _("only LSL shift allowed in thumb mode"));
10510 encode_thumb32_shifted_operand (2);
10515 constraint (inst
.instruction
== T_MNEM_adds
10516 || inst
.instruction
== T_MNEM_subs
,
10519 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10521 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10522 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10525 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10526 ? 0x0000 : 0x8000);
10527 inst
.instruction
|= (Rd
<< 4) | Rs
;
10528 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10532 Rn
= inst
.operands
[2].reg
;
10533 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10535 /* We now have Rd, Rs, and Rn set to registers. */
10536 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10538 /* Can't do this for SUB. */
10539 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10540 inst
.instruction
= T_OPCODE_ADD_HI
;
10541 inst
.instruction
|= (Rd
& 8) << 4;
10542 inst
.instruction
|= (Rd
& 7);
10544 inst
.instruction
|= Rn
<< 3;
10546 inst
.instruction
|= Rs
<< 3;
10548 constraint (1, _("dest must overlap one source register"));
10552 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10553 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10554 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10564 Rd
= inst
.operands
[0].reg
;
10565 reject_bad_reg (Rd
);
10567 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10569 /* Defer to section relaxation. */
10570 inst
.relax
= inst
.instruction
;
10571 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10572 inst
.instruction
|= Rd
<< 4;
10574 else if (unified_syntax
&& inst
.size_req
!= 2)
10576 /* Generate a 32-bit opcode. */
10577 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10578 inst
.instruction
|= Rd
<< 8;
10579 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10580 inst
.reloc
.pc_rel
= 1;
10584 /* Generate a 16-bit opcode. */
10585 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10586 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10587 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10588 inst
.reloc
.pc_rel
= 1;
10590 inst
.instruction
|= Rd
<< 4;
10594 /* Arithmetic instructions for which there is just one 16-bit
10595 instruction encoding, and it allows only two low registers.
10596 For maximal compatibility with ARM syntax, we allow three register
10597 operands even when Thumb-32 instructions are not available, as long
10598 as the first two are identical. For instance, both "sbc r0,r1" and
10599 "sbc r0,r0,r1" are allowed. */
10605 Rd
= inst
.operands
[0].reg
;
10606 Rs
= (inst
.operands
[1].present
10607 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10608 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10609 Rn
= inst
.operands
[2].reg
;
10611 reject_bad_reg (Rd
);
10612 reject_bad_reg (Rs
);
10613 if (inst
.operands
[2].isreg
)
10614 reject_bad_reg (Rn
);
10616 if (unified_syntax
)
10618 if (!inst
.operands
[2].isreg
)
10620 /* For an immediate, we always generate a 32-bit opcode;
10621 section relaxation will shrink it later if possible. */
10622 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10623 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10624 inst
.instruction
|= Rd
<< 8;
10625 inst
.instruction
|= Rs
<< 16;
10626 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10630 bfd_boolean narrow
;
10632 /* See if we can do this with a 16-bit instruction. */
10633 if (THUMB_SETS_FLAGS (inst
.instruction
))
10634 narrow
= !in_it_block ();
10636 narrow
= in_it_block ();
10638 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10640 if (inst
.operands
[2].shifted
)
10642 if (inst
.size_req
== 4)
10648 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10649 inst
.instruction
|= Rd
;
10650 inst
.instruction
|= Rn
<< 3;
10654 /* If we get here, it can't be done in 16 bits. */
10655 constraint (inst
.operands
[2].shifted
10656 && inst
.operands
[2].immisreg
,
10657 _("shift must be constant"));
10658 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10659 inst
.instruction
|= Rd
<< 8;
10660 inst
.instruction
|= Rs
<< 16;
10661 encode_thumb32_shifted_operand (2);
10666 /* On its face this is a lie - the instruction does set the
10667 flags. However, the only supported mnemonic in this mode
10668 says it doesn't. */
10669 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10671 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10672 _("unshifted register required"));
10673 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10674 constraint (Rd
!= Rs
,
10675 _("dest and source1 must be the same register"));
10677 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10678 inst
.instruction
|= Rd
;
10679 inst
.instruction
|= Rn
<< 3;
10683 /* Similarly, but for instructions where the arithmetic operation is
10684 commutative, so we can allow either of them to be different from
10685 the destination operand in a 16-bit instruction. For instance, all
10686 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10693 Rd
= inst
.operands
[0].reg
;
10694 Rs
= (inst
.operands
[1].present
10695 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10696 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10697 Rn
= inst
.operands
[2].reg
;
10699 reject_bad_reg (Rd
);
10700 reject_bad_reg (Rs
);
10701 if (inst
.operands
[2].isreg
)
10702 reject_bad_reg (Rn
);
10704 if (unified_syntax
)
10706 if (!inst
.operands
[2].isreg
)
10708 /* For an immediate, we always generate a 32-bit opcode;
10709 section relaxation will shrink it later if possible. */
10710 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10711 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10712 inst
.instruction
|= Rd
<< 8;
10713 inst
.instruction
|= Rs
<< 16;
10714 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10718 bfd_boolean narrow
;
10720 /* See if we can do this with a 16-bit instruction. */
10721 if (THUMB_SETS_FLAGS (inst
.instruction
))
10722 narrow
= !in_it_block ();
10724 narrow
= in_it_block ();
10726 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10728 if (inst
.operands
[2].shifted
)
10730 if (inst
.size_req
== 4)
10737 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10738 inst
.instruction
|= Rd
;
10739 inst
.instruction
|= Rn
<< 3;
10744 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10745 inst
.instruction
|= Rd
;
10746 inst
.instruction
|= Rs
<< 3;
10751 /* If we get here, it can't be done in 16 bits. */
10752 constraint (inst
.operands
[2].shifted
10753 && inst
.operands
[2].immisreg
,
10754 _("shift must be constant"));
10755 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10756 inst
.instruction
|= Rd
<< 8;
10757 inst
.instruction
|= Rs
<< 16;
10758 encode_thumb32_shifted_operand (2);
10763 /* On its face this is a lie - the instruction does set the
10764 flags. However, the only supported mnemonic in this mode
10765 says it doesn't. */
10766 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10768 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10769 _("unshifted register required"));
10770 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10772 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10773 inst
.instruction
|= Rd
;
10776 inst
.instruction
|= Rn
<< 3;
10778 inst
.instruction
|= Rs
<< 3;
10780 constraint (1, _("dest must overlap one source register"));
10788 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10789 constraint (msb
> 32, _("bit-field extends past end of register"));
10790 /* The instruction encoding stores the LSB and MSB,
10791 not the LSB and width. */
10792 Rd
= inst
.operands
[0].reg
;
10793 reject_bad_reg (Rd
);
10794 inst
.instruction
|= Rd
<< 8;
10795 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10796 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10797 inst
.instruction
|= msb
- 1;
10806 Rd
= inst
.operands
[0].reg
;
10807 reject_bad_reg (Rd
);
10809 /* #0 in second position is alternative syntax for bfc, which is
10810 the same instruction but with REG_PC in the Rm field. */
10811 if (!inst
.operands
[1].isreg
)
10815 Rn
= inst
.operands
[1].reg
;
10816 reject_bad_reg (Rn
);
10819 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10820 constraint (msb
> 32, _("bit-field extends past end of register"));
10821 /* The instruction encoding stores the LSB and MSB,
10822 not the LSB and width. */
10823 inst
.instruction
|= Rd
<< 8;
10824 inst
.instruction
|= Rn
<< 16;
10825 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10826 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10827 inst
.instruction
|= msb
- 1;
10835 Rd
= inst
.operands
[0].reg
;
10836 Rn
= inst
.operands
[1].reg
;
10838 reject_bad_reg (Rd
);
10839 reject_bad_reg (Rn
);
10841 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10842 _("bit-field extends past end of register"));
10843 inst
.instruction
|= Rd
<< 8;
10844 inst
.instruction
|= Rn
<< 16;
10845 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10846 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10847 inst
.instruction
|= inst
.operands
[3].imm
- 1;
10850 /* ARM V5 Thumb BLX (argument parse)
10851 BLX <target_addr> which is BLX(1)
10852 BLX <Rm> which is BLX(2)
10853 Unfortunately, there are two different opcodes for this mnemonic.
10854 So, the insns[].value is not used, and the code here zaps values
10855 into inst.instruction.
10857 ??? How to take advantage of the additional two bits of displacement
10858 available in Thumb32 mode? Need new relocation? */
10863 set_it_insn_type_last ();
10865 if (inst
.operands
[0].isreg
)
10867 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10868 /* We have a register, so this is BLX(2). */
10869 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10873 /* No register. This must be BLX(1). */
10874 inst
.instruction
= 0xf000e800;
10875 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
10887 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
10889 if (in_it_block ())
10891 /* Conditional branches inside IT blocks are encoded as unconditional
10893 cond
= COND_ALWAYS
;
10898 if (cond
!= COND_ALWAYS
)
10899 opcode
= T_MNEM_bcond
;
10901 opcode
= inst
.instruction
;
10904 && (inst
.size_req
== 4
10905 || (inst
.size_req
!= 2
10906 && (inst
.operands
[0].hasreloc
10907 || inst
.reloc
.exp
.X_op
== O_constant
))))
10909 inst
.instruction
= THUMB_OP32(opcode
);
10910 if (cond
== COND_ALWAYS
)
10911 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
10914 gas_assert (cond
!= 0xF);
10915 inst
.instruction
|= cond
<< 22;
10916 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
10921 inst
.instruction
= THUMB_OP16(opcode
);
10922 if (cond
== COND_ALWAYS
)
10923 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
10926 inst
.instruction
|= cond
<< 8;
10927 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
10929 /* Allow section relaxation. */
10930 if (unified_syntax
&& inst
.size_req
!= 2)
10931 inst
.relax
= opcode
;
10933 inst
.reloc
.type
= reloc
;
10934 inst
.reloc
.pc_rel
= 1;
10937 /* Actually do the work for Thumb state bkpt and hlt. The only difference
10938 between the two is the maximum immediate allowed - which is passed in
10941 do_t_bkpt_hlt1 (int range
)
10943 constraint (inst
.cond
!= COND_ALWAYS
,
10944 _("instruction is always unconditional"));
10945 if (inst
.operands
[0].present
)
10947 constraint (inst
.operands
[0].imm
> range
,
10948 _("immediate value out of range"));
10949 inst
.instruction
|= inst
.operands
[0].imm
;
10952 set_it_insn_type (NEUTRAL_IT_INSN
);
10958 do_t_bkpt_hlt1 (63);
10964 do_t_bkpt_hlt1 (255);
10968 do_t_branch23 (void)
10970 set_it_insn_type_last ();
10971 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
10973 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10974 this file. We used to simply ignore the PLT reloc type here --
10975 the branch encoding is now needed to deal with TLSCALL relocs.
10976 So if we see a PLT reloc now, put it back to how it used to be to
10977 keep the preexisting behaviour. */
10978 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
10979 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
10981 #if defined(OBJ_COFF)
10982 /* If the destination of the branch is a defined symbol which does not have
10983 the THUMB_FUNC attribute, then we must be calling a function which has
10984 the (interfacearm) attribute. We look for the Thumb entry point to that
10985 function and change the branch to refer to that function instead. */
10986 if ( inst
.reloc
.exp
.X_op
== O_symbol
10987 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10988 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10989 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10990 inst
.reloc
.exp
.X_add_symbol
=
10991 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
10998 set_it_insn_type_last ();
10999 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11000 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11001 should cause the alignment to be checked once it is known. This is
11002 because BX PC only works if the instruction is word aligned. */
11010 set_it_insn_type_last ();
11011 Rm
= inst
.operands
[0].reg
;
11012 reject_bad_reg (Rm
);
11013 inst
.instruction
|= Rm
<< 16;
11022 Rd
= inst
.operands
[0].reg
;
11023 Rm
= inst
.operands
[1].reg
;
11025 reject_bad_reg (Rd
);
11026 reject_bad_reg (Rm
);
11028 inst
.instruction
|= Rd
<< 8;
11029 inst
.instruction
|= Rm
<< 16;
11030 inst
.instruction
|= Rm
;
11036 set_it_insn_type (OUTSIDE_IT_INSN
);
11037 inst
.instruction
|= inst
.operands
[0].imm
;
11043 set_it_insn_type (OUTSIDE_IT_INSN
);
11045 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11046 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11048 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11049 inst
.instruction
= 0xf3af8000;
11050 inst
.instruction
|= imod
<< 9;
11051 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11052 if (inst
.operands
[1].present
)
11053 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11057 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11058 && (inst
.operands
[0].imm
& 4),
11059 _("selected processor does not support 'A' form "
11060 "of this instruction"));
11061 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11062 _("Thumb does not support the 2-argument "
11063 "form of this instruction"));
11064 inst
.instruction
|= inst
.operands
[0].imm
;
11068 /* THUMB CPY instruction (argument parse). */
11073 if (inst
.size_req
== 4)
11075 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11076 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11077 inst
.instruction
|= inst
.operands
[1].reg
;
11081 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11082 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11083 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11090 set_it_insn_type (OUTSIDE_IT_INSN
);
11091 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11092 inst
.instruction
|= inst
.operands
[0].reg
;
11093 inst
.reloc
.pc_rel
= 1;
11094 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11100 inst
.instruction
|= inst
.operands
[0].imm
;
11106 unsigned Rd
, Rn
, Rm
;
11108 Rd
= inst
.operands
[0].reg
;
11109 Rn
= (inst
.operands
[1].present
11110 ? inst
.operands
[1].reg
: Rd
);
11111 Rm
= inst
.operands
[2].reg
;
11113 reject_bad_reg (Rd
);
11114 reject_bad_reg (Rn
);
11115 reject_bad_reg (Rm
);
11117 inst
.instruction
|= Rd
<< 8;
11118 inst
.instruction
|= Rn
<< 16;
11119 inst
.instruction
|= Rm
;
11125 if (unified_syntax
&& inst
.size_req
== 4)
11126 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11128 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11134 unsigned int cond
= inst
.operands
[0].imm
;
11136 set_it_insn_type (IT_INSN
);
11137 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11139 now_it
.warn_deprecated
= FALSE
;
11141 /* If the condition is a negative condition, invert the mask. */
11142 if ((cond
& 0x1) == 0x0)
11144 unsigned int mask
= inst
.instruction
& 0x000f;
11146 if ((mask
& 0x7) == 0)
11148 /* No conversion needed. */
11149 now_it
.block_length
= 1;
11151 else if ((mask
& 0x3) == 0)
11154 now_it
.block_length
= 2;
11156 else if ((mask
& 0x1) == 0)
11159 now_it
.block_length
= 3;
11164 now_it
.block_length
= 4;
11167 inst
.instruction
&= 0xfff0;
11168 inst
.instruction
|= mask
;
11171 inst
.instruction
|= cond
<< 4;
11174 /* Helper function used for both push/pop and ldm/stm. */
11176 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11180 load
= (inst
.instruction
& (1 << 20)) != 0;
11182 if (mask
& (1 << 13))
11183 inst
.error
= _("SP not allowed in register list");
11185 if ((mask
& (1 << base
)) != 0
11187 inst
.error
= _("having the base register in the register list when "
11188 "using write back is UNPREDICTABLE");
11192 if (mask
& (1 << 15))
11194 if (mask
& (1 << 14))
11195 inst
.error
= _("LR and PC should not both be in register list");
11197 set_it_insn_type_last ();
11202 if (mask
& (1 << 15))
11203 inst
.error
= _("PC not allowed in register list");
11206 if ((mask
& (mask
- 1)) == 0)
11208 /* Single register transfers implemented as str/ldr. */
11211 if (inst
.instruction
& (1 << 23))
11212 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11214 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11218 if (inst
.instruction
& (1 << 23))
11219 inst
.instruction
= 0x00800000; /* ia -> [base] */
11221 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11224 inst
.instruction
|= 0xf8400000;
11226 inst
.instruction
|= 0x00100000;
11228 mask
= ffs (mask
) - 1;
11231 else if (writeback
)
11232 inst
.instruction
|= WRITE_BACK
;
11234 inst
.instruction
|= mask
;
11235 inst
.instruction
|= base
<< 16;
11241 /* This really doesn't seem worth it. */
11242 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11243 _("expression too complex"));
11244 constraint (inst
.operands
[1].writeback
,
11245 _("Thumb load/store multiple does not support {reglist}^"));
11247 if (unified_syntax
)
11249 bfd_boolean narrow
;
11253 /* See if we can use a 16-bit instruction. */
11254 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11255 && inst
.size_req
!= 4
11256 && !(inst
.operands
[1].imm
& ~0xff))
11258 mask
= 1 << inst
.operands
[0].reg
;
11260 if (inst
.operands
[0].reg
<= 7)
11262 if (inst
.instruction
== T_MNEM_stmia
11263 ? inst
.operands
[0].writeback
11264 : (inst
.operands
[0].writeback
11265 == !(inst
.operands
[1].imm
& mask
)))
11267 if (inst
.instruction
== T_MNEM_stmia
11268 && (inst
.operands
[1].imm
& mask
)
11269 && (inst
.operands
[1].imm
& (mask
- 1)))
11270 as_warn (_("value stored for r%d is UNKNOWN"),
11271 inst
.operands
[0].reg
);
11273 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11274 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11275 inst
.instruction
|= inst
.operands
[1].imm
;
11278 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11280 /* This means 1 register in reg list one of 3 situations:
11281 1. Instruction is stmia, but without writeback.
11282 2. lmdia without writeback, but with Rn not in
11284 3. ldmia with writeback, but with Rn in reglist.
11285 Case 3 is UNPREDICTABLE behaviour, so we handle
11286 case 1 and 2 which can be converted into a 16-bit
11287 str or ldr. The SP cases are handled below. */
11288 unsigned long opcode
;
11289 /* First, record an error for Case 3. */
11290 if (inst
.operands
[1].imm
& mask
11291 && inst
.operands
[0].writeback
)
11293 _("having the base register in the register list when "
11294 "using write back is UNPREDICTABLE");
11296 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11298 inst
.instruction
= THUMB_OP16 (opcode
);
11299 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11300 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11304 else if (inst
.operands
[0] .reg
== REG_SP
)
11306 if (inst
.operands
[0].writeback
)
11309 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11310 ? T_MNEM_push
: T_MNEM_pop
);
11311 inst
.instruction
|= inst
.operands
[1].imm
;
11314 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11317 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11318 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11319 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11327 if (inst
.instruction
< 0xffff)
11328 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11330 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11331 inst
.operands
[0].writeback
);
11336 constraint (inst
.operands
[0].reg
> 7
11337 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11338 constraint (inst
.instruction
!= T_MNEM_ldmia
11339 && inst
.instruction
!= T_MNEM_stmia
,
11340 _("Thumb-2 instruction only valid in unified syntax"));
11341 if (inst
.instruction
== T_MNEM_stmia
)
11343 if (!inst
.operands
[0].writeback
)
11344 as_warn (_("this instruction will write back the base register"));
11345 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11346 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11347 as_warn (_("value stored for r%d is UNKNOWN"),
11348 inst
.operands
[0].reg
);
11352 if (!inst
.operands
[0].writeback
11353 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11354 as_warn (_("this instruction will write back the base register"));
11355 else if (inst
.operands
[0].writeback
11356 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11357 as_warn (_("this instruction will not write back the base register"));
11360 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11361 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11362 inst
.instruction
|= inst
.operands
[1].imm
;
11369 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11370 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11371 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11372 || inst
.operands
[1].negative
,
11375 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11377 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11378 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11379 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11385 if (!inst
.operands
[1].present
)
11387 constraint (inst
.operands
[0].reg
== REG_LR
,
11388 _("r14 not allowed as first register "
11389 "when second register is omitted"));
11390 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11392 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11395 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11396 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11397 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11403 unsigned long opcode
;
11406 if (inst
.operands
[0].isreg
11407 && !inst
.operands
[0].preind
11408 && inst
.operands
[0].reg
== REG_PC
)
11409 set_it_insn_type_last ();
11411 opcode
= inst
.instruction
;
11412 if (unified_syntax
)
11414 if (!inst
.operands
[1].isreg
)
11416 if (opcode
<= 0xffff)
11417 inst
.instruction
= THUMB_OP32 (opcode
);
11418 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11421 if (inst
.operands
[1].isreg
11422 && !inst
.operands
[1].writeback
11423 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11424 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11425 && opcode
<= 0xffff
11426 && inst
.size_req
!= 4)
11428 /* Insn may have a 16-bit form. */
11429 Rn
= inst
.operands
[1].reg
;
11430 if (inst
.operands
[1].immisreg
)
11432 inst
.instruction
= THUMB_OP16 (opcode
);
11434 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11436 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11437 reject_bad_reg (inst
.operands
[1].imm
);
11439 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11440 && opcode
!= T_MNEM_ldrsb
)
11441 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11442 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11449 if (inst
.reloc
.pc_rel
)
11450 opcode
= T_MNEM_ldr_pc2
;
11452 opcode
= T_MNEM_ldr_pc
;
11456 if (opcode
== T_MNEM_ldr
)
11457 opcode
= T_MNEM_ldr_sp
;
11459 opcode
= T_MNEM_str_sp
;
11461 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11465 inst
.instruction
= inst
.operands
[0].reg
;
11466 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11468 inst
.instruction
|= THUMB_OP16 (opcode
);
11469 if (inst
.size_req
== 2)
11470 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11472 inst
.relax
= opcode
;
11476 /* Definitely a 32-bit variant. */
11478 /* Warning for Erratum 752419. */
11479 if (opcode
== T_MNEM_ldr
11480 && inst
.operands
[0].reg
== REG_SP
11481 && inst
.operands
[1].writeback
== 1
11482 && !inst
.operands
[1].immisreg
)
11484 if (no_cpu_selected ()
11485 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11486 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11487 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11488 as_warn (_("This instruction may be unpredictable "
11489 "if executed on M-profile cores "
11490 "with interrupts enabled."));
11493 /* Do some validations regarding addressing modes. */
11494 if (inst
.operands
[1].immisreg
)
11495 reject_bad_reg (inst
.operands
[1].imm
);
11497 constraint (inst
.operands
[1].writeback
== 1
11498 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11501 inst
.instruction
= THUMB_OP32 (opcode
);
11502 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11503 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11504 check_ldr_r15_aligned ();
11508 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11510 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11512 /* Only [Rn,Rm] is acceptable. */
11513 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11514 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11515 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11516 || inst
.operands
[1].negative
,
11517 _("Thumb does not support this addressing mode"));
11518 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11522 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11523 if (!inst
.operands
[1].isreg
)
11524 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11527 constraint (!inst
.operands
[1].preind
11528 || inst
.operands
[1].shifted
11529 || inst
.operands
[1].writeback
,
11530 _("Thumb does not support this addressing mode"));
11531 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11533 constraint (inst
.instruction
& 0x0600,
11534 _("byte or halfword not valid for base register"));
11535 constraint (inst
.operands
[1].reg
== REG_PC
11536 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11537 _("r15 based store not allowed"));
11538 constraint (inst
.operands
[1].immisreg
,
11539 _("invalid base register for register offset"));
11541 if (inst
.operands
[1].reg
== REG_PC
)
11542 inst
.instruction
= T_OPCODE_LDR_PC
;
11543 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11544 inst
.instruction
= T_OPCODE_LDR_SP
;
11546 inst
.instruction
= T_OPCODE_STR_SP
;
11548 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11549 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11553 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11554 if (!inst
.operands
[1].immisreg
)
11556 /* Immediate offset. */
11557 inst
.instruction
|= inst
.operands
[0].reg
;
11558 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11559 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11563 /* Register offset. */
11564 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11565 constraint (inst
.operands
[1].negative
,
11566 _("Thumb does not support this addressing mode"));
11569 switch (inst
.instruction
)
11571 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11572 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11573 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11574 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11575 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11576 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11577 case 0x5600 /* ldrsb */:
11578 case 0x5e00 /* ldrsh */: break;
11582 inst
.instruction
|= inst
.operands
[0].reg
;
11583 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11584 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11590 if (!inst
.operands
[1].present
)
11592 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11593 constraint (inst
.operands
[0].reg
== REG_LR
,
11594 _("r14 not allowed here"));
11595 constraint (inst
.operands
[0].reg
== REG_R12
,
11596 _("r12 not allowed here"));
11599 if (inst
.operands
[2].writeback
11600 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11601 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11602 as_warn (_("base register written back, and overlaps "
11603 "one of transfer registers"));
11605 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11606 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11607 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11613 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11614 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11620 unsigned Rd
, Rn
, Rm
, Ra
;
11622 Rd
= inst
.operands
[0].reg
;
11623 Rn
= inst
.operands
[1].reg
;
11624 Rm
= inst
.operands
[2].reg
;
11625 Ra
= inst
.operands
[3].reg
;
11627 reject_bad_reg (Rd
);
11628 reject_bad_reg (Rn
);
11629 reject_bad_reg (Rm
);
11630 reject_bad_reg (Ra
);
11632 inst
.instruction
|= Rd
<< 8;
11633 inst
.instruction
|= Rn
<< 16;
11634 inst
.instruction
|= Rm
;
11635 inst
.instruction
|= Ra
<< 12;
11641 unsigned RdLo
, RdHi
, Rn
, Rm
;
11643 RdLo
= inst
.operands
[0].reg
;
11644 RdHi
= inst
.operands
[1].reg
;
11645 Rn
= inst
.operands
[2].reg
;
11646 Rm
= inst
.operands
[3].reg
;
11648 reject_bad_reg (RdLo
);
11649 reject_bad_reg (RdHi
);
11650 reject_bad_reg (Rn
);
11651 reject_bad_reg (Rm
);
11653 inst
.instruction
|= RdLo
<< 12;
11654 inst
.instruction
|= RdHi
<< 8;
11655 inst
.instruction
|= Rn
<< 16;
11656 inst
.instruction
|= Rm
;
11660 do_t_mov_cmp (void)
11664 Rn
= inst
.operands
[0].reg
;
11665 Rm
= inst
.operands
[1].reg
;
11668 set_it_insn_type_last ();
11670 if (unified_syntax
)
11672 int r0off
= (inst
.instruction
== T_MNEM_mov
11673 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11674 unsigned long opcode
;
11675 bfd_boolean narrow
;
11676 bfd_boolean low_regs
;
11678 low_regs
= (Rn
<= 7 && Rm
<= 7);
11679 opcode
= inst
.instruction
;
11680 if (in_it_block ())
11681 narrow
= opcode
!= T_MNEM_movs
;
11683 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11684 if (inst
.size_req
== 4
11685 || inst
.operands
[1].shifted
)
11688 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11689 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11690 && !inst
.operands
[1].shifted
11694 inst
.instruction
= T2_SUBS_PC_LR
;
11698 if (opcode
== T_MNEM_cmp
)
11700 constraint (Rn
== REG_PC
, BAD_PC
);
11703 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11705 warn_deprecated_sp (Rm
);
11706 /* R15 was documented as a valid choice for Rm in ARMv6,
11707 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11708 tools reject R15, so we do too. */
11709 constraint (Rm
== REG_PC
, BAD_PC
);
11712 reject_bad_reg (Rm
);
11714 else if (opcode
== T_MNEM_mov
11715 || opcode
== T_MNEM_movs
)
11717 if (inst
.operands
[1].isreg
)
11719 if (opcode
== T_MNEM_movs
)
11721 reject_bad_reg (Rn
);
11722 reject_bad_reg (Rm
);
11726 /* This is mov.n. */
11727 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11728 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11730 as_tsktsk (_("Use of r%u as a source register is "
11731 "deprecated when r%u is the destination "
11732 "register."), Rm
, Rn
);
11737 /* This is mov.w. */
11738 constraint (Rn
== REG_PC
, BAD_PC
);
11739 constraint (Rm
== REG_PC
, BAD_PC
);
11740 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11744 reject_bad_reg (Rn
);
11747 if (!inst
.operands
[1].isreg
)
11749 /* Immediate operand. */
11750 if (!in_it_block () && opcode
== T_MNEM_mov
)
11752 if (low_regs
&& narrow
)
11754 inst
.instruction
= THUMB_OP16 (opcode
);
11755 inst
.instruction
|= Rn
<< 8;
11756 if (inst
.size_req
== 2)
11757 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11759 inst
.relax
= opcode
;
11763 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11764 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11765 inst
.instruction
|= Rn
<< r0off
;
11766 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11769 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11770 && (inst
.instruction
== T_MNEM_mov
11771 || inst
.instruction
== T_MNEM_movs
))
11773 /* Register shifts are encoded as separate shift instructions. */
11774 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11776 if (in_it_block ())
11781 if (inst
.size_req
== 4)
11784 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11790 switch (inst
.operands
[1].shift_kind
)
11793 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11796 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11799 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11802 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11808 inst
.instruction
= opcode
;
11811 inst
.instruction
|= Rn
;
11812 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11817 inst
.instruction
|= CONDS_BIT
;
11819 inst
.instruction
|= Rn
<< 8;
11820 inst
.instruction
|= Rm
<< 16;
11821 inst
.instruction
|= inst
.operands
[1].imm
;
11826 /* Some mov with immediate shift have narrow variants.
11827 Register shifts are handled above. */
11828 if (low_regs
&& inst
.operands
[1].shifted
11829 && (inst
.instruction
== T_MNEM_mov
11830 || inst
.instruction
== T_MNEM_movs
))
11832 if (in_it_block ())
11833 narrow
= (inst
.instruction
== T_MNEM_mov
);
11835 narrow
= (inst
.instruction
== T_MNEM_movs
);
11840 switch (inst
.operands
[1].shift_kind
)
11842 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11843 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11844 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11845 default: narrow
= FALSE
; break;
11851 inst
.instruction
|= Rn
;
11852 inst
.instruction
|= Rm
<< 3;
11853 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11857 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11858 inst
.instruction
|= Rn
<< r0off
;
11859 encode_thumb32_shifted_operand (1);
11863 switch (inst
.instruction
)
11866 /* In v4t or v5t a move of two lowregs produces unpredictable
11867 results. Don't allow this. */
11870 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
11871 "MOV Rd, Rs with two low registers is not "
11872 "permitted on this architecture");
11873 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
11877 inst
.instruction
= T_OPCODE_MOV_HR
;
11878 inst
.instruction
|= (Rn
& 0x8) << 4;
11879 inst
.instruction
|= (Rn
& 0x7);
11880 inst
.instruction
|= Rm
<< 3;
11884 /* We know we have low registers at this point.
11885 Generate LSLS Rd, Rs, #0. */
11886 inst
.instruction
= T_OPCODE_LSL_I
;
11887 inst
.instruction
|= Rn
;
11888 inst
.instruction
|= Rm
<< 3;
11894 inst
.instruction
= T_OPCODE_CMP_LR
;
11895 inst
.instruction
|= Rn
;
11896 inst
.instruction
|= Rm
<< 3;
11900 inst
.instruction
= T_OPCODE_CMP_HR
;
11901 inst
.instruction
|= (Rn
& 0x8) << 4;
11902 inst
.instruction
|= (Rn
& 0x7);
11903 inst
.instruction
|= Rm
<< 3;
11910 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11912 /* PR 10443: Do not silently ignore shifted operands. */
11913 constraint (inst
.operands
[1].shifted
,
11914 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11916 if (inst
.operands
[1].isreg
)
11918 if (Rn
< 8 && Rm
< 8)
11920 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11921 since a MOV instruction produces unpredictable results. */
11922 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11923 inst
.instruction
= T_OPCODE_ADD_I3
;
11925 inst
.instruction
= T_OPCODE_CMP_LR
;
11927 inst
.instruction
|= Rn
;
11928 inst
.instruction
|= Rm
<< 3;
11932 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11933 inst
.instruction
= T_OPCODE_MOV_HR
;
11935 inst
.instruction
= T_OPCODE_CMP_HR
;
11941 constraint (Rn
> 7,
11942 _("only lo regs allowed with immediate"));
11943 inst
.instruction
|= Rn
<< 8;
11944 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11955 top
= (inst
.instruction
& 0x00800000) != 0;
11956 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
11958 constraint (top
, _(":lower16: not allowed this instruction"));
11959 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
11961 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
11963 constraint (!top
, _(":upper16: not allowed this instruction"));
11964 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
11967 Rd
= inst
.operands
[0].reg
;
11968 reject_bad_reg (Rd
);
11970 inst
.instruction
|= Rd
<< 8;
11971 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
11973 imm
= inst
.reloc
.exp
.X_add_number
;
11974 inst
.instruction
|= (imm
& 0xf000) << 4;
11975 inst
.instruction
|= (imm
& 0x0800) << 15;
11976 inst
.instruction
|= (imm
& 0x0700) << 4;
11977 inst
.instruction
|= (imm
& 0x00ff);
11982 do_t_mvn_tst (void)
11986 Rn
= inst
.operands
[0].reg
;
11987 Rm
= inst
.operands
[1].reg
;
11989 if (inst
.instruction
== T_MNEM_cmp
11990 || inst
.instruction
== T_MNEM_cmn
)
11991 constraint (Rn
== REG_PC
, BAD_PC
);
11993 reject_bad_reg (Rn
);
11994 reject_bad_reg (Rm
);
11996 if (unified_syntax
)
11998 int r0off
= (inst
.instruction
== T_MNEM_mvn
11999 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12000 bfd_boolean narrow
;
12002 if (inst
.size_req
== 4
12003 || inst
.instruction
> 0xffff
12004 || inst
.operands
[1].shifted
12005 || Rn
> 7 || Rm
> 7)
12007 else if (inst
.instruction
== T_MNEM_cmn
12008 || inst
.instruction
== T_MNEM_tst
)
12010 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12011 narrow
= !in_it_block ();
12013 narrow
= in_it_block ();
12015 if (!inst
.operands
[1].isreg
)
12017 /* For an immediate, we always generate a 32-bit opcode;
12018 section relaxation will shrink it later if possible. */
12019 if (inst
.instruction
< 0xffff)
12020 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12021 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12022 inst
.instruction
|= Rn
<< r0off
;
12023 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12027 /* See if we can do this with a 16-bit instruction. */
12030 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12031 inst
.instruction
|= Rn
;
12032 inst
.instruction
|= Rm
<< 3;
12036 constraint (inst
.operands
[1].shifted
12037 && inst
.operands
[1].immisreg
,
12038 _("shift must be constant"));
12039 if (inst
.instruction
< 0xffff)
12040 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12041 inst
.instruction
|= Rn
<< r0off
;
12042 encode_thumb32_shifted_operand (1);
12048 constraint (inst
.instruction
> 0xffff
12049 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12050 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12051 _("unshifted register required"));
12052 constraint (Rn
> 7 || Rm
> 7,
12055 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12056 inst
.instruction
|= Rn
;
12057 inst
.instruction
|= Rm
<< 3;
12066 if (do_vfp_nsyn_mrs () == SUCCESS
)
12069 Rd
= inst
.operands
[0].reg
;
12070 reject_bad_reg (Rd
);
12071 inst
.instruction
|= Rd
<< 8;
12073 if (inst
.operands
[1].isreg
)
12075 unsigned br
= inst
.operands
[1].reg
;
12076 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12077 as_bad (_("bad register for mrs"));
12079 inst
.instruction
|= br
& (0xf << 16);
12080 inst
.instruction
|= (br
& 0x300) >> 4;
12081 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12085 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12087 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12089 /* PR gas/12698: The constraint is only applied for m_profile.
12090 If the user has specified -march=all, we want to ignore it as
12091 we are building for any CPU type, including non-m variants. */
12092 bfd_boolean m_profile
=
12093 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12094 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12095 "not support requested special purpose register"));
12098 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12100 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12101 _("'APSR', 'CPSR' or 'SPSR' expected"));
12103 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12104 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12105 inst
.instruction
|= 0xf0000;
12115 if (do_vfp_nsyn_msr () == SUCCESS
)
12118 constraint (!inst
.operands
[1].isreg
,
12119 _("Thumb encoding does not support an immediate here"));
12121 if (inst
.operands
[0].isreg
)
12122 flags
= (int)(inst
.operands
[0].reg
);
12124 flags
= inst
.operands
[0].imm
;
12126 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12128 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12130 /* PR gas/12698: The constraint is only applied for m_profile.
12131 If the user has specified -march=all, we want to ignore it as
12132 we are building for any CPU type, including non-m variants. */
12133 bfd_boolean m_profile
=
12134 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12135 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12136 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12137 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12138 && bits
!= PSR_f
)) && m_profile
,
12139 _("selected processor does not support requested special "
12140 "purpose register"));
12143 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12144 "requested special purpose register"));
12146 Rn
= inst
.operands
[1].reg
;
12147 reject_bad_reg (Rn
);
12149 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12150 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12151 inst
.instruction
|= (flags
& 0x300) >> 4;
12152 inst
.instruction
|= (flags
& 0xff);
12153 inst
.instruction
|= Rn
<< 16;
12159 bfd_boolean narrow
;
12160 unsigned Rd
, Rn
, Rm
;
12162 if (!inst
.operands
[2].present
)
12163 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12165 Rd
= inst
.operands
[0].reg
;
12166 Rn
= inst
.operands
[1].reg
;
12167 Rm
= inst
.operands
[2].reg
;
12169 if (unified_syntax
)
12171 if (inst
.size_req
== 4
12177 else if (inst
.instruction
== T_MNEM_muls
)
12178 narrow
= !in_it_block ();
12180 narrow
= in_it_block ();
12184 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12185 constraint (Rn
> 7 || Rm
> 7,
12192 /* 16-bit MULS/Conditional MUL. */
12193 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12194 inst
.instruction
|= Rd
;
12197 inst
.instruction
|= Rm
<< 3;
12199 inst
.instruction
|= Rn
<< 3;
12201 constraint (1, _("dest must overlap one source register"));
12205 constraint (inst
.instruction
!= T_MNEM_mul
,
12206 _("Thumb-2 MUL must not set flags"));
12208 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12209 inst
.instruction
|= Rd
<< 8;
12210 inst
.instruction
|= Rn
<< 16;
12211 inst
.instruction
|= Rm
<< 0;
12213 reject_bad_reg (Rd
);
12214 reject_bad_reg (Rn
);
12215 reject_bad_reg (Rm
);
12222 unsigned RdLo
, RdHi
, Rn
, Rm
;
12224 RdLo
= inst
.operands
[0].reg
;
12225 RdHi
= inst
.operands
[1].reg
;
12226 Rn
= inst
.operands
[2].reg
;
12227 Rm
= inst
.operands
[3].reg
;
12229 reject_bad_reg (RdLo
);
12230 reject_bad_reg (RdHi
);
12231 reject_bad_reg (Rn
);
12232 reject_bad_reg (Rm
);
12234 inst
.instruction
|= RdLo
<< 12;
12235 inst
.instruction
|= RdHi
<< 8;
12236 inst
.instruction
|= Rn
<< 16;
12237 inst
.instruction
|= Rm
;
12240 as_tsktsk (_("rdhi and rdlo must be different"));
12246 set_it_insn_type (NEUTRAL_IT_INSN
);
12248 if (unified_syntax
)
12250 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12252 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12253 inst
.instruction
|= inst
.operands
[0].imm
;
12257 /* PR9722: Check for Thumb2 availability before
12258 generating a thumb2 nop instruction. */
12259 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12261 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12262 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12265 inst
.instruction
= 0x46c0;
12270 constraint (inst
.operands
[0].present
,
12271 _("Thumb does not support NOP with hints"));
12272 inst
.instruction
= 0x46c0;
12279 if (unified_syntax
)
12281 bfd_boolean narrow
;
12283 if (THUMB_SETS_FLAGS (inst
.instruction
))
12284 narrow
= !in_it_block ();
12286 narrow
= in_it_block ();
12287 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12289 if (inst
.size_req
== 4)
12294 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12295 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12296 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12300 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12301 inst
.instruction
|= inst
.operands
[0].reg
;
12302 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12307 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12309 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12311 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12312 inst
.instruction
|= inst
.operands
[0].reg
;
12313 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12322 Rd
= inst
.operands
[0].reg
;
12323 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12325 reject_bad_reg (Rd
);
12326 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12327 reject_bad_reg (Rn
);
12329 inst
.instruction
|= Rd
<< 8;
12330 inst
.instruction
|= Rn
<< 16;
12332 if (!inst
.operands
[2].isreg
)
12334 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12335 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12341 Rm
= inst
.operands
[2].reg
;
12342 reject_bad_reg (Rm
);
12344 constraint (inst
.operands
[2].shifted
12345 && inst
.operands
[2].immisreg
,
12346 _("shift must be constant"));
12347 encode_thumb32_shifted_operand (2);
12354 unsigned Rd
, Rn
, Rm
;
12356 Rd
= inst
.operands
[0].reg
;
12357 Rn
= inst
.operands
[1].reg
;
12358 Rm
= inst
.operands
[2].reg
;
12360 reject_bad_reg (Rd
);
12361 reject_bad_reg (Rn
);
12362 reject_bad_reg (Rm
);
12364 inst
.instruction
|= Rd
<< 8;
12365 inst
.instruction
|= Rn
<< 16;
12366 inst
.instruction
|= Rm
;
12367 if (inst
.operands
[3].present
)
12369 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12370 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12371 _("expression too complex"));
12372 inst
.instruction
|= (val
& 0x1c) << 10;
12373 inst
.instruction
|= (val
& 0x03) << 6;
12380 if (!inst
.operands
[3].present
)
12384 inst
.instruction
&= ~0x00000020;
12386 /* PR 10168. Swap the Rm and Rn registers. */
12387 Rtmp
= inst
.operands
[1].reg
;
12388 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12389 inst
.operands
[2].reg
= Rtmp
;
12397 if (inst
.operands
[0].immisreg
)
12398 reject_bad_reg (inst
.operands
[0].imm
);
12400 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12404 do_t_push_pop (void)
12408 constraint (inst
.operands
[0].writeback
,
12409 _("push/pop do not support {reglist}^"));
12410 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12411 _("expression too complex"));
12413 mask
= inst
.operands
[0].imm
;
12414 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12415 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12416 else if (inst
.size_req
!= 4
12417 && (mask
& ~0xff) == (1 << (inst
.instruction
== T_MNEM_push
12418 ? REG_LR
: REG_PC
)))
12420 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12421 inst
.instruction
|= THUMB_PP_PC_LR
;
12422 inst
.instruction
|= mask
& 0xff;
12424 else if (unified_syntax
)
12426 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12427 encode_thumb2_ldmstm (13, mask
, TRUE
);
12431 inst
.error
= _("invalid register list to push/pop instruction");
12441 Rd
= inst
.operands
[0].reg
;
12442 Rm
= inst
.operands
[1].reg
;
12444 reject_bad_reg (Rd
);
12445 reject_bad_reg (Rm
);
12447 inst
.instruction
|= Rd
<< 8;
12448 inst
.instruction
|= Rm
<< 16;
12449 inst
.instruction
|= Rm
;
12457 Rd
= inst
.operands
[0].reg
;
12458 Rm
= inst
.operands
[1].reg
;
12460 reject_bad_reg (Rd
);
12461 reject_bad_reg (Rm
);
12463 if (Rd
<= 7 && Rm
<= 7
12464 && inst
.size_req
!= 4)
12466 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12467 inst
.instruction
|= Rd
;
12468 inst
.instruction
|= Rm
<< 3;
12470 else if (unified_syntax
)
12472 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12473 inst
.instruction
|= Rd
<< 8;
12474 inst
.instruction
|= Rm
<< 16;
12475 inst
.instruction
|= Rm
;
12478 inst
.error
= BAD_HIREG
;
12486 Rd
= inst
.operands
[0].reg
;
12487 Rm
= inst
.operands
[1].reg
;
12489 reject_bad_reg (Rd
);
12490 reject_bad_reg (Rm
);
12492 inst
.instruction
|= Rd
<< 8;
12493 inst
.instruction
|= Rm
;
12501 Rd
= inst
.operands
[0].reg
;
12502 Rs
= (inst
.operands
[1].present
12503 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12504 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12506 reject_bad_reg (Rd
);
12507 reject_bad_reg (Rs
);
12508 if (inst
.operands
[2].isreg
)
12509 reject_bad_reg (inst
.operands
[2].reg
);
12511 inst
.instruction
|= Rd
<< 8;
12512 inst
.instruction
|= Rs
<< 16;
12513 if (!inst
.operands
[2].isreg
)
12515 bfd_boolean narrow
;
12517 if ((inst
.instruction
& 0x00100000) != 0)
12518 narrow
= !in_it_block ();
12520 narrow
= in_it_block ();
12522 if (Rd
> 7 || Rs
> 7)
12525 if (inst
.size_req
== 4 || !unified_syntax
)
12528 if (inst
.reloc
.exp
.X_op
!= O_constant
12529 || inst
.reloc
.exp
.X_add_number
!= 0)
12532 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12533 relaxation, but it doesn't seem worth the hassle. */
12536 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12537 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12538 inst
.instruction
|= Rs
<< 3;
12539 inst
.instruction
|= Rd
;
12543 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12544 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12548 encode_thumb32_shifted_operand (2);
12554 if (warn_on_deprecated
12555 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12556 as_tsktsk (_("setend use is deprecated for ARMv8"));
12558 set_it_insn_type (OUTSIDE_IT_INSN
);
12559 if (inst
.operands
[0].imm
)
12560 inst
.instruction
|= 0x8;
12566 if (!inst
.operands
[1].present
)
12567 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12569 if (unified_syntax
)
12571 bfd_boolean narrow
;
12574 switch (inst
.instruction
)
12577 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12579 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12581 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12583 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12587 if (THUMB_SETS_FLAGS (inst
.instruction
))
12588 narrow
= !in_it_block ();
12590 narrow
= in_it_block ();
12591 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12593 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12595 if (inst
.operands
[2].isreg
12596 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12597 || inst
.operands
[2].reg
> 7))
12599 if (inst
.size_req
== 4)
12602 reject_bad_reg (inst
.operands
[0].reg
);
12603 reject_bad_reg (inst
.operands
[1].reg
);
12607 if (inst
.operands
[2].isreg
)
12609 reject_bad_reg (inst
.operands
[2].reg
);
12610 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12611 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12612 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12613 inst
.instruction
|= inst
.operands
[2].reg
;
12615 /* PR 12854: Error on extraneous shifts. */
12616 constraint (inst
.operands
[2].shifted
,
12617 _("extraneous shift as part of operand to shift insn"));
12621 inst
.operands
[1].shifted
= 1;
12622 inst
.operands
[1].shift_kind
= shift_kind
;
12623 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12624 ? T_MNEM_movs
: T_MNEM_mov
);
12625 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12626 encode_thumb32_shifted_operand (1);
12627 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12628 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12633 if (inst
.operands
[2].isreg
)
12635 switch (shift_kind
)
12637 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12638 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12639 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12640 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12644 inst
.instruction
|= inst
.operands
[0].reg
;
12645 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12647 /* PR 12854: Error on extraneous shifts. */
12648 constraint (inst
.operands
[2].shifted
,
12649 _("extraneous shift as part of operand to shift insn"));
12653 switch (shift_kind
)
12655 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12656 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12657 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12660 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12661 inst
.instruction
|= inst
.operands
[0].reg
;
12662 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12668 constraint (inst
.operands
[0].reg
> 7
12669 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12670 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12672 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12674 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12675 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12676 _("source1 and dest must be same register"));
12678 switch (inst
.instruction
)
12680 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12681 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12682 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12683 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12687 inst
.instruction
|= inst
.operands
[0].reg
;
12688 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12690 /* PR 12854: Error on extraneous shifts. */
12691 constraint (inst
.operands
[2].shifted
,
12692 _("extraneous shift as part of operand to shift insn"));
12696 switch (inst
.instruction
)
12698 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12699 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12700 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12701 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12704 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12705 inst
.instruction
|= inst
.operands
[0].reg
;
12706 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12714 unsigned Rd
, Rn
, Rm
;
12716 Rd
= inst
.operands
[0].reg
;
12717 Rn
= inst
.operands
[1].reg
;
12718 Rm
= inst
.operands
[2].reg
;
12720 reject_bad_reg (Rd
);
12721 reject_bad_reg (Rn
);
12722 reject_bad_reg (Rm
);
12724 inst
.instruction
|= Rd
<< 8;
12725 inst
.instruction
|= Rn
<< 16;
12726 inst
.instruction
|= Rm
;
12732 unsigned Rd
, Rn
, Rm
;
12734 Rd
= inst
.operands
[0].reg
;
12735 Rm
= inst
.operands
[1].reg
;
12736 Rn
= inst
.operands
[2].reg
;
12738 reject_bad_reg (Rd
);
12739 reject_bad_reg (Rn
);
12740 reject_bad_reg (Rm
);
12742 inst
.instruction
|= Rd
<< 8;
12743 inst
.instruction
|= Rn
<< 16;
12744 inst
.instruction
|= Rm
;
12750 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12751 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12752 _("SMC is not permitted on this architecture"));
12753 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12754 _("expression too complex"));
12755 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12756 inst
.instruction
|= (value
& 0xf000) >> 12;
12757 inst
.instruction
|= (value
& 0x0ff0);
12758 inst
.instruction
|= (value
& 0x000f) << 16;
12759 /* PR gas/15623: SMC instructions must be last in an IT block. */
12760 set_it_insn_type_last ();
12766 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12768 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12769 inst
.instruction
|= (value
& 0x0fff);
12770 inst
.instruction
|= (value
& 0xf000) << 4;
12774 do_t_ssat_usat (int bias
)
12778 Rd
= inst
.operands
[0].reg
;
12779 Rn
= inst
.operands
[2].reg
;
12781 reject_bad_reg (Rd
);
12782 reject_bad_reg (Rn
);
12784 inst
.instruction
|= Rd
<< 8;
12785 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12786 inst
.instruction
|= Rn
<< 16;
12788 if (inst
.operands
[3].present
)
12790 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12792 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12794 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12795 _("expression too complex"));
12797 if (shift_amount
!= 0)
12799 constraint (shift_amount
> 31,
12800 _("shift expression is too large"));
12802 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12803 inst
.instruction
|= 0x00200000; /* sh bit. */
12805 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12806 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12814 do_t_ssat_usat (1);
12822 Rd
= inst
.operands
[0].reg
;
12823 Rn
= inst
.operands
[2].reg
;
12825 reject_bad_reg (Rd
);
12826 reject_bad_reg (Rn
);
12828 inst
.instruction
|= Rd
<< 8;
12829 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12830 inst
.instruction
|= Rn
<< 16;
12836 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
12837 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
12838 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
12839 || inst
.operands
[2].negative
,
12842 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
12844 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12845 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12846 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12847 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12853 if (!inst
.operands
[2].present
)
12854 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
12856 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
12857 || inst
.operands
[0].reg
== inst
.operands
[2].reg
12858 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
12861 inst
.instruction
|= inst
.operands
[0].reg
;
12862 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12863 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
12864 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
12870 unsigned Rd
, Rn
, Rm
;
12872 Rd
= inst
.operands
[0].reg
;
12873 Rn
= inst
.operands
[1].reg
;
12874 Rm
= inst
.operands
[2].reg
;
12876 reject_bad_reg (Rd
);
12877 reject_bad_reg (Rn
);
12878 reject_bad_reg (Rm
);
12880 inst
.instruction
|= Rd
<< 8;
12881 inst
.instruction
|= Rn
<< 16;
12882 inst
.instruction
|= Rm
;
12883 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
12891 Rd
= inst
.operands
[0].reg
;
12892 Rm
= inst
.operands
[1].reg
;
12894 reject_bad_reg (Rd
);
12895 reject_bad_reg (Rm
);
12897 if (inst
.instruction
<= 0xffff
12898 && inst
.size_req
!= 4
12899 && Rd
<= 7 && Rm
<= 7
12900 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
12902 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12903 inst
.instruction
|= Rd
;
12904 inst
.instruction
|= Rm
<< 3;
12906 else if (unified_syntax
)
12908 if (inst
.instruction
<= 0xffff)
12909 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12910 inst
.instruction
|= Rd
<< 8;
12911 inst
.instruction
|= Rm
;
12912 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
12916 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
12917 _("Thumb encoding does not support rotation"));
12918 constraint (1, BAD_HIREG
);
12925 /* We have to do the following check manually as ARM_EXT_OS only applies
12927 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
12929 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
12930 /* This only applies to the v6m howver, not later architectures. */
12931 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
12932 as_bad (_("SVC is not permitted on this architecture"));
12933 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
12936 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
12945 half
= (inst
.instruction
& 0x10) != 0;
12946 set_it_insn_type_last ();
12947 constraint (inst
.operands
[0].immisreg
,
12948 _("instruction requires register index"));
12950 Rn
= inst
.operands
[0].reg
;
12951 Rm
= inst
.operands
[0].imm
;
12953 constraint (Rn
== REG_SP
, BAD_SP
);
12954 reject_bad_reg (Rm
);
12956 constraint (!half
&& inst
.operands
[0].shifted
,
12957 _("instruction does not allow shifted index"));
12958 inst
.instruction
|= (Rn
<< 16) | Rm
;
12964 if (!inst
.operands
[0].present
)
12965 inst
.operands
[0].imm
= 0;
12967 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
12969 constraint (inst
.size_req
== 2,
12970 _("immediate value out of range"));
12971 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12972 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
12973 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
12977 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12978 inst
.instruction
|= inst
.operands
[0].imm
;
12981 set_it_insn_type (NEUTRAL_IT_INSN
);
12988 do_t_ssat_usat (0);
12996 Rd
= inst
.operands
[0].reg
;
12997 Rn
= inst
.operands
[2].reg
;
12999 reject_bad_reg (Rd
);
13000 reject_bad_reg (Rn
);
13002 inst
.instruction
|= Rd
<< 8;
13003 inst
.instruction
|= inst
.operands
[1].imm
;
13004 inst
.instruction
|= Rn
<< 16;
13007 /* Neon instruction encoder helpers. */
13009 /* Encodings for the different types for various Neon opcodes. */
13011 /* An "invalid" code for the following tables. */
13014 struct neon_tab_entry
13017 unsigned float_or_poly
;
13018 unsigned scalar_or_imm
;
13021 /* Map overloaded Neon opcodes to their respective encodings. */
13022 #define NEON_ENC_TAB \
13023 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13024 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13025 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13026 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13027 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13028 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13029 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13030 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13031 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13032 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13033 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13034 /* Register variants of the following two instructions are encoded as
13035 vcge / vcgt with the operands reversed. */ \
13036 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13037 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13038 X(vfma, N_INV, 0x0000c10, N_INV), \
13039 X(vfms, N_INV, 0x0200c10, N_INV), \
13040 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13041 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13042 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13043 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13044 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13045 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13046 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13047 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13048 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13049 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13050 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13051 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13052 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13053 X(vshl, 0x0000400, N_INV, 0x0800510), \
13054 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13055 X(vand, 0x0000110, N_INV, 0x0800030), \
13056 X(vbic, 0x0100110, N_INV, 0x0800030), \
13057 X(veor, 0x1000110, N_INV, N_INV), \
13058 X(vorn, 0x0300110, N_INV, 0x0800010), \
13059 X(vorr, 0x0200110, N_INV, 0x0800010), \
13060 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13061 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13062 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13063 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13064 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13065 X(vst1, 0x0000000, 0x0800000, N_INV), \
13066 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13067 X(vst2, 0x0000100, 0x0800100, N_INV), \
13068 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13069 X(vst3, 0x0000200, 0x0800200, N_INV), \
13070 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13071 X(vst4, 0x0000300, 0x0800300, N_INV), \
13072 X(vmovn, 0x1b20200, N_INV, N_INV), \
13073 X(vtrn, 0x1b20080, N_INV, N_INV), \
13074 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13075 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13076 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13077 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13078 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13079 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13080 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13081 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13082 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13083 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13084 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13085 X(vseleq, 0xe000a00, N_INV, N_INV), \
13086 X(vselvs, 0xe100a00, N_INV, N_INV), \
13087 X(vselge, 0xe200a00, N_INV, N_INV), \
13088 X(vselgt, 0xe300a00, N_INV, N_INV), \
13089 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13090 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13091 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13092 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13093 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13094 X(aes, 0x3b00300, N_INV, N_INV), \
13095 X(sha3op, 0x2000c00, N_INV, N_INV), \
13096 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13097 X(sha2op, 0x3ba0380, N_INV, N_INV)
13101 #define X(OPC,I,F,S) N_MNEM_##OPC
13106 static const struct neon_tab_entry neon_enc_tab
[] =
13108 #define X(OPC,I,F,S) { (I), (F), (S) }
13113 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13114 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13115 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13116 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13117 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13118 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13119 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13120 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13121 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13122 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13123 #define NEON_ENC_SINGLE_(X) \
13124 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13125 #define NEON_ENC_DOUBLE_(X) \
13126 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13127 #define NEON_ENC_FPV8_(X) \
13128 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13130 #define NEON_ENCODE(type, inst) \
13133 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13134 inst.is_neon = 1; \
13138 #define check_neon_suffixes \
13141 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13143 as_bad (_("invalid neon suffix for non neon instruction")); \
13149 /* Define shapes for instruction operands. The following mnemonic characters
13150 are used in this table:
13152 F - VFP S<n> register
13153 D - Neon D<n> register
13154 Q - Neon Q<n> register
13158 L - D<n> register list
13160 This table is used to generate various data:
13161 - enumerations of the form NS_DDR to be used as arguments to
13163 - a table classifying shapes into single, double, quad, mixed.
13164 - a table used to drive neon_select_shape. */
13166 #define NEON_SHAPE_DEF \
13167 X(3, (D, D, D), DOUBLE), \
13168 X(3, (Q, Q, Q), QUAD), \
13169 X(3, (D, D, I), DOUBLE), \
13170 X(3, (Q, Q, I), QUAD), \
13171 X(3, (D, D, S), DOUBLE), \
13172 X(3, (Q, Q, S), QUAD), \
13173 X(2, (D, D), DOUBLE), \
13174 X(2, (Q, Q), QUAD), \
13175 X(2, (D, S), DOUBLE), \
13176 X(2, (Q, S), QUAD), \
13177 X(2, (D, R), DOUBLE), \
13178 X(2, (Q, R), QUAD), \
13179 X(2, (D, I), DOUBLE), \
13180 X(2, (Q, I), QUAD), \
13181 X(3, (D, L, D), DOUBLE), \
13182 X(2, (D, Q), MIXED), \
13183 X(2, (Q, D), MIXED), \
13184 X(3, (D, Q, I), MIXED), \
13185 X(3, (Q, D, I), MIXED), \
13186 X(3, (Q, D, D), MIXED), \
13187 X(3, (D, Q, Q), MIXED), \
13188 X(3, (Q, Q, D), MIXED), \
13189 X(3, (Q, D, S), MIXED), \
13190 X(3, (D, Q, S), MIXED), \
13191 X(4, (D, D, D, I), DOUBLE), \
13192 X(4, (Q, Q, Q, I), QUAD), \
13193 X(2, (F, F), SINGLE), \
13194 X(3, (F, F, F), SINGLE), \
13195 X(2, (F, I), SINGLE), \
13196 X(2, (F, D), MIXED), \
13197 X(2, (D, F), MIXED), \
13198 X(3, (F, F, I), MIXED), \
13199 X(4, (R, R, F, F), SINGLE), \
13200 X(4, (F, F, R, R), SINGLE), \
13201 X(3, (D, R, R), DOUBLE), \
13202 X(3, (R, R, D), DOUBLE), \
13203 X(2, (S, R), SINGLE), \
13204 X(2, (R, S), SINGLE), \
13205 X(2, (F, R), SINGLE), \
13206 X(2, (R, F), SINGLE)
13208 #define S2(A,B) NS_##A##B
13209 #define S3(A,B,C) NS_##A##B##C
13210 #define S4(A,B,C,D) NS_##A##B##C##D
13212 #define X(N, L, C) S##N L
13225 enum neon_shape_class
13233 #define X(N, L, C) SC_##C
13235 static enum neon_shape_class neon_shape_class
[] =
13253 /* Register widths of above. */
13254 static unsigned neon_shape_el_size
[] =
13265 struct neon_shape_info
13268 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13271 #define S2(A,B) { SE_##A, SE_##B }
13272 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13273 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13275 #define X(N, L, C) { N, S##N L }
13277 static struct neon_shape_info neon_shape_tab
[] =
13287 /* Bit masks used in type checking given instructions.
13288 'N_EQK' means the type must be the same as (or based on in some way) the key
13289 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13290 set, various other bits can be set as well in order to modify the meaning of
13291 the type constraint. */
13293 enum neon_type_mask
13317 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13318 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13319 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13320 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13321 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13322 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13323 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13324 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13325 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13326 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13327 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13329 N_MAX_NONSPECIAL
= N_P64
13332 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13334 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13335 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13336 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13337 #define N_SUF_32 (N_SU_32 | N_F32)
13338 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13339 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
13341 /* Pass this as the first type argument to neon_check_type to ignore types
13343 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13345 /* Select a "shape" for the current instruction (describing register types or
13346 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13347 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13348 function of operand parsing, so this function doesn't need to be called.
13349 Shapes should be listed in order of decreasing length. */
13351 static enum neon_shape
13352 neon_select_shape (enum neon_shape shape
, ...)
13355 enum neon_shape first_shape
= shape
;
13357 /* Fix missing optional operands. FIXME: we don't know at this point how
13358 many arguments we should have, so this makes the assumption that we have
13359 > 1. This is true of all current Neon opcodes, I think, but may not be
13360 true in the future. */
13361 if (!inst
.operands
[1].present
)
13362 inst
.operands
[1] = inst
.operands
[0];
13364 va_start (ap
, shape
);
13366 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13371 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13373 if (!inst
.operands
[j
].present
)
13379 switch (neon_shape_tab
[shape
].el
[j
])
13382 if (!(inst
.operands
[j
].isreg
13383 && inst
.operands
[j
].isvec
13384 && inst
.operands
[j
].issingle
13385 && !inst
.operands
[j
].isquad
))
13390 if (!(inst
.operands
[j
].isreg
13391 && inst
.operands
[j
].isvec
13392 && !inst
.operands
[j
].isquad
13393 && !inst
.operands
[j
].issingle
))
13398 if (!(inst
.operands
[j
].isreg
13399 && !inst
.operands
[j
].isvec
))
13404 if (!(inst
.operands
[j
].isreg
13405 && inst
.operands
[j
].isvec
13406 && inst
.operands
[j
].isquad
13407 && !inst
.operands
[j
].issingle
))
13412 if (!(!inst
.operands
[j
].isreg
13413 && !inst
.operands
[j
].isscalar
))
13418 if (!(!inst
.operands
[j
].isreg
13419 && inst
.operands
[j
].isscalar
))
13429 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13430 /* We've matched all the entries in the shape table, and we don't
13431 have any left over operands which have not been matched. */
13437 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13438 first_error (_("invalid instruction shape"));
13443 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13444 means the Q bit should be set). */
13447 neon_quad (enum neon_shape shape
)
13449 return neon_shape_class
[shape
] == SC_QUAD
;
13453 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13456 /* Allow modification to be made to types which are constrained to be
13457 based on the key element, based on bits set alongside N_EQK. */
13458 if ((typebits
& N_EQK
) != 0)
13460 if ((typebits
& N_HLF
) != 0)
13462 else if ((typebits
& N_DBL
) != 0)
13464 if ((typebits
& N_SGN
) != 0)
13465 *g_type
= NT_signed
;
13466 else if ((typebits
& N_UNS
) != 0)
13467 *g_type
= NT_unsigned
;
13468 else if ((typebits
& N_INT
) != 0)
13469 *g_type
= NT_integer
;
13470 else if ((typebits
& N_FLT
) != 0)
13471 *g_type
= NT_float
;
13472 else if ((typebits
& N_SIZ
) != 0)
13473 *g_type
= NT_untyped
;
13477 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13478 operand type, i.e. the single type specified in a Neon instruction when it
13479 is the only one given. */
13481 static struct neon_type_el
13482 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13484 struct neon_type_el dest
= *key
;
13486 gas_assert ((thisarg
& N_EQK
) != 0);
13488 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13493 /* Convert Neon type and size into compact bitmask representation. */
13495 static enum neon_type_mask
13496 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13503 case 8: return N_8
;
13504 case 16: return N_16
;
13505 case 32: return N_32
;
13506 case 64: return N_64
;
13514 case 8: return N_I8
;
13515 case 16: return N_I16
;
13516 case 32: return N_I32
;
13517 case 64: return N_I64
;
13525 case 16: return N_F16
;
13526 case 32: return N_F32
;
13527 case 64: return N_F64
;
13535 case 8: return N_P8
;
13536 case 16: return N_P16
;
13537 case 64: return N_P64
;
13545 case 8: return N_S8
;
13546 case 16: return N_S16
;
13547 case 32: return N_S32
;
13548 case 64: return N_S64
;
13556 case 8: return N_U8
;
13557 case 16: return N_U16
;
13558 case 32: return N_U32
;
13559 case 64: return N_U64
;
13570 /* Convert compact Neon bitmask type representation to a type and size. Only
13571 handles the case where a single bit is set in the mask. */
13574 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13575 enum neon_type_mask mask
)
13577 if ((mask
& N_EQK
) != 0)
13580 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13582 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13584 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13586 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13591 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13593 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13594 *type
= NT_unsigned
;
13595 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13596 *type
= NT_integer
;
13597 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13598 *type
= NT_untyped
;
13599 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13601 else if ((mask
& (N_F16
| N_F32
| N_F64
)) != 0)
13609 /* Modify a bitmask of allowed types. This is only needed for type
13613 modify_types_allowed (unsigned allowed
, unsigned mods
)
13616 enum neon_el_type type
;
13622 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13624 if (el_type_of_type_chk (&type
, &size
,
13625 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13627 neon_modify_type_size (mods
, &type
, &size
);
13628 destmask
|= type_chk_of_el_type (type
, size
);
13635 /* Check type and return type classification.
13636 The manual states (paraphrase): If one datatype is given, it indicates the
13638 - the second operand, if there is one
13639 - the operand, if there is no second operand
13640 - the result, if there are no operands.
13641 This isn't quite good enough though, so we use a concept of a "key" datatype
13642 which is set on a per-instruction basis, which is the one which matters when
13643 only one data type is written.
13644 Note: this function has side-effects (e.g. filling in missing operands). All
13645 Neon instructions should call it before performing bit encoding. */
13647 static struct neon_type_el
13648 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13651 unsigned i
, pass
, key_el
= 0;
13652 unsigned types
[NEON_MAX_TYPE_ELS
];
13653 enum neon_el_type k_type
= NT_invtype
;
13654 unsigned k_size
= -1u;
13655 struct neon_type_el badtype
= {NT_invtype
, -1};
13656 unsigned key_allowed
= 0;
13658 /* Optional registers in Neon instructions are always (not) in operand 1.
13659 Fill in the missing operand here, if it was omitted. */
13660 if (els
> 1 && !inst
.operands
[1].present
)
13661 inst
.operands
[1] = inst
.operands
[0];
13663 /* Suck up all the varargs. */
13665 for (i
= 0; i
< els
; i
++)
13667 unsigned thisarg
= va_arg (ap
, unsigned);
13668 if (thisarg
== N_IGNORE_TYPE
)
13673 types
[i
] = thisarg
;
13674 if ((thisarg
& N_KEY
) != 0)
13679 if (inst
.vectype
.elems
> 0)
13680 for (i
= 0; i
< els
; i
++)
13681 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13683 first_error (_("types specified in both the mnemonic and operands"));
13687 /* Duplicate inst.vectype elements here as necessary.
13688 FIXME: No idea if this is exactly the same as the ARM assembler,
13689 particularly when an insn takes one register and one non-register
13691 if (inst
.vectype
.elems
== 1 && els
> 1)
13694 inst
.vectype
.elems
= els
;
13695 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13696 for (j
= 0; j
< els
; j
++)
13698 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13701 else if (inst
.vectype
.elems
== 0 && els
> 0)
13704 /* No types were given after the mnemonic, so look for types specified
13705 after each operand. We allow some flexibility here; as long as the
13706 "key" operand has a type, we can infer the others. */
13707 for (j
= 0; j
< els
; j
++)
13708 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13709 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13711 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13713 for (j
= 0; j
< els
; j
++)
13714 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13715 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13720 first_error (_("operand types can't be inferred"));
13724 else if (inst
.vectype
.elems
!= els
)
13726 first_error (_("type specifier has the wrong number of parts"));
13730 for (pass
= 0; pass
< 2; pass
++)
13732 for (i
= 0; i
< els
; i
++)
13734 unsigned thisarg
= types
[i
];
13735 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13736 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13737 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13738 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13740 /* Decay more-specific signed & unsigned types to sign-insensitive
13741 integer types if sign-specific variants are unavailable. */
13742 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13743 && (types_allowed
& N_SU_ALL
) == 0)
13744 g_type
= NT_integer
;
13746 /* If only untyped args are allowed, decay any more specific types to
13747 them. Some instructions only care about signs for some element
13748 sizes, so handle that properly. */
13749 if (((types_allowed
& N_UNT
) == 0)
13750 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13751 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13752 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13753 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13754 g_type
= NT_untyped
;
13758 if ((thisarg
& N_KEY
) != 0)
13762 key_allowed
= thisarg
& ~N_KEY
;
13767 if ((thisarg
& N_VFP
) != 0)
13769 enum neon_shape_el regshape
;
13770 unsigned regwidth
, match
;
13772 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13775 first_error (_("invalid instruction shape"));
13778 regshape
= neon_shape_tab
[ns
].el
[i
];
13779 regwidth
= neon_shape_el_size
[regshape
];
13781 /* In VFP mode, operands must match register widths. If we
13782 have a key operand, use its width, else use the width of
13783 the current operand. */
13789 if (regwidth
!= match
)
13791 first_error (_("operand size must match register width"));
13796 if ((thisarg
& N_EQK
) == 0)
13798 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
13800 if ((given_type
& types_allowed
) == 0)
13802 first_error (_("bad type in Neon instruction"));
13808 enum neon_el_type mod_k_type
= k_type
;
13809 unsigned mod_k_size
= k_size
;
13810 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
13811 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
13813 first_error (_("inconsistent types in Neon instruction"));
13821 return inst
.vectype
.el
[key_el
];
13824 /* Neon-style VFP instruction forwarding. */
13826 /* Thumb VFP instructions have 0xE in the condition field. */
13829 do_vfp_cond_or_thumb (void)
13834 inst
.instruction
|= 0xe0000000;
13836 inst
.instruction
|= inst
.cond
<< 28;
13839 /* Look up and encode a simple mnemonic, for use as a helper function for the
13840 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13841 etc. It is assumed that operand parsing has already been done, and that the
13842 operands are in the form expected by the given opcode (this isn't necessarily
13843 the same as the form in which they were parsed, hence some massaging must
13844 take place before this function is called).
13845 Checks current arch version against that in the looked-up opcode. */
13848 do_vfp_nsyn_opcode (const char *opname
)
13850 const struct asm_opcode
*opcode
;
13852 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
13857 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
13858 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
13865 inst
.instruction
= opcode
->tvalue
;
13866 opcode
->tencode ();
13870 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
13871 opcode
->aencode ();
13876 do_vfp_nsyn_add_sub (enum neon_shape rs
)
13878 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
13883 do_vfp_nsyn_opcode ("fadds");
13885 do_vfp_nsyn_opcode ("fsubs");
13890 do_vfp_nsyn_opcode ("faddd");
13892 do_vfp_nsyn_opcode ("fsubd");
13896 /* Check operand types to see if this is a VFP instruction, and if so call
13900 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
13902 enum neon_shape rs
;
13903 struct neon_type_el et
;
13908 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13909 et
= neon_check_type (2, rs
,
13910 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13914 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13915 et
= neon_check_type (3, rs
,
13916 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13923 if (et
.type
!= NT_invtype
)
13934 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
13936 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
13941 do_vfp_nsyn_opcode ("fmacs");
13943 do_vfp_nsyn_opcode ("fnmacs");
13948 do_vfp_nsyn_opcode ("fmacd");
13950 do_vfp_nsyn_opcode ("fnmacd");
13955 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
13957 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
13962 do_vfp_nsyn_opcode ("ffmas");
13964 do_vfp_nsyn_opcode ("ffnmas");
13969 do_vfp_nsyn_opcode ("ffmad");
13971 do_vfp_nsyn_opcode ("ffnmad");
13976 do_vfp_nsyn_mul (enum neon_shape rs
)
13979 do_vfp_nsyn_opcode ("fmuls");
13981 do_vfp_nsyn_opcode ("fmuld");
13985 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
13987 int is_neg
= (inst
.instruction
& 0x80) != 0;
13988 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
13993 do_vfp_nsyn_opcode ("fnegs");
13995 do_vfp_nsyn_opcode ("fabss");
14000 do_vfp_nsyn_opcode ("fnegd");
14002 do_vfp_nsyn_opcode ("fabsd");
14006 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14007 insns belong to Neon, and are handled elsewhere. */
14010 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14012 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14016 do_vfp_nsyn_opcode ("fldmdbs");
14018 do_vfp_nsyn_opcode ("fldmias");
14023 do_vfp_nsyn_opcode ("fstmdbs");
14025 do_vfp_nsyn_opcode ("fstmias");
14030 do_vfp_nsyn_sqrt (void)
14032 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
14033 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
14036 do_vfp_nsyn_opcode ("fsqrts");
14038 do_vfp_nsyn_opcode ("fsqrtd");
14042 do_vfp_nsyn_div (void)
14044 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
14045 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14046 N_F32
| N_F64
| N_KEY
| N_VFP
);
14049 do_vfp_nsyn_opcode ("fdivs");
14051 do_vfp_nsyn_opcode ("fdivd");
14055 do_vfp_nsyn_nmul (void)
14057 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
14058 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14059 N_F32
| N_F64
| N_KEY
| N_VFP
);
14063 NEON_ENCODE (SINGLE
, inst
);
14064 do_vfp_sp_dyadic ();
14068 NEON_ENCODE (DOUBLE
, inst
);
14069 do_vfp_dp_rd_rn_rm ();
14071 do_vfp_cond_or_thumb ();
14075 do_vfp_nsyn_cmp (void)
14077 if (inst
.operands
[1].isreg
)
14079 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
14080 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
14084 NEON_ENCODE (SINGLE
, inst
);
14085 do_vfp_sp_monadic ();
14089 NEON_ENCODE (DOUBLE
, inst
);
14090 do_vfp_dp_rd_rm ();
14095 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
14096 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
14098 switch (inst
.instruction
& 0x0fffffff)
14101 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14104 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14112 NEON_ENCODE (SINGLE
, inst
);
14113 do_vfp_sp_compare_z ();
14117 NEON_ENCODE (DOUBLE
, inst
);
14121 do_vfp_cond_or_thumb ();
14125 nsyn_insert_sp (void)
14127 inst
.operands
[1] = inst
.operands
[0];
14128 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14129 inst
.operands
[0].reg
= REG_SP
;
14130 inst
.operands
[0].isreg
= 1;
14131 inst
.operands
[0].writeback
= 1;
14132 inst
.operands
[0].present
= 1;
14136 do_vfp_nsyn_push (void)
14139 if (inst
.operands
[1].issingle
)
14140 do_vfp_nsyn_opcode ("fstmdbs");
14142 do_vfp_nsyn_opcode ("fstmdbd");
14146 do_vfp_nsyn_pop (void)
14149 if (inst
.operands
[1].issingle
)
14150 do_vfp_nsyn_opcode ("fldmias");
14152 do_vfp_nsyn_opcode ("fldmiad");
14155 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14156 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14159 neon_dp_fixup (struct arm_it
* insn
)
14161 unsigned int i
= insn
->instruction
;
14166 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14177 insn
->instruction
= i
;
14180 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14184 neon_logbits (unsigned x
)
14186 return ffs (x
) - 4;
14189 #define LOW4(R) ((R) & 0xf)
14190 #define HI1(R) (((R) >> 4) & 1)
14192 /* Encode insns with bit pattern:
14194 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14195 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14197 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14198 different meaning for some instruction. */
14201 neon_three_same (int isquad
, int ubit
, int size
)
14203 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14204 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14205 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14206 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14207 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14208 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14209 inst
.instruction
|= (isquad
!= 0) << 6;
14210 inst
.instruction
|= (ubit
!= 0) << 24;
14212 inst
.instruction
|= neon_logbits (size
) << 20;
14214 neon_dp_fixup (&inst
);
14217 /* Encode instructions of the form:
14219 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14220 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14222 Don't write size if SIZE == -1. */
14225 neon_two_same (int qbit
, int ubit
, int size
)
14227 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14228 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14229 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14230 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14231 inst
.instruction
|= (qbit
!= 0) << 6;
14232 inst
.instruction
|= (ubit
!= 0) << 24;
14235 inst
.instruction
|= neon_logbits (size
) << 18;
14237 neon_dp_fixup (&inst
);
14240 /* Neon instruction encoders, in approximate order of appearance. */
14243 do_neon_dyadic_i_su (void)
14245 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14246 struct neon_type_el et
= neon_check_type (3, rs
,
14247 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14248 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14252 do_neon_dyadic_i64_su (void)
14254 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14255 struct neon_type_el et
= neon_check_type (3, rs
,
14256 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14257 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14261 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14264 unsigned size
= et
.size
>> 3;
14265 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14266 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14267 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14268 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14269 inst
.instruction
|= (isquad
!= 0) << 6;
14270 inst
.instruction
|= immbits
<< 16;
14271 inst
.instruction
|= (size
>> 3) << 7;
14272 inst
.instruction
|= (size
& 0x7) << 19;
14274 inst
.instruction
|= (uval
!= 0) << 24;
14276 neon_dp_fixup (&inst
);
14280 do_neon_shl_imm (void)
14282 if (!inst
.operands
[2].isreg
)
14284 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14285 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14286 int imm
= inst
.operands
[2].imm
;
14288 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14289 _("immediate out of range for shift"));
14290 NEON_ENCODE (IMMED
, inst
);
14291 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14295 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14296 struct neon_type_el et
= neon_check_type (3, rs
,
14297 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14300 /* VSHL/VQSHL 3-register variants have syntax such as:
14302 whereas other 3-register operations encoded by neon_three_same have
14305 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14307 tmp
= inst
.operands
[2].reg
;
14308 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14309 inst
.operands
[1].reg
= tmp
;
14310 NEON_ENCODE (INTEGER
, inst
);
14311 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14316 do_neon_qshl_imm (void)
14318 if (!inst
.operands
[2].isreg
)
14320 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14321 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14322 int imm
= inst
.operands
[2].imm
;
14324 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14325 _("immediate out of range for shift"));
14326 NEON_ENCODE (IMMED
, inst
);
14327 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14331 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14332 struct neon_type_el et
= neon_check_type (3, rs
,
14333 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14336 /* See note in do_neon_shl_imm. */
14337 tmp
= inst
.operands
[2].reg
;
14338 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14339 inst
.operands
[1].reg
= tmp
;
14340 NEON_ENCODE (INTEGER
, inst
);
14341 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14346 do_neon_rshl (void)
14348 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14349 struct neon_type_el et
= neon_check_type (3, rs
,
14350 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14353 tmp
= inst
.operands
[2].reg
;
14354 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14355 inst
.operands
[1].reg
= tmp
;
14356 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14360 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14362 /* Handle .I8 pseudo-instructions. */
14365 /* Unfortunately, this will make everything apart from zero out-of-range.
14366 FIXME is this the intended semantics? There doesn't seem much point in
14367 accepting .I8 if so. */
14368 immediate
|= immediate
<< 8;
14374 if (immediate
== (immediate
& 0x000000ff))
14376 *immbits
= immediate
;
14379 else if (immediate
== (immediate
& 0x0000ff00))
14381 *immbits
= immediate
>> 8;
14384 else if (immediate
== (immediate
& 0x00ff0000))
14386 *immbits
= immediate
>> 16;
14389 else if (immediate
== (immediate
& 0xff000000))
14391 *immbits
= immediate
>> 24;
14394 if ((immediate
& 0xffff) != (immediate
>> 16))
14395 goto bad_immediate
;
14396 immediate
&= 0xffff;
14399 if (immediate
== (immediate
& 0x000000ff))
14401 *immbits
= immediate
;
14404 else if (immediate
== (immediate
& 0x0000ff00))
14406 *immbits
= immediate
>> 8;
14411 first_error (_("immediate value out of range"));
14416 do_neon_logic (void)
14418 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14420 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14421 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14422 /* U bit and size field were set as part of the bitmask. */
14423 NEON_ENCODE (INTEGER
, inst
);
14424 neon_three_same (neon_quad (rs
), 0, -1);
14428 const int three_ops_form
= (inst
.operands
[2].present
14429 && !inst
.operands
[2].isreg
);
14430 const int immoperand
= (three_ops_form
? 2 : 1);
14431 enum neon_shape rs
= (three_ops_form
14432 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14433 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14434 struct neon_type_el et
= neon_check_type (2, rs
,
14435 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14436 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14440 if (et
.type
== NT_invtype
)
14443 if (three_ops_form
)
14444 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14445 _("first and second operands shall be the same register"));
14447 NEON_ENCODE (IMMED
, inst
);
14449 immbits
= inst
.operands
[immoperand
].imm
;
14452 /* .i64 is a pseudo-op, so the immediate must be a repeating
14454 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14455 inst
.operands
[immoperand
].reg
: 0))
14457 /* Set immbits to an invalid constant. */
14458 immbits
= 0xdeadbeef;
14465 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14469 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14473 /* Pseudo-instruction for VBIC. */
14474 neon_invert_size (&immbits
, 0, et
.size
);
14475 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14479 /* Pseudo-instruction for VORR. */
14480 neon_invert_size (&immbits
, 0, et
.size
);
14481 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14491 inst
.instruction
|= neon_quad (rs
) << 6;
14492 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14493 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14494 inst
.instruction
|= cmode
<< 8;
14495 neon_write_immbits (immbits
);
14497 neon_dp_fixup (&inst
);
14502 do_neon_bitfield (void)
14504 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14505 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14506 neon_three_same (neon_quad (rs
), 0, -1);
14510 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14513 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14514 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14516 if (et
.type
== NT_float
)
14518 NEON_ENCODE (FLOAT
, inst
);
14519 neon_three_same (neon_quad (rs
), 0, -1);
14523 NEON_ENCODE (INTEGER
, inst
);
14524 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14529 do_neon_dyadic_if_su (void)
14531 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14535 do_neon_dyadic_if_su_d (void)
14537 /* This version only allow D registers, but that constraint is enforced during
14538 operand parsing so we don't need to do anything extra here. */
14539 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14543 do_neon_dyadic_if_i_d (void)
14545 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14546 affected if we specify unsigned args. */
14547 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14550 enum vfp_or_neon_is_neon_bits
14553 NEON_CHECK_ARCH
= 2,
14554 NEON_CHECK_ARCH8
= 4
14557 /* Call this function if an instruction which may have belonged to the VFP or
14558 Neon instruction sets, but turned out to be a Neon instruction (due to the
14559 operand types involved, etc.). We have to check and/or fix-up a couple of
14562 - Make sure the user hasn't attempted to make a Neon instruction
14564 - Alter the value in the condition code field if necessary.
14565 - Make sure that the arch supports Neon instructions.
14567 Which of these operations take place depends on bits from enum
14568 vfp_or_neon_is_neon_bits.
14570 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14571 current instruction's condition is COND_ALWAYS, the condition field is
14572 changed to inst.uncond_value. This is necessary because instructions shared
14573 between VFP and Neon may be conditional for the VFP variants only, and the
14574 unconditional Neon version must have, e.g., 0xF in the condition field. */
14577 vfp_or_neon_is_neon (unsigned check
)
14579 /* Conditions are always legal in Thumb mode (IT blocks). */
14580 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14582 if (inst
.cond
!= COND_ALWAYS
)
14584 first_error (_(BAD_COND
));
14587 if (inst
.uncond_value
!= -1)
14588 inst
.instruction
|= inst
.uncond_value
<< 28;
14591 if ((check
& NEON_CHECK_ARCH
)
14592 && !mark_feature_used (&fpu_neon_ext_v1
))
14594 first_error (_(BAD_FPU
));
14598 if ((check
& NEON_CHECK_ARCH8
)
14599 && !mark_feature_used (&fpu_neon_ext_armv8
))
14601 first_error (_(BAD_FPU
));
14609 do_neon_addsub_if_i (void)
14611 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14614 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14617 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14618 affected if we specify unsigned args. */
14619 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14622 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14624 V<op> A,B (A is operand 0, B is operand 2)
14629 so handle that case specially. */
14632 neon_exchange_operands (void)
14634 void *scratch
= alloca (sizeof (inst
.operands
[0]));
14635 if (inst
.operands
[1].present
)
14637 /* Swap operands[1] and operands[2]. */
14638 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14639 inst
.operands
[1] = inst
.operands
[2];
14640 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14644 inst
.operands
[1] = inst
.operands
[2];
14645 inst
.operands
[2] = inst
.operands
[0];
14650 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14652 if (inst
.operands
[2].isreg
)
14655 neon_exchange_operands ();
14656 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14660 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14661 struct neon_type_el et
= neon_check_type (2, rs
,
14662 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14664 NEON_ENCODE (IMMED
, inst
);
14665 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14666 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14667 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14668 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14669 inst
.instruction
|= neon_quad (rs
) << 6;
14670 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14671 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14673 neon_dp_fixup (&inst
);
14680 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
14684 do_neon_cmp_inv (void)
14686 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
14692 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
14695 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14696 scalars, which are encoded in 5 bits, M : Rm.
14697 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14698 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14702 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
14704 unsigned regno
= NEON_SCALAR_REG (scalar
);
14705 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
14710 if (regno
> 7 || elno
> 3)
14712 return regno
| (elno
<< 3);
14715 if (regno
> 15 || elno
> 1)
14717 return regno
| (elno
<< 4);
14721 first_error (_("scalar out of range for multiply instruction"));
14727 /* Encode multiply / multiply-accumulate scalar instructions. */
14730 neon_mul_mac (struct neon_type_el et
, int ubit
)
14734 /* Give a more helpful error message if we have an invalid type. */
14735 if (et
.type
== NT_invtype
)
14738 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
14739 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14740 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14741 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14742 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14743 inst
.instruction
|= LOW4 (scalar
);
14744 inst
.instruction
|= HI1 (scalar
) << 5;
14745 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14746 inst
.instruction
|= neon_logbits (et
.size
) << 20;
14747 inst
.instruction
|= (ubit
!= 0) << 24;
14749 neon_dp_fixup (&inst
);
14753 do_neon_mac_maybe_scalar (void)
14755 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
14758 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14761 if (inst
.operands
[2].isscalar
)
14763 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14764 struct neon_type_el et
= neon_check_type (3, rs
,
14765 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
14766 NEON_ENCODE (SCALAR
, inst
);
14767 neon_mul_mac (et
, neon_quad (rs
));
14771 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14772 affected if we specify unsigned args. */
14773 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14778 do_neon_fmac (void)
14780 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
14783 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14786 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14792 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14793 struct neon_type_el et
= neon_check_type (3, rs
,
14794 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14795 neon_three_same (neon_quad (rs
), 0, et
.size
);
14798 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14799 same types as the MAC equivalents. The polynomial type for this instruction
14800 is encoded the same as the integer type. */
14805 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
14808 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14811 if (inst
.operands
[2].isscalar
)
14812 do_neon_mac_maybe_scalar ();
14814 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
14818 do_neon_qdmulh (void)
14820 if (inst
.operands
[2].isscalar
)
14822 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14823 struct neon_type_el et
= neon_check_type (3, rs
,
14824 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14825 NEON_ENCODE (SCALAR
, inst
);
14826 neon_mul_mac (et
, neon_quad (rs
));
14830 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14831 struct neon_type_el et
= neon_check_type (3, rs
,
14832 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14833 NEON_ENCODE (INTEGER
, inst
);
14834 /* The U bit (rounding) comes from bit mask. */
14835 neon_three_same (neon_quad (rs
), 0, et
.size
);
14840 do_neon_fcmp_absolute (void)
14842 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14843 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14844 /* Size field comes from bit mask. */
14845 neon_three_same (neon_quad (rs
), 1, -1);
14849 do_neon_fcmp_absolute_inv (void)
14851 neon_exchange_operands ();
14852 do_neon_fcmp_absolute ();
14856 do_neon_step (void)
14858 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14859 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14860 neon_three_same (neon_quad (rs
), 0, -1);
14864 do_neon_abs_neg (void)
14866 enum neon_shape rs
;
14867 struct neon_type_el et
;
14869 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
14872 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14875 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14876 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
14878 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14879 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14880 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14881 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14882 inst
.instruction
|= neon_quad (rs
) << 6;
14883 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14884 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14886 neon_dp_fixup (&inst
);
14892 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14893 struct neon_type_el et
= neon_check_type (2, rs
,
14894 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14895 int imm
= inst
.operands
[2].imm
;
14896 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14897 _("immediate out of range for insert"));
14898 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14904 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14905 struct neon_type_el et
= neon_check_type (2, rs
,
14906 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14907 int imm
= inst
.operands
[2].imm
;
14908 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14909 _("immediate out of range for insert"));
14910 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
14914 do_neon_qshlu_imm (void)
14916 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14917 struct neon_type_el et
= neon_check_type (2, rs
,
14918 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
14919 int imm
= inst
.operands
[2].imm
;
14920 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14921 _("immediate out of range for shift"));
14922 /* Only encodes the 'U present' variant of the instruction.
14923 In this case, signed types have OP (bit 8) set to 0.
14924 Unsigned types have OP set to 1. */
14925 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
14926 /* The rest of the bits are the same as other immediate shifts. */
14927 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14931 do_neon_qmovn (void)
14933 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14934 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14935 /* Saturating move where operands can be signed or unsigned, and the
14936 destination has the same signedness. */
14937 NEON_ENCODE (INTEGER
, inst
);
14938 if (et
.type
== NT_unsigned
)
14939 inst
.instruction
|= 0xc0;
14941 inst
.instruction
|= 0x80;
14942 neon_two_same (0, 1, et
.size
/ 2);
14946 do_neon_qmovun (void)
14948 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14949 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14950 /* Saturating move with unsigned results. Operands must be signed. */
14951 NEON_ENCODE (INTEGER
, inst
);
14952 neon_two_same (0, 1, et
.size
/ 2);
14956 do_neon_rshift_sat_narrow (void)
14958 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14959 or unsigned. If operands are unsigned, results must also be unsigned. */
14960 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14961 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14962 int imm
= inst
.operands
[2].imm
;
14963 /* This gets the bounds check, size encoding and immediate bits calculation
14967 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14968 VQMOVN.I<size> <Dd>, <Qm>. */
14971 inst
.operands
[2].present
= 0;
14972 inst
.instruction
= N_MNEM_vqmovn
;
14977 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14978 _("immediate out of range"));
14979 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
14983 do_neon_rshift_sat_narrow_u (void)
14985 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14986 or unsigned. If operands are unsigned, results must also be unsigned. */
14987 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14988 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14989 int imm
= inst
.operands
[2].imm
;
14990 /* This gets the bounds check, size encoding and immediate bits calculation
14994 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14995 VQMOVUN.I<size> <Dd>, <Qm>. */
14998 inst
.operands
[2].present
= 0;
14999 inst
.instruction
= N_MNEM_vqmovun
;
15004 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15005 _("immediate out of range"));
15006 /* FIXME: The manual is kind of unclear about what value U should have in
15007 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15009 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15013 do_neon_movn (void)
15015 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15016 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15017 NEON_ENCODE (INTEGER
, inst
);
15018 neon_two_same (0, 1, et
.size
/ 2);
15022 do_neon_rshift_narrow (void)
15024 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15025 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15026 int imm
= inst
.operands
[2].imm
;
15027 /* This gets the bounds check, size encoding and immediate bits calculation
15031 /* If immediate is zero then we are a pseudo-instruction for
15032 VMOVN.I<size> <Dd>, <Qm> */
15035 inst
.operands
[2].present
= 0;
15036 inst
.instruction
= N_MNEM_vmovn
;
15041 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15042 _("immediate out of range for narrowing operation"));
15043 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15047 do_neon_shll (void)
15049 /* FIXME: Type checking when lengthening. */
15050 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15051 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15052 unsigned imm
= inst
.operands
[2].imm
;
15054 if (imm
== et
.size
)
15056 /* Maximum shift variant. */
15057 NEON_ENCODE (INTEGER
, inst
);
15058 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15059 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15060 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15061 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15062 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15064 neon_dp_fixup (&inst
);
15068 /* A more-specific type check for non-max versions. */
15069 et
= neon_check_type (2, NS_QDI
,
15070 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15071 NEON_ENCODE (IMMED
, inst
);
15072 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15076 /* Check the various types for the VCVT instruction, and return which version
15077 the current instruction is. */
15079 #define CVT_FLAVOUR_VAR \
15080 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15081 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15082 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15083 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15084 /* Half-precision conversions. */ \
15085 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15086 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15087 /* VFP instructions. */ \
15088 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15089 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15090 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15091 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15092 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15093 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15094 /* VFP instructions with bitshift. */ \
15095 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15096 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15097 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15098 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15099 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15100 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15101 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15102 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15104 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15105 neon_cvt_flavour_##C,
15107 /* The different types of conversions we can do. */
15108 enum neon_cvt_flavour
15111 neon_cvt_flavour_invalid
,
15112 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15117 static enum neon_cvt_flavour
15118 get_neon_cvt_flavour (enum neon_shape rs
)
15120 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15121 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15122 if (et.type != NT_invtype) \
15124 inst.error = NULL; \
15125 return (neon_cvt_flavour_##C); \
15128 struct neon_type_el et
;
15129 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15130 || rs
== NS_FF
) ? N_VFP
: 0;
15131 /* The instruction versions which take an immediate take one register
15132 argument, which is extended to the width of the full register. Thus the
15133 "source" and "destination" registers must have the same width. Hack that
15134 here by making the size equal to the key (wider, in this case) operand. */
15135 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15139 return neon_cvt_flavour_invalid
;
15154 /* Neon-syntax VFP conversions. */
15157 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15159 const char *opname
= 0;
15161 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
15163 /* Conversions with immediate bitshift. */
15164 const char *enc
[] =
15166 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15172 if (flavour
< (int) ARRAY_SIZE (enc
))
15174 opname
= enc
[flavour
];
15175 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15176 _("operands 0 and 1 must be the same register"));
15177 inst
.operands
[1] = inst
.operands
[2];
15178 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15183 /* Conversions without bitshift. */
15184 const char *enc
[] =
15186 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15192 if (flavour
< (int) ARRAY_SIZE (enc
))
15193 opname
= enc
[flavour
];
15197 do_vfp_nsyn_opcode (opname
);
15201 do_vfp_nsyn_cvtz (void)
15203 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
15204 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15205 const char *enc
[] =
15207 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15213 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15214 do_vfp_nsyn_opcode (enc
[flavour
]);
15218 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15219 enum neon_cvt_mode mode
)
15224 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15225 D register operands. */
15226 if (flavour
== neon_cvt_flavour_s32_f64
15227 || flavour
== neon_cvt_flavour_u32_f64
)
15228 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15231 set_it_insn_type (OUTSIDE_IT_INSN
);
15235 case neon_cvt_flavour_s32_f64
:
15239 case neon_cvt_flavour_s32_f32
:
15243 case neon_cvt_flavour_u32_f64
:
15247 case neon_cvt_flavour_u32_f32
:
15252 first_error (_("invalid instruction shape"));
15258 case neon_cvt_mode_a
: rm
= 0; break;
15259 case neon_cvt_mode_n
: rm
= 1; break;
15260 case neon_cvt_mode_p
: rm
= 2; break;
15261 case neon_cvt_mode_m
: rm
= 3; break;
15262 default: first_error (_("invalid rounding mode")); return;
15265 NEON_ENCODE (FPV8
, inst
);
15266 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15267 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15268 inst
.instruction
|= sz
<< 8;
15269 inst
.instruction
|= op
<< 7;
15270 inst
.instruction
|= rm
<< 16;
15271 inst
.instruction
|= 0xf0000000;
15272 inst
.is_neon
= TRUE
;
15276 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15278 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15279 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
15280 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15282 /* PR11109: Handle round-to-zero for VCVT conversions. */
15283 if (mode
== neon_cvt_mode_z
15284 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15285 && (flavour
== neon_cvt_flavour_s32_f32
15286 || flavour
== neon_cvt_flavour_u32_f32
15287 || flavour
== neon_cvt_flavour_s32_f64
15288 || flavour
== neon_cvt_flavour_u32_f64
)
15289 && (rs
== NS_FD
|| rs
== NS_FF
))
15291 do_vfp_nsyn_cvtz ();
15295 /* VFP rather than Neon conversions. */
15296 if (flavour
>= neon_cvt_flavour_first_fp
)
15298 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15299 do_vfp_nsyn_cvt (rs
, flavour
);
15301 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15312 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
15314 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15317 /* Fixed-point conversion with #0 immediate is encoded as an
15318 integer conversion. */
15319 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15321 immbits
= 32 - inst
.operands
[2].imm
;
15322 NEON_ENCODE (IMMED
, inst
);
15323 if (flavour
!= neon_cvt_flavour_invalid
)
15324 inst
.instruction
|= enctab
[flavour
];
15325 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15326 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15327 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15328 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15329 inst
.instruction
|= neon_quad (rs
) << 6;
15330 inst
.instruction
|= 1 << 21;
15331 inst
.instruction
|= immbits
<< 16;
15333 neon_dp_fixup (&inst
);
15339 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15341 NEON_ENCODE (FLOAT
, inst
);
15342 set_it_insn_type (OUTSIDE_IT_INSN
);
15344 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15347 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15348 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15349 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15350 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15351 inst
.instruction
|= neon_quad (rs
) << 6;
15352 inst
.instruction
|= (flavour
== neon_cvt_flavour_u32_f32
) << 7;
15353 inst
.instruction
|= mode
<< 8;
15355 inst
.instruction
|= 0xfc000000;
15357 inst
.instruction
|= 0xf0000000;
15363 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
15365 NEON_ENCODE (INTEGER
, inst
);
15367 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15370 if (flavour
!= neon_cvt_flavour_invalid
)
15371 inst
.instruction
|= enctab
[flavour
];
15373 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15374 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15375 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15376 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15377 inst
.instruction
|= neon_quad (rs
) << 6;
15378 inst
.instruction
|= 2 << 18;
15380 neon_dp_fixup (&inst
);
15385 /* Half-precision conversions for Advanced SIMD -- neon. */
15390 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15392 as_bad (_("operand size must match register width"));
15397 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15399 as_bad (_("operand size must match register width"));
15404 inst
.instruction
= 0x3b60600;
15406 inst
.instruction
= 0x3b60700;
15408 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15409 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15410 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15411 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15412 neon_dp_fixup (&inst
);
15416 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15417 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15418 do_vfp_nsyn_cvt (rs
, flavour
);
15420 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15425 do_neon_cvtr (void)
15427 do_neon_cvt_1 (neon_cvt_mode_x
);
15433 do_neon_cvt_1 (neon_cvt_mode_z
);
15437 do_neon_cvta (void)
15439 do_neon_cvt_1 (neon_cvt_mode_a
);
15443 do_neon_cvtn (void)
15445 do_neon_cvt_1 (neon_cvt_mode_n
);
15449 do_neon_cvtp (void)
15451 do_neon_cvt_1 (neon_cvt_mode_p
);
15455 do_neon_cvtm (void)
15457 do_neon_cvt_1 (neon_cvt_mode_m
);
15461 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15464 mark_feature_used (&fpu_vfp_ext_armv8
);
15466 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15467 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15468 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15469 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15470 inst
.instruction
|= to
? 0x10000 : 0;
15471 inst
.instruction
|= t
? 0x80 : 0;
15472 inst
.instruction
|= is_double
? 0x100 : 0;
15473 do_vfp_cond_or_thumb ();
15477 do_neon_cvttb_1 (bfd_boolean t
)
15479 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_DF
, NS_NULL
);
15483 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15486 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15488 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15491 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15493 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15495 /* The VCVTB and VCVTT instructions with D-register operands
15496 don't work for SP only targets. */
15497 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15501 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15503 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15505 /* The VCVTB and VCVTT instructions with D-register operands
15506 don't work for SP only targets. */
15507 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15511 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15518 do_neon_cvtb (void)
15520 do_neon_cvttb_1 (FALSE
);
15525 do_neon_cvtt (void)
15527 do_neon_cvttb_1 (TRUE
);
15531 neon_move_immediate (void)
15533 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15534 struct neon_type_el et
= neon_check_type (2, rs
,
15535 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15536 unsigned immlo
, immhi
= 0, immbits
;
15537 int op
, cmode
, float_p
;
15539 constraint (et
.type
== NT_invtype
,
15540 _("operand size must be specified for immediate VMOV"));
15542 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15543 op
= (inst
.instruction
& (1 << 5)) != 0;
15545 immlo
= inst
.operands
[1].imm
;
15546 if (inst
.operands
[1].regisimm
)
15547 immhi
= inst
.operands
[1].reg
;
15549 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15550 _("immediate has bits set outside the operand size"));
15552 float_p
= inst
.operands
[1].immisfloat
;
15554 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15555 et
.size
, et
.type
)) == FAIL
)
15557 /* Invert relevant bits only. */
15558 neon_invert_size (&immlo
, &immhi
, et
.size
);
15559 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15560 with one or the other; those cases are caught by
15561 neon_cmode_for_move_imm. */
15563 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15564 &op
, et
.size
, et
.type
)) == FAIL
)
15566 first_error (_("immediate out of range"));
15571 inst
.instruction
&= ~(1 << 5);
15572 inst
.instruction
|= op
<< 5;
15574 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15575 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15576 inst
.instruction
|= neon_quad (rs
) << 6;
15577 inst
.instruction
|= cmode
<< 8;
15579 neon_write_immbits (immbits
);
15585 if (inst
.operands
[1].isreg
)
15587 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15589 NEON_ENCODE (INTEGER
, inst
);
15590 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15591 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15592 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15593 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15594 inst
.instruction
|= neon_quad (rs
) << 6;
15598 NEON_ENCODE (IMMED
, inst
);
15599 neon_move_immediate ();
15602 neon_dp_fixup (&inst
);
15605 /* Encode instructions of form:
15607 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15608 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15611 neon_mixed_length (struct neon_type_el et
, unsigned size
)
15613 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15614 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15615 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15616 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15617 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15618 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15619 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
15620 inst
.instruction
|= neon_logbits (size
) << 20;
15622 neon_dp_fixup (&inst
);
15626 do_neon_dyadic_long (void)
15628 /* FIXME: Type checking for lengthening op. */
15629 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15630 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15631 neon_mixed_length (et
, et
.size
);
15635 do_neon_abal (void)
15637 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15638 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15639 neon_mixed_length (et
, et
.size
);
15643 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
15645 if (inst
.operands
[2].isscalar
)
15647 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
15648 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
15649 NEON_ENCODE (SCALAR
, inst
);
15650 neon_mul_mac (et
, et
.type
== NT_unsigned
);
15654 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15655 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
15656 NEON_ENCODE (INTEGER
, inst
);
15657 neon_mixed_length (et
, et
.size
);
15662 do_neon_mac_maybe_scalar_long (void)
15664 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
15668 do_neon_dyadic_wide (void)
15670 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
15671 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15672 neon_mixed_length (et
, et
.size
);
15676 do_neon_dyadic_narrow (void)
15678 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15679 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
15680 /* Operand sign is unimportant, and the U bit is part of the opcode,
15681 so force the operand type to integer. */
15682 et
.type
= NT_integer
;
15683 neon_mixed_length (et
, et
.size
/ 2);
15687 do_neon_mul_sat_scalar_long (void)
15689 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
15693 do_neon_vmull (void)
15695 if (inst
.operands
[2].isscalar
)
15696 do_neon_mac_maybe_scalar_long ();
15699 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15700 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
15702 if (et
.type
== NT_poly
)
15703 NEON_ENCODE (POLY
, inst
);
15705 NEON_ENCODE (INTEGER
, inst
);
15707 /* For polynomial encoding the U bit must be zero, and the size must
15708 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15709 obviously, as 0b10). */
15712 /* Check we're on the correct architecture. */
15713 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
15715 _("Instruction form not available on this architecture.");
15720 neon_mixed_length (et
, et
.size
);
15727 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
15728 struct neon_type_el et
= neon_check_type (3, rs
,
15729 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15730 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
15732 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
15733 _("shift out of range"));
15734 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15735 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15736 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15737 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15738 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15739 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15740 inst
.instruction
|= neon_quad (rs
) << 6;
15741 inst
.instruction
|= imm
<< 8;
15743 neon_dp_fixup (&inst
);
15749 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15750 struct neon_type_el et
= neon_check_type (2, rs
,
15751 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15752 unsigned op
= (inst
.instruction
>> 7) & 3;
15753 /* N (width of reversed regions) is encoded as part of the bitmask. We
15754 extract it here to check the elements to be reversed are smaller.
15755 Otherwise we'd get a reserved instruction. */
15756 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
15757 gas_assert (elsize
!= 0);
15758 constraint (et
.size
>= elsize
,
15759 _("elements must be smaller than reversal region"));
15760 neon_two_same (neon_quad (rs
), 1, et
.size
);
15766 if (inst
.operands
[1].isscalar
)
15768 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
15769 struct neon_type_el et
= neon_check_type (2, rs
,
15770 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15771 unsigned sizebits
= et
.size
>> 3;
15772 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
15773 int logsize
= neon_logbits (et
.size
);
15774 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
15776 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
15779 NEON_ENCODE (SCALAR
, inst
);
15780 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15781 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15782 inst
.instruction
|= LOW4 (dm
);
15783 inst
.instruction
|= HI1 (dm
) << 5;
15784 inst
.instruction
|= neon_quad (rs
) << 6;
15785 inst
.instruction
|= x
<< 17;
15786 inst
.instruction
|= sizebits
<< 16;
15788 neon_dp_fixup (&inst
);
15792 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
15793 struct neon_type_el et
= neon_check_type (2, rs
,
15794 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15795 /* Duplicate ARM register to lanes of vector. */
15796 NEON_ENCODE (ARMREG
, inst
);
15799 case 8: inst
.instruction
|= 0x400000; break;
15800 case 16: inst
.instruction
|= 0x000020; break;
15801 case 32: inst
.instruction
|= 0x000000; break;
15804 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15805 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
15806 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
15807 inst
.instruction
|= neon_quad (rs
) << 21;
15808 /* The encoding for this instruction is identical for the ARM and Thumb
15809 variants, except for the condition field. */
15810 do_vfp_cond_or_thumb ();
15814 /* VMOV has particularly many variations. It can be one of:
15815 0. VMOV<c><q> <Qd>, <Qm>
15816 1. VMOV<c><q> <Dd>, <Dm>
15817 (Register operations, which are VORR with Rm = Rn.)
15818 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15819 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15821 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15822 (ARM register to scalar.)
15823 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15824 (Two ARM registers to vector.)
15825 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15826 (Scalar to ARM register.)
15827 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15828 (Vector to two ARM registers.)
15829 8. VMOV.F32 <Sd>, <Sm>
15830 9. VMOV.F64 <Dd>, <Dm>
15831 (VFP register moves.)
15832 10. VMOV.F32 <Sd>, #imm
15833 11. VMOV.F64 <Dd>, #imm
15834 (VFP float immediate load.)
15835 12. VMOV <Rd>, <Sm>
15836 (VFP single to ARM reg.)
15837 13. VMOV <Sd>, <Rm>
15838 (ARM reg to VFP single.)
15839 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15840 (Two ARM regs to two VFP singles.)
15841 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15842 (Two VFP singles to two ARM regs.)
15844 These cases can be disambiguated using neon_select_shape, except cases 1/9
15845 and 3/11 which depend on the operand type too.
15847 All the encoded bits are hardcoded by this function.
15849 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15850 Cases 5, 7 may be used with VFPv2 and above.
15852 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15853 can specify a type where it doesn't make sense to, and is ignored). */
15858 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
15859 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
15861 struct neon_type_el et
;
15862 const char *ldconst
= 0;
15866 case NS_DD
: /* case 1/9. */
15867 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15868 /* It is not an error here if no type is given. */
15870 if (et
.type
== NT_float
&& et
.size
== 64)
15872 do_vfp_nsyn_opcode ("fcpyd");
15875 /* fall through. */
15877 case NS_QQ
: /* case 0/1. */
15879 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15881 /* The architecture manual I have doesn't explicitly state which
15882 value the U bit should have for register->register moves, but
15883 the equivalent VORR instruction has U = 0, so do that. */
15884 inst
.instruction
= 0x0200110;
15885 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15886 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15887 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15888 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15889 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15890 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15891 inst
.instruction
|= neon_quad (rs
) << 6;
15893 neon_dp_fixup (&inst
);
15897 case NS_DI
: /* case 3/11. */
15898 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15900 if (et
.type
== NT_float
&& et
.size
== 64)
15902 /* case 11 (fconstd). */
15903 ldconst
= "fconstd";
15904 goto encode_fconstd
;
15906 /* fall through. */
15908 case NS_QI
: /* case 2/3. */
15909 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15911 inst
.instruction
= 0x0800010;
15912 neon_move_immediate ();
15913 neon_dp_fixup (&inst
);
15916 case NS_SR
: /* case 4. */
15918 unsigned bcdebits
= 0;
15920 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
15921 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
15923 /* .<size> is optional here, defaulting to .32. */
15924 if (inst
.vectype
.elems
== 0
15925 && inst
.operands
[0].vectype
.type
== NT_invtype
15926 && inst
.operands
[1].vectype
.type
== NT_invtype
)
15928 inst
.vectype
.el
[0].type
= NT_untyped
;
15929 inst
.vectype
.el
[0].size
= 32;
15930 inst
.vectype
.elems
= 1;
15933 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15934 logsize
= neon_logbits (et
.size
);
15936 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
15938 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
15939 && et
.size
!= 32, _(BAD_FPU
));
15940 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
15941 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
15945 case 8: bcdebits
= 0x8; break;
15946 case 16: bcdebits
= 0x1; break;
15947 case 32: bcdebits
= 0x0; break;
15951 bcdebits
|= x
<< logsize
;
15953 inst
.instruction
= 0xe000b10;
15954 do_vfp_cond_or_thumb ();
15955 inst
.instruction
|= LOW4 (dn
) << 16;
15956 inst
.instruction
|= HI1 (dn
) << 7;
15957 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15958 inst
.instruction
|= (bcdebits
& 3) << 5;
15959 inst
.instruction
|= (bcdebits
>> 2) << 21;
15963 case NS_DRR
: /* case 5 (fmdrr). */
15964 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
15967 inst
.instruction
= 0xc400b10;
15968 do_vfp_cond_or_thumb ();
15969 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
15970 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
15971 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15972 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
15975 case NS_RS
: /* case 6. */
15978 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
15979 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
15980 unsigned abcdebits
= 0;
15982 /* .<dt> is optional here, defaulting to .32. */
15983 if (inst
.vectype
.elems
== 0
15984 && inst
.operands
[0].vectype
.type
== NT_invtype
15985 && inst
.operands
[1].vectype
.type
== NT_invtype
)
15987 inst
.vectype
.el
[0].type
= NT_untyped
;
15988 inst
.vectype
.el
[0].size
= 32;
15989 inst
.vectype
.elems
= 1;
15992 et
= neon_check_type (2, NS_NULL
,
15993 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
15994 logsize
= neon_logbits (et
.size
);
15996 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
15998 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
15999 && et
.size
!= 32, _(BAD_FPU
));
16000 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16001 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16005 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16006 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16007 case 32: abcdebits
= 0x00; break;
16011 abcdebits
|= x
<< logsize
;
16012 inst
.instruction
= 0xe100b10;
16013 do_vfp_cond_or_thumb ();
16014 inst
.instruction
|= LOW4 (dn
) << 16;
16015 inst
.instruction
|= HI1 (dn
) << 7;
16016 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16017 inst
.instruction
|= (abcdebits
& 3) << 5;
16018 inst
.instruction
|= (abcdebits
>> 2) << 21;
16022 case NS_RRD
: /* case 7 (fmrrd). */
16023 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16026 inst
.instruction
= 0xc500b10;
16027 do_vfp_cond_or_thumb ();
16028 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16029 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16030 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16031 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16034 case NS_FF
: /* case 8 (fcpys). */
16035 do_vfp_nsyn_opcode ("fcpys");
16038 case NS_FI
: /* case 10 (fconsts). */
16039 ldconst
= "fconsts";
16041 if (is_quarter_float (inst
.operands
[1].imm
))
16043 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16044 do_vfp_nsyn_opcode (ldconst
);
16047 first_error (_("immediate out of range"));
16050 case NS_RF
: /* case 12 (fmrs). */
16051 do_vfp_nsyn_opcode ("fmrs");
16054 case NS_FR
: /* case 13 (fmsr). */
16055 do_vfp_nsyn_opcode ("fmsr");
16058 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16059 (one of which is a list), but we have parsed four. Do some fiddling to
16060 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16062 case NS_RRFF
: /* case 14 (fmrrs). */
16063 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16064 _("VFP registers must be adjacent"));
16065 inst
.operands
[2].imm
= 2;
16066 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16067 do_vfp_nsyn_opcode ("fmrrs");
16070 case NS_FFRR
: /* case 15 (fmsrr). */
16071 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16072 _("VFP registers must be adjacent"));
16073 inst
.operands
[1] = inst
.operands
[2];
16074 inst
.operands
[2] = inst
.operands
[3];
16075 inst
.operands
[0].imm
= 2;
16076 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16077 do_vfp_nsyn_opcode ("fmsrr");
16081 /* neon_select_shape has determined that the instruction
16082 shape is wrong and has already set the error message. */
16091 do_neon_rshift_round_imm (void)
16093 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16094 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16095 int imm
= inst
.operands
[2].imm
;
16097 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16100 inst
.operands
[2].present
= 0;
16105 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16106 _("immediate out of range for shift"));
16107 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16112 do_neon_movl (void)
16114 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16115 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16116 unsigned sizebits
= et
.size
>> 3;
16117 inst
.instruction
|= sizebits
<< 19;
16118 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16124 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16125 struct neon_type_el et
= neon_check_type (2, rs
,
16126 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16127 NEON_ENCODE (INTEGER
, inst
);
16128 neon_two_same (neon_quad (rs
), 1, et
.size
);
16132 do_neon_zip_uzp (void)
16134 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16135 struct neon_type_el et
= neon_check_type (2, rs
,
16136 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16137 if (rs
== NS_DD
&& et
.size
== 32)
16139 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16140 inst
.instruction
= N_MNEM_vtrn
;
16144 neon_two_same (neon_quad (rs
), 1, et
.size
);
16148 do_neon_sat_abs_neg (void)
16150 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16151 struct neon_type_el et
= neon_check_type (2, rs
,
16152 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16153 neon_two_same (neon_quad (rs
), 1, et
.size
);
16157 do_neon_pair_long (void)
16159 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16160 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16161 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16162 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16163 neon_two_same (neon_quad (rs
), 1, et
.size
);
16167 do_neon_recip_est (void)
16169 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16170 struct neon_type_el et
= neon_check_type (2, rs
,
16171 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
16172 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16173 neon_two_same (neon_quad (rs
), 1, et
.size
);
16179 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16180 struct neon_type_el et
= neon_check_type (2, rs
,
16181 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16182 neon_two_same (neon_quad (rs
), 1, et
.size
);
16188 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16189 struct neon_type_el et
= neon_check_type (2, rs
,
16190 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16191 neon_two_same (neon_quad (rs
), 1, et
.size
);
16197 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16198 struct neon_type_el et
= neon_check_type (2, rs
,
16199 N_EQK
| N_INT
, N_8
| N_KEY
);
16200 neon_two_same (neon_quad (rs
), 1, et
.size
);
16206 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16207 neon_two_same (neon_quad (rs
), 1, -1);
16211 do_neon_tbl_tbx (void)
16213 unsigned listlenbits
;
16214 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16216 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16218 first_error (_("bad list length for table lookup"));
16222 listlenbits
= inst
.operands
[1].imm
- 1;
16223 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16224 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16225 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16226 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16227 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16228 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16229 inst
.instruction
|= listlenbits
<< 8;
16231 neon_dp_fixup (&inst
);
16235 do_neon_ldm_stm (void)
16237 /* P, U and L bits are part of bitmask. */
16238 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16239 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16241 if (inst
.operands
[1].issingle
)
16243 do_vfp_nsyn_ldm_stm (is_dbmode
);
16247 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16248 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16250 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16251 _("register list must contain at least 1 and at most 16 "
16254 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16255 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16256 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16257 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16259 inst
.instruction
|= offsetbits
;
16261 do_vfp_cond_or_thumb ();
16265 do_neon_ldr_str (void)
16267 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16269 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16270 And is UNPREDICTABLE in thumb mode. */
16272 && inst
.operands
[1].reg
== REG_PC
16273 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16276 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16277 else if (warn_on_deprecated
)
16278 as_tsktsk (_("Use of PC here is deprecated"));
16281 if (inst
.operands
[0].issingle
)
16284 do_vfp_nsyn_opcode ("flds");
16286 do_vfp_nsyn_opcode ("fsts");
16291 do_vfp_nsyn_opcode ("fldd");
16293 do_vfp_nsyn_opcode ("fstd");
16297 /* "interleave" version also handles non-interleaving register VLD1/VST1
16301 do_neon_ld_st_interleave (void)
16303 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16304 N_8
| N_16
| N_32
| N_64
);
16305 unsigned alignbits
= 0;
16307 /* The bits in this table go:
16308 0: register stride of one (0) or two (1)
16309 1,2: register list length, minus one (1, 2, 3, 4).
16310 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16311 We use -1 for invalid entries. */
16312 const int typetable
[] =
16314 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16315 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16316 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16317 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16321 if (et
.type
== NT_invtype
)
16324 if (inst
.operands
[1].immisalign
)
16325 switch (inst
.operands
[1].imm
>> 8)
16327 case 64: alignbits
= 1; break;
16329 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16330 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16331 goto bad_alignment
;
16335 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16336 goto bad_alignment
;
16341 first_error (_("bad alignment"));
16345 inst
.instruction
|= alignbits
<< 4;
16346 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16348 /* Bits [4:6] of the immediate in a list specifier encode register stride
16349 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16350 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16351 up the right value for "type" in a table based on this value and the given
16352 list style, then stick it back. */
16353 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16354 | (((inst
.instruction
>> 8) & 3) << 3);
16356 typebits
= typetable
[idx
];
16358 constraint (typebits
== -1, _("bad list type for instruction"));
16359 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16360 _("bad element type for instruction"));
16362 inst
.instruction
&= ~0xf00;
16363 inst
.instruction
|= typebits
<< 8;
16366 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16367 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16368 otherwise. The variable arguments are a list of pairs of legal (size, align)
16369 values, terminated with -1. */
16372 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
16375 int result
= FAIL
, thissize
, thisalign
;
16377 if (!inst
.operands
[1].immisalign
)
16383 va_start (ap
, do_align
);
16387 thissize
= va_arg (ap
, int);
16388 if (thissize
== -1)
16390 thisalign
= va_arg (ap
, int);
16392 if (size
== thissize
&& align
== thisalign
)
16395 while (result
!= SUCCESS
);
16399 if (result
== SUCCESS
)
16402 first_error (_("unsupported alignment for instruction"));
16408 do_neon_ld_st_lane (void)
16410 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16411 int align_good
, do_align
= 0;
16412 int logsize
= neon_logbits (et
.size
);
16413 int align
= inst
.operands
[1].imm
>> 8;
16414 int n
= (inst
.instruction
>> 8) & 3;
16415 int max_el
= 64 / et
.size
;
16417 if (et
.type
== NT_invtype
)
16420 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16421 _("bad list length"));
16422 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16423 _("scalar index out of range"));
16424 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16426 _("stride of 2 unavailable when element size is 8"));
16430 case 0: /* VLD1 / VST1. */
16431 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
16433 if (align_good
== FAIL
)
16437 unsigned alignbits
= 0;
16440 case 16: alignbits
= 0x1; break;
16441 case 32: alignbits
= 0x3; break;
16444 inst
.instruction
|= alignbits
<< 4;
16448 case 1: /* VLD2 / VST2. */
16449 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
16451 if (align_good
== FAIL
)
16454 inst
.instruction
|= 1 << 4;
16457 case 2: /* VLD3 / VST3. */
16458 constraint (inst
.operands
[1].immisalign
,
16459 _("can't use alignment with this instruction"));
16462 case 3: /* VLD4 / VST4. */
16463 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16464 16, 64, 32, 64, 32, 128, -1);
16465 if (align_good
== FAIL
)
16469 unsigned alignbits
= 0;
16472 case 8: alignbits
= 0x1; break;
16473 case 16: alignbits
= 0x1; break;
16474 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16477 inst
.instruction
|= alignbits
<< 4;
16484 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16485 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16486 inst
.instruction
|= 1 << (4 + logsize
);
16488 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16489 inst
.instruction
|= logsize
<< 10;
16492 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16495 do_neon_ld_dup (void)
16497 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16498 int align_good
, do_align
= 0;
16500 if (et
.type
== NT_invtype
)
16503 switch ((inst
.instruction
>> 8) & 3)
16505 case 0: /* VLD1. */
16506 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16507 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16508 &do_align
, 16, 16, 32, 32, -1);
16509 if (align_good
== FAIL
)
16511 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16514 case 2: inst
.instruction
|= 1 << 5; break;
16515 default: first_error (_("bad list length")); return;
16517 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16520 case 1: /* VLD2. */
16521 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16522 &do_align
, 8, 16, 16, 32, 32, 64, -1);
16523 if (align_good
== FAIL
)
16525 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
16526 _("bad list length"));
16527 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16528 inst
.instruction
|= 1 << 5;
16529 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16532 case 2: /* VLD3. */
16533 constraint (inst
.operands
[1].immisalign
,
16534 _("can't use alignment with this instruction"));
16535 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
16536 _("bad list length"));
16537 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16538 inst
.instruction
|= 1 << 5;
16539 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16542 case 3: /* VLD4. */
16544 int align
= inst
.operands
[1].imm
>> 8;
16545 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16546 16, 64, 32, 64, 32, 128, -1);
16547 if (align_good
== FAIL
)
16549 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
16550 _("bad list length"));
16551 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16552 inst
.instruction
|= 1 << 5;
16553 if (et
.size
== 32 && align
== 128)
16554 inst
.instruction
|= 0x3 << 6;
16556 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16563 inst
.instruction
|= do_align
<< 4;
16566 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16567 apart from bits [11:4]. */
16570 do_neon_ldx_stx (void)
16572 if (inst
.operands
[1].isreg
)
16573 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16575 switch (NEON_LANE (inst
.operands
[0].imm
))
16577 case NEON_INTERLEAVE_LANES
:
16578 NEON_ENCODE (INTERLV
, inst
);
16579 do_neon_ld_st_interleave ();
16582 case NEON_ALL_LANES
:
16583 NEON_ENCODE (DUP
, inst
);
16584 if (inst
.instruction
== N_INV
)
16586 first_error ("only loads support such operands");
16593 NEON_ENCODE (LANE
, inst
);
16594 do_neon_ld_st_lane ();
16597 /* L bit comes from bit mask. */
16598 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16599 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16600 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16602 if (inst
.operands
[1].postind
)
16604 int postreg
= inst
.operands
[1].imm
& 0xf;
16605 constraint (!inst
.operands
[1].immisreg
,
16606 _("post-index must be a register"));
16607 constraint (postreg
== 0xd || postreg
== 0xf,
16608 _("bad register for post-index"));
16609 inst
.instruction
|= postreg
;
16613 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16614 constraint (inst
.reloc
.exp
.X_op
!= O_constant
16615 || inst
.reloc
.exp
.X_add_number
!= 0,
16618 if (inst
.operands
[1].writeback
)
16620 inst
.instruction
|= 0xd;
16623 inst
.instruction
|= 0xf;
16627 inst
.instruction
|= 0xf9000000;
16629 inst
.instruction
|= 0xf4000000;
16634 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
16636 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16637 D register operands. */
16638 if (neon_shape_class
[rs
] == SC_DOUBLE
)
16639 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16642 NEON_ENCODE (FPV8
, inst
);
16645 do_vfp_sp_dyadic ();
16647 do_vfp_dp_rd_rn_rm ();
16650 inst
.instruction
|= 0x100;
16652 inst
.instruction
|= 0xf0000000;
16658 set_it_insn_type (OUTSIDE_IT_INSN
);
16660 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
16661 first_error (_("invalid instruction shape"));
16667 set_it_insn_type (OUTSIDE_IT_INSN
);
16669 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
16672 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16675 neon_dyadic_misc (NT_untyped
, N_F32
, 0);
16679 do_vrint_1 (enum neon_cvt_mode mode
)
16681 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
16682 struct neon_type_el et
;
16687 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16688 D register operands. */
16689 if (neon_shape_class
[rs
] == SC_DOUBLE
)
16690 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16693 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
16694 if (et
.type
!= NT_invtype
)
16696 /* VFP encodings. */
16697 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
16698 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
16699 set_it_insn_type (OUTSIDE_IT_INSN
);
16701 NEON_ENCODE (FPV8
, inst
);
16703 do_vfp_sp_monadic ();
16705 do_vfp_dp_rd_rm ();
16709 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
16710 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
16711 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
16712 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
16713 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
16714 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
16715 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
16719 inst
.instruction
|= (rs
== NS_DD
) << 8;
16720 do_vfp_cond_or_thumb ();
16724 /* Neon encodings (or something broken...). */
16726 et
= neon_check_type (2, rs
, N_EQK
, N_F32
| N_KEY
);
16728 if (et
.type
== NT_invtype
)
16731 set_it_insn_type (OUTSIDE_IT_INSN
);
16732 NEON_ENCODE (FLOAT
, inst
);
16734 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16737 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16738 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16739 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16740 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16741 inst
.instruction
|= neon_quad (rs
) << 6;
16744 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
16745 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
16746 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
16747 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
16748 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
16749 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
16750 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
16755 inst
.instruction
|= 0xfc000000;
16757 inst
.instruction
|= 0xf0000000;
16764 do_vrint_1 (neon_cvt_mode_x
);
16770 do_vrint_1 (neon_cvt_mode_z
);
16776 do_vrint_1 (neon_cvt_mode_r
);
16782 do_vrint_1 (neon_cvt_mode_a
);
16788 do_vrint_1 (neon_cvt_mode_n
);
16794 do_vrint_1 (neon_cvt_mode_p
);
16800 do_vrint_1 (neon_cvt_mode_m
);
16803 /* Crypto v1 instructions. */
16805 do_crypto_2op_1 (unsigned elttype
, int op
)
16807 set_it_insn_type (OUTSIDE_IT_INSN
);
16809 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
16815 NEON_ENCODE (INTEGER
, inst
);
16816 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16817 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16818 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16819 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16821 inst
.instruction
|= op
<< 6;
16824 inst
.instruction
|= 0xfc000000;
16826 inst
.instruction
|= 0xf0000000;
16830 do_crypto_3op_1 (int u
, int op
)
16832 set_it_insn_type (OUTSIDE_IT_INSN
);
16834 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
16835 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
16840 NEON_ENCODE (INTEGER
, inst
);
16841 neon_three_same (1, u
, 8 << op
);
16847 do_crypto_2op_1 (N_8
, 0);
16853 do_crypto_2op_1 (N_8
, 1);
16859 do_crypto_2op_1 (N_8
, 2);
16865 do_crypto_2op_1 (N_8
, 3);
16871 do_crypto_3op_1 (0, 0);
16877 do_crypto_3op_1 (0, 1);
16883 do_crypto_3op_1 (0, 2);
16889 do_crypto_3op_1 (0, 3);
16895 do_crypto_3op_1 (1, 0);
16901 do_crypto_3op_1 (1, 1);
16905 do_sha256su1 (void)
16907 do_crypto_3op_1 (1, 2);
16913 do_crypto_2op_1 (N_32
, -1);
16919 do_crypto_2op_1 (N_32
, 0);
16923 do_sha256su0 (void)
16925 do_crypto_2op_1 (N_32
, 1);
16929 do_crc32_1 (unsigned int poly
, unsigned int sz
)
16931 unsigned int Rd
= inst
.operands
[0].reg
;
16932 unsigned int Rn
= inst
.operands
[1].reg
;
16933 unsigned int Rm
= inst
.operands
[2].reg
;
16935 set_it_insn_type (OUTSIDE_IT_INSN
);
16936 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
16937 inst
.instruction
|= LOW4 (Rn
) << 16;
16938 inst
.instruction
|= LOW4 (Rm
);
16939 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
16940 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
16942 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
16943 as_warn (UNPRED_REG ("r15"));
16944 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
16945 as_warn (UNPRED_REG ("r13"));
16985 /* Overall per-instruction processing. */
16987 /* We need to be able to fix up arbitrary expressions in some statements.
16988 This is so that we can handle symbols that are an arbitrary distance from
16989 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
16990 which returns part of an address in a form which will be valid for
16991 a data instruction. We do this by pushing the expression into a symbol
16992 in the expr_section, and creating a fix for that. */
16995 fix_new_arm (fragS
* frag
,
17009 /* Create an absolute valued symbol, so we have something to
17010 refer to in the object file. Unfortunately for us, gas's
17011 generic expression parsing will already have folded out
17012 any use of .set foo/.type foo %function that may have
17013 been used to set type information of the target location,
17014 that's being specified symbolically. We have to presume
17015 the user knows what they are doing. */
17019 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17021 symbol
= symbol_find_or_make (name
);
17022 S_SET_SEGMENT (symbol
, absolute_section
);
17023 symbol_set_frag (symbol
, &zero_address_frag
);
17024 S_SET_VALUE (symbol
, exp
->X_add_number
);
17025 exp
->X_op
= O_symbol
;
17026 exp
->X_add_symbol
= symbol
;
17027 exp
->X_add_number
= 0;
17033 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17034 (enum bfd_reloc_code_real
) reloc
);
17038 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17039 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17043 /* Mark whether the fix is to a THUMB instruction, or an ARM
17045 new_fix
->tc_fix_data
= thumb_mode
;
17048 /* Create a frg for an instruction requiring relaxation. */
17050 output_relax_insn (void)
17056 /* The size of the instruction is unknown, so tie the debug info to the
17057 start of the instruction. */
17058 dwarf2_emit_insn (0);
17060 switch (inst
.reloc
.exp
.X_op
)
17063 sym
= inst
.reloc
.exp
.X_add_symbol
;
17064 offset
= inst
.reloc
.exp
.X_add_number
;
17068 offset
= inst
.reloc
.exp
.X_add_number
;
17071 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17075 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17076 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17077 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17080 /* Write a 32-bit thumb instruction to buf. */
17082 put_thumb32_insn (char * buf
, unsigned long insn
)
17084 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17085 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17089 output_inst (const char * str
)
17095 as_bad ("%s -- `%s'", inst
.error
, str
);
17100 output_relax_insn ();
17103 if (inst
.size
== 0)
17106 to
= frag_more (inst
.size
);
17107 /* PR 9814: Record the thumb mode into the current frag so that we know
17108 what type of NOP padding to use, if necessary. We override any previous
17109 setting so that if the mode has changed then the NOPS that we use will
17110 match the encoding of the last instruction in the frag. */
17111 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17113 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17115 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17116 put_thumb32_insn (to
, inst
.instruction
);
17118 else if (inst
.size
> INSN_SIZE
)
17120 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17121 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17122 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17125 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17127 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17128 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17129 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17132 dwarf2_emit_insn (inst
.size
);
17136 output_it_inst (int cond
, int mask
, char * to
)
17138 unsigned long instruction
= 0xbf00;
17141 instruction
|= mask
;
17142 instruction
|= cond
<< 4;
17146 to
= frag_more (2);
17148 dwarf2_emit_insn (2);
17152 md_number_to_chars (to
, instruction
, 2);
17157 /* Tag values used in struct asm_opcode's tag field. */
17160 OT_unconditional
, /* Instruction cannot be conditionalized.
17161 The ARM condition field is still 0xE. */
17162 OT_unconditionalF
, /* Instruction cannot be conditionalized
17163 and carries 0xF in its ARM condition field. */
17164 OT_csuffix
, /* Instruction takes a conditional suffix. */
17165 OT_csuffixF
, /* Some forms of the instruction take a conditional
17166 suffix, others place 0xF where the condition field
17168 OT_cinfix3
, /* Instruction takes a conditional infix,
17169 beginning at character index 3. (In
17170 unified mode, it becomes a suffix.) */
17171 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
17172 tsts, cmps, cmns, and teqs. */
17173 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
17174 character index 3, even in unified mode. Used for
17175 legacy instructions where suffix and infix forms
17176 may be ambiguous. */
17177 OT_csuf_or_in3
, /* Instruction takes either a conditional
17178 suffix or an infix at character index 3. */
17179 OT_odd_infix_unc
, /* This is the unconditional variant of an
17180 instruction that takes a conditional infix
17181 at an unusual position. In unified mode,
17182 this variant will accept a suffix. */
17183 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17184 are the conditional variants of instructions that
17185 take conditional infixes in unusual positions.
17186 The infix appears at character index
17187 (tag - OT_odd_infix_0). These are not accepted
17188 in unified mode. */
17191 /* Subroutine of md_assemble, responsible for looking up the primary
17192 opcode from the mnemonic the user wrote. STR points to the
17193 beginning of the mnemonic.
17195 This is not simply a hash table lookup, because of conditional
17196 variants. Most instructions have conditional variants, which are
17197 expressed with a _conditional affix_ to the mnemonic. If we were
17198 to encode each conditional variant as a literal string in the opcode
17199 table, it would have approximately 20,000 entries.
17201 Most mnemonics take this affix as a suffix, and in unified syntax,
17202 'most' is upgraded to 'all'. However, in the divided syntax, some
17203 instructions take the affix as an infix, notably the s-variants of
17204 the arithmetic instructions. Of those instructions, all but six
17205 have the infix appear after the third character of the mnemonic.
17207 Accordingly, the algorithm for looking up primary opcodes given
17210 1. Look up the identifier in the opcode table.
17211 If we find a match, go to step U.
17213 2. Look up the last two characters of the identifier in the
17214 conditions table. If we find a match, look up the first N-2
17215 characters of the identifier in the opcode table. If we
17216 find a match, go to step CE.
17218 3. Look up the fourth and fifth characters of the identifier in
17219 the conditions table. If we find a match, extract those
17220 characters from the identifier, and look up the remaining
17221 characters in the opcode table. If we find a match, go
17226 U. Examine the tag field of the opcode structure, in case this is
17227 one of the six instructions with its conditional infix in an
17228 unusual place. If it is, the tag tells us where to find the
17229 infix; look it up in the conditions table and set inst.cond
17230 accordingly. Otherwise, this is an unconditional instruction.
17231 Again set inst.cond accordingly. Return the opcode structure.
17233 CE. Examine the tag field to make sure this is an instruction that
17234 should receive a conditional suffix. If it is not, fail.
17235 Otherwise, set inst.cond from the suffix we already looked up,
17236 and return the opcode structure.
17238 CM. Examine the tag field to make sure this is an instruction that
17239 should receive a conditional infix after the third character.
17240 If it is not, fail. Otherwise, undo the edits to the current
17241 line of input and proceed as for case CE. */
17243 static const struct asm_opcode
*
17244 opcode_lookup (char **str
)
17248 const struct asm_opcode
*opcode
;
17249 const struct asm_cond
*cond
;
17252 /* Scan up to the end of the mnemonic, which must end in white space,
17253 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17254 for (base
= end
= *str
; *end
!= '\0'; end
++)
17255 if (*end
== ' ' || *end
== '.')
17261 /* Handle a possible width suffix and/or Neon type suffix. */
17266 /* The .w and .n suffixes are only valid if the unified syntax is in
17268 if (unified_syntax
&& end
[1] == 'w')
17270 else if (unified_syntax
&& end
[1] == 'n')
17275 inst
.vectype
.elems
= 0;
17277 *str
= end
+ offset
;
17279 if (end
[offset
] == '.')
17281 /* See if we have a Neon type suffix (possible in either unified or
17282 non-unified ARM syntax mode). */
17283 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17286 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17292 /* Look for unaffixed or special-case affixed mnemonic. */
17293 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17298 if (opcode
->tag
< OT_odd_infix_0
)
17300 inst
.cond
= COND_ALWAYS
;
17304 if (warn_on_deprecated
&& unified_syntax
)
17305 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17306 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17307 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17310 inst
.cond
= cond
->value
;
17314 /* Cannot have a conditional suffix on a mnemonic of less than two
17316 if (end
- base
< 3)
17319 /* Look for suffixed mnemonic. */
17321 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17322 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17324 if (opcode
&& cond
)
17327 switch (opcode
->tag
)
17329 case OT_cinfix3_legacy
:
17330 /* Ignore conditional suffixes matched on infix only mnemonics. */
17334 case OT_cinfix3_deprecated
:
17335 case OT_odd_infix_unc
:
17336 if (!unified_syntax
)
17338 /* else fall through */
17342 case OT_csuf_or_in3
:
17343 inst
.cond
= cond
->value
;
17346 case OT_unconditional
:
17347 case OT_unconditionalF
:
17349 inst
.cond
= cond
->value
;
17352 /* Delayed diagnostic. */
17353 inst
.error
= BAD_COND
;
17354 inst
.cond
= COND_ALWAYS
;
17363 /* Cannot have a usual-position infix on a mnemonic of less than
17364 six characters (five would be a suffix). */
17365 if (end
- base
< 6)
17368 /* Look for infixed mnemonic in the usual position. */
17370 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17374 memcpy (save
, affix
, 2);
17375 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
17376 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17378 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
17379 memcpy (affix
, save
, 2);
17382 && (opcode
->tag
== OT_cinfix3
17383 || opcode
->tag
== OT_cinfix3_deprecated
17384 || opcode
->tag
== OT_csuf_or_in3
17385 || opcode
->tag
== OT_cinfix3_legacy
))
17388 if (warn_on_deprecated
&& unified_syntax
17389 && (opcode
->tag
== OT_cinfix3
17390 || opcode
->tag
== OT_cinfix3_deprecated
))
17391 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17393 inst
.cond
= cond
->value
;
17400 /* This function generates an initial IT instruction, leaving its block
17401 virtually open for the new instructions. Eventually,
17402 the mask will be updated by now_it_add_mask () each time
17403 a new instruction needs to be included in the IT block.
17404 Finally, the block is closed with close_automatic_it_block ().
17405 The block closure can be requested either from md_assemble (),
17406 a tencode (), or due to a label hook. */
17409 new_automatic_it_block (int cond
)
17411 now_it
.state
= AUTOMATIC_IT_BLOCK
;
17412 now_it
.mask
= 0x18;
17414 now_it
.block_length
= 1;
17415 mapping_state (MAP_THUMB
);
17416 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
17417 now_it
.warn_deprecated
= FALSE
;
17418 now_it
.insn_cond
= TRUE
;
17421 /* Close an automatic IT block.
17422 See comments in new_automatic_it_block (). */
17425 close_automatic_it_block (void)
17427 now_it
.mask
= 0x10;
17428 now_it
.block_length
= 0;
17431 /* Update the mask of the current automatically-generated IT
17432 instruction. See comments in new_automatic_it_block (). */
17435 now_it_add_mask (int cond
)
17437 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17438 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17439 | ((bitvalue) << (nbit)))
17440 const int resulting_bit
= (cond
& 1);
17442 now_it
.mask
&= 0xf;
17443 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17445 (5 - now_it
.block_length
));
17446 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17448 ((5 - now_it
.block_length
) - 1) );
17449 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
17452 #undef SET_BIT_VALUE
17455 /* The IT blocks handling machinery is accessed through the these functions:
17456 it_fsm_pre_encode () from md_assemble ()
17457 set_it_insn_type () optional, from the tencode functions
17458 set_it_insn_type_last () ditto
17459 in_it_block () ditto
17460 it_fsm_post_encode () from md_assemble ()
17461 force_automatic_it_block_close () from label habdling functions
17464 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
17465 initializing the IT insn type with a generic initial value depending
17466 on the inst.condition.
17467 2) During the tencode function, two things may happen:
17468 a) The tencode function overrides the IT insn type by
17469 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17470 b) The tencode function queries the IT block state by
17471 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17473 Both set_it_insn_type and in_it_block run the internal FSM state
17474 handling function (handle_it_state), because: a) setting the IT insn
17475 type may incur in an invalid state (exiting the function),
17476 and b) querying the state requires the FSM to be updated.
17477 Specifically we want to avoid creating an IT block for conditional
17478 branches, so it_fsm_pre_encode is actually a guess and we can't
17479 determine whether an IT block is required until the tencode () routine
17480 has decided what type of instruction this actually it.
17481 Because of this, if set_it_insn_type and in_it_block have to be used,
17482 set_it_insn_type has to be called first.
17484 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17485 determines the insn IT type depending on the inst.cond code.
17486 When a tencode () routine encodes an instruction that can be
17487 either outside an IT block, or, in the case of being inside, has to be
17488 the last one, set_it_insn_type_last () will determine the proper
17489 IT instruction type based on the inst.cond code. Otherwise,
17490 set_it_insn_type can be called for overriding that logic or
17491 for covering other cases.
17493 Calling handle_it_state () may not transition the IT block state to
17494 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17495 still queried. Instead, if the FSM determines that the state should
17496 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17497 after the tencode () function: that's what it_fsm_post_encode () does.
17499 Since in_it_block () calls the state handling function to get an
17500 updated state, an error may occur (due to invalid insns combination).
17501 In that case, inst.error is set.
17502 Therefore, inst.error has to be checked after the execution of
17503 the tencode () routine.
17505 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
17506 any pending state change (if any) that didn't take place in
17507 handle_it_state () as explained above. */
17510 it_fsm_pre_encode (void)
17512 if (inst
.cond
!= COND_ALWAYS
)
17513 inst
.it_insn_type
= INSIDE_IT_INSN
;
17515 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
17517 now_it
.state_handled
= 0;
17520 /* IT state FSM handling function. */
17523 handle_it_state (void)
17525 now_it
.state_handled
= 1;
17526 now_it
.insn_cond
= FALSE
;
17528 switch (now_it
.state
)
17530 case OUTSIDE_IT_BLOCK
:
17531 switch (inst
.it_insn_type
)
17533 case OUTSIDE_IT_INSN
:
17536 case INSIDE_IT_INSN
:
17537 case INSIDE_IT_LAST_INSN
:
17538 if (thumb_mode
== 0)
17541 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
17542 as_tsktsk (_("Warning: conditional outside an IT block"\
17547 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
17548 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
17550 /* Automatically generate the IT instruction. */
17551 new_automatic_it_block (inst
.cond
);
17552 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
17553 close_automatic_it_block ();
17557 inst
.error
= BAD_OUT_IT
;
17563 case IF_INSIDE_IT_LAST_INSN
:
17564 case NEUTRAL_IT_INSN
:
17568 now_it
.state
= MANUAL_IT_BLOCK
;
17569 now_it
.block_length
= 0;
17574 case AUTOMATIC_IT_BLOCK
:
17575 /* Three things may happen now:
17576 a) We should increment current it block size;
17577 b) We should close current it block (closing insn or 4 insns);
17578 c) We should close current it block and start a new one (due
17579 to incompatible conditions or
17580 4 insns-length block reached). */
17582 switch (inst
.it_insn_type
)
17584 case OUTSIDE_IT_INSN
:
17585 /* The closure of the block shall happen immediatelly,
17586 so any in_it_block () call reports the block as closed. */
17587 force_automatic_it_block_close ();
17590 case INSIDE_IT_INSN
:
17591 case INSIDE_IT_LAST_INSN
:
17592 case IF_INSIDE_IT_LAST_INSN
:
17593 now_it
.block_length
++;
17595 if (now_it
.block_length
> 4
17596 || !now_it_compatible (inst
.cond
))
17598 force_automatic_it_block_close ();
17599 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
17600 new_automatic_it_block (inst
.cond
);
17604 now_it
.insn_cond
= TRUE
;
17605 now_it_add_mask (inst
.cond
);
17608 if (now_it
.state
== AUTOMATIC_IT_BLOCK
17609 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
17610 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
17611 close_automatic_it_block ();
17614 case NEUTRAL_IT_INSN
:
17615 now_it
.block_length
++;
17616 now_it
.insn_cond
= TRUE
;
17618 if (now_it
.block_length
> 4)
17619 force_automatic_it_block_close ();
17621 now_it_add_mask (now_it
.cc
& 1);
17625 close_automatic_it_block ();
17626 now_it
.state
= MANUAL_IT_BLOCK
;
17631 case MANUAL_IT_BLOCK
:
17633 /* Check conditional suffixes. */
17634 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
17637 now_it
.mask
&= 0x1f;
17638 is_last
= (now_it
.mask
== 0x10);
17639 now_it
.insn_cond
= TRUE
;
17641 switch (inst
.it_insn_type
)
17643 case OUTSIDE_IT_INSN
:
17644 inst
.error
= BAD_NOT_IT
;
17647 case INSIDE_IT_INSN
:
17648 if (cond
!= inst
.cond
)
17650 inst
.error
= BAD_IT_COND
;
17655 case INSIDE_IT_LAST_INSN
:
17656 case IF_INSIDE_IT_LAST_INSN
:
17657 if (cond
!= inst
.cond
)
17659 inst
.error
= BAD_IT_COND
;
17664 inst
.error
= BAD_BRANCH
;
17669 case NEUTRAL_IT_INSN
:
17670 /* The BKPT instruction is unconditional even in an IT block. */
17674 inst
.error
= BAD_IT_IT
;
17684 struct depr_insn_mask
17686 unsigned long pattern
;
17687 unsigned long mask
;
17688 const char* description
;
17691 /* List of 16-bit instruction patterns deprecated in an IT block in
17693 static const struct depr_insn_mask depr_it_insns
[] = {
17694 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
17695 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
17696 { 0xa000, 0xb800, N_("ADR") },
17697 { 0x4800, 0xf800, N_("Literal loads") },
17698 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
17699 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
17700 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
17701 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
17702 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
17707 it_fsm_post_encode (void)
17711 if (!now_it
.state_handled
)
17712 handle_it_state ();
17714 if (now_it
.insn_cond
17715 && !now_it
.warn_deprecated
17716 && warn_on_deprecated
17717 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
17719 if (inst
.instruction
>= 0x10000)
17721 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
17722 "deprecated in ARMv8"));
17723 now_it
.warn_deprecated
= TRUE
;
17727 const struct depr_insn_mask
*p
= depr_it_insns
;
17729 while (p
->mask
!= 0)
17731 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
17733 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
17734 "of the following class are deprecated in ARMv8: "
17735 "%s"), p
->description
);
17736 now_it
.warn_deprecated
= TRUE
;
17744 if (now_it
.block_length
> 1)
17746 as_tsktsk (_("IT blocks containing more than one conditional "
17747 "instruction are deprecated in ARMv8"));
17748 now_it
.warn_deprecated
= TRUE
;
17752 is_last
= (now_it
.mask
== 0x10);
17755 now_it
.state
= OUTSIDE_IT_BLOCK
;
17761 force_automatic_it_block_close (void)
17763 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
17765 close_automatic_it_block ();
17766 now_it
.state
= OUTSIDE_IT_BLOCK
;
17774 if (!now_it
.state_handled
)
17775 handle_it_state ();
17777 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
17781 md_assemble (char *str
)
17784 const struct asm_opcode
* opcode
;
17786 /* Align the previous label if needed. */
17787 if (last_label_seen
!= NULL
)
17789 symbol_set_frag (last_label_seen
, frag_now
);
17790 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
17791 S_SET_SEGMENT (last_label_seen
, now_seg
);
17794 memset (&inst
, '\0', sizeof (inst
));
17795 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
17797 opcode
= opcode_lookup (&p
);
17800 /* It wasn't an instruction, but it might be a register alias of
17801 the form alias .req reg, or a Neon .dn/.qn directive. */
17802 if (! create_register_alias (str
, p
)
17803 && ! create_neon_reg_alias (str
, p
))
17804 as_bad (_("bad instruction `%s'"), str
);
17809 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
17810 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
17812 /* The value which unconditional instructions should have in place of the
17813 condition field. */
17814 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
17818 arm_feature_set variant
;
17820 variant
= cpu_variant
;
17821 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
17822 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
17823 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
17824 /* Check that this instruction is supported for this CPU. */
17825 if (!opcode
->tvariant
17826 || (thumb_mode
== 1
17827 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
17829 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
17832 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
17833 && opcode
->tencode
!= do_t_branch
)
17835 as_bad (_("Thumb does not support conditional execution"));
17839 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
17841 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
17842 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
17843 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
17845 /* Two things are addressed here.
17846 1) Implicit require narrow instructions on Thumb-1.
17847 This avoids relaxation accidentally introducing Thumb-2
17849 2) Reject wide instructions in non Thumb-2 cores. */
17850 if (inst
.size_req
== 0)
17852 else if (inst
.size_req
== 4)
17854 as_bad (_("selected processor does not support `%s' in Thumb-2 mode"), str
);
17860 inst
.instruction
= opcode
->tvalue
;
17862 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
17864 /* Prepare the it_insn_type for those encodings that don't set
17866 it_fsm_pre_encode ();
17868 opcode
->tencode ();
17870 it_fsm_post_encode ();
17873 if (!(inst
.error
|| inst
.relax
))
17875 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
17876 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
17877 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
17879 as_bad (_("cannot honor width suffix -- `%s'"), str
);
17884 /* Something has gone badly wrong if we try to relax a fixed size
17886 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
17888 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17889 *opcode
->tvariant
);
17890 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
17891 set those bits when Thumb-2 32-bit instructions are seen. ie.
17892 anything other than bl/blx and v6-M instructions.
17893 The impact of relaxable instructions will be considered later after we
17894 finish all relaxation. */
17895 if ((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
17896 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
17897 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
17898 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17901 check_neon_suffixes
;
17905 mapping_state (MAP_THUMB
);
17908 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
17912 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
17913 is_bx
= (opcode
->aencode
== do_bx
);
17915 /* Check that this instruction is supported for this CPU. */
17916 if (!(is_bx
&& fix_v4bx
)
17917 && !(opcode
->avariant
&&
17918 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
17920 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
17925 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
17929 inst
.instruction
= opcode
->avalue
;
17930 if (opcode
->tag
== OT_unconditionalF
)
17931 inst
.instruction
|= 0xFU
<< 28;
17933 inst
.instruction
|= inst
.cond
<< 28;
17934 inst
.size
= INSN_SIZE
;
17935 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
17937 it_fsm_pre_encode ();
17938 opcode
->aencode ();
17939 it_fsm_post_encode ();
17941 /* Arm mode bx is marked as both v4T and v5 because it's still required
17942 on a hypothetical non-thumb v5 core. */
17944 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
17946 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
17947 *opcode
->avariant
);
17949 check_neon_suffixes
;
17953 mapping_state (MAP_ARM
);
17958 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
17966 check_it_blocks_finished (void)
17971 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
17972 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
17973 == MANUAL_IT_BLOCK
)
17975 as_warn (_("section '%s' finished with an open IT block."),
17979 if (now_it
.state
== MANUAL_IT_BLOCK
)
17980 as_warn (_("file finished with an open IT block."));
17984 /* Various frobbings of labels and their addresses. */
17987 arm_start_line_hook (void)
17989 last_label_seen
= NULL
;
17993 arm_frob_label (symbolS
* sym
)
17995 last_label_seen
= sym
;
17997 ARM_SET_THUMB (sym
, thumb_mode
);
17999 #if defined OBJ_COFF || defined OBJ_ELF
18000 ARM_SET_INTERWORK (sym
, support_interwork
);
18003 force_automatic_it_block_close ();
18005 /* Note - do not allow local symbols (.Lxxx) to be labelled
18006 as Thumb functions. This is because these labels, whilst
18007 they exist inside Thumb code, are not the entry points for
18008 possible ARM->Thumb calls. Also, these labels can be used
18009 as part of a computed goto or switch statement. eg gcc
18010 can generate code that looks like this:
18012 ldr r2, [pc, .Laaa]
18022 The first instruction loads the address of the jump table.
18023 The second instruction converts a table index into a byte offset.
18024 The third instruction gets the jump address out of the table.
18025 The fourth instruction performs the jump.
18027 If the address stored at .Laaa is that of a symbol which has the
18028 Thumb_Func bit set, then the linker will arrange for this address
18029 to have the bottom bit set, which in turn would mean that the
18030 address computation performed by the third instruction would end
18031 up with the bottom bit set. Since the ARM is capable of unaligned
18032 word loads, the instruction would then load the incorrect address
18033 out of the jump table, and chaos would ensue. */
18034 if (label_is_thumb_function_name
18035 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18036 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18038 /* When the address of a Thumb function is taken the bottom
18039 bit of that address should be set. This will allow
18040 interworking between Arm and Thumb functions to work
18043 THUMB_SET_FUNC (sym
, 1);
18045 label_is_thumb_function_name
= FALSE
;
18048 dwarf2_emit_label (sym
);
18052 arm_data_in_code (void)
18054 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18056 *input_line_pointer
= '/';
18057 input_line_pointer
+= 5;
18058 *input_line_pointer
= 0;
18066 arm_canonicalize_symbol_name (char * name
)
18070 if (thumb_mode
&& (len
= strlen (name
)) > 5
18071 && streq (name
+ len
- 5, "/data"))
18072 *(name
+ len
- 5) = 0;
18077 /* Table of all register names defined by default. The user can
18078 define additional names with .req. Note that all register names
18079 should appear in both upper and lowercase variants. Some registers
18080 also have mixed-case names. */
18082 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18083 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18084 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18085 #define REGSET(p,t) \
18086 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18087 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18088 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18089 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18090 #define REGSETH(p,t) \
18091 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18092 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18093 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18094 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18095 #define REGSET2(p,t) \
18096 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18097 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18098 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18099 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18100 #define SPLRBANK(base,bank,t) \
18101 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18102 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18103 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18104 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18105 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18106 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18108 static const struct reg_entry reg_names
[] =
18110 /* ARM integer registers. */
18111 REGSET(r
, RN
), REGSET(R
, RN
),
18113 /* ATPCS synonyms. */
18114 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
18115 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
18116 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
18118 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
18119 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
18120 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
18122 /* Well-known aliases. */
18123 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
18124 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
18126 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
18127 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
18129 /* Coprocessor numbers. */
18130 REGSET(p
, CP
), REGSET(P
, CP
),
18132 /* Coprocessor register numbers. The "cr" variants are for backward
18134 REGSET(c
, CN
), REGSET(C
, CN
),
18135 REGSET(cr
, CN
), REGSET(CR
, CN
),
18137 /* ARM banked registers. */
18138 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
18139 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
18140 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
18141 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
18142 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
18143 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
18144 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
18146 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
18147 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
18148 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
18149 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
18150 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
18151 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
18152 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
18153 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
18155 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
18156 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
18157 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
18158 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
18159 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
18160 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
18161 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
18162 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18163 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18165 /* FPA registers. */
18166 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
18167 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
18169 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
18170 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
18172 /* VFP SP registers. */
18173 REGSET(s
,VFS
), REGSET(S
,VFS
),
18174 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18176 /* VFP DP Registers. */
18177 REGSET(d
,VFD
), REGSET(D
,VFD
),
18178 /* Extra Neon DP registers. */
18179 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18181 /* Neon QP registers. */
18182 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18184 /* VFP control registers. */
18185 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18186 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18187 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18188 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18189 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18190 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18192 /* Maverick DSP coprocessor registers. */
18193 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18194 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18196 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18197 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18198 REGDEF(dspsc
,0,DSPSC
),
18200 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18201 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18202 REGDEF(DSPSC
,0,DSPSC
),
18204 /* iWMMXt data registers - p0, c0-15. */
18205 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18207 /* iWMMXt control registers - p1, c0-3. */
18208 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18209 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18210 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18211 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18213 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18214 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18215 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18216 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18217 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18219 /* XScale accumulator registers. */
18220 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18226 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18227 within psr_required_here. */
18228 static const struct asm_psr psrs
[] =
18230 /* Backward compatibility notation. Note that "all" is no longer
18231 truly all possible PSR bits. */
18232 {"all", PSR_c
| PSR_f
},
18236 /* Individual flags. */
18242 /* Combinations of flags. */
18243 {"fs", PSR_f
| PSR_s
},
18244 {"fx", PSR_f
| PSR_x
},
18245 {"fc", PSR_f
| PSR_c
},
18246 {"sf", PSR_s
| PSR_f
},
18247 {"sx", PSR_s
| PSR_x
},
18248 {"sc", PSR_s
| PSR_c
},
18249 {"xf", PSR_x
| PSR_f
},
18250 {"xs", PSR_x
| PSR_s
},
18251 {"xc", PSR_x
| PSR_c
},
18252 {"cf", PSR_c
| PSR_f
},
18253 {"cs", PSR_c
| PSR_s
},
18254 {"cx", PSR_c
| PSR_x
},
18255 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18256 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18257 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18258 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18259 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18260 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18261 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18262 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18263 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18264 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18265 {"scf", PSR_s
| PSR_c
| PSR_f
},
18266 {"scx", PSR_s
| PSR_c
| PSR_x
},
18267 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18268 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18269 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18270 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18271 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18272 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18273 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18274 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18275 {"csf", PSR_c
| PSR_s
| PSR_f
},
18276 {"csx", PSR_c
| PSR_s
| PSR_x
},
18277 {"cxf", PSR_c
| PSR_x
| PSR_f
},
18278 {"cxs", PSR_c
| PSR_x
| PSR_s
},
18279 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
18280 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
18281 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
18282 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
18283 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
18284 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
18285 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
18286 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
18287 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
18288 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
18289 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
18290 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
18291 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
18292 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
18293 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
18294 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
18295 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
18296 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
18297 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
18298 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
18299 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
18300 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
18301 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
18302 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
18305 /* Table of V7M psr names. */
18306 static const struct asm_psr v7m_psrs
[] =
18308 {"apsr", 0 }, {"APSR", 0 },
18309 {"iapsr", 1 }, {"IAPSR", 1 },
18310 {"eapsr", 2 }, {"EAPSR", 2 },
18311 {"psr", 3 }, {"PSR", 3 },
18312 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
18313 {"ipsr", 5 }, {"IPSR", 5 },
18314 {"epsr", 6 }, {"EPSR", 6 },
18315 {"iepsr", 7 }, {"IEPSR", 7 },
18316 {"msp", 8 }, {"MSP", 8 },
18317 {"psp", 9 }, {"PSP", 9 },
18318 {"primask", 16}, {"PRIMASK", 16},
18319 {"basepri", 17}, {"BASEPRI", 17},
18320 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
18321 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
18322 {"faultmask", 19}, {"FAULTMASK", 19},
18323 {"control", 20}, {"CONTROL", 20}
18326 /* Table of all shift-in-operand names. */
18327 static const struct asm_shift_name shift_names
[] =
18329 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
18330 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
18331 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
18332 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
18333 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
18334 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
18337 /* Table of all explicit relocation names. */
18339 static struct reloc_entry reloc_names
[] =
18341 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
18342 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
18343 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
18344 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
18345 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
18346 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
18347 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
18348 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
18349 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
18350 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
18351 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
18352 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
18353 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
18354 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
18355 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
18356 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
18357 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
18358 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
18362 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
18363 static const struct asm_cond conds
[] =
18367 {"cs", 0x2}, {"hs", 0x2},
18368 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
18382 #define UL_BARRIER(L,U,CODE,FEAT) \
18383 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
18384 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
18386 static struct asm_barrier_opt barrier_opt_names
[] =
18388 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
18389 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
18390 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
18391 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
18392 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
18393 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
18394 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
18395 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
18396 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
18397 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
18398 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
18399 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
18400 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
18401 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
18402 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
18403 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
18408 /* Table of ARM-format instructions. */
18410 /* Macros for gluing together operand strings. N.B. In all cases
18411 other than OPS0, the trailing OP_stop comes from default
18412 zero-initialization of the unspecified elements of the array. */
18413 #define OPS0() { OP_stop, }
18414 #define OPS1(a) { OP_##a, }
18415 #define OPS2(a,b) { OP_##a,OP_##b, }
18416 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
18417 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
18418 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
18419 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
18421 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
18422 This is useful when mixing operands for ARM and THUMB, i.e. using the
18423 MIX_ARM_THUMB_OPERANDS macro.
18424 In order to use these macros, prefix the number of operands with _
18426 #define OPS_1(a) { a, }
18427 #define OPS_2(a,b) { a,b, }
18428 #define OPS_3(a,b,c) { a,b,c, }
18429 #define OPS_4(a,b,c,d) { a,b,c,d, }
18430 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
18431 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
18433 /* These macros abstract out the exact format of the mnemonic table and
18434 save some repeated characters. */
18436 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18437 #define TxCE(mnem, op, top, nops, ops, ae, te) \
18438 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
18439 THUMB_VARIANT, do_##ae, do_##te }
18441 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18442 a T_MNEM_xyz enumerator. */
18443 #define TCE(mnem, aop, top, nops, ops, ae, te) \
18444 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
18445 #define tCE(mnem, aop, top, nops, ops, ae, te) \
18446 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18448 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18449 infix after the third character. */
18450 #define TxC3(mnem, op, top, nops, ops, ae, te) \
18451 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
18452 THUMB_VARIANT, do_##ae, do_##te }
18453 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
18454 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
18455 THUMB_VARIANT, do_##ae, do_##te }
18456 #define TC3(mnem, aop, top, nops, ops, ae, te) \
18457 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
18458 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
18459 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
18460 #define tC3(mnem, aop, top, nops, ops, ae, te) \
18461 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18462 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
18463 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18465 /* Mnemonic that cannot be conditionalized. The ARM condition-code
18466 field is still 0xE. Many of the Thumb variants can be executed
18467 conditionally, so this is checked separately. */
18468 #define TUE(mnem, op, top, nops, ops, ae, te) \
18469 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18470 THUMB_VARIANT, do_##ae, do_##te }
18472 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18473 Used by mnemonics that have very minimal differences in the encoding for
18474 ARM and Thumb variants and can be handled in a common function. */
18475 #define TUEc(mnem, op, top, nops, ops, en) \
18476 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18477 THUMB_VARIANT, do_##en, do_##en }
18479 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18480 condition code field. */
18481 #define TUF(mnem, op, top, nops, ops, ae, te) \
18482 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
18483 THUMB_VARIANT, do_##ae, do_##te }
18485 /* ARM-only variants of all the above. */
18486 #define CE(mnem, op, nops, ops, ae) \
18487 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18489 #define C3(mnem, op, nops, ops, ae) \
18490 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18492 /* Legacy mnemonics that always have conditional infix after the third
18494 #define CL(mnem, op, nops, ops, ae) \
18495 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18496 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18498 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
18499 #define cCE(mnem, op, nops, ops, ae) \
18500 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18502 /* Legacy coprocessor instructions where conditional infix and conditional
18503 suffix are ambiguous. For consistency this includes all FPA instructions,
18504 not just the potentially ambiguous ones. */
18505 #define cCL(mnem, op, nops, ops, ae) \
18506 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18507 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18509 /* Coprocessor, takes either a suffix or a position-3 infix
18510 (for an FPA corner case). */
18511 #define C3E(mnem, op, nops, ops, ae) \
18512 { mnem, OPS##nops ops, OT_csuf_or_in3, \
18513 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18515 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
18516 { m1 #m2 m3, OPS##nops ops, \
18517 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
18518 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18520 #define CM(m1, m2, op, nops, ops, ae) \
18521 xCM_ (m1, , m2, op, nops, ops, ae), \
18522 xCM_ (m1, eq, m2, op, nops, ops, ae), \
18523 xCM_ (m1, ne, m2, op, nops, ops, ae), \
18524 xCM_ (m1, cs, m2, op, nops, ops, ae), \
18525 xCM_ (m1, hs, m2, op, nops, ops, ae), \
18526 xCM_ (m1, cc, m2, op, nops, ops, ae), \
18527 xCM_ (m1, ul, m2, op, nops, ops, ae), \
18528 xCM_ (m1, lo, m2, op, nops, ops, ae), \
18529 xCM_ (m1, mi, m2, op, nops, ops, ae), \
18530 xCM_ (m1, pl, m2, op, nops, ops, ae), \
18531 xCM_ (m1, vs, m2, op, nops, ops, ae), \
18532 xCM_ (m1, vc, m2, op, nops, ops, ae), \
18533 xCM_ (m1, hi, m2, op, nops, ops, ae), \
18534 xCM_ (m1, ls, m2, op, nops, ops, ae), \
18535 xCM_ (m1, ge, m2, op, nops, ops, ae), \
18536 xCM_ (m1, lt, m2, op, nops, ops, ae), \
18537 xCM_ (m1, gt, m2, op, nops, ops, ae), \
18538 xCM_ (m1, le, m2, op, nops, ops, ae), \
18539 xCM_ (m1, al, m2, op, nops, ops, ae)
18541 #define UE(mnem, op, nops, ops, ae) \
18542 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18544 #define UF(mnem, op, nops, ops, ae) \
18545 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18547 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
18548 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
18549 use the same encoding function for each. */
18550 #define NUF(mnem, op, nops, ops, enc) \
18551 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
18552 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18554 /* Neon data processing, version which indirects through neon_enc_tab for
18555 the various overloaded versions of opcodes. */
18556 #define nUF(mnem, op, nops, ops, enc) \
18557 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
18558 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18560 /* Neon insn with conditional suffix for the ARM version, non-overloaded
18562 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
18563 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
18564 THUMB_VARIANT, do_##enc, do_##enc }
18566 #define NCE(mnem, op, nops, ops, enc) \
18567 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18569 #define NCEF(mnem, op, nops, ops, enc) \
18570 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18572 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
18573 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
18574 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
18575 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18577 #define nCE(mnem, op, nops, ops, enc) \
18578 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18580 #define nCEF(mnem, op, nops, ops, enc) \
18581 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18585 static const struct asm_opcode insns
[] =
18587 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
18588 #define THUMB_VARIANT & arm_ext_v4t
18589 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18590 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18591 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18592 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18593 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18594 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18595 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18596 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18597 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18598 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18599 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18600 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18601 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18602 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18603 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18604 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18606 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
18607 for setting PSR flag bits. They are obsolete in V6 and do not
18608 have Thumb equivalents. */
18609 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18610 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18611 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
18612 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18613 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18614 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
18615 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18616 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18617 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
18619 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
18620 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
18621 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18622 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18624 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
18625 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18626 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
18628 OP_ADDRGLDR
),ldst
, t_ldst
),
18629 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18631 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18632 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18633 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18634 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18635 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18636 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18638 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
18639 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
18640 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
18641 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
18644 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
18645 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
18646 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
18647 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
18649 /* Thumb-compatibility pseudo ops. */
18650 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18651 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18652 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18653 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18654 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18655 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18656 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18657 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18658 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
18659 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
18660 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
18661 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
18663 /* These may simplify to neg. */
18664 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
18665 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
18667 #undef THUMB_VARIANT
18668 #define THUMB_VARIANT & arm_ext_v6
18670 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
18672 /* V1 instructions with no Thumb analogue prior to V6T2. */
18673 #undef THUMB_VARIANT
18674 #define THUMB_VARIANT & arm_ext_v6t2
18676 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18677 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18678 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
18680 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18681 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18682 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
18683 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18685 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18686 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18688 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18689 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18691 /* V1 instructions with no Thumb analogue at all. */
18692 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
18693 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
18695 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18696 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18697 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18698 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18699 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18700 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18701 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18702 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18705 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
18706 #undef THUMB_VARIANT
18707 #define THUMB_VARIANT & arm_ext_v4t
18709 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18710 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18712 #undef THUMB_VARIANT
18713 #define THUMB_VARIANT & arm_ext_v6t2
18715 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
18716 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
18718 /* Generic coprocessor instructions. */
18719 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18720 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18721 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18722 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18723 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18724 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18725 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18728 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
18730 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18731 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18734 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
18735 #undef THUMB_VARIANT
18736 #define THUMB_VARIANT & arm_ext_msr
18738 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
18739 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
18742 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
18743 #undef THUMB_VARIANT
18744 #define THUMB_VARIANT & arm_ext_v6t2
18746 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18747 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18748 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18749 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18750 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18751 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18752 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18753 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18756 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
18757 #undef THUMB_VARIANT
18758 #define THUMB_VARIANT & arm_ext_v4t
18760 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18761 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18762 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18763 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18764 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18765 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18768 #define ARM_VARIANT & arm_ext_v4t_5
18770 /* ARM Architecture 4T. */
18771 /* Note: bx (and blx) are required on V5, even if the processor does
18772 not support Thumb. */
18773 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
18776 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
18777 #undef THUMB_VARIANT
18778 #define THUMB_VARIANT & arm_ext_v5t
18780 /* Note: blx has 2 variants; the .value coded here is for
18781 BLX(2). Only this variant has conditional execution. */
18782 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
18783 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
18785 #undef THUMB_VARIANT
18786 #define THUMB_VARIANT & arm_ext_v6t2
18788 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
18789 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18790 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18791 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18792 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18793 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18794 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18795 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18798 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
18799 #undef THUMB_VARIANT
18800 #define THUMB_VARIANT & arm_ext_v5exp
18802 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18803 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18804 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18805 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18807 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18808 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18810 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18811 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18812 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18813 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18815 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18816 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18817 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18818 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18820 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18821 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18823 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18824 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18825 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18826 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18829 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
18830 #undef THUMB_VARIANT
18831 #define THUMB_VARIANT & arm_ext_v6t2
18833 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
18834 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
18836 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
18837 ADDRGLDRS
), ldrd
, t_ldstd
),
18839 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18840 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18843 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
18845 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
18848 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
18849 #undef THUMB_VARIANT
18850 #define THUMB_VARIANT & arm_ext_v6
18852 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18853 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18854 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18855 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18856 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18857 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18858 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18859 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18860 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18861 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
18863 #undef THUMB_VARIANT
18864 #define THUMB_VARIANT & arm_ext_v6t2
18866 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
18867 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18869 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18870 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18872 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
18873 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
18875 /* ARM V6 not included in V7M. */
18876 #undef THUMB_VARIANT
18877 #define THUMB_VARIANT & arm_ext_v6_notm
18878 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18879 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18880 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
18881 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
18882 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18883 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18884 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
18885 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18886 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
18887 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18888 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18889 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18890 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18891 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18892 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
18893 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
18894 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18895 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18897 /* ARM V6 not included in V7M (eg. integer SIMD). */
18898 #undef THUMB_VARIANT
18899 #define THUMB_VARIANT & arm_ext_v6_dsp
18900 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
18901 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
18902 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
18903 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18904 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18905 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18906 /* Old name for QASX. */
18907 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18908 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18909 /* Old name for QSAX. */
18910 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18911 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18912 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18913 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18914 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18915 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18916 /* Old name for SASX. */
18917 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18918 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18919 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18920 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18921 /* Old name for SHASX. */
18922 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18923 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18924 /* Old name for SHSAX. */
18925 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18926 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18927 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18928 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18929 /* Old name for SSAX. */
18930 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18931 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18932 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18933 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18934 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18935 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18936 /* Old name for UASX. */
18937 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18938 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18939 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18940 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18941 /* Old name for UHASX. */
18942 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18943 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18944 /* Old name for UHSAX. */
18945 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18946 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18947 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18948 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18949 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18950 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18951 /* Old name for UQASX. */
18952 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18953 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18954 /* Old name for UQSAX. */
18955 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18956 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18957 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18958 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18959 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18960 /* Old name for USAX. */
18961 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18962 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18963 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18964 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18965 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18966 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18967 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18968 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18969 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18970 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18971 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18972 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18973 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18974 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18975 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18976 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18977 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18978 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18979 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18980 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18981 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18982 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18983 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18984 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18985 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18986 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18987 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18988 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18989 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18990 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
18991 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
18992 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18993 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18994 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
18997 #define ARM_VARIANT & arm_ext_v6k
18998 #undef THUMB_VARIANT
18999 #define THUMB_VARIANT & arm_ext_v6k
19001 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19002 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19003 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19004 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19006 #undef THUMB_VARIANT
19007 #define THUMB_VARIANT & arm_ext_v6_notm
19008 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19010 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19011 RRnpcb
), strexd
, t_strexd
),
19013 #undef THUMB_VARIANT
19014 #define THUMB_VARIANT & arm_ext_v6t2
19015 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19017 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19019 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19021 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19023 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19026 #define ARM_VARIANT & arm_ext_sec
19027 #undef THUMB_VARIANT
19028 #define THUMB_VARIANT & arm_ext_sec
19030 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19033 #define ARM_VARIANT & arm_ext_virt
19034 #undef THUMB_VARIANT
19035 #define THUMB_VARIANT & arm_ext_virt
19037 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19038 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19041 #define ARM_VARIANT & arm_ext_pan
19042 #undef THUMB_VARIANT
19043 #define THUMB_VARIANT & arm_ext_pan
19045 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19048 #define ARM_VARIANT & arm_ext_v6t2
19049 #undef THUMB_VARIANT
19050 #define THUMB_VARIANT & arm_ext_v6t2
19052 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19053 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19054 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19055 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19057 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19058 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19059 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19060 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19062 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19063 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19064 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19065 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19067 /* Thumb-only instructions. */
19069 #define ARM_VARIANT NULL
19070 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19071 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19073 /* ARM does not really have an IT instruction, so always allow it.
19074 The opcode is copied from Thumb in order to allow warnings in
19075 -mimplicit-it=[never | arm] modes. */
19077 #define ARM_VARIANT & arm_ext_v1
19079 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
19080 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
19081 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
19082 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
19083 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
19084 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
19085 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
19086 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
19087 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
19088 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
19089 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
19090 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
19091 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
19092 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
19093 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
19094 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19095 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19096 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19098 /* Thumb2 only instructions. */
19100 #define ARM_VARIANT NULL
19102 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19103 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19104 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19105 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19106 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
19107 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
19109 /* Hardware division instructions. */
19111 #define ARM_VARIANT & arm_ext_adiv
19112 #undef THUMB_VARIANT
19113 #define THUMB_VARIANT & arm_ext_div
19115 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19116 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19118 /* ARM V6M/V7 instructions. */
19120 #define ARM_VARIANT & arm_ext_barrier
19121 #undef THUMB_VARIANT
19122 #define THUMB_VARIANT & arm_ext_barrier
19124 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
19125 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
19126 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
19128 /* ARM V7 instructions. */
19130 #define ARM_VARIANT & arm_ext_v7
19131 #undef THUMB_VARIANT
19132 #define THUMB_VARIANT & arm_ext_v7
19134 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
19135 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
19138 #define ARM_VARIANT & arm_ext_mp
19139 #undef THUMB_VARIANT
19140 #define THUMB_VARIANT & arm_ext_mp
19142 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
19144 /* AArchv8 instructions. */
19146 #define ARM_VARIANT & arm_ext_v8
19147 #undef THUMB_VARIANT
19148 #define THUMB_VARIANT & arm_ext_v8
19150 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
19151 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
19152 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19153 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
19155 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
19156 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19157 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19159 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
19161 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19163 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19165 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19166 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19167 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19168 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19169 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19170 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19172 /* ARMv8 T32 only. */
19174 #define ARM_VARIANT NULL
19175 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
19176 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
19177 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
19179 /* FP for ARMv8. */
19181 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19182 #undef THUMB_VARIANT
19183 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19185 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19186 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19187 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19188 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19189 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19190 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19191 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19192 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19193 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19194 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19195 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19196 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19197 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19198 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19199 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19200 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19201 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19203 /* Crypto v1 extensions. */
19205 #define ARM_VARIANT & fpu_crypto_ext_armv8
19206 #undef THUMB_VARIANT
19207 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19209 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19210 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19211 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19212 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19213 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19214 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19215 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19216 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19217 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19218 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19219 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19220 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19221 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19222 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19225 #define ARM_VARIANT & crc_ext_armv8
19226 #undef THUMB_VARIANT
19227 #define THUMB_VARIANT & crc_ext_armv8
19228 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19229 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19230 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19231 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19232 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19233 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19236 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19237 #undef THUMB_VARIANT
19238 #define THUMB_VARIANT NULL
19240 cCE("wfs", e200110
, 1, (RR
), rd
),
19241 cCE("rfs", e300110
, 1, (RR
), rd
),
19242 cCE("wfc", e400110
, 1, (RR
), rd
),
19243 cCE("rfc", e500110
, 1, (RR
), rd
),
19245 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19246 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19247 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19248 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19250 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19251 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19252 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19253 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19255 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
19256 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
19257 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
19258 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
19259 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
19260 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
19261 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
19262 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
19263 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
19264 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
19265 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
19266 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
19268 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
19269 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
19270 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
19271 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
19272 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
19273 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
19274 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
19275 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
19276 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
19277 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
19278 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
19279 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
19281 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
19282 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
19283 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
19284 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
19285 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
19286 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
19287 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
19288 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
19289 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
19290 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
19291 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
19292 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
19294 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
19295 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
19296 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
19297 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
19298 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
19299 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
19300 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
19301 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
19302 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
19303 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
19304 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
19305 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
19307 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
19308 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
19309 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
19310 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
19311 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
19312 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
19313 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
19314 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
19315 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
19316 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
19317 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
19318 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
19320 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
19321 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
19322 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
19323 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
19324 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
19325 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
19326 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
19327 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
19328 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
19329 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
19330 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
19331 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
19333 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
19334 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
19335 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
19336 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
19337 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
19338 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
19339 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
19340 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
19341 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
19342 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
19343 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
19344 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
19346 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
19347 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
19348 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
19349 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
19350 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
19351 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
19352 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
19353 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
19354 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
19355 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
19356 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
19357 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
19359 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
19360 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
19361 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
19362 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
19363 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
19364 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
19365 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
19366 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
19367 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
19368 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
19369 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
19370 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
19372 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
19373 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
19374 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
19375 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
19376 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
19377 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
19378 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
19379 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
19380 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
19381 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
19382 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
19383 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
19385 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
19386 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
19387 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
19388 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
19389 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
19390 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
19391 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
19392 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
19393 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
19394 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
19395 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
19396 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
19398 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
19399 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
19400 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
19401 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
19402 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
19403 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
19404 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
19405 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
19406 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
19407 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
19408 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
19409 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
19411 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
19412 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
19413 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
19414 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
19415 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
19416 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
19417 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
19418 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
19419 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
19420 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
19421 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
19422 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
19424 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
19425 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
19426 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
19427 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
19428 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
19429 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
19430 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
19431 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
19432 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
19433 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
19434 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
19435 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
19437 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
19438 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
19439 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
19440 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
19441 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
19442 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
19443 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
19444 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
19445 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
19446 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
19447 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
19448 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
19450 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
19451 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
19452 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
19453 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
19454 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
19455 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
19456 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
19457 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
19458 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
19459 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
19460 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
19461 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
19463 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19464 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19465 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19466 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19467 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19468 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19469 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19470 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19471 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19472 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19473 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19474 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19476 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19477 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19478 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19479 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19480 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19481 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19482 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19483 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19484 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19485 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19486 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19487 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19489 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19490 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19491 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19492 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19493 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19494 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19495 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19496 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19497 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19498 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19499 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19500 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19502 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19503 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19504 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19505 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19506 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19507 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19508 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19509 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19510 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19511 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19512 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19513 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19515 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19516 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19517 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19518 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19519 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19520 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19521 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19522 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19523 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19524 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19525 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19526 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19528 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19529 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19530 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19531 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19532 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19533 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19534 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19535 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19536 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19537 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19538 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19539 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19541 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19542 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19543 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19544 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19545 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19546 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19547 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19548 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19549 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19550 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19551 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19552 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19554 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19555 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19556 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19557 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19558 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19559 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19560 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19561 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19562 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19563 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19564 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19565 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19567 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19568 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19569 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19570 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19571 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19572 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19573 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19574 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19575 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19576 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19577 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19578 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19580 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19581 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19582 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19583 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19584 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19585 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19586 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19587 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19588 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19589 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19590 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19591 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19593 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19594 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19595 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19596 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19597 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19598 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19599 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19600 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19601 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19602 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19603 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19604 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19606 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19607 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19608 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19609 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19610 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19611 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19612 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19613 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19614 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19615 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19616 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19617 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19619 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19620 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19621 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19622 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19623 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19624 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19625 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19626 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19627 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19628 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19629 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19630 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19632 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19633 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19634 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19635 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19637 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
19638 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
19639 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
19640 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
19641 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
19642 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
19643 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
19644 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
19645 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
19646 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
19647 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
19648 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
19650 /* The implementation of the FIX instruction is broken on some
19651 assemblers, in that it accepts a precision specifier as well as a
19652 rounding specifier, despite the fact that this is meaningless.
19653 To be more compatible, we accept it as well, though of course it
19654 does not set any bits. */
19655 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
19656 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
19657 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
19658 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
19659 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
19660 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
19661 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
19662 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
19663 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
19664 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
19665 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
19666 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
19667 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
19669 /* Instructions that were new with the real FPA, call them V2. */
19671 #define ARM_VARIANT & fpu_fpa_ext_v2
19673 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19674 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19675 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19676 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19677 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19678 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19681 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
19683 /* Moves and type conversions. */
19684 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19685 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
19686 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
19687 cCE("fmstat", ef1fa10
, 0, (), noargs
),
19688 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
19689 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
19690 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19691 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19692 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19693 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19694 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19695 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19696 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
19697 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
19699 /* Memory operations. */
19700 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19701 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19702 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19703 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19704 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19705 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19706 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19707 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19708 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19709 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19710 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19711 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19712 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19713 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19714 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19715 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19716 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19717 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19719 /* Monadic operations. */
19720 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19721 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19722 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19724 /* Dyadic operations. */
19725 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19726 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19727 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19728 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19729 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19730 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19731 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19732 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19733 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19736 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19737 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
19738 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19739 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
19741 /* Double precision load/store are still present on single precision
19742 implementations. */
19743 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19744 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19745 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19746 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19747 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19748 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19749 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19750 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19751 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19752 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19755 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
19757 /* Moves and type conversions. */
19758 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19759 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19760 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19761 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19762 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19763 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19764 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19765 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19766 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19767 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19768 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19769 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19770 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19772 /* Monadic operations. */
19773 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19774 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19775 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19777 /* Dyadic operations. */
19778 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19779 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19780 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19781 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19782 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19783 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19784 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19785 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19786 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19789 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19790 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
19791 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19792 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
19795 #define ARM_VARIANT & fpu_vfp_ext_v2
19797 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
19798 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
19799 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
19800 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
19802 /* Instructions which may belong to either the Neon or VFP instruction sets.
19803 Individual encoder functions perform additional architecture checks. */
19805 #define ARM_VARIANT & fpu_vfp_ext_v1xd
19806 #undef THUMB_VARIANT
19807 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
19809 /* These mnemonics are unique to VFP. */
19810 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
19811 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
19812 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19813 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19814 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19815 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
19816 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
19817 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
19818 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
19819 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
19821 /* Mnemonics shared by Neon and VFP. */
19822 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
19823 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19824 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19826 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19827 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19829 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19830 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19832 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19833 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19834 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19835 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19836 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19837 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19838 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19839 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19841 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
19842 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
19843 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
19844 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
19847 /* NOTE: All VMOV encoding is special-cased! */
19848 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
19849 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
19851 #undef THUMB_VARIANT
19852 #define THUMB_VARIANT & fpu_neon_ext_v1
19854 #define ARM_VARIANT & fpu_neon_ext_v1
19856 /* Data processing with three registers of the same length. */
19857 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
19858 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
19859 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
19860 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19861 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19862 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19863 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19864 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19865 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19866 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
19867 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19868 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19869 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19870 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19871 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19872 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19873 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19874 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19875 /* If not immediate, fall back to neon_dyadic_i64_su.
19876 shl_imm should accept I8 I16 I32 I64,
19877 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
19878 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
19879 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
19880 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
19881 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
19882 /* Logic ops, types optional & ignored. */
19883 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19884 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19885 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19886 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19887 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19888 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19889 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19890 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19891 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
19892 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
19893 /* Bitfield ops, untyped. */
19894 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19895 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19896 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19897 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19898 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19899 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19900 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
19901 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19902 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19903 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19904 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19905 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19906 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19907 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
19908 back to neon_dyadic_if_su. */
19909 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19910 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19911 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19912 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19913 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19914 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19915 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19916 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19917 /* Comparison. Type I8 I16 I32 F32. */
19918 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
19919 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
19920 /* As above, D registers only. */
19921 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19922 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19923 /* Int and float variants, signedness unimportant. */
19924 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19925 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19926 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
19927 /* Add/sub take types I8 I16 I32 I64 F32. */
19928 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19929 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19930 /* vtst takes sizes 8, 16, 32. */
19931 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
19932 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
19933 /* VMUL takes I8 I16 I32 F32 P8. */
19934 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
19935 /* VQD{R}MULH takes S16 S32. */
19936 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19937 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19938 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19939 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19940 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19941 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19942 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19943 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19944 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19945 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19946 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19947 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19948 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19949 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19950 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19951 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19952 /* ARM v8.1 extension. */
19953 nUF(vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19954 nUF(vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19955 nUF(vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19956 nUF(vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19958 /* Two address, int/float. Types S8 S16 S32 F32. */
19959 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
19960 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
19962 /* Data processing with two registers and a shift amount. */
19963 /* Right shifts, and variants with rounding.
19964 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
19965 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
19966 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
19967 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
19968 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
19969 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
19970 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
19971 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
19972 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
19973 /* Shift and insert. Sizes accepted 8 16 32 64. */
19974 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
19975 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
19976 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
19977 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
19978 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
19979 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
19980 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
19981 /* Right shift immediate, saturating & narrowing, with rounding variants.
19982 Types accepted S16 S32 S64 U16 U32 U64. */
19983 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
19984 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
19985 /* As above, unsigned. Types accepted S16 S32 S64. */
19986 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
19987 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
19988 /* Right shift narrowing. Types accepted I16 I32 I64. */
19989 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
19990 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
19991 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
19992 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
19993 /* CVT with optional immediate for fixed-point variant. */
19994 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
19996 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
19997 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
19999 /* Data processing, three registers of different lengths. */
20000 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20001 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
20002 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20003 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20004 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20005 /* If not scalar, fall back to neon_dyadic_long.
20006 Vector types as above, scalar types S16 S32 U16 U32. */
20007 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20008 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20009 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20010 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20011 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20012 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20013 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20014 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20015 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20016 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20017 /* Saturating doubling multiplies. Types S16 S32. */
20018 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20019 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20020 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20021 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20022 S16 S32 U16 U32. */
20023 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20025 /* Extract. Size 8. */
20026 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20027 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20029 /* Two registers, miscellaneous. */
20030 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20031 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20032 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20033 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20034 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20035 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20036 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20037 /* Vector replicate. Sizes 8 16 32. */
20038 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
20039 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
20040 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20041 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
20042 /* VMOVN. Types I16 I32 I64. */
20043 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
20044 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20045 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
20046 /* VQMOVUN. Types S16 S32 S64. */
20047 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
20048 /* VZIP / VUZP. Sizes 8 16 32. */
20049 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20050 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20051 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20052 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20053 /* VQABS / VQNEG. Types S8 S16 S32. */
20054 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20055 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20056 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20057 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20058 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20059 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20060 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
20061 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20062 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
20063 /* Reciprocal estimates. Types U32 F32. */
20064 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20065 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
20066 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20067 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
20068 /* VCLS. Types S8 S16 S32. */
20069 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
20070 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
20071 /* VCLZ. Types I8 I16 I32. */
20072 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
20073 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
20074 /* VCNT. Size 8. */
20075 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
20076 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
20077 /* Two address, untyped. */
20078 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
20079 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
20080 /* VTRN. Sizes 8 16 32. */
20081 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
20082 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
20084 /* Table lookup. Size 8. */
20085 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20086 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20088 #undef THUMB_VARIANT
20089 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20091 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20093 /* Neon element/structure load/store. */
20094 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20095 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20096 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20097 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20098 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20099 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20100 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20101 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20103 #undef THUMB_VARIANT
20104 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20106 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20107 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
20108 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20109 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20110 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20111 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20112 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20113 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20114 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20115 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20117 #undef THUMB_VARIANT
20118 #define THUMB_VARIANT & fpu_vfp_ext_v3
20120 #define ARM_VARIANT & fpu_vfp_ext_v3
20122 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
20123 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20124 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20125 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20126 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20127 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20128 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20129 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20130 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20133 #define ARM_VARIANT & fpu_vfp_ext_fma
20134 #undef THUMB_VARIANT
20135 #define THUMB_VARIANT & fpu_vfp_ext_fma
20136 /* Mnemonics shared by Neon and VFP. These are included in the
20137 VFP FMA variant; NEON and VFP FMA always includes the NEON
20138 FMA instructions. */
20139 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20140 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20141 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20142 the v form should always be used. */
20143 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20144 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20145 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20146 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20147 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20148 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20150 #undef THUMB_VARIANT
20152 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20154 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20155 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20156 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20157 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20158 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20159 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20160 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
20161 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
20164 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20166 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
20167 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
20168 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
20169 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
20170 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
20171 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
20172 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
20173 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
20174 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
20175 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20176 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20177 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20178 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20179 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20180 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20181 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20182 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20183 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20184 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
20185 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
20186 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20187 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20188 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20189 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20190 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20191 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20192 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20193 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20194 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20195 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20196 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20197 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20198 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20199 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20200 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20201 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20202 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20203 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20204 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20205 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20206 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20207 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20208 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20209 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20210 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20211 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20212 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20213 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20214 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20215 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20216 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20217 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20218 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20219 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20220 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20221 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20222 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20223 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20224 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20225 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20226 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20227 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20228 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20229 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20230 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20231 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20232 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20233 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20234 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20235 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20236 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20237 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20238 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20239 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20240 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20241 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20242 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20243 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20244 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20245 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20246 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20247 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20248 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20249 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20250 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20251 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20252 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20253 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20254 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
20255 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20256 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20257 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20258 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20259 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20260 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20261 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20262 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20263 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20264 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20265 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20266 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20267 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20268 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20269 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20270 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20271 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20272 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20273 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20274 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20275 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20276 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
20277 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20278 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20279 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20280 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20281 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20282 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20283 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20284 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20285 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20286 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20287 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20288 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20289 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20290 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20291 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20292 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20293 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20294 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20295 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20296 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20297 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20298 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20299 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20300 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20301 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20302 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20303 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20304 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20305 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20306 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20307 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20308 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20309 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20310 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20311 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20312 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20313 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20314 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20315 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20316 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20317 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20318 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20319 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20320 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20321 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20322 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20323 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20324 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20325 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20326 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20327 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
20330 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20332 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
20333 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
20334 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
20335 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20336 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20337 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20338 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20339 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20340 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20341 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20342 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20343 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20344 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20345 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20346 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20347 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20348 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20349 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20350 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20351 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20352 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
20353 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20354 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20355 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20356 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20357 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20358 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20359 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20360 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20361 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20362 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20363 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20364 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20365 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20366 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20367 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20368 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20369 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20370 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20371 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20372 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20373 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20374 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20375 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20376 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20377 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20378 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20379 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20380 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20381 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20382 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20383 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20384 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20385 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20386 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20387 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20388 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20391 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
20393 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20394 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20395 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20396 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20397 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20398 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20399 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20400 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20401 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
20402 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
20403 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
20404 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
20405 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
20406 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
20407 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
20408 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
20409 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
20410 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
20411 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
20412 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
20413 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
20414 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
20415 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
20416 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
20417 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
20418 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
20419 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
20420 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
20421 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
20422 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
20423 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
20424 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
20425 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
20426 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
20427 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
20428 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
20429 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
20430 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
20431 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
20432 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
20433 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
20434 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
20435 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
20436 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
20437 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
20438 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
20439 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
20440 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
20441 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
20442 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
20443 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
20444 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
20445 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
20446 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
20447 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20448 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20449 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20450 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20451 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20452 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20453 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
20454 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
20455 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
20456 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
20457 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20458 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20459 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20460 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20461 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20462 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20463 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20464 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20465 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20466 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20467 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20468 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20471 #undef THUMB_VARIANT
20497 /* MD interface: bits in the object file. */
20499 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
20500 for use in the a.out file, and stores them in the array pointed to by buf.
20501 This knows about the endian-ness of the target machine and does
20502 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
20503 2 (short) and 4 (long) Floating numbers are put out as a series of
20504 LITTLENUMS (shorts, here at least). */
20507 md_number_to_chars (char * buf
, valueT val
, int n
)
20509 if (target_big_endian
)
20510 number_to_chars_bigendian (buf
, val
, n
);
20512 number_to_chars_littleendian (buf
, val
, n
);
20516 md_chars_to_number (char * buf
, int n
)
20519 unsigned char * where
= (unsigned char *) buf
;
20521 if (target_big_endian
)
20526 result
|= (*where
++ & 255);
20534 result
|= (where
[n
] & 255);
20541 /* MD interface: Sections. */
20543 /* Calculate the maximum variable size (i.e., excluding fr_fix)
20544 that an rs_machine_dependent frag may reach. */
20547 arm_frag_max_var (fragS
*fragp
)
20549 /* We only use rs_machine_dependent for variable-size Thumb instructions,
20550 which are either THUMB_SIZE (2) or INSN_SIZE (4).
20552 Note that we generate relaxable instructions even for cases that don't
20553 really need it, like an immediate that's a trivial constant. So we're
20554 overestimating the instruction size for some of those cases. Rather
20555 than putting more intelligence here, it would probably be better to
20556 avoid generating a relaxation frag in the first place when it can be
20557 determined up front that a short instruction will suffice. */
20559 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
20563 /* Estimate the size of a frag before relaxing. Assume everything fits in
20567 md_estimate_size_before_relax (fragS
* fragp
,
20568 segT segtype ATTRIBUTE_UNUSED
)
20574 /* Convert a machine dependent frag. */
20577 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
20579 unsigned long insn
;
20580 unsigned long old_op
;
20588 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20590 old_op
= bfd_get_16(abfd
, buf
);
20591 if (fragp
->fr_symbol
)
20593 exp
.X_op
= O_symbol
;
20594 exp
.X_add_symbol
= fragp
->fr_symbol
;
20598 exp
.X_op
= O_constant
;
20600 exp
.X_add_number
= fragp
->fr_offset
;
20601 opcode
= fragp
->fr_subtype
;
20604 case T_MNEM_ldr_pc
:
20605 case T_MNEM_ldr_pc2
:
20606 case T_MNEM_ldr_sp
:
20607 case T_MNEM_str_sp
:
20614 if (fragp
->fr_var
== 4)
20616 insn
= THUMB_OP32 (opcode
);
20617 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
20619 insn
|= (old_op
& 0x700) << 4;
20623 insn
|= (old_op
& 7) << 12;
20624 insn
|= (old_op
& 0x38) << 13;
20626 insn
|= 0x00000c00;
20627 put_thumb32_insn (buf
, insn
);
20628 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
20632 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
20634 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
20637 if (fragp
->fr_var
== 4)
20639 insn
= THUMB_OP32 (opcode
);
20640 insn
|= (old_op
& 0xf0) << 4;
20641 put_thumb32_insn (buf
, insn
);
20642 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
20646 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20647 exp
.X_add_number
-= 4;
20655 if (fragp
->fr_var
== 4)
20657 int r0off
= (opcode
== T_MNEM_mov
20658 || opcode
== T_MNEM_movs
) ? 0 : 8;
20659 insn
= THUMB_OP32 (opcode
);
20660 insn
= (insn
& 0xe1ffffff) | 0x10000000;
20661 insn
|= (old_op
& 0x700) << r0off
;
20662 put_thumb32_insn (buf
, insn
);
20663 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20667 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
20672 if (fragp
->fr_var
== 4)
20674 insn
= THUMB_OP32(opcode
);
20675 put_thumb32_insn (buf
, insn
);
20676 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
20679 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
20683 if (fragp
->fr_var
== 4)
20685 insn
= THUMB_OP32(opcode
);
20686 insn
|= (old_op
& 0xf00) << 14;
20687 put_thumb32_insn (buf
, insn
);
20688 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
20691 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
20694 case T_MNEM_add_sp
:
20695 case T_MNEM_add_pc
:
20696 case T_MNEM_inc_sp
:
20697 case T_MNEM_dec_sp
:
20698 if (fragp
->fr_var
== 4)
20700 /* ??? Choose between add and addw. */
20701 insn
= THUMB_OP32 (opcode
);
20702 insn
|= (old_op
& 0xf0) << 4;
20703 put_thumb32_insn (buf
, insn
);
20704 if (opcode
== T_MNEM_add_pc
)
20705 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
20707 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20710 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20718 if (fragp
->fr_var
== 4)
20720 insn
= THUMB_OP32 (opcode
);
20721 insn
|= (old_op
& 0xf0) << 4;
20722 insn
|= (old_op
& 0xf) << 16;
20723 put_thumb32_insn (buf
, insn
);
20724 if (insn
& (1 << 20))
20725 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20727 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20730 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20736 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
20737 (enum bfd_reloc_code_real
) reloc_type
);
20738 fixp
->fx_file
= fragp
->fr_file
;
20739 fixp
->fx_line
= fragp
->fr_line
;
20740 fragp
->fr_fix
+= fragp
->fr_var
;
20742 /* Set whether we use thumb-2 ISA based on final relaxation results. */
20743 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
20744 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
20745 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
20748 /* Return the size of a relaxable immediate operand instruction.
20749 SHIFT and SIZE specify the form of the allowable immediate. */
20751 relax_immediate (fragS
*fragp
, int size
, int shift
)
20757 /* ??? Should be able to do better than this. */
20758 if (fragp
->fr_symbol
)
20761 low
= (1 << shift
) - 1;
20762 mask
= (1 << (shift
+ size
)) - (1 << shift
);
20763 offset
= fragp
->fr_offset
;
20764 /* Force misaligned offsets to 32-bit variant. */
20767 if (offset
& ~mask
)
20772 /* Get the address of a symbol during relaxation. */
20774 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
20780 sym
= fragp
->fr_symbol
;
20781 sym_frag
= symbol_get_frag (sym
);
20782 know (S_GET_SEGMENT (sym
) != absolute_section
20783 || sym_frag
== &zero_address_frag
);
20784 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
20786 /* If frag has yet to be reached on this pass, assume it will
20787 move by STRETCH just as we did. If this is not so, it will
20788 be because some frag between grows, and that will force
20792 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
20796 /* Adjust stretch for any alignment frag. Note that if have
20797 been expanding the earlier code, the symbol may be
20798 defined in what appears to be an earlier frag. FIXME:
20799 This doesn't handle the fr_subtype field, which specifies
20800 a maximum number of bytes to skip when doing an
20802 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
20804 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
20807 stretch
= - ((- stretch
)
20808 & ~ ((1 << (int) f
->fr_offset
) - 1));
20810 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
20822 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
20825 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
20830 /* Assume worst case for symbols not known to be in the same section. */
20831 if (fragp
->fr_symbol
== NULL
20832 || !S_IS_DEFINED (fragp
->fr_symbol
)
20833 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20834 || S_IS_WEAK (fragp
->fr_symbol
))
20837 val
= relaxed_symbol_addr (fragp
, stretch
);
20838 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
20839 addr
= (addr
+ 4) & ~3;
20840 /* Force misaligned targets to 32-bit variant. */
20844 if (val
< 0 || val
> 1020)
20849 /* Return the size of a relaxable add/sub immediate instruction. */
20851 relax_addsub (fragS
*fragp
, asection
*sec
)
20856 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20857 op
= bfd_get_16(sec
->owner
, buf
);
20858 if ((op
& 0xf) == ((op
>> 4) & 0xf))
20859 return relax_immediate (fragp
, 8, 0);
20861 return relax_immediate (fragp
, 3, 0);
20864 /* Return TRUE iff the definition of symbol S could be pre-empted
20865 (overridden) at link or load time. */
20867 symbol_preemptible (symbolS
*s
)
20869 /* Weak symbols can always be pre-empted. */
20873 /* Non-global symbols cannot be pre-empted. */
20874 if (! S_IS_EXTERNAL (s
))
20878 /* In ELF, a global symbol can be marked protected, or private. In that
20879 case it can't be pre-empted (other definitions in the same link unit
20880 would violate the ODR). */
20881 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
20885 /* Other global symbols might be pre-empted. */
20889 /* Return the size of a relaxable branch instruction. BITS is the
20890 size of the offset field in the narrow instruction. */
20893 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
20899 /* Assume worst case for symbols not known to be in the same section. */
20900 if (!S_IS_DEFINED (fragp
->fr_symbol
)
20901 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20902 || S_IS_WEAK (fragp
->fr_symbol
))
20906 /* A branch to a function in ARM state will require interworking. */
20907 if (S_IS_DEFINED (fragp
->fr_symbol
)
20908 && ARM_IS_FUNC (fragp
->fr_symbol
))
20912 if (symbol_preemptible (fragp
->fr_symbol
))
20915 val
= relaxed_symbol_addr (fragp
, stretch
);
20916 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
20919 /* Offset is a signed value *2 */
20921 if (val
>= limit
|| val
< -limit
)
20927 /* Relax a machine dependent frag. This returns the amount by which
20928 the current size of the frag should change. */
20931 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
20936 oldsize
= fragp
->fr_var
;
20937 switch (fragp
->fr_subtype
)
20939 case T_MNEM_ldr_pc2
:
20940 newsize
= relax_adr (fragp
, sec
, stretch
);
20942 case T_MNEM_ldr_pc
:
20943 case T_MNEM_ldr_sp
:
20944 case T_MNEM_str_sp
:
20945 newsize
= relax_immediate (fragp
, 8, 2);
20949 newsize
= relax_immediate (fragp
, 5, 2);
20953 newsize
= relax_immediate (fragp
, 5, 1);
20957 newsize
= relax_immediate (fragp
, 5, 0);
20960 newsize
= relax_adr (fragp
, sec
, stretch
);
20966 newsize
= relax_immediate (fragp
, 8, 0);
20969 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
20972 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
20974 case T_MNEM_add_sp
:
20975 case T_MNEM_add_pc
:
20976 newsize
= relax_immediate (fragp
, 8, 2);
20978 case T_MNEM_inc_sp
:
20979 case T_MNEM_dec_sp
:
20980 newsize
= relax_immediate (fragp
, 7, 2);
20986 newsize
= relax_addsub (fragp
, sec
);
20992 fragp
->fr_var
= newsize
;
20993 /* Freeze wide instructions that are at or before the same location as
20994 in the previous pass. This avoids infinite loops.
20995 Don't freeze them unconditionally because targets may be artificially
20996 misaligned by the expansion of preceding frags. */
20997 if (stretch
<= 0 && newsize
> 2)
20999 md_convert_frag (sec
->owner
, sec
, fragp
);
21003 return newsize
- oldsize
;
21006 /* Round up a section size to the appropriate boundary. */
21009 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21012 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21013 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21015 /* For a.out, force the section size to be aligned. If we don't do
21016 this, BFD will align it for us, but it will not write out the
21017 final bytes of the section. This may be a bug in BFD, but it is
21018 easier to fix it here since that is how the other a.out targets
21022 align
= bfd_get_section_alignment (stdoutput
, segment
);
21023 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
21030 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21031 of an rs_align_code fragment. */
21034 arm_handle_align (fragS
* fragP
)
21036 static char const arm_noop
[2][2][4] =
21039 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21040 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21043 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21044 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21047 static char const thumb_noop
[2][2][2] =
21050 {0xc0, 0x46}, /* LE */
21051 {0x46, 0xc0}, /* BE */
21054 {0x00, 0xbf}, /* LE */
21055 {0xbf, 0x00} /* BE */
21058 static char const wide_thumb_noop
[2][4] =
21059 { /* Wide Thumb-2 */
21060 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21061 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21064 unsigned bytes
, fix
, noop_size
;
21067 const char *narrow_noop
= NULL
;
21072 if (fragP
->fr_type
!= rs_align_code
)
21075 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
21076 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
21079 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21080 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
21082 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
21084 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
21086 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21087 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
21089 narrow_noop
= thumb_noop
[1][target_big_endian
];
21090 noop
= wide_thumb_noop
[target_big_endian
];
21093 noop
= thumb_noop
[0][target_big_endian
];
21101 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21102 ? selected_cpu
: arm_arch_none
,
21104 [target_big_endian
];
21111 fragP
->fr_var
= noop_size
;
21113 if (bytes
& (noop_size
- 1))
21115 fix
= bytes
& (noop_size
- 1);
21117 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
21119 memset (p
, 0, fix
);
21126 if (bytes
& noop_size
)
21128 /* Insert a narrow noop. */
21129 memcpy (p
, narrow_noop
, noop_size
);
21131 bytes
-= noop_size
;
21135 /* Use wide noops for the remainder */
21139 while (bytes
>= noop_size
)
21141 memcpy (p
, noop
, noop_size
);
21143 bytes
-= noop_size
;
21147 fragP
->fr_fix
+= fix
;
21150 /* Called from md_do_align. Used to create an alignment
21151 frag in a code section. */
21154 arm_frag_align_code (int n
, int max
)
21158 /* We assume that there will never be a requirement
21159 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21160 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21165 _("alignments greater than %d bytes not supported in .text sections."),
21166 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
21167 as_fatal ("%s", err_msg
);
21170 p
= frag_var (rs_align_code
,
21171 MAX_MEM_FOR_RS_ALIGN_CODE
,
21173 (relax_substateT
) max
,
21180 /* Perform target specific initialisation of a frag.
21181 Note - despite the name this initialisation is not done when the frag
21182 is created, but only when its type is assigned. A frag can be created
21183 and used a long time before its type is set, so beware of assuming that
21184 this initialisationis performed first. */
21188 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
21190 /* Record whether this frag is in an ARM or a THUMB area. */
21191 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21194 #else /* OBJ_ELF is defined. */
21196 arm_init_frag (fragS
* fragP
, int max_chars
)
21198 int frag_thumb_mode
;
21200 /* If the current ARM vs THUMB mode has not already
21201 been recorded into this frag then do so now. */
21202 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
21203 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21205 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
21207 /* Record a mapping symbol for alignment frags. We will delete this
21208 later if the alignment ends up empty. */
21209 switch (fragP
->fr_type
)
21212 case rs_align_test
:
21214 mapping_state_2 (MAP_DATA
, max_chars
);
21216 case rs_align_code
:
21217 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
21224 /* When we change sections we need to issue a new mapping symbol. */
21227 arm_elf_change_section (void)
21229 /* Link an unlinked unwind index table section to the .text section. */
21230 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
21231 && elf_linked_to_section (now_seg
) == NULL
)
21232 elf_linked_to_section (now_seg
) = text_section
;
21236 arm_elf_section_type (const char * str
, size_t len
)
21238 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
21239 return SHT_ARM_EXIDX
;
21244 /* Code to deal with unwinding tables. */
21246 static void add_unwind_adjustsp (offsetT
);
21248 /* Generate any deferred unwind frame offset. */
21251 flush_pending_unwind (void)
21255 offset
= unwind
.pending_offset
;
21256 unwind
.pending_offset
= 0;
21258 add_unwind_adjustsp (offset
);
21261 /* Add an opcode to this list for this function. Two-byte opcodes should
21262 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21266 add_unwind_opcode (valueT op
, int length
)
21268 /* Add any deferred stack adjustment. */
21269 if (unwind
.pending_offset
)
21270 flush_pending_unwind ();
21272 unwind
.sp_restored
= 0;
21274 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
21276 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
21277 if (unwind
.opcodes
)
21278 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
21279 unwind
.opcode_alloc
);
21281 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
21286 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
21288 unwind
.opcode_count
++;
21292 /* Add unwind opcodes to adjust the stack pointer. */
21295 add_unwind_adjustsp (offsetT offset
)
21299 if (offset
> 0x200)
21301 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21306 /* Long form: 0xb2, uleb128. */
21307 /* This might not fit in a word so add the individual bytes,
21308 remembering the list is built in reverse order. */
21309 o
= (valueT
) ((offset
- 0x204) >> 2);
21311 add_unwind_opcode (0, 1);
21313 /* Calculate the uleb128 encoding of the offset. */
21317 bytes
[n
] = o
& 0x7f;
21323 /* Add the insn. */
21325 add_unwind_opcode (bytes
[n
- 1], 1);
21326 add_unwind_opcode (0xb2, 1);
21328 else if (offset
> 0x100)
21330 /* Two short opcodes. */
21331 add_unwind_opcode (0x3f, 1);
21332 op
= (offset
- 0x104) >> 2;
21333 add_unwind_opcode (op
, 1);
21335 else if (offset
> 0)
21337 /* Short opcode. */
21338 op
= (offset
- 4) >> 2;
21339 add_unwind_opcode (op
, 1);
21341 else if (offset
< 0)
21344 while (offset
> 0x100)
21346 add_unwind_opcode (0x7f, 1);
21349 op
= ((offset
- 4) >> 2) | 0x40;
21350 add_unwind_opcode (op
, 1);
21354 /* Finish the list of unwind opcodes for this function. */
21356 finish_unwind_opcodes (void)
21360 if (unwind
.fp_used
)
21362 /* Adjust sp as necessary. */
21363 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
21364 flush_pending_unwind ();
21366 /* After restoring sp from the frame pointer. */
21367 op
= 0x90 | unwind
.fp_reg
;
21368 add_unwind_opcode (op
, 1);
21371 flush_pending_unwind ();
21375 /* Start an exception table entry. If idx is nonzero this is an index table
21379 start_unwind_section (const segT text_seg
, int idx
)
21381 const char * text_name
;
21382 const char * prefix
;
21383 const char * prefix_once
;
21384 const char * group_name
;
21388 size_t sec_name_len
;
21395 prefix
= ELF_STRING_ARM_unwind
;
21396 prefix_once
= ELF_STRING_ARM_unwind_once
;
21397 type
= SHT_ARM_EXIDX
;
21401 prefix
= ELF_STRING_ARM_unwind_info
;
21402 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
21403 type
= SHT_PROGBITS
;
21406 text_name
= segment_name (text_seg
);
21407 if (streq (text_name
, ".text"))
21410 if (strncmp (text_name
, ".gnu.linkonce.t.",
21411 strlen (".gnu.linkonce.t.")) == 0)
21413 prefix
= prefix_once
;
21414 text_name
+= strlen (".gnu.linkonce.t.");
21417 prefix_len
= strlen (prefix
);
21418 text_len
= strlen (text_name
);
21419 sec_name_len
= prefix_len
+ text_len
;
21420 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
21421 memcpy (sec_name
, prefix
, prefix_len
);
21422 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
21423 sec_name
[prefix_len
+ text_len
] = '\0';
21429 /* Handle COMDAT group. */
21430 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
21432 group_name
= elf_group_name (text_seg
);
21433 if (group_name
== NULL
)
21435 as_bad (_("Group section `%s' has no group signature"),
21436 segment_name (text_seg
));
21437 ignore_rest_of_line ();
21440 flags
|= SHF_GROUP
;
21444 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
21446 /* Set the section link for index tables. */
21448 elf_linked_to_section (now_seg
) = text_seg
;
21452 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
21453 personality routine data. Returns zero, or the index table value for
21454 an inline entry. */
21457 create_unwind_entry (int have_data
)
21462 /* The current word of data. */
21464 /* The number of bytes left in this word. */
21467 finish_unwind_opcodes ();
21469 /* Remember the current text section. */
21470 unwind
.saved_seg
= now_seg
;
21471 unwind
.saved_subseg
= now_subseg
;
21473 start_unwind_section (now_seg
, 0);
21475 if (unwind
.personality_routine
== NULL
)
21477 if (unwind
.personality_index
== -2)
21480 as_bad (_("handlerdata in cantunwind frame"));
21481 return 1; /* EXIDX_CANTUNWIND. */
21484 /* Use a default personality routine if none is specified. */
21485 if (unwind
.personality_index
== -1)
21487 if (unwind
.opcode_count
> 3)
21488 unwind
.personality_index
= 1;
21490 unwind
.personality_index
= 0;
21493 /* Space for the personality routine entry. */
21494 if (unwind
.personality_index
== 0)
21496 if (unwind
.opcode_count
> 3)
21497 as_bad (_("too many unwind opcodes for personality routine 0"));
21501 /* All the data is inline in the index table. */
21504 while (unwind
.opcode_count
> 0)
21506 unwind
.opcode_count
--;
21507 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21511 /* Pad with "finish" opcodes. */
21513 data
= (data
<< 8) | 0xb0;
21520 /* We get two opcodes "free" in the first word. */
21521 size
= unwind
.opcode_count
- 2;
21525 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
21526 if (unwind
.personality_index
!= -1)
21528 as_bad (_("attempt to recreate an unwind entry"));
21532 /* An extra byte is required for the opcode count. */
21533 size
= unwind
.opcode_count
+ 1;
21536 size
= (size
+ 3) >> 2;
21538 as_bad (_("too many unwind opcodes"));
21540 frag_align (2, 0, 0);
21541 record_alignment (now_seg
, 2);
21542 unwind
.table_entry
= expr_build_dot ();
21544 /* Allocate the table entry. */
21545 ptr
= frag_more ((size
<< 2) + 4);
21546 /* PR 13449: Zero the table entries in case some of them are not used. */
21547 memset (ptr
, 0, (size
<< 2) + 4);
21548 where
= frag_now_fix () - ((size
<< 2) + 4);
21550 switch (unwind
.personality_index
)
21553 /* ??? Should this be a PLT generating relocation? */
21554 /* Custom personality routine. */
21555 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
21556 BFD_RELOC_ARM_PREL31
);
21561 /* Set the first byte to the number of additional words. */
21562 data
= size
> 0 ? size
- 1 : 0;
21566 /* ABI defined personality routines. */
21568 /* Three opcodes bytes are packed into the first word. */
21575 /* The size and first two opcode bytes go in the first word. */
21576 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
21581 /* Should never happen. */
21585 /* Pack the opcodes into words (MSB first), reversing the list at the same
21587 while (unwind
.opcode_count
> 0)
21591 md_number_to_chars (ptr
, data
, 4);
21596 unwind
.opcode_count
--;
21598 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21601 /* Finish off the last word. */
21604 /* Pad with "finish" opcodes. */
21606 data
= (data
<< 8) | 0xb0;
21608 md_number_to_chars (ptr
, data
, 4);
21613 /* Add an empty descriptor if there is no user-specified data. */
21614 ptr
= frag_more (4);
21615 md_number_to_chars (ptr
, 0, 4);
21622 /* Initialize the DWARF-2 unwind information for this procedure. */
21625 tc_arm_frame_initial_instructions (void)
21627 cfi_add_CFA_def_cfa (REG_SP
, 0);
21629 #endif /* OBJ_ELF */
21631 /* Convert REGNAME to a DWARF-2 register number. */
21634 tc_arm_regname_to_dw2regnum (char *regname
)
21636 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
21640 /* PR 16694: Allow VFP registers as well. */
21641 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
21645 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
21654 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
21658 exp
.X_op
= O_secrel
;
21659 exp
.X_add_symbol
= symbol
;
21660 exp
.X_add_number
= 0;
21661 emit_expr (&exp
, size
);
21665 /* MD interface: Symbol and relocation handling. */
21667 /* Return the address within the segment that a PC-relative fixup is
21668 relative to. For ARM, PC-relative fixups applied to instructions
21669 are generally relative to the location of the fixup plus 8 bytes.
21670 Thumb branches are offset by 4, and Thumb loads relative to PC
21671 require special handling. */
21674 md_pcrel_from_section (fixS
* fixP
, segT seg
)
21676 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21678 /* If this is pc-relative and we are going to emit a relocation
21679 then we just want to put out any pipeline compensation that the linker
21680 will need. Otherwise we want to use the calculated base.
21681 For WinCE we skip the bias for externals as well, since this
21682 is how the MS ARM-CE assembler behaves and we want to be compatible. */
21684 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
21685 || (arm_force_relocation (fixP
)
21687 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
21693 switch (fixP
->fx_r_type
)
21695 /* PC relative addressing on the Thumb is slightly odd as the
21696 bottom two bits of the PC are forced to zero for the
21697 calculation. This happens *after* application of the
21698 pipeline offset. However, Thumb adrl already adjusts for
21699 this, so we need not do it again. */
21700 case BFD_RELOC_ARM_THUMB_ADD
:
21703 case BFD_RELOC_ARM_THUMB_OFFSET
:
21704 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
21705 case BFD_RELOC_ARM_T32_ADD_PC12
:
21706 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
21707 return (base
+ 4) & ~3;
21709 /* Thumb branches are simply offset by +4. */
21710 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21711 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21712 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21713 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21714 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21717 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21719 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21720 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21721 && ARM_IS_FUNC (fixP
->fx_addsy
)
21722 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21723 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21726 /* BLX is like branches above, but forces the low two bits of PC to
21728 case BFD_RELOC_THUMB_PCREL_BLX
:
21730 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21731 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21732 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21733 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21734 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21735 return (base
+ 4) & ~3;
21737 /* ARM mode branches are offset by +8. However, the Windows CE
21738 loader expects the relocation not to take this into account. */
21739 case BFD_RELOC_ARM_PCREL_BLX
:
21741 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21742 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21743 && ARM_IS_FUNC (fixP
->fx_addsy
)
21744 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21745 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21748 case BFD_RELOC_ARM_PCREL_CALL
:
21750 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21751 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21752 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21753 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21754 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21757 case BFD_RELOC_ARM_PCREL_BRANCH
:
21758 case BFD_RELOC_ARM_PCREL_JUMP
:
21759 case BFD_RELOC_ARM_PLT32
:
21761 /* When handling fixups immediately, because we have already
21762 discovered the value of a symbol, or the address of the frag involved
21763 we must account for the offset by +8, as the OS loader will never see the reloc.
21764 see fixup_segment() in write.c
21765 The S_IS_EXTERNAL test handles the case of global symbols.
21766 Those need the calculated base, not just the pipe compensation the linker will need. */
21768 && fixP
->fx_addsy
!= NULL
21769 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21770 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
21778 /* ARM mode loads relative to PC are also offset by +8. Unlike
21779 branches, the Windows CE loader *does* expect the relocation
21780 to take this into account. */
21781 case BFD_RELOC_ARM_OFFSET_IMM
:
21782 case BFD_RELOC_ARM_OFFSET_IMM8
:
21783 case BFD_RELOC_ARM_HWLITERAL
:
21784 case BFD_RELOC_ARM_LITERAL
:
21785 case BFD_RELOC_ARM_CP_OFF_IMM
:
21789 /* Other PC-relative relocations are un-offset. */
21795 static bfd_boolean flag_warn_syms
= TRUE
;
21798 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
21800 /* PR 18347 - Warn if the user attempts to create a symbol with the same
21801 name as an ARM instruction. Whilst strictly speaking it is allowed, it
21802 does mean that the resulting code might be very confusing to the reader.
21803 Also this warning can be triggered if the user omits an operand before
21804 an immediate address, eg:
21808 GAS treats this as an assignment of the value of the symbol foo to a
21809 symbol LDR, and so (without this code) it will not issue any kind of
21810 warning or error message.
21812 Note - ARM instructions are case-insensitive but the strings in the hash
21813 table are all stored in lower case, so we must first ensure that name is
21815 if (flag_warn_syms
&& arm_ops_hsh
)
21817 char * nbuf
= strdup (name
);
21820 for (p
= nbuf
; *p
; p
++)
21822 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
21824 static struct hash_control
* already_warned
= NULL
;
21826 if (already_warned
== NULL
)
21827 already_warned
= hash_new ();
21828 /* Only warn about the symbol once. To keep the code
21829 simple we let hash_insert do the lookup for us. */
21830 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
21831 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
21840 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
21841 Otherwise we have no need to default values of symbols. */
21844 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
21847 if (name
[0] == '_' && name
[1] == 'G'
21848 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
21852 if (symbol_find (name
))
21853 as_bad (_("GOT already in the symbol table"));
21855 GOT_symbol
= symbol_new (name
, undefined_section
,
21856 (valueT
) 0, & zero_address_frag
);
21866 /* Subroutine of md_apply_fix. Check to see if an immediate can be
21867 computed as two separate immediate values, added together. We
21868 already know that this value cannot be computed by just one ARM
21871 static unsigned int
21872 validate_immediate_twopart (unsigned int val
,
21873 unsigned int * highpart
)
21878 for (i
= 0; i
< 32; i
+= 2)
21879 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
21885 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
21887 else if (a
& 0xff0000)
21889 if (a
& 0xff000000)
21891 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
21895 gas_assert (a
& 0xff000000);
21896 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
21899 return (a
& 0xff) | (i
<< 7);
21906 validate_offset_imm (unsigned int val
, int hwse
)
21908 if ((hwse
&& val
> 255) || val
> 4095)
21913 /* Subroutine of md_apply_fix. Do those data_ops which can take a
21914 negative immediate constant by altering the instruction. A bit of
21919 by inverting the second operand, and
21922 by negating the second operand. */
21925 negate_data_op (unsigned long * instruction
,
21926 unsigned long value
)
21929 unsigned long negated
, inverted
;
21931 negated
= encode_arm_immediate (-value
);
21932 inverted
= encode_arm_immediate (~value
);
21934 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
21937 /* First negates. */
21938 case OPCODE_SUB
: /* ADD <-> SUB */
21939 new_inst
= OPCODE_ADD
;
21944 new_inst
= OPCODE_SUB
;
21948 case OPCODE_CMP
: /* CMP <-> CMN */
21949 new_inst
= OPCODE_CMN
;
21954 new_inst
= OPCODE_CMP
;
21958 /* Now Inverted ops. */
21959 case OPCODE_MOV
: /* MOV <-> MVN */
21960 new_inst
= OPCODE_MVN
;
21965 new_inst
= OPCODE_MOV
;
21969 case OPCODE_AND
: /* AND <-> BIC */
21970 new_inst
= OPCODE_BIC
;
21975 new_inst
= OPCODE_AND
;
21979 case OPCODE_ADC
: /* ADC <-> SBC */
21980 new_inst
= OPCODE_SBC
;
21985 new_inst
= OPCODE_ADC
;
21989 /* We cannot do anything. */
21994 if (value
== (unsigned) FAIL
)
21997 *instruction
&= OPCODE_MASK
;
21998 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
22002 /* Like negate_data_op, but for Thumb-2. */
22004 static unsigned int
22005 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22009 unsigned int negated
, inverted
;
22011 negated
= encode_thumb32_immediate (-value
);
22012 inverted
= encode_thumb32_immediate (~value
);
22014 rd
= (*instruction
>> 8) & 0xf;
22015 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22018 /* ADD <-> SUB. Includes CMP <-> CMN. */
22019 case T2_OPCODE_SUB
:
22020 new_inst
= T2_OPCODE_ADD
;
22024 case T2_OPCODE_ADD
:
22025 new_inst
= T2_OPCODE_SUB
;
22029 /* ORR <-> ORN. Includes MOV <-> MVN. */
22030 case T2_OPCODE_ORR
:
22031 new_inst
= T2_OPCODE_ORN
;
22035 case T2_OPCODE_ORN
:
22036 new_inst
= T2_OPCODE_ORR
;
22040 /* AND <-> BIC. TST has no inverted equivalent. */
22041 case T2_OPCODE_AND
:
22042 new_inst
= T2_OPCODE_BIC
;
22049 case T2_OPCODE_BIC
:
22050 new_inst
= T2_OPCODE_AND
;
22055 case T2_OPCODE_ADC
:
22056 new_inst
= T2_OPCODE_SBC
;
22060 case T2_OPCODE_SBC
:
22061 new_inst
= T2_OPCODE_ADC
;
22065 /* We cannot do anything. */
22070 if (value
== (unsigned int)FAIL
)
22073 *instruction
&= T2_OPCODE_MASK
;
22074 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
22078 /* Read a 32-bit thumb instruction from buf. */
22079 static unsigned long
22080 get_thumb32_insn (char * buf
)
22082 unsigned long insn
;
22083 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
22084 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22090 /* We usually want to set the low bit on the address of thumb function
22091 symbols. In particular .word foo - . should have the low bit set.
22092 Generic code tries to fold the difference of two symbols to
22093 a constant. Prevent this and force a relocation when the first symbols
22094 is a thumb function. */
22097 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
22099 if (op
== O_subtract
22100 && l
->X_op
== O_symbol
22101 && r
->X_op
== O_symbol
22102 && THUMB_IS_FUNC (l
->X_add_symbol
))
22104 l
->X_op
= O_subtract
;
22105 l
->X_op_symbol
= r
->X_add_symbol
;
22106 l
->X_add_number
-= r
->X_add_number
;
22110 /* Process as normal. */
22114 /* Encode Thumb2 unconditional branches and calls. The encoding
22115 for the 2 are identical for the immediate values. */
22118 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
22120 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22123 addressT S
, I1
, I2
, lo
, hi
;
22125 S
= (value
>> 24) & 0x01;
22126 I1
= (value
>> 23) & 0x01;
22127 I2
= (value
>> 22) & 0x01;
22128 hi
= (value
>> 12) & 0x3ff;
22129 lo
= (value
>> 1) & 0x7ff;
22130 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22131 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22132 newval
|= (S
<< 10) | hi
;
22133 newval2
&= ~T2I1I2MASK
;
22134 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
22135 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22136 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22140 md_apply_fix (fixS
* fixP
,
22144 offsetT value
= * valP
;
22146 unsigned int newimm
;
22147 unsigned long temp
;
22149 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
22151 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
22153 /* Note whether this will delete the relocation. */
22155 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
22158 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22159 consistency with the behaviour on 32-bit hosts. Remember value
22161 value
&= 0xffffffff;
22162 value
^= 0x80000000;
22163 value
-= 0x80000000;
22166 fixP
->fx_addnumber
= value
;
22168 /* Same treatment for fixP->fx_offset. */
22169 fixP
->fx_offset
&= 0xffffffff;
22170 fixP
->fx_offset
^= 0x80000000;
22171 fixP
->fx_offset
-= 0x80000000;
22173 switch (fixP
->fx_r_type
)
22175 case BFD_RELOC_NONE
:
22176 /* This will need to go in the object file. */
22180 case BFD_RELOC_ARM_IMMEDIATE
:
22181 /* We claim that this fixup has been processed here,
22182 even if in fact we generate an error because we do
22183 not have a reloc for it, so tc_gen_reloc will reject it. */
22186 if (fixP
->fx_addsy
)
22188 const char *msg
= 0;
22190 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22191 msg
= _("undefined symbol %s used as an immediate value");
22192 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22193 msg
= _("symbol %s is in a different section");
22194 else if (S_IS_WEAK (fixP
->fx_addsy
))
22195 msg
= _("symbol %s is weak and may be overridden later");
22199 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22200 msg
, S_GET_NAME (fixP
->fx_addsy
));
22205 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22207 /* If the offset is negative, we should use encoding A2 for ADR. */
22208 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
22209 newimm
= negate_data_op (&temp
, value
);
22212 newimm
= encode_arm_immediate (value
);
22214 /* If the instruction will fail, see if we can fix things up by
22215 changing the opcode. */
22216 if (newimm
== (unsigned int) FAIL
)
22217 newimm
= negate_data_op (&temp
, value
);
22220 if (newimm
== (unsigned int) FAIL
)
22222 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22223 _("invalid constant (%lx) after fixup"),
22224 (unsigned long) value
);
22228 newimm
|= (temp
& 0xfffff000);
22229 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22232 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22234 unsigned int highpart
= 0;
22235 unsigned int newinsn
= 0xe1a00000; /* nop. */
22237 if (fixP
->fx_addsy
)
22239 const char *msg
= 0;
22241 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22242 msg
= _("undefined symbol %s used as an immediate value");
22243 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22244 msg
= _("symbol %s is in a different section");
22245 else if (S_IS_WEAK (fixP
->fx_addsy
))
22246 msg
= _("symbol %s is weak and may be overridden later");
22250 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22251 msg
, S_GET_NAME (fixP
->fx_addsy
));
22256 newimm
= encode_arm_immediate (value
);
22257 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22259 /* If the instruction will fail, see if we can fix things up by
22260 changing the opcode. */
22261 if (newimm
== (unsigned int) FAIL
22262 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
22264 /* No ? OK - try using two ADD instructions to generate
22266 newimm
= validate_immediate_twopart (value
, & highpart
);
22268 /* Yes - then make sure that the second instruction is
22270 if (newimm
!= (unsigned int) FAIL
)
22272 /* Still No ? Try using a negated value. */
22273 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
22274 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
22275 /* Otherwise - give up. */
22278 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22279 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22284 /* Replace the first operand in the 2nd instruction (which
22285 is the PC) with the destination register. We have
22286 already added in the PC in the first instruction and we
22287 do not want to do it again. */
22288 newinsn
&= ~ 0xf0000;
22289 newinsn
|= ((newinsn
& 0x0f000) << 4);
22292 newimm
|= (temp
& 0xfffff000);
22293 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22295 highpart
|= (newinsn
& 0xfffff000);
22296 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
22300 case BFD_RELOC_ARM_OFFSET_IMM
:
22301 if (!fixP
->fx_done
&& seg
->use_rela_p
)
22304 case BFD_RELOC_ARM_LITERAL
:
22310 if (validate_offset_imm (value
, 0) == FAIL
)
22312 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
22313 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22314 _("invalid literal constant: pool needs to be closer"));
22316 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22317 _("bad immediate value for offset (%ld)"),
22322 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22324 newval
&= 0xfffff000;
22327 newval
&= 0xff7ff000;
22328 newval
|= value
| (sign
? INDEX_UP
: 0);
22330 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22333 case BFD_RELOC_ARM_OFFSET_IMM8
:
22334 case BFD_RELOC_ARM_HWLITERAL
:
22340 if (validate_offset_imm (value
, 1) == FAIL
)
22342 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
22343 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22344 _("invalid literal constant: pool needs to be closer"));
22346 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22347 _("bad immediate value for 8-bit offset (%ld)"),
22352 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22354 newval
&= 0xfffff0f0;
22357 newval
&= 0xff7ff0f0;
22358 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
22360 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22363 case BFD_RELOC_ARM_T32_OFFSET_U8
:
22364 if (value
< 0 || value
> 1020 || value
% 4 != 0)
22365 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22366 _("bad immediate value for offset (%ld)"), (long) value
);
22369 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
22371 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
22374 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22375 /* This is a complicated relocation used for all varieties of Thumb32
22376 load/store instruction with immediate offset:
22378 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
22379 *4, optional writeback(W)
22380 (doubleword load/store)
22382 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
22383 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
22384 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
22385 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
22386 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
22388 Uppercase letters indicate bits that are already encoded at
22389 this point. Lowercase letters are our problem. For the
22390 second block of instructions, the secondary opcode nybble
22391 (bits 8..11) is present, and bit 23 is zero, even if this is
22392 a PC-relative operation. */
22393 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22395 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
22397 if ((newval
& 0xf0000000) == 0xe0000000)
22399 /* Doubleword load/store: 8-bit offset, scaled by 4. */
22401 newval
|= (1 << 23);
22404 if (value
% 4 != 0)
22406 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22407 _("offset not a multiple of 4"));
22413 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22414 _("offset out of range"));
22419 else if ((newval
& 0x000f0000) == 0x000f0000)
22421 /* PC-relative, 12-bit offset. */
22423 newval
|= (1 << 23);
22428 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22429 _("offset out of range"));
22434 else if ((newval
& 0x00000100) == 0x00000100)
22436 /* Writeback: 8-bit, +/- offset. */
22438 newval
|= (1 << 9);
22443 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22444 _("offset out of range"));
22449 else if ((newval
& 0x00000f00) == 0x00000e00)
22451 /* T-instruction: positive 8-bit offset. */
22452 if (value
< 0 || value
> 0xff)
22454 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22455 _("offset out of range"));
22463 /* Positive 12-bit or negative 8-bit offset. */
22467 newval
|= (1 << 23);
22477 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22478 _("offset out of range"));
22485 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
22486 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
22489 case BFD_RELOC_ARM_SHIFT_IMM
:
22490 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22491 if (((unsigned long) value
) > 32
22493 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
22495 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22496 _("shift expression is too large"));
22501 /* Shifts of zero must be done as lsl. */
22503 else if (value
== 32)
22505 newval
&= 0xfffff07f;
22506 newval
|= (value
& 0x1f) << 7;
22507 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22510 case BFD_RELOC_ARM_T32_IMMEDIATE
:
22511 case BFD_RELOC_ARM_T32_ADD_IMM
:
22512 case BFD_RELOC_ARM_T32_IMM12
:
22513 case BFD_RELOC_ARM_T32_ADD_PC12
:
22514 /* We claim that this fixup has been processed here,
22515 even if in fact we generate an error because we do
22516 not have a reloc for it, so tc_gen_reloc will reject it. */
22520 && ! S_IS_DEFINED (fixP
->fx_addsy
))
22522 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22523 _("undefined symbol %s used as an immediate value"),
22524 S_GET_NAME (fixP
->fx_addsy
));
22528 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22530 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
22533 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
22534 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22536 newimm
= encode_thumb32_immediate (value
);
22537 if (newimm
== (unsigned int) FAIL
)
22538 newimm
= thumb32_negate_data_op (&newval
, value
);
22540 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
22541 && newimm
== (unsigned int) FAIL
)
22543 /* Turn add/sum into addw/subw. */
22544 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22545 newval
= (newval
& 0xfeffffff) | 0x02000000;
22546 /* No flat 12-bit imm encoding for addsw/subsw. */
22547 if ((newval
& 0x00100000) == 0)
22549 /* 12 bit immediate for addw/subw. */
22553 newval
^= 0x00a00000;
22556 newimm
= (unsigned int) FAIL
;
22562 if (newimm
== (unsigned int)FAIL
)
22564 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22565 _("invalid constant (%lx) after fixup"),
22566 (unsigned long) value
);
22570 newval
|= (newimm
& 0x800) << 15;
22571 newval
|= (newimm
& 0x700) << 4;
22572 newval
|= (newimm
& 0x0ff);
22574 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
22575 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
22578 case BFD_RELOC_ARM_SMC
:
22579 if (((unsigned long) value
) > 0xffff)
22580 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22581 _("invalid smc expression"));
22582 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22583 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22584 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22587 case BFD_RELOC_ARM_HVC
:
22588 if (((unsigned long) value
) > 0xffff)
22589 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22590 _("invalid hvc expression"));
22591 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22592 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22593 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22596 case BFD_RELOC_ARM_SWI
:
22597 if (fixP
->tc_fix_data
!= 0)
22599 if (((unsigned long) value
) > 0xff)
22600 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22601 _("invalid swi expression"));
22602 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22604 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22608 if (((unsigned long) value
) > 0x00ffffff)
22609 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22610 _("invalid swi expression"));
22611 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22613 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22617 case BFD_RELOC_ARM_MULTI
:
22618 if (((unsigned long) value
) > 0xffff)
22619 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22620 _("invalid expression in load/store multiple"));
22621 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
22622 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22626 case BFD_RELOC_ARM_PCREL_CALL
:
22628 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22630 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22631 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22632 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22633 /* Flip the bl to blx. This is a simple flip
22634 bit here because we generate PCREL_CALL for
22635 unconditional bls. */
22637 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22638 newval
= newval
| 0x10000000;
22639 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22645 goto arm_branch_common
;
22647 case BFD_RELOC_ARM_PCREL_JUMP
:
22648 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22650 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22651 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22652 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22654 /* This would map to a bl<cond>, b<cond>,
22655 b<always> to a Thumb function. We
22656 need to force a relocation for this particular
22658 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22662 case BFD_RELOC_ARM_PLT32
:
22664 case BFD_RELOC_ARM_PCREL_BRANCH
:
22666 goto arm_branch_common
;
22668 case BFD_RELOC_ARM_PCREL_BLX
:
22671 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22673 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22674 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22675 && ARM_IS_FUNC (fixP
->fx_addsy
))
22677 /* Flip the blx to a bl and warn. */
22678 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22679 newval
= 0xeb000000;
22680 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22681 _("blx to '%s' an ARM ISA state function changed to bl"),
22683 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22689 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
22690 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
22694 /* We are going to store value (shifted right by two) in the
22695 instruction, in a 24 bit, signed field. Bits 26 through 32 either
22696 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
22697 also be be clear. */
22699 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22700 _("misaligned branch destination"));
22701 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
22702 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
22703 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22705 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22707 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22708 newval
|= (value
>> 2) & 0x00ffffff;
22709 /* Set the H bit on BLX instructions. */
22713 newval
|= 0x01000000;
22715 newval
&= ~0x01000000;
22717 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22721 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
22722 /* CBZ can only branch forward. */
22724 /* Attempts to use CBZ to branch to the next instruction
22725 (which, strictly speaking, are prohibited) will be turned into
22728 FIXME: It may be better to remove the instruction completely and
22729 perform relaxation. */
22732 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22733 newval
= 0xbf00; /* NOP encoding T1 */
22734 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22739 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22741 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22743 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22744 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
22745 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22750 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
22751 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
22752 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22754 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22756 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22757 newval
|= (value
& 0x1ff) >> 1;
22758 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22762 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
22763 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
22764 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22766 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22768 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22769 newval
|= (value
& 0xfff) >> 1;
22770 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22774 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22776 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22777 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22778 && ARM_IS_FUNC (fixP
->fx_addsy
)
22779 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22781 /* Force a relocation for a branch 20 bits wide. */
22784 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
22785 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22786 _("conditional branch out of range"));
22788 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22791 addressT S
, J1
, J2
, lo
, hi
;
22793 S
= (value
& 0x00100000) >> 20;
22794 J2
= (value
& 0x00080000) >> 19;
22795 J1
= (value
& 0x00040000) >> 18;
22796 hi
= (value
& 0x0003f000) >> 12;
22797 lo
= (value
& 0x00000ffe) >> 1;
22799 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22800 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22801 newval
|= (S
<< 10) | hi
;
22802 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
22803 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22804 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22808 case BFD_RELOC_THUMB_PCREL_BLX
:
22809 /* If there is a blx from a thumb state function to
22810 another thumb function flip this to a bl and warn
22814 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22815 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22816 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22818 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22819 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22820 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
22822 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22823 newval
= newval
| 0x1000;
22824 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22825 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22830 goto thumb_bl_common
;
22832 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22833 /* A bl from Thumb state ISA to an internal ARM state function
22834 is converted to a blx. */
22836 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22837 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22838 && ARM_IS_FUNC (fixP
->fx_addsy
)
22839 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22841 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22842 newval
= newval
& ~0x1000;
22843 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22844 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
22850 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22851 /* For a BLX instruction, make sure that the relocation is rounded up
22852 to a word boundary. This follows the semantics of the instruction
22853 which specifies that bit 1 of the target address will come from bit
22854 1 of the base address. */
22855 value
= (value
+ 3) & ~ 3;
22858 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
22859 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22860 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22863 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
22865 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
22866 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22867 else if ((value
& ~0x1ffffff)
22868 && ((value
& ~0x1ffffff) != ~0x1ffffff))
22869 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22870 _("Thumb2 branch out of range"));
22873 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22874 encode_thumb2_b_bl_offset (buf
, value
);
22878 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22879 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
22880 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22882 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22883 encode_thumb2_b_bl_offset (buf
, value
);
22888 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22893 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22894 md_number_to_chars (buf
, value
, 2);
22898 case BFD_RELOC_ARM_TLS_CALL
:
22899 case BFD_RELOC_ARM_THM_TLS_CALL
:
22900 case BFD_RELOC_ARM_TLS_DESCSEQ
:
22901 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
22902 case BFD_RELOC_ARM_TLS_GOTDESC
:
22903 case BFD_RELOC_ARM_TLS_GD32
:
22904 case BFD_RELOC_ARM_TLS_LE32
:
22905 case BFD_RELOC_ARM_TLS_IE32
:
22906 case BFD_RELOC_ARM_TLS_LDM32
:
22907 case BFD_RELOC_ARM_TLS_LDO32
:
22908 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
22911 case BFD_RELOC_ARM_GOT32
:
22912 case BFD_RELOC_ARM_GOTOFF
:
22915 case BFD_RELOC_ARM_GOT_PREL
:
22916 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22917 md_number_to_chars (buf
, value
, 4);
22920 case BFD_RELOC_ARM_TARGET2
:
22921 /* TARGET2 is not partial-inplace, so we need to write the
22922 addend here for REL targets, because it won't be written out
22923 during reloc processing later. */
22924 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22925 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
22929 case BFD_RELOC_RVA
:
22931 case BFD_RELOC_ARM_TARGET1
:
22932 case BFD_RELOC_ARM_ROSEGREL32
:
22933 case BFD_RELOC_ARM_SBREL32
:
22934 case BFD_RELOC_32_PCREL
:
22936 case BFD_RELOC_32_SECREL
:
22938 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22940 /* For WinCE we only do this for pcrel fixups. */
22941 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
22943 md_number_to_chars (buf
, value
, 4);
22947 case BFD_RELOC_ARM_PREL31
:
22948 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22950 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
22951 if ((value
^ (value
>> 1)) & 0x40000000)
22953 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22954 _("rel31 relocation overflow"));
22956 newval
|= value
& 0x7fffffff;
22957 md_number_to_chars (buf
, newval
, 4);
22962 case BFD_RELOC_ARM_CP_OFF_IMM
:
22963 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22964 if (value
< -1023 || value
> 1023 || (value
& 3))
22965 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22966 _("co-processor offset out of range"));
22971 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22972 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
22973 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22975 newval
= get_thumb32_insn (buf
);
22977 newval
&= 0xffffff00;
22980 newval
&= 0xff7fff00;
22981 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
22983 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22984 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
22985 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22987 put_thumb32_insn (buf
, newval
);
22990 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
22991 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
22992 if (value
< -255 || value
> 255)
22993 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22994 _("co-processor offset out of range"));
22996 goto cp_off_common
;
22998 case BFD_RELOC_ARM_THUMB_OFFSET
:
22999 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23000 /* Exactly what ranges, and where the offset is inserted depends
23001 on the type of instruction, we can establish this from the
23003 switch (newval
>> 12)
23005 case 4: /* PC load. */
23006 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
23007 forced to zero for these loads; md_pcrel_from has already
23008 compensated for this. */
23010 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23011 _("invalid offset, target not word aligned (0x%08lX)"),
23012 (((unsigned long) fixP
->fx_frag
->fr_address
23013 + (unsigned long) fixP
->fx_where
) & ~3)
23014 + (unsigned long) value
);
23016 if (value
& ~0x3fc)
23017 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23018 _("invalid offset, value too big (0x%08lX)"),
23021 newval
|= value
>> 2;
23024 case 9: /* SP load/store. */
23025 if (value
& ~0x3fc)
23026 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23027 _("invalid offset, value too big (0x%08lX)"),
23029 newval
|= value
>> 2;
23032 case 6: /* Word load/store. */
23034 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23035 _("invalid offset, value too big (0x%08lX)"),
23037 newval
|= value
<< 4; /* 6 - 2. */
23040 case 7: /* Byte load/store. */
23042 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23043 _("invalid offset, value too big (0x%08lX)"),
23045 newval
|= value
<< 6;
23048 case 8: /* Halfword load/store. */
23050 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23051 _("invalid offset, value too big (0x%08lX)"),
23053 newval
|= value
<< 5; /* 6 - 1. */
23057 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23058 "Unable to process relocation for thumb opcode: %lx",
23059 (unsigned long) newval
);
23062 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23065 case BFD_RELOC_ARM_THUMB_ADD
:
23066 /* This is a complicated relocation, since we use it for all of
23067 the following immediate relocations:
23071 9bit ADD/SUB SP word-aligned
23072 10bit ADD PC/SP word-aligned
23074 The type of instruction being processed is encoded in the
23081 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23083 int rd
= (newval
>> 4) & 0xf;
23084 int rs
= newval
& 0xf;
23085 int subtract
= !!(newval
& 0x8000);
23087 /* Check for HI regs, only very restricted cases allowed:
23088 Adjusting SP, and using PC or SP to get an address. */
23089 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
23090 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
23091 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23092 _("invalid Hi register with immediate"));
23094 /* If value is negative, choose the opposite instruction. */
23098 subtract
= !subtract
;
23100 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23101 _("immediate value out of range"));
23106 if (value
& ~0x1fc)
23107 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23108 _("invalid immediate for stack address calculation"));
23109 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
23110 newval
|= value
>> 2;
23112 else if (rs
== REG_PC
|| rs
== REG_SP
)
23114 /* PR gas/18541. If the addition is for a defined symbol
23115 within range of an ADR instruction then accept it. */
23118 && fixP
->fx_addsy
!= NULL
)
23122 if (! S_IS_DEFINED (fixP
->fx_addsy
)
23123 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
23124 || S_IS_WEAK (fixP
->fx_addsy
))
23126 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23127 _("address calculation needs a strongly defined nearby symbol"));
23131 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23133 /* Round up to the next 4-byte boundary. */
23138 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
23142 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23143 _("symbol too far away"));
23153 if (subtract
|| value
& ~0x3fc)
23154 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23155 _("invalid immediate for address calculation (value = 0x%08lX)"),
23156 (unsigned long) (subtract
? - value
: value
));
23157 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
23159 newval
|= value
>> 2;
23164 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23165 _("immediate value out of range"));
23166 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
23167 newval
|= (rd
<< 8) | value
;
23172 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23173 _("immediate value out of range"));
23174 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
23175 newval
|= rd
| (rs
<< 3) | (value
<< 6);
23178 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23181 case BFD_RELOC_ARM_THUMB_IMM
:
23182 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23183 if (value
< 0 || value
> 255)
23184 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23185 _("invalid immediate: %ld is out of range"),
23188 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23191 case BFD_RELOC_ARM_THUMB_SHIFT
:
23192 /* 5bit shift value (0..32). LSL cannot take 32. */
23193 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
23194 temp
= newval
& 0xf800;
23195 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
23196 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23197 _("invalid shift value: %ld"), (long) value
);
23198 /* Shifts of zero must be encoded as LSL. */
23200 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
23201 /* Shifts of 32 are encoded as zero. */
23202 else if (value
== 32)
23204 newval
|= value
<< 6;
23205 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23208 case BFD_RELOC_VTABLE_INHERIT
:
23209 case BFD_RELOC_VTABLE_ENTRY
:
23213 case BFD_RELOC_ARM_MOVW
:
23214 case BFD_RELOC_ARM_MOVT
:
23215 case BFD_RELOC_ARM_THUMB_MOVW
:
23216 case BFD_RELOC_ARM_THUMB_MOVT
:
23217 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23219 /* REL format relocations are limited to a 16-bit addend. */
23220 if (!fixP
->fx_done
)
23222 if (value
< -0x8000 || value
> 0x7fff)
23223 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23224 _("offset out of range"));
23226 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23227 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23232 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23233 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23235 newval
= get_thumb32_insn (buf
);
23236 newval
&= 0xfbf08f00;
23237 newval
|= (value
& 0xf000) << 4;
23238 newval
|= (value
& 0x0800) << 15;
23239 newval
|= (value
& 0x0700) << 4;
23240 newval
|= (value
& 0x00ff);
23241 put_thumb32_insn (buf
, newval
);
23245 newval
= md_chars_to_number (buf
, 4);
23246 newval
&= 0xfff0f000;
23247 newval
|= value
& 0x0fff;
23248 newval
|= (value
& 0xf000) << 4;
23249 md_number_to_chars (buf
, newval
, 4);
23254 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23255 case BFD_RELOC_ARM_ALU_PC_G0
:
23256 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23257 case BFD_RELOC_ARM_ALU_PC_G1
:
23258 case BFD_RELOC_ARM_ALU_PC_G2
:
23259 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23260 case BFD_RELOC_ARM_ALU_SB_G0
:
23261 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23262 case BFD_RELOC_ARM_ALU_SB_G1
:
23263 case BFD_RELOC_ARM_ALU_SB_G2
:
23264 gas_assert (!fixP
->fx_done
);
23265 if (!seg
->use_rela_p
)
23268 bfd_vma encoded_addend
;
23269 bfd_vma addend_abs
= abs (value
);
23271 /* Check that the absolute value of the addend can be
23272 expressed as an 8-bit constant plus a rotation. */
23273 encoded_addend
= encode_arm_immediate (addend_abs
);
23274 if (encoded_addend
== (unsigned int) FAIL
)
23275 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23276 _("the offset 0x%08lX is not representable"),
23277 (unsigned long) addend_abs
);
23279 /* Extract the instruction. */
23280 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23282 /* If the addend is positive, use an ADD instruction.
23283 Otherwise use a SUB. Take care not to destroy the S bit. */
23284 insn
&= 0xff1fffff;
23290 /* Place the encoded addend into the first 12 bits of the
23292 insn
&= 0xfffff000;
23293 insn
|= encoded_addend
;
23295 /* Update the instruction. */
23296 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23300 case BFD_RELOC_ARM_LDR_PC_G0
:
23301 case BFD_RELOC_ARM_LDR_PC_G1
:
23302 case BFD_RELOC_ARM_LDR_PC_G2
:
23303 case BFD_RELOC_ARM_LDR_SB_G0
:
23304 case BFD_RELOC_ARM_LDR_SB_G1
:
23305 case BFD_RELOC_ARM_LDR_SB_G2
:
23306 gas_assert (!fixP
->fx_done
);
23307 if (!seg
->use_rela_p
)
23310 bfd_vma addend_abs
= abs (value
);
23312 /* Check that the absolute value of the addend can be
23313 encoded in 12 bits. */
23314 if (addend_abs
>= 0x1000)
23315 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23316 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
23317 (unsigned long) addend_abs
);
23319 /* Extract the instruction. */
23320 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23322 /* If the addend is negative, clear bit 23 of the instruction.
23323 Otherwise set it. */
23325 insn
&= ~(1 << 23);
23329 /* Place the absolute value of the addend into the first 12 bits
23330 of the instruction. */
23331 insn
&= 0xfffff000;
23332 insn
|= addend_abs
;
23334 /* Update the instruction. */
23335 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23339 case BFD_RELOC_ARM_LDRS_PC_G0
:
23340 case BFD_RELOC_ARM_LDRS_PC_G1
:
23341 case BFD_RELOC_ARM_LDRS_PC_G2
:
23342 case BFD_RELOC_ARM_LDRS_SB_G0
:
23343 case BFD_RELOC_ARM_LDRS_SB_G1
:
23344 case BFD_RELOC_ARM_LDRS_SB_G2
:
23345 gas_assert (!fixP
->fx_done
);
23346 if (!seg
->use_rela_p
)
23349 bfd_vma addend_abs
= abs (value
);
23351 /* Check that the absolute value of the addend can be
23352 encoded in 8 bits. */
23353 if (addend_abs
>= 0x100)
23354 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23355 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
23356 (unsigned long) addend_abs
);
23358 /* Extract the instruction. */
23359 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23361 /* If the addend is negative, clear bit 23 of the instruction.
23362 Otherwise set it. */
23364 insn
&= ~(1 << 23);
23368 /* Place the first four bits of the absolute value of the addend
23369 into the first 4 bits of the instruction, and the remaining
23370 four into bits 8 .. 11. */
23371 insn
&= 0xfffff0f0;
23372 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
23374 /* Update the instruction. */
23375 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23379 case BFD_RELOC_ARM_LDC_PC_G0
:
23380 case BFD_RELOC_ARM_LDC_PC_G1
:
23381 case BFD_RELOC_ARM_LDC_PC_G2
:
23382 case BFD_RELOC_ARM_LDC_SB_G0
:
23383 case BFD_RELOC_ARM_LDC_SB_G1
:
23384 case BFD_RELOC_ARM_LDC_SB_G2
:
23385 gas_assert (!fixP
->fx_done
);
23386 if (!seg
->use_rela_p
)
23389 bfd_vma addend_abs
= abs (value
);
23391 /* Check that the absolute value of the addend is a multiple of
23392 four and, when divided by four, fits in 8 bits. */
23393 if (addend_abs
& 0x3)
23394 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23395 _("bad offset 0x%08lX (must be word-aligned)"),
23396 (unsigned long) addend_abs
);
23398 if ((addend_abs
>> 2) > 0xff)
23399 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23400 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
23401 (unsigned long) addend_abs
);
23403 /* Extract the instruction. */
23404 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23406 /* If the addend is negative, clear bit 23 of the instruction.
23407 Otherwise set it. */
23409 insn
&= ~(1 << 23);
23413 /* Place the addend (divided by four) into the first eight
23414 bits of the instruction. */
23415 insn
&= 0xfffffff0;
23416 insn
|= addend_abs
>> 2;
23418 /* Update the instruction. */
23419 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23423 case BFD_RELOC_ARM_V4BX
:
23424 /* This will need to go in the object file. */
23428 case BFD_RELOC_UNUSED
:
23430 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23431 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
23435 /* Translate internal representation of relocation info to BFD target
23439 tc_gen_reloc (asection
*section
, fixS
*fixp
)
23442 bfd_reloc_code_real_type code
;
23444 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
23446 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
23447 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
23448 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
23450 if (fixp
->fx_pcrel
)
23452 if (section
->use_rela_p
)
23453 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
23455 fixp
->fx_offset
= reloc
->address
;
23457 reloc
->addend
= fixp
->fx_offset
;
23459 switch (fixp
->fx_r_type
)
23462 if (fixp
->fx_pcrel
)
23464 code
= BFD_RELOC_8_PCREL
;
23469 if (fixp
->fx_pcrel
)
23471 code
= BFD_RELOC_16_PCREL
;
23476 if (fixp
->fx_pcrel
)
23478 code
= BFD_RELOC_32_PCREL
;
23482 case BFD_RELOC_ARM_MOVW
:
23483 if (fixp
->fx_pcrel
)
23485 code
= BFD_RELOC_ARM_MOVW_PCREL
;
23489 case BFD_RELOC_ARM_MOVT
:
23490 if (fixp
->fx_pcrel
)
23492 code
= BFD_RELOC_ARM_MOVT_PCREL
;
23496 case BFD_RELOC_ARM_THUMB_MOVW
:
23497 if (fixp
->fx_pcrel
)
23499 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
23503 case BFD_RELOC_ARM_THUMB_MOVT
:
23504 if (fixp
->fx_pcrel
)
23506 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
23510 case BFD_RELOC_NONE
:
23511 case BFD_RELOC_ARM_PCREL_BRANCH
:
23512 case BFD_RELOC_ARM_PCREL_BLX
:
23513 case BFD_RELOC_RVA
:
23514 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
23515 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
23516 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
23517 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23518 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23519 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23520 case BFD_RELOC_VTABLE_ENTRY
:
23521 case BFD_RELOC_VTABLE_INHERIT
:
23523 case BFD_RELOC_32_SECREL
:
23525 code
= fixp
->fx_r_type
;
23528 case BFD_RELOC_THUMB_PCREL_BLX
:
23530 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23531 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23534 code
= BFD_RELOC_THUMB_PCREL_BLX
;
23537 case BFD_RELOC_ARM_LITERAL
:
23538 case BFD_RELOC_ARM_HWLITERAL
:
23539 /* If this is called then the a literal has
23540 been referenced across a section boundary. */
23541 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23542 _("literal referenced across section boundary"));
23546 case BFD_RELOC_ARM_TLS_CALL
:
23547 case BFD_RELOC_ARM_THM_TLS_CALL
:
23548 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23549 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23550 case BFD_RELOC_ARM_GOT32
:
23551 case BFD_RELOC_ARM_GOTOFF
:
23552 case BFD_RELOC_ARM_GOT_PREL
:
23553 case BFD_RELOC_ARM_PLT32
:
23554 case BFD_RELOC_ARM_TARGET1
:
23555 case BFD_RELOC_ARM_ROSEGREL32
:
23556 case BFD_RELOC_ARM_SBREL32
:
23557 case BFD_RELOC_ARM_PREL31
:
23558 case BFD_RELOC_ARM_TARGET2
:
23559 case BFD_RELOC_ARM_TLS_LDO32
:
23560 case BFD_RELOC_ARM_PCREL_CALL
:
23561 case BFD_RELOC_ARM_PCREL_JUMP
:
23562 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23563 case BFD_RELOC_ARM_ALU_PC_G0
:
23564 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23565 case BFD_RELOC_ARM_ALU_PC_G1
:
23566 case BFD_RELOC_ARM_ALU_PC_G2
:
23567 case BFD_RELOC_ARM_LDR_PC_G0
:
23568 case BFD_RELOC_ARM_LDR_PC_G1
:
23569 case BFD_RELOC_ARM_LDR_PC_G2
:
23570 case BFD_RELOC_ARM_LDRS_PC_G0
:
23571 case BFD_RELOC_ARM_LDRS_PC_G1
:
23572 case BFD_RELOC_ARM_LDRS_PC_G2
:
23573 case BFD_RELOC_ARM_LDC_PC_G0
:
23574 case BFD_RELOC_ARM_LDC_PC_G1
:
23575 case BFD_RELOC_ARM_LDC_PC_G2
:
23576 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23577 case BFD_RELOC_ARM_ALU_SB_G0
:
23578 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23579 case BFD_RELOC_ARM_ALU_SB_G1
:
23580 case BFD_RELOC_ARM_ALU_SB_G2
:
23581 case BFD_RELOC_ARM_LDR_SB_G0
:
23582 case BFD_RELOC_ARM_LDR_SB_G1
:
23583 case BFD_RELOC_ARM_LDR_SB_G2
:
23584 case BFD_RELOC_ARM_LDRS_SB_G0
:
23585 case BFD_RELOC_ARM_LDRS_SB_G1
:
23586 case BFD_RELOC_ARM_LDRS_SB_G2
:
23587 case BFD_RELOC_ARM_LDC_SB_G0
:
23588 case BFD_RELOC_ARM_LDC_SB_G1
:
23589 case BFD_RELOC_ARM_LDC_SB_G2
:
23590 case BFD_RELOC_ARM_V4BX
:
23591 code
= fixp
->fx_r_type
;
23594 case BFD_RELOC_ARM_TLS_GOTDESC
:
23595 case BFD_RELOC_ARM_TLS_GD32
:
23596 case BFD_RELOC_ARM_TLS_LE32
:
23597 case BFD_RELOC_ARM_TLS_IE32
:
23598 case BFD_RELOC_ARM_TLS_LDM32
:
23599 /* BFD will include the symbol's address in the addend.
23600 But we don't want that, so subtract it out again here. */
23601 if (!S_IS_COMMON (fixp
->fx_addsy
))
23602 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
23603 code
= fixp
->fx_r_type
;
23607 case BFD_RELOC_ARM_IMMEDIATE
:
23608 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23609 _("internal relocation (type: IMMEDIATE) not fixed up"));
23612 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
23613 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23614 _("ADRL used for a symbol not defined in the same file"));
23617 case BFD_RELOC_ARM_OFFSET_IMM
:
23618 if (section
->use_rela_p
)
23620 code
= fixp
->fx_r_type
;
23624 if (fixp
->fx_addsy
!= NULL
23625 && !S_IS_DEFINED (fixp
->fx_addsy
)
23626 && S_IS_LOCAL (fixp
->fx_addsy
))
23628 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23629 _("undefined local label `%s'"),
23630 S_GET_NAME (fixp
->fx_addsy
));
23634 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23635 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
23642 switch (fixp
->fx_r_type
)
23644 case BFD_RELOC_NONE
: type
= "NONE"; break;
23645 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
23646 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
23647 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
23648 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
23649 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
23650 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
23651 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
23652 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
23653 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
23654 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
23655 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
23656 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
23657 default: type
= _("<unknown>"); break;
23659 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23660 _("cannot represent %s relocation in this object file format"),
23667 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
23669 && fixp
->fx_addsy
== GOT_symbol
)
23671 code
= BFD_RELOC_ARM_GOTPC
;
23672 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
23676 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
23678 if (reloc
->howto
== NULL
)
23680 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23681 _("cannot represent %s relocation in this object file format"),
23682 bfd_get_reloc_code_name (code
));
23686 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
23687 vtable entry to be used in the relocation's section offset. */
23688 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23689 reloc
->address
= fixp
->fx_offset
;
23694 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
23697 cons_fix_new_arm (fragS
* frag
,
23701 bfd_reloc_code_real_type reloc
)
23706 FIXME: @@ Should look at CPU word size. */
23710 reloc
= BFD_RELOC_8
;
23713 reloc
= BFD_RELOC_16
;
23717 reloc
= BFD_RELOC_32
;
23720 reloc
= BFD_RELOC_64
;
23725 if (exp
->X_op
== O_secrel
)
23727 exp
->X_op
= O_symbol
;
23728 reloc
= BFD_RELOC_32_SECREL
;
23732 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
23735 #if defined (OBJ_COFF)
23737 arm_validate_fix (fixS
* fixP
)
23739 /* If the destination of the branch is a defined symbol which does not have
23740 the THUMB_FUNC attribute, then we must be calling a function which has
23741 the (interfacearm) attribute. We look for the Thumb entry point to that
23742 function and change the branch to refer to that function instead. */
23743 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
23744 && fixP
->fx_addsy
!= NULL
23745 && S_IS_DEFINED (fixP
->fx_addsy
)
23746 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
23748 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
23755 arm_force_relocation (struct fix
* fixp
)
23757 #if defined (OBJ_COFF) && defined (TE_PE)
23758 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
23762 /* In case we have a call or a branch to a function in ARM ISA mode from
23763 a thumb function or vice-versa force the relocation. These relocations
23764 are cleared off for some cores that might have blx and simple transformations
23768 switch (fixp
->fx_r_type
)
23770 case BFD_RELOC_ARM_PCREL_JUMP
:
23771 case BFD_RELOC_ARM_PCREL_CALL
:
23772 case BFD_RELOC_THUMB_PCREL_BLX
:
23773 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
23777 case BFD_RELOC_ARM_PCREL_BLX
:
23778 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23779 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23780 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23781 if (ARM_IS_FUNC (fixp
->fx_addsy
))
23790 /* Resolve these relocations even if the symbol is extern or weak.
23791 Technically this is probably wrong due to symbol preemption.
23792 In practice these relocations do not have enough range to be useful
23793 at dynamic link time, and some code (e.g. in the Linux kernel)
23794 expects these references to be resolved. */
23795 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
23796 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
23797 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
23798 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
23799 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23800 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
23801 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
23802 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
23803 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23804 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
23805 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
23806 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
23807 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
23808 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
23811 /* Always leave these relocations for the linker. */
23812 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23813 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23814 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23817 /* Always generate relocations against function symbols. */
23818 if (fixp
->fx_r_type
== BFD_RELOC_32
23820 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
23823 return generic_force_reloc (fixp
);
23826 #if defined (OBJ_ELF) || defined (OBJ_COFF)
23827 /* Relocations against function names must be left unadjusted,
23828 so that the linker can use this information to generate interworking
23829 stubs. The MIPS version of this function
23830 also prevents relocations that are mips-16 specific, but I do not
23831 know why it does this.
23834 There is one other problem that ought to be addressed here, but
23835 which currently is not: Taking the address of a label (rather
23836 than a function) and then later jumping to that address. Such
23837 addresses also ought to have their bottom bit set (assuming that
23838 they reside in Thumb code), but at the moment they will not. */
23841 arm_fix_adjustable (fixS
* fixP
)
23843 if (fixP
->fx_addsy
== NULL
)
23846 /* Preserve relocations against symbols with function type. */
23847 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
23850 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
23851 && fixP
->fx_subsy
== NULL
)
23854 /* We need the symbol name for the VTABLE entries. */
23855 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
23856 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23859 /* Don't allow symbols to be discarded on GOT related relocs. */
23860 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
23861 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
23862 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
23863 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
23864 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
23865 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
23866 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
23867 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
23868 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
23869 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
23870 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
23871 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
23872 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
23873 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
23876 /* Similarly for group relocations. */
23877 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23878 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23879 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23882 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
23883 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
23884 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23885 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
23886 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
23887 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23888 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
23889 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
23890 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
23895 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
23900 elf32_arm_target_format (void)
23903 return (target_big_endian
23904 ? "elf32-bigarm-symbian"
23905 : "elf32-littlearm-symbian");
23906 #elif defined (TE_VXWORKS)
23907 return (target_big_endian
23908 ? "elf32-bigarm-vxworks"
23909 : "elf32-littlearm-vxworks");
23910 #elif defined (TE_NACL)
23911 return (target_big_endian
23912 ? "elf32-bigarm-nacl"
23913 : "elf32-littlearm-nacl");
23915 if (target_big_endian
)
23916 return "elf32-bigarm";
23918 return "elf32-littlearm";
23923 armelf_frob_symbol (symbolS
* symp
,
23926 elf_frob_symbol (symp
, puntp
);
23930 /* MD interface: Finalization. */
23935 literal_pool
* pool
;
23937 /* Ensure that all the IT blocks are properly closed. */
23938 check_it_blocks_finished ();
23940 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
23942 /* Put it at the end of the relevant section. */
23943 subseg_set (pool
->section
, pool
->sub_section
);
23945 arm_elf_change_section ();
23952 /* Remove any excess mapping symbols generated for alignment frags in
23953 SEC. We may have created a mapping symbol before a zero byte
23954 alignment; remove it if there's a mapping symbol after the
23957 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
23958 void *dummy ATTRIBUTE_UNUSED
)
23960 segment_info_type
*seginfo
= seg_info (sec
);
23963 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
23966 for (fragp
= seginfo
->frchainP
->frch_root
;
23968 fragp
= fragp
->fr_next
)
23970 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
23971 fragS
*next
= fragp
->fr_next
;
23973 /* Variable-sized frags have been converted to fixed size by
23974 this point. But if this was variable-sized to start with,
23975 there will be a fixed-size frag after it. So don't handle
23977 if (sym
== NULL
|| next
== NULL
)
23980 if (S_GET_VALUE (sym
) < next
->fr_address
)
23981 /* Not at the end of this frag. */
23983 know (S_GET_VALUE (sym
) == next
->fr_address
);
23987 if (next
->tc_frag_data
.first_map
!= NULL
)
23989 /* Next frag starts with a mapping symbol. Discard this
23991 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
23995 if (next
->fr_next
== NULL
)
23997 /* This mapping symbol is at the end of the section. Discard
23999 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
24000 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24004 /* As long as we have empty frags without any mapping symbols,
24006 /* If the next frag is non-empty and does not start with a
24007 mapping symbol, then this mapping symbol is required. */
24008 if (next
->fr_address
!= next
->fr_next
->fr_address
)
24011 next
= next
->fr_next
;
24013 while (next
!= NULL
);
24018 /* Adjust the symbol table. This marks Thumb symbols as distinct from
24022 arm_adjust_symtab (void)
24027 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24029 if (ARM_IS_THUMB (sym
))
24031 if (THUMB_IS_FUNC (sym
))
24033 /* Mark the symbol as a Thumb function. */
24034 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
24035 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
24036 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
24038 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
24039 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
24041 as_bad (_("%s: unexpected function type: %d"),
24042 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
24044 else switch (S_GET_STORAGE_CLASS (sym
))
24047 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
24050 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
24053 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
24061 if (ARM_IS_INTERWORK (sym
))
24062 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
24069 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24071 if (ARM_IS_THUMB (sym
))
24073 elf_symbol_type
* elf_sym
;
24075 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
24076 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
24078 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
24079 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
24081 /* If it's a .thumb_func, declare it as so,
24082 otherwise tag label as .code 16. */
24083 if (THUMB_IS_FUNC (sym
))
24084 elf_sym
->internal_elf_sym
.st_target_internal
24085 = ST_BRANCH_TO_THUMB
;
24086 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
24087 elf_sym
->internal_elf_sym
.st_info
=
24088 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
24093 /* Remove any overlapping mapping symbols generated by alignment frags. */
24094 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
24095 /* Now do generic ELF adjustments. */
24096 elf_adjust_symtab ();
24100 /* MD interface: Initialization. */
24103 set_constant_flonums (void)
24107 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
24108 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
24112 /* Auto-select Thumb mode if it's the only available instruction set for the
24113 given architecture. */
24116 autoselect_thumb_from_cpu_variant (void)
24118 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
24119 opcode_select (16);
24128 if ( (arm_ops_hsh
= hash_new ()) == NULL
24129 || (arm_cond_hsh
= hash_new ()) == NULL
24130 || (arm_shift_hsh
= hash_new ()) == NULL
24131 || (arm_psr_hsh
= hash_new ()) == NULL
24132 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
24133 || (arm_reg_hsh
= hash_new ()) == NULL
24134 || (arm_reloc_hsh
= hash_new ()) == NULL
24135 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
24136 as_fatal (_("virtual memory exhausted"));
24138 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
24139 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
24140 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
24141 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
24142 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
24143 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
24144 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
24145 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
24146 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
24147 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
24148 (void *) (v7m_psrs
+ i
));
24149 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
24150 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
24152 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
24154 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
24155 (void *) (barrier_opt_names
+ i
));
24157 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
24159 struct reloc_entry
* entry
= reloc_names
+ i
;
24161 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
24162 /* This makes encode_branch() use the EABI versions of this relocation. */
24163 entry
->reloc
= BFD_RELOC_UNUSED
;
24165 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
24169 set_constant_flonums ();
24171 /* Set the cpu variant based on the command-line options. We prefer
24172 -mcpu= over -march= if both are set (as for GCC); and we prefer
24173 -mfpu= over any other way of setting the floating point unit.
24174 Use of legacy options with new options are faulted. */
24177 if (mcpu_cpu_opt
|| march_cpu_opt
)
24178 as_bad (_("use of old and new-style options to set CPU type"));
24180 mcpu_cpu_opt
= legacy_cpu
;
24182 else if (!mcpu_cpu_opt
)
24183 mcpu_cpu_opt
= march_cpu_opt
;
24188 as_bad (_("use of old and new-style options to set FPU type"));
24190 mfpu_opt
= legacy_fpu
;
24192 else if (!mfpu_opt
)
24194 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
24195 || defined (TE_NetBSD) || defined (TE_VXWORKS))
24196 /* Some environments specify a default FPU. If they don't, infer it
24197 from the processor. */
24199 mfpu_opt
= mcpu_fpu_opt
;
24201 mfpu_opt
= march_fpu_opt
;
24203 mfpu_opt
= &fpu_default
;
24209 if (mcpu_cpu_opt
!= NULL
)
24210 mfpu_opt
= &fpu_default
;
24211 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
24212 mfpu_opt
= &fpu_arch_vfp_v2
;
24214 mfpu_opt
= &fpu_arch_fpa
;
24220 mcpu_cpu_opt
= &cpu_default
;
24221 selected_cpu
= cpu_default
;
24223 else if (no_cpu_selected ())
24224 selected_cpu
= cpu_default
;
24227 selected_cpu
= *mcpu_cpu_opt
;
24229 mcpu_cpu_opt
= &arm_arch_any
;
24232 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24234 autoselect_thumb_from_cpu_variant ();
24236 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
24238 #if defined OBJ_COFF || defined OBJ_ELF
24240 unsigned int flags
= 0;
24242 #if defined OBJ_ELF
24243 flags
= meabi_flags
;
24245 switch (meabi_flags
)
24247 case EF_ARM_EABI_UNKNOWN
:
24249 /* Set the flags in the private structure. */
24250 if (uses_apcs_26
) flags
|= F_APCS26
;
24251 if (support_interwork
) flags
|= F_INTERWORK
;
24252 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
24253 if (pic_code
) flags
|= F_PIC
;
24254 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
24255 flags
|= F_SOFT_FLOAT
;
24257 switch (mfloat_abi_opt
)
24259 case ARM_FLOAT_ABI_SOFT
:
24260 case ARM_FLOAT_ABI_SOFTFP
:
24261 flags
|= F_SOFT_FLOAT
;
24264 case ARM_FLOAT_ABI_HARD
:
24265 if (flags
& F_SOFT_FLOAT
)
24266 as_bad (_("hard-float conflicts with specified fpu"));
24270 /* Using pure-endian doubles (even if soft-float). */
24271 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
24272 flags
|= F_VFP_FLOAT
;
24274 #if defined OBJ_ELF
24275 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
24276 flags
|= EF_ARM_MAVERICK_FLOAT
;
24279 case EF_ARM_EABI_VER4
:
24280 case EF_ARM_EABI_VER5
:
24281 /* No additional flags to set. */
24288 bfd_set_private_flags (stdoutput
, flags
);
24290 /* We have run out flags in the COFF header to encode the
24291 status of ATPCS support, so instead we create a dummy,
24292 empty, debug section called .arm.atpcs. */
24297 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
24301 bfd_set_section_flags
24302 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
24303 bfd_set_section_size (stdoutput
, sec
, 0);
24304 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
24310 /* Record the CPU type as well. */
24311 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
24312 mach
= bfd_mach_arm_iWMMXt2
;
24313 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
24314 mach
= bfd_mach_arm_iWMMXt
;
24315 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
24316 mach
= bfd_mach_arm_XScale
;
24317 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
24318 mach
= bfd_mach_arm_ep9312
;
24319 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
24320 mach
= bfd_mach_arm_5TE
;
24321 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
24323 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24324 mach
= bfd_mach_arm_5T
;
24326 mach
= bfd_mach_arm_5
;
24328 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
24330 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24331 mach
= bfd_mach_arm_4T
;
24333 mach
= bfd_mach_arm_4
;
24335 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
24336 mach
= bfd_mach_arm_3M
;
24337 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
24338 mach
= bfd_mach_arm_3
;
24339 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
24340 mach
= bfd_mach_arm_2a
;
24341 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
24342 mach
= bfd_mach_arm_2
;
24344 mach
= bfd_mach_arm_unknown
;
24346 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
24349 /* Command line processing. */
24352 Invocation line includes a switch not recognized by the base assembler.
24353 See if it's a processor-specific option.
24355 This routine is somewhat complicated by the need for backwards
24356 compatibility (since older releases of gcc can't be changed).
24357 The new options try to make the interface as compatible as
24360 New options (supported) are:
24362 -mcpu=<cpu name> Assemble for selected processor
24363 -march=<architecture name> Assemble for selected architecture
24364 -mfpu=<fpu architecture> Assemble for selected FPU.
24365 -EB/-mbig-endian Big-endian
24366 -EL/-mlittle-endian Little-endian
24367 -k Generate PIC code
24368 -mthumb Start in Thumb mode
24369 -mthumb-interwork Code supports ARM/Thumb interworking
24371 -m[no-]warn-deprecated Warn about deprecated features
24372 -m[no-]warn-syms Warn when symbols match instructions
24374 For now we will also provide support for:
24376 -mapcs-32 32-bit Program counter
24377 -mapcs-26 26-bit Program counter
24378 -macps-float Floats passed in FP registers
24379 -mapcs-reentrant Reentrant code
24381 (sometime these will probably be replaced with -mapcs=<list of options>
24382 and -matpcs=<list of options>)
24384 The remaining options are only supported for back-wards compatibility.
24385 Cpu variants, the arm part is optional:
24386 -m[arm]1 Currently not supported.
24387 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
24388 -m[arm]3 Arm 3 processor
24389 -m[arm]6[xx], Arm 6 processors
24390 -m[arm]7[xx][t][[d]m] Arm 7 processors
24391 -m[arm]8[10] Arm 8 processors
24392 -m[arm]9[20][tdmi] Arm 9 processors
24393 -mstrongarm[110[0]] StrongARM processors
24394 -mxscale XScale processors
24395 -m[arm]v[2345[t[e]]] Arm architectures
24396 -mall All (except the ARM1)
24398 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
24399 -mfpe-old (No float load/store multiples)
24400 -mvfpxd VFP Single precision
24402 -mno-fpu Disable all floating point instructions
24404 The following CPU names are recognized:
24405 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
24406 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
24407 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
24408 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
24409 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
24410 arm10t arm10e, arm1020t, arm1020e, arm10200e,
24411 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
24415 const char * md_shortopts
= "m:k";
24417 #ifdef ARM_BI_ENDIAN
24418 #define OPTION_EB (OPTION_MD_BASE + 0)
24419 #define OPTION_EL (OPTION_MD_BASE + 1)
24421 #if TARGET_BYTES_BIG_ENDIAN
24422 #define OPTION_EB (OPTION_MD_BASE + 0)
24424 #define OPTION_EL (OPTION_MD_BASE + 1)
24427 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
24429 struct option md_longopts
[] =
24432 {"EB", no_argument
, NULL
, OPTION_EB
},
24435 {"EL", no_argument
, NULL
, OPTION_EL
},
24437 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
24438 {NULL
, no_argument
, NULL
, 0}
24442 size_t md_longopts_size
= sizeof (md_longopts
);
24444 struct arm_option_table
24446 char *option
; /* Option name to match. */
24447 char *help
; /* Help information. */
24448 int *var
; /* Variable to change. */
24449 int value
; /* What to change it to. */
24450 char *deprecated
; /* If non-null, print this message. */
24453 struct arm_option_table arm_opts
[] =
24455 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
24456 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
24457 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
24458 &support_interwork
, 1, NULL
},
24459 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
24460 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
24461 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
24463 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
24464 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
24465 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
24466 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
24469 /* These are recognized by the assembler, but have no affect on code. */
24470 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
24471 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
24473 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
24474 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
24475 &warn_on_deprecated
, 0, NULL
},
24476 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
24477 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
24478 {NULL
, NULL
, NULL
, 0, NULL
}
24481 struct arm_legacy_option_table
24483 char *option
; /* Option name to match. */
24484 const arm_feature_set
**var
; /* Variable to change. */
24485 const arm_feature_set value
; /* What to change it to. */
24486 char *deprecated
; /* If non-null, print this message. */
24489 const struct arm_legacy_option_table arm_legacy_opts
[] =
24491 /* DON'T add any new processors to this list -- we want the whole list
24492 to go away... Add them to the processors table instead. */
24493 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
24494 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
24495 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
24496 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
24497 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
24498 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
24499 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
24500 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
24501 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
24502 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
24503 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
24504 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
24505 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
24506 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
24507 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
24508 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
24509 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
24510 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
24511 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
24512 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
24513 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
24514 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
24515 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
24516 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
24517 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
24518 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
24519 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
24520 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
24521 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
24522 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
24523 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
24524 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
24525 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
24526 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
24527 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
24528 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
24529 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
24530 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
24531 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
24532 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
24533 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
24534 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
24535 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
24536 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
24537 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
24538 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
24539 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24540 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24541 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24542 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24543 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
24544 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
24545 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
24546 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
24547 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
24548 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
24549 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
24550 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
24551 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
24552 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
24553 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
24554 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
24555 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
24556 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
24557 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
24558 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
24559 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
24560 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
24561 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
24562 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
24563 N_("use -mcpu=strongarm110")},
24564 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
24565 N_("use -mcpu=strongarm1100")},
24566 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
24567 N_("use -mcpu=strongarm1110")},
24568 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
24569 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
24570 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
24572 /* Architecture variants -- don't add any more to this list either. */
24573 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
24574 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
24575 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
24576 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
24577 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
24578 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
24579 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
24580 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
24581 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
24582 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
24583 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
24584 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
24585 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
24586 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
24587 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
24588 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
24589 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
24590 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
24592 /* Floating point variants -- don't add any more to this list either. */
24593 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
24594 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
24595 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
24596 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
24597 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
24599 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
24602 struct arm_cpu_option_table
24606 const arm_feature_set value
;
24607 /* For some CPUs we assume an FPU unless the user explicitly sets
24609 const arm_feature_set default_fpu
;
24610 /* The canonical name of the CPU, or NULL to use NAME converted to upper
24612 const char *canonical_name
;
24615 /* This list should, at a minimum, contain all the cpu names
24616 recognized by GCC. */
24617 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
24618 static const struct arm_cpu_option_table arm_cpus
[] =
24620 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
24621 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
24622 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
24623 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
24624 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
24625 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24626 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24627 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24628 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24629 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24630 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24631 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24632 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24633 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24634 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24635 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24636 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24637 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24638 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24639 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24640 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24641 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24642 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24643 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24644 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24645 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24646 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24647 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24648 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24649 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24650 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24651 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24652 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24653 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24654 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24655 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24656 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24657 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24658 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24659 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
24660 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24661 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24662 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24663 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24664 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24665 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24666 /* For V5 or later processors we default to using VFP; but the user
24667 should really set the FPU type explicitly. */
24668 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24669 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24670 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
24671 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
24672 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
24673 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24674 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
24675 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24676 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24677 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
24678 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24679 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24680 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24681 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24682 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24683 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
24684 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24685 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24686 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24687 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
24689 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
24690 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24691 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24692 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24693 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24694 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24695 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
24696 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
24697 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
24699 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
24700 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
24701 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
24702 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
24703 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
24704 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6KZ
, FPU_NONE
, NULL
),
24705 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6KZ
, FPU_ARCH_VFP_V2
, NULL
),
24706 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
24707 FPU_NONE
, "Cortex-A5"),
24708 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24710 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
24711 ARM_FEATURE_COPROC (FPU_VFP_V3
24712 | FPU_NEON_EXT_V1
),
24714 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
24715 ARM_FEATURE_COPROC (FPU_VFP_V3
24716 | FPU_NEON_EXT_V1
),
24718 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24720 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24722 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24724 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24726 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24728 ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24730 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
24731 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
24733 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
24734 FPU_NONE
, "Cortex-R5"),
24735 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV
,
24736 FPU_ARCH_VFP_V3D16
,
24738 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M7"),
24739 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
24740 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
24741 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
24742 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
24743 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
24744 ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24747 /* ??? XSCALE is really an architecture. */
24748 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
24749 /* ??? iwmmxt is not a processor. */
24750 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
24751 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
24752 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
24754 ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
24755 FPU_ARCH_MAVERICK
, "ARM920T"),
24756 /* Marvell processors. */
24757 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A
| ARM_EXT_MP
24759 FPU_ARCH_VFP_V3D16
, NULL
),
24760 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A
| ARM_EXT_MP
24762 FPU_ARCH_NEON_VFP_V4
, NULL
),
24763 /* APM X-Gene family. */
24764 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24766 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24769 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
24773 struct arm_arch_option_table
24777 const arm_feature_set value
;
24778 const arm_feature_set default_fpu
;
24781 /* This list should, at a minimum, contain all the architecture names
24782 recognized by GCC. */
24783 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
24784 static const struct arm_arch_option_table arm_archs
[] =
24786 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
24787 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
24788 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
24789 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
24790 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
24791 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
24792 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
24793 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
24794 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
24795 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
24796 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
24797 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
24798 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
24799 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
24800 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
24801 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
24802 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
24803 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
24804 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
24805 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
24806 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
24807 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
24808 kept to preserve existing behaviour. */
24809 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
24810 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
24811 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
24812 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
24813 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
24814 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
24815 kept to preserve existing behaviour. */
24816 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
24817 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
24818 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
24819 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
24820 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
24821 /* The official spelling of the ARMv7 profile variants is the dashed form.
24822 Accept the non-dashed form for compatibility with old toolchains. */
24823 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
24824 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
24825 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
24826 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
24827 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
24828 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
24829 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
24830 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
24831 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
24832 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
24833 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
24834 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
24835 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
24836 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
24838 #undef ARM_ARCH_OPT
24840 /* ISA extensions in the co-processor and main instruction set space. */
24841 struct arm_option_extension_value_table
24845 const arm_feature_set merge_value
;
24846 const arm_feature_set clear_value
;
24847 const arm_feature_set allowed_archs
;
24850 /* The following table must be in alphabetical order with a NULL last entry.
24852 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, AA }
24853 static const struct arm_option_extension_value_table arm_extensions
[] =
24855 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
24856 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24857 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24858 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
24859 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24860 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
24861 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24862 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
24863 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
24864 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
| ARM_EXT_V7R
)),
24865 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
24866 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ANY
),
24867 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
24868 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ANY
),
24869 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
24870 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ANY
),
24871 ARM_EXT_OPT ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
24872 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
24873 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
| ARM_EXT_V7R
)),
24874 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
24875 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
24876 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24877 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
24878 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
24879 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
24880 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
24881 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
24882 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24883 ARM_EXT_OPT ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
24884 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
24885 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V7A
)),
24886 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
24888 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
24889 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
24890 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8
,
24891 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
24892 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24893 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
24894 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ANY
),
24895 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
24899 /* ISA floating-point and Advanced SIMD extensions. */
24900 struct arm_option_fpu_value_table
24903 const arm_feature_set value
;
24906 /* This list should, at a minimum, contain all the fpu names
24907 recognized by GCC. */
24908 static const struct arm_option_fpu_value_table arm_fpus
[] =
24910 {"softfpa", FPU_NONE
},
24911 {"fpe", FPU_ARCH_FPE
},
24912 {"fpe2", FPU_ARCH_FPE
},
24913 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
24914 {"fpa", FPU_ARCH_FPA
},
24915 {"fpa10", FPU_ARCH_FPA
},
24916 {"fpa11", FPU_ARCH_FPA
},
24917 {"arm7500fe", FPU_ARCH_FPA
},
24918 {"softvfp", FPU_ARCH_VFP
},
24919 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
24920 {"vfp", FPU_ARCH_VFP_V2
},
24921 {"vfp9", FPU_ARCH_VFP_V2
},
24922 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
24923 {"vfp10", FPU_ARCH_VFP_V2
},
24924 {"vfp10-r0", FPU_ARCH_VFP_V1
},
24925 {"vfpxd", FPU_ARCH_VFP_V1xD
},
24926 {"vfpv2", FPU_ARCH_VFP_V2
},
24927 {"vfpv3", FPU_ARCH_VFP_V3
},
24928 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
24929 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
24930 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
24931 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
24932 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
24933 {"arm1020t", FPU_ARCH_VFP_V1
},
24934 {"arm1020e", FPU_ARCH_VFP_V2
},
24935 {"arm1136jfs", FPU_ARCH_VFP_V2
},
24936 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
24937 {"maverick", FPU_ARCH_MAVERICK
},
24938 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
24939 {"neon-fp16", FPU_ARCH_NEON_FP16
},
24940 {"vfpv4", FPU_ARCH_VFP_V4
},
24941 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
24942 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
24943 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
24944 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
24945 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
24946 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
24947 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
24948 {"crypto-neon-fp-armv8",
24949 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
24950 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
24951 {"crypto-neon-fp-armv8.1",
24952 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
24953 {NULL
, ARM_ARCH_NONE
}
24956 struct arm_option_value_table
24962 static const struct arm_option_value_table arm_float_abis
[] =
24964 {"hard", ARM_FLOAT_ABI_HARD
},
24965 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
24966 {"soft", ARM_FLOAT_ABI_SOFT
},
24971 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
24972 static const struct arm_option_value_table arm_eabis
[] =
24974 {"gnu", EF_ARM_EABI_UNKNOWN
},
24975 {"4", EF_ARM_EABI_VER4
},
24976 {"5", EF_ARM_EABI_VER5
},
24981 struct arm_long_option_table
24983 char * option
; /* Substring to match. */
24984 char * help
; /* Help information. */
24985 int (* func
) (char * subopt
); /* Function to decode sub-option. */
24986 char * deprecated
; /* If non-null, print this message. */
24990 arm_parse_extension (char *str
, const arm_feature_set
**opt_p
)
24992 arm_feature_set
*ext_set
= (arm_feature_set
*)
24993 xmalloc (sizeof (arm_feature_set
));
24995 /* We insist on extensions being specified in alphabetical order, and with
24996 extensions being added before being removed. We achieve this by having
24997 the global ARM_EXTENSIONS table in alphabetical order, and using the
24998 ADDING_VALUE variable to indicate whether we are adding an extension (1)
24999 or removing it (0) and only allowing it to change in the order
25001 const struct arm_option_extension_value_table
* opt
= NULL
;
25002 int adding_value
= -1;
25004 /* Copy the feature set, so that we can modify it. */
25005 *ext_set
= **opt_p
;
25008 while (str
!= NULL
&& *str
!= 0)
25015 as_bad (_("invalid architectural extension"));
25020 ext
= strchr (str
, '+');
25025 len
= strlen (str
);
25027 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
25029 if (adding_value
!= 0)
25032 opt
= arm_extensions
;
25040 if (adding_value
== -1)
25043 opt
= arm_extensions
;
25045 else if (adding_value
!= 1)
25047 as_bad (_("must specify extensions to add before specifying "
25048 "those to remove"));
25055 as_bad (_("missing architectural extension"));
25059 gas_assert (adding_value
!= -1);
25060 gas_assert (opt
!= NULL
);
25062 /* Scan over the options table trying to find an exact match. */
25063 for (; opt
->name
!= NULL
; opt
++)
25064 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25066 /* Check we can apply the extension to this architecture. */
25067 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
25069 as_bad (_("extension does not apply to the base architecture"));
25073 /* Add or remove the extension. */
25075 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
25077 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
25082 if (opt
->name
== NULL
)
25084 /* Did we fail to find an extension because it wasn't specified in
25085 alphabetical order, or because it does not exist? */
25087 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25088 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25091 if (opt
->name
== NULL
)
25092 as_bad (_("unknown architectural extension `%s'"), str
);
25094 as_bad (_("architectural extensions must be specified in "
25095 "alphabetical order"));
25101 /* We should skip the extension we've just matched the next time
25113 arm_parse_cpu (char *str
)
25115 const struct arm_cpu_option_table
*opt
;
25116 char *ext
= strchr (str
, '+');
25122 len
= strlen (str
);
25126 as_bad (_("missing cpu name `%s'"), str
);
25130 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
25131 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25133 mcpu_cpu_opt
= &opt
->value
;
25134 mcpu_fpu_opt
= &opt
->default_fpu
;
25135 if (opt
->canonical_name
)
25136 strcpy (selected_cpu_name
, opt
->canonical_name
);
25141 for (i
= 0; i
< len
; i
++)
25142 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25143 selected_cpu_name
[i
] = 0;
25147 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
25152 as_bad (_("unknown cpu `%s'"), str
);
25157 arm_parse_arch (char *str
)
25159 const struct arm_arch_option_table
*opt
;
25160 char *ext
= strchr (str
, '+');
25166 len
= strlen (str
);
25170 as_bad (_("missing architecture name `%s'"), str
);
25174 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
25175 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25177 march_cpu_opt
= &opt
->value
;
25178 march_fpu_opt
= &opt
->default_fpu
;
25179 strcpy (selected_cpu_name
, opt
->name
);
25182 return arm_parse_extension (ext
, &march_cpu_opt
);
25187 as_bad (_("unknown architecture `%s'\n"), str
);
25192 arm_parse_fpu (char * str
)
25194 const struct arm_option_fpu_value_table
* opt
;
25196 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25197 if (streq (opt
->name
, str
))
25199 mfpu_opt
= &opt
->value
;
25203 as_bad (_("unknown floating point format `%s'\n"), str
);
25208 arm_parse_float_abi (char * str
)
25210 const struct arm_option_value_table
* opt
;
25212 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
25213 if (streq (opt
->name
, str
))
25215 mfloat_abi_opt
= opt
->value
;
25219 as_bad (_("unknown floating point abi `%s'\n"), str
);
25225 arm_parse_eabi (char * str
)
25227 const struct arm_option_value_table
*opt
;
25229 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
25230 if (streq (opt
->name
, str
))
25232 meabi_flags
= opt
->value
;
25235 as_bad (_("unknown EABI `%s'\n"), str
);
25241 arm_parse_it_mode (char * str
)
25243 bfd_boolean ret
= TRUE
;
25245 if (streq ("arm", str
))
25246 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
25247 else if (streq ("thumb", str
))
25248 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
25249 else if (streq ("always", str
))
25250 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
25251 else if (streq ("never", str
))
25252 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
25255 as_bad (_("unknown implicit IT mode `%s', should be "\
25256 "arm, thumb, always, or never."), str
);
25264 arm_ccs_mode (char * unused ATTRIBUTE_UNUSED
)
25266 codecomposer_syntax
= TRUE
;
25267 arm_comment_chars
[0] = ';';
25268 arm_line_separator_chars
[0] = 0;
25272 struct arm_long_option_table arm_long_opts
[] =
25274 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
25275 arm_parse_cpu
, NULL
},
25276 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
25277 arm_parse_arch
, NULL
},
25278 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
25279 arm_parse_fpu
, NULL
},
25280 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
25281 arm_parse_float_abi
, NULL
},
25283 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
25284 arm_parse_eabi
, NULL
},
25286 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
25287 arm_parse_it_mode
, NULL
},
25288 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
25289 arm_ccs_mode
, NULL
},
25290 {NULL
, NULL
, 0, NULL
}
25294 md_parse_option (int c
, char * arg
)
25296 struct arm_option_table
*opt
;
25297 const struct arm_legacy_option_table
*fopt
;
25298 struct arm_long_option_table
*lopt
;
25304 target_big_endian
= 1;
25310 target_big_endian
= 0;
25314 case OPTION_FIX_V4BX
:
25319 /* Listing option. Just ignore these, we don't support additional
25324 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25326 if (c
== opt
->option
[0]
25327 && ((arg
== NULL
&& opt
->option
[1] == 0)
25328 || streq (arg
, opt
->option
+ 1)))
25330 /* If the option is deprecated, tell the user. */
25331 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
25332 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25333 arg
? arg
: "", _(opt
->deprecated
));
25335 if (opt
->var
!= NULL
)
25336 *opt
->var
= opt
->value
;
25342 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
25344 if (c
== fopt
->option
[0]
25345 && ((arg
== NULL
&& fopt
->option
[1] == 0)
25346 || streq (arg
, fopt
->option
+ 1)))
25348 /* If the option is deprecated, tell the user. */
25349 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
25350 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25351 arg
? arg
: "", _(fopt
->deprecated
));
25353 if (fopt
->var
!= NULL
)
25354 *fopt
->var
= &fopt
->value
;
25360 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25362 /* These options are expected to have an argument. */
25363 if (c
== lopt
->option
[0]
25365 && strncmp (arg
, lopt
->option
+ 1,
25366 strlen (lopt
->option
+ 1)) == 0)
25368 /* If the option is deprecated, tell the user. */
25369 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
25370 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
25371 _(lopt
->deprecated
));
25373 /* Call the sup-option parser. */
25374 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
25385 md_show_usage (FILE * fp
)
25387 struct arm_option_table
*opt
;
25388 struct arm_long_option_table
*lopt
;
25390 fprintf (fp
, _(" ARM-specific assembler options:\n"));
25392 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25393 if (opt
->help
!= NULL
)
25394 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
25396 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25397 if (lopt
->help
!= NULL
)
25398 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
25402 -EB assemble code for a big-endian cpu\n"));
25407 -EL assemble code for a little-endian cpu\n"));
25411 --fix-v4bx Allow BX in ARMv4 code\n"));
25419 arm_feature_set flags
;
25420 } cpu_arch_ver_table
;
25422 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
25423 least features first. */
25424 static const cpu_arch_ver_table cpu_arch_ver
[] =
25430 {4, ARM_ARCH_V5TE
},
25431 {5, ARM_ARCH_V5TEJ
},
25435 {11, ARM_ARCH_V6M
},
25436 {12, ARM_ARCH_V6SM
},
25437 {8, ARM_ARCH_V6T2
},
25438 {10, ARM_ARCH_V7VE
},
25439 {10, ARM_ARCH_V7R
},
25440 {10, ARM_ARCH_V7M
},
25441 {14, ARM_ARCH_V8A
},
25445 /* Set an attribute if it has not already been set by the user. */
25447 aeabi_set_attribute_int (int tag
, int value
)
25450 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
25451 || !attributes_set_explicitly
[tag
])
25452 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
25456 aeabi_set_attribute_string (int tag
, const char *value
)
25459 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
25460 || !attributes_set_explicitly
[tag
])
25461 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
25464 /* Set the public EABI object attributes. */
25466 aeabi_set_public_attributes (void)
25471 int fp16_optional
= 0;
25472 arm_feature_set flags
;
25473 arm_feature_set tmp
;
25474 const cpu_arch_ver_table
*p
;
25476 /* Choose the architecture based on the capabilities of the requested cpu
25477 (if any) and/or the instructions actually used. */
25478 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
25479 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
25480 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
25482 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
25483 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
25485 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
25486 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
25488 selected_cpu
= flags
;
25490 /* Allow the user to override the reported architecture. */
25493 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
25494 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
25497 /* We need to make sure that the attributes do not identify us as v6S-M
25498 when the only v6S-M feature in use is the Operating System Extensions. */
25499 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
25500 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
25501 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
25505 for (p
= cpu_arch_ver
; p
->val
; p
++)
25507 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
25510 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
25514 /* The table lookup above finds the last architecture to contribute
25515 a new feature. Unfortunately, Tag13 is a subset of the union of
25516 v6T2 and v7-M, so it is never seen as contributing a new feature.
25517 We can not search for the last entry which is entirely used,
25518 because if no CPU is specified we build up only those flags
25519 actually used. Perhaps we should separate out the specified
25520 and implicit cases. Avoid taking this path for -march=all by
25521 checking for contradictory v7-A / v7-M features. */
25523 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
25524 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
25525 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
25528 /* Tag_CPU_name. */
25529 if (selected_cpu_name
[0])
25533 q
= selected_cpu_name
;
25534 if (strncmp (q
, "armv", 4) == 0)
25539 for (i
= 0; q
[i
]; i
++)
25540 q
[i
] = TOUPPER (q
[i
]);
25542 aeabi_set_attribute_string (Tag_CPU_name
, q
);
25545 /* Tag_CPU_arch. */
25546 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
25548 /* Tag_CPU_arch_profile. */
25549 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
25551 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
25553 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
25558 if (profile
!= '\0')
25559 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
25561 /* Tag_ARM_ISA_use. */
25562 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
25564 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
25566 /* Tag_THUMB_ISA_use. */
25567 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
25569 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
25570 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
25572 /* Tag_VFP_arch. */
25573 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
25574 aeabi_set_attribute_int (Tag_VFP_arch
,
25575 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
25577 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
25578 aeabi_set_attribute_int (Tag_VFP_arch
,
25579 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
25581 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
25584 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
25586 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
25588 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
25591 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
25592 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
25593 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
25594 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
25595 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
25597 /* Tag_ABI_HardFP_use. */
25598 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
25599 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
25600 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
25602 /* Tag_WMMX_arch. */
25603 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
25604 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
25605 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
25606 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
25608 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
25609 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
25610 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
25611 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
25613 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
25615 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
25619 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
25624 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
25625 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
25626 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
25630 We set Tag_DIV_use to two when integer divide instructions have been used
25631 in ARM state, or when Thumb integer divide instructions have been used,
25632 but we have no architecture profile set, nor have we any ARM instructions.
25634 For ARMv8 we set the tag to 0 as integer divide is implied by the base
25637 For new architectures we will have to check these tests. */
25638 gas_assert (arch
<= TAG_CPU_ARCH_V8
);
25639 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
))
25640 aeabi_set_attribute_int (Tag_DIV_use
, 0);
25641 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
25642 || (profile
== '\0'
25643 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
25644 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
25645 aeabi_set_attribute_int (Tag_DIV_use
, 2);
25647 /* Tag_MP_extension_use. */
25648 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
25649 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
25651 /* Tag Virtualization_use. */
25652 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
25654 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
25657 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
25660 /* Add the default contents for the .ARM.attributes section. */
25664 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
25667 aeabi_set_public_attributes ();
25669 #endif /* OBJ_ELF */
25672 /* Parse a .cpu directive. */
25675 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
25677 const struct arm_cpu_option_table
*opt
;
25681 name
= input_line_pointer
;
25682 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25683 input_line_pointer
++;
25684 saved_char
= *input_line_pointer
;
25685 *input_line_pointer
= 0;
25687 /* Skip the first "all" entry. */
25688 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
25689 if (streq (opt
->name
, name
))
25691 mcpu_cpu_opt
= &opt
->value
;
25692 selected_cpu
= opt
->value
;
25693 if (opt
->canonical_name
)
25694 strcpy (selected_cpu_name
, opt
->canonical_name
);
25698 for (i
= 0; opt
->name
[i
]; i
++)
25699 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25701 selected_cpu_name
[i
] = 0;
25703 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25704 *input_line_pointer
= saved_char
;
25705 demand_empty_rest_of_line ();
25708 as_bad (_("unknown cpu `%s'"), name
);
25709 *input_line_pointer
= saved_char
;
25710 ignore_rest_of_line ();
25714 /* Parse a .arch directive. */
25717 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
25719 const struct arm_arch_option_table
*opt
;
25723 name
= input_line_pointer
;
25724 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25725 input_line_pointer
++;
25726 saved_char
= *input_line_pointer
;
25727 *input_line_pointer
= 0;
25729 /* Skip the first "all" entry. */
25730 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
25731 if (streq (opt
->name
, name
))
25733 mcpu_cpu_opt
= &opt
->value
;
25734 selected_cpu
= opt
->value
;
25735 strcpy (selected_cpu_name
, opt
->name
);
25736 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25737 *input_line_pointer
= saved_char
;
25738 demand_empty_rest_of_line ();
25742 as_bad (_("unknown architecture `%s'\n"), name
);
25743 *input_line_pointer
= saved_char
;
25744 ignore_rest_of_line ();
25748 /* Parse a .object_arch directive. */
25751 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
25753 const struct arm_arch_option_table
*opt
;
25757 name
= input_line_pointer
;
25758 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25759 input_line_pointer
++;
25760 saved_char
= *input_line_pointer
;
25761 *input_line_pointer
= 0;
25763 /* Skip the first "all" entry. */
25764 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
25765 if (streq (opt
->name
, name
))
25767 object_arch
= &opt
->value
;
25768 *input_line_pointer
= saved_char
;
25769 demand_empty_rest_of_line ();
25773 as_bad (_("unknown architecture `%s'\n"), name
);
25774 *input_line_pointer
= saved_char
;
25775 ignore_rest_of_line ();
25778 /* Parse a .arch_extension directive. */
25781 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
25783 const struct arm_option_extension_value_table
*opt
;
25786 int adding_value
= 1;
25788 name
= input_line_pointer
;
25789 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25790 input_line_pointer
++;
25791 saved_char
= *input_line_pointer
;
25792 *input_line_pointer
= 0;
25794 if (strlen (name
) >= 2
25795 && strncmp (name
, "no", 2) == 0)
25801 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25802 if (streq (opt
->name
, name
))
25804 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
25806 as_bad (_("architectural extension `%s' is not allowed for the "
25807 "current base architecture"), name
);
25812 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
,
25815 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->clear_value
);
25817 mcpu_cpu_opt
= &selected_cpu
;
25818 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25819 *input_line_pointer
= saved_char
;
25820 demand_empty_rest_of_line ();
25824 if (opt
->name
== NULL
)
25825 as_bad (_("unknown architecture extension `%s'\n"), name
);
25827 *input_line_pointer
= saved_char
;
25828 ignore_rest_of_line ();
25831 /* Parse a .fpu directive. */
25834 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
25836 const struct arm_option_fpu_value_table
*opt
;
25840 name
= input_line_pointer
;
25841 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25842 input_line_pointer
++;
25843 saved_char
= *input_line_pointer
;
25844 *input_line_pointer
= 0;
25846 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25847 if (streq (opt
->name
, name
))
25849 mfpu_opt
= &opt
->value
;
25850 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25851 *input_line_pointer
= saved_char
;
25852 demand_empty_rest_of_line ();
25856 as_bad (_("unknown floating point format `%s'\n"), name
);
25857 *input_line_pointer
= saved_char
;
25858 ignore_rest_of_line ();
25861 /* Copy symbol information. */
25864 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
25866 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
25870 /* Given a symbolic attribute NAME, return the proper integer value.
25871 Returns -1 if the attribute is not known. */
25874 arm_convert_symbolic_attribute (const char *name
)
25876 static const struct
25881 attribute_table
[] =
25883 /* When you modify this table you should
25884 also modify the list in doc/c-arm.texi. */
25885 #define T(tag) {#tag, tag}
25886 T (Tag_CPU_raw_name
),
25889 T (Tag_CPU_arch_profile
),
25890 T (Tag_ARM_ISA_use
),
25891 T (Tag_THUMB_ISA_use
),
25895 T (Tag_Advanced_SIMD_arch
),
25896 T (Tag_PCS_config
),
25897 T (Tag_ABI_PCS_R9_use
),
25898 T (Tag_ABI_PCS_RW_data
),
25899 T (Tag_ABI_PCS_RO_data
),
25900 T (Tag_ABI_PCS_GOT_use
),
25901 T (Tag_ABI_PCS_wchar_t
),
25902 T (Tag_ABI_FP_rounding
),
25903 T (Tag_ABI_FP_denormal
),
25904 T (Tag_ABI_FP_exceptions
),
25905 T (Tag_ABI_FP_user_exceptions
),
25906 T (Tag_ABI_FP_number_model
),
25907 T (Tag_ABI_align_needed
),
25908 T (Tag_ABI_align8_needed
),
25909 T (Tag_ABI_align_preserved
),
25910 T (Tag_ABI_align8_preserved
),
25911 T (Tag_ABI_enum_size
),
25912 T (Tag_ABI_HardFP_use
),
25913 T (Tag_ABI_VFP_args
),
25914 T (Tag_ABI_WMMX_args
),
25915 T (Tag_ABI_optimization_goals
),
25916 T (Tag_ABI_FP_optimization_goals
),
25917 T (Tag_compatibility
),
25918 T (Tag_CPU_unaligned_access
),
25919 T (Tag_FP_HP_extension
),
25920 T (Tag_VFP_HP_extension
),
25921 T (Tag_ABI_FP_16bit_format
),
25922 T (Tag_MPextension_use
),
25924 T (Tag_nodefaults
),
25925 T (Tag_also_compatible_with
),
25926 T (Tag_conformance
),
25928 T (Tag_Virtualization_use
),
25929 /* We deliberately do not include Tag_MPextension_use_legacy. */
25937 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
25938 if (streq (name
, attribute_table
[i
].name
))
25939 return attribute_table
[i
].tag
;
25945 /* Apply sym value for relocations only in the case that they are for
25946 local symbols in the same segment as the fixup and you have the
25947 respective architectural feature for blx and simple switches. */
25949 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
25952 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
25953 /* PR 17444: If the local symbol is in a different section then a reloc
25954 will always be generated for it, so applying the symbol value now
25955 will result in a double offset being stored in the relocation. */
25956 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
25957 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
25959 switch (fixP
->fx_r_type
)
25961 case BFD_RELOC_ARM_PCREL_BLX
:
25962 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25963 if (ARM_IS_FUNC (fixP
->fx_addsy
))
25967 case BFD_RELOC_ARM_PCREL_CALL
:
25968 case BFD_RELOC_THUMB_PCREL_BLX
:
25969 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
25980 #endif /* OBJ_ELF */