1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
31 #include "safe-ctype.h"
33 /* Need TARGET_CPU. */
40 #include "opcode/arm.h"
44 #include "dwarf2dbg.h"
45 #include "dw2gencfi.h"
48 /* XXX Set this to 1 after the next binutils release. */
49 #define WARN_DEPRECATED 0
52 /* Must be at least the size of the largest unwind opcode (currently two). */
53 #define ARM_OPCODE_CHUNK_SIZE 8
55 /* This structure holds the unwinding state. */
60 symbolS
* table_entry
;
61 symbolS
* personality_routine
;
62 int personality_index
;
63 /* The segment containing the function. */
66 /* Opcodes generated from this function. */
67 unsigned char * opcodes
;
70 /* The number of bytes pushed to the stack. */
72 /* We don't add stack adjustment opcodes immediately so that we can merge
73 multiple adjustments. We can also omit the final adjustment
74 when using a frame pointer. */
75 offsetT pending_offset
;
76 /* These two fields are set by both unwind_movsp and unwind_setfp. They
77 hold the reg+offset to use when restoring sp from a frame pointer. */
80 /* Nonzero if an unwind_setfp directive has been seen. */
82 /* Nonzero if the last opcode restores sp from fp_reg. */
83 unsigned sp_restored
:1;
86 /* Bit N indicates that an R_ARM_NONE relocation has been output for
87 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
88 emitted only once per section, to save unnecessary bloat. */
89 static unsigned int marked_pr_dependency
= 0;
100 /* Types of processor to assemble for. */
101 #define ARM_1 ARM_ARCH_V1
102 #define ARM_2 ARM_ARCH_V2
103 #define ARM_3 ARM_ARCH_V2S
104 #define ARM_250 ARM_ARCH_V2S
105 #define ARM_6 ARM_ARCH_V3
106 #define ARM_7 ARM_ARCH_V3
107 #define ARM_8 ARM_ARCH_V4
108 #define ARM_9 ARM_ARCH_V4T
109 #define ARM_STRONG ARM_ARCH_V4
110 #define ARM_CPU_MASK 0x0000000f /* XXX? */
113 #if defined __XSCALE__
114 #define CPU_DEFAULT (ARM_ARCH_XSCALE)
116 #if defined __thumb__
117 #define CPU_DEFAULT (ARM_ARCH_V5T)
119 #define CPU_DEFAULT ARM_ANY
126 # define FPU_DEFAULT FPU_ARCH_FPA
127 # elif defined (TE_NetBSD)
129 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
131 /* Legacy a.out format. */
132 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
134 # elif defined (TE_VXWORKS)
135 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
137 /* For backwards compatibility, default to FPA. */
138 # define FPU_DEFAULT FPU_ARCH_FPA
140 #endif /* ifndef FPU_DEFAULT */
142 #define streq(a, b) (strcmp (a, b) == 0)
144 static unsigned long cpu_variant
;
146 /* Flags stored in private area of BFD structure. */
147 static int uses_apcs_26
= FALSE
;
148 static int atpcs
= FALSE
;
149 static int support_interwork
= FALSE
;
150 static int uses_apcs_float
= FALSE
;
151 static int pic_code
= FALSE
;
153 /* Variables that we set while parsing command-line options. Once all
154 options have been read we re-process these values to set the real
156 static int legacy_cpu
= -1;
157 static int legacy_fpu
= -1;
159 static int mcpu_cpu_opt
= -1;
160 static int mcpu_fpu_opt
= -1;
161 static int march_cpu_opt
= -1;
162 static int march_fpu_opt
= -1;
163 static int mfpu_opt
= -1;
164 static int mfloat_abi_opt
= -1;
167 static int meabi_flags
= EABI_DEFAULT
;
169 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
174 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
175 symbolS
* GOT_symbol
;
178 /* Size of relocation record. */
179 const int md_reloc_size
= 8;
181 /* 0: assemble for ARM,
182 1: assemble for Thumb,
183 2: assemble for Thumb even though target CPU does not support thumb
185 static int thumb_mode
= 0;
187 /* If unified_syntax is true, we are processing the new unified
188 ARM/Thumb syntax. Important differences from the old ARM mode:
190 - Immediate operands do not require a # prefix.
191 - Conditional affixes always appear at the end of the
192 instruction. (For backward compatibility, those instructions
193 that formerly had them in the middle, continue to accept them
195 - The IT instruction may appear, and if it does is validated
196 against subsequent conditional affixes. It does not generate
199 Important differences from the old Thumb mode:
201 - Immediate operands do not require a # prefix.
202 - Most of the V6T2 instructions are only available in unified mode.
203 - The .N and .W suffixes are recognized and honored (it is an error
204 if they cannot be honored).
205 - All instructions set the flags if and only if they have an 's' affix.
206 - Conditional affixes may be used. They are validated against
207 preceding IT instructions. Unlike ARM mode, you cannot use a
208 conditional affix except in the scope of an IT instruction. */
210 static bfd_boolean unified_syntax
= FALSE
;
215 unsigned long instruction
;
221 bfd_reloc_code_real_type type
;
230 unsigned present
: 1; /* Operand present. */
231 unsigned isreg
: 1; /* Operand was a register. */
232 unsigned immisreg
: 1; /* .imm field is a second register. */
233 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
234 unsigned writeback
: 1; /* Operand has trailing ! */
235 unsigned preind
: 1; /* Preindexed address. */
236 unsigned postind
: 1; /* Postindexed address. */
237 unsigned negative
: 1; /* Index register was negated. */
238 unsigned shifted
: 1; /* Shift applied to operation. */
239 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
243 static struct arm_it inst
;
245 #define NUM_FLOAT_VALS 8
247 const char * fp_const
[] =
249 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
252 /* Number of littlenums required to hold an extended precision number. */
253 #define MAX_LITTLENUMS 6
255 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
265 #define CP_T_X 0x00008000
266 #define CP_T_Y 0x00400000
268 #define CONDS_BIT 0x00100000
269 #define LOAD_BIT 0x00100000
271 #define DOUBLE_LOAD_FLAG 0x00000001
275 const char * template;
279 #define COND_ALWAYS 0xE
283 const char *template;
287 /* The bit that distinguishes CPSR and SPSR. */
288 #define SPSR_BIT (1 << 22)
290 /* The individual PSR flag bits. */
291 #define PSR_c (1 << 16)
292 #define PSR_x (1 << 17)
293 #define PSR_s (1 << 18)
294 #define PSR_f (1 << 19)
299 bfd_reloc_code_real_type reloc
;
304 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
309 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
312 /* ARM register categories. This includes coprocessor numbers and various
313 architecture extensions' registers. */
335 /* Structure for a hash table entry for a register. */
339 unsigned char number
;
341 unsigned char builtin
;
344 /* Diagnostics used when we don't get a register of the expected type. */
345 const char *const reg_expected_msgs
[] =
347 N_("ARM register expected"),
348 N_("bad or missing co-processor number"),
349 N_("co-processor register expected"),
350 N_("FPA register expected"),
351 N_("VFP single precision register expected"),
352 N_("VFP double precision register expected"),
353 N_("VFP system register expected"),
354 N_("Maverick MVF register expected"),
355 N_("Maverick MVD register expected"),
356 N_("Maverick MVFX register expected"),
357 N_("Maverick MVDX register expected"),
358 N_("Maverick MVAX register expected"),
359 N_("Maverick DSPSC register expected"),
360 N_("iWMMXt data register expected"),
361 N_("iWMMXt control register expected"),
362 N_("iWMMXt scalar register expected"),
363 N_("XScale accumulator register expected"),
366 /* Some well known registers that we refer to directly elsewhere. */
371 /* ARM instructions take 4bytes in the object file, Thumb instructions
377 /* Basic string to match. */
378 const char *template;
380 /* Parameters to instruction. */
381 unsigned char operands
[8];
383 /* Conditional tag - see opcode_lookup. */
384 unsigned int tag
: 4;
386 /* Basic instruction code. */
387 unsigned int avalue
: 28;
389 /* Thumb-format instruction code. */
392 /* Which architecture variant provides this instruction. */
393 unsigned long avariant
;
394 unsigned long tvariant
;
396 /* Function to call to encode instruction in ARM format. */
397 void (* aencode
) (void);
399 /* Function to call to encode instruction in Thumb format. */
400 void (* tencode
) (void);
403 /* Defines for various bits that we will want to toggle. */
404 #define INST_IMMEDIATE 0x02000000
405 #define OFFSET_REG 0x02000000
406 #define HWOFFSET_IMM 0x00400000
407 #define SHIFT_BY_REG 0x00000010
408 #define PRE_INDEX 0x01000000
409 #define INDEX_UP 0x00800000
410 #define WRITE_BACK 0x00200000
411 #define LDM_TYPE_2_OR_3 0x00400000
413 #define LITERAL_MASK 0xf000f000
414 #define OPCODE_MASK 0xfe1fffff
415 #define V4_STR_BIT 0x00000020
417 #define DATA_OP_SHIFT 21
419 /* Codes to distinguish the arithmetic instructions. */
430 #define OPCODE_CMP 10
431 #define OPCODE_CMN 11
432 #define OPCODE_ORR 12
433 #define OPCODE_MOV 13
434 #define OPCODE_BIC 14
435 #define OPCODE_MVN 15
437 #define T_OPCODE_MUL 0x4340
438 #define T_OPCODE_TST 0x4200
439 #define T_OPCODE_CMN 0x42c0
440 #define T_OPCODE_NEG 0x4240
441 #define T_OPCODE_MVN 0x43c0
443 #define T_OPCODE_ADD_R3 0x1800
444 #define T_OPCODE_SUB_R3 0x1a00
445 #define T_OPCODE_ADD_HI 0x4400
446 #define T_OPCODE_ADD_ST 0xb000
447 #define T_OPCODE_SUB_ST 0xb080
448 #define T_OPCODE_ADD_SP 0xa800
449 #define T_OPCODE_ADD_PC 0xa000
450 #define T_OPCODE_ADD_I8 0x3000
451 #define T_OPCODE_SUB_I8 0x3800
452 #define T_OPCODE_ADD_I3 0x1c00
453 #define T_OPCODE_SUB_I3 0x1e00
455 #define T_OPCODE_ASR_R 0x4100
456 #define T_OPCODE_LSL_R 0x4080
457 #define T_OPCODE_LSR_R 0x40c0
458 #define T_OPCODE_ROR_R 0x41c0
459 #define T_OPCODE_ASR_I 0x1000
460 #define T_OPCODE_LSL_I 0x0000
461 #define T_OPCODE_LSR_I 0x0800
463 #define T_OPCODE_MOV_I8 0x2000
464 #define T_OPCODE_CMP_I8 0x2800
465 #define T_OPCODE_CMP_LR 0x4280
466 #define T_OPCODE_MOV_HR 0x4600
467 #define T_OPCODE_CMP_HR 0x4500
469 #define T_OPCODE_LDR_PC 0x4800
470 #define T_OPCODE_LDR_SP 0x9800
471 #define T_OPCODE_STR_SP 0x9000
472 #define T_OPCODE_LDR_IW 0x6800
473 #define T_OPCODE_STR_IW 0x6000
474 #define T_OPCODE_LDR_IH 0x8800
475 #define T_OPCODE_STR_IH 0x8000
476 #define T_OPCODE_LDR_IB 0x7800
477 #define T_OPCODE_STR_IB 0x7000
478 #define T_OPCODE_LDR_RW 0x5800
479 #define T_OPCODE_STR_RW 0x5000
480 #define T_OPCODE_LDR_RH 0x5a00
481 #define T_OPCODE_STR_RH 0x5200
482 #define T_OPCODE_LDR_RB 0x5c00
483 #define T_OPCODE_STR_RB 0x5400
485 #define T_OPCODE_PUSH 0xb400
486 #define T_OPCODE_POP 0xbc00
488 #define T_OPCODE_BRANCH 0xe000
490 #define THUMB_SIZE 2 /* Size of thumb instruction. */
491 #define THUMB_PP_PC_LR 0x0100
492 #define THUMB_LOAD_BIT 0x0800
494 #define BAD_ARGS _("bad arguments to instruction")
495 #define BAD_PC _("r15 not allowed here")
496 #define BAD_COND _("instruction cannot be conditional")
497 #define BAD_OVERLAP _("registers may not be the same")
498 #define BAD_HIREG _("lo register required")
499 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
501 static struct hash_control
*arm_ops_hsh
;
502 static struct hash_control
*arm_cond_hsh
;
503 static struct hash_control
*arm_shift_hsh
;
504 static struct hash_control
*arm_psr_hsh
;
505 static struct hash_control
*arm_reg_hsh
;
506 static struct hash_control
*arm_reloc_hsh
;
508 /* Stuff needed to resolve the label ambiguity
518 symbolS
* last_label_seen
;
519 static int label_is_thumb_function_name
= FALSE
;
521 /* Literal pool structure. Held on a per-section
522 and per-sub-section basis. */
524 #define MAX_LITERAL_POOL_SIZE 1024
525 typedef struct literal_pool
527 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
528 unsigned int next_free_entry
;
533 struct literal_pool
* next
;
536 /* Pointer to a linked list of literal pools. */
537 literal_pool
* list_of_pools
= NULL
;
539 /* State variables for IT block handling. */
540 static bfd_boolean current_it_mask
= 0;
541 static int current_cc
;
546 /* This array holds the chars that always start a comment. If the
547 pre-processor is disabled, these aren't very useful. */
548 const char comment_chars
[] = "@";
550 /* This array holds the chars that only start a comment at the beginning of
551 a line. If the line seems to have the form '# 123 filename'
552 .line and .file directives will appear in the pre-processed output. */
553 /* Note that input_file.c hand checks for '#' at the beginning of the
554 first line of the input file. This is because the compiler outputs
555 #NO_APP at the beginning of its output. */
556 /* Also note that comments like this one will always work. */
557 const char line_comment_chars
[] = "#";
559 const char line_separator_chars
[] = ";";
561 /* Chars that can be used to separate mant
562 from exp in floating point numbers. */
563 const char EXP_CHARS
[] = "eE";
565 /* Chars that mean this number is a floating point constant. */
569 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
571 /* Prefix characters that indicate the start of an immediate
573 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
575 /* Separator character handling. */
577 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
580 skip_past_char (char ** str
, char c
)
590 #define skip_past_comma(str) skip_past_char (str, ',')
592 /* Arithmetic expressions (possibly involving symbols). */
594 /* Return TRUE if anything in the expression is a bignum. */
597 walk_no_bignums (symbolS
* sp
)
599 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
602 if (symbol_get_value_expression (sp
)->X_add_symbol
)
604 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
605 || (symbol_get_value_expression (sp
)->X_op_symbol
606 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
612 static int in_my_get_expression
= 0;
614 /* Third argument to my_get_expression. */
615 #define GE_NO_PREFIX 0
616 #define GE_IMM_PREFIX 1
617 #define GE_OPT_PREFIX 2
620 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
625 /* In unified syntax, all prefixes are optional. */
627 prefix_mode
= GE_OPT_PREFIX
;
631 case GE_NO_PREFIX
: break;
633 if (!is_immediate_prefix (**str
))
635 inst
.error
= _("immediate expression requires a # prefix");
641 if (is_immediate_prefix (**str
))
647 memset (ep
, 0, sizeof (expressionS
));
649 save_in
= input_line_pointer
;
650 input_line_pointer
= *str
;
651 in_my_get_expression
= 1;
652 seg
= expression (ep
);
653 in_my_get_expression
= 0;
655 if (ep
->X_op
== O_illegal
)
657 /* We found a bad expression in md_operand(). */
658 *str
= input_line_pointer
;
659 input_line_pointer
= save_in
;
660 if (inst
.error
== NULL
)
661 inst
.error
= _("bad expression");
666 if (seg
!= absolute_section
667 && seg
!= text_section
668 && seg
!= data_section
669 && seg
!= bss_section
670 && seg
!= undefined_section
)
672 inst
.error
= _("bad segment");
673 *str
= input_line_pointer
;
674 input_line_pointer
= save_in
;
679 /* Get rid of any bignums now, so that we don't generate an error for which
680 we can't establish a line number later on. Big numbers are never valid
681 in instructions, which is where this routine is always called. */
682 if (ep
->X_op
== O_big
684 && (walk_no_bignums (ep
->X_add_symbol
)
686 && walk_no_bignums (ep
->X_op_symbol
)))))
688 inst
.error
= _("invalid constant");
689 *str
= input_line_pointer
;
690 input_line_pointer
= save_in
;
694 *str
= input_line_pointer
;
695 input_line_pointer
= save_in
;
699 /* Turn a string in input_line_pointer into a floating point constant
700 of type TYPE, and store the appropriate bytes in *LITP. The number
701 of LITTLENUMS emitted is stored in *SIZEP. An error message is
702 returned, or NULL on OK.
704 Note that fp constants aren't represent in the normal way on the ARM.
705 In big endian mode, things are as expected. However, in little endian
706 mode fp constants are big-endian word-wise, and little-endian byte-wise
707 within the words. For example, (double) 1.1 in big endian mode is
708 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
709 the byte sequence 99 99 f1 3f 9a 99 99 99.
711 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
714 md_atof (int type
, char * litP
, int * sizeP
)
717 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
749 return _("bad call to MD_ATOF()");
752 t
= atof_ieee (input_line_pointer
, type
, words
);
754 input_line_pointer
= t
;
757 if (target_big_endian
)
759 for (i
= 0; i
< prec
; i
++)
761 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
767 if (cpu_variant
& FPU_ARCH_VFP
)
768 for (i
= prec
- 1; i
>= 0; i
--)
770 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
774 /* For a 4 byte float the order of elements in `words' is 1 0.
775 For an 8 byte float the order is 1 0 3 2. */
776 for (i
= 0; i
< prec
; i
+= 2)
778 md_number_to_chars (litP
, (valueT
) words
[i
+ 1], 2);
779 md_number_to_chars (litP
+ 2, (valueT
) words
[i
], 2);
787 /* We handle all bad expressions here, so that we can report the faulty
788 instruction in the error message. */
790 md_operand (expressionS
* expr
)
792 if (in_my_get_expression
)
793 expr
->X_op
= O_illegal
;
796 /* Immediate values. */
798 /* Generic immediate-value read function for use in directives.
799 Accepts anything that 'expression' can fold to a constant.
800 *val receives the number. */
803 immediate_for_directive (int *val
)
806 exp
.X_op
= O_illegal
;
808 if (is_immediate_prefix (*input_line_pointer
))
810 input_line_pointer
++;
814 if (exp
.X_op
!= O_constant
)
816 as_bad (_("expected #constant"));
817 ignore_rest_of_line ();
820 *val
= exp
.X_add_number
;
825 /* Register parsing. */
827 /* Generic register parser. CCP points to what should be the
828 beginning of a register name. If it is indeed a valid register
829 name, advance CCP over it and return the reg_entry structure;
830 otherwise return NULL. Does not issue diagnostics. */
832 static struct reg_entry
*
833 arm_reg_parse_multi (char **ccp
)
837 struct reg_entry
*reg
;
839 #ifdef REGISTER_PREFIX
840 if (*start
!= REGISTER_PREFIX
)
844 #ifdef OPTIONAL_REGISTER_PREFIX
845 if (*start
== OPTIONAL_REGISTER_PREFIX
)
850 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
855 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
857 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
866 /* As above, but the register must be of type TYPE, and the return
867 value is the register number or NULL. */
870 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
873 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
875 if (reg
&& reg
->type
== type
)
878 /* Alternative syntaxes are accepted for a few register classes. */
885 /* Generic coprocessor register names are allowed for these. */
886 if (reg
->type
== REG_TYPE_CN
)
891 /* For backward compatibility, a bare number is valid here. */
893 unsigned long processor
= strtoul (start
, ccp
, 10);
894 if (*ccp
!= start
&& processor
<= 15)
899 /* WC includes WCG. ??? I'm not sure this is true for all
900 instructions that take WC registers. */
901 if (reg
->type
== REG_TYPE_MMXWCG
)
913 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
915 parse_reg_list (char ** strp
)
921 /* We come back here if we get ranges concatenated by '+' or '|'. */
936 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
938 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
948 inst
.error
= _("bad range in register list");
952 for (i
= cur_reg
+ 1; i
< reg
; i
++)
954 if (range
& (1 << i
))
956 (_("Warning: duplicated register (r%d) in register list"),
964 if (range
& (1 << reg
))
965 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
967 else if (reg
<= cur_reg
)
968 as_tsktsk (_("Warning: register range not in ascending order"));
973 while (skip_past_comma (&str
) != FAIL
974 || (in_range
= 1, *str
++ == '-'));
979 inst
.error
= _("missing `}'");
987 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
990 if (expr
.X_op
== O_constant
)
992 if (expr
.X_add_number
993 != (expr
.X_add_number
& 0x0000ffff))
995 inst
.error
= _("invalid register mask");
999 if ((range
& expr
.X_add_number
) != 0)
1001 int regno
= range
& expr
.X_add_number
;
1004 regno
= (1 << regno
) - 1;
1006 (_("Warning: duplicated register (r%d) in register list"),
1010 range
|= expr
.X_add_number
;
1014 if (inst
.reloc
.type
!= 0)
1016 inst
.error
= _("expression too complex");
1020 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1021 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1022 inst
.reloc
.pc_rel
= 0;
1026 if (*str
== '|' || *str
== '+')
1032 while (another_range
);
1038 /* Parse a VFP register list. If the string is invalid return FAIL.
1039 Otherwise return the number of registers, and set PBASE to the first
1040 register. Double precision registers are matched if DP is nonzero. */
1043 parse_vfp_reg_list (char **str
, unsigned int *pbase
, int dp
)
1051 unsigned long mask
= 0;
1061 regtype
= REG_TYPE_VFD
;
1066 regtype
= REG_TYPE_VFS
;
1070 base_reg
= max_regs
;
1074 new_base
= arm_reg_parse (str
, regtype
);
1075 if (new_base
== FAIL
)
1077 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1081 if (new_base
< base_reg
)
1082 base_reg
= new_base
;
1084 if (mask
& (1 << new_base
))
1086 inst
.error
= _("invalid register list");
1090 if ((mask
>> new_base
) != 0 && ! warned
)
1092 as_tsktsk (_("register list not in ascending order"));
1096 mask
|= 1 << new_base
;
1099 if (**str
== '-') /* We have the start of a range expression */
1105 if ((high_range
= arm_reg_parse (str
, regtype
)) == FAIL
)
1107 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1111 if (high_range
<= new_base
)
1113 inst
.error
= _("register range not in ascending order");
1117 for (new_base
++; new_base
<= high_range
; new_base
++)
1119 if (mask
& (1 << new_base
))
1121 inst
.error
= _("invalid register list");
1125 mask
|= 1 << new_base
;
1130 while (skip_past_comma (str
) != FAIL
);
1134 /* Sanity check -- should have raised a parse error above. */
1135 if (count
== 0 || count
> max_regs
)
1140 /* Final test -- the registers must be consecutive. */
1142 for (i
= 0; i
< count
; i
++)
1144 if ((mask
& (1u << i
)) == 0)
1146 inst
.error
= _("non-contiguous register range");
1154 /* Parse an explicit relocation suffix on an expression. This is
1155 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1156 arm_reloc_hsh contains no entries, so this function can only
1157 succeed if there is no () after the word. Returns -1 on error,
1158 BFD_RELOC_UNUSED if there wasn't any suffix. */
1160 parse_reloc (char **str
)
1162 struct reloc_entry
*r
;
1166 return BFD_RELOC_UNUSED
;
1171 while (*q
&& *q
!= ')' && *q
!= ',')
1176 if ((r
= hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
1183 /* Directives: register aliases. */
1186 insert_reg_alias (char *str
, int number
, int type
)
1188 struct reg_entry
*new;
1191 if ((new = hash_find (arm_reg_hsh
, str
)) != 0)
1194 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
1196 /* Only warn about a redefinition if it's not defined as the
1198 else if (new->number
!= number
|| new->type
!= type
)
1199 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1204 name
= xstrdup (str
);
1205 new = xmalloc (sizeof (struct reg_entry
));
1208 new->number
= number
;
1210 new->builtin
= FALSE
;
1212 if (hash_insert (arm_reg_hsh
, name
, (PTR
) new))
1216 /* Look for the .req directive. This is of the form:
1218 new_register_name .req existing_register_name
1220 If we find one, or if it looks sufficiently like one that we want to
1221 handle any error here, return non-zero. Otherwise return zero. */
1224 create_register_alias (char * newname
, char *p
)
1226 struct reg_entry
*old
;
1227 char *oldname
, *nbuf
;
1230 /* The input scrubber ensures that whitespace after the mnemonic is
1231 collapsed to single spaces. */
1233 if (strncmp (oldname
, " .req ", 6) != 0)
1237 if (*oldname
== '\0')
1240 old
= hash_find (arm_reg_hsh
, oldname
);
1243 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1247 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1248 the desired alias name, and p points to its end. If not, then
1249 the desired alias name is in the global original_case_string. */
1250 #ifdef TC_CASE_SENSITIVE
1253 newname
= original_case_string
;
1254 nlen
= strlen (newname
);
1257 nbuf
= alloca (nlen
+ 1);
1258 memcpy (nbuf
, newname
, nlen
);
1261 /* Create aliases under the new name as stated; an all-lowercase
1262 version of the new name; and an all-uppercase version of the new
1264 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1266 for (p
= nbuf
; *p
; p
++)
1269 if (strncmp (nbuf
, newname
, nlen
))
1270 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1272 for (p
= nbuf
; *p
; p
++)
1275 if (strncmp (nbuf
, newname
, nlen
))
1276 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1281 /* Should never be called, as .req goes between the alias and the
1282 register name, not at the beginning of the line. */
1284 s_req (int a ATTRIBUTE_UNUSED
)
1286 as_bad (_("invalid syntax for .req directive"));
1289 /* The .unreq directive deletes an alias which was previously defined
1290 by .req. For example:
1296 s_unreq (int a ATTRIBUTE_UNUSED
)
1301 name
= input_line_pointer
;
1303 while (*input_line_pointer
!= 0
1304 && *input_line_pointer
!= ' '
1305 && *input_line_pointer
!= '\n')
1306 ++input_line_pointer
;
1308 saved_char
= *input_line_pointer
;
1309 *input_line_pointer
= 0;
1312 as_bad (_("invalid syntax for .unreq directive"));
1315 struct reg_entry
*reg
= hash_find (arm_reg_hsh
, name
);
1318 as_bad (_("unknown register alias '%s'"), name
);
1319 else if (reg
->builtin
)
1320 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1324 hash_delete (arm_reg_hsh
, name
);
1325 free ((char *) reg
->name
);
1330 *input_line_pointer
= saved_char
;
1331 demand_empty_rest_of_line ();
1334 /* Directives: Instruction set selection. */
1337 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
1338 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
1339 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1340 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1342 static enum mstate mapstate
= MAP_UNDEFINED
;
1345 mapping_state (enum mstate state
)
1348 const char * symname
;
1351 if (mapstate
== state
)
1352 /* The mapping symbol has already been emitted.
1353 There is nothing else to do. */
1362 type
= BSF_NO_FLAGS
;
1366 type
= BSF_NO_FLAGS
;
1370 type
= BSF_NO_FLAGS
;
1378 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1380 symbolP
= symbol_new (symname
, now_seg
, (valueT
) frag_now_fix (), frag_now
);
1381 symbol_table_insert (symbolP
);
1382 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1387 THUMB_SET_FUNC (symbolP
, 0);
1388 ARM_SET_THUMB (symbolP
, 0);
1389 ARM_SET_INTERWORK (symbolP
, support_interwork
);
1393 THUMB_SET_FUNC (symbolP
, 1);
1394 ARM_SET_THUMB (symbolP
, 1);
1395 ARM_SET_INTERWORK (symbolP
, support_interwork
);
1404 #define mapping_state(x) /* nothing */
1407 /* Find the real, Thumb encoded start of a Thumb function. */
1410 find_real_start (symbolS
* symbolP
)
1413 const char * name
= S_GET_NAME (symbolP
);
1414 symbolS
* new_target
;
1416 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
1417 #define STUB_NAME ".real_start_of"
1422 /* The compiler may generate BL instructions to local labels because
1423 it needs to perform a branch to a far away location. These labels
1424 do not have a corresponding ".real_start_of" label. We check
1425 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
1426 the ".real_start_of" convention for nonlocal branches. */
1427 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
1430 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
1431 new_target
= symbol_find (real_start
);
1433 if (new_target
== NULL
)
1435 as_warn ("Failed to find real start of function: %s\n", name
);
1436 new_target
= symbolP
;
1443 opcode_select (int width
)
1450 if (! (cpu_variant
& ARM_EXT_V4T
))
1451 as_bad (_("selected processor does not support THUMB opcodes"));
1454 /* No need to force the alignment, since we will have been
1455 coming from ARM mode, which is word-aligned. */
1456 record_alignment (now_seg
, 1);
1458 mapping_state (MAP_THUMB
);
1464 if ((cpu_variant
& ARM_ALL
) == ARM_EXT_V4T
)
1465 as_bad (_("selected processor does not support ARM opcodes"));
1470 frag_align (2, 0, 0);
1472 record_alignment (now_seg
, 1);
1474 mapping_state (MAP_ARM
);
1478 as_bad (_("invalid instruction size selected (%d)"), width
);
1483 s_arm (int ignore ATTRIBUTE_UNUSED
)
1486 demand_empty_rest_of_line ();
1490 s_thumb (int ignore ATTRIBUTE_UNUSED
)
1493 demand_empty_rest_of_line ();
1497 s_code (int unused ATTRIBUTE_UNUSED
)
1501 temp
= get_absolute_expression ();
1506 opcode_select (temp
);
1510 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
1515 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
1517 /* If we are not already in thumb mode go into it, EVEN if
1518 the target processor does not support thumb instructions.
1519 This is used by gcc/config/arm/lib1funcs.asm for example
1520 to compile interworking support functions even if the
1521 target processor should not support interworking. */
1525 record_alignment (now_seg
, 1);
1528 demand_empty_rest_of_line ();
1532 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
1536 /* The following label is the name/address of the start of a Thumb function.
1537 We need to know this for the interworking support. */
1538 label_is_thumb_function_name
= TRUE
;
1541 /* Perform a .set directive, but also mark the alias as
1542 being a thumb function. */
1545 s_thumb_set (int equiv
)
1547 /* XXX the following is a duplicate of the code for s_set() in read.c
1548 We cannot just call that code as we need to get at the symbol that
1555 /* Especial apologies for the random logic:
1556 This just grew, and could be parsed much more simply!
1558 name
= input_line_pointer
;
1559 delim
= get_symbol_end ();
1560 end_name
= input_line_pointer
;
1563 if (*input_line_pointer
!= ',')
1566 as_bad (_("expected comma after name \"%s\""), name
);
1568 ignore_rest_of_line ();
1572 input_line_pointer
++;
1575 if (name
[0] == '.' && name
[1] == '\0')
1577 /* XXX - this should not happen to .thumb_set. */
1581 if ((symbolP
= symbol_find (name
)) == NULL
1582 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
1585 /* When doing symbol listings, play games with dummy fragments living
1586 outside the normal fragment chain to record the file and line info
1588 if (listing
& LISTING_SYMBOLS
)
1590 extern struct list_info_struct
* listing_tail
;
1591 fragS
* dummy_frag
= xmalloc (sizeof (fragS
));
1593 memset (dummy_frag
, 0, sizeof (fragS
));
1594 dummy_frag
->fr_type
= rs_fill
;
1595 dummy_frag
->line
= listing_tail
;
1596 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
1597 dummy_frag
->fr_symbol
= symbolP
;
1601 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
1604 /* "set" symbols are local unless otherwise specified. */
1605 SF_SET_LOCAL (symbolP
);
1606 #endif /* OBJ_COFF */
1607 } /* Make a new symbol. */
1609 symbol_table_insert (symbolP
);
1614 && S_IS_DEFINED (symbolP
)
1615 && S_GET_SEGMENT (symbolP
) != reg_section
)
1616 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
1618 pseudo_set (symbolP
);
1620 demand_empty_rest_of_line ();
1622 /* XXX Now we come to the Thumb specific bit of code. */
1624 THUMB_SET_FUNC (symbolP
, 1);
1625 ARM_SET_THUMB (symbolP
, 1);
1626 #if defined OBJ_ELF || defined OBJ_COFF
1627 ARM_SET_INTERWORK (symbolP
, support_interwork
);
1631 /* Directives: Mode selection. */
1633 /* .syntax [unified|divided] - choose the new unified syntax
1634 (same for Arm and Thumb encoding, modulo slight differences in what
1635 can be represented) or the old divergent syntax for each mode. */
1637 s_syntax (int unused ATTRIBUTE_UNUSED
)
1641 name
= input_line_pointer
;
1642 delim
= get_symbol_end ();
1644 if (!strcasecmp (name
, "unified"))
1645 unified_syntax
= TRUE
;
1646 else if (!strcasecmp (name
, "divided"))
1647 unified_syntax
= FALSE
;
1650 as_bad (_("unrecognized syntax mode \"%s\""), name
);
1653 *input_line_pointer
= delim
;
1654 demand_empty_rest_of_line ();
1657 /* Directives: sectioning and alignment. */
1659 /* Same as s_align_ptwo but align 0 => align 2. */
1662 s_align (int unused ATTRIBUTE_UNUSED
)
1666 long max_alignment
= 15;
1668 temp
= get_absolute_expression ();
1669 if (temp
> max_alignment
)
1670 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
1673 as_bad (_("alignment negative. 0 assumed."));
1677 if (*input_line_pointer
== ',')
1679 input_line_pointer
++;
1680 temp_fill
= get_absolute_expression ();
1688 /* Only make a frag if we HAVE to. */
1689 if (temp
&& !need_pass_2
)
1690 frag_align (temp
, (int) temp_fill
, 0);
1691 demand_empty_rest_of_line ();
1693 record_alignment (now_seg
, temp
);
1697 s_bss (int ignore ATTRIBUTE_UNUSED
)
1699 /* We don't support putting frags in the BSS segment, we fake it by
1700 marking in_bss, then looking at s_skip for clues. */
1701 subseg_set (bss_section
, 0);
1702 demand_empty_rest_of_line ();
1703 mapping_state (MAP_DATA
);
1707 s_even (int ignore ATTRIBUTE_UNUSED
)
1709 /* Never make frag if expect extra pass. */
1711 frag_align (1, 0, 0);
1713 record_alignment (now_seg
, 1);
1715 demand_empty_rest_of_line ();
1718 /* Directives: Literal pools. */
1720 static literal_pool
*
1721 find_literal_pool (void)
1723 literal_pool
* pool
;
1725 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1727 if (pool
->section
== now_seg
1728 && pool
->sub_section
== now_subseg
)
1735 static literal_pool
*
1736 find_or_make_literal_pool (void)
1738 /* Next literal pool ID number. */
1739 static unsigned int latest_pool_num
= 1;
1740 literal_pool
* pool
;
1742 pool
= find_literal_pool ();
1746 /* Create a new pool. */
1747 pool
= xmalloc (sizeof (* pool
));
1751 pool
->next_free_entry
= 0;
1752 pool
->section
= now_seg
;
1753 pool
->sub_section
= now_subseg
;
1754 pool
->next
= list_of_pools
;
1755 pool
->symbol
= NULL
;
1757 /* Add it to the list. */
1758 list_of_pools
= pool
;
1761 /* New pools, and emptied pools, will have a NULL symbol. */
1762 if (pool
->symbol
== NULL
)
1764 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1765 (valueT
) 0, &zero_address_frag
);
1766 pool
->id
= latest_pool_num
++;
1773 /* Add the literal in the global 'inst'
1774 structure to the relevent literal pool. */
1777 add_to_lit_pool (void)
1779 literal_pool
* pool
;
1782 pool
= find_or_make_literal_pool ();
1784 /* Check if this literal value is already in the pool. */
1785 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1787 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
1788 && (inst
.reloc
.exp
.X_op
== O_constant
)
1789 && (pool
->literals
[entry
].X_add_number
1790 == inst
.reloc
.exp
.X_add_number
)
1791 && (pool
->literals
[entry
].X_unsigned
1792 == inst
.reloc
.exp
.X_unsigned
))
1795 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
1796 && (inst
.reloc
.exp
.X_op
== O_symbol
)
1797 && (pool
->literals
[entry
].X_add_number
1798 == inst
.reloc
.exp
.X_add_number
)
1799 && (pool
->literals
[entry
].X_add_symbol
1800 == inst
.reloc
.exp
.X_add_symbol
)
1801 && (pool
->literals
[entry
].X_op_symbol
1802 == inst
.reloc
.exp
.X_op_symbol
))
1806 /* Do we need to create a new entry? */
1807 if (entry
== pool
->next_free_entry
)
1809 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1811 inst
.error
= _("literal pool overflow");
1815 pool
->literals
[entry
] = inst
.reloc
.exp
;
1816 pool
->next_free_entry
+= 1;
1819 inst
.reloc
.exp
.X_op
= O_symbol
;
1820 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
1821 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
1826 /* Can't use symbol_new here, so have to create a symbol and then at
1827 a later date assign it a value. Thats what these functions do. */
1830 symbol_locate (symbolS
* symbolP
,
1831 const char * name
, /* It is copied, the caller can modify. */
1832 segT segment
, /* Segment identifier (SEG_<something>). */
1833 valueT valu
, /* Symbol value. */
1834 fragS
* frag
) /* Associated fragment. */
1836 unsigned int name_length
;
1837 char * preserved_copy_of_name
;
1839 name_length
= strlen (name
) + 1; /* +1 for \0. */
1840 obstack_grow (¬es
, name
, name_length
);
1841 preserved_copy_of_name
= obstack_finish (¬es
);
1843 #ifdef tc_canonicalize_symbol_name
1844 preserved_copy_of_name
=
1845 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1848 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1850 S_SET_SEGMENT (symbolP
, segment
);
1851 S_SET_VALUE (symbolP
, valu
);
1852 symbol_clear_list_pointers (symbolP
);
1854 symbol_set_frag (symbolP
, frag
);
1856 /* Link to end of symbol chain. */
1858 extern int symbol_table_frozen
;
1860 if (symbol_table_frozen
)
1864 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
1866 obj_symbol_new_hook (symbolP
);
1868 #ifdef tc_symbol_new_hook
1869 tc_symbol_new_hook (symbolP
);
1873 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1874 #endif /* DEBUG_SYMS */
1879 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1882 literal_pool
* pool
;
1885 pool
= find_literal_pool ();
1887 || pool
->symbol
== NULL
1888 || pool
->next_free_entry
== 0)
1891 mapping_state (MAP_DATA
);
1893 /* Align pool as you have word accesses.
1894 Only make a frag if we have to. */
1896 frag_align (2, 0, 0);
1898 record_alignment (now_seg
, 2);
1900 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1902 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1903 (valueT
) frag_now_fix (), frag_now
);
1904 symbol_table_insert (pool
->symbol
);
1906 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
1908 #if defined OBJ_COFF || defined OBJ_ELF
1909 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
1912 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1913 /* First output the expression in the instruction to the pool. */
1914 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
1916 /* Mark the pool as empty. */
1917 pool
->next_free_entry
= 0;
1918 pool
->symbol
= NULL
;
1922 /* Forward declarations for functions below, in the MD interface
1924 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
1925 static valueT
create_unwind_entry (int);
1926 static void start_unwind_section (const segT
, int);
1927 static void add_unwind_opcode (valueT
, int);
1928 static void flush_pending_unwind (void);
1930 /* Directives: Data. */
1933 s_arm_elf_cons (int nbytes
)
1937 #ifdef md_flush_pending_output
1938 md_flush_pending_output ();
1941 if (is_it_end_of_statement ())
1943 demand_empty_rest_of_line ();
1947 #ifdef md_cons_align
1948 md_cons_align (nbytes
);
1951 mapping_state (MAP_DATA
);
1955 char *base
= input_line_pointer
;
1959 if (exp
.X_op
!= O_symbol
)
1960 emit_expr (&exp
, (unsigned int) nbytes
);
1963 char *before_reloc
= input_line_pointer
;
1964 reloc
= parse_reloc (&input_line_pointer
);
1967 as_bad (_("unrecognized relocation suffix"));
1968 ignore_rest_of_line ();
1971 else if (reloc
== BFD_RELOC_UNUSED
)
1972 emit_expr (&exp
, (unsigned int) nbytes
);
1975 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
1976 int size
= bfd_get_reloc_size (howto
);
1978 if (reloc
== BFD_RELOC_ARM_PLT32
)
1980 as_bad (_("(plt) is only valid on branch targets"));
1981 reloc
= BFD_RELOC_UNUSED
;
1986 as_bad (_("%s relocations do not fit in %d bytes"),
1987 howto
->name
, nbytes
);
1990 /* We've parsed an expression stopping at O_symbol.
1991 But there may be more expression left now that we
1992 have parsed the relocation marker. Parse it again.
1993 XXX Surely there is a cleaner way to do this. */
1994 char *p
= input_line_pointer
;
1996 char *save_buf
= alloca (input_line_pointer
- base
);
1997 memcpy (save_buf
, base
, input_line_pointer
- base
);
1998 memmove (base
+ (input_line_pointer
- before_reloc
),
1999 base
, before_reloc
- base
);
2001 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
2003 memcpy (base
, save_buf
, p
- base
);
2005 offset
= nbytes
- size
;
2006 p
= frag_more ((int) nbytes
);
2007 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
2008 size
, &exp
, 0, reloc
);
2013 while (*input_line_pointer
++ == ',');
2015 /* Put terminator back into stream. */
2016 input_line_pointer
--;
2017 demand_empty_rest_of_line ();
2021 /* Parse a .rel31 directive. */
2024 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
2031 if (*input_line_pointer
== '1')
2032 highbit
= 0x80000000;
2033 else if (*input_line_pointer
!= '0')
2034 as_bad (_("expected 0 or 1"));
2036 input_line_pointer
++;
2037 if (*input_line_pointer
!= ',')
2038 as_bad (_("missing comma"));
2039 input_line_pointer
++;
2041 #ifdef md_flush_pending_output
2042 md_flush_pending_output ();
2045 #ifdef md_cons_align
2049 mapping_state (MAP_DATA
);
2054 md_number_to_chars (p
, highbit
, 4);
2055 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
2056 BFD_RELOC_ARM_PREL31
);
2058 demand_empty_rest_of_line ();
2061 /* Directives: AEABI stack-unwind tables. */
2063 /* Parse an unwind_fnstart directive. Simply records the current location. */
2066 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
2068 demand_empty_rest_of_line ();
2069 /* Mark the start of the function. */
2070 unwind
.proc_start
= expr_build_dot ();
2072 /* Reset the rest of the unwind info. */
2073 unwind
.opcode_count
= 0;
2074 unwind
.table_entry
= NULL
;
2075 unwind
.personality_routine
= NULL
;
2076 unwind
.personality_index
= -1;
2077 unwind
.frame_size
= 0;
2078 unwind
.fp_offset
= 0;
2081 unwind
.sp_restored
= 0;
2085 /* Parse a handlerdata directive. Creates the exception handling table entry
2086 for the function. */
2089 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
2091 demand_empty_rest_of_line ();
2092 if (unwind
.table_entry
)
2093 as_bad (_("dupicate .handlerdata directive"));
2095 create_unwind_entry (1);
2098 /* Parse an unwind_fnend directive. Generates the index table entry. */
2101 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
2107 demand_empty_rest_of_line ();
2109 /* Add eh table entry. */
2110 if (unwind
.table_entry
== NULL
)
2111 val
= create_unwind_entry (0);
2115 /* Add index table entry. This is two words. */
2116 start_unwind_section (unwind
.saved_seg
, 1);
2117 frag_align (2, 0, 0);
2118 record_alignment (now_seg
, 2);
2120 ptr
= frag_more (8);
2121 where
= frag_now_fix () - 8;
2123 /* Self relative offset of the function start. */
2124 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
2125 BFD_RELOC_ARM_PREL31
);
2127 /* Indicate dependency on EHABI-defined personality routines to the
2128 linker, if it hasn't been done already. */
2129 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
2130 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
2132 static const char *const name
[] = {
2133 "__aeabi_unwind_cpp_pr0",
2134 "__aeabi_unwind_cpp_pr1",
2135 "__aeabi_unwind_cpp_pr2"
2137 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
2138 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
2139 marked_pr_dependency
|= 1 << unwind
.personality_index
;
2140 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
2141 = marked_pr_dependency
;
2145 /* Inline exception table entry. */
2146 md_number_to_chars (ptr
+ 4, val
, 4);
2148 /* Self relative offset of the table entry. */
2149 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
2150 BFD_RELOC_ARM_PREL31
);
2152 /* Restore the original section. */
2153 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
2157 /* Parse an unwind_cantunwind directive. */
2160 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
2162 demand_empty_rest_of_line ();
2163 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
2164 as_bad (_("personality routine specified for cantunwind frame"));
2166 unwind
.personality_index
= -2;
2170 /* Parse a personalityindex directive. */
2173 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
2177 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
2178 as_bad (_("duplicate .personalityindex directive"));
2182 if (exp
.X_op
!= O_constant
2183 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
2185 as_bad (_("bad personality routine number"));
2186 ignore_rest_of_line ();
2190 unwind
.personality_index
= exp
.X_add_number
;
2192 demand_empty_rest_of_line ();
2196 /* Parse a personality directive. */
2199 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
2203 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
2204 as_bad (_("duplicate .personality directive"));
2206 name
= input_line_pointer
;
2207 c
= get_symbol_end ();
2208 p
= input_line_pointer
;
2209 unwind
.personality_routine
= symbol_find_or_make (name
);
2211 demand_empty_rest_of_line ();
2215 /* Parse a directive saving core registers. */
2218 s_arm_unwind_save_core (void)
2224 range
= parse_reg_list (&input_line_pointer
);
2227 as_bad (_("expected register list"));
2228 ignore_rest_of_line ();
2232 demand_empty_rest_of_line ();
2234 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
2235 into .unwind_save {..., sp...}. We aren't bothered about the value of
2236 ip because it is clobbered by calls. */
2237 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
2238 && (range
& 0x3000) == 0x1000)
2240 unwind
.opcode_count
--;
2241 unwind
.sp_restored
= 0;
2242 range
= (range
| 0x2000) & ~0x1000;
2243 unwind
.pending_offset
= 0;
2246 /* See if we can use the short opcodes. These pop a block of upto 8
2247 registers starting with r4, plus maybe r14. */
2248 for (n
= 0; n
< 8; n
++)
2250 /* Break at the first non-saved register. */
2251 if ((range
& (1 << (n
+ 4))) == 0)
2254 /* See if there are any other bits set. */
2255 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
2257 /* Use the long form. */
2258 op
= 0x8000 | ((range
>> 4) & 0xfff);
2259 add_unwind_opcode (op
, 2);
2263 /* Use the short form. */
2265 op
= 0xa8; /* Pop r14. */
2267 op
= 0xa0; /* Do not pop r14. */
2269 add_unwind_opcode (op
, 1);
2275 op
= 0xb100 | (range
& 0xf);
2276 add_unwind_opcode (op
, 2);
2279 /* Record the number of bytes pushed. */
2280 for (n
= 0; n
< 16; n
++)
2282 if (range
& (1 << n
))
2283 unwind
.frame_size
+= 4;
2288 /* Parse a directive saving FPA registers. */
2291 s_arm_unwind_save_fpa (int reg
)
2297 /* Get Number of registers to transfer. */
2298 if (skip_past_comma (&input_line_pointer
) != FAIL
)
2301 exp
.X_op
= O_illegal
;
2303 if (exp
.X_op
!= O_constant
)
2305 as_bad (_("expected , <constant>"));
2306 ignore_rest_of_line ();
2310 num_regs
= exp
.X_add_number
;
2312 if (num_regs
< 1 || num_regs
> 4)
2314 as_bad (_("number of registers must be in the range [1:4]"));
2315 ignore_rest_of_line ();
2319 demand_empty_rest_of_line ();
2324 op
= 0xb4 | (num_regs
- 1);
2325 add_unwind_opcode (op
, 1);
2330 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
2331 add_unwind_opcode (op
, 2);
2333 unwind
.frame_size
+= num_regs
* 12;
2337 /* Parse a directive saving VFP registers. */
2340 s_arm_unwind_save_vfp (void)
2346 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, 1);
2349 as_bad (_("expected register list"));
2350 ignore_rest_of_line ();
2354 demand_empty_rest_of_line ();
2359 op
= 0xb8 | (count
- 1);
2360 add_unwind_opcode (op
, 1);
2365 op
= 0xb300 | (reg
<< 4) | (count
- 1);
2366 add_unwind_opcode (op
, 2);
2368 unwind
.frame_size
+= count
* 8 + 4;
2372 /* Parse a directive saving iWMMXt data registers. */
2375 s_arm_unwind_save_mmxwr (void)
2383 if (*input_line_pointer
== '{')
2384 input_line_pointer
++;
2388 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
2392 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
2397 as_tsktsk (_("register list not in ascending order"));
2400 if (*input_line_pointer
== '-')
2402 input_line_pointer
++;
2403 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
2406 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
2409 else if (reg
>= hi_reg
)
2411 as_bad (_("bad register range"));
2414 for (; reg
< hi_reg
; reg
++)
2418 while (skip_past_comma (&input_line_pointer
) != FAIL
);
2420 if (*input_line_pointer
== '}')
2421 input_line_pointer
++;
2423 demand_empty_rest_of_line ();
2425 /* Generate any deferred opcodes becuuse we're going to be looking at
2427 flush_pending_unwind ();
2429 for (i
= 0; i
< 16; i
++)
2431 if (mask
& (1 << i
))
2432 unwind
.frame_size
+= 8;
2435 /* Attempt to combine with a previous opcode. We do this because gcc
2436 likes to output separate unwind directives for a single block of
2438 if (unwind
.opcode_count
> 0)
2440 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
2441 if ((i
& 0xf8) == 0xc0)
2444 /* Only merge if the blocks are contiguous. */
2447 if ((mask
& 0xfe00) == (1 << 9))
2449 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
2450 unwind
.opcode_count
--;
2453 else if (i
== 6 && unwind
.opcode_count
>= 2)
2455 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
2459 op
= 0xffff << (reg
- 1);
2461 || ((mask
& op
) == (1u << (reg
- 1))))
2463 op
= (1 << (reg
+ i
+ 1)) - 1;
2464 op
&= ~((1 << reg
) - 1);
2466 unwind
.opcode_count
-= 2;
2473 /* We want to generate opcodes in the order the registers have been
2474 saved, ie. descending order. */
2475 for (reg
= 15; reg
>= -1; reg
--)
2477 /* Save registers in blocks. */
2479 || !(mask
& (1 << reg
)))
2481 /* We found an unsaved reg. Generate opcodes to save the
2482 preceeding block. */
2488 op
= 0xc0 | (hi_reg
- 10);
2489 add_unwind_opcode (op
, 1);
2494 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
2495 add_unwind_opcode (op
, 2);
2504 ignore_rest_of_line ();
2508 s_arm_unwind_save_mmxwcg (void)
2515 if (*input_line_pointer
== '{')
2516 input_line_pointer
++;
2520 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
2524 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
2530 as_tsktsk (_("register list not in ascending order"));
2533 if (*input_line_pointer
== '-')
2535 input_line_pointer
++;
2536 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
2539 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
2542 else if (reg
>= hi_reg
)
2544 as_bad (_("bad register range"));
2547 for (; reg
< hi_reg
; reg
++)
2551 while (skip_past_comma (&input_line_pointer
) != FAIL
);
2553 if (*input_line_pointer
== '}')
2554 input_line_pointer
++;
2556 demand_empty_rest_of_line ();
2558 /* Generate any deferred opcodes becuuse we're going to be looking at
2560 flush_pending_unwind ();
2562 for (reg
= 0; reg
< 16; reg
++)
2564 if (mask
& (1 << reg
))
2565 unwind
.frame_size
+= 4;
2568 add_unwind_opcode (op
, 2);
2571 ignore_rest_of_line ();
2575 /* Parse an unwind_save directive. */
2578 s_arm_unwind_save (int ignored ATTRIBUTE_UNUSED
)
2581 struct reg_entry
*reg
;
2582 bfd_boolean had_brace
= FALSE
;
2584 /* Figure out what sort of save we have. */
2585 peek
= input_line_pointer
;
2593 reg
= arm_reg_parse_multi (&peek
);
2597 as_bad (_("register expected"));
2598 ignore_rest_of_line ();
2607 as_bad (_("FPA .unwind_save does not take a register list"));
2608 ignore_rest_of_line ();
2611 s_arm_unwind_save_fpa (reg
->number
);
2614 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
2615 case REG_TYPE_VFD
: s_arm_unwind_save_vfp (); return;
2616 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
2617 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
2620 as_bad (_(".unwind_save does not support this kind of register"));
2621 ignore_rest_of_line ();
2626 /* Parse an unwind_movsp directive. */
2629 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
2634 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
2637 as_bad (_(reg_expected_msgs
[REG_TYPE_RN
]));
2638 ignore_rest_of_line ();
2641 demand_empty_rest_of_line ();
2643 if (reg
== REG_SP
|| reg
== REG_PC
)
2645 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
2649 if (unwind
.fp_reg
!= REG_SP
)
2650 as_bad (_("unexpected .unwind_movsp directive"));
2652 /* Generate opcode to restore the value. */
2654 add_unwind_opcode (op
, 1);
2656 /* Record the information for later. */
2657 unwind
.fp_reg
= reg
;
2658 unwind
.fp_offset
= unwind
.frame_size
;
2659 unwind
.sp_restored
= 1;
2662 /* Parse an unwind_pad directive. */
2665 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
2669 if (immediate_for_directive (&offset
) == FAIL
)
2674 as_bad (_("stack increment must be multiple of 4"));
2675 ignore_rest_of_line ();
2679 /* Don't generate any opcodes, just record the details for later. */
2680 unwind
.frame_size
+= offset
;
2681 unwind
.pending_offset
+= offset
;
2683 demand_empty_rest_of_line ();
2686 /* Parse an unwind_setfp directive. */
2689 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
2695 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
2696 if (skip_past_comma (&input_line_pointer
) == FAIL
)
2699 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
2701 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
2703 as_bad (_("expected <reg>, <reg>"));
2704 ignore_rest_of_line ();
2708 /* Optional constant. */
2709 if (skip_past_comma (&input_line_pointer
) != FAIL
)
2711 if (immediate_for_directive (&offset
) == FAIL
)
2717 demand_empty_rest_of_line ();
2719 if (sp_reg
!= 13 && sp_reg
!= unwind
.fp_reg
)
2721 as_bad (_("register must be either sp or set by a previous"
2722 "unwind_movsp directive"));
2726 /* Don't generate any opcodes, just record the information for later. */
2727 unwind
.fp_reg
= fp_reg
;
2730 unwind
.fp_offset
= unwind
.frame_size
- offset
;
2732 unwind
.fp_offset
-= offset
;
2735 /* Parse an unwind_raw directive. */
2738 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
2741 /* This is an arbitary limit. */
2742 unsigned char op
[16];
2746 if (exp
.X_op
== O_constant
2747 && skip_past_comma (&input_line_pointer
) != FAIL
)
2749 unwind
.frame_size
+= exp
.X_add_number
;
2753 exp
.X_op
= O_illegal
;
2755 if (exp
.X_op
!= O_constant
)
2757 as_bad (_("expected <offset>, <opcode>"));
2758 ignore_rest_of_line ();
2764 /* Parse the opcode. */
2769 as_bad (_("unwind opcode too long"));
2770 ignore_rest_of_line ();
2772 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
2774 as_bad (_("invalid unwind opcode"));
2775 ignore_rest_of_line ();
2778 op
[count
++] = exp
.X_add_number
;
2780 /* Parse the next byte. */
2781 if (skip_past_comma (&input_line_pointer
) == FAIL
)
2787 /* Add the opcode bytes in reverse order. */
2789 add_unwind_opcode (op
[count
], 1);
2791 demand_empty_rest_of_line ();
2793 #endif /* OBJ_ELF */
2795 /* This table describes all the machine specific pseudo-ops the assembler
2796 has to support. The fields are:
2797 pseudo-op name without dot
2798 function to call to execute this pseudo-op
2799 Integer arg to pass to the function. */
2801 const pseudo_typeS md_pseudo_table
[] =
2803 /* Never called because '.req' does not start a line. */
2804 { "req", s_req
, 0 },
2805 { "unreq", s_unreq
, 0 },
2806 { "bss", s_bss
, 0 },
2807 { "align", s_align
, 0 },
2808 { "arm", s_arm
, 0 },
2809 { "thumb", s_thumb
, 0 },
2810 { "code", s_code
, 0 },
2811 { "force_thumb", s_force_thumb
, 0 },
2812 { "thumb_func", s_thumb_func
, 0 },
2813 { "thumb_set", s_thumb_set
, 0 },
2814 { "even", s_even
, 0 },
2815 { "ltorg", s_ltorg
, 0 },
2816 { "pool", s_ltorg
, 0 },
2817 { "syntax", s_syntax
, 0 },
2819 { "word", s_arm_elf_cons
, 4 },
2820 { "long", s_arm_elf_cons
, 4 },
2821 { "rel31", s_arm_rel31
, 0 },
2822 { "fnstart", s_arm_unwind_fnstart
, 0 },
2823 { "fnend", s_arm_unwind_fnend
, 0 },
2824 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
2825 { "personality", s_arm_unwind_personality
, 0 },
2826 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
2827 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
2828 { "save", s_arm_unwind_save
, 0 },
2829 { "movsp", s_arm_unwind_movsp
, 0 },
2830 { "pad", s_arm_unwind_pad
, 0 },
2831 { "setfp", s_arm_unwind_setfp
, 0 },
2832 { "unwind_raw", s_arm_unwind_raw
, 0 },
2836 { "extend", float_cons
, 'x' },
2837 { "ldouble", float_cons
, 'x' },
2838 { "packed", float_cons
, 'p' },
2842 /* Parser functions used exclusively in instruction operands. */
2844 /* Generic immediate-value read function for use in insn parsing.
2845 STR points to the beginning of the immediate (the leading #);
2846 VAL receives the value; if the value is outside [MIN, MAX]
2847 issue an error. PREFIX_OPT is true if the immediate prefix is
2851 parse_immediate (char **str
, int *val
, int min
, int max
,
2852 bfd_boolean prefix_opt
)
2855 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
2856 if (exp
.X_op
!= O_constant
)
2858 inst
.error
= _("constant expression required");
2862 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
2864 inst
.error
= _("immediate value out of range");
2868 *val
= exp
.X_add_number
;
2872 /* Returns the pseudo-register number of an FPA immediate constant,
2873 or FAIL if there isn't a valid constant here. */
2876 parse_fpa_immediate (char ** str
)
2878 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2884 /* First try and match exact strings, this is to guarantee
2885 that some formats will work even for cross assembly. */
2887 for (i
= 0; fp_const
[i
]; i
++)
2889 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
2893 *str
+= strlen (fp_const
[i
]);
2894 if (is_end_of_line
[(unsigned char) **str
])
2900 /* Just because we didn't get a match doesn't mean that the constant
2901 isn't valid, just that it is in a format that we don't
2902 automatically recognize. Try parsing it with the standard
2903 expression routines. */
2905 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
2907 /* Look for a raw floating point number. */
2908 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
2909 && is_end_of_line
[(unsigned char) *save_in
])
2911 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
2913 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
2915 if (words
[j
] != fp_values
[i
][j
])
2919 if (j
== MAX_LITTLENUMS
)
2927 /* Try and parse a more complex expression, this will probably fail
2928 unless the code uses a floating point prefix (eg "0f"). */
2929 save_in
= input_line_pointer
;
2930 input_line_pointer
= *str
;
2931 if (expression (&exp
) == absolute_section
2932 && exp
.X_op
== O_big
2933 && exp
.X_add_number
< 0)
2935 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
2937 if (gen_to_words (words
, 5, (long) 15) == 0)
2939 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
2941 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
2943 if (words
[j
] != fp_values
[i
][j
])
2947 if (j
== MAX_LITTLENUMS
)
2949 *str
= input_line_pointer
;
2950 input_line_pointer
= save_in
;
2957 *str
= input_line_pointer
;
2958 input_line_pointer
= save_in
;
2959 inst
.error
= _("invalid FPA immediate expression");
2963 /* Shift operands. */
2966 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
2969 struct asm_shift_name
2972 enum shift_kind kind
;
2975 /* Third argument to parse_shift. */
2976 enum parse_shift_mode
2978 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
2979 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
2980 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
2981 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
2982 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
2985 /* Parse a <shift> specifier on an ARM data processing instruction.
2986 This has three forms:
2988 (LSL|LSR|ASL|ASR|ROR) Rs
2989 (LSL|LSR|ASL|ASR|ROR) #imm
2992 Note that ASL is assimilated to LSL in the instruction encoding, and
2993 RRX to ROR #0 (which cannot be written as such). */
2996 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
2998 const struct asm_shift_name
*shift_name
;
2999 enum shift_kind shift
;
3004 for (p
= *str
; ISALPHA (*p
); p
++)
3009 inst
.error
= _("shift expression expected");
3013 shift_name
= hash_find_n (arm_shift_hsh
, *str
, p
- *str
);
3015 if (shift_name
== NULL
)
3017 inst
.error
= _("shift expression expected");
3021 shift
= shift_name
->kind
;
3025 case NO_SHIFT_RESTRICT
:
3026 case SHIFT_IMMEDIATE
: break;
3028 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
3029 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
3031 inst
.error
= _("'LSL' or 'ASR' required");
3036 case SHIFT_LSL_IMMEDIATE
:
3037 if (shift
!= SHIFT_LSL
)
3039 inst
.error
= _("'LSL' required");
3044 case SHIFT_ASR_IMMEDIATE
:
3045 if (shift
!= SHIFT_ASR
)
3047 inst
.error
= _("'ASR' required");
3055 if (shift
!= SHIFT_RRX
)
3057 /* Whitespace can appear here if the next thing is a bare digit. */
3058 skip_whitespace (p
);
3060 if (mode
== NO_SHIFT_RESTRICT
3061 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
3063 inst
.operands
[i
].imm
= reg
;
3064 inst
.operands
[i
].immisreg
= 1;
3066 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
3069 inst
.operands
[i
].shift_kind
= shift
;
3070 inst
.operands
[i
].shifted
= 1;
3075 /* Parse a <shifter_operand> for an ARM data processing instruction:
3078 #<immediate>, <rotate>
3082 where <shift> is defined by parse_shift above, and <rotate> is a
3083 multiple of 2 between 0 and 30. Validation of immediate operands
3084 is deferred to md_apply_fix. */
3087 parse_shifter_operand (char **str
, int i
)
3092 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
3094 inst
.operands
[i
].reg
= value
;
3095 inst
.operands
[i
].isreg
= 1;
3097 /* parse_shift will override this if appropriate */
3098 inst
.reloc
.exp
.X_op
= O_constant
;
3099 inst
.reloc
.exp
.X_add_number
= 0;
3101 if (skip_past_comma (str
) == FAIL
)
3104 /* Shift operation on register. */
3105 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
3108 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
3111 if (skip_past_comma (str
) == SUCCESS
)
3113 /* #x, y -- ie explicit rotation by Y. */
3114 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
3117 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
3119 inst
.error
= _("constant expression expected");
3123 value
= expr
.X_add_number
;
3124 if (value
< 0 || value
> 30 || value
% 2 != 0)
3126 inst
.error
= _("invalid rotation");
3129 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
3131 inst
.error
= _("invalid constant");
3135 /* Convert to decoded value. md_apply_fix will put it back. */
3136 inst
.reloc
.exp
.X_add_number
3137 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
3138 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
3141 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
3142 inst
.reloc
.pc_rel
= 0;
3146 /* Parse all forms of an ARM address expression. Information is written
3147 to inst.operands[i] and/or inst.reloc.
3149 Preindexed addressing (.preind=1):
3151 [Rn, #offset] .reg=Rn .reloc.exp=offset
3152 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3153 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3154 .shift_kind=shift .reloc.exp=shift_imm
3156 These three may have a trailing ! which causes .writeback to be set also.
3158 Postindexed addressing (.postind=1, .writeback=1):
3160 [Rn], #offset .reg=Rn .reloc.exp=offset
3161 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3162 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3163 .shift_kind=shift .reloc.exp=shift_imm
3165 Unindexed addressing (.preind=0, .postind=0):
3167 [Rn], {option} .reg=Rn .imm=option .immisreg=0
3171 [Rn]{!} shorthand for [Rn,#0]{!}
3172 =immediate .isreg=0 .reloc.exp=immediate
3173 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
3175 It is the caller's responsibility to check for addressing modes not
3176 supported by the instruction, and to set inst.reloc.type. */
3179 parse_address (char **str
, int i
)
3184 if (skip_past_char (&p
, '[') == FAIL
)
3186 if (skip_past_char (&p
, '=') == FAIL
)
3188 /* bare address - translate to PC-relative offset */
3189 inst
.reloc
.pc_rel
= 1;
3190 inst
.operands
[i
].reg
= REG_PC
;
3191 inst
.operands
[i
].isreg
= 1;
3192 inst
.operands
[i
].preind
= 1;
3194 /* else a load-constant pseudo op, no special treatment needed here */
3196 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
3203 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
3205 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
3208 inst
.operands
[i
].reg
= reg
;
3209 inst
.operands
[i
].isreg
= 1;
3211 if (skip_past_comma (&p
) == SUCCESS
)
3213 inst
.operands
[i
].preind
= 1;
3216 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
3218 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
3220 inst
.operands
[i
].imm
= reg
;
3221 inst
.operands
[i
].immisreg
= 1;
3223 if (skip_past_comma (&p
) == SUCCESS
)
3224 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
3229 if (inst
.operands
[i
].negative
)
3231 inst
.operands
[i
].negative
= 0;
3234 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
3239 if (skip_past_char (&p
, ']') == FAIL
)
3241 inst
.error
= _("']' expected");
3245 if (skip_past_char (&p
, '!') == SUCCESS
)
3246 inst
.operands
[i
].writeback
= 1;
3248 else if (skip_past_comma (&p
) == SUCCESS
)
3250 if (skip_past_char (&p
, '{') == SUCCESS
)
3252 /* [Rn], {expr} - unindexed, with option */
3253 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
3254 0, 255, TRUE
) == FAIL
)
3257 if (skip_past_char (&p
, '}') == FAIL
)
3259 inst
.error
= _("'}' expected at end of 'option' field");
3262 if (inst
.operands
[i
].preind
)
3264 inst
.error
= _("cannot combine index with option");
3272 inst
.operands
[i
].postind
= 1;
3273 inst
.operands
[i
].writeback
= 1;
3275 if (inst
.operands
[i
].preind
)
3277 inst
.error
= _("cannot combine pre- and post-indexing");
3282 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
3284 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
3286 inst
.operands
[i
].imm
= reg
;
3287 inst
.operands
[i
].immisreg
= 1;
3289 if (skip_past_comma (&p
) == SUCCESS
)
3290 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
3295 if (inst
.operands
[i
].negative
)
3297 inst
.operands
[i
].negative
= 0;
3300 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
3306 /* If at this point neither .preind nor .postind is set, we have a
3307 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
3308 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
3310 inst
.operands
[i
].preind
= 1;
3311 inst
.reloc
.exp
.X_op
= O_constant
;
3312 inst
.reloc
.exp
.X_add_number
= 0;
3318 /* Miscellaneous. */
3320 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
3321 or a bitmask suitable to be or-ed into the ARM msr instruction. */
3323 parse_psr (char **str
)
3326 unsigned long psr_field
;
3328 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
3329 feature for ease of use and backwards compatibility. */
3331 if (*p
== 's' || *p
== 'S')
3332 psr_field
= SPSR_BIT
;
3333 else if (*p
== 'c' || *p
== 'C')
3339 if (strncasecmp (p
, "PSR", 3) != 0)
3345 /* A suffix follows. */
3346 const struct asm_psr
*psr
;
3354 while (ISALNUM (*p
) || *p
== '_');
3356 psr
= hash_find_n (arm_psr_hsh
, start
, p
- start
);
3360 psr_field
|= psr
->field
;
3365 goto error
; /* Garbage after "[CS]PSR". */
3367 psr_field
|= (PSR_c
| PSR_f
);
3373 inst
.error
= _("flag for {c}psr instruction expected");
3377 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
3378 value suitable for splatting into the AIF field of the instruction. */
3381 parse_cps_flags (char **str
)
3390 case '\0': case ',':
3393 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
3394 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
3395 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
3398 inst
.error
= _("unrecognized CPS flag");
3403 if (saw_a_flag
== 0)
3405 inst
.error
= _("missing CPS flags");
3413 /* Parse an endian specifier ("BE" or "LE", case insensitive);
3414 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
3417 parse_endian_specifier (char **str
)
3422 if (strncasecmp (s
, "BE", 2))
3424 else if (strncasecmp (s
, "LE", 2))
3428 inst
.error
= _("valid endian specifiers are be or le");
3432 if (ISALNUM (s
[2]) || s
[2] == '_')
3434 inst
.error
= _("valid endian specifiers are be or le");
3439 return little_endian
;
3442 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
3443 value suitable for poking into the rotate field of an sxt or sxta
3444 instruction, or FAIL on error. */
3447 parse_ror (char **str
)
3452 if (strncasecmp (s
, "ROR", 3) == 0)
3456 inst
.error
= _("missing rotation field after comma");
3460 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
3465 case 0: *str
= s
; return 0x0;
3466 case 8: *str
= s
; return 0x1;
3467 case 16: *str
= s
; return 0x2;
3468 case 24: *str
= s
; return 0x3;
3471 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
3476 /* Parse a conditional code (from conds[] below). The value returned is in the
3477 range 0 .. 14, or FAIL. */
3479 parse_cond (char **str
)
3482 const struct asm_cond
*c
;
3485 while (ISALPHA (*q
))
3488 c
= hash_find_n (arm_cond_hsh
, p
, q
- p
);
3491 inst
.error
= _("condition required");
3499 /* Parse the operands of a table branch instruction. Similar to a memory
3502 parse_tb (char **str
)
3507 if (skip_past_char (&p
, '[') == FAIL
)
3510 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
3512 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
3515 inst
.operands
[0].reg
= reg
;
3517 if (skip_past_comma (&p
) == FAIL
)
3520 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
3522 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
3525 inst
.operands
[0].imm
= reg
;
3527 if (skip_past_comma (&p
) == SUCCESS
)
3529 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
3531 if (inst
.reloc
.exp
.X_add_number
!= 1)
3533 inst
.error
= _("invalid shift");
3536 inst
.operands
[0].shifted
= 1;
3539 if (skip_past_char (&p
, ']') == FAIL
)
3541 inst
.error
= _("']' expected");
3548 /* Matcher codes for parse_operands. */
3549 enum operand_parse_code
3551 OP_stop
, /* end of line */
3553 OP_RR
, /* ARM register */
3554 OP_RRnpc
, /* ARM register, not r15 */
3555 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
3556 OP_RRw
, /* ARM register, not r15, optional trailing ! */
3557 OP_RCP
, /* Coprocessor number */
3558 OP_RCN
, /* Coprocessor register */
3559 OP_RF
, /* FPA register */
3560 OP_RVS
, /* VFP single precision register */
3561 OP_RVD
, /* VFP double precision register */
3562 OP_RVC
, /* VFP control register */
3563 OP_RMF
, /* Maverick F register */
3564 OP_RMD
, /* Maverick D register */
3565 OP_RMFX
, /* Maverick FX register */
3566 OP_RMDX
, /* Maverick DX register */
3567 OP_RMAX
, /* Maverick AX register */
3568 OP_RMDS
, /* Maverick DSPSC register */
3569 OP_RIWR
, /* iWMMXt wR register */
3570 OP_RIWC
, /* iWMMXt wC register */
3571 OP_RIWG
, /* iWMMXt wCG register */
3572 OP_RXA
, /* XScale accumulator register */
3574 OP_REGLST
, /* ARM register list */
3575 OP_VRSLST
, /* VFP single-precision register list */
3576 OP_VRDLST
, /* VFP double-precision register list */
3578 OP_I7
, /* immediate value 0 .. 7 */
3579 OP_I15
, /* 0 .. 15 */
3580 OP_I16
, /* 1 .. 16 */
3581 OP_I31
, /* 0 .. 31 */
3582 OP_I31w
, /* 0 .. 31, optional trailing ! */
3583 OP_I32
, /* 1 .. 32 */
3584 OP_I63s
, /* -64 .. 63 */
3585 OP_I255
, /* 0 .. 255 */
3586 OP_Iffff
, /* 0 .. 65535 */
3588 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
3589 OP_I7b
, /* 0 .. 7 */
3590 OP_I15b
, /* 0 .. 15 */
3591 OP_I31b
, /* 0 .. 31 */
3593 OP_SH
, /* shifter operand */
3594 OP_ADDR
, /* Memory address expression (any mode) */
3595 OP_EXP
, /* arbitrary expression */
3596 OP_EXPi
, /* same, with optional immediate prefix */
3597 OP_EXPr
, /* same, with optional relocation suffix */
3599 OP_CPSF
, /* CPS flags */
3600 OP_ENDI
, /* Endianness specifier */
3601 OP_PSR
, /* CPSR/SPSR mask for msr */
3602 OP_COND
, /* conditional code */
3603 OP_TB
, /* Table branch. */
3605 OP_RRnpc_I0
, /* ARM register or literal 0 */
3606 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
3607 OP_RR_EXi
, /* ARM register or expression with imm prefix */
3608 OP_RF_IF
, /* FPA register or immediate */
3609 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
3611 /* Optional operands. */
3612 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
3613 OP_oI31b
, /* 0 .. 31 */
3614 OP_oIffffb
, /* 0 .. 65535 */
3615 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
3617 OP_oRR
, /* ARM register */
3618 OP_oRRnpc
, /* ARM register, not the PC */
3619 OP_oSHll
, /* LSL immediate */
3620 OP_oSHar
, /* ASR immediate */
3621 OP_oSHllar
, /* LSL or ASR immediate */
3622 OP_oROR
, /* ROR 0/8/16/24 */
3624 OP_FIRST_OPTIONAL
= OP_oI7b
3627 /* Generic instruction operand parser. This does no encoding and no
3628 semantic validation; it merely squirrels values away in the inst
3629 structure. Returns SUCCESS or FAIL depending on whether the
3630 specified grammar matched. */
3632 parse_operands (char *str
, const unsigned char *pattern
)
3634 unsigned const char *upat
= pattern
;
3635 char *backtrack_pos
= 0;
3636 const char *backtrack_error
= 0;
3637 int i
, val
, backtrack_index
= 0;
3639 #define po_char_or_fail(chr) do { \
3640 if (skip_past_char (&str, chr) == FAIL) \
3644 #define po_reg_or_fail(regtype) do { \
3645 val = arm_reg_parse (&str, regtype); \
3648 inst.error = _(reg_expected_msgs[regtype]); \
3651 inst.operands[i].reg = val; \
3652 inst.operands[i].isreg = 1; \
3655 #define po_reg_or_goto(regtype, label) do { \
3656 val = arm_reg_parse (&str, regtype); \
3660 inst.operands[i].reg = val; \
3661 inst.operands[i].isreg = 1; \
3664 #define po_imm_or_fail(min, max, popt) do { \
3665 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
3667 inst.operands[i].imm = val; \
3670 #define po_misc_or_fail(expr) do { \
3675 skip_whitespace (str
);
3677 for (i
= 0; upat
[i
] != OP_stop
; i
++)
3679 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
3681 /* Remember where we are in case we need to backtrack. */
3682 assert (!backtrack_pos
);
3683 backtrack_pos
= str
;
3684 backtrack_error
= inst
.error
;
3685 backtrack_index
= i
;
3689 po_char_or_fail (',');
3697 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
3698 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
3699 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
3700 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
3701 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
3702 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
3703 case OP_RVC
: po_reg_or_fail (REG_TYPE_VFC
); break;
3704 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
3705 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
3706 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
3707 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
3708 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
3709 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
3710 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
3711 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
3712 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
3713 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
3716 po_char_or_fail ('[');
3717 po_reg_or_fail (REG_TYPE_RN
);
3718 po_char_or_fail (']');
3722 po_reg_or_fail (REG_TYPE_RN
);
3723 if (skip_past_char (&str
, '!') == SUCCESS
)
3724 inst
.operands
[i
].writeback
= 1;
3728 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
3729 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
3730 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
3731 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
3732 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
3733 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
3734 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
3735 case OP_Iffff
: po_imm_or_fail ( 0, 0xffff, FALSE
); break;
3737 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
3739 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
3740 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
3742 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
3743 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
3745 /* Immediate variants */
3747 po_char_or_fail ('{');
3748 po_imm_or_fail (0, 255, TRUE
);
3749 po_char_or_fail ('}');
3753 /* The expression parser chokes on a trailing !, so we have
3754 to find it first and zap it. */
3757 while (*s
&& *s
!= ',')
3762 inst
.operands
[i
].writeback
= 1;
3764 po_imm_or_fail (0, 31, TRUE
);
3772 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
3777 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
3782 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
3784 if (inst
.reloc
.exp
.X_op
== O_symbol
)
3786 val
= parse_reloc (&str
);
3789 inst
.error
= _("unrecognized relocation suffix");
3792 else if (val
!= BFD_RELOC_UNUSED
)
3794 inst
.operands
[i
].imm
= val
;
3795 inst
.operands
[i
].hasreloc
= 1;
3800 /* Register or expression */
3801 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
3802 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
3804 /* Register or immediate */
3805 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
3806 I0
: po_imm_or_fail (0, 0, FALSE
); break;
3808 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
3810 if (!is_immediate_prefix (*str
))
3813 val
= parse_fpa_immediate (&str
);
3816 /* FPA immediates are encoded as registers 8-15.
3817 parse_fpa_immediate has already applied the offset. */
3818 inst
.operands
[i
].reg
= val
;
3819 inst
.operands
[i
].isreg
= 1;
3822 /* Two kinds of register */
3825 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
3826 if (rege
->type
!= REG_TYPE_MMXWR
3827 && rege
->type
!= REG_TYPE_MMXWC
3828 && rege
->type
!= REG_TYPE_MMXWCG
)
3830 inst
.error
= _("iWMMXt data or control register expected");
3833 inst
.operands
[i
].reg
= rege
->number
;
3834 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
3839 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
3840 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
3841 case OP_oROR
: val
= parse_ror (&str
); break;
3842 case OP_PSR
: val
= parse_psr (&str
); break;
3843 case OP_COND
: val
= parse_cond (&str
); break;
3846 po_misc_or_fail (parse_tb (&str
));
3849 /* Register lists */
3851 val
= parse_reg_list (&str
);
3854 inst
.operands
[1].writeback
= 1;
3860 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, 0);
3864 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, 1);
3867 /* Addressing modes */
3869 po_misc_or_fail (parse_address (&str
, i
));
3873 po_misc_or_fail (parse_shifter_operand (&str
, i
));
3877 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
3881 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
3885 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
3889 as_fatal ("unhandled operand code %d", upat
[i
]);
3892 /* Various value-based sanity checks and shared operations. We
3893 do not signal immediate failures for the register constraints;
3894 this allows a syntax error to take precedence. */
3902 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
3903 inst
.error
= BAD_PC
;
3916 inst
.operands
[i
].imm
= val
;
3923 /* If we get here, this operand was successfully parsed. */
3924 inst
.operands
[i
].present
= 1;
3928 inst
.error
= BAD_ARGS
;
3934 /* Do not backtrack over a trailing optional argument that
3935 absorbed some text. We will only fail again, with the
3936 'garbage following instruction' error message, which is
3937 probably less helpful than the current one. */
3938 if (backtrack_index
== i
&& backtrack_pos
!= str
3939 && upat
[i
+1] == OP_stop
)
3942 /* Try again, skipping the optional argument at backtrack_pos. */
3943 str
= backtrack_pos
;
3944 inst
.error
= backtrack_error
;
3945 inst
.operands
[backtrack_index
].present
= 0;
3946 i
= backtrack_index
;
3950 /* Check that we have parsed all the arguments. */
3951 if (*str
!= '\0' && !inst
.error
)
3952 inst
.error
= _("garbage following instruction");
3954 return inst
.error
? FAIL
: SUCCESS
;
3957 #undef po_char_or_fail
3958 #undef po_reg_or_fail
3959 #undef po_reg_or_goto
3960 #undef po_imm_or_fail
3962 /* Shorthand macro for instruction encoding functions issuing errors. */
3963 #define constraint(expr, err) do { \
3971 /* Functions for operand encoding. ARM, then Thumb. */
3973 #define rotate_left(v, n) (v << n | v >> (32 - n))
3975 /* If VAL can be encoded in the immediate field of an ARM instruction,
3976 return the encoded form. Otherwise, return FAIL. */
3979 encode_arm_immediate (unsigned int val
)
3983 for (i
= 0; i
< 32; i
+= 2)
3984 if ((a
= rotate_left (val
, i
)) <= 0xff)
3985 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
3990 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
3991 return the encoded form. Otherwise, return FAIL. */
3993 encode_thumb32_immediate (unsigned int val
)
4000 for (i
= 1; i
<= 24; i
++)
4003 if ((val
& ~(0xff << i
)) == 0)
4004 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
4008 if (val
== ((a
<< 16) | a
))
4010 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
4014 if (val
== ((a
<< 16) | a
))
4015 return 0x200 | (a
>> 8);
4019 /* Encode a VFP SP register number into inst.instruction. */
4022 encode_arm_vfp_sp_reg (int reg
, enum vfp_sp_reg_pos pos
)
4027 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
4031 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
4035 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
4043 /* Encode a <shift> in an ARM-format instruction. The immediate,
4044 if any, is handled by md_apply_fix. */
4046 encode_arm_shift (int i
)
4048 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
4049 inst
.instruction
|= SHIFT_ROR
<< 5;
4052 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
4053 if (inst
.operands
[i
].immisreg
)
4055 inst
.instruction
|= SHIFT_BY_REG
;
4056 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
4059 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
4064 encode_arm_shifter_operand (int i
)
4066 if (inst
.operands
[i
].isreg
)
4068 inst
.instruction
|= inst
.operands
[i
].reg
;
4069 encode_arm_shift (i
);
4072 inst
.instruction
|= INST_IMMEDIATE
;
4075 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
4077 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
4079 assert (inst
.operands
[i
].isreg
);
4080 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
4082 if (inst
.operands
[i
].preind
)
4086 inst
.error
= _("instruction does not accept preindexed addressing");
4089 inst
.instruction
|= PRE_INDEX
;
4090 if (inst
.operands
[i
].writeback
)
4091 inst
.instruction
|= WRITE_BACK
;
4094 else if (inst
.operands
[i
].postind
)
4096 assert (inst
.operands
[i
].writeback
);
4098 inst
.instruction
|= WRITE_BACK
;
4100 else /* unindexed - only for coprocessor */
4102 inst
.error
= _("instruction does not accept unindexed addressing");
4106 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
4107 && (((inst
.instruction
& 0x000f0000) >> 16)
4108 == ((inst
.instruction
& 0x0000f000) >> 12)))
4109 as_warn ((inst
.instruction
& LOAD_BIT
)
4110 ? _("destination register same as write-back base")
4111 : _("source register same as write-back base"));
4114 /* inst.operands[i] was set up by parse_address. Encode it into an
4115 ARM-format mode 2 load or store instruction. If is_t is true,
4116 reject forms that cannot be used with a T instruction (i.e. not
4119 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
4121 encode_arm_addr_mode_common (i
, is_t
);
4123 if (inst
.operands
[i
].immisreg
)
4125 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
4126 inst
.instruction
|= inst
.operands
[i
].imm
;
4127 if (!inst
.operands
[i
].negative
)
4128 inst
.instruction
|= INDEX_UP
;
4129 if (inst
.operands
[i
].shifted
)
4131 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
4132 inst
.instruction
|= SHIFT_ROR
<< 5;
4135 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
4136 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
4140 else /* immediate offset in inst.reloc */
4142 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4143 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
4147 /* inst.operands[i] was set up by parse_address. Encode it into an
4148 ARM-format mode 3 load or store instruction. Reject forms that
4149 cannot be used with such instructions. If is_t is true, reject
4150 forms that cannot be used with a T instruction (i.e. not
4153 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
4155 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
4157 inst
.error
= _("instruction does not accept scaled register index");
4161 encode_arm_addr_mode_common (i
, is_t
);
4163 if (inst
.operands
[i
].immisreg
)
4165 inst
.instruction
|= inst
.operands
[i
].imm
;
4166 if (!inst
.operands
[i
].negative
)
4167 inst
.instruction
|= INDEX_UP
;
4169 else /* immediate offset in inst.reloc */
4171 inst
.instruction
|= HWOFFSET_IMM
;
4172 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4173 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
4177 /* inst.operands[i] was set up by parse_address. Encode it into an
4178 ARM-format instruction. Reject all forms which cannot be encoded
4179 into a coprocessor load/store instruction. If wb_ok is false,
4180 reject use of writeback; if unind_ok is false, reject use of
4181 unindexed addressing. If reloc_override is not 0, use it instead
4182 of BFD_ARM_CP_OFF_IMM. */
4185 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
4187 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
4189 assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
4191 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
4193 assert (!inst
.operands
[i
].writeback
);
4196 inst
.error
= _("instruction does not support unindexed addressing");
4199 inst
.instruction
|= inst
.operands
[i
].imm
;
4200 inst
.instruction
|= INDEX_UP
;
4204 if (inst
.operands
[i
].preind
)
4205 inst
.instruction
|= PRE_INDEX
;
4207 if (inst
.operands
[i
].writeback
)
4209 if (inst
.operands
[i
].reg
== REG_PC
)
4211 inst
.error
= _("pc may not be used with write-back");
4216 inst
.error
= _("instruction does not support writeback");
4219 inst
.instruction
|= WRITE_BACK
;
4223 inst
.reloc
.type
= reloc_override
;
4225 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
4229 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
4230 Determine whether it can be performed with a move instruction; if
4231 it can, convert inst.instruction to that move instruction and
4232 return 1; if it can't, convert inst.instruction to a literal-pool
4233 load and return 0. If this is not a valid thing to do in the
4234 current context, set inst.error and return 1.
4236 inst.operands[i] describes the destination register. */
4239 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
4241 if ((inst
.instruction
& (thumb_p
? THUMB_LOAD_BIT
: LOAD_BIT
)) == 0)
4243 inst
.error
= _("invalid pseudo operation");
4246 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
4248 inst
.error
= _("constant expression expected");
4251 if (inst
.reloc
.exp
.X_op
== O_constant
)
4255 if ((inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
4257 /* This can be done with a mov(1) instruction. */
4258 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
4259 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
4265 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
4268 /* This can be done with a mov instruction. */
4269 inst
.instruction
&= LITERAL_MASK
;
4270 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
4271 inst
.instruction
|= value
& 0xfff;
4275 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
4278 /* This can be done with a mvn instruction. */
4279 inst
.instruction
&= LITERAL_MASK
;
4280 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
4281 inst
.instruction
|= value
& 0xfff;
4287 if (add_to_lit_pool () == FAIL
)
4289 inst
.error
= _("literal pool insertion failed");
4292 inst
.operands
[1].reg
= REG_PC
;
4293 inst
.operands
[1].isreg
= 1;
4294 inst
.operands
[1].preind
= 1;
4295 inst
.reloc
.pc_rel
= 1;
4296 inst
.reloc
.type
= (thumb_p
4297 ? BFD_RELOC_ARM_THUMB_OFFSET
4299 ? BFD_RELOC_ARM_HWLITERAL
4300 : BFD_RELOC_ARM_LITERAL
));
4304 /* Functions for instruction encoding, sorted by subarchitecture.
4305 First some generics; their names are taken from the conventional
4306 bit positions for register arguments in ARM format instructions. */
4316 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4322 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4323 inst
.instruction
|= inst
.operands
[1].reg
;
4329 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4330 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
4336 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
4337 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
4343 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4344 inst
.instruction
|= inst
.operands
[1].reg
;
4345 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
4351 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4352 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
4353 inst
.instruction
|= inst
.operands
[2].reg
;
4359 inst
.instruction
|= inst
.operands
[0].reg
;
4360 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
4361 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
4367 inst
.instruction
|= inst
.operands
[0].imm
;
4373 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4374 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
4377 /* ARM instructions, in alphabetical order by function name (except
4378 that wrapper functions appear immediately after the function they
4381 /* This is a pseudo-op of the form "adr rd, label" to be converted
4382 into a relative address of the form "add rd, pc, #label-.-8". */
4387 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
4389 /* Frag hacking will turn this into a sub instruction if the offset turns
4390 out to be negative. */
4391 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4392 inst
.reloc
.pc_rel
= 1;
4393 inst
.reloc
.exp
.X_add_number
-= 8;
4396 /* This is a pseudo-op of the form "adrl rd, label" to be converted
4397 into a relative address of the form:
4398 add rd, pc, #low(label-.-8)"
4399 add rd, rd, #high(label-.-8)" */
4404 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
4406 /* Frag hacking will turn this into a sub instruction if the offset turns
4407 out to be negative. */
4408 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
4409 inst
.reloc
.pc_rel
= 1;
4410 inst
.size
= INSN_SIZE
* 2;
4411 inst
.reloc
.exp
.X_add_number
-= 8;
4417 if (!inst
.operands
[1].present
)
4418 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
4419 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4420 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
4421 encode_arm_shifter_operand (2);
4427 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
4428 constraint (msb
> 32, _("bit-field extends past end of register"));
4429 /* The instruction encoding stores the LSB and MSB,
4430 not the LSB and width. */
4431 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4432 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
4433 inst
.instruction
|= (msb
- 1) << 16;
4441 /* #0 in second position is alternative syntax for bfc, which is
4442 the same instruction but with REG_PC in the Rm field. */
4443 if (!inst
.operands
[1].isreg
)
4444 inst
.operands
[1].reg
= REG_PC
;
4446 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
4447 constraint (msb
> 32, _("bit-field extends past end of register"));
4448 /* The instruction encoding stores the LSB and MSB,
4449 not the LSB and width. */
4450 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4451 inst
.instruction
|= inst
.operands
[1].reg
;
4452 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
4453 inst
.instruction
|= (msb
- 1) << 16;
4459 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
4460 _("bit-field extends past end of register"));
4461 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4462 inst
.instruction
|= inst
.operands
[1].reg
;
4463 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
4464 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
4467 /* ARM V5 breakpoint instruction (argument parse)
4468 BKPT <16 bit unsigned immediate>
4469 Instruction is not conditional.
4470 The bit pattern given in insns[] has the COND_ALWAYS condition,
4471 and it is an error if the caller tried to override that. */
4476 /* Top 12 of 16 bits to bits 19:8. */
4477 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
4479 /* Bottom 4 of 16 bits to bits 3:0. */
4480 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
4484 encode_branch (int default_reloc
)
4486 if (inst
.operands
[0].hasreloc
)
4488 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
4489 _("the only suffix valid here is '(plt)'"));
4490 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
4494 inst
.reloc
.type
= default_reloc
;
4496 inst
.reloc
.pc_rel
= 1;
4502 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
4505 /* ARM V5 branch-link-exchange instruction (argument parse)
4506 BLX <target_addr> ie BLX(1)
4507 BLX{<condition>} <Rm> ie BLX(2)
4508 Unfortunately, there are two different opcodes for this mnemonic.
4509 So, the insns[].value is not used, and the code here zaps values
4510 into inst.instruction.
4511 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
4516 if (inst
.operands
[0].isreg
)
4518 /* Arg is a register; the opcode provided by insns[] is correct.
4519 It is not illegal to do "blx pc", just useless. */
4520 if (inst
.operands
[0].reg
== REG_PC
)
4521 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
4523 inst
.instruction
|= inst
.operands
[0].reg
;
4527 /* Arg is an address; this instruction cannot be executed
4528 conditionally, and the opcode must be adjusted. */
4529 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
4530 inst
.instruction
= 0xfa000000;
4531 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
4538 if (inst
.operands
[0].reg
== REG_PC
)
4539 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
4541 inst
.instruction
|= inst
.operands
[0].reg
;
4545 /* ARM v5TEJ. Jump to Jazelle code. */
4550 if (inst
.operands
[0].reg
== REG_PC
)
4551 as_tsktsk (_("use of r15 in bxj is not really useful"));
4553 inst
.instruction
|= inst
.operands
[0].reg
;
4556 /* Co-processor data operation:
4557 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
4558 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
4562 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
4563 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
4564 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
4565 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
4566 inst
.instruction
|= inst
.operands
[4].reg
;
4567 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
4573 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
4574 encode_arm_shifter_operand (1);
4577 /* Transfer between coprocessor and ARM registers.
4578 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
4583 No special properties. */
4588 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
4589 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
4590 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
4591 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
4592 inst
.instruction
|= inst
.operands
[4].reg
;
4593 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
4596 /* Transfer between coprocessor register and pair of ARM registers.
4597 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
4602 Two XScale instructions are special cases of these:
4604 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
4605 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
4607 Result unpredicatable if Rd or Rn is R15. */
4612 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
4613 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
4614 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
4615 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
4616 inst
.instruction
|= inst
.operands
[4].reg
;
4622 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
4623 inst
.instruction
|= inst
.operands
[1].imm
;
4629 /* There is no IT instruction in ARM mode. We
4630 process it but do not generate code for it. */
4637 int base_reg
= inst
.operands
[0].reg
;
4638 int range
= inst
.operands
[1].imm
;
4640 inst
.instruction
|= base_reg
<< 16;
4641 inst
.instruction
|= range
;
4643 if (inst
.operands
[1].writeback
)
4644 inst
.instruction
|= LDM_TYPE_2_OR_3
;
4646 if (inst
.operands
[0].writeback
)
4648 inst
.instruction
|= WRITE_BACK
;
4649 /* Check for unpredictable uses of writeback. */
4650 if (inst
.instruction
& LOAD_BIT
)
4652 /* Not allowed in LDM type 2. */
4653 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
4654 && ((range
& (1 << REG_PC
)) == 0))
4655 as_warn (_("writeback of base register is UNPREDICTABLE"));
4656 /* Only allowed if base reg not in list for other types. */
4657 else if (range
& (1 << base_reg
))
4658 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
4662 /* Not allowed for type 2. */
4663 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
4664 as_warn (_("writeback of base register is UNPREDICTABLE"));
4665 /* Only allowed if base reg not in list, or first in list. */
4666 else if ((range
& (1 << base_reg
))
4667 && (range
& ((1 << base_reg
) - 1)))
4668 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
4673 /* ARMv5TE load-consecutive (argument parse)
4682 constraint (inst
.operands
[0].reg
% 2 != 0,
4683 _("first destination register must be even"));
4684 constraint (inst
.operands
[1].present
4685 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
4686 _("can only load two consecutive registers"));
4687 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
4688 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
4690 if (!inst
.operands
[1].present
)
4691 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
4693 if (inst
.instruction
& LOAD_BIT
)
4695 /* encode_arm_addr_mode_3 will diagnose overlap between the base
4696 register and the first register written; we have to diagnose
4697 overlap between the base and the second register written here. */
4699 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
4700 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
4701 as_warn (_("base register written back, and overlaps "
4702 "second destination register"));
4704 /* For an index-register load, the index register must not overlap the
4705 destination (even if not write-back). */
4706 else if (inst
.operands
[2].immisreg
4707 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
4708 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
4709 as_warn (_("index register overlaps destination register"));
4712 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4713 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
4719 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
4720 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
4721 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
4722 || inst
.operands
[1].negative
,
4723 _("instruction does not accept this addressing mode"));
4725 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
4727 constraint (inst
.reloc
.exp
.X_op
!= O_constant
4728 || inst
.reloc
.exp
.X_add_number
!= 0,
4729 _("offset must be zero in ARM encoding"));
4731 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4732 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
4733 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
4739 constraint (inst
.operands
[0].reg
% 2 != 0,
4740 _("even register required"));
4741 constraint (inst
.operands
[1].present
4742 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
4743 _("can only load two consecutive registers"));
4744 /* If op 1 were present and equal to PC, this function wouldn't
4745 have been called in the first place. */
4746 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
4748 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4749 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
4755 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4756 if (!inst
.operands
[1].isreg
)
4757 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
4759 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
4765 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
4767 if (inst
.operands
[1].preind
)
4769 constraint (inst
.reloc
.exp
.X_op
!= O_constant
||
4770 inst
.reloc
.exp
.X_add_number
!= 0,
4771 _("this instruction requires a post-indexed address"));
4773 inst
.operands
[1].preind
= 0;
4774 inst
.operands
[1].postind
= 1;
4775 inst
.operands
[1].writeback
= 1;
4777 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4778 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
4781 /* Halfword and signed-byte load/store operations. */
4786 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4787 if (!inst
.operands
[1].isreg
)
4788 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
4790 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
4796 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
4798 if (inst
.operands
[1].preind
)
4800 constraint (inst
.reloc
.exp
.X_op
!= O_constant
||
4801 inst
.reloc
.exp
.X_add_number
!= 0,
4802 _("this instruction requires a post-indexed address"));
4804 inst
.operands
[1].preind
= 0;
4805 inst
.operands
[1].postind
= 1;
4806 inst
.operands
[1].writeback
= 1;
4808 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4809 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
4812 /* Co-processor register load/store.
4813 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
4817 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
4818 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
4819 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
4825 /* This restriction does not apply to mls (nor to mla in v6, but
4826 that's hard to detect at present). */
4827 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
4828 && !(inst
.instruction
& 0x00400000))
4829 as_tsktsk (_("rd and rm should be different in mla"));
4831 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
4832 inst
.instruction
|= inst
.operands
[1].reg
;
4833 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
4834 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
4841 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4842 encode_arm_shifter_operand (1);
4845 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
4849 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4850 /* The value is in two pieces: 0:11, 16:19. */
4851 inst
.instruction
|= (inst
.operands
[1].imm
& 0x00000fff);
4852 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0000f000) << 4;
4858 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
4859 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
4861 _("'CPSR' or 'SPSR' expected"));
4862 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4863 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
4866 /* Two possible forms:
4867 "{C|S}PSR_<field>, Rm",
4868 "{C|S}PSR_f, #expression". */
4873 inst
.instruction
|= inst
.operands
[0].imm
;
4874 if (inst
.operands
[1].isreg
)
4875 inst
.instruction
|= inst
.operands
[1].reg
;
4878 inst
.instruction
|= INST_IMMEDIATE
;
4879 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4880 inst
.reloc
.pc_rel
= 0;
4887 if (!inst
.operands
[2].present
)
4888 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
4889 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
4890 inst
.instruction
|= inst
.operands
[1].reg
;
4891 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
4893 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
4894 as_tsktsk (_("rd and rm should be different in mul"));
4897 /* Long Multiply Parser
4898 UMULL RdLo, RdHi, Rm, Rs
4899 SMULL RdLo, RdHi, Rm, Rs
4900 UMLAL RdLo, RdHi, Rm, Rs
4901 SMLAL RdLo, RdHi, Rm, Rs. */
4906 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4907 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
4908 inst
.instruction
|= inst
.operands
[2].reg
;
4909 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
4911 /* rdhi, rdlo and rm must all be different. */
4912 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
4913 || inst
.operands
[0].reg
== inst
.operands
[2].reg
4914 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
4915 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
4921 if (inst
.operands
[0].present
)
4923 /* Architectural NOP hints are CPSR sets with no bits selected. */
4924 inst
.instruction
&= 0xf0000000;
4925 inst
.instruction
|= 0x0320f000 + inst
.operands
[0].imm
;
4929 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
4930 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
4931 Condition defaults to COND_ALWAYS.
4932 Error if Rd, Rn or Rm are R15. */
4937 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4938 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
4939 inst
.instruction
|= inst
.operands
[2].reg
;
4940 if (inst
.operands
[3].present
)
4941 encode_arm_shift (3);
4944 /* ARM V6 PKHTB (Argument Parse). */
4949 if (!inst
.operands
[3].present
)
4951 /* If the shift specifier is omitted, turn the instruction
4952 into pkhbt rd, rm, rn. */
4953 inst
.instruction
&= 0xfff00010;
4954 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4955 inst
.instruction
|= inst
.operands
[1].reg
;
4956 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
4960 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4961 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
4962 inst
.instruction
|= inst
.operands
[2].reg
;
4963 encode_arm_shift (3);
4967 /* ARMv5TE: Preload-Cache
4971 Syntactically, like LDR with B=1, W=0, L=1. */
4976 constraint (!inst
.operands
[0].isreg
,
4977 _("'[' expected after PLD mnemonic"));
4978 constraint (inst
.operands
[0].postind
,
4979 _("post-indexed expression used in preload instruction"));
4980 constraint (inst
.operands
[0].writeback
,
4981 _("writeback used in preload instruction"));
4982 constraint (!inst
.operands
[0].preind
,
4983 _("unindexed addressing used in preload instruction"));
4984 inst
.instruction
|= inst
.operands
[0].reg
;
4985 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
4991 inst
.operands
[1] = inst
.operands
[0];
4992 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
4993 inst
.operands
[0].isreg
= 1;
4994 inst
.operands
[0].writeback
= 1;
4995 inst
.operands
[0].reg
= REG_SP
;
4999 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
5000 word at the specified address and the following word
5002 Unconditionally executed.
5003 Error if Rn is R15. */
5008 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5009 if (inst
.operands
[0].writeback
)
5010 inst
.instruction
|= WRITE_BACK
;
5013 /* ARM V6 ssat (argument parse). */
5018 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5019 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
5020 inst
.instruction
|= inst
.operands
[2].reg
;
5022 if (inst
.operands
[3].present
)
5023 encode_arm_shift (3);
5026 /* ARM V6 usat (argument parse). */
5031 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5032 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
5033 inst
.instruction
|= inst
.operands
[2].reg
;
5035 if (inst
.operands
[3].present
)
5036 encode_arm_shift (3);
5039 /* ARM V6 ssat16 (argument parse). */
5044 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5045 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
5046 inst
.instruction
|= inst
.operands
[2].reg
;
5052 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5053 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
5054 inst
.instruction
|= inst
.operands
[2].reg
;
5057 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
5058 preserving the other bits.
5060 setend <endian_specifier>, where <endian_specifier> is either
5066 if (inst
.operands
[0].imm
)
5067 inst
.instruction
|= 0x200;
5073 unsigned int Rm
= (inst
.operands
[1].present
5074 ? inst
.operands
[1].reg
5075 : inst
.operands
[0].reg
);
5077 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5078 inst
.instruction
|= Rm
;
5079 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
5081 constraint (inst
.operands
[0].reg
!= Rm
,
5082 _("source1 and dest must be same register"));
5083 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
5084 inst
.instruction
|= SHIFT_BY_REG
;
5087 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
5093 inst
.reloc
.type
= BFD_RELOC_ARM_SMI
;
5094 inst
.reloc
.pc_rel
= 0;
5100 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
5101 inst
.reloc
.pc_rel
= 0;
5104 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
5105 SMLAxy{cond} Rd,Rm,Rs,Rn
5106 SMLAWy{cond} Rd,Rm,Rs,Rn
5107 Error if any register is R15. */
5112 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5113 inst
.instruction
|= inst
.operands
[1].reg
;
5114 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
5115 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
5118 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
5119 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
5120 Error if any register is R15.
5121 Warning if Rdlo == Rdhi. */
5126 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5127 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5128 inst
.instruction
|= inst
.operands
[2].reg
;
5129 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
5131 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
5132 as_tsktsk (_("rdhi and rdlo must be different"));
5135 /* ARM V5E (El Segundo) signed-multiply (argument parse)
5136 SMULxy{cond} Rd,Rm,Rs
5137 Error if any register is R15. */
5142 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5143 inst
.instruction
|= inst
.operands
[1].reg
;
5144 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
5147 /* ARM V6 srs (argument parse). */
5152 inst
.instruction
|= inst
.operands
[0].imm
;
5153 if (inst
.operands
[0].writeback
)
5154 inst
.instruction
|= WRITE_BACK
;
5157 /* ARM V6 strex (argument parse). */
5162 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
5163 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
5164 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
5165 || inst
.operands
[2].negative
,
5166 _("instruction does not accept this addressing mode"));
5168 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
5170 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
5171 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
5173 constraint (inst
.reloc
.exp
.X_op
!= O_constant
5174 || inst
.reloc
.exp
.X_add_number
!= 0,
5175 _("offset must be zero in ARM encoding"));
5177 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5178 inst
.instruction
|= inst
.operands
[1].reg
;
5179 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
5180 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5186 constraint (inst
.operands
[1].reg
% 2 != 0,
5187 _("even register required"));
5188 constraint (inst
.operands
[2].present
5189 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
5190 _("can only store two consecutive registers"));
5191 /* If op 2 were present and equal to PC, this function wouldn't
5192 have been called in the first place. */
5193 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
5195 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
5196 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
5197 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
5200 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5201 inst
.instruction
|= inst
.operands
[1].reg
;
5202 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
5205 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
5206 extends it to 32-bits, and adds the result to a value in another
5207 register. You can specify a rotation by 0, 8, 16, or 24 bits
5208 before extracting the 16-bit value.
5209 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
5210 Condition defaults to COND_ALWAYS.
5211 Error if any register uses R15. */
5216 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5217 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5218 inst
.instruction
|= inst
.operands
[2].reg
;
5219 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
5224 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
5225 Condition defaults to COND_ALWAYS.
5226 Error if any register uses R15. */
5231 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5232 inst
.instruction
|= inst
.operands
[1].reg
;
5233 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
5236 /* VFP instructions. In a logical order: SP variant first, monad
5237 before dyad, arithmetic then move then load/store. */
5240 do_vfp_sp_monadic (void)
5242 encode_arm_vfp_sp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
5243 encode_arm_vfp_sp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
5247 do_vfp_sp_dyadic (void)
5249 encode_arm_vfp_sp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
5250 encode_arm_vfp_sp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
5251 encode_arm_vfp_sp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
5255 do_vfp_sp_compare_z (void)
5257 encode_arm_vfp_sp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
5261 do_vfp_dp_sp_cvt (void)
5263 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5264 encode_arm_vfp_sp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
5268 do_vfp_sp_dp_cvt (void)
5270 encode_arm_vfp_sp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
5271 inst
.instruction
|= inst
.operands
[1].reg
;
5275 do_vfp_reg_from_sp (void)
5277 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5278 encode_arm_vfp_sp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
5282 do_vfp_reg2_from_sp2 (void)
5284 constraint (inst
.operands
[2].imm
!= 2,
5285 _("only two consecutive VFP SP registers allowed here"));
5286 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5287 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5288 encode_arm_vfp_sp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
5292 do_vfp_sp_from_reg (void)
5294 encode_arm_vfp_sp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
5295 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5299 do_vfp_sp2_from_reg2 (void)
5301 constraint (inst
.operands
[0].imm
!= 2,
5302 _("only two consecutive VFP SP registers allowed here"));
5303 encode_arm_vfp_sp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
5304 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5305 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
5309 do_vfp_sp_ldst (void)
5311 encode_arm_vfp_sp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
5312 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
5316 do_vfp_dp_ldst (void)
5318 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5319 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
5324 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
5326 if (inst
.operands
[0].writeback
)
5327 inst
.instruction
|= WRITE_BACK
;
5329 constraint (ldstm_type
!= VFP_LDSTMIA
,
5330 _("this addressing mode requires base-register writeback"));
5331 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5332 encode_arm_vfp_sp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
5333 inst
.instruction
|= inst
.operands
[1].imm
;
5337 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
5341 if (inst
.operands
[0].writeback
)
5342 inst
.instruction
|= WRITE_BACK
;
5344 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
5345 _("this addressing mode requires base-register writeback"));
5347 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5348 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5350 count
= inst
.operands
[1].imm
<< 1;
5351 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
5354 inst
.instruction
|= count
;
5358 do_vfp_sp_ldstmia (void)
5360 vfp_sp_ldstm (VFP_LDSTMIA
);
5364 do_vfp_sp_ldstmdb (void)
5366 vfp_sp_ldstm (VFP_LDSTMDB
);
5370 do_vfp_dp_ldstmia (void)
5372 vfp_dp_ldstm (VFP_LDSTMIA
);
5376 do_vfp_dp_ldstmdb (void)
5378 vfp_dp_ldstm (VFP_LDSTMDB
);
5382 do_vfp_xp_ldstmia (void)
5384 vfp_dp_ldstm (VFP_LDSTMIAX
);
5388 do_vfp_xp_ldstmdb (void)
5390 vfp_dp_ldstm (VFP_LDSTMDBX
);
5393 /* FPA instructions. Also in a logical order. */
5398 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5399 inst
.instruction
|= inst
.operands
[1].reg
;
5403 do_fpa_ldmstm (void)
5405 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5406 switch (inst
.operands
[1].imm
)
5408 case 1: inst
.instruction
|= CP_T_X
; break;
5409 case 2: inst
.instruction
|= CP_T_Y
; break;
5410 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
5415 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
5417 /* The instruction specified "ea" or "fd", so we can only accept
5418 [Rn]{!}. The instruction does not really support stacking or
5419 unstacking, so we have to emulate these by setting appropriate
5420 bits and offsets. */
5421 constraint (inst
.reloc
.exp
.X_op
!= O_constant
5422 || inst
.reloc
.exp
.X_add_number
!= 0,
5423 _("this instruction does not support indexing"));
5425 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
5426 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
5428 if (!(inst
.instruction
& INDEX_UP
))
5429 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
5431 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
5433 inst
.operands
[2].preind
= 0;
5434 inst
.operands
[2].postind
= 1;
5438 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
5441 /* iWMMXt instructions: strictly in alphabetical order. */
5444 do_iwmmxt_tandorc (void)
5446 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
5450 do_iwmmxt_textrc (void)
5452 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5453 inst
.instruction
|= inst
.operands
[1].imm
;
5457 do_iwmmxt_textrm (void)
5459 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5460 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5461 inst
.instruction
|= inst
.operands
[2].imm
;
5465 do_iwmmxt_tinsr (void)
5467 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5468 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5469 inst
.instruction
|= inst
.operands
[2].imm
;
5473 do_iwmmxt_tmia (void)
5475 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
5476 inst
.instruction
|= inst
.operands
[1].reg
;
5477 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
5481 do_iwmmxt_waligni (void)
5483 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5484 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5485 inst
.instruction
|= inst
.operands
[2].reg
;
5486 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
5490 do_iwmmxt_wmov (void)
5492 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
5493 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5494 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5495 inst
.instruction
|= inst
.operands
[1].reg
;
5499 do_iwmmxt_wldstbh (void)
5501 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5502 inst
.reloc
.exp
.X_add_number
*= 4;
5503 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_CP_OFF_IMM_S2
);
5507 do_iwmmxt_wldstw (void)
5509 /* RIWR_RIWC clears .isreg for a control register. */
5510 if (!inst
.operands
[0].isreg
)
5512 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
5513 inst
.instruction
|= 0xf0000000;
5516 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5517 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
5521 do_iwmmxt_wldstd (void)
5523 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5524 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
5528 do_iwmmxt_wshufh (void)
5530 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5531 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5532 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
5533 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
5537 do_iwmmxt_wzero (void)
5539 /* WZERO reg is an alias for WANDN reg, reg, reg. */
5540 inst
.instruction
|= inst
.operands
[0].reg
;
5541 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5542 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5545 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
5546 operations first, then control, shift, and load/store. */
5548 /* Insns like "foo X,Y,Z". */
5551 do_mav_triple (void)
5553 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5554 inst
.instruction
|= inst
.operands
[1].reg
;
5555 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
5558 /* Insns like "foo W,X,Y,Z".
5559 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
5564 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
5565 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5566 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
5567 inst
.instruction
|= inst
.operands
[3].reg
;
5570 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
5574 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5577 /* Maverick shift immediate instructions.
5578 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
5579 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
5584 int imm
= inst
.operands
[2].imm
;
5586 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5587 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5589 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
5590 Bits 5-7 of the insn should have bits 4-6 of the immediate.
5591 Bit 4 should be 0. */
5592 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
5594 inst
.instruction
|= imm
;
5597 /* XScale instructions. Also sorted arithmetic before move. */
5599 /* Xscale multiply-accumulate (argument parse)
5602 MIAxycc acc0,Rm,Rs. */
5607 inst
.instruction
|= inst
.operands
[1].reg
;
5608 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
5611 /* Xscale move-accumulator-register (argument parse)
5613 MARcc acc0,RdLo,RdHi. */
5618 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5619 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
5622 /* Xscale move-register-accumulator (argument parse)
5624 MRAcc RdLo,RdHi,acc0. */
5629 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
5630 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5631 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5634 /* Encoding functions relevant only to Thumb. */
5636 /* inst.operands[i] is a shifted-register operand; encode
5637 it into inst.instruction in the format used by Thumb32. */
5640 encode_thumb32_shifted_operand (int i
)
5642 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
5643 unsigned int shift
= inst
.operands
[i
].shift_kind
;
5645 constraint (inst
.operands
[i
].immisreg
,
5646 _("shift by register not allowed in thumb mode"));
5647 inst
.instruction
|= inst
.operands
[i
].reg
;
5648 if (shift
== SHIFT_RRX
)
5649 inst
.instruction
|= SHIFT_ROR
<< 4;
5652 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
5653 _("expression too complex"));
5655 constraint (value
> 32
5656 || (value
== 32 && (shift
== SHIFT_LSL
5657 || shift
== SHIFT_ROR
)),
5658 _("shift expression is too large"));
5662 else if (value
== 32)
5665 inst
.instruction
|= shift
<< 4;
5666 inst
.instruction
|= (value
& 0x1c) << 10;
5667 inst
.instruction
|= (value
& 0x03) << 6;
5672 /* inst.operands[i] was set up by parse_address. Encode it into a
5673 Thumb32 format load or store instruction. Reject forms that cannot
5674 be used with such instructions. If is_t is true, reject forms that
5675 cannot be used with a T instruction; if is_d is true, reject forms
5676 that cannot be used with a D instruction. */
5679 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
5681 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
5683 constraint (!inst
.operands
[i
].isreg
,
5684 _("Thumb does not support the ldr =N pseudo-operation"));
5686 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
5687 if (inst
.operands
[i
].immisreg
)
5689 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
5690 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
5691 constraint (inst
.operands
[i
].negative
,
5692 _("Thumb does not support negative register indexing"));
5693 constraint (inst
.operands
[i
].postind
,
5694 _("Thumb does not support register post-indexing"));
5695 constraint (inst
.operands
[i
].writeback
,
5696 _("Thumb does not support register indexing with writeback"));
5697 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
5698 _("Thumb supports only LSL in shifted register indexing"));
5700 inst
.instruction
|= inst
.operands
[1].imm
;
5701 if (inst
.operands
[i
].shifted
)
5703 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
5704 _("expression too complex"));
5705 constraint (inst
.reloc
.exp
.X_add_number
< 0
5706 || inst
.reloc
.exp
.X_add_number
> 3,
5707 _("shift out of range"));
5708 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
5710 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5712 else if (inst
.operands
[i
].preind
)
5714 constraint (is_pc
&& inst
.operands
[i
].writeback
,
5715 _("cannot use writeback with PC-relative addressing"));
5716 constraint (is_t
&& inst
.operands
[1].writeback
,
5717 _("cannot use writeback with this instruction"));
5721 inst
.instruction
|= 0x01000000;
5722 if (inst
.operands
[i
].writeback
)
5723 inst
.instruction
|= 0x00200000;
5727 inst
.instruction
|= 0x00000c00;
5728 if (inst
.operands
[i
].writeback
)
5729 inst
.instruction
|= 0x00000100;
5731 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
5733 else if (inst
.operands
[i
].postind
)
5735 assert (inst
.operands
[i
].writeback
);
5736 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
5737 constraint (is_t
, _("cannot use post-indexing with this instruction"));
5740 inst
.instruction
|= 0x00200000;
5742 inst
.instruction
|= 0x00000900;
5743 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
5745 else /* unindexed - only for coprocessor */
5746 inst
.error
= _("instruction does not accept unindexed addressing");
5749 /* Table of Thumb instructions which exist in both 16- and 32-bit
5750 encodings (the latter only in post-V6T2 cores). The index is the
5751 value used in the insns table below. When there is more than one
5752 possible 16-bit encoding for the instruction, this table always
5753 holds variant (1). */
5754 #define T16_32_TAB \
5755 X(adc, 4140, eb400000), \
5756 X(adcs, 4140, eb500000), \
5757 X(add, 1c00, eb000000), \
5758 X(adds, 1c00, eb100000), \
5759 X(adr, 000f, f20f0000), \
5760 X(and, 4000, ea000000), \
5761 X(ands, 4000, ea100000), \
5762 X(asr, 1000, fa40f000), \
5763 X(asrs, 1000, fa50f000), \
5764 X(bic, 4380, ea200000), \
5765 X(bics, 4380, ea300000), \
5766 X(cmn, 42c0, eb100f00), \
5767 X(cmp, 2800, ebb00f00), \
5768 X(cpsie, b660, f3af8400), \
5769 X(cpsid, b670, f3af8600), \
5770 X(cpy, 4600, ea4f0000), \
5771 X(eor, 4040, ea800000), \
5772 X(eors, 4040, ea900000), \
5773 X(ldmia, c800, e8900000), \
5774 X(ldr, 6800, f8500000), \
5775 X(ldrb, 7800, f8100000), \
5776 X(ldrh, 8800, f8300000), \
5777 X(ldrsb, 5600, f9100000), \
5778 X(ldrsh, 5e00, f9300000), \
5779 X(lsl, 0000, fa00f000), \
5780 X(lsls, 0000, fa10f000), \
5781 X(lsr, 0800, fa20f000), \
5782 X(lsrs, 0800, fa30f000), \
5783 X(mov, 2000, ea4f0000), \
5784 X(movs, 2000, ea5f0000), \
5785 X(mul, 4340, fb00f000), \
5786 X(muls, 4340, ffffffff), /* no 32b muls */ \
5787 X(mvn, 43c0, ea6f0000), \
5788 X(mvns, 43c0, ea7f0000), \
5789 X(neg, 4240, f1c00000), /* rsb #0 */ \
5790 X(negs, 4240, f1d00000), /* rsbs #0 */ \
5791 X(orr, 4300, ea400000), \
5792 X(orrs, 4300, ea500000), \
5793 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
5794 X(push, b400, e92d0000), /* stmdb sp!,... */ \
5795 X(rev, ba00, fa90f080), \
5796 X(rev16, ba40, fa90f090), \
5797 X(revsh, bac0, fa90f0b0), \
5798 X(ror, 41c0, fa60f000), \
5799 X(rors, 41c0, fa70f000), \
5800 X(sbc, 4180, eb600000), \
5801 X(sbcs, 4180, eb700000), \
5802 X(stmia, c000, e8800000), \
5803 X(str, 6000, f8400000), \
5804 X(strb, 7000, f8000000), \
5805 X(strh, 8000, f8200000), \
5806 X(sub, 1e00, eba00000), \
5807 X(subs, 1e00, ebb00000), \
5808 X(sxtb, b240, fa4ff080), \
5809 X(sxth, b200, fa0ff080), \
5810 X(tst, 4200, ea100f00), \
5811 X(uxtb, b2c0, fa5ff080), \
5812 X(uxth, b280, fa1ff080), \
5813 X(nop, bf00, f3af8000), \
5814 X(yield, bf10, f3af8001), \
5815 X(wfe, bf20, f3af8002), \
5816 X(wfi, bf30, f3af8003), \
5817 X(sev, bf40, f3af9004), /* typo, 8004? */
5819 /* To catch errors in encoding functions, the codes are all offset by
5820 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
5821 as 16-bit instructions. */
5822 #define X(a,b,c) T_MNEM_##a
5823 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
5826 #define X(a,b,c) 0x##b
5827 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
5828 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
5831 #define X(a,b,c) 0x##c
5832 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
5833 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
5834 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
5838 /* Thumb instruction encoders, in alphabetical order. */
5842 do_t_add_sub_w (void)
5846 Rd
= inst
.operands
[0].reg
;
5847 Rn
= inst
.operands
[1].reg
;
5849 constraint (Rd
== 15, _("PC not allowed as destination"));
5850 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
5851 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
5854 /* Parse an add or subtract instruction. We get here with inst.instruction
5855 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
5862 Rd
= inst
.operands
[0].reg
;
5863 Rs
= (inst
.operands
[1].present
5864 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
5865 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
5869 if (!inst
.operands
[2].isreg
)
5871 /* ??? Convert large immediates to addw/subw. */
5872 /* ??? 16-bit adds with small immediates. */
5873 /* For an immediate, we always generate a 32-bit opcode;
5874 section relaxation will shrink it later if possible. */
5875 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
5876 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
5877 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
5878 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5879 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
5883 Rn
= inst
.operands
[2].reg
;
5884 /* See if we can do this with a 16-bit instruction. */
5885 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
5889 if (inst
.instruction
== T_MNEM_adds
5890 || inst
.instruction
== T_MNEM_subs
)
5891 narrow
= (current_it_mask
== 0);
5893 narrow
= (current_it_mask
!= 0);
5894 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
5899 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
5900 || inst
.instruction
== T_MNEM_add
)
5903 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
5907 if (inst
.instruction
== T_MNEM_add
)
5911 inst
.instruction
= T_OPCODE_ADD_HI
;
5912 inst
.instruction
|= (Rd
& 8) << 4;
5913 inst
.instruction
|= (Rd
& 7);
5914 inst
.instruction
|= Rn
<< 3;
5917 /* ... because addition is commutative! */
5920 inst
.instruction
= T_OPCODE_ADD_HI
;
5921 inst
.instruction
|= (Rd
& 8) << 4;
5922 inst
.instruction
|= (Rd
& 7);
5923 inst
.instruction
|= Rs
<< 3;
5928 /* If we get here, it can't be done in 16 bits. */
5929 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
5930 _("shift must be constant"));
5931 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
5932 inst
.instruction
|= Rd
<< 8;
5933 inst
.instruction
|= Rs
<< 16;
5934 encode_thumb32_shifted_operand (2);
5939 constraint (inst
.instruction
== T_MNEM_adds
5940 || inst
.instruction
== T_MNEM_subs
,
5943 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
5945 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
5946 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
5949 inst
.instruction
= (inst
.instruction
== T_MNEM_add
5951 inst
.instruction
|= (Rd
<< 4) | Rs
;
5952 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
5956 Rn
= inst
.operands
[2].reg
;
5957 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
5959 /* We now have Rd, Rs, and Rn set to registers. */
5960 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
5962 /* Can't do this for SUB. */
5963 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
5964 inst
.instruction
= T_OPCODE_ADD_HI
;
5965 inst
.instruction
|= (Rd
& 8) << 4;
5966 inst
.instruction
|= (Rd
& 7);
5968 inst
.instruction
|= Rn
<< 3;
5970 inst
.instruction
|= Rs
<< 3;
5972 constraint (1, _("dest must overlap one source register"));
5976 inst
.instruction
= (inst
.instruction
== T_MNEM_add
5977 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
5978 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
5986 if (unified_syntax
&& inst
.size_req
!= 2)
5988 /* Always generate a 32-bit opcode;
5989 section relaxation will shrink it later if possible. */
5990 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
5991 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
5992 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
5993 inst
.reloc
.pc_rel
= 1;
5997 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
5998 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
5999 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
6000 inst
.reloc
.pc_rel
= 1;
6002 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
6006 /* Arithmetic instructions for which there is just one 16-bit
6007 instruction encoding, and it allows only two low registers.
6008 For maximal compatibility with ARM syntax, we allow three register
6009 operands even when Thumb-32 instructions are not available, as long
6010 as the first two are identical. For instance, both "sbc r0,r1" and
6011 "sbc r0,r0,r1" are allowed. */
6017 Rd
= inst
.operands
[0].reg
;
6018 Rs
= (inst
.operands
[1].present
6019 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
6020 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
6021 Rn
= inst
.operands
[2].reg
;
6025 if (!inst
.operands
[2].isreg
)
6027 /* For an immediate, we always generate a 32-bit opcode;
6028 section relaxation will shrink it later if possible. */
6029 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6030 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
6031 inst
.instruction
|= Rd
<< 8;
6032 inst
.instruction
|= Rs
<< 16;
6033 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
6039 /* See if we can do this with a 16-bit instruction. */
6040 if (THUMB_SETS_FLAGS (inst
.instruction
))
6041 narrow
= current_it_mask
== 0;
6043 narrow
= current_it_mask
!= 0;
6045 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
6047 if (inst
.operands
[2].shifted
)
6049 if (inst
.size_req
== 4)
6055 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6056 inst
.instruction
|= Rd
;
6057 inst
.instruction
|= Rn
<< 3;
6061 /* If we get here, it can't be done in 16 bits. */
6062 constraint (inst
.operands
[2].shifted
6063 && inst
.operands
[2].immisreg
,
6064 _("shift must be constant"));
6065 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6066 inst
.instruction
|= Rd
<< 8;
6067 inst
.instruction
|= Rs
<< 16;
6068 encode_thumb32_shifted_operand (2);
6073 /* On its face this is a lie - the instruction does set the
6074 flags. However, the only supported mnemonic in this mode
6076 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
6078 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
6079 _("unshifted register required"));
6080 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
6081 constraint (Rd
!= Rs
,
6082 _("dest and source1 must be the same register"));
6084 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6085 inst
.instruction
|= Rd
;
6086 inst
.instruction
|= Rn
<< 3;
6090 /* Similarly, but for instructions where the arithmetic operation is
6091 commutative, so we can allow either of them to be different from
6092 the destination operand in a 16-bit instruction. For instance, all
6093 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
6100 Rd
= inst
.operands
[0].reg
;
6101 Rs
= (inst
.operands
[1].present
6102 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
6103 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
6104 Rn
= inst
.operands
[2].reg
;
6108 if (!inst
.operands
[2].isreg
)
6110 /* For an immediate, we always generate a 32-bit opcode;
6111 section relaxation will shrink it later if possible. */
6112 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6113 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
6114 inst
.instruction
|= Rd
<< 8;
6115 inst
.instruction
|= Rs
<< 16;
6116 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
6122 /* See if we can do this with a 16-bit instruction. */
6123 if (THUMB_SETS_FLAGS (inst
.instruction
))
6124 narrow
= current_it_mask
== 0;
6126 narrow
= current_it_mask
!= 0;
6128 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
6130 if (inst
.operands
[2].shifted
)
6132 if (inst
.size_req
== 4)
6139 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6140 inst
.instruction
|= Rd
;
6141 inst
.instruction
|= Rn
<< 3;
6146 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6147 inst
.instruction
|= Rd
;
6148 inst
.instruction
|= Rs
<< 3;
6153 /* If we get here, it can't be done in 16 bits. */
6154 constraint (inst
.operands
[2].shifted
6155 && inst
.operands
[2].immisreg
,
6156 _("shift must be constant"));
6157 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6158 inst
.instruction
|= Rd
<< 8;
6159 inst
.instruction
|= Rs
<< 16;
6160 encode_thumb32_shifted_operand (2);
6165 /* On its face this is a lie - the instruction does set the
6166 flags. However, the only supported mnemonic in this mode
6168 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
6170 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
6171 _("unshifted register required"));
6172 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
6174 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6175 inst
.instruction
|= Rd
;
6178 inst
.instruction
|= Rn
<< 3;
6180 inst
.instruction
|= Rs
<< 3;
6182 constraint (1, _("dest must overlap one source register"));
6189 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
6190 constraint (msb
> 32, _("bit-field extends past end of register"));
6191 /* The instruction encoding stores the LSB and MSB,
6192 not the LSB and width. */
6193 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6194 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
6195 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
6196 inst
.instruction
|= msb
- 1;
6204 /* #0 in second position is alternative syntax for bfc, which is
6205 the same instruction but with REG_PC in the Rm field. */
6206 if (!inst
.operands
[1].isreg
)
6207 inst
.operands
[1].reg
= REG_PC
;
6209 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
6210 constraint (msb
> 32, _("bit-field extends past end of register"));
6211 /* The instruction encoding stores the LSB and MSB,
6212 not the LSB and width. */
6213 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6214 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6215 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
6216 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
6217 inst
.instruction
|= msb
- 1;
6223 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
6224 _("bit-field extends past end of register"));
6225 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6226 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6227 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
6228 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
6229 inst
.instruction
|= inst
.operands
[3].imm
- 1;
6232 /* ARM V5 Thumb BLX (argument parse)
6233 BLX <target_addr> which is BLX(1)
6234 BLX <Rm> which is BLX(2)
6235 Unfortunately, there are two different opcodes for this mnemonic.
6236 So, the insns[].value is not used, and the code here zaps values
6237 into inst.instruction.
6239 ??? How to take advantage of the additional two bits of displacement
6240 available in Thumb32 mode? Need new relocation? */
6245 if (inst
.operands
[0].isreg
)
6246 /* We have a register, so this is BLX(2). */
6247 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
6250 /* No register. This must be BLX(1). */
6251 inst
.instruction
= 0xf000e800;
6252 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
6253 inst
.reloc
.pc_rel
= 1;
6260 if (unified_syntax
&& inst
.size_req
!= 2)
6262 if (inst
.cond
== COND_ALWAYS
)
6264 inst
.instruction
= 0xf000b000;
6265 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
6269 assert (inst
.cond
!= 0xF);
6270 inst
.instruction
= (inst
.cond
<< 22) | 0xf0008000;
6271 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
6276 if (inst
.cond
== COND_ALWAYS
)
6277 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
6280 inst
.instruction
= 0xd000 | (inst
.cond
<< 8);
6281 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
6285 inst
.reloc
.pc_rel
= 1;
6291 if (inst
.operands
[0].present
)
6293 constraint (inst
.operands
[0].imm
> 255,
6294 _("immediate value out of range"));
6295 inst
.instruction
|= inst
.operands
[0].imm
;
6300 do_t_branch23 (void)
6302 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
6303 inst
.reloc
.pc_rel
= 1;
6305 /* If the destination of the branch is a defined symbol which does not have
6306 the THUMB_FUNC attribute, then we must be calling a function which has
6307 the (interfacearm) attribute. We look for the Thumb entry point to that
6308 function and change the branch to refer to that function instead. */
6309 if ( inst
.reloc
.exp
.X_op
== O_symbol
6310 && inst
.reloc
.exp
.X_add_symbol
!= NULL
6311 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
6312 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
6313 inst
.reloc
.exp
.X_add_symbol
=
6314 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
6320 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
6321 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
6322 should cause the alignment to be checked once it is known. This is
6323 because BX PC only works if the instruction is word aligned. */
6329 if (inst
.operands
[0].reg
== REG_PC
)
6330 as_tsktsk (_("use of r15 in bxj is not really useful"));
6332 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6338 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6339 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6340 inst
.instruction
|= inst
.operands
[1].reg
;
6347 && (inst
.operands
[1].present
|| inst
.size_req
== 4))
6349 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
6350 inst
.instruction
= 0xf3af8000;
6351 inst
.instruction
|= imod
<< 9;
6352 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
6353 if (inst
.operands
[1].present
)
6354 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
6358 constraint (inst
.operands
[1].present
,
6359 _("Thumb does not support the 2-argument "
6360 "form of this instruction"));
6361 inst
.instruction
|= inst
.operands
[0].imm
;
6365 /* THUMB CPY instruction (argument parse). */
6370 if (inst
.size_req
== 4)
6372 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
6373 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6374 inst
.instruction
|= inst
.operands
[1].reg
;
6378 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
6379 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
6380 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6387 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
6388 inst
.instruction
|= inst
.operands
[0].reg
;
6389 inst
.reloc
.pc_rel
= 1;
6390 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
6396 if (unified_syntax
&& inst
.size_req
== 4)
6397 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6399 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6405 unsigned int cond
= inst
.operands
[0].imm
;
6407 current_it_mask
= (inst
.instruction
& 0xf) | 0x10;
6410 /* If the condition is a negative condition, invert the mask. */
6411 if ((cond
& 0x1) == 0x0)
6413 unsigned int mask
= inst
.instruction
& 0x000f;
6415 if ((mask
& 0x7) == 0)
6416 /* no conversion needed */;
6417 else if ((mask
& 0x3) == 0)
6419 else if ((mask
& 0x1) == 0)
6424 inst
.instruction
&= 0xfff0;
6425 inst
.instruction
|= mask
;
6428 inst
.instruction
|= cond
<< 4;
6434 /* This really doesn't seem worth it. */
6435 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
6436 _("expression too complex"));
6437 constraint (inst
.operands
[1].writeback
,
6438 _("Thumb load/store multiple does not support {reglist}^"));
6442 /* See if we can use a 16-bit instruction. */
6443 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
6444 && inst
.size_req
!= 4
6445 && inst
.operands
[0].reg
<= 7
6446 && !(inst
.operands
[1].imm
& ~0xff)
6447 && (inst
.instruction
== T_MNEM_stmia
6448 ? inst
.operands
[0].writeback
6449 : (inst
.operands
[0].writeback
6450 == !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))))
6452 if (inst
.instruction
== T_MNEM_stmia
6453 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
6454 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
6455 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6456 inst
.operands
[0].reg
);
6458 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6459 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6460 inst
.instruction
|= inst
.operands
[1].imm
;
6464 if (inst
.operands
[1].imm
& (1 << 13))
6465 as_warn (_("SP should not be in register list"));
6466 if (inst
.instruction
== T_MNEM_stmia
)
6468 if (inst
.operands
[1].imm
& (1 << 15))
6469 as_warn (_("PC should not be in register list"));
6470 if (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
6471 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6472 inst
.operands
[0].reg
);
6476 if (inst
.operands
[1].imm
& (1 << 14)
6477 && inst
.operands
[1].imm
& (1 << 15))
6478 as_warn (_("LR and PC should not both be in register list"));
6479 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
6480 && inst
.operands
[0].writeback
)
6481 as_warn (_("base register should not be in register list "
6482 "when written back"));
6484 if (inst
.instruction
< 0xffff)
6485 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6486 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6487 inst
.instruction
|= inst
.operands
[1].imm
;
6488 if (inst
.operands
[0].writeback
)
6489 inst
.instruction
|= WRITE_BACK
;
6494 constraint (inst
.operands
[0].reg
> 7
6495 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
6496 if (inst
.instruction
== T_MNEM_stmia
)
6498 if (!inst
.operands
[0].writeback
)
6499 as_warn (_("this instruction will write back the base register"));
6500 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
6501 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
6502 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6503 inst
.operands
[0].reg
);
6507 if (!inst
.operands
[0].writeback
6508 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
6509 as_warn (_("this instruction will write back the base register"));
6510 else if (inst
.operands
[0].writeback
6511 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
6512 as_warn (_("this instruction will not write back the base register"));
6515 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6516 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6517 inst
.instruction
|= inst
.operands
[1].imm
;
6524 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
6525 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
6526 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
6527 || inst
.operands
[1].negative
,
6528 _("instruction does not accept this addressing mode"));
6530 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6531 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6532 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
6538 if (!inst
.operands
[1].present
)
6540 constraint (inst
.operands
[0].reg
== REG_LR
,
6541 _("r14 not allowed as first register "
6542 "when second register is omitted"));
6543 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
6545 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
6548 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6549 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
6550 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6558 /* Generation of 16-bit instructions for anything other than
6559 Rd, [Rn, Ri] is deferred to section relaxation time. */
6560 if (inst
.operands
[1].isreg
&& inst
.operands
[1].immisreg
6561 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
6562 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
6563 && inst
.operands
[1].reg
<= 7 && inst
.operands
[1].imm
<= 7
6564 && inst
.instruction
<= 0xffff)
6566 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6570 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6571 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6572 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
6576 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
6578 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
6580 /* Only [Rn,Rm] is acceptable. */
6581 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
6582 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
6583 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
6584 || inst
.operands
[1].negative
,
6585 _("Thumb does not support this addressing mode"));
6586 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6590 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6591 if (!inst
.operands
[1].isreg
)
6592 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
6595 constraint (!inst
.operands
[1].preind
6596 || inst
.operands
[1].shifted
6597 || inst
.operands
[1].writeback
,
6598 _("Thumb does not support this addressing mode"));
6599 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
6601 constraint (inst
.instruction
& 0x0600,
6602 _("byte or halfword not valid for base register"));
6603 constraint (inst
.operands
[1].reg
== REG_PC
6604 && !(inst
.instruction
& THUMB_LOAD_BIT
),
6605 _("r15 based store not allowed"));
6606 constraint (inst
.operands
[1].immisreg
,
6607 _("invalid base register for register offset"));
6609 if (inst
.operands
[1].reg
== REG_PC
)
6610 inst
.instruction
= T_OPCODE_LDR_PC
;
6611 else if (inst
.instruction
& THUMB_LOAD_BIT
)
6612 inst
.instruction
= T_OPCODE_LDR_SP
;
6614 inst
.instruction
= T_OPCODE_STR_SP
;
6616 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6617 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
6621 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
6622 if (!inst
.operands
[1].immisreg
)
6624 /* Immediate offset. */
6625 inst
.instruction
|= inst
.operands
[0].reg
;
6626 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6627 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
6631 /* Register offset. */
6632 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
6633 constraint (inst
.operands
[1].negative
,
6634 _("Thumb does not support this addressing mode"));
6637 switch (inst
.instruction
)
6639 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
6640 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
6641 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
6642 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
6643 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
6644 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
6645 case 0x5600 /* ldrsb */:
6646 case 0x5e00 /* ldrsh */: break;
6650 inst
.instruction
|= inst
.operands
[0].reg
;
6651 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6652 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
6658 if (!inst
.operands
[1].present
)
6660 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
6661 constraint (inst
.operands
[0].reg
== REG_LR
,
6662 _("r14 not allowed here"));
6664 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6665 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
6666 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
6673 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6674 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
6680 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6681 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6682 inst
.instruction
|= inst
.operands
[2].reg
;
6683 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
6689 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6690 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
6691 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6692 inst
.instruction
|= inst
.operands
[3].reg
;
6700 int r0off
= (inst
.instruction
== T_MNEM_mov
6701 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
6702 if (!inst
.operands
[1].isreg
)
6704 /* For an immediate, we always generate a 32-bit opcode;
6705 section relaxation will shrink it later if possible. */
6706 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6707 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
6708 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
6709 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
6711 else if (inst
.size_req
== 4
6712 || inst
.operands
[1].shifted
6713 || (inst
.instruction
== T_MNEM_movs
6714 && (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)))
6716 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6717 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
6718 encode_thumb32_shifted_operand (1);
6721 switch (inst
.instruction
)
6724 inst
.instruction
= T_OPCODE_MOV_HR
;
6725 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
6726 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
6727 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6731 /* We know we have low registers at this point.
6732 Generate ADD Rd, Rs, #0. */
6733 inst
.instruction
= T_OPCODE_ADD_I3
;
6734 inst
.instruction
|= inst
.operands
[0].reg
;
6735 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6739 if (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7)
6741 inst
.instruction
= T_OPCODE_CMP_LR
;
6742 inst
.instruction
|= inst
.operands
[0].reg
;
6743 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6747 inst
.instruction
= T_OPCODE_CMP_HR
;
6748 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
6749 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
6750 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6757 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6758 if (inst
.operands
[1].isreg
)
6760 if (inst
.operands
[0].reg
< 8 && inst
.operands
[1].reg
< 8)
6762 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
6763 since a MOV instruction produces unpredictable results. */
6764 if (inst
.instruction
== T_OPCODE_MOV_I8
)
6765 inst
.instruction
= T_OPCODE_ADD_I3
;
6767 inst
.instruction
= T_OPCODE_CMP_LR
;
6769 inst
.instruction
|= inst
.operands
[0].reg
;
6770 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6774 if (inst
.instruction
== T_OPCODE_MOV_I8
)
6775 inst
.instruction
= T_OPCODE_MOV_HR
;
6777 inst
.instruction
= T_OPCODE_CMP_HR
;
6783 constraint (inst
.operands
[0].reg
> 7,
6784 _("only lo regs allowed with immediate"));
6785 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6786 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
6793 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6794 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf000) << 4;
6795 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0800) << 15;
6796 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0700) << 4;
6797 inst
.instruction
|= (inst
.operands
[1].imm
& 0x00ff);
6805 int r0off
= (inst
.instruction
== T_MNEM_mvn
6806 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
6807 if (!inst
.operands
[1].isreg
)
6809 /* For an immediate, we always generate a 32-bit opcode;
6810 section relaxation will shrink it later if possible. */
6811 if (inst
.instruction
< 0xffff)
6812 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6813 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
6814 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
6815 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
6819 /* See if we can do this with a 16-bit instruction. */
6820 if (inst
.instruction
< 0xffff
6821 && THUMB_SETS_FLAGS (inst
.instruction
)
6822 && !inst
.operands
[1].shifted
6823 && inst
.operands
[0].reg
<= 7
6824 && inst
.operands
[1].reg
<= 7
6825 && inst
.size_req
!= 4)
6827 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6828 inst
.instruction
|= inst
.operands
[0].reg
;
6829 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6833 constraint (inst
.operands
[1].shifted
6834 && inst
.operands
[1].immisreg
,
6835 _("shift must be constant"));
6836 if (inst
.instruction
< 0xffff)
6837 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6838 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
6839 encode_thumb32_shifted_operand (1);
6845 constraint (inst
.instruction
> 0xffff
6846 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
6847 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
6848 _("unshifted register required"));
6849 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
6852 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6853 inst
.instruction
|= inst
.operands
[0].reg
;
6854 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6861 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
6862 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
6864 _("'CPSR' or 'SPSR' expected"));
6865 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6866 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
) >> 2;
6872 constraint (!inst
.operands
[1].isreg
,
6873 _("Thumb encoding does not support an immediate here"));
6874 inst
.instruction
|= (inst
.operands
[0].imm
& SPSR_BIT
) >> 2;
6875 inst
.instruction
|= (inst
.operands
[0].imm
& ~SPSR_BIT
) >> 8;
6876 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6882 if (!inst
.operands
[2].present
)
6883 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
6885 /* There is no 32-bit MULS and no 16-bit MUL. */
6886 if (unified_syntax
&& inst
.instruction
== T_MNEM_mul
)
6888 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6889 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6890 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6891 inst
.instruction
|= inst
.operands
[2].reg
<< 0;
6895 constraint (!unified_syntax
6896 && inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
6897 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
6900 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6901 inst
.instruction
|= inst
.operands
[0].reg
;
6903 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
6904 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
6905 else if (inst
.operands
[0].reg
== inst
.operands
[2].reg
)
6906 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6908 constraint (1, _("dest must overlap one source register"));
6915 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6916 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
6917 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6918 inst
.instruction
|= inst
.operands
[3].reg
;
6920 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
6921 as_tsktsk (_("rdhi and rdlo must be different"));
6929 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
6931 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6932 inst
.instruction
|= inst
.operands
[0].imm
;
6936 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6937 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
6942 constraint (inst
.operands
[0].present
,
6943 _("Thumb does not support NOP with hints"));
6944 inst
.instruction
= 0x46c0;
6953 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7
6954 || !THUMB_SETS_FLAGS (inst
.instruction
)
6955 || inst
.size_req
== 4)
6957 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6958 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6959 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6963 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6964 inst
.instruction
|= inst
.operands
[0].reg
;
6965 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6970 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
6972 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
6974 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6975 inst
.instruction
|= inst
.operands
[0].reg
;
6976 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6983 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6984 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6985 inst
.instruction
|= inst
.operands
[2].reg
;
6986 if (inst
.operands
[3].present
)
6988 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
6989 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
6990 _("expression too complex"));
6991 inst
.instruction
|= (val
& 0x1c) << 10;
6992 inst
.instruction
|= (val
& 0x03) << 6;
6999 if (!inst
.operands
[3].present
)
7000 inst
.instruction
&= ~0x00000020;
7007 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
7011 do_t_push_pop (void)
7015 constraint (inst
.operands
[0].writeback
,
7016 _("push/pop do not support {reglist}^"));
7017 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
7018 _("expression too complex"));
7020 mask
= inst
.operands
[0].imm
;
7021 if ((mask
& ~0xff) == 0)
7022 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7023 else if ((inst
.instruction
== T_MNEM_push
7024 && (mask
& ~0xff) == 1 << REG_LR
)
7025 || (inst
.instruction
== T_MNEM_pop
7026 && (mask
& ~0xff) == 1 << REG_PC
))
7028 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7029 inst
.instruction
|= THUMB_PP_PC_LR
;
7032 else if (unified_syntax
)
7034 if (mask
& (1 << 13))
7035 inst
.error
= _("SP not allowed in register list");
7036 if (inst
.instruction
== T_MNEM_push
)
7038 if (mask
& (1 << 15))
7039 inst
.error
= _("PC not allowed in register list");
7043 if (mask
& (1 << 14)
7044 && mask
& (1 << 15))
7045 inst
.error
= _("LR and PC should not both be in register list");
7047 if ((mask
& (mask
- 1)) == 0)
7049 /* Single register push/pop implemented as str/ldr. */
7050 if (inst
.instruction
== T_MNEM_push
)
7051 inst
.instruction
= 0xf84d0d04; /* str reg, [sp, #-4]! */
7053 inst
.instruction
= 0xf85d0b04; /* ldr reg, [sp], #4 */
7054 mask
= ffs(mask
) - 1;
7058 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
7062 inst
.error
= _("invalid register list to push/pop instruction");
7066 inst
.instruction
|= mask
;
7072 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7073 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7079 if (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
7080 && inst
.size_req
!= 4)
7082 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7083 inst
.instruction
|= inst
.operands
[0].reg
;
7084 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7086 else if (unified_syntax
)
7088 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
7089 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7090 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7091 inst
.instruction
|= inst
.operands
[1].reg
;
7094 inst
.error
= BAD_HIREG
;
7102 Rd
= inst
.operands
[0].reg
;
7103 Rs
= (inst
.operands
[1].present
7104 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
7105 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
7107 inst
.instruction
|= Rd
<< 8;
7108 inst
.instruction
|= Rs
<< 16;
7109 if (!inst
.operands
[2].isreg
)
7111 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
7112 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
7115 encode_thumb32_shifted_operand (2);
7121 if (inst
.operands
[0].imm
)
7122 inst
.instruction
|= 0x8;
7128 if (!inst
.operands
[1].present
)
7129 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7133 if (inst
.operands
[0].reg
> 7
7134 || inst
.operands
[1].reg
> 7
7135 || !THUMB_SETS_FLAGS (inst
.instruction
)
7136 || (!inst
.operands
[2].isreg
&& inst
.instruction
== T_MNEM_rors
)
7137 || (inst
.operands
[2].isreg
&& inst
.operands
[1].reg
!= inst
.operands
[0].reg
)
7138 || inst
.size_req
== 4)
7140 if (inst
.operands
[2].isreg
)
7142 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
7143 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7144 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7145 inst
.instruction
|= inst
.operands
[2].reg
;
7149 inst
.operands
[1].shifted
= 1;
7150 switch (inst
.instruction
)
7153 case T_MNEM_asrs
: inst
.operands
[1].shift_kind
= SHIFT_ASR
; break;
7155 case T_MNEM_lsls
: inst
.operands
[1].shift_kind
= SHIFT_LSL
; break;
7157 case T_MNEM_lsrs
: inst
.operands
[1].shift_kind
= SHIFT_LSR
; break;
7159 case T_MNEM_rors
: inst
.operands
[1].shift_kind
= SHIFT_ROR
; break;
7163 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
7164 ? T_MNEM_movs
: T_MNEM_mov
);
7165 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7166 encode_thumb32_shifted_operand (1);
7167 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
7168 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7173 if (inst
.operands
[2].isreg
)
7175 switch (inst
.instruction
)
7177 case T_MNEM_asrs
: inst
.instruction
= T_OPCODE_ASR_R
; break;
7178 case T_MNEM_lsls
: inst
.instruction
= T_OPCODE_LSL_R
; break;
7179 case T_MNEM_lsrs
: inst
.instruction
= T_OPCODE_LSR_R
; break;
7180 case T_MNEM_rors
: inst
.instruction
= T_OPCODE_ROR_R
; break;
7184 inst
.instruction
|= inst
.operands
[0].reg
;
7185 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
7189 switch (inst
.instruction
)
7191 case T_MNEM_asrs
: inst
.instruction
= T_OPCODE_ASR_I
; break;
7192 case T_MNEM_lsls
: inst
.instruction
= T_OPCODE_LSL_I
; break;
7193 case T_MNEM_lsrs
: inst
.instruction
= T_OPCODE_LSR_I
; break;
7196 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
7197 inst
.instruction
|= inst
.operands
[0].reg
;
7198 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7204 constraint (inst
.operands
[0].reg
> 7
7205 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
7206 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
7208 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
7210 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
7211 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
7212 _("source1 and dest must be same register"));
7214 switch (inst
.instruction
)
7216 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
7217 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
7218 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
7219 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
7223 inst
.instruction
|= inst
.operands
[0].reg
;
7224 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
7228 switch (inst
.instruction
)
7230 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
7231 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
7232 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
7233 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
7236 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
7237 inst
.instruction
|= inst
.operands
[0].reg
;
7238 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7246 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7247 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7248 inst
.instruction
|= inst
.operands
[2].reg
;
7254 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
7255 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
7256 _("expression too complex"));
7257 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7258 inst
.instruction
|= (value
& 0xf000) >> 12;
7259 inst
.instruction
|= (value
& 0x0ff0);
7260 inst
.instruction
|= (value
& 0x000f) << 16;
7266 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7267 inst
.instruction
|= inst
.operands
[1].imm
- 1;
7268 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7270 if (inst
.operands
[3].present
)
7272 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
7273 _("expression too complex"));
7275 if (inst
.reloc
.exp
.X_add_number
!= 0)
7277 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
7278 inst
.instruction
|= 0x00200000; /* sh bit */
7279 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
7280 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
7282 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7289 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7290 inst
.instruction
|= inst
.operands
[1].imm
- 1;
7291 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7297 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7298 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7299 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7300 || inst
.operands
[2].negative
,
7301 _("instruction does not accept this addressing mode"));
7303 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7304 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7305 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7306 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
7312 if (!inst
.operands
[2].present
)
7313 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
7315 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7316 || inst
.operands
[0].reg
== inst
.operands
[2].reg
7317 || inst
.operands
[0].reg
== inst
.operands
[3].reg
7318 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
7321 inst
.instruction
|= inst
.operands
[0].reg
;
7322 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7323 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7324 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7330 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7331 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7332 inst
.instruction
|= inst
.operands
[2].reg
;
7333 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
7339 if (inst
.instruction
<= 0xffff && inst
.size_req
!= 4
7340 && inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
7341 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
7343 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7344 inst
.instruction
|= inst
.operands
[0].reg
;
7345 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7347 else if (unified_syntax
)
7349 if (inst
.instruction
<= 0xffff)
7350 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
7351 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7352 inst
.instruction
|= inst
.operands
[1].reg
;
7353 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
7357 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
7358 _("Thumb encoding does not support rotation"));
7359 constraint (1, BAD_HIREG
);
7366 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7374 half
= (inst
.instruction
& 0x10) != 0;
7375 constraint (inst
.operands
[0].imm
== 15,
7376 _("PC is not a valid index register"));
7377 constraint (!half
&& inst
.operands
[0].shifted
,
7378 _("instruction does not allow shifted index"));
7379 constraint (half
&& !inst
.operands
[0].shifted
,
7380 _("instruction requires shifted index"));
7381 inst
.instruction
|= (inst
.operands
[0].reg
<< 16) | inst
.operands
[0].imm
;
7387 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7388 inst
.instruction
|= inst
.operands
[1].imm
;
7389 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7391 if (inst
.operands
[3].present
)
7393 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
7394 _("expression too complex"));
7395 if (inst
.reloc
.exp
.X_add_number
!= 0)
7397 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
7398 inst
.instruction
|= 0x00200000; /* sh bit */
7400 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
7401 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
7403 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7410 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7411 inst
.instruction
|= inst
.operands
[1].imm
;
7412 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7415 /* Overall per-instruction processing. */
7417 /* We need to be able to fix up arbitrary expressions in some statements.
7418 This is so that we can handle symbols that are an arbitrary distance from
7419 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
7420 which returns part of an address in a form which will be valid for
7421 a data instruction. We do this by pushing the expression into a symbol
7422 in the expr_section, and creating a fix for that. */
7425 fix_new_arm (fragS
* frag
,
7440 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
7444 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
7449 /* Mark whether the fix is to a THUMB instruction, or an ARM
7451 new_fix
->tc_fix_data
= thumb_mode
;
7455 output_inst (const char * str
)
7461 as_bad ("%s -- `%s'", inst
.error
, str
);
7467 to
= frag_more (inst
.size
);
7469 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
7471 assert (inst
.size
== (2 * THUMB_SIZE
));
7472 md_number_to_chars (to
, inst
.instruction
>> 16, THUMB_SIZE
);
7473 md_number_to_chars (to
+ THUMB_SIZE
, inst
.instruction
, THUMB_SIZE
);
7475 else if (inst
.size
> INSN_SIZE
)
7477 assert (inst
.size
== (2 * INSN_SIZE
));
7478 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
7479 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
7482 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
7484 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7485 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
7486 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
7490 dwarf2_emit_insn (inst
.size
);
7494 /* Tag values used in struct asm_opcode's tag field. */
7497 OT_unconditional
, /* Instruction cannot be conditionalized.
7498 The ARM condition field is still 0xE. */
7499 OT_unconditionalF
, /* Instruction cannot be conditionalized
7500 and carries 0xF in its ARM condition field. */
7501 OT_csuffix
, /* Instruction takes a conditional suffix. */
7502 OT_cinfix3
, /* Instruction takes a conditional infix,
7503 beginning at character index 3. (In
7504 unified mode, it becomes a suffix.) */
7505 OT_csuf_or_in3
, /* Instruction takes either a conditional
7506 suffix or an infix at character index 3.
7507 (In unified mode, a suffix only. */
7508 OT_odd_infix_unc
, /* This is the unconditional variant of an
7509 instruction that takes a conditional infix
7510 at an unusual position. In unified mode,
7511 this variant will accept a suffix. */
7512 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
7513 are the conditional variants of instructions that
7514 take conditional infixes in unusual positions.
7515 The infix appears at character index
7516 (tag - OT_odd_infix_0). These are not accepted
7520 /* Subroutine of md_assemble, responsible for looking up the primary
7521 opcode from the mnemonic the user wrote. STR points to the
7522 beginning of the mnemonic.
7524 This is not simply a hash table lookup, because of conditional
7525 variants. Most instructions have conditional variants, which are
7526 expressed with a _conditional affix_ to the mnemonic. If we were
7527 to encode each conditional variant as a literal string in the opcode
7528 table, it would have approximately 20,000 entries.
7530 Most mnemonics take this affix as a suffix, and in unified syntax,
7531 'most' is upgraded to 'all'. However, in the divided syntax, some
7532 instructions take the affix as an infix, notably the s-variants of
7533 the arithmetic instructions. Of those instructions, all but six
7534 have the infix appear after the third character of the mnemonic.
7536 Accordingly, the algorithm for looking up primary opcodes given
7539 1. Look up the identifier in the opcode table.
7540 If we find a match, go to step U.
7542 2. Look up the last two characters of the identifier in the
7543 conditions table. If we find a match, look up the first N-2
7544 characters of the identifier in the opcode table. If we
7545 find a match, go to step CE.
7547 3. Look up the fourth and fifth characters of the identifier in
7548 the conditions table. If we find a match, extract those
7549 characters from the identifier, and look up the remaining
7550 characters in the opcode table. If we find a match, go
7555 U. Examine the tag field of the opcode structure, in case this is
7556 one of the six instructions with its conditional infix in an
7557 unusual place. If it is, the tag tells us where to find the
7558 infix; look it up in the conditions table and set inst.cond
7559 accordingly. Otherwise, this is an unconditional instruction.
7560 Again set inst.cond accordingly. Return the opcode structure.
7562 CE. Examine the tag field to make sure this is an instruction that
7563 should receive a conditional suffix. If it is not, fail.
7564 Otherwise, set inst.cond from the suffix we already looked up,
7565 and return the opcode structure.
7567 CM. Examine the tag field to make sure this is an instruction that
7568 should receive a conditional infix after the third character.
7569 If it is not, fail. Otherwise, undo the edits to the current
7570 line of input and proceed as for case CE. */
7572 static const struct asm_opcode
*
7573 opcode_lookup (char **str
)
7577 const struct asm_opcode
*opcode
;
7578 const struct asm_cond
*cond
;
7580 /* Scan up to the end of the mnemonic, which must end in white space,
7581 '.' (in unified mode only), or end of string. */
7582 for (base
= end
= *str
; *end
!= '\0'; end
++)
7583 if (*end
== ' ' || (unified_syntax
&& *end
== '.'))
7589 /* Handle a possible width suffix. */
7592 if (end
[1] == 'w' && (end
[2] == ' ' || end
[2] == '\0'))
7594 else if (end
[1] == 'n' && (end
[2] == ' ' || end
[2] == '\0'))
7604 /* Look for unaffixed or special-case affixed mnemonic. */
7605 opcode
= hash_find_n (arm_ops_hsh
, base
, end
- base
);
7609 if (opcode
->tag
< OT_odd_infix_0
)
7611 inst
.cond
= COND_ALWAYS
;
7616 as_warn (_("conditional infixes are deprecated in unified syntax"));
7617 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
7618 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
7621 inst
.cond
= cond
->value
;
7625 /* Cannot have a conditional suffix on a mnemonic of less than two
7630 /* Look for suffixed mnemonic. */
7632 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
7633 opcode
= hash_find_n (arm_ops_hsh
, base
, affix
- base
);
7637 switch (opcode
->tag
)
7640 case OT_odd_infix_unc
:
7641 if (!unified_syntax
)
7643 /* else fall through */
7646 case OT_csuf_or_in3
:
7647 inst
.cond
= cond
->value
;
7650 case OT_unconditional
:
7651 case OT_unconditionalF
:
7652 /* delayed diagnostic */
7653 inst
.error
= BAD_COND
;
7654 inst
.cond
= COND_ALWAYS
;
7662 /* Cannot have a usual-position infix on a mnemonic of less than
7663 six characters (five would be a suffix). */
7667 /* Look for infixed mnemonic in the usual position. */
7669 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
7673 memcpy (save
, affix
, 2);
7674 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
7675 opcode
= hash_find_n (arm_ops_hsh
, base
, (end
- base
) - 2);
7676 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
7677 memcpy (affix
, save
, 2);
7679 if (opcode
&& (opcode
->tag
== OT_cinfix3
|| opcode
->tag
== OT_csuf_or_in3
))
7683 as_warn (_("conditional infixes are deprecated in unified syntax"));
7685 inst
.cond
= cond
->value
;
7693 md_assemble (char *str
)
7696 const struct asm_opcode
* opcode
;
7698 /* Align the previous label if needed. */
7699 if (last_label_seen
!= NULL
)
7701 symbol_set_frag (last_label_seen
, frag_now
);
7702 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
7703 S_SET_SEGMENT (last_label_seen
, now_seg
);
7706 memset (&inst
, '\0', sizeof (inst
));
7707 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7709 opcode
= opcode_lookup (&p
);
7712 /* It wasn't an instruction, but it might be a register alias of
7713 the form alias .req reg. */
7714 if (!create_register_alias (str
, p
))
7715 as_bad (_("bad instruction `%s'"), str
);
7722 /* Check that this instruction is supported for this CPU. */
7723 if (thumb_mode
== 1 && (opcode
->tvariant
& cpu_variant
) == 0)
7725 as_bad (_("selected processor does not support `%s'"), str
);
7728 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
7729 && opcode
->tencode
!= do_t_branch
)
7731 as_bad (_("Thumb does not support conditional execution"));
7735 /* Check conditional suffixes. */
7736 if (current_it_mask
)
7739 cond
= current_cc
^ ((current_it_mask
>> 4) & 1) ^ 1;
7740 if (cond
!= inst
.cond
)
7742 as_bad (_("incorrect condition in IT block"));
7745 current_it_mask
<<= 1;
7746 current_it_mask
&= 0x1f;
7748 else if (inst
.cond
!= COND_ALWAYS
&& opcode
->tencode
!= do_t_branch
)
7750 as_bad (_("thumb conditional instrunction not in IT block"));
7754 mapping_state (MAP_THUMB
);
7755 inst
.instruction
= opcode
->tvalue
;
7757 if (!parse_operands (p
, opcode
->operands
))
7760 /* Clear current_it_mask at the end of an IT block. */
7761 if (current_it_mask
== 0x10)
7762 current_it_mask
= 0;
7766 assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
7767 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
7768 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
7770 as_bad (_("cannot honor width suffix -- `%s'"), str
);
7777 /* Check that this instruction is supported for this CPU. */
7778 if ((opcode
->avariant
& cpu_variant
) == 0)
7780 as_bad (_("selected processor does not support `%s'"), str
);
7785 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
7789 mapping_state (MAP_ARM
);
7790 inst
.instruction
= opcode
->avalue
;
7791 if (opcode
->tag
== OT_unconditionalF
)
7792 inst
.instruction
|= 0xF << 28;
7794 inst
.instruction
|= inst
.cond
<< 28;
7795 inst
.size
= INSN_SIZE
;
7796 if (!parse_operands (p
, opcode
->operands
))
7802 /* Various frobbings of labels and their addresses. */
7805 arm_start_line_hook (void)
7807 last_label_seen
= NULL
;
7811 arm_frob_label (symbolS
* sym
)
7813 last_label_seen
= sym
;
7815 ARM_SET_THUMB (sym
, thumb_mode
);
7817 #if defined OBJ_COFF || defined OBJ_ELF
7818 ARM_SET_INTERWORK (sym
, support_interwork
);
7821 /* Note - do not allow local symbols (.Lxxx) to be labeled
7822 as Thumb functions. This is because these labels, whilst
7823 they exist inside Thumb code, are not the entry points for
7824 possible ARM->Thumb calls. Also, these labels can be used
7825 as part of a computed goto or switch statement. eg gcc
7826 can generate code that looks like this:
7838 The first instruction loads the address of the jump table.
7839 The second instruction converts a table index into a byte offset.
7840 The third instruction gets the jump address out of the table.
7841 The fourth instruction performs the jump.
7843 If the address stored at .Laaa is that of a symbol which has the
7844 Thumb_Func bit set, then the linker will arrange for this address
7845 to have the bottom bit set, which in turn would mean that the
7846 address computation performed by the third instruction would end
7847 up with the bottom bit set. Since the ARM is capable of unaligned
7848 word loads, the instruction would then load the incorrect address
7849 out of the jump table, and chaos would ensue. */
7850 if (label_is_thumb_function_name
7851 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
7852 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
7854 /* When the address of a Thumb function is taken the bottom
7855 bit of that address should be set. This will allow
7856 interworking between Arm and Thumb functions to work
7859 THUMB_SET_FUNC (sym
, 1);
7861 label_is_thumb_function_name
= FALSE
;
7866 arm_data_in_code (void)
7868 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
7870 *input_line_pointer
= '/';
7871 input_line_pointer
+= 5;
7872 *input_line_pointer
= 0;
7880 arm_canonicalize_symbol_name (char * name
)
7884 if (thumb_mode
&& (len
= strlen (name
)) > 5
7885 && streq (name
+ len
- 5, "/data"))
7886 *(name
+ len
- 5) = 0;
7891 /* Table of all register names defined by default. The user can
7892 define additional names with .req. Note that all register names
7893 should appear in both upper and lowercase variants. Some registers
7894 also have mixed-case names. */
7896 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
7897 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
7898 #define REGSET(p,t) \
7899 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
7900 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
7901 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
7902 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
7904 static const struct reg_entry reg_names
[] =
7906 /* ARM integer registers. */
7907 REGSET(r
, RN
), REGSET(R
, RN
),
7909 /* ATPCS synonyms. */
7910 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
7911 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
7912 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
7914 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
7915 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
7916 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
7918 /* Well-known aliases. */
7919 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
7920 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
7922 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
7923 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
7925 /* Coprocessor numbers. */
7926 REGSET(p
, CP
), REGSET(P
, CP
),
7928 /* Coprocessor register numbers. The "cr" variants are for backward
7930 REGSET(c
, CN
), REGSET(C
, CN
),
7931 REGSET(cr
, CN
), REGSET(CR
, CN
),
7933 /* FPA registers. */
7934 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
7935 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
7937 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
7938 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
7940 /* VFP SP registers. */
7942 REGNUM(s
,16,VFS
), REGNUM(s
,17,VFS
), REGNUM(s
,18,VFS
), REGNUM(s
,19,VFS
),
7943 REGNUM(s
,20,VFS
), REGNUM(s
,21,VFS
), REGNUM(s
,22,VFS
), REGNUM(s
,23,VFS
),
7944 REGNUM(s
,24,VFS
), REGNUM(s
,25,VFS
), REGNUM(s
,26,VFS
), REGNUM(s
,27,VFS
),
7945 REGNUM(s
,28,VFS
), REGNUM(s
,29,VFS
), REGNUM(s
,30,VFS
), REGNUM(s
,31,VFS
),
7948 REGNUM(S
,16,VFS
), REGNUM(S
,17,VFS
), REGNUM(S
,18,VFS
), REGNUM(S
,19,VFS
),
7949 REGNUM(S
,20,VFS
), REGNUM(S
,21,VFS
), REGNUM(S
,22,VFS
), REGNUM(S
,23,VFS
),
7950 REGNUM(S
,24,VFS
), REGNUM(S
,25,VFS
), REGNUM(S
,26,VFS
), REGNUM(S
,27,VFS
),
7951 REGNUM(S
,28,VFS
), REGNUM(S
,29,VFS
), REGNUM(S
,30,VFS
), REGNUM(S
,31,VFS
),
7953 /* VFP DP Registers. */
7954 REGSET(d
,VFD
), REGSET(D
,VFS
),
7956 /* VFP control registers. */
7957 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
7958 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
7960 /* Maverick DSP coprocessor registers. */
7961 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
7962 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
7964 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
7965 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
7966 REGDEF(dspsc
,0,DSPSC
),
7968 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
7969 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
7970 REGDEF(DSPSC
,0,DSPSC
),
7972 /* iWMMXt data registers - p0, c0-15. */
7973 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
7975 /* iWMMXt control registers - p1, c0-3. */
7976 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
7977 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
7978 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
7979 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
7981 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
7982 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
7983 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
7984 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
7985 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
7987 /* XScale accumulator registers. */
7988 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
7994 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
7995 within psr_required_here. */
7996 static const struct asm_psr psrs
[] =
7998 /* Backward compatibility notation. Note that "all" is no longer
7999 truly all possible PSR bits. */
8000 {"all", PSR_c
| PSR_f
},
8004 /* Individual flags. */
8009 /* Combinations of flags. */
8010 {"fs", PSR_f
| PSR_s
},
8011 {"fx", PSR_f
| PSR_x
},
8012 {"fc", PSR_f
| PSR_c
},
8013 {"sf", PSR_s
| PSR_f
},
8014 {"sx", PSR_s
| PSR_x
},
8015 {"sc", PSR_s
| PSR_c
},
8016 {"xf", PSR_x
| PSR_f
},
8017 {"xs", PSR_x
| PSR_s
},
8018 {"xc", PSR_x
| PSR_c
},
8019 {"cf", PSR_c
| PSR_f
},
8020 {"cs", PSR_c
| PSR_s
},
8021 {"cx", PSR_c
| PSR_x
},
8022 {"fsx", PSR_f
| PSR_s
| PSR_x
},
8023 {"fsc", PSR_f
| PSR_s
| PSR_c
},
8024 {"fxs", PSR_f
| PSR_x
| PSR_s
},
8025 {"fxc", PSR_f
| PSR_x
| PSR_c
},
8026 {"fcs", PSR_f
| PSR_c
| PSR_s
},
8027 {"fcx", PSR_f
| PSR_c
| PSR_x
},
8028 {"sfx", PSR_s
| PSR_f
| PSR_x
},
8029 {"sfc", PSR_s
| PSR_f
| PSR_c
},
8030 {"sxf", PSR_s
| PSR_x
| PSR_f
},
8031 {"sxc", PSR_s
| PSR_x
| PSR_c
},
8032 {"scf", PSR_s
| PSR_c
| PSR_f
},
8033 {"scx", PSR_s
| PSR_c
| PSR_x
},
8034 {"xfs", PSR_x
| PSR_f
| PSR_s
},
8035 {"xfc", PSR_x
| PSR_f
| PSR_c
},
8036 {"xsf", PSR_x
| PSR_s
| PSR_f
},
8037 {"xsc", PSR_x
| PSR_s
| PSR_c
},
8038 {"xcf", PSR_x
| PSR_c
| PSR_f
},
8039 {"xcs", PSR_x
| PSR_c
| PSR_s
},
8040 {"cfs", PSR_c
| PSR_f
| PSR_s
},
8041 {"cfx", PSR_c
| PSR_f
| PSR_x
},
8042 {"csf", PSR_c
| PSR_s
| PSR_f
},
8043 {"csx", PSR_c
| PSR_s
| PSR_x
},
8044 {"cxf", PSR_c
| PSR_x
| PSR_f
},
8045 {"cxs", PSR_c
| PSR_x
| PSR_s
},
8046 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
8047 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
8048 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
8049 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
8050 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
8051 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
8052 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
8053 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
8054 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
8055 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
8056 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
8057 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
8058 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
8059 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
8060 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
8061 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
8062 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
8063 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
8064 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
8065 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
8066 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
8067 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
8068 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
8069 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
8072 /* Table of all shift-in-operand names. */
8073 static const struct asm_shift_name shift_names
[] =
8075 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
8076 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
8077 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
8078 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
8079 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
8080 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
8083 /* Table of all explicit relocation names. */
8085 static struct reloc_entry reloc_names
[] =
8087 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
8088 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
8089 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
8090 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
8091 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
8092 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
8093 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
8094 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
8095 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
8096 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
8097 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
8101 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
8102 static const struct asm_cond conds
[] =
8106 {"cs", 0x2}, {"hs", 0x2},
8107 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
8121 /* Table of ARM-format instructions. */
8123 /* Macros for gluing together operand strings. N.B. In all cases
8124 other than OPS0, the trailing OP_stop comes from default
8125 zero-initialization of the unspecified elements of the array. */
8126 #define OPS0() { OP_stop, }
8127 #define OPS1(a) { OP_##a, }
8128 #define OPS2(a,b) { OP_##a,OP_##b, }
8129 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
8130 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
8131 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
8132 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
8134 /* These macros abstract out the exact format of the mnemonic table and
8135 save some repeated characters. */
8137 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
8138 #define TxCE(mnem, op, top, nops, ops, ae, te) \
8139 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
8140 THUMB_VARIANT, do_##ae, do_##te }
8142 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
8143 a T_MNEM_xyz enumerator. */
8144 #define TCE(mnem, aop, top, nops, ops, ae, te) \
8145 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
8146 #define tCE(mnem, aop, top, nops, ops, ae, te) \
8147 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
8149 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
8150 infix after the third character. */
8151 #define TxC3(mnem, op, top, nops, ops, ae, te) \
8152 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
8153 THUMB_VARIANT, do_##ae, do_##te }
8154 #define TC3(mnem, aop, top, nops, ops, ae, te) \
8155 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
8156 #define tC3(mnem, aop, top, nops, ops, ae, te) \
8157 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
8159 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
8160 appear in the condition table. */
8161 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
8162 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
8163 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
8165 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
8166 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
8167 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
8168 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
8169 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
8170 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
8171 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
8172 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
8173 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
8174 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
8175 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
8176 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
8177 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
8178 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
8179 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
8180 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
8181 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
8182 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
8183 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
8184 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
8186 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
8187 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
8188 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
8189 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
8191 /* Mnemonic that cannot be conditionalized. The ARM condition-code
8192 field is still 0xE. */
8193 #define TUE(mnem, op, top, nops, ops, ae, te) \
8194 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
8195 THUMB_VARIANT, do_##ae, do_##te }
8197 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
8198 condition code field. */
8199 #define TUF(mnem, op, top, nops, ops, ae, te) \
8200 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
8201 THUMB_VARIANT, do_##ae, do_##te }
8203 /* ARM-only variants of all the above. */
8204 #define CE(mnem, op, nops, ops, ae) \
8205 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8207 #define C3(mnem, op, nops, ops, ae) \
8208 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8210 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
8211 { #m1 #m2 #m3, OPS##nops ops, \
8212 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
8213 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8215 #define CM(m1, m2, op, nops, ops, ae) \
8216 xCM_(m1, , m2, op, nops, ops, ae), \
8217 xCM_(m1, eq, m2, op, nops, ops, ae), \
8218 xCM_(m1, ne, m2, op, nops, ops, ae), \
8219 xCM_(m1, cs, m2, op, nops, ops, ae), \
8220 xCM_(m1, hs, m2, op, nops, ops, ae), \
8221 xCM_(m1, cc, m2, op, nops, ops, ae), \
8222 xCM_(m1, ul, m2, op, nops, ops, ae), \
8223 xCM_(m1, lo, m2, op, nops, ops, ae), \
8224 xCM_(m1, mi, m2, op, nops, ops, ae), \
8225 xCM_(m1, pl, m2, op, nops, ops, ae), \
8226 xCM_(m1, vs, m2, op, nops, ops, ae), \
8227 xCM_(m1, vc, m2, op, nops, ops, ae), \
8228 xCM_(m1, hi, m2, op, nops, ops, ae), \
8229 xCM_(m1, ls, m2, op, nops, ops, ae), \
8230 xCM_(m1, ge, m2, op, nops, ops, ae), \
8231 xCM_(m1, lt, m2, op, nops, ops, ae), \
8232 xCM_(m1, gt, m2, op, nops, ops, ae), \
8233 xCM_(m1, le, m2, op, nops, ops, ae), \
8234 xCM_(m1, al, m2, op, nops, ops, ae)
8236 #define UE(mnem, op, nops, ops, ae) \
8237 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
8239 #define UF(mnem, op, nops, ops, ae) \
8240 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
8244 /* Thumb-only, unconditional. */
8245 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
8247 /* ARM-only, takes either a suffix or a position-3 infix
8248 (for an FPA corner case). */
8249 #define C3E(mnem, op, nops, ops, ae) \
8250 { #mnem, OPS##nops ops, OT_csuf_or_in3, 0x##op, 0, ARM_VARIANT, 0, do_##ae, 0 }
8252 static const struct asm_opcode insns
[] =
8254 #define ARM_VARIANT ARM_EXT_V1 /* Core ARM Instructions. */
8255 #define THUMB_VARIANT ARM_EXT_V4T
8256 tCE(and, 0000000, and, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8257 tC3(ands
, 0100000, ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8258 tCE(eor
, 0200000, eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8259 tC3(eors
, 0300000, eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8260 tCE(sub
, 0400000, sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
8261 tC3(subs
, 0500000, subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
8262 tCE(add
, 0800000, add
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
8263 tC3(adds
, 0900000, adds
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
8264 tCE(adc
, 0a00000
, adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8265 tC3(adcs
, 0b00000, adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8266 tCE(sbc
, 0c00000
, sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
8267 tC3(sbcs
, 0d00000
, sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
8268 tCE(orr
, 1800000, orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8269 tC3(orrs
, 1900000, orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8270 tCE(bic
, 1c00000
, bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
8271 tC3(bics
, 1d00000
, bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
8273 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
8274 for setting PSR flag bits. They are obsolete in V6 and do not
8275 have Thumb equivalents. */
8276 tCE(tst
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
8277 tC3(tsts
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
8278 C3(tstp
, 110f000
, 2, (RR
, SH
), cmp
),
8279 tCE(cmp
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
8280 tC3(cmps
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
8281 C3(cmpp
, 150f000
, 2, (RR
, SH
), cmp
),
8282 tCE(cmn
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
8283 tC3(cmns
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
8284 C3(cmnp
, 170f000
, 2, (RR
, SH
), cmp
),
8286 tCE(mov
, 1a00000
, mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
8287 tC3(movs
, 1b00000
, movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
8288 tCE(mvn
, 1e00000
, mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
8289 tC3(mvns
, 1f00000
, mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
8291 tCE(ldr
, 4100000, ldr
, 2, (RR
, ADDR
), ldst
, t_ldst
),
8292 tC3(ldrb
, 4500000, ldrb
, 2, (RR
, ADDR
), ldst
, t_ldst
),
8293 tCE(str
, 4000000, str
, 2, (RR
, ADDR
), ldst
, t_ldst
),
8294 tC3(strb
, 4400000, strb
, 2, (RR
, ADDR
), ldst
, t_ldst
),
8296 tC3(stmia
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8297 tC3(stmea
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8298 tC3(ldmia
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8299 tC3(ldmfd
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8301 TCE(swi
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
8302 TCE(b
, a000000
, e000
, 1, (EXPr
), branch
, t_branch
),
8303 TCE(bl
, b000000
, f000f800
, 1, (EXPr
), branch
, t_branch23
),
8306 tCE(adr
, 28f0000
, adr
, 2, (RR
, EXP
), adr
, t_adr
),
8307 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
8308 tCE(nop
, 1a00000
, nop
, 1, (oI255c
), nop
, t_nop
),
8310 /* Thumb-compatibility pseudo ops. */
8311 tCE(lsl
, 1a00000
, lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
8312 tC3(lsls
, 1b00000
, lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
8313 tCE(lsr
, 1a00020
, lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
8314 tC3(lsrs
, 1b00020
, lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
8315 tCE(asr
, 1a00040
, asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
8316 tC3(asrs
, 1b00040
, asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
8317 tCE(ror
, 1a00060
, ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
8318 tC3(rors
, 1b00060
, rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
8319 tCE(neg
, 2600000, neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
8320 tC3(negs
, 2700000, negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
8321 tCE(push
, 92d0000
, push
, 1, (REGLST
), push_pop
, t_push_pop
),
8322 tCE(pop
, 8bd0000
, pop
, 1, (REGLST
), push_pop
, t_push_pop
),
8324 #undef THUMB_VARIANT
8325 #define THUMB_VARIANT ARM_EXT_V6
8326 TCE(cpy
, 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
8328 /* V1 instructions with no Thumb analogue prior to V6T2. */
8329 #undef THUMB_VARIANT
8330 #define THUMB_VARIANT ARM_EXT_V6T2
8331 TCE(rsb
, 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
8332 TC3(rsbs
, 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
8333 TCE(teq
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
8334 TC3(teqs
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
8335 C3(teqp
, 130f000
, 2, (RR
, SH
), cmp
),
8337 TC3(ldrt
, 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
8338 TC3(ldrbt
, 4700000, f8300e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
8339 TC3(strt
, 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
8340 TC3(strbt
, 4600000, f8200e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
8342 TC3(stmdb
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8343 TC3(stmfd
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8345 TC3(ldmdb
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8346 TC3(ldmea
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8348 /* V1 instructions with no Thumb analogue at all. */
8349 CE(rsc
, 0e00000
, 3, (RR
, oRR
, SH
), arit
),
8350 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
8352 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
8353 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
8354 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
8355 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
8356 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
8357 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
8358 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
8359 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
8362 #define ARM_VARIANT ARM_EXT_V2 /* ARM 2 - multiplies. */
8363 #undef THUMB_VARIANT
8364 #define THUMB_VARIANT ARM_EXT_V4T
8365 tCE(mul
, 0000090, mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
8366 tC3(muls
, 0100090, muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
8368 #undef THUMB_VARIANT
8369 #define THUMB_VARIANT ARM_EXT_V6T2
8370 TCE(mla
, 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
8371 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
8373 /* Generic coprocessor instructions. */
8374 TCE(cdp
, e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
8375 TCE(ldc
, c100000
, ec100000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
8376 TC3(ldcl
, c500000
, ec500000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
8377 TCE(stc
, c000000
, ec000000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
8378 TC3(stcl
, c400000
, ec400000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
8379 TCE(mcr
, e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
8380 TCE(mrc
, e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
8383 #define ARM_VARIANT ARM_EXT_V2S /* ARM 3 - swp instructions. */
8384 CE(swp
, 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
8385 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
8388 #define ARM_VARIANT ARM_EXT_V3 /* ARM 6 Status register instructions. */
8389 TCE(mrs
, 10f0000
, f3ef8000
, 2, (RR
, PSR
), mrs
, t_mrs
),
8390 TCE(msr
, 120f000
, f3808000
, 2, (PSR
, RR_EXi
), msr
, t_msr
),
8393 #define ARM_VARIANT ARM_EXT_V3M /* ARM 7M long multiplies. */
8394 TCE(smull
, 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
8395 CM(smull
,s
, 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
8396 TCE(umull
, 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
8397 CM(umull
,s
, 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
8398 TCE(smlal
, 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
8399 CM(smlal
,s
, 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
8400 TCE(umlal
, 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
8401 CM(umlal
,s
, 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
8404 #define ARM_VARIANT ARM_EXT_V4 /* ARM Architecture 4. */
8405 #undef THUMB_VARIANT
8406 #define THUMB_VARIANT ARM_EXT_V4T
8407 tC3(ldrh
, 01000b0
, ldrh
, 2, (RR
, ADDR
), ldstv4
, t_ldst
),
8408 tC3(strh
, 00000b0
, strh
, 2, (RR
, ADDR
), ldstv4
, t_ldst
),
8409 tC3(ldrsh
, 01000f0
, ldrsh
, 2, (RR
, ADDR
), ldstv4
, t_ldst
),
8410 tC3(ldrsb
, 01000d0
, ldrsb
, 2, (RR
, ADDR
), ldstv4
, t_ldst
),
8411 tCM(ld
,sh
, 01000f0
, ldrsh
, 2, (RR
, ADDR
), ldstv4
, t_ldst
),
8412 tCM(ld
,sb
, 01000d0
, ldrsb
, 2, (RR
, ADDR
), ldstv4
, t_ldst
),
8415 #define ARM_VARIANT ARM_EXT_V4T|ARM_EXT_V5
8416 /* ARM Architecture 4T. */
8417 /* Note: bx (and blx) are required on V5, even if the processor does
8418 not support Thumb. */
8419 TCE(bx
, 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
8422 #define ARM_VARIANT ARM_EXT_V5 /* ARM Architecture 5T. */
8423 #undef THUMB_VARIANT
8424 #define THUMB_VARIANT ARM_EXT_V5T
8425 /* Note: blx has 2 variants; the .value coded here is for
8426 BLX(2). Only this variant has conditional execution. */
8427 TCE(blx
, 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
8428 TUE(bkpt
, 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
8430 #undef THUMB_VARIANT
8431 #define THUMB_VARIANT ARM_EXT_V6T2
8432 TCE(clz
, 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
8433 TUF(ldc2
, c100000
, fc100000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
8434 TUF(ldc2l
, c500000
, fc500000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
8435 TUF(stc2
, c000000
, fc000000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
8436 TUF(stc2l
, c400000
, fc400000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
8437 TUF(cdp2
, e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
8438 TUF(mcr2
, e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
8439 TUF(mrc2
, e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
8442 #define ARM_VARIANT ARM_EXT_V5ExP /* ARM Architecture 5TExP. */
8443 TCE(smlabb
, 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
8444 TCE(smlatb
, 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
8445 TCE(smlabt
, 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
8446 TCE(smlatt
, 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
8448 TCE(smlawb
, 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
8449 TCE(smlawt
, 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
8451 TCE(smlalbb
, 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
8452 TCE(smlaltb
, 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
8453 TCE(smlalbt
, 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
8454 TCE(smlaltt
, 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
8456 TCE(smulbb
, 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8457 TCE(smultb
, 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8458 TCE(smulbt
, 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8459 TCE(smultt
, 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8461 TCE(smulwb
, 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8462 TCE(smulwt
, 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8464 TCE(qadd
, 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
8465 TCE(qdadd
, 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
8466 TCE(qsub
, 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
8467 TCE(qdsub
, 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
8470 #define ARM_VARIANT ARM_EXT_V5E /* ARM Architecture 5TE. */
8471 TUF(pld
, 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
8472 TC3(ldrd
, 00000d0
, e9500000
, 3, (RRnpc
, oRRnpc
, ADDR
), ldrd
, t_ldstd
),
8473 TC3(strd
, 00000f0
, e9400000
, 3, (RRnpc
, oRRnpc
, ADDR
), ldrd
, t_ldstd
),
8475 TCE(mcrr
, c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
8476 TCE(mrrc
, c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
8479 #define ARM_VARIANT ARM_EXT_V5J /* ARM Architecture 5TEJ. */
8480 TCE(bxj
, 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
8483 #define ARM_VARIANT ARM_EXT_V6 /* ARM V6. */
8484 #undef THUMB_VARIANT
8485 #define THUMB_VARIANT ARM_EXT_V6
8486 TUF(cpsie
, 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
8487 TUF(cpsid
, 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
8488 tCE(rev
, 6bf0f30
, rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
8489 tCE(rev16
, 6bf0fb0
, rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
8490 tCE(revsh
, 6ff0fb0
, revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
8491 tCE(sxth
, 6bf0070
, sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
8492 tCE(uxth
, 6ff0070
, uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
8493 tCE(sxtb
, 6af0070
, sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
8494 tCE(uxtb
, 6ef0070
, uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
8495 TUF(setend
, 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
8497 #undef THUMB_VARIANT
8498 #define THUMB_VARIANT ARM_EXT_V6T2
8499 TUF(cps
, 1020000, f3af8100
, 1, (I31b
), imm0
, imm0
),
8500 TCE(ldrex
, 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
8501 TUF(mcrr2
, c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
8502 TUF(mrrc2
, c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
8503 TCE(pkhbt
, 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
8504 TCE(pkhtb
, 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
8505 TCE(qadd16
, 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8506 TCE(qadd8
, 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8507 TCE(qaddsubx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8508 TCE(qsub16
, 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8509 TCE(qsub8
, 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8510 TCE(qsubaddx
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8511 TCE(sadd16
, 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8512 TCE(sadd8
, 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8513 TCE(saddsubx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8514 TCE(shadd16
, 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8515 TCE(shadd8
, 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8516 TCE(shaddsubx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8517 TCE(shsub16
, 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8518 TCE(shsub8
, 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8519 TCE(shsubaddx
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8520 TCE(ssub16
, 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8521 TCE(ssub8
, 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8522 TCE(ssubaddx
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8523 TCE(uadd16
, 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8524 TCE(uadd8
, 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8525 TCE(uaddsubx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8526 TCE(uhadd16
, 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8527 TCE(uhadd8
, 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8528 TCE(uhaddsubx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8529 TCE(uhsub16
, 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8530 TCE(uhsub8
, 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8531 TCE(uhsubaddx
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8532 TCE(uqadd16
, 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8533 TCE(uqadd8
, 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8534 TCE(uqaddsubx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8535 TCE(uqsub16
, 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8536 TCE(uqsub8
, 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8537 TCE(uqsubaddx
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8538 TCE(usub16
, 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8539 TCE(usub8
, 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8540 TCE(usubaddx
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8541 TUF(rfeia
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
8542 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
8543 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
8544 TUF(rfedb
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
8545 TUF(rfefd
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
8546 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
8547 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
8548 TUF(rfeed
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
8549 TCE(sxtah
, 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
8550 TCE(sxtab16
, 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
8551 TCE(sxtab
, 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
8552 TCE(sxtb16
, 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
8553 TCE(uxtah
, 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
8554 TCE(uxtab16
, 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
8555 TCE(uxtab
, 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
8556 TCE(uxtb16
, 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
8557 TCE(sel
, 68000b0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8558 TCE(smlad
, 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
8559 TCE(smladx
, 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
8560 TCE(smlald
, 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
8561 TCE(smlaldx
, 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
8562 TCE(smlsd
, 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
8563 TCE(smlsdx
, 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
8564 TCE(smlsld
, 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
8565 TCE(smlsldx
, 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
8566 TCE(smmla
, 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
8567 TCE(smmlar
, 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
8568 TCE(smmls
, 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
8569 TCE(smmlsr
, 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
8570 TCE(smmul
, 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8571 TCE(smmulr
, 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8572 TCE(smuad
, 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8573 TCE(smuadx
, 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8574 TCE(smusd
, 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8575 TCE(smusdx
, 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8576 TUF(srsia
, 8cd0500
, e980c000
, 1, (I31w
), srs
, srs
),
8577 UF(srsib
, 9cd0500
, 1, (I31w
), srs
),
8578 UF(srsda
, 84d0500
, 1, (I31w
), srs
),
8579 TUF(srsdb
, 94d0500
, e800c000
, 1, (I31w
), srs
, srs
),
8580 TCE(ssat
, 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
8581 TCE(ssat16
, 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
8582 TCE(strex
, 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
8583 TCE(umaal
, 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
8584 TCE(usad8
, 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8585 TCE(usada8
, 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
8586 TCE(usat
, 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
8587 TCE(usat16
, 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
8590 #define ARM_VARIANT ARM_EXT_V6K
8591 #undef THUMB_VARIANT
8592 #define THUMB_VARIANT ARM_EXT_V6K
8593 tCE(yield
, 320f001
, yield
, 0, (), noargs
, t_hint
),
8594 tCE(wfe
, 320f002
, wfe
, 0, (), noargs
, t_hint
),
8595 tCE(wfi
, 320f003
, wfi
, 0, (), noargs
, t_hint
),
8596 tCE(sev
, 320f004
, sev
, 0, (), noargs
, t_hint
),
8598 #undef THUMB_VARIANT
8599 #define THUMB_VARIANT ARM_EXT_V6T2
8600 TCE(ldrexb
, 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
8601 TCE(ldrexh
, 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
8602 TCE(ldrexd
, 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
8603 TCE(strexb
, 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
8604 TCE(strexh
, 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
8605 TCE(strexd
, 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
8606 TUF(clrex
, 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
8609 #define ARM_VARIANT ARM_EXT_V6Z
8610 TCE(smi
, 1600070, f7f08000
, 1, (EXPi
), smi
, t_smi
),
8613 #define ARM_VARIANT ARM_EXT_V6T2
8614 TCE(bfc
, 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
8615 TCE(bfi
, 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
8616 TCE(sbfx
, 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
8617 TCE(ubfx
, 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
8619 TCE(mls
, 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
8620 TCE(movw
, 3000000, f2400000
, 2, (RRnpc
, Iffff
), mov16
, t_mov16
),
8621 TCE(movt
, 3400000, f2c00000
, 2, (RRnpc
, Iffff
), mov16
, t_mov16
),
8622 TCE(rbit
, 3ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
8624 TC3(ldrht
, 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
8625 TC3(ldrsht
, 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
8626 TC3(ldrsbt
, 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
8627 TC3(strht
, 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
8629 UT(cbnz
, b900
, 2, (RR
, EXP
), t_czb
),
8630 UT(cbz
, b100
, 2, (RR
, EXP
), t_czb
),
8631 /* ARM does not really have an IT instruction. */
8632 TUE(it
, 0, bf08
, 1, (COND
), it
, t_it
),
8633 TUE(itt
, 0, bf0c
, 1, (COND
), it
, t_it
),
8634 TUE(ite
, 0, bf04
, 1, (COND
), it
, t_it
),
8635 TUE(ittt
, 0, bf0e
, 1, (COND
), it
, t_it
),
8636 TUE(itet
, 0, bf06
, 1, (COND
), it
, t_it
),
8637 TUE(itte
, 0, bf0a
, 1, (COND
), it
, t_it
),
8638 TUE(itee
, 0, bf02
, 1, (COND
), it
, t_it
),
8639 TUE(itttt
, 0, bf0f
, 1, (COND
), it
, t_it
),
8640 TUE(itett
, 0, bf07
, 1, (COND
), it
, t_it
),
8641 TUE(ittet
, 0, bf0b
, 1, (COND
), it
, t_it
),
8642 TUE(iteet
, 0, bf03
, 1, (COND
), it
, t_it
),
8643 TUE(ittte
, 0, bf0d
, 1, (COND
), it
, t_it
),
8644 TUE(itete
, 0, bf05
, 1, (COND
), it
, t_it
),
8645 TUE(ittee
, 0, bf09
, 1, (COND
), it
, t_it
),
8646 TUE(iteee
, 0, bf01
, 1, (COND
), it
, t_it
),
8648 /* Thumb2 only instructions. */
8650 #define ARM_VARIANT 0
8652 TCE(addw
, 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
8653 TCE(subw
, 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
8654 TCE(tbb
, 0, e8d0f000
, 1, (TB
), 0, t_tb
),
8655 TCE(tbh
, 0, e8d0f010
, 1, (TB
), 0, t_tb
),
8658 #define ARM_VARIANT FPU_FPA_EXT_V1 /* Core FPA instruction set (V1). */
8659 CE(wfs
, e200110
, 1, (RR
), rd
),
8660 CE(rfs
, e300110
, 1, (RR
), rd
),
8661 CE(wfc
, e400110
, 1, (RR
), rd
),
8662 CE(rfc
, e500110
, 1, (RR
), rd
),
8664 C3(ldfs
, c100100
, 2, (RF
, ADDR
), rd_cpaddr
),
8665 C3(ldfd
, c108100
, 2, (RF
, ADDR
), rd_cpaddr
),
8666 C3(ldfe
, c500100
, 2, (RF
, ADDR
), rd_cpaddr
),
8667 C3(ldfp
, c508100
, 2, (RF
, ADDR
), rd_cpaddr
),
8669 C3(stfs
, c000100
, 2, (RF
, ADDR
), rd_cpaddr
),
8670 C3(stfd
, c008100
, 2, (RF
, ADDR
), rd_cpaddr
),
8671 C3(stfe
, c400100
, 2, (RF
, ADDR
), rd_cpaddr
),
8672 C3(stfp
, c408100
, 2, (RF
, ADDR
), rd_cpaddr
),
8674 C3(mvfs
, e008100
, 2, (RF
, RF_IF
), rd_rm
),
8675 C3(mvfsp
, e008120
, 2, (RF
, RF_IF
), rd_rm
),
8676 C3(mvfsm
, e008140
, 2, (RF
, RF_IF
), rd_rm
),
8677 C3(mvfsz
, e008160
, 2, (RF
, RF_IF
), rd_rm
),
8678 C3(mvfd
, e008180
, 2, (RF
, RF_IF
), rd_rm
),
8679 C3(mvfdp
, e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
8680 C3(mvfdm
, e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
8681 C3(mvfdz
, e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
8682 C3(mvfe
, e088100
, 2, (RF
, RF_IF
), rd_rm
),
8683 C3(mvfep
, e088120
, 2, (RF
, RF_IF
), rd_rm
),
8684 C3(mvfem
, e088140
, 2, (RF
, RF_IF
), rd_rm
),
8685 C3(mvfez
, e088160
, 2, (RF
, RF_IF
), rd_rm
),
8687 C3(mnfs
, e108100
, 2, (RF
, RF_IF
), rd_rm
),
8688 C3(mnfsp
, e108120
, 2, (RF
, RF_IF
), rd_rm
),
8689 C3(mnfsm
, e108140
, 2, (RF
, RF_IF
), rd_rm
),
8690 C3(mnfsz
, e108160
, 2, (RF
, RF_IF
), rd_rm
),
8691 C3(mnfd
, e108180
, 2, (RF
, RF_IF
), rd_rm
),
8692 C3(mnfdp
, e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
8693 C3(mnfdm
, e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
8694 C3(mnfdz
, e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
8695 C3(mnfe
, e188100
, 2, (RF
, RF_IF
), rd_rm
),
8696 C3(mnfep
, e188120
, 2, (RF
, RF_IF
), rd_rm
),
8697 C3(mnfem
, e188140
, 2, (RF
, RF_IF
), rd_rm
),
8698 C3(mnfez
, e188160
, 2, (RF
, RF_IF
), rd_rm
),
8700 C3(abss
, e208100
, 2, (RF
, RF_IF
), rd_rm
),
8701 C3(abssp
, e208120
, 2, (RF
, RF_IF
), rd_rm
),
8702 C3(abssm
, e208140
, 2, (RF
, RF_IF
), rd_rm
),
8703 C3(abssz
, e208160
, 2, (RF
, RF_IF
), rd_rm
),
8704 C3(absd
, e208180
, 2, (RF
, RF_IF
), rd_rm
),
8705 C3(absdp
, e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
8706 C3(absdm
, e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
8707 C3(absdz
, e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
8708 C3(abse
, e288100
, 2, (RF
, RF_IF
), rd_rm
),
8709 C3(absep
, e288120
, 2, (RF
, RF_IF
), rd_rm
),
8710 C3(absem
, e288140
, 2, (RF
, RF_IF
), rd_rm
),
8711 C3(absez
, e288160
, 2, (RF
, RF_IF
), rd_rm
),
8713 C3(rnds
, e308100
, 2, (RF
, RF_IF
), rd_rm
),
8714 C3(rndsp
, e308120
, 2, (RF
, RF_IF
), rd_rm
),
8715 C3(rndsm
, e308140
, 2, (RF
, RF_IF
), rd_rm
),
8716 C3(rndsz
, e308160
, 2, (RF
, RF_IF
), rd_rm
),
8717 C3(rndd
, e308180
, 2, (RF
, RF_IF
), rd_rm
),
8718 C3(rnddp
, e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
8719 C3(rnddm
, e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
8720 C3(rnddz
, e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
8721 C3(rnde
, e388100
, 2, (RF
, RF_IF
), rd_rm
),
8722 C3(rndep
, e388120
, 2, (RF
, RF_IF
), rd_rm
),
8723 C3(rndem
, e388140
, 2, (RF
, RF_IF
), rd_rm
),
8724 C3(rndez
, e388160
, 2, (RF
, RF_IF
), rd_rm
),
8726 C3(sqts
, e408100
, 2, (RF
, RF_IF
), rd_rm
),
8727 C3(sqtsp
, e408120
, 2, (RF
, RF_IF
), rd_rm
),
8728 C3(sqtsm
, e408140
, 2, (RF
, RF_IF
), rd_rm
),
8729 C3(sqtsz
, e408160
, 2, (RF
, RF_IF
), rd_rm
),
8730 C3(sqtd
, e408180
, 2, (RF
, RF_IF
), rd_rm
),
8731 C3(sqtdp
, e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
8732 C3(sqtdm
, e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
8733 C3(sqtdz
, e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
8734 C3(sqte
, e488100
, 2, (RF
, RF_IF
), rd_rm
),
8735 C3(sqtep
, e488120
, 2, (RF
, RF_IF
), rd_rm
),
8736 C3(sqtem
, e488140
, 2, (RF
, RF_IF
), rd_rm
),
8737 C3(sqtez
, e488160
, 2, (RF
, RF_IF
), rd_rm
),
8739 C3(logs
, e508100
, 2, (RF
, RF_IF
), rd_rm
),
8740 C3(logsp
, e508120
, 2, (RF
, RF_IF
), rd_rm
),
8741 C3(logsm
, e508140
, 2, (RF
, RF_IF
), rd_rm
),
8742 C3(logsz
, e508160
, 2, (RF
, RF_IF
), rd_rm
),
8743 C3(logd
, e508180
, 2, (RF
, RF_IF
), rd_rm
),
8744 C3(logdp
, e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
8745 C3(logdm
, e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
8746 C3(logdz
, e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
8747 C3(loge
, e588100
, 2, (RF
, RF_IF
), rd_rm
),
8748 C3(logep
, e588120
, 2, (RF
, RF_IF
), rd_rm
),
8749 C3(logem
, e588140
, 2, (RF
, RF_IF
), rd_rm
),
8750 C3(logez
, e588160
, 2, (RF
, RF_IF
), rd_rm
),
8752 C3(lgns
, e608100
, 2, (RF
, RF_IF
), rd_rm
),
8753 C3(lgnsp
, e608120
, 2, (RF
, RF_IF
), rd_rm
),
8754 C3(lgnsm
, e608140
, 2, (RF
, RF_IF
), rd_rm
),
8755 C3(lgnsz
, e608160
, 2, (RF
, RF_IF
), rd_rm
),
8756 C3(lgnd
, e608180
, 2, (RF
, RF_IF
), rd_rm
),
8757 C3(lgndp
, e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
8758 C3(lgndm
, e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
8759 C3(lgndz
, e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
8760 C3(lgne
, e688100
, 2, (RF
, RF_IF
), rd_rm
),
8761 C3(lgnep
, e688120
, 2, (RF
, RF_IF
), rd_rm
),
8762 C3(lgnem
, e688140
, 2, (RF
, RF_IF
), rd_rm
),
8763 C3(lgnez
, e688160
, 2, (RF
, RF_IF
), rd_rm
),
8765 C3(exps
, e708100
, 2, (RF
, RF_IF
), rd_rm
),
8766 C3(expsp
, e708120
, 2, (RF
, RF_IF
), rd_rm
),
8767 C3(expsm
, e708140
, 2, (RF
, RF_IF
), rd_rm
),
8768 C3(expsz
, e708160
, 2, (RF
, RF_IF
), rd_rm
),
8769 C3(expd
, e708180
, 2, (RF
, RF_IF
), rd_rm
),
8770 C3(expdp
, e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
8771 C3(expdm
, e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
8772 C3(expdz
, e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
8773 C3(expe
, e788100
, 2, (RF
, RF_IF
), rd_rm
),
8774 C3(expep
, e788120
, 2, (RF
, RF_IF
), rd_rm
),
8775 C3(expem
, e788140
, 2, (RF
, RF_IF
), rd_rm
),
8776 C3(expdz
, e788160
, 2, (RF
, RF_IF
), rd_rm
),
8778 C3(sins
, e808100
, 2, (RF
, RF_IF
), rd_rm
),
8779 C3(sinsp
, e808120
, 2, (RF
, RF_IF
), rd_rm
),
8780 C3(sinsm
, e808140
, 2, (RF
, RF_IF
), rd_rm
),
8781 C3(sinsz
, e808160
, 2, (RF
, RF_IF
), rd_rm
),
8782 C3(sind
, e808180
, 2, (RF
, RF_IF
), rd_rm
),
8783 C3(sindp
, e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
8784 C3(sindm
, e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
8785 C3(sindz
, e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
8786 C3(sine
, e888100
, 2, (RF
, RF_IF
), rd_rm
),
8787 C3(sinep
, e888120
, 2, (RF
, RF_IF
), rd_rm
),
8788 C3(sinem
, e888140
, 2, (RF
, RF_IF
), rd_rm
),
8789 C3(sinez
, e888160
, 2, (RF
, RF_IF
), rd_rm
),
8791 C3(coss
, e908100
, 2, (RF
, RF_IF
), rd_rm
),
8792 C3(cossp
, e908120
, 2, (RF
, RF_IF
), rd_rm
),
8793 C3(cossm
, e908140
, 2, (RF
, RF_IF
), rd_rm
),
8794 C3(cossz
, e908160
, 2, (RF
, RF_IF
), rd_rm
),
8795 C3(cosd
, e908180
, 2, (RF
, RF_IF
), rd_rm
),
8796 C3(cosdp
, e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
8797 C3(cosdm
, e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
8798 C3(cosdz
, e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
8799 C3(cose
, e988100
, 2, (RF
, RF_IF
), rd_rm
),
8800 C3(cosep
, e988120
, 2, (RF
, RF_IF
), rd_rm
),
8801 C3(cosem
, e988140
, 2, (RF
, RF_IF
), rd_rm
),
8802 C3(cosez
, e988160
, 2, (RF
, RF_IF
), rd_rm
),
8804 C3(tans
, ea08100
, 2, (RF
, RF_IF
), rd_rm
),
8805 C3(tansp
, ea08120
, 2, (RF
, RF_IF
), rd_rm
),
8806 C3(tansm
, ea08140
, 2, (RF
, RF_IF
), rd_rm
),
8807 C3(tansz
, ea08160
, 2, (RF
, RF_IF
), rd_rm
),
8808 C3(tand
, ea08180
, 2, (RF
, RF_IF
), rd_rm
),
8809 C3(tandp
, ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
8810 C3(tandm
, ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
8811 C3(tandz
, ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
8812 C3(tane
, ea88100
, 2, (RF
, RF_IF
), rd_rm
),
8813 C3(tanep
, ea88120
, 2, (RF
, RF_IF
), rd_rm
),
8814 C3(tanem
, ea88140
, 2, (RF
, RF_IF
), rd_rm
),
8815 C3(tanez
, ea88160
, 2, (RF
, RF_IF
), rd_rm
),
8817 C3(asns
, eb08100
, 2, (RF
, RF_IF
), rd_rm
),
8818 C3(asnsp
, eb08120
, 2, (RF
, RF_IF
), rd_rm
),
8819 C3(asnsm
, eb08140
, 2, (RF
, RF_IF
), rd_rm
),
8820 C3(asnsz
, eb08160
, 2, (RF
, RF_IF
), rd_rm
),
8821 C3(asnd
, eb08180
, 2, (RF
, RF_IF
), rd_rm
),
8822 C3(asndp
, eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
8823 C3(asndm
, eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
8824 C3(asndz
, eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
8825 C3(asne
, eb88100
, 2, (RF
, RF_IF
), rd_rm
),
8826 C3(asnep
, eb88120
, 2, (RF
, RF_IF
), rd_rm
),
8827 C3(asnem
, eb88140
, 2, (RF
, RF_IF
), rd_rm
),
8828 C3(asnez
, eb88160
, 2, (RF
, RF_IF
), rd_rm
),
8830 C3(acss
, ec08100
, 2, (RF
, RF_IF
), rd_rm
),
8831 C3(acssp
, ec08120
, 2, (RF
, RF_IF
), rd_rm
),
8832 C3(acssm
, ec08140
, 2, (RF
, RF_IF
), rd_rm
),
8833 C3(acssz
, ec08160
, 2, (RF
, RF_IF
), rd_rm
),
8834 C3(acsd
, ec08180
, 2, (RF
, RF_IF
), rd_rm
),
8835 C3(acsdp
, ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
8836 C3(acsdm
, ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
8837 C3(acsdz
, ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
8838 C3(acse
, ec88100
, 2, (RF
, RF_IF
), rd_rm
),
8839 C3(acsep
, ec88120
, 2, (RF
, RF_IF
), rd_rm
),
8840 C3(acsem
, ec88140
, 2, (RF
, RF_IF
), rd_rm
),
8841 C3(acsez
, ec88160
, 2, (RF
, RF_IF
), rd_rm
),
8843 C3(atns
, ed08100
, 2, (RF
, RF_IF
), rd_rm
),
8844 C3(atnsp
, ed08120
, 2, (RF
, RF_IF
), rd_rm
),
8845 C3(atnsm
, ed08140
, 2, (RF
, RF_IF
), rd_rm
),
8846 C3(atnsz
, ed08160
, 2, (RF
, RF_IF
), rd_rm
),
8847 C3(atnd
, ed08180
, 2, (RF
, RF_IF
), rd_rm
),
8848 C3(atndp
, ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
8849 C3(atndm
, ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
8850 C3(atndz
, ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
8851 C3(atne
, ed88100
, 2, (RF
, RF_IF
), rd_rm
),
8852 C3(atnep
, ed88120
, 2, (RF
, RF_IF
), rd_rm
),
8853 C3(atnem
, ed88140
, 2, (RF
, RF_IF
), rd_rm
),
8854 C3(atnez
, ed88160
, 2, (RF
, RF_IF
), rd_rm
),
8856 C3(urds
, ee08100
, 2, (RF
, RF_IF
), rd_rm
),
8857 C3(urdsp
, ee08120
, 2, (RF
, RF_IF
), rd_rm
),
8858 C3(urdsm
, ee08140
, 2, (RF
, RF_IF
), rd_rm
),
8859 C3(urdsz
, ee08160
, 2, (RF
, RF_IF
), rd_rm
),
8860 C3(urdd
, ee08180
, 2, (RF
, RF_IF
), rd_rm
),
8861 C3(urddp
, ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
8862 C3(urddm
, ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
8863 C3(urddz
, ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
8864 C3(urde
, ee88100
, 2, (RF
, RF_IF
), rd_rm
),
8865 C3(urdep
, ee88120
, 2, (RF
, RF_IF
), rd_rm
),
8866 C3(urdem
, ee88140
, 2, (RF
, RF_IF
), rd_rm
),
8867 C3(urdez
, ee88160
, 2, (RF
, RF_IF
), rd_rm
),
8869 C3(nrms
, ef08100
, 2, (RF
, RF_IF
), rd_rm
),
8870 C3(nrmsp
, ef08120
, 2, (RF
, RF_IF
), rd_rm
),
8871 C3(nrmsm
, ef08140
, 2, (RF
, RF_IF
), rd_rm
),
8872 C3(nrmsz
, ef08160
, 2, (RF
, RF_IF
), rd_rm
),
8873 C3(nrmd
, ef08180
, 2, (RF
, RF_IF
), rd_rm
),
8874 C3(nrmdp
, ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
8875 C3(nrmdm
, ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
8876 C3(nrmdz
, ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
8877 C3(nrme
, ef88100
, 2, (RF
, RF_IF
), rd_rm
),
8878 C3(nrmep
, ef88120
, 2, (RF
, RF_IF
), rd_rm
),
8879 C3(nrmem
, ef88140
, 2, (RF
, RF_IF
), rd_rm
),
8880 C3(nrmez
, ef88160
, 2, (RF
, RF_IF
), rd_rm
),
8882 C3(adfs
, e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8883 C3(adfsp
, e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8884 C3(adfsm
, e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8885 C3(adfsz
, e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8886 C3(adfd
, e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8887 C3(adfdp
, e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8888 C3(adfdm
, e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8889 C3(adfdz
, e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8890 C3(adfe
, e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8891 C3(adfep
, e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8892 C3(adfem
, e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8893 C3(adfez
, e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8895 C3(sufs
, e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8896 C3(sufsp
, e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8897 C3(sufsm
, e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8898 C3(sufsz
, e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8899 C3(sufd
, e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8900 C3(sufdp
, e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8901 C3(sufdm
, e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8902 C3(sufdz
, e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8903 C3(sufe
, e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8904 C3(sufep
, e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8905 C3(sufem
, e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8906 C3(sufez
, e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8908 C3(rsfs
, e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8909 C3(rsfsp
, e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8910 C3(rsfsm
, e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8911 C3(rsfsz
, e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8912 C3(rsfd
, e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8913 C3(rsfdp
, e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8914 C3(rsfdm
, e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8915 C3(rsfdz
, e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8916 C3(rsfe
, e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8917 C3(rsfep
, e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8918 C3(rsfem
, e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8919 C3(rsfez
, e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8921 C3(mufs
, e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8922 C3(mufsp
, e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8923 C3(mufsm
, e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8924 C3(mufsz
, e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8925 C3(mufd
, e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8926 C3(mufdp
, e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8927 C3(mufdm
, e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8928 C3(mufdz
, e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8929 C3(mufe
, e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8930 C3(mufep
, e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8931 C3(mufem
, e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8932 C3(mufez
, e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8934 C3(dvfs
, e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8935 C3(dvfsp
, e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8936 C3(dvfsm
, e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8937 C3(dvfsz
, e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8938 C3(dvfd
, e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8939 C3(dvfdp
, e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8940 C3(dvfdm
, e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8941 C3(dvfdz
, e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8942 C3(dvfe
, e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8943 C3(dvfep
, e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8944 C3(dvfem
, e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8945 C3(dvfez
, e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8947 C3(rdfs
, e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8948 C3(rdfsp
, e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8949 C3(rdfsm
, e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8950 C3(rdfsz
, e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8951 C3(rdfd
, e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8952 C3(rdfdp
, e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8953 C3(rdfdm
, e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8954 C3(rdfdz
, e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8955 C3(rdfe
, e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8956 C3(rdfep
, e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8957 C3(rdfem
, e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8958 C3(rdfez
, e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8960 C3(pows
, e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8961 C3(powsp
, e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8962 C3(powsm
, e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8963 C3(powsz
, e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8964 C3(powd
, e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8965 C3(powdp
, e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8966 C3(powdm
, e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8967 C3(powdz
, e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8968 C3(powe
, e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8969 C3(powep
, e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8970 C3(powem
, e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8971 C3(powez
, e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8973 C3(rpws
, e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8974 C3(rpwsp
, e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8975 C3(rpwsm
, e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8976 C3(rpwsz
, e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8977 C3(rpwd
, e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8978 C3(rpwdp
, e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8979 C3(rpwdm
, e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8980 C3(rpwdz
, e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8981 C3(rpwe
, e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8982 C3(rpwep
, e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8983 C3(rpwem
, e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8984 C3(rpwez
, e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8986 C3(rmfs
, e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8987 C3(rmfsp
, e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8988 C3(rmfsm
, e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8989 C3(rmfsz
, e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8990 C3(rmfd
, e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8991 C3(rmfdp
, e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8992 C3(rmfdm
, e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8993 C3(rmfdz
, e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8994 C3(rmfe
, e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8995 C3(rmfep
, e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8996 C3(rmfem
, e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8997 C3(rmfez
, e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8999 C3(fmls
, e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9000 C3(fmlsp
, e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9001 C3(fmlsm
, e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9002 C3(fmlsz
, e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9003 C3(fmld
, e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9004 C3(fmldp
, e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9005 C3(fmldm
, e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9006 C3(fmldz
, e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9007 C3(fmle
, e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9008 C3(fmlep
, e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9009 C3(fmlem
, e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9010 C3(fmlez
, e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9012 C3(fdvs
, ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9013 C3(fdvsp
, ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9014 C3(fdvsm
, ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9015 C3(fdvsz
, ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9016 C3(fdvd
, ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9017 C3(fdvdp
, ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9018 C3(fdvdm
, ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9019 C3(fdvdz
, ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9020 C3(fdve
, ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9021 C3(fdvep
, ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9022 C3(fdvem
, ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9023 C3(fdvez
, ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9025 C3(frds
, eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9026 C3(frdsp
, eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9027 C3(frdsm
, eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9028 C3(frdsz
, eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9029 C3(frdd
, eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9030 C3(frddp
, eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9031 C3(frddm
, eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9032 C3(frddz
, eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9033 C3(frde
, eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9034 C3(frdep
, eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9035 C3(frdem
, eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9036 C3(frdez
, eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9038 C3(pols
, ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9039 C3(polsp
, ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9040 C3(polsm
, ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9041 C3(polsz
, ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9042 C3(pold
, ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9043 C3(poldp
, ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9044 C3(poldm
, ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9045 C3(poldz
, ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9046 C3(pole
, ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9047 C3(polep
, ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9048 C3(polem
, ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9049 C3(polez
, ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9051 CE(cmf
, e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
9052 C3E(cmfe
, ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
9053 CE(cnf
, eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
9054 C3E(cnfe
, ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
9056 C3(flts
, e000110
, 2, (RF
, RR
), rn_rd
),
9057 C3(fltsp
, e000130
, 2, (RF
, RR
), rn_rd
),
9058 C3(fltsm
, e000150
, 2, (RF
, RR
), rn_rd
),
9059 C3(fltsz
, e000170
, 2, (RF
, RR
), rn_rd
),
9060 C3(fltd
, e000190
, 2, (RF
, RR
), rn_rd
),
9061 C3(fltdp
, e0001b0
, 2, (RF
, RR
), rn_rd
),
9062 C3(fltdm
, e0001d0
, 2, (RF
, RR
), rn_rd
),
9063 C3(fltdz
, e0001f0
, 2, (RF
, RR
), rn_rd
),
9064 C3(flte
, e080110
, 2, (RF
, RR
), rn_rd
),
9065 C3(fltep
, e080130
, 2, (RF
, RR
), rn_rd
),
9066 C3(fltem
, e080150
, 2, (RF
, RR
), rn_rd
),
9067 C3(fltez
, e080170
, 2, (RF
, RR
), rn_rd
),
9069 /* The implementation of the FIX instruction is broken on some
9070 assemblers, in that it accepts a precision specifier as well as a
9071 rounding specifier, despite the fact that this is meaningless.
9072 To be more compatible, we accept it as well, though of course it
9073 does not set any bits. */
9074 CE(fix
, e100110
, 2, (RR
, RF
), rd_rm
),
9075 C3(fixp
, e100130
, 2, (RR
, RF
), rd_rm
),
9076 C3(fixm
, e100150
, 2, (RR
, RF
), rd_rm
),
9077 C3(fixz
, e100170
, 2, (RR
, RF
), rd_rm
),
9078 C3(fixsp
, e100130
, 2, (RR
, RF
), rd_rm
),
9079 C3(fixsm
, e100150
, 2, (RR
, RF
), rd_rm
),
9080 C3(fixsz
, e100170
, 2, (RR
, RF
), rd_rm
),
9081 C3(fixdp
, e100130
, 2, (RR
, RF
), rd_rm
),
9082 C3(fixdm
, e100150
, 2, (RR
, RF
), rd_rm
),
9083 C3(fixdz
, e100170
, 2, (RR
, RF
), rd_rm
),
9084 C3(fixep
, e100130
, 2, (RR
, RF
), rd_rm
),
9085 C3(fixem
, e100150
, 2, (RR
, RF
), rd_rm
),
9086 C3(fixez
, e100170
, 2, (RR
, RF
), rd_rm
),
9088 /* Instructions that were new with the real FPA, call them V2. */
9090 #define ARM_VARIANT FPU_FPA_EXT_V2
9091 CE(lfm
, c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
9092 C3(lfmfd
, c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
9093 C3(lfmea
, d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
9094 CE(sfm
, c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
9095 C3(sfmfd
, d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
9096 C3(sfmea
, c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
9099 #define ARM_VARIANT FPU_VFP_EXT_V1xD /* VFP V1xD (single precision). */
9100 /* Moves and type conversions. */
9101 CE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9102 CE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
9103 CE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
9104 CE(fmstat
, ef1fa10
, 0, (), noargs
),
9105 CE(fsitos
, eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9106 CE(fuitos
, eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9107 CE(ftosis
, ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9108 CE(ftosizs
, ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9109 CE(ftouis
, ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9110 CE(ftouizs
, ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9111 CE(fmrx
, ef00a10
, 2, (RR
, RVC
), rd_rn
),
9112 CE(fmxr
, ee00a10
, 2, (RVC
, RR
), rn_rd
),
9114 /* Memory operations. */
9115 CE(flds
, d100a00
, 2, (RVS
, ADDR
), vfp_sp_ldst
),
9116 CE(fsts
, d000a00
, 2, (RVS
, ADDR
), vfp_sp_ldst
),
9117 CE(fldmias
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
9118 CE(fldmfds
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
9119 CE(fldmdbs
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
9120 CE(fldmeas
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
9121 CE(fldmiax
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
9122 CE(fldmfdx
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
9123 CE(fldmdbx
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
9124 CE(fldmeax
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
9125 CE(fstmias
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
9126 CE(fstmeas
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
9127 CE(fstmdbs
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
9128 CE(fstmfds
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
9129 CE(fstmiax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
9130 CE(fstmeax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
9131 CE(fstmdbx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
9132 CE(fstmfdx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
9134 /* Monadic operations. */
9135 CE(fabss
, eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9136 CE(fnegs
, eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9137 CE(fsqrts
, eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9139 /* Dyadic operations. */
9140 CE(fadds
, e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
9141 CE(fsubs
, e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
9142 CE(fmuls
, e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
9143 CE(fdivs
, e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
9144 CE(fmacs
, e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
9145 CE(fmscs
, e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
9146 CE(fnmuls
, e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
9147 CE(fnmacs
, e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
9148 CE(fnmscs
, e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
9151 CE(fcmps
, eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9152 CE(fcmpzs
, eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
9153 CE(fcmpes
, eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9154 CE(fcmpezs
, eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
9157 #define ARM_VARIANT FPU_VFP_EXT_V1 /* VFP V1 (Double precision). */
9158 /* Moves and type conversions. */
9159 CE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), rd_rm
),
9160 CE(fcvtds
, eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
9161 CE(fcvtsd
, eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
9162 CE(fmdhr
, e200b10
, 2, (RVD
, RR
), rn_rd
),
9163 CE(fmdlr
, e000b10
, 2, (RVD
, RR
), rn_rd
),
9164 CE(fmrdh
, e300b10
, 2, (RR
, RVD
), rd_rn
),
9165 CE(fmrdl
, e100b10
, 2, (RR
, RVD
), rd_rn
),
9166 CE(fsitod
, eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
9167 CE(fuitod
, eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
9168 CE(ftosid
, ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
9169 CE(ftosizd
, ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
9170 CE(ftouid
, ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
9171 CE(ftouizd
, ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
9173 /* Memory operations. */
9174 CE(fldd
, d100b00
, 2, (RVD
, ADDR
), vfp_dp_ldst
),
9175 CE(fstd
, d000b00
, 2, (RVD
, ADDR
), vfp_dp_ldst
),
9176 CE(fldmiad
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
9177 CE(fldmfdd
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
9178 CE(fldmdbd
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
9179 CE(fldmead
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
9180 CE(fstmiad
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
9181 CE(fstmead
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
9182 CE(fstmdbd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
9183 CE(fstmfdd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
9185 /* Monadic operations. */
9186 CE(fabsd
, eb00bc0
, 2, (RVD
, RVD
), rd_rm
),
9187 CE(fnegd
, eb10b40
, 2, (RVD
, RVD
), rd_rm
),
9188 CE(fsqrtd
, eb10bc0
, 2, (RVD
, RVD
), rd_rm
),
9190 /* Dyadic operations. */
9191 CE(faddd
, e300b00
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9192 CE(fsubd
, e300b40
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9193 CE(fmuld
, e200b00
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9194 CE(fdivd
, e800b00
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9195 CE(fmacd
, e000b00
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9196 CE(fmscd
, e100b00
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9197 CE(fnmuld
, e200b40
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9198 CE(fnmacd
, e000b40
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9199 CE(fnmscd
, e100b40
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9202 CE(fcmpd
, eb40b40
, 2, (RVD
, RVD
), rd_rm
),
9203 CE(fcmpzd
, eb50b40
, 1, (RVD
), rd
),
9204 CE(fcmped
, eb40bc0
, 2, (RVD
, RVD
), rd_rm
),
9205 CE(fcmpezd
, eb50bc0
, 1, (RVD
), rd
),
9208 #define ARM_VARIANT FPU_VFP_EXT_V2
9209 CE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
9210 CE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
9211 CE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), rm_rd_rn
),
9212 CE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), rd_rn_rm
),
9215 #define ARM_VARIANT ARM_CEXT_XSCALE /* Intel XScale extensions. */
9216 CE(mia
, e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
9217 CE(miaph
, e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
9218 CE(miabb
, e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
9219 CE(miabt
, e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
9220 CE(miatb
, e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
9221 CE(miatt
, e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
9222 CE(mar
, c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
9223 CE(mra
, c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
9226 #define ARM_VARIANT ARM_CEXT_IWMMXT /* Intel Wireless MMX technology. */
9227 CE(tandcb
, e13f130
, 1, (RR
), iwmmxt_tandorc
),
9228 CE(tandch
, e53f130
, 1, (RR
), iwmmxt_tandorc
),
9229 CE(tandcw
, e93f130
, 1, (RR
), iwmmxt_tandorc
),
9230 CE(tbcstb
, e400010
, 2, (RIWR
, RR
), rn_rd
),
9231 CE(tbcsth
, e400050
, 2, (RIWR
, RR
), rn_rd
),
9232 CE(tbcstw
, e400090
, 2, (RIWR
, RR
), rn_rd
),
9233 CE(textrcb
, e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
9234 CE(textrch
, e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
9235 CE(textrcw
, e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
9236 CE(textrmub
, e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
9237 CE(textrmuh
, e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
9238 CE(textrmuw
, e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
9239 CE(textrmsb
, e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
9240 CE(textrmsh
, e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
9241 CE(textrmsw
, e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
9242 CE(tinsrb
, e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
9243 CE(tinsrh
, e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
9244 CE(tinsrw
, e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
9245 CE(tmcr
, e000110
, 2, (RIWC
, RR
), rn_rd
),
9246 CE(tmcrr
, c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
9247 CE(tmia
, e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
9248 CE(tmiaph
, e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
9249 CE(tmiabb
, e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
9250 CE(tmiabt
, e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
9251 CE(tmiatb
, e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
9252 CE(tmiatt
, e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
9253 CE(tmovmskb
, e100030
, 2, (RR
, RIWR
), rd_rn
),
9254 CE(tmovmskh
, e500030
, 2, (RR
, RIWR
), rd_rn
),
9255 CE(tmovmskw
, e900030
, 2, (RR
, RIWR
), rd_rn
),
9256 CE(tmrc
, e100110
, 2, (RR
, RIWC
), rd_rn
),
9257 CE(tmrrc
, c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
9258 CE(torcb
, e13f150
, 1, (RR
), iwmmxt_tandorc
),
9259 CE(torch
, e53f150
, 1, (RR
), iwmmxt_tandorc
),
9260 CE(torcw
, e93f150
, 1, (RR
), iwmmxt_tandorc
),
9261 CE(waccb
, e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
9262 CE(wacch
, e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
9263 CE(waccw
, e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
9264 CE(waddbss
, e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9265 CE(waddb
, e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9266 CE(waddbus
, e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9267 CE(waddhss
, e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9268 CE(waddh
, e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9269 CE(waddhus
, e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9270 CE(waddwss
, eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9271 CE(waddw
, e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9272 CE(waddwus
, e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9273 CE(waligni
, e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
9274 CE(walignr0
, e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9275 CE(walignr1
, e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9276 CE(walignr2
, ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9277 CE(walignr3
, eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9278 CE(wand
, e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9279 CE(wandn
, e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9280 CE(wavg2b
, e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9281 CE(wavg2br
, e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9282 CE(wavg2h
, ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9283 CE(wavg2hr
, ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9284 CE(wcmpeqb
, e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9285 CE(wcmpeqh
, e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9286 CE(wcmpeqw
, e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9287 CE(wcmpgtub
, e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9288 CE(wcmpgtuh
, e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9289 CE(wcmpgtuw
, e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9290 CE(wcmpgtsb
, e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9291 CE(wcmpgtsh
, e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9292 CE(wcmpgtsw
, eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9293 CE(wldrb
, c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
9294 CE(wldrh
, c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
9295 CE(wldrw
, c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
9296 CE(wldrd
, c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
9297 CE(wmacs
, e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9298 CE(wmacsz
, e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9299 CE(wmacu
, e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9300 CE(wmacuz
, e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9301 CE(wmadds
, ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9302 CE(wmaddu
, e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9303 CE(wmaxsb
, e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9304 CE(wmaxsh
, e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9305 CE(wmaxsw
, ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9306 CE(wmaxub
, e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9307 CE(wmaxuh
, e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9308 CE(wmaxuw
, e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9309 CE(wminsb
, e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9310 CE(wminsh
, e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9311 CE(wminsw
, eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9312 CE(wminub
, e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9313 CE(wminuh
, e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9314 CE(wminuw
, e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9315 CE(wmov
, e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
9316 CE(wmulsm
, e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9317 CE(wmulsl
, e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9318 CE(wmulum
, e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9319 CE(wmulul
, e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9320 CE(wor
, e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9321 CE(wpackhss
, e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9322 CE(wpackhus
, e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9323 CE(wpackwss
, eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9324 CE(wpackwus
, e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9325 CE(wpackdss
, ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9326 CE(wpackdus
, ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9327 CE(wrorh
, e700040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9328 CE(wrorhg
, e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9329 CE(wrorw
, eb00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9330 CE(wrorwg
, eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9331 CE(wrord
, ef00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9332 CE(wrordg
, ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9333 CE(wsadb
, e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9334 CE(wsadbz
, e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9335 CE(wsadh
, e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9336 CE(wsadhz
, e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9337 CE(wshufh
, e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
9338 CE(wsllh
, e500040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9339 CE(wsllhg
, e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9340 CE(wsllw
, e900040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9341 CE(wsllwg
, e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9342 CE(wslld
, ed00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9343 CE(wslldg
, ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9344 CE(wsrah
, e400040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9345 CE(wsrahg
, e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9346 CE(wsraw
, e800040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9347 CE(wsrawg
, e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9348 CE(wsrad
, ec00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9349 CE(wsradg
, ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9350 CE(wsrlh
, e600040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9351 CE(wsrlhg
, e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9352 CE(wsrlw
, ea00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9353 CE(wsrlwg
, ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9354 CE(wsrld
, ee00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9355 CE(wsrldg
, ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9356 CE(wstrb
, c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
9357 CE(wstrh
, c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
9358 CE(wstrw
, c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
9359 CE(wstrd
, c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
9360 CE(wsubbss
, e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9361 CE(wsubb
, e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9362 CE(wsubbus
, e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9363 CE(wsubhss
, e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9364 CE(wsubh
, e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9365 CE(wsubhus
, e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9366 CE(wsubwss
, eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9367 CE(wsubw
, e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9368 CE(wsubwus
, e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9369 CE(wunpckehub
,e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
9370 CE(wunpckehuh
,e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
9371 CE(wunpckehuw
,e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
9372 CE(wunpckehsb
,e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
9373 CE(wunpckehsh
,e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
9374 CE(wunpckehsw
,ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
9375 CE(wunpckihb
, e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9376 CE(wunpckihh
, e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9377 CE(wunpckihw
, e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9378 CE(wunpckelub
,e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
9379 CE(wunpckeluh
,e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
9380 CE(wunpckeluw
,e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
9381 CE(wunpckelsb
,e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
9382 CE(wunpckelsh
,e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
9383 CE(wunpckelsw
,ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
9384 CE(wunpckilb
, e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9385 CE(wunpckilh
, e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9386 CE(wunpckilw
, e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9387 CE(wxor
, e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9388 CE(wzero
, e300000
, 1, (RIWR
), iwmmxt_wzero
),
9391 #define ARM_VARIANT ARM_CEXT_MAVERICK /* Cirrus Maverick instructions. */
9392 CE(cfldrs
, c100400
, 2, (RMF
, ADDR
), rd_cpaddr
),
9393 CE(cfldrd
, c500400
, 2, (RMD
, ADDR
), rd_cpaddr
),
9394 CE(cfldr32
, c100500
, 2, (RMFX
, ADDR
), rd_cpaddr
),
9395 CE(cfldr64
, c500500
, 2, (RMDX
, ADDR
), rd_cpaddr
),
9396 CE(cfstrs
, c000400
, 2, (RMF
, ADDR
), rd_cpaddr
),
9397 CE(cfstrd
, c400400
, 2, (RMD
, ADDR
), rd_cpaddr
),
9398 CE(cfstr32
, c000500
, 2, (RMFX
, ADDR
), rd_cpaddr
),
9399 CE(cfstr64
, c400500
, 2, (RMDX
, ADDR
), rd_cpaddr
),
9400 CE(cfmvsr
, e000450
, 2, (RMF
, RR
), rn_rd
),
9401 CE(cfmvrs
, e100450
, 2, (RR
, RMF
), rd_rn
),
9402 CE(cfmvdlr
, e000410
, 2, (RMD
, RR
), rn_rd
),
9403 CE(cfmvrdl
, e100410
, 2, (RR
, RMD
), rd_rn
),
9404 CE(cfmvdhr
, e000430
, 2, (RMD
, RR
), rn_rd
),
9405 CE(cfmvrdh
, e100430
, 2, (RR
, RMD
), rd_rn
),
9406 CE(cfmv64lr
, e000510
, 2, (RMDX
, RR
), rn_rd
),
9407 CE(cfmvr64l
, e100510
, 2, (RR
, RMDX
), rd_rn
),
9408 CE(cfmv64hr
, e000530
, 2, (RMDX
, RR
), rn_rd
),
9409 CE(cfmvr64h
, e100530
, 2, (RR
, RMDX
), rd_rn
),
9410 CE(cfmval32
, e200440
, 2, (RMAX
, RMFX
), rd_rn
),
9411 CE(cfmv32al
, e100440
, 2, (RMFX
, RMAX
), rd_rn
),
9412 CE(cfmvam32
, e200460
, 2, (RMAX
, RMFX
), rd_rn
),
9413 CE(cfmv32am
, e100460
, 2, (RMFX
, RMAX
), rd_rn
),
9414 CE(cfmvah32
, e200480
, 2, (RMAX
, RMFX
), rd_rn
),
9415 CE(cfmv32ah
, e100480
, 2, (RMFX
, RMAX
), rd_rn
),
9416 CE(cfmva32
, e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
9417 CE(cfmv32a
, e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
9418 CE(cfmva64
, e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
9419 CE(cfmv64a
, e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
9420 CE(cfmvsc32
, e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
9421 CE(cfmv32sc
, e1004e0
, 2, (RMDX
, RMDS
), rd
),
9422 CE(cfcpys
, e000400
, 2, (RMF
, RMF
), rd_rn
),
9423 CE(cfcpyd
, e000420
, 2, (RMD
, RMD
), rd_rn
),
9424 CE(cfcvtsd
, e000460
, 2, (RMD
, RMF
), rd_rn
),
9425 CE(cfcvtds
, e000440
, 2, (RMF
, RMD
), rd_rn
),
9426 CE(cfcvt32s
, e000480
, 2, (RMF
, RMFX
), rd_rn
),
9427 CE(cfcvt32d
, e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
9428 CE(cfcvt64s
, e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
9429 CE(cfcvt64d
, e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
9430 CE(cfcvts32
, e100580
, 2, (RMFX
, RMF
), rd_rn
),
9431 CE(cfcvtd32
, e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
9432 CE(cftruncs32
,e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
9433 CE(cftruncd32
,e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
9434 CE(cfrshl32
, e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
9435 CE(cfrshl64
, e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
9436 CE(cfsh32
, e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
9437 CE(cfsh64
, e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
9438 CE(cfcmps
, e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
9439 CE(cfcmpd
, e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
9440 CE(cfcmp32
, e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
9441 CE(cfcmp64
, e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
9442 CE(cfabss
, e300400
, 2, (RMF
, RMF
), rd_rn
),
9443 CE(cfabsd
, e300420
, 2, (RMD
, RMD
), rd_rn
),
9444 CE(cfnegs
, e300440
, 2, (RMF
, RMF
), rd_rn
),
9445 CE(cfnegd
, e300460
, 2, (RMD
, RMD
), rd_rn
),
9446 CE(cfadds
, e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
9447 CE(cfaddd
, e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
9448 CE(cfsubs
, e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
9449 CE(cfsubd
, e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
9450 CE(cfmuls
, e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
9451 CE(cfmuld
, e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
9452 CE(cfabs32
, e300500
, 2, (RMFX
, RMFX
), rd_rn
),
9453 CE(cfabs64
, e300520
, 2, (RMDX
, RMDX
), rd_rn
),
9454 CE(cfneg32
, e300540
, 2, (RMFX
, RMFX
), rd_rn
),
9455 CE(cfneg64
, e300560
, 2, (RMDX
, RMDX
), rd_rn
),
9456 CE(cfadd32
, e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
9457 CE(cfadd64
, e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
9458 CE(cfsub32
, e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
9459 CE(cfsub64
, e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
9460 CE(cfmul32
, e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
9461 CE(cfmul64
, e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
9462 CE(cfmac32
, e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
9463 CE(cfmsc32
, e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
9464 CE(cfmadd32
, e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
9465 CE(cfmsub32
, e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
9466 CE(cfmadda32
, e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
9467 CE(cfmsuba32
, e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
9470 #undef THUMB_VARIANT
9490 /* MD interface: bits in the object file. */
9492 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
9493 for use in the a.out file, and stores them in the array pointed to by buf.
9494 This knows about the endian-ness of the target machine and does
9495 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
9496 2 (short) and 4 (long) Floating numbers are put out as a series of
9497 LITTLENUMS (shorts, here at least). */
9500 md_number_to_chars (char * buf
, valueT val
, int n
)
9502 if (target_big_endian
)
9503 number_to_chars_bigendian (buf
, val
, n
);
9505 number_to_chars_littleendian (buf
, val
, n
);
9509 md_chars_to_number (char * buf
, int n
)
9512 unsigned char * where
= (unsigned char *) buf
;
9514 if (target_big_endian
)
9519 result
|= (*where
++ & 255);
9527 result
|= (where
[n
] & 255);
9534 /* MD interface: Sections. */
9537 md_estimate_size_before_relax (fragS
* fragP ATTRIBUTE_UNUSED
,
9538 segT segtype ATTRIBUTE_UNUSED
)
9540 as_fatal (_("md_estimate_size_before_relax\n"));
9544 /* Round up a section size to the appropriate boundary. */
9547 md_section_align (segT segment ATTRIBUTE_UNUSED
,
9553 /* Round all sects to multiple of 4. */
9554 return (size
+ 3) & ~3;
9558 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
9559 of an rs_align_code fragment. */
9562 arm_handle_align (fragS
* fragP
)
9564 static char const arm_noop
[4] = { 0x00, 0x00, 0xa0, 0xe1 };
9565 static char const thumb_noop
[2] = { 0xc0, 0x46 };
9566 static char const arm_bigend_noop
[4] = { 0xe1, 0xa0, 0x00, 0x00 };
9567 static char const thumb_bigend_noop
[2] = { 0x46, 0xc0 };
9569 int bytes
, fix
, noop_size
;
9573 if (fragP
->fr_type
!= rs_align_code
)
9576 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
9577 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
9580 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
9581 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
9583 if (fragP
->tc_frag_data
)
9585 if (target_big_endian
)
9586 noop
= thumb_bigend_noop
;
9589 noop_size
= sizeof (thumb_noop
);
9593 if (target_big_endian
)
9594 noop
= arm_bigend_noop
;
9597 noop_size
= sizeof (arm_noop
);
9600 if (bytes
& (noop_size
- 1))
9602 fix
= bytes
& (noop_size
- 1);
9608 while (bytes
>= noop_size
)
9610 memcpy (p
, noop
, noop_size
);
9616 fragP
->fr_fix
+= fix
;
9617 fragP
->fr_var
= noop_size
;
9620 /* Called from md_do_align. Used to create an alignment
9621 frag in a code section. */
9624 arm_frag_align_code (int n
, int max
)
9628 /* We assume that there will never be a requirement
9629 to support alignments greater than 32 bytes. */
9630 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
9631 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
9633 p
= frag_var (rs_align_code
,
9634 MAX_MEM_FOR_RS_ALIGN_CODE
,
9636 (relax_substateT
) max
,
9643 /* Perform target specific initialisation of a frag. */
9646 arm_init_frag (fragS
* fragP
)
9648 /* Record whether this frag is in an ARM or a THUMB area. */
9649 fragP
->tc_frag_data
= thumb_mode
;
9653 /* When we change sections we need to issue a new mapping symbol. */
9656 arm_elf_change_section (void)
9659 segment_info_type
*seginfo
;
9661 /* Link an unlinked unwind index table section to the .text section. */
9662 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
9663 && elf_linked_to_section (now_seg
) == NULL
)
9664 elf_linked_to_section (now_seg
) = text_section
;
9666 if (!SEG_NORMAL (now_seg
))
9669 flags
= bfd_get_section_flags (stdoutput
, now_seg
);
9671 /* We can ignore sections that only contain debug info. */
9672 if ((flags
& SEC_ALLOC
) == 0)
9675 seginfo
= seg_info (now_seg
);
9676 mapstate
= seginfo
->tc_segment_info_data
.mapstate
;
9677 marked_pr_dependency
= seginfo
->tc_segment_info_data
.marked_pr_dependency
;
9681 arm_elf_section_type (const char * str
, size_t len
)
9683 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
9684 return SHT_ARM_EXIDX
;
9689 /* Code to deal with unwinding tables. */
9691 static void add_unwind_adjustsp (offsetT
);
9693 /* Cenerate and deferred unwind frame offset. */
9696 flush_pending_unwind (void)
9700 offset
= unwind
.pending_offset
;
9701 unwind
.pending_offset
= 0;
9703 add_unwind_adjustsp (offset
);
9706 /* Add an opcode to this list for this function. Two-byte opcodes should
9707 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
9711 add_unwind_opcode (valueT op
, int length
)
9713 /* Add any deferred stack adjustment. */
9714 if (unwind
.pending_offset
)
9715 flush_pending_unwind ();
9717 unwind
.sp_restored
= 0;
9719 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
9721 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
9723 unwind
.opcodes
= xrealloc (unwind
.opcodes
,
9724 unwind
.opcode_alloc
);
9726 unwind
.opcodes
= xmalloc (unwind
.opcode_alloc
);
9731 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
9733 unwind
.opcode_count
++;
9737 /* Add unwind opcodes to adjust the stack pointer. */
9740 add_unwind_adjustsp (offsetT offset
)
9746 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
9751 /* Long form: 0xb2, uleb128. */
9752 /* This might not fit in a word so add the individual bytes,
9753 remembering the list is built in reverse order. */
9754 o
= (valueT
) ((offset
- 0x204) >> 2);
9756 add_unwind_opcode (0, 1);
9758 /* Calculate the uleb128 encoding of the offset. */
9762 bytes
[n
] = o
& 0x7f;
9770 add_unwind_opcode (bytes
[n
- 1], 1);
9771 add_unwind_opcode (0xb2, 1);
9773 else if (offset
> 0x100)
9775 /* Two short opcodes. */
9776 add_unwind_opcode (0x3f, 1);
9777 op
= (offset
- 0x104) >> 2;
9778 add_unwind_opcode (op
, 1);
9780 else if (offset
> 0)
9783 op
= (offset
- 4) >> 2;
9784 add_unwind_opcode (op
, 1);
9786 else if (offset
< 0)
9789 while (offset
> 0x100)
9791 add_unwind_opcode (0x7f, 1);
9794 op
= ((offset
- 4) >> 2) | 0x40;
9795 add_unwind_opcode (op
, 1);
9799 /* Finish the list of unwind opcodes for this function. */
9801 finish_unwind_opcodes (void)
9807 /* Adjust sp as neccessary. */
9808 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
9809 flush_pending_unwind ();
9811 /* After restoring sp from the frame pointer. */
9812 op
= 0x90 | unwind
.fp_reg
;
9813 add_unwind_opcode (op
, 1);
9816 flush_pending_unwind ();
9820 /* Start an exception table entry. If idx is nonzero this is an index table
9824 start_unwind_section (const segT text_seg
, int idx
)
9826 const char * text_name
;
9827 const char * prefix
;
9828 const char * prefix_once
;
9829 const char * group_name
;
9833 size_t sec_name_len
;
9840 prefix
= ELF_STRING_ARM_unwind
;
9841 prefix_once
= ELF_STRING_ARM_unwind_once
;
9842 type
= SHT_ARM_EXIDX
;
9846 prefix
= ELF_STRING_ARM_unwind_info
;
9847 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
9848 type
= SHT_PROGBITS
;
9851 text_name
= segment_name (text_seg
);
9852 if (streq (text_name
, ".text"))
9855 if (strncmp (text_name
, ".gnu.linkonce.t.",
9856 strlen (".gnu.linkonce.t.")) == 0)
9858 prefix
= prefix_once
;
9859 text_name
+= strlen (".gnu.linkonce.t.");
9862 prefix_len
= strlen (prefix
);
9863 text_len
= strlen (text_name
);
9864 sec_name_len
= prefix_len
+ text_len
;
9865 sec_name
= xmalloc (sec_name_len
+ 1);
9866 memcpy (sec_name
, prefix
, prefix_len
);
9867 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
9868 sec_name
[prefix_len
+ text_len
] = '\0';
9874 /* Handle COMDAT group. */
9875 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
9877 group_name
= elf_group_name (text_seg
);
9878 if (group_name
== NULL
)
9880 as_bad ("Group section `%s' has no group signature",
9881 segment_name (text_seg
));
9882 ignore_rest_of_line ();
9889 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
9891 /* Set the setion link for index tables. */
9893 elf_linked_to_section (now_seg
) = text_seg
;
9897 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
9898 personality routine data. Returns zero, or the index table value for
9899 and inline entry. */
9902 create_unwind_entry (int have_data
)
9907 /* The current word of data. */
9909 /* The number of bytes left in this word. */
9912 finish_unwind_opcodes ();
9914 /* Remember the current text section. */
9915 unwind
.saved_seg
= now_seg
;
9916 unwind
.saved_subseg
= now_subseg
;
9918 start_unwind_section (now_seg
, 0);
9920 if (unwind
.personality_routine
== NULL
)
9922 if (unwind
.personality_index
== -2)
9925 as_bad (_("handerdata in cantunwind frame"));
9926 return 1; /* EXIDX_CANTUNWIND. */
9929 /* Use a default personality routine if none is specified. */
9930 if (unwind
.personality_index
== -1)
9932 if (unwind
.opcode_count
> 3)
9933 unwind
.personality_index
= 1;
9935 unwind
.personality_index
= 0;
9938 /* Space for the personality routine entry. */
9939 if (unwind
.personality_index
== 0)
9941 if (unwind
.opcode_count
> 3)
9942 as_bad (_("too many unwind opcodes for personality routine 0"));
9946 /* All the data is inline in the index table. */
9949 while (unwind
.opcode_count
> 0)
9951 unwind
.opcode_count
--;
9952 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
9956 /* Pad with "finish" opcodes. */
9958 data
= (data
<< 8) | 0xb0;
9965 /* We get two opcodes "free" in the first word. */
9966 size
= unwind
.opcode_count
- 2;
9969 /* An extra byte is required for the opcode count. */
9970 size
= unwind
.opcode_count
+ 1;
9972 size
= (size
+ 3) >> 2;
9974 as_bad (_("too many unwind opcodes"));
9976 frag_align (2, 0, 0);
9977 record_alignment (now_seg
, 2);
9978 unwind
.table_entry
= expr_build_dot ();
9980 /* Allocate the table entry. */
9981 ptr
= frag_more ((size
<< 2) + 4);
9982 where
= frag_now_fix () - ((size
<< 2) + 4);
9984 switch (unwind
.personality_index
)
9987 /* ??? Should this be a PLT generating relocation? */
9988 /* Custom personality routine. */
9989 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
9990 BFD_RELOC_ARM_PREL31
);
9995 /* Set the first byte to the number of additional words. */
10000 /* ABI defined personality routines. */
10002 /* Three opcodes bytes are packed into the first word. */
10009 /* The size and first two opcode bytes go in the first word. */
10010 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
10015 /* Should never happen. */
10019 /* Pack the opcodes into words (MSB first), reversing the list at the same
10021 while (unwind
.opcode_count
> 0)
10025 md_number_to_chars (ptr
, data
, 4);
10030 unwind
.opcode_count
--;
10032 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
10035 /* Finish off the last word. */
10038 /* Pad with "finish" opcodes. */
10040 data
= (data
<< 8) | 0xb0;
10042 md_number_to_chars (ptr
, data
, 4);
10047 /* Add an empty descriptor if there is no user-specified data. */
10048 ptr
= frag_more (4);
10049 md_number_to_chars (ptr
, 0, 4);
10055 /* Convert REGNAME to a DWARF-2 register number. */
10058 tc_arm_regname_to_dw2regnum (const char *regname
)
10060 int reg
= arm_reg_parse ((char **) ®name
, REG_TYPE_RN
);
10068 /* Initialize the DWARF-2 unwind information for this procedure. */
10071 tc_arm_frame_initial_instructions (void)
10073 cfi_add_CFA_def_cfa (REG_SP
, 0);
10075 #endif /* OBJ_ELF */
10078 /* MD interface: Symbol and relocation handling. */
10080 /* Return the address within the segment that a PC-relative fixup is
10081 relative to. For ARM, PC-relative fixups applied to instructions
10082 are generally relative to the location of the fixup plus 8 bytes.
10083 Thumb branches are offset by 4, and Thumb loads relative to PC
10084 require special handling. */
10087 md_pcrel_from_section (fixS
* fixP
, segT seg
)
10089 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10091 /* If this is pc-relative and we are going to emit a relocation
10092 then we just want to put out any pipeline compensation that the linker
10093 will need. Otherwise we want to use the calculated base. */
10095 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
10096 || arm_force_relocation (fixP
)))
10099 switch (fixP
->fx_r_type
)
10101 /* PC relative addressing on the Thumb is slightly odd as the
10102 bottom two bits of the PC are forced to zero for the
10103 calculation. This happens *after* application of the
10104 pipeline offset. However, Thumb adrl already adjusts for
10105 this, so we need not do it again. */
10106 case BFD_RELOC_ARM_THUMB_ADD
:
10109 case BFD_RELOC_ARM_THUMB_OFFSET
:
10110 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
10111 case BFD_RELOC_ARM_T32_ADD_PC12
:
10112 return (base
+ 4) & ~3;
10114 /* Thumb branches are simply offset by +4. */
10115 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
10116 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
10117 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
10118 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
10119 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
10120 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
10121 case BFD_RELOC_THUMB_PCREL_BLX
:
10124 /* ARM mode branches are offset by +8. However, the Windows CE
10125 loader expects the relocation not to take this into account. */
10126 case BFD_RELOC_ARM_PCREL_BRANCH
:
10127 case BFD_RELOC_ARM_PCREL_BLX
:
10128 case BFD_RELOC_ARM_PLT32
:
10135 /* ARM mode loads relative to PC are also offset by +8. Unlike
10136 branches, the Windows CE loader *does* expect the relocation
10137 to take this into account. */
10138 case BFD_RELOC_ARM_OFFSET_IMM
:
10139 case BFD_RELOC_ARM_OFFSET_IMM8
:
10140 case BFD_RELOC_ARM_HWLITERAL
:
10141 case BFD_RELOC_ARM_LITERAL
:
10142 case BFD_RELOC_ARM_CP_OFF_IMM
:
10146 /* Other PC-relative relocations are un-offset. */
10152 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
10153 Otherwise we have no need to default values of symbols. */
10156 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
10159 if (name
[0] == '_' && name
[1] == 'G'
10160 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
10164 if (symbol_find (name
))
10165 as_bad ("GOT already in the symbol table");
10167 GOT_symbol
= symbol_new (name
, undefined_section
,
10168 (valueT
) 0, & zero_address_frag
);
10178 /* Subroutine of md_apply_fix. Check to see if an immediate can be
10179 computed as two separate immediate values, added together. We
10180 already know that this value cannot be computed by just one ARM
10183 static unsigned int
10184 validate_immediate_twopart (unsigned int val
,
10185 unsigned int * highpart
)
10190 for (i
= 0; i
< 32; i
+= 2)
10191 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
10197 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
10199 else if (a
& 0xff0000)
10201 if (a
& 0xff000000)
10203 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
10207 assert (a
& 0xff000000);
10208 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
10211 return (a
& 0xff) | (i
<< 7);
10218 validate_offset_imm (unsigned int val
, int hwse
)
10220 if ((hwse
&& val
> 255) || val
> 4095)
10225 /* Subroutine of md_apply_fix. Do those data_ops which can take a
10226 negative immediate constant by altering the instruction. A bit of
10231 by inverting the second operand, and
10234 by negating the second operand. */
10237 negate_data_op (unsigned long * instruction
,
10238 unsigned long value
)
10241 unsigned long negated
, inverted
;
10243 negated
= encode_arm_immediate (-value
);
10244 inverted
= encode_arm_immediate (~value
);
10246 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
10249 /* First negates. */
10250 case OPCODE_SUB
: /* ADD <-> SUB */
10251 new_inst
= OPCODE_ADD
;
10256 new_inst
= OPCODE_SUB
;
10260 case OPCODE_CMP
: /* CMP <-> CMN */
10261 new_inst
= OPCODE_CMN
;
10266 new_inst
= OPCODE_CMP
;
10270 /* Now Inverted ops. */
10271 case OPCODE_MOV
: /* MOV <-> MVN */
10272 new_inst
= OPCODE_MVN
;
10277 new_inst
= OPCODE_MOV
;
10281 case OPCODE_AND
: /* AND <-> BIC */
10282 new_inst
= OPCODE_BIC
;
10287 new_inst
= OPCODE_AND
;
10291 case OPCODE_ADC
: /* ADC <-> SBC */
10292 new_inst
= OPCODE_SBC
;
10297 new_inst
= OPCODE_ADC
;
10301 /* We cannot do anything. */
10306 if (value
== (unsigned) FAIL
)
10309 *instruction
&= OPCODE_MASK
;
10310 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
10315 md_apply_fix (fixS
* fixP
,
10319 offsetT value
= * valP
;
10321 unsigned int newimm
;
10322 unsigned long temp
;
10324 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10326 assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
10328 /* Note whether this will delete the relocation. */
10329 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
10332 /* On a 64-bit host, silently truncate 'value' to 32 bits for
10333 consistency with the behavior on 32-bit hosts. Remember value
10335 value
&= 0xffffffff;
10336 value
^= 0x80000000;
10337 value
-= 0x80000000;
10340 fixP
->fx_addnumber
= value
;
10342 /* Same treatment for fixP->fx_offset. */
10343 fixP
->fx_offset
&= 0xffffffff;
10344 fixP
->fx_offset
^= 0x80000000;
10345 fixP
->fx_offset
-= 0x80000000;
10347 switch (fixP
->fx_r_type
)
10349 case BFD_RELOC_NONE
:
10350 /* This will need to go in the object file. */
10354 case BFD_RELOC_ARM_IMMEDIATE
:
10355 /* We claim that this fixup has been processed here,
10356 even if in fact we generate an error because we do
10357 not have a reloc for it, so tc_gen_reloc will reject it. */
10361 && ! S_IS_DEFINED (fixP
->fx_addsy
))
10363 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10364 _("undefined symbol %s used as an immediate value"),
10365 S_GET_NAME (fixP
->fx_addsy
));
10369 newimm
= encode_arm_immediate (value
);
10370 temp
= md_chars_to_number (buf
, INSN_SIZE
);
10372 /* If the instruction will fail, see if we can fix things up by
10373 changing the opcode. */
10374 if (newimm
== (unsigned int) FAIL
10375 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
10377 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10378 _("invalid constant (%lx) after fixup"),
10379 (unsigned long) value
);
10383 newimm
|= (temp
& 0xfffff000);
10384 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
10387 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
10389 unsigned int highpart
= 0;
10390 unsigned int newinsn
= 0xe1a00000; /* nop. */
10392 newimm
= encode_arm_immediate (value
);
10393 temp
= md_chars_to_number (buf
, INSN_SIZE
);
10395 /* If the instruction will fail, see if we can fix things up by
10396 changing the opcode. */
10397 if (newimm
== (unsigned int) FAIL
10398 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
10400 /* No ? OK - try using two ADD instructions to generate
10402 newimm
= validate_immediate_twopart (value
, & highpart
);
10404 /* Yes - then make sure that the second instruction is
10406 if (newimm
!= (unsigned int) FAIL
)
10408 /* Still No ? Try using a negated value. */
10409 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
10410 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
10411 /* Otherwise - give up. */
10414 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10415 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
10420 /* Replace the first operand in the 2nd instruction (which
10421 is the PC) with the destination register. We have
10422 already added in the PC in the first instruction and we
10423 do not want to do it again. */
10424 newinsn
&= ~ 0xf0000;
10425 newinsn
|= ((newinsn
& 0x0f000) << 4);
10428 newimm
|= (temp
& 0xfffff000);
10429 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
10431 highpart
|= (newinsn
& 0xfffff000);
10432 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
10436 case BFD_RELOC_ARM_OFFSET_IMM
:
10437 case BFD_RELOC_ARM_LITERAL
:
10443 if (validate_offset_imm (value
, 0) == FAIL
)
10445 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
10446 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10447 _("invalid literal constant: pool needs to be closer"));
10449 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10450 _("bad immediate value for offset (%ld)"),
10455 newval
= md_chars_to_number (buf
, INSN_SIZE
);
10456 newval
&= 0xff7ff000;
10457 newval
|= value
| (sign
? INDEX_UP
: 0);
10458 md_number_to_chars (buf
, newval
, INSN_SIZE
);
10461 case BFD_RELOC_ARM_OFFSET_IMM8
:
10462 case BFD_RELOC_ARM_HWLITERAL
:
10468 if (validate_offset_imm (value
, 1) == FAIL
)
10470 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
10471 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10472 _("invalid literal constant: pool needs to be closer"));
10474 as_bad (_("bad immediate value for half-word offset (%ld)"),
10479 newval
= md_chars_to_number (buf
, INSN_SIZE
);
10480 newval
&= 0xff7ff0f0;
10481 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
10482 md_number_to_chars (buf
, newval
, INSN_SIZE
);
10485 case BFD_RELOC_ARM_T32_OFFSET_U8
:
10486 if (value
< 0 || value
> 1020 || value
% 4 != 0)
10487 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10488 _("bad immediate value for offset (%ld)"), (long) value
);
10491 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
10493 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
10496 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
10497 /* This is a complicated relocation used for all varieties of Thumb32
10498 load/store instruction with immediate offset:
10500 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
10501 *4, optional writeback(W)
10502 (doubleword load/store)
10504 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
10505 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
10506 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
10507 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
10508 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
10510 Uppercase letters indicate bits that are already encoded at
10511 this point. Lowercase letters are our problem. For the
10512 second block of instructions, the secondary opcode nybble
10513 (bits 8..11) is present, and bit 23 is zero, even if this is
10514 a PC-relative operation. */
10515 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
10517 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
10519 if ((newval
& 0xf0000000) == 0xe0000000)
10521 /* Doubleword load/store: 8-bit offset, scaled by 4. */
10523 newval
|= (1 << 23);
10526 if (value
% 4 != 0)
10528 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10529 _("offset not a multiple of 4"));
10535 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10536 _("offset out of range"));
10541 else if ((newval
& 0x000f0000) == 0x000f0000)
10543 /* PC-relative, 12-bit offset. */
10545 newval
|= (1 << 23);
10548 if (value
>= 0xfff)
10550 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10551 _("offset out of range"));
10556 else if ((newval
& 0x00000100) == 0x00000100)
10558 /* Writeback: 8-bit, +/- offset. */
10560 newval
|= (1 << 9);
10565 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10566 _("offset out of range"));
10571 else if ((newval
& 0x00000f00) == 0x00000e00)
10573 /* T-instruction: positive 8-bit offset. */
10574 if (value
< 0 || value
>= 0xff)
10576 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10577 _("offset out of range"));
10585 /* Positive 12-bit or negative 8-bit offset. */
10589 newval
|= (1 << 23);
10599 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10600 _("offset out of range"));
10607 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
10608 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
10611 case BFD_RELOC_ARM_SHIFT_IMM
:
10612 newval
= md_chars_to_number (buf
, INSN_SIZE
);
10613 if (((unsigned long) value
) > 32
10615 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
10617 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10618 _("shift expression is too large"));
10623 /* Shifts of zero must be done as lsl. */
10625 else if (value
== 32)
10627 newval
&= 0xfffff07f;
10628 newval
|= (value
& 0x1f) << 7;
10629 md_number_to_chars (buf
, newval
, INSN_SIZE
);
10632 case BFD_RELOC_ARM_T32_IMMEDIATE
:
10633 case BFD_RELOC_ARM_T32_IMM12
:
10634 case BFD_RELOC_ARM_T32_ADD_PC12
:
10635 /* We claim that this fixup has been processed here,
10636 even if in fact we generate an error because we do
10637 not have a reloc for it, so tc_gen_reloc will reject it. */
10641 && ! S_IS_DEFINED (fixP
->fx_addsy
))
10643 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10644 _("undefined symbol %s used as an immediate value"),
10645 S_GET_NAME (fixP
->fx_addsy
));
10649 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
10651 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
10653 /* FUTURE: Implement analogue of negate_data_op for T32. */
10654 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
)
10655 newimm
= encode_thumb32_immediate (value
);
10658 /* 12 bit immediate for addw/subw. */
10662 newval
^= 0x00a00000;
10665 newimm
= (unsigned int) FAIL
;
10670 if (newimm
== (unsigned int)FAIL
)
10672 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10673 _("invalid constant (%lx) after fixup"),
10674 (unsigned long) value
);
10678 newval
|= (newimm
& 0x800) << 15;
10679 newval
|= (newimm
& 0x700) << 4;
10680 newval
|= (newimm
& 0x0ff);
10682 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
10683 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
10686 case BFD_RELOC_ARM_SMI
:
10687 if (((unsigned long) value
) > 0xffff)
10688 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10689 _("invalid smi expression"));
10690 newval
= md_chars_to_number (buf
, INSN_SIZE
);
10691 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
10692 md_number_to_chars (buf
, newval
, INSN_SIZE
);
10695 case BFD_RELOC_ARM_SWI
:
10696 if (fixP
->tc_fix_data
!= 0)
10698 if (((unsigned long) value
) > 0xff)
10699 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10700 _("invalid swi expression"));
10701 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
10703 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
10707 if (((unsigned long) value
) > 0x00ffffff)
10708 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10709 _("invalid swi expression"));
10710 newval
= md_chars_to_number (buf
, INSN_SIZE
);
10712 md_number_to_chars (buf
, newval
, INSN_SIZE
);
10716 case BFD_RELOC_ARM_MULTI
:
10717 if (((unsigned long) value
) > 0xffff)
10718 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10719 _("invalid expression in load/store multiple"));
10720 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
10721 md_number_to_chars (buf
, newval
, INSN_SIZE
);
10724 case BFD_RELOC_ARM_PCREL_BRANCH
:
10726 case BFD_RELOC_ARM_PLT32
:
10729 /* We are going to store value (shifted right by two) in the
10730 instruction, in a 24 bit, signed field. Bits 0 and 1 must be
10731 clear, and bits 26 through 32 either all clear or all set. */
10732 if (value
& 0x00000003)
10733 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10734 _("misaligned branch destination"));
10735 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
10736 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
10737 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10738 _("branch out of range"));
10740 if (fixP
->fx_done
|| !seg
->use_rela_p
)
10742 newval
= md_chars_to_number (buf
, INSN_SIZE
);
10743 newval
|= (value
>> 2) & 0x00ffffff;
10744 md_number_to_chars (buf
, newval
, INSN_SIZE
);
10748 case BFD_RELOC_ARM_PCREL_BLX
:
10749 /* BLX allows bit 1 to be set in the branch destination, since
10750 it targets a Thumb instruction which is only required to be
10751 aligned modulo 2. Other constraints are as for B/BL. */
10752 if (value
& 0x00000001)
10753 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10754 _("misaligned BLX destination"));
10755 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
10756 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
10757 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10758 _("branch out of range"));
10760 if (fixP
->fx_done
|| !seg
->use_rela_p
)
10763 hbit
= (value
>> 1) & 1;
10764 value
= (value
>> 2) & 0x00ffffff;
10766 newval
= md_chars_to_number (buf
, INSN_SIZE
);
10767 newval
|= value
| hbit
<< 24;
10768 md_number_to_chars (buf
, newval
, INSN_SIZE
);
10772 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CZB */
10773 /* CZB can only branch forward. */
10775 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10776 _("branch out of range"));
10778 if (fixP
->fx_done
|| !seg
->use_rela_p
)
10780 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
10781 newval
|= ((value
& 0x2e) << 2) | ((value
& 0x40) << 3);
10782 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
10786 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
10787 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
10788 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10789 _("branch out of range"));
10791 if (fixP
->fx_done
|| !seg
->use_rela_p
)
10793 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
10794 newval
|= (value
& 0x1ff) >> 1;
10795 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
10799 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
10800 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
10801 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10802 _("branch out of range"));
10804 if (fixP
->fx_done
|| !seg
->use_rela_p
)
10806 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
10807 newval
|= (value
& 0xfff) >> 1;
10808 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
10812 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
10813 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
10814 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10815 _("conditional branch out of range"));
10817 if (fixP
->fx_done
|| !seg
->use_rela_p
)
10820 addressT S
, J1
, J2
, lo
, hi
;
10822 S
= (value
& 0x00100000) >> 20;
10823 J2
= (value
& 0x00080000) >> 19;
10824 J1
= (value
& 0x00040000) >> 18;
10825 hi
= (value
& 0x0003f000) >> 12;
10826 lo
= (value
& 0x00000ffe) >> 1;
10828 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
10829 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
10830 newval
|= (S
<< 10) | hi
;
10831 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
10832 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
10833 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
10837 case BFD_RELOC_THUMB_PCREL_BLX
:
10838 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
10839 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
10840 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10841 _("branch out of range"));
10843 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
10844 /* For a BLX instruction, make sure that the relocation is rounded up
10845 to a word boundary. This follows the semantics of the instruction
10846 which specifies that bit 1 of the target address will come from bit
10847 1 of the base address. */
10848 value
= (value
+ 1) & ~ 1;
10850 if (fixP
->fx_done
|| !seg
->use_rela_p
)
10854 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
10855 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
10856 newval
|= (value
& 0x7fffff) >> 12;
10857 newval2
|= (value
& 0xfff) >> 1;
10858 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
10859 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
10863 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
10864 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
10865 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10866 _("branch out of range"));
10868 if (fixP
->fx_done
|| !seg
->use_rela_p
)
10871 addressT S
, I1
, I2
, lo
, hi
;
10873 S
= (value
& 0x01000000) >> 24;
10874 I1
= (value
& 0x00800000) >> 23;
10875 I2
= (value
& 0x00400000) >> 22;
10876 hi
= (value
& 0x003ff000) >> 12;
10877 lo
= (value
& 0x00000ffe) >> 1;
10882 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
10883 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
10884 newval
|= (S
<< 10) | hi
;
10885 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
10886 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
10887 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
10892 if (fixP
->fx_done
|| !seg
->use_rela_p
)
10893 md_number_to_chars (buf
, value
, 1);
10897 if (fixP
->fx_done
|| !seg
->use_rela_p
)
10898 md_number_to_chars (buf
, value
, 2);
10902 case BFD_RELOC_ARM_TLS_GD32
:
10903 case BFD_RELOC_ARM_TLS_LE32
:
10904 case BFD_RELOC_ARM_TLS_IE32
:
10905 case BFD_RELOC_ARM_TLS_LDM32
:
10906 case BFD_RELOC_ARM_TLS_LDO32
:
10907 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10910 case BFD_RELOC_ARM_GOT32
:
10911 case BFD_RELOC_ARM_GOTOFF
:
10912 case BFD_RELOC_ARM_TARGET2
:
10913 if (fixP
->fx_done
|| !seg
->use_rela_p
)
10914 md_number_to_chars (buf
, 0, 4);
10918 case BFD_RELOC_RVA
:
10920 case BFD_RELOC_ARM_TARGET1
:
10921 case BFD_RELOC_ARM_ROSEGREL32
:
10922 case BFD_RELOC_ARM_SBREL32
:
10923 case BFD_RELOC_32_PCREL
:
10924 if (fixP
->fx_done
|| !seg
->use_rela_p
)
10925 md_number_to_chars (buf
, value
, 4);
10929 case BFD_RELOC_ARM_PREL31
:
10930 if (fixP
->fx_done
|| !seg
->use_rela_p
)
10932 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
10933 if ((value
^ (value
>> 1)) & 0x40000000)
10935 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10936 _("rel31 relocation overflow"));
10938 newval
|= value
& 0x7fffffff;
10939 md_number_to_chars (buf
, newval
, 4);
10944 case BFD_RELOC_ARM_CP_OFF_IMM
:
10945 if (value
< -1023 || value
> 1023 || (value
& 3))
10946 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10947 _("co-processor offset out of range"));
10952 newval
= md_chars_to_number (buf
, INSN_SIZE
) & 0xff7fff00;
10953 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
10955 newval
&= ~WRITE_BACK
;
10956 md_number_to_chars (buf
, newval
, INSN_SIZE
);
10959 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
10960 if (value
< -255 || value
> 255)
10961 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10962 _("co-processor offset out of range"));
10963 goto cp_off_common
;
10965 case BFD_RELOC_ARM_THUMB_OFFSET
:
10966 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
10967 /* Exactly what ranges, and where the offset is inserted depends
10968 on the type of instruction, we can establish this from the
10970 switch (newval
>> 12)
10972 case 4: /* PC load. */
10973 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
10974 forced to zero for these loads; md_pcrel_from has already
10975 compensated for this. */
10977 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10978 _("invalid offset, target not word aligned (0x%08lX)"),
10979 (((unsigned int) fixP
->fx_frag
->fr_address
10980 + (unsigned int) fixP
->fx_where
) & ~3) + value
);
10982 if (value
& ~0x3fc)
10983 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10984 _("invalid offset, value too big (0x%08lX)"),
10987 newval
|= value
>> 2;
10990 case 9: /* SP load/store. */
10991 if (value
& ~0x3fc)
10992 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10993 _("invalid offset, value too big (0x%08lX)"),
10995 newval
|= value
>> 2;
10998 case 6: /* Word load/store. */
11000 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11001 _("invalid offset, value too big (0x%08lX)"),
11003 newval
|= value
<< 4; /* 6 - 2. */
11006 case 7: /* Byte load/store. */
11008 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11009 _("invalid offset, value too big (0x%08lX)"),
11011 newval
|= value
<< 6;
11014 case 8: /* Halfword load/store. */
11016 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11017 _("invalid offset, value too big (0x%08lX)"),
11019 newval
|= value
<< 5; /* 6 - 1. */
11023 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11024 "Unable to process relocation for thumb opcode: %lx",
11025 (unsigned long) newval
);
11028 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
11031 case BFD_RELOC_ARM_THUMB_ADD
:
11032 /* This is a complicated relocation, since we use it for all of
11033 the following immediate relocations:
11037 9bit ADD/SUB SP word-aligned
11038 10bit ADD PC/SP word-aligned
11040 The type of instruction being processed is encoded in the
11047 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
11049 int rd
= (newval
>> 4) & 0xf;
11050 int rs
= newval
& 0xf;
11051 int subtract
= !!(newval
& 0x8000);
11053 /* Check for HI regs, only very restricted cases allowed:
11054 Adjusting SP, and using PC or SP to get an address. */
11055 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
11056 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
11057 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11058 _("invalid Hi register with immediate"));
11060 /* If value is negative, choose the opposite instruction. */
11064 subtract
= !subtract
;
11066 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11067 _("immediate value out of range"));
11072 if (value
& ~0x1fc)
11073 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11074 _("invalid immediate for stack address calculation"));
11075 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
11076 newval
|= value
>> 2;
11078 else if (rs
== REG_PC
|| rs
== REG_SP
)
11080 if (subtract
|| value
& ~0x3fc)
11081 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11082 _("invalid immediate for address calculation (value = 0x%08lX)"),
11083 (unsigned long) value
);
11084 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
11086 newval
|= value
>> 2;
11091 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11092 _("immediate value out of range"));
11093 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
11094 newval
|= (rd
<< 8) | value
;
11099 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11100 _("immediate value out of range"));
11101 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
11102 newval
|= rd
| (rs
<< 3) | (value
<< 6);
11105 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
11108 case BFD_RELOC_ARM_THUMB_IMM
:
11109 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
11110 if (value
< 0 || value
> 255)
11111 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11112 _("invalid immediate: %ld is too large"),
11115 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
11118 case BFD_RELOC_ARM_THUMB_SHIFT
:
11119 /* 5bit shift value (0..32). LSL cannot take 32. */
11120 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
11121 temp
= newval
& 0xf800;
11122 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
11123 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11124 _("invalid shift value: %ld"), (long) value
);
11125 /* Shifts of zero must be encoded as LSL. */
11127 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
11128 /* Shifts of 32 are encoded as zero. */
11129 else if (value
== 32)
11131 newval
|= value
<< 6;
11132 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
11135 case BFD_RELOC_VTABLE_INHERIT
:
11136 case BFD_RELOC_VTABLE_ENTRY
:
11140 case BFD_RELOC_UNUSED
:
11142 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11143 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
11147 /* Translate internal representation of relocation info to BFD target
11151 tc_gen_reloc (asection
* section ATTRIBUTE_UNUSED
,
11155 bfd_reloc_code_real_type code
;
11157 reloc
= xmalloc (sizeof (arelent
));
11159 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
11160 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11161 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11163 if (fixp
->fx_pcrel
)
11164 fixp
->fx_offset
= reloc
->address
;
11165 reloc
->addend
= fixp
->fx_offset
;
11167 switch (fixp
->fx_r_type
)
11170 if (fixp
->fx_pcrel
)
11172 code
= BFD_RELOC_8_PCREL
;
11177 if (fixp
->fx_pcrel
)
11179 code
= BFD_RELOC_16_PCREL
;
11184 if (fixp
->fx_pcrel
)
11186 code
= BFD_RELOC_32_PCREL
;
11190 case BFD_RELOC_NONE
:
11191 case BFD_RELOC_ARM_PCREL_BRANCH
:
11192 case BFD_RELOC_ARM_PCREL_BLX
:
11193 case BFD_RELOC_RVA
:
11194 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
11195 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
11196 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
11197 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
11198 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
11199 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
11200 case BFD_RELOC_THUMB_PCREL_BLX
:
11201 case BFD_RELOC_VTABLE_ENTRY
:
11202 case BFD_RELOC_VTABLE_INHERIT
:
11203 code
= fixp
->fx_r_type
;
11206 case BFD_RELOC_ARM_LITERAL
:
11207 case BFD_RELOC_ARM_HWLITERAL
:
11208 /* If this is called then the a literal has
11209 been referenced across a section boundary. */
11210 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11211 _("literal referenced across section boundary"));
11215 case BFD_RELOC_ARM_GOT32
:
11216 case BFD_RELOC_ARM_GOTOFF
:
11217 case BFD_RELOC_ARM_PLT32
:
11218 case BFD_RELOC_ARM_TARGET1
:
11219 case BFD_RELOC_ARM_ROSEGREL32
:
11220 case BFD_RELOC_ARM_SBREL32
:
11221 case BFD_RELOC_ARM_PREL31
:
11222 case BFD_RELOC_ARM_TARGET2
:
11223 case BFD_RELOC_ARM_TLS_LE32
:
11224 case BFD_RELOC_ARM_TLS_LDO32
:
11225 code
= fixp
->fx_r_type
;
11228 case BFD_RELOC_ARM_TLS_GD32
:
11229 case BFD_RELOC_ARM_TLS_IE32
:
11230 case BFD_RELOC_ARM_TLS_LDM32
:
11231 /* BFD will include the symbol's address in the addend.
11232 But we don't want that, so subtract it out again here. */
11233 if (!S_IS_COMMON (fixp
->fx_addsy
))
11234 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
11235 code
= fixp
->fx_r_type
;
11239 case BFD_RELOC_ARM_IMMEDIATE
:
11240 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11241 _("internal relocation (type: IMMEDIATE) not fixed up"));
11244 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
11245 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11246 _("ADRL used for a symbol not defined in the same file"));
11249 case BFD_RELOC_ARM_OFFSET_IMM
:
11250 if (fixp
->fx_addsy
!= NULL
11251 && !S_IS_DEFINED (fixp
->fx_addsy
)
11252 && S_IS_LOCAL (fixp
->fx_addsy
))
11254 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11255 _("undefined local label `%s'"),
11256 S_GET_NAME (fixp
->fx_addsy
));
11260 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11261 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
11268 switch (fixp
->fx_r_type
)
11270 case BFD_RELOC_NONE
: type
= "NONE"; break;
11271 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
11272 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
11273 case BFD_RELOC_ARM_SMI
: type
= "SMI"; break;
11274 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
11275 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
11276 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
11277 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
11278 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
11279 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
11280 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
11281 default: type
= _("<unknown>"); break;
11283 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11284 _("cannot represent %s relocation in this object file format"),
11291 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
11293 && fixp
->fx_addsy
== GOT_symbol
)
11295 code
= BFD_RELOC_ARM_GOTPC
;
11296 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
11300 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11302 if (reloc
->howto
== NULL
)
11304 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11305 _("cannot represent %s relocation in this object file format"),
11306 bfd_get_reloc_code_name (code
));
11310 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
11311 vtable entry to be used in the relocation's section offset. */
11312 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11313 reloc
->address
= fixp
->fx_offset
;
11318 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
11321 cons_fix_new_arm (fragS
* frag
,
11326 bfd_reloc_code_real_type type
;
11330 FIXME: @@ Should look at CPU word size. */
11334 type
= BFD_RELOC_8
;
11337 type
= BFD_RELOC_16
;
11341 type
= BFD_RELOC_32
;
11344 type
= BFD_RELOC_64
;
11348 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
11351 #if defined OBJ_COFF || defined OBJ_ELF
11353 arm_validate_fix (fixS
* fixP
)
11355 /* If the destination of the branch is a defined symbol which does not have
11356 the THUMB_FUNC attribute, then we must be calling a function which has
11357 the (interfacearm) attribute. We look for the Thumb entry point to that
11358 function and change the branch to refer to that function instead. */
11359 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
11360 && fixP
->fx_addsy
!= NULL
11361 && S_IS_DEFINED (fixP
->fx_addsy
)
11362 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
11364 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
11370 arm_force_relocation (struct fix
* fixp
)
11372 #if defined (OBJ_COFF) && defined (TE_PE)
11373 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
11377 /* Resolve these relocations even if the symbol is extern or weak. */
11378 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
11379 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
11380 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
)
11383 return generic_force_reloc (fixp
);
11387 /* This is a little hack to help the gas/arm/adrl.s test. It prevents
11388 local labels from being added to the output symbol table when they
11389 are used with the ADRL pseudo op. The ADRL relocation should always
11390 be resolved before the binbary is emitted, so it is safe to say that
11391 it is adjustable. */
11394 arm_fix_adjustable (fixS
* fixP
)
11396 if (fixP
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
)
11403 /* Relocations against Thumb function names must be left unadjusted,
11404 so that the linker can use this information to correctly set the
11405 bottom bit of their addresses. The MIPS version of this function
11406 also prevents relocations that are mips-16 specific, but I do not
11407 know why it does this.
11410 There is one other problem that ought to be addressed here, but
11411 which currently is not: Taking the address of a label (rather
11412 than a function) and then later jumping to that address. Such
11413 addresses also ought to have their bottom bit set (assuming that
11414 they reside in Thumb code), but at the moment they will not. */
11417 arm_fix_adjustable (fixS
* fixP
)
11419 if (fixP
->fx_addsy
== NULL
)
11422 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
11423 && fixP
->fx_subsy
== NULL
)
11426 /* We need the symbol name for the VTABLE entries. */
11427 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11428 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11431 /* Don't allow symbols to be discarded on GOT related relocs. */
11432 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
11433 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
11434 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
11435 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
11436 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
11437 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
11438 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
11439 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
11440 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
11447 elf32_arm_target_format (void)
11450 return (target_big_endian
11451 ? "elf32-bigarm-symbian"
11452 : "elf32-littlearm-symbian");
11453 #elif defined (TE_VXWORKS)
11454 return (target_big_endian
11455 ? "elf32-bigarm-vxworks"
11456 : "elf32-littlearm-vxworks");
11458 if (target_big_endian
)
11459 return "elf32-bigarm";
11461 return "elf32-littlearm";
11466 armelf_frob_symbol (symbolS
* symp
,
11469 elf_frob_symbol (symp
, puntp
);
11473 /* MD interface: Finalization. */
11475 /* A good place to do this, although this was probably not intended
11476 for this kind of use. We need to dump the literal pool before
11477 references are made to a null symbol pointer. */
11482 literal_pool
* pool
;
11484 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
11486 /* Put it at the end of the relevent section. */
11487 subseg_set (pool
->section
, pool
->sub_section
);
11489 arm_elf_change_section ();
11495 /* Adjust the symbol table. This marks Thumb symbols as distinct from
11499 arm_adjust_symtab (void)
11504 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
11506 if (ARM_IS_THUMB (sym
))
11508 if (THUMB_IS_FUNC (sym
))
11510 /* Mark the symbol as a Thumb function. */
11511 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
11512 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
11513 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
11515 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
11516 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
11518 as_bad (_("%s: unexpected function type: %d"),
11519 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
11521 else switch (S_GET_STORAGE_CLASS (sym
))
11524 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
11527 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
11530 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
11538 if (ARM_IS_INTERWORK (sym
))
11539 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
11546 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
11548 if (ARM_IS_THUMB (sym
))
11550 elf_symbol_type
* elf_sym
;
11552 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
11553 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
11555 if (! bfd_is_arm_mapping_symbol_name (elf_sym
->symbol
.name
))
11557 /* If it's a .thumb_func, declare it as so,
11558 otherwise tag label as .code 16. */
11559 if (THUMB_IS_FUNC (sym
))
11560 elf_sym
->internal_elf_sym
.st_info
=
11561 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
11563 elf_sym
->internal_elf_sym
.st_info
=
11564 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
11571 /* MD interface: Initialization. */
11574 set_constant_flonums (void)
11578 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
11579 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
11589 if ( (arm_ops_hsh
= hash_new ()) == NULL
11590 || (arm_cond_hsh
= hash_new ()) == NULL
11591 || (arm_shift_hsh
= hash_new ()) == NULL
11592 || (arm_psr_hsh
= hash_new ()) == NULL
11593 || (arm_reg_hsh
= hash_new ()) == NULL
11594 || (arm_reloc_hsh
= hash_new ()) == NULL
)
11595 as_fatal (_("virtual memory exhausted"));
11597 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
11598 hash_insert (arm_ops_hsh
, insns
[i
].template, (PTR
) (insns
+ i
));
11599 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
11600 hash_insert (arm_cond_hsh
, conds
[i
].template, (PTR
) (conds
+ i
));
11601 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
11602 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (PTR
) (shift_names
+ i
));
11603 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
11604 hash_insert (arm_psr_hsh
, psrs
[i
].template, (PTR
) (psrs
+ i
));
11605 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
11606 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (PTR
) (reg_names
+ i
));
11608 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
11609 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (PTR
) (reloc_names
+ i
));
11612 set_constant_flonums ();
11614 /* Set the cpu variant based on the command-line options. We prefer
11615 -mcpu= over -march= if both are set (as for GCC); and we prefer
11616 -mfpu= over any other way of setting the floating point unit.
11617 Use of legacy options with new options are faulted. */
11618 if (legacy_cpu
!= -1)
11620 if (mcpu_cpu_opt
!= -1 || march_cpu_opt
!= -1)
11621 as_bad (_("use of old and new-style options to set CPU type"));
11623 mcpu_cpu_opt
= legacy_cpu
;
11625 else if (mcpu_cpu_opt
== -1)
11626 mcpu_cpu_opt
= march_cpu_opt
;
11628 if (legacy_fpu
!= -1)
11630 if (mfpu_opt
!= -1)
11631 as_bad (_("use of old and new-style options to set FPU type"));
11633 mfpu_opt
= legacy_fpu
;
11635 else if (mfpu_opt
== -1)
11637 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
11638 /* Some environments specify a default FPU. If they don't, infer it
11639 from the processor. */
11640 if (mcpu_fpu_opt
!= -1)
11641 mfpu_opt
= mcpu_fpu_opt
;
11643 mfpu_opt
= march_fpu_opt
;
11645 mfpu_opt
= FPU_DEFAULT
;
11649 if (mfpu_opt
== -1)
11651 if (mcpu_cpu_opt
== -1)
11652 mfpu_opt
= FPU_DEFAULT
;
11653 else if (mcpu_cpu_opt
& ARM_EXT_V5
)
11654 mfpu_opt
= FPU_ARCH_VFP_V2
;
11656 mfpu_opt
= FPU_ARCH_FPA
;
11659 if (mcpu_cpu_opt
== -1)
11660 mcpu_cpu_opt
= CPU_DEFAULT
;
11662 cpu_variant
= mcpu_cpu_opt
| mfpu_opt
;
11664 #if defined OBJ_COFF || defined OBJ_ELF
11666 unsigned int flags
= 0;
11668 #if defined OBJ_ELF
11669 flags
= meabi_flags
;
11671 switch (meabi_flags
)
11673 case EF_ARM_EABI_UNKNOWN
:
11675 /* Set the flags in the private structure. */
11676 if (uses_apcs_26
) flags
|= F_APCS26
;
11677 if (support_interwork
) flags
|= F_INTERWORK
;
11678 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
11679 if (pic_code
) flags
|= F_PIC
;
11680 if ((cpu_variant
& FPU_ANY
) == FPU_NONE
11681 || (cpu_variant
& FPU_ANY
) == FPU_ARCH_VFP
) /* VFP layout only. */
11682 flags
|= F_SOFT_FLOAT
;
11684 switch (mfloat_abi_opt
)
11686 case ARM_FLOAT_ABI_SOFT
:
11687 case ARM_FLOAT_ABI_SOFTFP
:
11688 flags
|= F_SOFT_FLOAT
;
11691 case ARM_FLOAT_ABI_HARD
:
11692 if (flags
& F_SOFT_FLOAT
)
11693 as_bad (_("hard-float conflicts with specified fpu"));
11697 /* Using VFP conventions (even if soft-float). */
11698 if (cpu_variant
& FPU_VFP_EXT_NONE
)
11699 flags
|= F_VFP_FLOAT
;
11701 #if defined OBJ_ELF
11702 if (cpu_variant
& FPU_ARCH_MAVERICK
)
11703 flags
|= EF_ARM_MAVERICK_FLOAT
;
11706 case EF_ARM_EABI_VER4
:
11707 /* No additional flags to set. */
11714 bfd_set_private_flags (stdoutput
, flags
);
11716 /* We have run out flags in the COFF header to encode the
11717 status of ATPCS support, so instead we create a dummy,
11718 empty, debug section called .arm.atpcs. */
11723 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
11727 bfd_set_section_flags
11728 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
11729 bfd_set_section_size (stdoutput
, sec
, 0);
11730 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
11736 /* Record the CPU type as well. */
11737 switch (cpu_variant
& ARM_CPU_MASK
)
11740 mach
= bfd_mach_arm_2
;
11743 case ARM_3
: /* Also ARM_250. */
11744 mach
= bfd_mach_arm_2a
;
11747 case ARM_6
: /* Also ARM_7. */
11748 mach
= bfd_mach_arm_3
;
11752 mach
= bfd_mach_arm_unknown
;
11756 /* Catch special cases. */
11757 if (cpu_variant
& ARM_CEXT_IWMMXT
)
11758 mach
= bfd_mach_arm_iWMMXt
;
11759 else if (cpu_variant
& ARM_CEXT_XSCALE
)
11760 mach
= bfd_mach_arm_XScale
;
11761 else if (cpu_variant
& ARM_CEXT_MAVERICK
)
11762 mach
= bfd_mach_arm_ep9312
;
11763 else if (cpu_variant
& ARM_EXT_V5E
)
11764 mach
= bfd_mach_arm_5TE
;
11765 else if (cpu_variant
& ARM_EXT_V5
)
11767 if (cpu_variant
& ARM_EXT_V4T
)
11768 mach
= bfd_mach_arm_5T
;
11770 mach
= bfd_mach_arm_5
;
11772 else if (cpu_variant
& ARM_EXT_V4
)
11774 if (cpu_variant
& ARM_EXT_V4T
)
11775 mach
= bfd_mach_arm_4T
;
11777 mach
= bfd_mach_arm_4
;
11779 else if (cpu_variant
& ARM_EXT_V3M
)
11780 mach
= bfd_mach_arm_3M
;
11782 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
11785 /* Command line processing. */
11788 Invocation line includes a switch not recognized by the base assembler.
11789 See if it's a processor-specific option.
11791 This routine is somewhat complicated by the need for backwards
11792 compatibility (since older releases of gcc can't be changed).
11793 The new options try to make the interface as compatible as
11796 New options (supported) are:
11798 -mcpu=<cpu name> Assemble for selected processor
11799 -march=<architecture name> Assemble for selected architecture
11800 -mfpu=<fpu architecture> Assemble for selected FPU.
11801 -EB/-mbig-endian Big-endian
11802 -EL/-mlittle-endian Little-endian
11803 -k Generate PIC code
11804 -mthumb Start in Thumb mode
11805 -mthumb-interwork Code supports ARM/Thumb interworking
11807 For now we will also provide support for:
11809 -mapcs-32 32-bit Program counter
11810 -mapcs-26 26-bit Program counter
11811 -macps-float Floats passed in FP registers
11812 -mapcs-reentrant Reentrant code
11814 (sometime these will probably be replaced with -mapcs=<list of options>
11815 and -matpcs=<list of options>)
11817 The remaining options are only supported for back-wards compatibility.
11818 Cpu variants, the arm part is optional:
11819 -m[arm]1 Currently not supported.
11820 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
11821 -m[arm]3 Arm 3 processor
11822 -m[arm]6[xx], Arm 6 processors
11823 -m[arm]7[xx][t][[d]m] Arm 7 processors
11824 -m[arm]8[10] Arm 8 processors
11825 -m[arm]9[20][tdmi] Arm 9 processors
11826 -mstrongarm[110[0]] StrongARM processors
11827 -mxscale XScale processors
11828 -m[arm]v[2345[t[e]]] Arm architectures
11829 -mall All (except the ARM1)
11831 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
11832 -mfpe-old (No float load/store multiples)
11833 -mvfpxd VFP Single precision
11835 -mno-fpu Disable all floating point instructions
11837 The following CPU names are recognized:
11838 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
11839 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
11840 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
11841 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
11842 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
11843 arm10t arm10e, arm1020t, arm1020e, arm10200e,
11844 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
11848 const char * md_shortopts
= "m:k";
11850 #ifdef ARM_BI_ENDIAN
11851 #define OPTION_EB (OPTION_MD_BASE + 0)
11852 #define OPTION_EL (OPTION_MD_BASE + 1)
11854 #if TARGET_BYTES_BIG_ENDIAN
11855 #define OPTION_EB (OPTION_MD_BASE + 0)
11857 #define OPTION_EL (OPTION_MD_BASE + 1)
11861 struct option md_longopts
[] =
11864 {"EB", no_argument
, NULL
, OPTION_EB
},
11867 {"EL", no_argument
, NULL
, OPTION_EL
},
11869 {NULL
, no_argument
, NULL
, 0}
11872 size_t md_longopts_size
= sizeof (md_longopts
);
11874 struct arm_option_table
11876 char *option
; /* Option name to match. */
11877 char *help
; /* Help information. */
11878 int *var
; /* Variable to change. */
11879 int value
; /* What to change it to. */
11880 char *deprecated
; /* If non-null, print this message. */
11883 struct arm_option_table arm_opts
[] =
11885 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
11886 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
11887 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
11888 &support_interwork
, 1, NULL
},
11889 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
11890 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
11891 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
11893 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
11894 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
11895 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
11896 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
11899 /* These are recognized by the assembler, but have no affect on code. */
11900 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
11901 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
11903 /* DON'T add any new processors to this list -- we want the whole list
11904 to go away... Add them to the processors table instead. */
11905 {"marm1", NULL
, &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
11906 {"m1", NULL
, &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
11907 {"marm2", NULL
, &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
11908 {"m2", NULL
, &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
11909 {"marm250", NULL
, &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
11910 {"m250", NULL
, &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
11911 {"marm3", NULL
, &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
11912 {"m3", NULL
, &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
11913 {"marm6", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
11914 {"m6", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
11915 {"marm600", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
11916 {"m600", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
11917 {"marm610", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
11918 {"m610", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
11919 {"marm620", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
11920 {"m620", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
11921 {"marm7", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
11922 {"m7", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
11923 {"marm70", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
11924 {"m70", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
11925 {"marm700", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
11926 {"m700", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
11927 {"marm700i", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
11928 {"m700i", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
11929 {"marm710", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
11930 {"m710", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
11931 {"marm710c", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
11932 {"m710c", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
11933 {"marm720", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
11934 {"m720", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
11935 {"marm7d", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
11936 {"m7d", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
11937 {"marm7di", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
11938 {"m7di", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
11939 {"marm7m", NULL
, &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
11940 {"m7m", NULL
, &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
11941 {"marm7dm", NULL
, &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
11942 {"m7dm", NULL
, &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
11943 {"marm7dmi", NULL
, &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
11944 {"m7dmi", NULL
, &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
11945 {"marm7100", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
11946 {"m7100", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
11947 {"marm7500", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
11948 {"m7500", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
11949 {"marm7500fe", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
11950 {"m7500fe", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
11951 {"marm7t", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
11952 {"m7t", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
11953 {"marm7tdmi", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
11954 {"m7tdmi", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
11955 {"marm710t", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
11956 {"m710t", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
11957 {"marm720t", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
11958 {"m720t", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
11959 {"marm740t", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
11960 {"m740t", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
11961 {"marm8", NULL
, &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
11962 {"m8", NULL
, &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
11963 {"marm810", NULL
, &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
11964 {"m810", NULL
, &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
11965 {"marm9", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
11966 {"m9", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
11967 {"marm9tdmi", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
11968 {"m9tdmi", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
11969 {"marm920", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
11970 {"m920", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
11971 {"marm940", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
11972 {"m940", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
11973 {"mstrongarm", NULL
, &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
11974 {"mstrongarm110", NULL
, &legacy_cpu
, ARM_ARCH_V4
,
11975 N_("use -mcpu=strongarm110")},
11976 {"mstrongarm1100", NULL
, &legacy_cpu
, ARM_ARCH_V4
,
11977 N_("use -mcpu=strongarm1100")},
11978 {"mstrongarm1110", NULL
, &legacy_cpu
, ARM_ARCH_V4
,
11979 N_("use -mcpu=strongarm1110")},
11980 {"mxscale", NULL
, &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
11981 {"miwmmxt", NULL
, &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
11982 {"mall", NULL
, &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
11984 /* Architecture variants -- don't add any more to this list either. */
11985 {"mv2", NULL
, &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
11986 {"marmv2", NULL
, &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
11987 {"mv2a", NULL
, &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
11988 {"marmv2a", NULL
, &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
11989 {"mv3", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
11990 {"marmv3", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
11991 {"mv3m", NULL
, &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
11992 {"marmv3m", NULL
, &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
11993 {"mv4", NULL
, &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
11994 {"marmv4", NULL
, &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
11995 {"mv4t", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
11996 {"marmv4t", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
11997 {"mv5", NULL
, &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
11998 {"marmv5", NULL
, &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
11999 {"mv5t", NULL
, &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
12000 {"marmv5t", NULL
, &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
12001 {"mv5e", NULL
, &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
12002 {"marmv5e", NULL
, &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
12004 /* Floating point variants -- don't add any more to this list either. */
12005 {"mfpe-old", NULL
, &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
12006 {"mfpa10", NULL
, &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
12007 {"mfpa11", NULL
, &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
12008 {"mno-fpu", NULL
, &legacy_fpu
, 0,
12009 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
12011 {NULL
, NULL
, NULL
, 0, NULL
}
12014 struct arm_cpu_option_table
12018 /* For some CPUs we assume an FPU unless the user explicitly sets
12023 /* This list should, at a minimum, contain all the cpu names
12024 recognized by GCC. */
12025 static struct arm_cpu_option_table arm_cpus
[] =
12027 {"all", ARM_ANY
, FPU_ARCH_FPA
},
12028 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
12029 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
12030 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
12031 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
12032 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
},
12033 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
},
12034 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
},
12035 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
},
12036 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
},
12037 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
},
12038 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
12039 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
},
12040 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
12041 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
},
12042 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
12043 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
},
12044 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
},
12045 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
},
12046 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
},
12047 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
12048 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
},
12049 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
12050 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
12051 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
},
12052 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
},
12053 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
},
12054 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
},
12055 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
12056 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
12057 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
12058 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
},
12059 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
},
12060 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
},
12061 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
},
12062 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
},
12063 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
},
12064 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
},
12065 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
12066 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
12067 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
12068 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
12069 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
12070 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
12071 /* For V5 or later processors we default to using VFP; but the user
12072 should really set the FPU type explicitly. */
12073 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
},
12074 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
},
12075 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
},
12076 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
},
12077 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
},
12078 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
},
12079 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
},
12080 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
},
12081 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
},
12082 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
},
12083 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
},
12084 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
},
12085 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
},
12086 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
},
12087 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
},
12088 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
},
12089 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
},
12090 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
},
12091 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
},
12092 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
},
12093 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
},
12094 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
},
12095 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
},
12096 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
},
12097 /* ??? XSCALE is really an architecture. */
12098 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
},
12099 /* ??? iwmmxt is not a processor. */
12100 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
},
12101 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
},
12103 {"ep9312", ARM_ARCH_V4T
| ARM_CEXT_MAVERICK
, FPU_ARCH_MAVERICK
},
12107 struct arm_arch_option_table
12114 /* This list should, at a minimum, contain all the architecture names
12115 recognized by GCC. */
12116 static struct arm_arch_option_table arm_archs
[] =
12118 {"all", ARM_ANY
, FPU_ARCH_FPA
},
12119 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
12120 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
12121 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
12122 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
12123 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
12124 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
12125 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
12126 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
12127 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
12128 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
12129 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
12130 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
12131 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
12132 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
12133 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
12134 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
12135 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
12136 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
12137 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
12138 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
12139 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
12140 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
12141 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
12142 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
12143 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
12144 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
12145 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
12149 /* ISA extensions in the co-processor space. */
12150 struct arm_option_value_table
12156 static struct arm_option_value_table arm_extensions
[] =
12158 {"maverick", ARM_CEXT_MAVERICK
},
12159 {"xscale", ARM_CEXT_XSCALE
},
12160 {"iwmmxt", ARM_CEXT_IWMMXT
},
12164 /* This list should, at a minimum, contain all the fpu names
12165 recognized by GCC. */
12166 static struct arm_option_value_table arm_fpus
[] =
12168 {"softfpa", FPU_NONE
},
12169 {"fpe", FPU_ARCH_FPE
},
12170 {"fpe2", FPU_ARCH_FPE
},
12171 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
12172 {"fpa", FPU_ARCH_FPA
},
12173 {"fpa10", FPU_ARCH_FPA
},
12174 {"fpa11", FPU_ARCH_FPA
},
12175 {"arm7500fe", FPU_ARCH_FPA
},
12176 {"softvfp", FPU_ARCH_VFP
},
12177 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
12178 {"vfp", FPU_ARCH_VFP_V2
},
12179 {"vfp9", FPU_ARCH_VFP_V2
},
12180 {"vfp10", FPU_ARCH_VFP_V2
},
12181 {"vfp10-r0", FPU_ARCH_VFP_V1
},
12182 {"vfpxd", FPU_ARCH_VFP_V1xD
},
12183 {"arm1020t", FPU_ARCH_VFP_V1
},
12184 {"arm1020e", FPU_ARCH_VFP_V2
},
12185 {"arm1136jfs", FPU_ARCH_VFP_V2
},
12186 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
12187 {"maverick", FPU_ARCH_MAVERICK
},
12191 static struct arm_option_value_table arm_float_abis
[] =
12193 {"hard", ARM_FLOAT_ABI_HARD
},
12194 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
12195 {"soft", ARM_FLOAT_ABI_SOFT
},
12200 /* We only know how to output GNU and ver 4 (AAELF) formats. */
12201 static struct arm_option_value_table arm_eabis
[] =
12203 {"gnu", EF_ARM_EABI_UNKNOWN
},
12204 {"4", EF_ARM_EABI_VER4
},
12209 struct arm_long_option_table
12211 char * option
; /* Substring to match. */
12212 char * help
; /* Help information. */
12213 int (* func
) (char * subopt
); /* Function to decode sub-option. */
12214 char * deprecated
; /* If non-null, print this message. */
12218 arm_parse_extension (char * str
, int * opt_p
)
12220 while (str
!= NULL
&& *str
!= 0)
12222 struct arm_option_value_table
* opt
;
12228 as_bad (_("invalid architectural extension"));
12233 ext
= strchr (str
, '+');
12236 optlen
= ext
- str
;
12238 optlen
= strlen (str
);
12242 as_bad (_("missing architectural extension"));
12246 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
12247 if (strncmp (opt
->name
, str
, optlen
) == 0)
12249 *opt_p
|= opt
->value
;
12253 if (opt
->name
== NULL
)
12255 as_bad (_("unknown architectural extnsion `%s'"), str
);
12266 arm_parse_cpu (char * str
)
12268 struct arm_cpu_option_table
* opt
;
12269 char * ext
= strchr (str
, '+');
12273 optlen
= ext
- str
;
12275 optlen
= strlen (str
);
12279 as_bad (_("missing cpu name `%s'"), str
);
12283 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
12284 if (strncmp (opt
->name
, str
, optlen
) == 0)
12286 mcpu_cpu_opt
= opt
->value
;
12287 mcpu_fpu_opt
= opt
->default_fpu
;
12290 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
12295 as_bad (_("unknown cpu `%s'"), str
);
12300 arm_parse_arch (char * str
)
12302 struct arm_arch_option_table
*opt
;
12303 char *ext
= strchr (str
, '+');
12307 optlen
= ext
- str
;
12309 optlen
= strlen (str
);
12313 as_bad (_("missing architecture name `%s'"), str
);
12318 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
12319 if (streq (opt
->name
, str
))
12321 march_cpu_opt
= opt
->value
;
12322 march_fpu_opt
= opt
->default_fpu
;
12325 return arm_parse_extension (ext
, &march_cpu_opt
);
12330 as_bad (_("unknown architecture `%s'\n"), str
);
12335 arm_parse_fpu (char * str
)
12337 struct arm_option_value_table
* opt
;
12339 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
12340 if (streq (opt
->name
, str
))
12342 mfpu_opt
= opt
->value
;
12346 as_bad (_("unknown floating point format `%s'\n"), str
);
12351 arm_parse_float_abi (char * str
)
12353 struct arm_option_value_table
* opt
;
12355 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
12356 if (streq (opt
->name
, str
))
12358 mfloat_abi_opt
= opt
->value
;
12362 as_bad (_("unknown floating point abi `%s'\n"), str
);
12368 arm_parse_eabi (char * str
)
12370 struct arm_option_value_table
*opt
;
12372 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
12373 if (streq (opt
->name
, str
))
12375 meabi_flags
= opt
->value
;
12378 as_bad (_("unknown EABI `%s'\n"), str
);
12383 struct arm_long_option_table arm_long_opts
[] =
12385 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
12386 arm_parse_cpu
, NULL
},
12387 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
12388 arm_parse_arch
, NULL
},
12389 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
12390 arm_parse_fpu
, NULL
},
12391 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
12392 arm_parse_float_abi
, NULL
},
12394 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
12395 arm_parse_eabi
, NULL
},
12397 {NULL
, NULL
, 0, NULL
}
12401 md_parse_option (int c
, char * arg
)
12403 struct arm_option_table
*opt
;
12404 struct arm_long_option_table
*lopt
;
12410 target_big_endian
= 1;
12416 target_big_endian
= 0;
12421 /* Listing option. Just ignore these, we don't support additional
12426 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
12428 if (c
== opt
->option
[0]
12429 && ((arg
== NULL
&& opt
->option
[1] == 0)
12430 || streq (arg
, opt
->option
+ 1)))
12432 #if WARN_DEPRECATED
12433 /* If the option is deprecated, tell the user. */
12434 if (opt
->deprecated
!= NULL
)
12435 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
12436 arg
? arg
: "", _(opt
->deprecated
));
12439 if (opt
->var
!= NULL
)
12440 *opt
->var
= opt
->value
;
12446 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
12448 /* These options are expected to have an argument. */
12449 if (c
== lopt
->option
[0]
12451 && strncmp (arg
, lopt
->option
+ 1,
12452 strlen (lopt
->option
+ 1)) == 0)
12454 #if WARN_DEPRECATED
12455 /* If the option is deprecated, tell the user. */
12456 if (lopt
->deprecated
!= NULL
)
12457 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
12458 _(lopt
->deprecated
));
12461 /* Call the sup-option parser. */
12462 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
12473 md_show_usage (FILE * fp
)
12475 struct arm_option_table
*opt
;
12476 struct arm_long_option_table
*lopt
;
12478 fprintf (fp
, _(" ARM-specific assembler options:\n"));
12480 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
12481 if (opt
->help
!= NULL
)
12482 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
12484 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
12485 if (lopt
->help
!= NULL
)
12486 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
12490 -EB assemble code for a big-endian cpu\n"));
12495 -EL assemble code for a little-endian cpu\n"));