1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS
,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result
;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant
;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax
= FALSE
;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set
*legacy_cpu
= NULL
;
158 static const arm_feature_set
*legacy_fpu
= NULL
;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
162 static arm_feature_set
*mcpu_ext_opt
= NULL
;
163 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set
*march_cpu_opt
= NULL
;
167 static arm_feature_set
*march_ext_opt
= NULL
;
168 static const arm_feature_set
*march_fpu_opt
= NULL
;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set
*mfpu_opt
= NULL
;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
176 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
179 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
180 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
182 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
184 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
187 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
190 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
191 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
192 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
193 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
194 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
195 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
196 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
197 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
198 static const arm_feature_set arm_ext_v4t_5
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
200 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
201 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
202 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
203 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
204 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
205 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
206 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
207 /* Only for compatability of hint instructions. */
208 static const arm_feature_set arm_ext_v6k_v6t2
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
210 static const arm_feature_set arm_ext_v6_notm
=
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
212 static const arm_feature_set arm_ext_v6_dsp
=
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
214 static const arm_feature_set arm_ext_barrier
=
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
216 static const arm_feature_set arm_ext_msr
=
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
218 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
219 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
220 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
221 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
223 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
225 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
226 static const arm_feature_set arm_ext_m
=
227 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
228 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
229 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
230 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
231 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
232 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
233 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
234 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
235 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
236 static const arm_feature_set arm_ext_v8m_main
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
238 static const arm_feature_set arm_ext_v8_1m_main
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
240 /* Instructions in ARMv8-M only found in M profile architectures. */
241 static const arm_feature_set arm_ext_v8m_m_only
=
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
243 static const arm_feature_set arm_ext_v6t2_v8m
=
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
245 /* Instructions shared between ARMv8-A and ARMv8-M. */
246 static const arm_feature_set arm_ext_atomics
=
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
249 /* DSP instructions Tag_DSP_extension refers to. */
250 static const arm_feature_set arm_ext_dsp
=
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
253 static const arm_feature_set arm_ext_ras
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
255 /* FP16 instructions. */
256 static const arm_feature_set arm_ext_fp16
=
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
258 static const arm_feature_set arm_ext_fp16_fml
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
260 static const arm_feature_set arm_ext_v8_2
=
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
262 static const arm_feature_set arm_ext_v8_3
=
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
264 static const arm_feature_set arm_ext_sb
=
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
266 static const arm_feature_set arm_ext_predres
=
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
269 static const arm_feature_set arm_arch_any
= ARM_ANY
;
271 static const arm_feature_set fpu_any
= FPU_ANY
;
273 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
274 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
275 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
277 static const arm_feature_set arm_cext_iwmmxt2
=
278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
279 static const arm_feature_set arm_cext_iwmmxt
=
280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
281 static const arm_feature_set arm_cext_xscale
=
282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
283 static const arm_feature_set arm_cext_maverick
=
284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
285 static const arm_feature_set fpu_fpa_ext_v1
=
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
287 static const arm_feature_set fpu_fpa_ext_v2
=
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
289 static const arm_feature_set fpu_vfp_ext_v1xd
=
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
291 static const arm_feature_set fpu_vfp_ext_v1
=
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
293 static const arm_feature_set fpu_vfp_ext_v2
=
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
295 static const arm_feature_set fpu_vfp_ext_v3xd
=
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
297 static const arm_feature_set fpu_vfp_ext_v3
=
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
299 static const arm_feature_set fpu_vfp_ext_d32
=
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
301 static const arm_feature_set fpu_neon_ext_v1
=
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
303 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
305 static const arm_feature_set mve_ext
=
306 ARM_FEATURE_COPROC (FPU_MVE
);
307 static const arm_feature_set mve_fp_ext
=
308 ARM_FEATURE_COPROC (FPU_MVE_FP
);
310 static const arm_feature_set fpu_vfp_fp16
=
311 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
312 static const arm_feature_set fpu_neon_ext_fma
=
313 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
315 static const arm_feature_set fpu_vfp_ext_fma
=
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
317 static const arm_feature_set fpu_vfp_ext_armv8
=
318 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
319 static const arm_feature_set fpu_vfp_ext_armv8xd
=
320 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
321 static const arm_feature_set fpu_neon_ext_armv8
=
322 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
323 static const arm_feature_set fpu_crypto_ext_armv8
=
324 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
325 static const arm_feature_set crc_ext_armv8
=
326 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
327 static const arm_feature_set fpu_neon_ext_v8_1
=
328 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
329 static const arm_feature_set fpu_neon_ext_dotprod
=
330 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
332 static int mfloat_abi_opt
= -1;
333 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
335 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
336 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
338 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
339 /* Feature bits selected by the last -mcpu/-march or by the combination of the
340 last .cpu/.arch directive .arch_extension directives since that
342 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
343 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
344 static arm_feature_set selected_fpu
= FPU_NONE
;
345 /* Feature bits selected by the last .object_arch directive. */
346 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
347 /* Must be long enough to hold any of the names in arm_cpus. */
348 static char selected_cpu_name
[20];
350 extern FLONUM_TYPE generic_floating_point_number
;
352 /* Return if no cpu was selected on command-line. */
354 no_cpu_selected (void)
356 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
361 static int meabi_flags
= EABI_DEFAULT
;
363 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
366 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
371 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
376 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
377 symbolS
* GOT_symbol
;
380 /* 0: assemble for ARM,
381 1: assemble for Thumb,
382 2: assemble for Thumb even though target CPU does not support thumb
384 static int thumb_mode
= 0;
385 /* A value distinct from the possible values for thumb_mode that we
386 can use to record whether thumb_mode has been copied into the
387 tc_frag_data field of a frag. */
388 #define MODE_RECORDED (1 << 4)
390 /* Specifies the intrinsic IT insn behavior mode. */
391 enum implicit_it_mode
393 IMPLICIT_IT_MODE_NEVER
= 0x00,
394 IMPLICIT_IT_MODE_ARM
= 0x01,
395 IMPLICIT_IT_MODE_THUMB
= 0x02,
396 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
398 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
400 /* If unified_syntax is true, we are processing the new unified
401 ARM/Thumb syntax. Important differences from the old ARM mode:
403 - Immediate operands do not require a # prefix.
404 - Conditional affixes always appear at the end of the
405 instruction. (For backward compatibility, those instructions
406 that formerly had them in the middle, continue to accept them
408 - The IT instruction may appear, and if it does is validated
409 against subsequent conditional affixes. It does not generate
412 Important differences from the old Thumb mode:
414 - Immediate operands do not require a # prefix.
415 - Most of the V6T2 instructions are only available in unified mode.
416 - The .N and .W suffixes are recognized and honored (it is an error
417 if they cannot be honored).
418 - All instructions set the flags if and only if they have an 's' affix.
419 - Conditional affixes may be used. They are validated against
420 preceding IT instructions. Unlike ARM mode, you cannot use a
421 conditional affix except in the scope of an IT instruction. */
423 static bfd_boolean unified_syntax
= FALSE
;
425 /* An immediate operand can start with #, and ld*, st*, pld operands
426 can contain [ and ]. We need to tell APP not to elide whitespace
427 before a [, which can appear as the first operand for pld.
428 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
429 const char arm_symbol_chars
[] = "#[]{}";
444 enum neon_el_type type
;
448 #define NEON_MAX_TYPE_ELS 4
452 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
456 enum pred_instruction_type
462 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
463 if inside, should be the last one. */
464 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
465 i.e. BKPT and NOP. */
466 IT_INSN
, /* The IT insn has been parsed. */
467 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
468 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
469 a predication code. */
470 MVE_UNPREDICABLE_INSN
/* MVE instruction that is non-predicable. */
473 /* The maximum number of operands we need. */
474 #define ARM_IT_MAX_OPERANDS 6
475 #define ARM_IT_MAX_RELOCS 3
480 unsigned long instruction
;
484 /* "uncond_value" is set to the value in place of the conditional field in
485 unconditional versions of the instruction, or -1 if nothing is
488 struct neon_type vectype
;
489 /* This does not indicate an actual NEON instruction, only that
490 the mnemonic accepts neon-style type suffixes. */
492 /* Set to the opcode if the instruction needs relaxation.
493 Zero if the instruction is not relaxed. */
497 bfd_reloc_code_real_type type
;
500 } relocs
[ARM_IT_MAX_RELOCS
];
502 enum pred_instruction_type pred_insn_type
;
508 struct neon_type_el vectype
;
509 unsigned present
: 1; /* Operand present. */
510 unsigned isreg
: 1; /* Operand was a register. */
511 unsigned immisreg
: 2; /* .imm field is a second register.
512 0: imm, 1: gpr, 2: MVE Q-register. */
513 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
517 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
518 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
519 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
520 instructions. This allows us to disambiguate ARM <-> vector insns. */
521 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
522 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
523 unsigned isquad
: 1; /* Operand is SIMD quad register. */
524 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
525 unsigned iszr
: 1; /* Operand is ZR register. */
526 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
527 unsigned writeback
: 1; /* Operand has trailing ! */
528 unsigned preind
: 1; /* Preindexed address. */
529 unsigned postind
: 1; /* Postindexed address. */
530 unsigned negative
: 1; /* Index register was negated. */
531 unsigned shifted
: 1; /* Shift applied to operation. */
532 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
533 } operands
[ARM_IT_MAX_OPERANDS
];
536 static struct arm_it inst
;
538 #define NUM_FLOAT_VALS 8
540 const char * fp_const
[] =
542 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
545 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
555 #define CP_T_X 0x00008000
556 #define CP_T_Y 0x00400000
558 #define CONDS_BIT 0x00100000
559 #define LOAD_BIT 0x00100000
561 #define DOUBLE_LOAD_FLAG 0x00000001
565 const char * template_name
;
569 #define COND_ALWAYS 0xE
573 const char * template_name
;
577 struct asm_barrier_opt
579 const char * template_name
;
581 const arm_feature_set arch
;
584 /* The bit that distinguishes CPSR and SPSR. */
585 #define SPSR_BIT (1 << 22)
587 /* The individual PSR flag bits. */
588 #define PSR_c (1 << 16)
589 #define PSR_x (1 << 17)
590 #define PSR_s (1 << 18)
591 #define PSR_f (1 << 19)
596 bfd_reloc_code_real_type reloc
;
601 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
602 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
607 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
610 /* Bits for DEFINED field in neon_typed_alias. */
611 #define NTA_HASTYPE 1
612 #define NTA_HASINDEX 2
614 struct neon_typed_alias
616 unsigned char defined
;
618 struct neon_type_el eltype
;
621 /* ARM register categories. This includes coprocessor numbers and various
622 architecture extensions' registers. Each entry should have an error message
623 in reg_expected_msgs below. */
653 /* Structure for a hash table entry for a register.
654 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
655 information which states whether a vector type or index is specified (for a
656 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
662 unsigned char builtin
;
663 struct neon_typed_alias
* neon
;
666 /* Diagnostics used when we don't get a register of the expected type. */
667 const char * const reg_expected_msgs
[] =
669 [REG_TYPE_RN
] = N_("ARM register expected"),
670 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
671 [REG_TYPE_CN
] = N_("co-processor register expected"),
672 [REG_TYPE_FN
] = N_("FPA register expected"),
673 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
674 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
675 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
676 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
677 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
678 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
679 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
681 [REG_TYPE_VFC
] = N_("VFP system register expected"),
682 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
683 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
684 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
685 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
686 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
687 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
688 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
689 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
690 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
691 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
692 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
693 [REG_TYPE_RNB
] = N_("")
696 /* Some well known registers that we refer to directly elsewhere. */
702 /* ARM instructions take 4bytes in the object file, Thumb instructions
708 /* Basic string to match. */
709 const char * template_name
;
711 /* Parameters to instruction. */
712 unsigned int operands
[8];
714 /* Conditional tag - see opcode_lookup. */
715 unsigned int tag
: 4;
717 /* Basic instruction code. */
720 /* Thumb-format instruction code. */
723 /* Which architecture variant provides this instruction. */
724 const arm_feature_set
* avariant
;
725 const arm_feature_set
* tvariant
;
727 /* Function to call to encode instruction in ARM format. */
728 void (* aencode
) (void);
730 /* Function to call to encode instruction in Thumb format. */
731 void (* tencode
) (void);
733 /* Indicates whether this instruction may be vector predicated. */
734 unsigned int mayBeVecPred
: 1;
737 /* Defines for various bits that we will want to toggle. */
738 #define INST_IMMEDIATE 0x02000000
739 #define OFFSET_REG 0x02000000
740 #define HWOFFSET_IMM 0x00400000
741 #define SHIFT_BY_REG 0x00000010
742 #define PRE_INDEX 0x01000000
743 #define INDEX_UP 0x00800000
744 #define WRITE_BACK 0x00200000
745 #define LDM_TYPE_2_OR_3 0x00400000
746 #define CPSI_MMOD 0x00020000
748 #define LITERAL_MASK 0xf000f000
749 #define OPCODE_MASK 0xfe1fffff
750 #define V4_STR_BIT 0x00000020
751 #define VLDR_VMOV_SAME 0x0040f000
753 #define T2_SUBS_PC_LR 0xf3de8f00
755 #define DATA_OP_SHIFT 21
756 #define SBIT_SHIFT 20
758 #define T2_OPCODE_MASK 0xfe1fffff
759 #define T2_DATA_OP_SHIFT 21
760 #define T2_SBIT_SHIFT 20
762 #define A_COND_MASK 0xf0000000
763 #define A_PUSH_POP_OP_MASK 0x0fff0000
765 /* Opcodes for pushing/poping registers to/from the stack. */
766 #define A1_OPCODE_PUSH 0x092d0000
767 #define A2_OPCODE_PUSH 0x052d0004
768 #define A2_OPCODE_POP 0x049d0004
770 /* Codes to distinguish the arithmetic instructions. */
781 #define OPCODE_CMP 10
782 #define OPCODE_CMN 11
783 #define OPCODE_ORR 12
784 #define OPCODE_MOV 13
785 #define OPCODE_BIC 14
786 #define OPCODE_MVN 15
788 #define T2_OPCODE_AND 0
789 #define T2_OPCODE_BIC 1
790 #define T2_OPCODE_ORR 2
791 #define T2_OPCODE_ORN 3
792 #define T2_OPCODE_EOR 4
793 #define T2_OPCODE_ADD 8
794 #define T2_OPCODE_ADC 10
795 #define T2_OPCODE_SBC 11
796 #define T2_OPCODE_SUB 13
797 #define T2_OPCODE_RSB 14
799 #define T_OPCODE_MUL 0x4340
800 #define T_OPCODE_TST 0x4200
801 #define T_OPCODE_CMN 0x42c0
802 #define T_OPCODE_NEG 0x4240
803 #define T_OPCODE_MVN 0x43c0
805 #define T_OPCODE_ADD_R3 0x1800
806 #define T_OPCODE_SUB_R3 0x1a00
807 #define T_OPCODE_ADD_HI 0x4400
808 #define T_OPCODE_ADD_ST 0xb000
809 #define T_OPCODE_SUB_ST 0xb080
810 #define T_OPCODE_ADD_SP 0xa800
811 #define T_OPCODE_ADD_PC 0xa000
812 #define T_OPCODE_ADD_I8 0x3000
813 #define T_OPCODE_SUB_I8 0x3800
814 #define T_OPCODE_ADD_I3 0x1c00
815 #define T_OPCODE_SUB_I3 0x1e00
817 #define T_OPCODE_ASR_R 0x4100
818 #define T_OPCODE_LSL_R 0x4080
819 #define T_OPCODE_LSR_R 0x40c0
820 #define T_OPCODE_ROR_R 0x41c0
821 #define T_OPCODE_ASR_I 0x1000
822 #define T_OPCODE_LSL_I 0x0000
823 #define T_OPCODE_LSR_I 0x0800
825 #define T_OPCODE_MOV_I8 0x2000
826 #define T_OPCODE_CMP_I8 0x2800
827 #define T_OPCODE_CMP_LR 0x4280
828 #define T_OPCODE_MOV_HR 0x4600
829 #define T_OPCODE_CMP_HR 0x4500
831 #define T_OPCODE_LDR_PC 0x4800
832 #define T_OPCODE_LDR_SP 0x9800
833 #define T_OPCODE_STR_SP 0x9000
834 #define T_OPCODE_LDR_IW 0x6800
835 #define T_OPCODE_STR_IW 0x6000
836 #define T_OPCODE_LDR_IH 0x8800
837 #define T_OPCODE_STR_IH 0x8000
838 #define T_OPCODE_LDR_IB 0x7800
839 #define T_OPCODE_STR_IB 0x7000
840 #define T_OPCODE_LDR_RW 0x5800
841 #define T_OPCODE_STR_RW 0x5000
842 #define T_OPCODE_LDR_RH 0x5a00
843 #define T_OPCODE_STR_RH 0x5200
844 #define T_OPCODE_LDR_RB 0x5c00
845 #define T_OPCODE_STR_RB 0x5400
847 #define T_OPCODE_PUSH 0xb400
848 #define T_OPCODE_POP 0xbc00
850 #define T_OPCODE_BRANCH 0xe000
852 #define THUMB_SIZE 2 /* Size of thumb instruction. */
853 #define THUMB_PP_PC_LR 0x0100
854 #define THUMB_LOAD_BIT 0x0800
855 #define THUMB2_LOAD_BIT 0x00100000
857 #define BAD_SYNTAX _("syntax error")
858 #define BAD_ARGS _("bad arguments to instruction")
859 #define BAD_SP _("r13 not allowed here")
860 #define BAD_PC _("r15 not allowed here")
861 #define BAD_ODD _("Odd register not allowed here")
862 #define BAD_EVEN _("Even register not allowed here")
863 #define BAD_COND _("instruction cannot be conditional")
864 #define BAD_OVERLAP _("registers may not be the same")
865 #define BAD_HIREG _("lo register required")
866 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
867 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
868 #define BAD_BRANCH _("branch must be last instruction in IT block")
869 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
870 #define BAD_NOT_IT _("instruction not allowed in IT block")
871 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
872 #define BAD_FPU _("selected FPU does not support instruction")
873 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
874 #define BAD_OUT_VPT \
875 _("vector predicated instruction should be in VPT/VPST block")
876 #define BAD_IT_COND _("incorrect condition in IT block")
877 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
878 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
879 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
880 #define BAD_PC_ADDRESSING \
881 _("cannot use register index with PC-relative addressing")
882 #define BAD_PC_WRITEBACK \
883 _("cannot use writeback with PC-relative addressing")
884 #define BAD_RANGE _("branch out of range")
885 #define BAD_FP16 _("selected processor does not support fp16 instruction")
886 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
887 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
888 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
890 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
892 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
894 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
896 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
897 #define BAD_MVE_AUTO \
898 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
899 " use a valid -march or -mcpu option.")
900 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
901 "and source operands makes instruction UNPREDICTABLE")
902 #define BAD_EL_TYPE _("bad element type for instruction")
903 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
905 static struct hash_control
* arm_ops_hsh
;
906 static struct hash_control
* arm_cond_hsh
;
907 static struct hash_control
* arm_vcond_hsh
;
908 static struct hash_control
* arm_shift_hsh
;
909 static struct hash_control
* arm_psr_hsh
;
910 static struct hash_control
* arm_v7m_psr_hsh
;
911 static struct hash_control
* arm_reg_hsh
;
912 static struct hash_control
* arm_reloc_hsh
;
913 static struct hash_control
* arm_barrier_opt_hsh
;
915 /* Stuff needed to resolve the label ambiguity
924 symbolS
* last_label_seen
;
925 static int label_is_thumb_function_name
= FALSE
;
927 /* Literal pool structure. Held on a per-section
928 and per-sub-section basis. */
930 #define MAX_LITERAL_POOL_SIZE 1024
931 typedef struct literal_pool
933 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
934 unsigned int next_free_entry
;
940 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
942 struct literal_pool
* next
;
943 unsigned int alignment
;
946 /* Pointer to a linked list of literal pools. */
947 literal_pool
* list_of_pools
= NULL
;
949 typedef enum asmfunc_states
952 WAITING_ASMFUNC_NAME
,
956 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
959 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
961 static struct current_pred now_pred
;
965 now_pred_compatible (int cond
)
967 return (cond
& ~1) == (now_pred
.cc
& ~1);
971 conditional_insn (void)
973 return inst
.cond
!= COND_ALWAYS
;
976 static int in_pred_block (void);
978 static int handle_pred_state (void);
980 static void force_automatic_it_block_close (void);
982 static void it_fsm_post_encode (void);
984 #define set_pred_insn_type(type) \
987 inst.pred_insn_type = type; \
988 if (handle_pred_state () == FAIL) \
993 #define set_pred_insn_type_nonvoid(type, failret) \
996 inst.pred_insn_type = type; \
997 if (handle_pred_state () == FAIL) \
1002 #define set_pred_insn_type_last() \
1005 if (inst.cond == COND_ALWAYS) \
1006 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1008 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1012 /* Toggle value[pos]. */
1013 #define TOGGLE_BIT(value, pos) (value ^ (1 << pos))
1017 /* This array holds the chars that always start a comment. If the
1018 pre-processor is disabled, these aren't very useful. */
1019 char arm_comment_chars
[] = "@";
1021 /* This array holds the chars that only start a comment at the beginning of
1022 a line. If the line seems to have the form '# 123 filename'
1023 .line and .file directives will appear in the pre-processed output. */
1024 /* Note that input_file.c hand checks for '#' at the beginning of the
1025 first line of the input file. This is because the compiler outputs
1026 #NO_APP at the beginning of its output. */
1027 /* Also note that comments like this one will always work. */
1028 const char line_comment_chars
[] = "#";
1030 char arm_line_separator_chars
[] = ";";
1032 /* Chars that can be used to separate mant
1033 from exp in floating point numbers. */
1034 const char EXP_CHARS
[] = "eE";
1036 /* Chars that mean this number is a floating point constant. */
1037 /* As in 0f12.456 */
1038 /* or 0d1.2345e12 */
1040 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
1042 /* Prefix characters that indicate the start of an immediate
1044 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1046 /* Separator character handling. */
1048 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1051 skip_past_char (char ** str
, char c
)
1053 /* PR gas/14987: Allow for whitespace before the expected character. */
1054 skip_whitespace (*str
);
1065 #define skip_past_comma(str) skip_past_char (str, ',')
1067 /* Arithmetic expressions (possibly involving symbols). */
1069 /* Return TRUE if anything in the expression is a bignum. */
1072 walk_no_bignums (symbolS
* sp
)
1074 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1077 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1079 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1080 || (symbol_get_value_expression (sp
)->X_op_symbol
1081 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1087 static bfd_boolean in_my_get_expression
= FALSE
;
1089 /* Third argument to my_get_expression. */
1090 #define GE_NO_PREFIX 0
1091 #define GE_IMM_PREFIX 1
1092 #define GE_OPT_PREFIX 2
1093 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1094 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1095 #define GE_OPT_PREFIX_BIG 3
1098 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1102 /* In unified syntax, all prefixes are optional. */
1104 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1107 switch (prefix_mode
)
1109 case GE_NO_PREFIX
: break;
1111 if (!is_immediate_prefix (**str
))
1113 inst
.error
= _("immediate expression requires a # prefix");
1119 case GE_OPT_PREFIX_BIG
:
1120 if (is_immediate_prefix (**str
))
1127 memset (ep
, 0, sizeof (expressionS
));
1129 save_in
= input_line_pointer
;
1130 input_line_pointer
= *str
;
1131 in_my_get_expression
= TRUE
;
1133 in_my_get_expression
= FALSE
;
1135 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1137 /* We found a bad or missing expression in md_operand(). */
1138 *str
= input_line_pointer
;
1139 input_line_pointer
= save_in
;
1140 if (inst
.error
== NULL
)
1141 inst
.error
= (ep
->X_op
== O_absent
1142 ? _("missing expression") :_("bad expression"));
1146 /* Get rid of any bignums now, so that we don't generate an error for which
1147 we can't establish a line number later on. Big numbers are never valid
1148 in instructions, which is where this routine is always called. */
1149 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1150 && (ep
->X_op
== O_big
1151 || (ep
->X_add_symbol
1152 && (walk_no_bignums (ep
->X_add_symbol
)
1154 && walk_no_bignums (ep
->X_op_symbol
))))))
1156 inst
.error
= _("invalid constant");
1157 *str
= input_line_pointer
;
1158 input_line_pointer
= save_in
;
1162 *str
= input_line_pointer
;
1163 input_line_pointer
= save_in
;
1167 /* Turn a string in input_line_pointer into a floating point constant
1168 of type TYPE, and store the appropriate bytes in *LITP. The number
1169 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1170 returned, or NULL on OK.
1172 Note that fp constants aren't represent in the normal way on the ARM.
1173 In big endian mode, things are as expected. However, in little endian
1174 mode fp constants are big-endian word-wise, and little-endian byte-wise
1175 within the words. For example, (double) 1.1 in big endian mode is
1176 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1177 the byte sequence 99 99 f1 3f 9a 99 99 99.
1179 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1182 md_atof (int type
, char * litP
, int * sizeP
)
1185 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1217 return _("Unrecognized or unsupported floating point constant");
1220 t
= atof_ieee (input_line_pointer
, type
, words
);
1222 input_line_pointer
= t
;
1223 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1225 if (target_big_endian
)
1227 for (i
= 0; i
< prec
; i
++)
1229 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1230 litP
+= sizeof (LITTLENUM_TYPE
);
1235 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1236 for (i
= prec
- 1; i
>= 0; i
--)
1238 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1239 litP
+= sizeof (LITTLENUM_TYPE
);
1242 /* For a 4 byte float the order of elements in `words' is 1 0.
1243 For an 8 byte float the order is 1 0 3 2. */
1244 for (i
= 0; i
< prec
; i
+= 2)
1246 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1247 sizeof (LITTLENUM_TYPE
));
1248 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1249 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1250 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1257 /* We handle all bad expressions here, so that we can report the faulty
1258 instruction in the error message. */
1261 md_operand (expressionS
* exp
)
1263 if (in_my_get_expression
)
1264 exp
->X_op
= O_illegal
;
1267 /* Immediate values. */
1270 /* Generic immediate-value read function for use in directives.
1271 Accepts anything that 'expression' can fold to a constant.
1272 *val receives the number. */
1275 immediate_for_directive (int *val
)
1278 exp
.X_op
= O_illegal
;
1280 if (is_immediate_prefix (*input_line_pointer
))
1282 input_line_pointer
++;
1286 if (exp
.X_op
!= O_constant
)
1288 as_bad (_("expected #constant"));
1289 ignore_rest_of_line ();
1292 *val
= exp
.X_add_number
;
1297 /* Register parsing. */
1299 /* Generic register parser. CCP points to what should be the
1300 beginning of a register name. If it is indeed a valid register
1301 name, advance CCP over it and return the reg_entry structure;
1302 otherwise return NULL. Does not issue diagnostics. */
1304 static struct reg_entry
*
1305 arm_reg_parse_multi (char **ccp
)
1309 struct reg_entry
*reg
;
1311 skip_whitespace (start
);
1313 #ifdef REGISTER_PREFIX
1314 if (*start
!= REGISTER_PREFIX
)
1318 #ifdef OPTIONAL_REGISTER_PREFIX
1319 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1324 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1329 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1331 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1341 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1342 enum arm_reg_type type
)
1344 /* Alternative syntaxes are accepted for a few register classes. */
1351 /* Generic coprocessor register names are allowed for these. */
1352 if (reg
&& reg
->type
== REG_TYPE_CN
)
1357 /* For backward compatibility, a bare number is valid here. */
1359 unsigned long processor
= strtoul (start
, ccp
, 10);
1360 if (*ccp
!= start
&& processor
<= 15)
1365 case REG_TYPE_MMXWC
:
1366 /* WC includes WCG. ??? I'm not sure this is true for all
1367 instructions that take WC registers. */
1368 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1379 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1380 return value is the register number or FAIL. */
1383 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1386 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1389 /* Do not allow a scalar (reg+index) to parse as a register. */
1390 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1393 if (reg
&& reg
->type
== type
)
1396 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1403 /* Parse a Neon type specifier. *STR should point at the leading '.'
1404 character. Does no verification at this stage that the type fits the opcode
1411 Can all be legally parsed by this function.
1413 Fills in neon_type struct pointer with parsed information, and updates STR
1414 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1415 type, FAIL if not. */
1418 parse_neon_type (struct neon_type
*type
, char **str
)
1425 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1427 enum neon_el_type thistype
= NT_untyped
;
1428 unsigned thissize
= -1u;
1435 /* Just a size without an explicit type. */
1439 switch (TOLOWER (*ptr
))
1441 case 'i': thistype
= NT_integer
; break;
1442 case 'f': thistype
= NT_float
; break;
1443 case 'p': thistype
= NT_poly
; break;
1444 case 's': thistype
= NT_signed
; break;
1445 case 'u': thistype
= NT_unsigned
; break;
1447 thistype
= NT_float
;
1452 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1458 /* .f is an abbreviation for .f32. */
1459 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1464 thissize
= strtoul (ptr
, &ptr
, 10);
1466 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1469 as_bad (_("bad size %d in type specifier"), thissize
);
1477 type
->el
[type
->elems
].type
= thistype
;
1478 type
->el
[type
->elems
].size
= thissize
;
1483 /* Empty/missing type is not a successful parse. */
1484 if (type
->elems
== 0)
1492 /* Errors may be set multiple times during parsing or bit encoding
1493 (particularly in the Neon bits), but usually the earliest error which is set
1494 will be the most meaningful. Avoid overwriting it with later (cascading)
1495 errors by calling this function. */
1498 first_error (const char *err
)
1504 /* Parse a single type, e.g. ".s32", leading period included. */
1506 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1509 struct neon_type optype
;
1513 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1515 if (optype
.elems
== 1)
1516 *vectype
= optype
.el
[0];
1519 first_error (_("only one type should be specified for operand"));
1525 first_error (_("vector type expected"));
1537 /* Special meanings for indices (which have a range of 0-7), which will fit into
1540 #define NEON_ALL_LANES 15
1541 #define NEON_INTERLEAVE_LANES 14
1543 /* Record a use of the given feature. */
1545 record_feature_use (const arm_feature_set
*feature
)
1548 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1550 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1553 /* If the given feature available in the selected CPU, mark it as used.
1554 Returns TRUE iff feature is available. */
1556 mark_feature_used (const arm_feature_set
*feature
)
1559 /* Do not support the use of MVE only instructions when in auto-detection or
1561 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1562 && ARM_CPU_IS_ANY (cpu_variant
))
1564 first_error (BAD_MVE_AUTO
);
1567 /* Ensure the option is valid on the current architecture. */
1568 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1571 /* Add the appropriate architecture feature for the barrier option used.
1573 record_feature_use (feature
);
1578 /* Parse either a register or a scalar, with an optional type. Return the
1579 register number, and optionally fill in the actual type of the register
1580 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1581 type/index information in *TYPEINFO. */
1584 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1585 enum arm_reg_type
*rtype
,
1586 struct neon_typed_alias
*typeinfo
)
1589 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1590 struct neon_typed_alias atype
;
1591 struct neon_type_el parsetype
;
1595 atype
.eltype
.type
= NT_invtype
;
1596 atype
.eltype
.size
= -1;
1598 /* Try alternate syntax for some types of register. Note these are mutually
1599 exclusive with the Neon syntax extensions. */
1602 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1610 /* Undo polymorphism when a set of register types may be accepted. */
1611 if ((type
== REG_TYPE_NDQ
1612 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1613 || (type
== REG_TYPE_VFSD
1614 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1615 || (type
== REG_TYPE_NSDQ
1616 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1617 || reg
->type
== REG_TYPE_NQ
))
1618 || (type
== REG_TYPE_NSD
1619 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1620 || (type
== REG_TYPE_MMXWC
1621 && (reg
->type
== REG_TYPE_MMXWCG
)))
1622 type
= (enum arm_reg_type
) reg
->type
;
1624 if (type
== REG_TYPE_MQ
)
1626 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1629 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1632 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1634 first_error (_("expected MVE register [q0..q7]"));
1639 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1640 && (type
== REG_TYPE_NQ
))
1644 if (type
!= reg
->type
)
1650 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1652 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1654 first_error (_("can't redefine type for operand"));
1657 atype
.defined
|= NTA_HASTYPE
;
1658 atype
.eltype
= parsetype
;
1661 if (skip_past_char (&str
, '[') == SUCCESS
)
1663 if (type
!= REG_TYPE_VFD
1664 && !(type
== REG_TYPE_VFS
1665 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1666 && !(type
== REG_TYPE_NQ
1667 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1669 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1670 first_error (_("only D and Q registers may be indexed"));
1672 first_error (_("only D registers may be indexed"));
1676 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1678 first_error (_("can't change index for operand"));
1682 atype
.defined
|= NTA_HASINDEX
;
1684 if (skip_past_char (&str
, ']') == SUCCESS
)
1685 atype
.index
= NEON_ALL_LANES
;
1690 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1692 if (exp
.X_op
!= O_constant
)
1694 first_error (_("constant expression required"));
1698 if (skip_past_char (&str
, ']') == FAIL
)
1701 atype
.index
= exp
.X_add_number
;
1716 /* Like arm_reg_parse, but also allow the following extra features:
1717 - If RTYPE is non-zero, return the (possibly restricted) type of the
1718 register (e.g. Neon double or quad reg when either has been requested).
1719 - If this is a Neon vector type with additional type information, fill
1720 in the struct pointed to by VECTYPE (if non-NULL).
1721 This function will fault on encountering a scalar. */
1724 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1725 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1727 struct neon_typed_alias atype
;
1729 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1734 /* Do not allow regname(... to parse as a register. */
1738 /* Do not allow a scalar (reg+index) to parse as a register. */
1739 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1741 first_error (_("register operand expected, but got scalar"));
1746 *vectype
= atype
.eltype
;
1753 #define NEON_SCALAR_REG(X) ((X) >> 4)
1754 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1756 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1757 have enough information to be able to do a good job bounds-checking. So, we
1758 just do easy checks here, and do further checks later. */
1761 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1762 arm_reg_type reg_type
)
1766 struct neon_typed_alias atype
;
1769 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1787 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1790 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1792 first_error (_("scalar must have an index"));
1795 else if (atype
.index
>= reg_size
/ elsize
)
1797 first_error (_("scalar index out of range"));
1802 *type
= atype
.eltype
;
1806 return reg
* 16 + atype
.index
;
1809 /* Types of registers in a list. */
1822 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1825 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1831 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1833 /* We come back here if we get ranges concatenated by '+' or '|'. */
1836 skip_whitespace (str
);
1849 const char apsr_str
[] = "apsr";
1850 int apsr_str_len
= strlen (apsr_str
);
1852 reg
= arm_reg_parse (&str
, REGLIST_RN
);
1853 if (etype
== REGLIST_CLRM
)
1855 if (reg
== REG_SP
|| reg
== REG_PC
)
1857 else if (reg
== FAIL
1858 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1859 && !ISALPHA (*(str
+ apsr_str_len
)))
1862 str
+= apsr_str_len
;
1867 first_error (_("r0-r12, lr or APSR expected"));
1871 else /* etype == REGLIST_RN. */
1875 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
1886 first_error (_("bad range in register list"));
1890 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1892 if (range
& (1 << i
))
1894 (_("Warning: duplicated register (r%d) in register list"),
1902 if (range
& (1 << reg
))
1903 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1905 else if (reg
<= cur_reg
)
1906 as_tsktsk (_("Warning: register range not in ascending order"));
1911 while (skip_past_comma (&str
) != FAIL
1912 || (in_range
= 1, *str
++ == '-'));
1915 if (skip_past_char (&str
, '}') == FAIL
)
1917 first_error (_("missing `}'"));
1921 else if (etype
== REGLIST_RN
)
1925 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1928 if (exp
.X_op
== O_constant
)
1930 if (exp
.X_add_number
1931 != (exp
.X_add_number
& 0x0000ffff))
1933 inst
.error
= _("invalid register mask");
1937 if ((range
& exp
.X_add_number
) != 0)
1939 int regno
= range
& exp
.X_add_number
;
1942 regno
= (1 << regno
) - 1;
1944 (_("Warning: duplicated register (r%d) in register list"),
1948 range
|= exp
.X_add_number
;
1952 if (inst
.relocs
[0].type
!= 0)
1954 inst
.error
= _("expression too complex");
1958 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
1959 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
1960 inst
.relocs
[0].pc_rel
= 0;
1964 if (*str
== '|' || *str
== '+')
1970 while (another_range
);
1976 /* Parse a VFP register list. If the string is invalid return FAIL.
1977 Otherwise return the number of registers, and set PBASE to the first
1978 register. Parses registers of type ETYPE.
1979 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1980 - Q registers can be used to specify pairs of D registers
1981 - { } can be omitted from around a singleton register list
1982 FIXME: This is not implemented, as it would require backtracking in
1985 This could be done (the meaning isn't really ambiguous), but doesn't
1986 fit in well with the current parsing framework.
1987 - 32 D registers may be used (also true for VFPv3).
1988 FIXME: Types are ignored in these register lists, which is probably a
1992 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
1993 bfd_boolean
*partial_match
)
1998 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
2002 unsigned long mask
= 0;
2004 bfd_boolean vpr_seen
= FALSE
;
2005 bfd_boolean expect_vpr
=
2006 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2008 if (skip_past_char (&str
, '{') == FAIL
)
2010 inst
.error
= _("expecting {");
2017 case REGLIST_VFP_S_VPR
:
2018 regtype
= REG_TYPE_VFS
;
2023 case REGLIST_VFP_D_VPR
:
2024 regtype
= REG_TYPE_VFD
;
2027 case REGLIST_NEON_D
:
2028 regtype
= REG_TYPE_NDQ
;
2035 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2037 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2038 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2042 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2045 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2052 base_reg
= max_regs
;
2053 *partial_match
= FALSE
;
2057 int setmask
= 1, addregs
= 1;
2058 const char vpr_str
[] = "vpr";
2059 int vpr_str_len
= strlen (vpr_str
);
2061 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2065 if (new_base
== FAIL
2066 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2067 && !ISALPHA (*(str
+ vpr_str_len
))
2073 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2077 first_error (_("VPR expected last"));
2080 else if (new_base
== FAIL
)
2082 if (regtype
== REG_TYPE_VFS
)
2083 first_error (_("VFP single precision register or VPR "
2085 else /* regtype == REG_TYPE_VFD. */
2086 first_error (_("VFP/Neon double precision register or VPR "
2091 else if (new_base
== FAIL
)
2093 first_error (_(reg_expected_msgs
[regtype
]));
2097 *partial_match
= TRUE
;
2101 if (new_base
>= max_regs
)
2103 first_error (_("register out of range in list"));
2107 /* Note: a value of 2 * n is returned for the register Q<n>. */
2108 if (regtype
== REG_TYPE_NQ
)
2114 if (new_base
< base_reg
)
2115 base_reg
= new_base
;
2117 if (mask
& (setmask
<< new_base
))
2119 first_error (_("invalid register list"));
2123 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2125 as_tsktsk (_("register list not in ascending order"));
2129 mask
|= setmask
<< new_base
;
2132 if (*str
== '-') /* We have the start of a range expression */
2138 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2141 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2145 if (high_range
>= max_regs
)
2147 first_error (_("register out of range in list"));
2151 if (regtype
== REG_TYPE_NQ
)
2152 high_range
= high_range
+ 1;
2154 if (high_range
<= new_base
)
2156 inst
.error
= _("register range not in ascending order");
2160 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2162 if (mask
& (setmask
<< new_base
))
2164 inst
.error
= _("invalid register list");
2168 mask
|= setmask
<< new_base
;
2173 while (skip_past_comma (&str
) != FAIL
);
2177 /* Sanity check -- should have raised a parse error above. */
2178 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2183 if (expect_vpr
&& !vpr_seen
)
2185 first_error (_("VPR expected last"));
2189 /* Final test -- the registers must be consecutive. */
2191 for (i
= 0; i
< count
; i
++)
2193 if ((mask
& (1u << i
)) == 0)
2195 inst
.error
= _("non-contiguous register range");
2205 /* True if two alias types are the same. */
2208 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2216 if (a
->defined
!= b
->defined
)
2219 if ((a
->defined
& NTA_HASTYPE
) != 0
2220 && (a
->eltype
.type
!= b
->eltype
.type
2221 || a
->eltype
.size
!= b
->eltype
.size
))
2224 if ((a
->defined
& NTA_HASINDEX
) != 0
2225 && (a
->index
!= b
->index
))
2231 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2232 The base register is put in *PBASE.
2233 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2235 The register stride (minus one) is put in bit 4 of the return value.
2236 Bits [6:5] encode the list length (minus one).
2237 The type of the list elements is put in *ELTYPE, if non-NULL. */
2239 #define NEON_LANE(X) ((X) & 0xf)
2240 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2241 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2244 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2246 struct neon_type_el
*eltype
)
2253 int leading_brace
= 0;
2254 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2255 const char *const incr_error
= mve
? _("register stride must be 1") :
2256 _("register stride must be 1 or 2");
2257 const char *const type_error
= _("mismatched element/structure types in list");
2258 struct neon_typed_alias firsttype
;
2259 firsttype
.defined
= 0;
2260 firsttype
.eltype
.type
= NT_invtype
;
2261 firsttype
.eltype
.size
= -1;
2262 firsttype
.index
= -1;
2264 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2269 struct neon_typed_alias atype
;
2271 rtype
= REG_TYPE_MQ
;
2272 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2276 first_error (_(reg_expected_msgs
[rtype
]));
2283 if (rtype
== REG_TYPE_NQ
)
2289 else if (reg_incr
== -1)
2291 reg_incr
= getreg
- base_reg
;
2292 if (reg_incr
< 1 || reg_incr
> 2)
2294 first_error (_(incr_error
));
2298 else if (getreg
!= base_reg
+ reg_incr
* count
)
2300 first_error (_(incr_error
));
2304 if (! neon_alias_types_same (&atype
, &firsttype
))
2306 first_error (_(type_error
));
2310 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2314 struct neon_typed_alias htype
;
2315 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2317 lane
= NEON_INTERLEAVE_LANES
;
2318 else if (lane
!= NEON_INTERLEAVE_LANES
)
2320 first_error (_(type_error
));
2325 else if (reg_incr
!= 1)
2327 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2331 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2334 first_error (_(reg_expected_msgs
[rtype
]));
2337 if (! neon_alias_types_same (&htype
, &firsttype
))
2339 first_error (_(type_error
));
2342 count
+= hireg
+ dregs
- getreg
;
2346 /* If we're using Q registers, we can't use [] or [n] syntax. */
2347 if (rtype
== REG_TYPE_NQ
)
2353 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2357 else if (lane
!= atype
.index
)
2359 first_error (_(type_error
));
2363 else if (lane
== -1)
2364 lane
= NEON_INTERLEAVE_LANES
;
2365 else if (lane
!= NEON_INTERLEAVE_LANES
)
2367 first_error (_(type_error
));
2372 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2374 /* No lane set by [x]. We must be interleaving structures. */
2376 lane
= NEON_INTERLEAVE_LANES
;
2379 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2380 || (count
> 1 && reg_incr
== -1))
2382 first_error (_("error parsing element/structure list"));
2386 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2388 first_error (_("expected }"));
2396 *eltype
= firsttype
.eltype
;
2401 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2404 /* Parse an explicit relocation suffix on an expression. This is
2405 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2406 arm_reloc_hsh contains no entries, so this function can only
2407 succeed if there is no () after the word. Returns -1 on error,
2408 BFD_RELOC_UNUSED if there wasn't any suffix. */
2411 parse_reloc (char **str
)
2413 struct reloc_entry
*r
;
2417 return BFD_RELOC_UNUSED
;
2422 while (*q
&& *q
!= ')' && *q
!= ',')
2427 if ((r
= (struct reloc_entry
*)
2428 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2435 /* Directives: register aliases. */
2437 static struct reg_entry
*
2438 insert_reg_alias (char *str
, unsigned number
, int type
)
2440 struct reg_entry
*new_reg
;
2443 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2445 if (new_reg
->builtin
)
2446 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2448 /* Only warn about a redefinition if it's not defined as the
2450 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2451 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2456 name
= xstrdup (str
);
2457 new_reg
= XNEW (struct reg_entry
);
2459 new_reg
->name
= name
;
2460 new_reg
->number
= number
;
2461 new_reg
->type
= type
;
2462 new_reg
->builtin
= FALSE
;
2463 new_reg
->neon
= NULL
;
2465 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2472 insert_neon_reg_alias (char *str
, int number
, int type
,
2473 struct neon_typed_alias
*atype
)
2475 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2479 first_error (_("attempt to redefine typed alias"));
2485 reg
->neon
= XNEW (struct neon_typed_alias
);
2486 *reg
->neon
= *atype
;
2490 /* Look for the .req directive. This is of the form:
2492 new_register_name .req existing_register_name
2494 If we find one, or if it looks sufficiently like one that we want to
2495 handle any error here, return TRUE. Otherwise return FALSE. */
2498 create_register_alias (char * newname
, char *p
)
2500 struct reg_entry
*old
;
2501 char *oldname
, *nbuf
;
2504 /* The input scrubber ensures that whitespace after the mnemonic is
2505 collapsed to single spaces. */
2507 if (strncmp (oldname
, " .req ", 6) != 0)
2511 if (*oldname
== '\0')
2514 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2517 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2521 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2522 the desired alias name, and p points to its end. If not, then
2523 the desired alias name is in the global original_case_string. */
2524 #ifdef TC_CASE_SENSITIVE
2527 newname
= original_case_string
;
2528 nlen
= strlen (newname
);
2531 nbuf
= xmemdup0 (newname
, nlen
);
2533 /* Create aliases under the new name as stated; an all-lowercase
2534 version of the new name; and an all-uppercase version of the new
2536 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2538 for (p
= nbuf
; *p
; p
++)
2541 if (strncmp (nbuf
, newname
, nlen
))
2543 /* If this attempt to create an additional alias fails, do not bother
2544 trying to create the all-lower case alias. We will fail and issue
2545 a second, duplicate error message. This situation arises when the
2546 programmer does something like:
2549 The second .req creates the "Foo" alias but then fails to create
2550 the artificial FOO alias because it has already been created by the
2552 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2559 for (p
= nbuf
; *p
; p
++)
2562 if (strncmp (nbuf
, newname
, nlen
))
2563 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2570 /* Create a Neon typed/indexed register alias using directives, e.g.:
2575 These typed registers can be used instead of the types specified after the
2576 Neon mnemonic, so long as all operands given have types. Types can also be
2577 specified directly, e.g.:
2578 vadd d0.s32, d1.s32, d2.s32 */
2581 create_neon_reg_alias (char *newname
, char *p
)
2583 enum arm_reg_type basetype
;
2584 struct reg_entry
*basereg
;
2585 struct reg_entry mybasereg
;
2586 struct neon_type ntype
;
2587 struct neon_typed_alias typeinfo
;
2588 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2591 typeinfo
.defined
= 0;
2592 typeinfo
.eltype
.type
= NT_invtype
;
2593 typeinfo
.eltype
.size
= -1;
2594 typeinfo
.index
= -1;
2598 if (strncmp (p
, " .dn ", 5) == 0)
2599 basetype
= REG_TYPE_VFD
;
2600 else if (strncmp (p
, " .qn ", 5) == 0)
2601 basetype
= REG_TYPE_NQ
;
2610 basereg
= arm_reg_parse_multi (&p
);
2612 if (basereg
&& basereg
->type
!= basetype
)
2614 as_bad (_("bad type for register"));
2618 if (basereg
== NULL
)
2621 /* Try parsing as an integer. */
2622 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2623 if (exp
.X_op
!= O_constant
)
2625 as_bad (_("expression must be constant"));
2628 basereg
= &mybasereg
;
2629 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2635 typeinfo
= *basereg
->neon
;
2637 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2639 /* We got a type. */
2640 if (typeinfo
.defined
& NTA_HASTYPE
)
2642 as_bad (_("can't redefine the type of a register alias"));
2646 typeinfo
.defined
|= NTA_HASTYPE
;
2647 if (ntype
.elems
!= 1)
2649 as_bad (_("you must specify a single type only"));
2652 typeinfo
.eltype
= ntype
.el
[0];
2655 if (skip_past_char (&p
, '[') == SUCCESS
)
2658 /* We got a scalar index. */
2660 if (typeinfo
.defined
& NTA_HASINDEX
)
2662 as_bad (_("can't redefine the index of a scalar alias"));
2666 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2668 if (exp
.X_op
!= O_constant
)
2670 as_bad (_("scalar index must be constant"));
2674 typeinfo
.defined
|= NTA_HASINDEX
;
2675 typeinfo
.index
= exp
.X_add_number
;
2677 if (skip_past_char (&p
, ']') == FAIL
)
2679 as_bad (_("expecting ]"));
2684 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2685 the desired alias name, and p points to its end. If not, then
2686 the desired alias name is in the global original_case_string. */
2687 #ifdef TC_CASE_SENSITIVE
2688 namelen
= nameend
- newname
;
2690 newname
= original_case_string
;
2691 namelen
= strlen (newname
);
2694 namebuf
= xmemdup0 (newname
, namelen
);
2696 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2697 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2699 /* Insert name in all uppercase. */
2700 for (p
= namebuf
; *p
; p
++)
2703 if (strncmp (namebuf
, newname
, namelen
))
2704 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2705 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2707 /* Insert name in all lowercase. */
2708 for (p
= namebuf
; *p
; p
++)
2711 if (strncmp (namebuf
, newname
, namelen
))
2712 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2713 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2719 /* Should never be called, as .req goes between the alias and the
2720 register name, not at the beginning of the line. */
2723 s_req (int a ATTRIBUTE_UNUSED
)
2725 as_bad (_("invalid syntax for .req directive"));
2729 s_dn (int a ATTRIBUTE_UNUSED
)
2731 as_bad (_("invalid syntax for .dn directive"));
2735 s_qn (int a ATTRIBUTE_UNUSED
)
2737 as_bad (_("invalid syntax for .qn directive"));
2740 /* The .unreq directive deletes an alias which was previously defined
2741 by .req. For example:
2747 s_unreq (int a ATTRIBUTE_UNUSED
)
2752 name
= input_line_pointer
;
2754 while (*input_line_pointer
!= 0
2755 && *input_line_pointer
!= ' '
2756 && *input_line_pointer
!= '\n')
2757 ++input_line_pointer
;
2759 saved_char
= *input_line_pointer
;
2760 *input_line_pointer
= 0;
2763 as_bad (_("invalid syntax for .unreq directive"));
2766 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2770 as_bad (_("unknown register alias '%s'"), name
);
2771 else if (reg
->builtin
)
2772 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2779 hash_delete (arm_reg_hsh
, name
, FALSE
);
2780 free ((char *) reg
->name
);
2785 /* Also locate the all upper case and all lower case versions.
2786 Do not complain if we cannot find one or the other as it
2787 was probably deleted above. */
2789 nbuf
= strdup (name
);
2790 for (p
= nbuf
; *p
; p
++)
2792 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2795 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2796 free ((char *) reg
->name
);
2802 for (p
= nbuf
; *p
; p
++)
2804 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2807 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2808 free ((char *) reg
->name
);
2818 *input_line_pointer
= saved_char
;
2819 demand_empty_rest_of_line ();
2822 /* Directives: Instruction set selection. */
2825 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2826 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2827 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2828 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2830 /* Create a new mapping symbol for the transition to STATE. */
2833 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2836 const char * symname
;
2843 type
= BSF_NO_FLAGS
;
2847 type
= BSF_NO_FLAGS
;
2851 type
= BSF_NO_FLAGS
;
2857 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2858 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2863 THUMB_SET_FUNC (symbolP
, 0);
2864 ARM_SET_THUMB (symbolP
, 0);
2865 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2869 THUMB_SET_FUNC (symbolP
, 1);
2870 ARM_SET_THUMB (symbolP
, 1);
2871 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2879 /* Save the mapping symbols for future reference. Also check that
2880 we do not place two mapping symbols at the same offset within a
2881 frag. We'll handle overlap between frags in
2882 check_mapping_symbols.
2884 If .fill or other data filling directive generates zero sized data,
2885 the mapping symbol for the following code will have the same value
2886 as the one generated for the data filling directive. In this case,
2887 we replace the old symbol with the new one at the same address. */
2890 if (frag
->tc_frag_data
.first_map
!= NULL
)
2892 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2893 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2895 frag
->tc_frag_data
.first_map
= symbolP
;
2897 if (frag
->tc_frag_data
.last_map
!= NULL
)
2899 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2900 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2901 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2903 frag
->tc_frag_data
.last_map
= symbolP
;
2906 /* We must sometimes convert a region marked as code to data during
2907 code alignment, if an odd number of bytes have to be padded. The
2908 code mapping symbol is pushed to an aligned address. */
2911 insert_data_mapping_symbol (enum mstate state
,
2912 valueT value
, fragS
*frag
, offsetT bytes
)
2914 /* If there was already a mapping symbol, remove it. */
2915 if (frag
->tc_frag_data
.last_map
!= NULL
2916 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2918 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2922 know (frag
->tc_frag_data
.first_map
== symp
);
2923 frag
->tc_frag_data
.first_map
= NULL
;
2925 frag
->tc_frag_data
.last_map
= NULL
;
2926 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2929 make_mapping_symbol (MAP_DATA
, value
, frag
);
2930 make_mapping_symbol (state
, value
+ bytes
, frag
);
2933 static void mapping_state_2 (enum mstate state
, int max_chars
);
2935 /* Set the mapping state to STATE. Only call this when about to
2936 emit some STATE bytes to the file. */
2938 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2940 mapping_state (enum mstate state
)
2942 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2944 if (mapstate
== state
)
2945 /* The mapping symbol has already been emitted.
2946 There is nothing else to do. */
2949 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2951 All ARM instructions require 4-byte alignment.
2952 (Almost) all Thumb instructions require 2-byte alignment.
2954 When emitting instructions into any section, mark the section
2957 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2958 but themselves require 2-byte alignment; this applies to some
2959 PC- relative forms. However, these cases will involve implicit
2960 literal pool generation or an explicit .align >=2, both of
2961 which will cause the section to me marked with sufficient
2962 alignment. Thus, we don't handle those cases here. */
2963 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2965 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2966 /* This case will be evaluated later. */
2969 mapping_state_2 (state
, 0);
2972 /* Same as mapping_state, but MAX_CHARS bytes have already been
2973 allocated. Put the mapping symbol that far back. */
2976 mapping_state_2 (enum mstate state
, int max_chars
)
2978 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2980 if (!SEG_NORMAL (now_seg
))
2983 if (mapstate
== state
)
2984 /* The mapping symbol has already been emitted.
2985 There is nothing else to do. */
2988 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2989 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2991 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2992 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2995 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2998 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2999 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
3003 #define mapping_state(x) ((void)0)
3004 #define mapping_state_2(x, y) ((void)0)
3007 /* Find the real, Thumb encoded start of a Thumb function. */
3011 find_real_start (symbolS
* symbolP
)
3014 const char * name
= S_GET_NAME (symbolP
);
3015 symbolS
* new_target
;
3017 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3018 #define STUB_NAME ".real_start_of"
3023 /* The compiler may generate BL instructions to local labels because
3024 it needs to perform a branch to a far away location. These labels
3025 do not have a corresponding ".real_start_of" label. We check
3026 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3027 the ".real_start_of" convention for nonlocal branches. */
3028 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3031 real_start
= concat (STUB_NAME
, name
, NULL
);
3032 new_target
= symbol_find (real_start
);
3035 if (new_target
== NULL
)
3037 as_warn (_("Failed to find real start of function: %s\n"), name
);
3038 new_target
= symbolP
;
3046 opcode_select (int width
)
3053 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3054 as_bad (_("selected processor does not support THUMB opcodes"));
3057 /* No need to force the alignment, since we will have been
3058 coming from ARM mode, which is word-aligned. */
3059 record_alignment (now_seg
, 1);
3066 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3067 as_bad (_("selected processor does not support ARM opcodes"));
3072 frag_align (2, 0, 0);
3074 record_alignment (now_seg
, 1);
3079 as_bad (_("invalid instruction size selected (%d)"), width
);
3084 s_arm (int ignore ATTRIBUTE_UNUSED
)
3087 demand_empty_rest_of_line ();
3091 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3094 demand_empty_rest_of_line ();
3098 s_code (int unused ATTRIBUTE_UNUSED
)
3102 temp
= get_absolute_expression ();
3107 opcode_select (temp
);
3111 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3116 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3118 /* If we are not already in thumb mode go into it, EVEN if
3119 the target processor does not support thumb instructions.
3120 This is used by gcc/config/arm/lib1funcs.asm for example
3121 to compile interworking support functions even if the
3122 target processor should not support interworking. */
3126 record_alignment (now_seg
, 1);
3129 demand_empty_rest_of_line ();
3133 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3137 /* The following label is the name/address of the start of a Thumb function.
3138 We need to know this for the interworking support. */
3139 label_is_thumb_function_name
= TRUE
;
3142 /* Perform a .set directive, but also mark the alias as
3143 being a thumb function. */
3146 s_thumb_set (int equiv
)
3148 /* XXX the following is a duplicate of the code for s_set() in read.c
3149 We cannot just call that code as we need to get at the symbol that
3156 /* Especial apologies for the random logic:
3157 This just grew, and could be parsed much more simply!
3159 delim
= get_symbol_name (& name
);
3160 end_name
= input_line_pointer
;
3161 (void) restore_line_pointer (delim
);
3163 if (*input_line_pointer
!= ',')
3166 as_bad (_("expected comma after name \"%s\""), name
);
3168 ignore_rest_of_line ();
3172 input_line_pointer
++;
3175 if (name
[0] == '.' && name
[1] == '\0')
3177 /* XXX - this should not happen to .thumb_set. */
3181 if ((symbolP
= symbol_find (name
)) == NULL
3182 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3185 /* When doing symbol listings, play games with dummy fragments living
3186 outside the normal fragment chain to record the file and line info
3188 if (listing
& LISTING_SYMBOLS
)
3190 extern struct list_info_struct
* listing_tail
;
3191 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3193 memset (dummy_frag
, 0, sizeof (fragS
));
3194 dummy_frag
->fr_type
= rs_fill
;
3195 dummy_frag
->line
= listing_tail
;
3196 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
3197 dummy_frag
->fr_symbol
= symbolP
;
3201 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3204 /* "set" symbols are local unless otherwise specified. */
3205 SF_SET_LOCAL (symbolP
);
3206 #endif /* OBJ_COFF */
3207 } /* Make a new symbol. */
3209 symbol_table_insert (symbolP
);
3214 && S_IS_DEFINED (symbolP
)
3215 && S_GET_SEGMENT (symbolP
) != reg_section
)
3216 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3218 pseudo_set (symbolP
);
3220 demand_empty_rest_of_line ();
3222 /* XXX Now we come to the Thumb specific bit of code. */
3224 THUMB_SET_FUNC (symbolP
, 1);
3225 ARM_SET_THUMB (symbolP
, 1);
3226 #if defined OBJ_ELF || defined OBJ_COFF
3227 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3231 /* Directives: Mode selection. */
3233 /* .syntax [unified|divided] - choose the new unified syntax
3234 (same for Arm and Thumb encoding, modulo slight differences in what
3235 can be represented) or the old divergent syntax for each mode. */
3237 s_syntax (int unused ATTRIBUTE_UNUSED
)
3241 delim
= get_symbol_name (& name
);
3243 if (!strcasecmp (name
, "unified"))
3244 unified_syntax
= TRUE
;
3245 else if (!strcasecmp (name
, "divided"))
3246 unified_syntax
= FALSE
;
3249 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3252 (void) restore_line_pointer (delim
);
3253 demand_empty_rest_of_line ();
3256 /* Directives: sectioning and alignment. */
3259 s_bss (int ignore ATTRIBUTE_UNUSED
)
3261 /* We don't support putting frags in the BSS segment, we fake it by
3262 marking in_bss, then looking at s_skip for clues. */
3263 subseg_set (bss_section
, 0);
3264 demand_empty_rest_of_line ();
3266 #ifdef md_elf_section_change_hook
3267 md_elf_section_change_hook ();
3272 s_even (int ignore ATTRIBUTE_UNUSED
)
3274 /* Never make frag if expect extra pass. */
3276 frag_align (1, 0, 0);
3278 record_alignment (now_seg
, 1);
3280 demand_empty_rest_of_line ();
3283 /* Directives: CodeComposer Studio. */
3285 /* .ref (for CodeComposer Studio syntax only). */
3287 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3289 if (codecomposer_syntax
)
3290 ignore_rest_of_line ();
3292 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3295 /* If name is not NULL, then it is used for marking the beginning of a
3296 function, whereas if it is NULL then it means the function end. */
3298 asmfunc_debug (const char * name
)
3300 static const char * last_name
= NULL
;
3304 gas_assert (last_name
== NULL
);
3307 if (debug_type
== DEBUG_STABS
)
3308 stabs_generate_asm_func (name
, name
);
3312 gas_assert (last_name
!= NULL
);
3314 if (debug_type
== DEBUG_STABS
)
3315 stabs_generate_asm_endfunc (last_name
, last_name
);
3322 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3324 if (codecomposer_syntax
)
3326 switch (asmfunc_state
)
3328 case OUTSIDE_ASMFUNC
:
3329 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3332 case WAITING_ASMFUNC_NAME
:
3333 as_bad (_(".asmfunc repeated."));
3336 case WAITING_ENDASMFUNC
:
3337 as_bad (_(".asmfunc without function."));
3340 demand_empty_rest_of_line ();
3343 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3347 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3349 if (codecomposer_syntax
)
3351 switch (asmfunc_state
)
3353 case OUTSIDE_ASMFUNC
:
3354 as_bad (_(".endasmfunc without a .asmfunc."));
3357 case WAITING_ASMFUNC_NAME
:
3358 as_bad (_(".endasmfunc without function."));
3361 case WAITING_ENDASMFUNC
:
3362 asmfunc_state
= OUTSIDE_ASMFUNC
;
3363 asmfunc_debug (NULL
);
3366 demand_empty_rest_of_line ();
3369 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3373 s_ccs_def (int name
)
3375 if (codecomposer_syntax
)
3378 as_bad (_(".def pseudo-op only available with -mccs flag."));
3381 /* Directives: Literal pools. */
3383 static literal_pool
*
3384 find_literal_pool (void)
3386 literal_pool
* pool
;
3388 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3390 if (pool
->section
== now_seg
3391 && pool
->sub_section
== now_subseg
)
3398 static literal_pool
*
3399 find_or_make_literal_pool (void)
3401 /* Next literal pool ID number. */
3402 static unsigned int latest_pool_num
= 1;
3403 literal_pool
* pool
;
3405 pool
= find_literal_pool ();
3409 /* Create a new pool. */
3410 pool
= XNEW (literal_pool
);
3414 pool
->next_free_entry
= 0;
3415 pool
->section
= now_seg
;
3416 pool
->sub_section
= now_subseg
;
3417 pool
->next
= list_of_pools
;
3418 pool
->symbol
= NULL
;
3419 pool
->alignment
= 2;
3421 /* Add it to the list. */
3422 list_of_pools
= pool
;
3425 /* New pools, and emptied pools, will have a NULL symbol. */
3426 if (pool
->symbol
== NULL
)
3428 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3429 (valueT
) 0, &zero_address_frag
);
3430 pool
->id
= latest_pool_num
++;
3437 /* Add the literal in the global 'inst'
3438 structure to the relevant literal pool. */
3441 add_to_lit_pool (unsigned int nbytes
)
3443 #define PADDING_SLOT 0x1
3444 #define LIT_ENTRY_SIZE_MASK 0xFF
3445 literal_pool
* pool
;
3446 unsigned int entry
, pool_size
= 0;
3447 bfd_boolean padding_slot_p
= FALSE
;
3453 imm1
= inst
.operands
[1].imm
;
3454 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3455 : inst
.relocs
[0].exp
.X_unsigned
? 0
3456 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3457 if (target_big_endian
)
3460 imm2
= inst
.operands
[1].imm
;
3464 pool
= find_or_make_literal_pool ();
3466 /* Check if this literal value is already in the pool. */
3467 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3471 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3472 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3473 && (pool
->literals
[entry
].X_add_number
3474 == inst
.relocs
[0].exp
.X_add_number
)
3475 && (pool
->literals
[entry
].X_md
== nbytes
)
3476 && (pool
->literals
[entry
].X_unsigned
3477 == inst
.relocs
[0].exp
.X_unsigned
))
3480 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3481 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3482 && (pool
->literals
[entry
].X_add_number
3483 == inst
.relocs
[0].exp
.X_add_number
)
3484 && (pool
->literals
[entry
].X_add_symbol
3485 == inst
.relocs
[0].exp
.X_add_symbol
)
3486 && (pool
->literals
[entry
].X_op_symbol
3487 == inst
.relocs
[0].exp
.X_op_symbol
)
3488 && (pool
->literals
[entry
].X_md
== nbytes
))
3491 else if ((nbytes
== 8)
3492 && !(pool_size
& 0x7)
3493 && ((entry
+ 1) != pool
->next_free_entry
)
3494 && (pool
->literals
[entry
].X_op
== O_constant
)
3495 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3496 && (pool
->literals
[entry
].X_unsigned
3497 == inst
.relocs
[0].exp
.X_unsigned
)
3498 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3499 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3500 && (pool
->literals
[entry
+ 1].X_unsigned
3501 == inst
.relocs
[0].exp
.X_unsigned
))
3504 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3505 if (padding_slot_p
&& (nbytes
== 4))
3511 /* Do we need to create a new entry? */
3512 if (entry
== pool
->next_free_entry
)
3514 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3516 inst
.error
= _("literal pool overflow");
3522 /* For 8-byte entries, we align to an 8-byte boundary,
3523 and split it into two 4-byte entries, because on 32-bit
3524 host, 8-byte constants are treated as big num, thus
3525 saved in "generic_bignum" which will be overwritten
3526 by later assignments.
3528 We also need to make sure there is enough space for
3531 We also check to make sure the literal operand is a
3533 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3534 || inst
.relocs
[0].exp
.X_op
== O_big
))
3536 inst
.error
= _("invalid type for literal pool");
3539 else if (pool_size
& 0x7)
3541 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3543 inst
.error
= _("literal pool overflow");
3547 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3548 pool
->literals
[entry
].X_op
= O_constant
;
3549 pool
->literals
[entry
].X_add_number
= 0;
3550 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3551 pool
->next_free_entry
+= 1;
3554 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3556 inst
.error
= _("literal pool overflow");
3560 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3561 pool
->literals
[entry
].X_op
= O_constant
;
3562 pool
->literals
[entry
].X_add_number
= imm1
;
3563 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3564 pool
->literals
[entry
++].X_md
= 4;
3565 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3566 pool
->literals
[entry
].X_op
= O_constant
;
3567 pool
->literals
[entry
].X_add_number
= imm2
;
3568 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3569 pool
->literals
[entry
].X_md
= 4;
3570 pool
->alignment
= 3;
3571 pool
->next_free_entry
+= 1;
3575 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3576 pool
->literals
[entry
].X_md
= 4;
3580 /* PR ld/12974: Record the location of the first source line to reference
3581 this entry in the literal pool. If it turns out during linking that the
3582 symbol does not exist we will be able to give an accurate line number for
3583 the (first use of the) missing reference. */
3584 if (debug_type
== DEBUG_DWARF2
)
3585 dwarf2_where (pool
->locs
+ entry
);
3587 pool
->next_free_entry
+= 1;
3589 else if (padding_slot_p
)
3591 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3592 pool
->literals
[entry
].X_md
= nbytes
;
3595 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3596 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3597 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3603 tc_start_label_without_colon (void)
3605 bfd_boolean ret
= TRUE
;
3607 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3609 const char *label
= input_line_pointer
;
3611 while (!is_end_of_line
[(int) label
[-1]])
3616 as_bad (_("Invalid label '%s'"), label
);
3620 asmfunc_debug (label
);
3622 asmfunc_state
= WAITING_ENDASMFUNC
;
3628 /* Can't use symbol_new here, so have to create a symbol and then at
3629 a later date assign it a value. That's what these functions do. */
3632 symbol_locate (symbolS
* symbolP
,
3633 const char * name
, /* It is copied, the caller can modify. */
3634 segT segment
, /* Segment identifier (SEG_<something>). */
3635 valueT valu
, /* Symbol value. */
3636 fragS
* frag
) /* Associated fragment. */
3639 char * preserved_copy_of_name
;
3641 name_length
= strlen (name
) + 1; /* +1 for \0. */
3642 obstack_grow (¬es
, name
, name_length
);
3643 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3645 #ifdef tc_canonicalize_symbol_name
3646 preserved_copy_of_name
=
3647 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3650 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3652 S_SET_SEGMENT (symbolP
, segment
);
3653 S_SET_VALUE (symbolP
, valu
);
3654 symbol_clear_list_pointers (symbolP
);
3656 symbol_set_frag (symbolP
, frag
);
3658 /* Link to end of symbol chain. */
3660 extern int symbol_table_frozen
;
3662 if (symbol_table_frozen
)
3666 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3668 obj_symbol_new_hook (symbolP
);
3670 #ifdef tc_symbol_new_hook
3671 tc_symbol_new_hook (symbolP
);
3675 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3676 #endif /* DEBUG_SYMS */
3680 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3683 literal_pool
* pool
;
3686 pool
= find_literal_pool ();
3688 || pool
->symbol
== NULL
3689 || pool
->next_free_entry
== 0)
3692 /* Align pool as you have word accesses.
3693 Only make a frag if we have to. */
3695 frag_align (pool
->alignment
, 0, 0);
3697 record_alignment (now_seg
, 2);
3700 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3701 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3703 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3705 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3706 (valueT
) frag_now_fix (), frag_now
);
3707 symbol_table_insert (pool
->symbol
);
3709 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3711 #if defined OBJ_COFF || defined OBJ_ELF
3712 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3715 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3718 if (debug_type
== DEBUG_DWARF2
)
3719 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3721 /* First output the expression in the instruction to the pool. */
3722 emit_expr (&(pool
->literals
[entry
]),
3723 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3726 /* Mark the pool as empty. */
3727 pool
->next_free_entry
= 0;
3728 pool
->symbol
= NULL
;
3732 /* Forward declarations for functions below, in the MD interface
3734 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3735 static valueT
create_unwind_entry (int);
3736 static void start_unwind_section (const segT
, int);
3737 static void add_unwind_opcode (valueT
, int);
3738 static void flush_pending_unwind (void);
3740 /* Directives: Data. */
3743 s_arm_elf_cons (int nbytes
)
3747 #ifdef md_flush_pending_output
3748 md_flush_pending_output ();
3751 if (is_it_end_of_statement ())
3753 demand_empty_rest_of_line ();
3757 #ifdef md_cons_align
3758 md_cons_align (nbytes
);
3761 mapping_state (MAP_DATA
);
3765 char *base
= input_line_pointer
;
3769 if (exp
.X_op
!= O_symbol
)
3770 emit_expr (&exp
, (unsigned int) nbytes
);
3773 char *before_reloc
= input_line_pointer
;
3774 reloc
= parse_reloc (&input_line_pointer
);
3777 as_bad (_("unrecognized relocation suffix"));
3778 ignore_rest_of_line ();
3781 else if (reloc
== BFD_RELOC_UNUSED
)
3782 emit_expr (&exp
, (unsigned int) nbytes
);
3785 reloc_howto_type
*howto
= (reloc_howto_type
*)
3786 bfd_reloc_type_lookup (stdoutput
,
3787 (bfd_reloc_code_real_type
) reloc
);
3788 int size
= bfd_get_reloc_size (howto
);
3790 if (reloc
== BFD_RELOC_ARM_PLT32
)
3792 as_bad (_("(plt) is only valid on branch targets"));
3793 reloc
= BFD_RELOC_UNUSED
;
3798 as_bad (ngettext ("%s relocations do not fit in %d byte",
3799 "%s relocations do not fit in %d bytes",
3801 howto
->name
, nbytes
);
3804 /* We've parsed an expression stopping at O_symbol.
3805 But there may be more expression left now that we
3806 have parsed the relocation marker. Parse it again.
3807 XXX Surely there is a cleaner way to do this. */
3808 char *p
= input_line_pointer
;
3810 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3812 memcpy (save_buf
, base
, input_line_pointer
- base
);
3813 memmove (base
+ (input_line_pointer
- before_reloc
),
3814 base
, before_reloc
- base
);
3816 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3818 memcpy (base
, save_buf
, p
- base
);
3820 offset
= nbytes
- size
;
3821 p
= frag_more (nbytes
);
3822 memset (p
, 0, nbytes
);
3823 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3824 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3830 while (*input_line_pointer
++ == ',');
3832 /* Put terminator back into stream. */
3833 input_line_pointer
--;
3834 demand_empty_rest_of_line ();
3837 /* Emit an expression containing a 32-bit thumb instruction.
3838 Implementation based on put_thumb32_insn. */
3841 emit_thumb32_expr (expressionS
* exp
)
3843 expressionS exp_high
= *exp
;
3845 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3846 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3847 exp
->X_add_number
&= 0xffff;
3848 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3851 /* Guess the instruction size based on the opcode. */
3854 thumb_insn_size (int opcode
)
3856 if ((unsigned int) opcode
< 0xe800u
)
3858 else if ((unsigned int) opcode
>= 0xe8000000u
)
3865 emit_insn (expressionS
*exp
, int nbytes
)
3869 if (exp
->X_op
== O_constant
)
3874 size
= thumb_insn_size (exp
->X_add_number
);
3878 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3880 as_bad (_(".inst.n operand too big. "\
3881 "Use .inst.w instead"));
3886 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
3887 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
3889 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3891 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3892 emit_thumb32_expr (exp
);
3894 emit_expr (exp
, (unsigned int) size
);
3896 it_fsm_post_encode ();
3900 as_bad (_("cannot determine Thumb instruction size. " \
3901 "Use .inst.n/.inst.w instead"));
3904 as_bad (_("constant expression required"));
3909 /* Like s_arm_elf_cons but do not use md_cons_align and
3910 set the mapping state to MAP_ARM/MAP_THUMB. */
3913 s_arm_elf_inst (int nbytes
)
3915 if (is_it_end_of_statement ())
3917 demand_empty_rest_of_line ();
3921 /* Calling mapping_state () here will not change ARM/THUMB,
3922 but will ensure not to be in DATA state. */
3925 mapping_state (MAP_THUMB
);
3930 as_bad (_("width suffixes are invalid in ARM mode"));
3931 ignore_rest_of_line ();
3937 mapping_state (MAP_ARM
);
3946 if (! emit_insn (& exp
, nbytes
))
3948 ignore_rest_of_line ();
3952 while (*input_line_pointer
++ == ',');
3954 /* Put terminator back into stream. */
3955 input_line_pointer
--;
3956 demand_empty_rest_of_line ();
3959 /* Parse a .rel31 directive. */
3962 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3969 if (*input_line_pointer
== '1')
3970 highbit
= 0x80000000;
3971 else if (*input_line_pointer
!= '0')
3972 as_bad (_("expected 0 or 1"));
3974 input_line_pointer
++;
3975 if (*input_line_pointer
!= ',')
3976 as_bad (_("missing comma"));
3977 input_line_pointer
++;
3979 #ifdef md_flush_pending_output
3980 md_flush_pending_output ();
3983 #ifdef md_cons_align
3987 mapping_state (MAP_DATA
);
3992 md_number_to_chars (p
, highbit
, 4);
3993 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3994 BFD_RELOC_ARM_PREL31
);
3996 demand_empty_rest_of_line ();
3999 /* Directives: AEABI stack-unwind tables. */
4001 /* Parse an unwind_fnstart directive. Simply records the current location. */
4004 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4006 demand_empty_rest_of_line ();
4007 if (unwind
.proc_start
)
4009 as_bad (_("duplicate .fnstart directive"));
4013 /* Mark the start of the function. */
4014 unwind
.proc_start
= expr_build_dot ();
4016 /* Reset the rest of the unwind info. */
4017 unwind
.opcode_count
= 0;
4018 unwind
.table_entry
= NULL
;
4019 unwind
.personality_routine
= NULL
;
4020 unwind
.personality_index
= -1;
4021 unwind
.frame_size
= 0;
4022 unwind
.fp_offset
= 0;
4023 unwind
.fp_reg
= REG_SP
;
4025 unwind
.sp_restored
= 0;
4029 /* Parse a handlerdata directive. Creates the exception handling table entry
4030 for the function. */
4033 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4035 demand_empty_rest_of_line ();
4036 if (!unwind
.proc_start
)
4037 as_bad (MISSING_FNSTART
);
4039 if (unwind
.table_entry
)
4040 as_bad (_("duplicate .handlerdata directive"));
4042 create_unwind_entry (1);
4045 /* Parse an unwind_fnend directive. Generates the index table entry. */
4048 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4053 unsigned int marked_pr_dependency
;
4055 demand_empty_rest_of_line ();
4057 if (!unwind
.proc_start
)
4059 as_bad (_(".fnend directive without .fnstart"));
4063 /* Add eh table entry. */
4064 if (unwind
.table_entry
== NULL
)
4065 val
= create_unwind_entry (0);
4069 /* Add index table entry. This is two words. */
4070 start_unwind_section (unwind
.saved_seg
, 1);
4071 frag_align (2, 0, 0);
4072 record_alignment (now_seg
, 2);
4074 ptr
= frag_more (8);
4076 where
= frag_now_fix () - 8;
4078 /* Self relative offset of the function start. */
4079 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4080 BFD_RELOC_ARM_PREL31
);
4082 /* Indicate dependency on EHABI-defined personality routines to the
4083 linker, if it hasn't been done already. */
4084 marked_pr_dependency
4085 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4086 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4087 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4089 static const char *const name
[] =
4091 "__aeabi_unwind_cpp_pr0",
4092 "__aeabi_unwind_cpp_pr1",
4093 "__aeabi_unwind_cpp_pr2"
4095 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4096 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4097 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4098 |= 1 << unwind
.personality_index
;
4102 /* Inline exception table entry. */
4103 md_number_to_chars (ptr
+ 4, val
, 4);
4105 /* Self relative offset of the table entry. */
4106 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4107 BFD_RELOC_ARM_PREL31
);
4109 /* Restore the original section. */
4110 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4112 unwind
.proc_start
= NULL
;
4116 /* Parse an unwind_cantunwind directive. */
4119 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4121 demand_empty_rest_of_line ();
4122 if (!unwind
.proc_start
)
4123 as_bad (MISSING_FNSTART
);
4125 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4126 as_bad (_("personality routine specified for cantunwind frame"));
4128 unwind
.personality_index
= -2;
4132 /* Parse a personalityindex directive. */
4135 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4139 if (!unwind
.proc_start
)
4140 as_bad (MISSING_FNSTART
);
4142 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4143 as_bad (_("duplicate .personalityindex directive"));
4147 if (exp
.X_op
!= O_constant
4148 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4150 as_bad (_("bad personality routine number"));
4151 ignore_rest_of_line ();
4155 unwind
.personality_index
= exp
.X_add_number
;
4157 demand_empty_rest_of_line ();
4161 /* Parse a personality directive. */
4164 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4168 if (!unwind
.proc_start
)
4169 as_bad (MISSING_FNSTART
);
4171 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4172 as_bad (_("duplicate .personality directive"));
4174 c
= get_symbol_name (& name
);
4175 p
= input_line_pointer
;
4177 ++ input_line_pointer
;
4178 unwind
.personality_routine
= symbol_find_or_make (name
);
4180 demand_empty_rest_of_line ();
4184 /* Parse a directive saving core registers. */
4187 s_arm_unwind_save_core (void)
4193 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4196 as_bad (_("expected register list"));
4197 ignore_rest_of_line ();
4201 demand_empty_rest_of_line ();
4203 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4204 into .unwind_save {..., sp...}. We aren't bothered about the value of
4205 ip because it is clobbered by calls. */
4206 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4207 && (range
& 0x3000) == 0x1000)
4209 unwind
.opcode_count
--;
4210 unwind
.sp_restored
= 0;
4211 range
= (range
| 0x2000) & ~0x1000;
4212 unwind
.pending_offset
= 0;
4218 /* See if we can use the short opcodes. These pop a block of up to 8
4219 registers starting with r4, plus maybe r14. */
4220 for (n
= 0; n
< 8; n
++)
4222 /* Break at the first non-saved register. */
4223 if ((range
& (1 << (n
+ 4))) == 0)
4226 /* See if there are any other bits set. */
4227 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4229 /* Use the long form. */
4230 op
= 0x8000 | ((range
>> 4) & 0xfff);
4231 add_unwind_opcode (op
, 2);
4235 /* Use the short form. */
4237 op
= 0xa8; /* Pop r14. */
4239 op
= 0xa0; /* Do not pop r14. */
4241 add_unwind_opcode (op
, 1);
4248 op
= 0xb100 | (range
& 0xf);
4249 add_unwind_opcode (op
, 2);
4252 /* Record the number of bytes pushed. */
4253 for (n
= 0; n
< 16; n
++)
4255 if (range
& (1 << n
))
4256 unwind
.frame_size
+= 4;
4261 /* Parse a directive saving FPA registers. */
4264 s_arm_unwind_save_fpa (int reg
)
4270 /* Get Number of registers to transfer. */
4271 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4274 exp
.X_op
= O_illegal
;
4276 if (exp
.X_op
!= O_constant
)
4278 as_bad (_("expected , <constant>"));
4279 ignore_rest_of_line ();
4283 num_regs
= exp
.X_add_number
;
4285 if (num_regs
< 1 || num_regs
> 4)
4287 as_bad (_("number of registers must be in the range [1:4]"));
4288 ignore_rest_of_line ();
4292 demand_empty_rest_of_line ();
4297 op
= 0xb4 | (num_regs
- 1);
4298 add_unwind_opcode (op
, 1);
4303 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4304 add_unwind_opcode (op
, 2);
4306 unwind
.frame_size
+= num_regs
* 12;
4310 /* Parse a directive saving VFP registers for ARMv6 and above. */
4313 s_arm_unwind_save_vfp_armv6 (void)
4318 int num_vfpv3_regs
= 0;
4319 int num_regs_below_16
;
4320 bfd_boolean partial_match
;
4322 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4326 as_bad (_("expected register list"));
4327 ignore_rest_of_line ();
4331 demand_empty_rest_of_line ();
4333 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4334 than FSTMX/FLDMX-style ones). */
4336 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4338 num_vfpv3_regs
= count
;
4339 else if (start
+ count
> 16)
4340 num_vfpv3_regs
= start
+ count
- 16;
4342 if (num_vfpv3_regs
> 0)
4344 int start_offset
= start
> 16 ? start
- 16 : 0;
4345 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4346 add_unwind_opcode (op
, 2);
4349 /* Generate opcode for registers numbered in the range 0 .. 15. */
4350 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4351 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4352 if (num_regs_below_16
> 0)
4354 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4355 add_unwind_opcode (op
, 2);
4358 unwind
.frame_size
+= count
* 8;
4362 /* Parse a directive saving VFP registers for pre-ARMv6. */
4365 s_arm_unwind_save_vfp (void)
4370 bfd_boolean partial_match
;
4372 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4376 as_bad (_("expected register list"));
4377 ignore_rest_of_line ();
4381 demand_empty_rest_of_line ();
4386 op
= 0xb8 | (count
- 1);
4387 add_unwind_opcode (op
, 1);
4392 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4393 add_unwind_opcode (op
, 2);
4395 unwind
.frame_size
+= count
* 8 + 4;
4399 /* Parse a directive saving iWMMXt data registers. */
4402 s_arm_unwind_save_mmxwr (void)
4410 if (*input_line_pointer
== '{')
4411 input_line_pointer
++;
4415 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4419 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4424 as_tsktsk (_("register list not in ascending order"));
4427 if (*input_line_pointer
== '-')
4429 input_line_pointer
++;
4430 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4433 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4436 else if (reg
>= hi_reg
)
4438 as_bad (_("bad register range"));
4441 for (; reg
< hi_reg
; reg
++)
4445 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4447 skip_past_char (&input_line_pointer
, '}');
4449 demand_empty_rest_of_line ();
4451 /* Generate any deferred opcodes because we're going to be looking at
4453 flush_pending_unwind ();
4455 for (i
= 0; i
< 16; i
++)
4457 if (mask
& (1 << i
))
4458 unwind
.frame_size
+= 8;
4461 /* Attempt to combine with a previous opcode. We do this because gcc
4462 likes to output separate unwind directives for a single block of
4464 if (unwind
.opcode_count
> 0)
4466 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4467 if ((i
& 0xf8) == 0xc0)
4470 /* Only merge if the blocks are contiguous. */
4473 if ((mask
& 0xfe00) == (1 << 9))
4475 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4476 unwind
.opcode_count
--;
4479 else if (i
== 6 && unwind
.opcode_count
>= 2)
4481 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4485 op
= 0xffff << (reg
- 1);
4487 && ((mask
& op
) == (1u << (reg
- 1))))
4489 op
= (1 << (reg
+ i
+ 1)) - 1;
4490 op
&= ~((1 << reg
) - 1);
4492 unwind
.opcode_count
-= 2;
4499 /* We want to generate opcodes in the order the registers have been
4500 saved, ie. descending order. */
4501 for (reg
= 15; reg
>= -1; reg
--)
4503 /* Save registers in blocks. */
4505 || !(mask
& (1 << reg
)))
4507 /* We found an unsaved reg. Generate opcodes to save the
4514 op
= 0xc0 | (hi_reg
- 10);
4515 add_unwind_opcode (op
, 1);
4520 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4521 add_unwind_opcode (op
, 2);
4530 ignore_rest_of_line ();
4534 s_arm_unwind_save_mmxwcg (void)
4541 if (*input_line_pointer
== '{')
4542 input_line_pointer
++;
4544 skip_whitespace (input_line_pointer
);
4548 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4552 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4558 as_tsktsk (_("register list not in ascending order"));
4561 if (*input_line_pointer
== '-')
4563 input_line_pointer
++;
4564 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4567 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4570 else if (reg
>= hi_reg
)
4572 as_bad (_("bad register range"));
4575 for (; reg
< hi_reg
; reg
++)
4579 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4581 skip_past_char (&input_line_pointer
, '}');
4583 demand_empty_rest_of_line ();
4585 /* Generate any deferred opcodes because we're going to be looking at
4587 flush_pending_unwind ();
4589 for (reg
= 0; reg
< 16; reg
++)
4591 if (mask
& (1 << reg
))
4592 unwind
.frame_size
+= 4;
4595 add_unwind_opcode (op
, 2);
4598 ignore_rest_of_line ();
4602 /* Parse an unwind_save directive.
4603 If the argument is non-zero, this is a .vsave directive. */
4606 s_arm_unwind_save (int arch_v6
)
4609 struct reg_entry
*reg
;
4610 bfd_boolean had_brace
= FALSE
;
4612 if (!unwind
.proc_start
)
4613 as_bad (MISSING_FNSTART
);
4615 /* Figure out what sort of save we have. */
4616 peek
= input_line_pointer
;
4624 reg
= arm_reg_parse_multi (&peek
);
4628 as_bad (_("register expected"));
4629 ignore_rest_of_line ();
4638 as_bad (_("FPA .unwind_save does not take a register list"));
4639 ignore_rest_of_line ();
4642 input_line_pointer
= peek
;
4643 s_arm_unwind_save_fpa (reg
->number
);
4647 s_arm_unwind_save_core ();
4652 s_arm_unwind_save_vfp_armv6 ();
4654 s_arm_unwind_save_vfp ();
4657 case REG_TYPE_MMXWR
:
4658 s_arm_unwind_save_mmxwr ();
4661 case REG_TYPE_MMXWCG
:
4662 s_arm_unwind_save_mmxwcg ();
4666 as_bad (_(".unwind_save does not support this kind of register"));
4667 ignore_rest_of_line ();
4672 /* Parse an unwind_movsp directive. */
4675 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4681 if (!unwind
.proc_start
)
4682 as_bad (MISSING_FNSTART
);
4684 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4687 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4688 ignore_rest_of_line ();
4692 /* Optional constant. */
4693 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4695 if (immediate_for_directive (&offset
) == FAIL
)
4701 demand_empty_rest_of_line ();
4703 if (reg
== REG_SP
|| reg
== REG_PC
)
4705 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4709 if (unwind
.fp_reg
!= REG_SP
)
4710 as_bad (_("unexpected .unwind_movsp directive"));
4712 /* Generate opcode to restore the value. */
4714 add_unwind_opcode (op
, 1);
4716 /* Record the information for later. */
4717 unwind
.fp_reg
= reg
;
4718 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4719 unwind
.sp_restored
= 1;
4722 /* Parse an unwind_pad directive. */
4725 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4729 if (!unwind
.proc_start
)
4730 as_bad (MISSING_FNSTART
);
4732 if (immediate_for_directive (&offset
) == FAIL
)
4737 as_bad (_("stack increment must be multiple of 4"));
4738 ignore_rest_of_line ();
4742 /* Don't generate any opcodes, just record the details for later. */
4743 unwind
.frame_size
+= offset
;
4744 unwind
.pending_offset
+= offset
;
4746 demand_empty_rest_of_line ();
4749 /* Parse an unwind_setfp directive. */
4752 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4758 if (!unwind
.proc_start
)
4759 as_bad (MISSING_FNSTART
);
4761 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4762 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4765 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4767 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4769 as_bad (_("expected <reg>, <reg>"));
4770 ignore_rest_of_line ();
4774 /* Optional constant. */
4775 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4777 if (immediate_for_directive (&offset
) == FAIL
)
4783 demand_empty_rest_of_line ();
4785 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4787 as_bad (_("register must be either sp or set by a previous"
4788 "unwind_movsp directive"));
4792 /* Don't generate any opcodes, just record the information for later. */
4793 unwind
.fp_reg
= fp_reg
;
4795 if (sp_reg
== REG_SP
)
4796 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4798 unwind
.fp_offset
-= offset
;
4801 /* Parse an unwind_raw directive. */
4804 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4807 /* This is an arbitrary limit. */
4808 unsigned char op
[16];
4811 if (!unwind
.proc_start
)
4812 as_bad (MISSING_FNSTART
);
4815 if (exp
.X_op
== O_constant
4816 && skip_past_comma (&input_line_pointer
) != FAIL
)
4818 unwind
.frame_size
+= exp
.X_add_number
;
4822 exp
.X_op
= O_illegal
;
4824 if (exp
.X_op
!= O_constant
)
4826 as_bad (_("expected <offset>, <opcode>"));
4827 ignore_rest_of_line ();
4833 /* Parse the opcode. */
4838 as_bad (_("unwind opcode too long"));
4839 ignore_rest_of_line ();
4841 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4843 as_bad (_("invalid unwind opcode"));
4844 ignore_rest_of_line ();
4847 op
[count
++] = exp
.X_add_number
;
4849 /* Parse the next byte. */
4850 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4856 /* Add the opcode bytes in reverse order. */
4858 add_unwind_opcode (op
[count
], 1);
4860 demand_empty_rest_of_line ();
4864 /* Parse a .eabi_attribute directive. */
4867 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4869 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4871 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4872 attributes_set_explicitly
[tag
] = 1;
4875 /* Emit a tls fix for the symbol. */
4878 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4882 #ifdef md_flush_pending_output
4883 md_flush_pending_output ();
4886 #ifdef md_cons_align
4890 /* Since we're just labelling the code, there's no need to define a
4893 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4894 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4895 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4896 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4898 #endif /* OBJ_ELF */
4900 static void s_arm_arch (int);
4901 static void s_arm_object_arch (int);
4902 static void s_arm_cpu (int);
4903 static void s_arm_fpu (int);
4904 static void s_arm_arch_extension (int);
4909 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4916 if (exp
.X_op
== O_symbol
)
4917 exp
.X_op
= O_secrel
;
4919 emit_expr (&exp
, 4);
4921 while (*input_line_pointer
++ == ',');
4923 input_line_pointer
--;
4924 demand_empty_rest_of_line ();
4928 /* This table describes all the machine specific pseudo-ops the assembler
4929 has to support. The fields are:
4930 pseudo-op name without dot
4931 function to call to execute this pseudo-op
4932 Integer arg to pass to the function. */
4934 const pseudo_typeS md_pseudo_table
[] =
4936 /* Never called because '.req' does not start a line. */
4937 { "req", s_req
, 0 },
4938 /* Following two are likewise never called. */
4941 { "unreq", s_unreq
, 0 },
4942 { "bss", s_bss
, 0 },
4943 { "align", s_align_ptwo
, 2 },
4944 { "arm", s_arm
, 0 },
4945 { "thumb", s_thumb
, 0 },
4946 { "code", s_code
, 0 },
4947 { "force_thumb", s_force_thumb
, 0 },
4948 { "thumb_func", s_thumb_func
, 0 },
4949 { "thumb_set", s_thumb_set
, 0 },
4950 { "even", s_even
, 0 },
4951 { "ltorg", s_ltorg
, 0 },
4952 { "pool", s_ltorg
, 0 },
4953 { "syntax", s_syntax
, 0 },
4954 { "cpu", s_arm_cpu
, 0 },
4955 { "arch", s_arm_arch
, 0 },
4956 { "object_arch", s_arm_object_arch
, 0 },
4957 { "fpu", s_arm_fpu
, 0 },
4958 { "arch_extension", s_arm_arch_extension
, 0 },
4960 { "word", s_arm_elf_cons
, 4 },
4961 { "long", s_arm_elf_cons
, 4 },
4962 { "inst.n", s_arm_elf_inst
, 2 },
4963 { "inst.w", s_arm_elf_inst
, 4 },
4964 { "inst", s_arm_elf_inst
, 0 },
4965 { "rel31", s_arm_rel31
, 0 },
4966 { "fnstart", s_arm_unwind_fnstart
, 0 },
4967 { "fnend", s_arm_unwind_fnend
, 0 },
4968 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4969 { "personality", s_arm_unwind_personality
, 0 },
4970 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4971 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4972 { "save", s_arm_unwind_save
, 0 },
4973 { "vsave", s_arm_unwind_save
, 1 },
4974 { "movsp", s_arm_unwind_movsp
, 0 },
4975 { "pad", s_arm_unwind_pad
, 0 },
4976 { "setfp", s_arm_unwind_setfp
, 0 },
4977 { "unwind_raw", s_arm_unwind_raw
, 0 },
4978 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4979 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4983 /* These are used for dwarf. */
4987 /* These are used for dwarf2. */
4988 { "file", dwarf2_directive_file
, 0 },
4989 { "loc", dwarf2_directive_loc
, 0 },
4990 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4992 { "extend", float_cons
, 'x' },
4993 { "ldouble", float_cons
, 'x' },
4994 { "packed", float_cons
, 'p' },
4996 {"secrel32", pe_directive_secrel
, 0},
4999 /* These are for compatibility with CodeComposer Studio. */
5000 {"ref", s_ccs_ref
, 0},
5001 {"def", s_ccs_def
, 0},
5002 {"asmfunc", s_ccs_asmfunc
, 0},
5003 {"endasmfunc", s_ccs_endasmfunc
, 0},
5008 /* Parser functions used exclusively in instruction operands. */
5010 /* Generic immediate-value read function for use in insn parsing.
5011 STR points to the beginning of the immediate (the leading #);
5012 VAL receives the value; if the value is outside [MIN, MAX]
5013 issue an error. PREFIX_OPT is true if the immediate prefix is
5017 parse_immediate (char **str
, int *val
, int min
, int max
,
5018 bfd_boolean prefix_opt
)
5022 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5023 if (exp
.X_op
!= O_constant
)
5025 inst
.error
= _("constant expression required");
5029 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5031 inst
.error
= _("immediate value out of range");
5035 *val
= exp
.X_add_number
;
5039 /* Less-generic immediate-value read function with the possibility of loading a
5040 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5041 instructions. Puts the result directly in inst.operands[i]. */
5044 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5045 bfd_boolean allow_symbol_p
)
5048 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5051 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5053 if (exp_p
->X_op
== O_constant
)
5055 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5056 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5057 O_constant. We have to be careful not to break compilation for
5058 32-bit X_add_number, though. */
5059 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5061 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5062 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5064 inst
.operands
[i
].regisimm
= 1;
5067 else if (exp_p
->X_op
== O_big
5068 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5070 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5072 /* Bignums have their least significant bits in
5073 generic_bignum[0]. Make sure we put 32 bits in imm and
5074 32 bits in reg, in a (hopefully) portable way. */
5075 gas_assert (parts
!= 0);
5077 /* Make sure that the number is not too big.
5078 PR 11972: Bignums can now be sign-extended to the
5079 size of a .octa so check that the out of range bits
5080 are all zero or all one. */
5081 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5083 LITTLENUM_TYPE m
= -1;
5085 if (generic_bignum
[parts
* 2] != 0
5086 && generic_bignum
[parts
* 2] != m
)
5089 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5090 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5094 inst
.operands
[i
].imm
= 0;
5095 for (j
= 0; j
< parts
; j
++, idx
++)
5096 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
5097 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5098 inst
.operands
[i
].reg
= 0;
5099 for (j
= 0; j
< parts
; j
++, idx
++)
5100 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
5101 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5102 inst
.operands
[i
].regisimm
= 1;
5104 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5112 /* Returns the pseudo-register number of an FPA immediate constant,
5113 or FAIL if there isn't a valid constant here. */
5116 parse_fpa_immediate (char ** str
)
5118 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5124 /* First try and match exact strings, this is to guarantee
5125 that some formats will work even for cross assembly. */
5127 for (i
= 0; fp_const
[i
]; i
++)
5129 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5133 *str
+= strlen (fp_const
[i
]);
5134 if (is_end_of_line
[(unsigned char) **str
])
5140 /* Just because we didn't get a match doesn't mean that the constant
5141 isn't valid, just that it is in a format that we don't
5142 automatically recognize. Try parsing it with the standard
5143 expression routines. */
5145 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5147 /* Look for a raw floating point number. */
5148 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5149 && is_end_of_line
[(unsigned char) *save_in
])
5151 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5153 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5155 if (words
[j
] != fp_values
[i
][j
])
5159 if (j
== MAX_LITTLENUMS
)
5167 /* Try and parse a more complex expression, this will probably fail
5168 unless the code uses a floating point prefix (eg "0f"). */
5169 save_in
= input_line_pointer
;
5170 input_line_pointer
= *str
;
5171 if (expression (&exp
) == absolute_section
5172 && exp
.X_op
== O_big
5173 && exp
.X_add_number
< 0)
5175 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5177 #define X_PRECISION 5
5178 #define E_PRECISION 15L
5179 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5181 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5183 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5185 if (words
[j
] != fp_values
[i
][j
])
5189 if (j
== MAX_LITTLENUMS
)
5191 *str
= input_line_pointer
;
5192 input_line_pointer
= save_in
;
5199 *str
= input_line_pointer
;
5200 input_line_pointer
= save_in
;
5201 inst
.error
= _("invalid FPA immediate expression");
5205 /* Returns 1 if a number has "quarter-precision" float format
5206 0baBbbbbbc defgh000 00000000 00000000. */
5209 is_quarter_float (unsigned imm
)
5211 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5212 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5216 /* Detect the presence of a floating point or integer zero constant,
5220 parse_ifimm_zero (char **in
)
5224 if (!is_immediate_prefix (**in
))
5226 /* In unified syntax, all prefixes are optional. */
5227 if (!unified_syntax
)
5233 /* Accept #0x0 as a synonym for #0. */
5234 if (strncmp (*in
, "0x", 2) == 0)
5237 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5242 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5243 &generic_floating_point_number
);
5246 && generic_floating_point_number
.sign
== '+'
5247 && (generic_floating_point_number
.low
5248 > generic_floating_point_number
.leader
))
5254 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5255 0baBbbbbbc defgh000 00000000 00000000.
5256 The zero and minus-zero cases need special handling, since they can't be
5257 encoded in the "quarter-precision" float format, but can nonetheless be
5258 loaded as integer constants. */
5261 parse_qfloat_immediate (char **ccp
, int *immed
)
5265 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5266 int found_fpchar
= 0;
5268 skip_past_char (&str
, '#');
5270 /* We must not accidentally parse an integer as a floating-point number. Make
5271 sure that the value we parse is not an integer by checking for special
5272 characters '.' or 'e'.
5273 FIXME: This is a horrible hack, but doing better is tricky because type
5274 information isn't in a very usable state at parse time. */
5276 skip_whitespace (fpnum
);
5278 if (strncmp (fpnum
, "0x", 2) == 0)
5282 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5283 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5293 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5295 unsigned fpword
= 0;
5298 /* Our FP word must be 32 bits (single-precision FP). */
5299 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5301 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5305 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5318 /* Shift operands. */
5321 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5324 struct asm_shift_name
5327 enum shift_kind kind
;
5330 /* Third argument to parse_shift. */
5331 enum parse_shift_mode
5333 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5334 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5335 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5336 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5337 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5338 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5341 /* Parse a <shift> specifier on an ARM data processing instruction.
5342 This has three forms:
5344 (LSL|LSR|ASL|ASR|ROR) Rs
5345 (LSL|LSR|ASL|ASR|ROR) #imm
5348 Note that ASL is assimilated to LSL in the instruction encoding, and
5349 RRX to ROR #0 (which cannot be written as such). */
5352 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5354 const struct asm_shift_name
*shift_name
;
5355 enum shift_kind shift
;
5360 for (p
= *str
; ISALPHA (*p
); p
++)
5365 inst
.error
= _("shift expression expected");
5369 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5372 if (shift_name
== NULL
)
5374 inst
.error
= _("shift expression expected");
5378 shift
= shift_name
->kind
;
5382 case NO_SHIFT_RESTRICT
:
5383 case SHIFT_IMMEDIATE
:
5384 if (shift
== SHIFT_UXTW
)
5386 inst
.error
= _("'UXTW' not allowed here");
5391 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5392 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5394 inst
.error
= _("'LSL' or 'ASR' required");
5399 case SHIFT_LSL_IMMEDIATE
:
5400 if (shift
!= SHIFT_LSL
)
5402 inst
.error
= _("'LSL' required");
5407 case SHIFT_ASR_IMMEDIATE
:
5408 if (shift
!= SHIFT_ASR
)
5410 inst
.error
= _("'ASR' required");
5414 case SHIFT_UXTW_IMMEDIATE
:
5415 if (shift
!= SHIFT_UXTW
)
5417 inst
.error
= _("'UXTW' required");
5425 if (shift
!= SHIFT_RRX
)
5427 /* Whitespace can appear here if the next thing is a bare digit. */
5428 skip_whitespace (p
);
5430 if (mode
== NO_SHIFT_RESTRICT
5431 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5433 inst
.operands
[i
].imm
= reg
;
5434 inst
.operands
[i
].immisreg
= 1;
5436 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5439 inst
.operands
[i
].shift_kind
= shift
;
5440 inst
.operands
[i
].shifted
= 1;
5445 /* Parse a <shifter_operand> for an ARM data processing instruction:
5448 #<immediate>, <rotate>
5452 where <shift> is defined by parse_shift above, and <rotate> is a
5453 multiple of 2 between 0 and 30. Validation of immediate operands
5454 is deferred to md_apply_fix. */
5457 parse_shifter_operand (char **str
, int i
)
5462 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5464 inst
.operands
[i
].reg
= value
;
5465 inst
.operands
[i
].isreg
= 1;
5467 /* parse_shift will override this if appropriate */
5468 inst
.relocs
[0].exp
.X_op
= O_constant
;
5469 inst
.relocs
[0].exp
.X_add_number
= 0;
5471 if (skip_past_comma (str
) == FAIL
)
5474 /* Shift operation on register. */
5475 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5478 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5481 if (skip_past_comma (str
) == SUCCESS
)
5483 /* #x, y -- ie explicit rotation by Y. */
5484 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5487 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5489 inst
.error
= _("constant expression expected");
5493 value
= exp
.X_add_number
;
5494 if (value
< 0 || value
> 30 || value
% 2 != 0)
5496 inst
.error
= _("invalid rotation");
5499 if (inst
.relocs
[0].exp
.X_add_number
< 0
5500 || inst
.relocs
[0].exp
.X_add_number
> 255)
5502 inst
.error
= _("invalid constant");
5506 /* Encode as specified. */
5507 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5511 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5512 inst
.relocs
[0].pc_rel
= 0;
5516 /* Group relocation information. Each entry in the table contains the
5517 textual name of the relocation as may appear in assembler source
5518 and must end with a colon.
5519 Along with this textual name are the relocation codes to be used if
5520 the corresponding instruction is an ALU instruction (ADD or SUB only),
5521 an LDR, an LDRS, or an LDC. */
5523 struct group_reloc_table_entry
5534 /* Varieties of non-ALU group relocation. */
5542 static struct group_reloc_table_entry group_reloc_table
[] =
5543 { /* Program counter relative: */
5545 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5550 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5551 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5552 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5553 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5555 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5560 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5561 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5562 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5563 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5565 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5566 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5567 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5568 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5569 /* Section base relative */
5571 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5576 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5577 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5578 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5579 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5581 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5586 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5587 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5588 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5589 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5591 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5592 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5593 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5594 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5595 /* Absolute thumb alu relocations. */
5597 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5602 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5607 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5612 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5617 /* Given the address of a pointer pointing to the textual name of a group
5618 relocation as may appear in assembler source, attempt to find its details
5619 in group_reloc_table. The pointer will be updated to the character after
5620 the trailing colon. On failure, FAIL will be returned; SUCCESS
5621 otherwise. On success, *entry will be updated to point at the relevant
5622 group_reloc_table entry. */
5625 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5628 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5630 int length
= strlen (group_reloc_table
[i
].name
);
5632 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5633 && (*str
)[length
] == ':')
5635 *out
= &group_reloc_table
[i
];
5636 *str
+= (length
+ 1);
5644 /* Parse a <shifter_operand> for an ARM data processing instruction
5645 (as for parse_shifter_operand) where group relocations are allowed:
5648 #<immediate>, <rotate>
5649 #:<group_reloc>:<expression>
5653 where <group_reloc> is one of the strings defined in group_reloc_table.
5654 The hashes are optional.
5656 Everything else is as for parse_shifter_operand. */
5658 static parse_operand_result
5659 parse_shifter_operand_group_reloc (char **str
, int i
)
5661 /* Determine if we have the sequence of characters #: or just :
5662 coming next. If we do, then we check for a group relocation.
5663 If we don't, punt the whole lot to parse_shifter_operand. */
5665 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5666 || (*str
)[0] == ':')
5668 struct group_reloc_table_entry
*entry
;
5670 if ((*str
)[0] == '#')
5675 /* Try to parse a group relocation. Anything else is an error. */
5676 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5678 inst
.error
= _("unknown group relocation");
5679 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5682 /* We now have the group relocation table entry corresponding to
5683 the name in the assembler source. Next, we parse the expression. */
5684 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5685 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5687 /* Record the relocation type (always the ALU variant here). */
5688 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5689 gas_assert (inst
.relocs
[0].type
!= 0);
5691 return PARSE_OPERAND_SUCCESS
;
5694 return parse_shifter_operand (str
, i
) == SUCCESS
5695 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5697 /* Never reached. */
5700 /* Parse a Neon alignment expression. Information is written to
5701 inst.operands[i]. We assume the initial ':' has been skipped.
5703 align .imm = align << 8, .immisalign=1, .preind=0 */
5704 static parse_operand_result
5705 parse_neon_alignment (char **str
, int i
)
5710 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5712 if (exp
.X_op
!= O_constant
)
5714 inst
.error
= _("alignment must be constant");
5715 return PARSE_OPERAND_FAIL
;
5718 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5719 inst
.operands
[i
].immisalign
= 1;
5720 /* Alignments are not pre-indexes. */
5721 inst
.operands
[i
].preind
= 0;
5724 return PARSE_OPERAND_SUCCESS
;
5727 /* Parse all forms of an ARM address expression. Information is written
5728 to inst.operands[i] and/or inst.relocs[0].
5730 Preindexed addressing (.preind=1):
5732 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5733 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5734 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5735 .shift_kind=shift .relocs[0].exp=shift_imm
5737 These three may have a trailing ! which causes .writeback to be set also.
5739 Postindexed addressing (.postind=1, .writeback=1):
5741 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5742 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5743 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5744 .shift_kind=shift .relocs[0].exp=shift_imm
5746 Unindexed addressing (.preind=0, .postind=0):
5748 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5752 [Rn]{!} shorthand for [Rn,#0]{!}
5753 =immediate .isreg=0 .relocs[0].exp=immediate
5754 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5756 It is the caller's responsibility to check for addressing modes not
5757 supported by the instruction, and to set inst.relocs[0].type. */
5759 static parse_operand_result
5760 parse_address_main (char **str
, int i
, int group_relocations
,
5761 group_reloc_type group_type
)
5766 if (skip_past_char (&p
, '[') == FAIL
)
5768 if (skip_past_char (&p
, '=') == FAIL
)
5770 /* Bare address - translate to PC-relative offset. */
5771 inst
.relocs
[0].pc_rel
= 1;
5772 inst
.operands
[i
].reg
= REG_PC
;
5773 inst
.operands
[i
].isreg
= 1;
5774 inst
.operands
[i
].preind
= 1;
5776 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5777 return PARSE_OPERAND_FAIL
;
5779 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5780 /*allow_symbol_p=*/TRUE
))
5781 return PARSE_OPERAND_FAIL
;
5784 return PARSE_OPERAND_SUCCESS
;
5787 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5788 skip_whitespace (p
);
5790 if (group_type
== GROUP_MVE
)
5792 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5793 struct neon_type_el et
;
5794 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5796 inst
.operands
[i
].isquad
= 1;
5798 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5800 inst
.error
= BAD_ADDR_MODE
;
5801 return PARSE_OPERAND_FAIL
;
5804 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5806 if (group_type
== GROUP_MVE
)
5807 inst
.error
= BAD_ADDR_MODE
;
5809 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5810 return PARSE_OPERAND_FAIL
;
5812 inst
.operands
[i
].reg
= reg
;
5813 inst
.operands
[i
].isreg
= 1;
5815 if (skip_past_comma (&p
) == SUCCESS
)
5817 inst
.operands
[i
].preind
= 1;
5820 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5822 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5823 struct neon_type_el et
;
5824 if (group_type
== GROUP_MVE
5825 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5827 inst
.operands
[i
].immisreg
= 2;
5828 inst
.operands
[i
].imm
= reg
;
5830 if (skip_past_comma (&p
) == SUCCESS
)
5832 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
5834 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
5835 inst
.relocs
[0].exp
.X_add_number
= 0;
5838 return PARSE_OPERAND_FAIL
;
5841 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5843 inst
.operands
[i
].imm
= reg
;
5844 inst
.operands
[i
].immisreg
= 1;
5846 if (skip_past_comma (&p
) == SUCCESS
)
5847 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5848 return PARSE_OPERAND_FAIL
;
5850 else if (skip_past_char (&p
, ':') == SUCCESS
)
5852 /* FIXME: '@' should be used here, but it's filtered out by generic
5853 code before we get to see it here. This may be subject to
5855 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5857 if (result
!= PARSE_OPERAND_SUCCESS
)
5862 if (inst
.operands
[i
].negative
)
5864 inst
.operands
[i
].negative
= 0;
5868 if (group_relocations
5869 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5871 struct group_reloc_table_entry
*entry
;
5873 /* Skip over the #: or : sequence. */
5879 /* Try to parse a group relocation. Anything else is an
5881 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5883 inst
.error
= _("unknown group relocation");
5884 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5887 /* We now have the group relocation table entry corresponding to
5888 the name in the assembler source. Next, we parse the
5890 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5891 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5893 /* Record the relocation type. */
5898 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
5903 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5908 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
5915 if (inst
.relocs
[0].type
== 0)
5917 inst
.error
= _("this group relocation is not allowed on this instruction");
5918 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5925 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5926 return PARSE_OPERAND_FAIL
;
5927 /* If the offset is 0, find out if it's a +0 or -0. */
5928 if (inst
.relocs
[0].exp
.X_op
== O_constant
5929 && inst
.relocs
[0].exp
.X_add_number
== 0)
5931 skip_whitespace (q
);
5935 skip_whitespace (q
);
5938 inst
.operands
[i
].negative
= 1;
5943 else if (skip_past_char (&p
, ':') == SUCCESS
)
5945 /* FIXME: '@' should be used here, but it's filtered out by generic code
5946 before we get to see it here. This may be subject to change. */
5947 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5949 if (result
!= PARSE_OPERAND_SUCCESS
)
5953 if (skip_past_char (&p
, ']') == FAIL
)
5955 inst
.error
= _("']' expected");
5956 return PARSE_OPERAND_FAIL
;
5959 if (skip_past_char (&p
, '!') == SUCCESS
)
5960 inst
.operands
[i
].writeback
= 1;
5962 else if (skip_past_comma (&p
) == SUCCESS
)
5964 if (skip_past_char (&p
, '{') == SUCCESS
)
5966 /* [Rn], {expr} - unindexed, with option */
5967 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5968 0, 255, TRUE
) == FAIL
)
5969 return PARSE_OPERAND_FAIL
;
5971 if (skip_past_char (&p
, '}') == FAIL
)
5973 inst
.error
= _("'}' expected at end of 'option' field");
5974 return PARSE_OPERAND_FAIL
;
5976 if (inst
.operands
[i
].preind
)
5978 inst
.error
= _("cannot combine index with option");
5979 return PARSE_OPERAND_FAIL
;
5982 return PARSE_OPERAND_SUCCESS
;
5986 inst
.operands
[i
].postind
= 1;
5987 inst
.operands
[i
].writeback
= 1;
5989 if (inst
.operands
[i
].preind
)
5991 inst
.error
= _("cannot combine pre- and post-indexing");
5992 return PARSE_OPERAND_FAIL
;
5996 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5998 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5999 struct neon_type_el et
;
6000 if (group_type
== GROUP_MVE
6001 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6003 inst
.operands
[i
].immisreg
= 2;
6004 inst
.operands
[i
].imm
= reg
;
6006 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6008 /* We might be using the immediate for alignment already. If we
6009 are, OR the register number into the low-order bits. */
6010 if (inst
.operands
[i
].immisalign
)
6011 inst
.operands
[i
].imm
|= reg
;
6013 inst
.operands
[i
].imm
= reg
;
6014 inst
.operands
[i
].immisreg
= 1;
6016 if (skip_past_comma (&p
) == SUCCESS
)
6017 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6018 return PARSE_OPERAND_FAIL
;
6024 if (inst
.operands
[i
].negative
)
6026 inst
.operands
[i
].negative
= 0;
6029 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6030 return PARSE_OPERAND_FAIL
;
6031 /* If the offset is 0, find out if it's a +0 or -0. */
6032 if (inst
.relocs
[0].exp
.X_op
== O_constant
6033 && inst
.relocs
[0].exp
.X_add_number
== 0)
6035 skip_whitespace (q
);
6039 skip_whitespace (q
);
6042 inst
.operands
[i
].negative
= 1;
6048 /* If at this point neither .preind nor .postind is set, we have a
6049 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6050 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6052 inst
.operands
[i
].preind
= 1;
6053 inst
.relocs
[0].exp
.X_op
= O_constant
;
6054 inst
.relocs
[0].exp
.X_add_number
= 0;
6057 return PARSE_OPERAND_SUCCESS
;
6061 parse_address (char **str
, int i
)
6063 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6067 static parse_operand_result
6068 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6070 return parse_address_main (str
, i
, 1, type
);
6073 /* Parse an operand for a MOVW or MOVT instruction. */
6075 parse_half (char **str
)
6080 skip_past_char (&p
, '#');
6081 if (strncasecmp (p
, ":lower16:", 9) == 0)
6082 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6083 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6084 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6086 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6089 skip_whitespace (p
);
6092 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6095 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6097 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6099 inst
.error
= _("constant expression expected");
6102 if (inst
.relocs
[0].exp
.X_add_number
< 0
6103 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6105 inst
.error
= _("immediate value out of range");
6113 /* Miscellaneous. */
6115 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6116 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6118 parse_psr (char **str
, bfd_boolean lhs
)
6121 unsigned long psr_field
;
6122 const struct asm_psr
*psr
;
6124 bfd_boolean is_apsr
= FALSE
;
6125 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6127 /* PR gas/12698: If the user has specified -march=all then m_profile will
6128 be TRUE, but we want to ignore it in this case as we are building for any
6129 CPU type, including non-m variants. */
6130 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6133 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6134 feature for ease of use and backwards compatibility. */
6136 if (strncasecmp (p
, "SPSR", 4) == 0)
6139 goto unsupported_psr
;
6141 psr_field
= SPSR_BIT
;
6143 else if (strncasecmp (p
, "CPSR", 4) == 0)
6146 goto unsupported_psr
;
6150 else if (strncasecmp (p
, "APSR", 4) == 0)
6152 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6153 and ARMv7-R architecture CPUs. */
6162 while (ISALNUM (*p
) || *p
== '_');
6164 if (strncasecmp (start
, "iapsr", 5) == 0
6165 || strncasecmp (start
, "eapsr", 5) == 0
6166 || strncasecmp (start
, "xpsr", 4) == 0
6167 || strncasecmp (start
, "psr", 3) == 0)
6168 p
= start
+ strcspn (start
, "rR") + 1;
6170 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
6176 /* If APSR is being written, a bitfield may be specified. Note that
6177 APSR itself is handled above. */
6178 if (psr
->field
<= 3)
6180 psr_field
= psr
->field
;
6186 /* M-profile MSR instructions have the mask field set to "10", except
6187 *PSR variants which modify APSR, which may use a different mask (and
6188 have been handled already). Do that by setting the PSR_f field
6190 return psr
->field
| (lhs
? PSR_f
: 0);
6193 goto unsupported_psr
;
6199 /* A suffix follows. */
6205 while (ISALNUM (*p
) || *p
== '_');
6209 /* APSR uses a notation for bits, rather than fields. */
6210 unsigned int nzcvq_bits
= 0;
6211 unsigned int g_bit
= 0;
6214 for (bit
= start
; bit
!= p
; bit
++)
6216 switch (TOLOWER (*bit
))
6219 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6223 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6227 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6231 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6235 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6239 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6243 inst
.error
= _("unexpected bit specified after APSR");
6248 if (nzcvq_bits
== 0x1f)
6253 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6255 inst
.error
= _("selected processor does not "
6256 "support DSP extension");
6263 if ((nzcvq_bits
& 0x20) != 0
6264 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6265 || (g_bit
& 0x2) != 0)
6267 inst
.error
= _("bad bitmask specified after APSR");
6273 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6278 psr_field
|= psr
->field
;
6284 goto error
; /* Garbage after "[CS]PSR". */
6286 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6287 is deprecated, but allow it anyway. */
6291 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6294 else if (!m_profile
)
6295 /* These bits are never right for M-profile devices: don't set them
6296 (only code paths which read/write APSR reach here). */
6297 psr_field
|= (PSR_c
| PSR_f
);
6303 inst
.error
= _("selected processor does not support requested special "
6304 "purpose register");
6308 inst
.error
= _("flag for {c}psr instruction expected");
6313 parse_sys_vldr_vstr (char **str
)
6322 {"FPSCR", 0x1, 0x0},
6323 {"FPSCR_nzcvqc", 0x2, 0x0},
6326 {"FPCXTNS", 0x6, 0x1},
6327 {"FPCXTS", 0x7, 0x1}
6329 char *op_end
= strchr (*str
, ',');
6330 size_t op_strlen
= op_end
- *str
;
6332 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6334 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6336 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6345 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6346 value suitable for splatting into the AIF field of the instruction. */
6349 parse_cps_flags (char **str
)
6358 case '\0': case ',':
6361 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6362 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6363 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6366 inst
.error
= _("unrecognized CPS flag");
6371 if (saw_a_flag
== 0)
6373 inst
.error
= _("missing CPS flags");
6381 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6382 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6385 parse_endian_specifier (char **str
)
6390 if (strncasecmp (s
, "BE", 2))
6392 else if (strncasecmp (s
, "LE", 2))
6396 inst
.error
= _("valid endian specifiers are be or le");
6400 if (ISALNUM (s
[2]) || s
[2] == '_')
6402 inst
.error
= _("valid endian specifiers are be or le");
6407 return little_endian
;
6410 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6411 value suitable for poking into the rotate field of an sxt or sxta
6412 instruction, or FAIL on error. */
6415 parse_ror (char **str
)
6420 if (strncasecmp (s
, "ROR", 3) == 0)
6424 inst
.error
= _("missing rotation field after comma");
6428 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6433 case 0: *str
= s
; return 0x0;
6434 case 8: *str
= s
; return 0x1;
6435 case 16: *str
= s
; return 0x2;
6436 case 24: *str
= s
; return 0x3;
6439 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6444 /* Parse a conditional code (from conds[] below). The value returned is in the
6445 range 0 .. 14, or FAIL. */
6447 parse_cond (char **str
)
6450 const struct asm_cond
*c
;
6452 /* Condition codes are always 2 characters, so matching up to
6453 3 characters is sufficient. */
6458 while (ISALPHA (*q
) && n
< 3)
6460 cond
[n
] = TOLOWER (*q
);
6465 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6468 inst
.error
= _("condition required");
6476 /* Parse an option for a barrier instruction. Returns the encoding for the
6479 parse_barrier (char **str
)
6482 const struct asm_barrier_opt
*o
;
6485 while (ISALPHA (*q
))
6488 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6493 if (!mark_feature_used (&o
->arch
))
6500 /* Parse the operands of a table branch instruction. Similar to a memory
6503 parse_tb (char **str
)
6508 if (skip_past_char (&p
, '[') == FAIL
)
6510 inst
.error
= _("'[' expected");
6514 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6516 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6519 inst
.operands
[0].reg
= reg
;
6521 if (skip_past_comma (&p
) == FAIL
)
6523 inst
.error
= _("',' expected");
6527 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6529 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6532 inst
.operands
[0].imm
= reg
;
6534 if (skip_past_comma (&p
) == SUCCESS
)
6536 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6538 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6540 inst
.error
= _("invalid shift");
6543 inst
.operands
[0].shifted
= 1;
6546 if (skip_past_char (&p
, ']') == FAIL
)
6548 inst
.error
= _("']' expected");
6555 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6556 information on the types the operands can take and how they are encoded.
6557 Up to four operands may be read; this function handles setting the
6558 ".present" field for each read operand itself.
6559 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6560 else returns FAIL. */
6563 parse_neon_mov (char **str
, int *which_operand
)
6565 int i
= *which_operand
, val
;
6566 enum arm_reg_type rtype
;
6568 struct neon_type_el optype
;
6570 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6572 /* Cases 17 or 19. */
6573 inst
.operands
[i
].reg
= val
;
6574 inst
.operands
[i
].isvec
= 1;
6575 inst
.operands
[i
].isscalar
= 2;
6576 inst
.operands
[i
].vectype
= optype
;
6577 inst
.operands
[i
++].present
= 1;
6579 if (skip_past_comma (&ptr
) == FAIL
)
6582 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6584 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6585 inst
.operands
[i
].reg
= val
;
6586 inst
.operands
[i
].isreg
= 1;
6587 inst
.operands
[i
].present
= 1;
6589 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6591 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6592 inst
.operands
[i
].reg
= val
;
6593 inst
.operands
[i
].isvec
= 1;
6594 inst
.operands
[i
].isscalar
= 2;
6595 inst
.operands
[i
].vectype
= optype
;
6596 inst
.operands
[i
++].present
= 1;
6598 if (skip_past_comma (&ptr
) == FAIL
)
6601 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6604 inst
.operands
[i
].reg
= val
;
6605 inst
.operands
[i
].isreg
= 1;
6606 inst
.operands
[i
++].present
= 1;
6608 if (skip_past_comma (&ptr
) == FAIL
)
6611 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6614 inst
.operands
[i
].reg
= val
;
6615 inst
.operands
[i
].isreg
= 1;
6616 inst
.operands
[i
].present
= 1;
6620 first_error (_("expected ARM or MVE vector register"));
6624 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6626 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6627 inst
.operands
[i
].reg
= val
;
6628 inst
.operands
[i
].isscalar
= 1;
6629 inst
.operands
[i
].vectype
= optype
;
6630 inst
.operands
[i
++].present
= 1;
6632 if (skip_past_comma (&ptr
) == FAIL
)
6635 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6638 inst
.operands
[i
].reg
= val
;
6639 inst
.operands
[i
].isreg
= 1;
6640 inst
.operands
[i
].present
= 1;
6642 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6644 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6647 /* Cases 0, 1, 2, 3, 5 (D only). */
6648 if (skip_past_comma (&ptr
) == FAIL
)
6651 inst
.operands
[i
].reg
= val
;
6652 inst
.operands
[i
].isreg
= 1;
6653 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6654 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6655 inst
.operands
[i
].isvec
= 1;
6656 inst
.operands
[i
].vectype
= optype
;
6657 inst
.operands
[i
++].present
= 1;
6659 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6661 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6662 Case 13: VMOV <Sd>, <Rm> */
6663 inst
.operands
[i
].reg
= val
;
6664 inst
.operands
[i
].isreg
= 1;
6665 inst
.operands
[i
].present
= 1;
6667 if (rtype
== REG_TYPE_NQ
)
6669 first_error (_("can't use Neon quad register here"));
6672 else if (rtype
!= REG_TYPE_VFS
)
6675 if (skip_past_comma (&ptr
) == FAIL
)
6677 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6679 inst
.operands
[i
].reg
= val
;
6680 inst
.operands
[i
].isreg
= 1;
6681 inst
.operands
[i
].present
= 1;
6684 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6687 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6688 Case 1: VMOV<c><q> <Dd>, <Dm>
6689 Case 8: VMOV.F32 <Sd>, <Sm>
6690 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6692 inst
.operands
[i
].reg
= val
;
6693 inst
.operands
[i
].isreg
= 1;
6694 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6695 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6696 inst
.operands
[i
].isvec
= 1;
6697 inst
.operands
[i
].vectype
= optype
;
6698 inst
.operands
[i
].present
= 1;
6700 if (skip_past_comma (&ptr
) == SUCCESS
)
6705 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6708 inst
.operands
[i
].reg
= val
;
6709 inst
.operands
[i
].isreg
= 1;
6710 inst
.operands
[i
++].present
= 1;
6712 if (skip_past_comma (&ptr
) == FAIL
)
6715 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6718 inst
.operands
[i
].reg
= val
;
6719 inst
.operands
[i
].isreg
= 1;
6720 inst
.operands
[i
].present
= 1;
6723 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6724 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6725 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6726 Case 10: VMOV.F32 <Sd>, #<imm>
6727 Case 11: VMOV.F64 <Dd>, #<imm> */
6728 inst
.operands
[i
].immisfloat
= 1;
6729 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6731 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6732 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6736 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6740 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6742 /* Cases 6, 7, 16, 18. */
6743 inst
.operands
[i
].reg
= val
;
6744 inst
.operands
[i
].isreg
= 1;
6745 inst
.operands
[i
++].present
= 1;
6747 if (skip_past_comma (&ptr
) == FAIL
)
6750 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6752 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6753 inst
.operands
[i
].reg
= val
;
6754 inst
.operands
[i
].isscalar
= 2;
6755 inst
.operands
[i
].present
= 1;
6756 inst
.operands
[i
].vectype
= optype
;
6758 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6760 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6761 inst
.operands
[i
].reg
= val
;
6762 inst
.operands
[i
].isscalar
= 1;
6763 inst
.operands
[i
].present
= 1;
6764 inst
.operands
[i
].vectype
= optype
;
6766 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6768 inst
.operands
[i
].reg
= val
;
6769 inst
.operands
[i
].isreg
= 1;
6770 inst
.operands
[i
++].present
= 1;
6772 if (skip_past_comma (&ptr
) == FAIL
)
6775 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6778 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6780 inst
.operands
[i
].reg
= val
;
6781 inst
.operands
[i
].isreg
= 1;
6782 inst
.operands
[i
].isvec
= 1;
6783 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6784 inst
.operands
[i
].vectype
= optype
;
6785 inst
.operands
[i
].present
= 1;
6787 if (rtype
== REG_TYPE_VFS
)
6791 if (skip_past_comma (&ptr
) == FAIL
)
6793 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6796 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6799 inst
.operands
[i
].reg
= val
;
6800 inst
.operands
[i
].isreg
= 1;
6801 inst
.operands
[i
].isvec
= 1;
6802 inst
.operands
[i
].issingle
= 1;
6803 inst
.operands
[i
].vectype
= optype
;
6804 inst
.operands
[i
].present
= 1;
6809 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6812 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6813 inst
.operands
[i
].reg
= val
;
6814 inst
.operands
[i
].isvec
= 1;
6815 inst
.operands
[i
].isscalar
= 2;
6816 inst
.operands
[i
].vectype
= optype
;
6817 inst
.operands
[i
++].present
= 1;
6819 if (skip_past_comma (&ptr
) == FAIL
)
6822 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6825 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
6828 inst
.operands
[i
].reg
= val
;
6829 inst
.operands
[i
].isvec
= 1;
6830 inst
.operands
[i
].isscalar
= 2;
6831 inst
.operands
[i
].vectype
= optype
;
6832 inst
.operands
[i
].present
= 1;
6836 first_error (_("VFP single, double or MVE vector register"
6842 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6846 inst
.operands
[i
].reg
= val
;
6847 inst
.operands
[i
].isreg
= 1;
6848 inst
.operands
[i
].isvec
= 1;
6849 inst
.operands
[i
].issingle
= 1;
6850 inst
.operands
[i
].vectype
= optype
;
6851 inst
.operands
[i
].present
= 1;
6856 first_error (_("parse error"));
6860 /* Successfully parsed the operands. Update args. */
6866 first_error (_("expected comma"));
6870 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6874 /* Use this macro when the operand constraints are different
6875 for ARM and THUMB (e.g. ldrd). */
6876 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6877 ((arm_operand) | ((thumb_operand) << 16))
6879 /* Matcher codes for parse_operands. */
6880 enum operand_parse_code
6882 OP_stop
, /* end of line */
6884 OP_RR
, /* ARM register */
6885 OP_RRnpc
, /* ARM register, not r15 */
6886 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6887 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6888 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6889 optional trailing ! */
6890 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6891 OP_RCP
, /* Coprocessor number */
6892 OP_RCN
, /* Coprocessor register */
6893 OP_RF
, /* FPA register */
6894 OP_RVS
, /* VFP single precision register */
6895 OP_RVD
, /* VFP double precision register (0..15) */
6896 OP_RND
, /* Neon double precision register (0..31) */
6897 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
6898 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
6900 OP_RNQ
, /* Neon quad precision register */
6901 OP_RNQMQ
, /* Neon quad or MVE vector register. */
6902 OP_RVSD
, /* VFP single or double precision register */
6903 OP_RVSD_COND
, /* VFP single, double precision register or condition code. */
6904 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
6905 OP_RNSD
, /* Neon single or double precision register */
6906 OP_RNDQ
, /* Neon double or quad precision register */
6907 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
6908 OP_RNDQMQR
, /* Neon double, quad, MVE vector or ARM register. */
6909 OP_RNSDQ
, /* Neon single, double or quad precision register */
6910 OP_RNSC
, /* Neon scalar D[X] */
6911 OP_RVC
, /* VFP control register */
6912 OP_RMF
, /* Maverick F register */
6913 OP_RMD
, /* Maverick D register */
6914 OP_RMFX
, /* Maverick FX register */
6915 OP_RMDX
, /* Maverick DX register */
6916 OP_RMAX
, /* Maverick AX register */
6917 OP_RMDS
, /* Maverick DSPSC register */
6918 OP_RIWR
, /* iWMMXt wR register */
6919 OP_RIWC
, /* iWMMXt wC register */
6920 OP_RIWG
, /* iWMMXt wCG register */
6921 OP_RXA
, /* XScale accumulator register */
6923 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
6925 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
6927 OP_RMQ
, /* MVE vector register. */
6928 OP_RMQRZ
, /* MVE vector or ARM register including ZR. */
6929 OP_RMQRR
, /* MVE vector or ARM register. */
6931 /* New operands for Armv8.1-M Mainline. */
6932 OP_LR
, /* ARM LR register */
6933 OP_RRe
, /* ARM register, only even numbered. */
6934 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
6935 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
6936 OP_RR_ZR
, /* ARM register or ZR but no PC */
6938 OP_REGLST
, /* ARM register list */
6939 OP_CLRMLST
, /* CLRM register list */
6940 OP_VRSLST
, /* VFP single-precision register list */
6941 OP_VRDLST
, /* VFP double-precision register list */
6942 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6943 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6944 OP_NSTRLST
, /* Neon element/structure list */
6945 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
6946 OP_MSTRLST2
, /* MVE vector list with two elements. */
6947 OP_MSTRLST4
, /* MVE vector list with four elements. */
6949 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6950 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6951 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6952 OP_RSVDMQ_FI0
, /* VFP S, D, MVE vector register or floating point immediate
6954 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6955 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
6956 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6957 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
6959 OP_RNSDQ_RNSC_MQ_RR
, /* Vector S, D or Q reg, or MVE vector reg , or Neon
6960 scalar, or ARM register. */
6961 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6962 OP_RNDQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, or ARM register. */
6963 OP_RNDQMQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
6965 OP_RNDQMQ_RNSC
, /* Neon D, Q or MVE vector reg, or Neon scalar. */
6966 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6967 OP_VMOV
, /* Neon VMOV operands. */
6968 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6969 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
6971 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6972 OP_RNDQMQ_I63b_RR
, /* Neon D or Q reg, immediate for shift, MVE vector or
6974 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6975 OP_VLDR
, /* VLDR operand. */
6977 OP_I0
, /* immediate zero */
6978 OP_I7
, /* immediate value 0 .. 7 */
6979 OP_I15
, /* 0 .. 15 */
6980 OP_I16
, /* 1 .. 16 */
6981 OP_I16z
, /* 0 .. 16 */
6982 OP_I31
, /* 0 .. 31 */
6983 OP_I31w
, /* 0 .. 31, optional trailing ! */
6984 OP_I32
, /* 1 .. 32 */
6985 OP_I32z
, /* 0 .. 32 */
6986 OP_I63
, /* 0 .. 63 */
6987 OP_I63s
, /* -64 .. 63 */
6988 OP_I64
, /* 1 .. 64 */
6989 OP_I64z
, /* 0 .. 64 */
6990 OP_I255
, /* 0 .. 255 */
6992 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6993 OP_I7b
, /* 0 .. 7 */
6994 OP_I15b
, /* 0 .. 15 */
6995 OP_I31b
, /* 0 .. 31 */
6997 OP_SH
, /* shifter operand */
6998 OP_SHG
, /* shifter operand with possible group relocation */
6999 OP_ADDR
, /* Memory address expression (any mode) */
7000 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
7001 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
7002 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
7003 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
7004 OP_EXP
, /* arbitrary expression */
7005 OP_EXPi
, /* same, with optional immediate prefix */
7006 OP_EXPr
, /* same, with optional relocation suffix */
7007 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
7008 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
7009 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
7010 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7012 OP_CPSF
, /* CPS flags */
7013 OP_ENDI
, /* Endianness specifier */
7014 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
7015 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
7016 OP_COND
, /* conditional code */
7017 OP_TB
, /* Table branch. */
7019 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
7021 OP_RRnpc_I0
, /* ARM register or literal 0 */
7022 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7023 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7024 OP_RF_IF
, /* FPA register or immediate */
7025 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7026 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7028 /* Optional operands. */
7029 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7030 OP_oI31b
, /* 0 .. 31 */
7031 OP_oI32b
, /* 1 .. 32 */
7032 OP_oI32z
, /* 0 .. 32 */
7033 OP_oIffffb
, /* 0 .. 65535 */
7034 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7036 OP_oRR
, /* ARM register */
7037 OP_oLR
, /* ARM LR register */
7038 OP_oRRnpc
, /* ARM register, not the PC */
7039 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7040 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7041 OP_oRND
, /* Optional Neon double precision register */
7042 OP_oRNQ
, /* Optional Neon quad precision register */
7043 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7044 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7045 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7046 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7048 OP_oSHll
, /* LSL immediate */
7049 OP_oSHar
, /* ASR immediate */
7050 OP_oSHllar
, /* LSL or ASR immediate */
7051 OP_oROR
, /* ROR 0/8/16/24 */
7052 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7054 OP_oRMQRZ
, /* optional MVE vector or ARM register including ZR. */
7056 /* Some pre-defined mixed (ARM/THUMB) operands. */
7057 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7058 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7059 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7061 OP_FIRST_OPTIONAL
= OP_oI7b
7064 /* Generic instruction operand parser. This does no encoding and no
7065 semantic validation; it merely squirrels values away in the inst
7066 structure. Returns SUCCESS or FAIL depending on whether the
7067 specified grammar matched. */
7069 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
7071 unsigned const int *upat
= pattern
;
7072 char *backtrack_pos
= 0;
7073 const char *backtrack_error
= 0;
7074 int i
, val
= 0, backtrack_index
= 0;
7075 enum arm_reg_type rtype
;
7076 parse_operand_result result
;
7077 unsigned int op_parse_code
;
7078 bfd_boolean partial_match
;
7080 #define po_char_or_fail(chr) \
7083 if (skip_past_char (&str, chr) == FAIL) \
7088 #define po_reg_or_fail(regtype) \
7091 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7092 & inst.operands[i].vectype); \
7095 first_error (_(reg_expected_msgs[regtype])); \
7098 inst.operands[i].reg = val; \
7099 inst.operands[i].isreg = 1; \
7100 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7101 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7102 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7103 || rtype == REG_TYPE_VFD \
7104 || rtype == REG_TYPE_NQ); \
7105 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7109 #define po_reg_or_goto(regtype, label) \
7112 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7113 & inst.operands[i].vectype); \
7117 inst.operands[i].reg = val; \
7118 inst.operands[i].isreg = 1; \
7119 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7120 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7121 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7122 || rtype == REG_TYPE_VFD \
7123 || rtype == REG_TYPE_NQ); \
7124 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7128 #define po_imm_or_fail(min, max, popt) \
7131 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7133 inst.operands[i].imm = val; \
7137 #define po_scalar_or_goto(elsz, label, reg_type) \
7140 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7144 inst.operands[i].reg = val; \
7145 inst.operands[i].isscalar = 1; \
7149 #define po_misc_or_fail(expr) \
7157 #define po_misc_or_fail_no_backtrack(expr) \
7161 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7162 backtrack_pos = 0; \
7163 if (result != PARSE_OPERAND_SUCCESS) \
7168 #define po_barrier_or_imm(str) \
7171 val = parse_barrier (&str); \
7172 if (val == FAIL && ! ISALPHA (*str)) \
7175 /* ISB can only take SY as an option. */ \
7176 || ((inst.instruction & 0xf0) == 0x60 \
7179 inst.error = _("invalid barrier type"); \
7180 backtrack_pos = 0; \
7186 skip_whitespace (str
);
7188 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7190 op_parse_code
= upat
[i
];
7191 if (op_parse_code
>= 1<<16)
7192 op_parse_code
= thumb
? (op_parse_code
>> 16)
7193 : (op_parse_code
& ((1<<16)-1));
7195 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7197 /* Remember where we are in case we need to backtrack. */
7198 backtrack_pos
= str
;
7199 backtrack_error
= inst
.error
;
7200 backtrack_index
= i
;
7203 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7204 po_char_or_fail (',');
7206 switch (op_parse_code
)
7218 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7219 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7220 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7221 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7222 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7223 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7226 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7230 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7233 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7235 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7237 /* Also accept generic coprocessor regs for unknown registers. */
7239 po_reg_or_fail (REG_TYPE_CN
);
7241 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7242 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7243 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7244 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7245 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7246 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7247 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7248 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7249 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7250 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7253 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7256 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7257 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7259 po_reg_or_goto (REG_TYPE_RN
, try_rndqmq
);
7264 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7268 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7270 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7273 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7275 po_reg_or_goto (REG_TYPE_VFSD
, try_cond
);
7278 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7280 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7285 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7288 po_reg_or_fail (REG_TYPE_NSDQ
);
7292 po_reg_or_goto (REG_TYPE_RN
, try_rmq
);
7296 po_reg_or_fail (REG_TYPE_MQ
);
7298 /* Neon scalar. Using an element size of 8 means that some invalid
7299 scalars are accepted here, so deal with those in later code. */
7300 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7304 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7307 po_imm_or_fail (0, 0, TRUE
);
7312 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7316 po_reg_or_goto (REG_TYPE_MQ
, try_rsvd_fi0
);
7321 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7324 if (parse_ifimm_zero (&str
))
7325 inst
.operands
[i
].imm
= 0;
7329 = _("only floating point zero is allowed as immediate value");
7337 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7340 po_reg_or_fail (REG_TYPE_RN
);
7344 case OP_RNSDQ_RNSC_MQ_RR
:
7345 po_reg_or_goto (REG_TYPE_RN
, try_rnsdq_rnsc_mq
);
7348 case OP_RNSDQ_RNSC_MQ
:
7349 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7354 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7358 po_reg_or_fail (REG_TYPE_NSDQ
);
7365 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7368 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7371 po_reg_or_fail (REG_TYPE_NSD
);
7375 case OP_RNDQMQ_RNSC_RR
:
7376 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc_rr
);
7379 case OP_RNDQ_RNSC_RR
:
7380 po_reg_or_goto (REG_TYPE_RN
, try_rndq_rnsc
);
7382 case OP_RNDQMQ_RNSC
:
7383 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc
);
7388 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7391 po_reg_or_fail (REG_TYPE_NDQ
);
7397 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7400 po_reg_or_fail (REG_TYPE_VFD
);
7405 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7406 not careful then bad things might happen. */
7407 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7410 case OP_RNDQMQ_Ibig
:
7411 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_ibig
);
7416 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7419 /* There's a possibility of getting a 64-bit immediate here, so
7420 we need special handling. */
7421 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7424 inst
.error
= _("immediate value is out of range");
7430 case OP_RNDQMQ_I63b_RR
:
7431 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_i63b_rr
);
7434 po_reg_or_goto (REG_TYPE_RN
, try_rndq_i63b
);
7439 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7442 po_imm_or_fail (0, 63, TRUE
);
7447 po_char_or_fail ('[');
7448 po_reg_or_fail (REG_TYPE_RN
);
7449 po_char_or_fail (']');
7455 po_reg_or_fail (REG_TYPE_RN
);
7456 if (skip_past_char (&str
, '!') == SUCCESS
)
7457 inst
.operands
[i
].writeback
= 1;
7461 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7462 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7463 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7464 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7465 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7466 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7467 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7468 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7469 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7470 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7471 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7472 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7474 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7476 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7477 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7479 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7480 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7481 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7482 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7484 /* Immediate variants */
7486 po_char_or_fail ('{');
7487 po_imm_or_fail (0, 255, TRUE
);
7488 po_char_or_fail ('}');
7492 /* The expression parser chokes on a trailing !, so we have
7493 to find it first and zap it. */
7496 while (*s
&& *s
!= ',')
7501 inst
.operands
[i
].writeback
= 1;
7503 po_imm_or_fail (0, 31, TRUE
);
7511 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7516 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7521 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7523 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7525 val
= parse_reloc (&str
);
7528 inst
.error
= _("unrecognized relocation suffix");
7531 else if (val
!= BFD_RELOC_UNUSED
)
7533 inst
.operands
[i
].imm
= val
;
7534 inst
.operands
[i
].hasreloc
= 1;
7540 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7542 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7544 inst
.operands
[i
].hasreloc
= 1;
7546 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7548 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7549 inst
.operands
[i
].hasreloc
= 0;
7553 /* Operand for MOVW or MOVT. */
7555 po_misc_or_fail (parse_half (&str
));
7558 /* Register or expression. */
7559 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7560 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7562 /* Register or immediate. */
7563 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7564 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7566 case OP_RRnpcsp_I32
: po_reg_or_goto (REG_TYPE_RN
, I32
); break;
7567 I32
: po_imm_or_fail (1, 32, FALSE
); break;
7569 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7571 if (!is_immediate_prefix (*str
))
7574 val
= parse_fpa_immediate (&str
);
7577 /* FPA immediates are encoded as registers 8-15.
7578 parse_fpa_immediate has already applied the offset. */
7579 inst
.operands
[i
].reg
= val
;
7580 inst
.operands
[i
].isreg
= 1;
7583 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7584 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7586 /* Two kinds of register. */
7589 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7591 || (rege
->type
!= REG_TYPE_MMXWR
7592 && rege
->type
!= REG_TYPE_MMXWC
7593 && rege
->type
!= REG_TYPE_MMXWCG
))
7595 inst
.error
= _("iWMMXt data or control register expected");
7598 inst
.operands
[i
].reg
= rege
->number
;
7599 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7605 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7607 || (rege
->type
!= REG_TYPE_MMXWC
7608 && rege
->type
!= REG_TYPE_MMXWCG
))
7610 inst
.error
= _("iWMMXt control register expected");
7613 inst
.operands
[i
].reg
= rege
->number
;
7614 inst
.operands
[i
].isreg
= 1;
7619 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7620 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7621 case OP_oROR
: val
= parse_ror (&str
); break;
7623 case OP_COND
: val
= parse_cond (&str
); break;
7624 case OP_oBARRIER_I15
:
7625 po_barrier_or_imm (str
); break;
7627 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7633 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7634 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7636 inst
.error
= _("Banked registers are not available with this "
7642 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7646 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7649 val
= parse_sys_vldr_vstr (&str
);
7653 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7656 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7658 if (strncasecmp (str
, "APSR_", 5) == 0)
7665 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7666 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7667 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7668 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7669 default: found
= 16;
7673 inst
.operands
[i
].isvec
= 1;
7674 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7675 inst
.operands
[i
].reg
= REG_PC
;
7682 po_misc_or_fail (parse_tb (&str
));
7685 /* Register lists. */
7687 val
= parse_reg_list (&str
, REGLIST_RN
);
7690 inst
.operands
[i
].writeback
= 1;
7696 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7700 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7705 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7710 /* Allow Q registers too. */
7711 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7712 REGLIST_NEON_D
, &partial_match
);
7716 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7717 REGLIST_VFP_S
, &partial_match
);
7718 inst
.operands
[i
].issingle
= 1;
7723 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7724 REGLIST_VFP_D_VPR
, &partial_match
);
7725 if (val
== FAIL
&& !partial_match
)
7728 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7729 REGLIST_VFP_S_VPR
, &partial_match
);
7730 inst
.operands
[i
].issingle
= 1;
7735 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7736 REGLIST_NEON_D
, &partial_match
);
7741 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7742 1, &inst
.operands
[i
].vectype
);
7743 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7747 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7748 0, &inst
.operands
[i
].vectype
);
7751 /* Addressing modes */
7753 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7757 po_misc_or_fail (parse_address (&str
, i
));
7761 po_misc_or_fail_no_backtrack (
7762 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7766 po_misc_or_fail_no_backtrack (
7767 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7771 po_misc_or_fail_no_backtrack (
7772 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7776 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7780 po_misc_or_fail_no_backtrack (
7781 parse_shifter_operand_group_reloc (&str
, i
));
7785 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7789 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7793 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7798 po_reg_or_goto (REG_TYPE_MQ
, try_rr_zr
);
7803 po_reg_or_goto (REG_TYPE_RN
, ZR
);
7806 po_reg_or_fail (REG_TYPE_ZR
);
7810 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7813 /* Various value-based sanity checks and shared operations. We
7814 do not signal immediate failures for the register constraints;
7815 this allows a syntax error to take precedence. */
7816 switch (op_parse_code
)
7824 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7825 inst
.error
= BAD_PC
;
7830 case OP_RRnpcsp_I32
:
7831 if (inst
.operands
[i
].isreg
)
7833 if (inst
.operands
[i
].reg
== REG_PC
)
7834 inst
.error
= BAD_PC
;
7835 else if (inst
.operands
[i
].reg
== REG_SP
7836 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7837 relaxed since ARMv8-A. */
7838 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7841 inst
.error
= BAD_SP
;
7847 if (inst
.operands
[i
].isreg
7848 && inst
.operands
[i
].reg
== REG_PC
7849 && (inst
.operands
[i
].writeback
|| thumb
))
7850 inst
.error
= BAD_PC
;
7855 if (inst
.operands
[i
].isreg
)
7865 case OP_oBARRIER_I15
:
7878 inst
.operands
[i
].imm
= val
;
7883 if (inst
.operands
[i
].reg
!= REG_LR
)
7884 inst
.error
= _("operand must be LR register");
7890 if (!inst
.operands
[i
].iszr
&& inst
.operands
[i
].reg
== REG_PC
)
7891 inst
.error
= BAD_PC
;
7895 if (inst
.operands
[i
].isreg
7896 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
7897 inst
.error
= BAD_ODD
;
7901 if (inst
.operands
[i
].isreg
)
7903 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
7904 inst
.error
= BAD_EVEN
;
7905 else if (inst
.operands
[i
].reg
== REG_SP
)
7906 as_tsktsk (MVE_BAD_SP
);
7907 else if (inst
.operands
[i
].reg
== REG_PC
)
7908 inst
.error
= BAD_PC
;
7916 /* If we get here, this operand was successfully parsed. */
7917 inst
.operands
[i
].present
= 1;
7921 inst
.error
= BAD_ARGS
;
7926 /* The parse routine should already have set inst.error, but set a
7927 default here just in case. */
7929 inst
.error
= BAD_SYNTAX
;
7933 /* Do not backtrack over a trailing optional argument that
7934 absorbed some text. We will only fail again, with the
7935 'garbage following instruction' error message, which is
7936 probably less helpful than the current one. */
7937 if (backtrack_index
== i
&& backtrack_pos
!= str
7938 && upat
[i
+1] == OP_stop
)
7941 inst
.error
= BAD_SYNTAX
;
7945 /* Try again, skipping the optional argument at backtrack_pos. */
7946 str
= backtrack_pos
;
7947 inst
.error
= backtrack_error
;
7948 inst
.operands
[backtrack_index
].present
= 0;
7949 i
= backtrack_index
;
7953 /* Check that we have parsed all the arguments. */
7954 if (*str
!= '\0' && !inst
.error
)
7955 inst
.error
= _("garbage following instruction");
7957 return inst
.error
? FAIL
: SUCCESS
;
7960 #undef po_char_or_fail
7961 #undef po_reg_or_fail
7962 #undef po_reg_or_goto
7963 #undef po_imm_or_fail
7964 #undef po_scalar_or_fail
7965 #undef po_barrier_or_imm
7967 /* Shorthand macro for instruction encoding functions issuing errors. */
7968 #define constraint(expr, err) \
7979 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7980 instructions are unpredictable if these registers are used. This
7981 is the BadReg predicate in ARM's Thumb-2 documentation.
7983 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7984 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7985 #define reject_bad_reg(reg) \
7987 if (reg == REG_PC) \
7989 inst.error = BAD_PC; \
7992 else if (reg == REG_SP \
7993 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7995 inst.error = BAD_SP; \
8000 /* If REG is R13 (the stack pointer), warn that its use is
8002 #define warn_deprecated_sp(reg) \
8004 if (warn_on_deprecated && reg == REG_SP) \
8005 as_tsktsk (_("use of r13 is deprecated")); \
8008 /* Functions for operand encoding. ARM, then Thumb. */
8010 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
8012 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8014 The only binary encoding difference is the Coprocessor number. Coprocessor
8015 9 is used for half-precision calculations or conversions. The format of the
8016 instruction is the same as the equivalent Coprocessor 10 instruction that
8017 exists for Single-Precision operation. */
8020 do_scalar_fp16_v82_encode (void)
8022 if (inst
.cond
< COND_ALWAYS
)
8023 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8024 " the behaviour is UNPREDICTABLE"));
8025 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
8028 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
8029 mark_feature_used (&arm_ext_fp16
);
8032 /* If VAL can be encoded in the immediate field of an ARM instruction,
8033 return the encoded form. Otherwise, return FAIL. */
8036 encode_arm_immediate (unsigned int val
)
8043 for (i
= 2; i
< 32; i
+= 2)
8044 if ((a
= rotate_left (val
, i
)) <= 0xff)
8045 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
8050 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8051 return the encoded form. Otherwise, return FAIL. */
8053 encode_thumb32_immediate (unsigned int val
)
8060 for (i
= 1; i
<= 24; i
++)
8063 if ((val
& ~(0xff << i
)) == 0)
8064 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
8068 if (val
== ((a
<< 16) | a
))
8070 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
8074 if (val
== ((a
<< 16) | a
))
8075 return 0x200 | (a
>> 8);
8079 /* Encode a VFP SP or DP register number into inst.instruction. */
8082 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
8084 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
8087 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
8090 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8093 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8098 first_error (_("D register out of range for selected VFP version"));
8106 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8110 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8114 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8118 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8122 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8126 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8134 /* Encode a <shift> in an ARM-format instruction. The immediate,
8135 if any, is handled by md_apply_fix. */
8137 encode_arm_shift (int i
)
8139 /* register-shifted register. */
8140 if (inst
.operands
[i
].immisreg
)
8143 for (op_index
= 0; op_index
<= i
; ++op_index
)
8145 /* Check the operand only when it's presented. In pre-UAL syntax,
8146 if the destination register is the same as the first operand, two
8147 register form of the instruction can be used. */
8148 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8149 && inst
.operands
[op_index
].reg
== REG_PC
)
8150 as_warn (UNPRED_REG ("r15"));
8153 if (inst
.operands
[i
].imm
== REG_PC
)
8154 as_warn (UNPRED_REG ("r15"));
8157 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8158 inst
.instruction
|= SHIFT_ROR
<< 5;
8161 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8162 if (inst
.operands
[i
].immisreg
)
8164 inst
.instruction
|= SHIFT_BY_REG
;
8165 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8168 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8173 encode_arm_shifter_operand (int i
)
8175 if (inst
.operands
[i
].isreg
)
8177 inst
.instruction
|= inst
.operands
[i
].reg
;
8178 encode_arm_shift (i
);
8182 inst
.instruction
|= INST_IMMEDIATE
;
8183 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8184 inst
.instruction
|= inst
.operands
[i
].imm
;
8188 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8190 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
8193 Generate an error if the operand is not a register. */
8194 constraint (!inst
.operands
[i
].isreg
,
8195 _("Instruction does not support =N addresses"));
8197 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8199 if (inst
.operands
[i
].preind
)
8203 inst
.error
= _("instruction does not accept preindexed addressing");
8206 inst
.instruction
|= PRE_INDEX
;
8207 if (inst
.operands
[i
].writeback
)
8208 inst
.instruction
|= WRITE_BACK
;
8211 else if (inst
.operands
[i
].postind
)
8213 gas_assert (inst
.operands
[i
].writeback
);
8215 inst
.instruction
|= WRITE_BACK
;
8217 else /* unindexed - only for coprocessor */
8219 inst
.error
= _("instruction does not accept unindexed addressing");
8223 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8224 && (((inst
.instruction
& 0x000f0000) >> 16)
8225 == ((inst
.instruction
& 0x0000f000) >> 12)))
8226 as_warn ((inst
.instruction
& LOAD_BIT
)
8227 ? _("destination register same as write-back base")
8228 : _("source register same as write-back base"));
8231 /* inst.operands[i] was set up by parse_address. Encode it into an
8232 ARM-format mode 2 load or store instruction. If is_t is true,
8233 reject forms that cannot be used with a T instruction (i.e. not
8236 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
8238 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8240 encode_arm_addr_mode_common (i
, is_t
);
8242 if (inst
.operands
[i
].immisreg
)
8244 constraint ((inst
.operands
[i
].imm
== REG_PC
8245 || (is_pc
&& inst
.operands
[i
].writeback
)),
8247 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8248 inst
.instruction
|= inst
.operands
[i
].imm
;
8249 if (!inst
.operands
[i
].negative
)
8250 inst
.instruction
|= INDEX_UP
;
8251 if (inst
.operands
[i
].shifted
)
8253 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8254 inst
.instruction
|= SHIFT_ROR
<< 5;
8257 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8258 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8262 else /* immediate offset in inst.relocs[0] */
8264 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8266 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8268 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8269 cannot use PC in addressing.
8270 PC cannot be used in writeback addressing, either. */
8271 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8274 /* Use of PC in str is deprecated for ARMv7. */
8275 if (warn_on_deprecated
8277 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8278 as_tsktsk (_("use of PC in this instruction is deprecated"));
8281 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8283 /* Prefer + for zero encoded value. */
8284 if (!inst
.operands
[i
].negative
)
8285 inst
.instruction
|= INDEX_UP
;
8286 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8291 /* inst.operands[i] was set up by parse_address. Encode it into an
8292 ARM-format mode 3 load or store instruction. Reject forms that
8293 cannot be used with such instructions. If is_t is true, reject
8294 forms that cannot be used with a T instruction (i.e. not
8297 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
8299 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8301 inst
.error
= _("instruction does not accept scaled register index");
8305 encode_arm_addr_mode_common (i
, is_t
);
8307 if (inst
.operands
[i
].immisreg
)
8309 constraint ((inst
.operands
[i
].imm
== REG_PC
8310 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8312 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8314 inst
.instruction
|= inst
.operands
[i
].imm
;
8315 if (!inst
.operands
[i
].negative
)
8316 inst
.instruction
|= INDEX_UP
;
8318 else /* immediate offset in inst.relocs[0] */
8320 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8321 && inst
.operands
[i
].writeback
),
8323 inst
.instruction
|= HWOFFSET_IMM
;
8324 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8326 /* Prefer + for zero encoded value. */
8327 if (!inst
.operands
[i
].negative
)
8328 inst
.instruction
|= INDEX_UP
;
8330 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8335 /* Write immediate bits [7:0] to the following locations:
8337 |28/24|23 19|18 16|15 4|3 0|
8338 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8340 This function is used by VMOV/VMVN/VORR/VBIC. */
8343 neon_write_immbits (unsigned immbits
)
8345 inst
.instruction
|= immbits
& 0xf;
8346 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8347 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8350 /* Invert low-order SIZE bits of XHI:XLO. */
8353 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8355 unsigned immlo
= xlo
? *xlo
: 0;
8356 unsigned immhi
= xhi
? *xhi
: 0;
8361 immlo
= (~immlo
) & 0xff;
8365 immlo
= (~immlo
) & 0xffff;
8369 immhi
= (~immhi
) & 0xffffffff;
8373 immlo
= (~immlo
) & 0xffffffff;
8387 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8391 neon_bits_same_in_bytes (unsigned imm
)
8393 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8394 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8395 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8396 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8399 /* For immediate of above form, return 0bABCD. */
8402 neon_squash_bits (unsigned imm
)
8404 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8405 | ((imm
& 0x01000000) >> 21);
8408 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8411 neon_qfloat_bits (unsigned imm
)
8413 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8416 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8417 the instruction. *OP is passed as the initial value of the op field, and
8418 may be set to a different value depending on the constant (i.e.
8419 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8420 MVN). If the immediate looks like a repeated pattern then also
8421 try smaller element sizes. */
8424 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8425 unsigned *immbits
, int *op
, int size
,
8426 enum neon_el_type type
)
8428 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8430 if (type
== NT_float
&& !float_p
)
8433 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8435 if (size
!= 32 || *op
== 1)
8437 *immbits
= neon_qfloat_bits (immlo
);
8443 if (neon_bits_same_in_bytes (immhi
)
8444 && neon_bits_same_in_bytes (immlo
))
8448 *immbits
= (neon_squash_bits (immhi
) << 4)
8449 | neon_squash_bits (immlo
);
8460 if (immlo
== (immlo
& 0x000000ff))
8465 else if (immlo
== (immlo
& 0x0000ff00))
8467 *immbits
= immlo
>> 8;
8470 else if (immlo
== (immlo
& 0x00ff0000))
8472 *immbits
= immlo
>> 16;
8475 else if (immlo
== (immlo
& 0xff000000))
8477 *immbits
= immlo
>> 24;
8480 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8482 *immbits
= (immlo
>> 8) & 0xff;
8485 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8487 *immbits
= (immlo
>> 16) & 0xff;
8491 if ((immlo
& 0xffff) != (immlo
>> 16))
8498 if (immlo
== (immlo
& 0x000000ff))
8503 else if (immlo
== (immlo
& 0x0000ff00))
8505 *immbits
= immlo
>> 8;
8509 if ((immlo
& 0xff) != (immlo
>> 8))
8514 if (immlo
== (immlo
& 0x000000ff))
8516 /* Don't allow MVN with 8-bit immediate. */
8526 #if defined BFD_HOST_64_BIT
8527 /* Returns TRUE if double precision value V may be cast
8528 to single precision without loss of accuracy. */
8531 is_double_a_single (bfd_int64_t v
)
8533 int exp
= (int)((v
>> 52) & 0x7FF);
8534 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8536 return (exp
== 0 || exp
== 0x7FF
8537 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8538 && (mantissa
& 0x1FFFFFFFl
) == 0;
8541 /* Returns a double precision value casted to single precision
8542 (ignoring the least significant bits in exponent and mantissa). */
8545 double_to_single (bfd_int64_t v
)
8547 int sign
= (int) ((v
>> 63) & 1l);
8548 int exp
= (int) ((v
>> 52) & 0x7FF);
8549 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8555 exp
= exp
- 1023 + 127;
8564 /* No denormalized numbers. */
8570 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8572 #endif /* BFD_HOST_64_BIT */
8581 static void do_vfp_nsyn_opcode (const char *);
8583 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8584 Determine whether it can be performed with a move instruction; if
8585 it can, convert inst.instruction to that move instruction and
8586 return TRUE; if it can't, convert inst.instruction to a literal-pool
8587 load and return FALSE. If this is not a valid thing to do in the
8588 current context, set inst.error and return TRUE.
8590 inst.operands[i] describes the destination register. */
8593 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8596 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8597 bfd_boolean arm_p
= (t
== CONST_ARM
);
8600 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8604 if ((inst
.instruction
& tbit
) == 0)
8606 inst
.error
= _("invalid pseudo operation");
8610 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8611 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8612 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8614 inst
.error
= _("constant expression expected");
8618 if (inst
.relocs
[0].exp
.X_op
== O_constant
8619 || inst
.relocs
[0].exp
.X_op
== O_big
)
8621 #if defined BFD_HOST_64_BIT
8626 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8628 LITTLENUM_TYPE w
[X_PRECISION
];
8631 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8633 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8635 /* FIXME: Should we check words w[2..5] ? */
8640 #if defined BFD_HOST_64_BIT
8642 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8643 << LITTLENUM_NUMBER_OF_BITS
)
8644 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8645 << LITTLENUM_NUMBER_OF_BITS
)
8646 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8647 << LITTLENUM_NUMBER_OF_BITS
)
8648 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8650 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8651 | (l
[0] & LITTLENUM_MASK
);
8655 v
= inst
.relocs
[0].exp
.X_add_number
;
8657 if (!inst
.operands
[i
].issingle
)
8661 /* LDR should not use lead in a flag-setting instruction being
8662 chosen so we do not check whether movs can be used. */
8664 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8665 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8666 && inst
.operands
[i
].reg
!= 13
8667 && inst
.operands
[i
].reg
!= 15)
8669 /* Check if on thumb2 it can be done with a mov.w, mvn or
8670 movw instruction. */
8671 unsigned int newimm
;
8672 bfd_boolean isNegated
;
8674 newimm
= encode_thumb32_immediate (v
);
8675 if (newimm
!= (unsigned int) FAIL
)
8679 newimm
= encode_thumb32_immediate (~v
);
8680 if (newimm
!= (unsigned int) FAIL
)
8684 /* The number can be loaded with a mov.w or mvn
8686 if (newimm
!= (unsigned int) FAIL
8687 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8689 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8690 | (inst
.operands
[i
].reg
<< 8));
8691 /* Change to MOVN. */
8692 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8693 inst
.instruction
|= (newimm
& 0x800) << 15;
8694 inst
.instruction
|= (newimm
& 0x700) << 4;
8695 inst
.instruction
|= (newimm
& 0x0ff);
8698 /* The number can be loaded with a movw instruction. */
8699 else if ((v
& ~0xFFFF) == 0
8700 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8702 int imm
= v
& 0xFFFF;
8704 inst
.instruction
= 0xf2400000; /* MOVW. */
8705 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8706 inst
.instruction
|= (imm
& 0xf000) << 4;
8707 inst
.instruction
|= (imm
& 0x0800) << 15;
8708 inst
.instruction
|= (imm
& 0x0700) << 4;
8709 inst
.instruction
|= (imm
& 0x00ff);
8710 /* In case this replacement is being done on Armv8-M
8711 Baseline we need to make sure to disable the
8712 instruction size check, as otherwise GAS will reject
8713 the use of this T32 instruction. */
8721 int value
= encode_arm_immediate (v
);
8725 /* This can be done with a mov instruction. */
8726 inst
.instruction
&= LITERAL_MASK
;
8727 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8728 inst
.instruction
|= value
& 0xfff;
8732 value
= encode_arm_immediate (~ v
);
8735 /* This can be done with a mvn instruction. */
8736 inst
.instruction
&= LITERAL_MASK
;
8737 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8738 inst
.instruction
|= value
& 0xfff;
8742 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8745 unsigned immbits
= 0;
8746 unsigned immlo
= inst
.operands
[1].imm
;
8747 unsigned immhi
= inst
.operands
[1].regisimm
8748 ? inst
.operands
[1].reg
8749 : inst
.relocs
[0].exp
.X_unsigned
8751 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8752 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8753 &op
, 64, NT_invtype
);
8757 neon_invert_size (&immlo
, &immhi
, 64);
8759 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8760 &op
, 64, NT_invtype
);
8765 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8771 /* Fill other bits in vmov encoding for both thumb and arm. */
8773 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8775 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8776 neon_write_immbits (immbits
);
8784 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8785 if (inst
.operands
[i
].issingle
8786 && is_quarter_float (inst
.operands
[1].imm
)
8787 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8789 inst
.operands
[1].imm
=
8790 neon_qfloat_bits (v
);
8791 do_vfp_nsyn_opcode ("fconsts");
8795 /* If our host does not support a 64-bit type then we cannot perform
8796 the following optimization. This mean that there will be a
8797 discrepancy between the output produced by an assembler built for
8798 a 32-bit-only host and the output produced from a 64-bit host, but
8799 this cannot be helped. */
8800 #if defined BFD_HOST_64_BIT
8801 else if (!inst
.operands
[1].issingle
8802 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8804 if (is_double_a_single (v
)
8805 && is_quarter_float (double_to_single (v
)))
8807 inst
.operands
[1].imm
=
8808 neon_qfloat_bits (double_to_single (v
));
8809 do_vfp_nsyn_opcode ("fconstd");
8817 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8818 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8821 inst
.operands
[1].reg
= REG_PC
;
8822 inst
.operands
[1].isreg
= 1;
8823 inst
.operands
[1].preind
= 1;
8824 inst
.relocs
[0].pc_rel
= 1;
8825 inst
.relocs
[0].type
= (thumb_p
8826 ? BFD_RELOC_ARM_THUMB_OFFSET
8828 ? BFD_RELOC_ARM_HWLITERAL
8829 : BFD_RELOC_ARM_LITERAL
));
8833 /* inst.operands[i] was set up by parse_address. Encode it into an
8834 ARM-format instruction. Reject all forms which cannot be encoded
8835 into a coprocessor load/store instruction. If wb_ok is false,
8836 reject use of writeback; if unind_ok is false, reject use of
8837 unindexed addressing. If reloc_override is not 0, use it instead
8838 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8839 (in which case it is preserved). */
8842 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8844 if (!inst
.operands
[i
].isreg
)
8847 if (! inst
.operands
[0].isvec
)
8849 inst
.error
= _("invalid co-processor operand");
8852 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8856 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8858 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8860 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8862 gas_assert (!inst
.operands
[i
].writeback
);
8865 inst
.error
= _("instruction does not support unindexed addressing");
8868 inst
.instruction
|= inst
.operands
[i
].imm
;
8869 inst
.instruction
|= INDEX_UP
;
8873 if (inst
.operands
[i
].preind
)
8874 inst
.instruction
|= PRE_INDEX
;
8876 if (inst
.operands
[i
].writeback
)
8878 if (inst
.operands
[i
].reg
== REG_PC
)
8880 inst
.error
= _("pc may not be used with write-back");
8885 inst
.error
= _("instruction does not support writeback");
8888 inst
.instruction
|= WRITE_BACK
;
8892 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
8893 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8894 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
8895 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8898 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8900 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8903 /* Prefer + for zero encoded value. */
8904 if (!inst
.operands
[i
].negative
)
8905 inst
.instruction
|= INDEX_UP
;
8910 /* Functions for instruction encoding, sorted by sub-architecture.
8911 First some generics; their names are taken from the conventional
8912 bit positions for register arguments in ARM format instructions. */
8922 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8928 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8934 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8935 inst
.instruction
|= inst
.operands
[1].reg
;
8941 inst
.instruction
|= inst
.operands
[0].reg
;
8942 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8948 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8949 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8955 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8956 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8962 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8963 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8967 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8969 if (ARM_CPU_IS_ANY (cpu_variant
))
8971 as_tsktsk ("%s", msg
);
8974 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8986 unsigned Rn
= inst
.operands
[2].reg
;
8987 /* Enforce restrictions on SWP instruction. */
8988 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8990 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8991 _("Rn must not overlap other operands"));
8993 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8995 if (!check_obsolete (&arm_ext_v8
,
8996 _("swp{b} use is obsoleted for ARMv8 and later"))
8997 && warn_on_deprecated
8998 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8999 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
9002 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9003 inst
.instruction
|= inst
.operands
[1].reg
;
9004 inst
.instruction
|= Rn
<< 16;
9010 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9011 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9012 inst
.instruction
|= inst
.operands
[2].reg
;
9018 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
9019 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
9020 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
9021 || inst
.relocs
[0].exp
.X_add_number
!= 0),
9023 inst
.instruction
|= inst
.operands
[0].reg
;
9024 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9025 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9031 inst
.instruction
|= inst
.operands
[0].imm
;
9037 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9038 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9041 /* ARM instructions, in alphabetical order by function name (except
9042 that wrapper functions appear immediately after the function they
9045 /* This is a pseudo-op of the form "adr rd, label" to be converted
9046 into a relative address of the form "add rd, pc, #label-.-8". */
9051 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9053 /* Frag hacking will turn this into a sub instruction if the offset turns
9054 out to be negative. */
9055 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9056 inst
.relocs
[0].pc_rel
= 1;
9057 inst
.relocs
[0].exp
.X_add_number
-= 8;
9059 if (support_interwork
9060 && inst
.relocs
[0].exp
.X_op
== O_symbol
9061 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9062 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9063 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9064 inst
.relocs
[0].exp
.X_add_number
|= 1;
9067 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9068 into a relative address of the form:
9069 add rd, pc, #low(label-.-8)"
9070 add rd, rd, #high(label-.-8)" */
9075 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9077 /* Frag hacking will turn this into a sub instruction if the offset turns
9078 out to be negative. */
9079 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
9080 inst
.relocs
[0].pc_rel
= 1;
9081 inst
.size
= INSN_SIZE
* 2;
9082 inst
.relocs
[0].exp
.X_add_number
-= 8;
9084 if (support_interwork
9085 && inst
.relocs
[0].exp
.X_op
== O_symbol
9086 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9087 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9088 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9089 inst
.relocs
[0].exp
.X_add_number
|= 1;
9095 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9096 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9098 if (!inst
.operands
[1].present
)
9099 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9100 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9101 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9102 encode_arm_shifter_operand (2);
9108 if (inst
.operands
[0].present
)
9109 inst
.instruction
|= inst
.operands
[0].imm
;
9111 inst
.instruction
|= 0xf;
9117 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9118 constraint (msb
> 32, _("bit-field extends past end of register"));
9119 /* The instruction encoding stores the LSB and MSB,
9120 not the LSB and width. */
9121 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9122 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9123 inst
.instruction
|= (msb
- 1) << 16;
9131 /* #0 in second position is alternative syntax for bfc, which is
9132 the same instruction but with REG_PC in the Rm field. */
9133 if (!inst
.operands
[1].isreg
)
9134 inst
.operands
[1].reg
= REG_PC
;
9136 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9137 constraint (msb
> 32, _("bit-field extends past end of register"));
9138 /* The instruction encoding stores the LSB and MSB,
9139 not the LSB and width. */
9140 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9141 inst
.instruction
|= inst
.operands
[1].reg
;
9142 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9143 inst
.instruction
|= (msb
- 1) << 16;
9149 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9150 _("bit-field extends past end of register"));
9151 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9152 inst
.instruction
|= inst
.operands
[1].reg
;
9153 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9154 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9157 /* ARM V5 breakpoint instruction (argument parse)
9158 BKPT <16 bit unsigned immediate>
9159 Instruction is not conditional.
9160 The bit pattern given in insns[] has the COND_ALWAYS condition,
9161 and it is an error if the caller tried to override that. */
9166 /* Top 12 of 16 bits to bits 19:8. */
9167 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9169 /* Bottom 4 of 16 bits to bits 3:0. */
9170 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9174 encode_branch (int default_reloc
)
9176 if (inst
.operands
[0].hasreloc
)
9178 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9179 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9180 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9181 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9182 ? BFD_RELOC_ARM_PLT32
9183 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9186 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9187 inst
.relocs
[0].pc_rel
= 1;
9194 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9195 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9198 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9205 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9207 if (inst
.cond
== COND_ALWAYS
)
9208 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9210 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9214 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9217 /* ARM V5 branch-link-exchange instruction (argument parse)
9218 BLX <target_addr> ie BLX(1)
9219 BLX{<condition>} <Rm> ie BLX(2)
9220 Unfortunately, there are two different opcodes for this mnemonic.
9221 So, the insns[].value is not used, and the code here zaps values
9222 into inst.instruction.
9223 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9228 if (inst
.operands
[0].isreg
)
9230 /* Arg is a register; the opcode provided by insns[] is correct.
9231 It is not illegal to do "blx pc", just useless. */
9232 if (inst
.operands
[0].reg
== REG_PC
)
9233 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9235 inst
.instruction
|= inst
.operands
[0].reg
;
9239 /* Arg is an address; this instruction cannot be executed
9240 conditionally, and the opcode must be adjusted.
9241 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9242 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9243 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9244 inst
.instruction
= 0xfa000000;
9245 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9252 bfd_boolean want_reloc
;
9254 if (inst
.operands
[0].reg
== REG_PC
)
9255 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9257 inst
.instruction
|= inst
.operands
[0].reg
;
9258 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9259 it is for ARMv4t or earlier. */
9260 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9261 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9262 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9266 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9271 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9275 /* ARM v5TEJ. Jump to Jazelle code. */
9280 if (inst
.operands
[0].reg
== REG_PC
)
9281 as_tsktsk (_("use of r15 in bxj is not really useful"));
9283 inst
.instruction
|= inst
.operands
[0].reg
;
9286 /* Co-processor data operation:
9287 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9288 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9292 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9293 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9294 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9295 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9296 inst
.instruction
|= inst
.operands
[4].reg
;
9297 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9303 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9304 encode_arm_shifter_operand (1);
9307 /* Transfer between coprocessor and ARM registers.
9308 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9313 No special properties. */
9315 struct deprecated_coproc_regs_s
9322 arm_feature_set deprecated
;
9323 arm_feature_set obsoleted
;
9324 const char *dep_msg
;
9325 const char *obs_msg
;
9328 #define DEPR_ACCESS_V8 \
9329 N_("This coprocessor register access is deprecated in ARMv8")
9331 /* Table of all deprecated coprocessor registers. */
9332 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9334 {15, 0, 7, 10, 5, /* CP15DMB. */
9335 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9336 DEPR_ACCESS_V8
, NULL
},
9337 {15, 0, 7, 10, 4, /* CP15DSB. */
9338 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9339 DEPR_ACCESS_V8
, NULL
},
9340 {15, 0, 7, 5, 4, /* CP15ISB. */
9341 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9342 DEPR_ACCESS_V8
, NULL
},
9343 {14, 6, 1, 0, 0, /* TEEHBR. */
9344 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9345 DEPR_ACCESS_V8
, NULL
},
9346 {14, 6, 0, 0, 0, /* TEECR. */
9347 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9348 DEPR_ACCESS_V8
, NULL
},
9351 #undef DEPR_ACCESS_V8
9353 static const size_t deprecated_coproc_reg_count
=
9354 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9362 Rd
= inst
.operands
[2].reg
;
9365 if (inst
.instruction
== 0xee000010
9366 || inst
.instruction
== 0xfe000010)
9368 reject_bad_reg (Rd
);
9369 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9371 constraint (Rd
== REG_SP
, BAD_SP
);
9376 if (inst
.instruction
== 0xe000010)
9377 constraint (Rd
== REG_PC
, BAD_PC
);
9380 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9382 const struct deprecated_coproc_regs_s
*r
=
9383 deprecated_coproc_regs
+ i
;
9385 if (inst
.operands
[0].reg
== r
->cp
9386 && inst
.operands
[1].imm
== r
->opc1
9387 && inst
.operands
[3].reg
== r
->crn
9388 && inst
.operands
[4].reg
== r
->crm
9389 && inst
.operands
[5].imm
== r
->opc2
)
9391 if (! ARM_CPU_IS_ANY (cpu_variant
)
9392 && warn_on_deprecated
9393 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9394 as_tsktsk ("%s", r
->dep_msg
);
9398 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9399 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9400 inst
.instruction
|= Rd
<< 12;
9401 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9402 inst
.instruction
|= inst
.operands
[4].reg
;
9403 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9406 /* Transfer between coprocessor register and pair of ARM registers.
9407 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9412 Two XScale instructions are special cases of these:
9414 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9415 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9417 Result unpredictable if Rd or Rn is R15. */
9424 Rd
= inst
.operands
[2].reg
;
9425 Rn
= inst
.operands
[3].reg
;
9429 reject_bad_reg (Rd
);
9430 reject_bad_reg (Rn
);
9434 constraint (Rd
== REG_PC
, BAD_PC
);
9435 constraint (Rn
== REG_PC
, BAD_PC
);
9438 /* Only check the MRRC{2} variants. */
9439 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9441 /* If Rd == Rn, error that the operation is
9442 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9443 constraint (Rd
== Rn
, BAD_OVERLAP
);
9446 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9447 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9448 inst
.instruction
|= Rd
<< 12;
9449 inst
.instruction
|= Rn
<< 16;
9450 inst
.instruction
|= inst
.operands
[4].reg
;
9456 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9457 if (inst
.operands
[1].present
)
9459 inst
.instruction
|= CPSI_MMOD
;
9460 inst
.instruction
|= inst
.operands
[1].imm
;
9467 inst
.instruction
|= inst
.operands
[0].imm
;
9473 unsigned Rd
, Rn
, Rm
;
9475 Rd
= inst
.operands
[0].reg
;
9476 Rn
= (inst
.operands
[1].present
9477 ? inst
.operands
[1].reg
: Rd
);
9478 Rm
= inst
.operands
[2].reg
;
9480 constraint ((Rd
== REG_PC
), BAD_PC
);
9481 constraint ((Rn
== REG_PC
), BAD_PC
);
9482 constraint ((Rm
== REG_PC
), BAD_PC
);
9484 inst
.instruction
|= Rd
<< 16;
9485 inst
.instruction
|= Rn
<< 0;
9486 inst
.instruction
|= Rm
<< 8;
9492 /* There is no IT instruction in ARM mode. We
9493 process it to do the validation as if in
9494 thumb mode, just in case the code gets
9495 assembled for thumb using the unified syntax. */
9500 set_pred_insn_type (IT_INSN
);
9501 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9502 now_pred
.cc
= inst
.operands
[0].imm
;
9506 /* If there is only one register in the register list,
9507 then return its register number. Otherwise return -1. */
9509 only_one_reg_in_list (int range
)
9511 int i
= ffs (range
) - 1;
9512 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9516 encode_ldmstm(int from_push_pop_mnem
)
9518 int base_reg
= inst
.operands
[0].reg
;
9519 int range
= inst
.operands
[1].imm
;
9522 inst
.instruction
|= base_reg
<< 16;
9523 inst
.instruction
|= range
;
9525 if (inst
.operands
[1].writeback
)
9526 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9528 if (inst
.operands
[0].writeback
)
9530 inst
.instruction
|= WRITE_BACK
;
9531 /* Check for unpredictable uses of writeback. */
9532 if (inst
.instruction
& LOAD_BIT
)
9534 /* Not allowed in LDM type 2. */
9535 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9536 && ((range
& (1 << REG_PC
)) == 0))
9537 as_warn (_("writeback of base register is UNPREDICTABLE"));
9538 /* Only allowed if base reg not in list for other types. */
9539 else if (range
& (1 << base_reg
))
9540 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9544 /* Not allowed for type 2. */
9545 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9546 as_warn (_("writeback of base register is UNPREDICTABLE"));
9547 /* Only allowed if base reg not in list, or first in list. */
9548 else if ((range
& (1 << base_reg
))
9549 && (range
& ((1 << base_reg
) - 1)))
9550 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9554 /* If PUSH/POP has only one register, then use the A2 encoding. */
9555 one_reg
= only_one_reg_in_list (range
);
9556 if (from_push_pop_mnem
&& one_reg
>= 0)
9558 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9560 if (is_push
&& one_reg
== 13 /* SP */)
9561 /* PR 22483: The A2 encoding cannot be used when
9562 pushing the stack pointer as this is UNPREDICTABLE. */
9565 inst
.instruction
&= A_COND_MASK
;
9566 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9567 inst
.instruction
|= one_reg
<< 12;
9574 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9577 /* ARMv5TE load-consecutive (argument parse)
9586 constraint (inst
.operands
[0].reg
% 2 != 0,
9587 _("first transfer register must be even"));
9588 constraint (inst
.operands
[1].present
9589 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9590 _("can only transfer two consecutive registers"));
9591 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9592 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9594 if (!inst
.operands
[1].present
)
9595 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9597 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9598 register and the first register written; we have to diagnose
9599 overlap between the base and the second register written here. */
9601 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9602 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9603 as_warn (_("base register written back, and overlaps "
9604 "second transfer register"));
9606 if (!(inst
.instruction
& V4_STR_BIT
))
9608 /* For an index-register load, the index register must not overlap the
9609 destination (even if not write-back). */
9610 if (inst
.operands
[2].immisreg
9611 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9612 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9613 as_warn (_("index register overlaps transfer register"));
9615 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9616 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9622 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9623 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9624 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9625 || inst
.operands
[1].negative
9626 /* This can arise if the programmer has written
9628 or if they have mistakenly used a register name as the last
9631 It is very difficult to distinguish between these two cases
9632 because "rX" might actually be a label. ie the register
9633 name has been occluded by a symbol of the same name. So we
9634 just generate a general 'bad addressing mode' type error
9635 message and leave it up to the programmer to discover the
9636 true cause and fix their mistake. */
9637 || (inst
.operands
[1].reg
== REG_PC
),
9640 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9641 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9642 _("offset must be zero in ARM encoding"));
9644 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9646 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9647 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9648 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9654 constraint (inst
.operands
[0].reg
% 2 != 0,
9655 _("even register required"));
9656 constraint (inst
.operands
[1].present
9657 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9658 _("can only load two consecutive registers"));
9659 /* If op 1 were present and equal to PC, this function wouldn't
9660 have been called in the first place. */
9661 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9663 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9664 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9667 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9668 which is not a multiple of four is UNPREDICTABLE. */
9670 check_ldr_r15_aligned (void)
9672 constraint (!(inst
.operands
[1].immisreg
)
9673 && (inst
.operands
[0].reg
== REG_PC
9674 && inst
.operands
[1].reg
== REG_PC
9675 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9676 _("ldr to register 15 must be 4-byte aligned"));
9682 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9683 if (!inst
.operands
[1].isreg
)
9684 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9686 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9687 check_ldr_r15_aligned ();
9693 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9695 if (inst
.operands
[1].preind
)
9697 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9698 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9699 _("this instruction requires a post-indexed address"));
9701 inst
.operands
[1].preind
= 0;
9702 inst
.operands
[1].postind
= 1;
9703 inst
.operands
[1].writeback
= 1;
9705 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9706 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9709 /* Halfword and signed-byte load/store operations. */
9714 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9715 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9716 if (!inst
.operands
[1].isreg
)
9717 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9719 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9725 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9727 if (inst
.operands
[1].preind
)
9729 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9730 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9731 _("this instruction requires a post-indexed address"));
9733 inst
.operands
[1].preind
= 0;
9734 inst
.operands
[1].postind
= 1;
9735 inst
.operands
[1].writeback
= 1;
9737 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9738 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9741 /* Co-processor register load/store.
9742 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9746 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9747 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9748 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9754 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9755 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9756 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9757 && !(inst
.instruction
& 0x00400000))
9758 as_tsktsk (_("Rd and Rm should be different in mla"));
9760 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9761 inst
.instruction
|= inst
.operands
[1].reg
;
9762 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9763 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9769 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9770 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9772 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9773 encode_arm_shifter_operand (1);
9776 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9783 top
= (inst
.instruction
& 0x00400000) != 0;
9784 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
9785 _(":lower16: not allowed in this instruction"));
9786 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
9787 _(":upper16: not allowed in this instruction"));
9788 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9789 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
9791 imm
= inst
.relocs
[0].exp
.X_add_number
;
9792 /* The value is in two pieces: 0:11, 16:19. */
9793 inst
.instruction
|= (imm
& 0x00000fff);
9794 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9799 do_vfp_nsyn_mrs (void)
9801 if (inst
.operands
[0].isvec
)
9803 if (inst
.operands
[1].reg
!= 1)
9804 first_error (_("operand 1 must be FPSCR"));
9805 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9806 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9807 do_vfp_nsyn_opcode ("fmstat");
9809 else if (inst
.operands
[1].isvec
)
9810 do_vfp_nsyn_opcode ("fmrx");
9818 do_vfp_nsyn_msr (void)
9820 if (inst
.operands
[0].isvec
)
9821 do_vfp_nsyn_opcode ("fmxr");
9831 unsigned Rt
= inst
.operands
[0].reg
;
9833 if (thumb_mode
&& Rt
== REG_SP
)
9835 inst
.error
= BAD_SP
;
9839 /* MVFR2 is only valid at ARMv8-A. */
9840 if (inst
.operands
[1].reg
== 5)
9841 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9844 /* APSR_ sets isvec. All other refs to PC are illegal. */
9845 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9847 inst
.error
= BAD_PC
;
9851 /* If we get through parsing the register name, we just insert the number
9852 generated into the instruction without further validation. */
9853 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9854 inst
.instruction
|= (Rt
<< 12);
9860 unsigned Rt
= inst
.operands
[1].reg
;
9863 reject_bad_reg (Rt
);
9864 else if (Rt
== REG_PC
)
9866 inst
.error
= BAD_PC
;
9870 /* MVFR2 is only valid for ARMv8-A. */
9871 if (inst
.operands
[0].reg
== 5)
9872 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9875 /* If we get through parsing the register name, we just insert the number
9876 generated into the instruction without further validation. */
9877 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9878 inst
.instruction
|= (Rt
<< 12);
9886 if (do_vfp_nsyn_mrs () == SUCCESS
)
9889 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9890 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9892 if (inst
.operands
[1].isreg
)
9894 br
= inst
.operands
[1].reg
;
9895 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
9896 as_bad (_("bad register for mrs"));
9900 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9901 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9903 _("'APSR', 'CPSR' or 'SPSR' expected"));
9904 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9907 inst
.instruction
|= br
;
9910 /* Two possible forms:
9911 "{C|S}PSR_<field>, Rm",
9912 "{C|S}PSR_f, #expression". */
9917 if (do_vfp_nsyn_msr () == SUCCESS
)
9920 inst
.instruction
|= inst
.operands
[0].imm
;
9921 if (inst
.operands
[1].isreg
)
9922 inst
.instruction
|= inst
.operands
[1].reg
;
9925 inst
.instruction
|= INST_IMMEDIATE
;
9926 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9927 inst
.relocs
[0].pc_rel
= 0;
9934 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9936 if (!inst
.operands
[2].present
)
9937 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9938 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9939 inst
.instruction
|= inst
.operands
[1].reg
;
9940 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9942 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9943 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9944 as_tsktsk (_("Rd and Rm should be different in mul"));
9947 /* Long Multiply Parser
9948 UMULL RdLo, RdHi, Rm, Rs
9949 SMULL RdLo, RdHi, Rm, Rs
9950 UMLAL RdLo, RdHi, Rm, Rs
9951 SMLAL RdLo, RdHi, Rm, Rs. */
9956 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9957 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9958 inst
.instruction
|= inst
.operands
[2].reg
;
9959 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9961 /* rdhi and rdlo must be different. */
9962 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9963 as_tsktsk (_("rdhi and rdlo must be different"));
9965 /* rdhi, rdlo and rm must all be different before armv6. */
9966 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9967 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9968 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9969 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9975 if (inst
.operands
[0].present
9976 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9978 /* Architectural NOP hints are CPSR sets with no bits selected. */
9979 inst
.instruction
&= 0xf0000000;
9980 inst
.instruction
|= 0x0320f000;
9981 if (inst
.operands
[0].present
)
9982 inst
.instruction
|= inst
.operands
[0].imm
;
9986 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9987 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9988 Condition defaults to COND_ALWAYS.
9989 Error if Rd, Rn or Rm are R15. */
9994 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9995 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9996 inst
.instruction
|= inst
.operands
[2].reg
;
9997 if (inst
.operands
[3].present
)
9998 encode_arm_shift (3);
10001 /* ARM V6 PKHTB (Argument Parse). */
10006 if (!inst
.operands
[3].present
)
10008 /* If the shift specifier is omitted, turn the instruction
10009 into pkhbt rd, rm, rn. */
10010 inst
.instruction
&= 0xfff00010;
10011 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10012 inst
.instruction
|= inst
.operands
[1].reg
;
10013 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10017 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10018 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10019 inst
.instruction
|= inst
.operands
[2].reg
;
10020 encode_arm_shift (3);
10024 /* ARMv5TE: Preload-Cache
10025 MP Extensions: Preload for write
10029 Syntactically, like LDR with B=1, W=0, L=1. */
10034 constraint (!inst
.operands
[0].isreg
,
10035 _("'[' expected after PLD mnemonic"));
10036 constraint (inst
.operands
[0].postind
,
10037 _("post-indexed expression used in preload instruction"));
10038 constraint (inst
.operands
[0].writeback
,
10039 _("writeback used in preload instruction"));
10040 constraint (!inst
.operands
[0].preind
,
10041 _("unindexed addressing used in preload instruction"));
10042 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10045 /* ARMv7: PLI <addr_mode> */
10049 constraint (!inst
.operands
[0].isreg
,
10050 _("'[' expected after PLI mnemonic"));
10051 constraint (inst
.operands
[0].postind
,
10052 _("post-indexed expression used in preload instruction"));
10053 constraint (inst
.operands
[0].writeback
,
10054 _("writeback used in preload instruction"));
10055 constraint (!inst
.operands
[0].preind
,
10056 _("unindexed addressing used in preload instruction"));
10057 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10058 inst
.instruction
&= ~PRE_INDEX
;
10064 constraint (inst
.operands
[0].writeback
,
10065 _("push/pop do not support {reglist}^"));
10066 inst
.operands
[1] = inst
.operands
[0];
10067 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
10068 inst
.operands
[0].isreg
= 1;
10069 inst
.operands
[0].writeback
= 1;
10070 inst
.operands
[0].reg
= REG_SP
;
10071 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
10074 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10075 word at the specified address and the following word
10077 Unconditionally executed.
10078 Error if Rn is R15. */
10083 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10084 if (inst
.operands
[0].writeback
)
10085 inst
.instruction
|= WRITE_BACK
;
10088 /* ARM V6 ssat (argument parse). */
10093 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10094 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
10095 inst
.instruction
|= inst
.operands
[2].reg
;
10097 if (inst
.operands
[3].present
)
10098 encode_arm_shift (3);
10101 /* ARM V6 usat (argument parse). */
10106 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10107 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10108 inst
.instruction
|= inst
.operands
[2].reg
;
10110 if (inst
.operands
[3].present
)
10111 encode_arm_shift (3);
10114 /* ARM V6 ssat16 (argument parse). */
10119 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10120 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10121 inst
.instruction
|= inst
.operands
[2].reg
;
10127 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10128 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10129 inst
.instruction
|= inst
.operands
[2].reg
;
10132 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10133 preserving the other bits.
10135 setend <endian_specifier>, where <endian_specifier> is either
10141 if (warn_on_deprecated
10142 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10143 as_tsktsk (_("setend use is deprecated for ARMv8"));
10145 if (inst
.operands
[0].imm
)
10146 inst
.instruction
|= 0x200;
10152 unsigned int Rm
= (inst
.operands
[1].present
10153 ? inst
.operands
[1].reg
10154 : inst
.operands
[0].reg
);
10156 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10157 inst
.instruction
|= Rm
;
10158 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10160 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10161 inst
.instruction
|= SHIFT_BY_REG
;
10162 /* PR 12854: Error on extraneous shifts. */
10163 constraint (inst
.operands
[2].shifted
,
10164 _("extraneous shift as part of operand to shift insn"));
10167 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10173 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10174 inst
.relocs
[0].pc_rel
= 0;
10180 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10181 inst
.relocs
[0].pc_rel
= 0;
10187 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10188 inst
.relocs
[0].pc_rel
= 0;
10194 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10195 _("selected processor does not support SETPAN instruction"));
10197 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10203 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10204 _("selected processor does not support SETPAN instruction"));
10206 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10209 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10210 SMLAxy{cond} Rd,Rm,Rs,Rn
10211 SMLAWy{cond} Rd,Rm,Rs,Rn
10212 Error if any register is R15. */
10217 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10218 inst
.instruction
|= inst
.operands
[1].reg
;
10219 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10220 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10223 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10224 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10225 Error if any register is R15.
10226 Warning if Rdlo == Rdhi. */
10231 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10232 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10233 inst
.instruction
|= inst
.operands
[2].reg
;
10234 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10236 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10237 as_tsktsk (_("rdhi and rdlo must be different"));
10240 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10241 SMULxy{cond} Rd,Rm,Rs
10242 Error if any register is R15. */
10247 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10248 inst
.instruction
|= inst
.operands
[1].reg
;
10249 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10252 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10253 the same for both ARM and Thumb-2. */
10260 if (inst
.operands
[0].present
)
10262 reg
= inst
.operands
[0].reg
;
10263 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10268 inst
.instruction
|= reg
<< 16;
10269 inst
.instruction
|= inst
.operands
[1].imm
;
10270 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10271 inst
.instruction
|= WRITE_BACK
;
10274 /* ARM V6 strex (argument parse). */
10279 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10280 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10281 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10282 || inst
.operands
[2].negative
10283 /* See comment in do_ldrex(). */
10284 || (inst
.operands
[2].reg
== REG_PC
),
10287 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10288 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10290 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10291 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10292 _("offset must be zero in ARM encoding"));
10294 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10295 inst
.instruction
|= inst
.operands
[1].reg
;
10296 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10297 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10301 do_t_strexbh (void)
10303 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10304 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10305 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10306 || inst
.operands
[2].negative
,
10309 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10310 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10318 constraint (inst
.operands
[1].reg
% 2 != 0,
10319 _("even register required"));
10320 constraint (inst
.operands
[2].present
10321 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10322 _("can only store two consecutive registers"));
10323 /* If op 2 were present and equal to PC, this function wouldn't
10324 have been called in the first place. */
10325 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10327 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10328 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10329 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10332 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10333 inst
.instruction
|= inst
.operands
[1].reg
;
10334 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10341 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10342 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10350 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10351 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10356 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10357 extends it to 32-bits, and adds the result to a value in another
10358 register. You can specify a rotation by 0, 8, 16, or 24 bits
10359 before extracting the 16-bit value.
10360 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10361 Condition defaults to COND_ALWAYS.
10362 Error if any register uses R15. */
10367 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10368 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10369 inst
.instruction
|= inst
.operands
[2].reg
;
10370 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10375 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10376 Condition defaults to COND_ALWAYS.
10377 Error if any register uses R15. */
10382 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10383 inst
.instruction
|= inst
.operands
[1].reg
;
10384 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10387 /* VFP instructions. In a logical order: SP variant first, monad
10388 before dyad, arithmetic then move then load/store. */
10391 do_vfp_sp_monadic (void)
10393 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10394 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10397 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10398 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10402 do_vfp_sp_dyadic (void)
10404 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10405 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10406 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10410 do_vfp_sp_compare_z (void)
10412 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10416 do_vfp_dp_sp_cvt (void)
10418 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10419 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10423 do_vfp_sp_dp_cvt (void)
10425 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10426 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10430 do_vfp_reg_from_sp (void)
10432 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10433 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10436 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10437 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10441 do_vfp_reg2_from_sp2 (void)
10443 constraint (inst
.operands
[2].imm
!= 2,
10444 _("only two consecutive VFP SP registers allowed here"));
10445 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10446 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10447 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10451 do_vfp_sp_from_reg (void)
10453 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10454 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10457 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10458 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10462 do_vfp_sp2_from_reg2 (void)
10464 constraint (inst
.operands
[0].imm
!= 2,
10465 _("only two consecutive VFP SP registers allowed here"));
10466 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10467 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10468 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10472 do_vfp_sp_ldst (void)
10474 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10475 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10479 do_vfp_dp_ldst (void)
10481 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10482 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10487 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10489 if (inst
.operands
[0].writeback
)
10490 inst
.instruction
|= WRITE_BACK
;
10492 constraint (ldstm_type
!= VFP_LDSTMIA
,
10493 _("this addressing mode requires base-register writeback"));
10494 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10495 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10496 inst
.instruction
|= inst
.operands
[1].imm
;
10500 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10504 if (inst
.operands
[0].writeback
)
10505 inst
.instruction
|= WRITE_BACK
;
10507 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10508 _("this addressing mode requires base-register writeback"));
10510 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10511 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10513 count
= inst
.operands
[1].imm
<< 1;
10514 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10517 inst
.instruction
|= count
;
10521 do_vfp_sp_ldstmia (void)
10523 vfp_sp_ldstm (VFP_LDSTMIA
);
10527 do_vfp_sp_ldstmdb (void)
10529 vfp_sp_ldstm (VFP_LDSTMDB
);
10533 do_vfp_dp_ldstmia (void)
10535 vfp_dp_ldstm (VFP_LDSTMIA
);
10539 do_vfp_dp_ldstmdb (void)
10541 vfp_dp_ldstm (VFP_LDSTMDB
);
10545 do_vfp_xp_ldstmia (void)
10547 vfp_dp_ldstm (VFP_LDSTMIAX
);
10551 do_vfp_xp_ldstmdb (void)
10553 vfp_dp_ldstm (VFP_LDSTMDBX
);
10557 do_vfp_dp_rd_rm (void)
10559 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10560 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10563 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10564 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10568 do_vfp_dp_rn_rd (void)
10570 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10571 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10575 do_vfp_dp_rd_rn (void)
10577 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10578 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10582 do_vfp_dp_rd_rn_rm (void)
10584 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10585 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10588 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10589 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10590 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10594 do_vfp_dp_rd (void)
10596 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10600 do_vfp_dp_rm_rd_rn (void)
10602 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10603 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10606 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10607 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10608 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10611 /* VFPv3 instructions. */
10613 do_vfp_sp_const (void)
10615 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10616 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10617 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10621 do_vfp_dp_const (void)
10623 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10624 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10625 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10629 vfp_conv (int srcsize
)
10631 int immbits
= srcsize
- inst
.operands
[1].imm
;
10633 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10635 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10636 i.e. immbits must be in range 0 - 16. */
10637 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10640 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10642 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10643 i.e. immbits must be in range 0 - 31. */
10644 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10648 inst
.instruction
|= (immbits
& 1) << 5;
10649 inst
.instruction
|= (immbits
>> 1);
10653 do_vfp_sp_conv_16 (void)
10655 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10660 do_vfp_dp_conv_16 (void)
10662 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10667 do_vfp_sp_conv_32 (void)
10669 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10674 do_vfp_dp_conv_32 (void)
10676 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10680 /* FPA instructions. Also in a logical order. */
10685 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10686 inst
.instruction
|= inst
.operands
[1].reg
;
10690 do_fpa_ldmstm (void)
10692 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10693 switch (inst
.operands
[1].imm
)
10695 case 1: inst
.instruction
|= CP_T_X
; break;
10696 case 2: inst
.instruction
|= CP_T_Y
; break;
10697 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10702 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10704 /* The instruction specified "ea" or "fd", so we can only accept
10705 [Rn]{!}. The instruction does not really support stacking or
10706 unstacking, so we have to emulate these by setting appropriate
10707 bits and offsets. */
10708 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10709 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10710 _("this instruction does not support indexing"));
10712 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10713 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10715 if (!(inst
.instruction
& INDEX_UP
))
10716 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
10718 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10720 inst
.operands
[2].preind
= 0;
10721 inst
.operands
[2].postind
= 1;
10725 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10728 /* iWMMXt instructions: strictly in alphabetical order. */
10731 do_iwmmxt_tandorc (void)
10733 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10737 do_iwmmxt_textrc (void)
10739 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10740 inst
.instruction
|= inst
.operands
[1].imm
;
10744 do_iwmmxt_textrm (void)
10746 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10747 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10748 inst
.instruction
|= inst
.operands
[2].imm
;
10752 do_iwmmxt_tinsr (void)
10754 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10755 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10756 inst
.instruction
|= inst
.operands
[2].imm
;
10760 do_iwmmxt_tmia (void)
10762 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10763 inst
.instruction
|= inst
.operands
[1].reg
;
10764 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10768 do_iwmmxt_waligni (void)
10770 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10771 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10772 inst
.instruction
|= inst
.operands
[2].reg
;
10773 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10777 do_iwmmxt_wmerge (void)
10779 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10780 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10781 inst
.instruction
|= inst
.operands
[2].reg
;
10782 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10786 do_iwmmxt_wmov (void)
10788 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10789 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10790 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10791 inst
.instruction
|= inst
.operands
[1].reg
;
10795 do_iwmmxt_wldstbh (void)
10798 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10800 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10802 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10803 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10807 do_iwmmxt_wldstw (void)
10809 /* RIWR_RIWC clears .isreg for a control register. */
10810 if (!inst
.operands
[0].isreg
)
10812 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10813 inst
.instruction
|= 0xf0000000;
10816 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10817 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10821 do_iwmmxt_wldstd (void)
10823 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10824 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10825 && inst
.operands
[1].immisreg
)
10827 inst
.instruction
&= ~0x1a000ff;
10828 inst
.instruction
|= (0xfU
<< 28);
10829 if (inst
.operands
[1].preind
)
10830 inst
.instruction
|= PRE_INDEX
;
10831 if (!inst
.operands
[1].negative
)
10832 inst
.instruction
|= INDEX_UP
;
10833 if (inst
.operands
[1].writeback
)
10834 inst
.instruction
|= WRITE_BACK
;
10835 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10836 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
10837 inst
.instruction
|= inst
.operands
[1].imm
;
10840 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10844 do_iwmmxt_wshufh (void)
10846 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10847 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10848 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10849 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10853 do_iwmmxt_wzero (void)
10855 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10856 inst
.instruction
|= inst
.operands
[0].reg
;
10857 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10858 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10862 do_iwmmxt_wrwrwr_or_imm5 (void)
10864 if (inst
.operands
[2].isreg
)
10867 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10868 _("immediate operand requires iWMMXt2"));
10870 if (inst
.operands
[2].imm
== 0)
10872 switch ((inst
.instruction
>> 20) & 0xf)
10878 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10879 inst
.operands
[2].imm
= 16;
10880 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10886 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10887 inst
.operands
[2].imm
= 32;
10888 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10895 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10897 wrn
= (inst
.instruction
>> 16) & 0xf;
10898 inst
.instruction
&= 0xff0fff0f;
10899 inst
.instruction
|= wrn
;
10900 /* Bail out here; the instruction is now assembled. */
10905 /* Map 32 -> 0, etc. */
10906 inst
.operands
[2].imm
&= 0x1f;
10907 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10911 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10912 operations first, then control, shift, and load/store. */
10914 /* Insns like "foo X,Y,Z". */
10917 do_mav_triple (void)
10919 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10920 inst
.instruction
|= inst
.operands
[1].reg
;
10921 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10924 /* Insns like "foo W,X,Y,Z".
10925 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10930 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10931 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10932 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10933 inst
.instruction
|= inst
.operands
[3].reg
;
10936 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10938 do_mav_dspsc (void)
10940 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10943 /* Maverick shift immediate instructions.
10944 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10945 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10948 do_mav_shift (void)
10950 int imm
= inst
.operands
[2].imm
;
10952 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10953 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10955 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10956 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10957 Bit 4 should be 0. */
10958 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10960 inst
.instruction
|= imm
;
10963 /* XScale instructions. Also sorted arithmetic before move. */
10965 /* Xscale multiply-accumulate (argument parse)
10968 MIAxycc acc0,Rm,Rs. */
10973 inst
.instruction
|= inst
.operands
[1].reg
;
10974 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10977 /* Xscale move-accumulator-register (argument parse)
10979 MARcc acc0,RdLo,RdHi. */
10984 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10985 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10988 /* Xscale move-register-accumulator (argument parse)
10990 MRAcc RdLo,RdHi,acc0. */
10995 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10996 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10997 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11000 /* Encoding functions relevant only to Thumb. */
11002 /* inst.operands[i] is a shifted-register operand; encode
11003 it into inst.instruction in the format used by Thumb32. */
11006 encode_thumb32_shifted_operand (int i
)
11008 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11009 unsigned int shift
= inst
.operands
[i
].shift_kind
;
11011 constraint (inst
.operands
[i
].immisreg
,
11012 _("shift by register not allowed in thumb mode"));
11013 inst
.instruction
|= inst
.operands
[i
].reg
;
11014 if (shift
== SHIFT_RRX
)
11015 inst
.instruction
|= SHIFT_ROR
<< 4;
11018 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11019 _("expression too complex"));
11021 constraint (value
> 32
11022 || (value
== 32 && (shift
== SHIFT_LSL
11023 || shift
== SHIFT_ROR
)),
11024 _("shift expression is too large"));
11028 else if (value
== 32)
11031 inst
.instruction
|= shift
<< 4;
11032 inst
.instruction
|= (value
& 0x1c) << 10;
11033 inst
.instruction
|= (value
& 0x03) << 6;
11038 /* inst.operands[i] was set up by parse_address. Encode it into a
11039 Thumb32 format load or store instruction. Reject forms that cannot
11040 be used with such instructions. If is_t is true, reject forms that
11041 cannot be used with a T instruction; if is_d is true, reject forms
11042 that cannot be used with a D instruction. If it is a store insn,
11043 reject PC in Rn. */
11046 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
11048 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
11050 constraint (!inst
.operands
[i
].isreg
,
11051 _("Instruction does not support =N addresses"));
11053 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
11054 if (inst
.operands
[i
].immisreg
)
11056 constraint (is_pc
, BAD_PC_ADDRESSING
);
11057 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
11058 constraint (inst
.operands
[i
].negative
,
11059 _("Thumb does not support negative register indexing"));
11060 constraint (inst
.operands
[i
].postind
,
11061 _("Thumb does not support register post-indexing"));
11062 constraint (inst
.operands
[i
].writeback
,
11063 _("Thumb does not support register indexing with writeback"));
11064 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
11065 _("Thumb supports only LSL in shifted register indexing"));
11067 inst
.instruction
|= inst
.operands
[i
].imm
;
11068 if (inst
.operands
[i
].shifted
)
11070 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11071 _("expression too complex"));
11072 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11073 || inst
.relocs
[0].exp
.X_add_number
> 3,
11074 _("shift out of range"));
11075 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11077 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11079 else if (inst
.operands
[i
].preind
)
11081 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
11082 constraint (is_t
&& inst
.operands
[i
].writeback
,
11083 _("cannot use writeback with this instruction"));
11084 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
11085 BAD_PC_ADDRESSING
);
11089 inst
.instruction
|= 0x01000000;
11090 if (inst
.operands
[i
].writeback
)
11091 inst
.instruction
|= 0x00200000;
11095 inst
.instruction
|= 0x00000c00;
11096 if (inst
.operands
[i
].writeback
)
11097 inst
.instruction
|= 0x00000100;
11099 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11101 else if (inst
.operands
[i
].postind
)
11103 gas_assert (inst
.operands
[i
].writeback
);
11104 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11105 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11108 inst
.instruction
|= 0x00200000;
11110 inst
.instruction
|= 0x00000900;
11111 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11113 else /* unindexed - only for coprocessor */
11114 inst
.error
= _("instruction does not accept unindexed addressing");
11117 /* Table of Thumb instructions which exist in 16- and/or 32-bit
11118 encodings (the latter only in post-V6T2 cores). The index is the
11119 value used in the insns table below. When there is more than one
11120 possible 16-bit encoding for the instruction, this table always
11122 Also contains several pseudo-instructions used during relaxation. */
11123 #define T16_32_TAB \
11124 X(_adc, 4140, eb400000), \
11125 X(_adcs, 4140, eb500000), \
11126 X(_add, 1c00, eb000000), \
11127 X(_adds, 1c00, eb100000), \
11128 X(_addi, 0000, f1000000), \
11129 X(_addis, 0000, f1100000), \
11130 X(_add_pc,000f, f20f0000), \
11131 X(_add_sp,000d, f10d0000), \
11132 X(_adr, 000f, f20f0000), \
11133 X(_and, 4000, ea000000), \
11134 X(_ands, 4000, ea100000), \
11135 X(_asr, 1000, fa40f000), \
11136 X(_asrs, 1000, fa50f000), \
11137 X(_b, e000, f000b000), \
11138 X(_bcond, d000, f0008000), \
11139 X(_bf, 0000, f040e001), \
11140 X(_bfcsel,0000, f000e001), \
11141 X(_bfx, 0000, f060e001), \
11142 X(_bfl, 0000, f000c001), \
11143 X(_bflx, 0000, f070e001), \
11144 X(_bic, 4380, ea200000), \
11145 X(_bics, 4380, ea300000), \
11146 X(_cinc, 0000, ea509000), \
11147 X(_cinv, 0000, ea50a000), \
11148 X(_cmn, 42c0, eb100f00), \
11149 X(_cmp, 2800, ebb00f00), \
11150 X(_cneg, 0000, ea50b000), \
11151 X(_cpsie, b660, f3af8400), \
11152 X(_cpsid, b670, f3af8600), \
11153 X(_cpy, 4600, ea4f0000), \
11154 X(_csel, 0000, ea508000), \
11155 X(_cset, 0000, ea5f900f), \
11156 X(_csetm, 0000, ea5fa00f), \
11157 X(_csinc, 0000, ea509000), \
11158 X(_csinv, 0000, ea50a000), \
11159 X(_csneg, 0000, ea50b000), \
11160 X(_dec_sp,80dd, f1ad0d00), \
11161 X(_dls, 0000, f040e001), \
11162 X(_dlstp, 0000, f000e001), \
11163 X(_eor, 4040, ea800000), \
11164 X(_eors, 4040, ea900000), \
11165 X(_inc_sp,00dd, f10d0d00), \
11166 X(_lctp, 0000, f00fe001), \
11167 X(_ldmia, c800, e8900000), \
11168 X(_ldr, 6800, f8500000), \
11169 X(_ldrb, 7800, f8100000), \
11170 X(_ldrh, 8800, f8300000), \
11171 X(_ldrsb, 5600, f9100000), \
11172 X(_ldrsh, 5e00, f9300000), \
11173 X(_ldr_pc,4800, f85f0000), \
11174 X(_ldr_pc2,4800, f85f0000), \
11175 X(_ldr_sp,9800, f85d0000), \
11176 X(_le, 0000, f00fc001), \
11177 X(_letp, 0000, f01fc001), \
11178 X(_lsl, 0000, fa00f000), \
11179 X(_lsls, 0000, fa10f000), \
11180 X(_lsr, 0800, fa20f000), \
11181 X(_lsrs, 0800, fa30f000), \
11182 X(_mov, 2000, ea4f0000), \
11183 X(_movs, 2000, ea5f0000), \
11184 X(_mul, 4340, fb00f000), \
11185 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11186 X(_mvn, 43c0, ea6f0000), \
11187 X(_mvns, 43c0, ea7f0000), \
11188 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11189 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11190 X(_orr, 4300, ea400000), \
11191 X(_orrs, 4300, ea500000), \
11192 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11193 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11194 X(_rev, ba00, fa90f080), \
11195 X(_rev16, ba40, fa90f090), \
11196 X(_revsh, bac0, fa90f0b0), \
11197 X(_ror, 41c0, fa60f000), \
11198 X(_rors, 41c0, fa70f000), \
11199 X(_sbc, 4180, eb600000), \
11200 X(_sbcs, 4180, eb700000), \
11201 X(_stmia, c000, e8800000), \
11202 X(_str, 6000, f8400000), \
11203 X(_strb, 7000, f8000000), \
11204 X(_strh, 8000, f8200000), \
11205 X(_str_sp,9000, f84d0000), \
11206 X(_sub, 1e00, eba00000), \
11207 X(_subs, 1e00, ebb00000), \
11208 X(_subi, 8000, f1a00000), \
11209 X(_subis, 8000, f1b00000), \
11210 X(_sxtb, b240, fa4ff080), \
11211 X(_sxth, b200, fa0ff080), \
11212 X(_tst, 4200, ea100f00), \
11213 X(_uxtb, b2c0, fa5ff080), \
11214 X(_uxth, b280, fa1ff080), \
11215 X(_nop, bf00, f3af8000), \
11216 X(_yield, bf10, f3af8001), \
11217 X(_wfe, bf20, f3af8002), \
11218 X(_wfi, bf30, f3af8003), \
11219 X(_wls, 0000, f040c001), \
11220 X(_wlstp, 0000, f000c001), \
11221 X(_sev, bf40, f3af8004), \
11222 X(_sevl, bf50, f3af8005), \
11223 X(_udf, de00, f7f0a000)
11225 /* To catch errors in encoding functions, the codes are all offset by
11226 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11227 as 16-bit instructions. */
11228 #define X(a,b,c) T_MNEM##a
11229 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11232 #define X(a,b,c) 0x##b
11233 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11234 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11237 #define X(a,b,c) 0x##c
11238 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11239 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11240 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11244 /* Thumb instruction encoders, in alphabetical order. */
11246 /* ADDW or SUBW. */
11249 do_t_add_sub_w (void)
11253 Rd
= inst
.operands
[0].reg
;
11254 Rn
= inst
.operands
[1].reg
;
11256 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11257 is the SP-{plus,minus}-immediate form of the instruction. */
11259 constraint (Rd
== REG_PC
, BAD_PC
);
11261 reject_bad_reg (Rd
);
11263 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11264 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11267 /* Parse an add or subtract instruction. We get here with inst.instruction
11268 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11271 do_t_add_sub (void)
11275 Rd
= inst
.operands
[0].reg
;
11276 Rs
= (inst
.operands
[1].present
11277 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11278 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11281 set_pred_insn_type_last ();
11283 if (unified_syntax
)
11286 bfd_boolean narrow
;
11289 flags
= (inst
.instruction
== T_MNEM_adds
11290 || inst
.instruction
== T_MNEM_subs
);
11292 narrow
= !in_pred_block ();
11294 narrow
= in_pred_block ();
11295 if (!inst
.operands
[2].isreg
)
11299 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11300 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11302 add
= (inst
.instruction
== T_MNEM_add
11303 || inst
.instruction
== T_MNEM_adds
);
11305 if (inst
.size_req
!= 4)
11307 /* Attempt to use a narrow opcode, with relaxation if
11309 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11310 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11311 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11312 opcode
= T_MNEM_add_sp
;
11313 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11314 opcode
= T_MNEM_add_pc
;
11315 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11318 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11320 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11324 inst
.instruction
= THUMB_OP16(opcode
);
11325 inst
.instruction
|= (Rd
<< 4) | Rs
;
11326 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11327 || (inst
.relocs
[0].type
11328 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11330 if (inst
.size_req
== 2)
11331 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11333 inst
.relax
= opcode
;
11337 constraint (inst
.size_req
== 2, BAD_HIREG
);
11339 if (inst
.size_req
== 4
11340 || (inst
.size_req
!= 2 && !opcode
))
11342 constraint ((inst
.relocs
[0].type
11343 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11344 && (inst
.relocs
[0].type
11345 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11346 THUMB1_RELOC_ONLY
);
11349 constraint (add
, BAD_PC
);
11350 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11351 _("only SUBS PC, LR, #const allowed"));
11352 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11353 _("expression too complex"));
11354 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11355 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11356 _("immediate value out of range"));
11357 inst
.instruction
= T2_SUBS_PC_LR
11358 | inst
.relocs
[0].exp
.X_add_number
;
11359 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11362 else if (Rs
== REG_PC
)
11364 /* Always use addw/subw. */
11365 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11366 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11370 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11371 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11374 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11376 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11378 inst
.instruction
|= Rd
<< 8;
11379 inst
.instruction
|= Rs
<< 16;
11384 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11385 unsigned int shift
= inst
.operands
[2].shift_kind
;
11387 Rn
= inst
.operands
[2].reg
;
11388 /* See if we can do this with a 16-bit instruction. */
11389 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11391 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11396 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11397 || inst
.instruction
== T_MNEM_add
)
11399 : T_OPCODE_SUB_R3
);
11400 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11404 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11406 /* Thumb-1 cores (except v6-M) require at least one high
11407 register in a narrow non flag setting add. */
11408 if (Rd
> 7 || Rn
> 7
11409 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11410 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11417 inst
.instruction
= T_OPCODE_ADD_HI
;
11418 inst
.instruction
|= (Rd
& 8) << 4;
11419 inst
.instruction
|= (Rd
& 7);
11420 inst
.instruction
|= Rn
<< 3;
11426 constraint (Rd
== REG_PC
, BAD_PC
);
11427 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11428 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11429 constraint (Rs
== REG_PC
, BAD_PC
);
11430 reject_bad_reg (Rn
);
11432 /* If we get here, it can't be done in 16 bits. */
11433 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11434 _("shift must be constant"));
11435 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11436 inst
.instruction
|= Rd
<< 8;
11437 inst
.instruction
|= Rs
<< 16;
11438 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11439 _("shift value over 3 not allowed in thumb mode"));
11440 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11441 _("only LSL shift allowed in thumb mode"));
11442 encode_thumb32_shifted_operand (2);
11447 constraint (inst
.instruction
== T_MNEM_adds
11448 || inst
.instruction
== T_MNEM_subs
,
11451 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11453 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11454 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11457 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11458 ? 0x0000 : 0x8000);
11459 inst
.instruction
|= (Rd
<< 4) | Rs
;
11460 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11464 Rn
= inst
.operands
[2].reg
;
11465 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11467 /* We now have Rd, Rs, and Rn set to registers. */
11468 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11470 /* Can't do this for SUB. */
11471 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11472 inst
.instruction
= T_OPCODE_ADD_HI
;
11473 inst
.instruction
|= (Rd
& 8) << 4;
11474 inst
.instruction
|= (Rd
& 7);
11476 inst
.instruction
|= Rn
<< 3;
11478 inst
.instruction
|= Rs
<< 3;
11480 constraint (1, _("dest must overlap one source register"));
11484 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11485 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11486 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11496 Rd
= inst
.operands
[0].reg
;
11497 reject_bad_reg (Rd
);
11499 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11501 /* Defer to section relaxation. */
11502 inst
.relax
= inst
.instruction
;
11503 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11504 inst
.instruction
|= Rd
<< 4;
11506 else if (unified_syntax
&& inst
.size_req
!= 2)
11508 /* Generate a 32-bit opcode. */
11509 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11510 inst
.instruction
|= Rd
<< 8;
11511 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11512 inst
.relocs
[0].pc_rel
= 1;
11516 /* Generate a 16-bit opcode. */
11517 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11518 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11519 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11520 inst
.relocs
[0].pc_rel
= 1;
11521 inst
.instruction
|= Rd
<< 4;
11524 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11525 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11526 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11527 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11528 inst
.relocs
[0].exp
.X_add_number
+= 1;
11531 /* Arithmetic instructions for which there is just one 16-bit
11532 instruction encoding, and it allows only two low registers.
11533 For maximal compatibility with ARM syntax, we allow three register
11534 operands even when Thumb-32 instructions are not available, as long
11535 as the first two are identical. For instance, both "sbc r0,r1" and
11536 "sbc r0,r0,r1" are allowed. */
11542 Rd
= inst
.operands
[0].reg
;
11543 Rs
= (inst
.operands
[1].present
11544 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11545 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11546 Rn
= inst
.operands
[2].reg
;
11548 reject_bad_reg (Rd
);
11549 reject_bad_reg (Rs
);
11550 if (inst
.operands
[2].isreg
)
11551 reject_bad_reg (Rn
);
11553 if (unified_syntax
)
11555 if (!inst
.operands
[2].isreg
)
11557 /* For an immediate, we always generate a 32-bit opcode;
11558 section relaxation will shrink it later if possible. */
11559 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11560 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11561 inst
.instruction
|= Rd
<< 8;
11562 inst
.instruction
|= Rs
<< 16;
11563 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11567 bfd_boolean narrow
;
11569 /* See if we can do this with a 16-bit instruction. */
11570 if (THUMB_SETS_FLAGS (inst
.instruction
))
11571 narrow
= !in_pred_block ();
11573 narrow
= in_pred_block ();
11575 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11577 if (inst
.operands
[2].shifted
)
11579 if (inst
.size_req
== 4)
11585 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11586 inst
.instruction
|= Rd
;
11587 inst
.instruction
|= Rn
<< 3;
11591 /* If we get here, it can't be done in 16 bits. */
11592 constraint (inst
.operands
[2].shifted
11593 && inst
.operands
[2].immisreg
,
11594 _("shift must be constant"));
11595 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11596 inst
.instruction
|= Rd
<< 8;
11597 inst
.instruction
|= Rs
<< 16;
11598 encode_thumb32_shifted_operand (2);
11603 /* On its face this is a lie - the instruction does set the
11604 flags. However, the only supported mnemonic in this mode
11605 says it doesn't. */
11606 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11608 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11609 _("unshifted register required"));
11610 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11611 constraint (Rd
!= Rs
,
11612 _("dest and source1 must be the same register"));
11614 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11615 inst
.instruction
|= Rd
;
11616 inst
.instruction
|= Rn
<< 3;
11620 /* Similarly, but for instructions where the arithmetic operation is
11621 commutative, so we can allow either of them to be different from
11622 the destination operand in a 16-bit instruction. For instance, all
11623 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11630 Rd
= inst
.operands
[0].reg
;
11631 Rs
= (inst
.operands
[1].present
11632 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11633 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11634 Rn
= inst
.operands
[2].reg
;
11636 reject_bad_reg (Rd
);
11637 reject_bad_reg (Rs
);
11638 if (inst
.operands
[2].isreg
)
11639 reject_bad_reg (Rn
);
11641 if (unified_syntax
)
11643 if (!inst
.operands
[2].isreg
)
11645 /* For an immediate, we always generate a 32-bit opcode;
11646 section relaxation will shrink it later if possible. */
11647 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11648 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11649 inst
.instruction
|= Rd
<< 8;
11650 inst
.instruction
|= Rs
<< 16;
11651 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11655 bfd_boolean narrow
;
11657 /* See if we can do this with a 16-bit instruction. */
11658 if (THUMB_SETS_FLAGS (inst
.instruction
))
11659 narrow
= !in_pred_block ();
11661 narrow
= in_pred_block ();
11663 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11665 if (inst
.operands
[2].shifted
)
11667 if (inst
.size_req
== 4)
11674 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11675 inst
.instruction
|= Rd
;
11676 inst
.instruction
|= Rn
<< 3;
11681 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11682 inst
.instruction
|= Rd
;
11683 inst
.instruction
|= Rs
<< 3;
11688 /* If we get here, it can't be done in 16 bits. */
11689 constraint (inst
.operands
[2].shifted
11690 && inst
.operands
[2].immisreg
,
11691 _("shift must be constant"));
11692 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11693 inst
.instruction
|= Rd
<< 8;
11694 inst
.instruction
|= Rs
<< 16;
11695 encode_thumb32_shifted_operand (2);
11700 /* On its face this is a lie - the instruction does set the
11701 flags. However, the only supported mnemonic in this mode
11702 says it doesn't. */
11703 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11705 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11706 _("unshifted register required"));
11707 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11709 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11710 inst
.instruction
|= Rd
;
11713 inst
.instruction
|= Rn
<< 3;
11715 inst
.instruction
|= Rs
<< 3;
11717 constraint (1, _("dest must overlap one source register"));
11725 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11726 constraint (msb
> 32, _("bit-field extends past end of register"));
11727 /* The instruction encoding stores the LSB and MSB,
11728 not the LSB and width. */
11729 Rd
= inst
.operands
[0].reg
;
11730 reject_bad_reg (Rd
);
11731 inst
.instruction
|= Rd
<< 8;
11732 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11733 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11734 inst
.instruction
|= msb
- 1;
11743 Rd
= inst
.operands
[0].reg
;
11744 reject_bad_reg (Rd
);
11746 /* #0 in second position is alternative syntax for bfc, which is
11747 the same instruction but with REG_PC in the Rm field. */
11748 if (!inst
.operands
[1].isreg
)
11752 Rn
= inst
.operands
[1].reg
;
11753 reject_bad_reg (Rn
);
11756 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11757 constraint (msb
> 32, _("bit-field extends past end of register"));
11758 /* The instruction encoding stores the LSB and MSB,
11759 not the LSB and width. */
11760 inst
.instruction
|= Rd
<< 8;
11761 inst
.instruction
|= Rn
<< 16;
11762 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11763 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11764 inst
.instruction
|= msb
- 1;
11772 Rd
= inst
.operands
[0].reg
;
11773 Rn
= inst
.operands
[1].reg
;
11775 reject_bad_reg (Rd
);
11776 reject_bad_reg (Rn
);
11778 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11779 _("bit-field extends past end of register"));
11780 inst
.instruction
|= Rd
<< 8;
11781 inst
.instruction
|= Rn
<< 16;
11782 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11783 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11784 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11787 /* ARM V5 Thumb BLX (argument parse)
11788 BLX <target_addr> which is BLX(1)
11789 BLX <Rm> which is BLX(2)
11790 Unfortunately, there are two different opcodes for this mnemonic.
11791 So, the insns[].value is not used, and the code here zaps values
11792 into inst.instruction.
11794 ??? How to take advantage of the additional two bits of displacement
11795 available in Thumb32 mode? Need new relocation? */
11800 set_pred_insn_type_last ();
11802 if (inst
.operands
[0].isreg
)
11804 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11805 /* We have a register, so this is BLX(2). */
11806 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11810 /* No register. This must be BLX(1). */
11811 inst
.instruction
= 0xf000e800;
11812 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11821 bfd_reloc_code_real_type reloc
;
11824 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
11826 if (in_pred_block ())
11828 /* Conditional branches inside IT blocks are encoded as unconditional
11830 cond
= COND_ALWAYS
;
11835 if (cond
!= COND_ALWAYS
)
11836 opcode
= T_MNEM_bcond
;
11838 opcode
= inst
.instruction
;
11841 && (inst
.size_req
== 4
11842 || (inst
.size_req
!= 2
11843 && (inst
.operands
[0].hasreloc
11844 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
11846 inst
.instruction
= THUMB_OP32(opcode
);
11847 if (cond
== COND_ALWAYS
)
11848 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11851 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11852 _("selected architecture does not support "
11853 "wide conditional branch instruction"));
11855 gas_assert (cond
!= 0xF);
11856 inst
.instruction
|= cond
<< 22;
11857 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11862 inst
.instruction
= THUMB_OP16(opcode
);
11863 if (cond
== COND_ALWAYS
)
11864 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11867 inst
.instruction
|= cond
<< 8;
11868 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11870 /* Allow section relaxation. */
11871 if (unified_syntax
&& inst
.size_req
!= 2)
11872 inst
.relax
= opcode
;
11874 inst
.relocs
[0].type
= reloc
;
11875 inst
.relocs
[0].pc_rel
= 1;
11878 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11879 between the two is the maximum immediate allowed - which is passed in
11882 do_t_bkpt_hlt1 (int range
)
11884 constraint (inst
.cond
!= COND_ALWAYS
,
11885 _("instruction is always unconditional"));
11886 if (inst
.operands
[0].present
)
11888 constraint (inst
.operands
[0].imm
> range
,
11889 _("immediate value out of range"));
11890 inst
.instruction
|= inst
.operands
[0].imm
;
11893 set_pred_insn_type (NEUTRAL_IT_INSN
);
11899 do_t_bkpt_hlt1 (63);
11905 do_t_bkpt_hlt1 (255);
11909 do_t_branch23 (void)
11911 set_pred_insn_type_last ();
11912 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11914 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11915 this file. We used to simply ignore the PLT reloc type here --
11916 the branch encoding is now needed to deal with TLSCALL relocs.
11917 So if we see a PLT reloc now, put it back to how it used to be to
11918 keep the preexisting behaviour. */
11919 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
11920 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11922 #if defined(OBJ_COFF)
11923 /* If the destination of the branch is a defined symbol which does not have
11924 the THUMB_FUNC attribute, then we must be calling a function which has
11925 the (interfacearm) attribute. We look for the Thumb entry point to that
11926 function and change the branch to refer to that function instead. */
11927 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
11928 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11929 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11930 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11931 inst
.relocs
[0].exp
.X_add_symbol
11932 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
11939 set_pred_insn_type_last ();
11940 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11941 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11942 should cause the alignment to be checked once it is known. This is
11943 because BX PC only works if the instruction is word aligned. */
11951 set_pred_insn_type_last ();
11952 Rm
= inst
.operands
[0].reg
;
11953 reject_bad_reg (Rm
);
11954 inst
.instruction
|= Rm
<< 16;
11963 Rd
= inst
.operands
[0].reg
;
11964 Rm
= inst
.operands
[1].reg
;
11966 reject_bad_reg (Rd
);
11967 reject_bad_reg (Rm
);
11969 inst
.instruction
|= Rd
<< 8;
11970 inst
.instruction
|= Rm
<< 16;
11971 inst
.instruction
|= Rm
;
11974 /* For the Armv8.1-M conditional instructions. */
11978 unsigned Rd
, Rn
, Rm
;
11981 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
11983 Rd
= inst
.operands
[0].reg
;
11984 switch (inst
.instruction
)
11990 Rn
= inst
.operands
[1].reg
;
11991 Rm
= inst
.operands
[2].reg
;
11992 cond
= inst
.operands
[3].imm
;
11993 constraint (Rn
== REG_SP
, BAD_SP
);
11994 constraint (Rm
== REG_SP
, BAD_SP
);
12000 Rn
= inst
.operands
[1].reg
;
12001 cond
= inst
.operands
[2].imm
;
12002 /* Invert the last bit to invert the cond. */
12003 cond
= TOGGLE_BIT (cond
, 0);
12004 constraint (Rn
== REG_SP
, BAD_SP
);
12010 cond
= inst
.operands
[1].imm
;
12011 /* Invert the last bit to invert the cond. */
12012 cond
= TOGGLE_BIT (cond
, 0);
12020 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12021 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12022 inst
.instruction
|= Rd
<< 8;
12023 inst
.instruction
|= Rn
<< 16;
12024 inst
.instruction
|= Rm
;
12025 inst
.instruction
|= cond
<< 4;
12031 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12037 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12038 inst
.instruction
|= inst
.operands
[0].imm
;
12044 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12046 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
12047 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
12049 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
12050 inst
.instruction
= 0xf3af8000;
12051 inst
.instruction
|= imod
<< 9;
12052 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
12053 if (inst
.operands
[1].present
)
12054 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
12058 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
12059 && (inst
.operands
[0].imm
& 4),
12060 _("selected processor does not support 'A' form "
12061 "of this instruction"));
12062 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
12063 _("Thumb does not support the 2-argument "
12064 "form of this instruction"));
12065 inst
.instruction
|= inst
.operands
[0].imm
;
12069 /* THUMB CPY instruction (argument parse). */
12074 if (inst
.size_req
== 4)
12076 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
12077 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12078 inst
.instruction
|= inst
.operands
[1].reg
;
12082 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
12083 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
12084 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12091 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12092 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12093 inst
.instruction
|= inst
.operands
[0].reg
;
12094 inst
.relocs
[0].pc_rel
= 1;
12095 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
12101 inst
.instruction
|= inst
.operands
[0].imm
;
12107 unsigned Rd
, Rn
, Rm
;
12109 Rd
= inst
.operands
[0].reg
;
12110 Rn
= (inst
.operands
[1].present
12111 ? inst
.operands
[1].reg
: Rd
);
12112 Rm
= inst
.operands
[2].reg
;
12114 reject_bad_reg (Rd
);
12115 reject_bad_reg (Rn
);
12116 reject_bad_reg (Rm
);
12118 inst
.instruction
|= Rd
<< 8;
12119 inst
.instruction
|= Rn
<< 16;
12120 inst
.instruction
|= Rm
;
12126 if (unified_syntax
&& inst
.size_req
== 4)
12127 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12129 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12135 unsigned int cond
= inst
.operands
[0].imm
;
12137 set_pred_insn_type (IT_INSN
);
12138 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
12139 now_pred
.cc
= cond
;
12140 now_pred
.warn_deprecated
= FALSE
;
12141 now_pred
.type
= SCALAR_PRED
;
12143 /* If the condition is a negative condition, invert the mask. */
12144 if ((cond
& 0x1) == 0x0)
12146 unsigned int mask
= inst
.instruction
& 0x000f;
12148 if ((mask
& 0x7) == 0)
12150 /* No conversion needed. */
12151 now_pred
.block_length
= 1;
12153 else if ((mask
& 0x3) == 0)
12156 now_pred
.block_length
= 2;
12158 else if ((mask
& 0x1) == 0)
12161 now_pred
.block_length
= 3;
12166 now_pred
.block_length
= 4;
12169 inst
.instruction
&= 0xfff0;
12170 inst
.instruction
|= mask
;
12173 inst
.instruction
|= cond
<< 4;
12176 /* Helper function used for both push/pop and ldm/stm. */
12178 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
12179 bfd_boolean writeback
)
12181 bfd_boolean load
, store
;
12183 gas_assert (base
!= -1 || !do_io
);
12184 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12185 store
= do_io
&& !load
;
12187 if (mask
& (1 << 13))
12188 inst
.error
= _("SP not allowed in register list");
12190 if (do_io
&& (mask
& (1 << base
)) != 0
12192 inst
.error
= _("having the base register in the register list when "
12193 "using write back is UNPREDICTABLE");
12197 if (mask
& (1 << 15))
12199 if (mask
& (1 << 14))
12200 inst
.error
= _("LR and PC should not both be in register list");
12202 set_pred_insn_type_last ();
12207 if (mask
& (1 << 15))
12208 inst
.error
= _("PC not allowed in register list");
12211 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12213 /* Single register transfers implemented as str/ldr. */
12216 if (inst
.instruction
& (1 << 23))
12217 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12219 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12223 if (inst
.instruction
& (1 << 23))
12224 inst
.instruction
= 0x00800000; /* ia -> [base] */
12226 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12229 inst
.instruction
|= 0xf8400000;
12231 inst
.instruction
|= 0x00100000;
12233 mask
= ffs (mask
) - 1;
12236 else if (writeback
)
12237 inst
.instruction
|= WRITE_BACK
;
12239 inst
.instruction
|= mask
;
12241 inst
.instruction
|= base
<< 16;
12247 /* This really doesn't seem worth it. */
12248 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12249 _("expression too complex"));
12250 constraint (inst
.operands
[1].writeback
,
12251 _("Thumb load/store multiple does not support {reglist}^"));
12253 if (unified_syntax
)
12255 bfd_boolean narrow
;
12259 /* See if we can use a 16-bit instruction. */
12260 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12261 && inst
.size_req
!= 4
12262 && !(inst
.operands
[1].imm
& ~0xff))
12264 mask
= 1 << inst
.operands
[0].reg
;
12266 if (inst
.operands
[0].reg
<= 7)
12268 if (inst
.instruction
== T_MNEM_stmia
12269 ? inst
.operands
[0].writeback
12270 : (inst
.operands
[0].writeback
12271 == !(inst
.operands
[1].imm
& mask
)))
12273 if (inst
.instruction
== T_MNEM_stmia
12274 && (inst
.operands
[1].imm
& mask
)
12275 && (inst
.operands
[1].imm
& (mask
- 1)))
12276 as_warn (_("value stored for r%d is UNKNOWN"),
12277 inst
.operands
[0].reg
);
12279 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12280 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12281 inst
.instruction
|= inst
.operands
[1].imm
;
12284 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12286 /* This means 1 register in reg list one of 3 situations:
12287 1. Instruction is stmia, but without writeback.
12288 2. lmdia without writeback, but with Rn not in
12290 3. ldmia with writeback, but with Rn in reglist.
12291 Case 3 is UNPREDICTABLE behaviour, so we handle
12292 case 1 and 2 which can be converted into a 16-bit
12293 str or ldr. The SP cases are handled below. */
12294 unsigned long opcode
;
12295 /* First, record an error for Case 3. */
12296 if (inst
.operands
[1].imm
& mask
12297 && inst
.operands
[0].writeback
)
12299 _("having the base register in the register list when "
12300 "using write back is UNPREDICTABLE");
12302 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12304 inst
.instruction
= THUMB_OP16 (opcode
);
12305 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12306 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12310 else if (inst
.operands
[0] .reg
== REG_SP
)
12312 if (inst
.operands
[0].writeback
)
12315 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12316 ? T_MNEM_push
: T_MNEM_pop
);
12317 inst
.instruction
|= inst
.operands
[1].imm
;
12320 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12323 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12324 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12325 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12333 if (inst
.instruction
< 0xffff)
12334 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12336 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
12337 inst
.operands
[1].imm
,
12338 inst
.operands
[0].writeback
);
12343 constraint (inst
.operands
[0].reg
> 7
12344 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12345 constraint (inst
.instruction
!= T_MNEM_ldmia
12346 && inst
.instruction
!= T_MNEM_stmia
,
12347 _("Thumb-2 instruction only valid in unified syntax"));
12348 if (inst
.instruction
== T_MNEM_stmia
)
12350 if (!inst
.operands
[0].writeback
)
12351 as_warn (_("this instruction will write back the base register"));
12352 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12353 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12354 as_warn (_("value stored for r%d is UNKNOWN"),
12355 inst
.operands
[0].reg
);
12359 if (!inst
.operands
[0].writeback
12360 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12361 as_warn (_("this instruction will write back the base register"));
12362 else if (inst
.operands
[0].writeback
12363 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12364 as_warn (_("this instruction will not write back the base register"));
12367 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12368 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12369 inst
.instruction
|= inst
.operands
[1].imm
;
12376 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12377 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12378 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12379 || inst
.operands
[1].negative
,
12382 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12384 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12385 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12386 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12392 if (!inst
.operands
[1].present
)
12394 constraint (inst
.operands
[0].reg
== REG_LR
,
12395 _("r14 not allowed as first register "
12396 "when second register is omitted"));
12397 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12399 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12402 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12403 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12404 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12410 unsigned long opcode
;
12413 if (inst
.operands
[0].isreg
12414 && !inst
.operands
[0].preind
12415 && inst
.operands
[0].reg
== REG_PC
)
12416 set_pred_insn_type_last ();
12418 opcode
= inst
.instruction
;
12419 if (unified_syntax
)
12421 if (!inst
.operands
[1].isreg
)
12423 if (opcode
<= 0xffff)
12424 inst
.instruction
= THUMB_OP32 (opcode
);
12425 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12428 if (inst
.operands
[1].isreg
12429 && !inst
.operands
[1].writeback
12430 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12431 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12432 && opcode
<= 0xffff
12433 && inst
.size_req
!= 4)
12435 /* Insn may have a 16-bit form. */
12436 Rn
= inst
.operands
[1].reg
;
12437 if (inst
.operands
[1].immisreg
)
12439 inst
.instruction
= THUMB_OP16 (opcode
);
12441 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12443 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12444 reject_bad_reg (inst
.operands
[1].imm
);
12446 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12447 && opcode
!= T_MNEM_ldrsb
)
12448 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12449 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12456 if (inst
.relocs
[0].pc_rel
)
12457 opcode
= T_MNEM_ldr_pc2
;
12459 opcode
= T_MNEM_ldr_pc
;
12463 if (opcode
== T_MNEM_ldr
)
12464 opcode
= T_MNEM_ldr_sp
;
12466 opcode
= T_MNEM_str_sp
;
12468 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12472 inst
.instruction
= inst
.operands
[0].reg
;
12473 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12475 inst
.instruction
|= THUMB_OP16 (opcode
);
12476 if (inst
.size_req
== 2)
12477 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12479 inst
.relax
= opcode
;
12483 /* Definitely a 32-bit variant. */
12485 /* Warning for Erratum 752419. */
12486 if (opcode
== T_MNEM_ldr
12487 && inst
.operands
[0].reg
== REG_SP
12488 && inst
.operands
[1].writeback
== 1
12489 && !inst
.operands
[1].immisreg
)
12491 if (no_cpu_selected ()
12492 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12493 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12494 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12495 as_warn (_("This instruction may be unpredictable "
12496 "if executed on M-profile cores "
12497 "with interrupts enabled."));
12500 /* Do some validations regarding addressing modes. */
12501 if (inst
.operands
[1].immisreg
)
12502 reject_bad_reg (inst
.operands
[1].imm
);
12504 constraint (inst
.operands
[1].writeback
== 1
12505 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12508 inst
.instruction
= THUMB_OP32 (opcode
);
12509 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12510 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12511 check_ldr_r15_aligned ();
12515 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12517 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12519 /* Only [Rn,Rm] is acceptable. */
12520 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12521 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12522 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12523 || inst
.operands
[1].negative
,
12524 _("Thumb does not support this addressing mode"));
12525 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12529 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12530 if (!inst
.operands
[1].isreg
)
12531 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12534 constraint (!inst
.operands
[1].preind
12535 || inst
.operands
[1].shifted
12536 || inst
.operands
[1].writeback
,
12537 _("Thumb does not support this addressing mode"));
12538 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12540 constraint (inst
.instruction
& 0x0600,
12541 _("byte or halfword not valid for base register"));
12542 constraint (inst
.operands
[1].reg
== REG_PC
12543 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12544 _("r15 based store not allowed"));
12545 constraint (inst
.operands
[1].immisreg
,
12546 _("invalid base register for register offset"));
12548 if (inst
.operands
[1].reg
== REG_PC
)
12549 inst
.instruction
= T_OPCODE_LDR_PC
;
12550 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12551 inst
.instruction
= T_OPCODE_LDR_SP
;
12553 inst
.instruction
= T_OPCODE_STR_SP
;
12555 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12556 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12560 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12561 if (!inst
.operands
[1].immisreg
)
12563 /* Immediate offset. */
12564 inst
.instruction
|= inst
.operands
[0].reg
;
12565 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12566 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12570 /* Register offset. */
12571 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12572 constraint (inst
.operands
[1].negative
,
12573 _("Thumb does not support this addressing mode"));
12576 switch (inst
.instruction
)
12578 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12579 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12580 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12581 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12582 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12583 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12584 case 0x5600 /* ldrsb */:
12585 case 0x5e00 /* ldrsh */: break;
12589 inst
.instruction
|= inst
.operands
[0].reg
;
12590 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12591 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12597 if (!inst
.operands
[1].present
)
12599 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12600 constraint (inst
.operands
[0].reg
== REG_LR
,
12601 _("r14 not allowed here"));
12602 constraint (inst
.operands
[0].reg
== REG_R12
,
12603 _("r12 not allowed here"));
12606 if (inst
.operands
[2].writeback
12607 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12608 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12609 as_warn (_("base register written back, and overlaps "
12610 "one of transfer registers"));
12612 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12613 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12614 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12620 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12621 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12627 unsigned Rd
, Rn
, Rm
, Ra
;
12629 Rd
= inst
.operands
[0].reg
;
12630 Rn
= inst
.operands
[1].reg
;
12631 Rm
= inst
.operands
[2].reg
;
12632 Ra
= inst
.operands
[3].reg
;
12634 reject_bad_reg (Rd
);
12635 reject_bad_reg (Rn
);
12636 reject_bad_reg (Rm
);
12637 reject_bad_reg (Ra
);
12639 inst
.instruction
|= Rd
<< 8;
12640 inst
.instruction
|= Rn
<< 16;
12641 inst
.instruction
|= Rm
;
12642 inst
.instruction
|= Ra
<< 12;
12648 unsigned RdLo
, RdHi
, Rn
, Rm
;
12650 RdLo
= inst
.operands
[0].reg
;
12651 RdHi
= inst
.operands
[1].reg
;
12652 Rn
= inst
.operands
[2].reg
;
12653 Rm
= inst
.operands
[3].reg
;
12655 reject_bad_reg (RdLo
);
12656 reject_bad_reg (RdHi
);
12657 reject_bad_reg (Rn
);
12658 reject_bad_reg (Rm
);
12660 inst
.instruction
|= RdLo
<< 12;
12661 inst
.instruction
|= RdHi
<< 8;
12662 inst
.instruction
|= Rn
<< 16;
12663 inst
.instruction
|= Rm
;
12667 do_t_mov_cmp (void)
12671 Rn
= inst
.operands
[0].reg
;
12672 Rm
= inst
.operands
[1].reg
;
12675 set_pred_insn_type_last ();
12677 if (unified_syntax
)
12679 int r0off
= (inst
.instruction
== T_MNEM_mov
12680 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12681 unsigned long opcode
;
12682 bfd_boolean narrow
;
12683 bfd_boolean low_regs
;
12685 low_regs
= (Rn
<= 7 && Rm
<= 7);
12686 opcode
= inst
.instruction
;
12687 if (in_pred_block ())
12688 narrow
= opcode
!= T_MNEM_movs
;
12690 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12691 if (inst
.size_req
== 4
12692 || inst
.operands
[1].shifted
)
12695 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12696 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12697 && !inst
.operands
[1].shifted
12701 inst
.instruction
= T2_SUBS_PC_LR
;
12705 if (opcode
== T_MNEM_cmp
)
12707 constraint (Rn
== REG_PC
, BAD_PC
);
12710 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12712 warn_deprecated_sp (Rm
);
12713 /* R15 was documented as a valid choice for Rm in ARMv6,
12714 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12715 tools reject R15, so we do too. */
12716 constraint (Rm
== REG_PC
, BAD_PC
);
12719 reject_bad_reg (Rm
);
12721 else if (opcode
== T_MNEM_mov
12722 || opcode
== T_MNEM_movs
)
12724 if (inst
.operands
[1].isreg
)
12726 if (opcode
== T_MNEM_movs
)
12728 reject_bad_reg (Rn
);
12729 reject_bad_reg (Rm
);
12733 /* This is mov.n. */
12734 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
12735 && (Rm
== REG_SP
|| Rm
== REG_PC
))
12737 as_tsktsk (_("Use of r%u as a source register is "
12738 "deprecated when r%u is the destination "
12739 "register."), Rm
, Rn
);
12744 /* This is mov.w. */
12745 constraint (Rn
== REG_PC
, BAD_PC
);
12746 constraint (Rm
== REG_PC
, BAD_PC
);
12747 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12748 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12752 reject_bad_reg (Rn
);
12755 if (!inst
.operands
[1].isreg
)
12757 /* Immediate operand. */
12758 if (!in_pred_block () && opcode
== T_MNEM_mov
)
12760 if (low_regs
&& narrow
)
12762 inst
.instruction
= THUMB_OP16 (opcode
);
12763 inst
.instruction
|= Rn
<< 8;
12764 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12765 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12767 if (inst
.size_req
== 2)
12768 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12770 inst
.relax
= opcode
;
12775 constraint ((inst
.relocs
[0].type
12776 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
12777 && (inst
.relocs
[0].type
12778 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
12779 THUMB1_RELOC_ONLY
);
12781 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12782 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12783 inst
.instruction
|= Rn
<< r0off
;
12784 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12787 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12788 && (inst
.instruction
== T_MNEM_mov
12789 || inst
.instruction
== T_MNEM_movs
))
12791 /* Register shifts are encoded as separate shift instructions. */
12792 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12794 if (in_pred_block ())
12799 if (inst
.size_req
== 4)
12802 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12808 switch (inst
.operands
[1].shift_kind
)
12811 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12814 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12817 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12820 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12826 inst
.instruction
= opcode
;
12829 inst
.instruction
|= Rn
;
12830 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12835 inst
.instruction
|= CONDS_BIT
;
12837 inst
.instruction
|= Rn
<< 8;
12838 inst
.instruction
|= Rm
<< 16;
12839 inst
.instruction
|= inst
.operands
[1].imm
;
12844 /* Some mov with immediate shift have narrow variants.
12845 Register shifts are handled above. */
12846 if (low_regs
&& inst
.operands
[1].shifted
12847 && (inst
.instruction
== T_MNEM_mov
12848 || inst
.instruction
== T_MNEM_movs
))
12850 if (in_pred_block ())
12851 narrow
= (inst
.instruction
== T_MNEM_mov
);
12853 narrow
= (inst
.instruction
== T_MNEM_movs
);
12858 switch (inst
.operands
[1].shift_kind
)
12860 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12861 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12862 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12863 default: narrow
= FALSE
; break;
12869 inst
.instruction
|= Rn
;
12870 inst
.instruction
|= Rm
<< 3;
12871 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12875 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12876 inst
.instruction
|= Rn
<< r0off
;
12877 encode_thumb32_shifted_operand (1);
12881 switch (inst
.instruction
)
12884 /* In v4t or v5t a move of two lowregs produces unpredictable
12885 results. Don't allow this. */
12888 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12889 "MOV Rd, Rs with two low registers is not "
12890 "permitted on this architecture");
12891 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12895 inst
.instruction
= T_OPCODE_MOV_HR
;
12896 inst
.instruction
|= (Rn
& 0x8) << 4;
12897 inst
.instruction
|= (Rn
& 0x7);
12898 inst
.instruction
|= Rm
<< 3;
12902 /* We know we have low registers at this point.
12903 Generate LSLS Rd, Rs, #0. */
12904 inst
.instruction
= T_OPCODE_LSL_I
;
12905 inst
.instruction
|= Rn
;
12906 inst
.instruction
|= Rm
<< 3;
12912 inst
.instruction
= T_OPCODE_CMP_LR
;
12913 inst
.instruction
|= Rn
;
12914 inst
.instruction
|= Rm
<< 3;
12918 inst
.instruction
= T_OPCODE_CMP_HR
;
12919 inst
.instruction
|= (Rn
& 0x8) << 4;
12920 inst
.instruction
|= (Rn
& 0x7);
12921 inst
.instruction
|= Rm
<< 3;
12928 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12930 /* PR 10443: Do not silently ignore shifted operands. */
12931 constraint (inst
.operands
[1].shifted
,
12932 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12934 if (inst
.operands
[1].isreg
)
12936 if (Rn
< 8 && Rm
< 8)
12938 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12939 since a MOV instruction produces unpredictable results. */
12940 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12941 inst
.instruction
= T_OPCODE_ADD_I3
;
12943 inst
.instruction
= T_OPCODE_CMP_LR
;
12945 inst
.instruction
|= Rn
;
12946 inst
.instruction
|= Rm
<< 3;
12950 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12951 inst
.instruction
= T_OPCODE_MOV_HR
;
12953 inst
.instruction
= T_OPCODE_CMP_HR
;
12959 constraint (Rn
> 7,
12960 _("only lo regs allowed with immediate"));
12961 inst
.instruction
|= Rn
<< 8;
12962 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12973 top
= (inst
.instruction
& 0x00800000) != 0;
12974 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
12976 constraint (top
, _(":lower16: not allowed in this instruction"));
12977 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
12979 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
12981 constraint (!top
, _(":upper16: not allowed in this instruction"));
12982 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
12985 Rd
= inst
.operands
[0].reg
;
12986 reject_bad_reg (Rd
);
12988 inst
.instruction
|= Rd
<< 8;
12989 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
12991 imm
= inst
.relocs
[0].exp
.X_add_number
;
12992 inst
.instruction
|= (imm
& 0xf000) << 4;
12993 inst
.instruction
|= (imm
& 0x0800) << 15;
12994 inst
.instruction
|= (imm
& 0x0700) << 4;
12995 inst
.instruction
|= (imm
& 0x00ff);
13000 do_t_mvn_tst (void)
13004 Rn
= inst
.operands
[0].reg
;
13005 Rm
= inst
.operands
[1].reg
;
13007 if (inst
.instruction
== T_MNEM_cmp
13008 || inst
.instruction
== T_MNEM_cmn
)
13009 constraint (Rn
== REG_PC
, BAD_PC
);
13011 reject_bad_reg (Rn
);
13012 reject_bad_reg (Rm
);
13014 if (unified_syntax
)
13016 int r0off
= (inst
.instruction
== T_MNEM_mvn
13017 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
13018 bfd_boolean narrow
;
13020 if (inst
.size_req
== 4
13021 || inst
.instruction
> 0xffff
13022 || inst
.operands
[1].shifted
13023 || Rn
> 7 || Rm
> 7)
13025 else if (inst
.instruction
== T_MNEM_cmn
13026 || inst
.instruction
== T_MNEM_tst
)
13028 else if (THUMB_SETS_FLAGS (inst
.instruction
))
13029 narrow
= !in_pred_block ();
13031 narrow
= in_pred_block ();
13033 if (!inst
.operands
[1].isreg
)
13035 /* For an immediate, we always generate a 32-bit opcode;
13036 section relaxation will shrink it later if possible. */
13037 if (inst
.instruction
< 0xffff)
13038 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13039 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13040 inst
.instruction
|= Rn
<< r0off
;
13041 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13045 /* See if we can do this with a 16-bit instruction. */
13048 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13049 inst
.instruction
|= Rn
;
13050 inst
.instruction
|= Rm
<< 3;
13054 constraint (inst
.operands
[1].shifted
13055 && inst
.operands
[1].immisreg
,
13056 _("shift must be constant"));
13057 if (inst
.instruction
< 0xffff)
13058 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13059 inst
.instruction
|= Rn
<< r0off
;
13060 encode_thumb32_shifted_operand (1);
13066 constraint (inst
.instruction
> 0xffff
13067 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
13068 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
13069 _("unshifted register required"));
13070 constraint (Rn
> 7 || Rm
> 7,
13073 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13074 inst
.instruction
|= Rn
;
13075 inst
.instruction
|= Rm
<< 3;
13084 if (do_vfp_nsyn_mrs () == SUCCESS
)
13087 Rd
= inst
.operands
[0].reg
;
13088 reject_bad_reg (Rd
);
13089 inst
.instruction
|= Rd
<< 8;
13091 if (inst
.operands
[1].isreg
)
13093 unsigned br
= inst
.operands
[1].reg
;
13094 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
13095 as_bad (_("bad register for mrs"));
13097 inst
.instruction
|= br
& (0xf << 16);
13098 inst
.instruction
|= (br
& 0x300) >> 4;
13099 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
13103 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13105 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13107 /* PR gas/12698: The constraint is only applied for m_profile.
13108 If the user has specified -march=all, we want to ignore it as
13109 we are building for any CPU type, including non-m variants. */
13110 bfd_boolean m_profile
=
13111 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13112 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
13113 "not support requested special purpose register"));
13116 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13118 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
13119 _("'APSR', 'CPSR' or 'SPSR' expected"));
13121 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13122 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
13123 inst
.instruction
|= 0xf0000;
13133 if (do_vfp_nsyn_msr () == SUCCESS
)
13136 constraint (!inst
.operands
[1].isreg
,
13137 _("Thumb encoding does not support an immediate here"));
13139 if (inst
.operands
[0].isreg
)
13140 flags
= (int)(inst
.operands
[0].reg
);
13142 flags
= inst
.operands
[0].imm
;
13144 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13146 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13148 /* PR gas/12698: The constraint is only applied for m_profile.
13149 If the user has specified -march=all, we want to ignore it as
13150 we are building for any CPU type, including non-m variants. */
13151 bfd_boolean m_profile
=
13152 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13153 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13154 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13155 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13156 && bits
!= PSR_f
)) && m_profile
,
13157 _("selected processor does not support requested special "
13158 "purpose register"));
13161 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13162 "requested special purpose register"));
13164 Rn
= inst
.operands
[1].reg
;
13165 reject_bad_reg (Rn
);
13167 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13168 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13169 inst
.instruction
|= (flags
& 0x300) >> 4;
13170 inst
.instruction
|= (flags
& 0xff);
13171 inst
.instruction
|= Rn
<< 16;
13177 bfd_boolean narrow
;
13178 unsigned Rd
, Rn
, Rm
;
13180 if (!inst
.operands
[2].present
)
13181 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13183 Rd
= inst
.operands
[0].reg
;
13184 Rn
= inst
.operands
[1].reg
;
13185 Rm
= inst
.operands
[2].reg
;
13187 if (unified_syntax
)
13189 if (inst
.size_req
== 4
13195 else if (inst
.instruction
== T_MNEM_muls
)
13196 narrow
= !in_pred_block ();
13198 narrow
= in_pred_block ();
13202 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13203 constraint (Rn
> 7 || Rm
> 7,
13210 /* 16-bit MULS/Conditional MUL. */
13211 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13212 inst
.instruction
|= Rd
;
13215 inst
.instruction
|= Rm
<< 3;
13217 inst
.instruction
|= Rn
<< 3;
13219 constraint (1, _("dest must overlap one source register"));
13223 constraint (inst
.instruction
!= T_MNEM_mul
,
13224 _("Thumb-2 MUL must not set flags"));
13226 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13227 inst
.instruction
|= Rd
<< 8;
13228 inst
.instruction
|= Rn
<< 16;
13229 inst
.instruction
|= Rm
<< 0;
13231 reject_bad_reg (Rd
);
13232 reject_bad_reg (Rn
);
13233 reject_bad_reg (Rm
);
13240 unsigned RdLo
, RdHi
, Rn
, Rm
;
13242 RdLo
= inst
.operands
[0].reg
;
13243 RdHi
= inst
.operands
[1].reg
;
13244 Rn
= inst
.operands
[2].reg
;
13245 Rm
= inst
.operands
[3].reg
;
13247 reject_bad_reg (RdLo
);
13248 reject_bad_reg (RdHi
);
13249 reject_bad_reg (Rn
);
13250 reject_bad_reg (Rm
);
13252 inst
.instruction
|= RdLo
<< 12;
13253 inst
.instruction
|= RdHi
<< 8;
13254 inst
.instruction
|= Rn
<< 16;
13255 inst
.instruction
|= Rm
;
13258 as_tsktsk (_("rdhi and rdlo must be different"));
13264 set_pred_insn_type (NEUTRAL_IT_INSN
);
13266 if (unified_syntax
)
13268 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13270 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13271 inst
.instruction
|= inst
.operands
[0].imm
;
13275 /* PR9722: Check for Thumb2 availability before
13276 generating a thumb2 nop instruction. */
13277 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13279 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13280 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13283 inst
.instruction
= 0x46c0;
13288 constraint (inst
.operands
[0].present
,
13289 _("Thumb does not support NOP with hints"));
13290 inst
.instruction
= 0x46c0;
13297 if (unified_syntax
)
13299 bfd_boolean narrow
;
13301 if (THUMB_SETS_FLAGS (inst
.instruction
))
13302 narrow
= !in_pred_block ();
13304 narrow
= in_pred_block ();
13305 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13307 if (inst
.size_req
== 4)
13312 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13313 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13314 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13318 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13319 inst
.instruction
|= inst
.operands
[0].reg
;
13320 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13325 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13327 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13329 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13330 inst
.instruction
|= inst
.operands
[0].reg
;
13331 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13340 Rd
= inst
.operands
[0].reg
;
13341 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13343 reject_bad_reg (Rd
);
13344 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13345 reject_bad_reg (Rn
);
13347 inst
.instruction
|= Rd
<< 8;
13348 inst
.instruction
|= Rn
<< 16;
13350 if (!inst
.operands
[2].isreg
)
13352 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13353 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13359 Rm
= inst
.operands
[2].reg
;
13360 reject_bad_reg (Rm
);
13362 constraint (inst
.operands
[2].shifted
13363 && inst
.operands
[2].immisreg
,
13364 _("shift must be constant"));
13365 encode_thumb32_shifted_operand (2);
13372 unsigned Rd
, Rn
, Rm
;
13374 Rd
= inst
.operands
[0].reg
;
13375 Rn
= inst
.operands
[1].reg
;
13376 Rm
= inst
.operands
[2].reg
;
13378 reject_bad_reg (Rd
);
13379 reject_bad_reg (Rn
);
13380 reject_bad_reg (Rm
);
13382 inst
.instruction
|= Rd
<< 8;
13383 inst
.instruction
|= Rn
<< 16;
13384 inst
.instruction
|= Rm
;
13385 if (inst
.operands
[3].present
)
13387 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13388 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13389 _("expression too complex"));
13390 inst
.instruction
|= (val
& 0x1c) << 10;
13391 inst
.instruction
|= (val
& 0x03) << 6;
13398 if (!inst
.operands
[3].present
)
13402 inst
.instruction
&= ~0x00000020;
13404 /* PR 10168. Swap the Rm and Rn registers. */
13405 Rtmp
= inst
.operands
[1].reg
;
13406 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13407 inst
.operands
[2].reg
= Rtmp
;
13415 if (inst
.operands
[0].immisreg
)
13416 reject_bad_reg (inst
.operands
[0].imm
);
13418 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
13422 do_t_push_pop (void)
13426 constraint (inst
.operands
[0].writeback
,
13427 _("push/pop do not support {reglist}^"));
13428 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13429 _("expression too complex"));
13431 mask
= inst
.operands
[0].imm
;
13432 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13433 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13434 else if (inst
.size_req
!= 4
13435 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13436 ? REG_LR
: REG_PC
)))
13438 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13439 inst
.instruction
|= THUMB_PP_PC_LR
;
13440 inst
.instruction
|= mask
& 0xff;
13442 else if (unified_syntax
)
13444 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13445 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13449 inst
.error
= _("invalid register list to push/pop instruction");
13457 if (unified_syntax
)
13458 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13461 inst
.error
= _("invalid register list to push/pop instruction");
13467 do_t_vscclrm (void)
13469 if (inst
.operands
[0].issingle
)
13471 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13472 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13473 inst
.instruction
|= inst
.operands
[0].imm
;
13477 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13478 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13479 inst
.instruction
|= 1 << 8;
13480 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13489 Rd
= inst
.operands
[0].reg
;
13490 Rm
= inst
.operands
[1].reg
;
13492 reject_bad_reg (Rd
);
13493 reject_bad_reg (Rm
);
13495 inst
.instruction
|= Rd
<< 8;
13496 inst
.instruction
|= Rm
<< 16;
13497 inst
.instruction
|= Rm
;
13505 Rd
= inst
.operands
[0].reg
;
13506 Rm
= inst
.operands
[1].reg
;
13508 reject_bad_reg (Rd
);
13509 reject_bad_reg (Rm
);
13511 if (Rd
<= 7 && Rm
<= 7
13512 && inst
.size_req
!= 4)
13514 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13515 inst
.instruction
|= Rd
;
13516 inst
.instruction
|= Rm
<< 3;
13518 else if (unified_syntax
)
13520 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13521 inst
.instruction
|= Rd
<< 8;
13522 inst
.instruction
|= Rm
<< 16;
13523 inst
.instruction
|= Rm
;
13526 inst
.error
= BAD_HIREG
;
13534 Rd
= inst
.operands
[0].reg
;
13535 Rm
= inst
.operands
[1].reg
;
13537 reject_bad_reg (Rd
);
13538 reject_bad_reg (Rm
);
13540 inst
.instruction
|= Rd
<< 8;
13541 inst
.instruction
|= Rm
;
13549 Rd
= inst
.operands
[0].reg
;
13550 Rs
= (inst
.operands
[1].present
13551 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13552 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13554 reject_bad_reg (Rd
);
13555 reject_bad_reg (Rs
);
13556 if (inst
.operands
[2].isreg
)
13557 reject_bad_reg (inst
.operands
[2].reg
);
13559 inst
.instruction
|= Rd
<< 8;
13560 inst
.instruction
|= Rs
<< 16;
13561 if (!inst
.operands
[2].isreg
)
13563 bfd_boolean narrow
;
13565 if ((inst
.instruction
& 0x00100000) != 0)
13566 narrow
= !in_pred_block ();
13568 narrow
= in_pred_block ();
13570 if (Rd
> 7 || Rs
> 7)
13573 if (inst
.size_req
== 4 || !unified_syntax
)
13576 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13577 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13580 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13581 relaxation, but it doesn't seem worth the hassle. */
13584 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13585 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13586 inst
.instruction
|= Rs
<< 3;
13587 inst
.instruction
|= Rd
;
13591 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13592 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13596 encode_thumb32_shifted_operand (2);
13602 if (warn_on_deprecated
13603 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13604 as_tsktsk (_("setend use is deprecated for ARMv8"));
13606 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13607 if (inst
.operands
[0].imm
)
13608 inst
.instruction
|= 0x8;
13614 if (!inst
.operands
[1].present
)
13615 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13617 if (unified_syntax
)
13619 bfd_boolean narrow
;
13622 switch (inst
.instruction
)
13625 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13627 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13629 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13631 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13635 if (THUMB_SETS_FLAGS (inst
.instruction
))
13636 narrow
= !in_pred_block ();
13638 narrow
= in_pred_block ();
13639 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13641 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13643 if (inst
.operands
[2].isreg
13644 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13645 || inst
.operands
[2].reg
> 7))
13647 if (inst
.size_req
== 4)
13650 reject_bad_reg (inst
.operands
[0].reg
);
13651 reject_bad_reg (inst
.operands
[1].reg
);
13655 if (inst
.operands
[2].isreg
)
13657 reject_bad_reg (inst
.operands
[2].reg
);
13658 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13659 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13660 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13661 inst
.instruction
|= inst
.operands
[2].reg
;
13663 /* PR 12854: Error on extraneous shifts. */
13664 constraint (inst
.operands
[2].shifted
,
13665 _("extraneous shift as part of operand to shift insn"));
13669 inst
.operands
[1].shifted
= 1;
13670 inst
.operands
[1].shift_kind
= shift_kind
;
13671 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13672 ? T_MNEM_movs
: T_MNEM_mov
);
13673 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13674 encode_thumb32_shifted_operand (1);
13675 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13676 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13681 if (inst
.operands
[2].isreg
)
13683 switch (shift_kind
)
13685 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13686 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13687 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13688 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13692 inst
.instruction
|= inst
.operands
[0].reg
;
13693 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13695 /* PR 12854: Error on extraneous shifts. */
13696 constraint (inst
.operands
[2].shifted
,
13697 _("extraneous shift as part of operand to shift insn"));
13701 switch (shift_kind
)
13703 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13704 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13705 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13708 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13709 inst
.instruction
|= inst
.operands
[0].reg
;
13710 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13716 constraint (inst
.operands
[0].reg
> 7
13717 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
13718 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13720 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
13722 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
13723 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13724 _("source1 and dest must be same register"));
13726 switch (inst
.instruction
)
13728 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13729 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13730 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13731 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13735 inst
.instruction
|= inst
.operands
[0].reg
;
13736 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13738 /* PR 12854: Error on extraneous shifts. */
13739 constraint (inst
.operands
[2].shifted
,
13740 _("extraneous shift as part of operand to shift insn"));
13744 switch (inst
.instruction
)
13746 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13747 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13748 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13749 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
13752 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13753 inst
.instruction
|= inst
.operands
[0].reg
;
13754 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13762 unsigned Rd
, Rn
, Rm
;
13764 Rd
= inst
.operands
[0].reg
;
13765 Rn
= inst
.operands
[1].reg
;
13766 Rm
= inst
.operands
[2].reg
;
13768 reject_bad_reg (Rd
);
13769 reject_bad_reg (Rn
);
13770 reject_bad_reg (Rm
);
13772 inst
.instruction
|= Rd
<< 8;
13773 inst
.instruction
|= Rn
<< 16;
13774 inst
.instruction
|= Rm
;
13780 unsigned Rd
, Rn
, Rm
;
13782 Rd
= inst
.operands
[0].reg
;
13783 Rm
= inst
.operands
[1].reg
;
13784 Rn
= inst
.operands
[2].reg
;
13786 reject_bad_reg (Rd
);
13787 reject_bad_reg (Rn
);
13788 reject_bad_reg (Rm
);
13790 inst
.instruction
|= Rd
<< 8;
13791 inst
.instruction
|= Rn
<< 16;
13792 inst
.instruction
|= Rm
;
13798 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13799 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13800 _("SMC is not permitted on this architecture"));
13801 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13802 _("expression too complex"));
13803 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13804 inst
.instruction
|= (value
& 0xf000) >> 12;
13805 inst
.instruction
|= (value
& 0x0ff0);
13806 inst
.instruction
|= (value
& 0x000f) << 16;
13807 /* PR gas/15623: SMC instructions must be last in an IT block. */
13808 set_pred_insn_type_last ();
13814 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13816 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13817 inst
.instruction
|= (value
& 0x0fff);
13818 inst
.instruction
|= (value
& 0xf000) << 4;
13822 do_t_ssat_usat (int bias
)
13826 Rd
= inst
.operands
[0].reg
;
13827 Rn
= inst
.operands
[2].reg
;
13829 reject_bad_reg (Rd
);
13830 reject_bad_reg (Rn
);
13832 inst
.instruction
|= Rd
<< 8;
13833 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
13834 inst
.instruction
|= Rn
<< 16;
13836 if (inst
.operands
[3].present
)
13838 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
13840 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13842 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13843 _("expression too complex"));
13845 if (shift_amount
!= 0)
13847 constraint (shift_amount
> 31,
13848 _("shift expression is too large"));
13850 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13851 inst
.instruction
|= 0x00200000; /* sh bit. */
13853 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13854 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13862 do_t_ssat_usat (1);
13870 Rd
= inst
.operands
[0].reg
;
13871 Rn
= inst
.operands
[2].reg
;
13873 reject_bad_reg (Rd
);
13874 reject_bad_reg (Rn
);
13876 inst
.instruction
|= Rd
<< 8;
13877 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13878 inst
.instruction
|= Rn
<< 16;
13884 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13885 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13886 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13887 || inst
.operands
[2].negative
,
13890 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13892 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13893 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13894 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13895 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13901 if (!inst
.operands
[2].present
)
13902 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13904 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13905 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13906 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13909 inst
.instruction
|= inst
.operands
[0].reg
;
13910 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13911 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13912 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13918 unsigned Rd
, Rn
, Rm
;
13920 Rd
= inst
.operands
[0].reg
;
13921 Rn
= inst
.operands
[1].reg
;
13922 Rm
= inst
.operands
[2].reg
;
13924 reject_bad_reg (Rd
);
13925 reject_bad_reg (Rn
);
13926 reject_bad_reg (Rm
);
13928 inst
.instruction
|= Rd
<< 8;
13929 inst
.instruction
|= Rn
<< 16;
13930 inst
.instruction
|= Rm
;
13931 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13939 Rd
= inst
.operands
[0].reg
;
13940 Rm
= inst
.operands
[1].reg
;
13942 reject_bad_reg (Rd
);
13943 reject_bad_reg (Rm
);
13945 if (inst
.instruction
<= 0xffff
13946 && inst
.size_req
!= 4
13947 && Rd
<= 7 && Rm
<= 7
13948 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13950 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13951 inst
.instruction
|= Rd
;
13952 inst
.instruction
|= Rm
<< 3;
13954 else if (unified_syntax
)
13956 if (inst
.instruction
<= 0xffff)
13957 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13958 inst
.instruction
|= Rd
<< 8;
13959 inst
.instruction
|= Rm
;
13960 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13964 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13965 _("Thumb encoding does not support rotation"));
13966 constraint (1, BAD_HIREG
);
13973 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
13982 half
= (inst
.instruction
& 0x10) != 0;
13983 set_pred_insn_type_last ();
13984 constraint (inst
.operands
[0].immisreg
,
13985 _("instruction requires register index"));
13987 Rn
= inst
.operands
[0].reg
;
13988 Rm
= inst
.operands
[0].imm
;
13990 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13991 constraint (Rn
== REG_SP
, BAD_SP
);
13992 reject_bad_reg (Rm
);
13994 constraint (!half
&& inst
.operands
[0].shifted
,
13995 _("instruction does not allow shifted index"));
13996 inst
.instruction
|= (Rn
<< 16) | Rm
;
14002 if (!inst
.operands
[0].present
)
14003 inst
.operands
[0].imm
= 0;
14005 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
14007 constraint (inst
.size_req
== 2,
14008 _("immediate value out of range"));
14009 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14010 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
14011 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
14015 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14016 inst
.instruction
|= inst
.operands
[0].imm
;
14019 set_pred_insn_type (NEUTRAL_IT_INSN
);
14026 do_t_ssat_usat (0);
14034 Rd
= inst
.operands
[0].reg
;
14035 Rn
= inst
.operands
[2].reg
;
14037 reject_bad_reg (Rd
);
14038 reject_bad_reg (Rn
);
14040 inst
.instruction
|= Rd
<< 8;
14041 inst
.instruction
|= inst
.operands
[1].imm
;
14042 inst
.instruction
|= Rn
<< 16;
14045 /* Checking the range of the branch offset (VAL) with NBITS bits
14046 and IS_SIGNED signedness. Also checks the LSB to be 0. */
14048 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
14050 gas_assert (nbits
> 0 && nbits
<= 32);
14053 int cmp
= (1 << (nbits
- 1));
14054 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
14059 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
14065 /* For branches in Armv8.1-M Mainline. */
14067 do_t_branch_future (void)
14069 unsigned long insn
= inst
.instruction
;
14071 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14072 if (inst
.operands
[0].hasreloc
== 0)
14074 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
14075 as_bad (BAD_BRANCH_OFF
);
14077 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
14081 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
14082 inst
.relocs
[0].pc_rel
= 1;
14088 if (inst
.operands
[1].hasreloc
== 0)
14090 int val
= inst
.operands
[1].imm
;
14091 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
14092 as_bad (BAD_BRANCH_OFF
);
14094 int immA
= (val
& 0x0001f000) >> 12;
14095 int immB
= (val
& 0x00000ffc) >> 2;
14096 int immC
= (val
& 0x00000002) >> 1;
14097 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14101 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
14102 inst
.relocs
[1].pc_rel
= 1;
14107 if (inst
.operands
[1].hasreloc
== 0)
14109 int val
= inst
.operands
[1].imm
;
14110 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
14111 as_bad (BAD_BRANCH_OFF
);
14113 int immA
= (val
& 0x0007f000) >> 12;
14114 int immB
= (val
& 0x00000ffc) >> 2;
14115 int immC
= (val
& 0x00000002) >> 1;
14116 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14120 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
14121 inst
.relocs
[1].pc_rel
= 1;
14125 case T_MNEM_bfcsel
:
14127 if (inst
.operands
[1].hasreloc
== 0)
14129 int val
= inst
.operands
[1].imm
;
14130 int immA
= (val
& 0x00001000) >> 12;
14131 int immB
= (val
& 0x00000ffc) >> 2;
14132 int immC
= (val
& 0x00000002) >> 1;
14133 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14137 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
14138 inst
.relocs
[1].pc_rel
= 1;
14142 if (inst
.operands
[2].hasreloc
== 0)
14144 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
14145 int val2
= inst
.operands
[2].imm
;
14146 int val0
= inst
.operands
[0].imm
& 0x1f;
14147 int diff
= val2
- val0
;
14149 inst
.instruction
|= 1 << 17; /* T bit. */
14150 else if (diff
!= 2)
14151 as_bad (_("out of range label-relative fixup value"));
14155 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14156 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14157 inst
.relocs
[2].pc_rel
= 1;
14161 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14162 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14167 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14174 /* Helper function for do_t_loloop to handle relocations. */
14176 v8_1_loop_reloc (int is_le
)
14178 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14180 int value
= inst
.relocs
[0].exp
.X_add_number
;
14181 value
= (is_le
) ? -value
: value
;
14183 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
14184 as_bad (BAD_BRANCH_OFF
);
14188 immh
= (value
& 0x00000ffc) >> 2;
14189 imml
= (value
& 0x00000002) >> 1;
14191 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14195 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14196 inst
.relocs
[0].pc_rel
= 1;
14200 /* For shifts in MVE. */
14202 do_mve_scalar_shift (void)
14204 if (!inst
.operands
[2].present
)
14206 inst
.operands
[2] = inst
.operands
[1];
14207 inst
.operands
[1].reg
= 0xf;
14210 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14211 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14213 if (inst
.operands
[2].isreg
)
14215 /* Assuming Rm is already checked not to be 11x1. */
14216 constraint (inst
.operands
[2].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14217 constraint (inst
.operands
[2].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14218 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
14222 /* Assuming imm is already checked as [1,32]. */
14223 unsigned int value
= inst
.operands
[2].imm
;
14224 inst
.instruction
|= (value
& 0x1c) << 10;
14225 inst
.instruction
|= (value
& 0x03) << 6;
14226 /* Change last 4 bits from 0xd to 0xf. */
14227 inst
.instruction
|= 0x2;
14231 /* MVE instruction encoder helpers. */
14232 #define M_MNEM_vabav 0xee800f01
14233 #define M_MNEM_vmladav 0xeef00e00
14234 #define M_MNEM_vmladava 0xeef00e20
14235 #define M_MNEM_vmladavx 0xeef01e00
14236 #define M_MNEM_vmladavax 0xeef01e20
14237 #define M_MNEM_vmlsdav 0xeef00e01
14238 #define M_MNEM_vmlsdava 0xeef00e21
14239 #define M_MNEM_vmlsdavx 0xeef01e01
14240 #define M_MNEM_vmlsdavax 0xeef01e21
14241 #define M_MNEM_vmullt 0xee011e00
14242 #define M_MNEM_vmullb 0xee010e00
14243 #define M_MNEM_vst20 0xfc801e00
14244 #define M_MNEM_vst21 0xfc801e20
14245 #define M_MNEM_vst40 0xfc801e01
14246 #define M_MNEM_vst41 0xfc801e21
14247 #define M_MNEM_vst42 0xfc801e41
14248 #define M_MNEM_vst43 0xfc801e61
14249 #define M_MNEM_vld20 0xfc901e00
14250 #define M_MNEM_vld21 0xfc901e20
14251 #define M_MNEM_vld40 0xfc901e01
14252 #define M_MNEM_vld41 0xfc901e21
14253 #define M_MNEM_vld42 0xfc901e41
14254 #define M_MNEM_vld43 0xfc901e61
14255 #define M_MNEM_vstrb 0xec000e00
14256 #define M_MNEM_vstrh 0xec000e10
14257 #define M_MNEM_vstrw 0xec000e40
14258 #define M_MNEM_vstrd 0xec000e50
14259 #define M_MNEM_vldrb 0xec100e00
14260 #define M_MNEM_vldrh 0xec100e10
14261 #define M_MNEM_vldrw 0xec100e40
14262 #define M_MNEM_vldrd 0xec100e50
14263 #define M_MNEM_vmovlt 0xeea01f40
14264 #define M_MNEM_vmovlb 0xeea00f40
14265 #define M_MNEM_vmovnt 0xfe311e81
14266 #define M_MNEM_vmovnb 0xfe310e81
14267 #define M_MNEM_vadc 0xee300f00
14268 #define M_MNEM_vadci 0xee301f00
14269 #define M_MNEM_vbrsr 0xfe011e60
14270 #define M_MNEM_vaddlv 0xee890f00
14271 #define M_MNEM_vaddlva 0xee890f20
14272 #define M_MNEM_vaddv 0xeef10f00
14273 #define M_MNEM_vaddva 0xeef10f20
14274 #define M_MNEM_vddup 0xee011f6e
14275 #define M_MNEM_vdwdup 0xee011f60
14276 #define M_MNEM_vidup 0xee010f6e
14277 #define M_MNEM_viwdup 0xee010f60
14278 #define M_MNEM_vmaxv 0xeee20f00
14279 #define M_MNEM_vmaxav 0xeee00f00
14280 #define M_MNEM_vminv 0xeee20f80
14281 #define M_MNEM_vminav 0xeee00f80
14282 #define M_MNEM_vmlaldav 0xee800e00
14283 #define M_MNEM_vmlaldava 0xee800e20
14284 #define M_MNEM_vmlaldavx 0xee801e00
14285 #define M_MNEM_vmlaldavax 0xee801e20
14286 #define M_MNEM_vmlsldav 0xee800e01
14287 #define M_MNEM_vmlsldava 0xee800e21
14288 #define M_MNEM_vmlsldavx 0xee801e01
14289 #define M_MNEM_vmlsldavax 0xee801e21
14290 #define M_MNEM_vrmlaldavhx 0xee801f00
14291 #define M_MNEM_vrmlaldavhax 0xee801f20
14292 #define M_MNEM_vrmlsldavh 0xfe800e01
14293 #define M_MNEM_vrmlsldavha 0xfe800e21
14294 #define M_MNEM_vrmlsldavhx 0xfe801e01
14295 #define M_MNEM_vrmlsldavhax 0xfe801e21
14296 #define M_MNEM_vqmovnt 0xee331e01
14297 #define M_MNEM_vqmovnb 0xee330e01
14298 #define M_MNEM_vqmovunt 0xee311e81
14299 #define M_MNEM_vqmovunb 0xee310e81
14300 #define M_MNEM_vshrnt 0xee801fc1
14301 #define M_MNEM_vshrnb 0xee800fc1
14302 #define M_MNEM_vrshrnt 0xfe801fc1
14303 #define M_MNEM_vqshrnt 0xee801f40
14304 #define M_MNEM_vqshrnb 0xee800f40
14305 #define M_MNEM_vqshrunt 0xee801fc0
14306 #define M_MNEM_vqshrunb 0xee800fc0
14307 #define M_MNEM_vrshrnb 0xfe800fc1
14308 #define M_MNEM_vqrshrnt 0xee801f41
14309 #define M_MNEM_vqrshrnb 0xee800f41
14310 #define M_MNEM_vqrshrunt 0xfe801fc0
14311 #define M_MNEM_vqrshrunb 0xfe800fc0
14313 /* Neon instruction encoder helpers. */
14315 /* Encodings for the different types for various Neon opcodes. */
14317 /* An "invalid" code for the following tables. */
14320 struct neon_tab_entry
14323 unsigned float_or_poly
;
14324 unsigned scalar_or_imm
;
14327 /* Map overloaded Neon opcodes to their respective encodings. */
14328 #define NEON_ENC_TAB \
14329 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14330 X(vabdl, 0x0800700, N_INV, N_INV), \
14331 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14332 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14333 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14334 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14335 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14336 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14337 X(vaddl, 0x0800000, N_INV, N_INV), \
14338 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14339 X(vsubl, 0x0800200, N_INV, N_INV), \
14340 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14341 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14342 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14343 /* Register variants of the following two instructions are encoded as
14344 vcge / vcgt with the operands reversed. */ \
14345 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14346 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14347 X(vfma, N_INV, 0x0000c10, N_INV), \
14348 X(vfms, N_INV, 0x0200c10, N_INV), \
14349 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14350 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14351 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14352 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14353 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14354 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14355 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14356 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14357 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14358 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14359 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14360 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14361 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14362 X(vshl, 0x0000400, N_INV, 0x0800510), \
14363 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14364 X(vand, 0x0000110, N_INV, 0x0800030), \
14365 X(vbic, 0x0100110, N_INV, 0x0800030), \
14366 X(veor, 0x1000110, N_INV, N_INV), \
14367 X(vorn, 0x0300110, N_INV, 0x0800010), \
14368 X(vorr, 0x0200110, N_INV, 0x0800010), \
14369 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14370 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14371 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14372 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14373 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14374 X(vst1, 0x0000000, 0x0800000, N_INV), \
14375 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14376 X(vst2, 0x0000100, 0x0800100, N_INV), \
14377 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14378 X(vst3, 0x0000200, 0x0800200, N_INV), \
14379 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14380 X(vst4, 0x0000300, 0x0800300, N_INV), \
14381 X(vmovn, 0x1b20200, N_INV, N_INV), \
14382 X(vtrn, 0x1b20080, N_INV, N_INV), \
14383 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14384 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14385 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14386 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14387 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14388 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14389 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14390 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14391 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14392 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14393 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14394 X(vseleq, 0xe000a00, N_INV, N_INV), \
14395 X(vselvs, 0xe100a00, N_INV, N_INV), \
14396 X(vselge, 0xe200a00, N_INV, N_INV), \
14397 X(vselgt, 0xe300a00, N_INV, N_INV), \
14398 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14399 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14400 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14401 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14402 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14403 X(aes, 0x3b00300, N_INV, N_INV), \
14404 X(sha3op, 0x2000c00, N_INV, N_INV), \
14405 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14406 X(sha2op, 0x3ba0380, N_INV, N_INV)
14410 #define X(OPC,I,F,S) N_MNEM_##OPC
14415 static const struct neon_tab_entry neon_enc_tab
[] =
14417 #define X(OPC,I,F,S) { (I), (F), (S) }
14422 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14423 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14424 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14425 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14426 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14427 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14428 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14429 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14430 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14431 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14432 #define NEON_ENC_SINGLE_(X) \
14433 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14434 #define NEON_ENC_DOUBLE_(X) \
14435 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14436 #define NEON_ENC_FPV8_(X) \
14437 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14439 #define NEON_ENCODE(type, inst) \
14442 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14443 inst.is_neon = 1; \
14447 #define check_neon_suffixes \
14450 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14452 as_bad (_("invalid neon suffix for non neon instruction")); \
14458 /* Define shapes for instruction operands. The following mnemonic characters
14459 are used in this table:
14461 F - VFP S<n> register
14462 D - Neon D<n> register
14463 Q - Neon Q<n> register
14467 L - D<n> register list
14469 This table is used to generate various data:
14470 - enumerations of the form NS_DDR to be used as arguments to
14472 - a table classifying shapes into single, double, quad, mixed.
14473 - a table used to drive neon_select_shape. */
14475 #define NEON_SHAPE_DEF \
14476 X(4, (R, R, Q, Q), QUAD), \
14477 X(4, (Q, R, R, I), QUAD), \
14478 X(4, (R, R, S, S), QUAD), \
14479 X(4, (S, S, R, R), QUAD), \
14480 X(3, (Q, R, I), QUAD), \
14481 X(3, (I, Q, Q), QUAD), \
14482 X(3, (I, Q, R), QUAD), \
14483 X(3, (R, Q, Q), QUAD), \
14484 X(3, (D, D, D), DOUBLE), \
14485 X(3, (Q, Q, Q), QUAD), \
14486 X(3, (D, D, I), DOUBLE), \
14487 X(3, (Q, Q, I), QUAD), \
14488 X(3, (D, D, S), DOUBLE), \
14489 X(3, (Q, Q, S), QUAD), \
14490 X(3, (Q, Q, R), QUAD), \
14491 X(3, (R, R, Q), QUAD), \
14492 X(2, (R, Q), QUAD), \
14493 X(2, (D, D), DOUBLE), \
14494 X(2, (Q, Q), QUAD), \
14495 X(2, (D, S), DOUBLE), \
14496 X(2, (Q, S), QUAD), \
14497 X(2, (D, R), DOUBLE), \
14498 X(2, (Q, R), QUAD), \
14499 X(2, (D, I), DOUBLE), \
14500 X(2, (Q, I), QUAD), \
14501 X(3, (D, L, D), DOUBLE), \
14502 X(2, (D, Q), MIXED), \
14503 X(2, (Q, D), MIXED), \
14504 X(3, (D, Q, I), MIXED), \
14505 X(3, (Q, D, I), MIXED), \
14506 X(3, (Q, D, D), MIXED), \
14507 X(3, (D, Q, Q), MIXED), \
14508 X(3, (Q, Q, D), MIXED), \
14509 X(3, (Q, D, S), MIXED), \
14510 X(3, (D, Q, S), MIXED), \
14511 X(4, (D, D, D, I), DOUBLE), \
14512 X(4, (Q, Q, Q, I), QUAD), \
14513 X(4, (D, D, S, I), DOUBLE), \
14514 X(4, (Q, Q, S, I), QUAD), \
14515 X(2, (F, F), SINGLE), \
14516 X(3, (F, F, F), SINGLE), \
14517 X(2, (F, I), SINGLE), \
14518 X(2, (F, D), MIXED), \
14519 X(2, (D, F), MIXED), \
14520 X(3, (F, F, I), MIXED), \
14521 X(4, (R, R, F, F), SINGLE), \
14522 X(4, (F, F, R, R), SINGLE), \
14523 X(3, (D, R, R), DOUBLE), \
14524 X(3, (R, R, D), DOUBLE), \
14525 X(2, (S, R), SINGLE), \
14526 X(2, (R, S), SINGLE), \
14527 X(2, (F, R), SINGLE), \
14528 X(2, (R, F), SINGLE), \
14529 /* Used for MVE tail predicated loop instructions. */\
14530 X(2, (R, R), QUAD), \
14531 /* Half float shape supported so far. */\
14532 X (2, (H, D), MIXED), \
14533 X (2, (D, H), MIXED), \
14534 X (2, (H, F), MIXED), \
14535 X (2, (F, H), MIXED), \
14536 X (2, (H, H), HALF), \
14537 X (2, (H, R), HALF), \
14538 X (2, (R, H), HALF), \
14539 X (2, (H, I), HALF), \
14540 X (3, (H, H, H), HALF), \
14541 X (3, (H, F, I), MIXED), \
14542 X (3, (F, H, I), MIXED), \
14543 X (3, (D, H, H), MIXED), \
14544 X (3, (D, H, S), MIXED)
14546 #define S2(A,B) NS_##A##B
14547 #define S3(A,B,C) NS_##A##B##C
14548 #define S4(A,B,C,D) NS_##A##B##C##D
14550 #define X(N, L, C) S##N L
14563 enum neon_shape_class
14572 #define X(N, L, C) SC_##C
14574 static enum neon_shape_class neon_shape_class
[] =
14593 /* Register widths of above. */
14594 static unsigned neon_shape_el_size
[] =
14606 struct neon_shape_info
14609 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14612 #define S2(A,B) { SE_##A, SE_##B }
14613 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14614 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14616 #define X(N, L, C) { N, S##N L }
14618 static struct neon_shape_info neon_shape_tab
[] =
14628 /* Bit masks used in type checking given instructions.
14629 'N_EQK' means the type must be the same as (or based on in some way) the key
14630 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14631 set, various other bits can be set as well in order to modify the meaning of
14632 the type constraint. */
14634 enum neon_type_mask
14658 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14659 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14660 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14661 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
14662 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
14663 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
14664 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14665 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14666 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14667 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
14668 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
14670 N_MAX_NONSPECIAL
= N_P64
14673 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14675 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14676 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14677 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
14678 #define N_S_32 (N_S8 | N_S16 | N_S32)
14679 #define N_F_16_32 (N_F16 | N_F32)
14680 #define N_SUF_32 (N_SU_32 | N_F_16_32)
14681 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
14682 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
14683 #define N_F_ALL (N_F16 | N_F32 | N_F64)
14684 #define N_I_MVE (N_I8 | N_I16 | N_I32)
14685 #define N_F_MVE (N_F16 | N_F32)
14686 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14688 /* Pass this as the first type argument to neon_check_type to ignore types
14690 #define N_IGNORE_TYPE (N_KEY | N_EQK)
14692 /* Select a "shape" for the current instruction (describing register types or
14693 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14694 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14695 function of operand parsing, so this function doesn't need to be called.
14696 Shapes should be listed in order of decreasing length. */
14698 static enum neon_shape
14699 neon_select_shape (enum neon_shape shape
, ...)
14702 enum neon_shape first_shape
= shape
;
14704 /* Fix missing optional operands. FIXME: we don't know at this point how
14705 many arguments we should have, so this makes the assumption that we have
14706 > 1. This is true of all current Neon opcodes, I think, but may not be
14707 true in the future. */
14708 if (!inst
.operands
[1].present
)
14709 inst
.operands
[1] = inst
.operands
[0];
14711 va_start (ap
, shape
);
14713 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
14718 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
14720 if (!inst
.operands
[j
].present
)
14726 switch (neon_shape_tab
[shape
].el
[j
])
14728 /* If a .f16, .16, .u16, .s16 type specifier is given over
14729 a VFP single precision register operand, it's essentially
14730 means only half of the register is used.
14732 If the type specifier is given after the mnemonics, the
14733 information is stored in inst.vectype. If the type specifier
14734 is given after register operand, the information is stored
14735 in inst.operands[].vectype.
14737 When there is only one type specifier, and all the register
14738 operands are the same type of hardware register, the type
14739 specifier applies to all register operands.
14741 If no type specifier is given, the shape is inferred from
14742 operand information.
14745 vadd.f16 s0, s1, s2: NS_HHH
14746 vabs.f16 s0, s1: NS_HH
14747 vmov.f16 s0, r1: NS_HR
14748 vmov.f16 r0, s1: NS_RH
14749 vcvt.f16 r0, s1: NS_RH
14750 vcvt.f16.s32 s2, s2, #29: NS_HFI
14751 vcvt.f16.s32 s2, s2: NS_HF
14754 if (!(inst
.operands
[j
].isreg
14755 && inst
.operands
[j
].isvec
14756 && inst
.operands
[j
].issingle
14757 && !inst
.operands
[j
].isquad
14758 && ((inst
.vectype
.elems
== 1
14759 && inst
.vectype
.el
[0].size
== 16)
14760 || (inst
.vectype
.elems
> 1
14761 && inst
.vectype
.el
[j
].size
== 16)
14762 || (inst
.vectype
.elems
== 0
14763 && inst
.operands
[j
].vectype
.type
!= NT_invtype
14764 && inst
.operands
[j
].vectype
.size
== 16))))
14769 if (!(inst
.operands
[j
].isreg
14770 && inst
.operands
[j
].isvec
14771 && inst
.operands
[j
].issingle
14772 && !inst
.operands
[j
].isquad
14773 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
14774 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
14775 || (inst
.vectype
.elems
== 0
14776 && (inst
.operands
[j
].vectype
.size
== 32
14777 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
14782 if (!(inst
.operands
[j
].isreg
14783 && inst
.operands
[j
].isvec
14784 && !inst
.operands
[j
].isquad
14785 && !inst
.operands
[j
].issingle
))
14790 if (!(inst
.operands
[j
].isreg
14791 && !inst
.operands
[j
].isvec
))
14796 if (!(inst
.operands
[j
].isreg
14797 && inst
.operands
[j
].isvec
14798 && inst
.operands
[j
].isquad
14799 && !inst
.operands
[j
].issingle
))
14804 if (!(!inst
.operands
[j
].isreg
14805 && !inst
.operands
[j
].isscalar
))
14810 if (!(!inst
.operands
[j
].isreg
14811 && inst
.operands
[j
].isscalar
))
14821 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
14822 /* We've matched all the entries in the shape table, and we don't
14823 have any left over operands which have not been matched. */
14829 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
14830 first_error (_("invalid instruction shape"));
14835 /* True if SHAPE is predominantly a quadword operation (most of the time, this
14836 means the Q bit should be set). */
14839 neon_quad (enum neon_shape shape
)
14841 return neon_shape_class
[shape
] == SC_QUAD
;
14845 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
14848 /* Allow modification to be made to types which are constrained to be
14849 based on the key element, based on bits set alongside N_EQK. */
14850 if ((typebits
& N_EQK
) != 0)
14852 if ((typebits
& N_HLF
) != 0)
14854 else if ((typebits
& N_DBL
) != 0)
14856 if ((typebits
& N_SGN
) != 0)
14857 *g_type
= NT_signed
;
14858 else if ((typebits
& N_UNS
) != 0)
14859 *g_type
= NT_unsigned
;
14860 else if ((typebits
& N_INT
) != 0)
14861 *g_type
= NT_integer
;
14862 else if ((typebits
& N_FLT
) != 0)
14863 *g_type
= NT_float
;
14864 else if ((typebits
& N_SIZ
) != 0)
14865 *g_type
= NT_untyped
;
14869 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
14870 operand type, i.e. the single type specified in a Neon instruction when it
14871 is the only one given. */
14873 static struct neon_type_el
14874 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
14876 struct neon_type_el dest
= *key
;
14878 gas_assert ((thisarg
& N_EQK
) != 0);
14880 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
14885 /* Convert Neon type and size into compact bitmask representation. */
14887 static enum neon_type_mask
14888 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
14895 case 8: return N_8
;
14896 case 16: return N_16
;
14897 case 32: return N_32
;
14898 case 64: return N_64
;
14906 case 8: return N_I8
;
14907 case 16: return N_I16
;
14908 case 32: return N_I32
;
14909 case 64: return N_I64
;
14917 case 16: return N_F16
;
14918 case 32: return N_F32
;
14919 case 64: return N_F64
;
14927 case 8: return N_P8
;
14928 case 16: return N_P16
;
14929 case 64: return N_P64
;
14937 case 8: return N_S8
;
14938 case 16: return N_S16
;
14939 case 32: return N_S32
;
14940 case 64: return N_S64
;
14948 case 8: return N_U8
;
14949 case 16: return N_U16
;
14950 case 32: return N_U32
;
14951 case 64: return N_U64
;
14962 /* Convert compact Neon bitmask type representation to a type and size. Only
14963 handles the case where a single bit is set in the mask. */
14966 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
14967 enum neon_type_mask mask
)
14969 if ((mask
& N_EQK
) != 0)
14972 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
14974 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
14976 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
14978 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
14983 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
14985 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
14986 *type
= NT_unsigned
;
14987 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
14988 *type
= NT_integer
;
14989 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
14990 *type
= NT_untyped
;
14991 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
14993 else if ((mask
& (N_F_ALL
)) != 0)
15001 /* Modify a bitmask of allowed types. This is only needed for type
15005 modify_types_allowed (unsigned allowed
, unsigned mods
)
15008 enum neon_el_type type
;
15014 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
15016 if (el_type_of_type_chk (&type
, &size
,
15017 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
15019 neon_modify_type_size (mods
, &type
, &size
);
15020 destmask
|= type_chk_of_el_type (type
, size
);
15027 /* Check type and return type classification.
15028 The manual states (paraphrase): If one datatype is given, it indicates the
15030 - the second operand, if there is one
15031 - the operand, if there is no second operand
15032 - the result, if there are no operands.
15033 This isn't quite good enough though, so we use a concept of a "key" datatype
15034 which is set on a per-instruction basis, which is the one which matters when
15035 only one data type is written.
15036 Note: this function has side-effects (e.g. filling in missing operands). All
15037 Neon instructions should call it before performing bit encoding. */
15039 static struct neon_type_el
15040 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
15043 unsigned i
, pass
, key_el
= 0;
15044 unsigned types
[NEON_MAX_TYPE_ELS
];
15045 enum neon_el_type k_type
= NT_invtype
;
15046 unsigned k_size
= -1u;
15047 struct neon_type_el badtype
= {NT_invtype
, -1};
15048 unsigned key_allowed
= 0;
15050 /* Optional registers in Neon instructions are always (not) in operand 1.
15051 Fill in the missing operand here, if it was omitted. */
15052 if (els
> 1 && !inst
.operands
[1].present
)
15053 inst
.operands
[1] = inst
.operands
[0];
15055 /* Suck up all the varargs. */
15057 for (i
= 0; i
< els
; i
++)
15059 unsigned thisarg
= va_arg (ap
, unsigned);
15060 if (thisarg
== N_IGNORE_TYPE
)
15065 types
[i
] = thisarg
;
15066 if ((thisarg
& N_KEY
) != 0)
15071 if (inst
.vectype
.elems
> 0)
15072 for (i
= 0; i
< els
; i
++)
15073 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
15075 first_error (_("types specified in both the mnemonic and operands"));
15079 /* Duplicate inst.vectype elements here as necessary.
15080 FIXME: No idea if this is exactly the same as the ARM assembler,
15081 particularly when an insn takes one register and one non-register
15083 if (inst
.vectype
.elems
== 1 && els
> 1)
15086 inst
.vectype
.elems
= els
;
15087 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
15088 for (j
= 0; j
< els
; j
++)
15090 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15093 else if (inst
.vectype
.elems
== 0 && els
> 0)
15096 /* No types were given after the mnemonic, so look for types specified
15097 after each operand. We allow some flexibility here; as long as the
15098 "key" operand has a type, we can infer the others. */
15099 for (j
= 0; j
< els
; j
++)
15100 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
15101 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
15103 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
15105 for (j
= 0; j
< els
; j
++)
15106 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
15107 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15112 first_error (_("operand types can't be inferred"));
15116 else if (inst
.vectype
.elems
!= els
)
15118 first_error (_("type specifier has the wrong number of parts"));
15122 for (pass
= 0; pass
< 2; pass
++)
15124 for (i
= 0; i
< els
; i
++)
15126 unsigned thisarg
= types
[i
];
15127 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
15128 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
15129 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
15130 unsigned g_size
= inst
.vectype
.el
[i
].size
;
15132 /* Decay more-specific signed & unsigned types to sign-insensitive
15133 integer types if sign-specific variants are unavailable. */
15134 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
15135 && (types_allowed
& N_SU_ALL
) == 0)
15136 g_type
= NT_integer
;
15138 /* If only untyped args are allowed, decay any more specific types to
15139 them. Some instructions only care about signs for some element
15140 sizes, so handle that properly. */
15141 if (((types_allowed
& N_UNT
) == 0)
15142 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
15143 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
15144 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
15145 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
15146 g_type
= NT_untyped
;
15150 if ((thisarg
& N_KEY
) != 0)
15154 key_allowed
= thisarg
& ~N_KEY
;
15156 /* Check architecture constraint on FP16 extension. */
15158 && k_type
== NT_float
15159 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15161 inst
.error
= _(BAD_FP16
);
15168 if ((thisarg
& N_VFP
) != 0)
15170 enum neon_shape_el regshape
;
15171 unsigned regwidth
, match
;
15173 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15176 first_error (_("invalid instruction shape"));
15179 regshape
= neon_shape_tab
[ns
].el
[i
];
15180 regwidth
= neon_shape_el_size
[regshape
];
15182 /* In VFP mode, operands must match register widths. If we
15183 have a key operand, use its width, else use the width of
15184 the current operand. */
15190 /* FP16 will use a single precision register. */
15191 if (regwidth
== 32 && match
== 16)
15193 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15197 inst
.error
= _(BAD_FP16
);
15202 if (regwidth
!= match
)
15204 first_error (_("operand size must match register width"));
15209 if ((thisarg
& N_EQK
) == 0)
15211 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15213 if ((given_type
& types_allowed
) == 0)
15215 first_error (BAD_SIMD_TYPE
);
15221 enum neon_el_type mod_k_type
= k_type
;
15222 unsigned mod_k_size
= k_size
;
15223 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15224 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15226 first_error (_("inconsistent types in Neon instruction"));
15234 return inst
.vectype
.el
[key_el
];
15237 /* Neon-style VFP instruction forwarding. */
15239 /* Thumb VFP instructions have 0xE in the condition field. */
15242 do_vfp_cond_or_thumb (void)
15247 inst
.instruction
|= 0xe0000000;
15249 inst
.instruction
|= inst
.cond
<< 28;
15252 /* Look up and encode a simple mnemonic, for use as a helper function for the
15253 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15254 etc. It is assumed that operand parsing has already been done, and that the
15255 operands are in the form expected by the given opcode (this isn't necessarily
15256 the same as the form in which they were parsed, hence some massaging must
15257 take place before this function is called).
15258 Checks current arch version against that in the looked-up opcode. */
15261 do_vfp_nsyn_opcode (const char *opname
)
15263 const struct asm_opcode
*opcode
;
15265 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
15270 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15271 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15278 inst
.instruction
= opcode
->tvalue
;
15279 opcode
->tencode ();
15283 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15284 opcode
->aencode ();
15289 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15291 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15293 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15296 do_vfp_nsyn_opcode ("fadds");
15298 do_vfp_nsyn_opcode ("fsubs");
15300 /* ARMv8.2 fp16 instruction. */
15302 do_scalar_fp16_v82_encode ();
15307 do_vfp_nsyn_opcode ("faddd");
15309 do_vfp_nsyn_opcode ("fsubd");
15313 /* Check operand types to see if this is a VFP instruction, and if so call
15317 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15319 enum neon_shape rs
;
15320 struct neon_type_el et
;
15325 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15326 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15330 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15331 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15332 N_F_ALL
| N_KEY
| N_VFP
);
15339 if (et
.type
!= NT_invtype
)
15350 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15352 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15354 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15357 do_vfp_nsyn_opcode ("fmacs");
15359 do_vfp_nsyn_opcode ("fnmacs");
15361 /* ARMv8.2 fp16 instruction. */
15363 do_scalar_fp16_v82_encode ();
15368 do_vfp_nsyn_opcode ("fmacd");
15370 do_vfp_nsyn_opcode ("fnmacd");
15375 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15377 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15379 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15382 do_vfp_nsyn_opcode ("ffmas");
15384 do_vfp_nsyn_opcode ("ffnmas");
15386 /* ARMv8.2 fp16 instruction. */
15388 do_scalar_fp16_v82_encode ();
15393 do_vfp_nsyn_opcode ("ffmad");
15395 do_vfp_nsyn_opcode ("ffnmad");
15400 do_vfp_nsyn_mul (enum neon_shape rs
)
15402 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15404 do_vfp_nsyn_opcode ("fmuls");
15406 /* ARMv8.2 fp16 instruction. */
15408 do_scalar_fp16_v82_encode ();
15411 do_vfp_nsyn_opcode ("fmuld");
15415 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15417 int is_neg
= (inst
.instruction
& 0x80) != 0;
15418 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15420 if (rs
== NS_FF
|| rs
== NS_HH
)
15423 do_vfp_nsyn_opcode ("fnegs");
15425 do_vfp_nsyn_opcode ("fabss");
15427 /* ARMv8.2 fp16 instruction. */
15429 do_scalar_fp16_v82_encode ();
15434 do_vfp_nsyn_opcode ("fnegd");
15436 do_vfp_nsyn_opcode ("fabsd");
15440 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15441 insns belong to Neon, and are handled elsewhere. */
15444 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15446 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15450 do_vfp_nsyn_opcode ("fldmdbs");
15452 do_vfp_nsyn_opcode ("fldmias");
15457 do_vfp_nsyn_opcode ("fstmdbs");
15459 do_vfp_nsyn_opcode ("fstmias");
15464 do_vfp_nsyn_sqrt (void)
15466 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15467 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15469 if (rs
== NS_FF
|| rs
== NS_HH
)
15471 do_vfp_nsyn_opcode ("fsqrts");
15473 /* ARMv8.2 fp16 instruction. */
15475 do_scalar_fp16_v82_encode ();
15478 do_vfp_nsyn_opcode ("fsqrtd");
15482 do_vfp_nsyn_div (void)
15484 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15485 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15486 N_F_ALL
| N_KEY
| N_VFP
);
15488 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15490 do_vfp_nsyn_opcode ("fdivs");
15492 /* ARMv8.2 fp16 instruction. */
15494 do_scalar_fp16_v82_encode ();
15497 do_vfp_nsyn_opcode ("fdivd");
15501 do_vfp_nsyn_nmul (void)
15503 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15504 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15505 N_F_ALL
| N_KEY
| N_VFP
);
15507 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15509 NEON_ENCODE (SINGLE
, inst
);
15510 do_vfp_sp_dyadic ();
15512 /* ARMv8.2 fp16 instruction. */
15514 do_scalar_fp16_v82_encode ();
15518 NEON_ENCODE (DOUBLE
, inst
);
15519 do_vfp_dp_rd_rn_rm ();
15521 do_vfp_cond_or_thumb ();
15525 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15529 neon_logbits (unsigned x
)
15531 return ffs (x
) - 4;
15534 #define LOW4(R) ((R) & 0xf)
15535 #define HI1(R) (((R) >> 4) & 1)
15538 mve_get_vcmp_vpt_cond (struct neon_type_el et
)
15543 first_error (BAD_EL_TYPE
);
15546 switch (inst
.operands
[0].imm
)
15549 first_error (_("invalid condition"));
15571 /* only accept eq and ne. */
15572 if (inst
.operands
[0].imm
> 1)
15574 first_error (_("invalid condition"));
15577 return inst
.operands
[0].imm
;
15579 if (inst
.operands
[0].imm
== 0x2)
15581 else if (inst
.operands
[0].imm
== 0x8)
15585 first_error (_("invalid condition"));
15589 switch (inst
.operands
[0].imm
)
15592 first_error (_("invalid condition"));
15608 /* Should be unreachable. */
15615 /* We are dealing with a vector predicated block. */
15616 if (inst
.operands
[0].present
)
15618 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15619 struct neon_type_el et
15620 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15623 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15625 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15627 if (et
.type
== NT_invtype
)
15630 if (et
.type
== NT_float
)
15632 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15634 constraint (et
.size
!= 16 && et
.size
!= 32, BAD_EL_TYPE
);
15635 inst
.instruction
|= (et
.size
== 16) << 28;
15636 inst
.instruction
|= 0x3 << 20;
15640 constraint (et
.size
!= 8 && et
.size
!= 16 && et
.size
!= 32,
15642 inst
.instruction
|= 1 << 28;
15643 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15646 if (inst
.operands
[2].isquad
)
15648 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15649 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15650 inst
.instruction
|= (fcond
& 0x2) >> 1;
15654 if (inst
.operands
[2].reg
== REG_SP
)
15655 as_tsktsk (MVE_BAD_SP
);
15656 inst
.instruction
|= 1 << 6;
15657 inst
.instruction
|= (fcond
& 0x2) << 4;
15658 inst
.instruction
|= inst
.operands
[2].reg
;
15660 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15661 inst
.instruction
|= (fcond
& 0x4) << 10;
15662 inst
.instruction
|= (fcond
& 0x1) << 7;
15665 set_pred_insn_type (VPT_INSN
);
15667 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
15668 | ((inst
.instruction
& 0xe000) >> 13);
15669 now_pred
.warn_deprecated
= FALSE
;
15670 now_pred
.type
= VECTOR_PRED
;
15677 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
15678 if (!inst
.operands
[1].isreg
|| !inst
.operands
[1].isquad
)
15679 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
15680 if (!inst
.operands
[2].present
)
15681 first_error (_("MVE vector or ARM register expected"));
15682 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15684 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
15685 if ((inst
.instruction
& 0xffffffff) == N_MNEM_vcmpe
15686 && inst
.operands
[1].isquad
)
15688 inst
.instruction
= N_MNEM_vcmp
;
15692 if (inst
.cond
> COND_ALWAYS
)
15693 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15695 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15697 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15698 struct neon_type_el et
15699 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15702 constraint (rs
== NS_IQR
&& inst
.operands
[2].reg
== REG_PC
15703 && !inst
.operands
[2].iszr
, BAD_PC
);
15705 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15707 inst
.instruction
= 0xee010f00;
15708 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15709 inst
.instruction
|= (fcond
& 0x4) << 10;
15710 inst
.instruction
|= (fcond
& 0x1) << 7;
15711 if (et
.type
== NT_float
)
15713 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15715 inst
.instruction
|= (et
.size
== 16) << 28;
15716 inst
.instruction
|= 0x3 << 20;
15720 inst
.instruction
|= 1 << 28;
15721 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15723 if (inst
.operands
[2].isquad
)
15725 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15726 inst
.instruction
|= (fcond
& 0x2) >> 1;
15727 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15731 if (inst
.operands
[2].reg
== REG_SP
)
15732 as_tsktsk (MVE_BAD_SP
);
15733 inst
.instruction
|= 1 << 6;
15734 inst
.instruction
|= (fcond
& 0x2) << 4;
15735 inst
.instruction
|= inst
.operands
[2].reg
;
15743 do_mve_vmaxa_vmina (void)
15745 if (inst
.cond
> COND_ALWAYS
)
15746 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15748 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15750 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
15751 struct neon_type_el et
15752 = neon_check_type (2, rs
, N_EQK
, N_KEY
| N_S8
| N_S16
| N_S32
);
15754 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15755 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15756 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15757 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15758 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15763 do_mve_vfmas (void)
15765 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
15766 struct neon_type_el et
15767 = neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
, N_EQK
);
15769 if (inst
.cond
> COND_ALWAYS
)
15770 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15772 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15774 if (inst
.operands
[2].reg
== REG_SP
)
15775 as_tsktsk (MVE_BAD_SP
);
15776 else if (inst
.operands
[2].reg
== REG_PC
)
15777 as_tsktsk (MVE_BAD_PC
);
15779 inst
.instruction
|= (et
.size
== 16) << 28;
15780 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15781 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15782 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15783 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15784 inst
.instruction
|= inst
.operands
[2].reg
;
15789 do_mve_viddup (void)
15791 if (inst
.cond
> COND_ALWAYS
)
15792 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15794 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15796 unsigned imm
= inst
.relocs
[0].exp
.X_add_number
;
15797 constraint (imm
!= 1 && imm
!= 2 && imm
!= 4 && imm
!= 8,
15798 _("immediate must be either 1, 2, 4 or 8"));
15800 enum neon_shape rs
;
15801 struct neon_type_el et
;
15803 if (inst
.instruction
== M_MNEM_vddup
|| inst
.instruction
== M_MNEM_vidup
)
15805 rs
= neon_select_shape (NS_QRI
, NS_NULL
);
15806 et
= neon_check_type (2, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
);
15811 constraint ((inst
.operands
[2].reg
% 2) != 1, BAD_EVEN
);
15812 if (inst
.operands
[2].reg
== REG_SP
)
15813 as_tsktsk (MVE_BAD_SP
);
15814 else if (inst
.operands
[2].reg
== REG_PC
)
15815 first_error (BAD_PC
);
15817 rs
= neon_select_shape (NS_QRRI
, NS_NULL
);
15818 et
= neon_check_type (3, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
, N_EQK
);
15819 Rm
= inst
.operands
[2].reg
>> 1;
15821 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15822 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15823 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15824 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15825 inst
.instruction
|= (imm
> 2) << 7;
15826 inst
.instruction
|= Rm
<< 1;
15827 inst
.instruction
|= (imm
== 2 || imm
== 8);
15832 do_mve_vmlas (void)
15834 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
15835 struct neon_type_el et
15836 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
15838 if (inst
.operands
[2].reg
== REG_PC
)
15839 as_tsktsk (MVE_BAD_PC
);
15840 else if (inst
.operands
[2].reg
== REG_SP
)
15841 as_tsktsk (MVE_BAD_SP
);
15843 if (inst
.cond
> COND_ALWAYS
)
15844 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15846 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15848 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
15849 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15850 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15851 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15852 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15853 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15854 inst
.instruction
|= inst
.operands
[2].reg
;
15859 do_mve_vshll (void)
15861 struct neon_type_el et
15862 = neon_check_type (2, NS_QQI
, N_EQK
, N_S8
| N_U8
| N_S16
| N_U16
| N_KEY
);
15864 if (inst
.cond
> COND_ALWAYS
)
15865 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15867 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15869 int imm
= inst
.operands
[2].imm
;
15870 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15871 _("immediate value out of range"));
15873 if ((unsigned)imm
== et
.size
)
15875 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15876 inst
.instruction
|= 0x110001;
15880 inst
.instruction
|= (et
.size
+ imm
) << 16;
15881 inst
.instruction
|= 0x800140;
15884 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
15885 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15886 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15887 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15888 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15893 do_mve_vshlc (void)
15895 if (inst
.cond
> COND_ALWAYS
)
15896 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15898 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15900 if (inst
.operands
[1].reg
== REG_PC
)
15901 as_tsktsk (MVE_BAD_PC
);
15902 else if (inst
.operands
[1].reg
== REG_SP
)
15903 as_tsktsk (MVE_BAD_SP
);
15905 int imm
= inst
.operands
[2].imm
;
15906 constraint (imm
< 1 || imm
> 32, _("immediate value out of range"));
15908 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15909 inst
.instruction
|= (imm
& 0x1f) << 16;
15910 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15911 inst
.instruction
|= inst
.operands
[1].reg
;
15916 do_mve_vshrn (void)
15919 switch (inst
.instruction
)
15921 case M_MNEM_vshrnt
:
15922 case M_MNEM_vshrnb
:
15923 case M_MNEM_vrshrnt
:
15924 case M_MNEM_vrshrnb
:
15925 types
= N_I16
| N_I32
;
15927 case M_MNEM_vqshrnt
:
15928 case M_MNEM_vqshrnb
:
15929 case M_MNEM_vqrshrnt
:
15930 case M_MNEM_vqrshrnb
:
15931 types
= N_U16
| N_U32
| N_S16
| N_S32
;
15933 case M_MNEM_vqshrunt
:
15934 case M_MNEM_vqshrunb
:
15935 case M_MNEM_vqrshrunt
:
15936 case M_MNEM_vqrshrunb
:
15937 types
= N_S16
| N_S32
;
15943 struct neon_type_el et
= neon_check_type (2, NS_QQI
, N_EQK
, types
| N_KEY
);
15945 if (inst
.cond
> COND_ALWAYS
)
15946 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15948 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15950 unsigned Qd
= inst
.operands
[0].reg
;
15951 unsigned Qm
= inst
.operands
[1].reg
;
15952 unsigned imm
= inst
.operands
[2].imm
;
15953 constraint (imm
< 1 || ((unsigned) imm
) > (et
.size
/ 2),
15955 ? _("immediate operand expected in the range [1,8]")
15956 : _("immediate operand expected in the range [1,16]"));
15958 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
15959 inst
.instruction
|= HI1 (Qd
) << 22;
15960 inst
.instruction
|= (et
.size
- imm
) << 16;
15961 inst
.instruction
|= LOW4 (Qd
) << 12;
15962 inst
.instruction
|= HI1 (Qm
) << 5;
15963 inst
.instruction
|= LOW4 (Qm
);
15968 do_mve_vqmovn (void)
15970 struct neon_type_el et
;
15971 if (inst
.instruction
== M_MNEM_vqmovnt
15972 || inst
.instruction
== M_MNEM_vqmovnb
)
15973 et
= neon_check_type (2, NS_QQ
, N_EQK
,
15974 N_U16
| N_U32
| N_S16
| N_S32
| N_KEY
);
15976 et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15978 if (inst
.cond
> COND_ALWAYS
)
15979 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15981 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15983 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
15984 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15985 inst
.instruction
|= (et
.size
== 32) << 18;
15986 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15987 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15988 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15993 do_mve_vpsel (void)
15995 neon_select_shape (NS_QQQ
, NS_NULL
);
15997 if (inst
.cond
> COND_ALWAYS
)
15998 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16000 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16002 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16003 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16004 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16005 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16006 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16007 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16012 do_mve_vpnot (void)
16014 if (inst
.cond
> COND_ALWAYS
)
16015 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16017 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16021 do_mve_vmaxnma_vminnma (void)
16023 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16024 struct neon_type_el et
16025 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
16027 if (inst
.cond
> COND_ALWAYS
)
16028 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16030 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16032 inst
.instruction
|= (et
.size
== 16) << 28;
16033 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16034 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16035 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16036 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16041 do_mve_vcmul (void)
16043 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
16044 struct neon_type_el et
16045 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F_MVE
| N_KEY
);
16047 if (inst
.cond
> COND_ALWAYS
)
16048 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16050 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16052 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
16053 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
16054 _("immediate out of range"));
16056 if (et
.size
== 32 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
16057 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
16058 as_tsktsk (BAD_MVE_SRCDEST
);
16060 inst
.instruction
|= (et
.size
== 32) << 28;
16061 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16062 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16063 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16064 inst
.instruction
|= (rot
> 90) << 12;
16065 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16066 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16067 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16068 inst
.instruction
|= (rot
== 90 || rot
== 270);
16072 /* To handle the Low Overhead Loop instructions
16073 in Armv8.1-M Mainline and MVE. */
16077 unsigned long insn
= inst
.instruction
;
16079 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
16081 if (insn
== T_MNEM_lctp
)
16084 set_pred_insn_type (MVE_OUTSIDE_PRED_INSN
);
16086 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16088 struct neon_type_el et
16089 = neon_check_type (2, NS_RR
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16090 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16097 constraint (!inst
.operands
[0].present
,
16099 /* fall through. */
16102 if (!inst
.operands
[0].present
)
16103 inst
.instruction
|= 1 << 21;
16105 v8_1_loop_reloc (TRUE
);
16110 v8_1_loop_reloc (FALSE
);
16111 /* fall through. */
16114 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
16116 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16117 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16118 else if (inst
.operands
[1].reg
== REG_PC
)
16119 as_tsktsk (MVE_BAD_PC
);
16120 if (inst
.operands
[1].reg
== REG_SP
)
16121 as_tsktsk (MVE_BAD_SP
);
16123 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
16133 do_vfp_nsyn_cmp (void)
16135 enum neon_shape rs
;
16136 if (!inst
.operands
[0].isreg
)
16143 constraint (inst
.operands
[2].present
, BAD_SYNTAX
);
16144 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
16148 if (inst
.operands
[1].isreg
)
16150 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
16151 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
16153 if (rs
== NS_FF
|| rs
== NS_HH
)
16155 NEON_ENCODE (SINGLE
, inst
);
16156 do_vfp_sp_monadic ();
16160 NEON_ENCODE (DOUBLE
, inst
);
16161 do_vfp_dp_rd_rm ();
16166 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
16167 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
16169 switch (inst
.instruction
& 0x0fffffff)
16172 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
16175 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
16181 if (rs
== NS_FI
|| rs
== NS_HI
)
16183 NEON_ENCODE (SINGLE
, inst
);
16184 do_vfp_sp_compare_z ();
16188 NEON_ENCODE (DOUBLE
, inst
);
16192 do_vfp_cond_or_thumb ();
16194 /* ARMv8.2 fp16 instruction. */
16195 if (rs
== NS_HI
|| rs
== NS_HH
)
16196 do_scalar_fp16_v82_encode ();
16200 nsyn_insert_sp (void)
16202 inst
.operands
[1] = inst
.operands
[0];
16203 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
16204 inst
.operands
[0].reg
= REG_SP
;
16205 inst
.operands
[0].isreg
= 1;
16206 inst
.operands
[0].writeback
= 1;
16207 inst
.operands
[0].present
= 1;
16211 do_vfp_nsyn_push (void)
16215 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16216 _("register list must contain at least 1 and at most 16 "
16219 if (inst
.operands
[1].issingle
)
16220 do_vfp_nsyn_opcode ("fstmdbs");
16222 do_vfp_nsyn_opcode ("fstmdbd");
16226 do_vfp_nsyn_pop (void)
16230 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16231 _("register list must contain at least 1 and at most 16 "
16234 if (inst
.operands
[1].issingle
)
16235 do_vfp_nsyn_opcode ("fldmias");
16237 do_vfp_nsyn_opcode ("fldmiad");
16240 /* Fix up Neon data-processing instructions, ORing in the correct bits for
16241 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16244 neon_dp_fixup (struct arm_it
* insn
)
16246 unsigned int i
= insn
->instruction
;
16251 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16262 insn
->instruction
= i
;
16266 mve_encode_qqr (int size
, int U
, int fp
)
16268 if (inst
.operands
[2].reg
== REG_SP
)
16269 as_tsktsk (MVE_BAD_SP
);
16270 else if (inst
.operands
[2].reg
== REG_PC
)
16271 as_tsktsk (MVE_BAD_PC
);
16276 if (((unsigned)inst
.instruction
) == 0xd00)
16277 inst
.instruction
= 0xee300f40;
16279 else if (((unsigned)inst
.instruction
) == 0x200d00)
16280 inst
.instruction
= 0xee301f40;
16282 else if (((unsigned)inst
.instruction
) == 0x1000d10)
16283 inst
.instruction
= 0xee310e60;
16285 /* Setting size which is 1 for F16 and 0 for F32. */
16286 inst
.instruction
|= (size
== 16) << 28;
16291 if (((unsigned)inst
.instruction
) == 0x800)
16292 inst
.instruction
= 0xee010f40;
16294 else if (((unsigned)inst
.instruction
) == 0x1000800)
16295 inst
.instruction
= 0xee011f40;
16297 else if (((unsigned)inst
.instruction
) == 0)
16298 inst
.instruction
= 0xee000f40;
16300 else if (((unsigned)inst
.instruction
) == 0x200)
16301 inst
.instruction
= 0xee001f40;
16303 else if (((unsigned)inst
.instruction
) == 0x900)
16304 inst
.instruction
= 0xee010e40;
16306 else if (((unsigned)inst
.instruction
) == 0x910)
16307 inst
.instruction
= 0xee011e60;
16309 else if (((unsigned)inst
.instruction
) == 0x10)
16310 inst
.instruction
= 0xee000f60;
16312 else if (((unsigned)inst
.instruction
) == 0x210)
16313 inst
.instruction
= 0xee001f60;
16315 else if (((unsigned)inst
.instruction
) == 0x3000b10)
16316 inst
.instruction
= 0xee000e40;
16318 else if (((unsigned)inst
.instruction
) == 0x0000b00)
16319 inst
.instruction
= 0xee010e60;
16321 else if (((unsigned)inst
.instruction
) == 0x1000b00)
16322 inst
.instruction
= 0xfe010e60;
16325 inst
.instruction
|= U
<< 28;
16327 /* Setting bits for size. */
16328 inst
.instruction
|= neon_logbits (size
) << 20;
16330 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16331 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16332 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16333 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16334 inst
.instruction
|= inst
.operands
[2].reg
;
16339 mve_encode_rqq (unsigned bit28
, unsigned size
)
16341 inst
.instruction
|= bit28
<< 28;
16342 inst
.instruction
|= neon_logbits (size
) << 20;
16343 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16344 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16345 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16346 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16347 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16352 mve_encode_qqq (int ubit
, int size
)
16355 inst
.instruction
|= (ubit
!= 0) << 28;
16356 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16357 inst
.instruction
|= neon_logbits (size
) << 20;
16358 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16359 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16360 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16361 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16362 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16368 mve_encode_rq (unsigned bit28
, unsigned size
)
16370 inst
.instruction
|= bit28
<< 28;
16371 inst
.instruction
|= neon_logbits (size
) << 18;
16372 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16373 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16378 mve_encode_rrqq (unsigned U
, unsigned size
)
16380 constraint (inst
.operands
[3].reg
> 14, MVE_BAD_QREG
);
16382 inst
.instruction
|= U
<< 28;
16383 inst
.instruction
|= (inst
.operands
[1].reg
>> 1) << 20;
16384 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
) << 16;
16385 inst
.instruction
|= (size
== 32) << 16;
16386 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16387 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 7;
16388 inst
.instruction
|= inst
.operands
[3].reg
;
16392 /* Encode insns with bit pattern:
16394 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16395 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16397 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16398 different meaning for some instruction. */
16401 neon_three_same (int isquad
, int ubit
, int size
)
16403 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16404 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16405 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16406 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16407 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16408 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16409 inst
.instruction
|= (isquad
!= 0) << 6;
16410 inst
.instruction
|= (ubit
!= 0) << 24;
16412 inst
.instruction
|= neon_logbits (size
) << 20;
16414 neon_dp_fixup (&inst
);
16417 /* Encode instructions of the form:
16419 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16420 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
16422 Don't write size if SIZE == -1. */
16425 neon_two_same (int qbit
, int ubit
, int size
)
16427 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16428 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16429 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16430 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16431 inst
.instruction
|= (qbit
!= 0) << 6;
16432 inst
.instruction
|= (ubit
!= 0) << 24;
16435 inst
.instruction
|= neon_logbits (size
) << 18;
16437 neon_dp_fixup (&inst
);
16440 enum vfp_or_neon_is_neon_bits
16443 NEON_CHECK_ARCH
= 2,
16444 NEON_CHECK_ARCH8
= 4
16447 /* Call this function if an instruction which may have belonged to the VFP or
16448 Neon instruction sets, but turned out to be a Neon instruction (due to the
16449 operand types involved, etc.). We have to check and/or fix-up a couple of
16452 - Make sure the user hasn't attempted to make a Neon instruction
16454 - Alter the value in the condition code field if necessary.
16455 - Make sure that the arch supports Neon instructions.
16457 Which of these operations take place depends on bits from enum
16458 vfp_or_neon_is_neon_bits.
16460 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16461 current instruction's condition is COND_ALWAYS, the condition field is
16462 changed to inst.uncond_value. This is necessary because instructions shared
16463 between VFP and Neon may be conditional for the VFP variants only, and the
16464 unconditional Neon version must have, e.g., 0xF in the condition field. */
16467 vfp_or_neon_is_neon (unsigned check
)
16469 /* Conditions are always legal in Thumb mode (IT blocks). */
16470 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
16472 if (inst
.cond
!= COND_ALWAYS
)
16474 first_error (_(BAD_COND
));
16477 if (inst
.uncond_value
!= -1)
16478 inst
.instruction
|= inst
.uncond_value
<< 28;
16482 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
16483 || ((check
& NEON_CHECK_ARCH8
)
16484 && !mark_feature_used (&fpu_neon_ext_armv8
)))
16486 first_error (_(BAD_FPU
));
16494 /* Return TRUE if the SIMD instruction is available for the current
16495 cpu_variant. FP is set to TRUE if this is a SIMD floating-point
16496 instruction. CHECK contains th. CHECK contains the set of bits to pass to
16497 vfp_or_neon_is_neon for the NEON specific checks. */
16500 check_simd_pred_availability (int fp
, unsigned check
)
16502 if (inst
.cond
> COND_ALWAYS
)
16504 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16506 inst
.error
= BAD_FPU
;
16509 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16511 else if (inst
.cond
< COND_ALWAYS
)
16513 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16514 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16515 else if (vfp_or_neon_is_neon (check
) == FAIL
)
16520 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
16521 && vfp_or_neon_is_neon (check
) == FAIL
)
16524 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16525 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16530 /* Neon instruction encoders, in approximate order of appearance. */
16533 do_neon_dyadic_i_su (void)
16535 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16538 enum neon_shape rs
;
16539 struct neon_type_el et
;
16540 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16541 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16543 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16545 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
16549 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16551 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16555 do_neon_dyadic_i64_su (void)
16557 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
16559 enum neon_shape rs
;
16560 struct neon_type_el et
;
16561 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16563 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16564 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16568 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16569 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16572 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16574 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16578 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
16581 unsigned size
= et
.size
>> 3;
16582 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16583 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16584 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16585 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16586 inst
.instruction
|= (isquad
!= 0) << 6;
16587 inst
.instruction
|= immbits
<< 16;
16588 inst
.instruction
|= (size
>> 3) << 7;
16589 inst
.instruction
|= (size
& 0x7) << 19;
16591 inst
.instruction
|= (uval
!= 0) << 24;
16593 neon_dp_fixup (&inst
);
16599 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16602 if (!inst
.operands
[2].isreg
)
16604 enum neon_shape rs
;
16605 struct neon_type_el et
;
16606 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16608 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16609 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_MVE
);
16613 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16614 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
16616 int imm
= inst
.operands
[2].imm
;
16618 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16619 _("immediate out of range for shift"));
16620 NEON_ENCODE (IMMED
, inst
);
16621 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
16625 enum neon_shape rs
;
16626 struct neon_type_el et
;
16627 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16629 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16630 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16634 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16635 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16641 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16642 _("invalid instruction shape"));
16643 if (inst
.operands
[2].reg
== REG_SP
)
16644 as_tsktsk (MVE_BAD_SP
);
16645 else if (inst
.operands
[2].reg
== REG_PC
)
16646 as_tsktsk (MVE_BAD_PC
);
16648 inst
.instruction
= 0xee311e60;
16649 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16650 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16651 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16652 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16653 inst
.instruction
|= inst
.operands
[2].reg
;
16660 /* VSHL/VQSHL 3-register variants have syntax such as:
16662 whereas other 3-register operations encoded by neon_three_same have
16665 (i.e. with Dn & Dm reversed). Swap operands[1].reg and
16666 operands[2].reg here. */
16667 tmp
= inst
.operands
[2].reg
;
16668 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16669 inst
.operands
[1].reg
= tmp
;
16670 NEON_ENCODE (INTEGER
, inst
);
16671 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16677 do_neon_qshl (void)
16679 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16682 if (!inst
.operands
[2].isreg
)
16684 enum neon_shape rs
;
16685 struct neon_type_el et
;
16686 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16688 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16689 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_SU_MVE
);
16693 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16694 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16696 int imm
= inst
.operands
[2].imm
;
16698 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16699 _("immediate out of range for shift"));
16700 NEON_ENCODE (IMMED
, inst
);
16701 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
16705 enum neon_shape rs
;
16706 struct neon_type_el et
;
16708 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16710 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16711 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16715 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16716 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16721 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16722 _("invalid instruction shape"));
16723 if (inst
.operands
[2].reg
== REG_SP
)
16724 as_tsktsk (MVE_BAD_SP
);
16725 else if (inst
.operands
[2].reg
== REG_PC
)
16726 as_tsktsk (MVE_BAD_PC
);
16728 inst
.instruction
= 0xee311ee0;
16729 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16730 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16731 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16732 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16733 inst
.instruction
|= inst
.operands
[2].reg
;
16740 /* See note in do_neon_shl. */
16741 tmp
= inst
.operands
[2].reg
;
16742 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16743 inst
.operands
[1].reg
= tmp
;
16744 NEON_ENCODE (INTEGER
, inst
);
16745 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16751 do_neon_rshl (void)
16753 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16756 enum neon_shape rs
;
16757 struct neon_type_el et
;
16758 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16760 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16761 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16765 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16766 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16773 if (inst
.operands
[2].reg
== REG_PC
)
16774 as_tsktsk (MVE_BAD_PC
);
16775 else if (inst
.operands
[2].reg
== REG_SP
)
16776 as_tsktsk (MVE_BAD_SP
);
16778 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16779 _("invalid instruction shape"));
16781 if (inst
.instruction
== 0x0000510)
16782 /* We are dealing with vqrshl. */
16783 inst
.instruction
= 0xee331ee0;
16785 /* We are dealing with vrshl. */
16786 inst
.instruction
= 0xee331e60;
16788 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16789 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16790 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16791 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16792 inst
.instruction
|= inst
.operands
[2].reg
;
16797 tmp
= inst
.operands
[2].reg
;
16798 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16799 inst
.operands
[1].reg
= tmp
;
16800 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16805 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
16807 /* Handle .I8 pseudo-instructions. */
16810 /* Unfortunately, this will make everything apart from zero out-of-range.
16811 FIXME is this the intended semantics? There doesn't seem much point in
16812 accepting .I8 if so. */
16813 immediate
|= immediate
<< 8;
16819 if (immediate
== (immediate
& 0x000000ff))
16821 *immbits
= immediate
;
16824 else if (immediate
== (immediate
& 0x0000ff00))
16826 *immbits
= immediate
>> 8;
16829 else if (immediate
== (immediate
& 0x00ff0000))
16831 *immbits
= immediate
>> 16;
16834 else if (immediate
== (immediate
& 0xff000000))
16836 *immbits
= immediate
>> 24;
16839 if ((immediate
& 0xffff) != (immediate
>> 16))
16840 goto bad_immediate
;
16841 immediate
&= 0xffff;
16844 if (immediate
== (immediate
& 0x000000ff))
16846 *immbits
= immediate
;
16849 else if (immediate
== (immediate
& 0x0000ff00))
16851 *immbits
= immediate
>> 8;
16856 first_error (_("immediate value out of range"));
16861 do_neon_logic (void)
16863 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
16865 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16867 && !check_simd_pred_availability (FALSE
,
16868 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16870 else if (rs
!= NS_QQQ
16871 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
16872 first_error (BAD_FPU
);
16874 neon_check_type (3, rs
, N_IGNORE_TYPE
);
16875 /* U bit and size field were set as part of the bitmask. */
16876 NEON_ENCODE (INTEGER
, inst
);
16877 neon_three_same (neon_quad (rs
), 0, -1);
16881 const int three_ops_form
= (inst
.operands
[2].present
16882 && !inst
.operands
[2].isreg
);
16883 const int immoperand
= (three_ops_form
? 2 : 1);
16884 enum neon_shape rs
= (three_ops_form
16885 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
16886 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
16887 /* Because neon_select_shape makes the second operand a copy of the first
16888 if the second operand is not present. */
16890 && !check_simd_pred_availability (FALSE
,
16891 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16893 else if (rs
!= NS_QQI
16894 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
16895 first_error (BAD_FPU
);
16897 struct neon_type_el et
;
16898 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16899 et
= neon_check_type (2, rs
, N_I32
| N_I16
| N_KEY
, N_EQK
);
16901 et
= neon_check_type (2, rs
, N_I8
| N_I16
| N_I32
| N_I64
| N_F32
16904 if (et
.type
== NT_invtype
)
16906 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
16911 if (three_ops_form
)
16912 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16913 _("first and second operands shall be the same register"));
16915 NEON_ENCODE (IMMED
, inst
);
16917 immbits
= inst
.operands
[immoperand
].imm
;
16920 /* .i64 is a pseudo-op, so the immediate must be a repeating
16922 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
16923 inst
.operands
[immoperand
].reg
: 0))
16925 /* Set immbits to an invalid constant. */
16926 immbits
= 0xdeadbeef;
16933 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16937 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16941 /* Pseudo-instruction for VBIC. */
16942 neon_invert_size (&immbits
, 0, et
.size
);
16943 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16947 /* Pseudo-instruction for VORR. */
16948 neon_invert_size (&immbits
, 0, et
.size
);
16949 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16959 inst
.instruction
|= neon_quad (rs
) << 6;
16960 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16961 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16962 inst
.instruction
|= cmode
<< 8;
16963 neon_write_immbits (immbits
);
16965 neon_dp_fixup (&inst
);
16970 do_neon_bitfield (void)
16972 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16973 neon_check_type (3, rs
, N_IGNORE_TYPE
);
16974 neon_three_same (neon_quad (rs
), 0, -1);
16978 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
16981 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
16982 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
16984 if (et
.type
== NT_float
)
16986 NEON_ENCODE (FLOAT
, inst
);
16988 mve_encode_qqr (et
.size
, 0, 1);
16990 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
16994 NEON_ENCODE (INTEGER
, inst
);
16996 mve_encode_qqr (et
.size
, et
.type
== ubit_meaning
, 0);
16998 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
17004 do_neon_dyadic_if_su_d (void)
17006 /* This version only allow D registers, but that constraint is enforced during
17007 operand parsing so we don't need to do anything extra here. */
17008 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17012 do_neon_dyadic_if_i_d (void)
17014 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17015 affected if we specify unsigned args. */
17016 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17020 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
17022 constraint (size
< 32, BAD_ADDR_MODE
);
17023 constraint (size
!= elsize
, BAD_EL_TYPE
);
17024 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17025 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
17026 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
17027 _("destination register and offset register may not be the"
17030 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17037 constraint ((imm
% (size
/ 8) != 0)
17038 || imm
> (0x7f << neon_logbits (size
)),
17039 (size
== 32) ? _("immediate must be a multiple of 4 in the"
17040 " range of +/-[0,508]")
17041 : _("immediate must be a multiple of 8 in the"
17042 " range of +/-[0,1016]"));
17043 inst
.instruction
|= 0x11 << 24;
17044 inst
.instruction
|= add
<< 23;
17045 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17046 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17047 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17048 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17049 inst
.instruction
|= 1 << 12;
17050 inst
.instruction
|= (size
== 64) << 8;
17051 inst
.instruction
&= 0xffffff00;
17052 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17053 inst
.instruction
|= imm
>> neon_logbits (size
);
17057 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
17059 unsigned os
= inst
.operands
[1].imm
>> 5;
17060 constraint (os
!= 0 && size
== 8,
17061 _("can not shift offsets when accessing less than half-word"));
17062 constraint (os
&& os
!= neon_logbits (size
),
17063 _("shift immediate must be 1, 2 or 3 for half-word, word"
17064 " or double-word accesses respectively"));
17065 if (inst
.operands
[1].reg
== REG_PC
)
17066 as_tsktsk (MVE_BAD_PC
);
17071 constraint (elsize
>= 64, BAD_EL_TYPE
);
17074 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17078 constraint (elsize
!= size
, BAD_EL_TYPE
);
17083 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
17087 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
17088 _("destination register and offset register may not be"
17090 constraint (size
== elsize
&& inst
.vectype
.el
[0].type
!= NT_unsigned
,
17092 constraint (inst
.vectype
.el
[0].type
!= NT_unsigned
17093 && inst
.vectype
.el
[0].type
!= NT_signed
, BAD_EL_TYPE
);
17094 inst
.instruction
|= (inst
.vectype
.el
[0].type
== NT_unsigned
) << 28;
17098 constraint (inst
.vectype
.el
[0].type
!= NT_untyped
, BAD_EL_TYPE
);
17101 inst
.instruction
|= 1 << 23;
17102 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17103 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17104 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17105 inst
.instruction
|= neon_logbits (elsize
) << 7;
17106 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
17107 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
17108 inst
.instruction
|= !!os
;
17112 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
17114 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
17116 constraint (size
>= 64, BAD_ADDR_MODE
);
17120 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17123 constraint (elsize
!= size
, BAD_EL_TYPE
);
17130 constraint (elsize
!= size
&& type
!= NT_unsigned
17131 && type
!= NT_signed
, BAD_EL_TYPE
);
17135 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
17138 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17146 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
17151 constraint (1, _("immediate must be in the range of +/-[0,127]"));
17154 constraint (1, _("immediate must be a multiple of 2 in the"
17155 " range of +/-[0,254]"));
17158 constraint (1, _("immediate must be a multiple of 4 in the"
17159 " range of +/-[0,508]"));
17164 if (size
!= elsize
)
17166 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
17167 constraint (inst
.operands
[0].reg
> 14,
17168 _("MVE vector register in the range [Q0..Q7] expected"));
17169 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
17170 inst
.instruction
|= (size
== 16) << 19;
17171 inst
.instruction
|= neon_logbits (elsize
) << 7;
17175 if (inst
.operands
[1].reg
== REG_PC
)
17176 as_tsktsk (MVE_BAD_PC
);
17177 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17178 as_tsktsk (MVE_BAD_SP
);
17179 inst
.instruction
|= 1 << 12;
17180 inst
.instruction
|= neon_logbits (size
) << 7;
17182 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
17183 inst
.instruction
|= add
<< 23;
17184 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17185 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17186 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17187 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17188 inst
.instruction
&= 0xffffff80;
17189 inst
.instruction
|= imm
>> neon_logbits (size
);
17194 do_mve_vstr_vldr (void)
17199 if (inst
.cond
> COND_ALWAYS
)
17200 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17202 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17204 switch (inst
.instruction
)
17211 /* fall through. */
17217 /* fall through. */
17223 /* fall through. */
17229 /* fall through. */
17234 unsigned elsize
= inst
.vectype
.el
[0].size
;
17236 if (inst
.operands
[1].isquad
)
17238 /* We are dealing with [Q, imm]{!} cases. */
17239 do_mve_vstr_vldr_QI (size
, elsize
, load
);
17243 if (inst
.operands
[1].immisreg
== 2)
17245 /* We are dealing with [R, Q, {UXTW #os}] cases. */
17246 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
17248 else if (!inst
.operands
[1].immisreg
)
17250 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
17251 do_mve_vstr_vldr_RI (size
, elsize
, load
);
17254 constraint (1, BAD_ADDR_MODE
);
17261 do_mve_vst_vld (void)
17263 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17266 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
17267 || inst
.relocs
[0].exp
.X_add_number
!= 0
17268 || inst
.operands
[1].immisreg
!= 0,
17270 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
17271 if (inst
.operands
[1].reg
== REG_PC
)
17272 as_tsktsk (MVE_BAD_PC
);
17273 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17274 as_tsktsk (MVE_BAD_SP
);
17277 /* These instructions are one of the "exceptions" mentioned in
17278 handle_pred_state. They are MVE instructions that are not VPT compatible
17279 and do not accept a VPT code, thus appending such a code is a syntax
17281 if (inst
.cond
> COND_ALWAYS
)
17282 first_error (BAD_SYNTAX
);
17283 /* If we append a scalar condition code we can set this to
17284 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
17285 else if (inst
.cond
< COND_ALWAYS
)
17286 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17288 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
17290 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17291 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17292 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17293 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17294 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
17299 do_mve_vaddlv (void)
17301 enum neon_shape rs
= neon_select_shape (NS_RRQ
, NS_NULL
);
17302 struct neon_type_el et
17303 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S32
| N_U32
| N_KEY
);
17305 if (et
.type
== NT_invtype
)
17306 first_error (BAD_EL_TYPE
);
17308 if (inst
.cond
> COND_ALWAYS
)
17309 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17311 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17313 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17315 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17316 inst
.instruction
|= inst
.operands
[1].reg
<< 19;
17317 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
17318 inst
.instruction
|= inst
.operands
[2].reg
;
17323 do_neon_dyadic_if_su (void)
17325 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17326 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17329 constraint ((inst
.instruction
== ((unsigned) N_MNEM_vmax
)
17330 || inst
.instruction
== ((unsigned) N_MNEM_vmin
))
17331 && et
.type
== NT_float
17332 && !ARM_CPU_HAS_FEATURE (cpu_variant
,fpu_neon_ext_v1
), BAD_FPU
);
17334 if (!check_simd_pred_availability (et
.type
== NT_float
,
17335 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17338 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17342 do_neon_addsub_if_i (void)
17344 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
17345 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
17348 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17349 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
17350 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
17352 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
17353 /* If we are parsing Q registers and the element types match MVE, which NEON
17354 also supports, then we must check whether this is an instruction that can
17355 be used by both MVE/NEON. This distinction can be made based on whether
17356 they are predicated or not. */
17357 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
17359 if (!check_simd_pred_availability (et
.type
== NT_float
,
17360 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17365 /* If they are either in a D register or are using an unsupported. */
17367 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17371 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17372 affected if we specify unsigned args. */
17373 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
17376 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17378 V<op> A,B (A is operand 0, B is operand 2)
17383 so handle that case specially. */
17386 neon_exchange_operands (void)
17388 if (inst
.operands
[1].present
)
17390 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
17392 /* Swap operands[1] and operands[2]. */
17393 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
17394 inst
.operands
[1] = inst
.operands
[2];
17395 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
17400 inst
.operands
[1] = inst
.operands
[2];
17401 inst
.operands
[2] = inst
.operands
[0];
17406 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
17408 if (inst
.operands
[2].isreg
)
17411 neon_exchange_operands ();
17412 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
17416 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17417 struct neon_type_el et
= neon_check_type (2, rs
,
17418 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
17420 NEON_ENCODE (IMMED
, inst
);
17421 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17422 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17423 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17424 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17425 inst
.instruction
|= neon_quad (rs
) << 6;
17426 inst
.instruction
|= (et
.type
== NT_float
) << 10;
17427 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17429 neon_dp_fixup (&inst
);
17436 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
17440 do_neon_cmp_inv (void)
17442 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
17448 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
17451 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
17452 scalars, which are encoded in 5 bits, M : Rm.
17453 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17454 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
17457 Dot Product instructions are similar to multiply instructions except elsize
17458 should always be 32.
17460 This function translates SCALAR, which is GAS's internal encoding of indexed
17461 scalar register, to raw encoding. There is also register and index range
17462 check based on ELSIZE. */
17465 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
17467 unsigned regno
= NEON_SCALAR_REG (scalar
);
17468 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
17473 if (regno
> 7 || elno
> 3)
17475 return regno
| (elno
<< 3);
17478 if (regno
> 15 || elno
> 1)
17480 return regno
| (elno
<< 4);
17484 first_error (_("scalar out of range for multiply instruction"));
17490 /* Encode multiply / multiply-accumulate scalar instructions. */
17493 neon_mul_mac (struct neon_type_el et
, int ubit
)
17497 /* Give a more helpful error message if we have an invalid type. */
17498 if (et
.type
== NT_invtype
)
17501 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
17502 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17503 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17504 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17505 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17506 inst
.instruction
|= LOW4 (scalar
);
17507 inst
.instruction
|= HI1 (scalar
) << 5;
17508 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17509 inst
.instruction
|= neon_logbits (et
.size
) << 20;
17510 inst
.instruction
|= (ubit
!= 0) << 24;
17512 neon_dp_fixup (&inst
);
17516 do_neon_mac_maybe_scalar (void)
17518 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
17521 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17524 if (inst
.operands
[2].isscalar
)
17526 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17527 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17528 struct neon_type_el et
= neon_check_type (3, rs
,
17529 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
17530 NEON_ENCODE (SCALAR
, inst
);
17531 neon_mul_mac (et
, neon_quad (rs
));
17533 else if (!inst
.operands
[2].isvec
)
17535 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17537 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17538 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17540 neon_dyadic_misc (NT_unsigned
, N_SU_MVE
, 0);
17544 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17545 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17546 affected if we specify unsigned args. */
17547 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17552 do_neon_fmac (void)
17554 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_fma
)
17555 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
17558 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17561 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17563 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17564 struct neon_type_el et
= neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
,
17569 if (inst
.operands
[2].reg
== REG_SP
)
17570 as_tsktsk (MVE_BAD_SP
);
17571 else if (inst
.operands
[2].reg
== REG_PC
)
17572 as_tsktsk (MVE_BAD_PC
);
17574 inst
.instruction
= 0xee310e40;
17575 inst
.instruction
|= (et
.size
== 16) << 28;
17576 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17577 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17578 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17579 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 6;
17580 inst
.instruction
|= inst
.operands
[2].reg
;
17587 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17590 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17596 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17597 struct neon_type_el et
= neon_check_type (3, rs
,
17598 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17599 neon_three_same (neon_quad (rs
), 0, et
.size
);
17602 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
17603 same types as the MAC equivalents. The polynomial type for this instruction
17604 is encoded the same as the integer type. */
17609 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
17612 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17615 if (inst
.operands
[2].isscalar
)
17617 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17618 do_neon_mac_maybe_scalar ();
17622 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17624 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17625 struct neon_type_el et
17626 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_I_MVE
| N_F_MVE
| N_KEY
);
17627 if (et
.type
== NT_float
)
17628 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
17631 neon_dyadic_misc (NT_float
, N_I_MVE
| N_F_MVE
, 0);
17635 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17636 neon_dyadic_misc (NT_poly
,
17637 N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
17643 do_neon_qdmulh (void)
17645 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17648 if (inst
.operands
[2].isscalar
)
17650 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17651 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17652 struct neon_type_el et
= neon_check_type (3, rs
,
17653 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17654 NEON_ENCODE (SCALAR
, inst
);
17655 neon_mul_mac (et
, neon_quad (rs
));
17659 enum neon_shape rs
;
17660 struct neon_type_el et
;
17661 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17663 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17664 et
= neon_check_type (3, rs
,
17665 N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17669 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17670 et
= neon_check_type (3, rs
,
17671 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17674 NEON_ENCODE (INTEGER
, inst
);
17676 mve_encode_qqr (et
.size
, 0, 0);
17678 /* The U bit (rounding) comes from bit mask. */
17679 neon_three_same (neon_quad (rs
), 0, et
.size
);
17684 do_mve_vaddv (void)
17686 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
17687 struct neon_type_el et
17688 = neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
17690 if (et
.type
== NT_invtype
)
17691 first_error (BAD_EL_TYPE
);
17693 if (inst
.cond
> COND_ALWAYS
)
17694 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17696 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17698 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17700 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
17704 do_mve_vhcadd (void)
17706 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
17707 struct neon_type_el et
17708 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17710 if (inst
.cond
> COND_ALWAYS
)
17711 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17713 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17715 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
17716 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17718 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
17719 as_tsktsk (_("Warning: 32-bit element size and same first and third "
17720 "operand makes instruction UNPREDICTABLE"));
17722 mve_encode_qqq (0, et
.size
);
17723 inst
.instruction
|= (rot
== 270) << 12;
17728 do_mve_vqdmull (void)
17730 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17731 struct neon_type_el et
17732 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17735 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
17736 || (rs
== NS_QQQ
&& inst
.operands
[0].reg
== inst
.operands
[2].reg
)))
17737 as_tsktsk (BAD_MVE_SRCDEST
);
17739 if (inst
.cond
> COND_ALWAYS
)
17740 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17742 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17746 mve_encode_qqq (et
.size
== 32, 64);
17747 inst
.instruction
|= 1;
17751 mve_encode_qqr (64, et
.size
== 32, 0);
17752 inst
.instruction
|= 0x3 << 5;
17759 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17760 struct neon_type_el et
17761 = neon_check_type (3, rs
, N_KEY
| N_I32
, N_EQK
, N_EQK
);
17763 if (et
.type
== NT_invtype
)
17764 first_error (BAD_EL_TYPE
);
17766 if (inst
.cond
> COND_ALWAYS
)
17767 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17769 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17771 mve_encode_qqq (0, 64);
17775 do_mve_vbrsr (void)
17777 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17778 struct neon_type_el et
17779 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17781 if (inst
.cond
> COND_ALWAYS
)
17782 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17784 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17786 mve_encode_qqr (et
.size
, 0, 0);
17792 neon_check_type (3, NS_QQQ
, N_EQK
, N_EQK
, N_I32
| N_KEY
);
17794 if (inst
.cond
> COND_ALWAYS
)
17795 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17797 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17799 mve_encode_qqq (1, 64);
17803 do_mve_vmulh (void)
17805 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17806 struct neon_type_el et
17807 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17809 if (inst
.cond
> COND_ALWAYS
)
17810 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17812 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17814 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
17818 do_mve_vqdmlah (void)
17820 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17821 struct neon_type_el et
17822 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17824 if (inst
.cond
> COND_ALWAYS
)
17825 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17827 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17829 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
17833 do_mve_vqdmladh (void)
17835 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17836 struct neon_type_el et
17837 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17839 if (inst
.cond
> COND_ALWAYS
)
17840 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17842 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17845 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
17846 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
17847 as_tsktsk (BAD_MVE_SRCDEST
);
17849 mve_encode_qqq (0, et
.size
);
17854 do_mve_vmull (void)
17857 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
17858 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
17859 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
17860 && inst
.cond
== COND_ALWAYS
17861 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
17866 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17867 N_SUF_32
| N_F64
| N_P8
17868 | N_P16
| N_I_MVE
| N_KEY
);
17869 if (((et
.type
== NT_poly
) && et
.size
== 8
17870 && ARM_CPU_IS_ANY (cpu_variant
))
17871 || (et
.type
== NT_integer
) || (et
.type
== NT_float
))
17878 constraint (rs
!= NS_QQQ
, BAD_FPU
);
17879 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17880 N_SU_32
| N_P8
| N_P16
| N_KEY
);
17882 /* We are dealing with MVE's vmullt. */
17884 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
17885 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
17886 as_tsktsk (BAD_MVE_SRCDEST
);
17888 if (inst
.cond
> COND_ALWAYS
)
17889 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17891 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17893 if (et
.type
== NT_poly
)
17894 mve_encode_qqq (neon_logbits (et
.size
), 64);
17896 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
17901 inst
.instruction
= N_MNEM_vmul
;
17904 inst
.pred_insn_type
= INSIDE_IT_INSN
;
17909 do_mve_vabav (void)
17911 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
17916 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17919 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
17920 | N_S16
| N_S32
| N_U8
| N_U16
17923 if (inst
.cond
> COND_ALWAYS
)
17924 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17926 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17928 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
17932 do_mve_vmladav (void)
17934 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
17935 struct neon_type_el et
= neon_check_type (3, rs
,
17936 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17938 if (et
.type
== NT_unsigned
17939 && (inst
.instruction
== M_MNEM_vmladavx
17940 || inst
.instruction
== M_MNEM_vmladavax
17941 || inst
.instruction
== M_MNEM_vmlsdav
17942 || inst
.instruction
== M_MNEM_vmlsdava
17943 || inst
.instruction
== M_MNEM_vmlsdavx
17944 || inst
.instruction
== M_MNEM_vmlsdavax
))
17945 first_error (BAD_SIMD_TYPE
);
17947 constraint (inst
.operands
[2].reg
> 14,
17948 _("MVE vector register in the range [Q0..Q7] expected"));
17950 if (inst
.cond
> COND_ALWAYS
)
17951 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17953 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17955 if (inst
.instruction
== M_MNEM_vmlsdav
17956 || inst
.instruction
== M_MNEM_vmlsdava
17957 || inst
.instruction
== M_MNEM_vmlsdavx
17958 || inst
.instruction
== M_MNEM_vmlsdavax
)
17959 inst
.instruction
|= (et
.size
== 8) << 28;
17961 inst
.instruction
|= (et
.size
== 8) << 8;
17963 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
17964 inst
.instruction
|= (et
.size
== 32) << 16;
17968 do_mve_vmlaldav (void)
17970 enum neon_shape rs
= neon_select_shape (NS_RRQQ
, NS_NULL
);
17971 struct neon_type_el et
17972 = neon_check_type (4, rs
, N_EQK
, N_EQK
, N_EQK
,
17973 N_S16
| N_S32
| N_U16
| N_U32
| N_KEY
);
17975 if (et
.type
== NT_unsigned
17976 && (inst
.instruction
== M_MNEM_vmlsldav
17977 || inst
.instruction
== M_MNEM_vmlsldava
17978 || inst
.instruction
== M_MNEM_vmlsldavx
17979 || inst
.instruction
== M_MNEM_vmlsldavax
))
17980 first_error (BAD_SIMD_TYPE
);
17982 if (inst
.cond
> COND_ALWAYS
)
17983 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17985 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17987 mve_encode_rrqq (et
.type
== NT_unsigned
, et
.size
);
17991 do_mve_vrmlaldavh (void)
17993 struct neon_type_el et
;
17994 if (inst
.instruction
== M_MNEM_vrmlsldavh
17995 || inst
.instruction
== M_MNEM_vrmlsldavha
17996 || inst
.instruction
== M_MNEM_vrmlsldavhx
17997 || inst
.instruction
== M_MNEM_vrmlsldavhax
)
17999 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18000 if (inst
.operands
[1].reg
== REG_SP
)
18001 as_tsktsk (MVE_BAD_SP
);
18005 if (inst
.instruction
== M_MNEM_vrmlaldavhx
18006 || inst
.instruction
== M_MNEM_vrmlaldavhax
)
18007 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18009 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
,
18010 N_U32
| N_S32
| N_KEY
);
18011 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
18012 with vmax/min instructions, making the use of SP in assembly really
18013 nonsensical, so instead of issuing a warning like we do for other uses
18014 of SP for the odd register operand we error out. */
18015 constraint (inst
.operands
[1].reg
== REG_SP
, BAD_SP
);
18018 /* Make sure we still check the second operand is an odd one and that PC is
18019 disallowed. This because we are parsing for any GPR operand, to be able
18020 to distinguish between giving a warning or an error for SP as described
18022 constraint ((inst
.operands
[1].reg
% 2) != 1, BAD_EVEN
);
18023 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
18025 if (inst
.cond
> COND_ALWAYS
)
18026 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18028 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18030 mve_encode_rrqq (et
.type
== NT_unsigned
, 0);
18035 do_mve_vmaxnmv (void)
18037 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18038 struct neon_type_el et
18039 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
18041 if (inst
.cond
> COND_ALWAYS
)
18042 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18044 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18046 if (inst
.operands
[0].reg
== REG_SP
)
18047 as_tsktsk (MVE_BAD_SP
);
18048 else if (inst
.operands
[0].reg
== REG_PC
)
18049 as_tsktsk (MVE_BAD_PC
);
18051 mve_encode_rq (et
.size
== 16, 64);
18055 do_mve_vmaxv (void)
18057 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18058 struct neon_type_el et
;
18060 if (inst
.instruction
== M_MNEM_vmaxv
|| inst
.instruction
== M_MNEM_vminv
)
18061 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
18063 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18065 if (inst
.cond
> COND_ALWAYS
)
18066 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18068 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18070 if (inst
.operands
[0].reg
== REG_SP
)
18071 as_tsktsk (MVE_BAD_SP
);
18072 else if (inst
.operands
[0].reg
== REG_PC
)
18073 as_tsktsk (MVE_BAD_PC
);
18075 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18080 do_neon_qrdmlah (void)
18082 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18084 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18086 /* Check we're on the correct architecture. */
18087 if (!mark_feature_used (&fpu_neon_ext_armv8
))
18089 = _("instruction form not available on this architecture.");
18090 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
18092 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
18093 record_feature_use (&fpu_neon_ext_v8_1
);
18095 if (inst
.operands
[2].isscalar
)
18097 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18098 struct neon_type_el et
= neon_check_type (3, rs
,
18099 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18100 NEON_ENCODE (SCALAR
, inst
);
18101 neon_mul_mac (et
, neon_quad (rs
));
18105 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18106 struct neon_type_el et
= neon_check_type (3, rs
,
18107 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18108 NEON_ENCODE (INTEGER
, inst
);
18109 /* The U bit (rounding) comes from bit mask. */
18110 neon_three_same (neon_quad (rs
), 0, et
.size
);
18115 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18116 struct neon_type_el et
18117 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18119 NEON_ENCODE (INTEGER
, inst
);
18120 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18125 do_neon_fcmp_absolute (void)
18127 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18128 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18129 N_F_16_32
| N_KEY
);
18130 /* Size field comes from bit mask. */
18131 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
18135 do_neon_fcmp_absolute_inv (void)
18137 neon_exchange_operands ();
18138 do_neon_fcmp_absolute ();
18142 do_neon_step (void)
18144 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18145 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18146 N_F_16_32
| N_KEY
);
18147 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
18151 do_neon_abs_neg (void)
18153 enum neon_shape rs
;
18154 struct neon_type_el et
;
18156 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
18159 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18160 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
18162 if (!check_simd_pred_availability (et
.type
== NT_float
,
18163 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18166 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18167 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18168 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18169 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18170 inst
.instruction
|= neon_quad (rs
) << 6;
18171 inst
.instruction
|= (et
.type
== NT_float
) << 10;
18172 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18174 neon_dp_fixup (&inst
);
18180 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18183 enum neon_shape rs
;
18184 struct neon_type_el et
;
18185 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18187 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18188 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18192 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18193 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18197 int imm
= inst
.operands
[2].imm
;
18198 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18199 _("immediate out of range for insert"));
18200 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18206 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18209 enum neon_shape rs
;
18210 struct neon_type_el et
;
18211 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18213 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18214 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18218 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18219 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18222 int imm
= inst
.operands
[2].imm
;
18223 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18224 _("immediate out of range for insert"));
18225 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
18229 do_neon_qshlu_imm (void)
18231 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18234 enum neon_shape rs
;
18235 struct neon_type_el et
;
18236 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18238 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18239 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18243 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18244 et
= neon_check_type (2, rs
, N_EQK
| N_UNS
,
18245 N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
18248 int imm
= inst
.operands
[2].imm
;
18249 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18250 _("immediate out of range for shift"));
18251 /* Only encodes the 'U present' variant of the instruction.
18252 In this case, signed types have OP (bit 8) set to 0.
18253 Unsigned types have OP set to 1. */
18254 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
18255 /* The rest of the bits are the same as other immediate shifts. */
18256 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18260 do_neon_qmovn (void)
18262 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18263 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18264 /* Saturating move where operands can be signed or unsigned, and the
18265 destination has the same signedness. */
18266 NEON_ENCODE (INTEGER
, inst
);
18267 if (et
.type
== NT_unsigned
)
18268 inst
.instruction
|= 0xc0;
18270 inst
.instruction
|= 0x80;
18271 neon_two_same (0, 1, et
.size
/ 2);
18275 do_neon_qmovun (void)
18277 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18278 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18279 /* Saturating move with unsigned results. Operands must be signed. */
18280 NEON_ENCODE (INTEGER
, inst
);
18281 neon_two_same (0, 1, et
.size
/ 2);
18285 do_neon_rshift_sat_narrow (void)
18287 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18288 or unsigned. If operands are unsigned, results must also be unsigned. */
18289 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18290 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18291 int imm
= inst
.operands
[2].imm
;
18292 /* This gets the bounds check, size encoding and immediate bits calculation
18296 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18297 VQMOVN.I<size> <Dd>, <Qm>. */
18300 inst
.operands
[2].present
= 0;
18301 inst
.instruction
= N_MNEM_vqmovn
;
18306 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18307 _("immediate out of range"));
18308 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
18312 do_neon_rshift_sat_narrow_u (void)
18314 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18315 or unsigned. If operands are unsigned, results must also be unsigned. */
18316 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18317 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18318 int imm
= inst
.operands
[2].imm
;
18319 /* This gets the bounds check, size encoding and immediate bits calculation
18323 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18324 VQMOVUN.I<size> <Dd>, <Qm>. */
18327 inst
.operands
[2].present
= 0;
18328 inst
.instruction
= N_MNEM_vqmovun
;
18333 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18334 _("immediate out of range"));
18335 /* FIXME: The manual is kind of unclear about what value U should have in
18336 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18338 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
18342 do_neon_movn (void)
18344 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18345 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18346 NEON_ENCODE (INTEGER
, inst
);
18347 neon_two_same (0, 1, et
.size
/ 2);
18351 do_neon_rshift_narrow (void)
18353 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18354 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18355 int imm
= inst
.operands
[2].imm
;
18356 /* This gets the bounds check, size encoding and immediate bits calculation
18360 /* If immediate is zero then we are a pseudo-instruction for
18361 VMOVN.I<size> <Dd>, <Qm> */
18364 inst
.operands
[2].present
= 0;
18365 inst
.instruction
= N_MNEM_vmovn
;
18370 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18371 _("immediate out of range for narrowing operation"));
18372 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
18376 do_neon_shll (void)
18378 /* FIXME: Type checking when lengthening. */
18379 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
18380 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
18381 unsigned imm
= inst
.operands
[2].imm
;
18383 if (imm
== et
.size
)
18385 /* Maximum shift variant. */
18386 NEON_ENCODE (INTEGER
, inst
);
18387 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18388 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18389 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18390 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18391 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18393 neon_dp_fixup (&inst
);
18397 /* A more-specific type check for non-max versions. */
18398 et
= neon_check_type (2, NS_QDI
,
18399 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18400 NEON_ENCODE (IMMED
, inst
);
18401 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
18405 /* Check the various types for the VCVT instruction, and return which version
18406 the current instruction is. */
18408 #define CVT_FLAVOUR_VAR \
18409 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18410 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18411 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18412 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18413 /* Half-precision conversions. */ \
18414 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18415 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18416 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18417 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
18418 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18419 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
18420 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18421 Compared with single/double precision variants, only the co-processor \
18422 field is different, so the encoding flow is reused here. */ \
18423 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18424 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18425 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18426 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
18427 /* VFP instructions. */ \
18428 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18429 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18430 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18431 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18432 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18433 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18434 /* VFP instructions with bitshift. */ \
18435 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18436 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18437 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18438 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18439 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18440 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18441 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18442 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18444 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18445 neon_cvt_flavour_##C,
18447 /* The different types of conversions we can do. */
18448 enum neon_cvt_flavour
18451 neon_cvt_flavour_invalid
,
18452 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
18457 static enum neon_cvt_flavour
18458 get_neon_cvt_flavour (enum neon_shape rs
)
18460 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18461 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18462 if (et.type != NT_invtype) \
18464 inst.error = NULL; \
18465 return (neon_cvt_flavour_##C); \
18468 struct neon_type_el et
;
18469 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
18470 || rs
== NS_FF
) ? N_VFP
: 0;
18471 /* The instruction versions which take an immediate take one register
18472 argument, which is extended to the width of the full register. Thus the
18473 "source" and "destination" registers must have the same width. Hack that
18474 here by making the size equal to the key (wider, in this case) operand. */
18475 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
18479 return neon_cvt_flavour_invalid
;
18494 /* Neon-syntax VFP conversions. */
18497 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
18499 const char *opname
= 0;
18501 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
18502 || rs
== NS_FHI
|| rs
== NS_HFI
)
18504 /* Conversions with immediate bitshift. */
18505 const char *enc
[] =
18507 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18513 if (flavour
< (int) ARRAY_SIZE (enc
))
18515 opname
= enc
[flavour
];
18516 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
18517 _("operands 0 and 1 must be the same register"));
18518 inst
.operands
[1] = inst
.operands
[2];
18519 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
18524 /* Conversions without bitshift. */
18525 const char *enc
[] =
18527 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18533 if (flavour
< (int) ARRAY_SIZE (enc
))
18534 opname
= enc
[flavour
];
18538 do_vfp_nsyn_opcode (opname
);
18540 /* ARMv8.2 fp16 VCVT instruction. */
18541 if (flavour
== neon_cvt_flavour_s32_f16
18542 || flavour
== neon_cvt_flavour_u32_f16
18543 || flavour
== neon_cvt_flavour_f16_u32
18544 || flavour
== neon_cvt_flavour_f16_s32
)
18545 do_scalar_fp16_v82_encode ();
18549 do_vfp_nsyn_cvtz (void)
18551 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
18552 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18553 const char *enc
[] =
18555 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18561 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
18562 do_vfp_nsyn_opcode (enc
[flavour
]);
18566 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
18567 enum neon_cvt_mode mode
)
18572 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18573 D register operands. */
18574 if (flavour
== neon_cvt_flavour_s32_f64
18575 || flavour
== neon_cvt_flavour_u32_f64
)
18576 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18579 if (flavour
== neon_cvt_flavour_s32_f16
18580 || flavour
== neon_cvt_flavour_u32_f16
)
18581 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
18584 set_pred_insn_type (OUTSIDE_PRED_INSN
);
18588 case neon_cvt_flavour_s32_f64
:
18592 case neon_cvt_flavour_s32_f32
:
18596 case neon_cvt_flavour_s32_f16
:
18600 case neon_cvt_flavour_u32_f64
:
18604 case neon_cvt_flavour_u32_f32
:
18608 case neon_cvt_flavour_u32_f16
:
18613 first_error (_("invalid instruction shape"));
18619 case neon_cvt_mode_a
: rm
= 0; break;
18620 case neon_cvt_mode_n
: rm
= 1; break;
18621 case neon_cvt_mode_p
: rm
= 2; break;
18622 case neon_cvt_mode_m
: rm
= 3; break;
18623 default: first_error (_("invalid rounding mode")); return;
18626 NEON_ENCODE (FPV8
, inst
);
18627 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
18628 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
18629 inst
.instruction
|= sz
<< 8;
18631 /* ARMv8.2 fp16 VCVT instruction. */
18632 if (flavour
== neon_cvt_flavour_s32_f16
18633 ||flavour
== neon_cvt_flavour_u32_f16
)
18634 do_scalar_fp16_v82_encode ();
18635 inst
.instruction
|= op
<< 7;
18636 inst
.instruction
|= rm
<< 16;
18637 inst
.instruction
|= 0xf0000000;
18638 inst
.is_neon
= TRUE
;
18642 do_neon_cvt_1 (enum neon_cvt_mode mode
)
18644 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
18645 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
18646 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
18648 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18650 if (flavour
== neon_cvt_flavour_invalid
)
18653 /* PR11109: Handle round-to-zero for VCVT conversions. */
18654 if (mode
== neon_cvt_mode_z
18655 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
18656 && (flavour
== neon_cvt_flavour_s16_f16
18657 || flavour
== neon_cvt_flavour_u16_f16
18658 || flavour
== neon_cvt_flavour_s32_f32
18659 || flavour
== neon_cvt_flavour_u32_f32
18660 || flavour
== neon_cvt_flavour_s32_f64
18661 || flavour
== neon_cvt_flavour_u32_f64
)
18662 && (rs
== NS_FD
|| rs
== NS_FF
))
18664 do_vfp_nsyn_cvtz ();
18668 /* ARMv8.2 fp16 VCVT conversions. */
18669 if (mode
== neon_cvt_mode_z
18670 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
18671 && (flavour
== neon_cvt_flavour_s32_f16
18672 || flavour
== neon_cvt_flavour_u32_f16
)
18675 do_vfp_nsyn_cvtz ();
18676 do_scalar_fp16_v82_encode ();
18680 /* VFP rather than Neon conversions. */
18681 if (flavour
>= neon_cvt_flavour_first_fp
)
18683 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
18684 do_vfp_nsyn_cvt (rs
, flavour
);
18686 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
18694 if (mode
== neon_cvt_mode_z
18695 && (flavour
== neon_cvt_flavour_f16_s16
18696 || flavour
== neon_cvt_flavour_f16_u16
18697 || flavour
== neon_cvt_flavour_s16_f16
18698 || flavour
== neon_cvt_flavour_u16_f16
18699 || flavour
== neon_cvt_flavour_f32_u32
18700 || flavour
== neon_cvt_flavour_f32_s32
18701 || flavour
== neon_cvt_flavour_s32_f32
18702 || flavour
== neon_cvt_flavour_u32_f32
))
18704 if (!check_simd_pred_availability (TRUE
,
18705 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18708 else if (mode
== neon_cvt_mode_n
)
18710 /* We are dealing with vcvt with the 'ne' condition. */
18712 inst
.instruction
= N_MNEM_vcvt
;
18713 do_neon_cvt_1 (neon_cvt_mode_z
);
18716 /* fall through. */
18720 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
18721 0x0000100, 0x1000100, 0x0, 0x1000000};
18723 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18724 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18727 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18729 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
18730 _("immediate value out of range"));
18733 case neon_cvt_flavour_f16_s16
:
18734 case neon_cvt_flavour_f16_u16
:
18735 case neon_cvt_flavour_s16_f16
:
18736 case neon_cvt_flavour_u16_f16
:
18737 constraint (inst
.operands
[2].imm
> 16,
18738 _("immediate value out of range"));
18740 case neon_cvt_flavour_f32_u32
:
18741 case neon_cvt_flavour_f32_s32
:
18742 case neon_cvt_flavour_s32_f32
:
18743 case neon_cvt_flavour_u32_f32
:
18744 constraint (inst
.operands
[2].imm
> 32,
18745 _("immediate value out of range"));
18748 inst
.error
= BAD_FPU
;
18753 /* Fixed-point conversion with #0 immediate is encoded as an
18754 integer conversion. */
18755 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
18757 NEON_ENCODE (IMMED
, inst
);
18758 if (flavour
!= neon_cvt_flavour_invalid
)
18759 inst
.instruction
|= enctab
[flavour
];
18760 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18761 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18762 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18763 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18764 inst
.instruction
|= neon_quad (rs
) << 6;
18765 inst
.instruction
|= 1 << 21;
18766 if (flavour
< neon_cvt_flavour_s16_f16
)
18768 inst
.instruction
|= 1 << 21;
18769 immbits
= 32 - inst
.operands
[2].imm
;
18770 inst
.instruction
|= immbits
<< 16;
18774 inst
.instruction
|= 3 << 20;
18775 immbits
= 16 - inst
.operands
[2].imm
;
18776 inst
.instruction
|= immbits
<< 16;
18777 inst
.instruction
&= ~(1 << 9);
18780 neon_dp_fixup (&inst
);
18785 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
18786 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
18787 && (flavour
== neon_cvt_flavour_s16_f16
18788 || flavour
== neon_cvt_flavour_u16_f16
18789 || flavour
== neon_cvt_flavour_s32_f32
18790 || flavour
== neon_cvt_flavour_u32_f32
))
18792 if (!check_simd_pred_availability (TRUE
,
18793 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
18796 else if (mode
== neon_cvt_mode_z
18797 && (flavour
== neon_cvt_flavour_f16_s16
18798 || flavour
== neon_cvt_flavour_f16_u16
18799 || flavour
== neon_cvt_flavour_s16_f16
18800 || flavour
== neon_cvt_flavour_u16_f16
18801 || flavour
== neon_cvt_flavour_f32_u32
18802 || flavour
== neon_cvt_flavour_f32_s32
18803 || flavour
== neon_cvt_flavour_s32_f32
18804 || flavour
== neon_cvt_flavour_u32_f32
))
18806 if (!check_simd_pred_availability (TRUE
,
18807 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18810 /* fall through. */
18812 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
18815 NEON_ENCODE (FLOAT
, inst
);
18816 if (!check_simd_pred_availability (TRUE
,
18817 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
18820 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18821 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18822 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18823 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18824 inst
.instruction
|= neon_quad (rs
) << 6;
18825 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
18826 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
18827 inst
.instruction
|= mode
<< 8;
18828 if (flavour
== neon_cvt_flavour_u16_f16
18829 || flavour
== neon_cvt_flavour_s16_f16
)
18830 /* Mask off the original size bits and reencode them. */
18831 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
18834 inst
.instruction
|= 0xfc000000;
18836 inst
.instruction
|= 0xf0000000;
18842 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
18843 0x100, 0x180, 0x0, 0x080};
18845 NEON_ENCODE (INTEGER
, inst
);
18847 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18849 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18853 if (flavour
!= neon_cvt_flavour_invalid
)
18854 inst
.instruction
|= enctab
[flavour
];
18856 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18857 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18858 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18859 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18860 inst
.instruction
|= neon_quad (rs
) << 6;
18861 if (flavour
>= neon_cvt_flavour_s16_f16
18862 && flavour
<= neon_cvt_flavour_f16_u16
)
18863 /* Half precision. */
18864 inst
.instruction
|= 1 << 18;
18866 inst
.instruction
|= 2 << 18;
18868 neon_dp_fixup (&inst
);
18873 /* Half-precision conversions for Advanced SIMD -- neon. */
18876 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18880 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
18882 as_bad (_("operand size must match register width"));
18887 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
18889 as_bad (_("operand size must match register width"));
18894 inst
.instruction
= 0x3b60600;
18896 inst
.instruction
= 0x3b60700;
18898 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18899 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18900 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18901 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18902 neon_dp_fixup (&inst
);
18906 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
18907 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
18908 do_vfp_nsyn_cvt (rs
, flavour
);
18910 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
18915 do_neon_cvtr (void)
18917 do_neon_cvt_1 (neon_cvt_mode_x
);
18923 do_neon_cvt_1 (neon_cvt_mode_z
);
18927 do_neon_cvta (void)
18929 do_neon_cvt_1 (neon_cvt_mode_a
);
18933 do_neon_cvtn (void)
18935 do_neon_cvt_1 (neon_cvt_mode_n
);
18939 do_neon_cvtp (void)
18941 do_neon_cvt_1 (neon_cvt_mode_p
);
18945 do_neon_cvtm (void)
18947 do_neon_cvt_1 (neon_cvt_mode_m
);
18951 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
18954 mark_feature_used (&fpu_vfp_ext_armv8
);
18956 encode_arm_vfp_reg (inst
.operands
[0].reg
,
18957 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
18958 encode_arm_vfp_reg (inst
.operands
[1].reg
,
18959 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
18960 inst
.instruction
|= to
? 0x10000 : 0;
18961 inst
.instruction
|= t
? 0x80 : 0;
18962 inst
.instruction
|= is_double
? 0x100 : 0;
18963 do_vfp_cond_or_thumb ();
18967 do_neon_cvttb_1 (bfd_boolean t
)
18969 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
18970 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
18974 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
18976 int single_to_half
= 0;
18977 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_ARCH
))
18980 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18982 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18983 && (flavour
== neon_cvt_flavour_u16_f16
18984 || flavour
== neon_cvt_flavour_s16_f16
18985 || flavour
== neon_cvt_flavour_f16_s16
18986 || flavour
== neon_cvt_flavour_f16_u16
18987 || flavour
== neon_cvt_flavour_u32_f32
18988 || flavour
== neon_cvt_flavour_s32_f32
18989 || flavour
== neon_cvt_flavour_f32_s32
18990 || flavour
== neon_cvt_flavour_f32_u32
))
18993 inst
.instruction
= N_MNEM_vcvt
;
18994 set_pred_insn_type (INSIDE_VPT_INSN
);
18995 do_neon_cvt_1 (neon_cvt_mode_z
);
18998 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
18999 single_to_half
= 1;
19000 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
19002 first_error (BAD_FPU
);
19006 inst
.instruction
= 0xee3f0e01;
19007 inst
.instruction
|= single_to_half
<< 28;
19008 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19009 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
19010 inst
.instruction
|= t
<< 12;
19011 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19012 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
19015 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
19018 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
19020 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
19023 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
19025 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
19027 /* The VCVTB and VCVTT instructions with D-register operands
19028 don't work for SP only targets. */
19029 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19033 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
19035 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
19037 /* The VCVTB and VCVTT instructions with D-register operands
19038 don't work for SP only targets. */
19039 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19043 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
19050 do_neon_cvtb (void)
19052 do_neon_cvttb_1 (FALSE
);
19057 do_neon_cvtt (void)
19059 do_neon_cvttb_1 (TRUE
);
19063 neon_move_immediate (void)
19065 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
19066 struct neon_type_el et
= neon_check_type (2, rs
,
19067 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
19068 unsigned immlo
, immhi
= 0, immbits
;
19069 int op
, cmode
, float_p
;
19071 constraint (et
.type
== NT_invtype
,
19072 _("operand size must be specified for immediate VMOV"));
19074 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
19075 op
= (inst
.instruction
& (1 << 5)) != 0;
19077 immlo
= inst
.operands
[1].imm
;
19078 if (inst
.operands
[1].regisimm
)
19079 immhi
= inst
.operands
[1].reg
;
19081 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
19082 _("immediate has bits set outside the operand size"));
19084 float_p
= inst
.operands
[1].immisfloat
;
19086 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
19087 et
.size
, et
.type
)) == FAIL
)
19089 /* Invert relevant bits only. */
19090 neon_invert_size (&immlo
, &immhi
, et
.size
);
19091 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
19092 with one or the other; those cases are caught by
19093 neon_cmode_for_move_imm. */
19095 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
19096 &op
, et
.size
, et
.type
)) == FAIL
)
19098 first_error (_("immediate out of range"));
19103 inst
.instruction
&= ~(1 << 5);
19104 inst
.instruction
|= op
<< 5;
19106 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19107 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19108 inst
.instruction
|= neon_quad (rs
) << 6;
19109 inst
.instruction
|= cmode
<< 8;
19111 neon_write_immbits (immbits
);
19117 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19120 if (inst
.operands
[1].isreg
)
19122 enum neon_shape rs
;
19123 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19124 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19126 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19128 NEON_ENCODE (INTEGER
, inst
);
19129 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19130 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19131 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19132 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19133 inst
.instruction
|= neon_quad (rs
) << 6;
19137 NEON_ENCODE (IMMED
, inst
);
19138 neon_move_immediate ();
19141 neon_dp_fixup (&inst
);
19143 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19145 constraint (!inst
.operands
[1].isreg
&& !inst
.operands
[0].isquad
, BAD_FPU
);
19146 constraint ((inst
.instruction
& 0xd00) == 0xd00,
19147 _("immediate value out of range"));
19151 /* Encode instructions of form:
19153 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
19154 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
19157 neon_mixed_length (struct neon_type_el et
, unsigned size
)
19159 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19160 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19161 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19162 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19163 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19164 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19165 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
19166 inst
.instruction
|= neon_logbits (size
) << 20;
19168 neon_dp_fixup (&inst
);
19172 do_neon_dyadic_long (void)
19174 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
19177 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
19180 NEON_ENCODE (INTEGER
, inst
);
19181 /* FIXME: Type checking for lengthening op. */
19182 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19183 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19184 neon_mixed_length (et
, et
.size
);
19186 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19187 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
19189 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
19190 in an IT block with le/lt conditions. */
19192 if (inst
.cond
== 0xf)
19194 else if (inst
.cond
== 0x10)
19197 inst
.pred_insn_type
= INSIDE_IT_INSN
;
19199 if (inst
.instruction
== N_MNEM_vaddl
)
19201 inst
.instruction
= N_MNEM_vadd
;
19202 do_neon_addsub_if_i ();
19204 else if (inst
.instruction
== N_MNEM_vsubl
)
19206 inst
.instruction
= N_MNEM_vsub
;
19207 do_neon_addsub_if_i ();
19209 else if (inst
.instruction
== N_MNEM_vabdl
)
19211 inst
.instruction
= N_MNEM_vabd
;
19212 do_neon_dyadic_if_su ();
19216 first_error (BAD_FPU
);
19220 do_neon_abal (void)
19222 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19223 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19224 neon_mixed_length (et
, et
.size
);
19228 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
19230 if (inst
.operands
[2].isscalar
)
19232 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
19233 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
19234 NEON_ENCODE (SCALAR
, inst
);
19235 neon_mul_mac (et
, et
.type
== NT_unsigned
);
19239 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19240 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
19241 NEON_ENCODE (INTEGER
, inst
);
19242 neon_mixed_length (et
, et
.size
);
19247 do_neon_mac_maybe_scalar_long (void)
19249 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
19252 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19253 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
19256 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
19258 unsigned regno
= NEON_SCALAR_REG (scalar
);
19259 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
19263 if (regno
> 7 || elno
> 3)
19266 return ((regno
& 0x7)
19267 | ((elno
& 0x1) << 3)
19268 | (((elno
>> 1) & 0x1) << 5));
19272 if (regno
> 15 || elno
> 1)
19275 return (((regno
& 0x1) << 5)
19276 | ((regno
>> 1) & 0x7)
19277 | ((elno
& 0x1) << 3));
19281 first_error (_("scalar out of range for multiply instruction"));
19286 do_neon_fmac_maybe_scalar_long (int subtype
)
19288 enum neon_shape rs
;
19290 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
19291 field (bits[21:20]) has different meaning. For scalar index variant, it's
19292 used to differentiate add and subtract, otherwise it's with fixed value
19296 if (inst
.cond
!= COND_ALWAYS
)
19297 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19298 "behaviour is UNPREDICTABLE"));
19300 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
19303 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19306 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19307 be a scalar index register. */
19308 if (inst
.operands
[2].isscalar
)
19310 high8
= 0xfe000000;
19313 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
19317 high8
= 0xfc000000;
19320 inst
.instruction
|= (0x1 << 23);
19321 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
19324 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
19326 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19327 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19328 so we simply pass -1 as size. */
19329 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
19330 neon_three_same (quad_p
, 0, size
);
19332 /* Undo neon_dp_fixup. Redo the high eight bits. */
19333 inst
.instruction
&= 0x00ffffff;
19334 inst
.instruction
|= high8
;
19336 #define LOW1(R) ((R) & 0x1)
19337 #define HI4(R) (((R) >> 1) & 0xf)
19338 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19339 whether the instruction is in Q form and whether Vm is a scalar indexed
19341 if (inst
.operands
[2].isscalar
)
19344 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
19345 inst
.instruction
&= 0xffffffd0;
19346 inst
.instruction
|= rm
;
19350 /* Redo Rn as well. */
19351 inst
.instruction
&= 0xfff0ff7f;
19352 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19353 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19358 /* Redo Rn and Rm. */
19359 inst
.instruction
&= 0xfff0ff50;
19360 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19361 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19362 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
19363 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
19368 do_neon_vfmal (void)
19370 return do_neon_fmac_maybe_scalar_long (0);
19374 do_neon_vfmsl (void)
19376 return do_neon_fmac_maybe_scalar_long (1);
19380 do_neon_dyadic_wide (void)
19382 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
19383 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19384 neon_mixed_length (et
, et
.size
);
19388 do_neon_dyadic_narrow (void)
19390 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19391 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
19392 /* Operand sign is unimportant, and the U bit is part of the opcode,
19393 so force the operand type to integer. */
19394 et
.type
= NT_integer
;
19395 neon_mixed_length (et
, et
.size
/ 2);
19399 do_neon_mul_sat_scalar_long (void)
19401 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
19405 do_neon_vmull (void)
19407 if (inst
.operands
[2].isscalar
)
19408 do_neon_mac_maybe_scalar_long ();
19411 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19412 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
19414 if (et
.type
== NT_poly
)
19415 NEON_ENCODE (POLY
, inst
);
19417 NEON_ENCODE (INTEGER
, inst
);
19419 /* For polynomial encoding the U bit must be zero, and the size must
19420 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19421 obviously, as 0b10). */
19424 /* Check we're on the correct architecture. */
19425 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
19427 _("Instruction form not available on this architecture.");
19432 neon_mixed_length (et
, et
.size
);
19439 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19440 struct neon_type_el et
= neon_check_type (3, rs
,
19441 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
19442 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
19444 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
19445 _("shift out of range"));
19446 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19447 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19448 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19449 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19450 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19451 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19452 inst
.instruction
|= neon_quad (rs
) << 6;
19453 inst
.instruction
|= imm
<< 8;
19455 neon_dp_fixup (&inst
);
19461 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19464 enum neon_shape rs
;
19465 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19466 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19468 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19470 struct neon_type_el et
= neon_check_type (2, rs
,
19471 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19473 unsigned op
= (inst
.instruction
>> 7) & 3;
19474 /* N (width of reversed regions) is encoded as part of the bitmask. We
19475 extract it here to check the elements to be reversed are smaller.
19476 Otherwise we'd get a reserved instruction. */
19477 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
19479 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
) && elsize
== 64
19480 && inst
.operands
[0].reg
== inst
.operands
[1].reg
)
19481 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19482 " operands makes instruction UNPREDICTABLE"));
19484 gas_assert (elsize
!= 0);
19485 constraint (et
.size
>= elsize
,
19486 _("elements must be smaller than reversal region"));
19487 neon_two_same (neon_quad (rs
), 1, et
.size
);
19493 if (inst
.operands
[1].isscalar
)
19495 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19497 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
19498 struct neon_type_el et
= neon_check_type (2, rs
,
19499 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19500 unsigned sizebits
= et
.size
>> 3;
19501 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19502 int logsize
= neon_logbits (et
.size
);
19503 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
19505 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
19508 NEON_ENCODE (SCALAR
, inst
);
19509 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19510 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19511 inst
.instruction
|= LOW4 (dm
);
19512 inst
.instruction
|= HI1 (dm
) << 5;
19513 inst
.instruction
|= neon_quad (rs
) << 6;
19514 inst
.instruction
|= x
<< 17;
19515 inst
.instruction
|= sizebits
<< 16;
19517 neon_dp_fixup (&inst
);
19521 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
19522 struct neon_type_el et
= neon_check_type (2, rs
,
19523 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19526 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
))
19530 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19533 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19535 if (inst
.operands
[1].reg
== REG_SP
)
19536 as_tsktsk (MVE_BAD_SP
);
19537 else if (inst
.operands
[1].reg
== REG_PC
)
19538 as_tsktsk (MVE_BAD_PC
);
19541 /* Duplicate ARM register to lanes of vector. */
19542 NEON_ENCODE (ARMREG
, inst
);
19545 case 8: inst
.instruction
|= 0x400000; break;
19546 case 16: inst
.instruction
|= 0x000020; break;
19547 case 32: inst
.instruction
|= 0x000000; break;
19550 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
19551 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
19552 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
19553 inst
.instruction
|= neon_quad (rs
) << 21;
19554 /* The encoding for this instruction is identical for the ARM and Thumb
19555 variants, except for the condition field. */
19556 do_vfp_cond_or_thumb ();
19561 do_mve_mov (int toQ
)
19563 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19565 if (inst
.cond
> COND_ALWAYS
)
19566 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
19568 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
19577 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
19578 _("Index one must be [2,3] and index two must be two less than"
19580 constraint (inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
19581 _("General purpose registers may not be the same"));
19582 constraint (inst
.operands
[Rt
].reg
== REG_SP
19583 || inst
.operands
[Rt2
].reg
== REG_SP
,
19585 constraint (inst
.operands
[Rt
].reg
== REG_PC
19586 || inst
.operands
[Rt2
].reg
== REG_PC
,
19589 inst
.instruction
= 0xec000f00;
19590 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
19591 inst
.instruction
|= !!toQ
<< 20;
19592 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
19593 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
19594 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
19595 inst
.instruction
|= inst
.operands
[Rt
].reg
;
19601 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19604 if (inst
.cond
> COND_ALWAYS
)
19605 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
19607 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
19609 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
19612 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19613 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
19614 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19615 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19616 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19621 /* VMOV has particularly many variations. It can be one of:
19622 0. VMOV<c><q> <Qd>, <Qm>
19623 1. VMOV<c><q> <Dd>, <Dm>
19624 (Register operations, which are VORR with Rm = Rn.)
19625 2. VMOV<c><q>.<dt> <Qd>, #<imm>
19626 3. VMOV<c><q>.<dt> <Dd>, #<imm>
19628 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
19629 (ARM register to scalar.)
19630 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
19631 (Two ARM registers to vector.)
19632 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
19633 (Scalar to ARM register.)
19634 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
19635 (Vector to two ARM registers.)
19636 8. VMOV.F32 <Sd>, <Sm>
19637 9. VMOV.F64 <Dd>, <Dm>
19638 (VFP register moves.)
19639 10. VMOV.F32 <Sd>, #imm
19640 11. VMOV.F64 <Dd>, #imm
19641 (VFP float immediate load.)
19642 12. VMOV <Rd>, <Sm>
19643 (VFP single to ARM reg.)
19644 13. VMOV <Sd>, <Rm>
19645 (ARM reg to VFP single.)
19646 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
19647 (Two ARM regs to two VFP singles.)
19648 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
19649 (Two VFP singles to two ARM regs.)
19650 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
19651 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
19652 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
19653 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
19655 These cases can be disambiguated using neon_select_shape, except cases 1/9
19656 and 3/11 which depend on the operand type too.
19658 All the encoded bits are hardcoded by this function.
19660 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
19661 Cases 5, 7 may be used with VFPv2 and above.
19663 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
19664 can specify a type where it doesn't make sense to, and is ignored). */
19669 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
19670 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
19671 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
19672 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
19674 struct neon_type_el et
;
19675 const char *ldconst
= 0;
19679 case NS_DD
: /* case 1/9. */
19680 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
19681 /* It is not an error here if no type is given. */
19683 if (et
.type
== NT_float
&& et
.size
== 64)
19685 do_vfp_nsyn_opcode ("fcpyd");
19688 /* fall through. */
19690 case NS_QQ
: /* case 0/1. */
19692 if (!check_simd_pred_availability (FALSE
,
19693 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19695 /* The architecture manual I have doesn't explicitly state which
19696 value the U bit should have for register->register moves, but
19697 the equivalent VORR instruction has U = 0, so do that. */
19698 inst
.instruction
= 0x0200110;
19699 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19700 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19701 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19702 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19703 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19704 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19705 inst
.instruction
|= neon_quad (rs
) << 6;
19707 neon_dp_fixup (&inst
);
19711 case NS_DI
: /* case 3/11. */
19712 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
19714 if (et
.type
== NT_float
&& et
.size
== 64)
19716 /* case 11 (fconstd). */
19717 ldconst
= "fconstd";
19718 goto encode_fconstd
;
19720 /* fall through. */
19722 case NS_QI
: /* case 2/3. */
19723 if (!check_simd_pred_availability (FALSE
,
19724 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19726 inst
.instruction
= 0x0800010;
19727 neon_move_immediate ();
19728 neon_dp_fixup (&inst
);
19731 case NS_SR
: /* case 4. */
19733 unsigned bcdebits
= 0;
19735 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
19736 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
19738 /* .<size> is optional here, defaulting to .32. */
19739 if (inst
.vectype
.elems
== 0
19740 && inst
.operands
[0].vectype
.type
== NT_invtype
19741 && inst
.operands
[1].vectype
.type
== NT_invtype
)
19743 inst
.vectype
.el
[0].type
= NT_untyped
;
19744 inst
.vectype
.el
[0].size
= 32;
19745 inst
.vectype
.elems
= 1;
19748 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19749 logsize
= neon_logbits (et
.size
);
19753 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19754 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
19759 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
19760 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19764 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19766 if (inst
.operands
[1].reg
== REG_SP
)
19767 as_tsktsk (MVE_BAD_SP
);
19768 else if (inst
.operands
[1].reg
== REG_PC
)
19769 as_tsktsk (MVE_BAD_PC
);
19771 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
19773 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
19774 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
19779 case 8: bcdebits
= 0x8; break;
19780 case 16: bcdebits
= 0x1; break;
19781 case 32: bcdebits
= 0x0; break;
19785 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
19787 inst
.instruction
= 0xe000b10;
19788 do_vfp_cond_or_thumb ();
19789 inst
.instruction
|= LOW4 (dn
) << 16;
19790 inst
.instruction
|= HI1 (dn
) << 7;
19791 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
19792 inst
.instruction
|= (bcdebits
& 3) << 5;
19793 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
19794 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
19798 case NS_DRR
: /* case 5 (fmdrr). */
19799 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19800 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19803 inst
.instruction
= 0xc400b10;
19804 do_vfp_cond_or_thumb ();
19805 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
19806 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
19807 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
19808 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
19811 case NS_RS
: /* case 6. */
19814 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19815 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
19816 unsigned abcdebits
= 0;
19818 /* .<dt> is optional here, defaulting to .32. */
19819 if (inst
.vectype
.elems
== 0
19820 && inst
.operands
[0].vectype
.type
== NT_invtype
19821 && inst
.operands
[1].vectype
.type
== NT_invtype
)
19823 inst
.vectype
.el
[0].type
= NT_untyped
;
19824 inst
.vectype
.el
[0].size
= 32;
19825 inst
.vectype
.elems
= 1;
19828 et
= neon_check_type (2, NS_NULL
,
19829 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
19830 logsize
= neon_logbits (et
.size
);
19834 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19835 && vfp_or_neon_is_neon (NEON_CHECK_CC
19836 | NEON_CHECK_ARCH
) == FAIL
)
19841 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
19842 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19846 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19848 if (inst
.operands
[0].reg
== REG_SP
)
19849 as_tsktsk (MVE_BAD_SP
);
19850 else if (inst
.operands
[0].reg
== REG_PC
)
19851 as_tsktsk (MVE_BAD_PC
);
19854 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
19856 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
19857 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
19861 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
19862 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
19863 case 32: abcdebits
= 0x00; break;
19867 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
19868 inst
.instruction
= 0xe100b10;
19869 do_vfp_cond_or_thumb ();
19870 inst
.instruction
|= LOW4 (dn
) << 16;
19871 inst
.instruction
|= HI1 (dn
) << 7;
19872 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
19873 inst
.instruction
|= (abcdebits
& 3) << 5;
19874 inst
.instruction
|= (abcdebits
>> 2) << 21;
19875 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
19879 case NS_RRD
: /* case 7 (fmrrd). */
19880 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19881 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19884 inst
.instruction
= 0xc500b10;
19885 do_vfp_cond_or_thumb ();
19886 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
19887 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
19888 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19889 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19892 case NS_FF
: /* case 8 (fcpys). */
19893 do_vfp_nsyn_opcode ("fcpys");
19897 case NS_FI
: /* case 10 (fconsts). */
19898 ldconst
= "fconsts";
19900 if (!inst
.operands
[1].immisfloat
)
19903 /* Immediate has to fit in 8 bits so float is enough. */
19904 float imm
= (float) inst
.operands
[1].imm
;
19905 memcpy (&new_imm
, &imm
, sizeof (float));
19906 /* But the assembly may have been written to provide an integer
19907 bit pattern that equates to a float, so check that the
19908 conversion has worked. */
19909 if (is_quarter_float (new_imm
))
19911 if (is_quarter_float (inst
.operands
[1].imm
))
19912 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
19914 inst
.operands
[1].imm
= new_imm
;
19915 inst
.operands
[1].immisfloat
= 1;
19919 if (is_quarter_float (inst
.operands
[1].imm
))
19921 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
19922 do_vfp_nsyn_opcode (ldconst
);
19924 /* ARMv8.2 fp16 vmov.f16 instruction. */
19926 do_scalar_fp16_v82_encode ();
19929 first_error (_("immediate out of range"));
19933 case NS_RF
: /* case 12 (fmrs). */
19934 do_vfp_nsyn_opcode ("fmrs");
19935 /* ARMv8.2 fp16 vmov.f16 instruction. */
19937 do_scalar_fp16_v82_encode ();
19941 case NS_FR
: /* case 13 (fmsr). */
19942 do_vfp_nsyn_opcode ("fmsr");
19943 /* ARMv8.2 fp16 vmov.f16 instruction. */
19945 do_scalar_fp16_v82_encode ();
19955 /* The encoders for the fmrrs and fmsrr instructions expect three operands
19956 (one of which is a list), but we have parsed four. Do some fiddling to
19957 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
19959 case NS_RRFF
: /* case 14 (fmrrs). */
19960 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19961 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19963 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
19964 _("VFP registers must be adjacent"));
19965 inst
.operands
[2].imm
= 2;
19966 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
19967 do_vfp_nsyn_opcode ("fmrrs");
19970 case NS_FFRR
: /* case 15 (fmsrr). */
19971 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19972 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19974 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
19975 _("VFP registers must be adjacent"));
19976 inst
.operands
[1] = inst
.operands
[2];
19977 inst
.operands
[2] = inst
.operands
[3];
19978 inst
.operands
[0].imm
= 2;
19979 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
19980 do_vfp_nsyn_opcode ("fmsrr");
19984 /* neon_select_shape has determined that the instruction
19985 shape is wrong and has already set the error message. */
19996 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
19997 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
19998 && !inst
.operands
[2].present
))
20000 inst
.instruction
= 0;
20003 set_pred_insn_type (INSIDE_IT_INSN
);
20008 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20011 if (inst
.cond
!= COND_ALWAYS
)
20012 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
20014 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
20015 | N_S16
| N_U16
| N_KEY
);
20017 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
20018 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20019 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
20020 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20021 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20022 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20027 do_neon_rshift_round_imm (void)
20029 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20032 enum neon_shape rs
;
20033 struct neon_type_el et
;
20035 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20037 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
20038 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
20042 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
20043 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
20045 int imm
= inst
.operands
[2].imm
;
20047 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
20050 inst
.operands
[2].present
= 0;
20055 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
20056 _("immediate out of range for shift"));
20057 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
20062 do_neon_movhf (void)
20064 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
20065 constraint (rs
!= NS_HH
, _("invalid suffix"));
20067 if (inst
.cond
!= COND_ALWAYS
)
20071 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
20072 " the behaviour is UNPREDICTABLE"));
20076 inst
.error
= BAD_COND
;
20081 do_vfp_sp_monadic ();
20084 inst
.instruction
|= 0xf0000000;
20088 do_neon_movl (void)
20090 struct neon_type_el et
= neon_check_type (2, NS_QD
,
20091 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
20092 unsigned sizebits
= et
.size
>> 3;
20093 inst
.instruction
|= sizebits
<< 19;
20094 neon_two_same (0, et
.type
== NT_unsigned
, -1);
20100 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20101 struct neon_type_el et
= neon_check_type (2, rs
,
20102 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20103 NEON_ENCODE (INTEGER
, inst
);
20104 neon_two_same (neon_quad (rs
), 1, et
.size
);
20108 do_neon_zip_uzp (void)
20110 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20111 struct neon_type_el et
= neon_check_type (2, rs
,
20112 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20113 if (rs
== NS_DD
&& et
.size
== 32)
20115 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
20116 inst
.instruction
= N_MNEM_vtrn
;
20120 neon_two_same (neon_quad (rs
), 1, et
.size
);
20124 do_neon_sat_abs_neg (void)
20126 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20129 enum neon_shape rs
;
20130 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20131 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20133 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20134 struct neon_type_el et
= neon_check_type (2, rs
,
20135 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20136 neon_two_same (neon_quad (rs
), 1, et
.size
);
20140 do_neon_pair_long (void)
20142 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20143 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
20144 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
20145 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
20146 neon_two_same (neon_quad (rs
), 1, et
.size
);
20150 do_neon_recip_est (void)
20152 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20153 struct neon_type_el et
= neon_check_type (2, rs
,
20154 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
20155 inst
.instruction
|= (et
.type
== NT_float
) << 8;
20156 neon_two_same (neon_quad (rs
), 1, et
.size
);
20162 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20165 enum neon_shape rs
;
20166 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20167 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20169 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20171 struct neon_type_el et
= neon_check_type (2, rs
,
20172 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20173 neon_two_same (neon_quad (rs
), 1, et
.size
);
20179 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20182 enum neon_shape rs
;
20183 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20184 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20186 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20188 struct neon_type_el et
= neon_check_type (2, rs
,
20189 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
20190 neon_two_same (neon_quad (rs
), 1, et
.size
);
20196 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20197 struct neon_type_el et
= neon_check_type (2, rs
,
20198 N_EQK
| N_INT
, N_8
| N_KEY
);
20199 neon_two_same (neon_quad (rs
), 1, et
.size
);
20205 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20206 neon_two_same (neon_quad (rs
), 1, -1);
20210 do_neon_tbl_tbx (void)
20212 unsigned listlenbits
;
20213 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
20215 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
20217 first_error (_("bad list length for table lookup"));
20221 listlenbits
= inst
.operands
[1].imm
- 1;
20222 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20223 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20224 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20225 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20226 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20227 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20228 inst
.instruction
|= listlenbits
<< 8;
20230 neon_dp_fixup (&inst
);
20234 do_neon_ldm_stm (void)
20236 /* P, U and L bits are part of bitmask. */
20237 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
20238 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
20240 if (inst
.operands
[1].issingle
)
20242 do_vfp_nsyn_ldm_stm (is_dbmode
);
20246 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
20247 _("writeback (!) must be used for VLDMDB and VSTMDB"));
20249 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20250 _("register list must contain at least 1 and at most 16 "
20253 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
20254 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
20255 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
20256 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
20258 inst
.instruction
|= offsetbits
;
20260 do_vfp_cond_or_thumb ();
20264 do_neon_ldr_str (void)
20266 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
20268 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20269 And is UNPREDICTABLE in thumb mode. */
20271 && inst
.operands
[1].reg
== REG_PC
20272 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
20275 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20276 else if (warn_on_deprecated
)
20277 as_tsktsk (_("Use of PC here is deprecated"));
20280 if (inst
.operands
[0].issingle
)
20283 do_vfp_nsyn_opcode ("flds");
20285 do_vfp_nsyn_opcode ("fsts");
20287 /* ARMv8.2 vldr.16/vstr.16 instruction. */
20288 if (inst
.vectype
.el
[0].size
== 16)
20289 do_scalar_fp16_v82_encode ();
20294 do_vfp_nsyn_opcode ("fldd");
20296 do_vfp_nsyn_opcode ("fstd");
20301 do_t_vldr_vstr_sysreg (void)
20303 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
20304 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
20306 /* Use of PC is UNPREDICTABLE. */
20307 if (inst
.operands
[1].reg
== REG_PC
)
20308 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20310 if (inst
.operands
[1].immisreg
)
20311 inst
.error
= _("instruction does not accept register index");
20313 if (!inst
.operands
[1].isreg
)
20314 inst
.error
= _("instruction does not accept PC-relative addressing");
20316 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
20317 inst
.error
= _("immediate value out of range");
20319 inst
.instruction
= 0xec000f80;
20321 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
20322 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
20323 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
20324 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
20328 do_vldr_vstr (void)
20330 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
20332 /* VLDR/VSTR (System Register). */
20335 if (!mark_feature_used (&arm_ext_v8_1m_main
))
20336 as_bad (_("Instruction not permitted on this architecture"));
20338 do_t_vldr_vstr_sysreg ();
20343 if (!mark_feature_used (&fpu_vfp_ext_v1xd
))
20344 as_bad (_("Instruction not permitted on this architecture"));
20345 do_neon_ldr_str ();
20349 /* "interleave" version also handles non-interleaving register VLD1/VST1
20353 do_neon_ld_st_interleave (void)
20355 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
20356 N_8
| N_16
| N_32
| N_64
);
20357 unsigned alignbits
= 0;
20359 /* The bits in this table go:
20360 0: register stride of one (0) or two (1)
20361 1,2: register list length, minus one (1, 2, 3, 4).
20362 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20363 We use -1 for invalid entries. */
20364 const int typetable
[] =
20366 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20367 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20368 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20369 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20373 if (et
.type
== NT_invtype
)
20376 if (inst
.operands
[1].immisalign
)
20377 switch (inst
.operands
[1].imm
>> 8)
20379 case 64: alignbits
= 1; break;
20381 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
20382 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20383 goto bad_alignment
;
20387 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20388 goto bad_alignment
;
20393 first_error (_("bad alignment"));
20397 inst
.instruction
|= alignbits
<< 4;
20398 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20400 /* Bits [4:6] of the immediate in a list specifier encode register stride
20401 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20402 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20403 up the right value for "type" in a table based on this value and the given
20404 list style, then stick it back. */
20405 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
20406 | (((inst
.instruction
>> 8) & 3) << 3);
20408 typebits
= typetable
[idx
];
20410 constraint (typebits
== -1, _("bad list type for instruction"));
20411 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
20414 inst
.instruction
&= ~0xf00;
20415 inst
.instruction
|= typebits
<< 8;
20418 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20419 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20420 otherwise. The variable arguments are a list of pairs of legal (size, align)
20421 values, terminated with -1. */
20424 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
20427 int result
= FAIL
, thissize
, thisalign
;
20429 if (!inst
.operands
[1].immisalign
)
20435 va_start (ap
, do_alignment
);
20439 thissize
= va_arg (ap
, int);
20440 if (thissize
== -1)
20442 thisalign
= va_arg (ap
, int);
20444 if (size
== thissize
&& align
== thisalign
)
20447 while (result
!= SUCCESS
);
20451 if (result
== SUCCESS
)
20454 first_error (_("unsupported alignment for instruction"));
20460 do_neon_ld_st_lane (void)
20462 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20463 int align_good
, do_alignment
= 0;
20464 int logsize
= neon_logbits (et
.size
);
20465 int align
= inst
.operands
[1].imm
>> 8;
20466 int n
= (inst
.instruction
>> 8) & 3;
20467 int max_el
= 64 / et
.size
;
20469 if (et
.type
== NT_invtype
)
20472 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
20473 _("bad list length"));
20474 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
20475 _("scalar index out of range"));
20476 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
20478 _("stride of 2 unavailable when element size is 8"));
20482 case 0: /* VLD1 / VST1. */
20483 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
20485 if (align_good
== FAIL
)
20489 unsigned alignbits
= 0;
20492 case 16: alignbits
= 0x1; break;
20493 case 32: alignbits
= 0x3; break;
20496 inst
.instruction
|= alignbits
<< 4;
20500 case 1: /* VLD2 / VST2. */
20501 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
20502 16, 32, 32, 64, -1);
20503 if (align_good
== FAIL
)
20506 inst
.instruction
|= 1 << 4;
20509 case 2: /* VLD3 / VST3. */
20510 constraint (inst
.operands
[1].immisalign
,
20511 _("can't use alignment with this instruction"));
20514 case 3: /* VLD4 / VST4. */
20515 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20516 16, 64, 32, 64, 32, 128, -1);
20517 if (align_good
== FAIL
)
20521 unsigned alignbits
= 0;
20524 case 8: alignbits
= 0x1; break;
20525 case 16: alignbits
= 0x1; break;
20526 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
20529 inst
.instruction
|= alignbits
<< 4;
20536 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
20537 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20538 inst
.instruction
|= 1 << (4 + logsize
);
20540 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
20541 inst
.instruction
|= logsize
<< 10;
20544 /* Encode single n-element structure to all lanes VLD<n> instructions. */
20547 do_neon_ld_dup (void)
20549 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20550 int align_good
, do_alignment
= 0;
20552 if (et
.type
== NT_invtype
)
20555 switch ((inst
.instruction
>> 8) & 3)
20557 case 0: /* VLD1. */
20558 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
20559 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20560 &do_alignment
, 16, 16, 32, 32, -1);
20561 if (align_good
== FAIL
)
20563 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
20566 case 2: inst
.instruction
|= 1 << 5; break;
20567 default: first_error (_("bad list length")); return;
20569 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20572 case 1: /* VLD2. */
20573 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20574 &do_alignment
, 8, 16, 16, 32, 32, 64,
20576 if (align_good
== FAIL
)
20578 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
20579 _("bad list length"));
20580 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20581 inst
.instruction
|= 1 << 5;
20582 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20585 case 2: /* VLD3. */
20586 constraint (inst
.operands
[1].immisalign
,
20587 _("can't use alignment with this instruction"));
20588 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
20589 _("bad list length"));
20590 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20591 inst
.instruction
|= 1 << 5;
20592 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20595 case 3: /* VLD4. */
20597 int align
= inst
.operands
[1].imm
>> 8;
20598 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20599 16, 64, 32, 64, 32, 128, -1);
20600 if (align_good
== FAIL
)
20602 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
20603 _("bad list length"));
20604 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20605 inst
.instruction
|= 1 << 5;
20606 if (et
.size
== 32 && align
== 128)
20607 inst
.instruction
|= 0x3 << 6;
20609 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20616 inst
.instruction
|= do_alignment
<< 4;
20619 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
20620 apart from bits [11:4]. */
20623 do_neon_ldx_stx (void)
20625 if (inst
.operands
[1].isreg
)
20626 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
20628 switch (NEON_LANE (inst
.operands
[0].imm
))
20630 case NEON_INTERLEAVE_LANES
:
20631 NEON_ENCODE (INTERLV
, inst
);
20632 do_neon_ld_st_interleave ();
20635 case NEON_ALL_LANES
:
20636 NEON_ENCODE (DUP
, inst
);
20637 if (inst
.instruction
== N_INV
)
20639 first_error ("only loads support such operands");
20646 NEON_ENCODE (LANE
, inst
);
20647 do_neon_ld_st_lane ();
20650 /* L bit comes from bit mask. */
20651 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20652 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20653 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
20655 if (inst
.operands
[1].postind
)
20657 int postreg
= inst
.operands
[1].imm
& 0xf;
20658 constraint (!inst
.operands
[1].immisreg
,
20659 _("post-index must be a register"));
20660 constraint (postreg
== 0xd || postreg
== 0xf,
20661 _("bad register for post-index"));
20662 inst
.instruction
|= postreg
;
20666 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
20667 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
20668 || inst
.relocs
[0].exp
.X_add_number
!= 0,
20671 if (inst
.operands
[1].writeback
)
20673 inst
.instruction
|= 0xd;
20676 inst
.instruction
|= 0xf;
20680 inst
.instruction
|= 0xf9000000;
20682 inst
.instruction
|= 0xf4000000;
20687 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
20689 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20690 D register operands. */
20691 if (neon_shape_class
[rs
] == SC_DOUBLE
)
20692 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20695 NEON_ENCODE (FPV8
, inst
);
20697 if (rs
== NS_FFF
|| rs
== NS_HHH
)
20699 do_vfp_sp_dyadic ();
20701 /* ARMv8.2 fp16 instruction. */
20703 do_scalar_fp16_v82_encode ();
20706 do_vfp_dp_rd_rn_rm ();
20709 inst
.instruction
|= 0x100;
20711 inst
.instruction
|= 0xf0000000;
20717 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20719 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
20720 first_error (_("invalid instruction shape"));
20726 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20727 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20729 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
20732 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
20735 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
20739 do_vrint_1 (enum neon_cvt_mode mode
)
20741 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
20742 struct neon_type_el et
;
20747 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20748 D register operands. */
20749 if (neon_shape_class
[rs
] == SC_DOUBLE
)
20750 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20753 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
20755 if (et
.type
!= NT_invtype
)
20757 /* VFP encodings. */
20758 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
20759 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
20760 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20762 NEON_ENCODE (FPV8
, inst
);
20763 if (rs
== NS_FF
|| rs
== NS_HH
)
20764 do_vfp_sp_monadic ();
20766 do_vfp_dp_rd_rm ();
20770 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
20771 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
20772 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
20773 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
20774 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
20775 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
20776 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
20780 inst
.instruction
|= (rs
== NS_DD
) << 8;
20781 do_vfp_cond_or_thumb ();
20783 /* ARMv8.2 fp16 vrint instruction. */
20785 do_scalar_fp16_v82_encode ();
20789 /* Neon encodings (or something broken...). */
20791 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
20793 if (et
.type
== NT_invtype
)
20796 if (!check_simd_pred_availability (TRUE
,
20797 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
20800 NEON_ENCODE (FLOAT
, inst
);
20802 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20803 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20804 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20805 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20806 inst
.instruction
|= neon_quad (rs
) << 6;
20807 /* Mask off the original size bits and reencode them. */
20808 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
20809 | neon_logbits (et
.size
) << 18);
20813 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
20814 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
20815 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
20816 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
20817 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
20818 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
20819 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
20824 inst
.instruction
|= 0xfc000000;
20826 inst
.instruction
|= 0xf0000000;
20833 do_vrint_1 (neon_cvt_mode_x
);
20839 do_vrint_1 (neon_cvt_mode_z
);
20845 do_vrint_1 (neon_cvt_mode_r
);
20851 do_vrint_1 (neon_cvt_mode_a
);
20857 do_vrint_1 (neon_cvt_mode_n
);
20863 do_vrint_1 (neon_cvt_mode_p
);
20869 do_vrint_1 (neon_cvt_mode_m
);
20873 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
20875 unsigned regno
= NEON_SCALAR_REG (opnd
);
20876 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
20878 if (elsize
== 16 && elno
< 2 && regno
< 16)
20879 return regno
| (elno
<< 4);
20880 else if (elsize
== 32 && elno
== 0)
20883 first_error (_("scalar out of range"));
20890 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
)
20891 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
20892 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
20893 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
20894 _("expression too complex"));
20895 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
20896 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
20897 _("immediate out of range"));
20900 if (!check_simd_pred_availability (TRUE
,
20901 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
20904 if (inst
.operands
[2].isscalar
)
20906 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
20907 first_error (_("invalid instruction shape"));
20908 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
20909 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
20910 N_KEY
| N_F16
| N_F32
).size
;
20911 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
20913 inst
.instruction
= 0xfe000800;
20914 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20915 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20916 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20917 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20918 inst
.instruction
|= LOW4 (m
);
20919 inst
.instruction
|= HI1 (m
) << 5;
20920 inst
.instruction
|= neon_quad (rs
) << 6;
20921 inst
.instruction
|= rot
<< 20;
20922 inst
.instruction
|= (size
== 32) << 23;
20926 enum neon_shape rs
;
20927 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
20928 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
20930 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
20932 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
20933 N_KEY
| N_F16
| N_F32
).size
;
20934 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
) && size
== 32
20935 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
20936 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
20937 as_tsktsk (BAD_MVE_SRCDEST
);
20939 neon_three_same (neon_quad (rs
), 0, -1);
20940 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
20941 inst
.instruction
|= 0xfc200800;
20942 inst
.instruction
|= rot
<< 23;
20943 inst
.instruction
|= (size
== 32) << 20;
20950 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20951 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
20952 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
20953 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
20954 _("expression too complex"));
20956 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
20957 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
20958 enum neon_shape rs
;
20959 struct neon_type_el et
;
20960 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20962 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
20963 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
);
20967 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
20968 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
| N_I8
20970 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
20971 as_tsktsk (_("Warning: 32-bit element size and same first and third "
20972 "operand makes instruction UNPREDICTABLE"));
20975 if (et
.type
== NT_invtype
)
20978 if (!check_simd_pred_availability (et
.type
== NT_float
,
20979 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
20982 if (et
.type
== NT_float
)
20984 neon_three_same (neon_quad (rs
), 0, -1);
20985 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
20986 inst
.instruction
|= 0xfc800800;
20987 inst
.instruction
|= (rot
== 270) << 24;
20988 inst
.instruction
|= (et
.size
== 32) << 20;
20992 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
20993 inst
.instruction
= 0xfe000f00;
20994 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20995 inst
.instruction
|= neon_logbits (et
.size
) << 20;
20996 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20997 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20998 inst
.instruction
|= (rot
== 270) << 12;
20999 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21000 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
21001 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
21006 /* Dot Product instructions encoding support. */
21009 do_neon_dotproduct (int unsigned_p
)
21011 enum neon_shape rs
;
21012 unsigned scalar_oprd2
= 0;
21015 if (inst
.cond
!= COND_ALWAYS
)
21016 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
21017 "is UNPREDICTABLE"));
21019 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
21022 /* Dot Product instructions are in three-same D/Q register format or the third
21023 operand can be a scalar index register. */
21024 if (inst
.operands
[2].isscalar
)
21026 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
21027 high8
= 0xfe000000;
21028 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21032 high8
= 0xfc000000;
21033 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21037 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
21039 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
21041 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
21042 Product instruction, so we pass 0 as the "ubit" parameter. And the
21043 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
21044 neon_three_same (neon_quad (rs
), 0, 32);
21046 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
21047 different NEON three-same encoding. */
21048 inst
.instruction
&= 0x00ffffff;
21049 inst
.instruction
|= high8
;
21050 /* Encode 'U' bit which indicates signedness. */
21051 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
21052 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
21053 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
21054 the instruction encoding. */
21055 if (inst
.operands
[2].isscalar
)
21057 inst
.instruction
&= 0xffffffd0;
21058 inst
.instruction
|= LOW4 (scalar_oprd2
);
21059 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
21063 /* Dot Product instructions for signed integer. */
21066 do_neon_dotproduct_s (void)
21068 return do_neon_dotproduct (0);
21071 /* Dot Product instructions for unsigned integer. */
21074 do_neon_dotproduct_u (void)
21076 return do_neon_dotproduct (1);
21079 /* Crypto v1 instructions. */
21081 do_crypto_2op_1 (unsigned elttype
, int op
)
21083 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21085 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
21091 NEON_ENCODE (INTEGER
, inst
);
21092 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21093 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21094 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
21095 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
21097 inst
.instruction
|= op
<< 6;
21100 inst
.instruction
|= 0xfc000000;
21102 inst
.instruction
|= 0xf0000000;
21106 do_crypto_3op_1 (int u
, int op
)
21108 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21110 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
21111 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
21116 NEON_ENCODE (INTEGER
, inst
);
21117 neon_three_same (1, u
, 8 << op
);
21123 do_crypto_2op_1 (N_8
, 0);
21129 do_crypto_2op_1 (N_8
, 1);
21135 do_crypto_2op_1 (N_8
, 2);
21141 do_crypto_2op_1 (N_8
, 3);
21147 do_crypto_3op_1 (0, 0);
21153 do_crypto_3op_1 (0, 1);
21159 do_crypto_3op_1 (0, 2);
21165 do_crypto_3op_1 (0, 3);
21171 do_crypto_3op_1 (1, 0);
21177 do_crypto_3op_1 (1, 1);
21181 do_sha256su1 (void)
21183 do_crypto_3op_1 (1, 2);
21189 do_crypto_2op_1 (N_32
, -1);
21195 do_crypto_2op_1 (N_32
, 0);
21199 do_sha256su0 (void)
21201 do_crypto_2op_1 (N_32
, 1);
21205 do_crc32_1 (unsigned int poly
, unsigned int sz
)
21207 unsigned int Rd
= inst
.operands
[0].reg
;
21208 unsigned int Rn
= inst
.operands
[1].reg
;
21209 unsigned int Rm
= inst
.operands
[2].reg
;
21211 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21212 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
21213 inst
.instruction
|= LOW4 (Rn
) << 16;
21214 inst
.instruction
|= LOW4 (Rm
);
21215 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
21216 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
21218 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
21219 as_warn (UNPRED_REG ("r15"));
21261 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21263 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
21264 do_vfp_sp_dp_cvt ();
21265 do_vfp_cond_or_thumb ();
21269 /* Overall per-instruction processing. */
21271 /* We need to be able to fix up arbitrary expressions in some statements.
21272 This is so that we can handle symbols that are an arbitrary distance from
21273 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
21274 which returns part of an address in a form which will be valid for
21275 a data instruction. We do this by pushing the expression into a symbol
21276 in the expr_section, and creating a fix for that. */
21279 fix_new_arm (fragS
* frag
,
21293 /* Create an absolute valued symbol, so we have something to
21294 refer to in the object file. Unfortunately for us, gas's
21295 generic expression parsing will already have folded out
21296 any use of .set foo/.type foo %function that may have
21297 been used to set type information of the target location,
21298 that's being specified symbolically. We have to presume
21299 the user knows what they are doing. */
21303 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
21305 symbol
= symbol_find_or_make (name
);
21306 S_SET_SEGMENT (symbol
, absolute_section
);
21307 symbol_set_frag (symbol
, &zero_address_frag
);
21308 S_SET_VALUE (symbol
, exp
->X_add_number
);
21309 exp
->X_op
= O_symbol
;
21310 exp
->X_add_symbol
= symbol
;
21311 exp
->X_add_number
= 0;
21317 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
21318 (enum bfd_reloc_code_real
) reloc
);
21322 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
21323 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
21327 /* Mark whether the fix is to a THUMB instruction, or an ARM
21329 new_fix
->tc_fix_data
= thumb_mode
;
21332 /* Create a frg for an instruction requiring relaxation. */
21334 output_relax_insn (void)
21340 /* The size of the instruction is unknown, so tie the debug info to the
21341 start of the instruction. */
21342 dwarf2_emit_insn (0);
21344 switch (inst
.relocs
[0].exp
.X_op
)
21347 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
21348 offset
= inst
.relocs
[0].exp
.X_add_number
;
21352 offset
= inst
.relocs
[0].exp
.X_add_number
;
21355 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
21359 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
21360 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
21361 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
21364 /* Write a 32-bit thumb instruction to buf. */
21366 put_thumb32_insn (char * buf
, unsigned long insn
)
21368 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
21369 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
21373 output_inst (const char * str
)
21379 as_bad ("%s -- `%s'", inst
.error
, str
);
21384 output_relax_insn ();
21387 if (inst
.size
== 0)
21390 to
= frag_more (inst
.size
);
21391 /* PR 9814: Record the thumb mode into the current frag so that we know
21392 what type of NOP padding to use, if necessary. We override any previous
21393 setting so that if the mode has changed then the NOPS that we use will
21394 match the encoding of the last instruction in the frag. */
21395 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21397 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
21399 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
21400 put_thumb32_insn (to
, inst
.instruction
);
21402 else if (inst
.size
> INSN_SIZE
)
21404 gas_assert (inst
.size
== (2 * INSN_SIZE
));
21405 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
21406 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
21409 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
21412 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
21414 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
21415 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
21416 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
21417 inst
.relocs
[r
].type
);
21420 dwarf2_emit_insn (inst
.size
);
21424 output_it_inst (int cond
, int mask
, char * to
)
21426 unsigned long instruction
= 0xbf00;
21429 instruction
|= mask
;
21430 instruction
|= cond
<< 4;
21434 to
= frag_more (2);
21436 dwarf2_emit_insn (2);
21440 md_number_to_chars (to
, instruction
, 2);
21445 /* Tag values used in struct asm_opcode's tag field. */
21448 OT_unconditional
, /* Instruction cannot be conditionalized.
21449 The ARM condition field is still 0xE. */
21450 OT_unconditionalF
, /* Instruction cannot be conditionalized
21451 and carries 0xF in its ARM condition field. */
21452 OT_csuffix
, /* Instruction takes a conditional suffix. */
21453 OT_csuffixF
, /* Some forms of the instruction take a scalar
21454 conditional suffix, others place 0xF where the
21455 condition field would be, others take a vector
21456 conditional suffix. */
21457 OT_cinfix3
, /* Instruction takes a conditional infix,
21458 beginning at character index 3. (In
21459 unified mode, it becomes a suffix.) */
21460 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
21461 tsts, cmps, cmns, and teqs. */
21462 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
21463 character index 3, even in unified mode. Used for
21464 legacy instructions where suffix and infix forms
21465 may be ambiguous. */
21466 OT_csuf_or_in3
, /* Instruction takes either a conditional
21467 suffix or an infix at character index 3. */
21468 OT_odd_infix_unc
, /* This is the unconditional variant of an
21469 instruction that takes a conditional infix
21470 at an unusual position. In unified mode,
21471 this variant will accept a suffix. */
21472 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
21473 are the conditional variants of instructions that
21474 take conditional infixes in unusual positions.
21475 The infix appears at character index
21476 (tag - OT_odd_infix_0). These are not accepted
21477 in unified mode. */
21480 /* Subroutine of md_assemble, responsible for looking up the primary
21481 opcode from the mnemonic the user wrote. STR points to the
21482 beginning of the mnemonic.
21484 This is not simply a hash table lookup, because of conditional
21485 variants. Most instructions have conditional variants, which are
21486 expressed with a _conditional affix_ to the mnemonic. If we were
21487 to encode each conditional variant as a literal string in the opcode
21488 table, it would have approximately 20,000 entries.
21490 Most mnemonics take this affix as a suffix, and in unified syntax,
21491 'most' is upgraded to 'all'. However, in the divided syntax, some
21492 instructions take the affix as an infix, notably the s-variants of
21493 the arithmetic instructions. Of those instructions, all but six
21494 have the infix appear after the third character of the mnemonic.
21496 Accordingly, the algorithm for looking up primary opcodes given
21499 1. Look up the identifier in the opcode table.
21500 If we find a match, go to step U.
21502 2. Look up the last two characters of the identifier in the
21503 conditions table. If we find a match, look up the first N-2
21504 characters of the identifier in the opcode table. If we
21505 find a match, go to step CE.
21507 3. Look up the fourth and fifth characters of the identifier in
21508 the conditions table. If we find a match, extract those
21509 characters from the identifier, and look up the remaining
21510 characters in the opcode table. If we find a match, go
21515 U. Examine the tag field of the opcode structure, in case this is
21516 one of the six instructions with its conditional infix in an
21517 unusual place. If it is, the tag tells us where to find the
21518 infix; look it up in the conditions table and set inst.cond
21519 accordingly. Otherwise, this is an unconditional instruction.
21520 Again set inst.cond accordingly. Return the opcode structure.
21522 CE. Examine the tag field to make sure this is an instruction that
21523 should receive a conditional suffix. If it is not, fail.
21524 Otherwise, set inst.cond from the suffix we already looked up,
21525 and return the opcode structure.
21527 CM. Examine the tag field to make sure this is an instruction that
21528 should receive a conditional infix after the third character.
21529 If it is not, fail. Otherwise, undo the edits to the current
21530 line of input and proceed as for case CE. */
21532 static const struct asm_opcode
*
21533 opcode_lookup (char **str
)
21537 const struct asm_opcode
*opcode
;
21538 const struct asm_cond
*cond
;
21541 /* Scan up to the end of the mnemonic, which must end in white space,
21542 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
21543 for (base
= end
= *str
; *end
!= '\0'; end
++)
21544 if (*end
== ' ' || *end
== '.')
21550 /* Handle a possible width suffix and/or Neon type suffix. */
21555 /* The .w and .n suffixes are only valid if the unified syntax is in
21557 if (unified_syntax
&& end
[1] == 'w')
21559 else if (unified_syntax
&& end
[1] == 'n')
21564 inst
.vectype
.elems
= 0;
21566 *str
= end
+ offset
;
21568 if (end
[offset
] == '.')
21570 /* See if we have a Neon type suffix (possible in either unified or
21571 non-unified ARM syntax mode). */
21572 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
21575 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
21581 /* Look for unaffixed or special-case affixed mnemonic. */
21582 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21587 if (opcode
->tag
< OT_odd_infix_0
)
21589 inst
.cond
= COND_ALWAYS
;
21593 if (warn_on_deprecated
&& unified_syntax
)
21594 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
21595 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
21596 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21599 inst
.cond
= cond
->value
;
21602 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21604 /* Cannot have a conditional suffix on a mnemonic of less than a character.
21606 if (end
- base
< 2)
21609 cond
= (const struct asm_cond
*) hash_find_n (arm_vcond_hsh
, affix
, 1);
21610 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21612 /* If this opcode can not be vector predicated then don't accept it with a
21613 vector predication code. */
21614 if (opcode
&& !opcode
->mayBeVecPred
)
21617 if (!opcode
|| !cond
)
21619 /* Cannot have a conditional suffix on a mnemonic of less than two
21621 if (end
- base
< 3)
21624 /* Look for suffixed mnemonic. */
21626 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21627 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21631 if (opcode
&& cond
)
21634 switch (opcode
->tag
)
21636 case OT_cinfix3_legacy
:
21637 /* Ignore conditional suffixes matched on infix only mnemonics. */
21641 case OT_cinfix3_deprecated
:
21642 case OT_odd_infix_unc
:
21643 if (!unified_syntax
)
21645 /* Fall through. */
21649 case OT_csuf_or_in3
:
21650 inst
.cond
= cond
->value
;
21653 case OT_unconditional
:
21654 case OT_unconditionalF
:
21656 inst
.cond
= cond
->value
;
21659 /* Delayed diagnostic. */
21660 inst
.error
= BAD_COND
;
21661 inst
.cond
= COND_ALWAYS
;
21670 /* Cannot have a usual-position infix on a mnemonic of less than
21671 six characters (five would be a suffix). */
21672 if (end
- base
< 6)
21675 /* Look for infixed mnemonic in the usual position. */
21677 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21681 memcpy (save
, affix
, 2);
21682 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
21683 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21685 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
21686 memcpy (affix
, save
, 2);
21689 && (opcode
->tag
== OT_cinfix3
21690 || opcode
->tag
== OT_cinfix3_deprecated
21691 || opcode
->tag
== OT_csuf_or_in3
21692 || opcode
->tag
== OT_cinfix3_legacy
))
21695 if (warn_on_deprecated
&& unified_syntax
21696 && (opcode
->tag
== OT_cinfix3
21697 || opcode
->tag
== OT_cinfix3_deprecated
))
21698 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
21700 inst
.cond
= cond
->value
;
21707 /* This function generates an initial IT instruction, leaving its block
21708 virtually open for the new instructions. Eventually,
21709 the mask will be updated by now_pred_add_mask () each time
21710 a new instruction needs to be included in the IT block.
21711 Finally, the block is closed with close_automatic_it_block ().
21712 The block closure can be requested either from md_assemble (),
21713 a tencode (), or due to a label hook. */
21716 new_automatic_it_block (int cond
)
21718 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
21719 now_pred
.mask
= 0x18;
21720 now_pred
.cc
= cond
;
21721 now_pred
.block_length
= 1;
21722 mapping_state (MAP_THUMB
);
21723 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
21724 now_pred
.warn_deprecated
= FALSE
;
21725 now_pred
.insn_cond
= TRUE
;
21728 /* Close an automatic IT block.
21729 See comments in new_automatic_it_block (). */
21732 close_automatic_it_block (void)
21734 now_pred
.mask
= 0x10;
21735 now_pred
.block_length
= 0;
21738 /* Update the mask of the current automatically-generated IT
21739 instruction. See comments in new_automatic_it_block (). */
21742 now_pred_add_mask (int cond
)
21744 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
21745 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
21746 | ((bitvalue) << (nbit)))
21747 const int resulting_bit
= (cond
& 1);
21749 now_pred
.mask
&= 0xf;
21750 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
21752 (5 - now_pred
.block_length
));
21753 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
21755 ((5 - now_pred
.block_length
) - 1));
21756 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
21759 #undef SET_BIT_VALUE
21762 /* The IT blocks handling machinery is accessed through the these functions:
21763 it_fsm_pre_encode () from md_assemble ()
21764 set_pred_insn_type () optional, from the tencode functions
21765 set_pred_insn_type_last () ditto
21766 in_pred_block () ditto
21767 it_fsm_post_encode () from md_assemble ()
21768 force_automatic_it_block_close () from label handling functions
21771 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
21772 initializing the IT insn type with a generic initial value depending
21773 on the inst.condition.
21774 2) During the tencode function, two things may happen:
21775 a) The tencode function overrides the IT insn type by
21776 calling either set_pred_insn_type (type) or
21777 set_pred_insn_type_last ().
21778 b) The tencode function queries the IT block state by
21779 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
21781 Both set_pred_insn_type and in_pred_block run the internal FSM state
21782 handling function (handle_pred_state), because: a) setting the IT insn
21783 type may incur in an invalid state (exiting the function),
21784 and b) querying the state requires the FSM to be updated.
21785 Specifically we want to avoid creating an IT block for conditional
21786 branches, so it_fsm_pre_encode is actually a guess and we can't
21787 determine whether an IT block is required until the tencode () routine
21788 has decided what type of instruction this actually it.
21789 Because of this, if set_pred_insn_type and in_pred_block have to be
21790 used, set_pred_insn_type has to be called first.
21792 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
21793 that determines the insn IT type depending on the inst.cond code.
21794 When a tencode () routine encodes an instruction that can be
21795 either outside an IT block, or, in the case of being inside, has to be
21796 the last one, set_pred_insn_type_last () will determine the proper
21797 IT instruction type based on the inst.cond code. Otherwise,
21798 set_pred_insn_type can be called for overriding that logic or
21799 for covering other cases.
21801 Calling handle_pred_state () may not transition the IT block state to
21802 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
21803 still queried. Instead, if the FSM determines that the state should
21804 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
21805 after the tencode () function: that's what it_fsm_post_encode () does.
21807 Since in_pred_block () calls the state handling function to get an
21808 updated state, an error may occur (due to invalid insns combination).
21809 In that case, inst.error is set.
21810 Therefore, inst.error has to be checked after the execution of
21811 the tencode () routine.
21813 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
21814 any pending state change (if any) that didn't take place in
21815 handle_pred_state () as explained above. */
21818 it_fsm_pre_encode (void)
21820 if (inst
.cond
!= COND_ALWAYS
)
21821 inst
.pred_insn_type
= INSIDE_IT_INSN
;
21823 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
21825 now_pred
.state_handled
= 0;
21828 /* IT state FSM handling function. */
21829 /* MVE instructions and non-MVE instructions are handled differently because of
21830 the introduction of VPT blocks.
21831 Specifications say that any non-MVE instruction inside a VPT block is
21832 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
21833 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
21834 few exceptions we have MVE_UNPREDICABLE_INSN.
21835 The error messages provided depending on the different combinations possible
21836 are described in the cases below:
21837 For 'most' MVE instructions:
21838 1) In an IT block, with an IT code: syntax error
21839 2) In an IT block, with a VPT code: error: must be in a VPT block
21840 3) In an IT block, with no code: warning: UNPREDICTABLE
21841 4) In a VPT block, with an IT code: syntax error
21842 5) In a VPT block, with a VPT code: OK!
21843 6) In a VPT block, with no code: error: missing code
21844 7) Outside a pred block, with an IT code: error: syntax error
21845 8) Outside a pred block, with a VPT code: error: should be in a VPT block
21846 9) Outside a pred block, with no code: OK!
21847 For non-MVE instructions:
21848 10) In an IT block, with an IT code: OK!
21849 11) In an IT block, with a VPT code: syntax error
21850 12) In an IT block, with no code: error: missing code
21851 13) In a VPT block, with an IT code: error: should be in an IT block
21852 14) In a VPT block, with a VPT code: syntax error
21853 15) In a VPT block, with no code: UNPREDICTABLE
21854 16) Outside a pred block, with an IT code: error: should be in an IT block
21855 17) Outside a pred block, with a VPT code: syntax error
21856 18) Outside a pred block, with no code: OK!
21861 handle_pred_state (void)
21863 now_pred
.state_handled
= 1;
21864 now_pred
.insn_cond
= FALSE
;
21866 switch (now_pred
.state
)
21868 case OUTSIDE_PRED_BLOCK
:
21869 switch (inst
.pred_insn_type
)
21871 case MVE_UNPREDICABLE_INSN
:
21872 case MVE_OUTSIDE_PRED_INSN
:
21873 if (inst
.cond
< COND_ALWAYS
)
21875 /* Case 7: Outside a pred block, with an IT code: error: syntax
21877 inst
.error
= BAD_SYNTAX
;
21880 /* Case 9: Outside a pred block, with no code: OK! */
21882 case OUTSIDE_PRED_INSN
:
21883 if (inst
.cond
> COND_ALWAYS
)
21885 /* Case 17: Outside a pred block, with a VPT code: syntax error.
21887 inst
.error
= BAD_SYNTAX
;
21890 /* Case 18: Outside a pred block, with no code: OK! */
21893 case INSIDE_VPT_INSN
:
21894 /* Case 8: Outside a pred block, with a VPT code: error: should be in
21896 inst
.error
= BAD_OUT_VPT
;
21899 case INSIDE_IT_INSN
:
21900 case INSIDE_IT_LAST_INSN
:
21901 if (inst
.cond
< COND_ALWAYS
)
21903 /* Case 16: Outside a pred block, with an IT code: error: should
21904 be in an IT block. */
21905 if (thumb_mode
== 0)
21908 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
21909 as_tsktsk (_("Warning: conditional outside an IT block"\
21914 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
21915 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
21917 /* Automatically generate the IT instruction. */
21918 new_automatic_it_block (inst
.cond
);
21919 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
21920 close_automatic_it_block ();
21924 inst
.error
= BAD_OUT_IT
;
21930 else if (inst
.cond
> COND_ALWAYS
)
21932 /* Case 17: Outside a pred block, with a VPT code: syntax error.
21934 inst
.error
= BAD_SYNTAX
;
21939 case IF_INSIDE_IT_LAST_INSN
:
21940 case NEUTRAL_IT_INSN
:
21944 if (inst
.cond
!= COND_ALWAYS
)
21945 first_error (BAD_SYNTAX
);
21946 now_pred
.state
= MANUAL_PRED_BLOCK
;
21947 now_pred
.block_length
= 0;
21948 now_pred
.type
= VECTOR_PRED
;
21952 now_pred
.state
= MANUAL_PRED_BLOCK
;
21953 now_pred
.block_length
= 0;
21954 now_pred
.type
= SCALAR_PRED
;
21959 case AUTOMATIC_PRED_BLOCK
:
21960 /* Three things may happen now:
21961 a) We should increment current it block size;
21962 b) We should close current it block (closing insn or 4 insns);
21963 c) We should close current it block and start a new one (due
21964 to incompatible conditions or
21965 4 insns-length block reached). */
21967 switch (inst
.pred_insn_type
)
21969 case INSIDE_VPT_INSN
:
21971 case MVE_UNPREDICABLE_INSN
:
21972 case MVE_OUTSIDE_PRED_INSN
:
21974 case OUTSIDE_PRED_INSN
:
21975 /* The closure of the block shall happen immediately,
21976 so any in_pred_block () call reports the block as closed. */
21977 force_automatic_it_block_close ();
21980 case INSIDE_IT_INSN
:
21981 case INSIDE_IT_LAST_INSN
:
21982 case IF_INSIDE_IT_LAST_INSN
:
21983 now_pred
.block_length
++;
21985 if (now_pred
.block_length
> 4
21986 || !now_pred_compatible (inst
.cond
))
21988 force_automatic_it_block_close ();
21989 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
21990 new_automatic_it_block (inst
.cond
);
21994 now_pred
.insn_cond
= TRUE
;
21995 now_pred_add_mask (inst
.cond
);
21998 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
21999 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
22000 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
22001 close_automatic_it_block ();
22004 case NEUTRAL_IT_INSN
:
22005 now_pred
.block_length
++;
22006 now_pred
.insn_cond
= TRUE
;
22008 if (now_pred
.block_length
> 4)
22009 force_automatic_it_block_close ();
22011 now_pred_add_mask (now_pred
.cc
& 1);
22015 close_automatic_it_block ();
22016 now_pred
.state
= MANUAL_PRED_BLOCK
;
22021 case MANUAL_PRED_BLOCK
:
22024 if (now_pred
.type
== SCALAR_PRED
)
22026 /* Check conditional suffixes. */
22027 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
22028 now_pred
.mask
<<= 1;
22029 now_pred
.mask
&= 0x1f;
22030 is_last
= (now_pred
.mask
== 0x10);
22034 now_pred
.cc
^= (now_pred
.mask
>> 4);
22035 cond
= now_pred
.cc
+ 0xf;
22036 now_pred
.mask
<<= 1;
22037 now_pred
.mask
&= 0x1f;
22038 is_last
= now_pred
.mask
== 0x10;
22040 now_pred
.insn_cond
= TRUE
;
22042 switch (inst
.pred_insn_type
)
22044 case OUTSIDE_PRED_INSN
:
22045 if (now_pred
.type
== SCALAR_PRED
)
22047 if (inst
.cond
== COND_ALWAYS
)
22049 /* Case 12: In an IT block, with no code: error: missing
22051 inst
.error
= BAD_NOT_IT
;
22054 else if (inst
.cond
> COND_ALWAYS
)
22056 /* Case 11: In an IT block, with a VPT code: syntax error.
22058 inst
.error
= BAD_SYNTAX
;
22061 else if (thumb_mode
)
22063 /* This is for some special cases where a non-MVE
22064 instruction is not allowed in an IT block, such as cbz,
22065 but are put into one with a condition code.
22066 You could argue this should be a syntax error, but we
22067 gave the 'not allowed in IT block' diagnostic in the
22068 past so we will keep doing so. */
22069 inst
.error
= BAD_NOT_IT
;
22076 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
22077 as_tsktsk (MVE_NOT_VPT
);
22080 case MVE_OUTSIDE_PRED_INSN
:
22081 if (now_pred
.type
== SCALAR_PRED
)
22083 if (inst
.cond
== COND_ALWAYS
)
22085 /* Case 3: In an IT block, with no code: warning:
22087 as_tsktsk (MVE_NOT_IT
);
22090 else if (inst
.cond
< COND_ALWAYS
)
22092 /* Case 1: In an IT block, with an IT code: syntax error.
22094 inst
.error
= BAD_SYNTAX
;
22102 if (inst
.cond
< COND_ALWAYS
)
22104 /* Case 4: In a VPT block, with an IT code: syntax error.
22106 inst
.error
= BAD_SYNTAX
;
22109 else if (inst
.cond
== COND_ALWAYS
)
22111 /* Case 6: In a VPT block, with no code: error: missing
22113 inst
.error
= BAD_NOT_VPT
;
22121 case MVE_UNPREDICABLE_INSN
:
22122 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
22124 case INSIDE_IT_INSN
:
22125 if (inst
.cond
> COND_ALWAYS
)
22127 /* Case 11: In an IT block, with a VPT code: syntax error. */
22128 /* Case 14: In a VPT block, with a VPT code: syntax error. */
22129 inst
.error
= BAD_SYNTAX
;
22132 else if (now_pred
.type
== SCALAR_PRED
)
22134 /* Case 10: In an IT block, with an IT code: OK! */
22135 if (cond
!= inst
.cond
)
22137 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
22144 /* Case 13: In a VPT block, with an IT code: error: should be
22146 inst
.error
= BAD_OUT_IT
;
22151 case INSIDE_VPT_INSN
:
22152 if (now_pred
.type
== SCALAR_PRED
)
22154 /* Case 2: In an IT block, with a VPT code: error: must be in a
22156 inst
.error
= BAD_OUT_VPT
;
22159 /* Case 5: In a VPT block, with a VPT code: OK! */
22160 else if (cond
!= inst
.cond
)
22162 inst
.error
= BAD_VPT_COND
;
22166 case INSIDE_IT_LAST_INSN
:
22167 case IF_INSIDE_IT_LAST_INSN
:
22168 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
22170 /* Case 4: In a VPT block, with an IT code: syntax error. */
22171 /* Case 11: In an IT block, with a VPT code: syntax error. */
22172 inst
.error
= BAD_SYNTAX
;
22175 else if (cond
!= inst
.cond
)
22177 inst
.error
= BAD_IT_COND
;
22182 inst
.error
= BAD_BRANCH
;
22187 case NEUTRAL_IT_INSN
:
22188 /* The BKPT instruction is unconditional even in a IT or VPT
22193 if (now_pred
.type
== SCALAR_PRED
)
22195 inst
.error
= BAD_IT_IT
;
22198 /* fall through. */
22200 if (inst
.cond
== COND_ALWAYS
)
22202 /* Executing a VPT/VPST instruction inside an IT block or a
22203 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
22205 if (now_pred
.type
== SCALAR_PRED
)
22206 as_tsktsk (MVE_NOT_IT
);
22208 as_tsktsk (MVE_NOT_VPT
);
22213 /* VPT/VPST do not accept condition codes. */
22214 inst
.error
= BAD_SYNTAX
;
22225 struct depr_insn_mask
22227 unsigned long pattern
;
22228 unsigned long mask
;
22229 const char* description
;
22232 /* List of 16-bit instruction patterns deprecated in an IT block in
22234 static const struct depr_insn_mask depr_it_insns
[] = {
22235 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
22236 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
22237 { 0xa000, 0xb800, N_("ADR") },
22238 { 0x4800, 0xf800, N_("Literal loads") },
22239 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
22240 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
22241 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
22242 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
22243 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
22248 it_fsm_post_encode (void)
22252 if (!now_pred
.state_handled
)
22253 handle_pred_state ();
22255 if (now_pred
.insn_cond
22256 && !now_pred
.warn_deprecated
22257 && warn_on_deprecated
22258 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
22259 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
22261 if (inst
.instruction
>= 0x10000)
22263 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
22264 "performance deprecated in ARMv8-A and ARMv8-R"));
22265 now_pred
.warn_deprecated
= TRUE
;
22269 const struct depr_insn_mask
*p
= depr_it_insns
;
22271 while (p
->mask
!= 0)
22273 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
22275 as_tsktsk (_("IT blocks containing 16-bit Thumb "
22276 "instructions of the following class are "
22277 "performance deprecated in ARMv8-A and "
22278 "ARMv8-R: %s"), p
->description
);
22279 now_pred
.warn_deprecated
= TRUE
;
22287 if (now_pred
.block_length
> 1)
22289 as_tsktsk (_("IT blocks containing more than one conditional "
22290 "instruction are performance deprecated in ARMv8-A and "
22292 now_pred
.warn_deprecated
= TRUE
;
22296 is_last
= (now_pred
.mask
== 0x10);
22299 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
22305 force_automatic_it_block_close (void)
22307 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
22309 close_automatic_it_block ();
22310 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
22316 in_pred_block (void)
22318 if (!now_pred
.state_handled
)
22319 handle_pred_state ();
22321 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
22324 /* Whether OPCODE only has T32 encoding. Since this function is only used by
22325 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
22326 here, hence the "known" in the function name. */
22329 known_t32_only_insn (const struct asm_opcode
*opcode
)
22331 /* Original Thumb-1 wide instruction. */
22332 if (opcode
->tencode
== do_t_blx
22333 || opcode
->tencode
== do_t_branch23
22334 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
22335 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
22338 /* Wide-only instruction added to ARMv8-M Baseline. */
22339 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
22340 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
22341 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
22342 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
22348 /* Whether wide instruction variant can be used if available for a valid OPCODE
22352 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
22354 if (known_t32_only_insn (opcode
))
22357 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
22358 of variant T3 of B.W is checked in do_t_branch. */
22359 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22360 && opcode
->tencode
== do_t_branch
)
22363 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
22364 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22365 && opcode
->tencode
== do_t_mov_cmp
22366 /* Make sure CMP instruction is not affected. */
22367 && opcode
->aencode
== do_mov
)
22370 /* Wide instruction variants of all instructions with narrow *and* wide
22371 variants become available with ARMv6t2. Other opcodes are either
22372 narrow-only or wide-only and are thus available if OPCODE is valid. */
22373 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
22376 /* OPCODE with narrow only instruction variant or wide variant not
22382 md_assemble (char *str
)
22385 const struct asm_opcode
* opcode
;
22387 /* Align the previous label if needed. */
22388 if (last_label_seen
!= NULL
)
22390 symbol_set_frag (last_label_seen
, frag_now
);
22391 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
22392 S_SET_SEGMENT (last_label_seen
, now_seg
);
22395 memset (&inst
, '\0', sizeof (inst
));
22397 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
22398 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
22400 opcode
= opcode_lookup (&p
);
22403 /* It wasn't an instruction, but it might be a register alias of
22404 the form alias .req reg, or a Neon .dn/.qn directive. */
22405 if (! create_register_alias (str
, p
)
22406 && ! create_neon_reg_alias (str
, p
))
22407 as_bad (_("bad instruction `%s'"), str
);
22412 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
22413 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
22415 /* The value which unconditional instructions should have in place of the
22416 condition field. */
22417 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
22421 arm_feature_set variant
;
22423 variant
= cpu_variant
;
22424 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
22425 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
22426 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
22427 /* Check that this instruction is supported for this CPU. */
22428 if (!opcode
->tvariant
22429 || (thumb_mode
== 1
22430 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
22432 if (opcode
->tencode
== do_t_swi
)
22433 as_bad (_("SVC is not permitted on this architecture"));
22435 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
22438 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
22439 && opcode
->tencode
!= do_t_branch
)
22441 as_bad (_("Thumb does not support conditional execution"));
22445 /* Two things are addressed here:
22446 1) Implicit require narrow instructions on Thumb-1.
22447 This avoids relaxation accidentally introducing Thumb-2
22449 2) Reject wide instructions in non Thumb-2 cores.
22451 Only instructions with narrow and wide variants need to be handled
22452 but selecting all non wide-only instructions is easier. */
22453 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
22454 && !t32_insn_ok (variant
, opcode
))
22456 if (inst
.size_req
== 0)
22458 else if (inst
.size_req
== 4)
22460 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
22461 as_bad (_("selected processor does not support 32bit wide "
22462 "variant of instruction `%s'"), str
);
22464 as_bad (_("selected processor does not support `%s' in "
22465 "Thumb-2 mode"), str
);
22470 inst
.instruction
= opcode
->tvalue
;
22472 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
22474 /* Prepare the pred_insn_type for those encodings that don't set
22476 it_fsm_pre_encode ();
22478 opcode
->tencode ();
22480 it_fsm_post_encode ();
22483 if (!(inst
.error
|| inst
.relax
))
22485 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
22486 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
22487 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
22489 as_bad (_("cannot honor width suffix -- `%s'"), str
);
22494 /* Something has gone badly wrong if we try to relax a fixed size
22496 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
22498 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
22499 *opcode
->tvariant
);
22500 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
22501 set those bits when Thumb-2 32-bit instructions are seen. The impact
22502 of relaxable instructions will be considered later after we finish all
22504 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
22505 variant
= arm_arch_none
;
22507 variant
= cpu_variant
;
22508 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
22509 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
22512 check_neon_suffixes
;
22516 mapping_state (MAP_THUMB
);
22519 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
22523 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
22524 is_bx
= (opcode
->aencode
== do_bx
);
22526 /* Check that this instruction is supported for this CPU. */
22527 if (!(is_bx
&& fix_v4bx
)
22528 && !(opcode
->avariant
&&
22529 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
22531 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
22536 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
22540 inst
.instruction
= opcode
->avalue
;
22541 if (opcode
->tag
== OT_unconditionalF
)
22542 inst
.instruction
|= 0xFU
<< 28;
22544 inst
.instruction
|= inst
.cond
<< 28;
22545 inst
.size
= INSN_SIZE
;
22546 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
22548 it_fsm_pre_encode ();
22549 opcode
->aencode ();
22550 it_fsm_post_encode ();
22552 /* Arm mode bx is marked as both v4T and v5 because it's still required
22553 on a hypothetical non-thumb v5 core. */
22555 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
22557 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
22558 *opcode
->avariant
);
22560 check_neon_suffixes
;
22564 mapping_state (MAP_ARM
);
22569 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
22577 check_pred_blocks_finished (void)
22582 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
22583 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
22584 == MANUAL_PRED_BLOCK
)
22586 if (now_pred
.type
== SCALAR_PRED
)
22587 as_warn (_("section '%s' finished with an open IT block."),
22590 as_warn (_("section '%s' finished with an open VPT/VPST block."),
22594 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
22596 if (now_pred
.type
== SCALAR_PRED
)
22597 as_warn (_("file finished with an open IT block."));
22599 as_warn (_("file finished with an open VPT/VPST block."));
22604 /* Various frobbings of labels and their addresses. */
22607 arm_start_line_hook (void)
22609 last_label_seen
= NULL
;
22613 arm_frob_label (symbolS
* sym
)
22615 last_label_seen
= sym
;
22617 ARM_SET_THUMB (sym
, thumb_mode
);
22619 #if defined OBJ_COFF || defined OBJ_ELF
22620 ARM_SET_INTERWORK (sym
, support_interwork
);
22623 force_automatic_it_block_close ();
22625 /* Note - do not allow local symbols (.Lxxx) to be labelled
22626 as Thumb functions. This is because these labels, whilst
22627 they exist inside Thumb code, are not the entry points for
22628 possible ARM->Thumb calls. Also, these labels can be used
22629 as part of a computed goto or switch statement. eg gcc
22630 can generate code that looks like this:
22632 ldr r2, [pc, .Laaa]
22642 The first instruction loads the address of the jump table.
22643 The second instruction converts a table index into a byte offset.
22644 The third instruction gets the jump address out of the table.
22645 The fourth instruction performs the jump.
22647 If the address stored at .Laaa is that of a symbol which has the
22648 Thumb_Func bit set, then the linker will arrange for this address
22649 to have the bottom bit set, which in turn would mean that the
22650 address computation performed by the third instruction would end
22651 up with the bottom bit set. Since the ARM is capable of unaligned
22652 word loads, the instruction would then load the incorrect address
22653 out of the jump table, and chaos would ensue. */
22654 if (label_is_thumb_function_name
22655 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
22656 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
22658 /* When the address of a Thumb function is taken the bottom
22659 bit of that address should be set. This will allow
22660 interworking between Arm and Thumb functions to work
22663 THUMB_SET_FUNC (sym
, 1);
22665 label_is_thumb_function_name
= FALSE
;
22668 dwarf2_emit_label (sym
);
22672 arm_data_in_code (void)
22674 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
22676 *input_line_pointer
= '/';
22677 input_line_pointer
+= 5;
22678 *input_line_pointer
= 0;
22686 arm_canonicalize_symbol_name (char * name
)
22690 if (thumb_mode
&& (len
= strlen (name
)) > 5
22691 && streq (name
+ len
- 5, "/data"))
22692 *(name
+ len
- 5) = 0;
22697 /* Table of all register names defined by default. The user can
22698 define additional names with .req. Note that all register names
22699 should appear in both upper and lowercase variants. Some registers
22700 also have mixed-case names. */
22702 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
22703 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
22704 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
22705 #define REGSET(p,t) \
22706 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
22707 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
22708 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
22709 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
22710 #define REGSETH(p,t) \
22711 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
22712 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
22713 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
22714 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
22715 #define REGSET2(p,t) \
22716 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
22717 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
22718 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
22719 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
22720 #define SPLRBANK(base,bank,t) \
22721 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
22722 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
22723 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
22724 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
22725 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
22726 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
22728 static const struct reg_entry reg_names
[] =
22730 /* ARM integer registers. */
22731 REGSET(r
, RN
), REGSET(R
, RN
),
22733 /* ATPCS synonyms. */
22734 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
22735 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
22736 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
22738 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
22739 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
22740 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
22742 /* Well-known aliases. */
22743 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
22744 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
22746 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
22747 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
22749 /* Defining the new Zero register from ARMv8.1-M. */
22753 /* Coprocessor numbers. */
22754 REGSET(p
, CP
), REGSET(P
, CP
),
22756 /* Coprocessor register numbers. The "cr" variants are for backward
22758 REGSET(c
, CN
), REGSET(C
, CN
),
22759 REGSET(cr
, CN
), REGSET(CR
, CN
),
22761 /* ARM banked registers. */
22762 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
22763 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
22764 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
22765 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
22766 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
22767 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
22768 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
22770 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
22771 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
22772 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
22773 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
22774 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
22775 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
22776 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
22777 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
22779 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
22780 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
22781 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
22782 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
22783 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
22784 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
22785 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
22786 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
22787 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
22789 /* FPA registers. */
22790 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
22791 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
22793 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
22794 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
22796 /* VFP SP registers. */
22797 REGSET(s
,VFS
), REGSET(S
,VFS
),
22798 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
22800 /* VFP DP Registers. */
22801 REGSET(d
,VFD
), REGSET(D
,VFD
),
22802 /* Extra Neon DP registers. */
22803 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
22805 /* Neon QP registers. */
22806 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
22808 /* VFP control registers. */
22809 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
22810 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
22811 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
22812 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
22813 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
22814 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
22815 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
22817 /* Maverick DSP coprocessor registers. */
22818 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
22819 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
22821 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
22822 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
22823 REGDEF(dspsc
,0,DSPSC
),
22825 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
22826 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
22827 REGDEF(DSPSC
,0,DSPSC
),
22829 /* iWMMXt data registers - p0, c0-15. */
22830 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
22832 /* iWMMXt control registers - p1, c0-3. */
22833 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
22834 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
22835 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
22836 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
22838 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
22839 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
22840 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
22841 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
22842 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
22844 /* XScale accumulator registers. */
22845 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
22851 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
22852 within psr_required_here. */
22853 static const struct asm_psr psrs
[] =
22855 /* Backward compatibility notation. Note that "all" is no longer
22856 truly all possible PSR bits. */
22857 {"all", PSR_c
| PSR_f
},
22861 /* Individual flags. */
22867 /* Combinations of flags. */
22868 {"fs", PSR_f
| PSR_s
},
22869 {"fx", PSR_f
| PSR_x
},
22870 {"fc", PSR_f
| PSR_c
},
22871 {"sf", PSR_s
| PSR_f
},
22872 {"sx", PSR_s
| PSR_x
},
22873 {"sc", PSR_s
| PSR_c
},
22874 {"xf", PSR_x
| PSR_f
},
22875 {"xs", PSR_x
| PSR_s
},
22876 {"xc", PSR_x
| PSR_c
},
22877 {"cf", PSR_c
| PSR_f
},
22878 {"cs", PSR_c
| PSR_s
},
22879 {"cx", PSR_c
| PSR_x
},
22880 {"fsx", PSR_f
| PSR_s
| PSR_x
},
22881 {"fsc", PSR_f
| PSR_s
| PSR_c
},
22882 {"fxs", PSR_f
| PSR_x
| PSR_s
},
22883 {"fxc", PSR_f
| PSR_x
| PSR_c
},
22884 {"fcs", PSR_f
| PSR_c
| PSR_s
},
22885 {"fcx", PSR_f
| PSR_c
| PSR_x
},
22886 {"sfx", PSR_s
| PSR_f
| PSR_x
},
22887 {"sfc", PSR_s
| PSR_f
| PSR_c
},
22888 {"sxf", PSR_s
| PSR_x
| PSR_f
},
22889 {"sxc", PSR_s
| PSR_x
| PSR_c
},
22890 {"scf", PSR_s
| PSR_c
| PSR_f
},
22891 {"scx", PSR_s
| PSR_c
| PSR_x
},
22892 {"xfs", PSR_x
| PSR_f
| PSR_s
},
22893 {"xfc", PSR_x
| PSR_f
| PSR_c
},
22894 {"xsf", PSR_x
| PSR_s
| PSR_f
},
22895 {"xsc", PSR_x
| PSR_s
| PSR_c
},
22896 {"xcf", PSR_x
| PSR_c
| PSR_f
},
22897 {"xcs", PSR_x
| PSR_c
| PSR_s
},
22898 {"cfs", PSR_c
| PSR_f
| PSR_s
},
22899 {"cfx", PSR_c
| PSR_f
| PSR_x
},
22900 {"csf", PSR_c
| PSR_s
| PSR_f
},
22901 {"csx", PSR_c
| PSR_s
| PSR_x
},
22902 {"cxf", PSR_c
| PSR_x
| PSR_f
},
22903 {"cxs", PSR_c
| PSR_x
| PSR_s
},
22904 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
22905 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
22906 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
22907 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
22908 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
22909 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
22910 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
22911 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
22912 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
22913 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
22914 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
22915 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
22916 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
22917 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
22918 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
22919 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
22920 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
22921 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
22922 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
22923 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
22924 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
22925 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
22926 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
22927 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
22930 /* Table of V7M psr names. */
22931 static const struct asm_psr v7m_psrs
[] =
22933 {"apsr", 0x0 }, {"APSR", 0x0 },
22934 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
22935 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
22936 {"psr", 0x3 }, {"PSR", 0x3 },
22937 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
22938 {"ipsr", 0x5 }, {"IPSR", 0x5 },
22939 {"epsr", 0x6 }, {"EPSR", 0x6 },
22940 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
22941 {"msp", 0x8 }, {"MSP", 0x8 },
22942 {"psp", 0x9 }, {"PSP", 0x9 },
22943 {"msplim", 0xa }, {"MSPLIM", 0xa },
22944 {"psplim", 0xb }, {"PSPLIM", 0xb },
22945 {"primask", 0x10}, {"PRIMASK", 0x10},
22946 {"basepri", 0x11}, {"BASEPRI", 0x11},
22947 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
22948 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
22949 {"control", 0x14}, {"CONTROL", 0x14},
22950 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
22951 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
22952 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
22953 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
22954 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
22955 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
22956 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
22957 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
22958 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
22961 /* Table of all shift-in-operand names. */
22962 static const struct asm_shift_name shift_names
[] =
22964 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
22965 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
22966 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
22967 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
22968 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
22969 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
22970 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
22973 /* Table of all explicit relocation names. */
22975 static struct reloc_entry reloc_names
[] =
22977 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
22978 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
22979 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
22980 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
22981 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
22982 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
22983 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
22984 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
22985 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
22986 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
22987 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
22988 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
22989 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
22990 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
22991 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
22992 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
22993 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
22994 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
22995 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
22996 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
22997 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
22998 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
22999 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
23000 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
23001 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
23002 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
23003 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
23007 /* Table of all conditional affixes. */
23008 static const struct asm_cond conds
[] =
23012 {"cs", 0x2}, {"hs", 0x2},
23013 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
23026 static const struct asm_cond vconds
[] =
23032 #define UL_BARRIER(L,U,CODE,FEAT) \
23033 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
23034 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
23036 static struct asm_barrier_opt barrier_opt_names
[] =
23038 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
23039 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
23040 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
23041 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
23042 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
23043 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
23044 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
23045 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
23046 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
23047 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
23048 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
23049 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
23050 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
23051 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
23052 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
23053 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
23058 /* Table of ARM-format instructions. */
23060 /* Macros for gluing together operand strings. N.B. In all cases
23061 other than OPS0, the trailing OP_stop comes from default
23062 zero-initialization of the unspecified elements of the array. */
23063 #define OPS0() { OP_stop, }
23064 #define OPS1(a) { OP_##a, }
23065 #define OPS2(a,b) { OP_##a,OP_##b, }
23066 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
23067 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
23068 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
23069 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
23071 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
23072 This is useful when mixing operands for ARM and THUMB, i.e. using the
23073 MIX_ARM_THUMB_OPERANDS macro.
23074 In order to use these macros, prefix the number of operands with _
23076 #define OPS_1(a) { a, }
23077 #define OPS_2(a,b) { a,b, }
23078 #define OPS_3(a,b,c) { a,b,c, }
23079 #define OPS_4(a,b,c,d) { a,b,c,d, }
23080 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
23081 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
23083 /* These macros abstract out the exact format of the mnemonic table and
23084 save some repeated characters. */
23086 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
23087 #define TxCE(mnem, op, top, nops, ops, ae, te) \
23088 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
23089 THUMB_VARIANT, do_##ae, do_##te, 0 }
23091 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
23092 a T_MNEM_xyz enumerator. */
23093 #define TCE(mnem, aop, top, nops, ops, ae, te) \
23094 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
23095 #define tCE(mnem, aop, top, nops, ops, ae, te) \
23096 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23098 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
23099 infix after the third character. */
23100 #define TxC3(mnem, op, top, nops, ops, ae, te) \
23101 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
23102 THUMB_VARIANT, do_##ae, do_##te, 0 }
23103 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
23104 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
23105 THUMB_VARIANT, do_##ae, do_##te, 0 }
23106 #define TC3(mnem, aop, top, nops, ops, ae, te) \
23107 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
23108 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
23109 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
23110 #define tC3(mnem, aop, top, nops, ops, ae, te) \
23111 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23112 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
23113 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23115 /* Mnemonic that cannot be conditionalized. The ARM condition-code
23116 field is still 0xE. Many of the Thumb variants can be executed
23117 conditionally, so this is checked separately. */
23118 #define TUE(mnem, op, top, nops, ops, ae, te) \
23119 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
23120 THUMB_VARIANT, do_##ae, do_##te, 0 }
23122 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
23123 Used by mnemonics that have very minimal differences in the encoding for
23124 ARM and Thumb variants and can be handled in a common function. */
23125 #define TUEc(mnem, op, top, nops, ops, en) \
23126 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
23127 THUMB_VARIANT, do_##en, do_##en, 0 }
23129 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
23130 condition code field. */
23131 #define TUF(mnem, op, top, nops, ops, ae, te) \
23132 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
23133 THUMB_VARIANT, do_##ae, do_##te, 0 }
23135 /* ARM-only variants of all the above. */
23136 #define CE(mnem, op, nops, ops, ae) \
23137 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23139 #define C3(mnem, op, nops, ops, ae) \
23140 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23142 /* Thumb-only variants of TCE and TUE. */
23143 #define ToC(mnem, top, nops, ops, te) \
23144 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23147 #define ToU(mnem, top, nops, ops, te) \
23148 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
23151 /* T_MNEM_xyz enumerator variants of ToC. */
23152 #define toC(mnem, top, nops, ops, te) \
23153 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
23156 /* T_MNEM_xyz enumerator variants of ToU. */
23157 #define toU(mnem, top, nops, ops, te) \
23158 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
23161 /* Legacy mnemonics that always have conditional infix after the third
23163 #define CL(mnem, op, nops, ops, ae) \
23164 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
23165 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23167 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
23168 #define cCE(mnem, op, nops, ops, ae) \
23169 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23171 /* mov instructions that are shared between coprocessor and MVE. */
23172 #define mcCE(mnem, op, nops, ops, ae) \
23173 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
23175 /* Legacy coprocessor instructions where conditional infix and conditional
23176 suffix are ambiguous. For consistency this includes all FPA instructions,
23177 not just the potentially ambiguous ones. */
23178 #define cCL(mnem, op, nops, ops, ae) \
23179 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
23180 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23182 /* Coprocessor, takes either a suffix or a position-3 infix
23183 (for an FPA corner case). */
23184 #define C3E(mnem, op, nops, ops, ae) \
23185 { mnem, OPS##nops ops, OT_csuf_or_in3, \
23186 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23188 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
23189 { m1 #m2 m3, OPS##nops ops, \
23190 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
23191 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23193 #define CM(m1, m2, op, nops, ops, ae) \
23194 xCM_ (m1, , m2, op, nops, ops, ae), \
23195 xCM_ (m1, eq, m2, op, nops, ops, ae), \
23196 xCM_ (m1, ne, m2, op, nops, ops, ae), \
23197 xCM_ (m1, cs, m2, op, nops, ops, ae), \
23198 xCM_ (m1, hs, m2, op, nops, ops, ae), \
23199 xCM_ (m1, cc, m2, op, nops, ops, ae), \
23200 xCM_ (m1, ul, m2, op, nops, ops, ae), \
23201 xCM_ (m1, lo, m2, op, nops, ops, ae), \
23202 xCM_ (m1, mi, m2, op, nops, ops, ae), \
23203 xCM_ (m1, pl, m2, op, nops, ops, ae), \
23204 xCM_ (m1, vs, m2, op, nops, ops, ae), \
23205 xCM_ (m1, vc, m2, op, nops, ops, ae), \
23206 xCM_ (m1, hi, m2, op, nops, ops, ae), \
23207 xCM_ (m1, ls, m2, op, nops, ops, ae), \
23208 xCM_ (m1, ge, m2, op, nops, ops, ae), \
23209 xCM_ (m1, lt, m2, op, nops, ops, ae), \
23210 xCM_ (m1, gt, m2, op, nops, ops, ae), \
23211 xCM_ (m1, le, m2, op, nops, ops, ae), \
23212 xCM_ (m1, al, m2, op, nops, ops, ae)
23214 #define UE(mnem, op, nops, ops, ae) \
23215 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23217 #define UF(mnem, op, nops, ops, ae) \
23218 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23220 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
23221 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
23222 use the same encoding function for each. */
23223 #define NUF(mnem, op, nops, ops, enc) \
23224 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23225 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23227 /* Neon data processing, version which indirects through neon_enc_tab for
23228 the various overloaded versions of opcodes. */
23229 #define nUF(mnem, op, nops, ops, enc) \
23230 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23231 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23233 /* Neon insn with conditional suffix for the ARM version, non-overloaded
23235 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23236 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
23237 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23239 #define NCE(mnem, op, nops, ops, enc) \
23240 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23242 #define NCEF(mnem, op, nops, ops, enc) \
23243 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23245 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
23246 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23247 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
23248 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23250 #define nCE(mnem, op, nops, ops, enc) \
23251 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23253 #define nCEF(mnem, op, nops, ops, enc) \
23254 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23257 #define mCEF(mnem, op, nops, ops, enc) \
23258 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
23259 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23262 /* nCEF but for MVE predicated instructions. */
23263 #define mnCEF(mnem, op, nops, ops, enc) \
23264 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23266 /* nCE but for MVE predicated instructions. */
23267 #define mnCE(mnem, op, nops, ops, enc) \
23268 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23270 /* NUF but for potentially MVE predicated instructions. */
23271 #define MNUF(mnem, op, nops, ops, enc) \
23272 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23273 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23275 /* nUF but for potentially MVE predicated instructions. */
23276 #define mnUF(mnem, op, nops, ops, enc) \
23277 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23278 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23280 /* ToC but for potentially MVE predicated instructions. */
23281 #define mToC(mnem, top, nops, ops, te) \
23282 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23285 /* NCE but for MVE predicated instructions. */
23286 #define MNCE(mnem, op, nops, ops, enc) \
23287 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23289 /* NCEF but for MVE predicated instructions. */
23290 #define MNCEF(mnem, op, nops, ops, enc) \
23291 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23294 static const struct asm_opcode insns
[] =
23296 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
23297 #define THUMB_VARIANT & arm_ext_v4t
23298 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23299 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23300 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23301 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23302 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
23303 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
23304 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
23305 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
23306 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23307 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23308 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23309 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23310 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23311 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23312 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23313 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23315 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
23316 for setting PSR flag bits. They are obsolete in V6 and do not
23317 have Thumb equivalents. */
23318 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23319 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23320 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
23321 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23322 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23323 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
23324 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23325 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23326 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
23328 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
23329 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
23330 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23331 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23333 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
23334 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23335 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
23337 OP_ADDRGLDR
),ldst
, t_ldst
),
23338 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23340 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23341 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23342 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23343 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23344 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23345 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23347 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
23348 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
23351 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
23352 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
23353 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
23354 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
23356 /* Thumb-compatibility pseudo ops. */
23357 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23358 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23359 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23360 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23361 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23362 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23363 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23364 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23365 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
23366 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
23367 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
23368 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
23370 /* These may simplify to neg. */
23371 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23372 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23374 #undef THUMB_VARIANT
23375 #define THUMB_VARIANT & arm_ext_os
23377 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23378 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23380 #undef THUMB_VARIANT
23381 #define THUMB_VARIANT & arm_ext_v6
23383 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
23385 /* V1 instructions with no Thumb analogue prior to V6T2. */
23386 #undef THUMB_VARIANT
23387 #define THUMB_VARIANT & arm_ext_v6t2
23389 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23390 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23391 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
23393 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23394 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23395 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
23396 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23398 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23399 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23401 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23402 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23404 /* V1 instructions with no Thumb analogue at all. */
23405 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
23406 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
23408 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23409 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23410 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23411 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23412 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23413 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23414 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23415 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23418 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
23419 #undef THUMB_VARIANT
23420 #define THUMB_VARIANT & arm_ext_v4t
23422 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23423 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23425 #undef THUMB_VARIANT
23426 #define THUMB_VARIANT & arm_ext_v6t2
23428 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
23429 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
23431 /* Generic coprocessor instructions. */
23432 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
23433 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23434 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23435 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23436 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23437 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23438 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23441 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
23443 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23444 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23447 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
23448 #undef THUMB_VARIANT
23449 #define THUMB_VARIANT & arm_ext_msr
23451 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
23452 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
23455 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
23456 #undef THUMB_VARIANT
23457 #define THUMB_VARIANT & arm_ext_v6t2
23459 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23460 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23461 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23462 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23463 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23464 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23465 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23466 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23469 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
23470 #undef THUMB_VARIANT
23471 #define THUMB_VARIANT & arm_ext_v4t
23473 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23474 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23475 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23476 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23477 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23478 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23481 #define ARM_VARIANT & arm_ext_v4t_5
23483 /* ARM Architecture 4T. */
23484 /* Note: bx (and blx) are required on V5, even if the processor does
23485 not support Thumb. */
23486 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
23489 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
23490 #undef THUMB_VARIANT
23491 #define THUMB_VARIANT & arm_ext_v5t
23493 /* Note: blx has 2 variants; the .value coded here is for
23494 BLX(2). Only this variant has conditional execution. */
23495 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
23496 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
23498 #undef THUMB_VARIANT
23499 #define THUMB_VARIANT & arm_ext_v6t2
23501 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
23502 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23503 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23504 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23505 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23506 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
23507 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23508 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23511 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
23512 #undef THUMB_VARIANT
23513 #define THUMB_VARIANT & arm_ext_v5exp
23515 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23516 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23517 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23518 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23520 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23521 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23523 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23524 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23525 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23526 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23528 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23529 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23530 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23531 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23533 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23534 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23536 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23537 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23538 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23539 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23542 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
23543 #undef THUMB_VARIANT
23544 #define THUMB_VARIANT & arm_ext_v6t2
23546 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
23547 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
23549 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
23550 ADDRGLDRS
), ldrd
, t_ldstd
),
23552 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23553 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23556 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
23558 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
23561 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
23562 #undef THUMB_VARIANT
23563 #define THUMB_VARIANT & arm_ext_v6
23565 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
23566 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
23567 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23568 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23569 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23570 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23571 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23572 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23573 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23574 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
23576 #undef THUMB_VARIANT
23577 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23579 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
23580 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23582 #undef THUMB_VARIANT
23583 #define THUMB_VARIANT & arm_ext_v6t2
23585 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23586 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23588 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
23589 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
23591 /* ARM V6 not included in V7M. */
23592 #undef THUMB_VARIANT
23593 #define THUMB_VARIANT & arm_ext_v6_notm
23594 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23595 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23596 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
23597 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
23598 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
23599 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23600 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
23601 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
23602 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
23603 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23604 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23605 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23606 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
23607 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
23608 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
23609 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
23610 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
23611 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
23612 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
23614 /* ARM V6 not included in V7M (eg. integer SIMD). */
23615 #undef THUMB_VARIANT
23616 #define THUMB_VARIANT & arm_ext_v6_dsp
23617 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
23618 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
23619 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23620 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23621 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23622 /* Old name for QASX. */
23623 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23624 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23625 /* Old name for QSAX. */
23626 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23627 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23628 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23629 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23630 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23631 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23632 /* Old name for SASX. */
23633 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23634 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23635 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23636 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23637 /* Old name for SHASX. */
23638 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23639 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23640 /* Old name for SHSAX. */
23641 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23642 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23643 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23644 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23645 /* Old name for SSAX. */
23646 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23647 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23648 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23649 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23650 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23651 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23652 /* Old name for UASX. */
23653 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23654 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23655 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23656 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23657 /* Old name for UHASX. */
23658 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23659 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23660 /* Old name for UHSAX. */
23661 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23662 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23663 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23664 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23665 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23666 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23667 /* Old name for UQASX. */
23668 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23669 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23670 /* Old name for UQSAX. */
23671 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23672 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23673 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23674 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23675 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23676 /* Old name for USAX. */
23677 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23678 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23679 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23680 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23681 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23682 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23683 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23684 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23685 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23686 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23687 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23688 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23689 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23690 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23691 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23692 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23693 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23694 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23695 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23696 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23697 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23698 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23699 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23700 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23701 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23702 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23703 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23704 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23705 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23706 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
23707 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
23708 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23709 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23710 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
23713 #define ARM_VARIANT & arm_ext_v6k_v6t2
23714 #undef THUMB_VARIANT
23715 #define THUMB_VARIANT & arm_ext_v6k_v6t2
23717 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
23718 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
23719 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
23720 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
23722 #undef THUMB_VARIANT
23723 #define THUMB_VARIANT & arm_ext_v6_notm
23724 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
23726 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
23727 RRnpcb
), strexd
, t_strexd
),
23729 #undef THUMB_VARIANT
23730 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23731 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
23733 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
23735 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23737 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23739 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
23742 #define ARM_VARIANT & arm_ext_sec
23743 #undef THUMB_VARIANT
23744 #define THUMB_VARIANT & arm_ext_sec
23746 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
23749 #define ARM_VARIANT & arm_ext_virt
23750 #undef THUMB_VARIANT
23751 #define THUMB_VARIANT & arm_ext_virt
23753 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
23754 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
23757 #define ARM_VARIANT & arm_ext_pan
23758 #undef THUMB_VARIANT
23759 #define THUMB_VARIANT & arm_ext_pan
23761 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
23764 #define ARM_VARIANT & arm_ext_v6t2
23765 #undef THUMB_VARIANT
23766 #define THUMB_VARIANT & arm_ext_v6t2
23768 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
23769 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
23770 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
23771 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
23773 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
23774 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
23776 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23777 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23778 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23779 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23782 #define ARM_VARIANT & arm_ext_v3
23783 #undef THUMB_VARIANT
23784 #define THUMB_VARIANT & arm_ext_v6t2
23786 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
23787 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
23788 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
23791 #define ARM_VARIANT & arm_ext_v6t2
23792 #undef THUMB_VARIANT
23793 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23794 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
23795 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
23797 /* Thumb-only instructions. */
23799 #define ARM_VARIANT NULL
23800 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
23801 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
23803 /* ARM does not really have an IT instruction, so always allow it.
23804 The opcode is copied from Thumb in order to allow warnings in
23805 -mimplicit-it=[never | arm] modes. */
23807 #define ARM_VARIANT & arm_ext_v1
23808 #undef THUMB_VARIANT
23809 #define THUMB_VARIANT & arm_ext_v6t2
23811 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
23812 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
23813 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
23814 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
23815 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
23816 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
23817 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
23818 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
23819 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
23820 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
23821 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
23822 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
23823 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
23824 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
23825 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
23826 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
23827 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
23828 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
23830 /* Thumb2 only instructions. */
23832 #define ARM_VARIANT NULL
23834 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
23835 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
23836 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
23837 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
23838 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
23839 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
23841 /* Hardware division instructions. */
23843 #define ARM_VARIANT & arm_ext_adiv
23844 #undef THUMB_VARIANT
23845 #define THUMB_VARIANT & arm_ext_div
23847 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
23848 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
23850 /* ARM V6M/V7 instructions. */
23852 #define ARM_VARIANT & arm_ext_barrier
23853 #undef THUMB_VARIANT
23854 #define THUMB_VARIANT & arm_ext_barrier
23856 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
23857 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
23858 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
23860 /* ARM V7 instructions. */
23862 #define ARM_VARIANT & arm_ext_v7
23863 #undef THUMB_VARIANT
23864 #define THUMB_VARIANT & arm_ext_v7
23866 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
23867 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
23870 #define ARM_VARIANT & arm_ext_mp
23871 #undef THUMB_VARIANT
23872 #define THUMB_VARIANT & arm_ext_mp
23874 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
23876 /* AArchv8 instructions. */
23878 #define ARM_VARIANT & arm_ext_v8
23880 /* Instructions shared between armv8-a and armv8-m. */
23881 #undef THUMB_VARIANT
23882 #define THUMB_VARIANT & arm_ext_atomics
23884 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23885 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23886 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23887 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
23888 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
23889 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
23890 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23891 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
23892 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23893 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
23895 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
23897 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
23899 #undef THUMB_VARIANT
23900 #define THUMB_VARIANT & arm_ext_v8
23902 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
23903 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
23905 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
23908 /* Defined in V8 but is in undefined encoding space for earlier
23909 architectures. However earlier architectures are required to treat
23910 this instuction as a semihosting trap as well. Hence while not explicitly
23911 defined as such, it is in fact correct to define the instruction for all
23913 #undef THUMB_VARIANT
23914 #define THUMB_VARIANT & arm_ext_v1
23916 #define ARM_VARIANT & arm_ext_v1
23917 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
23919 /* ARMv8 T32 only. */
23921 #define ARM_VARIANT NULL
23922 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
23923 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
23924 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
23926 /* FP for ARMv8. */
23928 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
23929 #undef THUMB_VARIANT
23930 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
23932 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23933 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23934 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23935 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23936 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
23937 mnCE(vrintz
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintz
),
23938 mnCE(vrintx
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintx
),
23939 mnUF(vrinta
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrinta
),
23940 mnUF(vrintn
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintn
),
23941 mnUF(vrintp
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintp
),
23942 mnUF(vrintm
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintm
),
23944 /* Crypto v1 extensions. */
23946 #define ARM_VARIANT & fpu_crypto_ext_armv8
23947 #undef THUMB_VARIANT
23948 #define THUMB_VARIANT & fpu_crypto_ext_armv8
23950 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
23951 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
23952 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
23953 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
23954 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
23955 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
23956 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
23957 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
23958 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
23959 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
23960 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
23961 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
23962 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
23963 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
23966 #define ARM_VARIANT & crc_ext_armv8
23967 #undef THUMB_VARIANT
23968 #define THUMB_VARIANT & crc_ext_armv8
23969 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
23970 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
23971 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
23972 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
23973 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
23974 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
23976 /* ARMv8.2 RAS extension. */
23978 #define ARM_VARIANT & arm_ext_ras
23979 #undef THUMB_VARIANT
23980 #define THUMB_VARIANT & arm_ext_ras
23981 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
23984 #define ARM_VARIANT & arm_ext_v8_3
23985 #undef THUMB_VARIANT
23986 #define THUMB_VARIANT & arm_ext_v8_3
23987 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
23990 #define ARM_VARIANT & fpu_neon_ext_dotprod
23991 #undef THUMB_VARIANT
23992 #define THUMB_VARIANT & fpu_neon_ext_dotprod
23993 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
23994 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
23997 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
23998 #undef THUMB_VARIANT
23999 #define THUMB_VARIANT NULL
24001 cCE("wfs", e200110
, 1, (RR
), rd
),
24002 cCE("rfs", e300110
, 1, (RR
), rd
),
24003 cCE("wfc", e400110
, 1, (RR
), rd
),
24004 cCE("rfc", e500110
, 1, (RR
), rd
),
24006 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24007 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24008 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24009 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24011 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24012 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24013 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24014 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24016 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
24017 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
24018 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
24019 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
24020 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
24021 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
24022 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
24023 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
24024 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
24025 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
24026 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
24027 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
24029 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
24030 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
24031 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
24032 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
24033 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
24034 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
24035 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
24036 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
24037 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
24038 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
24039 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
24040 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
24042 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
24043 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
24044 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
24045 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
24046 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
24047 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
24048 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
24049 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
24050 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
24051 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
24052 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
24053 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
24055 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
24056 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
24057 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
24058 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
24059 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
24060 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
24061 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
24062 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
24063 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
24064 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
24065 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
24066 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
24068 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
24069 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
24070 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
24071 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
24072 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
24073 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
24074 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
24075 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
24076 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
24077 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
24078 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
24079 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
24081 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
24082 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
24083 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
24084 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
24085 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
24086 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
24087 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
24088 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
24089 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
24090 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
24091 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
24092 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
24094 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
24095 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
24096 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
24097 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
24098 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
24099 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
24100 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
24101 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
24102 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
24103 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
24104 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
24105 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
24107 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
24108 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
24109 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
24110 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
24111 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
24112 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
24113 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
24114 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
24115 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
24116 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
24117 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
24118 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
24120 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
24121 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
24122 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
24123 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
24124 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
24125 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
24126 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
24127 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
24128 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
24129 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
24130 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
24131 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
24133 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
24134 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
24135 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
24136 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
24137 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
24138 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
24139 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
24140 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
24141 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
24142 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
24143 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
24144 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
24146 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
24147 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
24148 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
24149 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
24150 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
24151 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
24152 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
24153 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
24154 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
24155 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
24156 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
24157 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
24159 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
24160 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
24161 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
24162 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
24163 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
24164 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
24165 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
24166 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
24167 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
24168 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
24169 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
24170 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
24172 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
24173 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
24174 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
24175 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
24176 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
24177 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
24178 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
24179 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
24180 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
24181 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
24182 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
24183 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
24185 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
24186 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
24187 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
24188 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
24189 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
24190 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
24191 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
24192 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
24193 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
24194 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
24195 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
24196 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
24198 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
24199 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
24200 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
24201 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
24202 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
24203 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
24204 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
24205 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
24206 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
24207 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
24208 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
24209 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
24211 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
24212 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
24213 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
24214 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
24215 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
24216 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
24217 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
24218 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
24219 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
24220 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
24221 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
24222 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
24224 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24225 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24226 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24227 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24228 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24229 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24230 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24231 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24232 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24233 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24234 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24235 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24237 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24238 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24239 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24240 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24241 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24242 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24243 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24244 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24245 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24246 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24247 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24248 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24250 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24251 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24252 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24253 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24254 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24255 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24256 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24257 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24258 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24259 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24260 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24261 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24263 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24264 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24265 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24266 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24267 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24268 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24269 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24270 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24271 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24272 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24273 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24274 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24276 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24277 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24278 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24279 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24280 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24281 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24282 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24283 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24284 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24285 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24286 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24287 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24289 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24290 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24291 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24292 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24293 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24294 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24295 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24296 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24297 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24298 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24299 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24300 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24302 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24303 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24304 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24305 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24306 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24307 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24308 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24309 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24310 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24311 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24312 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24313 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24315 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24316 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24317 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24318 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24319 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24320 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24321 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24322 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24323 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24324 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24325 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24326 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24328 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24329 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24330 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24331 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24332 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24333 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24334 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24335 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24336 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24337 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24338 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24339 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24341 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24342 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24343 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24344 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24345 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24346 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24347 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24348 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24349 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24350 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24351 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24352 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24354 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24355 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24356 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24357 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24358 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24359 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24360 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24361 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24362 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24363 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24364 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24365 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24367 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24368 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24369 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24370 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24371 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24372 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24373 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24374 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24375 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24376 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24377 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24378 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24380 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24381 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24382 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24383 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24384 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24385 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24386 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24387 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24388 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24389 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24390 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24391 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24393 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24394 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24395 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24396 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24398 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
24399 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
24400 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
24401 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
24402 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
24403 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
24404 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
24405 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
24406 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
24407 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
24408 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
24409 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
24411 /* The implementation of the FIX instruction is broken on some
24412 assemblers, in that it accepts a precision specifier as well as a
24413 rounding specifier, despite the fact that this is meaningless.
24414 To be more compatible, we accept it as well, though of course it
24415 does not set any bits. */
24416 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
24417 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
24418 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
24419 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
24420 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
24421 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
24422 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
24423 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
24424 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
24425 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
24426 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
24427 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
24428 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
24430 /* Instructions that were new with the real FPA, call them V2. */
24432 #define ARM_VARIANT & fpu_fpa_ext_v2
24434 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24435 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24436 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24437 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24438 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24439 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24442 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
24444 /* Moves and type conversions. */
24445 cCE("fmstat", ef1fa10
, 0, (), noargs
),
24446 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
24447 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
24448 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24449 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24450 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24451 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24452 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24453 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24454 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
24455 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
24457 /* Memory operations. */
24458 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24459 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24460 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24461 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24462 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24463 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24464 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24465 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24466 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24467 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24468 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24469 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24470 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24471 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24472 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24473 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24474 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24475 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24477 /* Monadic operations. */
24478 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24479 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24480 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24482 /* Dyadic operations. */
24483 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24484 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24485 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24486 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24487 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24488 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24489 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24490 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24491 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24494 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24495 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
24496 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24497 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
24499 /* Double precision load/store are still present on single precision
24500 implementations. */
24501 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
24502 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
24503 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24504 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24505 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24506 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24507 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24508 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24509 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24510 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24513 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
24515 /* Moves and type conversions. */
24516 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24517 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24518 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
24519 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
24520 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
24521 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
24522 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24523 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24524 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24525 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24526 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24527 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24529 /* Monadic operations. */
24530 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24531 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24532 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24534 /* Dyadic operations. */
24535 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24536 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24537 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24538 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24539 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24540 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24541 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24542 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24543 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24546 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24547 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
24548 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24549 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
24551 /* Instructions which may belong to either the Neon or VFP instruction sets.
24552 Individual encoder functions perform additional architecture checks. */
24554 #define ARM_VARIANT & fpu_vfp_ext_v1xd
24555 #undef THUMB_VARIANT
24556 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
24558 /* These mnemonics are unique to VFP. */
24559 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
24560 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
24561 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24562 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24563 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24564 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
24565 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
24566 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
24568 /* Mnemonics shared by Neon and VFP. */
24569 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
24571 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24572 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24573 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24574 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24575 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24576 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24578 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
24579 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
24580 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
24581 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
24584 /* NOTE: All VMOV encoding is special-cased! */
24585 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
24587 #undef THUMB_VARIANT
24588 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
24589 by different feature bits. Since we are setting the Thumb guard, we can
24590 require Thumb-1 which makes it a nop guard and set the right feature bit in
24591 do_vldr_vstr (). */
24592 #define THUMB_VARIANT & arm_ext_v4t
24593 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
24594 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
24597 #define ARM_VARIANT & arm_ext_fp16
24598 #undef THUMB_VARIANT
24599 #define THUMB_VARIANT & arm_ext_fp16
24600 /* New instructions added from v8.2, allowing the extraction and insertion of
24601 the upper 16 bits of a 32-bit vector register. */
24602 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
24603 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
24605 /* New backported fma/fms instructions optional in v8.2. */
24606 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
24607 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
24609 #undef THUMB_VARIANT
24610 #define THUMB_VARIANT & fpu_neon_ext_v1
24612 #define ARM_VARIANT & fpu_neon_ext_v1
24614 /* Data processing with three registers of the same length. */
24615 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
24616 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
24617 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
24618 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24619 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24620 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24621 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
24622 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
24623 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
24624 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
24625 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
24626 /* If not immediate, fall back to neon_dyadic_i64_su.
24627 shl should accept I8 I16 I32 I64,
24628 qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */
24629 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl
),
24630 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl
),
24631 /* Logic ops, types optional & ignored. */
24632 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24633 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24634 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24635 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24636 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
24637 /* Bitfield ops, untyped. */
24638 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24639 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24640 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24641 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24642 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24643 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24644 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
24645 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24646 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24647 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24648 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
24649 back to neon_dyadic_if_su. */
24650 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
24651 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
24652 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
24653 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
24654 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
24655 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
24656 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
24657 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
24658 /* Comparison. Type I8 I16 I32 F32. */
24659 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
24660 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
24661 /* As above, D registers only. */
24662 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
24663 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
24664 /* Int and float variants, signedness unimportant. */
24665 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
24666 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
24667 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
24668 /* Add/sub take types I8 I16 I32 I64 F32. */
24669 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
24670 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
24671 /* vtst takes sizes 8, 16, 32. */
24672 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
24673 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
24674 /* VMUL takes I8 I16 I32 F32 P8. */
24675 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
24676 /* VQD{R}MULH takes S16 S32. */
24677 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
24678 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
24679 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
24680 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
24681 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
24682 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
24683 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
24684 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
24685 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
24686 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
24687 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
24688 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
24689 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
24690 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
24691 /* ARM v8.1 extension. */
24692 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
24693 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
24694 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
24696 /* Two address, int/float. Types S8 S16 S32 F32. */
24697 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
24698 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
24700 /* Data processing with two registers and a shift amount. */
24701 /* Right shifts, and variants with rounding.
24702 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
24703 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
24704 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
24705 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
24706 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
24707 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
24708 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
24709 /* Shift and insert. Sizes accepted 8 16 32 64. */
24710 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
24711 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
24712 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
24713 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
24714 /* Right shift immediate, saturating & narrowing, with rounding variants.
24715 Types accepted S16 S32 S64 U16 U32 U64. */
24716 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
24717 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
24718 /* As above, unsigned. Types accepted S16 S32 S64. */
24719 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
24720 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
24721 /* Right shift narrowing. Types accepted I16 I32 I64. */
24722 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
24723 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
24724 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
24725 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
24726 /* CVT with optional immediate for fixed-point variant. */
24727 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
24729 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
24731 /* Data processing, three registers of different lengths. */
24732 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
24733 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
24734 /* If not scalar, fall back to neon_dyadic_long.
24735 Vector types as above, scalar types S16 S32 U16 U32. */
24736 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
24737 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
24738 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
24739 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
24740 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
24741 /* Dyadic, narrowing insns. Types I16 I32 I64. */
24742 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24743 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24744 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24745 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24746 /* Saturating doubling multiplies. Types S16 S32. */
24747 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24748 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24749 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24750 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
24751 S16 S32 U16 U32. */
24752 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
24754 /* Extract. Size 8. */
24755 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
24756 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
24758 /* Two registers, miscellaneous. */
24759 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
24760 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
24761 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
24762 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
24763 /* Vector replicate. Sizes 8 16 32. */
24764 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
24765 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
24766 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
24767 /* VMOVN. Types I16 I32 I64. */
24768 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
24769 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
24770 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
24771 /* VQMOVUN. Types S16 S32 S64. */
24772 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
24773 /* VZIP / VUZP. Sizes 8 16 32. */
24774 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
24775 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
24776 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
24777 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
24778 /* VQABS / VQNEG. Types S8 S16 S32. */
24779 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
24780 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
24781 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
24782 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
24783 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
24784 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
24785 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
24786 /* Reciprocal estimates. Types U32 F16 F32. */
24787 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
24788 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
24789 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
24790 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
24791 /* VCLS. Types S8 S16 S32. */
24792 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
24793 /* VCLZ. Types I8 I16 I32. */
24794 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
24795 /* VCNT. Size 8. */
24796 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
24797 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
24798 /* Two address, untyped. */
24799 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
24800 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
24801 /* VTRN. Sizes 8 16 32. */
24802 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
24803 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
24805 /* Table lookup. Size 8. */
24806 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
24807 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
24809 #undef THUMB_VARIANT
24810 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
24812 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
24814 /* Neon element/structure load/store. */
24815 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24816 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24817 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24818 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24819 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24820 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24821 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24822 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24824 #undef THUMB_VARIANT
24825 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
24827 #define ARM_VARIANT & fpu_vfp_ext_v3xd
24828 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
24829 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24830 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24831 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24832 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24833 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24834 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24835 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24836 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24838 #undef THUMB_VARIANT
24839 #define THUMB_VARIANT & fpu_vfp_ext_v3
24841 #define ARM_VARIANT & fpu_vfp_ext_v3
24843 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
24844 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24845 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24846 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24847 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24848 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24849 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24850 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24851 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24854 #define ARM_VARIANT & fpu_vfp_ext_fma
24855 #undef THUMB_VARIANT
24856 #define THUMB_VARIANT & fpu_vfp_ext_fma
24857 /* Mnemonics shared by Neon, VFP and MVE. These are included in the
24858 VFP FMA variant; NEON and VFP FMA always includes the NEON
24859 FMA instructions. */
24860 mnCEF(vfma
, _vfma
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_fmac
),
24861 mnCEF(vfms
, _vfms
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), neon_fmac
),
24863 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
24864 the v form should always be used. */
24865 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24866 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24867 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24868 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24869 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24870 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24872 #undef THUMB_VARIANT
24874 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
24876 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24877 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24878 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24879 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24880 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24881 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24882 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
24883 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
24886 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
24888 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
24889 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
24890 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
24891 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
24892 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
24893 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
24894 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
24895 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
24896 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
24897 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24898 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24899 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24900 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24901 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24902 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24903 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
24904 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
24905 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
24906 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
24907 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
24908 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24909 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24910 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24911 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24912 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24913 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24914 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
24915 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
24916 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
24917 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
24918 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
24919 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
24920 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
24921 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
24922 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24923 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24924 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24925 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24926 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24927 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24928 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24929 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24930 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24931 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24932 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24933 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24934 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
24935 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24936 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24937 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24938 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24939 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24940 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24941 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24942 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24943 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24944 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24945 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24946 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24947 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24948 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24949 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24950 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24951 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24952 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24953 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24954 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24955 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24956 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
24957 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
24958 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24959 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24960 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24961 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24962 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24963 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24964 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24965 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24966 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24967 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24968 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24969 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24970 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24971 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24972 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24973 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24974 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24975 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24976 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
24977 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24978 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24979 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24980 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24981 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24982 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24983 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24984 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24985 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24986 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24987 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24988 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24989 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24990 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24991 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24992 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24993 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24994 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24995 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24996 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24997 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24998 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
24999 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25000 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25001 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25002 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25003 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25004 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25005 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25006 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25007 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25008 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25009 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25010 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25011 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25012 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25013 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25014 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25015 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25016 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25017 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25018 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25019 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
25020 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
25021 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25022 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25023 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25024 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25025 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25026 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25027 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25028 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25029 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25030 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25031 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25032 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25033 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25034 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25035 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25036 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25037 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25038 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25039 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25040 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25041 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25042 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25043 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25044 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25045 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25046 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25047 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25048 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25049 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
25052 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
25054 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
25055 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
25056 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
25057 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25058 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25059 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25060 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25061 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25062 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25063 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25064 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25065 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25066 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25067 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25068 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25069 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25070 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25071 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25072 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25073 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25074 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
25075 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25076 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25077 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25078 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25079 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25080 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25081 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25082 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25083 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25084 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25085 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25086 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25087 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25088 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25089 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25090 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25091 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25092 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25093 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25094 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25095 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25096 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25097 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25098 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25099 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25100 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25101 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25102 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25103 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25104 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25105 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25106 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25107 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25108 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25109 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25110 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25113 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
25115 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
25116 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
25117 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
25118 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
25119 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
25120 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
25121 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
25122 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
25123 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
25124 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
25125 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
25126 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
25127 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
25128 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
25129 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
25130 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
25131 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
25132 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
25133 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
25134 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
25135 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
25136 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
25137 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
25138 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
25139 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
25140 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
25141 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
25142 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
25143 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
25144 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
25145 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
25146 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
25147 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
25148 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
25149 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
25150 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
25151 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
25152 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
25153 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
25154 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
25155 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
25156 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
25157 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
25158 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
25159 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
25160 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
25161 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
25162 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
25163 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
25164 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
25165 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
25166 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
25167 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
25168 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
25169 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25170 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25171 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25172 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25173 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25174 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25175 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
25176 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
25177 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
25178 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
25179 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25180 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25181 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25182 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25183 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25184 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25185 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25186 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25187 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
25188 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
25189 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
25190 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
25192 /* ARMv8.5-A instructions. */
25194 #define ARM_VARIANT & arm_ext_sb
25195 #undef THUMB_VARIANT
25196 #define THUMB_VARIANT & arm_ext_sb
25197 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
25200 #define ARM_VARIANT & arm_ext_predres
25201 #undef THUMB_VARIANT
25202 #define THUMB_VARIANT & arm_ext_predres
25203 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
25204 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
25205 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
25207 /* ARMv8-M instructions. */
25209 #define ARM_VARIANT NULL
25210 #undef THUMB_VARIANT
25211 #define THUMB_VARIANT & arm_ext_v8m
25212 ToU("sg", e97fe97f
, 0, (), noargs
),
25213 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
25214 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
25215 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
25216 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
25217 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
25218 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
25220 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
25221 instructions behave as nop if no VFP is present. */
25222 #undef THUMB_VARIANT
25223 #define THUMB_VARIANT & arm_ext_v8m_main
25224 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
25225 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
25227 /* Armv8.1-M Mainline instructions. */
25228 #undef THUMB_VARIANT
25229 #define THUMB_VARIANT & arm_ext_v8_1m_main
25230 toU("cinc", _cinc
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25231 toU("cinv", _cinv
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25232 toU("cneg", _cneg
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25233 toU("csel", _csel
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25234 toU("csetm", _csetm
, 2, (RRnpcsp
, COND
), t_cond
),
25235 toU("cset", _cset
, 2, (RRnpcsp
, COND
), t_cond
),
25236 toU("csinc", _csinc
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25237 toU("csinv", _csinv
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25238 toU("csneg", _csneg
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25240 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
25241 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
25242 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
25243 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
25244 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
25246 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
25247 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
25248 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
25250 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
25251 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
25253 #undef THUMB_VARIANT
25254 #define THUMB_VARIANT & mve_ext
25255 ToC("lsll", ea50010d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
25256 ToC("lsrl", ea50011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25257 ToC("asrl", ea50012d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
25258 ToC("uqrshll", ea51010d
, 3, (RRe
, RRo
, RRnpcsp
), mve_scalar_shift
),
25259 ToC("sqrshrl", ea51012d
, 3, (RRe
, RRo
, RRnpcsp
), mve_scalar_shift
),
25260 ToC("uqshll", ea51010f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25261 ToC("urshrl", ea51011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25262 ToC("srshrl", ea51012f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25263 ToC("sqshll", ea51013f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25264 ToC("uqrshl", ea500f0d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
25265 ToC("sqrshr", ea500f2d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
25266 ToC("uqshl", ea500f0f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25267 ToC("urshr", ea500f1f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25268 ToC("srshr", ea500f2f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25269 ToC("sqshl", ea500f3f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25271 ToC("vpt", ee410f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25272 ToC("vptt", ee018f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25273 ToC("vpte", ee418f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25274 ToC("vpttt", ee014f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25275 ToC("vptte", ee01cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25276 ToC("vptet", ee41cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25277 ToC("vptee", ee414f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25278 ToC("vptttt", ee012f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25279 ToC("vpttte", ee016f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25280 ToC("vpttet", ee01ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25281 ToC("vpttee", ee01af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25282 ToC("vptett", ee41af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25283 ToC("vptete", ee41ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25284 ToC("vpteet", ee416f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25285 ToC("vpteee", ee412f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25287 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
25288 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
25289 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
25290 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
25291 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
25292 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
25293 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
25294 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
25295 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
25296 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
25297 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
25298 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
25299 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
25300 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
25301 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
25303 /* MVE and MVE FP only. */
25304 mToC("vhcadd", ee000f00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vhcadd
),
25305 mCEF(vadc
, _vadc
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
25306 mCEF(vadci
, _vadci
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
25307 mToC("vsbc", fe300f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
25308 mToC("vsbci", fe301f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
25309 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
25310 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
25311 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25312 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25313 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25314 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25315 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25316 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25317 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25318 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25319 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25320 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25322 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25323 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25324 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25325 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25326 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25327 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25328 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25329 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25330 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25331 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25332 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25333 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25334 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25335 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25336 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25337 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25338 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25339 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25340 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25341 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25343 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
25344 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
25345 mCEF(vbrsr
, _vbrsr
, 3, (RMQ
, RMQ
, RR
), mve_vbrsr
),
25346 mCEF(vaddlv
, _vaddlv
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25347 mCEF(vaddlva
, _vaddlva
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25348 mCEF(vaddv
, _vaddv
, 2, (RRe
, RMQ
), mve_vaddv
),
25349 mCEF(vaddva
, _vaddva
, 2, (RRe
, RMQ
), mve_vaddv
),
25350 mCEF(vddup
, _vddup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25351 mCEF(vdwdup
, _vdwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25352 mCEF(vidup
, _vidup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25353 mCEF(viwdup
, _viwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25354 mToC("vmaxa", ee330e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25355 mToC("vmina", ee331e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25356 mCEF(vmaxv
, _vmaxv
, 2, (RR
, RMQ
), mve_vmaxv
),
25357 mCEF(vmaxav
, _vmaxav
, 2, (RR
, RMQ
), mve_vmaxv
),
25358 mCEF(vminv
, _vminv
, 2, (RR
, RMQ
), mve_vmaxv
),
25359 mCEF(vminav
, _vminav
, 2, (RR
, RMQ
), mve_vmaxv
),
25361 mCEF(vmlaldav
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25362 mCEF(vmlaldava
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25363 mCEF(vmlaldavx
, _vmlaldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25364 mCEF(vmlaldavax
, _vmlaldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25365 mCEF(vmlalv
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25366 mCEF(vmlalva
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25367 mCEF(vmlsldav
, _vmlsldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25368 mCEF(vmlsldava
, _vmlsldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25369 mCEF(vmlsldavx
, _vmlsldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25370 mCEF(vmlsldavax
, _vmlsldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25371 mToC("vrmlaldavh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25372 mToC("vrmlaldavha",ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25373 mCEF(vrmlaldavhx
, _vrmlaldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25374 mCEF(vrmlaldavhax
, _vrmlaldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25375 mToC("vrmlalvh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25376 mToC("vrmlalvha", ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25377 mCEF(vrmlsldavh
, _vrmlsldavh
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25378 mCEF(vrmlsldavha
, _vrmlsldavha
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25379 mCEF(vrmlsldavhx
, _vrmlsldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25380 mCEF(vrmlsldavhax
, _vrmlsldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25382 mToC("vmlas", ee011e40
, 3, (RMQ
, RMQ
, RR
), mve_vmlas
),
25383 mToC("vmulh", ee010e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25384 mToC("vrmulh", ee011e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25385 mToC("vpnot", fe310f4d
, 0, (), mve_vpnot
),
25386 mToC("vpsel", fe310f01
, 3, (RMQ
, RMQ
, RMQ
), mve_vpsel
),
25388 mToC("vqdmladh", ee000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25389 mToC("vqdmladhx", ee001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25390 mToC("vqrdmladh", ee000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25391 mToC("vqrdmladhx",ee001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25392 mToC("vqdmlsdh", fe000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25393 mToC("vqdmlsdhx", fe001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25394 mToC("vqrdmlsdh", fe000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25395 mToC("vqrdmlsdhx",fe001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25396 mToC("vqdmlah", ee000e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25397 mToC("vqdmlash", ee001e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25398 mToC("vqrdmlash", ee001e40
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25399 mToC("vqdmullt", ee301f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25400 mToC("vqdmullb", ee300f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25401 mCEF(vqmovnt
, _vqmovnt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25402 mCEF(vqmovnb
, _vqmovnb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25403 mCEF(vqmovunt
, _vqmovunt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25404 mCEF(vqmovunb
, _vqmovunb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25406 mCEF(vshrnt
, _vshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25407 mCEF(vshrnb
, _vshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25408 mCEF(vrshrnt
, _vrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25409 mCEF(vrshrnb
, _vrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25410 mCEF(vqshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25411 mCEF(vqshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25412 mCEF(vqshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25413 mCEF(vqshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25414 mCEF(vqrshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25415 mCEF(vqrshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25416 mCEF(vqrshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25417 mCEF(vqrshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25419 mToC("vshlc", eea00fc0
, 3, (RMQ
, RR
, I32z
), mve_vshlc
),
25420 mToC("vshllt", ee201e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
25421 mToC("vshllb", ee200e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
25423 toU("dlstp", _dlstp
, 2, (LR
, RR
), t_loloop
),
25424 toU("wlstp", _wlstp
, 3, (LR
, RR
, EXP
), t_loloop
),
25425 toU("letp", _letp
, 2, (LR
, EXP
), t_loloop
),
25426 toU("lctp", _lctp
, 0, (), t_loloop
),
25428 #undef THUMB_VARIANT
25429 #define THUMB_VARIANT & mve_fp_ext
25430 mToC("vcmul", ee300e00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vcmul
),
25431 mToC("vfmas", ee311e40
, 3, (RMQ
, RMQ
, RR
), mve_vfmas
),
25432 mToC("vmaxnma", ee3f0e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25433 mToC("vminnma", ee3f1e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25434 mToC("vmaxnmv", eeee0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25435 mToC("vmaxnmav",eeec0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25436 mToC("vminnmv", eeee0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25437 mToC("vminnmav",eeec0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25440 #define ARM_VARIANT & fpu_vfp_ext_v1
25441 #undef THUMB_VARIANT
25442 #define THUMB_VARIANT & arm_ext_v6t2
25443 mnCEF(vmla
, _vmla
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mac_maybe_scalar
),
25444 mnCEF(vmul
, _vmul
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mul
),
25446 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25449 #define ARM_VARIANT & fpu_vfp_ext_v1xd
25451 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
25452 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
25453 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
25454 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25456 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
25457 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25458 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25460 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25461 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25463 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
25464 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
25466 mnCE(vcmp
, _vcmp
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25467 mnCE(vcmpe
, _vcmpe
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25470 #define ARM_VARIANT & fpu_vfp_ext_v2
25472 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
25473 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
25474 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
25475 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
25478 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
25479 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
25480 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
25481 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
25482 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
25483 mnUF(vmaxnm
, _vmaxnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
25484 mnUF(vminnm
, _vminnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
25487 #define ARM_VARIANT & fpu_neon_ext_v1
25488 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25489 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
25490 mnUF(vaddl
, _vaddl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
25491 mnUF(vsubl
, _vsubl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
25492 mnUF(vand
, _vand
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25493 mnUF(vbic
, _vbic
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25494 mnUF(vorr
, _vorr
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25495 mnUF(vorn
, _vorn
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25496 mnUF(veor
, _veor
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_logic
),
25497 MNUF(vcls
, 1b00400
, 2, (RNDQMQ
, RNDQMQ
), neon_cls
),
25498 MNUF(vclz
, 1b00480
, 2, (RNDQMQ
, RNDQMQ
), neon_clz
),
25499 mnCE(vdup
, _vdup
, 2, (RNDQMQ
, RR_RNSC
), neon_dup
),
25500 MNUF(vhadd
, 00000000, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
25501 MNUF(vrhadd
, 00000100, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_i_su
),
25502 MNUF(vhsub
, 00000200, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
25503 mnUF(vmin
, _vmin
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25504 mnUF(vmax
, _vmax
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25505 MNUF(vqadd
, 0000010, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
25506 MNUF(vqsub
, 0000210, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
25507 mnUF(vmvn
, _vmvn
, 2, (RNDQMQ
, RNDQMQ_Ibig
), neon_mvn
),
25508 MNUF(vqabs
, 1b00700
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
25509 MNUF(vqneg
, 1b00780
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
25510 mnUF(vqrdmlah
, _vqrdmlah
,3, (RNDQMQ
, oRNDQMQ
, RNDQ_RNSC_RR
), neon_qrdmlah
),
25511 mnUF(vqdmulh
, _vqdmulh
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
25512 mnUF(vqrdmulh
, _vqrdmulh
,3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
25513 MNUF(vqrshl
, 0000510, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
25514 MNUF(vrshl
, 0000500, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
25515 MNUF(vshr
, 0800010, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
25516 MNUF(vrshr
, 0800210, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
25517 MNUF(vsli
, 1800510, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_sli
),
25518 MNUF(vsri
, 1800410, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_sri
),
25519 MNUF(vrev64
, 1b00000
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25520 MNUF(vrev32
, 1b00080
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25521 MNUF(vrev16
, 1b00100
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25522 mnUF(vshl
, _vshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_shl
),
25523 mnUF(vqshl
, _vqshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_qshl
),
25524 MNUF(vqshlu
, 1800610, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_qshlu_imm
),
25527 #define ARM_VARIANT & arm_ext_v8_3
25528 #undef THUMB_VARIANT
25529 #define THUMB_VARIANT & arm_ext_v6t2_v8m
25530 MNUF (vcadd
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ
, EXPi
), vcadd
),
25531 MNUF (vcmla
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ_RNSC
, EXPi
), vcmla
),
25534 #undef THUMB_VARIANT
25566 /* MD interface: bits in the object file. */
25568 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
25569 for use in the a.out file, and stores them in the array pointed to by buf.
25570 This knows about the endian-ness of the target machine and does
25571 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
25572 2 (short) and 4 (long) Floating numbers are put out as a series of
25573 LITTLENUMS (shorts, here at least). */
25576 md_number_to_chars (char * buf
, valueT val
, int n
)
25578 if (target_big_endian
)
25579 number_to_chars_bigendian (buf
, val
, n
);
25581 number_to_chars_littleendian (buf
, val
, n
);
25585 md_chars_to_number (char * buf
, int n
)
25588 unsigned char * where
= (unsigned char *) buf
;
25590 if (target_big_endian
)
25595 result
|= (*where
++ & 255);
25603 result
|= (where
[n
] & 255);
25610 /* MD interface: Sections. */
25612 /* Calculate the maximum variable size (i.e., excluding fr_fix)
25613 that an rs_machine_dependent frag may reach. */
25616 arm_frag_max_var (fragS
*fragp
)
25618 /* We only use rs_machine_dependent for variable-size Thumb instructions,
25619 which are either THUMB_SIZE (2) or INSN_SIZE (4).
25621 Note that we generate relaxable instructions even for cases that don't
25622 really need it, like an immediate that's a trivial constant. So we're
25623 overestimating the instruction size for some of those cases. Rather
25624 than putting more intelligence here, it would probably be better to
25625 avoid generating a relaxation frag in the first place when it can be
25626 determined up front that a short instruction will suffice. */
25628 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
25632 /* Estimate the size of a frag before relaxing. Assume everything fits in
25636 md_estimate_size_before_relax (fragS
* fragp
,
25637 segT segtype ATTRIBUTE_UNUSED
)
25643 /* Convert a machine dependent frag. */
25646 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
25648 unsigned long insn
;
25649 unsigned long old_op
;
25657 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
25659 old_op
= bfd_get_16(abfd
, buf
);
25660 if (fragp
->fr_symbol
)
25662 exp
.X_op
= O_symbol
;
25663 exp
.X_add_symbol
= fragp
->fr_symbol
;
25667 exp
.X_op
= O_constant
;
25669 exp
.X_add_number
= fragp
->fr_offset
;
25670 opcode
= fragp
->fr_subtype
;
25673 case T_MNEM_ldr_pc
:
25674 case T_MNEM_ldr_pc2
:
25675 case T_MNEM_ldr_sp
:
25676 case T_MNEM_str_sp
:
25683 if (fragp
->fr_var
== 4)
25685 insn
= THUMB_OP32 (opcode
);
25686 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
25688 insn
|= (old_op
& 0x700) << 4;
25692 insn
|= (old_op
& 7) << 12;
25693 insn
|= (old_op
& 0x38) << 13;
25695 insn
|= 0x00000c00;
25696 put_thumb32_insn (buf
, insn
);
25697 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
25701 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
25703 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
25706 if (fragp
->fr_var
== 4)
25708 insn
= THUMB_OP32 (opcode
);
25709 insn
|= (old_op
& 0xf0) << 4;
25710 put_thumb32_insn (buf
, insn
);
25711 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
25715 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25716 exp
.X_add_number
-= 4;
25724 if (fragp
->fr_var
== 4)
25726 int r0off
= (opcode
== T_MNEM_mov
25727 || opcode
== T_MNEM_movs
) ? 0 : 8;
25728 insn
= THUMB_OP32 (opcode
);
25729 insn
= (insn
& 0xe1ffffff) | 0x10000000;
25730 insn
|= (old_op
& 0x700) << r0off
;
25731 put_thumb32_insn (buf
, insn
);
25732 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
25736 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
25741 if (fragp
->fr_var
== 4)
25743 insn
= THUMB_OP32(opcode
);
25744 put_thumb32_insn (buf
, insn
);
25745 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
25748 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
25752 if (fragp
->fr_var
== 4)
25754 insn
= THUMB_OP32(opcode
);
25755 insn
|= (old_op
& 0xf00) << 14;
25756 put_thumb32_insn (buf
, insn
);
25757 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
25760 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
25763 case T_MNEM_add_sp
:
25764 case T_MNEM_add_pc
:
25765 case T_MNEM_inc_sp
:
25766 case T_MNEM_dec_sp
:
25767 if (fragp
->fr_var
== 4)
25769 /* ??? Choose between add and addw. */
25770 insn
= THUMB_OP32 (opcode
);
25771 insn
|= (old_op
& 0xf0) << 4;
25772 put_thumb32_insn (buf
, insn
);
25773 if (opcode
== T_MNEM_add_pc
)
25774 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
25776 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
25779 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25787 if (fragp
->fr_var
== 4)
25789 insn
= THUMB_OP32 (opcode
);
25790 insn
|= (old_op
& 0xf0) << 4;
25791 insn
|= (old_op
& 0xf) << 16;
25792 put_thumb32_insn (buf
, insn
);
25793 if (insn
& (1 << 20))
25794 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
25796 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
25799 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25805 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
25806 (enum bfd_reloc_code_real
) reloc_type
);
25807 fixp
->fx_file
= fragp
->fr_file
;
25808 fixp
->fx_line
= fragp
->fr_line
;
25809 fragp
->fr_fix
+= fragp
->fr_var
;
25811 /* Set whether we use thumb-2 ISA based on final relaxation results. */
25812 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
25813 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
25814 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
25817 /* Return the size of a relaxable immediate operand instruction.
25818 SHIFT and SIZE specify the form of the allowable immediate. */
25820 relax_immediate (fragS
*fragp
, int size
, int shift
)
25826 /* ??? Should be able to do better than this. */
25827 if (fragp
->fr_symbol
)
25830 low
= (1 << shift
) - 1;
25831 mask
= (1 << (shift
+ size
)) - (1 << shift
);
25832 offset
= fragp
->fr_offset
;
25833 /* Force misaligned offsets to 32-bit variant. */
25836 if (offset
& ~mask
)
25841 /* Get the address of a symbol during relaxation. */
25843 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
25849 sym
= fragp
->fr_symbol
;
25850 sym_frag
= symbol_get_frag (sym
);
25851 know (S_GET_SEGMENT (sym
) != absolute_section
25852 || sym_frag
== &zero_address_frag
);
25853 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
25855 /* If frag has yet to be reached on this pass, assume it will
25856 move by STRETCH just as we did. If this is not so, it will
25857 be because some frag between grows, and that will force
25861 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
25865 /* Adjust stretch for any alignment frag. Note that if have
25866 been expanding the earlier code, the symbol may be
25867 defined in what appears to be an earlier frag. FIXME:
25868 This doesn't handle the fr_subtype field, which specifies
25869 a maximum number of bytes to skip when doing an
25871 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
25873 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
25876 stretch
= - ((- stretch
)
25877 & ~ ((1 << (int) f
->fr_offset
) - 1));
25879 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
25891 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
25894 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
25899 /* Assume worst case for symbols not known to be in the same section. */
25900 if (fragp
->fr_symbol
== NULL
25901 || !S_IS_DEFINED (fragp
->fr_symbol
)
25902 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
25903 || S_IS_WEAK (fragp
->fr_symbol
))
25906 val
= relaxed_symbol_addr (fragp
, stretch
);
25907 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
25908 addr
= (addr
+ 4) & ~3;
25909 /* Force misaligned targets to 32-bit variant. */
25913 if (val
< 0 || val
> 1020)
25918 /* Return the size of a relaxable add/sub immediate instruction. */
25920 relax_addsub (fragS
*fragp
, asection
*sec
)
25925 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
25926 op
= bfd_get_16(sec
->owner
, buf
);
25927 if ((op
& 0xf) == ((op
>> 4) & 0xf))
25928 return relax_immediate (fragp
, 8, 0);
25930 return relax_immediate (fragp
, 3, 0);
25933 /* Return TRUE iff the definition of symbol S could be pre-empted
25934 (overridden) at link or load time. */
25936 symbol_preemptible (symbolS
*s
)
25938 /* Weak symbols can always be pre-empted. */
25942 /* Non-global symbols cannot be pre-empted. */
25943 if (! S_IS_EXTERNAL (s
))
25947 /* In ELF, a global symbol can be marked protected, or private. In that
25948 case it can't be pre-empted (other definitions in the same link unit
25949 would violate the ODR). */
25950 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
25954 /* Other global symbols might be pre-empted. */
25958 /* Return the size of a relaxable branch instruction. BITS is the
25959 size of the offset field in the narrow instruction. */
25962 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
25968 /* Assume worst case for symbols not known to be in the same section. */
25969 if (!S_IS_DEFINED (fragp
->fr_symbol
)
25970 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
25971 || S_IS_WEAK (fragp
->fr_symbol
))
25975 /* A branch to a function in ARM state will require interworking. */
25976 if (S_IS_DEFINED (fragp
->fr_symbol
)
25977 && ARM_IS_FUNC (fragp
->fr_symbol
))
25981 if (symbol_preemptible (fragp
->fr_symbol
))
25984 val
= relaxed_symbol_addr (fragp
, stretch
);
25985 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
25988 /* Offset is a signed value *2 */
25990 if (val
>= limit
|| val
< -limit
)
25996 /* Relax a machine dependent frag. This returns the amount by which
25997 the current size of the frag should change. */
26000 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
26005 oldsize
= fragp
->fr_var
;
26006 switch (fragp
->fr_subtype
)
26008 case T_MNEM_ldr_pc2
:
26009 newsize
= relax_adr (fragp
, sec
, stretch
);
26011 case T_MNEM_ldr_pc
:
26012 case T_MNEM_ldr_sp
:
26013 case T_MNEM_str_sp
:
26014 newsize
= relax_immediate (fragp
, 8, 2);
26018 newsize
= relax_immediate (fragp
, 5, 2);
26022 newsize
= relax_immediate (fragp
, 5, 1);
26026 newsize
= relax_immediate (fragp
, 5, 0);
26029 newsize
= relax_adr (fragp
, sec
, stretch
);
26035 newsize
= relax_immediate (fragp
, 8, 0);
26038 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
26041 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
26043 case T_MNEM_add_sp
:
26044 case T_MNEM_add_pc
:
26045 newsize
= relax_immediate (fragp
, 8, 2);
26047 case T_MNEM_inc_sp
:
26048 case T_MNEM_dec_sp
:
26049 newsize
= relax_immediate (fragp
, 7, 2);
26055 newsize
= relax_addsub (fragp
, sec
);
26061 fragp
->fr_var
= newsize
;
26062 /* Freeze wide instructions that are at or before the same location as
26063 in the previous pass. This avoids infinite loops.
26064 Don't freeze them unconditionally because targets may be artificially
26065 misaligned by the expansion of preceding frags. */
26066 if (stretch
<= 0 && newsize
> 2)
26068 md_convert_frag (sec
->owner
, sec
, fragp
);
26072 return newsize
- oldsize
;
26075 /* Round up a section size to the appropriate boundary. */
26078 md_section_align (segT segment ATTRIBUTE_UNUSED
,
26084 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
26085 of an rs_align_code fragment. */
26088 arm_handle_align (fragS
* fragP
)
26090 static unsigned char const arm_noop
[2][2][4] =
26093 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
26094 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
26097 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
26098 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
26101 static unsigned char const thumb_noop
[2][2][2] =
26104 {0xc0, 0x46}, /* LE */
26105 {0x46, 0xc0}, /* BE */
26108 {0x00, 0xbf}, /* LE */
26109 {0xbf, 0x00} /* BE */
26112 static unsigned char const wide_thumb_noop
[2][4] =
26113 { /* Wide Thumb-2 */
26114 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
26115 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
26118 unsigned bytes
, fix
, noop_size
;
26120 const unsigned char * noop
;
26121 const unsigned char *narrow_noop
= NULL
;
26126 if (fragP
->fr_type
!= rs_align_code
)
26129 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
26130 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
26133 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
26134 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
26136 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
26138 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
26140 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
26141 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
26143 narrow_noop
= thumb_noop
[1][target_big_endian
];
26144 noop
= wide_thumb_noop
[target_big_endian
];
26147 noop
= thumb_noop
[0][target_big_endian
];
26155 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
26156 ? selected_cpu
: arm_arch_none
,
26158 [target_big_endian
];
26165 fragP
->fr_var
= noop_size
;
26167 if (bytes
& (noop_size
- 1))
26169 fix
= bytes
& (noop_size
- 1);
26171 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
26173 memset (p
, 0, fix
);
26180 if (bytes
& noop_size
)
26182 /* Insert a narrow noop. */
26183 memcpy (p
, narrow_noop
, noop_size
);
26185 bytes
-= noop_size
;
26189 /* Use wide noops for the remainder */
26193 while (bytes
>= noop_size
)
26195 memcpy (p
, noop
, noop_size
);
26197 bytes
-= noop_size
;
26201 fragP
->fr_fix
+= fix
;
26204 /* Called from md_do_align. Used to create an alignment
26205 frag in a code section. */
26208 arm_frag_align_code (int n
, int max
)
26212 /* We assume that there will never be a requirement
26213 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
26214 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
26219 _("alignments greater than %d bytes not supported in .text sections."),
26220 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
26221 as_fatal ("%s", err_msg
);
26224 p
= frag_var (rs_align_code
,
26225 MAX_MEM_FOR_RS_ALIGN_CODE
,
26227 (relax_substateT
) max
,
26234 /* Perform target specific initialisation of a frag.
26235 Note - despite the name this initialisation is not done when the frag
26236 is created, but only when its type is assigned. A frag can be created
26237 and used a long time before its type is set, so beware of assuming that
26238 this initialisation is performed first. */
26242 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
26244 /* Record whether this frag is in an ARM or a THUMB area. */
26245 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
26248 #else /* OBJ_ELF is defined. */
26250 arm_init_frag (fragS
* fragP
, int max_chars
)
26252 bfd_boolean frag_thumb_mode
;
26254 /* If the current ARM vs THUMB mode has not already
26255 been recorded into this frag then do so now. */
26256 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
26257 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
26259 /* PR 21809: Do not set a mapping state for debug sections
26260 - it just confuses other tools. */
26261 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
26264 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
26266 /* Record a mapping symbol for alignment frags. We will delete this
26267 later if the alignment ends up empty. */
26268 switch (fragP
->fr_type
)
26271 case rs_align_test
:
26273 mapping_state_2 (MAP_DATA
, max_chars
);
26275 case rs_align_code
:
26276 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
26283 /* When we change sections we need to issue a new mapping symbol. */
26286 arm_elf_change_section (void)
26288 /* Link an unlinked unwind index table section to the .text section. */
26289 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
26290 && elf_linked_to_section (now_seg
) == NULL
)
26291 elf_linked_to_section (now_seg
) = text_section
;
26295 arm_elf_section_type (const char * str
, size_t len
)
26297 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
26298 return SHT_ARM_EXIDX
;
26303 /* Code to deal with unwinding tables. */
26305 static void add_unwind_adjustsp (offsetT
);
26307 /* Generate any deferred unwind frame offset. */
26310 flush_pending_unwind (void)
26314 offset
= unwind
.pending_offset
;
26315 unwind
.pending_offset
= 0;
26317 add_unwind_adjustsp (offset
);
26320 /* Add an opcode to this list for this function. Two-byte opcodes should
26321 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
26325 add_unwind_opcode (valueT op
, int length
)
26327 /* Add any deferred stack adjustment. */
26328 if (unwind
.pending_offset
)
26329 flush_pending_unwind ();
26331 unwind
.sp_restored
= 0;
26333 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
26335 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
26336 if (unwind
.opcodes
)
26337 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
26338 unwind
.opcode_alloc
);
26340 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
26345 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
26347 unwind
.opcode_count
++;
26351 /* Add unwind opcodes to adjust the stack pointer. */
26354 add_unwind_adjustsp (offsetT offset
)
26358 if (offset
> 0x200)
26360 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
26365 /* Long form: 0xb2, uleb128. */
26366 /* This might not fit in a word so add the individual bytes,
26367 remembering the list is built in reverse order. */
26368 o
= (valueT
) ((offset
- 0x204) >> 2);
26370 add_unwind_opcode (0, 1);
26372 /* Calculate the uleb128 encoding of the offset. */
26376 bytes
[n
] = o
& 0x7f;
26382 /* Add the insn. */
26384 add_unwind_opcode (bytes
[n
- 1], 1);
26385 add_unwind_opcode (0xb2, 1);
26387 else if (offset
> 0x100)
26389 /* Two short opcodes. */
26390 add_unwind_opcode (0x3f, 1);
26391 op
= (offset
- 0x104) >> 2;
26392 add_unwind_opcode (op
, 1);
26394 else if (offset
> 0)
26396 /* Short opcode. */
26397 op
= (offset
- 4) >> 2;
26398 add_unwind_opcode (op
, 1);
26400 else if (offset
< 0)
26403 while (offset
> 0x100)
26405 add_unwind_opcode (0x7f, 1);
26408 op
= ((offset
- 4) >> 2) | 0x40;
26409 add_unwind_opcode (op
, 1);
26413 /* Finish the list of unwind opcodes for this function. */
26416 finish_unwind_opcodes (void)
26420 if (unwind
.fp_used
)
26422 /* Adjust sp as necessary. */
26423 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
26424 flush_pending_unwind ();
26426 /* After restoring sp from the frame pointer. */
26427 op
= 0x90 | unwind
.fp_reg
;
26428 add_unwind_opcode (op
, 1);
26431 flush_pending_unwind ();
26435 /* Start an exception table entry. If idx is nonzero this is an index table
26439 start_unwind_section (const segT text_seg
, int idx
)
26441 const char * text_name
;
26442 const char * prefix
;
26443 const char * prefix_once
;
26444 const char * group_name
;
26452 prefix
= ELF_STRING_ARM_unwind
;
26453 prefix_once
= ELF_STRING_ARM_unwind_once
;
26454 type
= SHT_ARM_EXIDX
;
26458 prefix
= ELF_STRING_ARM_unwind_info
;
26459 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
26460 type
= SHT_PROGBITS
;
26463 text_name
= segment_name (text_seg
);
26464 if (streq (text_name
, ".text"))
26467 if (strncmp (text_name
, ".gnu.linkonce.t.",
26468 strlen (".gnu.linkonce.t.")) == 0)
26470 prefix
= prefix_once
;
26471 text_name
+= strlen (".gnu.linkonce.t.");
26474 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
26480 /* Handle COMDAT group. */
26481 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
26483 group_name
= elf_group_name (text_seg
);
26484 if (group_name
== NULL
)
26486 as_bad (_("Group section `%s' has no group signature"),
26487 segment_name (text_seg
));
26488 ignore_rest_of_line ();
26491 flags
|= SHF_GROUP
;
26495 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
26498 /* Set the section link for index tables. */
26500 elf_linked_to_section (now_seg
) = text_seg
;
26504 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
26505 personality routine data. Returns zero, or the index table value for
26506 an inline entry. */
26509 create_unwind_entry (int have_data
)
26514 /* The current word of data. */
26516 /* The number of bytes left in this word. */
26519 finish_unwind_opcodes ();
26521 /* Remember the current text section. */
26522 unwind
.saved_seg
= now_seg
;
26523 unwind
.saved_subseg
= now_subseg
;
26525 start_unwind_section (now_seg
, 0);
26527 if (unwind
.personality_routine
== NULL
)
26529 if (unwind
.personality_index
== -2)
26532 as_bad (_("handlerdata in cantunwind frame"));
26533 return 1; /* EXIDX_CANTUNWIND. */
26536 /* Use a default personality routine if none is specified. */
26537 if (unwind
.personality_index
== -1)
26539 if (unwind
.opcode_count
> 3)
26540 unwind
.personality_index
= 1;
26542 unwind
.personality_index
= 0;
26545 /* Space for the personality routine entry. */
26546 if (unwind
.personality_index
== 0)
26548 if (unwind
.opcode_count
> 3)
26549 as_bad (_("too many unwind opcodes for personality routine 0"));
26553 /* All the data is inline in the index table. */
26556 while (unwind
.opcode_count
> 0)
26558 unwind
.opcode_count
--;
26559 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
26563 /* Pad with "finish" opcodes. */
26565 data
= (data
<< 8) | 0xb0;
26572 /* We get two opcodes "free" in the first word. */
26573 size
= unwind
.opcode_count
- 2;
26577 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
26578 if (unwind
.personality_index
!= -1)
26580 as_bad (_("attempt to recreate an unwind entry"));
26584 /* An extra byte is required for the opcode count. */
26585 size
= unwind
.opcode_count
+ 1;
26588 size
= (size
+ 3) >> 2;
26590 as_bad (_("too many unwind opcodes"));
26592 frag_align (2, 0, 0);
26593 record_alignment (now_seg
, 2);
26594 unwind
.table_entry
= expr_build_dot ();
26596 /* Allocate the table entry. */
26597 ptr
= frag_more ((size
<< 2) + 4);
26598 /* PR 13449: Zero the table entries in case some of them are not used. */
26599 memset (ptr
, 0, (size
<< 2) + 4);
26600 where
= frag_now_fix () - ((size
<< 2) + 4);
26602 switch (unwind
.personality_index
)
26605 /* ??? Should this be a PLT generating relocation? */
26606 /* Custom personality routine. */
26607 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
26608 BFD_RELOC_ARM_PREL31
);
26613 /* Set the first byte to the number of additional words. */
26614 data
= size
> 0 ? size
- 1 : 0;
26618 /* ABI defined personality routines. */
26620 /* Three opcodes bytes are packed into the first word. */
26627 /* The size and first two opcode bytes go in the first word. */
26628 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
26633 /* Should never happen. */
26637 /* Pack the opcodes into words (MSB first), reversing the list at the same
26639 while (unwind
.opcode_count
> 0)
26643 md_number_to_chars (ptr
, data
, 4);
26648 unwind
.opcode_count
--;
26650 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
26653 /* Finish off the last word. */
26656 /* Pad with "finish" opcodes. */
26658 data
= (data
<< 8) | 0xb0;
26660 md_number_to_chars (ptr
, data
, 4);
26665 /* Add an empty descriptor if there is no user-specified data. */
26666 ptr
= frag_more (4);
26667 md_number_to_chars (ptr
, 0, 4);
26674 /* Initialize the DWARF-2 unwind information for this procedure. */
26677 tc_arm_frame_initial_instructions (void)
26679 cfi_add_CFA_def_cfa (REG_SP
, 0);
26681 #endif /* OBJ_ELF */
26683 /* Convert REGNAME to a DWARF-2 register number. */
26686 tc_arm_regname_to_dw2regnum (char *regname
)
26688 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
26692 /* PR 16694: Allow VFP registers as well. */
26693 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
26697 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
26706 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
26710 exp
.X_op
= O_secrel
;
26711 exp
.X_add_symbol
= symbol
;
26712 exp
.X_add_number
= 0;
26713 emit_expr (&exp
, size
);
26717 /* MD interface: Symbol and relocation handling. */
26719 /* Return the address within the segment that a PC-relative fixup is
26720 relative to. For ARM, PC-relative fixups applied to instructions
26721 are generally relative to the location of the fixup plus 8 bytes.
26722 Thumb branches are offset by 4, and Thumb loads relative to PC
26723 require special handling. */
26726 md_pcrel_from_section (fixS
* fixP
, segT seg
)
26728 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26730 /* If this is pc-relative and we are going to emit a relocation
26731 then we just want to put out any pipeline compensation that the linker
26732 will need. Otherwise we want to use the calculated base.
26733 For WinCE we skip the bias for externals as well, since this
26734 is how the MS ARM-CE assembler behaves and we want to be compatible. */
26736 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
26737 || (arm_force_relocation (fixP
)
26739 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
26745 switch (fixP
->fx_r_type
)
26747 /* PC relative addressing on the Thumb is slightly odd as the
26748 bottom two bits of the PC are forced to zero for the
26749 calculation. This happens *after* application of the
26750 pipeline offset. However, Thumb adrl already adjusts for
26751 this, so we need not do it again. */
26752 case BFD_RELOC_ARM_THUMB_ADD
:
26755 case BFD_RELOC_ARM_THUMB_OFFSET
:
26756 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
26757 case BFD_RELOC_ARM_T32_ADD_PC12
:
26758 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
26759 return (base
+ 4) & ~3;
26761 /* Thumb branches are simply offset by +4. */
26762 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
26763 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
26764 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
26765 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
26766 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
26767 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
26768 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
26769 case BFD_RELOC_ARM_THUMB_BF17
:
26770 case BFD_RELOC_ARM_THUMB_BF19
:
26771 case BFD_RELOC_ARM_THUMB_BF13
:
26772 case BFD_RELOC_ARM_THUMB_LOOP12
:
26775 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26777 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26778 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26779 && ARM_IS_FUNC (fixP
->fx_addsy
)
26780 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26781 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26784 /* BLX is like branches above, but forces the low two bits of PC to
26786 case BFD_RELOC_THUMB_PCREL_BLX
:
26788 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26789 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26790 && THUMB_IS_FUNC (fixP
->fx_addsy
)
26791 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26792 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26793 return (base
+ 4) & ~3;
26795 /* ARM mode branches are offset by +8. However, the Windows CE
26796 loader expects the relocation not to take this into account. */
26797 case BFD_RELOC_ARM_PCREL_BLX
:
26799 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26800 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26801 && ARM_IS_FUNC (fixP
->fx_addsy
)
26802 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26803 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26806 case BFD_RELOC_ARM_PCREL_CALL
:
26808 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26809 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26810 && THUMB_IS_FUNC (fixP
->fx_addsy
)
26811 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26812 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26815 case BFD_RELOC_ARM_PCREL_BRANCH
:
26816 case BFD_RELOC_ARM_PCREL_JUMP
:
26817 case BFD_RELOC_ARM_PLT32
:
26819 /* When handling fixups immediately, because we have already
26820 discovered the value of a symbol, or the address of the frag involved
26821 we must account for the offset by +8, as the OS loader will never see the reloc.
26822 see fixup_segment() in write.c
26823 The S_IS_EXTERNAL test handles the case of global symbols.
26824 Those need the calculated base, not just the pipe compensation the linker will need. */
26826 && fixP
->fx_addsy
!= NULL
26827 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26828 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
26836 /* ARM mode loads relative to PC are also offset by +8. Unlike
26837 branches, the Windows CE loader *does* expect the relocation
26838 to take this into account. */
26839 case BFD_RELOC_ARM_OFFSET_IMM
:
26840 case BFD_RELOC_ARM_OFFSET_IMM8
:
26841 case BFD_RELOC_ARM_HWLITERAL
:
26842 case BFD_RELOC_ARM_LITERAL
:
26843 case BFD_RELOC_ARM_CP_OFF_IMM
:
26847 /* Other PC-relative relocations are un-offset. */
26853 static bfd_boolean flag_warn_syms
= TRUE
;
26856 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
26858 /* PR 18347 - Warn if the user attempts to create a symbol with the same
26859 name as an ARM instruction. Whilst strictly speaking it is allowed, it
26860 does mean that the resulting code might be very confusing to the reader.
26861 Also this warning can be triggered if the user omits an operand before
26862 an immediate address, eg:
26866 GAS treats this as an assignment of the value of the symbol foo to a
26867 symbol LDR, and so (without this code) it will not issue any kind of
26868 warning or error message.
26870 Note - ARM instructions are case-insensitive but the strings in the hash
26871 table are all stored in lower case, so we must first ensure that name is
26873 if (flag_warn_syms
&& arm_ops_hsh
)
26875 char * nbuf
= strdup (name
);
26878 for (p
= nbuf
; *p
; p
++)
26880 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
26882 static struct hash_control
* already_warned
= NULL
;
26884 if (already_warned
== NULL
)
26885 already_warned
= hash_new ();
26886 /* Only warn about the symbol once. To keep the code
26887 simple we let hash_insert do the lookup for us. */
26888 if (hash_insert (already_warned
, nbuf
, NULL
) == NULL
)
26889 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
26898 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
26899 Otherwise we have no need to default values of symbols. */
26902 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
26905 if (name
[0] == '_' && name
[1] == 'G'
26906 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
26910 if (symbol_find (name
))
26911 as_bad (_("GOT already in the symbol table"));
26913 GOT_symbol
= symbol_new (name
, undefined_section
,
26914 (valueT
) 0, & zero_address_frag
);
26924 /* Subroutine of md_apply_fix. Check to see if an immediate can be
26925 computed as two separate immediate values, added together. We
26926 already know that this value cannot be computed by just one ARM
26929 static unsigned int
26930 validate_immediate_twopart (unsigned int val
,
26931 unsigned int * highpart
)
26936 for (i
= 0; i
< 32; i
+= 2)
26937 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
26943 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
26945 else if (a
& 0xff0000)
26947 if (a
& 0xff000000)
26949 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
26953 gas_assert (a
& 0xff000000);
26954 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
26957 return (a
& 0xff) | (i
<< 7);
26964 validate_offset_imm (unsigned int val
, int hwse
)
26966 if ((hwse
&& val
> 255) || val
> 4095)
26971 /* Subroutine of md_apply_fix. Do those data_ops which can take a
26972 negative immediate constant by altering the instruction. A bit of
26977 by inverting the second operand, and
26980 by negating the second operand. */
26983 negate_data_op (unsigned long * instruction
,
26984 unsigned long value
)
26987 unsigned long negated
, inverted
;
26989 negated
= encode_arm_immediate (-value
);
26990 inverted
= encode_arm_immediate (~value
);
26992 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
26995 /* First negates. */
26996 case OPCODE_SUB
: /* ADD <-> SUB */
26997 new_inst
= OPCODE_ADD
;
27002 new_inst
= OPCODE_SUB
;
27006 case OPCODE_CMP
: /* CMP <-> CMN */
27007 new_inst
= OPCODE_CMN
;
27012 new_inst
= OPCODE_CMP
;
27016 /* Now Inverted ops. */
27017 case OPCODE_MOV
: /* MOV <-> MVN */
27018 new_inst
= OPCODE_MVN
;
27023 new_inst
= OPCODE_MOV
;
27027 case OPCODE_AND
: /* AND <-> BIC */
27028 new_inst
= OPCODE_BIC
;
27033 new_inst
= OPCODE_AND
;
27037 case OPCODE_ADC
: /* ADC <-> SBC */
27038 new_inst
= OPCODE_SBC
;
27043 new_inst
= OPCODE_ADC
;
27047 /* We cannot do anything. */
27052 if (value
== (unsigned) FAIL
)
27055 *instruction
&= OPCODE_MASK
;
27056 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
27060 /* Like negate_data_op, but for Thumb-2. */
27062 static unsigned int
27063 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
27067 unsigned int negated
, inverted
;
27069 negated
= encode_thumb32_immediate (-value
);
27070 inverted
= encode_thumb32_immediate (~value
);
27072 rd
= (*instruction
>> 8) & 0xf;
27073 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
27076 /* ADD <-> SUB. Includes CMP <-> CMN. */
27077 case T2_OPCODE_SUB
:
27078 new_inst
= T2_OPCODE_ADD
;
27082 case T2_OPCODE_ADD
:
27083 new_inst
= T2_OPCODE_SUB
;
27087 /* ORR <-> ORN. Includes MOV <-> MVN. */
27088 case T2_OPCODE_ORR
:
27089 new_inst
= T2_OPCODE_ORN
;
27093 case T2_OPCODE_ORN
:
27094 new_inst
= T2_OPCODE_ORR
;
27098 /* AND <-> BIC. TST has no inverted equivalent. */
27099 case T2_OPCODE_AND
:
27100 new_inst
= T2_OPCODE_BIC
;
27107 case T2_OPCODE_BIC
:
27108 new_inst
= T2_OPCODE_AND
;
27113 case T2_OPCODE_ADC
:
27114 new_inst
= T2_OPCODE_SBC
;
27118 case T2_OPCODE_SBC
:
27119 new_inst
= T2_OPCODE_ADC
;
27123 /* We cannot do anything. */
27128 if (value
== (unsigned int)FAIL
)
27131 *instruction
&= T2_OPCODE_MASK
;
27132 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
27136 /* Read a 32-bit thumb instruction from buf. */
27138 static unsigned long
27139 get_thumb32_insn (char * buf
)
27141 unsigned long insn
;
27142 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
27143 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27148 /* We usually want to set the low bit on the address of thumb function
27149 symbols. In particular .word foo - . should have the low bit set.
27150 Generic code tries to fold the difference of two symbols to
27151 a constant. Prevent this and force a relocation when the first symbols
27152 is a thumb function. */
27155 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
27157 if (op
== O_subtract
27158 && l
->X_op
== O_symbol
27159 && r
->X_op
== O_symbol
27160 && THUMB_IS_FUNC (l
->X_add_symbol
))
27162 l
->X_op
= O_subtract
;
27163 l
->X_op_symbol
= r
->X_add_symbol
;
27164 l
->X_add_number
-= r
->X_add_number
;
27168 /* Process as normal. */
27172 /* Encode Thumb2 unconditional branches and calls. The encoding
27173 for the 2 are identical for the immediate values. */
27176 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
27178 #define T2I1I2MASK ((1 << 13) | (1 << 11))
27181 addressT S
, I1
, I2
, lo
, hi
;
27183 S
= (value
>> 24) & 0x01;
27184 I1
= (value
>> 23) & 0x01;
27185 I2
= (value
>> 22) & 0x01;
27186 hi
= (value
>> 12) & 0x3ff;
27187 lo
= (value
>> 1) & 0x7ff;
27188 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27189 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27190 newval
|= (S
<< 10) | hi
;
27191 newval2
&= ~T2I1I2MASK
;
27192 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
27193 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27194 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27198 md_apply_fix (fixS
* fixP
,
27202 offsetT value
= * valP
;
27204 unsigned int newimm
;
27205 unsigned long temp
;
27207 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
27209 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
27211 /* Note whether this will delete the relocation. */
27213 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
27216 /* On a 64-bit host, silently truncate 'value' to 32 bits for
27217 consistency with the behaviour on 32-bit hosts. Remember value
27219 value
&= 0xffffffff;
27220 value
^= 0x80000000;
27221 value
-= 0x80000000;
27224 fixP
->fx_addnumber
= value
;
27226 /* Same treatment for fixP->fx_offset. */
27227 fixP
->fx_offset
&= 0xffffffff;
27228 fixP
->fx_offset
^= 0x80000000;
27229 fixP
->fx_offset
-= 0x80000000;
27231 switch (fixP
->fx_r_type
)
27233 case BFD_RELOC_NONE
:
27234 /* This will need to go in the object file. */
27238 case BFD_RELOC_ARM_IMMEDIATE
:
27239 /* We claim that this fixup has been processed here,
27240 even if in fact we generate an error because we do
27241 not have a reloc for it, so tc_gen_reloc will reject it. */
27244 if (fixP
->fx_addsy
)
27246 const char *msg
= 0;
27248 if (! S_IS_DEFINED (fixP
->fx_addsy
))
27249 msg
= _("undefined symbol %s used as an immediate value");
27250 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27251 msg
= _("symbol %s is in a different section");
27252 else if (S_IS_WEAK (fixP
->fx_addsy
))
27253 msg
= _("symbol %s is weak and may be overridden later");
27257 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27258 msg
, S_GET_NAME (fixP
->fx_addsy
));
27263 temp
= md_chars_to_number (buf
, INSN_SIZE
);
27265 /* If the offset is negative, we should use encoding A2 for ADR. */
27266 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
27267 newimm
= negate_data_op (&temp
, value
);
27270 newimm
= encode_arm_immediate (value
);
27272 /* If the instruction will fail, see if we can fix things up by
27273 changing the opcode. */
27274 if (newimm
== (unsigned int) FAIL
)
27275 newimm
= negate_data_op (&temp
, value
);
27276 /* MOV accepts both ARM modified immediate (A1 encoding) and
27277 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
27278 When disassembling, MOV is preferred when there is no encoding
27280 if (newimm
== (unsigned int) FAIL
27281 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
27282 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
27283 && !((temp
>> SBIT_SHIFT
) & 0x1)
27284 && value
>= 0 && value
<= 0xffff)
27286 /* Clear bits[23:20] to change encoding from A1 to A2. */
27287 temp
&= 0xff0fffff;
27288 /* Encoding high 4bits imm. Code below will encode the remaining
27290 temp
|= (value
& 0x0000f000) << 4;
27291 newimm
= value
& 0x00000fff;
27295 if (newimm
== (unsigned int) FAIL
)
27297 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27298 _("invalid constant (%lx) after fixup"),
27299 (unsigned long) value
);
27303 newimm
|= (temp
& 0xfffff000);
27304 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27307 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
27309 unsigned int highpart
= 0;
27310 unsigned int newinsn
= 0xe1a00000; /* nop. */
27312 if (fixP
->fx_addsy
)
27314 const char *msg
= 0;
27316 if (! S_IS_DEFINED (fixP
->fx_addsy
))
27317 msg
= _("undefined symbol %s used as an immediate value");
27318 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27319 msg
= _("symbol %s is in a different section");
27320 else if (S_IS_WEAK (fixP
->fx_addsy
))
27321 msg
= _("symbol %s is weak and may be overridden later");
27325 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27326 msg
, S_GET_NAME (fixP
->fx_addsy
));
27331 newimm
= encode_arm_immediate (value
);
27332 temp
= md_chars_to_number (buf
, INSN_SIZE
);
27334 /* If the instruction will fail, see if we can fix things up by
27335 changing the opcode. */
27336 if (newimm
== (unsigned int) FAIL
27337 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
27339 /* No ? OK - try using two ADD instructions to generate
27341 newimm
= validate_immediate_twopart (value
, & highpart
);
27343 /* Yes - then make sure that the second instruction is
27345 if (newimm
!= (unsigned int) FAIL
)
27347 /* Still No ? Try using a negated value. */
27348 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
27349 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
27350 /* Otherwise - give up. */
27353 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27354 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
27359 /* Replace the first operand in the 2nd instruction (which
27360 is the PC) with the destination register. We have
27361 already added in the PC in the first instruction and we
27362 do not want to do it again. */
27363 newinsn
&= ~ 0xf0000;
27364 newinsn
|= ((newinsn
& 0x0f000) << 4);
27367 newimm
|= (temp
& 0xfffff000);
27368 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27370 highpart
|= (newinsn
& 0xfffff000);
27371 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
27375 case BFD_RELOC_ARM_OFFSET_IMM
:
27376 if (!fixP
->fx_done
&& seg
->use_rela_p
)
27378 /* Fall through. */
27380 case BFD_RELOC_ARM_LITERAL
:
27386 if (validate_offset_imm (value
, 0) == FAIL
)
27388 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
27389 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27390 _("invalid literal constant: pool needs to be closer"));
27392 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27393 _("bad immediate value for offset (%ld)"),
27398 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27400 newval
&= 0xfffff000;
27403 newval
&= 0xff7ff000;
27404 newval
|= value
| (sign
? INDEX_UP
: 0);
27406 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27409 case BFD_RELOC_ARM_OFFSET_IMM8
:
27410 case BFD_RELOC_ARM_HWLITERAL
:
27416 if (validate_offset_imm (value
, 1) == FAIL
)
27418 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
27419 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27420 _("invalid literal constant: pool needs to be closer"));
27422 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27423 _("bad immediate value for 8-bit offset (%ld)"),
27428 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27430 newval
&= 0xfffff0f0;
27433 newval
&= 0xff7ff0f0;
27434 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
27436 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27439 case BFD_RELOC_ARM_T32_OFFSET_U8
:
27440 if (value
< 0 || value
> 1020 || value
% 4 != 0)
27441 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27442 _("bad immediate value for offset (%ld)"), (long) value
);
27445 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
27447 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
27450 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
27451 /* This is a complicated relocation used for all varieties of Thumb32
27452 load/store instruction with immediate offset:
27454 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
27455 *4, optional writeback(W)
27456 (doubleword load/store)
27458 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
27459 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
27460 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
27461 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
27462 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
27464 Uppercase letters indicate bits that are already encoded at
27465 this point. Lowercase letters are our problem. For the
27466 second block of instructions, the secondary opcode nybble
27467 (bits 8..11) is present, and bit 23 is zero, even if this is
27468 a PC-relative operation. */
27469 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27471 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
27473 if ((newval
& 0xf0000000) == 0xe0000000)
27475 /* Doubleword load/store: 8-bit offset, scaled by 4. */
27477 newval
|= (1 << 23);
27480 if (value
% 4 != 0)
27482 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27483 _("offset not a multiple of 4"));
27489 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27490 _("offset out of range"));
27495 else if ((newval
& 0x000f0000) == 0x000f0000)
27497 /* PC-relative, 12-bit offset. */
27499 newval
|= (1 << 23);
27504 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27505 _("offset out of range"));
27510 else if ((newval
& 0x00000100) == 0x00000100)
27512 /* Writeback: 8-bit, +/- offset. */
27514 newval
|= (1 << 9);
27519 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27520 _("offset out of range"));
27525 else if ((newval
& 0x00000f00) == 0x00000e00)
27527 /* T-instruction: positive 8-bit offset. */
27528 if (value
< 0 || value
> 0xff)
27530 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27531 _("offset out of range"));
27539 /* Positive 12-bit or negative 8-bit offset. */
27543 newval
|= (1 << 23);
27553 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27554 _("offset out of range"));
27561 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
27562 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
27565 case BFD_RELOC_ARM_SHIFT_IMM
:
27566 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27567 if (((unsigned long) value
) > 32
27569 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
27571 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27572 _("shift expression is too large"));
27577 /* Shifts of zero must be done as lsl. */
27579 else if (value
== 32)
27581 newval
&= 0xfffff07f;
27582 newval
|= (value
& 0x1f) << 7;
27583 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27586 case BFD_RELOC_ARM_T32_IMMEDIATE
:
27587 case BFD_RELOC_ARM_T32_ADD_IMM
:
27588 case BFD_RELOC_ARM_T32_IMM12
:
27589 case BFD_RELOC_ARM_T32_ADD_PC12
:
27590 /* We claim that this fixup has been processed here,
27591 even if in fact we generate an error because we do
27592 not have a reloc for it, so tc_gen_reloc will reject it. */
27596 && ! S_IS_DEFINED (fixP
->fx_addsy
))
27598 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27599 _("undefined symbol %s used as an immediate value"),
27600 S_GET_NAME (fixP
->fx_addsy
));
27604 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27606 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
27609 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
27610 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
27611 Thumb2 modified immediate encoding (T2). */
27612 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
27613 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
27615 newimm
= encode_thumb32_immediate (value
);
27616 if (newimm
== (unsigned int) FAIL
)
27617 newimm
= thumb32_negate_data_op (&newval
, value
);
27619 if (newimm
== (unsigned int) FAIL
)
27621 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
27623 /* Turn add/sum into addw/subw. */
27624 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
27625 newval
= (newval
& 0xfeffffff) | 0x02000000;
27626 /* No flat 12-bit imm encoding for addsw/subsw. */
27627 if ((newval
& 0x00100000) == 0)
27629 /* 12 bit immediate for addw/subw. */
27633 newval
^= 0x00a00000;
27636 newimm
= (unsigned int) FAIL
;
27643 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
27644 UINT16 (T3 encoding), MOVW only accepts UINT16. When
27645 disassembling, MOV is preferred when there is no encoding
27647 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
27648 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
27649 but with the Rn field [19:16] set to 1111. */
27650 && (((newval
>> 16) & 0xf) == 0xf)
27651 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
27652 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
27653 && value
>= 0 && value
<= 0xffff)
27655 /* Toggle bit[25] to change encoding from T2 to T3. */
27657 /* Clear bits[19:16]. */
27658 newval
&= 0xfff0ffff;
27659 /* Encoding high 4bits imm. Code below will encode the
27660 remaining low 12bits. */
27661 newval
|= (value
& 0x0000f000) << 4;
27662 newimm
= value
& 0x00000fff;
27667 if (newimm
== (unsigned int)FAIL
)
27669 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27670 _("invalid constant (%lx) after fixup"),
27671 (unsigned long) value
);
27675 newval
|= (newimm
& 0x800) << 15;
27676 newval
|= (newimm
& 0x700) << 4;
27677 newval
|= (newimm
& 0x0ff);
27679 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
27680 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
27683 case BFD_RELOC_ARM_SMC
:
27684 if (((unsigned long) value
) > 0xffff)
27685 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27686 _("invalid smc expression"));
27687 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27688 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
27689 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27692 case BFD_RELOC_ARM_HVC
:
27693 if (((unsigned long) value
) > 0xffff)
27694 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27695 _("invalid hvc expression"));
27696 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27697 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
27698 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27701 case BFD_RELOC_ARM_SWI
:
27702 if (fixP
->tc_fix_data
!= 0)
27704 if (((unsigned long) value
) > 0xff)
27705 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27706 _("invalid swi expression"));
27707 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27709 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27713 if (((unsigned long) value
) > 0x00ffffff)
27714 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27715 _("invalid swi expression"));
27716 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27718 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27722 case BFD_RELOC_ARM_MULTI
:
27723 if (((unsigned long) value
) > 0xffff)
27724 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27725 _("invalid expression in load/store multiple"));
27726 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
27727 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27731 case BFD_RELOC_ARM_PCREL_CALL
:
27733 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27735 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27736 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27737 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27738 /* Flip the bl to blx. This is a simple flip
27739 bit here because we generate PCREL_CALL for
27740 unconditional bls. */
27742 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27743 newval
= newval
| 0x10000000;
27744 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27750 goto arm_branch_common
;
27752 case BFD_RELOC_ARM_PCREL_JUMP
:
27753 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27755 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27756 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27757 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27759 /* This would map to a bl<cond>, b<cond>,
27760 b<always> to a Thumb function. We
27761 need to force a relocation for this particular
27763 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27766 /* Fall through. */
27768 case BFD_RELOC_ARM_PLT32
:
27770 case BFD_RELOC_ARM_PCREL_BRANCH
:
27772 goto arm_branch_common
;
27774 case BFD_RELOC_ARM_PCREL_BLX
:
27777 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27779 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27780 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27781 && ARM_IS_FUNC (fixP
->fx_addsy
))
27783 /* Flip the blx to a bl and warn. */
27784 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
27785 newval
= 0xeb000000;
27786 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
27787 _("blx to '%s' an ARM ISA state function changed to bl"),
27789 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27795 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
27796 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
27800 /* We are going to store value (shifted right by two) in the
27801 instruction, in a 24 bit, signed field. Bits 26 through 32 either
27802 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
27805 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27806 _("misaligned branch destination"));
27807 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
27808 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
27809 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27811 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27813 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27814 newval
|= (value
>> 2) & 0x00ffffff;
27815 /* Set the H bit on BLX instructions. */
27819 newval
|= 0x01000000;
27821 newval
&= ~0x01000000;
27823 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27827 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
27828 /* CBZ can only branch forward. */
27830 /* Attempts to use CBZ to branch to the next instruction
27831 (which, strictly speaking, are prohibited) will be turned into
27834 FIXME: It may be better to remove the instruction completely and
27835 perform relaxation. */
27838 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27839 newval
= 0xbf00; /* NOP encoding T1 */
27840 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27845 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27847 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27849 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27850 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
27851 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27856 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
27857 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
27858 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27860 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27862 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27863 newval
|= (value
& 0x1ff) >> 1;
27864 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27868 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
27869 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
27870 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27872 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27874 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27875 newval
|= (value
& 0xfff) >> 1;
27876 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27880 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27882 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27883 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27884 && ARM_IS_FUNC (fixP
->fx_addsy
)
27885 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27887 /* Force a relocation for a branch 20 bits wide. */
27890 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
27891 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27892 _("conditional branch out of range"));
27894 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27897 addressT S
, J1
, J2
, lo
, hi
;
27899 S
= (value
& 0x00100000) >> 20;
27900 J2
= (value
& 0x00080000) >> 19;
27901 J1
= (value
& 0x00040000) >> 18;
27902 hi
= (value
& 0x0003f000) >> 12;
27903 lo
= (value
& 0x00000ffe) >> 1;
27905 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27906 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27907 newval
|= (S
<< 10) | hi
;
27908 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
27909 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27910 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27914 case BFD_RELOC_THUMB_PCREL_BLX
:
27915 /* If there is a blx from a thumb state function to
27916 another thumb function flip this to a bl and warn
27920 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27921 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27922 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27924 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
27925 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
27926 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
27928 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27929 newval
= newval
| 0x1000;
27930 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
27931 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
27936 goto thumb_bl_common
;
27938 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27939 /* A bl from Thumb state ISA to an internal ARM state function
27940 is converted to a blx. */
27942 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27943 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27944 && ARM_IS_FUNC (fixP
->fx_addsy
)
27945 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27947 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27948 newval
= newval
& ~0x1000;
27949 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
27950 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
27956 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
27957 /* For a BLX instruction, make sure that the relocation is rounded up
27958 to a word boundary. This follows the semantics of the instruction
27959 which specifies that bit 1 of the target address will come from bit
27960 1 of the base address. */
27961 value
= (value
+ 3) & ~ 3;
27964 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
27965 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
27966 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
27969 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
27971 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
27972 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27973 else if ((value
& ~0x1ffffff)
27974 && ((value
& ~0x1ffffff) != ~0x1ffffff))
27975 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27976 _("Thumb2 branch out of range"));
27979 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27980 encode_thumb2_b_bl_offset (buf
, value
);
27984 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27985 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
27986 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27988 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27989 encode_thumb2_b_bl_offset (buf
, value
);
27994 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27999 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28000 md_number_to_chars (buf
, value
, 2);
28004 case BFD_RELOC_ARM_TLS_CALL
:
28005 case BFD_RELOC_ARM_THM_TLS_CALL
:
28006 case BFD_RELOC_ARM_TLS_DESCSEQ
:
28007 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
28008 case BFD_RELOC_ARM_TLS_GOTDESC
:
28009 case BFD_RELOC_ARM_TLS_GD32
:
28010 case BFD_RELOC_ARM_TLS_LE32
:
28011 case BFD_RELOC_ARM_TLS_IE32
:
28012 case BFD_RELOC_ARM_TLS_LDM32
:
28013 case BFD_RELOC_ARM_TLS_LDO32
:
28014 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
28017 /* Same handling as above, but with the arm_fdpic guard. */
28018 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
28019 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
28020 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
28023 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
28027 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28028 _("Relocation supported only in FDPIC mode"));
28032 case BFD_RELOC_ARM_GOT32
:
28033 case BFD_RELOC_ARM_GOTOFF
:
28036 case BFD_RELOC_ARM_GOT_PREL
:
28037 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28038 md_number_to_chars (buf
, value
, 4);
28041 case BFD_RELOC_ARM_TARGET2
:
28042 /* TARGET2 is not partial-inplace, so we need to write the
28043 addend here for REL targets, because it won't be written out
28044 during reloc processing later. */
28045 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28046 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
28049 /* Relocations for FDPIC. */
28050 case BFD_RELOC_ARM_GOTFUNCDESC
:
28051 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
28052 case BFD_RELOC_ARM_FUNCDESC
:
28055 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28056 md_number_to_chars (buf
, 0, 4);
28060 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28061 _("Relocation supported only in FDPIC mode"));
28066 case BFD_RELOC_RVA
:
28068 case BFD_RELOC_ARM_TARGET1
:
28069 case BFD_RELOC_ARM_ROSEGREL32
:
28070 case BFD_RELOC_ARM_SBREL32
:
28071 case BFD_RELOC_32_PCREL
:
28073 case BFD_RELOC_32_SECREL
:
28075 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28077 /* For WinCE we only do this for pcrel fixups. */
28078 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
28080 md_number_to_chars (buf
, value
, 4);
28084 case BFD_RELOC_ARM_PREL31
:
28085 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28087 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
28088 if ((value
^ (value
>> 1)) & 0x40000000)
28090 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28091 _("rel31 relocation overflow"));
28093 newval
|= value
& 0x7fffffff;
28094 md_number_to_chars (buf
, newval
, 4);
28099 case BFD_RELOC_ARM_CP_OFF_IMM
:
28100 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
28101 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
28102 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
28103 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28105 newval
= get_thumb32_insn (buf
);
28106 if ((newval
& 0x0f200f00) == 0x0d000900)
28108 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
28109 has permitted values that are multiples of 2, in the range 0
28111 if (value
< -510 || value
> 510 || (value
& 1))
28112 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28113 _("co-processor offset out of range"));
28115 else if ((newval
& 0xfe001f80) == 0xec000f80)
28117 if (value
< -511 || value
> 512 || (value
& 3))
28118 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28119 _("co-processor offset out of range"));
28121 else if (value
< -1023 || value
> 1023 || (value
& 3))
28122 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28123 _("co-processor offset out of range"));
28128 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
28129 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
28130 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28132 newval
= get_thumb32_insn (buf
);
28135 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
28136 newval
&= 0xffffff80;
28138 newval
&= 0xffffff00;
28142 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
28143 newval
&= 0xff7fff80;
28145 newval
&= 0xff7fff00;
28146 if ((newval
& 0x0f200f00) == 0x0d000900)
28148 /* This is a fp16 vstr/vldr.
28150 It requires the immediate offset in the instruction is shifted
28151 left by 1 to be a half-word offset.
28153 Here, left shift by 1 first, and later right shift by 2
28154 should get the right offset. */
28157 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
28159 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
28160 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
28161 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28163 put_thumb32_insn (buf
, newval
);
28166 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
28167 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
28168 if (value
< -255 || value
> 255)
28169 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28170 _("co-processor offset out of range"));
28172 goto cp_off_common
;
28174 case BFD_RELOC_ARM_THUMB_OFFSET
:
28175 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28176 /* Exactly what ranges, and where the offset is inserted depends
28177 on the type of instruction, we can establish this from the
28179 switch (newval
>> 12)
28181 case 4: /* PC load. */
28182 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
28183 forced to zero for these loads; md_pcrel_from has already
28184 compensated for this. */
28186 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28187 _("invalid offset, target not word aligned (0x%08lX)"),
28188 (((unsigned long) fixP
->fx_frag
->fr_address
28189 + (unsigned long) fixP
->fx_where
) & ~3)
28190 + (unsigned long) value
);
28192 if (value
& ~0x3fc)
28193 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28194 _("invalid offset, value too big (0x%08lX)"),
28197 newval
|= value
>> 2;
28200 case 9: /* SP load/store. */
28201 if (value
& ~0x3fc)
28202 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28203 _("invalid offset, value too big (0x%08lX)"),
28205 newval
|= value
>> 2;
28208 case 6: /* Word load/store. */
28210 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28211 _("invalid offset, value too big (0x%08lX)"),
28213 newval
|= value
<< 4; /* 6 - 2. */
28216 case 7: /* Byte load/store. */
28218 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28219 _("invalid offset, value too big (0x%08lX)"),
28221 newval
|= value
<< 6;
28224 case 8: /* Halfword load/store. */
28226 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28227 _("invalid offset, value too big (0x%08lX)"),
28229 newval
|= value
<< 5; /* 6 - 1. */
28233 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28234 "Unable to process relocation for thumb opcode: %lx",
28235 (unsigned long) newval
);
28238 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28241 case BFD_RELOC_ARM_THUMB_ADD
:
28242 /* This is a complicated relocation, since we use it for all of
28243 the following immediate relocations:
28247 9bit ADD/SUB SP word-aligned
28248 10bit ADD PC/SP word-aligned
28250 The type of instruction being processed is encoded in the
28257 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28259 int rd
= (newval
>> 4) & 0xf;
28260 int rs
= newval
& 0xf;
28261 int subtract
= !!(newval
& 0x8000);
28263 /* Check for HI regs, only very restricted cases allowed:
28264 Adjusting SP, and using PC or SP to get an address. */
28265 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
28266 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
28267 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28268 _("invalid Hi register with immediate"));
28270 /* If value is negative, choose the opposite instruction. */
28274 subtract
= !subtract
;
28276 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28277 _("immediate value out of range"));
28282 if (value
& ~0x1fc)
28283 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28284 _("invalid immediate for stack address calculation"));
28285 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
28286 newval
|= value
>> 2;
28288 else if (rs
== REG_PC
|| rs
== REG_SP
)
28290 /* PR gas/18541. If the addition is for a defined symbol
28291 within range of an ADR instruction then accept it. */
28294 && fixP
->fx_addsy
!= NULL
)
28298 if (! S_IS_DEFINED (fixP
->fx_addsy
)
28299 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
28300 || S_IS_WEAK (fixP
->fx_addsy
))
28302 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28303 _("address calculation needs a strongly defined nearby symbol"));
28307 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
28309 /* Round up to the next 4-byte boundary. */
28314 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
28318 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28319 _("symbol too far away"));
28329 if (subtract
|| value
& ~0x3fc)
28330 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28331 _("invalid immediate for address calculation (value = 0x%08lX)"),
28332 (unsigned long) (subtract
? - value
: value
));
28333 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
28335 newval
|= value
>> 2;
28340 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28341 _("immediate value out of range"));
28342 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
28343 newval
|= (rd
<< 8) | value
;
28348 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28349 _("immediate value out of range"));
28350 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
28351 newval
|= rd
| (rs
<< 3) | (value
<< 6);
28354 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28357 case BFD_RELOC_ARM_THUMB_IMM
:
28358 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28359 if (value
< 0 || value
> 255)
28360 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28361 _("invalid immediate: %ld is out of range"),
28364 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28367 case BFD_RELOC_ARM_THUMB_SHIFT
:
28368 /* 5bit shift value (0..32). LSL cannot take 32. */
28369 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
28370 temp
= newval
& 0xf800;
28371 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
28372 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28373 _("invalid shift value: %ld"), (long) value
);
28374 /* Shifts of zero must be encoded as LSL. */
28376 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
28377 /* Shifts of 32 are encoded as zero. */
28378 else if (value
== 32)
28380 newval
|= value
<< 6;
28381 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28384 case BFD_RELOC_VTABLE_INHERIT
:
28385 case BFD_RELOC_VTABLE_ENTRY
:
28389 case BFD_RELOC_ARM_MOVW
:
28390 case BFD_RELOC_ARM_MOVT
:
28391 case BFD_RELOC_ARM_THUMB_MOVW
:
28392 case BFD_RELOC_ARM_THUMB_MOVT
:
28393 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28395 /* REL format relocations are limited to a 16-bit addend. */
28396 if (!fixP
->fx_done
)
28398 if (value
< -0x8000 || value
> 0x7fff)
28399 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28400 _("offset out of range"));
28402 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
28403 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28408 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
28409 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28411 newval
= get_thumb32_insn (buf
);
28412 newval
&= 0xfbf08f00;
28413 newval
|= (value
& 0xf000) << 4;
28414 newval
|= (value
& 0x0800) << 15;
28415 newval
|= (value
& 0x0700) << 4;
28416 newval
|= (value
& 0x00ff);
28417 put_thumb32_insn (buf
, newval
);
28421 newval
= md_chars_to_number (buf
, 4);
28422 newval
&= 0xfff0f000;
28423 newval
|= value
& 0x0fff;
28424 newval
|= (value
& 0xf000) << 4;
28425 md_number_to_chars (buf
, newval
, 4);
28430 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
28431 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
28432 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
28433 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
28434 gas_assert (!fixP
->fx_done
);
28437 bfd_boolean is_mov
;
28438 bfd_vma encoded_addend
= value
;
28440 /* Check that addend can be encoded in instruction. */
28441 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
28442 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28443 _("the offset 0x%08lX is not representable"),
28444 (unsigned long) encoded_addend
);
28446 /* Extract the instruction. */
28447 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
28448 is_mov
= (insn
& 0xf800) == 0x2000;
28453 if (!seg
->use_rela_p
)
28454 insn
|= encoded_addend
;
28460 /* Extract the instruction. */
28461 /* Encoding is the following
28466 /* The following conditions must be true :
28471 rd
= (insn
>> 4) & 0xf;
28473 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
28474 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28475 _("Unable to process relocation for thumb opcode: %lx"),
28476 (unsigned long) insn
);
28478 /* Encode as ADD immediate8 thumb 1 code. */
28479 insn
= 0x3000 | (rd
<< 8);
28481 /* Place the encoded addend into the first 8 bits of the
28483 if (!seg
->use_rela_p
)
28484 insn
|= encoded_addend
;
28487 /* Update the instruction. */
28488 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
28492 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
28493 case BFD_RELOC_ARM_ALU_PC_G0
:
28494 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
28495 case BFD_RELOC_ARM_ALU_PC_G1
:
28496 case BFD_RELOC_ARM_ALU_PC_G2
:
28497 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
28498 case BFD_RELOC_ARM_ALU_SB_G0
:
28499 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
28500 case BFD_RELOC_ARM_ALU_SB_G1
:
28501 case BFD_RELOC_ARM_ALU_SB_G2
:
28502 gas_assert (!fixP
->fx_done
);
28503 if (!seg
->use_rela_p
)
28506 bfd_vma encoded_addend
;
28507 bfd_vma addend_abs
= llabs (value
);
28509 /* Check that the absolute value of the addend can be
28510 expressed as an 8-bit constant plus a rotation. */
28511 encoded_addend
= encode_arm_immediate (addend_abs
);
28512 if (encoded_addend
== (unsigned int) FAIL
)
28513 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28514 _("the offset 0x%08lX is not representable"),
28515 (unsigned long) addend_abs
);
28517 /* Extract the instruction. */
28518 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28520 /* If the addend is positive, use an ADD instruction.
28521 Otherwise use a SUB. Take care not to destroy the S bit. */
28522 insn
&= 0xff1fffff;
28528 /* Place the encoded addend into the first 12 bits of the
28530 insn
&= 0xfffff000;
28531 insn
|= encoded_addend
;
28533 /* Update the instruction. */
28534 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28538 case BFD_RELOC_ARM_LDR_PC_G0
:
28539 case BFD_RELOC_ARM_LDR_PC_G1
:
28540 case BFD_RELOC_ARM_LDR_PC_G2
:
28541 case BFD_RELOC_ARM_LDR_SB_G0
:
28542 case BFD_RELOC_ARM_LDR_SB_G1
:
28543 case BFD_RELOC_ARM_LDR_SB_G2
:
28544 gas_assert (!fixP
->fx_done
);
28545 if (!seg
->use_rela_p
)
28548 bfd_vma addend_abs
= llabs (value
);
28550 /* Check that the absolute value of the addend can be
28551 encoded in 12 bits. */
28552 if (addend_abs
>= 0x1000)
28553 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28554 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
28555 (unsigned long) addend_abs
);
28557 /* Extract the instruction. */
28558 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28560 /* If the addend is negative, clear bit 23 of the instruction.
28561 Otherwise set it. */
28563 insn
&= ~(1 << 23);
28567 /* Place the absolute value of the addend into the first 12 bits
28568 of the instruction. */
28569 insn
&= 0xfffff000;
28570 insn
|= addend_abs
;
28572 /* Update the instruction. */
28573 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28577 case BFD_RELOC_ARM_LDRS_PC_G0
:
28578 case BFD_RELOC_ARM_LDRS_PC_G1
:
28579 case BFD_RELOC_ARM_LDRS_PC_G2
:
28580 case BFD_RELOC_ARM_LDRS_SB_G0
:
28581 case BFD_RELOC_ARM_LDRS_SB_G1
:
28582 case BFD_RELOC_ARM_LDRS_SB_G2
:
28583 gas_assert (!fixP
->fx_done
);
28584 if (!seg
->use_rela_p
)
28587 bfd_vma addend_abs
= llabs (value
);
28589 /* Check that the absolute value of the addend can be
28590 encoded in 8 bits. */
28591 if (addend_abs
>= 0x100)
28592 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28593 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
28594 (unsigned long) addend_abs
);
28596 /* Extract the instruction. */
28597 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28599 /* If the addend is negative, clear bit 23 of the instruction.
28600 Otherwise set it. */
28602 insn
&= ~(1 << 23);
28606 /* Place the first four bits of the absolute value of the addend
28607 into the first 4 bits of the instruction, and the remaining
28608 four into bits 8 .. 11. */
28609 insn
&= 0xfffff0f0;
28610 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
28612 /* Update the instruction. */
28613 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28617 case BFD_RELOC_ARM_LDC_PC_G0
:
28618 case BFD_RELOC_ARM_LDC_PC_G1
:
28619 case BFD_RELOC_ARM_LDC_PC_G2
:
28620 case BFD_RELOC_ARM_LDC_SB_G0
:
28621 case BFD_RELOC_ARM_LDC_SB_G1
:
28622 case BFD_RELOC_ARM_LDC_SB_G2
:
28623 gas_assert (!fixP
->fx_done
);
28624 if (!seg
->use_rela_p
)
28627 bfd_vma addend_abs
= llabs (value
);
28629 /* Check that the absolute value of the addend is a multiple of
28630 four and, when divided by four, fits in 8 bits. */
28631 if (addend_abs
& 0x3)
28632 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28633 _("bad offset 0x%08lX (must be word-aligned)"),
28634 (unsigned long) addend_abs
);
28636 if ((addend_abs
>> 2) > 0xff)
28637 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28638 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
28639 (unsigned long) addend_abs
);
28641 /* Extract the instruction. */
28642 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28644 /* If the addend is negative, clear bit 23 of the instruction.
28645 Otherwise set it. */
28647 insn
&= ~(1 << 23);
28651 /* Place the addend (divided by four) into the first eight
28652 bits of the instruction. */
28653 insn
&= 0xfffffff0;
28654 insn
|= addend_abs
>> 2;
28656 /* Update the instruction. */
28657 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28661 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
28663 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28664 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28665 && ARM_IS_FUNC (fixP
->fx_addsy
)
28666 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28668 /* Force a relocation for a branch 5 bits wide. */
28671 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
28672 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28675 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28677 addressT boff
= value
>> 1;
28679 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28680 newval
|= (boff
<< 7);
28681 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28685 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
28687 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28688 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28689 && ARM_IS_FUNC (fixP
->fx_addsy
)
28690 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28694 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
28695 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28696 _("branch out of range"));
28698 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28700 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28702 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
28703 addressT diff
= value
- boff
;
28707 newval
|= 1 << 1; /* T bit. */
28709 else if (diff
!= 2)
28711 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28712 _("out of range label-relative fixup value"));
28714 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28718 case BFD_RELOC_ARM_THUMB_BF17
:
28720 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28721 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28722 && ARM_IS_FUNC (fixP
->fx_addsy
)
28723 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28725 /* Force a relocation for a branch 17 bits wide. */
28729 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
28730 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28733 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28736 addressT immA
, immB
, immC
;
28738 immA
= (value
& 0x0001f000) >> 12;
28739 immB
= (value
& 0x00000ffc) >> 2;
28740 immC
= (value
& 0x00000002) >> 1;
28742 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28743 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28745 newval2
|= (immC
<< 11) | (immB
<< 1);
28746 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28747 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28751 case BFD_RELOC_ARM_THUMB_BF19
:
28753 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28754 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28755 && ARM_IS_FUNC (fixP
->fx_addsy
)
28756 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28758 /* Force a relocation for a branch 19 bits wide. */
28762 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
28763 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28766 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28769 addressT immA
, immB
, immC
;
28771 immA
= (value
& 0x0007f000) >> 12;
28772 immB
= (value
& 0x00000ffc) >> 2;
28773 immC
= (value
& 0x00000002) >> 1;
28775 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28776 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28778 newval2
|= (immC
<< 11) | (immB
<< 1);
28779 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28780 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28784 case BFD_RELOC_ARM_THUMB_BF13
:
28786 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28787 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28788 && ARM_IS_FUNC (fixP
->fx_addsy
)
28789 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28791 /* Force a relocation for a branch 13 bits wide. */
28795 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
28796 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28799 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28802 addressT immA
, immB
, immC
;
28804 immA
= (value
& 0x00001000) >> 12;
28805 immB
= (value
& 0x00000ffc) >> 2;
28806 immC
= (value
& 0x00000002) >> 1;
28808 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28809 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28811 newval2
|= (immC
<< 11) | (immB
<< 1);
28812 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28813 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28817 case BFD_RELOC_ARM_THUMB_LOOP12
:
28819 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28820 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28821 && ARM_IS_FUNC (fixP
->fx_addsy
)
28822 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28824 /* Force a relocation for a branch 12 bits wide. */
28828 bfd_vma insn
= get_thumb32_insn (buf
);
28829 /* le lr, <label>, le <label> or letp lr, <label> */
28830 if (((insn
& 0xffffffff) == 0xf00fc001)
28831 || ((insn
& 0xffffffff) == 0xf02fc001)
28832 || ((insn
& 0xffffffff) == 0xf01fc001))
28835 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
28836 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28838 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28840 addressT imml
, immh
;
28842 immh
= (value
& 0x00000ffc) >> 2;
28843 imml
= (value
& 0x00000002) >> 1;
28845 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28846 newval
|= (imml
<< 11) | (immh
<< 1);
28847 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
28851 case BFD_RELOC_ARM_V4BX
:
28852 /* This will need to go in the object file. */
28856 case BFD_RELOC_UNUSED
:
28858 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28859 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
28863 /* Translate internal representation of relocation info to BFD target
28867 tc_gen_reloc (asection
*section
, fixS
*fixp
)
28870 bfd_reloc_code_real_type code
;
28872 reloc
= XNEW (arelent
);
28874 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
28875 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
28876 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
28878 if (fixp
->fx_pcrel
)
28880 if (section
->use_rela_p
)
28881 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
28883 fixp
->fx_offset
= reloc
->address
;
28885 reloc
->addend
= fixp
->fx_offset
;
28887 switch (fixp
->fx_r_type
)
28890 if (fixp
->fx_pcrel
)
28892 code
= BFD_RELOC_8_PCREL
;
28895 /* Fall through. */
28898 if (fixp
->fx_pcrel
)
28900 code
= BFD_RELOC_16_PCREL
;
28903 /* Fall through. */
28906 if (fixp
->fx_pcrel
)
28908 code
= BFD_RELOC_32_PCREL
;
28911 /* Fall through. */
28913 case BFD_RELOC_ARM_MOVW
:
28914 if (fixp
->fx_pcrel
)
28916 code
= BFD_RELOC_ARM_MOVW_PCREL
;
28919 /* Fall through. */
28921 case BFD_RELOC_ARM_MOVT
:
28922 if (fixp
->fx_pcrel
)
28924 code
= BFD_RELOC_ARM_MOVT_PCREL
;
28927 /* Fall through. */
28929 case BFD_RELOC_ARM_THUMB_MOVW
:
28930 if (fixp
->fx_pcrel
)
28932 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
28935 /* Fall through. */
28937 case BFD_RELOC_ARM_THUMB_MOVT
:
28938 if (fixp
->fx_pcrel
)
28940 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
28943 /* Fall through. */
28945 case BFD_RELOC_NONE
:
28946 case BFD_RELOC_ARM_PCREL_BRANCH
:
28947 case BFD_RELOC_ARM_PCREL_BLX
:
28948 case BFD_RELOC_RVA
:
28949 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
28950 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
28951 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
28952 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
28953 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
28954 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
28955 case BFD_RELOC_VTABLE_ENTRY
:
28956 case BFD_RELOC_VTABLE_INHERIT
:
28958 case BFD_RELOC_32_SECREL
:
28960 code
= fixp
->fx_r_type
;
28963 case BFD_RELOC_THUMB_PCREL_BLX
:
28965 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
28966 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
28969 code
= BFD_RELOC_THUMB_PCREL_BLX
;
28972 case BFD_RELOC_ARM_LITERAL
:
28973 case BFD_RELOC_ARM_HWLITERAL
:
28974 /* If this is called then the a literal has
28975 been referenced across a section boundary. */
28976 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28977 _("literal referenced across section boundary"));
28981 case BFD_RELOC_ARM_TLS_CALL
:
28982 case BFD_RELOC_ARM_THM_TLS_CALL
:
28983 case BFD_RELOC_ARM_TLS_DESCSEQ
:
28984 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
28985 case BFD_RELOC_ARM_GOT32
:
28986 case BFD_RELOC_ARM_GOTOFF
:
28987 case BFD_RELOC_ARM_GOT_PREL
:
28988 case BFD_RELOC_ARM_PLT32
:
28989 case BFD_RELOC_ARM_TARGET1
:
28990 case BFD_RELOC_ARM_ROSEGREL32
:
28991 case BFD_RELOC_ARM_SBREL32
:
28992 case BFD_RELOC_ARM_PREL31
:
28993 case BFD_RELOC_ARM_TARGET2
:
28994 case BFD_RELOC_ARM_TLS_LDO32
:
28995 case BFD_RELOC_ARM_PCREL_CALL
:
28996 case BFD_RELOC_ARM_PCREL_JUMP
:
28997 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
28998 case BFD_RELOC_ARM_ALU_PC_G0
:
28999 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
29000 case BFD_RELOC_ARM_ALU_PC_G1
:
29001 case BFD_RELOC_ARM_ALU_PC_G2
:
29002 case BFD_RELOC_ARM_LDR_PC_G0
:
29003 case BFD_RELOC_ARM_LDR_PC_G1
:
29004 case BFD_RELOC_ARM_LDR_PC_G2
:
29005 case BFD_RELOC_ARM_LDRS_PC_G0
:
29006 case BFD_RELOC_ARM_LDRS_PC_G1
:
29007 case BFD_RELOC_ARM_LDRS_PC_G2
:
29008 case BFD_RELOC_ARM_LDC_PC_G0
:
29009 case BFD_RELOC_ARM_LDC_PC_G1
:
29010 case BFD_RELOC_ARM_LDC_PC_G2
:
29011 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
29012 case BFD_RELOC_ARM_ALU_SB_G0
:
29013 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
29014 case BFD_RELOC_ARM_ALU_SB_G1
:
29015 case BFD_RELOC_ARM_ALU_SB_G2
:
29016 case BFD_RELOC_ARM_LDR_SB_G0
:
29017 case BFD_RELOC_ARM_LDR_SB_G1
:
29018 case BFD_RELOC_ARM_LDR_SB_G2
:
29019 case BFD_RELOC_ARM_LDRS_SB_G0
:
29020 case BFD_RELOC_ARM_LDRS_SB_G1
:
29021 case BFD_RELOC_ARM_LDRS_SB_G2
:
29022 case BFD_RELOC_ARM_LDC_SB_G0
:
29023 case BFD_RELOC_ARM_LDC_SB_G1
:
29024 case BFD_RELOC_ARM_LDC_SB_G2
:
29025 case BFD_RELOC_ARM_V4BX
:
29026 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
29027 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
29028 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
29029 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
29030 case BFD_RELOC_ARM_GOTFUNCDESC
:
29031 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
29032 case BFD_RELOC_ARM_FUNCDESC
:
29033 case BFD_RELOC_ARM_THUMB_BF17
:
29034 case BFD_RELOC_ARM_THUMB_BF19
:
29035 case BFD_RELOC_ARM_THUMB_BF13
:
29036 code
= fixp
->fx_r_type
;
29039 case BFD_RELOC_ARM_TLS_GOTDESC
:
29040 case BFD_RELOC_ARM_TLS_GD32
:
29041 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
29042 case BFD_RELOC_ARM_TLS_LE32
:
29043 case BFD_RELOC_ARM_TLS_IE32
:
29044 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
29045 case BFD_RELOC_ARM_TLS_LDM32
:
29046 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
29047 /* BFD will include the symbol's address in the addend.
29048 But we don't want that, so subtract it out again here. */
29049 if (!S_IS_COMMON (fixp
->fx_addsy
))
29050 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
29051 code
= fixp
->fx_r_type
;
29055 case BFD_RELOC_ARM_IMMEDIATE
:
29056 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29057 _("internal relocation (type: IMMEDIATE) not fixed up"));
29060 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
29061 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29062 _("ADRL used for a symbol not defined in the same file"));
29065 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
29066 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
29067 case BFD_RELOC_ARM_THUMB_LOOP12
:
29068 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29069 _("%s used for a symbol not defined in the same file"),
29070 bfd_get_reloc_code_name (fixp
->fx_r_type
));
29073 case BFD_RELOC_ARM_OFFSET_IMM
:
29074 if (section
->use_rela_p
)
29076 code
= fixp
->fx_r_type
;
29080 if (fixp
->fx_addsy
!= NULL
29081 && !S_IS_DEFINED (fixp
->fx_addsy
)
29082 && S_IS_LOCAL (fixp
->fx_addsy
))
29084 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29085 _("undefined local label `%s'"),
29086 S_GET_NAME (fixp
->fx_addsy
));
29090 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29091 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
29098 switch (fixp
->fx_r_type
)
29100 case BFD_RELOC_NONE
: type
= "NONE"; break;
29101 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
29102 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
29103 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
29104 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
29105 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
29106 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
29107 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
29108 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
29109 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
29110 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
29111 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
29112 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
29113 default: type
= _("<unknown>"); break;
29115 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29116 _("cannot represent %s relocation in this object file format"),
29123 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
29125 && fixp
->fx_addsy
== GOT_symbol
)
29127 code
= BFD_RELOC_ARM_GOTPC
;
29128 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
29132 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
29134 if (reloc
->howto
== NULL
)
29136 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29137 _("cannot represent %s relocation in this object file format"),
29138 bfd_get_reloc_code_name (code
));
29142 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
29143 vtable entry to be used in the relocation's section offset. */
29144 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
29145 reloc
->address
= fixp
->fx_offset
;
29150 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
29153 cons_fix_new_arm (fragS
* frag
,
29157 bfd_reloc_code_real_type reloc
)
29162 FIXME: @@ Should look at CPU word size. */
29166 reloc
= BFD_RELOC_8
;
29169 reloc
= BFD_RELOC_16
;
29173 reloc
= BFD_RELOC_32
;
29176 reloc
= BFD_RELOC_64
;
29181 if (exp
->X_op
== O_secrel
)
29183 exp
->X_op
= O_symbol
;
29184 reloc
= BFD_RELOC_32_SECREL
;
29188 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
29191 #if defined (OBJ_COFF)
29193 arm_validate_fix (fixS
* fixP
)
29195 /* If the destination of the branch is a defined symbol which does not have
29196 the THUMB_FUNC attribute, then we must be calling a function which has
29197 the (interfacearm) attribute. We look for the Thumb entry point to that
29198 function and change the branch to refer to that function instead. */
29199 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
29200 && fixP
->fx_addsy
!= NULL
29201 && S_IS_DEFINED (fixP
->fx_addsy
)
29202 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
29204 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
29211 arm_force_relocation (struct fix
* fixp
)
29213 #if defined (OBJ_COFF) && defined (TE_PE)
29214 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
29218 /* In case we have a call or a branch to a function in ARM ISA mode from
29219 a thumb function or vice-versa force the relocation. These relocations
29220 are cleared off for some cores that might have blx and simple transformations
29224 switch (fixp
->fx_r_type
)
29226 case BFD_RELOC_ARM_PCREL_JUMP
:
29227 case BFD_RELOC_ARM_PCREL_CALL
:
29228 case BFD_RELOC_THUMB_PCREL_BLX
:
29229 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
29233 case BFD_RELOC_ARM_PCREL_BLX
:
29234 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29235 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
29236 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29237 if (ARM_IS_FUNC (fixp
->fx_addsy
))
29246 /* Resolve these relocations even if the symbol is extern or weak.
29247 Technically this is probably wrong due to symbol preemption.
29248 In practice these relocations do not have enough range to be useful
29249 at dynamic link time, and some code (e.g. in the Linux kernel)
29250 expects these references to be resolved. */
29251 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
29252 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
29253 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
29254 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
29255 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29256 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
29257 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
29258 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
29259 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
29260 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
29261 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
29262 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
29263 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
29264 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
29267 /* Always leave these relocations for the linker. */
29268 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
29269 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
29270 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
29273 /* Always generate relocations against function symbols. */
29274 if (fixp
->fx_r_type
== BFD_RELOC_32
29276 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
29279 return generic_force_reloc (fixp
);
29282 #if defined (OBJ_ELF) || defined (OBJ_COFF)
29283 /* Relocations against function names must be left unadjusted,
29284 so that the linker can use this information to generate interworking
29285 stubs. The MIPS version of this function
29286 also prevents relocations that are mips-16 specific, but I do not
29287 know why it does this.
29290 There is one other problem that ought to be addressed here, but
29291 which currently is not: Taking the address of a label (rather
29292 than a function) and then later jumping to that address. Such
29293 addresses also ought to have their bottom bit set (assuming that
29294 they reside in Thumb code), but at the moment they will not. */
29297 arm_fix_adjustable (fixS
* fixP
)
29299 if (fixP
->fx_addsy
== NULL
)
29302 /* Preserve relocations against symbols with function type. */
29303 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
29306 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
29307 && fixP
->fx_subsy
== NULL
)
29310 /* We need the symbol name for the VTABLE entries. */
29311 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
29312 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
29315 /* Don't allow symbols to be discarded on GOT related relocs. */
29316 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
29317 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
29318 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
29319 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
29320 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
29321 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
29322 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
29323 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
29324 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
29325 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
29326 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
29327 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
29328 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
29329 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
29330 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
29331 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
29332 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
29335 /* Similarly for group relocations. */
29336 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
29337 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
29338 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
29341 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
29342 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
29343 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
29344 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
29345 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
29346 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
29347 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
29348 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
29349 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
29352 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
29353 offsets, so keep these symbols. */
29354 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
29355 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
29360 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
29364 elf32_arm_target_format (void)
29367 return (target_big_endian
29368 ? "elf32-bigarm-symbian"
29369 : "elf32-littlearm-symbian");
29370 #elif defined (TE_VXWORKS)
29371 return (target_big_endian
29372 ? "elf32-bigarm-vxworks"
29373 : "elf32-littlearm-vxworks");
29374 #elif defined (TE_NACL)
29375 return (target_big_endian
29376 ? "elf32-bigarm-nacl"
29377 : "elf32-littlearm-nacl");
29381 if (target_big_endian
)
29382 return "elf32-bigarm-fdpic";
29384 return "elf32-littlearm-fdpic";
29388 if (target_big_endian
)
29389 return "elf32-bigarm";
29391 return "elf32-littlearm";
29397 armelf_frob_symbol (symbolS
* symp
,
29400 elf_frob_symbol (symp
, puntp
);
29404 /* MD interface: Finalization. */
29409 literal_pool
* pool
;
29411 /* Ensure that all the predication blocks are properly closed. */
29412 check_pred_blocks_finished ();
29414 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
29416 /* Put it at the end of the relevant section. */
29417 subseg_set (pool
->section
, pool
->sub_section
);
29419 arm_elf_change_section ();
29426 /* Remove any excess mapping symbols generated for alignment frags in
29427 SEC. We may have created a mapping symbol before a zero byte
29428 alignment; remove it if there's a mapping symbol after the
29431 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
29432 void *dummy ATTRIBUTE_UNUSED
)
29434 segment_info_type
*seginfo
= seg_info (sec
);
29437 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
29440 for (fragp
= seginfo
->frchainP
->frch_root
;
29442 fragp
= fragp
->fr_next
)
29444 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
29445 fragS
*next
= fragp
->fr_next
;
29447 /* Variable-sized frags have been converted to fixed size by
29448 this point. But if this was variable-sized to start with,
29449 there will be a fixed-size frag after it. So don't handle
29451 if (sym
== NULL
|| next
== NULL
)
29454 if (S_GET_VALUE (sym
) < next
->fr_address
)
29455 /* Not at the end of this frag. */
29457 know (S_GET_VALUE (sym
) == next
->fr_address
);
29461 if (next
->tc_frag_data
.first_map
!= NULL
)
29463 /* Next frag starts with a mapping symbol. Discard this
29465 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
29469 if (next
->fr_next
== NULL
)
29471 /* This mapping symbol is at the end of the section. Discard
29473 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
29474 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
29478 /* As long as we have empty frags without any mapping symbols,
29480 /* If the next frag is non-empty and does not start with a
29481 mapping symbol, then this mapping symbol is required. */
29482 if (next
->fr_address
!= next
->fr_next
->fr_address
)
29485 next
= next
->fr_next
;
29487 while (next
!= NULL
);
29492 /* Adjust the symbol table. This marks Thumb symbols as distinct from
29496 arm_adjust_symtab (void)
29501 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
29503 if (ARM_IS_THUMB (sym
))
29505 if (THUMB_IS_FUNC (sym
))
29507 /* Mark the symbol as a Thumb function. */
29508 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
29509 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
29510 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
29512 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
29513 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
29515 as_bad (_("%s: unexpected function type: %d"),
29516 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
29518 else switch (S_GET_STORAGE_CLASS (sym
))
29521 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
29524 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
29527 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
29535 if (ARM_IS_INTERWORK (sym
))
29536 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
29543 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
29545 if (ARM_IS_THUMB (sym
))
29547 elf_symbol_type
* elf_sym
;
29549 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
29550 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
29552 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
29553 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
29555 /* If it's a .thumb_func, declare it as so,
29556 otherwise tag label as .code 16. */
29557 if (THUMB_IS_FUNC (sym
))
29558 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
29559 ST_BRANCH_TO_THUMB
);
29560 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
29561 elf_sym
->internal_elf_sym
.st_info
=
29562 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
29567 /* Remove any overlapping mapping symbols generated by alignment frags. */
29568 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
29569 /* Now do generic ELF adjustments. */
29570 elf_adjust_symtab ();
29574 /* MD interface: Initialization. */
29577 set_constant_flonums (void)
29581 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
29582 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
29586 /* Auto-select Thumb mode if it's the only available instruction set for the
29587 given architecture. */
29590 autoselect_thumb_from_cpu_variant (void)
29592 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
29593 opcode_select (16);
29602 if ( (arm_ops_hsh
= hash_new ()) == NULL
29603 || (arm_cond_hsh
= hash_new ()) == NULL
29604 || (arm_vcond_hsh
= hash_new ()) == NULL
29605 || (arm_shift_hsh
= hash_new ()) == NULL
29606 || (arm_psr_hsh
= hash_new ()) == NULL
29607 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
29608 || (arm_reg_hsh
= hash_new ()) == NULL
29609 || (arm_reloc_hsh
= hash_new ()) == NULL
29610 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
29611 as_fatal (_("virtual memory exhausted"));
29613 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
29614 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
29615 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
29616 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
29617 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
29618 hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, (void *) (vconds
+ i
));
29619 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
29620 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
29621 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
29622 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
29623 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
29624 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
29625 (void *) (v7m_psrs
+ i
));
29626 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
29627 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
29629 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
29631 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
29632 (void *) (barrier_opt_names
+ i
));
29634 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
29636 struct reloc_entry
* entry
= reloc_names
+ i
;
29638 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
29639 /* This makes encode_branch() use the EABI versions of this relocation. */
29640 entry
->reloc
= BFD_RELOC_UNUSED
;
29642 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
29646 set_constant_flonums ();
29648 /* Set the cpu variant based on the command-line options. We prefer
29649 -mcpu= over -march= if both are set (as for GCC); and we prefer
29650 -mfpu= over any other way of setting the floating point unit.
29651 Use of legacy options with new options are faulted. */
29654 if (mcpu_cpu_opt
|| march_cpu_opt
)
29655 as_bad (_("use of old and new-style options to set CPU type"));
29657 selected_arch
= *legacy_cpu
;
29659 else if (mcpu_cpu_opt
)
29661 selected_arch
= *mcpu_cpu_opt
;
29662 selected_ext
= *mcpu_ext_opt
;
29664 else if (march_cpu_opt
)
29666 selected_arch
= *march_cpu_opt
;
29667 selected_ext
= *march_ext_opt
;
29669 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
29674 as_bad (_("use of old and new-style options to set FPU type"));
29676 selected_fpu
= *legacy_fpu
;
29679 selected_fpu
= *mfpu_opt
;
29682 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
29683 || defined (TE_NetBSD) || defined (TE_VXWORKS))
29684 /* Some environments specify a default FPU. If they don't, infer it
29685 from the processor. */
29687 selected_fpu
= *mcpu_fpu_opt
;
29688 else if (march_fpu_opt
)
29689 selected_fpu
= *march_fpu_opt
;
29691 selected_fpu
= fpu_default
;
29695 if (ARM_FEATURE_ZERO (selected_fpu
))
29697 if (!no_cpu_selected ())
29698 selected_fpu
= fpu_default
;
29700 selected_fpu
= fpu_arch_fpa
;
29704 if (ARM_FEATURE_ZERO (selected_arch
))
29706 selected_arch
= cpu_default
;
29707 selected_cpu
= selected_arch
;
29709 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
29711 /* Autodection of feature mode: allow all features in cpu_variant but leave
29712 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
29713 after all instruction have been processed and we can decide what CPU
29714 should be selected. */
29715 if (ARM_FEATURE_ZERO (selected_arch
))
29716 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
29718 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
29721 autoselect_thumb_from_cpu_variant ();
29723 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
29725 #if defined OBJ_COFF || defined OBJ_ELF
29727 unsigned int flags
= 0;
29729 #if defined OBJ_ELF
29730 flags
= meabi_flags
;
29732 switch (meabi_flags
)
29734 case EF_ARM_EABI_UNKNOWN
:
29736 /* Set the flags in the private structure. */
29737 if (uses_apcs_26
) flags
|= F_APCS26
;
29738 if (support_interwork
) flags
|= F_INTERWORK
;
29739 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
29740 if (pic_code
) flags
|= F_PIC
;
29741 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
29742 flags
|= F_SOFT_FLOAT
;
29744 switch (mfloat_abi_opt
)
29746 case ARM_FLOAT_ABI_SOFT
:
29747 case ARM_FLOAT_ABI_SOFTFP
:
29748 flags
|= F_SOFT_FLOAT
;
29751 case ARM_FLOAT_ABI_HARD
:
29752 if (flags
& F_SOFT_FLOAT
)
29753 as_bad (_("hard-float conflicts with specified fpu"));
29757 /* Using pure-endian doubles (even if soft-float). */
29758 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
29759 flags
|= F_VFP_FLOAT
;
29761 #if defined OBJ_ELF
29762 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
29763 flags
|= EF_ARM_MAVERICK_FLOAT
;
29766 case EF_ARM_EABI_VER4
:
29767 case EF_ARM_EABI_VER5
:
29768 /* No additional flags to set. */
29775 bfd_set_private_flags (stdoutput
, flags
);
29777 /* We have run out flags in the COFF header to encode the
29778 status of ATPCS support, so instead we create a dummy,
29779 empty, debug section called .arm.atpcs. */
29784 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
29788 bfd_set_section_flags
29789 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
29790 bfd_set_section_size (stdoutput
, sec
, 0);
29791 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
29797 /* Record the CPU type as well. */
29798 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
29799 mach
= bfd_mach_arm_iWMMXt2
;
29800 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
29801 mach
= bfd_mach_arm_iWMMXt
;
29802 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
29803 mach
= bfd_mach_arm_XScale
;
29804 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
29805 mach
= bfd_mach_arm_ep9312
;
29806 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
29807 mach
= bfd_mach_arm_5TE
;
29808 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
29810 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
29811 mach
= bfd_mach_arm_5T
;
29813 mach
= bfd_mach_arm_5
;
29815 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
29817 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
29818 mach
= bfd_mach_arm_4T
;
29820 mach
= bfd_mach_arm_4
;
29822 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
29823 mach
= bfd_mach_arm_3M
;
29824 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
29825 mach
= bfd_mach_arm_3
;
29826 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
29827 mach
= bfd_mach_arm_2a
;
29828 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
29829 mach
= bfd_mach_arm_2
;
29831 mach
= bfd_mach_arm_unknown
;
29833 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
29836 /* Command line processing. */
29839 Invocation line includes a switch not recognized by the base assembler.
29840 See if it's a processor-specific option.
29842 This routine is somewhat complicated by the need for backwards
29843 compatibility (since older releases of gcc can't be changed).
29844 The new options try to make the interface as compatible as
29847 New options (supported) are:
29849 -mcpu=<cpu name> Assemble for selected processor
29850 -march=<architecture name> Assemble for selected architecture
29851 -mfpu=<fpu architecture> Assemble for selected FPU.
29852 -EB/-mbig-endian Big-endian
29853 -EL/-mlittle-endian Little-endian
29854 -k Generate PIC code
29855 -mthumb Start in Thumb mode
29856 -mthumb-interwork Code supports ARM/Thumb interworking
29858 -m[no-]warn-deprecated Warn about deprecated features
29859 -m[no-]warn-syms Warn when symbols match instructions
29861 For now we will also provide support for:
29863 -mapcs-32 32-bit Program counter
29864 -mapcs-26 26-bit Program counter
29865 -macps-float Floats passed in FP registers
29866 -mapcs-reentrant Reentrant code
29868 (sometime these will probably be replaced with -mapcs=<list of options>
29869 and -matpcs=<list of options>)
29871 The remaining options are only supported for back-wards compatibility.
29872 Cpu variants, the arm part is optional:
29873 -m[arm]1 Currently not supported.
29874 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
29875 -m[arm]3 Arm 3 processor
29876 -m[arm]6[xx], Arm 6 processors
29877 -m[arm]7[xx][t][[d]m] Arm 7 processors
29878 -m[arm]8[10] Arm 8 processors
29879 -m[arm]9[20][tdmi] Arm 9 processors
29880 -mstrongarm[110[0]] StrongARM processors
29881 -mxscale XScale processors
29882 -m[arm]v[2345[t[e]]] Arm architectures
29883 -mall All (except the ARM1)
29885 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
29886 -mfpe-old (No float load/store multiples)
29887 -mvfpxd VFP Single precision
29889 -mno-fpu Disable all floating point instructions
29891 The following CPU names are recognized:
29892 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
29893 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
29894 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
29895 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
29896 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
29897 arm10t arm10e, arm1020t, arm1020e, arm10200e,
29898 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
29902 const char * md_shortopts
= "m:k";
29904 #ifdef ARM_BI_ENDIAN
29905 #define OPTION_EB (OPTION_MD_BASE + 0)
29906 #define OPTION_EL (OPTION_MD_BASE + 1)
29908 #if TARGET_BYTES_BIG_ENDIAN
29909 #define OPTION_EB (OPTION_MD_BASE + 0)
29911 #define OPTION_EL (OPTION_MD_BASE + 1)
29914 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
29915 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
29917 struct option md_longopts
[] =
29920 {"EB", no_argument
, NULL
, OPTION_EB
},
29923 {"EL", no_argument
, NULL
, OPTION_EL
},
29925 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
29927 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
29929 {NULL
, no_argument
, NULL
, 0}
29932 size_t md_longopts_size
= sizeof (md_longopts
);
29934 struct arm_option_table
29936 const char * option
; /* Option name to match. */
29937 const char * help
; /* Help information. */
29938 int * var
; /* Variable to change. */
29939 int value
; /* What to change it to. */
29940 const char * deprecated
; /* If non-null, print this message. */
29943 struct arm_option_table arm_opts
[] =
29945 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
29946 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
29947 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
29948 &support_interwork
, 1, NULL
},
29949 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
29950 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
29951 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
29953 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
29954 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
29955 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
29956 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
29959 /* These are recognized by the assembler, but have no affect on code. */
29960 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
29961 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
29963 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
29964 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
29965 &warn_on_deprecated
, 0, NULL
},
29966 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
29967 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
29968 {NULL
, NULL
, NULL
, 0, NULL
}
29971 struct arm_legacy_option_table
29973 const char * option
; /* Option name to match. */
29974 const arm_feature_set
** var
; /* Variable to change. */
29975 const arm_feature_set value
; /* What to change it to. */
29976 const char * deprecated
; /* If non-null, print this message. */
29979 const struct arm_legacy_option_table arm_legacy_opts
[] =
29981 /* DON'T add any new processors to this list -- we want the whole list
29982 to go away... Add them to the processors table instead. */
29983 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
29984 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
29985 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
29986 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
29987 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
29988 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
29989 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
29990 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
29991 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
29992 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
29993 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
29994 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
29995 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
29996 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
29997 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
29998 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
29999 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
30000 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
30001 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
30002 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
30003 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
30004 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
30005 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
30006 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
30007 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
30008 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
30009 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
30010 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
30011 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
30012 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
30013 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
30014 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
30015 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
30016 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
30017 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
30018 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
30019 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
30020 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
30021 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
30022 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
30023 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
30024 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
30025 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
30026 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
30027 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
30028 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
30029 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30030 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30031 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30032 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30033 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
30034 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
30035 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
30036 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
30037 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
30038 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
30039 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
30040 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
30041 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
30042 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
30043 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
30044 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
30045 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
30046 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
30047 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
30048 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
30049 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
30050 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
30051 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
30052 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
30053 N_("use -mcpu=strongarm110")},
30054 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
30055 N_("use -mcpu=strongarm1100")},
30056 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
30057 N_("use -mcpu=strongarm1110")},
30058 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
30059 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
30060 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
30062 /* Architecture variants -- don't add any more to this list either. */
30063 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
30064 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
30065 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
30066 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
30067 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
30068 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
30069 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
30070 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
30071 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
30072 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
30073 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
30074 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
30075 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
30076 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
30077 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
30078 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
30079 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
30080 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
30082 /* Floating point variants -- don't add any more to this list either. */
30083 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
30084 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
30085 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
30086 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
30087 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
30089 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
30092 struct arm_cpu_option_table
30096 const arm_feature_set value
;
30097 const arm_feature_set ext
;
30098 /* For some CPUs we assume an FPU unless the user explicitly sets
30100 const arm_feature_set default_fpu
;
30101 /* The canonical name of the CPU, or NULL to use NAME converted to upper
30103 const char * canonical_name
;
30106 /* This list should, at a minimum, contain all the cpu names
30107 recognized by GCC. */
30108 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
30110 static const struct arm_cpu_option_table arm_cpus
[] =
30112 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
30115 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
30118 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
30121 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
30124 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
30127 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
30130 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
30133 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
30136 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
30139 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
30142 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
30145 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
30148 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
30151 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
30154 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
30157 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
30160 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
30163 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
30166 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
30169 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
30172 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
30175 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
30178 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
30181 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
30184 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
30187 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
30190 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
30193 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
30196 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
30199 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
30202 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
30205 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
30208 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
30211 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
30214 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
30217 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
30220 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
30223 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
30226 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
30229 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
30232 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
30235 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
30238 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
30241 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
30244 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
30247 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
30251 /* For V5 or later processors we default to using VFP; but the user
30252 should really set the FPU type explicitly. */
30253 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
30256 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
30259 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
30262 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
30265 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
30268 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
30271 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
30274 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
30277 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
30280 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
30283 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
30286 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
30289 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
30292 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
30295 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
30298 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
30301 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
30304 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
30307 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
30310 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
30313 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
30316 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
30319 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
30322 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
30325 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
30328 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
30331 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
30334 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
30337 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
30340 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
30343 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
30346 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
30349 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
30352 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
30355 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
30358 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
30361 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
30362 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30364 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
30366 FPU_ARCH_NEON_VFP_V4
),
30367 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
30368 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30369 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30370 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
30371 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30372 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30373 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
30375 FPU_ARCH_NEON_VFP_V4
),
30376 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
30378 FPU_ARCH_NEON_VFP_V4
),
30379 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
30381 FPU_ARCH_NEON_VFP_V4
),
30382 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
30383 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30384 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30385 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
30386 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30387 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30388 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
30389 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30390 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30391 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
30392 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30393 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30394 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
30395 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30396 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30397 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
30398 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30399 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30400 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
30401 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30402 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30403 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
30404 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30405 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30406 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
30407 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30408 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30409 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
30410 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30411 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30412 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
30415 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
30417 FPU_ARCH_VFP_V3D16
),
30418 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
30419 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30421 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
30422 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30423 FPU_ARCH_VFP_V3D16
),
30424 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
30425 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30426 FPU_ARCH_VFP_V3D16
),
30427 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
30428 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30429 FPU_ARCH_NEON_VFP_ARMV8
),
30430 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
30431 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30433 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
30436 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
30439 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
30442 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
30445 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
30448 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
30451 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
30454 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
30455 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30456 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30457 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
30458 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30459 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30460 /* ??? XSCALE is really an architecture. */
30461 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
30465 /* ??? iwmmxt is not a processor. */
30466 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
30469 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
30472 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
30477 ARM_CPU_OPT ("ep9312", "ARM920T",
30478 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
30479 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
30481 /* Marvell processors. */
30482 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
30483 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30484 FPU_ARCH_VFP_V3D16
),
30485 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
30486 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30487 FPU_ARCH_NEON_VFP_V4
),
30489 /* APM X-Gene family. */
30490 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
30492 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30493 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
30494 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30495 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30497 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
30501 struct arm_ext_table
30505 const arm_feature_set merge
;
30506 const arm_feature_set clear
;
30509 struct arm_arch_option_table
30513 const arm_feature_set value
;
30514 const arm_feature_set default_fpu
;
30515 const struct arm_ext_table
* ext_table
;
30518 /* Used to add support for +E and +noE extension. */
30519 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
30520 /* Used to add support for a +E extension. */
30521 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
30522 /* Used to add support for a +noE extension. */
30523 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
30525 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
30526 ~0 & ~FPU_ENDIAN_PURE)
30528 static const struct arm_ext_table armv5te_ext_table
[] =
30530 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
30531 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30534 static const struct arm_ext_table armv7_ext_table
[] =
30536 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30537 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30540 static const struct arm_ext_table armv7ve_ext_table
[] =
30542 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
30543 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
30544 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
30545 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30546 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
30547 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
30548 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
30550 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
30551 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
30553 /* Aliases for +simd. */
30554 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
30556 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30557 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30558 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
30560 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30563 static const struct arm_ext_table armv7a_ext_table
[] =
30565 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30566 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
30567 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
30568 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30569 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
30570 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
30571 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
30573 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
30574 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
30576 /* Aliases for +simd. */
30577 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30578 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30580 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
30581 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
30583 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
30584 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
30585 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30588 static const struct arm_ext_table armv7r_ext_table
[] =
30590 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
30591 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
30592 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30593 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
30594 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
30595 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30596 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30597 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
30598 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30601 static const struct arm_ext_table armv7em_ext_table
[] =
30603 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
30604 /* Alias for +fp, used to be known as fpv4-sp-d16. */
30605 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
30606 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
30607 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
30608 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
30609 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30612 static const struct arm_ext_table armv8a_ext_table
[] =
30614 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
30615 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
30616 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30617 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30619 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30620 should use the +simd option to turn on FP. */
30621 ARM_REMOVE ("fp", ALL_FP
),
30622 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30623 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30624 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30628 static const struct arm_ext_table armv81a_ext_table
[] =
30630 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
30631 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
30632 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30634 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30635 should use the +simd option to turn on FP. */
30636 ARM_REMOVE ("fp", ALL_FP
),
30637 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30638 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30639 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30642 static const struct arm_ext_table armv82a_ext_table
[] =
30644 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
30645 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
30646 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
30647 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
30648 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30649 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30651 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30652 should use the +simd option to turn on FP. */
30653 ARM_REMOVE ("fp", ALL_FP
),
30654 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30655 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30656 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30659 static const struct arm_ext_table armv84a_ext_table
[] =
30661 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30662 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
30663 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
30664 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30666 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30667 should use the +simd option to turn on FP. */
30668 ARM_REMOVE ("fp", ALL_FP
),
30669 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30670 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30671 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30674 static const struct arm_ext_table armv85a_ext_table
[] =
30676 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30677 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
30678 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
30679 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30681 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30682 should use the +simd option to turn on FP. */
30683 ARM_REMOVE ("fp", ALL_FP
),
30684 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30687 static const struct arm_ext_table armv8m_main_ext_table
[] =
30689 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30690 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
30691 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
30692 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
30693 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30696 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
30698 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30699 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
30701 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30702 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
30705 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30706 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
30707 ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE
),
30708 ARM_FEATURE_COPROC (FPU_MVE
| FPU_MVE_FP
)),
30710 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30711 FPU_MVE
| FPU_MVE_FP
| FPU_VFP_V5_SP_D16
|
30712 FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
30713 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30716 static const struct arm_ext_table armv8r_ext_table
[] =
30718 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
30719 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
30720 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30721 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30722 ARM_REMOVE ("fp", ALL_FP
),
30723 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
30724 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30727 /* This list should, at a minimum, contain all the architecture names
30728 recognized by GCC. */
30729 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
30730 #define ARM_ARCH_OPT2(N, V, DF, ext) \
30731 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
30733 static const struct arm_arch_option_table arm_archs
[] =
30735 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
30736 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
30737 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
30738 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
30739 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
30740 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
30741 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
30742 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
30743 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
30744 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
30745 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
30746 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
30747 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
30748 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
30749 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
30750 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
30751 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
30752 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
30753 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
30754 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
30755 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
30756 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
30757 kept to preserve existing behaviour. */
30758 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
30759 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
30760 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
30761 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
30762 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
30763 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
30764 kept to preserve existing behaviour. */
30765 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
30766 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
30767 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
30768 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
30769 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
30770 /* The official spelling of the ARMv7 profile variants is the dashed form.
30771 Accept the non-dashed form for compatibility with old toolchains. */
30772 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
30773 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
30774 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
30775 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
30776 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
30777 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
30778 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
30779 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
30780 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
30781 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
30783 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
30785 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
30786 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
30787 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
30788 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
30789 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
30790 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
30791 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
30792 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
30793 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
30794 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
30795 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
30797 #undef ARM_ARCH_OPT
30799 /* ISA extensions in the co-processor and main instruction set space. */
30801 struct arm_option_extension_value_table
30805 const arm_feature_set merge_value
;
30806 const arm_feature_set clear_value
;
30807 /* List of architectures for which an extension is available. ARM_ARCH_NONE
30808 indicates that an extension is available for all architectures while
30809 ARM_ANY marks an empty entry. */
30810 const arm_feature_set allowed_archs
[2];
30813 /* The following table must be in alphabetical order with a NULL last entry. */
30815 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
30816 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
30818 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
30819 use the context sensitive approach using arm_ext_table's. */
30820 static const struct arm_option_extension_value_table arm_extensions
[] =
30822 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30823 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30824 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30825 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
30826 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30827 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
30828 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
30830 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30831 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30832 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
30833 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
30834 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30835 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30836 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30838 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
30839 | ARM_EXT2_FP16_FML
),
30840 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
30841 | ARM_EXT2_FP16_FML
),
30843 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30844 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30845 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
30846 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
30847 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
30848 Thumb divide instruction. Due to this having the same name as the
30849 previous entry, this will be ignored when doing command-line parsing and
30850 only considered by build attribute selection code. */
30851 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
30852 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
30853 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
30854 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
30855 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
30856 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
30857 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
30858 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
30859 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
30860 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
30861 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
30862 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
30863 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
30864 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
30865 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
30866 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
30867 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
30868 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
30869 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
30870 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
30871 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
30873 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
30874 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
30875 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
30876 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
30877 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
30878 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
30879 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
30880 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
30882 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30883 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30884 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
30885 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
30886 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
30887 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
30888 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30889 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
30891 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
30892 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
30893 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
30894 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
30895 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
30899 /* ISA floating-point and Advanced SIMD extensions. */
30900 struct arm_option_fpu_value_table
30903 const arm_feature_set value
;
30906 /* This list should, at a minimum, contain all the fpu names
30907 recognized by GCC. */
30908 static const struct arm_option_fpu_value_table arm_fpus
[] =
30910 {"softfpa", FPU_NONE
},
30911 {"fpe", FPU_ARCH_FPE
},
30912 {"fpe2", FPU_ARCH_FPE
},
30913 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
30914 {"fpa", FPU_ARCH_FPA
},
30915 {"fpa10", FPU_ARCH_FPA
},
30916 {"fpa11", FPU_ARCH_FPA
},
30917 {"arm7500fe", FPU_ARCH_FPA
},
30918 {"softvfp", FPU_ARCH_VFP
},
30919 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
30920 {"vfp", FPU_ARCH_VFP_V2
},
30921 {"vfp9", FPU_ARCH_VFP_V2
},
30922 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
30923 {"vfp10", FPU_ARCH_VFP_V2
},
30924 {"vfp10-r0", FPU_ARCH_VFP_V1
},
30925 {"vfpxd", FPU_ARCH_VFP_V1xD
},
30926 {"vfpv2", FPU_ARCH_VFP_V2
},
30927 {"vfpv3", FPU_ARCH_VFP_V3
},
30928 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
30929 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
30930 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
30931 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
30932 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
30933 {"arm1020t", FPU_ARCH_VFP_V1
},
30934 {"arm1020e", FPU_ARCH_VFP_V2
},
30935 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
30936 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
30937 {"maverick", FPU_ARCH_MAVERICK
},
30938 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
30939 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
30940 {"neon-fp16", FPU_ARCH_NEON_FP16
},
30941 {"vfpv4", FPU_ARCH_VFP_V4
},
30942 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
30943 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
30944 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
30945 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
30946 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
30947 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
30948 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
30949 {"crypto-neon-fp-armv8",
30950 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
30951 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
30952 {"crypto-neon-fp-armv8.1",
30953 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
30954 {NULL
, ARM_ARCH_NONE
}
30957 struct arm_option_value_table
30963 static const struct arm_option_value_table arm_float_abis
[] =
30965 {"hard", ARM_FLOAT_ABI_HARD
},
30966 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
30967 {"soft", ARM_FLOAT_ABI_SOFT
},
30972 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
30973 static const struct arm_option_value_table arm_eabis
[] =
30975 {"gnu", EF_ARM_EABI_UNKNOWN
},
30976 {"4", EF_ARM_EABI_VER4
},
30977 {"5", EF_ARM_EABI_VER5
},
30982 struct arm_long_option_table
30984 const char * option
; /* Substring to match. */
30985 const char * help
; /* Help information. */
30986 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
30987 const char * deprecated
; /* If non-null, print this message. */
30991 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
30992 arm_feature_set
*ext_set
,
30993 const struct arm_ext_table
*ext_table
)
30995 /* We insist on extensions being specified in alphabetical order, and with
30996 extensions being added before being removed. We achieve this by having
30997 the global ARM_EXTENSIONS table in alphabetical order, and using the
30998 ADDING_VALUE variable to indicate whether we are adding an extension (1)
30999 or removing it (0) and only allowing it to change in the order
31001 const struct arm_option_extension_value_table
* opt
= NULL
;
31002 const arm_feature_set arm_any
= ARM_ANY
;
31003 int adding_value
= -1;
31005 while (str
!= NULL
&& *str
!= 0)
31012 as_bad (_("invalid architectural extension"));
31017 ext
= strchr (str
, '+');
31022 len
= strlen (str
);
31024 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
31026 if (adding_value
!= 0)
31029 opt
= arm_extensions
;
31037 if (adding_value
== -1)
31040 opt
= arm_extensions
;
31042 else if (adding_value
!= 1)
31044 as_bad (_("must specify extensions to add before specifying "
31045 "those to remove"));
31052 as_bad (_("missing architectural extension"));
31056 gas_assert (adding_value
!= -1);
31057 gas_assert (opt
!= NULL
);
31059 if (ext_table
!= NULL
)
31061 const struct arm_ext_table
* ext_opt
= ext_table
;
31062 bfd_boolean found
= FALSE
;
31063 for (; ext_opt
->name
!= NULL
; ext_opt
++)
31064 if (ext_opt
->name_len
== len
31065 && strncmp (ext_opt
->name
, str
, len
) == 0)
31069 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
31070 /* TODO: Option not supported. When we remove the
31071 legacy table this case should error out. */
31074 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
31078 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
31079 /* TODO: Option not supported. When we remove the
31080 legacy table this case should error out. */
31082 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
31094 /* Scan over the options table trying to find an exact match. */
31095 for (; opt
->name
!= NULL
; opt
++)
31096 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31098 int i
, nb_allowed_archs
=
31099 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
31100 /* Check we can apply the extension to this architecture. */
31101 for (i
= 0; i
< nb_allowed_archs
; i
++)
31104 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
31106 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
31109 if (i
== nb_allowed_archs
)
31111 as_bad (_("extension does not apply to the base architecture"));
31115 /* Add or remove the extension. */
31117 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
31119 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
31121 /* Allowing Thumb division instructions for ARMv7 in autodetection
31122 rely on this break so that duplicate extensions (extensions
31123 with the same name as a previous extension in the list) are not
31124 considered for command-line parsing. */
31128 if (opt
->name
== NULL
)
31130 /* Did we fail to find an extension because it wasn't specified in
31131 alphabetical order, or because it does not exist? */
31133 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31134 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31137 if (opt
->name
== NULL
)
31138 as_bad (_("unknown architectural extension `%s'"), str
);
31140 as_bad (_("architectural extensions must be specified in "
31141 "alphabetical order"));
31147 /* We should skip the extension we've just matched the next time
31159 arm_parse_cpu (const char *str
)
31161 const struct arm_cpu_option_table
*opt
;
31162 const char *ext
= strchr (str
, '+');
31168 len
= strlen (str
);
31172 as_bad (_("missing cpu name `%s'"), str
);
31176 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
31177 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31179 mcpu_cpu_opt
= &opt
->value
;
31180 if (mcpu_ext_opt
== NULL
)
31181 mcpu_ext_opt
= XNEW (arm_feature_set
);
31182 *mcpu_ext_opt
= opt
->ext
;
31183 mcpu_fpu_opt
= &opt
->default_fpu
;
31184 if (opt
->canonical_name
)
31186 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
31187 strcpy (selected_cpu_name
, opt
->canonical_name
);
31193 if (len
>= sizeof selected_cpu_name
)
31194 len
= (sizeof selected_cpu_name
) - 1;
31196 for (i
= 0; i
< len
; i
++)
31197 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
31198 selected_cpu_name
[i
] = 0;
31202 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
31207 as_bad (_("unknown cpu `%s'"), str
);
31212 arm_parse_arch (const char *str
)
31214 const struct arm_arch_option_table
*opt
;
31215 const char *ext
= strchr (str
, '+');
31221 len
= strlen (str
);
31225 as_bad (_("missing architecture name `%s'"), str
);
31229 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
31230 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31232 march_cpu_opt
= &opt
->value
;
31233 if (march_ext_opt
== NULL
)
31234 march_ext_opt
= XNEW (arm_feature_set
);
31235 *march_ext_opt
= arm_arch_none
;
31236 march_fpu_opt
= &opt
->default_fpu
;
31237 strcpy (selected_cpu_name
, opt
->name
);
31240 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
31246 as_bad (_("unknown architecture `%s'\n"), str
);
31251 arm_parse_fpu (const char * str
)
31253 const struct arm_option_fpu_value_table
* opt
;
31255 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
31256 if (streq (opt
->name
, str
))
31258 mfpu_opt
= &opt
->value
;
31262 as_bad (_("unknown floating point format `%s'\n"), str
);
31267 arm_parse_float_abi (const char * str
)
31269 const struct arm_option_value_table
* opt
;
31271 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
31272 if (streq (opt
->name
, str
))
31274 mfloat_abi_opt
= opt
->value
;
31278 as_bad (_("unknown floating point abi `%s'\n"), str
);
31284 arm_parse_eabi (const char * str
)
31286 const struct arm_option_value_table
*opt
;
31288 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
31289 if (streq (opt
->name
, str
))
31291 meabi_flags
= opt
->value
;
31294 as_bad (_("unknown EABI `%s'\n"), str
);
31300 arm_parse_it_mode (const char * str
)
31302 bfd_boolean ret
= TRUE
;
31304 if (streq ("arm", str
))
31305 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
31306 else if (streq ("thumb", str
))
31307 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
31308 else if (streq ("always", str
))
31309 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
31310 else if (streq ("never", str
))
31311 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
31314 as_bad (_("unknown implicit IT mode `%s', should be "\
31315 "arm, thumb, always, or never."), str
);
31323 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
31325 codecomposer_syntax
= TRUE
;
31326 arm_comment_chars
[0] = ';';
31327 arm_line_separator_chars
[0] = 0;
31331 struct arm_long_option_table arm_long_opts
[] =
31333 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
31334 arm_parse_cpu
, NULL
},
31335 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
31336 arm_parse_arch
, NULL
},
31337 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
31338 arm_parse_fpu
, NULL
},
31339 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
31340 arm_parse_float_abi
, NULL
},
31342 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
31343 arm_parse_eabi
, NULL
},
31345 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
31346 arm_parse_it_mode
, NULL
},
31347 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
31348 arm_ccs_mode
, NULL
},
31349 {NULL
, NULL
, 0, NULL
}
31353 md_parse_option (int c
, const char * arg
)
31355 struct arm_option_table
*opt
;
31356 const struct arm_legacy_option_table
*fopt
;
31357 struct arm_long_option_table
*lopt
;
31363 target_big_endian
= 1;
31369 target_big_endian
= 0;
31373 case OPTION_FIX_V4BX
:
31381 #endif /* OBJ_ELF */
31384 /* Listing option. Just ignore these, we don't support additional
31389 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
31391 if (c
== opt
->option
[0]
31392 && ((arg
== NULL
&& opt
->option
[1] == 0)
31393 || streq (arg
, opt
->option
+ 1)))
31395 /* If the option is deprecated, tell the user. */
31396 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
31397 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
31398 arg
? arg
: "", _(opt
->deprecated
));
31400 if (opt
->var
!= NULL
)
31401 *opt
->var
= opt
->value
;
31407 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
31409 if (c
== fopt
->option
[0]
31410 && ((arg
== NULL
&& fopt
->option
[1] == 0)
31411 || streq (arg
, fopt
->option
+ 1)))
31413 /* If the option is deprecated, tell the user. */
31414 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
31415 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
31416 arg
? arg
: "", _(fopt
->deprecated
));
31418 if (fopt
->var
!= NULL
)
31419 *fopt
->var
= &fopt
->value
;
31425 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
31427 /* These options are expected to have an argument. */
31428 if (c
== lopt
->option
[0]
31430 && strncmp (arg
, lopt
->option
+ 1,
31431 strlen (lopt
->option
+ 1)) == 0)
31433 /* If the option is deprecated, tell the user. */
31434 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
31435 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
31436 _(lopt
->deprecated
));
31438 /* Call the sup-option parser. */
31439 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
31450 md_show_usage (FILE * fp
)
31452 struct arm_option_table
*opt
;
31453 struct arm_long_option_table
*lopt
;
31455 fprintf (fp
, _(" ARM-specific assembler options:\n"));
31457 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
31458 if (opt
->help
!= NULL
)
31459 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
31461 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
31462 if (lopt
->help
!= NULL
)
31463 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
31467 -EB assemble code for a big-endian cpu\n"));
31472 -EL assemble code for a little-endian cpu\n"));
31476 --fix-v4bx Allow BX in ARMv4 code\n"));
31480 --fdpic generate an FDPIC object file\n"));
31481 #endif /* OBJ_ELF */
31489 arm_feature_set flags
;
31490 } cpu_arch_ver_table
;
31492 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
31493 chronologically for architectures, with an exception for ARMv6-M and
31494 ARMv6S-M due to legacy reasons. No new architecture should have a
31495 special case. This allows for build attribute selection results to be
31496 stable when new architectures are added. */
31497 static const cpu_arch_ver_table cpu_arch_ver
[] =
31499 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
31500 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
31501 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
31502 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
31503 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
31504 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
31505 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
31506 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
31507 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
31508 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
31509 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
31510 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
31511 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
31512 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
31513 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
31514 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
31515 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
31516 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
31517 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
31518 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
31519 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
31520 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
31521 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
31522 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
31524 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
31525 always selected build attributes to match those of ARMv6-M
31526 (resp. ARMv6S-M). However, due to these architectures being a strict
31527 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
31528 would be selected when fully respecting chronology of architectures.
31529 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
31530 move them before ARMv7 architectures. */
31531 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
31532 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
31534 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
31535 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
31536 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
31537 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
31538 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
31539 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
31540 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
31541 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
31542 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
31543 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
31544 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
31545 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
31546 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
31547 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
31548 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
31549 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
31550 {-1, ARM_ARCH_NONE
}
31553 /* Set an attribute if it has not already been set by the user. */
31556 aeabi_set_attribute_int (int tag
, int value
)
31559 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
31560 || !attributes_set_explicitly
[tag
])
31561 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
31565 aeabi_set_attribute_string (int tag
, const char *value
)
31568 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
31569 || !attributes_set_explicitly
[tag
])
31570 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
31573 /* Return whether features in the *NEEDED feature set are available via
31574 extensions for the architecture whose feature set is *ARCH_FSET. */
31577 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
31578 const arm_feature_set
*needed
)
31580 int i
, nb_allowed_archs
;
31581 arm_feature_set ext_fset
;
31582 const struct arm_option_extension_value_table
*opt
;
31584 ext_fset
= arm_arch_none
;
31585 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31587 /* Extension does not provide any feature we need. */
31588 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
31592 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
31593 for (i
= 0; i
< nb_allowed_archs
; i
++)
31596 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
31599 /* Extension is available, add it. */
31600 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
31601 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
31605 /* Can we enable all features in *needed? */
31606 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
31609 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
31610 a given architecture feature set *ARCH_EXT_FSET including extension feature
31611 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
31612 - if true, check for an exact match of the architecture modulo extensions;
31613 - otherwise, select build attribute value of the first superset
31614 architecture released so that results remains stable when new architectures
31616 For -march/-mcpu=all the build attribute value of the most featureful
31617 architecture is returned. Tag_CPU_arch_profile result is returned in
31621 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
31622 const arm_feature_set
*ext_fset
,
31623 char *profile
, int exact_match
)
31625 arm_feature_set arch_fset
;
31626 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
31628 /* Select most featureful architecture with all its extensions if building
31629 for -march=all as the feature sets used to set build attributes. */
31630 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
31632 /* Force revisiting of decision for each new architecture. */
31633 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
31635 return TAG_CPU_ARCH_V8
;
31638 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
31640 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
31642 arm_feature_set known_arch_fset
;
31644 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
31647 /* Base architecture match user-specified architecture and
31648 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
31649 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
31654 /* Base architecture match user-specified architecture only
31655 (eg. ARMv6-M in the same case as above). Record it in case we
31656 find a match with above condition. */
31657 else if (p_ver_ret
== NULL
31658 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
31664 /* Architecture has all features wanted. */
31665 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
31667 arm_feature_set added_fset
;
31669 /* Compute features added by this architecture over the one
31670 recorded in p_ver_ret. */
31671 if (p_ver_ret
!= NULL
)
31672 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
31674 /* First architecture that match incl. with extensions, or the
31675 only difference in features over the recorded match is
31676 features that were optional and are now mandatory. */
31677 if (p_ver_ret
== NULL
31678 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
31684 else if (p_ver_ret
== NULL
)
31686 arm_feature_set needed_ext_fset
;
31688 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
31690 /* Architecture has all features needed when using some
31691 extensions. Record it and continue searching in case there
31692 exist an architecture providing all needed features without
31693 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
31695 if (have_ext_for_needed_feat_p (&known_arch_fset
,
31702 if (p_ver_ret
== NULL
)
31706 /* Tag_CPU_arch_profile. */
31707 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
31708 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
31709 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
31710 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
31712 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
31714 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
31718 return p_ver_ret
->val
;
31721 /* Set the public EABI object attributes. */
31724 aeabi_set_public_attributes (void)
31726 char profile
= '\0';
31729 int fp16_optional
= 0;
31730 int skip_exact_match
= 0;
31731 arm_feature_set flags
, flags_arch
, flags_ext
;
31733 /* Autodetection mode, choose the architecture based the instructions
31735 if (no_cpu_selected ())
31737 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
31739 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
31740 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
31742 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
31743 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
31745 /* Code run during relaxation relies on selected_cpu being set. */
31746 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
31747 flags_ext
= arm_arch_none
;
31748 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
31749 selected_ext
= flags_ext
;
31750 selected_cpu
= flags
;
31752 /* Otherwise, choose the architecture based on the capabilities of the
31756 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
31757 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
31758 flags_ext
= selected_ext
;
31759 flags
= selected_cpu
;
31761 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
31763 /* Allow the user to override the reported architecture. */
31764 if (!ARM_FEATURE_ZERO (selected_object_arch
))
31766 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
31767 flags_ext
= arm_arch_none
;
31770 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
31772 /* When this function is run again after relaxation has happened there is no
31773 way to determine whether an architecture or CPU was specified by the user:
31774 - selected_cpu is set above for relaxation to work;
31775 - march_cpu_opt is not set if only -mcpu or .cpu is used;
31776 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
31777 Therefore, if not in -march=all case we first try an exact match and fall
31778 back to autodetection. */
31779 if (!skip_exact_match
)
31780 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
31782 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
31784 as_bad (_("no architecture contains all the instructions used\n"));
31786 /* Tag_CPU_name. */
31787 if (selected_cpu_name
[0])
31791 q
= selected_cpu_name
;
31792 if (strncmp (q
, "armv", 4) == 0)
31797 for (i
= 0; q
[i
]; i
++)
31798 q
[i
] = TOUPPER (q
[i
]);
31800 aeabi_set_attribute_string (Tag_CPU_name
, q
);
31803 /* Tag_CPU_arch. */
31804 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
31806 /* Tag_CPU_arch_profile. */
31807 if (profile
!= '\0')
31808 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
31810 /* Tag_DSP_extension. */
31811 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
31812 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
31814 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
31815 /* Tag_ARM_ISA_use. */
31816 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
31817 || ARM_FEATURE_ZERO (flags_arch
))
31818 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
31820 /* Tag_THUMB_ISA_use. */
31821 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
31822 || ARM_FEATURE_ZERO (flags_arch
))
31826 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
31827 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
31829 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
31833 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
31836 /* Tag_VFP_arch. */
31837 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
31838 aeabi_set_attribute_int (Tag_VFP_arch
,
31839 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
31841 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
31842 aeabi_set_attribute_int (Tag_VFP_arch
,
31843 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
31845 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
31848 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
31850 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
31852 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
31855 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
31856 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
31857 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
31858 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
31859 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
31861 /* Tag_ABI_HardFP_use. */
31862 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
31863 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
31864 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
31866 /* Tag_WMMX_arch. */
31867 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
31868 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
31869 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
31870 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
31872 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
31873 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
31874 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
31875 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
31876 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
31877 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
31879 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
31881 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
31885 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
31890 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
31891 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
31892 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
31893 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
31895 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
31896 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
31897 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
31901 We set Tag_DIV_use to two when integer divide instructions have been used
31902 in ARM state, or when Thumb integer divide instructions have been used,
31903 but we have no architecture profile set, nor have we any ARM instructions.
31905 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
31906 by the base architecture.
31908 For new architectures we will have to check these tests. */
31909 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
31910 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
31911 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
31912 aeabi_set_attribute_int (Tag_DIV_use
, 0);
31913 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
31914 || (profile
== '\0'
31915 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
31916 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
31917 aeabi_set_attribute_int (Tag_DIV_use
, 2);
31919 /* Tag_MP_extension_use. */
31920 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
31921 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
31923 /* Tag Virtualization_use. */
31924 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
31926 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
31929 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
31932 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
31933 finished and free extension feature bits which will not be used anymore. */
31936 arm_md_post_relax (void)
31938 aeabi_set_public_attributes ();
31939 XDELETE (mcpu_ext_opt
);
31940 mcpu_ext_opt
= NULL
;
31941 XDELETE (march_ext_opt
);
31942 march_ext_opt
= NULL
;
31945 /* Add the default contents for the .ARM.attributes section. */
31950 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
31953 aeabi_set_public_attributes ();
31955 #endif /* OBJ_ELF */
31957 /* Parse a .cpu directive. */
31960 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
31962 const struct arm_cpu_option_table
*opt
;
31966 name
= input_line_pointer
;
31967 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31968 input_line_pointer
++;
31969 saved_char
= *input_line_pointer
;
31970 *input_line_pointer
= 0;
31972 /* Skip the first "all" entry. */
31973 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
31974 if (streq (opt
->name
, name
))
31976 selected_arch
= opt
->value
;
31977 selected_ext
= opt
->ext
;
31978 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
31979 if (opt
->canonical_name
)
31980 strcpy (selected_cpu_name
, opt
->canonical_name
);
31984 for (i
= 0; opt
->name
[i
]; i
++)
31985 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
31987 selected_cpu_name
[i
] = 0;
31989 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
31991 *input_line_pointer
= saved_char
;
31992 demand_empty_rest_of_line ();
31995 as_bad (_("unknown cpu `%s'"), name
);
31996 *input_line_pointer
= saved_char
;
31997 ignore_rest_of_line ();
32000 /* Parse a .arch directive. */
32003 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
32005 const struct arm_arch_option_table
*opt
;
32009 name
= input_line_pointer
;
32010 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32011 input_line_pointer
++;
32012 saved_char
= *input_line_pointer
;
32013 *input_line_pointer
= 0;
32015 /* Skip the first "all" entry. */
32016 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
32017 if (streq (opt
->name
, name
))
32019 selected_arch
= opt
->value
;
32020 selected_ext
= arm_arch_none
;
32021 selected_cpu
= selected_arch
;
32022 strcpy (selected_cpu_name
, opt
->name
);
32023 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32024 *input_line_pointer
= saved_char
;
32025 demand_empty_rest_of_line ();
32029 as_bad (_("unknown architecture `%s'\n"), name
);
32030 *input_line_pointer
= saved_char
;
32031 ignore_rest_of_line ();
32034 /* Parse a .object_arch directive. */
32037 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
32039 const struct arm_arch_option_table
*opt
;
32043 name
= input_line_pointer
;
32044 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32045 input_line_pointer
++;
32046 saved_char
= *input_line_pointer
;
32047 *input_line_pointer
= 0;
32049 /* Skip the first "all" entry. */
32050 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
32051 if (streq (opt
->name
, name
))
32053 selected_object_arch
= opt
->value
;
32054 *input_line_pointer
= saved_char
;
32055 demand_empty_rest_of_line ();
32059 as_bad (_("unknown architecture `%s'\n"), name
);
32060 *input_line_pointer
= saved_char
;
32061 ignore_rest_of_line ();
32064 /* Parse a .arch_extension directive. */
32067 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
32069 const struct arm_option_extension_value_table
*opt
;
32072 int adding_value
= 1;
32074 name
= input_line_pointer
;
32075 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32076 input_line_pointer
++;
32077 saved_char
= *input_line_pointer
;
32078 *input_line_pointer
= 0;
32080 if (strlen (name
) >= 2
32081 && strncmp (name
, "no", 2) == 0)
32087 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32088 if (streq (opt
->name
, name
))
32090 int i
, nb_allowed_archs
=
32091 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
32092 for (i
= 0; i
< nb_allowed_archs
; i
++)
32095 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
32097 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
32101 if (i
== nb_allowed_archs
)
32103 as_bad (_("architectural extension `%s' is not allowed for the "
32104 "current base architecture"), name
);
32109 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
32112 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
32114 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
32115 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32116 *input_line_pointer
= saved_char
;
32117 demand_empty_rest_of_line ();
32118 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
32119 on this return so that duplicate extensions (extensions with the
32120 same name as a previous extension in the list) are not considered
32121 for command-line parsing. */
32125 if (opt
->name
== NULL
)
32126 as_bad (_("unknown architecture extension `%s'\n"), name
);
32128 *input_line_pointer
= saved_char
;
32129 ignore_rest_of_line ();
32132 /* Parse a .fpu directive. */
32135 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
32137 const struct arm_option_fpu_value_table
*opt
;
32141 name
= input_line_pointer
;
32142 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32143 input_line_pointer
++;
32144 saved_char
= *input_line_pointer
;
32145 *input_line_pointer
= 0;
32147 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
32148 if (streq (opt
->name
, name
))
32150 selected_fpu
= opt
->value
;
32151 #ifndef CPU_DEFAULT
32152 if (no_cpu_selected ())
32153 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
32156 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32157 *input_line_pointer
= saved_char
;
32158 demand_empty_rest_of_line ();
32162 as_bad (_("unknown floating point format `%s'\n"), name
);
32163 *input_line_pointer
= saved_char
;
32164 ignore_rest_of_line ();
32167 /* Copy symbol information. */
32170 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
32172 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
32176 /* Given a symbolic attribute NAME, return the proper integer value.
32177 Returns -1 if the attribute is not known. */
32180 arm_convert_symbolic_attribute (const char *name
)
32182 static const struct
32187 attribute_table
[] =
32189 /* When you modify this table you should
32190 also modify the list in doc/c-arm.texi. */
32191 #define T(tag) {#tag, tag}
32192 T (Tag_CPU_raw_name
),
32195 T (Tag_CPU_arch_profile
),
32196 T (Tag_ARM_ISA_use
),
32197 T (Tag_THUMB_ISA_use
),
32201 T (Tag_Advanced_SIMD_arch
),
32202 T (Tag_PCS_config
),
32203 T (Tag_ABI_PCS_R9_use
),
32204 T (Tag_ABI_PCS_RW_data
),
32205 T (Tag_ABI_PCS_RO_data
),
32206 T (Tag_ABI_PCS_GOT_use
),
32207 T (Tag_ABI_PCS_wchar_t
),
32208 T (Tag_ABI_FP_rounding
),
32209 T (Tag_ABI_FP_denormal
),
32210 T (Tag_ABI_FP_exceptions
),
32211 T (Tag_ABI_FP_user_exceptions
),
32212 T (Tag_ABI_FP_number_model
),
32213 T (Tag_ABI_align_needed
),
32214 T (Tag_ABI_align8_needed
),
32215 T (Tag_ABI_align_preserved
),
32216 T (Tag_ABI_align8_preserved
),
32217 T (Tag_ABI_enum_size
),
32218 T (Tag_ABI_HardFP_use
),
32219 T (Tag_ABI_VFP_args
),
32220 T (Tag_ABI_WMMX_args
),
32221 T (Tag_ABI_optimization_goals
),
32222 T (Tag_ABI_FP_optimization_goals
),
32223 T (Tag_compatibility
),
32224 T (Tag_CPU_unaligned_access
),
32225 T (Tag_FP_HP_extension
),
32226 T (Tag_VFP_HP_extension
),
32227 T (Tag_ABI_FP_16bit_format
),
32228 T (Tag_MPextension_use
),
32230 T (Tag_nodefaults
),
32231 T (Tag_also_compatible_with
),
32232 T (Tag_conformance
),
32234 T (Tag_Virtualization_use
),
32235 T (Tag_DSP_extension
),
32237 /* We deliberately do not include Tag_MPextension_use_legacy. */
32245 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
32246 if (streq (name
, attribute_table
[i
].name
))
32247 return attribute_table
[i
].tag
;
32252 /* Apply sym value for relocations only in the case that they are for
32253 local symbols in the same segment as the fixup and you have the
32254 respective architectural feature for blx and simple switches. */
32257 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
32260 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
32261 /* PR 17444: If the local symbol is in a different section then a reloc
32262 will always be generated for it, so applying the symbol value now
32263 will result in a double offset being stored in the relocation. */
32264 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
32265 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
32267 switch (fixP
->fx_r_type
)
32269 case BFD_RELOC_ARM_PCREL_BLX
:
32270 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
32271 if (ARM_IS_FUNC (fixP
->fx_addsy
))
32275 case BFD_RELOC_ARM_PCREL_CALL
:
32276 case BFD_RELOC_THUMB_PCREL_BLX
:
32277 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
32288 #endif /* OBJ_ELF */